Surface Preparation of Poly-Si Using Dry Cleaning for Minimizing Interfacial Resistance
As the integration density of memory increases, a low resistivity gate electrode is essential to meet the current needs of high speed operation. It has been known that one of major limitation of low resistivity gate is dopant penetration between poly-si and metal gate. Those dopants are penetrated and segregated on the surface of poly-si when annealed, which increases interfacial resistance and causes detrimental performance on the devices. Surface oxidation, level of boron oxide or silicon oxide on the poly-si surface is also getting higher after annealing. Therefore, it is necessary to remove those dopants oxidized layers on the surface of the activated poly-si in order to obtain minimal increases of interfacial resistance.
Paul Mertens, Marc Meuris and Marc Heyns
C. K. Seong et al., "Surface Preparation of Poly-Si Using Dry Cleaning for Minimizing Interfacial Resistance", Solid State Phenomena, Vol. 195, pp. 71-74, 2013