Ultra Clean Processing of Semiconductor Surfaces XI

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Authors: B. Brennan, S. McDonnell, D. Zhernokletov, H. Dong, C.L. Hinkle, J. Kim, R.M. Wallace
Abstract: Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an enhanced propensity to form interfacial defects is anticipated, as well as the need for surface passivation methods to mitigate such defects. In this work, we outline our recent results using in-situ methods to study the ALD high-k/III-V interface. We begin by briefly summarizing our results for III-As compounds, and then further discuss recent work on III-P and III-Sb compounds. While arsenides are under consideration for nMOS devices, antimonides are of interest for pMOS. InP is under consideration for quantum well channel MOS structures in order to serve as a better nMOS channel interface. In all cases, a high-k dielectric interface is employed to limit off-state tunneling current leakage.
Authors: Matthias Müller, Sonja Sioncke, Annelies Delabie, Burkhard Beckhoff
Abstract: Thin films of high-k material are becoming more and more used for semiconductor devices. A further shrinking of the devices requires also a further reduction of the high-k film thickness. With this reduction of the high-k thickness down to just a few nanometers two technical challenges have to be addressed. The first one is the ALD process for the deposition of the high-k material. Usually the ALD process can be well controlled by tuning the number of process cycles. But it is theoretically predicted [1] that the growth-per-cycle of the first cycles can be different than the steady growth-per-cycle which is obtained for high cycle numbers. This effect is caused by a not fully covered initial surface during the first cycles. Only when the deposited material forms a closed surface and the surface probabilities are the same for each following cycle the deposition rate will be constant. The second challenge is that the electrical properties of thin films with a thickness of a few nanometers are significantly determined by the quality of the interface between the film and the substrate.
Authors: Dennis H. van Dorp, Daniel Cuypers, Sophia Arnauts, Paul W. Mertens, Stefan de Gendt
Abstract: Compound semiconductors based on group III and V elements of the periodic system have high charge carrier mobility and are, therefore, candidates for channel material in future CMOS devices [1]. In order to design wet chemical solutions that lead to appropriate surface pre-conditioning and allow for nanoscale processing and minimal substrate loss, a thorough understanding of the interactions between the substrate and the chemical solutions is needed and the basic etching mechanisms needs to be resolved. The focus of this research is on InP in acidic solutions. ESH aspects are also considered.
Authors: Kanwal Jit Singh
Abstract: BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moore's law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratio's, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Young's modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .
Authors: M. Sankarapandian, B. Peethala, D. Canaperi, Daniel Peter, Philipp Engesser, Harald Okorn-Schmidt
Abstract: Pattern collapse has long been known in photoresist patterning where the resist patterns merge or collapse during rinsing and drying steps [. The forces responsible for this collapse were identified as capillary forces during the drying process. Structures such as titanium nitride DRAM cylinders [ and silicon Flash shallow trench isolation (STI) lines have also been observed to be pattern collapse sensitive due to increase in aspect ratio of the features. Micro-electromechanical systems (MEMS) devices also show a similar phenomenon, but on a larger length scale, and is referred to as stiction [. For the technology nodes <14 nm, back-end-of-line (BEOL) low-k structures are also on the verge to show pattern collapse behavior. Whether a structure is sensitive to pattern collapse or not depends on several parameters, which will be analyzed in this paper.
Authors: Nicole Ahner, Sven Zimmermann, Matthias Schaller, Stefan E. Schulz
Abstract: The integration of porous ultra low dielectric constant materials (ULK) for isolation within the interconnect system of integrated circuits is a promising approach to reduce RC-delays and crosstalk due to shrinking feature sizes [1]. Actually the focus is on porous CVD-SiCOH materials, which consist of a Si-O-Si backbone and organic species (e.g. CH3) to lower polarizability and prevent moisture uptake to remarkably decrease the k-value [2]. The integration of porous low-k materials is very challenging, especially looking at patterning, resist stripping and etch residue removal, where commonly plasma processing has been applied. But plasma processing of ULK materials, especially using oxygen plasmas, is known to degrade electrical, optical and structural material properties by removing carbon from the film and densification of the surface near areas of the ULK [5]. Carbon depletion may also lead to the incorporation of-OH groups, which easily form silanols and therefore increase moisture absorption and k-values [2]. Besides the development of nondamaging plasma processes, wet cleaning is a promising alternative to avoid ULK damage while removing organic plasma etch residues. Additionally wet cleaning steps are always necessary to remove inorganic residues, which do not form volatile reaction products and can therefore not be removed by plasma processing.
Authors: Els Kesters, Q.T. Le, I. Simms, K. Nafus, H. Struyf, S. De Gendt
Abstract: In back-end of line processing (BEOL), the polymer deposited on the dielectric sidewalls during the etch process must be removed prior to subsequent processing steps to achieve high adhesion and good coverage of materials deposited in the etched features [1, . Typically, this is done by a combination of a short plasma treatment and a diluted wet clean, or by wet cleans alone. On the one hand, for porous dielectric stacks, a mild plasma treatment that preserves the integrity of the low-k dielectrics would not be sufficient to effectively remove this residue. With regard to wet clean, diluted aqueous solutions (e.g. HF-based) are not efficient for polymer removal without etching the underlying dielectric to lift off the polymer, leading to unacceptable critical dimension (CD) loss. In addition, analytical techniques available for direct characterization of sidewall residues are limited. For a fast screening of potential chemistries capable of dissolving/removing polymer residues generated during the low-k etch, a model fluoropolymer was deposited on a blanket, checkerboard low-k substrate. The present study mainly focused on the characterization of model polymer after deposition (as-deposited) and after immersion in aqueous and solvent-based cleaning solutions. The polymer removal efficiency was influenced/ improved by UV treatments prior to wet clean processes. In the second part of the study, selected UV treatment conditions and cleaning solutions were applied to low-k patterned structures using Angle-resolved X-ray photoelectron spectroscopy (AR-XPS) to characterize the dielectric sidewall before and after UV modification and the subsequent cleaning process.
Authors: Francesca Milanesi, Francesco Pipia, Simona Spadoni, Salvo Grasso, Enrica Ravizza, Mario Pistoni, Mauro Alessandri
Abstract: The interest towards Copper RDL (Re-Distribution Layer) is due to some advantages related to this approach. First of all it is cheaper than conventional Damascene approach; moreover it allows thicknesses as high as 10µm or more whereas with Damascene architecture Cu thickness is limited to <5µm. Figure 1 introduces the architecture concept, which is based on a quite long ECD growth on a substrate with patterned PhotoResist.
Authors: Atsushi Otake, Akira Kuroda, Roger Luo, Paul R. Bernatis
Abstract: Copper has become the material of choice for the interconnects in semiconductor devices due to its low resistance and ease of processing [1]. Device fabrication with copper requires electrochemical deposition and chemical mechanical planarization (CMP). Since the polished copper surface generated during CMP is considered to be one of the most important factors which determine the performance of the interconnect, post-CMP cleaners must efficiently remove residues generated by the polishing process [2]. CMP slurries and post-CMP cleaners frequently include corrosion inhibitors to form a protecting layer on copper surface. If a thick organic film remains on copper after cleaning processes, it can have unfavorable effects on performance of copper interconnects. To minimize this issue, the authors earlier described a corrosion inhibitor which formed a very thin protective layer and that was easily removed by plasma treatment [3, 4].
Authors: Hun Hee Lee, Min Sang Yun, Hyun Wook Lee, Jin Goo Park
Abstract: As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+ (dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+ chemicals for cleaning processes also increases [.

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