Abstract: Metallic contamination on silicon surfaces has a detrimental impact on ULSI device performance and yield. Surface metal impurities degrade gate oxide integrity while metal impurities dissolved in silicon cause recombination centers and result in junction leakage. Surface metal impurities penetrate silicon by the colliding with dopant during ion implantation and are also diffused in silicon by subsequent annealing [. The diffusion behavior of metal impurities in silicon is well-known [. While metal impurities often penetrate silicon through the silicon oxide in ULSI processing, little work has been reported on the diffusion behavior of metal impurities penetrating silicon oxide. We demonstrated the diffusion behavior of metal impurities penetrating silicon substrates with different thickness of silicon oxide by the collision with dopant during ion implantation.
Abstract: High-k gate dielectrics and metal gate electrodes have become essential for emerging device technologies because they enable the continuous scaling down of devices while maintaining a high performance [. However, since they are composed of novel metallic elements that have never before been used in conventional processes, special care must be taken when handling these materials in the production line. In particular, cross-contamination that occurs due to transporting contamination via processed wafers can cause serious problems such as deterioration of device properties and yield loss [. The process of cleaning the backside and bevel of a wafer is now increasingly important for avoiding these problems. To date, there has been no detailed evaluation of contamination removal on various films performed for elements such as hafnium, which is one of the key elements in high-k/metal gate technologies. In this study, we evaluated hafnium contamination on three types of wafer surface after the cleaning process and investigated the cause of different residual amounts of hafnium contamination on the different wafers.
Abstract: In high-tech processing even smallest concentrations of metal ions in process media are of the utmost significance because they cause expensive production failures. Currently, cost-intensive equipment, special trained staff and time consuming analyses are necessary to detect these contaminations in order to avoid failures. The Centers of Excellence Nanochem and Sensorics at the University of Applied Sciences Regensburg (owner of patent PCT/EP2010/064833) and their industrial partner Micro-Epsilon GmbH are developing a new miniaturized measurement device which allows cost-effective real-time analysis of fluidic media for the first time. The system is fully automated and can be directly connected to wet-etch benches. Hence it allows continuous real-time surveillance of metal contaminations in the ppb-range through absorption spectroscopy in process media. For this purpose a very small sample amount of the process medium and a specific complexing agent are mixed together. This leads to an increase in the molar extinction coefficients and though even smallest contaminations become visible. The main parts of our development are the simulation of the different system components, their production and chemical analyses with the evaluation model.
Abstract: The continuing shrinking of the component dimensions in ULSI technology requires junction depths in the 20-nm regime and below to avoid leakage currents. These ultra shallow dopant distributions can be formed by ultra-low energy (ULE) ion implantation. However, accurate measurement techniques for ultra-shallow dopant profiles are required in order to characterize ULE implantation and the necessary rapid thermal annealing (RTA) processes.
Abstract: Micro-contamination exerts ever-increasing adverse impact on semiconductor manufacturing as device integration scale keeps increasing and device geometry continues decreasing. In particular, contaminations from particles, trace metals, and/or organic compounds can reduce device yield, quality, and reliability [. Metallic impurities from materials used for process equipment are one of the major contamination sources.
Abstract: The large scale of production of modern PV manufacturing as well as the cost pressure demand a different approach to cleaning processes in semiconductor and PV applications. The subject of this presentation is, to highlight aspects of similarities and differences.
Total added cost/m2 of Si are estimated for typical PV manufacturing conditions and compared to semiconductor applications. Typical technical solutions are reviewed. They are compared to the anticipated technical and cost requirements in the near future according to PV roadmaps and cell concepts which are evident today.
Starting with typical cleaning processes during the wafering (sawing, cleaning, separation) up to cell processing (texturing, diffusion, coating and plating) the main cleaning processes are presented and their specifics are indicated. Finally recontamination and conditioning in production lines are reviewed.
Abstract: Although the chemical reaction is well known, the anisotropic etching of Si in alkaline solutions is a complex process. This is particularly true in the solar industry where a large mass of silicon is typically introduced into the etch bath. The etch by-products (silicates) affect the balance of the etching specie. If adequate compensation is not made for these by-products, a significant drop in etch rate and an increase in contamination levels is typically noticed. Because of this contamination, production lines would suffer from unpredictable wafer characteristics and hence lower cell performance.
Abstract: The cumulative installed solar power generation has been rising exponentially over the past decade. This has lead to a concomitant rise in production capabilities, leading eventually to excess production capabilities and rapid price declines per unit. In order to compete with the standard electricity generation the cost of solar panel production and installation needs to decrease even further. At the same time the solar panel and cell makers need to be able to keep a healthy margin. A crucial element in this exercise is a close control on the Cost of Ownership (CoO) of a solar cell / panel fabrication site.
Abstract: The semiconductor industry considers wet cleans to be critical surface preparation steps. The Si/SiO2 interface, for example, is very critical to achieve high gate oxide integrity and avoid leakage or stacking faults. Similarly, the solar industry has seen the value of wet processes to achieve best cell performance. In this study, we highlight the effect of pre-cleans, texturization and final cleans on cell parameters. We also studied the importance of coupling these wet cleaning and texturization steps with the PECVD steps to achieve the film quality required for highest solar cell efficiency.
Abstract: For further enhancement of solar energy conversion efficiency the passivation of silicon (Si) substrate surfaces and interfaces of Si-based solar cell devices is a decisive precondition to reduce recombination losses of photogenerated charge carriers. These losses are mainly controlled by surface charges, the density and the character of rechargeable interface states (Dit) , which are induced by defects localised in a small interlayer extending over only few Å. Therefore, the application of fast non-destructive methods for characterization of the electronic interface properties directly during the technological process has received an increasing interest in recent years.