Abstract: Concerning the processes of the semiconductor industry, device integration is increasing and cell structure is becoming more complicated, which brings many new kinds of challenges. The basic requirements for a future integration device are minimum feature size reduction with device integration and high-speed operation with sufficient cell capacitance. Many kinds of conventional films including electrode and dielectric materials should be altered to meet device requirements. Moreover, as the allowance level for contaminants on substrate surfaces becomes more stringent, the importance of removing them becomes even greater. Because of this, the semiconductor process for high quality device fabrication will never be realized without perfect cleaning on all surfaces. It is reported that the conventional cleaning solutions such as a NH4OH/H2O2/H2O (SC-1) solution (1:4:20, 80 °C), H2SO4/H2O2 (SPM) solution (4:1, 90 to 120°C), and HCl/H2O2/H2O (HPM) solution (1:1:6, 80 to 90°C) are not compatible with metal film exposed surfaces with very tiny patterns, due to the fast etching rate of metal films  . In 1995, at the base of the mechanism of the removal of the adhered contaminants such as metallic impurities, particles and organics, T. Ohmi proposed a total room temperature wet cleaning process (so called “UCT cleaning”) . As a result of the continuous research on developed cleaning, the five steps process was revised to a four step room temperature wet cleaning for real device cleaning. The cleaning consists of 1) CO2 added O3-UPW cleaning for removing organic and metallic impurities, 2) NH3 added H2-UPW+MS cleaning for removing of particles, 3) HF/H2O2(FPM) cleaning for removing metallic impurities, and 4) H2-UPW+MS rinse for the removal of chemical residues, prevention of particle re-adhesion, suppression of native oxide growth, and enhancement of H-termination.
Abstract: HfO2 gate stack has been one of the most popular subjects of research in recent years due to its outstanding material properties, such as high-k (20~25), wide band gap (~5.68eV), and the compatibility with Si-based semiconductor process technology. However, the interfacial layer (IL) with a reduced k-value between HfO2 dielectric and Si channel is still a critical issue for future ultra large scale integration (ULSI) technology application of the HfO2 gate stack. Various ways have been studied to improve the IL properties of HfO2 gate stack and to achieve ~1nm-thick equivalent oxide thickness (EOT) of the gate stack. Recently, fluorine incorporations into the HfO2 gate stack have been suggested for improvement of the electrical properties of the gate stack by defect passivation.1,2 However, it was reported that the SiOx IL grows during the fluorine treatment of HfO2 film, which finally led to degradation of electrical characteristics.2 In this paper, we present interesting findings on the IL removal effect of fluorine incorporation into the HfO2 gate stack where a post-gate dry cleaning technique is used with the NF3/NH3 plasma.
Abstract: Novel scaling approaches such as sGe channels on strain relaxed SiGe buffers, source/drain (S/D) stressors for FINFETs are usually grown using epitaxial process. Prior to the epitaxial growth, the starting surface should be free from oxygen and organic impurities. If not, these impurities would act as nucleating centres for defect formation resulting in defective epi growth. Conventionally, the wafers are HF dipped and then subjected to in-situ hydrogen bake at a temperature of 800°C in order to remove the above said impurities present on the wafer surface . However, subjecting the strain relaxed SiGe to such high temperature baking would lead to roughening/islanding and subjecting the fins to high temperature baking might result in severe surface reflow . As a result, the device performance would be adversely affected.
Abstract: Epitaxial growth requires a clean starting surface for the growth of a high-quality crystalline layer. For epitaxy on Si, an HF-last wet clean followed by an in-situ high-temperature hydrogen bake is the reference pre-epi clean sequence to obtain an oxygen-free surface [1, 2]. The temperature required to remove all residual oxygen also makes the surface atoms mobile, resulting in reflow. The high temperatures used during the H2-bake can also result in intolerable doping profile changes. A lower temperature pre-epi clean sequence is required to avoid this reflow, especially when moving away from Si. In addition the high temperatures needed during a H2-bake would result in the relaxation of high mobility channels, e.g. strained Si1-xGex or III-V materials . Several low temperatures pre-epi cleaning solutions have been proposed in the past, e.g. GeH4-assisted H2-bake  or more recently, a GeH4-assisted HCl clean . In this study we looked at the interaction between HF-last wet clean and the in-situ GeH4-assisted HCl clean prior to Si0.8Ge0.2-on-Si epitaxy.
Abstract: PR-mask oxide wet etching process is generally applied for the formation of dual gate oxide (Gox) transistor (TR) with different thickness of gate oxide. Oxide residues, which could not be removed properly with conventional wet etching process by dHF was observed when PR rework process by strip with SPM and SC1 was preceded before oxide wet etching. The root cause on this oxide removal retardation issue was studied by XPS for the analysis of surface element, SEM for the observation of surface morphology and optical spectroscopy for the measurement of thickness of oxide. It was found that PR rework process is main factor for oxide residue, because no unetched oxide layer was observed after dHF etching if there was no PR rework. A model test showed that when NH4OH component was included during PR rework process, retardation of oxide etching was occurred. The abnormal high content of carbon ingredient on oxide surface after NH4OH treatment with SC1 or NH4OH only solution shows that some kind of blocking layer generated upon adsorbed NH4OH molecules on oxide surface may hinder oxide wet etching by HF. It is postulated that anionic molecules such as PAG (photoacid generator) or anionic surfactant arisen from PR developing process may be able to combine with NH4OH molecules, forming complex layer by electrostatic interaction. This assumption was clearly verified that no oxide residues was found after dHF etching if ozonated water (O3 DIW) treatment was applied between PR developing and oxide wet etching step, since O3DIW can remove organic component with high efficiency, resulting the elimination of blocking layer for wet etching process.
Abstract: RCA clean has evolved since 1965 . Typically used before critical thermal steps, depositions/etches, or after strip operations, these solutions are robust and reliable. Stringent semiconductor demands of shrinking feature size, increased contamination sensitivity and cost pressure have led to cleaning projects that improve performance and reduce chemical usage. One of the sources of contamination is the process chemicals themselves, where wafers are exposed to chemicals for etching or cleaning. Concerns over contamination are compounded in wet benches where chemical baths are re-circulated for periods up to 24 hours. Metal impurities can arise from insufficiently pure chemicals or water, tanks, carriers, plumbing components, chemical containers, incoming wafers and handling equipment. Strict chemical, DIW and material specifications as well as dilute chemistry and reduced temperature have benefited the industry as a whole. Trends such as lower temperature/concentration SC1, and higher temperature/concentration SC2 have reached a point of diminishing returns for metal contamination reduction. In the same way, chemical and water purity are well below detection, so improvements are difficult to quantify.
Abstract: Metal contamination impact on transistors’ degradation has been widely studied. Nonetheless, most of the work has been performed on blanket wafers, or based on punctual yield crisis during the integrated circuits’ manufacturing. This paper proposes a comparison of the contamination and metals removal efficiency between blanket wafers and inside deep silicon trenches.
Abstract: In a typical Power Device on the 0.16μm node, the isolation module is one of the most critical steps. The trench to be filled in those devices is rather deep and needs a considerable amount of a suitable dielectric material. The choice of dielectric in the present paper is falling on the SubAtmosphericUndopedSilicaGlass (SAUSG oxide) .
Abstract: The definition of sub-20 nm electronic devices for the newest generation of smart phones, computer and automotive is calling for very innovative FEOL wet chemical cleans. The electronic properties are very sensitive, in respect of the surface morphology on a Si-wafer. Most of the modern wet cleans are based on the RCA-clean . Innovative cleans, like for example the IMEC-clean  and modified RCA clean were developed, using ozone-DIW mixture (O3-DIW), in order to improve the cleaning performance , . Since several years electrolyzed water (EW) is used in semiconductor manufacturing . An electrochemical reaction is induced by an electrode and a small amount of ammonia hydroxide (NH4OH) or ammonia sulfate and DIW .