1.2 kV SiC MOSFET with Low Specific ON-Resistance and High Immunity to Parasitic Turn-On

. With the capability to switch at high speed, there are important concerns about Parasitic Turn-On (PTO) when using SiC MOSFETs in switching applications with fundamental half-bridge configuration [1]. In this work, we present 1200V SiC planar MOSFETs with low specific ON-resistance (Rsp), fast switching characteristics and high immunity to PTO. The PTO immunity is verified by experimental comparison to several commercially available SiC MOSFETs.


Introduction
SiC MOSFETs are now widely used in numerous applications, especially automotive applications such as traction inverters and fast charging stations.Thanks to its superior physical properties, SiC MOSFETs are expected to operate with low RDSON and fast switching condition.Nevertheless, under fast switching condition in half-bridge configuration, complementary device, i.e., Body Diode (BD) can experience unwanted PTO [1,2].
PTO is described as an unwanted effect during MOSFET switch turn-on, i.e., BD turn-off.Here, while BD VDS rising to take VDD, device's internal nonlinear capacitances like CGS, CGD and CDS are also in transient mode.Charging current from CGD unwantedly charge CGS as well as gate resistor RG_EXT+ RG_INT and pull-up the HS VGS.If the HS VGS is pulled over device's VTH, the BD channel will open under a high VDS voltage.The HS VGS pulled-up event during BD turn-off was described as [2]: (1) Equation ( 1) qualitatively stated that, HS VGS pull-up depend on device's CGS, CGD, switching speed and total RG.There were efforts on design novel gate drivers to limit PTO when using SiC MOSFETs in switching application [3].Therefore, from device design perspective, it is important to design and optimize the device structure to obtain SiC MOSFETs that are highly robust against PTO.
In this work, we introduce 1200V SiC MOSFETs with low RDSON, fast switching characteristics and an optimized capacitance CISS/CRSS ratio for a highly robust device against PTO.

Device Fabrication and Measurements Set-up
Planar implanted SiC MOSFETs with a total chip area of 24.6mm 2 and optimized cell design for 1200V were fabricated using 150mm SiC epitaxial wafers.Devices were then packaged and measured in TO-247-4L housing.A Keithley S500 integrated test system were used for DC measurements and pulsed high current measurements, using a pulse width of 230 µs.Double Pulse Tester (DPT) were used for switching measurements and PTO evaluation.In our switching measurements, the Low Side (LS) device is the active switch and High Side (HS) device is the BD.Simplified device structure, measurements set-up and simplified circuit diagram were described elsewhere [4,5].

DC Characteristics
Fig. 1a represents the typical measured device's transfer characteristics at RT and at 175°C, with VDS=0.1V.Device's typical VTH is 3V at RT and 2V at 175ºC, respectively (with VD=VG @ID=33mA).Fig. 1b shows measured output characteristics at RT and 175ºC, with VGS=18V.Device's typical RDSON is 12 mΩ at RT and 25 mΩ at 175ºC, respectively.The measured device will be referred as device #1 in following sections.

Switching Characteristics
For switching evaluation, the same type of device as well as gate driver and RG_EXT was always used on both high side (HS) BD and low side (LS) switch.Fig. 2 show the measured switching turnon and turn-off characteristics of the device #1 with ID=140A, corresponding to J=700A/cm 2 .Fast switching characteristics is observed where the devices turn-off ID=140A in less than 20ns, and turnon at di/dt≈ 6A/ns with extracted EOFF=1160µJ and EON=1280µJ, respectively.The observed oscillations are difficult to avoid in the DPT system for these fast switching events.

Capacitance-Voltage (C-V) Characteristics
As discussed, PTO occurs during HS BD turn-off and it is caused by the charging current of the reverse transfer capacitance CRSS as it creates a voltage drop across the total gate resistance (RG_INT+RG_EXT) and the input capacitances CISS [1,2].If the VGS induced by this CRSS charging event exceeds device's VTH, then PTO is triggered in the HS MOSFET and creates additional BD "reverse recovery" current.PTO is therefore dependent on device capacitances like CRSS and CISS, the total gate resistance (RG_INT+RG_EXT), the switching speed, VTH, and temperature.Fig. 3a shows high voltage C-V characteristics of device #1 with good CISS/CRSS ratios over a wide VDS range.For comparing different devices, we present the area independent CISS/CRSS ratio.Fig. 3b displays measured CISS/CRSS ratio of the devices #1 and three reference commercially available SiC MOSFETs.Device #1 shows significantly higher CISS/CRSS ratio compared to the other devices for the whole VDS range.Other parameters that could affect device's PTO characteristics like devices RG_INT and VTH as well as its RT RDSON were also listed in Table #1

Parasitic Turn-On
To investigate PTO, LS switch conditions (e.g., VGS, Temperature, RG_EXT) were kept constant to maintain a fixed di/dt.HS VGS=0V were applied and HS device were varied in HS RG_EXT and in temperature (from RT to 175°C).VDD=800V were applied in this study.
Fig. 4a shows measured switching turn-on characteristics using the device #1 at RT as the HS BD, with different HS RG_EXT.No switching turn-on dependence on HS RG_EXT is observed even with very high HS RG_EXT.Same measurements with even higher RG_EXT up to few hundreds Ω or device with even lower RT VTH, e.g., VTH=2.1V also show almost no sign of PTO (data not shown).
Fig. 4b-d) represent measured switching turn-on characteristics with different HS RG_EXT, using competitor A (trench), competitor B (planar) and competitor C (planar) as the HS BD at RT, respectively.Different degrees of PTO can be observed when using these devices as the HS BD.We believe the excellent CISS/CRSS ratio as shown in Fig. 3b is the critical factor for the high immunity to PTO that is observed for the device #1, and that this CISS/CRSS ratio is more important to suppress PTO than the VTH level.High Temperature Parasitic Turn-On Fig. 5 displays measured turn-on characteristics vs. RG_EXT using device #1 as the HS BD at 175°C, at different current densities.At T=175°C (with a lower VTH compared to RT) at different current densities with VDD=800V and a turn-on di/dt=6A/ns, no sign of PTO can be observed, even with a high RG_EXT=56Ω.These results further highlight the strong immunity of device #1 against PTO.

Fig. 3b .
Fig. 3b.Measured CISS/CRSS ratio of the devices considered in this work.

Solid State Phenomena Vol. 360 Fig. 4 .
Fig. 4. Measured switching turn-on with HS RG_EXT variation for PTO evaluation by using different devices as the BD: a) Device #1; b) Competitor A Trench; c) Competitor B Planar; d) Competitor C Planar.

Fig. 5 .
Fig. 5. Measured switching turn-on with HS RG_EXT variation for PTO evaluation measured by using device 1 as the HS BD in T=175°C with different current densities.

Table 1 .
. Summary of measured RG_INT and VTH as well as RDSON of device considered in this work