Solid State Phenomena, ISSN: 1662-9779, Vol. 360, pp 95-101

doi: 10.4028/p-hWcw4I

© 2024 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2023-09-06

Accepted:
2024-04-12

Online:
2024-08-23

On the TCAD Modeling of Non-Permanent Gate Current Increase During Short-Circuit Test in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/SSP.360.95.pdf

Jaume Roig , Sara Kochoska , Basil Vlachakis , Jimmy Franchi and Thanh-Toan Pham

onsemi, Westerring 15, 9700 Oudenaarde, Belgium

onsemi, Einsteinring 28, 85609 Aschheim, Germany

onsemi, Isafjordsgatan 32C, 16440 Kista, Sweden

jaume.roig@onsemi.com, sara.kochoska@onsemi.com, basil.vlachakis@onsemi.com, djimmy.franchi@onsemi.com, Thanh-Toan.Pham@onsemi.com

Keywords: short circuit, gate leakage, thermionic effect, direct tunneling model.

Abstract

Under short-circuit (SC) testing SiC MOSFETs exhibit an exceptional increase of gate current ( 100 's mA ) which is not observed in their Si counterparts. Electro-thermal TCAD simulations are capable to accurately mimic all the details of measured gate current waveforms ( ) by capturing multiple physical mechanisms. One of these mechanisms is the thermionic or Schottky emission effect occurring at extreme temperatures ( ) for relatively thick gate oxides ( ). For the first time, it is proven that TCAD tunneling models, recommended for very thin oxides ( ), are suitable to reproduce the thermionic effect and predict in SiC MOSFETs under SC test.

Introduction

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SiC power devices have gained significant attention in recent years due to their superior performance compared to traditional silicon-based devices. However, the design and optimization of SiC power devices pose unique challenges, particularly in the realm of Technology Computer-Aided Design (TCAD) modeling. TCAD physical models play a crucial role in simulating and predicting the behavior of semiconductor devices, aiding in their design, fabrication, and reliability assessment.

The transition from Si to SiC introduces several complexities that make TCAD modeling for SiC power devices a challenging task. First, SiC exhibits unique material properties, such as wide bandgap, high breakdown voltage, and high thermal conductivity, which significantly improve device performance [1,2,3]. Most of these material properties lack a standardized material parameter database for SiC . Second, SiC devices can exhibit complex physical phenomena, including trapping and recombination mechanisms, interface states, electro-thermal anisotropy, and surface roughness effects . Third, SiC power devices often operate at higher temperatures and switching frequencies, leading to increased power densities and self-heating effects.

An accurate representation of electro-thermal effects in TCAD models is crucial for predicting device behavior in short-circuit (SC) test. SC withstanding time (SCWT) is a critical success criterion in inverters for motor control and its simulation requires a combination of TCAD and SPICE elements in the so called mixed-mode (MM) approach. Reproducing SC measured waveforms is only possible by accounting for test circuitry and parasitic elements [9, 10]. Moreover, it has been recently discovered that SiC MOSFETs under SC exhibit unique physical mechanisms that may shape waveforms (see Fig. 1) [11, 12, 13]. Here, refers to non-permanent current and unrelated to thermomechanical degradation [12]. In a previous work [13], in Regions 1 and 2 was categorized as displacement current. Differently, in Region 3 is dominated by thermionic effect through the gate oxide [14]. This work is devoted to the TCAD modelling of Region 3 by means of tunneling models offered by a software vendor [15]. In a first section, these models will be succinctly explained. A second section is focalized on 1D TCAD simulations of SiC MOS to investigate these models and their dependencies. In the end, a third section focuses on 2D TCAD simulations with calibrated power MOSFET structures using tunneling models and being eventually compared with measurements.

Fig. 1. Schematic representation of and waveforms in SiC MOSFETs during a non-destructive SC test. This work is focused on TCAD physical models for Region 3.

Fig. 1. Schematic representation of and waveforms in SiC MOSFETs during a non-destructive SC test. This work is focused on TCAD physical models for Region 3.

Fig. 2. Schematic cross-section of planar SiC MOSFET with a description of temperature points , cutlines AA ' and BB', and band diagram along AA' cutline in inversion conditions.

Fig. 2. Schematic cross-section of planar SiC MOSFET with a description of temperature points , cutlines AA ' and BB', and band diagram along AA' cutline in inversion conditions.

Physical Models for Tunneling and Schottky Emission

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Electron tunneling models for MOS structures play a fundamental role in nanoscale dimensions [16]. It refers to the phenomenon where electrons traverse an oxide barrier in MOS devices, influencing device characteristics such as leakage current, gate capacitance, and subthreshold slope. For relatively low temperature and high electric fields ( ) the Fowler-Nordheim (FN) model is commonly used to analytically calculate the tunneling electron current density by

where is the elementary charge, h the Plank's constant, the semiconductor-oxide barrier height, the effective mass of electron in the oxide and the electrical field magnitude. SC temperatures can surpass 1200 K in the gate oxide ( in Fig. 2), thus enhancing the electron energy over the potential barrier energy as it occurs in Schottky emission (SE). Hence, a more suited model for a scenario with medium and high is the analytical formula for SE in [14]

where is temperature, is Boltzmann's constant, and are the relative and vacuum permittivities. A fundamental difference between Eq. 1 and Eq. 2 is the dependence with . In Eq. 1, , whereas is constant in Eq. 2 due to the explicit dependence. In TCAD simulations there are two available tunneling models for 1D, 2D and 3D MOS structures that are described in the following. Aside from capturing tunneling effects like FN and direct tunnelling (DT), the SE mechanism is also supported for electrons with energies above the potential barrier as schematically described by the energy band diagram in Fig. 2. Other tunneling mechanisms like trap-assisted-tunneling (TAT) are neglected in this study but they may be relevant for gate oxides with low quality and a high density of near-interface traps.

Direct Tunneling Model (DT) is a robust and simple approach to compute the tunneling currents in MOS structures. Its application is restricted to tunneling through insulators due the assumption of a trapezoidal energy barrier and it incorporates the concept of the transmission coefficient in accordance with the model presented in [15]. The electron current density is expressed as

where is a mass prefactor ( ) and is the energy of the elastic tunneling process. Inside the integral in Eq. 3, is a function derived from the integration of the Fermi-Dirac distribution function, multiplying the temperature at the two sides of the oxide barrier. is the transmission coefficient, which is a measure of the probability that an electron will successfully tunnel through the barrier. has intrinsic dependences on , effective thickness of the barrier ( ), and effective masses in gate contact, insulator and semiconductor substrate ( and for electrons in SiC MOS). For a 1D MOS structure, is merely the oxide thickness ( ), however a 2D scenario requires an analysis along different paths for every interface point. A complete description of the model formulation and implementation is available in [15].

Non-Local Tunneling Model (NLT) is the most versatile modeling approach used to accurately simulate carrier tunneling but it also implies high computational cost. NLT considers the electron transport through the entire device region, accounting for a spatial variation of and its impact on the tunneling probability. As in DT, it is also based on a transmission coefficient , however computation follows the WKB approximation, and it could be optionally done with 1D Schrödinger equation [18]. Differently from DT, NLT handles arbitrary barrier shapes, includes carrier heating terms, and allows to describe tunneling between the valence band and conduction band.

1D MOS Analysis

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In order to perform a simplified comparison between models, a 1D MOS TCAD structure is built following the layer stack described by AA' in Fig. 2. This basic structure is constituted by a layer with sandwiched between two highly doped n -type and PolySi layers. An area factor to convert current density into current is roughly estimated by considering the die area and the overlap between source and PolySi gate in a commercial 1.2 kV SiC MOSFET [19], named as DUT1 in this manuscript. Electrical simulations are conducted by sweeping the AA' potential ( ) in stationary conditions for different temperatures. The simulated vs. and vs. T curves are plotted in Figs. 3 and 4, respectively, including the analytical calculations from the sum of Eq. 1 and Eq. 2. It is inferred from Fig. 3 that all the models generate an in a range between mA and A for the typical SC conditions of and Temperature ( ).

Fig. 3. vs. for different Temperatures ( ) comparing 1D TCAD simulations (NLT & DT) and analytical calculations (Eq. Eq. 2). DT uses .

Fig. 3. vs. for different Temperatures ( ) comparing 1D TCAD simulations (NLT & DT) and analytical calculations (Eq. Eq. 2). DT uses .

Fig. 4. vs. Temperature at comparing 1D TCAD simulations (NLT & DT) and analytical calculations (Eq. Eq. 2). DT uses and constant .

Fig. 4. vs. Temperature at comparing 1D TCAD simulations (NLT & DT) and analytical calculations (Eq. Eq. 2). DT uses and constant .

Fig. 5. (a) vs. for different temperatures ( ) from measurements, 1D TCAD simulations (DT) and analytical calculations (Eq. Eq. 2). (b) Zoom in (a) for the region dominated by FN effect ( )

Fig. 5. (a) vs. for different temperatures ( ) from measurements, 1D TCAD simulations (DT) and analytical calculations (Eq. Eq. 2). (b) Zoom in (a) for the region dominated by FN effect ( )

The good match between NLT and DT models at is better observed from the yellow and violet symbols in Fig. 4 when , where both models show an above the analytical calculations. In terms of computational speed, DT runs two times faster than NLT and is less prone to suffer convergence issues. To further simplify the DT model, a constant is evaluated. It can be observed by Fig. 3 (grey symbols) that using an average , which is the value provided in [20] at 1500 K , is also a reasonable approach. On the other hand, fixing (orange symbols), which is the value assumed at 300 K , leads to an drop of two orders of magnitude in the Temperature space of interest. Finally, it is also interesting to observe that , typically used in Si at 300 K , diminishes in one order of magnitude compared to SiC at 300 K . This means that Region 3 is not expected to be noticeable in Si MOS devices due to the larger barrier height.

A deeper analysis of a scenario dominated by FN is possible from Fig. 5. Moreover, Fig. 5 includes stationary measurements in DUT1 for temperatures below 500 K . At relatively low temperature, a FN dominance is observed for . Despite the current resolution limit of the B1505 curve tracer ( ), it can be observed that both DT simulations and analytical formulas are able to predict the right order of magnitude. As shown in Fig. 3, NLT simulations exhibit four orders of magnitude larger , thus being less accurate than DT in conditions with predominant FN.

2D Power MOSFET Analysis

The original version of this paper is available on https://www.scientific.net/SSP.360.95.pdf

This section reports the results from SC test in MM simulations with DT model. Aside from the DT model, the rest of the TCAD models related to electrical properties and the test setup parasitics were calibrated in preliminary works for DUT1 [1, 9, 10]. To properly account for the self-heating effect, reported SiC thermal models are used [3]. It is worth to point out that prior works never included TCAD tunneling models to replicate in this specific scenario. As a closest reference, a circuit model for was developed for electro-thermal macro-modelling in [21]. Other works using TCAD tools to reproduce SC in power MOSFETs show an increase at the instant where rises due to thermal runaway [20]. Under these circumstances, is essentially constituted by displacement current generated from the fast potential decay under the gate, as described in [8].

Fig. 6 compares simulated and measured waveforms for and extracted with the following set of conditions: and room temperature. Fig. 7 extends the comparison to different values and 800 V ). Both Figs. 6 and 7 exhibit a reasonably good match between measurement and simulation. Some discrepancies in are most probably causing slightly larger values simulated . A deeper analysis of and , plotted in Fig. 8, shows that during the ramp-time ( ), and remain under the metal fusion point and the intrinsic temperature , respectively. This is in accordance with the fact that DUT1 does not fail or degrade during a single SC test.

Furthermore, under the same SC test conditions, a sequence of ten SC tests are conducted on the same DUT1, with cooling intervals of 30 s between consecutive SC tests. This sequenced test does not show a variation in the measured waveforms, nor the main electrical parameters, including Ig. Fig. 9 exhibits the SiC surface electron tunnelling current density ( ), perpendicular electric field ( ) and lattice temperature ( ) profiles at times indicated in Fig. 8. As expected, the maximum is found in the area with highest under the overlap between source and PolySi gate. However, Fig. 9 reveals that the channel region along the Pbody is also significantly contributing to as well. This relevant contribution in the channel area obeys to a combination of high and high , where the latter is approximately 100 K higher than the in the area with PolySi overlap. Aside from these two areas, is negligible in the rest of the gate interface. As a final remark, from the 2D nature of the thermionic effect along the gate, it can be concluded that 2D TCAD simulations are expected to offer an improved prediction of current during the SC test compared to 1D TCAD simulations or analytical formulas.

Fig. 6. Measured vs. TCAD simulated waveforms for and ( link ) in a SiC MOSFET. TCAD model includes DT with .

Fig. 6. Measured vs. TCAD simulated waveforms for and ( link ) in a SiC MOSFET. TCAD model includes DT with .

Fig. 8. TCAD simulated waveforms for , and . times selected for inspection of physical magnitudes are indicated.

Fig. 8. TCAD simulated waveforms for , and . times selected for inspection of physical magnitudes are indicated.

Fig. 7. Measured vs. TCAD simulated waveforms for and , ) in a SiC MOSFET. TCAD model includes DT with .

Fig. 7. Measured vs. TCAD simulated waveforms for and , ) in a SiC MOSFET. TCAD model includes DT with .

Fig. 9. SiC surface profiles for and at times indicated in Fig. 8. Top cross section of half basic cell shows the surface position with respect to the gate structure.

Fig. 9. SiC surface profiles for and at times indicated in Fig. 8. Top cross section of half basic cell shows the surface position with respect to the gate structure.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.360.95.pdf

This work addresses the use of TCAD models to replicate the thermionic effect through the gate in SiC power MOSFETs, which is one of the most intricate phenomena appearing during the SC test. The NLT and DT models, normally recommended for nanoscale devices, have been evaluated in 1D MOS and 2D power MOSFET structures. By comparing TCAD simulations to experimental results and analytical calculations it is concluded that the DT model exhibits the best TCAD simulation tradeoff in terms of accuracy and time consumption. Once the DT model with an averaged and constant is established, a deep physical analysis of the dynamic gate current during the SC test is carried out. This analysis reveals that in SiC power MOSFETs there are two main device areas contributing to the by means of the thermionic effect: the PolySi overlap and channel areas. Finally, the good fit between experiment and simulations invites to the usage of TCAD tools as a preferred tool for a more comprehensive understanding of SC-related effects and for a reliable optimization of SiC power MOSFETs with enhanced SC ruggedness.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/SSP.360.95.pdf

We would like to express our sincere gratitude to Detlef Conrad from Synopsys for his support to the understanding and implementation of the models investigated in this work.

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The original version of this paper is available on https://www.scientific.net/SSP.360.95.pdf

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