Papers by Author: Albert A. Burk

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Authors: Qing Chun Jon Zhang, Robert Callanan, Anant K. Agarwal, Albert A. Burk, Michael J. O'Loughlin, John W. Palmour, Charles Scozzie
Abstract: 4H-SiC Bipolar Junction Transistors (BJTs) and hybrid Darlington Transistors with 10 kV/10 A capability have been demonstrated for the first time. The SiC BJT (chip size: 0.75 cm2 with an active area of 0.336 cm2) conducts a collector current of 10 A (~ 30 A/cm2) with a forward voltage drop of 4.0 V (forced current gain βforced: 20) corresponding to a specific on-resistance of ~ 130 mΩ•cm2 at 25°C. The DC current gain, β, at a collector voltage of 15 V is measured to be 28 at a base current of 1 A. Both open emitter breakdown voltage (BVCBO) and open base breakdown voltage (BVCEO) of ~10 kV have been achieved. The 10 kV SiC Darlington transistor pair consists of a 10 A SiC BJT as the output device and a 1 A SiC BJT as the driver. The forward voltage drop of 4.5 V is measured at 10 A of collector current. The DC forced current gain at the collector voltage of 5.0 V was measured to be 440 at room temperature.
Authors: Q. Jon Zhang, Anant K. Agarwal, Craig Capell, L. Cheng, Michael J. O'Loughlin, Albert A. Burk, John W. Palmour, Sergey L. Rumyantsev, T. Saxena, Michael E. Levinshtein, A. Ogunniyi, Heather O'Brien, Charles Scozzie
Abstract: In this paper, for the first time, we report 12 kV, 1 cm2 SiC GTOs demonstrated with a novel negative bevel termination, which improves the breakdown voltage by >3.5 kV compared to the conventional multiple-zone Junction Termination Extension (JTE). The significant improvement in the blocking voltage was attributed to the elimination of the electrical field crowding in the periphery of the mesa with conventional JTE termination. This new termination has been used in both electrically and optically triggered SiC GTOs. An ultrafast turn-on speed of 70 ns has been measured on 12 kV, 1 cm2 SiC light triggered GTOs.
Authors: Q. Jon Zhang, Charlotte Jonas, Albert A. Burk, Craig Capell, Jonathan Young, Robert Callanan, Anant K. Agarwal, John W. Palmour, Bruce Geil, Charles Scozzie
Abstract: 4H-SiC BJTs with a common emitter current gain (b) of 108 at 25°C have been demonstrated. The high current gain was accomplished by using a base as thin as 0.25 μm. The current gain decreases at high temperatures but is still greater than 40 at 300°C. The device demonstrates an open emitter breakdown voltage (BVCBO) of 1150 V, and an open base breakdown voltage (BVCEO) of 250 V. A low specific on-resistance of 3.6 mW-cm2 at 25°C was achieved. The BJTs have shown blocking capabilities over a wide range of operating temperatures up to 300°C.
Authors: Anant K. Agarwal, Qing Chun Jon Zhang, Robert Callanan, Craig Capell, Albert A. Burk, Michael J. O'Loughlin, John W. Palmour, Victor Temple, Robert E. Stahlbush, Joshua D. Caldwell, Heather O'Brian, Charles Scozzie
Abstract: In this paper, for the first time, we report a large area (1 cm2) SiC GTO with 9 kV blocking voltage fabricated on 100-mm 4H-SiC substrates with much reduced Basal Plane Dislocation (BPD) density. The static and dynamic characteristics are described. A forward drop of 3.7 V at 100 A (100 A/cm2) is measured at 25°C. A slight positive temperature coefficient of the forward drop is present at 300 A/cm2, indicating the possibility of paralleling multiple devices for higher current capability. The device exhibits extremely low leakage currents at high temperatures. The device has shown fast turn-on time of 53.9 nsec, and ~3.5 s of turn-off time, respectively. A stable forward voltage drop after electrical stress for >1000 hours has been achieved.
Authors: Robert E. Stahlbush, Nadeemullah A. Mahadik, Q. Jon Zhang, Albert A. Burk, Brett A. Hull, Jonathan Young
Abstract: Basal plane dislocations (BPDs) introduced into SiC epitaxial layers, 25 μm thick, by the combination of implantation and activation anneal are directly observed by ultraviolet photoluminescence (UVPL) imaging. BPD loops appear to originate at micron-sized or smaller areas at the surface. These loops expand by gliding along the basal plane in the offcut direction until the loops approach the substrate. The loops can glide perpendicular to the offcut direction by many millimeters.
Authors: Nadeemullah A. Mahadik, Robert E. Stahlbush, Joshua D. Caldwell, Michael J. O'Loughlin, Albert A. Burk
Abstract: The effect of extended defects on carrier lifetime was investigated in 140 um thick 4H-SiC epilayers using whole wafer ultraviolet photoluminescence (UVPL) and microwave photoconductive decay (uPCD) mapping. Half-loop arrays (HLA) seen in the UVPL images showed a corresponding lifetime degradation in the same region, even before expansion of the HLAs to form SFs. Lifetime lowering was also seen for a defect comprising of a small 3C-SiC inclusion with a larger misoriented 4H-SiC region. Additionally, formation of slip planes after high temperature annealing was observed, which consequently shows a lifetime reduction in that region.
Authors: Anant K. Agarwal, Albert A. Burk, Robert Callanan, Craig Capell, Mrinal K. Das, Sarah K. Haney, Brett A. Hull, Charlotte Jonas, Michael J. O'Loughlin, Michael O`Neil, John W. Palmour, Adrian R. Powell, Jim Richmond, Sei Hyung Ryu, Robert E. Stahlbush, Joseph J. Sumakeris, Q. Jon Zhang
Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.
Authors: Elif Berkman, R.T. Leonard, Michael J. Paisley, Y. Khlebnikov, Michael J. O'Loughlin, Albert A. Burk, Adrian R. Powell, D.P. Malta, E. Deyneka, M.F. Brady, I. Khlebnikov, Valeri F. Tsvetkov, H.McD. Hobgood, Joseph J. Sumakeris, C. Basceri, Vijay Balakrishna, Calvin H. Carter Jr., C. Balkas
Abstract: Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.
Authors: Sei Hyung Ryu, Lin Cheng, Sarit Dhar, Craig Capell, Charlotte Jonas, Robert Callanan, Michael J. O'Loughlin, Albert A. Burk, Aivars J. Lelis, Charles J. Scozzie, Anant K. Agarwal, John W. Palmour
Abstract: We present our recent developments in 4H-SiC power DMOSFETs. 4H-SiC DMOSFETs with a room temperature specific on-resistance of 3.7 mΩ-cm2 with a gate bias of 20 V, and an avalanche voltage of 1550 V with gate shorted to source, was demonstrated. A threshold voltage of 3.5 V was extracted from the power DMOSFET, and a subthreshold swing of 200 mV/dec was measured. The device was successfully scaled to an active area of 0.4 cm2, and the resulting device showed a drain current of 377 A at a forward voltage drop of 3.8 V at 25oC.
Authors: Sei Hyung Ryu, Lin Cheng, Sarit Dhar, Craig Capell, Charlotte Jonas, Jack Clayton, Matt Donofrio, Michael J. O'Loughlin, Albert A. Burk, Anant K. Agarwal, John W. Palmour
Abstract: We present our latest developments in ultra high voltage 4H-SiC IGBTs. A 6.7 mm x 6.7 mm 4H-SiC N-IGBT with an active area of 0.16 cm2 showed a blocking voltage of 12.5 kV, and demonstrated a room temperature differential specific on-resistance of 5.3 mΩ-cm2 with a gate bias of 20 V. A 4H-SiC P-IGBT exhibited a record high blocking voltage of 15 kV, while showing a differential specific on-resistance of 24 mΩ-cm2. A comparison between P- and N- IGBTs in 4H-SiC is provided in this paper.
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