Papers by Author: Bernd Thomas

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Authors: Birgit Kallinger, Bernd Thomas, Patrick Berwian, Jochen Friedrich, Gerd Trachta, Arnd Dietrich Weber
Abstract: Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.
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Authors: Dethard Peters, Wolfgang Bartsch, Bernd Thomas, R. Sommer
Abstract: The paper compares static and dynamic characteristics of 6.5 kV SiC PiN diodes fabricated with different p-emitters. The version with the thickest p-emitter (4 µm) showed the lowest forward voltage (3.4 V at 100 A/cm²) and the lowest (negative) temperature coefficient. Forward voltage DC stress tests revealed a stability within the measurement error of the test apparatus (<50 mV). The dynamic performance showed a soft recovery even at 4 kV. The reverse recovery charge Qrr is analyzed for different forward currents and junction temperatures. The dynamic losses of the SiC PiN diode are marginal with view to the application in industrial inverters.
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Authors: Christian Hecht, Bernd Thomas, René A. Stein, Peter Friedrichs
Abstract: In this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 7×3” or 6×100mm wafers per run in a new 100mm setup. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm and 7×3” runs will be shown. Results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3”, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.
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Authors: Dethard Peters, Bernd Thomas, T. Duetemeyer, T. Hunger, R. Sommer
Abstract: The paper describes first results of 6.5 kV SiC PiN diode modules which are designed as neutral point valves for medium-voltage power inverters rated for 1000 A. The power module consists of 4 AlN DCB substrates soldered on an AlSiC base plate. Each DCB is equipped with 20 SiC PiN diodes operating in parallel. The total active area of all 80 diode chips is 5.68 cm². At the rated current of 2 x 500A the forward voltage drops from 4.1 V at room temperature to 3.9 V at an averaged junction temperature of 125°C. The switching experiments show a very low reverse recovery charge of about 30 µC only. The conduction loss is comparable to the corresponding 6.5 kV silicon diode whereas the dynamic loss is marginal with respect to the forward conduction loss if the switching frequency is held below 10 kHz.
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Authors: Bernd Thomas, Christian Hecht, René A. Stein, Peter Friedrichs
Abstract: The rapid market development for SiC-devices during the last years can be attributed particularly to the success in supplying high-quality SiC wafers and corresponding epitaxial layers. The device quality could be enhanced and the costs were reduced by enlarging the wafer size as well as by a significant progress in epitaxial growth of active layers by using multi-wafer CVD systems. In this paper we want to give an overview of CVD multi-wafer systems used for SiC growth in the past and today. We present recent results of SiC homoepitaxial growth using our multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5×3” wafers per run and can be upgraded to a 7×3” or 5×4” setup. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity of doping and thickness have been grown. Issues like reproducibility, drift of parameters and system stability over several runs will be discussed.
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Authors: Ioana Pintilie, L. Pintilie, K. Irmscher, Bernd Thomas
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Authors: Birgit Kallinger, Bernd Thomas, Sebastian Polster, Patrick Berwian, Jochen Friedrich
Abstract: Basal Plane Dislocations (BPDs) in SiC are thought to cause degradation of bipolar diodes with blocking voltages > 2kV by triggering the formation and expansion of stacking faults during device operation. Hence, low N doped, thick epitaxial layers without BPDs are urgently needed for the realization of long-term stable SiC bipolar diodes. Such epilayers can be achieved if the conversion of the BPD into another harmless dislocation type is supported by proper epitaxial growth parameters and use of vicinal (off-cut) substrates. In this work, the influence of the substrate’s off-cut angle and of the epilayer thickness on BPD density and surface morphology were investigated. The BPD densities of epilayers grown on 2° and 4° off-cut substrates were very low compared to growth on 8° off-axis substrates. X-Ray Topography has proved that all the Threading Dislocations (TD) propagate from the substrate to the epilayer and that BPDs in the substrate convert to Threading Edge Dislocations (TED) in the epilayer, i.e. the dislocation density (DD) of the substrate determines the epilayer’s DD. The conversion of BPDs is supported by the presence of bunched steps as for growth of thick layers on 2° and 4° off-cut substrates.
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Authors: René A. Stein, Bernd Thomas, Christian Hecht
Abstract: Epitaxial layers have been grown on the (0001) C-face of 2- and 3-inch 4H-SiC wafers. Growth conditions like temperature, pressure, and C/Si ratio have been varied. In both systems smooth surface morphologies could be obtained. The main challenge of epitaxial growth on the Cface of 4H-SiC for electronic device applications seems to be the control of low doping concentration. High temperature and low pressure are the key parameters to reduce the nitrogen incorporation. The hot-wall CVD system used for these experiments allowed the application of higher temperatures and lower pressures than the cold-wall equipment. The lowest doping concentration of 2.5x1015 cm-3 has been achieved by hot-wall epitaxy using a temperature of 1625 °C, a system pressure of 50 hPa, a C/Si ratio of 1.4, and a growth rate of 6.5 2mh-1. Good doping homogeneity on 2-inch and 3-inch wafers could be achieved. For a doping level of ND-NA= 3×1015 cm-3 sigma is about 15%.
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Authors: Bernd Thomas, Christian Hecht
Abstract: In this paper we present recent results of epitaxial growth of 4H-SiC on 3” (0001) 8° and 4° off-oriented wafers using a multi-wafer hot-wall CVD system. This equipment exhibits a capacity of 5x3” or 7x2” wafers per run. By optimizing the process conditions epitaxial layers with excellent crystal quality, purity and homogeneity in doping and thickness were grown. The intra-wafer as well as the wafer-to-wafer homogeneity will be illustrated by doping and thickness mappings of a full-loaded run. Surface morphology of epitaxial layers on 8° and 4° off-oriented wafers was investigated by atomic force microscopy.
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Authors: Christian Hecht, René A. Stein, Bernd Thomas, Larissa Wehrhahn-Kilian, Jonas Rosberg, Hiroya Kitahata, Frank Wischmeyer
Abstract: In this paper, we present first results of epitaxial layer deposition using a novel warm-wall CVD multi-wafer system AIX 2800G4 WW from AIXTRON with a capability of processing 10x100mm wafers per run. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 10x100mm runs will be shown and compared to results of the 6x100mm setup of our hot-wall reactor VP2000HW by AIXTRON used for device production since 2001.
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