Papers by Author: Brett A. Hull

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Authors: Brett A. Hull, Sei Hyung Ryu, Q. Jon Zhang, Charlotte Jonas, Michael J. O'Loughlin, Robert Callanan, John W. Palmour
Abstract: DMOSFETs fabricated in 4H-SiC with capabilities for blocking in excess of 1700V and conducting 20A continuous current in the on-state are presented. These SiC DMOSFETs remain functional to temperatures in excess of 225°C, with leakage current at 1700V at 225°C of less than 5 A with VGS = 0V. The DMOSFETs show excellent switching characteristics, with total switching energy of 1.8 to 1.95 mJ over the entire temperature range of testing (25°C to 200°C), when switched from the blocking state at 1200V to conducting at 20A in a clamped inductive load switching circuit. The electrical characteristics are compared to commercially available Si IGBTs rated to 1700V with similar current ratings as the SiC DMOSFET described herein.
Authors: Sei Hyung Ryu, Sumi Krishnaswami, Brett A. Hull, Bradley Heath, Fatima Husna, Jim Richmond, Anant K. Agarwal, John W. Palmour, James D. Scofield
Abstract: High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.
Authors: Robert E. Stahlbush, Nadeemullah A. Mahadik, Q. Jon Zhang, Albert A. Burk, Brett A. Hull, Jonathan Young
Abstract: Basal plane dislocations (BPDs) introduced into SiC epitaxial layers, 25 μm thick, by the combination of implantation and activation anneal are directly observed by ultraviolet photoluminescence (UVPL) imaging. BPD loops appear to originate at micron-sized or smaller areas at the surface. These loops expand by gliding along the basal plane in the offcut direction until the loops approach the substrate. The loops can glide perpendicular to the offcut direction by many millimeters.
Authors: Anant K. Agarwal, Albert A. Burk, Robert Callanan, Craig Capell, Mrinal K. Das, Sarah K. Haney, Brett A. Hull, Charlotte Jonas, Michael J. O'Loughlin, Michael O`Neil, John W. Palmour, Adrian R. Powell, Jim Richmond, Sei Hyung Ryu, Robert E. Stahlbush, Joseph J. Sumakeris, Q. Jon Zhang
Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.
Authors: Joseph J. Sumakeris, Brett A. Hull, Michael J. O'Loughlin, Marek Skowronski, Vijay Balakrishna
Abstract: We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a semi-sacrificial basal plane dislocation (BPD) conversion epilayer, polishing away a portion of that conversion epilayer to recover a smooth surface and then growing the device epilayers following specific methods to prevent the reintroduction of BPDs. With our best processing, we achieve a BPD density of < 10 cm-2 and an extended defect density of < 1.5 cm-2. Specifics of low BPD processing and particular concerns and metrics will be discussed in regard to process optimization and simplification.
Authors: Sei Hyung Ryu, Sumi Krishnaswami, Brett A. Hull, Bradley Heath, Mrinal K. Das, Jim Richmond, Anant K. Agarwal, John W. Palmour, James D. Scofield
Abstract: 8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.
Authors: Brett A. Hull, Joseph J. Sumakeris, Michael J. O'Loughlin, Q. Jon Zhang, Jim Richmond, Adrian R. Powell, Michael J. Paisley, Valeri F. Tsvetkov, A. Hefner, Angel Rivera
Abstract: DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.
Authors: Mrinal K. Das, Joseph J. Sumakeris, Brett A. Hull, Jim Richmond, Sumi Krishnaswami, Adrian R. Powell
Abstract: The path to commericializing a 4H-SiC power PiN diode has faced many difficult challenges. In this work, we report a 50 A, 10 kV 4H-SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with VF as low as 3.9 V @ 100 A/cm2. Furthermore, incorporation of two independent basal plane dislocation reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices that exhibit a high degree of forward voltage stability with encouraging reverse blocking capability. This results in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm x 8.7 mm power PiN diode chips—the largest SiC chip reported to date.
Authors: Pavel A. Ivanov, Michael E. Levinshtein, Mykola S. Boltovets, Valentyn A. Krivutsa, John W. Palmour, Mrinal K. Das, Brett A. Hull
Abstract: Forward current-voltage (I-V) characteristics and non-equilibrium carrier lifetime, τ were measured in 4H-SiC pin diodes (10-kV rated, 100 μm base width). The τ value was found to be 3.7 μs at room temperature by measurements of open circuit voltage decay. To the best of the authors' knowledge, the above lifetime value is the highest reported for 4H-SiC. The forward voltage drops were measured to be 3.44 V at current density of 100 A/cm2 and 5.45 V at 1000 A/cm2 showing a very deep modulation of the blocking base by injected carriers. Diodes operated well at elevated temperatures up to 400oC. No essential forward degradation was detected after 300- A×min current stress at 400oC.
Authors: Ronald Green, Aderinto Ogunniyi, Dimeji Ibitayo, Gail Koebke, Mark Morgenstern, Aivars J. Lelis, Corey Dickens, Brett A. Hull
Abstract: In this paper, large area (0.18cm2) SiC DMOSFETs with 1.2 kV and 20 A rating are evaluated for power electronic switching applications. A drain-to-source voltage drop VDS of 2 V at a forward drain current of 20 A (JD = 110 A/cm2) was obtained and a specific on-resistance of 18 mΩ-cm2 was extracted at room temperature. The device on-resistance was measured up to 150°C and initially decreases with increasing temperature, but remains relatively flat over the entire temperature range, demonstrating stable device behavior. High voltage blocking of 1.2 kV between 25°C and 150°C is also demonstrated with a gate-to-source voltage VGS = 0 V. The drain leakage current under reverse bias and high temperature stress is shown to increase from 10 μA at 25°C to 27 μA at 150°C while maintaining the full blocking rating of the device. Experimental results from double-pulse clamped inductive load tests are presented demonstrating fast high voltage and high current switching capability. High voltage resistive-switching measurements on parallel connected SiC DMOSFETs were performed with VDS having rise and fall times of 49 and 74 ns respectively. Thermal camera images taken of parallel connected DMOSFET die during repetitive switching operation with VDS = 420 V, IDS = 25 A and a 40% duty cycle shows a 2°C difference in die temperature, which suggests even current sharing and temperature stable device operation.
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