Papers by Author: David J. Spry

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Authors: Kevin M. Speer, David J. Spry, Andrew J. Trunek, Philip G. Neudeck, M.A. Crimp, J.T. Hile, C. Burda, P. Pirouz
Abstract: pn diodes have recently been fabricated from 3C-SiC material heteroepitaxially grown atop on-axis 4H-SiC mesa substrate arrays [1,2]. Using an optical emission microscope (OEM), we have investigated these diodes under forward bias, particularly including defective 3C-SiC films with in-grown stacking faults (SFs) nucleated on 4H-SiC mesas with steps from screw dislocations. Bright linear features are observed along <110> directions in electroluminescence (EL) images. These features have been further investigated using electron channeling contrast imaging (ECCI) [3]. The general characteristics of the ECCI images—together with the bright to dark contrast reversal with variations of the excitation error—strongly suggest that the bright linear features are partial dislocations bounding triangular SFs in the 3C-SiC films. However, unlike partial dislocations in 4H-SiC diodes whose recombination-enhanced dislocation motion serves to expand SF regions, all the partial dislocations we observed during the electrical stressing were immobile across a wide range of current injection levels (1 to 1000 A/cm2).
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Authors: Philip G. Neudeck, J. Anthony Powell, David J. Spry, Andrew J. Trunek, X. Huang, William M. Vetter, Michael Dudley, Marek Skowronski, Jin Qiang Liu
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Authors: Andrew J. Trunek, Philip G. Neudeck, J. Anthony Powell, David J. Spry
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Authors: Philip G. Neudeck, Liang Yu Chen, David J. Spry, Glenn M. Beheim, Carl W. Chang
Abstract: This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA’s on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 °C. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 °C to 500 °C.
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Authors: David J. Spry, Philip G. Neudeck, Liang Yu Chen, Laura J. Evans, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim
Abstract: The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.
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Authors: Philip G. Neudeck, David J. Spry, Liang Yu Chen
Abstract: This work reports a theoretical and experimental study of 4H-SiC JFET threshold voltage as a function of substrate body bias, device position on the wafer, and temperature from 25 °C (298K) to 500 °C (773K). Based on these results, an alternative approach to SPICE circuit simulation of body effect for SiC JFETs is proposed.
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Authors: Andrew J. Trunek, Philip G. Neudeck, David J. Spry
Abstract: We report on further observations of homoepitaxially grown 4H silicon carbide (SiC) cantilevers on commercial on-axis mesa patterned substrates. Mesa shapes with hollow interiors were designed to significantly increase the ratio of dislocation-free cantilever area to pregrowth mesa area. Mesas that did not contain axial screw dislocations (SD’s) continued to expand laterally until uncontrolled growth in the trench regions rises up to interfere / merge with the laterally expanding cantilevers. Molten KOH etching revealed high defect density in regions where trench growth merged with the laterally expanding cantilevers. The remaining portions of the cantilevers, except for central coalescence points, remained free of dislocations.
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Authors: Philip G. Neudeck, David J. Spry, Liang Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim
Abstract: Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.
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Authors: David J. Spry, Philip G. Neudeck, Liang Yu Chen, Glenn M. Beheim, Robert S. Okojie, Carl W. Chang, Roger D. Meredith, Terry L. Ferrier, Laura J. Evans
Abstract: This paper reports on the fabrication and testing of 6H-SiC junction field effect transistors (JFETs) and a simple differential amplifier integrated circuit that have demonstrated 2000 hours of electrical operation at 500 °C without degradation. The high-temperature ohmic contacts, dielectric passivation, and packaging technology that enabled such 500 °C durability are briefly described. Key JFET parameters of threshold voltage, on-state resistance, transconductance, and on-state current, as well as the gain of the differential amplifier integrated circuit, exhibited less than 7% change over the first 2000 hours of 500 °C operational testing.
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Authors: David J. Spry, Andrew J. Trunek, Philip G. Neudeck
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