Papers by Author: Dorothy Lukco

Paper TitlePage

Authors: Laura J. Evans, Robert S. Okojie, Dorothy Lukco
Abstract: We report on the initial demonstration of a tungsten-nickel (75:25 at. %) ohmic contact to silicon carbide (SiC) that performed for up to fifteen hours of heat treatment in argon at 1000 °C. The transfer length method (TLM) test structure was used to evaluate the contacts. Samples showed consistent ohmic behavior with specific contact resistance values averaging 5 x 10-4 Ω-cm2. The development of this contact metallization should allow silicon carbide devices to operate more reliably at the present maximum operating temperature of 600 °C while potentially extending operations to 1000 °C.
841
Authors: David J. Spry, Philip G. Neudeck, Liang Yu Chen, Laura J. Evans, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim
Abstract: The fabrication and prolonged 500 °C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 °C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 °C operating time. Evidence is presented for four distinct issues that significantly impacted 500 °C IC operational yield and lifetime for this wafer.
1112
Authors: Philip G. Neudeck, David J. Spry, Liang Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim
Abstract: Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.
567
Authors: David J. Spry, Philip G. Neudeck, Liang Yu Chen, Dorothy Lukco, Carl W. Chang, Glenn M. Beheim, Michael J. Krasowski, Norman F. Prokop
Abstract: Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC’s with two levels of metal interconnect capable of prolonged operation at 500 °C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 °C. A 3-stage oscillator functioned for over 3000 hours at 500 °C in air ambient. Improved reproducibility remains to be accomplished.
908
Authors: David J. Spry, Philip G. Neudeck, Dorothy Lukco, Liang Yu Chen, Michael J. Krasowski, Norman F. Prokop, Carl W. Chang, Glenn M. Beheim
Abstract: This report describes more than 5000 hours of successful 500 °C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 °C. After 100 hours of 500 °C burn-in, the circuits (except for 2 failures) exhibit less than 10% change in output characteristics for the remainder of 500 °C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460 °C in comparison to what is observed for Earth-atmosphere oven testing at 500 °C.
949
Authors: Robert S. Okojie, Dorothy Lukco
Abstract: We report the initial results of using co-sputtered Pt:Ti 80:20 at. % composition ratio metallization as a diffusion barrier against gold (Au) and oxygen (O), as an interconnect layer, as well as forming simultaneous ohmic contacts to n-and p-type 4H-SiC. Having a single conductor with such combined multi-functional attributes would appreciably reduce the fabrication costs, processing time and complexity that are inherent in the production of SiC based devices. Auger Electron Spectroscopy, Focused Ion Beam-assisted Field Emission Scanning Electron Microscopy and Energy Dispersive Spectroscopy analyses revealed no Au and O migration to the SiC contact surface and minimal diffusion through the Pt:Ti barrier layer after 15 minutes of exposure at 800 oC in atmosphere, thus offering potential long term stability of the ohmic contacts. Specific contact resistance values of 7 x 10-5 and 7.4 x 10-4 Ω-cm2 were obtained on the n (Nd=7 x 1018 cm-3) and p (Na=2 x 1020 cm-3) -type 4H-SiC, respectively. The resistivity of 75 μΩ-cm was obtained for the Pt:Ti layer that was sandwiched between two SiO2 layers and annealed in pure O ambient up to 900 °C, which offers promise as a high temperature interconnect metallization.
381
Showing 1 to 6 of 6 Paper Titles