Papers by Author: Fabrizio Roccaforte

Paper TitlePage

Authors: Francesco La Via, Fabrizio Roccaforte, Antonino La Magna, Roberta Nipoti, Fulvio Mancarella, Peter J. Wellmann, Danilo Crippa, Marco Mauceri, Peter Ward, Leo Miglio, Marcin Zielinski, Adolf Schöner, Ahmed Nejim, Laura Vivani, Rositza Yakimova, Mikael Syväjärvi, Gregory Grosset, Frank Torregrosa, Michael Jennings, Philip A. Mawby, Ruggero Anzalone, Salvatore Coffa, Hiroyuki Nagasawa
Abstract: The cubic polytype of SiC (3C-SiC) is the only one that can be grown on silicon substrate with the thickness required for targeted applications. Possibility to grow such layers has remained for a long period a real advantage in terms of scalability. Even the relatively narrow band-gap of 3C-SiC (2.3eV), which is often regarded as detrimental in comparison with other polytypes, can in fact be an advantage. However, the crystalline quality of 3C-SiC on silicon has to be improved in order to benefit from the intrinsic 3C-SiC properties. In this project new approaches for the reduction of defects will be used and new compliance substrates that can help to reduce the stress and the defect density at the same time will be explored. Numerical simulations will be applied to optimize growth conditions and reduce stress in the material. The structure of the final devices will be simulated using the appropriated numerical tools where new numerical model will be introduced to take into account the properties of the new material. Thanks to these simulations tools and the new material with low defect density, several devices that can work at high power and with low power consumption will be realized within the project.
Authors: Antonella Sciuto, Fabrizio Roccaforte, Salvatore di Franco, Vito Raineri, S.F. Liotta, Sergio Billotta, Giovanni Bonanno, Massimiliano Belluso
Abstract: The fabrication of high sensitive diodes array is very attractive for spectroscopic and astronomical UV imaging applications, particularly when visible light rejection is required. Wide band gap materials are excellent candidates for UV “visible blind” detection. In this paper, we demonstrate an array of Schottky UV-diodes on 4H-SiC with a single pixel area of about 1.44 mm2 and a total area of about 29 mm2. The Schottky photodiodes are based on the pinch-off surface effect, the front electrode being an interdigit Ni2Si contact that allows the direct light exposure of the optically active device area. For the proposed array, the optically active area is about the 48 % of total area. The single pixel dark current was below 0.1 nA up to –50 V and a fabrication yield of about 90 % was observed. The external quantum efficiency of the proposed array exhibits a peak of 45 % at the 289 nm wavelength and a visible rejection ratio > 4 ×103.
Authors: Patrick Fiorenza, Alessia Frazzetto, Lukas K. Swanson, Filippo Giannazzo, Fabrizio Roccaforte
Abstract: In this work the field effect mobility measured on lateral n-channel MOSFETs in 4H-SiC with Al implanted body was correlated with the interface trap density measured on MOS capacitors. The test devices were fabricated on samples subjected to different post implantation annealing conditions (i.e. with or without a protective carbon capping layer) and to an identical post-oxidation annealing in N2O. Despite the improved interfacial morphology, a reduction of the peak mobility (from 40 to 24 cm2V-1s-1) was observed using the carbon capping layer. An increase in the density of interface traps was consistently found. Nanoscale measurements of the active dopant concentration in the SiC channel region by cross-sectional scanning capacitance microscopy showed an higher compensation of p-type SiC for the sample processed without the capping layer, which indicates a more efficient incorporation of nitrogen at the SiO2/SiC interface.
Authors: Vito Raineri, Lucia Calcagno, Filippo Giannazzo, D. Goghero, F. Musumeci, Fabrizio Roccaforte, Francesco La Via
Authors: Mariaconcetta Canino, Filippo Giannazzo, Fabrizio Roccaforte, Antonella Poggi, Sandro Solmi, Vito Raineri, Roberta Nipoti
Abstract: The surface morphology and the electrical activation of P+ implanted 4H-SiC were investigated with respect to annealing treatments that differ only for the heating rate. P+ implantation was carried out in lightly doped n-type epitaxial layers. The implantation temperature was 300 °C. The computed P profile was 250 nm thick with a concentration of 1×1020 cm-3. Two samples underwent annealing at 1400 °C in argon with different constant ramp up rates equal to 0.05° C/s and 40 °C/s. A third sample underwent an incoherent light Rapid Thermal Annealing (RTA) at 1100 °C in argon before the annealing at 1400 °C with the lower ramp rate. The ramp up of the RTA process is a few hundred degrees per second. Atomic Force Microscopy (AFM) micrographs pointed out that the surface roughness of the samples annealed at 1400 °C increases with increasing heating rate and that the critical temperature for surface roughening is above 1100 °C. Independently on the annealing cycle, Scanning Capacitance Microscopy (SCM) measurements showed that the P profiles are uniform over the implantation thickness and have plateau concentration around 9×1018 cm-3 in all the implanted samples. The fraction of P atoms activated as donors is 13% of the total implanted fluence.
Authors: Filippo Giannazzo, Fabrizio Roccaforte, Dario Salinas, Vito Raineri
Abstract: In the present work, we systematically studied the effect of the annealing temperature (from 1400 °C to 1650 °C) on the electrical activation of 4H-SiC implanted with multiple energy (from 40 to 550 keV) and medium dose (1×1013 cm-2) Al ions. The evolution of the acceptor (NA) and compensating donor (ND) depth profiles was monitored by the combined use of scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). We demonstrated that the electrical activation of the implanted layer with increasing annealing temperature is the result of the increase in the acceptor concentration and of the decrease in the ND/NA ratio. Atomic force microscopy (AFM) morphological analyses indicated that the surface quality is preserved even after the 1650 °C annealing process.
Authors: Patrick Fiorenza, Antonino La Magna, Marilena Vivona, Filippo Giannazzo, Fabrizio Roccaforte
Abstract: This paper reports on the conduction mechanisms and trapping effects in SiO2/4H-SiC MOS-based devices subjected to post deposition annealing in N2O. In particular, the anomalous Fowler-Nordheim (FN) tunnelling through the SiO2/4H-SiC barrier observed under consecutive reverse bias sweeps was studied by temperature and time dependent gate current measurements. The excess of gate current with respect to the theoretical FN predictions was explained by a charge-discharge mechanism of Near Interface Traps (NITs) in the oxide. The gate current transient was described with a semi-empirical analytical model, modifying the standard FN model with a time-dependent electric field to account for the neutralization of trapped charges at NITs.
Authors: Emanuela Schilirò, Salvatore di Franco, Patrick Fiorenza, Corrado Bongiorno, Hassan Gargouri, Mario Saggio, Raffaella Lo Nigro, Fabrizio Roccaforte
Abstract: This work reports on the growth and characterization of Al2O3 films on 4H-SiC, by Plasma Enhanced-Atomic Layer Deposition (PE-ALD). Different techniques were used to investigate the morphological, structural and electrical features of the Al2O3 films, both with and without the presence of a thin SiO2 layer, thermally grown on the 4H-SiC before ALD. Capacitance-voltage measurements on MOS structures resulted in a higher dielectric constant (ε~8.4) for the Al2O3/SiO2/SiC stack, with respect to that of the Al2O3/SiC sample (ε~ 6.7). Moreover, Current density-Electric Field measurements demonstrated a reduction of the leakage current and an improvement of the breakdown behaviour in the presence of the interfacial thermally grown SiO2. Basing on these preliminary results, possible applications of ALD-Al2O3 as gate insulator in 4H-SiC MOSFETs can be envisaged.
Authors: Antonino La Magna, Ioannis Deretzis, Filippo Giannazzo, Giuseppe Nicotra, Fabrizio Roccaforte, Corrado Spinella, Rositza Yakimova
Abstract: A Kinetic Monte Carlo scheme is applied to simulate with atomic resolution the synthesis of mono (few) layer(s) graphene (Gr) from a silicon carbide (SiC) substrate by selective evaporation of silicon (Si) atoms. The simulation computes the individual dynamics of the residual carbon (C) atoms which diffuse and reconfigure starting from the positions occupied in the SiC hexagonal lattice to the final Gr honeycomb structure. During the transition they gradually modify hybridization (from sp3 to sp2) and bond partners (from Si-C to C-C). We demonstrate that our method is able to recover the complex evolution steps of the epitaxial Gr on SiC in large systems for large time intervals. Moreover, the simulation results can be validated directly by means of comparison with experimental data when varying the material (e.g. initial surface configuration or polarity) or process (e.g. temperature and pressure) conditions.
Authors: Patrick Fiorenza, Lukas K. Swanson, Marilena Vivona, Filippo Giannazzo, Corrado Bongiorno, Simona Lorenti, Alessia Frazzetto, Fabrizio Roccaforte
Abstract: This paper reports a comparative characterization of SiO2/SiC interfaces subjected to post-oxide-deposition annealing in N2O or POCl3. Annealing process of the gate oxide in POCl3 allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm2V-1s-1) with respect to the N2O annealing (about 20 cm2V-1s-1), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl3, as a consequence of the strong incorporation of phosphorous inside the SiO2 matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl3.
Showing 1 to 10 of 84 Paper Titles