Papers by Author: Feng Pan

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Authors: Quan Run Fan, Feng Pan
Abstract: In traditional EDA flow, Technology mapping is performed after logic synthesis. Besides programmable logic blocks, heterogeneous FPGAs also have some hard blocks, such as memory block and multiplier, built in it. After logic synthesis, it will be difficult for technology mapping to find sub-circuits that can be implemented in hard blocks. In this paper, a systematic technology mapping approach is proposed. In the design phase, with the support of CAD tools, a module based design approach is used to map some design block to large hard blocks. During register transfer level synthesis, some functions that are suitable to be implemented in small hard blocks are identified. Other logic functions are mapped into lookup tables with different input size.
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