Papers by Author: Filippo Giannazzo

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Authors: Patrick Fiorenza, Alessia Frazzetto, Lukas K. Swanson, Filippo Giannazzo, Fabrizio Roccaforte
Abstract: In this work the field effect mobility measured on lateral n-channel MOSFETs in 4H-SiC with Al implanted body was correlated with the interface trap density measured on MOS capacitors. The test devices were fabricated on samples subjected to different post implantation annealing conditions (i.e. with or without a protective carbon capping layer) and to an identical post-oxidation annealing in N2O. Despite the improved interfacial morphology, a reduction of the peak mobility (from 40 to 24 cm2V-1s-1) was observed using the carbon capping layer. An increase in the density of interface traps was consistently found. Nanoscale measurements of the active dopant concentration in the SiC channel region by cross-sectional scanning capacitance microscopy showed an higher compensation of p-type SiC for the sample processed without the capping layer, which indicates a more efficient incorporation of nitrogen at the SiO2/SiC interface.
Authors: Vito Raineri, Lucia Calcagno, Filippo Giannazzo, D. Goghero, F. Musumeci, Fabrizio Roccaforte, Francesco La Via
Authors: Mariaconcetta Canino, Filippo Giannazzo, Fabrizio Roccaforte, Antonella Poggi, Sandro Solmi, Vito Raineri, Roberta Nipoti
Abstract: The surface morphology and the electrical activation of P+ implanted 4H-SiC were investigated with respect to annealing treatments that differ only for the heating rate. P+ implantation was carried out in lightly doped n-type epitaxial layers. The implantation temperature was 300 °C. The computed P profile was 250 nm thick with a concentration of 1×1020 cm-3. Two samples underwent annealing at 1400 °C in argon with different constant ramp up rates equal to 0.05° C/s and 40 °C/s. A third sample underwent an incoherent light Rapid Thermal Annealing (RTA) at 1100 °C in argon before the annealing at 1400 °C with the lower ramp rate. The ramp up of the RTA process is a few hundred degrees per second. Atomic Force Microscopy (AFM) micrographs pointed out that the surface roughness of the samples annealed at 1400 °C increases with increasing heating rate and that the critical temperature for surface roughening is above 1100 °C. Independently on the annealing cycle, Scanning Capacitance Microscopy (SCM) measurements showed that the P profiles are uniform over the implantation thickness and have plateau concentration around 9×1018 cm-3 in all the implanted samples. The fraction of P atoms activated as donors is 13% of the total implanted fluence.
Authors: Filippo Giannazzo, Fabrizio Roccaforte, Dario Salinas, Vito Raineri
Abstract: In the present work, we systematically studied the effect of the annealing temperature (from 1400 °C to 1650 °C) on the electrical activation of 4H-SiC implanted with multiple energy (from 40 to 550 keV) and medium dose (1×1013 cm-2) Al ions. The evolution of the acceptor (NA) and compensating donor (ND) depth profiles was monitored by the combined use of scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). We demonstrated that the electrical activation of the implanted layer with increasing annealing temperature is the result of the increase in the acceptor concentration and of the decrease in the ND/NA ratio. Atomic force microscopy (AFM) morphological analyses indicated that the surface quality is preserved even after the 1650 °C annealing process.
Authors: Patrick Fiorenza, Antonino La Magna, Marilena Vivona, Filippo Giannazzo, Fabrizio Roccaforte
Abstract: This paper reports on the conduction mechanisms and trapping effects in SiO2/4H-SiC MOS-based devices subjected to post deposition annealing in N2O. In particular, the anomalous Fowler-Nordheim (FN) tunnelling through the SiO2/4H-SiC barrier observed under consecutive reverse bias sweeps was studied by temperature and time dependent gate current measurements. The excess of gate current with respect to the theoretical FN predictions was explained by a charge-discharge mechanism of Near Interface Traps (NITs) in the oxide. The gate current transient was described with a semi-empirical analytical model, modifying the standard FN model with a time-dependent electric field to account for the neutralization of trapped charges at NITs.
Authors: Antonino La Magna, Ioannis Deretzis, Filippo Giannazzo, Giuseppe Nicotra, Fabrizio Roccaforte, Corrado Spinella, Rositza Yakimova
Abstract: A Kinetic Monte Carlo scheme is applied to simulate with atomic resolution the synthesis of mono (few) layer(s) graphene (Gr) from a silicon carbide (SiC) substrate by selective evaporation of silicon (Si) atoms. The simulation computes the individual dynamics of the residual carbon (C) atoms which diffuse and reconfigure starting from the positions occupied in the SiC hexagonal lattice to the final Gr honeycomb structure. During the transition they gradually modify hybridization (from sp3 to sp2) and bond partners (from Si-C to C-C). We demonstrate that our method is able to recover the complex evolution steps of the epitaxial Gr on SiC in large systems for large time intervals. Moreover, the simulation results can be validated directly by means of comparison with experimental data when varying the material (e.g. initial surface configuration or polarity) or process (e.g. temperature and pressure) conditions.
Authors: Patrick Fiorenza, Lukas K. Swanson, Marilena Vivona, Filippo Giannazzo, Corrado Bongiorno, Simona Lorenti, Alessia Frazzetto, Fabrizio Roccaforte
Abstract: This paper reports a comparative characterization of SiO2/SiC interfaces subjected to post-oxide-deposition annealing in N2O or POCl3. Annealing process of the gate oxide in POCl3 allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm2V-1s-1) with respect to the N2O annealing (about 20 cm2V-1s-1), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl3, as a consequence of the strong incorporation of phosphorous inside the SiO2 matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl3.
Authors: Francesco Ruffino, Filippo Giannazzo, Fabrizio Roccaforte, Vito Raineri, Maria Grazia Grimaldi
Abstract: In this work, a methodology, based on a self-organization process, to form gold nanoclusters on the 6H-SiC surface, is illustrated. By scanning electron microscopy and atomic force microscopy the gold self-organization induced by annealing processes was studied and modelled by classical limited surface diffusion ripening theories. These studies allowed us to fabricate Au nanoclusres/SiC nanostructured materials with tunable structural properties. The local electrical properties of such a nanostructured material were probed, by conductive atomic force microscopy collecting high statistics of I-V curves. The main observed result was the Schottky barrier height (SBH) dependence on the cluster size. This behaviour is interpreted considering the physics of few electron quantum dots merged with the ballistic transport. A quite satisfying agreement between the theoretical forecast behaviour and the experimental data has been found.
Authors: Marilena Vivona, Giuseppe Greco, Salvatore di Franco, Filippo Giannazzo, Fabrizio Roccaforte, Alessia Frazzetto, Simone Rascunà, Edoardo Zanetti, Alfio Guarnera, Mario Saggio
Abstract: The knowledge of the temperature behavior of Ohmic contacts is an important issue to understand the device operation. This work reports an electrical characterization as a function of the temperature carried out on nickel silicide (Ni2Si) Ohmic contacts, used both for n-type and p-type implanted 4H-SiC layers. The temperature dependence of the specific contact resistance suggested that a thermionic field emission mechanism dominates the current transport for contacts on p-type material, whereas a current transport by tunneling is likely occurring in the contacts on n-type implanted SiC. Furthermore, from the temperature dependence of the electrical characteristics, the activation energies for Al and P dopants were determined, resulting of 145 meV and 35 meV, respectively. The thermal stability of the electrical parameters has been demonstrated upon a long-term (up to ~100 hours) cycling in the temperature range 200-400°C.
Authors: Patrick Fiorenza, Filippo Giannazzo, Alessia Frazzetto, Alfio Guarnera, Mario Saggio, Fabrizio Roccaforte
Abstract: This paper reports on the conduction mechanisms through the gate oxide and trapping effects at SiO2/4H-SiC interfaces in MOS-based devices subjected to post deposition annealing in N2O. The phenomena were studied by temperature dependent current–voltage measurements. The analysis of both n and p-MOS capacitors and of n-channel MOSFETs operating in the “gate-controlled-diode” configuration revealed an anomalous hole conduction behaviour through the SiO2/4H-SiC interface, with the onset of current conduction moving towards more negative values during subsequent voltage sweeps. The observed gate current instabilities upon subsequent voltage sweeps were deeply investigated by temperature dependent cyclic gate current measurements. The results were explained by the charge-discharge mechanism of hole traps in the oxide.
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