Papers by Author: Hiroshi Tsuge

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Authors: Takashi Aigo, Wataru Ito, Hiroshi Tsuge, Hirokatsu Yashiro, Masakazu Katsuno, Tatsuo Fujimoto, Wataru Ohashi
Abstract: 4H-SiC epitaxial growth on 2˚ off-axis substrates using trichlorosilane (TCS) is presented. Good surface morphology was obtained for epilayers with C/Si ratios of 0.6 and 0.8 at a growth temperature of 1600°C. The triangle defect density was reduced to a level below 5 cm-2 at 1600°C and below 1 cm-2 at 1625°C for a C/Si ratio of 0.8. Photoluminescence (PL) measurements were carried out with band-pass filters of 420 nm, 460 nm, and 480 nm to detect stacking faults. A stacking fault density of below 5 cm-2 was achieved at 1600°C and 1625°C with a C/Si ratio of 0.8. The optimal conditions for TCS growth were a C/Si ratio of 0.8 and a growth temperature of 1600°C. The evaluation of stacking faults and etch pit density indicated that the use of 2˚ off-axis substrates and TCS is effective for reducing basal plane dislocations. Comparing these results to those using silane (SiH4) with HCl added, it was demonstrated that TCS is much more suitable for obtaining high-quality epilayers on 2º off-axis substrates.
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Authors: Takashi Aigo, M. Sawamura, Tatsuo Fujimoto, Masakazu Katsuno, Hirokatsu Yashiro, Hiroshi Tsuge, Masashi Nakabayashi, Taizo Hoshino, Noboru Ohtani
Abstract: 4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.
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Authors: Tatsuo Fujimoto, Hiroshi Tsuge, Masakazu Katsuno, Shinya Sato, Hirokatsu Yashiro, Hosei Hirano, Takayuki Yano
Abstract: A possible mechanism of hexagonal void movement during Physical vapor transport (PVT)-growth is proposed in terms of quasi-equilibrium phase transition process based upon the Si-C binary phase diagram. The hexagonal void movement can be realized when two different reactions occurs simultaneously: (1) SiC(s) solidification and (2) decomposition without graphitization. Further, the kinetic instability of the void movement observed is also discussed, and found to be explainable if the effect of the temperature gradient existing in the crystal grown in conventional PVT-process is included.
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Authors: Masakazu Katsuno, Tatsuo Fujimoto, Hirokatsu Yashiro, Hiroshi Tsuge, Shinya Sato, Hosei Hirano, Takayuki Yano, Wataru Ohashi
Abstract: Structures and propagating behaviors of threading dislocations (TDs) in PVT-grown 4H-SiC single crystals were both investigated using Synchrotron monochromatic X-ray topography. Comparative studies by examining images obtained for the crystals with different diffraction geometries of (0004) and (11-20) of 4H-SiC revealed that a large amount of TDs are likely to be mixed in character, i.e., dislocations with Burgers vector components of both <0004> and <11-20>. Closer observations of topography images has revealed that, although TDs lie largely along the c-axis direction, some of the TDs show quite a complex propagating behavior: not extending in a straight line but meandering along the growth direction.
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Authors: Hirokatsu Yashiro, Tatsuo Fujimoto, Noboru Ohtani, Taizo Hoshino, Masakazu Katsuno, Takashi Aigo, Hiroshi Tsuge, Masashi Nakabayashi, Hosei Hirano, Kohei Tatsumi
Abstract: The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.
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Authors: Takashi Aigo, Wataru Ito, Hiroshi Tsuge, Hirokatsu Yashiro, Masakazu Katsuno, Tatsuo Fujimoto, Takayuki Yano
Abstract: In this paper, we present the formation of extended epitaxial defects, such as carrot defects, from threading screw dislocations (TSDs) with a morphological feature at the surface of the substrates. It was confirmed using highly sensitive surface observation, atomic force microscopy (AFM) and KOH etching that the surface roughness around a TSD was observed as the morphological feature and TSDs with such a morphological feature formed extended epitaxial defects with high frequency of appearance compared to usual TSDs without any features. The density of TSDs with such morphological feature depended on the polishing methods. Furthermore, we observed that the formation and shapes of extended defects from TSDs with such morphological feature were affected by step-bunching at the surface of the epilayers.
629
Authors: Tatsuo Fujimoto, Noboru Ohtani, Shinya Sato, Masakazu Katsuno, Hiroshi Tsuge, Wataru Ohashi
Abstract: Sublimation-recrystallization processes occurring during PVT are investigated from the viewpoint of quasi-equilibrium phase transitions of SiC. In addition to the elemental reaction processes of PVT, other phenomena such as silicon droplet formation and in-situ etching are also discussed based upon the Si-C binary phase diagram, and possible mechanisms are proposed.
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Authors: Masashi Nakabayashi, Tatsuo Fujimoto, Masakazu Katsuno, Hiroshi Tsuge, Takashi Aigo, S. Satoh, Hirokatsu Yashiro, Taizo Hoshino, Hosei Hirano, Wataru Ohashi
Abstract: In-grown type stacking faults (SFs) like structures were observed in 100mm diameter 4H-SiC crystals by Photoluminescence (PL) mappings, and structural analyses using HRTEM clarified that the SF-like structures were comprised of 6H (3, 3) stacking sequences. The stacking sequences of the SF-like structures observed are different from the SFs formed in the a-face grown crystals, suggesting that it is due to 6H nucleation on {0001} plane terraces.
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Authors: Masashi Nakabayashi, Tatsuo Fujimoto, Masakazu Katsuno, Noboru Ohtani, Hiroshi Tsuge, Hirokatsu Yashiro, Takashi Aigo, Taizo Hoshino, Hosei Hirano, Kohei Tatsumi
Abstract: The theromoelastic stress in post-growth SiC crystals has been investigated in order to suppress the cracks which were frequently observed in SiC crystals with larger diameters. Optimizing the temperature distribution in growing crystals lead to reduction of tensile stress components, and thus resulting in crack-free 100mm diameter SiC crystals with micropipe (MP) densities of 0.025/cm2. The concept of process optimization we established is confirmed to be effective to the growth of large diameter SiC crystals with mechanical stability.
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Authors: Hiroshi Tsuge, Shinya Sato, Masakazu Katsuno, Tatsuo Fujimoto, Wataru Ohashi
Abstract: Large diameter 4H-SiC single crystal wafers with higher quality are required to improve the yields of devices fabricated onto the SiC wafers. For crystal growths with higher quality, it is important to prepare seed crystals with lower defect densities. In particular, the edge part of the seed has to be prepared with considerable care because the crystallinity of the enlarged part of grown crystals depends much upon the surface condition of the seed crystal during radial expansion growth. We found that growth with fewer defect and micropipe densities, specifically at the periphery of the crystal, is possible by utilizing in-situ etching process for the seed crystal surface. We have also performed intense numerical calculations of the temperature distribution around the seed surface, and discussed growth conditions which cause the in-situ etching effective to improvement of the crystallinity in enlarged crystals.
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