Papers by Author: Joseph J. Sumakeris

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Authors: Q. Jon Zhang, Charlotte Jonas, Joseph J. Sumakeris, Anant K. Agarwal, John W. Palmour
Abstract: DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).
Authors: Mrinal K. Das, Q. Jon Zhang, Robert Callanan, Craig Capell, Jack Clayton, Matthew Donofrio, Sarah K. Haney, Fatima Husna, Charlotte Jonas, Jim Richmond, Joseph J. Sumakeris
Abstract: For the first time, high power 4H-SiC n-IGBTs have been demonstrated with 13 kV blocking and a low Rdiff,on of 22 mWcm2 which surpasses the 4H-SiC material limit for unipolar devices. Normally-off operation and >10 kV blocking is maintained up to 200oC base plate temperature. The on-state resistance has a slight positive temperature coefficient which makes the n-IGBT attractive for parallel configurations. MOS characterization reveals a low net positive fixed charge density in the oxide and a low interface trap density near the conduction band which produces a 3 V threshold and a peak channel mobility of 18 cm2/Vs in the lateral MOSFET test structure. Finally, encouraging device yields of 64% in the on-state and 27% in the blocking indicate that the 4H-SiC n-IGBT may eventually become a viable power device technology.
Authors: Joseph J. Sumakeris, Mrinal K. Das, H. McD. Hobgood, Stephan G. Müller, Michael J. Paisley, Seo Young Ha, Marek Skowronski, John W. Palmour, Calvin H. Carter Jr.
Authors: Adrian R. Powell, Joseph J. Sumakeris, Yuri Khlebnikov, Michael J. Paisley, R.T. Leonard, Eugene Deyneka, Sumit Gangwal, Jyothi Ambati, V. Tsevtkov, Jeff Seaman, Andy McClure, Chris Horton, Olek Kramarenko, Varad Sakhalkar, M. O’Loughlin, Albert A. Burk, J.Q. Guo, Michael Dudley, Elif Balkas
Abstract: The growth of large diameter silicon carbide (SiC) crystals produced by the physical vapor transport (PVT) method is outlined. Methods to increase the crystal diameters, and to turn these large diameter crystals into substrates that are ready for the epitaxial growth of SiC or other non homogeneous epitaxial layers are discussed. We review the present status of 150 mm and 200 mm substrate quality at Cree, Inc. in terms of crystallinity, dislocation density as well as the final substrate surface quality.
Authors: Anant K. Agarwal, Albert A. Burk, Robert Callanan, Craig Capell, Mrinal K. Das, Sarah K. Haney, Brett A. Hull, Charlotte Jonas, Michael J. O'Loughlin, Michael O`Neil, John W. Palmour, Adrian R. Powell, Jim Richmond, Sei Hyung Ryu, Robert E. Stahlbush, Joseph J. Sumakeris, Q. Jon Zhang
Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.
Authors: Sung Wook Huh, Joseph J. Sumakeris, A.Y. Polyakov, Marek Skowronski, Paul B. Klein, B.V. Shanabrook, Michael J. O'Loughlin
Abstract: Carrier lifetimes and the dominant electron and hole traps were investigated in a set of thick (9-104mm) undoped 4H-SiC epitaxial layers grown by CVD homoepitaxy. Deep trap spectra were measured by deep level transient spectroscopy (DLTS) with electrical or optical injection, while lifetimes were measured by room temperature time-resolved photoluminescence (PL). The main electron traps detected in all samples were due to Ti, Z1/Z2 centers, and EH6/EH7 centers. Two boron-related hole traps were observed with activation energies of 0.3 eV (boron acceptors) and 0.6 eV (boron-related D centers). The concentration of electron traps decreased with increasing layer thickness and increased toward the edge of the wafers. PL lifetimes were in the 400 ns-1800 ns range with varying injection and generally correlated with changes in the density of Z1/Z2 and to a lesser extent the EH6/EH7 electron traps. However, the results of DLTS measurements on p-i-n diode structures suggest that the capture of injected holes is much more efficient for the Z1/Z2 traps compared to the EH6/EH7 centers making the Z1/Z2 more probable candidates for the role of lifetime killers. A good fit of the thickness dependence of the measured lifetimes to the usual analytical form was obtained assuming that Z1/Z2 is the dominant hole recombination center and that the surface recombination velocity was 2500 cm/sec.
Authors: Elif Berkman, R.T. Leonard, Michael J. Paisley, Y. Khlebnikov, Michael J. O'Loughlin, Albert A. Burk, Adrian R. Powell, D.P. Malta, E. Deyneka, M.F. Brady, I. Khlebnikov, Valeri F. Tsvetkov, H.McD. Hobgood, Joseph J. Sumakeris, C. Basceri, Vijay Balakrishna, Calvin H. Carter Jr., C. Balkas
Abstract: Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.
Authors: Joseph J. Sumakeris, Brett A. Hull, Michael J. O'Loughlin, Marek Skowronski, Vijay Balakrishna
Abstract: We detail a comprehensive approach to preparing epiwafers for bipolar SiC power devices which entails etching the substrate, growing a semi-sacrificial basal plane dislocation (BPD) conversion epilayer, polishing away a portion of that conversion epilayer to recover a smooth surface and then growing the device epilayers following specific methods to prevent the reintroduction of BPDs. With our best processing, we achieve a BPD density of < 10 cm-2 and an extended defect density of < 1.5 cm-2. Specifics of low BPD processing and particular concerns and metrics will be discussed in regard to process optimization and simplification.
Authors: Joseph J. Sumakeris, Mrinal K. Das, Seo Young Ha, Edward Hurt, Kenneth G. Irvine, Michael J. Paisley, Michael J. O'Loughlin, John W. Palmour, Marek Skowronski, H. McD. Hobgood, Calvin H. Carter Jr.
Abstract: We present a survey of the most important factors relating to an epitaxial SiC growth process that is suitable for bipolar power devices. During the last several years, we have advanced our hot-wall SiC epitaxial growth technology to the point that we can support the transition of bipolar power devices from demonstrations to applications. Two major concerns in developing a suitable epitaxial technology are epilayer uniformity and extended defect density. Our state-of-theart capability permits the realization of 1-cm2 area devices with exceptional yields. Another major concern is the stability of bipolar devices during forward conduction. We have developed proprietary substrate and epilayer preparation technologies that have essentially eliminated Vf drift as a significant barrier to the exploitation of SiC based bipolar devices.
Authors: Brett A. Hull, Joseph J. Sumakeris, Michael J. O'Loughlin, Q. Jon Zhang, Jim Richmond, Adrian R. Powell, Michael J. Paisley, Valeri F. Tsvetkov, A. Hefner, Angel Rivera
Abstract: DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.
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