Papers by Author: Masato Noborio

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Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.
Authors: Michael Grieb, Masato Noborio, Dethard Peters, Anton J. Bauer, Peter Friedrichs, Tsunenobu Kimoto, Heiner Ryssel
Abstract: The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.
Authors: Tsunenobu Kimoto, Gan Feng, Toru Hiyoshi, Koutarou Kawahara, Masato Noborio, Jun Suda
Abstract: Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.
Authors: Masato Noborio, Michael Grieb, Anton J. Bauer, Dethard Peters, Peter Friedrichs, Jun Suda, Tsunenobu Kimoto
Abstract: In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.
Authors: Michael Grieb, Masato Noborio, Dethard Peters, Anton J. Bauer, Peter Friedrichs, Tsunenobu Kimoto, Heiner Ryssel
Abstract: In this work, the electrical characteristics and the reliability of 80nm thick deposited oxides annealed in NO and N2O on the 4H-SiC Si-face for gate oxide application in MOS devices is analyzed by C-V, I-V measurements and by constant current stress. Compared to thermally grown oxides, the deposited oxides annealed in N2O or NO showed improved electrical properties. Dit-values lower than 1011cm-2eV-1 have been achieved for the NO sample. The intrinsic QBD-values of deposited and annealed oxides are one order of magnitudes higher than the highest values reported for thermally grown oxides. Also MOSFETS were fabricated with a channel mobility of 20.05 cm2/Vs for the NO annealed deposited oxide. Furthermore annealing in NO is preferred to annealing in N2O regarding µFE- and QBD-values.
Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.
Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.
Authors: Sergey A. Reshanov, Svetlana Beljakowa, Thomas Frank, Bernd Zippelius, Michael Krieger, Gerhard Pensl, Masato Noborio, Tsunenobu Kimoto
Abstract: Conventional MOSFETs and Hall-bar MOSFETs are fabricated side by side by over-oxidation of N-implanted or N-/Al-coimplanted 4H-SiC layers. It is demonstrated that the N-/Al-coimplanted MOSFETs possess a positive threshold voltage at room temperature and reach high values of the channel mobility. The effective electron mobility and Hall mobility in Hall-bar MOSFETs are 31 cm2/Vs and 150 cm2/Vs, respectively, indicating a high density of interface traps in spite of the excellent high mobility values.
Authors: Tsunenobu Kimoto, H. Kawano, Masato Noborio, Jun Suda, Hiroyuki Matsunami
Abstract: Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.
Authors: Yuichiro Nanen, Hironori Yoshioka, Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: 4H-SiC (0001) MOSFETs with a three-dimensional gate structure, which has a top channel on the (0001) face and side-wall channels on the {11-20} face have been fabricated. The three-dimensional gate structures with a 1-5 m width and 0.8 m height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300°C. The fabricated MOSFETs have exhibited superior characteristics: ION / IOFF, the subthreshold swing and VTH are 1010, 250 mV/decade and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1 m-wide MOSFET is ten times higher than that of a conventional planar MOSFET.
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