Papers by Author: Patrick Berwian

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Authors: Birgit Kallinger, Bernd Thomas, Patrick Berwian, Jochen Friedrich, Gerd Trachta, Arnd Dietrich Weber
Abstract: Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.
Authors: Birgit Kallinger, Bernd Thomas, Sebastian Polster, Patrick Berwian, Jochen Friedrich
Abstract: Basal Plane Dislocations (BPDs) in SiC are thought to cause degradation of bipolar diodes with blocking voltages > 2kV by triggering the formation and expansion of stacking faults during device operation. Hence, low N doped, thick epitaxial layers without BPDs are urgently needed for the realization of long-term stable SiC bipolar diodes. Such epilayers can be achieved if the conversion of the BPD into another harmless dislocation type is supported by proper epitaxial growth parameters and use of vicinal (off-cut) substrates. In this work, the influence of the substrate’s off-cut angle and of the epilayer thickness on BPD density and surface morphology were investigated. The BPD densities of epilayers grown on 2° and 4° off-cut substrates were very low compared to growth on 8° off-axis substrates. X-Ray Topography has proved that all the Threading Dislocations (TD) propagate from the substrate to the epilayer and that BPDs in the substrate convert to Threading Edge Dislocations (TED) in the epilayer, i.e. the dislocation density (DD) of the substrate determines the epilayer’s DD. The conversion of BPDs is supported by the presence of bunched steps as for growth of thick layers on 2° and 4° off-cut substrates.
Authors: Birgit Kallinger, Christian Ehlers, Patrick Berwian, Mathias Rommel, Jochen Friedrich
Abstract: The addition of hydrogen chloride (HCl) to our conventional CVD process allows for high growth rates up to 50 μm/h while maintaining the step-flow growth mode. Such epilayers exhibit quite low total concentrations of point defects less than 2 x 1013 cm-3. But, the HCl addition shows an ambivalent influence on the concentration of the lifetime killer defect Z1/2. For low growth rates, the Z1/2 concentration slightly decreases with increasing HCl addition. For higher growth rates, the Z1/2 concentration increases with increasing HCl addition.
Authors: Patrick Berwian, Daniel Kaminzky, Katharina Rosshirt, Birgit Kallinger, Jochen Friedrich, Steffen Oppel, Adrian Schneider, Michael Schütz
Abstract: A new tool for characterizing extended defects in Silicon Carbide (SiC) based on photoluminescence imaging is presented. In contrast to other techniques like Defect Selective Etching (DSE) or X-ray topography this technique is both fast and non-destructive. It is shown that several defect types, especially those relevant for the performance of electronic devices on SiC (i.e. Stacking Faults and Basal Plane Dislocations) can be investigated. The tool is therefore usable in research and development for a quick feedback on process related defect generation as well as in a production environment for quality control.
Authors: Jürgen Erlekampf, Daniel Kaminzky, Katharina Rosshirt, Birgit Kallinger, Mathias Rommel, Patrick Berwian, Jochen Friedrich, Lothar Frey
Abstract: The development of bipolar 4H-SiC devices for high blocking voltages requires the growth of high carrier lifetime epitaxial layers with low Z1/2 concentrations. This paper shows a comprehensive investigation of the influence of epitaxial growth parameters (C/Si ratio and growth temperature) on Z1/2 concentration and minority carrier lifetime. On the basis of a discovered exponential correlation of Z1/2 with the C/Si ratio and growth temperature, a competitive low Z1/2 concentration of 1.9∙1012 cm-3 could be achieved by lowering the growth temperature and switching to higher C/Si ratio. Thermodynamic considerations by an Arrhenius approach reveal a dependency of the formation enthalpy of Z1/2 on the thermal process and process conditions of the epitaxial growth. Furthermore, the correlation between Z1/2 and the effective minority carrier lifetime confirms the occurrence of a necessary second recombination mechanism beside the common recombination at deep levels by Shockley-Read-Hall for low Z1/2 concentration.
Authors: Birgit Kallinger, Patrick Berwian, Jochen Friedrich, Mathias Rommel, Maral Azizi, Christian Hecht, Peter Friedrichs
Abstract: 4H-SiC homoepitaxial layers with different thicknesses from 12.5 µm up to 50 µm were investigated by microwave-detected photoconductivity decay (µ-PCD), deep level transient spectroscopy (DLTS) and defect selective etching (DSE) to shed light on the influence of the epilayer thickness and structural defects on the effective minority carrier lifetime. It is shown that the effective lifetime, resulting directly from the µ-PCD measurement, is significantly influenced by the surface recombination lifetime. Therefore, an adequate correction of the measured data is necessary to determine the bulk lifetime. The bulk lifetime of these epilayers is in the order of several microseconds. Furthermore, areas with high dislocation density are correlated to areas with locally reduced effective lifetime.
Authors: Daniel Kaminzky, Birgit Kallinger, Patrick Berwian, Mathias Rommel, Jochen Friedrich
Abstract: We present an extended model for the simulation of the effective minority carrier lifetime in 4H-SiC epiwafers after optical excitation. This multilayer model uses measured values (such as doping profile, point defect concentration and capture cross sections, epilayer thickness) as input parameters. The bulk lifetime and the diffusion constant are calculated from the actual time dependent excess carrier profiles, resulting in more realistic transients having different decay regimes than in other models. This enables a better understanding of optical lifetime measurements.
Authors: Birgit Kallinger, Daniel Kaminzky, Patrick Berwian, Jochen Friedrich, Steffen Oppel
Abstract: Electrical testing with regard to bipolar degradation of high voltage SiC devices cannot be done on wafer level, but only expensively after module assembly. We show that 4H-SiC material can be optically stressed by applying high UV laser intensities, i.e. bipolar degradation as in electrical stress tests can be provoked on wafer level. Therefore, optical stressing can be used for control measurements and reliability testing. Different injection (=stress) levels have been used similar to the typical doping level of the base material and similar to the established electrical stress test. The analysis of degradation is done by photoluminescence imaging which is a well-established technique for revealing structural defects such as Basal Plane Dislocations (BPDs) and stacking faults (SFs) in 4H-SiC epiwafers and partially processed devices.
Authors: Birgit Kallinger, Patrick Berwian, Jochen Friedrich, Christian Hecht, Dethard Peters, Peter Friedrichs, Bernd Thomas
Abstract: 4H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.
Authors: Christoph Friedrich Bayer, Eberhard Bär, Birgit Kallinger, Patrick Berwian
Abstract: This work shows thermal simulations of a package of 48/96 high-voltage (6.5 kV/1 kA) PiN diodes. A temperature dependent heat generation for a forward voltage of 3.6 V with a realistic heat generating volume in the diode of (2.7x2.7x0.01) mm3 was used. The thermal coupling of two diodes was determined to be less than 1 % for a distance between the diodes of 10 mm. The temperature distribution for the entire module has been studied for two different ceramic insulating materials, AlN and Al2O3, as well as for two numbers of diodes, 48 and 96. This led to a maximum temperature of 106 °C/118 °C (AlN, 48/96 diodes) and 123 °C/144 °C (Al2O3, 48/96 diodes). Assuming a constant applied voltage, a variance of ±0.5 V of the characteristic curve (forward voltage versus current) due to variations in the production process was considered fork single diodes. For a shift of +0.5 V for a single diode, the maximum temperature difference to the cooler temperature becomes approximately twice the original difference. Additionally, the operation under constant current (7.1 A, 10.2 A, 14.2 A) was studied including single diode failure. For single diode failure, the resulting change of the maximum temperature would be less than 3 %.
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