Papers by Author: Satoru Nogami

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Authors: Norihito Yabuki, Satoshi Torimi, Satoru Nogami, Makoto Kitabatake, Tadaaki Kaneko
Abstract: We propose the Si-vapor ambient anneal as a cap-free activation annealing (A/A) method for Silicon Carbide (SiC) using Tantalum Carbide / Tantalum composite materials (TaC/Ta). This method prevents the roughening of SiC surface by controlling the process function without conventional Carbon (C)-cap [1,2]. In this report, we evaluated the warping behavior of SiC wafer to confirm the effect of ion implantation (I/I) temperature (TI/I) and epi-ready treatment using Si-vapor ambient anneal. Wafer warp suppressing effect of high temperature I/I was confirmed and large wafer warpage occurred due to thinning of the wafer thickness. Furthermore we also observed the simultaneous improvement of the sharp edge shape and sidewall roughness of the trench under the appropriate conditions of the Si-vapor ambient anneal. It is possible to shape the round shape of the trench edge and to improve the roughness of trench sidewall by Si-vapor ambient anneal simultaneously with activation annealing process.
Authors: Satoshi Torimi, Norihito Yabuki, Takuya Sakaguchi, Masato Shinohara, Yoji Teramoto, Satoru Nogami, Makoto Kitabatake, Junji Senzaki
Abstract: We investigate electrical characteristics of the pn-diode fabricated using the epitaxial films on the surface damage-free 4H-SiC (0001) Si-face 4° off-cut wafers prepared by the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. The forward and reverse current-voltage (I-V) characteristics of pn-diodes correlated to the epitaxial defects are discussed. The device at the defect-free area includes 11 % failed diodes on the chemo-mechanical polishing (CMP) wafer while 0 % on the Si-VE wafer. The latent scratches and mechanical damages, which increase the forward and reverse leakage current of the pn-diodes, are completely removed by the Si-VE. The Si-VE exposes the carbon inclusions in the wafer to form the small bump which ends up with the larger bump defect on the epitaxial surface. These bumps cause leak current of the forward characteristics while all of the reverse characteristics are normal. The epitaxial film on the Si-VE surface has less density of the basal plane dislocations (BPDs) than the conventional CMP. It is hard to recognize the safe device on the CMP wafer without additional reliability test. The Si-VE wafer shows the apparent breakdown voltage fail on every small-number diode including BPDs under the simple test. It is considered that the Si-VE is possible to reduce ambiguity of the device characteristics under the relationship with the defects in comparison with the CMP.
Authors: Norihito Yabuki, Satoshi Torimi, Satoru Nogami, Makoto Kitabatake, Tadaaki Kaneko
Abstract: We propose the thermal chemical etching process for Silicon Carbide (SiC) under the Si-vapor ambient using Tantalum Carbide / metal Tantalum composite materials (TaC/Ta). In this process, the high-rate “Si-vapor etching” method is applied to the removal of the surface damage and the formation of epi-ready surface. Over 10μm of “Si-vapor etching” provides smooth surface without latent scratch and low stacking faults density as same as on the CMP after epitaxial growth, which are observed by confocal microscope with differential interference contrast (C-DIC) microscope and Photo-Luminescence (PL) imaging measurement. Furthermore, the low-rate Si-vapor etching method, “Si-vapor ambient annealing” is applied to post-implantation activation annealing process without conventional C-cap. “Si-vapor ambient annealing” provides lower sheet resistance and smoother surface than the C-cap annealing after very high temperature annealing up to 2000 °C.
Authors: Satoshi Torimi, Satoru Nogami, Tadaaki Kaneko
Abstract: As a new post-implantation activation annealing of Silicon Carbide (SiC), we propose the Si-vapor ambient anneal using Tantalum Carbide / metal Tantalum composite materials (TaC/Ta). In this technique, semi-closed TaC/Ta container which can supply Si-vapor ambient is used, and Si vapor compensates thermal desorption Si atoms from the SiC surface above 1500°C and can maintain the original surface morphology by controlling a process temperature and Ar back pressure. Therefore the Si-vapor ambient anneal is able to simplify the process of conventional activation anneal methods using refractory cap-layers for protecting SiC surface from thermal damage of Si-atom desorption. Experiments were performed under Ar 1.3kPa at 1600/1700°C for 5min optimized conditions in a 6inch TaC/Ta container, and the Al+ ion-implanted 4H-SiC properties after annealing were characterized by atomic force microscopy (AFM), Rutherford Back-scattering Spectrometry (RBS) channeling method, and four-point probe method. According to evaluation, there was no roughening of SiC surface from AFM topographic images and recovery of crystallinity at the ion-implanted layer was equivalent to by the conventional cap-layer method from RBS channeling measurement. The sheet resistance of 12kΩ/ at 1700°C equal to the typical Al+ ion implanted p-type SiC is confirmed by four-point probe method.
Authors: Satoshi Torimi, Koji Ashida, Norihito Yabuki, Masato Shinohara, Takuya Sakaguchi, Yoji Teramoto, Satoru Nogami, Makoto Kitabatake, Tadaaki Kaneko
Abstract: As a new thinning and surface planarizing process of Silicon Carbide (SiC) wafer, we propose the completely thermal-chemical etching process; Si-vapor etching (Si-VE) technology. In this work, the effects of mechanical strength and surface step-terrace structure by Si-VE are investigated on the 4° off-axis 4H-SiC (0001) Si-face substrates. The indentation hardness of Si-VE surface is superior to the conventional chemo-mechanical polishing (CMP) surface even after epitaxial growth. The transverse strength of thinned Si-VE substrate is also superior to the conventional mechanically ground substrate. The surface step-terrace structures are observed by the low energy electron channeling contrast (LE-ECC) imaging technique. The latent scratch causes bunched step lines (BSLs) with various inhomogeneous step morphologies only on the CMP surface.
Authors: Koji Ashida, Daichi Dojima, Satoshi Torimi, Norihito Yabuki, Yusuke Sudo, Takuya Sakaguchi, Satoru Nogami, Makoto Kitabatake, Tadaaki Kaneko
Abstract: Mechanism of surface roughening caused by the polishing induced subsurface damage on 4o off-cut 4H-SiC (0001) substrate during thermal etching, CVD epitaxial growth, and the subsequent high temperature annealing was investigated in the wide temperature range of 1000-1800°C. Different from the previous study based on a macroscopic characterization by optical microscopy, microscopic characterization based on a scanning electron microscopy (SEM) was employed in this study. By utilizing the SEM operated under various conditions, disordered step arrangements as well as stacking faults and dislocations were imaged. The obtained results revealed that the SFs cause the fluctuation in the step kinetics, resulting in the step bunching formation during the thermal process.
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