Papers by Author: T. Paul Chow

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Authors: Sumi Krishnaswami, Anant K. Agarwal, Craig Capell, Jim Richmond, Sei Hyung Ryu, John W. Palmour, S. Balachandran, T. Paul Chow, Stephen Baynes, Bruce Geil, Kenneth A. Jones, Charles Scozzie
Abstract: 1000 V Bipolar Junction Transistor and integrated Darlington pairs with high current gain have been developed in 4H-SiC. The 3.38 mm x 3.38 mm BJT devices with an active area of 3 mm x 3 mm showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm2, at a forward voltage drop of 2 V. A common-emitter current gain of 40 was measured on these devices. A specific on-resistance of 6.0 mW-cm2 was observed at room temperature. The onresistance increases at higher temperatures, while the current gain decreases to 30 at 275°C. In addition, an integrated Darlington pair with an active area of 3 mm x 3 mm showed a collector current of 30 A at a forward drop of 4 V at room temperature. A current gain of 2400 was measured on these devices. A BVCEO of 1000 V was measured on both of these devices.
Authors: Lin Zhu, Mayura Shanbhag, T. Paul Chow, Kenneth A. Jones, Matthew H. Ervin, Pankaj B. Shah, Michael A. Derenge, R.D. Vispute, T. Venkatesan, Anant K. Agarwal
Authors: Harsh Naik, T. Paul Chow
Abstract: This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.
Authors: Sauvik Chowdhury, Collin W. Hitchcock, Rajendra Dahal, Ishwara B. Bhat, T. Paul Chow
Abstract: We experimentally demonstrate 4H-SiC n-channel, DMOS Insulated Gate Bipolar Transistors (IGBTs) on 180 µm thick lightly doped free-standing n- substrates with an ion-implanted collector region, and metal-oxide-semiconductor (MOS) gate on (0001) and (000-1) surfaces. The IGBTs show an on-state current of 20A/cm2 at a power dissipation of 300W/cm2. Threshold voltage of 7.5V and 10.5V was obtained on Si-face and C-face respectively. Both IGBTs show a small positive temperature coefficient of the forward voltage drop, which is useful for easy parallelization of devices.
Authors: W. Wang, S. Banerjee, T. Paul Chow, Ronald J. Gutmann
Authors: Y. Wang, Peter A. Losee, S. Balachandran, I. Bhat, T. Paul Chow, Y. Wang, B.J. Skromme, J.K. Kim, E.F. Schubert
Abstract: Low resistance p-layers are achieved in this paper using a graphite cap to protect SiC surface from out-diffusion of Si during high temperature post-implantation annealing, which is carried out to maximize the activation of Al dopant in 4H-SiC. With a graphite layer converted from photoresist, as high as 1700 and 1800oC post-implantation annealing is able to be used. Low RMS roughness of surface after high temperature annealing shows the effectiveness of the graphite cap. Small sheet resistance and resistivity are also achieved from the high temperature annealing. At room temperature, sheet resistances of 9.8 and 1.3 k/□, and the corresponding resistivities of 235 and 31 m-cm are obtained from 1700 and 1800oC annealed samples, respectively. The Al ionization energy extracted from Arrhenius plot is also close to the typical reported values. Therefore, it can be concluded that, using graphite cap could help to activate the Al dopant effectively during high temperature annealing.
Authors: Jeffery B. Fedison, Z. Li, V. Khemka, Nudjarin Ramungul, T. Paul Chow, Mario Ghezzo, James W. Kretchmer, Ahmed Elasser
Authors: W. Huang, T. Khan, T. Paul Chow
Abstract: Both n-type and p-type GaN MOS capacitors with plasma-enhanced CVD-SiO2 as the gate oxide were characterized using both capacitance and conductance techniques. From a n type MOS capacitor, an interface state density of 3.8×1010/cm2-eV was estimated at 0.19eV near the conduction band and decreases deeper into the bandgap while from a p type MOS capacitor, an interface state density of 1.4×1011/cm2-eV 0.61eV above the valence band was estimated and decreases deeper into the bandgap. Unlike the symmetric interface state density distribution in Si, an asymmetric interface state density distribution with lower density near the conduction band and higher density near the valence band has been determined.
Authors: Nudjarin Ramungul, Yan Jun Zheng, R. Patel, V. Khemka, T. Paul Chow
Authors: V. Khemka, K. Chatty, T. Paul Chow, Ronald J. Gutmann
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