Papers by Author: Tatsuo Fujimoto

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Authors: Tatsuo Fujimoto, Masakazu Katsuno, Noboru Ohtani, Takashi Aigo, Hirokatsu Yashiro
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Authors: Takashi Aigo, Wataru Ito, Hiroshi Tsuge, Hirokatsu Yashiro, Masakazu Katsuno, Tatsuo Fujimoto, Wataru Ohashi
Abstract: 4H-SiC epitaxial growth on 2˚ off-axis substrates using trichlorosilane (TCS) is presented. Good surface morphology was obtained for epilayers with C/Si ratios of 0.6 and 0.8 at a growth temperature of 1600°C. The triangle defect density was reduced to a level below 5 cm-2 at 1600°C and below 1 cm-2 at 1625°C for a C/Si ratio of 0.8. Photoluminescence (PL) measurements were carried out with band-pass filters of 420 nm, 460 nm, and 480 nm to detect stacking faults. A stacking fault density of below 5 cm-2 was achieved at 1600°C and 1625°C with a C/Si ratio of 0.8. The optimal conditions for TCS growth were a C/Si ratio of 0.8 and a growth temperature of 1600°C. The evaluation of stacking faults and etch pit density indicated that the use of 2˚ off-axis substrates and TCS is effective for reducing basal plane dislocations. Comparing these results to those using silane (SiH4) with HCl added, it was demonstrated that TCS is much more suitable for obtaining high-quality epilayers on 2º off-axis substrates.
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Authors: Takashi Aigo, M. Sawamura, Tatsuo Fujimoto, Masakazu Katsuno, Hirokatsu Yashiro, Hiroshi Tsuge, Masashi Nakabayashi, Taizo Hoshino, Noboru Ohtani
Abstract: 4H-SiC epitaxial layers on Carbon-face (C-face) substrates were grown by a low-pressure hot-wall type chemical vapor deposition system. The C-face substrates were prepared by fine mechanical polishing using diamond abrasives with the grit size of 0.25 %m and in-situ HCl etching at 1400°C, which produced surface roughness of 0.27 nm. The use of the smooth substrates made it possible to decrease the substrate temperature and specular surface morphologies were realized at C/Si ratios of 1.5 or less both for a substrate temperature of 1550°C and for that of 1500°C. Surface roughness of 0.26 nm and the residual donor concentration of 6.7×1014 cm-3 were obtained for a C-face epitaxial layer grown at a C/Si ratio of 1.5 and at a substrate temperature of 1550°C. Schottky barrier diodes were fabricated on a non-doped C-face epitaxial layer grown at 1500°C and it was verified that a high quality metal-semiconductor interface was formed on the epitaxial layer.
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Authors: Tatsuo Fujimoto, Hiroshi Tsuge, Masakazu Katsuno, Shinya Sato, Hirokatsu Yashiro, Hosei Hirano, Takayuki Yano
Abstract: A possible mechanism of hexagonal void movement during Physical vapor transport (PVT)-growth is proposed in terms of quasi-equilibrium phase transition process based upon the Si-C binary phase diagram. The hexagonal void movement can be realized when two different reactions occurs simultaneously: (1) SiC(s) solidification and (2) decomposition without graphitization. Further, the kinetic instability of the void movement observed is also discussed, and found to be explainable if the effect of the temperature gradient existing in the crystal grown in conventional PVT-process is included.
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Authors: Kiyo Okawa, Yuina Mannen, Kentaro Shioura, Noboru Ohtani, Masakazu Katsuno, Hiroshi Tsuge, Shinya Sato, Tatsuo Fujimoto
Abstract: The annealing behavior of electrical resistivities perpendicular and parallel to the basal plane of heavily nitrogen-doped 4H-SiC crystals was investigated. The temperature dependencies of the resistivities exhibited characteristic behaviors after multiple rounds of high-temperature annealing (1100°C, 30 min). High-temperature annealing induced stacking fault formation to various extents in heavily nitrogen-doped 4H-SiC crystals. Based on these results, we discuss the cause and mechanism of the observed annealing-induced changes in electrical resistivities of the crystals.
293
Authors: Yoshihito Teramoto, Yuki Tabuchi, Daisuke Fukunaga, Kohei Ohtomo, Noboru Ohtani, Masakazu Katsuno, Tatsuo Fujimoto, Shinya Sato, Hiroshi Tsuge, Takayuki Yano
Abstract: Basal plane bending and stress distribution in physical vapor transport-grown n-type 4H-SiC crystals were investigated. High resolution X-ray diffraction measurements were performed on commercially available 3-inch-diameter 4H-SiC substrates and along the growth front surface of as-grown 1-inch-diameter 4H-SiC boules. The measurements revealed that structural parameters such as the c-lattice constant, basal plane tilting, and FWHM showed characteristic variations across the substrates and as-gown boules, indicating that the crystals had a non-uniform distribution of dislocations comprising domain structures. Residual stress measured by micro Raman spectroscopy showed a similar behavior, which was an oscillatory spatial variation. On the basis of these results, defect structures in the crystals are elucidated.
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Authors: Takashi Aigo, Wataru Itoh, Tatsuo Fujimoto, Takayuki Yano
Abstract: In this paper, we present a comparison of defects in 4H-SiC epilayers grown on 4o off-axis (0001) and (000-1) substrates. It was confirmed using high sensitive surface observation and micro-Raman spectroscopy that the generation of epitaxial defects on (000-1) C-face substrates was less susceptible to substrate morphological defects such as pits than that on (0001) Si-face substrates and 'comet-like' defects on (000-1) C-faces were caused by the inclusion of 3C-SiC. Moreover, PL imaging observation showed that stacking fault densities decreased when increasing the growth temperature, and they increased when increasing the C/Si ratio, irrespective of the face polarity. The densities, however, were lower for C-faces at higher growth temperature and C/Si ratio. The present results indicated that C-faces were preferable to Si-faces to achieve smooth step-flow growth suppressing epitaxial defects and stacking faults, which were influenced by the substrate morphological defects and the fluctuation of C/Si ratio in the epitaxial growth.
143
Authors: Masakazu Katsuno, Tatsuo Fujimoto, Hirokatsu Yashiro, Hiroshi Tsuge, Shinya Sato, Hosei Hirano, Takayuki Yano, Wataru Ohashi
Abstract: Structures and propagating behaviors of threading dislocations (TDs) in PVT-grown 4H-SiC single crystals were both investigated using Synchrotron monochromatic X-ray topography. Comparative studies by examining images obtained for the crystals with different diffraction geometries of (0004) and (11-20) of 4H-SiC revealed that a large amount of TDs are likely to be mixed in character, i.e., dislocations with Burgers vector components of both <0004> and <11-20>. Closer observations of topography images has revealed that, although TDs lie largely along the c-axis direction, some of the TDs show quite a complex propagating behavior: not extending in a straight line but meandering along the growth direction.
355
Authors: Toshihisa Nishioka, Tatsuo Fujimoto
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Authors: Hirokatsu Yashiro, Tatsuo Fujimoto, Noboru Ohtani, Taizo Hoshino, Masakazu Katsuno, Takashi Aigo, Hiroshi Tsuge, Masashi Nakabayashi, Hosei Hirano, Kohei Tatsumi
Abstract: The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.
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