Papers by Author: Yasunori Tanaka

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Authors: Yasunori Tanaka, Koji Yano, Mitsuo Okamoto, Akio Takatsuka, Kazuo Arai, Tsutomu Yatsuo
Abstract: We have succeeded to fabricate SiC buried gate static induction transistors (BGSITs) with the breakdown voltage VBR of 1270 V at the gate voltage VGS of –12 V and the specific on-resistance RonS of 1.21 mΩ·cm2 at VGS = 2.5 V. The turn-off behaviors of BGSITs strongly depend on the source length WS, which is the distance between the gate electrodes. The rise time tr of BGSIT for WS = 1,070 μm is 395 nsec, while that for WS = 210 μm is 70nsec. From the 3D computer simulations, we confirmed that the difference in turn-off behavior came from the time delay in potential barrier formation in channel region because of high p+ gate resistivity. The turn-off behaviors also depend on the operation temperature, especially for long WS. On the other hand, the turn-on behaviors hardly depend on the WS and temperature.
Authors: Dai Okamoto, Yasunori Tanaka, Tomonori Mizushima, Mitsuru Yoshikawa, Hiroyuki Fujisawa, Kensuke Takenaka, Shinsuke Harada, Shuji Ogata, Toshihiko Hayashi, Toru Izumi, Tetsuro Hemmi, Atsushi Tanaka, Koji Nakayama, Katsunori Asano, Kazushi Matsumoto, Naoyuki Ohse, Mina Ryo, Chiharu Ota, Kazuto Takao, Makoto Mizukami, Tomohisa Kato, Manabu Takei, Yoshiyuki Yonezawa, Kenji Fukuda, Hajime Okumura
Abstract: We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (RonAactive) of 12 mW·cm2. The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.
Authors: Hiroshi Kono, Masaru Furukawa, Keiko Ariyoshi, Takuma Suzuki, Yasunori Tanaka, Takashi Shinohe
Abstract: Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.
Authors: Akio Takatsuka, Yasunori Tanaka, Koji Yano, Norio Matsumoto, Tsutomu Yatsuo, Kazuo Arai
Abstract: 3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.
Authors: Yusuke Kobayashi, Shinsuke Harada, Hiroshi Ishimori, Shinji Takasu, Takahito Kojima, Keiko Ariyoshi, Mitsuru Sometani, Junji Senzaki, Manabu Takei, Yasunori Tanaka, Hajime Okumura
Abstract: A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843 V and the maximum Eox at breakdown voltage was estimated to be 3.2 MV/cm.
Authors: Akio Takatsuka, Yasunori Tanaka, Koji Yano, Tsutomu Yatsuo, Kazuo Arai
Abstract: In this work, we succeeded in developing high performance normally-off SiC buried gate static induction transistors (SiC-BGSITs). To achieve the normally-off characteristics, design parameters around the channel region were optimized and process conditions were improved to realize these parameters. The off-state characteristic of the SiC-BGSIT showed an avalanche breakdown voltage of VBR=980 V at a gate voltage of VG=0 V. Furthermore, the leakage current at VD=950 V is lower than 0.5 μA. These results indicate that the BGSIT has a good normally-off characteristic. At VG=2.5 V, an on-resistance of 28.0 mΩ corresponding to the specific on-resistance of 1.89 mΩ•cm2 was obtained and the current rating was calculated as 33 A at a power density of 200 W/cm2 in the on-state characteristic.
Authors: Hironori Yoshioka, Takashi Nakamura, Junji Senzaki, Atsushi Shimozato, Yasunori Tanaka, Hajime Okumura, Tsunenobu Kimoto
Abstract: We focused on the inability of the common high-low method to detect very fast interface states, and developed methods to evaluate such states (CψS method). We have investigated correlation between the interface state density (DIT) evaluated by the CψS method and MOSFET performance, and found that the DIT(CψS) was well reflected in MOSFET performance. Very fast interface states which are generated by nitridation restricted the improvement of subthreshold slope and field-effect mobility.
Authors: Masayuki Yamamoto, Yasunori Tanaka, Tsutomu Yatsuo, Koji Yano
Abstract: We investigate a cascode configuration of a normally-on SiC-Buried Gate Static Induction Transistor (SiC-BGSIT) and Si-MOSFET as an alternative switching device of the SiC-MOSFET. It is shown that the transconductance of our cascode device is much higher than that of commercial SiC-MOSFETs while the switching speed is much faster than that of normally-off SiC-BGSITs. The origin of the fast switching speed in this cascode configuration is discussed in terms of a simulated reverse transfer capacitance.
Authors: Kenji Fukuda, Shinsuke Harada, Junji Senzaki, Mitsuo Okamoto, Yasunori Tanaka, Akimasa Kinoshita, Ryouji Kosugi, Kazu Kojima, Makoto Kato, Atsushi Shimozato, Kenji Suzuki, Yusuke Hayashi, Kazuto Takao, Tomohisa Kato, Shin Ichi Nishizawa, Tsutomu Yatsuo, Hajime Okumura, Hiromichi Ohashi, Kazuo Arai
Abstract: The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm2 and excellent dynamic characteristics.
Authors: Junji Senzaki, Atsushi Shimozato, Kazutoshi Kojima, Tomohisa Kato, Yasunori Tanaka, Kenji Fukuda, Hajime Okumura
Abstract: Influences of wafer-related defect and gate oxide fabrication process on MOS characteristics with gate oxides thermally grown on 4H-SiC (0001) wafer have been investigated for a realization of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of DRY oxidation temperature and the applying of N2O and H2 POAs. In addition, it was clearly shown that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is effective technique for the improvement of SiC MOS reliability.
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