Papers by Author: Carl Mikael Zetterling

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Authors: Arash Salemi, Hossein Elahipanah, Carl Mikael Zetterling, Mikael Östling
Abstract: Implantation-free mesa etched 10+ kV 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. An area-optimized junction termination extension (O-JTE) is implemented in order to achieve a high breakdown voltage. The diodes design allows a high breakdown voltage of about 19.3 kV according to simulations by Sentaurus TCAD. No breakdown voltage is recorded up to 10 kV with a very low leakage current of 0.1 μA. The current spreading within the thick drift layer is considered and a voltage drop (VF) of 8.3 V and 11.4 V are measured at 50 A/cm2 and 100 A/cm2, respectively. The differential on-resistance (Diff. Ron) of 67.7 mΩ.cm2 and 55.7 mΩ.cm2 are measured at 50 A/cm2 and 100 A/cm2, respectively.
Authors: Hyung Seok Lee, Martin Domeij, Carl Mikael Zetterling, Reza Ghandi, Mikael Östling, Fredrik Allerstam, Einar Ö. Sveinbjörnsson
Abstract: This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage (BVCEO) of 1200 V, a maximum current gain (β) of 60 and the low on-resistance (Rsp_on)of 5.2 mΩcm2. The high gain is attributed to an improved surface passivation SiO2 layer which was grown in N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm × 1.8 mm showed a current gain of 53 in pulsed mode and a forward voltage drop of VCE=2V at IC=15 A (JC=460 A/cm2).
Authors: Hossein Elahipanah, Arash Salemi, Carl Mikael Zetterling, Mikael Östling
Abstract: A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.
Authors: Hirofumi Nagatsuma, Shin Ichiro Kuroki, Milantha de Silva, Seiji Ishikawa, Tomonori Maeda, Hiroshi Sezaki, Takamaro Kikkawa, Mikael Östling, Carl Mikael Zetterling
Abstract: 4H-SiC nMOSFETs with As-doped S/D and NbNi silicide ohmic contacts were demonstrated for radiation-hard CMOS electronics. The threshold voltage Vth was designed to be 3.0 V by TCAD simulation, and was 3.6 – 3.8 V at the fabricated devices. On / off ratio was approximately 105.
Authors: Shuoben Hou, Per Erik Hellström, Carl Mikael Zetterling, Mikael Östling
Abstract: An in-house fabricated 4H-SiC PIN diode that has both optical sensing and temperature sensing functions from room temperature (RT) to 550 °C is presented. The two sensing functions can be simply converted from one to the other by switching the bias voltage on the diode. The optical responsivity of the diode at 365 nm is 31.8 mA/W at 550 °C. The temperature sensitivity of the diode is 2.7 mV/°C at the forward current of 1 μA.
Authors: Hyung Seok Lee, Martin Domeij, Carl Mikael Zetterling, Mikael Östling
Abstract: 4H-SiC BJTs have been fabricated with varying geometrical designs. The maximum value of the current gain was about 30 at IC=85 mA, VCE=14 V and room temperature (RT) for a 20 μm emitter width structure. A collector-emitter voltage drop VCE of 2 V at a forward collector current 55 mA (JC = 128 A/cm2) was obtained and a specific on-resistance of 15.4 m2·cm2 was extracted at RT. Optimum emitter finger widths and base-contact implant distances were derived from measurement. The temperature dependent DC I-V characteristics of the BJTs have been studied resulting in 45 % reduction of the gain and 75 % increase of the on-resistance at 225 oC compared to RT. Forward-bias stress on SiC BJTs was investigated and about 20 % reduction of the initial current gain was found after 27.5 hours. Resistive switching measurements with packaged SiC BJTs were performed showing a resistive fast turn-on with a VCE fall-time of 90 ns. The results indicate that significantly faster switching can be obtained by actively controlling the base current.
Authors: Shin Ichiro Kuroki, Tatsuya Kurose, Hirofumi Nagatsuma, Seiji Ishikawa, Tomonori Maeda, Hiroshi Sezaki, Takamaro Kikkawa, Takahiro Makino, Takeshi Ohshima, Mikael Östling, Carl Mikael Zetterling
Abstract: For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.
Authors: Fanny Dahlquist, J.O. Svedberg, Carl Mikael Zetterling, Mikael Östling, Bo Breitholtz, H. Lendenmann
Authors: Erik Danielsson, Martin Domeij, Hyung Seok Lee, Carl Mikael Zetterling, Mikael Östling, Adolf Schöner, Christer Hallin
Abstract: 4H-SiC BJTs were fabricated using epitaxial regrowth instead of ion implantation to form a highly doped extrinsic base layer necessary for a good base ohmic contact. A remaining p+ regrowth spacer at the edge of the base-emitter junction is proposed to explain a low current gain of 6 for the BJTs. A breakdown voltage of 1000 V was obtained for devices with Al implanted JTE.
Authors: Ye Tian, Luigia Lanni, Ana Rusu, Carl Mikael Zetterling
Abstract: This paper presents a monolithic 4H-SiC BJT latched emitter-coupled logic (ECL) comparator for high temperature analog-to-digital conversion. The comparator consists of a low-gain pre-amplifier, a track and latch stage and an output buffer. For low-speed input signals, the comparator input offset voltage is 3.9 mV at 27 °C and monotonically increases up to 9.1 mV at 500 °C. The single-ended output swing is 5.5 V at 27 °C and 3.9 V at 500 °C. The minimum comparison time is around 1μs from 27 °C to 500 °C. The whole comparator dissipates 464 mW in average over the considered temperature range with a 15 V power supply. It consumes 2.25 × 0.84 mm2 chip area (with the bond pads included).
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