Papers by Author: Jun Suda

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Authors: Masato Noborio, Jun Suda, Tsunenobu Kimoto
Abstract: SiC lateral double RESURF MOSFETs have been fabricated on the 4H-SiC (000-1)C face. By utilizing the C face, the channel resistance can be reduced because the C-face MOSFETs show higher channel mobility than the Si-face MOSFETs. In addition, by employing the double RESURF structure, the drift resistance is decreased and the breakdown voltage is increased with increasing the RESURF doses. The fabricated RESURF MOSFETs on the 4H-SiC (000-1)C face have demonstrated a low on-resistance of 40 mΩcm2 at an oxide field of 3 MV/cm and a breakdown voltage of 1580 V at zero gate bias. The figure-of-merit of the MOSFET is 62 MW/cm2, which is more than 10 times better than the conventional “Si limit” and the highest value among any lateral MOSFETs to date.
Authors: J. Kaido, Tsunenobu Kimoto, Jun Suda, Hiroyuki Matsunami
Authors: Hiroaki Sato, Ichiro Shoji, Jun Suda, Takashi Kondo
Abstract: Second-order nonlinear-optical coefficients of 4H and 6H-SiC have been measured with the wedge technique. Using high-quality (11-20) samples as well as performing rigorous measurements and analyses, the three independent components, d31 (= d32), d15 (= d24), and d33, have been accurately determined. We have found that the nonlinear-optical coefficients are nearly the same between the measured 4H and 6H-SiC samples within the experimental accuracy; d31 = 5.4 pm/V, d15 = 6.2 pm/V, and d33 = 9.7pm/V.
Authors: Toru Hiyoshi, Tsutomu Hori, Jun Suda, Tsunenobu Kimoto
Abstract: A 10 kV 4H-SiC PiN diode with an improved junction termination structure has been fabricated. An improved bevel mesa structure, nearly vertical side-wall at the edge of pn junction and rounded corner at mesa bottom, has been formed by reactive ion etching (RIE). The junction termination extension (JTE) region has been optimized by device simulation, and simulated breakdown voltage has been compared with experimental results. The locations of electric field crowding and diode breakdown have been discussed.
Authors: Y. Miyazawa, C.S. Chang, H. Sato, Jun Suda, T. Hiraoka, Kiichi Kanda, T. Ariga
Abstract: Joining technology of CP-Titanium and Titanium alloy is very important for manufacturing field. In that case of titanium brazing, chemical compositions of brazing filler metal and brazing atmosphere are very important. In this study, CP-Ti/CP-Ti and Ti alloy/Stainless Steel were brazed with Ti-based laminated brazing filler metal by using continuous type furnace under Ar gas atmosphere containing extremely low oxygen. Laminated filler was fabricated by roll bonding technology. Chemical compositions of laminated filler metal used in this study were Ti-15Cu-15Ni and Ti-20Zr-20Cu-20Ni. Brazing temperature employed in this study was 850, 900, 950, and 1000 C. These brazing temperatures were based on thermal analysis results and alpha-beta transformation temperature of the base metal used in this study. Firstly melting properties of laminated brazing filler metal was investigated with DTA and DSC. Secondary joint characteristics were estimated by micro-structural observation at the joint and mechanical properties measurement. Sound joint was obtained in this study according to outside appearance of the specimen. Ti-20Zr-20Cu-20Ni filler had low melting point as compared with Ti-15Cu-15Ni according to thermal analysis results and fillet form-ability. Ni and Cu were diffused from molten brazing filler to base metal during brazing and Ti-Cu-Ni eutectoid reaction was took placed at the based metal during cooling after brazing.
Authors: Tsunenobu Kimoto, Gan Feng, Toru Hiyoshi, Koutarou Kawahara, Masato Noborio, Jun Suda
Abstract: Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.
Authors: Yuichiro Nanen, Jun Suda, Tsunenobu Kimoto
Abstract: Characteristics of high-voltage lateral silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) with various reduced surface field (RESURF) structures were simulated. Breakdown voltage was enhanced from 5300 V for single-zone RESURF to 7400 V for two-zone, and to 7600 V for quasi-modulated RESURF MOSFETs.
Authors: Sho Sasaki, Jun Suda, Tsunenobu Kimoto
Abstract: The c- and a-lattice constants of nitrogen-doped 4H-SiC were measured in the wide temperature range (RT - 1100°C). The samples used in this study were heavily doped substrates and lightly-doped free-standing epilayers. The lattice constants at room temperature are almost identical for all the samples. However, the lattice contraction by heavy nitrogen doping was clearly observed at high temperatures, which indicates that the thermal expansion coefficients are dependent on the nitrogen concentration. The lattice mismatch (Δd/d) between a lightly-doped free-standing epilayer (Nd = 6x1014 cm-3) and a heavily-doped substrate (Nd = 2x1019 cm-3) was calculated as 1.7x10-4 at 1100°C. The authors also investigated lattice constants of high-dose N+, P+, and Al+-implanted 4H-SiC. Reciprocal space mapping (RSM) was utilized to investigate the lattice mismatch and misorientation. The RSM images show the c-lattice expansion and c-axis tilt of the ion-implanted layers, irrespective of ion species. The authors conclude that the lattice expansion is not caused by heavy doping itself, but by secondary defects formed after the ion-implantation and activation-annealing process.
Authors: H. Kawano, Tsunenobu Kimoto, Jun Suda, Hiroyuki Matsunami
Abstract: Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.
Authors: Masato Noborio, Michael Grieb, Anton J. Bauer, Dethard Peters, Peter Friedrichs, Jun Suda, Tsunenobu Kimoto
Abstract: In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.
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