Papers by Author: Kenji Fukuda

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Authors: Hiroshi Kono, Takuma Suzuki, Kazuto Takao, Masaru Furukawa, Makoto Mizukami, Chiharu Ota, Shinsuke Harada, Junji Senzaki, Kenji Fukuda, Takashi Shinohe
Abstract: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.
607
Authors: Hiroshi Kono, Takuma Suzuki, Makoto Mizukami, Chiharu Ota, Shinsuke Harada, Junji Senzaki, Kenji Fukuda, Takashi Shinohe
Abstract: Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.
987
Authors: Dai Okamoto, Yasunori Tanaka, Tomonori Mizushima, Mitsuru Yoshikawa, Hiroyuki Fujisawa, Kensuke Takenaka, Shinsuke Harada, Shuji Ogata, Toshihiko Hayashi, Toru Izumi, Tetsuro Hemmi, Atsushi Tanaka, Koji Nakayama, Katsunori Asano, Kazushi Matsumoto, Naoyuki Ohse, Mina Ryo, Chiharu Ota, Kazuto Takao, Makoto Mizukami, Tomohisa Kato, Manabu Takei, Yoshiyuki Yonezawa, Kenji Fukuda, Hajime Okumura
Abstract: We successfully fabricated 13-kV, 20-A, 8 mm × 8 mm, drift-free 4H-SiC PiN diodes. The fabricated diodes exhibited breakdown voltages that exceeded 13 kV, a forward voltage drop of 4.9–5.3 V, and an on-resistance (RonAactive) of 12 mW·cm2. The blocking yield at 10 kV on a 3-in wafer exceeded 90%. We investigated failed devices using Candela defect maps and light-emission images and found that a few devices failed because of large defects on the chip. We also demonstrated that the fabricated diodes can be used in conducting high-voltage and high-current switching tests.
855
Authors: Takashi Tsuji, Hiromu Shiomi, Naoyuki Ohse, Yasuhiko Onishi, Kenji Fukuda
Abstract: In this paper, newly developed 3300V-class IEMOSFETs were presented. By means of the optimization of current spreading layers (CSLs), we could achieve low specific on-resistance (RONA) of 11.6mΩcm2, while maintaining high blocking voltage (BVDSS) of 3978V. The RONA analysis revealed drastic reduction of JFET resistance compared to a MOSFET without a CSL. High ruggedness with the avalanche withstanding energy of 4.6J/cm2 was achieved by the optimal device design of the edge termination. We could also confirm favorable characteristics of RONA, BVDSS and threshold voltage (VTH) at high temperatures up to 200C, and the fast switching behavior.
962
Authors: Shinsuke Harada, Makoto Kato, Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Kazuo Arai
Abstract: The channel mobility in the SiC MOSFET degrades on the rough surface of the p-well formed by ion implantation. Recently, we have developed a double-epitaxial MOSFET (DEMOSFET), in which the p-well comprises two stacked epitaxially grown p-type layers and an n-type region between the p-wells is formed by ion implantation. This device exhibited a low on-resistance of 8.5 mcm2 with a blocking voltage of 600 V. In this study, to further improve the performance, we newly developed a device structure named implantation and epitaxial MOSFET (IEMOSFET). In this device, the p-well is formed by selective high-concentration p+ implantation followed by low-concentration p- epitaxial growth. The fabricated IEMOSFET with a buried channel exhibited superior characteristics to the DEMOSFET. The extremely low specific on-resistance of 4.3 mcm2 was achieved with a blocking voltage of 1100 V. This value is the lowest in the normally-off SiC MOSFETs.
1281
Authors: Seiji Suzuki, Shinsuke Harada, Tsutomu Yatsuo, Ryouji Kosugi, Junji Senzaki, Kenji Fukuda
753
Authors: Mitsuo Okamoto, Seiji Suzuki, Makoto Kato, Tsutomu Yatsuo, Kenji Fukuda
Abstract: We have fabricated lateral RESURF MOSFETs on 4H-SiC(0001) Si-face and (000-1) C-face substrates, and compared those properties. The channel mobility of a lateral test MOSFET on a C-face was 41 cm2/Vs, which was much higher than 5 cm2/Vs for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was improved to 79 mΩcm2 as comparison with 2400 mΩcm2 for Si-face. The breakdown voltage was 490V for Si-face and 460V for C-face, which was 82% and 79% of the designed breakdown voltage of 600V, respectively. The device breakdown occurred destructively at the gate electrode edge.
805
Authors: Kenji Fukuda, Makoto Kato, Junji Senzaki, Kazutoshi Kojima, Takaya Suzuki
1417
Authors: Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Hajime Okumura, Kazuo Arai
Abstract: From a viewpoint of device application using p-channel SiC MOSFETs, control of their channel properties is of great importance. We aimed to control the electrical properties of 4H-SiC p-channel MOSFETs through locating the p-type epitaxial layer at the channel area, so called “epi-channel MOSFET” structure. We varied the dopant concentrations and the thickness of the epi-channel layer, and investigated their electrical properties. In case of heavily doped epi-channel samples, the devices indicated “normally-on” characteristics, and their channel mobility decreased slightly in comparison with the inversion-type devices. As for lightly doped epi-channel samples, the subthreshold current increased with thickness of the epi-channel layer keeping their “normally-off” characteristics. Their channel mobility also increased with thickness of the epi-channel layer. The peak value of field effect channel mobility of the sample with 2.5 μm thickness and 5×1015 /cm3 dopant concentration epi-channel was 18.1 cm2/Vs.
711
Authors: Kenji Fukuda, Junji Senzaki, Mitsuhiro Kushibe, Kazutoshi Kojima, Ryouji Kosugi, Seiji Suzuki, Shinsuke Harada, Takaya Suzuki, Tomoyuki Tanaka, Kazuo Arai
1057
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