Papers by Author: Leonid Fursin

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Authors: Yu Zhu Li, Leonid Fursin, J. Wu, Petre Alexandrov, Jian H. Zhao
Authors: J. Wu, Leonid Fursin, Yu Zhu Li, Petre Alexandrov, Jian H. Zhao
Authors: Jian H. Zhao, Leonid Fursin, Petre Alexandrov, Larry X. Li, M. Weiner
Authors: Jian Hui Zhang, Leonid Fursin, Xue Qing Li, Xiao Hui Wang, Jian H. Zhao, Brenda L. VanMil, Rachael L. Myers-Ward, Charles R. Eddy, D. Kurt Gaskill
Abstract: This work reports 4H-SiC bipolar junction transistor (BJT) results based upon our first intentionally graded base BJT wafer with both base and emitter epi-layers continuously grown in the same reactor. The 4H-SiC BJTs were designed to improve the common emitter current gain through the built-in electrical fields originating from the grading of the base doping. Continuously-grown epi-layers are also believed to be the key to increasing carrier lifetime and high current gains. The 4H-SiC BJT wafer was grown in an Aixtron/Epigress VP508, a horizontal hot-wall chemical vapor deposition reactor using standard silane/propane chemistry and nitrogen and aluminum dopants. High performance 4H-SiC BJTs based on this initial non-optimized graded base doping have been demonstrated, including a 4H-SiC BJT with a DC current gain of ~33, specific on-resistance of 2.9 mcm2, and blocking voltage VCEO of over 1000 V.
Authors: Petre Alexandrov, B. Wright, M. Pan, M. Weiner, Leonid Fursin, Jian H. Zhao
Authors: Jian H. Zhao, Kiyoshi Tone, Larry X. Li, Petre Alexandrov, Leonid Fursin, M. Weiner
Authors: Larry X. Li, Leonid Fursin, Jian H. Zhao, Petre Alexandrov, M. Pan, M. Weiner, Terry Burke, G. Khalil
Authors: Yan Bin Luo, Leonid Fursin, Jian H. Zhao, Petre Alexandrov, B. Wright, M. Weiner
Authors: Y. Zhang, Kuang Sheng, Ming Su, Jian H. Zhao, Petre Alexandrov, Leonid Fursin
Abstract: A series of high voltage (HV) and low voltage (LV) lateral JFETs are successfully developed in 4H-SiC based on the vertical channel LJFET (VC-LJFET) device platform. Both room temperature and 300 oC characterizations are presented. The HV JFET shows a specific-on resistance of 12.8 mΩ·cm2 and is capable of conducting current larger than 3 A at room temperature. A threshold voltage drop of about 0.5 V for HV and LV JFETs is observed when temperature varies from room temperature to 300 oC. The measured increase of specific-on resistance with temperature due to a reduction of electron mobility agrees with the numerical prediction. The first demonstration of SiC power integrated circuits (PIC) is also reported, which shows 5 MHz switching at VDS of 200 V and on-state current of 0.4 A.
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