Papers by Author: Philip G. Neudeck

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Authors: Xiao An Fu, Amita Patil, Philip G. Neudeck, Glenn M. Beheim, Steven Garverick, Mehran Mehregany
Abstract: This paper reports fabrication and electrical characterization of 6H-SiC n-channel, depletion-mode, junction-field-effect transistors (JFETs) for use in high-temperature analog integrated circuits for sensing and control in propulsion, power systems, and geothermal exploration. Electrical characteristics of the resulting JFET devices have been measured across the wafer as a function of temperature, from room temperature to 450oC. The results indicate that the JFETs are suitable for high-gain amplifiers in high-temperature sensor signal processing circuits.
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Authors: Kevin M. Speer, Philip G. Neudeck, Mehran Mehregany
Abstract: The SiC vacuum field-effect transistor (VacFET) was first reported in 2010 as a diagnostic tool for characterizing the fundamental properties of the inverted SiC semiconductor surface without confounding issues associated with thermal oxidation. In this paper, interface state densities are extracted from measurements of threshold voltage instability on a SiC VacFET and a SiC MOSFET. It is shown that removing the oxide can reduce the interface state density by more than 70%.
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Authors: Kevin M. Speer, David J. Spry, Andrew J. Trunek, Philip G. Neudeck, M.A. Crimp, J.T. Hile, C. Burda, P. Pirouz
Abstract: pn diodes have recently been fabricated from 3C-SiC material heteroepitaxially grown atop on-axis 4H-SiC mesa substrate arrays [1,2]. Using an optical emission microscope (OEM), we have investigated these diodes under forward bias, particularly including defective 3C-SiC films with in-grown stacking faults (SFs) nucleated on 4H-SiC mesas with steps from screw dislocations. Bright linear features are observed along <110> directions in electroluminescence (EL) images. These features have been further investigated using electron channeling contrast imaging (ECCI) [3]. The general characteristics of the ECCI images—together with the bright to dark contrast reversal with variations of the excitation error—strongly suggest that the bright linear features are partial dislocations bounding triangular SFs in the 3C-SiC films. However, unlike partial dislocations in 4H-SiC diodes whose recombination-enhanced dislocation motion serves to expand SF regions, all the partial dislocations we observed during the electrical stressing were immobile across a wide range of current injection levels (1 to 1000 A/cm2).
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Authors: Philip G. Neudeck, J. Anthony Powell, David J. Spry, Andrew J. Trunek, X. Huang, William M. Vetter, Michael Dudley, Marek Skowronski, Jin Qiang Liu
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Authors: Philip G. Neudeck, Michael J. Krasowski, Liang Yu Chen, Norman F. Prokop
Abstract: The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 °C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 °C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 °C to +500 °C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.
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Authors: X. Huang, Michael Dudley, W. Cho, Robert S. Okojie, Philip G. Neudeck
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Authors: Andrew J. Trunek, Philip G. Neudeck, J. Anthony Powell, David J. Spry
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Authors: C.M. Schnabel, M. Tabib-Azar, S.G. Bailey, Philip G. Neudeck, H.B. Su, Michael Dudley, R.P. Raffaelle
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Authors: N. Keskar, K. Shenai, Philip G. Neudeck
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Authors: Philip G. Neudeck, Liang Yu Chen, David J. Spry, Glenn M. Beheim, Carl W. Chang
Abstract: This work reports DC electrical characterization of a 76 mm diameter 4H-SiC JFET test wafer fabricated as part of NASA’s on-going efforts to realize medium-scale ICs with prolonged and stable circuit operation at temperatures as high as 500 °C. In particular, these measurements provide quantitative parameter ranges for use in JFET IC design and simulation. Larger than expected parameter variations were observed both as a function of position across the wafer as well as a function of ambient testing temperature from 23 °C to 500 °C.
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