Papers by Author: Rachael L. Myers-Ward

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Authors: Jian Hui Zhang, Leonid Fursin, Xue Qing Li, Xiao Hui Wang, Jian H. Zhao, Brenda L. VanMil, Rachael L. Myers-Ward, Charles R. Eddy, D. Kurt Gaskill
Abstract: This work reports 4H-SiC bipolar junction transistor (BJT) results based upon our first intentionally graded base BJT wafer with both base and emitter epi-layers continuously grown in the same reactor. The 4H-SiC BJTs were designed to improve the common emitter current gain through the built-in electrical fields originating from the grading of the base doping. Continuously-grown epi-layers are also believed to be the key to increasing carrier lifetime and high current gains. The 4H-SiC BJT wafer was grown in an Aixtron/Epigress VP508, a horizontal hot-wall chemical vapor deposition reactor using standard silane/propane chemistry and nitrogen and aluminum dopants. High performance 4H-SiC BJTs based on this initial non-optimized graded base doping have been demonstrated, including a 4H-SiC BJT with a DC current gain of ~33, specific on-resistance of 2.9 mcm2, and blocking voltage VCEO of over 1000 V.
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Authors: Jun Hu, Xiao Bin Xin, Petre Alexandrov, Jian H. Zhao, Brenda L. VanMil, D. Kurt Gaskill, Kok Keong Lew, Rachael L. Myers-Ward, Charles R. Eddy
Abstract: This paper reports a 4H-SiC single photo avalanche diode (SPAD) operating at the solar blind wavelength of 280 nm. The SPAD has an avalanche breakdown voltage of 114V. At 90% and 95% of the breakdown voltage, the SPAD shows a low dark current of 57.2fA and 159fA, respectively. The quantum efficiency of 29.8% at 280nm and <0.007% at 400nm indicates a high UV-to-visible rejection ratio of >4300. Single photon counting measurement at 280nm shows that a single photon detection efficiency of 2.83% with a low dark count rate of 22kHz is achieved at the avalanche breakdown voltage of 116.8V.
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Authors: Zachary Stum, A.V. Bolotnikov, Peter A. Losee, Kevin Matocha, Steve Arthur, Jeff Nasadoski, R. Ramakrishna Rao, O.S. Saadeh, Ljubisa Stevanovic, Rachael L. Myers-Ward, Charles R. Eddy, D. Kurt Gaskill
Abstract: Doubly-implanted SiC vertical MOSFETs were fabricated displaying a blocking voltage of 4.2kV and a specific on-resistance of 23 mΩ-cm2, on a 4.5mm x 2.25mm device. Design variations on smaller (1.1mm x 1.1mm) devices showed on-resistance as low as 17 mΩ-cm2 with a blocking voltage of 3.3kV. Analysis is presented of the on-resistance and temperature dependence (up to 175°C), as well as switching performance. Switching tests taken at 1000V and 6A showed turn-on and turn-off transients of approximately 20-40ns.
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Authors: Robert E. Stahlbush, Rachael L. Myers-Ward, Brenda L. VanMil, D. Kurt Gaskill, Charles R. Eddy
Abstract: The recently developed technique of UVPL imaging has been used to track the path of basal plane dislocations (BPDs) in SiC epitaxial layers. The glide of BPDs during epitaxial growth has been observed and the role of this glide in forming half-loop arrays has been examined. The ability to track the path of BPDs through the epitaxy has made it possible to develop a BPD reduction process for epitaxy grown on 8° offcut wafers, which uses an in situ growth interrupt and has achieved a BPD reduction of > 98%. The images also provide insight into the strong BPD reduction that typically occurs in epitaxy grown on 4° offcut wafers.
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Authors: Y. Shishkin, Rachael L. Myers-Ward, Stephen E. Saddow, Alexander Galyukov, A.N. Vorob'ev, D. Brovin, D. Bazarevskiy, R.A. Talalaev, Yuri N. Makarov
Abstract: A fully-comprehensive three-dimensional simulation of a CVD epitaxial growth process has been undertaken and is reported here. Based on a previously developed simulation platform, which connects fluid dynamics and thermal temperature profiling with chemical species kinetics, a complete model of the reaction process in a low pressure hot-wall CVD reactor has been developed. Close agreement between the growth rate observed experimentally and simulated theoretically has been achieved. Such an approach should provide the researcher with sufficient insight into the expected growth rate in the reactor as well as any variations in growth across the hot zone.
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Authors: Brenda L. VanMil, Robert E. Stahlbush, Rachael L. Myers-Ward, Yoosuf N. Picard, S.A. Kitt, J.M. McCrate, S.L. Katz, D. Kurt Gaskill, Charles R. Eddy
Abstract: Conversion of basal plane dislocations (BPD) to threading edge dislocations (TED) in 8° off-cut 4H-SiC within an n+ buffer layer would eliminate the nucleation site for Shockley-type stacking faults in active device regions grown on such buffer layers. To that end, the propagation and conversion of BPDs through in situ growth interrupts is monitored using ultraviolet photoluminescence (UVPL) wafer mapping. The optimized growth interrupt scheme lasts for 45 minutes with a propane mass flow of 10 sccm at growth temperature. This scheme has shown a conversion efficiency of up to 99% for samples with electron (hole) concentrations < 5x1014 cm-3 (8x1015 cm-3). Samples subjected to a 45 or 90 minute interrupt under 10 sccm of propane, regardless of conversion efficiency, exhibit a “slit” in the surface morphology associated with each BPD and oriented perpendicular to the off-cut and BPD propagation direction. Repetition of the optimal interrupt sequence with a 5 μm epilayer spacer grown between the two interrupts resulted in the same conversion efficiency as a single optimal growth interrupt. Incorporation of the optimal interrupt into an n+ layer is more complicated as attempts to do so in layers doped with nitrogen to 2x1018, 2x1017 and 2x1016 cm-3 resulted in conversion efficiencies of ~6%.
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Authors: Serguei I. Maximenko, Jaime A. Freitas, Yoosuf N. Picard, Paul B. Klein, Rachael L. Myers-Ward, Kok Keong Lew, Peter G. Muzykov, D. Kurt Gaskill, Charles R. Eddy, Tangali S. Sudarshan
Abstract: The effect of various types of in-grown stacking faults and threading screw/edge type dislocations on carrier lifetime and diffusion lengths in 4H-SiC epitaxial films was investigated through cathodoluminescence decays and charge collection efficiencies of electron beam induced current signals at specific defects sites. Most stacking faults yielded ~40% reduction in the carrier lifetime. Moreover, drastic lifetime reductions were observed in regions containing surface triangular defects and bulk 3C polytype inclusions. Dislocations of both types serve as efficient recombination centers, though stronger reduction in diffusion lengths was observed in the vicinity of screw type dislocations.
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Authors: D. Kurt Gaskill, Michael A. Mastro, Kok Keong Lew, Brenda L. VanMil, Rachael L. Myers-Ward, Ronald T. Holm, Charles R. Eddy
Abstract: A set of three 4H-SiC wafers with manufacturer specified micropipe density of 0-5 cm-2 were characterized by x-ray diffraction (XRD) maps before and after final chemical-mechanical polish. After final polish, the wafers were also investigated with atomic force microscopy, radius of curvature measurements and cross-polarization (x-pol) mapping. It was found that there was largely a lack of correlation between the XRD and x-pol maps, which strongly suggests that x-pol is insensitive to crystalline imperfections to which XRD is sensitive.
235
Authors: O.Y. Goue, Yu Yang, J.Q. Guo, Balaji Raghothamachar, Michael Dudley, J.L. Hosteller, Rachael L. Myers-Ward, Paul B. Klein, D. Kurt Gaskill
Abstract: Lifetime maps for two 4H-SiC epi-wafers (samples 1 and 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the type and distribution of structural defects mapped by synchrotron X-ray topography (white beam and monochromatic). Sample 1 showed lower lifetime inside one of its higher doped facet regions and along its edges. The low lifetime in the facet region was associated with the presence of a high density of multi-layered Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). These stacking faults are likely double Shockley stacking faults (DSSFs) and probably nucleated from scratches present on the substrate surface and LAGBs present in that region, propagating during epilayer growth. In contrast, sample 2 showed a reduced carrier lifetime in the middle region associated with a network of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that are generated during epilayer growth. Along the edges of both samples, overlapping triangular defects, microcracks and BPD loops lowered lifetime.
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Authors: Rachael L. Myers-Ward, Stephen E. Saddow, Shailaja P. Rao, Karl D. Hobart, M. Fatemi, Francis J. Kub
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