Papers by Author: Toru Hiyoshi

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Authors: Toru Hiyoshi, Tsutomu Hori, Jun Suda, Tsunenobu Kimoto
Abstract: A 10 kV 4H-SiC PiN diode with an improved junction termination structure has been fabricated. An improved bevel mesa structure, nearly vertical side-wall at the edge of pn junction and rounded corner at mesa bottom, has been formed by reactive ion etching (RIE). The junction termination extension (JTE) region has been optimized by device simulation, and simulated breakdown voltage has been compared with experimental results. The locations of electric field crowding and diode breakdown have been discussed.
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Authors: Tsunenobu Kimoto, Gan Feng, Toru Hiyoshi, Koutarou Kawahara, Masato Noborio, Jun Suda
Abstract: Extended defects and deep levels generated during epitaxial growth of 4H-SiC and device processing have been reviewed. Three types in-grown stacking faults, (6,2), (5,3), and (4,4) structures, have been identified in epilayers with a density of 1-10 cm-2. Almost all the major deep levels present in as-grown epilayers have been eliminated (< 1x1011 cm-3) by two-step annealing, thermal oxidation at 1150-1300oC followed by Ar annealing at 1550oC. The proposed two-step annealing is also effective in reducing various deep levels generated by ion implantation and dry etching. The interface properties and MOSFET characteristics with several gate oxides are presented. By utilizing the deposited SiO2 annealed in N2O at 1300oC, a lowest interface state density and a reasonably high channel mobility for both n- and p-channel MOSFETs with an improved oxide reliability have been attained.
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Authors: Koutarou Kawahara, Giovanni Alfieri, Toru Hiyoshi, Gerhard Pensl, Tsunenobu Kimoto
Abstract: The authors have investigated effects of thermal oxidation on deep levels in the whole energy range of bandgap of 4H-SiC which are generated by ion implantation, by deep level transient spectroscopy (DLTS). The dominant defects in n-type samples after ion implantation and high-temperature annealing at 1700oC, IN3 (Z1/2: Ec – 0.63 eV) and IN9 (EH6/7: Ec – 1.5 eV) in low-dose-implanted samples, can be remarkably reduced by oxidation at 1150oC. However, in p-type samples, the IP8 (HK4: Ev + 1.4 eV) survives and additional defects, several defects such as IP4 (HK0: Ev + 0.72 eV) appear after thermal oxidation in low-dose-implanted samples. The defects except for the IP8 center can be reduced by subsequent annealing at 1400oC. These phenomena are explained by a model that excess interstitials are generated at the oxidizing interface and diffuse into the bulk region.
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