Papers by Author: Xue Qing Li

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Authors: Petre Alexandrov, Anup Bhalla, Zhong Da Li, Xue Qing Li, John Bendel, Jonathan Dodge
Abstract: We present a SiC Trench JFET technology that achieves a record setting specific on-resistance (RDSA) of 0.75mohm.cm2. These SiC devices are combined with optimized low voltage MOSFETs to form co-packaged cascode transistors, which provide unprecedented performance benefits, with a clear path to direct cost parity with silicon superjunction devices. These devices are shown to be useful for all circuit topologies..
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Authors: Leonid Fursin, Xue Qing Li, Xing Huang, Ke Zhu, William Simon, Anup Bhalla
Abstract: To address stringent performance and reliability requirements of industrial and traction power conversion systems we have developed planar 3,300V MOSFETs at a 6-inch SiC-compatible silicon CMOS foundry. By optimizing the unit cell structure and using a deep current-spreading layer we demonstrated a low MOSFET specific on-resistance RDSA=11.2 mΩ·cm2 (ID=5A, VGS=15V) and fast switching for the baseline design. Robust short-circuit handling (7.5μs at Vds=1500V and 5.0μs at Vds=2200V) was demonstrated with an alternative unit cell design with RDSA=14.8 mΩ·cm2 (ID=5A, VGS=15V).
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Authors: Leonid Fursin, Frank Hoffmann, John Hostetler, Xue Qing Li, Matthew Fox, Petre Alexandrov, Mari Anne Gagliardi, Mark Holveck
Abstract: A growing demand for smart and flexible photovoltaic power conversion and pulsed-power systems is leading to rapid development and commercialization of medium voltage 6.5 - 24 kV, wide-bang gap rectifiers and switches. Conventional silicon bipolar switches are limited to roughly 8 kV breakdown voltages and scaling up the voltage rating requires very thick wafers presenting significant manufacturing challenges. Very thick drift layers of silicon devices also translate into a very high minority carrier charge injected during forward conduction for an efficient conductivity modulation, hence leading to an extremely slow switching speed and poor efficiency. In this paper USCi presents the development of 6.5 kV 4H-SiC gate-turn-off thyristors (GTOs) with multiple floating guard-ring edge termination, and describes their application in an AC-link grid-tied solar inverter system.
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Authors: Jian Hui Zhang, Jian Hui Zhao, Xiao Hui Wang, Xue Qing Li, Leonid Fursin, Petre Alexandrov, Mari Anne Gagliardi, Mike Lange, Christopher Dries
Abstract: This paper reports our recent study on 4H-SiC power bipolar junction transistors (BJTs) with deep mesa edge termination. 1200 V – 10 A 4H-SiC power BJTs with an active area of 4.64 mm2 have been demonstrated using deep mesa for direct edge termination and device isolation. The BJT’s DC current gain () is about 37, and the specific on-resistance (RSP-ON) is ~ 3.0 m-cm2. The BJT fabrication is substantially simplified and an overall 10% reduction in the device area is achieved compared to the multi-step JTE-based SiC-BJTs.
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Authors: Petre Alexandrov, Xue Qing Li, Jian Hui Zhao
Abstract: An optically controlled power switch based on 4H-SiC Trenched and Implanted Vertical JFETs (TIVJFET) was developed that comprises three parts: an LED light-source driver, light-triggered integrated gate buffer driver, and vertical high power normally-off switch. The light-triggered integrated gate buffer driver includes a photodiode and four stages of low voltage 4H-SiC TIVJFETs, which are hybrid integrated. Optically gated power switching was experimentally demonstrated with a maximum switching frequency of about 50 kHz, the system performance limiting factors were clearly identified and experimentally confirmed, and ways to substantially increase the switching frequency were shown. From calculations, based on realistically possible system parameters values, it could be seen that a maximum switching frequency around 1 MHz is theoretically possible with a proper choice of light source, detector, and buffer transistor parameters.
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Authors: Xue Qing Li, Anup Bhalla, Petre Alexandrov
Abstract: This work investigates the short-circuit capability of SiC cascode by performing two-dimensional electro-thermal TCAD simulations. The effects of the threshold voltage of the SiC JFET on the cascode short-circuit withstand time are studied. A design trade-off between the JFET specific-on resistance and the cascode short-circuit withstand time is determined. The experimental results are also presented.
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Authors: Xue Qing Li, Petre Alexandrov, Leonid Fursin, Christopher Dries, Jian Hui Zhao
Abstract: This paper reports the design and experimental demonstration of a novel bi-directional solid-state disconnect (SSD) based on Silicon Carbide (SiC) depletion-mode junction field effect transistors (JFETs) for protecting critical sensitive components in high power systems. The SSD is able to provide a fast disconnect action upon receiving a preset trip current flowing through it and has a very low insertion loss, which makes it suitable for high power applications. For the application in 150kW six-phase power inverter systems, an insertion loss of less than 0.91% and a current fall time of less than 20μs for trip currents of about 800A have been demonstrated experimentally. To the best of our knowledge, there are no other solid-state disconnects available of comparable parameters.
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