Characteristics Evaluation and Device Design

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Characteristics Evaluation and Device Design

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Sócientific.Net

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Volume1022 of
Key Engineering Materials
ISSN print 1013-9826
ISSN web 1662-9795

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-05

Online:
2025-09-08

Preface

The original version of this paper is available on https://www.scientific.net/KEM.1022.-1.pdf

The presented special edition is dedicated to advances in the characteristics analysis and device design of silicon carbide ( SiC ) power electronics, highlighting the relation between semiconductor properties, structure peculiarities of the finished devices, and their functional performance optimisation. The contributions examine a wide range of devices, including SiC thyristors, trench MOSFET structures, PiN diodes, Schottky diodes, etc.

Key functional aspects such as breakdown voltage, drain voltage behaviour, channel mobility, and junction termination extension are analysed, alongside innovations in the design of bidirectional power switches, as well as practical aspects of using TCAD modelling for device simulation and optimisation.

By combining technological advances, modern design methodologies, and performance evaluation techniques, this special edition provides a comprehensive overview of state-of-the-art approaches in developing the next generation of SiC-based power devices.

Table of Contents

Preface

Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

Kamil Kotra, Sigo Scharnholz, Ralf Hassdorf, Milan Zuvic, Klaus Hoffmann

SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Ilaria Matacena, Luca Maresca, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento

TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

Hemant Dixit, Daniel J. Lichtenwalner, Andreas Scholze, Sei Hyung Ryu

On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

Arne Benjamin Renz, Yifan Jiang, Peter Michael Gammon, Erfan Bashar, Jiankang Bu

The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Yisi Liu, Saeed Jahdi, Mana Hosseinzadehlish, Ian Laird, Phil Mellor, Konstantinos Floros, Ingo Lüdtke

Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Seung Yup Jang, Dong Young Kim, Dinuth C.Y.B. Yapa Mudiyanselage, Ho Jung Lee, Chung Kwang Lee, Jin Gon Kim, Dong Kyun Kim, Woong Je Sung

Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Yoshitaka Kimura, Takaaki Tominaga, Yutaka Fukui, Akifumi Iijima, Kohei Adachi, Fumitoshi Yamamoto, Yasuhiro Kagawa, Kazushi Kono

SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Jenny Damcevska, Sima Dimitrijev, Ji Sheng Han, Daniel Haasmann, Philip Tanner

Three Level Pulses to Investigate Gate Switching Instability

Dick Scholten, Juergen Uschmann

DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Ting Qiang Yang, Marco Perazzi, Christopher Zellner, Georg Pfusterschmied, Ulrich Schmid

TCAD Model Parameter Calibration Strategy for SiC MOSFET

Jieun Lee, Jong Min Kim, Seung Hyun Kim, Hee Bae Lee, Young Chul Kim, Hyun Chul Nah

Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Ayan K. Biswas, Daniel J. Lichtenwalner, Brett Hull, Donald A. Gajewski, Satyaki Ganguly

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/characteristics-evaluation-and-device-design/978-3-0364-1914-5

Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 1-8

doi: 10.4028/p-TfWv54

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-02-14

Accepted:
2025-02-20

Online:
2025-09-08

Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

Kamil Kotra , Sigo Scharnholz , Ralf Hassdorf , Milan Zuvic and Klaus Hoffmann

French-German Research Institute of Saint-Louis (ISL), 5 rue du Général Cassagnou, 68300 Saint-Louis, France

Department of Electrical Engineering, Power Electronics, Helmut Schmidt University, Holstenhofweg 85, 22043 Hamburg, Germany

kamil.kotra@isl.eu, sigo.scharnholz@isl.eu, ralf.hassdorf@isl.eu, milan.zuvic@isl.eu,

Keywords: 4 H -SiC, Thyristor, Pulsed Power, TCAD Simulation, Junction Termination, Etched JTE

Abstract

H -SiC thyristors are of particular interest in pulsed power applications due to their ability to block high voltages and transfer high current densities along with fast switching times. Here, we present a paper that demonstrates both (i) the impact of the design parameters on the blocking characteristics based on simulations taking into account the anisotropy of and (ii) a critical comparison to real devices having equivalent epitaxial structural design. Simulations and measurements show that an etched junction termination extension (JTE) is suitable to design highvoltage SiC thyristors. Concerning breakdown voltage, the real devices data agree to simulations for junction termination extension thickness in the relevant region. Besides the actual JTE thickness and doping concentration, the presence of a relatively thin field-stop layer might explain the discrepancy between experiment and simulation.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

Silicon carbide high power thyristors constitute the most promising switching device technology for pulsed power which potentially also could find their application in the civil domain, e.g., in HVDC distribution systems [1]. While medium-voltage , unipolar SiC switches like SiC MOSFETs have been widely commercialized today, high voltage ( ) and especially very high voltage bipolar SiC devices like thyristors have not. This opens up the possibility for development and optimization of device parameters and technology. Here, we focus on the design and electrical characteristics of the thyristor and the effect of SiC anisotropy, the structural relationship of which between the junction termination extension (JTE) design and the underlying crystallographic orientation has been paid not that much of attention [2]. The main technological challenge is the design of an efficient JTE to significantly mitigate critical electric field distributions originating not only at the device periphery but also at their planar junctions, permitting to blocking very high voltage [3]. For ease of device processing, we focus on 1-step/3-step JTE design having the advantage to be realized using simple standard etching protocols [4].

Commercially high quality wafers are grown in (0001) surface orientation, which causes the on-state current flow and electric field to be distributed mainly along the c -axis. However, the etched JTE introduces a crystallographic structure disorder in the direction perpendicular to the plane. To optimize the breakdown voltage of a SiC thyristor it is important to design an appropriate JTE to avoid hot spots (spikes) of the electric field, which may generate local avalanche centers that trigger a breakdown in the device. Using multi-step design brings us closer to bevelled etch termination which is considered to be the most efficient one, by selectively removing charges from the junction at the edges [5]. The use of a 3-step design gives us another advantage over the 1-
step JTE. It can be seen that we achieve high breakdown voltage for different JTE etching depths, which are less prone against fluctuations resulting from reactive ion etching. The optimization can be done using TCAD simulation tools such as the Sentaurus software used in our case.

In this paper, we present the measurement results of breakdown voltage ( ) and on-state characteristics of SiC thyristors with a thick drift layer and compare them with simulations. They prove that an etched JTE is suitable to design high-voltage SiC thyristors. We also report high influence of field-stop layer on in punch through design which has not been fully investigated before. Finally, due to the complex and anisotropic nature of the SiC band structure, we investigate the influence of the and crystallographic orientations on the etched JTE thyristor breakdown voltage.

Device and Simulated Structures

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

A schematic cross-section of the fabricated and simulated thyristor with JTE is shown in Fig. 1. For our devices, we chose an substrate on which epitaxial layers were grown. The -drift layer is thick and has a concentration of ; it is separated from the substrate by a thin field-stop (p-buffer) layer, the doping concentration of which, given by the manufacturer, is and the thickness is . The n -base (gate) layer is thick and has a concentration of , and the -anode is thick and has a concentration of . The entire structure was covered with a thick passivation of . The fully processed wafer, fabricated at ISL, comprises thyristors with 1-step JTE, see Fig. 2. The devices have an active conduction area between the edge termination of .

[picture]

Fig. 1. Cross-section of thyristor half-cell, with simulated quasi-1D thyristor structure (region A) and central PiN diode with JTE (region B), respectively.

Fig. 1. Cross-section of thyristor half-cell, with simulated quasi-1D thyristor structure (region A) and central PiN diode with JTE (region B), respectively.

[picture]

Fig. 2. Processed SiC wafer with thyristor devices under investigation (left) and bonded die (right).

Fig. 2. Processed SiC wafer with thyristor devices under investigation (left) and bonded die (right).

In our simulations, in order to shorten the simulation time, the structure of the entire thyristor was simplified depending on the task under investi-gation. For simulating the maximum and the onstate characteristic, it was simplified to a quasi-1D thyristor structure (cf. Fig. 1, region A). Simulating the determined by the JTE, we can simplify the structure to the central PiN diode, located between the -drift and n -base (cf. Fig. 1, region B ). For the PiN diode, the cell width in simulation is and, for the quasi-1D thyristor structure, the width is . All simulated structures are scaled in c-direction by an area factor of per width, which corresponds to an area of for contacts.

In the study, we focused on de-vices with 1 -step and 3 -step JTE. For 1 -step JTE, the simulation length is and, for 3-step JTE, each step covers which in total is equal to the single step design. The main parameter determining the value is the actual JTE thickness, This thickness defines the amount of charge, which translates into a changing electric field distribution. In the case of the single-step design structure, we checked the breakdown voltage values for depths from 0.5 to . In case of the design with a 3-step JTE, it was first necessary to determine the most optimal DJTE step value (cf. Fig. 1). For this purpose, we used the DJTE value of the single JTE step for which we obtained the highest breakdown voltage, and based on this we varied the height of the step from 0.2 to . It turned out that the maximum results were obtained for . Using this value, we again performed simulations with DJTE in the range of . In parallel, we varied also the thickness of the field-stop (p-buffer) layer (using , and ), and its concentration from to .

To portray the thyristor in Sentaurus we used the built-in models for mobility, carrier lifetime, recombination, bandgap narrowing and avalanche. The two default lifetime models used in the simulations are the Shockley-Read-Hall (SRH) Concentration Dependent Lifetime Model and the Auger Recombination Lifetime model.

To simulate the breakdown voltage, it is necessary to use an avalanche model based on impact ionization coefficients. Due to the anisotropy of silicon carbide, the Okuto-Crowell model was used for avalanche generation, the simplified formula (see, Ref. 6 using: ) of which is presented in Eq. 1:

where is the electric field and are impact ionization coefficients defined as the number of electron-hole pairs generated by impact ionization under a certain electric field. In our simulations,
we used the basic impact ionization coefficients taking into account the anisotropy of SiC which are presented in Table 1.

Table 1. Impact ionization parameters from Ref. 7 used for the Okuto-Crowell model.

Crystallographic orientation | an [cm⁻¹] | bn [V×cm⁻¹] | ap [cm⁻¹] | bp [V×cm⁻¹]
<0001> | 1.76×10⁸ | 3.3×10⁷ | 3.41×10⁸ | 2.5×10⁷
<11̄20> | 2.1×10⁷ | 1.7×10⁷ | 2.96×10⁷ | 1.6×10⁷

The use of this model is important to correctly simulate the breakdown voltage because the mass of the carriers varies depending on the crystallographic orientation. From the point of basic device physics, it is clear effective masses have their impact on the acceleration of carriers when an electric field is applied which then directly translates into mobility, transport, and drift velocity, and in turn contributes to the impact ionization coefficients [8].

Blocking Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

Simulation results concerning the breakdown voltage of the SiC thyristor under investigation with 1-step and 3-step JTE are shown in Fig. 3. The graph shows that using a larger number of steps results in a higher breakdown voltage. Regarding the 1 -step JTE (anisotropic case) a maximum Vbr of 11.5 kV is reached when is close to whereas, for the 3-step JTE, the maximum is 15 kV for . This corresponds to and of the theoretical value, respectively, simulated using a simple 1D-diode structure.

The results of measurements, performed on a thyristor with a 1 -step JTE, where the optimal DJTE was assumed to be (see Fig. 3, denoted "only <0001>"), show that for the best device the breakdown voltage is 7 kV . Fig. 4 shows the I-V characteristics in forward blocking direction. Comparing the measurement results with simulations for a 2D-PiN diode with 1-step JTE, it can be seen that the blocking voltage more closely corresponds to the D etching depth of (Fig. 3), which is within the limit of technological and measure-ment errors.

[picture]

Fig. 3. Simulation of as a function of for 1 -step and 3-step JTE ( , each for anisotropic and isotropic impact ionization (cf. values in Table 1).

Fig. 3. Simulation of as a function of for 1 -step and 3-step JTE ( , each for anisotropic and isotropic impact ionization (cf. values in Table 1).

[picture]

Fig. 4. Measured forward blocking characteristic of one of the best devices compared to simulation.

Fig. 4. Measured forward blocking characteristic of one of the best devices compared to simulation.

Regarding these measurement results, we see that the experimentally obtained breakdown voltage does not attain the best simulation results, based on the specifications/capabili-ties of the SiC wafer used. Therefore, we investigated how the blocking voltage is influenced by the para-meters of the field-stop (p-buffer) layer (Fig. 5). Due to the punch-through design of our thyristor, which provides a more gradual distribution of the electric field in the drift layer [5], the field-stop layer concentration is of great importance. Regarding the simulation results in Fig. 5, it can be assumed that the thick field-stop ( p -buffer) layer must actually have a concentration of , instead of , as denoted in the wafer specification. Thus, if only the field-stop layer is considered, the limited efficiency of 7 kV gained in measurement could be attributed to its unexpectedly low doping concentra-tion.

In Fig. 3, we also present the influence of anisotropy for devices with 1 -step and 3 -step etched JTE. In addition to the simulations already described above, Hatake-yama's impact ionization coefficients (Table 1) were used individually, with the anisotropy deactivated. This made possible to investigate the influence of individual crystallo-graphic orientations on the break-down voltage. For 1-step JTE with up to , we observe that the anisotropic results are in between the results for the individual crystallo-graphic orientations. Above this , the values are closer to those for the orientation. For 3-step JTE, it can be seen that the breakdown voltage results, for practically the entire range of thicknesses, are close to the voltage value obtained when using coefficients of the <0001> direction. A deviation is observed only for the thickness of , for which (with ) we are approaching a quasi-2-step JTE (same holds for values below ).

[picture]

Fig. 5. Simulation of as a function of field-stop (p-buffer) layer concentration (NBuf) and thickness (DBuf).

Fig. 5. Simulation of as a function of field-stop (p-buffer) layer concentration (NBuf) and thickness (DBuf).

Analyzing these results, we observe that in the case of a 1 -step JTE, the electric field distributed along the JTE translates into a larger share of the anisotropy phenomenon in direction, while, for a 3-step JTE, due to the divided JTE regions, <0001> direction becomes dominant. Regarding the 1-step JTE, the interpretation corresponds to what has been shown and concluded in Ref. 7, concerning an implanted JTE: When the implantation dose (which compares to the thickness in case of our etched JTE) becomes higher than the optimum, the breakdown occurs at the outer edge of the JTE, where the electric field is rather lateral, and thus is dominated by the lower impact ionization coefficients in direction. In case of an etched JTE, the same argumentation holds for a thickness, lower than the optimum, when the breakdown occurs at the inner edge of the JTE. Around the optimum thickness, the electric field is homogenously spread along the JTE and therefore, rather aligned in<0001> direction. Thus, as can be observed in Fig. 3 for the "anisotropic" curve of the 1step JTE, the breakdown voltage is turning over towards the " " curve and then back to the one for direction. Using a 3-step JTE, on the other hand, allows spreading the electric field for a much wider range of DJTE. Therefore, the "anisotropic" curve of the 3 -step JTE in Fig. 3 approaches the one limited to <0001> orientation along almost the entire range.

On-State Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

The on-state characteristics of the simulated and measured SiC thyristors are presented in Fig. 6 for two drift layer thicknesses ( and , respectively. The default carrier lifetime values for electrons ( ) and holes ( ), implemented in the Sentaurus parameter file, are and , respectively. To turn the thyristors on, we apply a current to the gate, for both simulations and measure-ments. The measurements for both the and thick drift layer show a much higher on-state voltage drop than the simulations, when the default lifetime values and no contact resistance are considered. For a thick drift layer, we measure a forward voltage drop of 3.8 V at , while, for a drift layer, we determine 5.8 V . At first glance, this is consistent as the thicker drift layer comes up with a higher resistance. However, comparing the results with the simu-lations we see that the thickness of the drift layer does not have that much of an impact on the forward voltage drop.

[picture]

Fig. 6. Simulated and measured on-state characteristics of SiC thyristors with different drift layer thicknesses Dri ( : specific contact resistivity, : electron lifetime).

Fig. 6. Simulated and measured on-state characteristics of SiC thyristors with different drift layer thicknesses Dri ( : specific contact resistivity, : electron lifetime).

One reason for this behavior could be that no additional series resistance has been taken into account in the initial simulations. Looking for a relevant contribution of such a resistance, we identified the anode contact resistance, the value of which was determined using TLM test structures on both SiC wafers concerned, here, quantitatively in the order of . Using this value in the simulations allowed getting close to the measured on-state characteristic in case of the drift layer. For the drift layer, however, the dashed line in Fig. 6 indicates that some other contribution must be attributed to the much larger, measured voltage drop.

An additional explanation for the discrepancy between simulation and measurement could be the very short lifetime of the carriers due to the large amount of carbon vacancy defects incorporated, which shorten the diffusion length of minority carriers in the drift region [10]. It should be noted that, to effectively reducing the number of these carbon vacancy defects, various high temperature processes have been proposed, although, here, none of our devices was treated in that direction. Thus, in order to investigate the influence of the electron lifetime, , the minority carrier lifetime in the p-type drift layer, was reduced to 500 ns , a value still seen as typical in spite of the underlying indirect-transition band structure [10]. As the dotted lines in Fig. 6 show, this reduction further increases the voltage drop in the case of the drift layer. As expected for a thin drift layer (here ), the carrier lifetime has no significant effect in this aspect.

Finally, in order to getting close to the measured curve of the SiC thyristor with the drift layer, the contact resistance was further increased in the simulations, in accordance with a specific resistivity of , a value taken from TLM measurements in the center of the wafer under investigation (cf. Figs. 2). Even though a further reduction of would increase the total voltage drop, it further increases the threshold voltage as well, and therefore does not result in a better match to the measurement curve.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

In this paper, SiC thyristors with 1 -step and 3 -step JTE were presented as high voltage blocking devices for pulsed power applications. Experimental devices with a 1-step JTE confirm the breakdown voltage simulation results when a lower doping concentration value of the field-stop (pbuffer) layer is taken into account. According to the simulations, the use of a 3 -step JTE would allow a breakdown voltage of for an appropriately selected etching depth. Comparing breakdown
simulations based on anisotropic impact ionization with those just partially using coefficients for either <0001> or <11 orientation, revealed that a 1-step JTE is strongly affected by the lower coefficients of the direction. Therefore, a JTE with multiple steps does not only benefit from an increased robustness to process variations, in particular concerning the thickness D JTE, but also from a higher breakdown voltage in <0001> direction. Thus, the relatively low breakdown voltage of our experimental devices can partially be related to the fact, that they have only a 1 -step JTE implemented. Regarding on-state characteristics, we demonstrated that the SiC thyristor devices under investigation work properly with a relatively low on-resistance. TCAD simulations permitted to relate the actual voltage drop to both a series resistance, most probably of the anode contacts, and a relatively low minority carrier lifetime in the drift layer of 500 ns . Further investigation on the carrier lifetime impact needs to be done due to its high relevance for dynamic switching.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.1.pdf

H. O'Brien, A. Ogunniyi, S.H. Ryu, T. Tsoi, S.B. Bayne, "High-voltage silicon carbide thyristors on n -doped epi for pulsed power", in Proc. IEEE Int. Pulsed Power Conference, Denver, CO, USA, 2021, pp. 1-4.

Z. Li, K. Zhou, L. Zhang, X. Xu, L. Li, J. Li, G. Dai, "A simple multistep etched termination technique for 4H-SiC GTO thyristors", Solid State Electronics, vol. 151, 2019, pp. 1-5.

P. Godignon, J. Montserrat, J. Rebello, D. Planson, "Edge terminations for power devices: A critical issue", Materials Science Forum, vol. 1062, 2022, pp. 570-575.

G. Pâques, S. Scharnholz, N. Dheilly, D. Planson, R.W. De Doncker, "High-voltage 4H-SiC thyristors with a graded etched junction termination extension", IEEE Electron Device Letters, vol. 32, no. 10, 2011, pp. 1421-1423.

B.J. Baliga, "Fundamentals of Power Semiconductor Devices", Springer Science, New York, NY, USA, 2008.

SentaurusTM Device User Guide, version S-2021-06, Synopsys Inc., 2021, p. 445.

T. Hatakeyama, J. Nishio, C. Ota, T. Shinohe, "Physical modeling and scaling properties of 4HSiC power devices", Proc. IEEE Int. Conf. on Simulation of Semiconductor Processes and Devices, Tokyo, Japan, 2005, pp. 171-174.

T. Kimoto, J.A. Cooper, "Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications", John Wiley & Sons Singapore Pte. Ltd, 2014, pp.11-30.

S. Scharnholz, R. Hassdorf, J. Grau, K. Kotra, M. Zuvic, B. Vergne, unpublished results.

T. Kimoto, "High-voltage SiC power devices for improved energy efficiency", Proc. Jpn. Acad., no. 4, 2022, pp. 161-189.

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The original version of this eBook is available on https://www.scientific.net/book/characteristics-evaluation-and-device-design/978-3-0364-1914-5

Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 9-14

doi: 10.4028/p-A8OKYn

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-24

Accepted:
2025-02-24

Online:
2025-09-08

SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

The original version of this paper is available on https://www.scientific.net/KEM.1022.9.pdf

Ilaria Matacena , Luca Maresca , Michele Riccio , Andrea Irace , Giovanni Breglio , Santolo Daliento

Dept. of Electrical Engineering and Information Technologies, University of Naples Federico II, via Claudio, 21, 80125, Naples, Italy

ailaria.matacena@unina.it, bluca.maresca@unina.it, michele.riccio@unina.it, dandrea.irace@unina.it, ebreglio@unina.it, 'daliento@unina.it,

Keywords: SiC MOSFET, Capacitance, C-V curve.

Abstract

There are some technological issues in SiC MOSFETs that are still unsolved. One of the main problems is the high density of traps/defects at the interface. Traps distribution at such interface is complex and it affects the overall performance of the device. The high-density of defects at the interface is a relevant problem since it can influence the overall performance of the device, causing detrimental impacts on threshold voltage stability, channel mobility and leakage current amplitude. Due to the fundamental importance of the interface characterization, several techniques have been employed to investigate defects properties related to this region. In this work non-classical measurements are performed. Capacitance is measured between Gate and Source terminals while a fix DC voltage is imposed on the Drain. This latter is considered among positive values in the first case, while it is chosen as a negative voltage in the second case. The arising capacitances in both cases show an unexpected behavior which can be related to interface properties. To this aim numerical analysis is performed in Sentaurus TCAD environment.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.9.pdf

Silicon Carbide ( SiC ) MOSFETs are gradually replacing Silicon ( Si ) MOSFETs due to the excellent properties of SiC material. High thermal conductivity and high bandgap [1] are indeed properties of such material. These devices technology has undergone a great development in last decades. However, there are still some issues that are not completely solved. Among these it worth to be mentioned that the density of defects arising at the interface is orders of magnitudes higher with respect to . These defects can affect some crucial properties of the overall device [2] such as the channel mobility[4] and threshold voltage instability [3]. Given the key role played by the quality of the mentioned interface, several techniques have been considered to characterize the defect/traps interface density. Among these, the most used methods are based on the measurement of impedance, and more in detail capacitance varying with voltage. These techniques are widely used in various applications ranging from semiconductor devices and solar cells [5]-[13] to batteries [14]. This method is non-destructive, and it allows a fast characterization procedure. In literatures, most part of the studies for power devices are carried out on MOS structure where it is possible to rely to low-high frequency capacitance method [15]-[19]. The capacitance behavior in MOS structure changes drastically with varying frequency [20] and this variation can give information about the defects/traps in the device under test. In fact, the inversion charge is able to follow the applied stimulus only if the frequency is sufficiently low, due to the low thermal carrier generation in the depletion region. This means that in the inversion region the behavior of the capacitance is mainly described by the inversion charge not able to follow the high frequency of the applied stimulus. The last statement holds true only in the case of MOS structure. In MOSFETs, the situation is different since the channel is refilled with carriers coming from the Source and Drani regions in the inversion region. Thus, capacitance behavior in the inversion region results not varied for low and high frequency and the low-high frequency method cannot be used in this case [21]. From the foregoing, it is clear the necessity to accurately analyze the capacitance arising from a MOSFET device. This
can be performed by means of numerical environments which enable to characterize the interface properties [22]-[26]. The mentioned capacitance is usually measured at the Gate terminal and connecting Drain and Source terminals [27]-[29]. In previous works [25],[30]-[33], we investigated a non-classical C-V measurements on commercially available planar SiC MOSFETs. In these studies, experimental data are obtained by applying the AC small signal on the Gate, while a fix DC bias is applied on the Drain and the Source terminal is grounded. The so obtained capacitance shows an unexpected peak in the inversion region, which can be related to the interface properties and the channel region. In this work, the capacitance trend is investigated when the applied fix Drain voltage assumes negative values. Experimental results are shown and supported by numerical analysis. The presented model is built in Sentaurus TCAD environment. An unexpected peak in capacitance behavior is found in both experimental and numerical results.

Experimental Results

The original version of this paper is available on https://www.scientific.net/KEM.1022.9.pdf

Capacitance is measured on commercially available planar SiC MOSFETs, as shown in Fig. 1. The excitation signal consisting of a DC voltage ranging from -10 V to 10 V with a superimposed AC small signal, Fig. 1ii, is applied on the Gate of the device under test. A fix DC bias, Fig. 1iii is applied on the Drain, while the Source is connected to ground. The Gate capacitance measured when the Drain is biased with fix positive values is presented in Fig. 2. Capacitance has classical behavior, i.e. the case when (dotted line), in the accumulation and depletion region. In the inversion region the situation drastically changes when . A sharp peak arises, and its height is higher as VDS increases. The experimental curves obtained when a positive Drain voltage is applied show a non-negligible peak centered at a voltage close to the threshold voltage. The arising peak appears more prominent as the applied Drain voltage increases. In previous works, the peak shape was associated to traps in the channel region [22] under the interface. The experimental data collected when the applied Drain voltage is negative are presented in Fig. 3 and Fig. 4. Such curves exhibit a different behavior from the previous case. These capacitances show a sudden decrease between the depletion and inversion region, highlighted region in the mentioned figures. The capacitance reaches its minimum for a Gate voltage which is decreasing with higher negative Drain bias. After such behavior, the capacitance increases, showing a peak in the inversion region.

[picture]

Fig. 1. i) Experimental setup; ii) Gate imposed voltage; iii) Drain applied voltage.

Fig. 1. i) Experimental setup; ii) Gate imposed voltage; iii) Drain applied voltage.

[picture]

Fig. 2 Experimental C-V curves obtained from a commercial device with positive Vds.

Fig. 2. Experimental C-V curves obtained from a commercial device with positive Vds.

[picture]

Fig. 4 Experimental curves obtained from a commercial device with negative Vds.

Fig. 4. Experimental curves obtained from a commercial device with negative Vds.

[picture]

Fig. 3 Experimental C-V curves obtained from a commercial device with negative .

Fig. 3. Experimental C-V curves obtained from a commercial device with negative .

[picture]

Fig. 5. Sketch of the TCAD structure.

Fig. 5. Sketch of the TCAD structure.

Numerical Setup

The original version of this paper is available on https://www.scientific.net/KEM.1022.9.pdf

A numerical framework has been developed in Sentaurus TCAD tool by Synopsys. The structure under test is presented in Fig. 5. The performed analysis consists in an AC small signal analysis which allows to investigate the capacitance behavior [23]. Numerical results obtained by considering both negative and positive Drain voltages are reported in Fig. 6. More in detail, the values considered for Vds range from 1 V to -1 V in steps of 0.1 V . The Gate voltage has been swept from -10 V to 10 V . The AC superimposed signal has been chosen with a magnitude of 100 mV and a frequency of 100 kHz . The presented curves show similar trends to the experimental collected data. For positive Drain voltage, the capacitance peak is higher as the voltage increases, while the curves obtained with negative Drain voltage exhibit a decrease after which the behavior starts to increase again. Also, referring to the numerical results in the case of negative Drain bias, the capacitance shows a minimum at a lower Gate voltage as negative Drain voltage increases. The dependence of capacitance from interface traps when Drain is negatively biased has also been considered. More in detail a uniform traps distribution along the interface has been described. In the first case only acceptors traps have been considered. The capacitance trend obtained is presented in Fig. 7, for a Drain voltage . Acceptors modify the capacitance behavior in the inversion region and, more in detail, the capacitance decreases more as traps concentration increases. The influence of donor traps has also been investigated. Numerical capacitance trends are shown on Fig. 8 for the case . Those results show as donors modify the right part (i.e. the accumulation and depletion regions) of the capacitance curve.

[picture]

Fig. 6 Numerical C-V curves obtained with negative and positive .

Fig. 6. Numerical C-V curves obtained with negative and positive .

[picture]

Fig. 7. Numerical C-V curves obtained with a trap distribution of acceptors.

Fig. 7. Numerical C-V curves obtained with a trap distribution of acceptors.

[picture]

Fig. 8. Numerical C-V curves obtained with a trap distribution of donors.

Fig. 8. Numerical C-V curves obtained with a trap distribution of donors.

Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1022.9.pdf

In this work, we exploited a non-classical C-V measurement with different types of Drain biasing. More in detail, Gate capacitance is measured when a fix bias is imposed on the Drain. The Drain voltage imposed is considered both positive and negative. The resulting curves exhibit a sharp peak near the threshold voltage in either case. Experimental data are supported by numerical analysis performed in Sentaurus TCAD. Numerical results have shown similar trends to those obtained in experiments. Numerical analysis has also shown how capacitance curve measured with negative biased Drain modifies when a distribution of acceptors/donors traps is described at interface.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.9.pdf

B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

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Lancellotti, L., Lisi, N., Veneri, P. D., Bobeico, E., Matacena, I., & Guerriero, P. (2019, July). Graphene-on-Silicon solar cells with graphite contacts. In 2019 International Conference on Clean Electrical Power (ICCEP) (pp. 199-203). IEEE.

Gobbo, C., Di Palma, V., Trifiletti, V., Malerba, C., Valentini, M., Matacena, I., ... & Tseberlidis, G. (2023). Effect of the interface on the charge extraction in Cd -free kesterite solar cells. Energies, 16(10), 4137.

Sonnet, A. M., Hinkle, C.L., Heh, D., Bersuker, G., & Vogel, E.M. (2010). Impact of semiconductor and interface-state capacitance on metal/high-k/GaAs capacitance-voltage characteristics. IEEE transactions on electron devices, 57(10), 2599-2606.

Lancellotti, L., Bobeico, E., Della Noce, M., Veneri, P. D., & Matacena, I. (2018, June). Work function determination of transparent contact for a: -Si heterojunction solar cells. In 2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC/I&CPS Europe) (pp. 1-5). IEEE.

Matacena, I., Guerriero, P., Lancellotti, L., Alfano, B., De Maria, A., La Ferrara, V., ... & Daliento, S. (2023). Impedance spectroscopy analysis of perovskite solar cell stability. Energies, 16(13), 4951.

Westerhoff, U., Kurbach, K., Lienesch, F., & Kurrat, M. (2016). Analysis of lithium-ion battery models based on electrochemical impedance spectroscopy. Energy Technology, 4(12), 16201630.

Matacena, I., Lancellotti, L., Daliento, S., Alfano, B., De Maria, A., La Ferrara, V., ... & Guerriero, P. (2023). Impedance Spectroscopy of Perovskite Solar Cells With SnO 2 Embedding Graphene Nanoplatelets. IEEE Journal of Photovoltaics.

Turut, A. (2020). On current-voltage and capacitance-voltage characteristics of metalsemiconductor contacts. Turkish Journal of Physics, 44(4), 302-347.

Matacena, I., et al. "Capacitance-Voltage Investigation of Encapsulated Graphene/Silicon Solar Cells." IEEE Transactions on Electron Devices (2023).

Gaberšček, M. (2022). Impedance spectroscopy of battery cells: Theory versus experiment. Current Opinion in Electrochemistry, 32, 100917

Chang, Yao-Wen, et al. "Charge-based capacitance measurement for bias-dependent capacitance." IEEE Electron Device Letters 27.5 (2006): 390-392.

Almora, Osbel, et al. "On Mott-Schottky analysis interpretation of capacitance measurements in organometal perovskite solar cells." Applied Physics Letters 109.17 (2016).

Gobbo, Carla, et al. "Effect of the interface on the charge extraction in Cd -free kesterite solar cells." Energies 16.10 (2023): 4137.

Matacena, Ilaria, et al. "Forward bias capacitance investigation as a powerful tool to monitor graphene/silicon interfaces." Solar Energy 226 (2021): 1-8.

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Schroder, D.K. Semiconductor Material and Device Characterization, 3rd ed.; Wiley: Hoboken, NJ, USA, 2006.

Hu, Chenming Calvin. "Modern Semiconductor Devices for Integrated Circuits." Part I: Electrons and holes in a semiconductor (2011).

Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, S. Daliento, & A. Castellazzi, (2022). SiC MOSFET CV Characteristics with Positive Biased Drain. In Materials Science Forum (Vol. 1062, pp. 653-657). Trans Tech Publications Ltd

L. Maresca et al. Influence of the MOSFET Interface Traps Distribution on C V Measurements Evaluated by TCAD Simulations. IEEE Journal of Emerging and Selected Topics in Power Electronics 9.2 (2019): 2171-2179.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2022, June). Experimental Analysis of CV and IV Curves Hysteresis in SiC MOSFETs. In Materials Science Forum (Vol. 1062, pp. 669-675). Trans Tech Publications Ltd.

Matacena, Ilaria, et al. "SiC MOSFET CV Curves Analysis with Floating Drain Configuration." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

Matacena, Ilaria, et al. "Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Wei, Jiaxing, et al. "Interfacial damage extraction method for SiC power MOSFETs based on CV characteristics." 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). IEEE, 2017.

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Jouha, Wadia, et al. "Physical study of SiC power MOSFETs towards HTRB stress based on CV characteristics." IEEE Transactions on Device and Materials Reliability 20.3 (2020): 506511.

Matacena, Ilaria, et al. "SiC MOSFETs Capacitance study." e-Prime-Advances in Electrical Engineering, Electronics and Energy (2023): 100251.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2023, July). SiC MOSFETs Biased CV Curves: A Temperature Investigation. In Materials Science Forum (Vol. 1091, pp. 31-36). Trans Tech Publications Ltd.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2024). Frequency Investigation of SiC MOSFETs CV Curves with Biased Drain. Solid State Phenomena, 360, 145-149.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2022, July). SiC/SiO 2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain. In 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp. 1-5). IEEE.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 15-19

doi: 10.4028/p-UdUGq3

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-14

Accepted:
2025-08-14

Online:
2025-09-08

TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

Wolfspeed, 4600 Silicon Drive, Durham, NC 27703, USA

Hemant.Dixit@Wolfspeed.com, daniel.lichtenwalner@wolfspeed.com, Andreas.Scholze@Wolfspeed.com, dsei-hyung.ryu@wolfspeed.com,

Keywords: TCAD, Mobility model, a-face, lateral MOSFET.

Abstract

Channel mobility is one of the most critical parameters in based Power MOSFETs and contributes a significant fraction of device on-state resistance. Experimentally, it has been shown that the a-face channel mobility is much higher compared to the Si-face, making a-face a very attractive option for a wide range of applications in the power electronics market. However, modelling of the a-face channel mobility using Technology Computer Aided Design tools is not well established due to the complex nature of channel mobility due to a variety of scattering mechanisms involved. In this paper, we present a well calibrated a-face channel mobility model that shows an excellent match with the available experimental data and further provides critical insights into the anisotropic nature of channel mobility in 4H-SiC MOSFET structures.

Hemant Dixit, Daniel J. Lichtenwalner, Andreas Scholzeand Sei-Hyung Ryud

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

[picture]

Fig. 1. a) Hexagonal crystal structure of showing various faces b) Schematic of lateral MOSFET created using Si-face orientation c) Schematic of lateral MOSFET created using a-face orientation

Fig. 1. a) Hexagonal crystal structure of showing various faces b) Schematic of lateral MOSFET created using Si-face orientation c) Schematic of lateral MOSFET created using a-face orientation

Channel mobility is one of the most critical parameters in based Power MOSFETs and contributes a significant fraction of device on-state resistance (RON). has a hexagonal crystal structure and the bulk mobility is anisotropic, larger in the (0001) direction (parallel to the a-face or m -face), and lower perpendicular to that (along Si-face directions) as illustrated in Figure 1. Such an anisotropic nature is also observed in channel mobilities when channels are formed along these crystallographic orientations. Experimentally, it has been shown that the a-face channel mobility is much higher compared to the Si-face, making a-face a very attractive option for a wide range of
applications in the power electronics market . However, to the best of our knowledge, Technology Computer Aided Design (TCAD) modelling of the a-face channel mobility is not well established in the literature [ 3,4 ]. Thus, here we present a well calibrated a-face channel mobility model that shows an excellent match with the available experimental data and further provides critical insights into the anisotropic nature of channel mobility in 4H-SiC MOSFET structures.

Experimental Details

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

a-face lateral MOSFETs used in this paper are special test structures which are fabricated on p-type epilayers, grown on a-face cut substrates [1]. P-type doped epitaxial layers, having well concentrations of about , are grown on the a-face cut substrate. Gate oxide was deposited with a CVD process, followed by nitric oxide (NO) passivation anneals. Poly-Si was deposited and patterned for the gate electrodes, with ohmic contacts formed to implanted source and drain regions. These lateral MOSFETs are all long-channel devices ( ) to ensure accurate field-effect (FE) mobility extraction. Temperature dependent drain current (Id) versus gate bias (Vg) characteristics are shown in Fig. 2a). The channel FE mobilities as a function of temperature for a-face lateral MOSFETs is calculated using the derivatives of the Id-Vg characteristics and are shown in Fig. 2b). Next, we also plotted the temperature dependence of the peak channel mobility as shown in Fig. 2c) and observed opposite trends for Si-face and a-face. For Si-face, the peak channel mobility increases with increasing temperature whereas for the a-face a decrease in peak channel mobility with increasing temperature.

[picture]

Fig. 2. a) Id-Vg measurement on Si-face lateral MOSFET b) Extracted field-effect channel mobilities for the Si-face and a-face showing strong enhancement in peak mobility for similar P -well concentrations c) Corresponding temperature dependence of the peak value of channel mobility for the Si-face and a-face.

Fig. 2. a) Id-Vg measurement on Si-face lateral MOSFET b) Extracted field-effect channel mobilities for the Si-face and a-face showing strong enhancement in peak mobility for similar P -well concentrations c) Corresponding temperature dependence of the peak value of channel mobility for the Si-face and a-face.

Channel Mobility and it's Components

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

Modelling channel mobility is a complex task due to a variety of scattering mechanisms that compete and dictate the total channel mobility along with its temperature dependence. The standard channel mobility model consists of bulk, Surface Roughness (SR), Surface Phonon (SP), and Remote Coulomb Scattering (RCS) terms combined using Matthiessen's rule. This is illustrated in Figure 3. By reviewing literature, we observed that the standard mobility models developed for Silicon technology perform poorly in describing the physics of SiC MOS interface. As shown by earlier literature and our previous work on modelling Si-face channel mobility term [3,4,6], it is not possible to describe the temperature and P -well surface concentration dependence of channel mobility using semi-empirical parameters developed for the Silicon technology. Thus, a straightforward adoption of the available mobility models misses on critical customizations that are necessary to describe the
unique material properties of crystal. In this work, we take on this challenge and have developed a new set of semi-empirical parameters for the -oxide interface. Here we start with the approach originally proposed by C. Lombardi et. Al. [6] and later significantly revise the proposed semi-empirical formulation to describe experimental data. Our TCAD simulations are performed using the Silvaco Victory Process and Victory Device tools. The interface trap density is estimated using high-low C-V measurements and was used as input for the RCS portion. An extensive calibration of SR, SP and RCS model terms was performed to match the experimental data for measured a-face channel mobility.

[picture]

Fig. 3. Schematic illustration of the channel mobility components: the electrons flowing across source to drain experience three primary scattering mechanisms and these are termed as Remote Coulomb Scattering (RCS) due to the charges present at the oxide interface, Surface Phonon (SP) due to atomic rearrangement of the atoms at the interface, and the Surface Roughness (SR) term that represent reduction of the electron mean free path due to geometrical roughness at the interface.

Fig. 3. Schematic illustration of the channel mobility components: the electrons flowing across source to drain experience three primary scattering mechanisms and these are termed as Remote Coulomb Scattering (RCS) due to the charges present at the oxide interface, Surface Phonon (SP) due to atomic rearrangement of the atoms at the interface, and the Surface Roughness (SR) term that represent reduction of the electron mean free path due to geometrical roughness at the interface.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

We tested our revised channel mobility model on channel mobility curves obtained specially created lateral MOSFET test structures having a-face and Si-face orientations. The TCAD predicted and experimentally measured temperature dependence of channel mobility curves is shown in Figure 4. As evident from Figure 4 a) and 4 b), we obtain an excellent match with the measured mobility curves across multiple temperatures (ranging between ). The Si-face lateral MOSFET has P-well surface concentration of about , whereas P-well surface concentration for a-face lateral MOSFET is about . From the comparison of the simulated and measured channel mobility curves, our revised a-face channel mobility model shows predictive capability across multiple lattice temperatures.

[picture]

Fig. 4. a) TCAD predictions for a-face channel mobility and its temperature dependence - the markers represent the measurement, and the lines show TCAD result b) TCAD predictions for Si-face channel mobility and its temperature dependence.

Fig. 4. a) TCAD predictions for a-face channel mobility and its temperature dependence - the markers represent the measurement, and the lines show TCAD result b) TCAD predictions for Si-face channel mobility and its temperature dependence.

Analysis of Channel Mobility Components

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

Next, we perform a component-wise analysis of total channel mobility that unravels the complex but interesting interplay among a variety of scattering mechanisms. Figure 5 a) shows the mobility components for the Si -face with a P -well concentration of towards illustration. Here, following the Matthiessen's rule, we observe that the total channel mobility is determined by the RCS and SP terms which are predominant scattering mechanisms. Further, at very high gate biases the channel mobility is limited by the SP term alone. The mobility components for a-face and Si-face are shown in Figure 5 b) and 5 c), respectively. Note, here we have excluded the total channel mobility in this graph for adding clarity - but since these components are added using the Matthiessen's rule, the lowest value is dominant contributor towards the total channel mobility as a function of applied E-field. The solid lines in this plot represent the mobility components at room temperature and the dashed lines represent the components at . First, we observe that our revised channel model predicts that the peak value of channel mobility is determined by the cross-over between the RCS and SP terms across the temperature range considered (between ). Next the peak channel mobility is determined by the cross-over between the RCS and SP terms which are the lowest components as a function of applied E-field/gate bias. The higher density of interface traps ( ) present at the Si-face results in stronger Coulomb scattering and thus limiting RCS component. Similarly, for Si-face, the stronger surface phonon scattering also limits the peak channel mobility. In contrast to these observations, for a-face, we observe that the RCS mobility is much higher due to lower interface trap density ( ) along the a-face orientation. Furthermore, the SP limited mobility is also higher for a-face compared to Si-face - which explains the enhancement of peak channel mobility going from the Si-face to a-face. The temperature dependence of the peak channel mobility can be understood as follows. For both the Si-face and a-face the SP mobility is reduced with increasing temperature. However, for the Si-face the RCS slope at is strongly enhanced and the crossover indicates higher peak channel mobility at compared to . Whereas, for the a-face, the RCS mobility is weakly enhanced at compared to and the cross-over is dominated by the reduction of SP mobility with increasing temperatures.

[picture]

Fig. 5. a) Mobility components for Si -face at - the peak value of the total channel mobility is determined by the cross-over of the RCS and SP terms b) Mobility components for Si-face at (solid lines) and (dashed lines) c) Mobility components for a-face at (solid lines) and (dashed lines) - note the total mobility term is not shown in the graph for clarity.

Fig. 5. a) Mobility components for Si -face at - the peak value of the total channel mobility is determined by the cross-over of the RCS and SP terms b) Mobility components for Si-face at (solid lines) and (dashed lines) c) Mobility components for a-face at (solid lines) and (dashed lines) - note the total mobility term is not shown in the graph for clarity.

Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

In this paper, we presented TCAD modelling of the channel mobility for lateral MOSFET test structures created using the Si -face and a-face orientations. A revision of standard mobility model is necessary to capture the unique material properties of crystal. We developed channel mobility models for both the Si-face and a-face orientations. The TCAD results are in excellent agreement with measured data and successfully predict the channel mobility curve along with their temperature dependence. The mobility component analysis further reveals the complex interplay among the various scattering mechanisms that are responsible for determining the total channel mobility. In conclusion, our revised channel mobility models allow us to predict the anisotropic nature of channel mobility and thereby perform predictive TCAD simulations of MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.15.pdf

Lichtenwalner, Daniel J., et al. "Comparison of channel mobility and oxide properties of MOSFET devices on Si-face (0001) and A-face (11-20) ." MRS Online Proceedings Library (OPL) 1693 (2014): mrss14-1693.

Palmour, John W., et al. "Silicon carbide power MOSFETs: Breakthrough performance from 900 V up to 15 kV ." 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014.

Noguchi, M., et al. "Determination of intrinsic phonon-limited mobility and carrier transport property extraction of MOSFETs." 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017.

Uhnevionak V., et al. "Comprehensive study of the electron scattering mechanisms in 4H-SiC MOSFETs." IEEE TED 62.8 (2015): 2562.

Dixit, Hemant et al. "Temperature Dependent Mobility Model for Predictive TCAD Simulations of 4H-SiC", ICSCRM 2022.

Dixit, Hemant et al. "Revised Channel Mobility Model for Predictive TCAD Simulations of 4H-SiC MOSFETs", ICSCRM 2023.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 21-28

doi: 10.4028/p-Fg79mF

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-03-21

Accepted:
2025-03-21

Online:
2025-09-08

On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

The original version of this paper is available on https://www.scientific.net/KEM.1022.21.pdf

Arne Benjamin Renz , Yifan Jiang , P.M. Gammon , Erfan Bashar and Jiankang Bu

University of Warwick, School of Engineering, Coventry, UK

PGC Consultancy Ltd, Stratford-upon-Avon, UK

Ideal Power Inc, Austin, TX, USA

Arne.Renz@warwick.ac.uk , Yifan.jiang@idealpower.com , P.M.Gammon@warwick.ac.uk, E.Bashar.1@warwick.ac.uk , Jiankang.Bu@idealpower.com

Abstract

A bidirectional field-effect transistor (FETs), known as a BTRAN , was designed, fabricated and characterized on silicon carbide ( SiC ) for the first time. After grinding to original substrate, atomic force microscopy revealed grinding marks and an increase of surface roughness to a rms value of 7.812 nm ( scan area), but these were suitable for further device processing. A lifetime enhancement oxidation process carried out on both sides of the drift region at for 4 hrs in dilute oxygen ( ) enhanced the average carrier lifetime from to . After device fabrication, functionality was proven both on-die and on a custom-made PCB design that enabled access to all four terminals (topside and bottomside) in the on-state and offstate. Off-state measurements revealed a breakdown voltage exceeding 7 kV . In summary, these encouraging results, with necessary improvements of contact resistivity, will build the foundation for the second generation of SiC BTRAN devices.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.21.pdf

Power electronics are a key enabling technology in the process towards a fully electrified society. Modern power conversion is integral in delivering efficient electric vehicles (EVs) and their fast charging stations, advanced motor drives and the integration of renewable energy into a modern grid. With an EV market share of targeted by the US Government and the fact that about of all electricity is used to power and drive electric motors, it becomes evident that efficiency of power electronics systems will be at the center of any policy that wants to steer society towards a more sustainable energy economy.

In these applications, well-developed converter topologies are key. Ideally, these would contain semiconductor switches that have both excellent blocking capabilities in both directions and bidirectional current conduction in the on-state [1]. However, none of the conventional semiconductor switches, e.g., insulated-gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), can provide these functionalities alone, such that multiple discrete device topologies are typically deployed. As an example, an inverse-series connection of two silicon ( Si ) MOSFETs achieves switching functionality in two directions, but the total on-resistance (Ron) is doubled compared to a single device. To circumvent this, a second arrangement needs to be connected in parallel. This means that, for the realization of bidirectional switching capability, using common power semiconductors results in a fourfold increase in chip area and cost. The introduction of monolithic bidirectional switches (MBDSs) with a single shared drift region for blocking either voltage polarity, and two gates, means that these converter topologies need to reevaluated.

The research activities on MBDS devices can be traced back to the early 2000s, with early activities focusing on IGBTs that were reverse-blocking [2]. Within a few years, multiple companies started to investigate MBDSs based on gallium nitride (GaN) high-electron mobility transistors (HEMTs). These devices were typically rated at around 600 V , with resistances reaching .

In silicon carbide (SiC), MBDS device development is still at a very early stage. Research activities have so far resulted in the successful fabrication of a monolithic bidirectional IGBT, where demonstrator devices have successfully blocked up to 7 kV [3]. However, processing requires a nonstandard, processing methods, including grinding away the original wafer to access the backside of the drift region, double sided lifetime enhancement, and double-sided photolithography including backside alignment. When packaged, novel cooling solutions as both sides of the wafer feature intricate structures, such as gates, base and emitter regions.

This work aims to demonstrate a SiC BTRAN device concept that was originally developed for Si processing [4]. This features a field-effect transistor (FET) on each side of the wafer with a shared collector region (B-TRAN ). Vertical Si devices have achieved a blocking voltage of and were able to support pulsed currents of up to . In this investigation, we aim to transfer this concept to . Firstly, vertical PiN diodes and lateral devices were simulated, fabricated and characterized on both the C -face and Si -face , as required to produce a TRAN . The carrier lifetime of the thick drift region was then optimized to enable sufficient carrier diffusion for conductivity modulation.

Experimental

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Devices were fabricated on a 100 mm diameter, thick -substrate, onto which was grown a thick n-type unintentionally doped ( ) epitaxial layer. After initial alignment mark formation between topside and bottomside, the samples were flipped to remove the -substrate by means of grinding. The scanning electron microscope (SEM) image in Fig. 2 shows the resulting cross-section of the wafer. High-temperature oxidation was then carried out at in a dilute oxygen ambient ( ) on both the Si -face and C -face to improve the carrier lifetime,

[picture]

Fig.1. Cross-sectional representation of the JFET structures (left and middle) and the full BTRAN device (right).

Fig.1. Cross-sectional representation of the JFET structures (left and middle) and the full BTRAN device (right).

[picture]

Fig.1. Cross-sectional representation of the JFET structures (left and middle) and the full BTRAN device (right).

Fig.1. Cross-sectional representation of the JFET structures (left and middle) and the full BTRAN device (right).

[picture]

Fig. 2. (Left) The drift region thickness post-grinding, measured by cross-sectional SEM imaging. (Right) Optical microscopy image of the finished one-sided BTRAN device, fabricated on the Cface after substrate removal.

Fig. 2. (Left) The drift region thickness post-grinding, measured by cross-sectional SEM imaging. (Right) Optical microscopy image of the finished one-sided BTRAN device, fabricated on the Cface after substrate removal.

similar to [5]. - implants and -implants were then carried out on both the Si-face and C -face to enable gate, source (on the BTRAN) and cathode and anode ohmic contact formation (on the PiN diodes). A thick passivation layer was then deposited on both samples by means of lowpressure chemical vapour deposition (LPCVD), using tetraethyl orthosilicate (TEOS) as Si precursor before a thick aluminium (Al) pad metal was deposited to aid with device testing and wire bonding. The final device structure can be seen in Fig. 1, with microscopy images in Fig. 2. Atomic force microscopy (AFM) measurements were carried out on a Bruker Icon AFM in peakforce tapping mode to extract surface roughness and quantify any possible large wafer bow post-grinding.

The enhancement throughout the drift thickness is diffusion limited due to the low diffusion coefficients of carbon and oxygen in SiC. Common carrier lifetime measurement techniques such as microwave-detected photoconductance decay ( -PCD) probe the near-surface region of the epilayer, give an indication of carrier lifetime. Time transient data was measured by -photoconductive decay (PCD), which has a 355 nm ultraviolet (UV) laser source. The effective carrier lifetime was assessed prior to and after lifetime enhancement in a custom Freiberg Instruments spotMDP setup.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1022.21.pdf

Low surface quality post-grinding is required for the success of the device fabrication. An extensive AFM investigation was conducted once the samples had their substrates removed and prior to further processing. An overview of the extracted root mean square (RMS) values can be found in Table 1. Representative images of the top side and bottom side can be found in Fig. 3 below. A full wafer post-grinding is depicted in Fig. 4 (left), too.

Table I. Extracted surface roughness parameters post-substrate removal. All measurements were done at room temperature.

[picture]

Fig. 3. (Left) Image of a representative scan of the (left) frontside, which did not undergo the processing and achieved a rms surface roughness value and (right) backside, which was grinded, showing grinding marks post-processing.

Fig. 3. (Left) Image of a representative scan of the (left) frontside, which did not undergo the processing and achieved a rms surface roughness value and (right) backside, which was grinded, showing grinding marks post-processing.

The surface quality of the thick, as-grown, epitaxial layer can be seen when observing the extracted rms values from the top. Here, even surface roughness values that are extracted from a scan area are significantly lower than 1 nm , with values averaging 0.55 nm . No obvious further surface modifications/decorations were visible during any topside measurement, with all measurements averaging tightly at around 0.5 nm . After the substrate was then fully removed by grinding, the surface showed grinding marks throughout, with surface roughness values averaging 10 times higher at 5.96 nm . With all contacts in the BTRAN devices being ohmic, fabrication was then continued.

[picture]

Fig. 4. (Left) Image of a full four inch wafer post-grinding, with bright spots representing triangular defects in the epilayer and right) u-PCD measurements before and after hightemperature oxidation ( ), with 400 measurements being taken at room temperature per dataset.

Fig. 4. (Left) Image of a full four inch wafer post-grinding, with bright spots representing triangular defects in the epilayer and right) u-PCD measurements before and after hightemperature oxidation ( ), with 400 measurements being taken at room temperature per dataset.

[picture]

Fig.5. Gate-source forward (left) and reverse (right) characteristics of diodes fabricated on Cand Si-face.

Fig.5. Gate-source forward (left) and reverse (right) characteristics of diodes fabricated on Cand Si-face.

[picture]

Fig.6. On state of vertical PiN diodes fabricated on both the C-and Si-face.

Fig.6. On state of vertical PiN diodes fabricated on both the C-and Si-face.

After the grinding process, an analysis of the transient carrier lifetime on the Si - and C -face was carried out before and after the lifetime enhancement oxidation process. The results are shown in Fig. 4 (b), where 400 spot measurements were taken at room temperature across the wafer. More details about the 4 hour lifetime enhancement procedure can be found in [5]. Prior to the lifetime enhancement treatment, the effective carrier lifetime on the thinned wafer averaged about , both on the Si- and the C-face. After the thermal oxidation process, the lifetime was increased to approximately , which will enhance conductivity modulation in the thick drift region.

[picture]

Fig. 7. (Left) Final chip on PCB for bi-directional switching of the BTRAN , allowing for the static characterization of multiple devices on that chip. Individual devices were then wire bonded to contact pads that are located outside of this chip. (Right) blocking voltage of a single tested BTRAN device, showing no visible signs of leakage up to 7 kV .

Fig. 7. (Left) Final chip on PCB for bi-directional switching of the BTRAN , allowing for the static characterization of multiple devices on that chip. Individual devices were then wire bonded to contact pads that are located outside of this chip. (Right) blocking voltage of a single tested BTRAN device, showing no visible signs of leakage up to 7 kV .

The active area design comprised a trench etch into the gate area, into which a -region of 200 nm was implanted.

After fabrication, the lateral P -gate to N -source breakdown in the devices was measured on wafer, depicted in Fig. 5, right, where the breakdown exceeds 100 V , outperforming TCAD simulation results. Representative on-state results for the lateral JFETs (Fig. 5, left) and vertical PiN diodes (Fig. 6) show the functionality of the fabricated structures.

Having proven the general functionality of the fabricated structures on-die, wafers were laser cut and chips were then soldered onto custom-made PCBs. These were designed to allow access to terminals on both the back side and the top side of the same chip. An example of a chip that had been soldered onto one of these PCBs can be seen in Fig. 7 (left) below. Terminals were bonded to terminal pads by means of wire bonding using approx. aluminium wire. Once this was done, we were able to measure the blocking voltage (S1-G2) between the topside source and bottom side gate, all the way up to 7 kV . To prevent arcing, fluorinert gel was applied directly before the leakage measurements were carried out. A representative device with poor leakage performance is shown in Fig. 7 (right). Some devices managed to show excellent breakdown performance, as demonstrated in the same figure.. For leakage measurements, all other terminals were left floating.
The same configuration also allowed for the on-state measurement of devices, which can be seen in Fig. 8 (left) and the on-state voltage drop in Fig. 8 (right).

[picture]

Fig. 8. (Left) On-state of the observed SiC BTRAN and (Right) on-state voltage drop on individual devices..

Fig. 8. (Left) On-state of the observed SiC BTRAN and (Right) on-state voltage drop on individual devices..

The on-state (G1-S1) was then measured using a B1505 A probe station with a high-current extender (bottom left). The G1-S1 diode performance, with forward current up to 100 mA , could be observed on Fig. 8(left). The other terminals were left floating. A specific contact resistivity of the p-type ohmic contact of and of the n-type ohmic contact were extracted from TLM measurements and can be one source of the relatively high resistance that can be observed in the on-state of the PiN diodes, as well as the BTRAN . In Fig. 8 (right), the on-state voltage drop between devices can be seen, confirming this trend. Here, a DC voltage of 30 V was applied across the topside of the base, for current injection through the base. The voltage was then swept between the topside source (S1) and gate on the bottom side (G2).

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1022.21.pdf

In this investigation, we successfully simulated, designed, fabricated and characterized the first fully functional silicon carbide BTRAN device. As part of the challenges in the fabrication process, we demonstrated, that, after substrate removal, the backside of the wafer showed grinding marks and an increase in surface roughness up to 7.812 nm , when investigated on a by means of atomic force microscopy.

To help conductivity modulate the device, a carrier lifetime enhancement investigation was conducted, where we oxidized the samples in a high-temperature furnace at for 4 hrs in dilute oxygen ambient ( ). This raised the lifetime relatively uniformly from (pretreatment) to approximately (post-enhancement), both on the C - and Si-face of a full 4 " wafer.

The fully fabricated structures were then measured on-die, where on-states showed the full functionality of one-sided structures laterally, although the conduction response suffered heavily from high specific contact resistivities, averaging and on TLM structures for p -type and n -type ohmic contacts, respectively. Selected chips were then soldered on a custom-made PCB design, allowing the static characterization of the full BTRAN devices by enabling access to both contacts on the topside and backside of the chip. Here, on-states of the full device structures showed general functionality, although suffering from high specific contact resistivities. A promising performance off-state was demonstrated, blocking more than 7 kV . In summary, these encouraging results, with necessary improvements of contact resistivity, will build the foundation for a second generation of BTRAN devices to full commercialization.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.21.pdf

Huber,J, and Kolar. J.W., "Monolithic Bidirectional Power Transistors", in IEEE Power Electronics Magazine, Volume. 10, 2023.

S. Chowdhury et al., "Operating principles, design considerations, and experimental characteristics of high-voltage bidirectional IGBTs", in IEEE Trans. Electron Devices, vol.64, pp. 888-896, 2017.

F. Vollmaier et al., "Performance evaluation of future T-type PFC rectifier and inverter systems with monolithic bidirectional 600 V GaN switches", in Proc. IEEE Energy Convers. Congr. Expo. (ECCE), pp. 5297-5304, 2021.

M. Dong et al., "BTRAN Optimization and Performance Characterization.", in 2023 IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 1835-1839, 2023.

T. Kimoto et al., "Carrier lifetime and breakdown phenomena in SiC power device material.", in Journal of Physics D: Applied Physics, vol. 51, pp. 363001, 2018.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-evaluation-and-device-design/978-3-0364-1914-5

Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 29-36

doi: 10.4028/p-Y4W1rg

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-03-02

Accepted:
2025-03-06

Online:
2025-09-08

The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

Yisi Liu , Saeed Jahdi , Mana Hosseinzadehlish , lan Laird , Phil Mellor , Konstantinos Floros and Ingo Lüdtke

University of Bristol, Bristol, BS8 1UB, United Kingdom

Compound Semiconductor Applications Catapult, Newport, NP10 8BE, United Kingdom

yisi.liu@bristol.ac.uk, saeed.jahdi@bristol.ac.uk, m.hosseinzadeh@bristol.ac.uk, eian.laird@bristol.ac.uk, ep.h.mellor@bristol.ac.uk, konstantinos.floros@csa.catapult.org.uk, gingo.ludtke@csa.catapult.org.uk

Abstract

In this paper, the performance in quadrant operation of and generation SiC power MOSFETs have been evaluated. These are the Gen-3 1.2 kV & 18 A Planar SiC MOSFET, Gen-3 1.2 kV & 19 A Asymmetrical Trench SiC MOSFET, Gen-4 1.2 kV & 26 A Symmetrical DoubleTrench SiC MOSFET and Gen-4 1.2 kV & 19 A Trench-Assisted Planar SiC MOSFET. Further, the transients of early-stage degradation development are investigated by conducting continuous stress current thorough body diode of the aforementioned devices to explore the extent of degradation in the body diodes of SiC MOSFETs. These devices are compared to provide a better understanding of the impact of different structures.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

The evolution of power electronics has been recently entangled with the developments of silicon carbide ( SiC ) MOSFET technologies due to its high breakdown electric field and thermal conductivity . Over the years, SiC MOSFET technology has undergone several generational improvements. The newest generation SiC MOSFETs have delivered improvements in critical performance metrics, i.e. the switching rates and on-state resistance due to the novel design structures employed such as aggressive cell pitching and substrate thinning. The cross-sectional schematics of both the Generation and Generation devices are shown in Fig. 1. The Fig. 1(a) and (b) show the typical structure of Gen-3 SiC Planar and Asymmetrical Trench MOSFETs, while Fig. 1(c) and (d) show the newer SiC Symmetrical Double-Trench and Trench-Assisted Planar MOSFETs. The Gate-Trench structured SiC MOSFETs typically suffer more from gate oxide reliability issues because of the high electric field at the bottom of the gate trench [5]. To improve this, the P-wells in Gen-4 design are deeper, as shown in Fig. 1(c), which further distances the high electric field from the gate, providing better protection. These improvements provide better gate oxide reliability and higher efficiency in the first quadrant operation.

MOSFETs also allow the quadrant channel conduction while the body diode is used for freewheeling during the switching dead band. This feature helps prevent voltage spikes, ensuring device protection and enhancing circuit reliability [6-9]. There are some questions in terms of the performance of the body diode of recent devices though. For example, body diode of the Symmetrical Double-Trench MOSFET could have worse reverse recovery because of the deeper P-wells, which results in additional carriers that must be extracted during the turn-off process. This is also unclear in case of the SiC Trench-Assisted Planar MOSFETs [10]. It is also unclear whether different structures could mitigate the severity of bipolar degradation. To address this, double pulse tests and continuous DC current stress tests are conducted on both and Gen devices to investigate the impacts of the newly emerged structures to these performance metrics.

[picture]

Fig. 1. The cross-sectional view of the studied SiC MOSFETs: (a) Planar; (b) Asymmetrical Trench; (c) Symmetrical Double-Trench; (d) Trench-Assisted Planar.

Fig. 1. The cross-sectional view of the studied SiC MOSFETs: (a) Planar; (b) Asymmetrical Trench; (c) Symmetrical Double-Trench; (d) Trench-Assisted Planar.

TheQuadrant Operation: Transients & Reverse Recovery

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

Firstly, measurements are performed at a wide range of switching rates using a bespoke double pulse test board on 1.2 kV devices, planar rated at 18 A , Asymmetrical Trench rated at 19 A , Symmetrical Double-Trench rared at 26 A, and Trench-Assisted Planar rated at 19 A. All devices have the same range of on-resistance. The body diode reverse recovery for each device is tested under different switching rates emulated by gate resistances on the switching MOSFET ranging between 10 to in room temperature to enable evaluation of their performance under different switching rates. The trends of reverse recovery at room temperature for gate resistances of is shown in Fig. 2, while the performances of different device technologies are compared with the charges calculated as shown in Fig. 3. The measurements indicate that the Planar SiC MOSFET and Trench-Assistant Planar MOSFET exhibit swift reverse recovery and lower peak reverse recovery currents at room temperature, while the SiC Symmetrical Double-Trench MOSFET show slightly higher peak currents.

As temperature increases, the carrier lifetime extends, resulting in longer reverse recovery times. Different MOSFET structures have different sensitivities to the changes in temperature. The SiC Planar MOSFET and the Trench Assisted Planar MOSFET exhibit very short reverse recovery periods and lowest peak reverse recovery currents at room temperature, while the SiC Symmetrical Double Trench MOSFET shows slightly higher peak currents, and the SiC Asymmetrical Trench MOSFET shows the highest. However, as temperature increases to , and then further followed to , as shown in Fig. 3, the SiC Asymmetrical Trench MOSFET maintains a relatively stable peak reverse recovery current while other devices show significantly deteriorated reverse recovery especially in the case of the SiC Symmetrical Double-Trench MOSFET.

The temperature dependence of the reverse recovery charges of different gate resistances under temperature and are also calculated as shown in Fig. 4. The reverse recovery charges of the Planar and Trench-Assisted Planar are close under different temperatures. The Asymmetrical Trench are less sensitive to the change of temperatures, while the Symmetrical Double-Trench devices are more sensitive to the temperature variations especially at higher temperatures. This indicates the effect of the deepen P-well in the structure which provide more carriers to be removed during the reverse recovery.

The above experimental results highlight the importance of considering both thermal dynamics and device architecture in SiC MOSFET performance. The varying impacts of temperature on different devices emphasize the need for further research.

[picture]

Fig. 2. Reverse recovery trends at room temperature with of and .

Fig. 2. Reverse recovery trends at room temperature with of and .

[picture]

Fig. 3. Reverse recovery charges with temperature from to with of .

Fig. 3. Reverse recovery charges with temperature from to with of .

[picture]

Fig. 4. Reverse recovery charges with temperatures with between 10 to .

Fig. 4. Reverse recovery charges with temperatures with between 10 to .

Evaluation of Degradation

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

Bipolar degradation in a MOSFET's body diode occurs due to the existing Basal Plane Dislocation (BPD) in growth, formed during the device fabrication. BPDs can expand during device operation, especially under high current conditions, leading to Shockley Stacking Faults (SSFs) which will result in higher on-state resistance.

According to [11-14], bipolar degradation can be fully developed even in relatively short time span if under adequate electrothermal stress in converter operation. To investigate the development of bipolar degradation in different structures of SiC power MOSFETs, constant current stress are conducted on the body diode of DUTs for 8 hours with increasing levels of electrothermal stress with the test board shown in Fig. 5. The real-time are logged using the Tektronix MDO34 oscilloscope. The change of indicates the change of the on-state resistance of body diode. It is noted that during the test, the temperatures are controlled by a temperature controller to prevent thermal runaway. All data is collected only after the temperature of MOSFETs reach steady state. During the tests, the temperature of devices are monitored using FLIR E5 thermography camera.

[picture]

Fig. 5. Test set up for analysis of bipolar degradation mechanisms under continuous current stress.

Fig. 5. Test set up for analysis of bipolar degradation mechanisms under continuous current stress.

The logging data of devices under different current stresses of and 8 A are compared in Fig. 6. The difference in large-scale is negligible, given the level of electrothermal stress applied, however, zooming indicate the staring trends of degradation which could cascade if the stress time is further prolonged. It is important to note that the bipolar degradation level and process could vary among the different samples of the same structure and manufacture [13], as it is also dependent on the BPDs that are formed during the fabrication process. More detailed performances of different devices under various current stresses are discussed below.

Firstly, devices are tested under 3 A for 8 hours. Slight increasing trends can be found in Planar, Asymmetrical Trench, and the Trench-Assisted Planar, while the of Symmetrical Double-Trench remains stable throughout. This indicates that under lower current, the development of degradation is slow.

[picture]

Fig. 6. Comparisons under different current stresses: (a) Planar; (b) Asymmetrical Trench; (c) Symmetrical Double-Trench; and (d) Trench-Assisted Planar.

Fig. 6. Comparisons under different current stresses: (a) Planar; (b) Asymmetrical Trench; (c) Symmetrical Double-Trench; and (d) Trench-Assisted Planar.

To further investigate the rate of degradation under different stresses, the continuous current is increased to 6 A. The of the devices are shown in Fig. 7, Fig. 8, Fig. 9 and Fig. 10 together with the IV characteristics. The measured temperatures that was monitored during the tests. A consistently increasing trend occurs at the start of the test for Planar and it keeps increasing gradually for approximately 4 hours, which indicates the gradual development of initial stages of SSFs. After that, remains relatively stable until the test is ceased. The temperature of device is controlled around
. Different from the continuous increase of the Planar, of Asymmetrical Trench remains stable at the first 3 hours with the temperature . Afterwards, it keeps increasing gradually for 4 hours. This indicates a small step change, followed by a stable state. In the Symmetrical Double Trench, it is observed that begins to rise after the temperature reaches and remains steady, which could correspond to the initial expansions of BPD defects. The increasing trend last for 6 hours. More specifically, increasing slope in the first hour is relatively larger and then remains stable for a short period, followed up by a gradual long increasing process. This suggests that even under the same current stress, the development speed of BPDs can vary. As for the Trench-Assisted Planar, there is no obvious increasing trend or abrupt increase while remains relatively stable throughout the test.

The I-V characteristics are compared for before and after the tests. Through local amplification it can be found that the on-state resistances increase slightly. Nevertheless, the difference between fresh and stressed devices are still very small. It must be noted that to prevent the spontaneous turn-on of the device, the gate and source terminals of the device are short-circuited to each other through hardwiring. Nevertheless, as the gate voltage is not negative, the potential role of channel conduction in third quadrant must be observed.

[picture]

Fig. 7. of Planar under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

Fig. 7. of Planar under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

[picture]

Fig. 8. of Asymmetrical Trench under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

Fig. 8. of Asymmetrical Trench under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

[picture]

Fig. 9. of Symmetrical Double Trench under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

Fig. 9. of Symmetrical Double Trench under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

[picture]

Fig. 10. of Trench-Assisted Planar under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

Fig. 10. of Trench-Assisted Planar under continuous DC current stress 6 A and comparisons of I-V characteristics of body diode before and after the test.

The observation in Figures 7 to 10 is just the beginning of any potential degradation, with 6 A current at only 8 hours. To observe actual degradations, both the current and time period of stressing of the device must be increased. This is expected to lead more deviations in the IV.

To promote further electrothermal stress, the current is further increased to 8 A to apply additional stress on the devices and check if the initiation of any BPD defects will change. The temperatures under steady state are shown in Fig. 11 while the logging data are shown in Fig. 12. The outer temperatures of devices are all above while the maximum operating temperature is about for all devices. From the Fig. 12 it can be seen that the Planar remains stable for 4 hours and then increases gradually. As for the Asymmetrical Trench, two step increase can be found. And the second formation of BPD defect is obviously quicker than the first one, which happened after 5 hours. Only one step increase can be found in the Symmetrical Double-Trench device and the TrenchAssisted remains stable through the test.

[picture]

Fig. 11. Thermal images of DUTs during the 8A DC stress test: (a) Planar with ; (b) Asymmetrical Trench with ; (c) Symmetrical Double-Trench with ; and (d) Trench-Assisted Planar with .

Fig. 11. Thermal images of DUTs during the 8A DC stress test: (a) Planar with ; (b) Asymmetrical Trench with ; (c) Symmetrical Double-Trench with ; and (d) Trench-Assisted Planar with .

[picture]

Fig. 12. of four structures in continuous DC current stress of 8A: (a) Planar; (b) Asymmetrical Trench; (c) Symmetrical Double-Trench; (d) Trench-Assisted Planar.

Fig. 12. of four structures in continuous DC current stress of 8A: (a) Planar; (b) Asymmetrical Trench; (c) Symmetrical Double-Trench; (d) Trench-Assisted Planar.

To gain a better understanding of mechanism of degradation, a 3C-layer as of total cell width is inserted in the structure of different SiC MOSFETs at different depths, including and in the models developed in Silvaco TCAD in Fig. 13. The different locations of defect do not lead to an obvious change in I-V characteristics, indicating that the location of the defect has low impact on the overall increase of on-state resistance, though local amplifications of current density can be observed. More research is required to investigate the impact of the defect density, location and severity on amplification of the degradation effects in trench SiC devices.

[picture]

Fig. 13. The cross-sectional views of current densities of, (a) Symmetrical Double-Trench, (b) Planar, (c) Asymmetrical Trench, and (d) Trench-Assisted Planar gate SiC MOSFETs with a 3C-layer at of total cell width inserted in depths of and .

Fig. 13. The cross-sectional views of current densities of, (a) Symmetrical Double-Trench, (b) Planar, (c) Asymmetrical Trench, and (d) Trench-Assisted Planar gate SiC MOSFETs with a 3C-layer at of total cell width inserted in depths of and .

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

In this paper, the quadrant operation and the effects of bipolar degradation of the Gen-3 and Gen-4 SiC MOSFETs are studied. In the -quadrant measurements, the Gen-4 devices show more variations in responses to temperature changes in terms of reverse recovery characteristics compared to Gen-3 devices. In terms of initiation of bipolar degradation, it can be seen that the Symmetrical Double-Trench SiC MOSFET starts to exhibit some signs of bipolar degradation similar to the devices, while the Trench-Assisted Planar MOSFET maintains a very stable performance throughout the tests. Although these findings highlight the impact of different structures on the temperature
response and reliability of MOSFET body diodes, and the fact that electrothermal stress can initiate some bipolar degradation, the observed variations are still too small for conclusive conclusions on the exact scope of degradation in long term operations. Based on this study, further measurements are required likely in range of 100+ hours of operation to cascade the SSF and BPD faults to the extent that degradation would be observable.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

This work is partly funded by collaboration with the Compound Semiconductor Applications Catapult in Newport, UK, funded as part of the EPSRC Catapult Network's 'Innovation Launchpad Network+' program with grant EP/W037009/1 through the Researcher-in-Residence stream, and partly funded by the UK EPSRC grant EP/Y000307/1.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.29.pdf

J. O. Gonzalez, et al., "Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs," in IEEE Transactions on Industrial Electronics, vol. 67, no. 9, pp. 7375-7385, Sept. 2020.

J. Yang, et al., "Impact of Temperature and Switching Rate on Properties of Crosstalk on Symmetrical & Asymmetrical Double-trench SiC Power MOSFET," 47th Annual Conference of the IEEE Industrial Electronics Society (IECON), Canada, 2021, pp. 1-6.

A. Albanna, et al., "Performance comparison and device analysis Between Si IGBT and SiC MOSFET," IEEE Transportation Electrification Conference and Expo (ITEC), 2016, pp. 1-6.

J. Ortiz Gonzalez, et al., "Benchmarking the robustness of Si and SiC MOSFETs: Unclamped inductive switching and short-circuit performance", Micr. Reliability, Vol 138, 114719, 2022.

S. Zhu, et al., "Reliability Comparison of Commercial Planar and Trench 4H-SiC Power MOSFETs," IEEE Int. Reliability Physics Sym. (IRPS), Monterey, USA, 2023, pp. 1-5.

M. R. Ahmed, et al., "Switching performance of a SiC MOSFET body diode and SiC schottky diodes at different temperatures," IEEE Energy Conversion Cong. & Expo, 2017, p. 5487-94.

S. Jahdi, et al., "Electrothermal modeling and characterization of SiC Schottky and silicon PiN diodes switching transients," IEEE Energy Conv. Cong. (ECCE), 2014, pp. 2817-2823.

J. Yang, et al., "Investigation of Performance of Double-Trench SiC Power MOSFETs in Forward and Reverse Quadrant Operation," PCIM Europe, 2021, pp. 1-8.

M. Kang, et al., "Body Diode Reliability of Commercial SiC Power MOSFETs," IEEE 7th Workshop on Wide Bandgap Devices (WiPDA), Raleigh, US, 2019, pp. 416-419.

(Accessed 20/Sep/2024)

Z. Zhu, et al., "Degradation of MOSFET body diode under repetitive surge current stress," Int. Sym. on Power Semiconductor Device (ISPSD), Austria, 2020, pp. 182-185.

S. Palanisamy, et al., "Investigation of the bipolar degradation of SiC MOSFET body diodes and the influence of current density," IEEE Int. Reliability Physic Sym., Monterey, US, 2021.

Hassan Hamad, et al., "First results on 1.2 kV SiC MOSFET body diode robustness tests", Microelectronics Reliability, Volume 151,2023,115264.

Y. Wu, et al., "Evaluation of Bipolar Degradation in SiC MOSFETs for Converter Design," IEEE Energy Conversion Congress & Expo (ECCE), Nashville, USA, 2023, pp. 5359-5365.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-evaluation-and-device-design/978-3-0364-1914-5

Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 37-43

doi: 10.4028/p-Qf5QM9

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-01

Accepted:
2025-08-04

Online:
2025-09-08

Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

Seung Yup Jang , Dongyoung Kim ,

Dinuth C.Y.B. Yapa Mudiyanselage , Hojung Lee , Chungkwang Lee , Jingon Kim , Dongkyun Kim , and Woongje Sung

¹College of Nanotechnology Science and Engineering, University at Albany, Albany NY, 12203, USA

LX Semicon, 2621 Nambusunhwan-ro, Gangnam-gu, Seoul 06267, Republic of Korea

sjang3@albany.edu, kimd1@sunypoly.edu, dyapamudiyanselage@albany.edu, kimdk3@lxsemicon.com, wsung@albany.edu

Keywords: 4H-Silicon Carbide (SiC), MOSFET, Trench, Manufacture, Implantation, Simulation

Abstract

This paper presents the development and optimization of a 1.2 kV Silicon Carbide (SiC) Trench MOSFET with a Bottom P-well (BPW), designed to achieve a compact structure and a simplified fabrication process. By performing the BPW implant before the trench etching process and utilizing it in conjunction with a shallow trench, the process complexity was reduced while maintaining effective corner coverage of the trench gate. Comprehensive simulations and unit process analyses were conducted to evaluate the effects of the hard mask sidewall angle, P-well, and JFET implant doses on device characteristics. Optimal performance was achieved by introducing an additional implant in the P -well region, which significantly enhanced breakdown voltage without affecting channel properties. The optimized device demonstrated a specific on-resistance ( ) of , a breakdown voltage (BV) of 1600 V , and a threshold voltage ( ) of 3 V , with potential further reductions in through substrate thinning.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

Silicon Carbide (SiC) Trench MOSFETs have attracted significant attention due to their inherent scalability, leading to high cell densities and a high mobility plane, which result in low channel resistance-especially advantageous for voltage ratings of 1200 V or less. The key feature of the SiC Trench MOSFET structure is the formation of a deep P-region to protect the trench corners. This can be achieved by epitaxial regrowth after implantation [1], etching followed by implantation through the etched region [2], or high-energy deep aluminum (Al) implantation [3].

Recently, trench structures have been developed in more sophisticated ways, featuring extremely narrow cell pitches [4], the use of multiple epi-regrowth techniques [5], and 3D designs [6] to optimize the trade-off between on-resistance ( ) and the electric field at the oxide more efficiently. Many of these advanced structures have been developed by Integrated Device Manufacturers (IDMs) or laboratories with internal process development and integration capabilities.

Developing a complete process flow for trench structures from ground up is a time-consuming, costly, and challenging endeavor, especially when working with fabrication facilities that lack support for trench process design kits. This is because the technologies mentioned above require multiple process development steps, in addition to developing the trench module process (etching, rounding, oxidation, etc.), which are not necessary for the basic SiC planar MOSFET process. Therefore, it is highly desirable for device engineers to design a simple trench structure that lowers the barriers to adoption for fabrication facilities.

Our objective is to create a 1.2 kV SiC Trench MOSFET structure with the simplest possible process flow and validate its feasibility through TCAD simulations and unit process fabrication. This paper introduces the novel concept and fundamental characteristics of a compact 1.2 kV SiC Trench

MOSFET featuring a Bottom P-well (BPW), illustrating its optimization using process parameters derived from unit process development. The proposed device is characterized by a shallow trench structure with a BPW that can be implemented through conventional ion implantation, eliminating the need for a multi-MeV ion implanter.

Device Design and Process Flow of the Proposed Device

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

Fig. 1(a) illustrates a 1.2 kV SiC Trench MOSFET with a BPW implemented through TCAD process simulation (Synopsys Sentaurus). The source contacts are intermittently placed in the orthogonal direction to reduce the cell pitch. The easiest way to think of forming a BPW is to have an Al implant on the bottom of a trench. Forming a BPW on the etched bottom after trench etching offers the advantage of utilizing the etched depth to create a deep P-region with a low-energy implant. Additionally, the self-aligned process ensures there is no misalignment between the gate trench and the BPW. However, in this case, the BPW width is typically not wide enough to fully cover the trench corners, and several process-related factors must be considered, including the formation of hard masking when implanting after etching, and surface protection during activation annealing of the etched side. Therefore, to streamline the fabrication process, we decided to first perform all implantations (JFET, JTE, BPW, P-well, N+, P+), activate them, and then proceed to etch the gate trench, as shown in Fig. 1(c). By completing all implantations and activation prior to trench etching, we were able to leverage the already established planar MOSFET implant module process.

For the effective BPW formation, the Al implant needs to be deep enough to cover the trench gate corners. We limited the Al implant energy to a reasonably high value, with a maximum of 1.1 MeV . As a result, the peak depth of the BPW is around , which sufficiently covers the relatively shallow trench corners, as shown in Fig. 1(b). The use of a 1.1 MeV Al implant,

[picture]

Fig. 1. (a) Cross-sectional view of the SiC Trench MOSFET with Bottom P-well (BPW) by TCAD process simulation. (b) SEM cross-section image of the etched SiC wafer followed by rounding process. (c) Brief process flow from Implantation to Gate oxidation.

Fig. 1. (a) Cross-sectional view of the SiC Trench MOSFET with Bottom P-well (BPW) by TCAD process simulation. (b) SEM cross-section image of the etched SiC wafer followed by rounding process. (c) Brief process flow from Implantation to Gate oxidation.

resulting in a -deep BPW, makes the MOSFET structure vertically compact. Additionally, the design avoids extra structures on each side, such as a deep P-well or source trench [7]. The BPW is much wider than the gate trench to fully cover the trench corners-even in the case of misalignmentand to block the high bias from the bottom in the OFF state. This also makes the structure horizontally compact.

To effectively arrange the N+ / P-well / JFET / BPW regions in a vertically and horizontally compact manner, the N-type doping concentration in the JFET region must be high enough to prevent pinch-off. However, an excessively high N doping concentration in the JFET region would lower the breakdown voltage (BV), necessitating careful optimization of the process.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

The simulated electrical properties of this structure are presented in Fig. 2. We simulated the specific on-resistance ( ), threshold voltage ( ), and BV as functions of the total dose of P -well and JFET implants. The compact structure needs to ensure stable blocking performance by maintaining sufficient Al doping concentrations in the P -well while also achieving low on-state resistance with adequate N doping concentrations in the JFET region.

We set the maximum total P -well dose at and then tested reduced doses. The total JFET dose was varied from 1.31 E 13 to . At a total JFET dose of , the JFET region is completely pinched-off, resulting in a very high . As the JFET dose exceeds 1.5E13 typically falls below under most conditions, despite the structure having a very narrow JFET region for current flow. This is due to the high JFET doping concentration, which exceeds .

However, lower BV is observed when a high JFET dose is combined with a P -well concentration below . The optimized conditions were found with a JFET dose of and a P -well dose at , resulting in an of , a BV of approximately 1600 V , and a of .

[picture]

Fig. 2. Simulated specific on-resistance ( ), threshold voltage ( ), and breakdown voltage (BV) of the SiC Trench MOSFET. Total JFET dose and total P -well dose were validated for different split.

Fig. 2. Simulated specific on-resistance ( ), threshold voltage ( ), and breakdown voltage (BV) of the SiC Trench MOSFET. Total JFET dose and total P -well dose were validated for different split.

[picture]

Fig. 3. (a) SEM cross-section image of the fabricated 3.8 um thick hard mask for the BPW implantation. (b) BPW implant profiles from the process simulation with the hard mask angle of and .

Fig. 3. (a) SEM cross-section image of the fabricated 3.8 um thick hard mask for the BPW implantation. (b) BPW implant profiles from the process simulation with the hard mask angle of and .

For the 1.1 MeV Al implant to form a BPW region, a relatively thick oxide hard mask is required. The sidewall angle of the hard mask affects the implant profiles, making it crucial to investigate the impact of the hard mask angle on device performance. To block the 1.1 MeV Al implant, a hard mask is sufficient, but to accommodate a wider range of BPW depths, we developed a thick hard mask (Fig. 3(a)) and examined its impact on the BPW implant profile using TCAD process simulation.

[picture]

Fig. 4. (a) Simulated cross-sections of the SiC Trench MOSFET with the BPW hard mask angle of (a) and (b) . (c) Simulated Ron,sp, Vth, and BV of the devices with the hard mask angle of and . Various JFET and P-well dose splits were tested.

Fig. 4. (a) Simulated cross-sections of the SiC Trench MOSFET with the BPW hard mask angle of (a) and (b) . (c) Simulated Ron,sp, Vth, and BV of the devices with the hard mask angle of and . Various JFET and P-well dose splits were tested.

[picture]

Fig. 5. (a) Cross-sectional view of the proposed SiC Trench MOSFET. P-doping in the P-well region is enhanced by the additional implant. (b) Net doping concentration profile across the additional enhanced region.

Fig. 5. (a) Cross-sectional view of the proposed SiC Trench MOSFET. P-doping in the P-well region is enhanced by the additional implant. (b) Net doping concentration profile across the additional enhanced region.

As shown in Fig. 3(a), the SEM analysis of the fabricated hard mask revealed an average angle of . However, when simulated with TCAD process simulator, we assumed an angle to account for potential process variations. As illustrated in Fig. 3(b), the hard mask results in a noticeable Al upward tail compared to the case, which could significantly affect device performance.

Simulation results show the impact of this process variation on device characteristics, as illustrated in Fig. 4. Compared to the case (Fig. 4(a)), the upward Al tail caused by the hard mask angle increases the Al concentration in the channel region (Fig. 4(b)), reducing the JFET width and the net N doping concentration. As a result, the overall is elevated, and the also increases. However, the overall BV is improved across the tested P -well dose range.

Thus, the optimization process should prioritize lowering the P -well doping concentration and increasing the N concentration in the JFET region to achieve reasonable and . However, constraints from reach-through effects due to weak P -well doping in combination with excessive N concentration must also be considered. The optimized conditions result in an of , a BV of approximately 1600 V , and a that is too high, exceeding 6 V .

To address performance trade-offs, we introduce an additional implant in the P -well region on either side of the device, where reach-through occurs, to enhance the Al concentration (Fig. 5). We added a single Al implant positioned at an appropriate distance from the gate trench. If placed too close to the channel region, it could affect the Vth and channel resistance. While this additional structure may require a new mask layer, it is possible to share the contact source mask to simplify the process.

The addition of the implant dramatically improves device performance, as summarized in Fig. 6. When comparing the structure without the added to the one with the added , for a JFET total dose of , there is no alteration to the channel concentration, thus maintaining the same and . However, the BV margin significantly increases due to the prevention of reach-through. As a result, the P-well dose can be reduced to or less without causing reach-through, allowing for a further increase in the JFET concentration, thereby reducing .

For a JFET total dose of up to , the BV is maintained, and the avalanche breakdown occurs at the bottom of the BPW. The optimized performance with the proposed enhanced doping yields an of , a BV of 1600 V , and a reasonable of 3 V . The maximum electric field of the gate oxide at a drain voltage of 1200 V remains sufficiently low, around . It is important to note that this simulation was conducted with a substrate; therefore, if substrate grinding is accounted for, could be as low as .

[picture]

Fig. 6. Simulated Ron,sp, Vth, and BV of the proposed SiC Trench MOSFET. The results for the device without additional implants are plotted for the reference. The maximum electric field at the gate oxide was measured to be when drain voltage was 1200 V as shown in the inset.

Fig. 6. Simulated Ron,sp, Vth, and BV of the proposed SiC Trench MOSFET. The results for the device without additional implants are plotted for the reference. The maximum electric field at the gate oxide was measured to be when drain voltage was 1200 V as shown in the inset.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

In this study, we developed and optimized a 1.2 kV SiC Trench MOSFET with a Bottom P-well (BPW), focusing on achieving a compact device structure with a simplified process flow. By performing the BPW implant before trench etching and using it in conjunction with the shallow trench, we reduced process complexity while maintaining effective corner coverage of the trench gate. Through extensive simulations, we investigated the impact of various factors such as hard mask angle, P-well and JFET implant doses on key device characteristics, including on-resistance ( ), threshold voltage ( ), and breakdown voltage (BV). To improve device performance, we introduced an additional implant in the P -well region, which significantly enhanced the breakdown voltage without altering channel properties. This addition enabled the reduction of P -well dose and allowed for higher JFET doping concentrations, leading to a further reduction in . The final optimized structure achieved an of , a BV of 1600 V , and a of 3 V , with a gate oxide electric field of at 1200 V drain voltage. Further substrate grinding could reduce to . These results demonstrate that the proposed design and process optimizations are effective in balancing performance trade-offs while maintaining manufacturability, making this approach highly attractive for fabricating SiC Trench MOSFETs.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

This work was supported by LX Semicon.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.37.pdf

S. Harada, Y. Kobayashi, A. Kinoshita, N. Ohse, T. Kojima, M. Iwaya, H. Shiomi, H. Kitai, S. Kyogoku, K. Ariyoshi, Y. Onishi, and H. Kimura, Materials Science Forum, 897 (2017) 497500.

R. Tanaka, K. Sugawara, Y. Fukui, H. Hatta, H. Koketsu, H. Suzuki, Y. Miyata, K. Taguchi, Y. Kagawa, S. Tomohisa, and N. Miura, Materials Science Forum, 1004 (2019) 770-775.

S. Harada, Y. Kobayashi, K. Ariyoshi, T. Kojima, J. Senzaki, Y. Tanaka, and H. Okumura, IEEE Electron Device Letters, 37 (2016), 314-316.

M. Sampath, D. Morisette, and J. A. Cooper, Key Engineering Materials, 946 (2023) 95-102.

S. Harada, Y. Kobayashi, S. Kyogoku, T. Morimoto, T. Tanaka, M. Takei, and H. Okumura, IEEE International Electron Devices Meeting (2018), 8.2.1-8.2.4.

Y. Ebihara, Aiko Ichimura, S. Mitani, M. Noborio, Y. Takeuchi, S. Mizuno, T. Yamamoto, and K. Tsuruta, International Symposium on Power Semiconductor Devices & ICs (2018), 44-47.

Y. Kobayashi, S. Harada, H. Ishimori, S. Takasu, T. Kojima, K. Ariyoshi, M. Sometani, J. Senzaki, M. Takei, Y. Tanaka, and H. Okumura, Materials Science Forum, 858 (2016), 974977.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 45-51

doi: 10.4028/p-6st6Ux

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-08

Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

The original version of this paper is available on https://www.scientific.net/KEM.1022.45.pdf

Yoshitaka Kimura , Takaaki Tominaga , Yutaka Fukui , Akifumi lijima , Kohei Adachi , Fumitoshi Yamamoto , Yasuhiro Kagawa , and Kazushi Kono

Component Production Engineering Center, Mitsubishi Electric Corporation, 8-1-1, Tsukaguchi-Honmachi, Amagasaki-shi, Hyogo, 661-8661, Japan

Advanced Tech. R&D Center, Mitsubishi Electric Corporation, 8-1-1, Tsukaguchi-Honmachi, Amagasaki-shi, Hyogo, 661-8661, Japan

Power Device Works, Mitsubishi Electric Corporation, 1-1-1 Imajyukuhigashi, Nishi-ku, Fukuoka-shi, Fukuoka, 819-0192 Japan

Power Device Works, Mitsubishi Electric Corporation, 997 Miyoshi, Koushi-shi, Kumamoto, 861-1197 Japan

Kimura.Yoshitaka@ay.MitsubishiElectric.co.jp, Tominaga.Takaaki@dy.MitsubishiElectric.co.jp,

Fukui.Yutaka@dx.MitsubishiElectric.co.jp, dijima.Akifumi@bc.MitsubishiElectric.co.jp,

Adachi.Kohei@da.MitsubishiElectric.co.jp, Yamamoto.Fumitoshi@dx.MitsubishiElectric.co.jp,

Kagawa.Yasuhiro@cj.MitsubishiElectric.co.jp, Kono.Kazushi@dx.MitsubishiElectric.co.jp

Keywords: Silicon Carbide, MOSFET, Trench-Gate, Bottom Oxide Protection, Edge-termination, Guard ring

Abstract

In this study, we investigated a trench-gate silicon carbide metal-oxide-semiconductor field-effect transistor (SiC-MOSFET) edge-termination structure using an oxide film along the trench surface to simplify the manufacturing process. The trench structure in the termination region serves as a guard ring, eliminating the need for a separate guard ring process and thereby reducing the number of process steps. To suppress electric field concentration at the edge of the cell region under high voltage, a boundary region between the cell and termination regions was implemented. Technology Computer-Aided Design (TCAD) device simulations confirmed that by using the boundary region and narrowing the mesa width, avalanche breakdown was prevented up to the breakdown voltage of the cell region.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.45.pdf

A trench-gate silicon carbide metal-oxide-semiconductor field-effect transistor ( SiC -MOSFET) is anticipated to achieve low specific on-resistance ( ) by increasing cell density and enhancing channel mobility [1]. We previously reported a 1.2 kV class trench-gate SiC-MOSFET that achieved low [2]. With the increasing demand for 1.2 kV class trench-gate SiC-MOSFETs in the electric vehicle market, reducing the number of process steps is crucial. Various termination structures for trench-gate SiC-MOSFETs have also been explored [3,4]. Conventional termination structures require additional process steps to form a guard ring. In this study, we investigated an edgetermination structure using an oxide film along the trench surface. Since the trench structure in the termination region acts as a guard ring, the need for a separate guard ring process is eliminated, thereby reducing the number of process steps. Technology Computer-Aided Design (TCAD) simulations confirmed the breakdown voltage, electric field, and impact ionization characteristics of this structure.

Design and Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1022.45.pdf

Figure 1 shows the schematic cross-sectional view of the edge-termination structure using an oxide film along the trench surface [5]. This structure is composed three regions: the cell, boundary, and termination regions. The color of the electrodes in the trench structure corresponds to the electrical potential. Gray electrodes within the cell region are connected to the gate potential. Light gray electrodes within the boundary region are connected to the source potential. Green electrodes within the termination region are at floating potential and are not connected to each other. In the cell region, current flows when the gate is turned on. The termination region comprises floating electrodes, an oxide film along the trench surface, and a surrounding p-type implanted layer. The lateral electric field is gradually relaxed due to the oxide film along the trench surface. In the boundary region, the gate electrode is connected to the source electrode, preventing current flow through the channel, and avoiding changes in the lateral electrostatic potential. The boundary region separates the cell and termination regions.

Figure 2 also illustrates the cross-sectional fabrication process flow of the trench-gate SiCMOSFET edge-termination structure. (i) First, the p-type well region and n-type source region are formed by vertical Al and N implantation into the n-type drift layer using photolithography. (ii) Next, an hard mask for SiC trench etching is created by dry etching after deposition with photolithography. (iii) The SiC trench structure is then formed by dry etching using the hard mask. (iv) The bottom p-well (BPW) is formed by vertical self-aligned implantation into the trench bottom with the hard mask remaining after SiC trench etching. In conventional edge-termination structures, a resist mask must be formed by photolithography in areas where the BPW is not to be formed. However, in this structure, the BPW is used as a guard ring, eliminating the need for a resist mask, and the BPW is formed using only an hard mask, making photolithography unnecessary and reducing the number of process steps. (v) The hard mask is then removed, and the p-type and n-type sidewall regions are formed by tilted Al and N implantation with photolithography, respectively. Conventional edge-termination structures require additional implantation steps involving photolithography to form edge-termination structures such as guard rings [6] or the junction termination extension (JTE) [7], but the edge-termination structure of the present invention eliminates these steps. (vi) Finally, activation annealing, gate formation, contact formation, and metallization are carried out.

By adopting this edge-termination structure, it is possible to eliminate manufacturing processes required for forming edge-termination structures such as guard rings or JTE, thereby reducing the need for multiple steps, including photolithography, etching, and cleaning. However, forming trenches in the boundary and termination regions with the same mesa width as the cell region leads to electric field concentration at the edge of the cell region, which reduces the device breakdown voltage below the cell breakdown voltage. Therefore, we explored methods to suppress the reduction in breakdown voltage.

[picture]

Fig. 1. Schematic of the cross-sectional view of the edge-termination structure

Fig. 1. Schematic of the cross-sectional view of the edge-termination structure

[picture]

Fig. 2. Cross-sectional fabrication process flow of the trench-gate SiC-MOSFET edge-termination structure

Fig. 2. Cross-sectional fabrication process flow of the trench-gate SiC-MOSFET edge-termination structure

Structure that Realizes Cell Breakdown Voltage

The original version of this paper is available on https://www.scientific.net/KEM.1022.45.pdf

Figure 3 illustrates the schematic cross-sectional view of (a) the structure where the termination region is directly adjacent to the cell region and (b) the structure where the cell and termination regions are separated by a boundary region. Figure 4 shows the electric-field distribution and voltage equipotential lines for (a) and (b) when 1.35 kV is applied. The structure with a boundary region (b) suppresses the electric field at the edge of the cell region more effectively than the structure without a boundary region (a). Figure 5 presents the electric field profile at the C 1 point in Figure 3 under 1.35 kV . The maximum electric field value is higher in structure (a) than in structure (b). Additionally, in structure (a), the maximum electric field occurs at the edge of the cell region, whereas in structure (b), it is located within the cell region. In the cell region, an n-type implanted layer extends to the trench sidewall to ensure a current path. A depletion layer forms in the n-type implanted layer, resulting in a higher electric field compared to the area surrounded by the p-type implanted layer [8]. In structure (a), the electric field is further concentrated due to lateral electric field relaxation [9], reducing the breakdown voltage. In structure (b), the trench structure adjacent to the cell region, where the electric field tends to concentrate, is set to the source potential. Consequently, lateral electric field relaxation begins at a point farther from the cell region, separating the electric field concentration caused by lateral electric field relaxation from that on the trench sidewalls, thereby preventing a decrease in breakdown voltage.

Figure 6 depicts the simulated breakdown voltage dependence on mesa width for structures with and without a boundary region. Structures with a boundary region exhibit higher breakdown voltages compared to those without one. This improvement in breakdown voltage is attributed to the separations of the cell and termination regions by the boundary region, which suppresses electric field concentration at the edge of the cell region.-Furthermore, reducing the mesa width further suppresses electric field concentration [10]. BPW at the bottom of the trench acts as a guard ring, if the mesa
width is reduced, the electric field that can be mitigated by a single trench structure becomes smaller. Reducing the mesa width extends the depletion layer, but it suppresses electric field concentration and increases the breakdown voltage. When the mesa width is or less, the breakdown voltage matches that of the cell region. In the structure without a boundary region, reducing the mesa width can improve breakdown voltage, but it does not reach the breakdown voltage of the cell region.-For mesa width down to , the depletion layer does not extend to the edge of the termination region, resulting in an increase in breakdown voltage. However, when the mesa width is reduced to , the depletion layer reaches the edge of the termination region, causing the electric field to concentrate at the edges of the cell and termination regions, which decreases the breakdown voltage [10].

[picture]

Fig. 3. Schematic cross-sectional view of structures with and without boundary region

Fig. 3. Schematic cross-sectional view of structures with and without boundary region

[picture]

Fig. 4. Electric field distribution and voltage equipotential lines under 1.35 kV based on simulation (boundary and termination mesa width is )

Fig. 4. Electric field distribution and voltage equipotential lines under 1.35 kV based on simulation (boundary and termination mesa width is )

[picture]

Fig. 5. Electric field profile applied at 1.35 kV at the C 1 point (boundary and termination mesa width is )

Fig. 5. Electric field profile applied at 1.35 kV at the C 1 point (boundary and termination mesa width is )

Figure 7 shows the impact ionization rate at the time of avalanche breakdown for mesa widths of and for structures with and without a boundary region. For structures with the boundary region, avalanche breakdown occurs at the edge of the boundary region with a mesa width of but occurs inside the cell region with a mesa width of . In contrast, for structures without the boundary region, avalanche breakdown does not occur inside the cell region regardless of the mesa width. As described, achieving the cell breakdown voltage can be accomplished by reducing the mesa width and incorporating a boundary region in the edge-termination structure using an oxide film along the trench surface.

[picture]

Fig. 6. Dependence of the simulated breakdown voltage on mesa width for structures with and without a boundary region (the number of trenches in the termination region is constant)

Fig. 6. Dependence of the simulated breakdown voltage on mesa width for structures with and without a boundary region (the number of trenches in the termination region is constant)

[picture]

Fig. 7. Impact ionization rate at the time of avalanche breakdown for mesa widths of and

Fig. 7. Impact ionization rate at the time of avalanche breakdown for mesa widths of and

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1022.45.pdf

In this study, we conducted TCAD simulations to analyze the breakdown characteristics of the edge-termination structure using an oxide film along the trench surface. By utilizing the trench structure as a guard ring, we eliminate the need for a separate guard ring process, thereby reducing the number of process steps. Our observations indicate that with the boundary region, when the mesa width is or less, the breakdown voltage of the termination region matches that of the cell region. The lateral electric field relaxation is separated from the electric field concentration on the trench sidewalls, which helps suppress the decrease in breakdown voltage. We plan further optimization the edge-termination structure and verify its robustness.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.45.pdf

H. Yano, H. Nakao, H. Mikami, T. Hatayama, Y. Uraoka and T. Fuyuki, Appl. Phys. Lett. 90, 042102 (2007).

K. Sugawara, Y. Fukui, R. Tanaka, K. Adachi, Y. Kagawa, S. Tomohisa, N. Miura, E. Suekawa and Y. Terasaki, PCIM 2021, pp. 504-508.

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology (2014)

P. Godignon, J. Montserrat, J. Rebollo and D. Planson, Mater. Sci. Forum 2022, 1062, 570575.

Y. Fukui, K. Sugawara, R. Tanaka, H. Koketsu, H. Hatta, Y. Miyata, H. Suzuki, K. Taguchi, Y. Kagawa, S. Tomohisa and N. Miura, ICSCRM 2019, pp. 764-769.

D. C. Sheridan, G. Niu, J. N. Merrett, J. D. Cressler, C. Ellis and C. C. Tin, Solid-State Electronics 44 (2000) 1367-1372

V. A. K. Temple, IEDM Technical Digest (1977), pp. 423-426.

R. Tanaka, K. Sugawara, Y. Fukui, H. Hatta, H. Koketsu, H. Suzuki, Y. Miyata, K. Taguchi, Y. Kagawa, S. Tomohisa and N. Miura, ICSCRM 2019, pp. 770-775.

V. A. K. Temple and M. S. Adler, IEEE Transactions on Electron Devices, Vol. ED-22, pp. 910-916. (1975)

X. Deng, Y. Guo, T. Dai, C. Li, X. Chen, W. Chen, Y. Zhang and B. Zhang, Materials Science in Semiconductor Processing 68 (2017), pp. 108-113.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-evaluation-and-device-design/978-3-0364-1914-5

Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 53-61

doi: 10.4028/p-Vh7ZaF

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Revised:
2025-04-29

Accepted:
2025-04-29

Online:
2025-09-08

SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

The original version of this paper is available on https://www.scientific.net/KEM.1022.53.pdf

Jenny Damcevska , Sima Dimitrijev , Jisheng Han , Daniel Haasmann , and Philip Tanner

¹Queensland Micro- and Nanotechnology Centre, Griffith University, Nathan, Qld. 4111, Australia

School of Engineering and Built Environment, Griffith University, Nathan, Qld. 4111, Australia

Institute of Novel Semiconductors, Shandong University, Shanda Nan Lu, China

ajenny.damcevska@griffithuni.edu.au, s.dimitrijev@griffith.edu.au, j.han@sdu.edu.cn, d.haasmann@griffith.edu.au, p.tanner@griffith.edu.au

Keywords: Schottky diode, surge current, edge termination, thermal capacitance, wafer thinning.

Abstract

This paper shows results of SiC Schottky diodes fabricated without ion-implanted P-type regions. Diodes with blocking voltages up to are demonstrated utilizing an epitaxial P-type ring with sloped edges for the edge termination. Reverse-bias currents at temperatures higher than , and at nominal blocking voltages of , and 1700 V , are shown to match the theoretical values based on the two fundamental current mechanisms: tunneling and thermionic emission. In comparison to JBS and MPS diodes, the whole anode area is active, which enables homogeneous current flow and comparable isothermal characteristics without the usual wafer thinning. In addition, the non-thinned wafer results in larger thermal capacitance, allowing for higher repetitive peak surge currents for the same junction temperature within the maximum operating temperature of .

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.53.pdf

Reverse-bias current and forward surge-current capability of SiC Schottky diodes are two important parameters that motivated a departure from pure SiC Schottky-barrier diodes (SBD). The predominant modifications in commercial SiC Schottky diodes, which address observed issues with these two parameters, include the junction barrier Schottky (JBS) diode for reduced reverse-bias current, and the merged Schottky (MPS) diode for improved non-repetitive surge current [1]. A key feature of both structures is the integration of implanted P-type regions, with specific geometric properties, to achieve the desired forward and reverse characteristics. The P-type regions in both JBS and MPS diodes require the use of ion implantation, along with precise photolithography to achieve designed width of and spacing between the P-type regions [2].
This paper discusses a patented design and summarizes the results of a modern SiC SBD without any ion-implanted P-type regions. The following sections discuss the performance of these diodes with respect to three specific parameters: edge termination, reverse-bias current, and surge-current capability.

Edge Termination

The original version of this paper is available on https://www.scientific.net/KEM.1022.53.pdf

When ion-implanted P-type regions are used for edge termination, their depth and the spacing between them can be used to reduce electric-field crowding at the edge of the diode [3]. Without ionimplanted P-type regions, an epitaxial P-type layer can be used with sloped edges to create tapered density of negatively charged acceptors with the aim of reducing the field crowding. This approach
was attempted in the mid-1990's by applying a silicon-nitride mask and oxidation of the top P-type layer to create a P-type ring with sloped edges around the N-type active area of the Schottky diode [4]. However, the breakdown voltages remained below 600 V . The SBD structure shown in Fig. 1 has enabled reverse-bias voltages higher than , as shown by the reverse-bias characteristics in Fig. 2. This was achieved by reducing the angle of the P-type ring to and depositing of as surface passivation. Figure 3 shows that this edge termination and surface passivation almost eliminated the perimeter.

[picture]

Fig. 1. Cross-section of patented SiC Schottky diode without ion-implanted P-type regions [5]. The recess etching needed to define the edge-termination ring was performed by plasma etching for all diodes reported in this paper.

Fig. 1. Cross-section of patented SiC Schottky diode without ion-implanted P-type regions [5]. The recess etching needed to define the edge-termination ring was performed by plasma etching for all diodes reported in this paper.

[picture]

Fig. 2. Reverse bias characteristics of an SBD with the edge termination shown in Fig. 1 and with Ntype drift region designed for blocking voltage of 4,500 V ( )

Fig. 2. Reverse bias characteristics of an SBD with the edge termination shown in Fig. 1 and with Ntype drift region designed for blocking voltage of 4,500 V ( )

[picture]

Fig. 3. Measured reverse-bias current densities (symbols) for diodes designed for 1700 V blocking voltage with different perimeter-to-area ratios. The slope of the linear-regression line shows that the perimeter current is negligible in comparison to the current through the main body.

Fig. 3. Measured reverse-bias current densities (symbols) for diodes designed for 1700 V blocking voltage with different perimeter-to-area ratios. The slope of the linear-regression line shows that the perimeter current is negligible in comparison to the current through the main body.

Another important feature of the structure in Fig. 1 is that the anode metal and the P-type ring form a Schottky diode rather than Ohmic contact. The advantage of this feature is that the Schottky diode to the P-type ring is reverse biased when the main Schottky diode with the N-type drift region is forward biased. Consequently, the associated reliability issues with forward-biased junctions at high current densities, resulting from carrier injections and recombination in SiC [3, 6-9], is eliminated.

Reverse-Bias Current

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Implanted P-type pockets are used in JBS diodes to protect the metal-semiconductor contact by setting the maximum electric field away from the interface . These P-type pockets are densely spaced so that the depletion layers that they create with the N-type region are merged at high reverse voltages . When a JBS diode is forward biased, the current flows between the P-type pockets. This means that the active metal-semiconductor area of the diode is reduced. Figures 4, 5, and 6 show the current-voltage characteristics of SBDs with homogeneous Ti-SiC contacts in the active area, with N-type drift layers designed for three blocking voltages: , , and . The edge termination shown in Fig. 1 was the same for all blocking voltages.

[picture]

Fig. 4. Forward (a) and reverse (b) current-voltage characteristics of diode

Fig. 4. Forward (a) and reverse (b) current-voltage characteristics of diode

[picture]

Fig. 5. Forward (a) and reverse (b) current-voltage characteristics of diode

Fig. 5. Forward (a) and reverse (b) current-voltage characteristics of diode

[picture]

Fig. 6. Forward (a) and reverse (b) current-voltage characteristics of diode

Fig. 6. Forward (a) and reverse (b) current-voltage characteristics of diode

A study of this type of homogeneous SiC Schottky diode showed that the reverse-bias current at junction temperatures above is due to the two fundamental current mechanisms: (1) tunneling and (2) thermionic emission [10]. Consequently, there is no diode-to-diode variation in the reverse current above , and the measured currents match the theoretical model based on these two fundamental current mechanisms without fitting parameters [10]. Measured reverse currents at room temperature exhibit some device-to-device variation and they are higher than the theoretical currents. This indicates that the reverse currents at room temperature include variable leakages through defects at the metal-semiconductor contact, which could be a topic for a future study and confirmation.

Surge-Current Capability

The original version of this paper is available on https://www.scientific.net/KEM.1022.53.pdf

The forward surge-current capability of SiC Schottky diodes is usually classified in two ways: (1) repetitive and (2) non-repetitive peak current of either 10 ms or 8.3 ms half sine waves to correspond to either 50 Hz or 60 Hz sinusoidal voltage, respectively [11-39]. The non-repetitive peak surge current is usually determined by applying single half sine wave pulses with increasing peak-current amplitudes until a diode failure [11-14], and then de-rating the peak current to about of the value that causes failures. To increase the non-repetitive surge current capability in diodes utilizing ion implantation of P-type layers, P-N junctions are created with Ohmic contact to the P-type regions and with areas designed to turn on the P-N junctions when a certain forward voltage is reached. This way, both the Schottky diode and the P-N junction diodes conduct the surge current, resulting in a reduced forward voltage and a reduced power dissipation [6]. With this effect, the non-repetitive surge current of MPS diodes is typically higher than in the case of homogeneous SBD's. However, the integrated P-type regions reduce the area of Schottky contact. To compensate for the increased on resistance due to the reduced Schottky-contract area, the SiC substrate in both JBS and MPS diodes is thinned. In terms of thermal characteristics, this thinning reduces both the thermal resistance and the thermal
capacitance. The positive effect of the reduced thermal resistance is well established but there is a negative effect of the reduced thermal capacitance that is not well understood.
The negative effect of the reduced thermal capacitance by wafer thinning relates to the maximum junction temperature during surge-current pulses, which is relevant for the repetitive surge-current capability of Schottky diodes. To show this effect, we used the method of junction-temperature measurement during a surge-current pulse that is illustrated in Fig. 7.

[picture]

Fig. 7. Illustration of the method applied to measure the junction temperature during a surge-current pulse, , by matching a surge-current loop to isothermal characteristics (data from [40]).

Fig. 7. Illustration of the method applied to measure the junction temperature during a surge-current pulse, , by matching a surge-current loop to isothermal characteristics (data from [40]).

The results shown in Fig. 8 compare a commercial thinned MPS and a non-thinned homogeneous SBD, both rated at 20 A and 1200 V , for the case of a relatively small peak surge current: 80 A , which is four times higher than the nominal current. The chip areas of these two diodes are similar because the gain in Schottky-contact area due to the removal of the P-type regions in the case of SBDs is needed to compensate for the higher specific resistance of the non-thinned substrate and, therefore, to match the turn-on voltage of these diodes. Importantly, the thermal capacitance of the homogeneous SBD is about three times larger because of the larger chip thickness. The power dissipation in these diodes is also similar, given that the P-N junctions in the MPS diodes are not turned on at this surge-current level and the forward characteristics of the turned on Schottky diodes are similar. The difference is due to the larger thermal capacitance of the non-thinned homogeneous SBD, which absorbs the dissipated heat at lower junction temperatures, as shown in Fig. 8 and analyzed in detail in [40].

[picture]

Fig. 8. Comparison of the junction temperatures of a thinned MPS diode and non-thinned homogeneous SBD during a surge current pulse with the peak value of 80 A , which is four times higher than the nominal current (data from [40]).

Fig. 8. Comparison of the junction temperatures of a thinned MPS diode and non-thinned homogeneous SBD during a surge current pulse with the peak value of 80 A , which is four times higher than the nominal current (data from [40]).

Figure 9 shows that the junction temperature of the non-thinned homogeneous SBD remains below the maximum operating junction temperature of for the peak surge current of 120 A , which is six times higher than the nominal forward current. In comparison, the junction temperature of the thinned MPS diode reaches the maximum operating junction temperature with the peak surge current of 100 A , which is five times higher than the nominal current.

[picture]

Fig. 9. The effect of the larger thermal capacitance of the non-thinned homogeneous SBD is that the junction temperature remains below the maximum operating junction temperature for larger peak surge currents (a) in comparison to the thinned MPS diode (b) (data from [40]).

Fig. 9. The effect of the larger thermal capacitance of the non-thinned homogeneous SBD is that the junction temperature remains below the maximum operating junction temperature for larger peak surge currents (a) in comparison to the thinned MPS diode (b) (data from [40]).

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1022.53.pdf

In this paper, we present a homogeneous SiC SBD that has been fabricated without ion-implanted Ptype regions, with a summary of the results relating to three key performance parameters: edge termination, reverse-bias current, and surge current capability. Regarding the edge termination, the electric field crowding is reduced by utilizing an epitaxial P-type ring with sloped edges. With a reduction in the angle of the P -type ring to , the perimeter current at the edge termination is essentially eliminated, which enabled reverse-bias voltages higher than . In addition, a study of the homogenous SBD with nominal blocking voltages of , and 1700 V , demonstrated that the reverse-bias current at junction temperatures above is due to the two fundamental current mechanisms of tunneling and thermionic emission. Regarding the surge current capability, the SBD illustrated higher repetitive peak surge currents than the MPS diode for the same junction temperature, within the maximum operating temperature of . This result is because the SBDs were fabricated without wafer thinning and with similar areas to MPS diodes, which corresponds to higher thermal capacitance that absorbs more heat dissipation at the same temperature.

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The original version of this paper is available on https://www.scientific.net/KEM.1022.53.pdf

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 63-68

doi: 10.4028/p-vz2eBi

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-18

Revised:
2025-02-25

Accepted:
2025-03-20

Online:
2025-09-08

Three Level Pulses to Investigate Gate Switching Instability

The original version of this paper is available on https://www.scientific.net/KEM.1022.63.pdf

D. Scholten , J. Uschmann

Advanced Technologies and Micro Systems, Robert Bosch GmbH, Germany, Mobility Electronics, Robert Bosch GmbH, Germany

dick.scholten@de.bosch.com, bjuergen.uschmann@de.bosch.com

Keywords: 4 H -SiC MOSFET, threshold voltage, Vth-drift, interface traps, GSS, GSI.

Abstract

We use novel three-level pulse sequences, where the intermediate level is either above or below the threshold voltage, to investigate gate switching instability (GSI) in 4H-SiC-MOSFETs. Results with sequences with an intermediate level above the threshold voltage ( ) seem to falsify the hypothesis that trapped holes remaining at the interface after switching to the on-state, are the root cause for GSI, as was described in [1,2]. Fast switching applications may cause negative transient pulses on the gate electrode during the off-state. Results with sequences with an intermediate level below threshold show that such transients may cause an increased -drift. Introducing a delay between the transient and the turn-on of the transistor in such pulse sequences, does not mitigate the effect of a negative transient on the -drift.

Introduction

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Gate switching stress (GSS) using a gate voltage sequence as shown in Fig. 1a causes a positive threshold voltage drift that scales with number of cycles rather than stress duration, as this drift is largely independent of frequency. The -drift increases for lower as indicated by some exemplary results shown in Fig. 1b and also known from literature [3-6]. Two common theories to explain both the strong dependence on the minimum voltage level of the stress sequence and the scaling with number of switching cycles are local field enhancement and recombination induced interface degradation [3-5]. Both theories assume that electrons are expelled from interface traps during the low-level interval. Note, that this is equivalent to capturing of holes in interface traps. Local field enhancement assumes that a significant number of trapped holes remain at the interface after switching the gate to a positive voltage. Eventually these trapped holes will recombine with inversion layer electrons, but until then, they give rise to an internal electric field which adds up to the external field causing enhanced electron trapping. GSI has been shown to follow a power law up to at least 2 MHz with duty cycle [3]. Therefore, internal field enhancement must assume that a significant number of holes recombines within 250 ns . Otherwise, the enhancement would be constant during the on-state, shifting the Vth-drift dependence on number of pulses towards a dependence on total duration of the high level.

Recombination induced interface degradation assumes that the energy released by recombination at interface traps causes reconfiguration of atomic bonds at the interface that result in electron traps. We propose a stress sequence using three voltage levels with intermediate level higher than the threshold voltage that largely avoids internal field enhancement to check the validity of that theory.

Gate switching instability is usually investigated using a gate driving circuit that switches between a negative low level and a positive high level to generate the gate switching stress. To assess the expected threshold voltage drift in an application, a sensible choice would be to take and as used in the application for the positive and negative voltage level in GSS. However, overshoots at the rising or falling edge of the gate voltage signal may significantly increase the -drift [2]. Overshoots typically happen when using a small gate resistor to allow a high gate current for fast switching. The induced overshoot voltage may be estimated by multiplying the inductance of the gate connection with the maximum of the time derivative of the gate current. Even with modules optimized for low inductance of the gate connection, some overshoot may need to be accepted to minimize the switching
losses. To account for the significant effect of overshoots, the JEDEC guideline JEP195 proposes to test two-level GSS for worst case conditions in the application, by setting the high level at least as high as the peak of the overshoot and the low level at least as low as the peak of the undershoot [7].

[picture]

Fig. 1. (a) Gate voltage sequence for gate switching stress, where the shaded area represents the region below the threshold voltage. (b) Exemplary results that show the increase of threshold voltage drift with lower Voff.

Fig. 1. (a) Gate voltage sequence for gate switching stress, where the shaded area represents the region below the threshold voltage. (b) Exemplary results that show the increase of threshold voltage drift with lower Voff.

Apart from overshoots due to the combination of gate inductance and fast gate switching, there are also transients on the gate voltage signal from capacitive coupling to the drain connection. Fig 2a shows a typical half bridge including some parasitic components and Fig 2b shows schematic drain voltage and gate voltage curves of the low side. Consider the case that the high side is switched off while the low side was already off and assume that the load will pull the output to ground in a short time. The drain voltage of the low side will then suddenly drop to ground and the capacitance between the gate and drain of the low side will couple this negative voltage slope into the gate electrode, resulting in an undershoot and some oscillations during the off-state as indicated by . When the high side is turned on, while the low side is already off, we have a similar process. The fast rise of the drain voltage of the low side will couple in the gate electrode of the low side, risking an accidental turn-on (also called parasitic turn-on) of the low side, when gate voltage exceeds . The oscillations after this fast rise of the gate voltage may cause oscillations with corresponding undershoot as indicated by .

[picture]

Fig. 2. (a) Schematic representation of a half bridge including parasitic capacitors between the terminals, showing how a fast voltage slope at the drain may couple into the gate connection of the parasitic gate drain capacitance. (b) Schematic drain voltage curve of the low side switch and the gate voltage curve of the low side switch with some indicated voltage levels of different undershoots and oscillations due to coupling with the drain connection.

Fig. 2. (a) Schematic representation of a half bridge including parasitic capacitors between the terminals, showing how a fast voltage slope at the drain may couple into the gate connection of the parasitic gate drain capacitance. (b) Schematic drain voltage curve of the low side switch and the gate voltage curve of the low side switch with some indicated voltage levels of different undershoots and oscillations due to coupling with the drain connection.

Depending on module design, the different kind of undershoots may reach a voltage far below VOFF and following the reasoning of the JEDEC guideline described above, we should take the lowest transient peak voltage as the low level in a two-level GSI experiment to obtain worst case conditions. As transients may be very short in time and may also have a delay before switching, it will be interesting if this reduces the -drift compared to worst case conditions with a constant low level. We therefore propose a stress sequence using three voltage levels with intermediate level at negative voltage to check the effect of a delay between a transient and the switching time-point for the on-state on the -drift.

Experimental Setup

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We designed a setup to generate the three level gate stress sequences proposed in the previous section, with a relay to switch between stress phase and measurement phase. During the stress phase, source and drain are shorted and driven by a gate driver IC with duty cycle at 500 kHz . The gate is driven at the same frequency and duty cycle by a second independent channel of the IC. The effective gate-source voltage is thus the difference between the voltage supplied to the gate and the voltage supplied to the source-drain connection. Voltages and delay between the driver channels are set such that we obtain the gate stress voltage sequence shown in Fig. 3. The sequences in Fig. 3b and Fig. 3c use , and +4 V for the intermediate voltage, which is higher than the threshold voltage and thus causes inversion at the interface. The sequences in Fig. 3d and Fig. 3e use and -3 V for the intermediate voltage, which avoids inversion at the interface. We used commercially available devices (IMBG120R234M2H) with a small gate capacitance to allow fast switching without oscillations despite the relay in the drive path. Both stress and measurements were done at room temperature. To separate the -drift due to GSI from the drift originating from the interface traps with time constants shorter than a few seconds, we included an aggressive preconditioning before each -measurement by applying -18 V for 1 s and then applying +20 V for 1 s , repeating that preconditioning sequence five times. The was measured with gate and drain shorted and forcing -0.9 mA at the source contact.

[picture]

Fig. 3. (a) Schematic representation of the experimental setup to generate three-level waveforms with independent drivers for gate and source/drain and switches for intermediate measurement of including aggressive preconditioning. (b) Three-level stress sequence with area below indicated by light shading and intermediate level higher than . The intermediate level defines a delay between and , as indicated by the arrow. (c) Same as before, but without delay. (d) Three-level stress sequence with area below the intermediate level indicated by darker shading. The intermediate level defines a delay between and , as indicated by the arrow. (e) Same as before but without delay.

Fig. 3. (a) Schematic representation of the experimental setup to generate three-level waveforms with independent drivers for gate and source/drain and switches for intermediate measurement of including aggressive preconditioning. (b) Three-level stress sequence with area below indicated by light shading and intermediate level higher than . The intermediate level defines a delay between and , as indicated by the arrow. (c) Same as before, but without delay. (d) Three-level stress sequence with area below the intermediate level indicated by darker shading. The intermediate level defines a delay between and , as indicated by the arrow. (e) Same as before but without delay.

Results of Three-Level Stress with Intermediate Level Higher than the Threshold Voltage

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Fig. 4a shows measured oscilloscope traces of a single cycle based on the gate voltage sequences of Fig. 3b and Fig. 3c, with the intermediate level at +4 V . The traces differ in the delays, listed in the legend, between the end of the lower level and the beginning of the upper level. Fig. 4b shows twolevel sequences used as references. The measured with positive pulse sequence from Fig. 4b does not show any drift, whereas the curve from the negative pulse sequence shows a significant drift, as shown in Fig. 5a. The three level stress pulse sequences all show very similar -drift curves. A close-up of these curves in Fig. 5b shows that the -drift slightly increases with reduction of the delay.

[picture]

Fig. 4. (a) Oscilloscope trace of a single cycle of the applied voltage sequences. Three level sequences with different delays between the end of the lower level and the beginning of the upper level. (b) Reference sequences with only two levels.

Fig. 4. (a) Oscilloscope trace of a single cycle of the applied voltage sequences. Three level sequences with different delays between the end of the lower level and the beginning of the upper level. (b) Reference sequences with only two levels.

[picture]

Fig. 5. (a) -drift due to gate switching stress with the stress voltage sequences of the previous figure. LinLog plot. (b) Log-Log plot of the three level pulse sequences at high number of sequence cycles.

Fig. 5. (a) -drift due to gate switching stress with the stress voltage sequences of the previous figure. LinLog plot. (b) Log-Log plot of the three level pulse sequences at high number of sequence cycles.

Results of Three-Level Stress with Intermediate Level At Negative Voltage

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Fig. 6a shows the oscilloscope traces of the applied stress voltage sequences to investigate the effect of a negative pulse during the off-state. The trace without negative pulse is used as a reference. Fig. 6b shows that the negative pulse significantly increases the -drift and that the delay between the end of the lower level and the beginning of the upper level, does not make a significant difference.

[picture]

Fig. 6. Experiment to test the effect of a negative pulse during the off-state. (a) Oscilloscope traces of a single cycle of the applied gate stress voltage sequence with different delays between the end of the lower level and the beginning of the upper level. (b) Resulting -drift after a high number of cycles.

Fig. 6. Experiment to test the effect of a negative pulse during the off-state. (a) Oscilloscope traces of a single cycle of the applied gate stress voltage sequence with different delays between the end of the lower level and the beginning of the upper level. (b) Resulting -drift after a high number of cycles.

Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1022.63.pdf

The measured with the positive pulse sequence shown in Fig. 4b, believed to avoid GSI, does not show any drift in Fig. 5a, indicating that the preconditioning is sufficient to avoid -drift from interface traps with trapping time constants shorter than a few seconds. The measured with the negative pulse sequence shown in Fig. 4b, shows significant drift in Fig. 5a, indicating that even with low positive voltages, GSI is triggered effectively. Therefore, the -drift curves shown in this paper are believed to be due to GSI.

The three-level stress sequences with intermediate level higher than the threshold voltage, as shown in Fig. 3b and Fig. 3c, were used to test the hypothesis based on internal electric field enhancement. We use the intermediate level above the threshold voltage to force the majority of the holes, trapped at the interface during the off-state, to recombine with channel electrons. As explained in the introduction, we expect that a significant number of holes recombine within 250 ns . Thus, when switching to the on-state, we largely avoid internal field enhancement. Fig. 5 allows a comparison of the curve without an intermediate level, i.e. no delay, before turn-on and thus with internal field enhancement, with the curve with an intermediate delay of 420 ns , where we would not expect significant field enhancement. We do see a slight increase for the curve without delay, which may be due to internal field enhancement. However, it is unlikely that increasing the delay would reduce the -drift such that we end up at the combined -drift of the reference curves with the positive and negative pulse in Fig. 4b, which would correspond to the case where we do not have GSI. The hypothesis for internal field enhancement as the root cause for GSI seems therefore unlikely. If we assume electron-hole recombination as the driving force for GSI, then the -drift only depends on and and would be independent of the delay, matching the results much better.

As explained in Fig. 2, real applications may have large negative transients during the off-state and the curves in Fig 6. indicate that such transients may significantly increase the -drift. This may be due to the additional hole accumulation during the negative transient as indicated by the dark shaded area in Fig. 3(d)-(e). The delay between the transient and switching on the transistor does not significantly change the -drift. It seems that there is no "relaxation" after a transient curve to mitigate the effect of a negative transient on the -drift.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1022.63.pdf

This work has been carried out within TRANSFORM project which has received funding from the Key Digital Technologies Joint Undertaking (KDT JU) under Grant Agreement No101007237. The JU receives support from the European Union's Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.63.pdf

Scholten, D., Baringhaus, J., Krebs, D., & Noll, S. (2023). „Hypothesis to Explain Threshold Drift due to Dynamic Bipolar Gate Stress." In Materials Science Forum (Vol. 1090, pp. 159164). Trans Tech Publications, Ltd. https://doi.org/10.4028/p-bt3i95.

H. Jiang, X. Zhong, G. Qiu, L. Tang, X. Qi and L. Ran. "Dynamic Gate Stress Induced Threshold Voltage Drift of Silicon Carbide MOSFET", in IEEE Electron Device Letters, vol. 41, no. 9, pp. 1284-1287, Sept. 2020, doi: 10.1109/LED.2020.3007626.

M. W. Feil et al., "Gate Switching Instability in Silicon Carbide MOSFETs-Part I: Experimental," in IEEE Transactions on Electron Devices, vol. 71, no. 7, pp. 4210-4217, July 2024, doi: 10.1109/TED.2024.3397636.

T. Grasser, M. W. Feil, K. Waschneck, H. Reisinger, J. Berens, D. Waldhoer, A. Vasilev, M. Waltl, T. Aichinger, M. Bockstedte, W. Gustin, and G. Pobegen, "Gate Switching Instability in Silicon Carbide MOSFETs-Part II: Modeling", Transactions on Electron Devices, 71, 4218 (2024), DOI:10.1109/TED.2024.3397629.

P. Salmen et al., "Gate-switching-stress test: Electrical parameter stability of SiC MOSFETs in switching operation," Microelectronics Reliability, vol. 135, p. 114575, Aug. 2022.

Lelis, A. J., & Habersat, D. B. (2023). „AC-Stress Degradation in SiC MOSFETs”. In Materials Science Forum (Vol. 1092, pp. 151-155). Trans Tech Publications, Ltd.

"Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-OxideSemiconductor Devices for Power Electronic Conversion", JEP195, JEDEC, Feb 2023

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 69-76

doi: 10.4028/p-M8r40M

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Accepted:
2025-05-05

Online:
2025-09-08

DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

The original version of this paper is available on https://www.scientific.net/KEM.1022.69.pdf

Tingqiang Yang , Marco Perazzi , Christopher Zellner , Georg Pfusterschmied , Ulrich Schmid

Institute of Sensor and Actuator Systems, TU Wien, Gusshausstrasse 27-29, 1040 Vienna, Austria

Christian Doppler Laboratory for Sustainable Silicon Carbide Technology, Gusshausstrasse 2729, 1040 Vienna, Austria

georg.pfusterschmied@tuwien.ac.at, ulrich.e366.schmid@tuwien.ac.at

Keywords: Porous 4H-SiC, surface termination, PECE, DFT.

Abstract

In our previous work, single-crystalline porous thin foils were successfully released from a monocrystalline wafer by photoelectrochemical etching (PECE). This technology is promising for the next-generation power device fabrication processes (e.g. costefficient engineered substrates) and micro-electromechanical systems. The surface terminations of the pore walls will affect the behavior in the further fabrication process and application, thus motivating the need for detailed investigations. This work based on DFT calculations focuses on the surface terminations of five 4 H -SiC non-polar surfaces, i.e. and , which can well represent the walls of the C-face etched pores penetrating through the released foil along the [0001] direction. The surface energies of the stoichiometric surfaces are found to be in the sequence of . All these surfaces have high chemical affinity to and even more to HF . In particular, for the complete surface termination by HF , the relative stability of these crystal planes can be changed and depends on the HF chemical potential. For example, in the range of HF chemical potential from -4.10 to -1.70 eV , the becomes more stable than the . This preliminary research provides insight into the surface chemistry of the non-polar surfaces, especially the and , which have rarely been investigated.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1022.69.pdf

Compared to standard silicon, the wide-bandgap semiconductor well-known for its high electrical breakdown strength, high bulk carrier mobility, high-temperature stability and high thermal conductivity enables the realization of power devices with enhanced efficiency even under higher voltage, frequency and temperature conditions [1]. Its chemical inertness and mechanical resistance, on the one hand, render the -based devices capable of operating in harsh environments but, on the other hand, results in challenges in the device fabrication process.

Etching is an important technique in the manufacturing process of power electronics. Wet etching can be an effective and low-cost method, which, in contrast to dry etching, brings little damage to the subsurface and requires less sophisticated equipment [2]. Normally, wet etching at room temperature requires external stimulation, typically through voltage bias and light irradiation.

Photoelectrochemical etching (PECE) is performed with ultraviolet (UV) light illumination and a positive voltage bias at the electrode in HF or KOH solution [2-6]. The UV light illumination generates electrons and holes in the , and the positive voltage pushes the holes to the interface between the electrode and electrolyte. In HF aqueous solution, which is more common and utilized in our previous research, the chemical reactions are expected to involve the carbon transforming into CO or and the Si dissolving as [4-6]. Through these reactions, the PECE can effectively porosify the 4 H -SiC with nanometer-sized pore structures deep into the bulk. This technology promises to optimize power device fabrication processes on cost-efficient, engineered substrates [7].

Besides the application in power electronics, porosified SiC has extensive applications in catalysis, sensors and MEMS [5, 8, 9].

The crystal structure of sequentially stacks a Si and a C layer in z -direction, and commercially available wafers are normally exposed with two polar crystal surfaces (i.e., Si-face and C-face) with a small tilt angle. Our previous research of PECE in HF solution has discovered that the pores etched from the C -face propagate along the [0001] direction [4, 10], as shown in Fig. 1a. The pore diameter can be easily tuned but in a limited range by varying the applied voltage with no relevant effect on the etching direction [4].

The resulting SiC porous structure will exhibit a higher surface-to-volume ratio with respect to the initial wafer implying a lasting change in its physical and chemical properties, and thus representing a remarkable platform for in-depth investigations.

Density functional theory (DFT) simulation has been extensively utilized to investigate material surface chemistry down to the atomic scale. Previous achievements of DFT in this field include the work of Dhar et al. revealing the termination of Si - and C -faces of by simulating the interaction between HF and the last oxygen layer at the oxide/ SiC interface [11].

[picture]

Fig. 1 (a) SEM image of cross-section view of the pores in etched from C -face, (b) the expression of ( ), ( ), ( ), ( ) and ( ) in a hexagonal system, (c) pore shape by hypothesizing the equal surface energies, (d) atom structures of the five crystal planes (The structures show three supercells which are divided by the two vertical brown lines. The grey balls represent C atoms, while the yellow Si .)

Fig. 1. (a) SEM image of cross-section view of the pores in etched from C -face, (b) the expression of ( ), ( ), ( ), ( ) and ( ) in a hexagonal system, (c) pore shape by hypothesizing the equal surface energies, (d) atom structures of the five crystal planes (The structures show three supercells which are divided by the two vertical brown lines. The grey balls represent C atoms, while the yellow Si .)

The pores, etched from C -face of , are along [0001] direction and thus are mainly exposed with non-polar 4 H -SiC surfaces, such as and . Fig. 1b shows these crystal planes in a hexagonal system. Because of hexagonal symmetry, the five crystal plane families could build a 48-gon pore wall, as shown in Fig. 1c, by utilizing Wulff's theorem and hypothesizing the equal surface energies. The 48-gon is almost a circle and can represent the pore walls. Herein, the DFT calculations are performed to investigate the surface termination of these nonpolar crystal planes during photoelectrochemical pore formation in the HF aqueous solution. Next, the surface energies of the ideal stoichiometric surfaces are calculated. Finally, adsorption of HF and on these surfaces is simulated to obtain the energetically favorable surface termination in HF aqueous solution. Accordingly, the surface energies of the terminated surfaces are also compared at a specific chemical potential of HF .

Computational Details

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The periodic DFT calculations were performed by the plane-wave program Quantum Espresso 7.1 based on the general gradient approximation (GGA) in the form of a Perdew-Burke-Ernzerhof (PBE) functional [12]. The pseudo-potentials were chosen according to the standard solid-state pseudopotential libraries (SSSP) to represent the core electrons of each type of atom in the system [13]. The primitive cell was first relaxed with cutoff energy ( ) of 45 Ry for the size of the plane wave basis set and a Monkhorst-Pack grid of for Brillouin-zone integration. The relaxed 4H-SiC primitive cell is still in P63mc [186] symmetry with , which is very close to the experimental results [14]. Supercells of , and surfaces were built based on the relaxed primitive cell, as shown in Fig. 1d. All the atoms at the surface have at most one dangling bond, and thus the cleaved surfaces have their own most stable stoichiometric termination. One can also note that the high-index planes, i.e. , and , are composed of and in different ratios.

The parameters of the supercells and the corresponding k-pints grids are listed in Table 1. Some atoms are fixed to simulate the bulk, while others can be relaxed to simulate the surface. As shown in Fig. 2a, b by taking as an example, for the surface energy calculation of the stoichiometric surface, the whole slab is put in the middle of the supercell in -direction and the atoms of the middle layer are fixed so that both sides can be relaxed. In contrast, only one side of the slab is simulated for the surface termination by HF and to reduce the calculation cost. Hence, the slab is at the bottom of the supercell, and the bottom-layer atoms are fixed. For adsorption energy calculation, the is increased to 55 Ry for the structures due to the requirement by the H atom, and van de Waals interaction is considered by the Grimme-D3 method [15]. Last but not least, a 20 Å vacuum layer is added in -direction to avoid the boundary effect induced by the periodic lattice.

Table 1 The parameters of supercells, k-point, of stoichiometric surfaces

Crystal planes | Supercell lattice [Å³] | Atoms of supercell | Dangling bond | k-point | Esurf [meV/Å²]
(1010) | 12.38 × 10.13 × 37.87 | 112 C, 112 Si | 8C, 8Si | 3 × 4 × 1 | 179
(1120) | 10.13 × 10.72 × 40.12 | 112 C, 112 Si | 8C, 8Si | 4 × 4 × 1 | 172
(2130) | 10.13 × 8.19 × 37.90 | 72 C, 72 Si | 6C, 6Si | 4 × 5 × 1 | 178
(3140) | 10.13 × 11.16 × 37.84 | 92 C, 92 Si | 8C, 8Si | 4 × 4 × 1 | 180
(3250) | 10.13 × 13.49 × 35.78 | 104C, 104 Si | 10C, 10Si | 4 × 3 × 1 | 176

[picture]

Fig. 2 Atom structures of unrelaxed supercells (a) for stoichiometric surface energy calculation and (b) for surface termination simulation, (c) Wulff construction by the calculated stoichiometric surface energies and (d) the corresponding pore shape.

Fig. 2. Atom structures of unrelaxed supercells (a) for stoichiometric surface energy calculation and (b) for surface termination simulation, (c) Wulff construction by the calculated stoichiometric surface energies and (d) the corresponding pore shape.

The surface energy ( ) per unit area is calculated by Eq. 1

where is the energy of the two-side relaxed slab, N the number of primitive cells in the slab and is the energy of the primitive cell. The adsorption energy ( ) of each single molecule is by Eq. 2

where is the energy of the one-side relaxed slab together with the n number of molecules adsorbed, and and is the energy of the slab and the molecule, respectively.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/KEM.1022.69.pdf

The of the five crystal planes are listed in Table 1. For the stoichiometric surfaces, the 4 H SiC is the most stable non-polar crystal plane, followed by and . Rauls et al. have also reported that the surface energy of the ( ) is lower than that of the [16]. Based on these surface energies, the pore shape can be constructed by Wulff's theorem (Fig. 2c, d) [17]. Naturally, the surfaces cannot be clean in the HF aqueous solution. High temperature annealing in the inert atmosphere, for example helium, can result in a clean surface and allow the pore to reorganize into the equilibrium shape. However, the surface history of the pore walls, i.e. the terminations, must influence on the reorganization. To explain the behaviors of the pore during annealing, there is a need to understand the terminations of the pore walls during PECE.

All the surfaces of the pore wall are highly affinitive to the HF and molecules in the etching solution. Fig. 3 shows the adsorption configurations of a single HF or molecule on the and surfaces. On the are terrace and channel sites (Fig. 3a-d), which one can easily identify in Fig. 2a, b. The HF molecule can be dissociatively adsorbed at both sites with F boding to Si and H to C (Fig. 3a, b). The at the terrace and channel sites are -4.36 and -4.78 eV . For , the terrace site only allows the molecular adsorption with the O bonding to Si (Fig. 3c) and Eads of -0.73 eV , and the channel site makes the dissociative adsorption of favorable with of -4.36 eV (Fig. 3d). The reason for the high at the channel site is that the two dangling bonds of the pair of the Si and C at the channel point towards each other, which allows the hydrogen bond interaction between H and the F (or O ) after the dissociation of HF ( or ).

There is not much difference for the sites on the surface, where HF and can be dissociatively adsorbed with values of -3.65 and -3.09 eV (Fig. 3e, f).

Since the and possess the same sites as those on the and , all of them render the dissociative adsorption of HF and . Additionally, they have the corner sites, as indicated in Fig. 2d, whereas the corner sites do not facilitate the adsorption. The Eads of a single HF and molecule on these non-polar crystal planes are listed in Table 2. The former ranges from -3.87 to -4.78 eV , and the latter from -3.12 to -4.36 eV . All these surfaces are more affinitive to HF .

[picture]

Fig. 3 Atom configurations. (a, b) A single HF and (c, d) a single adsorbed on the terrace and channel site of the , and (e) A single HF and (f) a single adsorbed on the . (The white balls are the H atoms, the red O and the blue F .)

Fig. 3. Atom configurations. (a, b) A single HF and (c, d) a single adsorbed on the terrace and channel site of the , and (e) A single HF and (f) a single adsorbed on the . (The white balls are the H atoms, the red O and the blue F .)

The high affinity of HF can make the surface completely terminated only with HF , i.e. all the dangling Si and C bonds are replaced with the F and the H . The full layer adsorption of HF on the 4H-SiC ( ) and ( ) surfaces are shown Fig. 4a, b. The average of each molecule on these five surfaces is still very high ( ), as listed in Table 2. The shows the highest per HF but the lowest per unit area. By adding the per unit area to the of the stoichiometric crystal planes, the of the terminated crystal planes can be obtained (Last column of Table 2). All of them are negative values, suggesting that the can be dissolved by HF at high HF chemical potential [18]. The calculated reaction energy of is -4.22 eV . This reaction has been identified and its reverse reaction has been utilized to deposit SiC film with plasma [19, 20]. The high affinity of HF on the surface originates from the high strength of Si-F ( ) and bond ( )) [19].

As mentioned, the Eads of the HF is calculated by Eq. 2 with being the energy of a single HF molecule. However, the value of is related to the chemical potential of each element or each composition in the practical system [21]. The Eq. 2 is very close to a system with a high HF chemical potential, such as a pure HF gas phase at high temperature. In the HF aqueous solution for PECE the HF chemical potential should be much lower. By setting the chemical potential of a single HF molecule as zero, the of the terminated crystal planes can be obtained at the lower HF chemical potential, as shown in Fig. 4c. With the decrease of HF chemical potential, the fully covered surfaces increase their and thus become less stable. Hence, in a diluent HF aqueous solution, some HF could be replaced with molecule by considering that the surfaces also have high chemical affinity to .

Table 2 The values of HF and and the of the completely terminated crystal planes.

Crystal planes | aEads [eV] | bEads [meV/Å²] | cEsurf[meV/Å²]
HF | H₂O | Comp. HF | Comp. HF | Comp. HF
(1010) | −4.78 | −4.36 | −4.21 | −267 | −90
(1120) | −3.65 | −3.09 | −3.78 | −279 | −106
(2130) | −4.48 | −3.45 | −3.89 | −282 | −104
(3140) | −4.70 | −4.21 | −3.93 | −278 | −98
(3250) | −3.87 | −3.12 | −3.85 | −282 | −105

Note: means the of each single molecule, the per unit area, and the of the HF terminated crystal planes with respect to the chemical potential of a single HF molecule. The value of the last column is the intersection in Fig. 4c.

[picture]

Fig. 4 Atom configurations of a full-layer HF adsorption on the (a) ( ) and (b) ( ), (c) the of the crystal planes with respect to HF chemical potential which is set the potential of a single HF molecule as zero. The slope is , where n is the number of the adsorbed HF molecule and A is the surface area.

Fig. 4. Atom configurations of a full-layer HF adsorption on the (a) ( ) and (b) ( ), (c) the of the crystal planes with respect to HF chemical potential which is set the potential of a single HF molecule as zero. The slope is , where n is the number of the adsorbed HF molecule and A is the surface area.

Another significant point shown in Fig. 4c is that the stability order of the crystal planes can be changed by the HF adsorption. The stoichiometric 4H-SiC is less stable than , whereas in the range of HF chemical potential from -4.10 to -1.70 eV the becomes more stable.

Summary and Outlook

The original version of this paper is available on https://www.scientific.net/KEM.1022.69.pdf

In this work, we simulate the terminations of five non-polar surfaces, i.e. , and , which can well represent the walls of the C-face etched pores penetrating in [0001] direction. The of the stoichiometric surfaces are calculated, with the sequence of . Adsorption of a single HF or molecule on the surfaces are also calculated, and the results demonstrate that all the surfaces are more affinitive to HF than . Accordingly, we simulate the surfaces completely terminated with HF and obtain their relative stability with respect to the HF chemical potential.

This preliminary research provides some insight into the surface chemistry of the nonpolar surfaces among which the and have rarely been investigated. However, our simulation is somehow an idealistic case where these stoichiometric crystal planes are hypothesized to be created under an ultra-clean condition and then directly immersed into the HF aqueous solution. The practical surface terminations are expected to be more complicated and should be influenced by the etching mechanism, which is still under study whether the is directly dissolved by HF or it is firstly oxidized into by and then dissolved HF . This research understanding of surface chemistry helps to reveal the etching mechanism. In the near future, the surface reaction of HF and on these crystal planes will be simulated.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1022.69.pdf

The financial support by the Austrian Federal Ministry of Labour and Economy, the National Foundation for Research, Technology and Development and the Christian Doppler Research Association is gratefully acknowledged. We also acknowledge the computation resource from the Vienna Scientific Cluster (VSC-5).

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.69.pdf

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S. Whiteley, A. Sorensen, J. J. Vajo, R. Sfadia, T. D. Ladd, S. Cui, J. Graetz, Dopant selective photoelectrochemical etching of SiC, J. Electrochem. Soc. 170 (2023) 036508.

M. Leitgeb, G. Pfusterschmied, S. Schwarz, B. Depuydt, J. Cho, U. Schmid, Communicationcurrent oscillations in photoelectrochemical etching of monocrystalline 4 H silicon carbide, ECS J. Solid State Sci. Technol. 10 (2021) 073003.

M. Leitgeb, C. Zellner, M. Schneider, U. Schmid, Porous single crystalline 4H silicon carbide rugate mirrors APL Mater. 5 (2017) 106106.

M. Leitgeb, C. Zellner, C. Hufnagl, M. Schneider, S. Schwab, H. Hutter, U. Schmid, Stacked layers of different porosity in 4 H SiC substrates applying a photoelectrochemical approach, J . Electrochem. Soc. 164 (2017) E337.

C. S. Solanki, R. R. Bilyalov, J. Poortmans, J. Nijs, R. Mertens, Porous silicon layer transfer processes for solar cells, Sol. Energ. Mater. Sol. C. 83 (2004) 101-113.

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G. Tuci, Y. Liu, A. Rossin, X. Guo, C. Pham, G. Giambastiani, C. Pham-Huu, Porous silicon carbide (SiC): a chance for improving catalysts or just another active-phase carrier? Chem. Rev. 121 (2021) 10559-10665.

M. Leitgeb, C. Zellner, M. Schneider, U. Schmid, A combination of metal assisted photochemical and photoelectrochemical etching for tailored porosification of 4 H SiC substrates, ECS J. Solid State Sci. Technol. 5 (2016) P556.

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P. Giannozz, S. Baroni, N. Bonini, M. Calandra, R. Car, C. Cavazzoni, D. Ceresoli, G. L. Chiarotti, M. Cococcioni, I. Dabo, et al., QUANTUM ESPRESSO: a modular and open-source software project for quantum simulations of materials, J. Phys.: Condens. Matter 21 (2009) 395502.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 77-82

doi: 10.4028/p-6pxJ5v

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-27

Accepted:
2025-02-27

Online:
2025-09-08

TCAD Model Parameter Calibration Strategy for SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1022.77.pdf

Jieun Lee , Jong Min Kim , Seung Hyun Kim , Hee Bae Lee , Young Chul Kim , and Hyunchul Nah

TE Center, DB Hitek Co. Ltd, Bucheon Gyeonggi-do 14519, Korea

TD Team3, DB Hitek Co. Ltd, Bucheon Gyeonggi-do 14519, Korea

ajieun.lee2@dbhitek.com, bjongmin.kim1@dbhitek.com, seunghyun.kim3@dbhitek.com, heebae.lee@dbhitek.com, youngchul.kim@dbhitek.com, hyunchul.nah@dbhitek.com

Keywords: SiC Power MOSFET, TCAD Simulation, Model Parameter, Calibration, Short-Circuit

Abstract

We present an accurate calibration strategy for TCAD model parameters of a 1200 V vertical Silicon-Carbide (SiC) MOSFET, considering key physical characteristics of SiC such as trap distribution along the interface, mobility degradation, and Schottky contact for the p-type region. Initially, static characteristics are used to calibrate the interface traps and mobility model parameters in the low electric field region after matching the simulated doping profile with SIMS. Subsequently, capacitance-voltage (C-V) characteristics are calibrated by considering both the capacitance in periphery and the Schottky effect for the p-type well (PWell) region. Finally, the calibrated model was used to evaluate SC withstand time using mixed-mode TCAD simulation. The simulated static and dynamic performance, including short-circuit (SC) withstand time, are in good agreement to the measurements with an error rate of less than . In summary, we propose a TCAD model parameter calibration method for highly accurate simulation of 1200 V vertical SiC MOSFETs, which will contribute to finding process and design solutions that consider both static and dynamic characteristics.

Introduction

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SiC MOSFETs are highly desirable due to their lower on-resistance (RoN), higher breakdown voltage, and stronger high temperature performance compared to silicon devices in medium power applications [1-2]. The faster switching and higher power density inherent in these applications present new challenges for SiC MOSFET device designers. An accurate set of model parameters in a device simulator is essential to perform reliable simulations, as the absence of full simulation support requires costly fabrication-based design cycles. However, TCAD simulations for SiC often lead to inaccurate results primarily due to insufficient information on interface properties, as well as bulk/interface mobility degradation resulting from variations in manufacturing batches, processes, and application conditions. Previous studies have primarily focused on calibrating interface traps only, which limits their applicability across a wide voltage range [2-3]. This limitation arises because the device performance is also significantly influenced by other properties such as bulk traps, mobility degradation, and Schottky barrier effects. In this study, we present an accurate calibration strategy for TCAD model parameters of a 1200 V vertical SiC MOSFET by considering the overall physical model parameters including trap distribution along the interface, mobility degradation, Schottky contact characteristics, and periphery dimensions. The proposed method has demonstrated enhanced predictive performance for current-voltage (I-V) ( ), C-V characteristics ( ), and SC performance ( ).

Simulation and Results

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Fig. 1 shows the cross-sectional view of the conventional 1200 V vertical SiC MOSFET along with its resistance model, which is used to calibrate the static characteristics. The proposed calibration method is based on the default model parameters of from the latest version of Sentaurus TCAD [4]. This model utilizes a wide-bandgap material featuring high critical electric field,
saturation velocity, and thermal conductivity. However, it characterizes zero interface/bulk trap density and ideal Ohmic contact, which are not realistic [4]. Consequently, as shown in Fig. 2, we propose a TCAD model parameter calibration flows to provide designers with more realistic and accurate simulation results.

[picture]

Fig. 1. The cross-sectional view of a 1200 V vertical SiC MOSFET with a resistance model for I-V calibration (RDrift = resistance in drift region (N-epi), Rwafer = resistance in high doped wafer, Rcs, resistances in source and drain contacts, respectively, resistance in N -plus source, channel resistance, resistance in JFET region, Twafer thickness of highly doped wafer, width).

Fig. 1. The cross-sectional view of a 1200 V vertical SiC MOSFET with a resistance model for I-V calibration (RDrift = resistance in drift region (N-epi), Rwafer = resistance in high doped wafer, Rcs, resistances in source and drain contacts, respectively, resistance in N -plus source, channel resistance, resistance in JFET region, Twafer thickness of highly doped wafer, width).

The process calibration of the device structure and doping profiles is crucial as the initial step in device calibration. We compared the SIMS profile with the process simulation results and calibrated the Monte-Carlo model parameters in TCAD as the first step (not shown in here). For the device model parameter calibration, the static characteristics, especially the current-voltage (I-V) characteristics, are considered as the second step to apply the appropriate mobility models and the interface characteristics. Since the density of states ( ) at the interface is more than two orders of magnitude higher than at the interface [5], resulting in reduced channel mobility and device reliability issues, estimating the accurate interface trap density in this step is the most important. In the resistance model depicted in Fig. 1, only the channel resistance ( ) varies with gate bias, and it is high enough in the subthreshold (SS) region which means the total resistance (R ) can be set to . Since the SS slope is mainly affected by the interface trap density, once the oxide capacitance and channel doping concentration are determined, estimating the order of can be simplified without requiring C-V measurements that necessitate a lateral MOSFET structure. Vt is adjusted by applying a fixed charge in , which does not impact gate controllability. And the upper Vt region, which is affected by the remaining resistances as well as Rch, is adjusted by changing the mobility/Schottky model parameters for the JFET/Drift/N+ regions.
For the dynamic characteristics, the main feature is the characteristics. Each capacitance indirectly represents the accuracy of doping concentration, device structure, and area. Since the doping concentration of the simulation is calibrated with the actual SIMS profile, it is essential to consider device dimension factors to understand characteristics. For the input capacitance ( ) and output capacitance ( ) calibration, both active (cell) and peripheral (ring and gate-pad (Fig. 3(a))) areas are taken into account because gate-source capacitance ( ) and drain-source capacitance are the primary capacitances in the peripheral area as shown in Fig. 3(b). In addition, since the reverse transfer capacitance ( ) characteristic according to the drain voltage is the main characteristic of the switching overshoot characteristic, it is crucial to ensure model consistency by considering the Schottky barrier because P-plus typically has a large Schottky barrier in SiC [6].

[picture]

Fig. 2. The proposed TCAD calibration flow for the SiC MOSFET, including its relevant model parameters within Sentaurus workbench and the resistances shown in Fig. 1.

Fig. 2. The proposed TCAD calibration flow for the SiC MOSFET, including its relevant model parameters within Sentaurus workbench and the resistances shown in Fig. 1.

[picture]

Fig. 3. (a) Top view of the SiC MOSFET device. (b) Vertical structure and its capacitance model in the ring and gate-pad regions. are the main capacitances in this area. Gate-drain capacitance is nearly zero due to the source-connected P -plus region blocking the gate.

Fig. 3. (a) Top view of the SiC MOSFET device. (b) Vertical structure and its capacitance model in the ring and gate-pad regions. are the main capacitances in this area. Gate-drain capacitance is nearly zero due to the source-connected P -plus region blocking the gate.

Figure 4 shows the improved accuracy of the TCAD model created using the proposed calibration method as evidenced by its comparison with the I-V experimental data. A good matching is observed in all curves under various bias conditions ( and ). The I-V calibration achieved through the proposed procedure indicates that the calibrated set of model parameters operates on devices with different W (not depicted here). This suggests that the calibrated TCAD well models each component of the resistance in Figure 1, including mobility degradation in both bulk and interface regions, as well as parasitic resistance components in the wafer and contact regions.

Figure 5 compares the TCAD simulation with the experimental results of the characteristics. Since the area of the ring and gate pad corresponding to the periphery constitutes more than of the total chip area, and must reflect the impact of the ring and gate pad, as shown in Fig. 5 (a) and (b). Additionally, as shown in Fig. 3 (b), does not affect the periphery area. Since a certain area of PWell (Fig. 1) can function as floating nodes due to the Schottky barrier of the P-plus contact, the floating node effect of PWell is considered in Crss calibration, resulting in good matching with the
experimental data shown in Fig. 5(c). The proposed model exhibits an error rate of less than 5% for SS Slope, , Ron, and capacitances.

[picture]

Fig. 4. Measured vs. TCAD (a) with changing and (b) with changing before and after calibration, respectively.

Fig. 4. Measured vs. TCAD (a) with changing and (b) with changing before and after calibration, respectively.

[picture]

Fig. 5. Measured data vs. calibrated TCAD simulation results of C-V characteristics ( ) ((a) , (b) , (c) ).

Fig. 5. Measured data vs. calibrated TCAD simulation results of C-V characteristics ( ) ((a) , (b) , (c) ).

Finally, the calibrated model parameters were used to evaluate the most important characteristic of SiC MOSFETs: SC withstand time using mixed-mode TCAD simulation. The SC test circuit is shown in Fig. 6. Besides the calibrated model parameters, all other physical model parameters for thermal characteristics in supported by Synopsys have been applied in the SC simulation. During the simulation, after the gate voltage turns off, the total current does not reach zero due to carrier generation induced by the high lattice temperature, as shown in Fig. 6 (d). This leakage current increases the lattice temperature, leading to further increase in leakage current through a positive feedback loop. The generated holes flow through the PWell to Pplus, increasing the electrostatic potential in PWell and reducing the energy barrier, as shown in Fig. 6 (d), resulting in parasitic BJT turn-on in the vertical direction under PWell. The pattern of the SC failure characteristics after Vgs turns off in TCAD matches the measurement results. The simulated SC withstand time was very similar to the measurements with an error rate of less than .

[picture]

Fig. 6. (a) Circuit diagram for SC test . (b) Measurement and (c) TCAD results of the SC test under the failure condition, respectively. Failure in simulation is determined when the maximum lattice temperature exceeds 1900 K and the drain current increases again after the gate turns off. (d) Simulated vertical conduction band diagram at each time in Fig. 6 (c).

Fig. 6. (a) Circuit diagram for SC test . (b) Measurement and (c) TCAD results of the SC test under the failure condition, respectively. Failure in simulation is determined when the maximum lattice temperature exceeds 1900 K and the drain current increases again after the gate turns off. (d) Simulated vertical conduction band diagram at each time in Fig. 6 (c).

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1022.77.pdf

In summary, we have proposed a TCAD model parameter calibration method for highly accurate simulation of 1200 V vertical SiC MOSFETs. This method will contribute to finding process and design solutions that consider both static and dynamic characteristics. The calibrated model parameters can be used to analyze 2D/3D cell design to improve Ron-BV trade-off characteristics, process modifications, or other dynamic characteristics such as reverse recovery, gate charge, unclamped inductive switching, etc.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/KEM.1022.77.pdf

This work was supported by the Industrial Strategic Technology Development Program (00144306) funded by the Ministry of Trade, Industry & Energy (MOTIE), South Korea and Ecofriendly & High-efficiency 1200 V SiC MOSFET Development for Commercialization in Energy Industry (00431820), South Korea.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.77.pdf

J. Victory, J.R Guitart, R. Krishna, K. Jia, D, Zurek, P. Betak, C. He, and J. Lehocky, Simulation Challenges of SiC MOSFET Switching Performance and Reliability, SISPAD (2023), PL-02.

K. Lee, M. Domeij, B. Buono, K. Gumaelius, J. Franchi, F. Allerstam, J. Victory, M. Baghaie, and T. Neyer, Device Simulation Modeling of 1200 V SiC MOSFETs, PCIM Europe (2017), 190-195.

L. Maresca, I. Matacena, M. Riccio, A. Irace, G. Breglio, and S. Deliento, TCAD model calibration for the interface trap distribution of a planar SiC MOSFET, IEEE WiPDA Asia (2020).

Sentaurus TCAD Tools Suite. V-2023.09. Synopsys.

V.V. Afanasev, M. Bassler, G. Pensl, and M. Schulz. "Intrinsic interface states." Physica Status Solidi (a) 162, no. 1 (1997), 321-337.

K. Vasilevskiy, and K. Zenkentes, Advancing Silicon Carbide Electronics Technology I, Materials Research Forum, Chaper.3.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-evaluation-and-device-design/978-3-0364-1914-5

Key Engineering Materials, ISSN: 1662-9795, Vol. 1022, pp 83-88

doi: 10.4028/p-vHPv5Z

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Revised:
2025-02-06

Accepted:
2025-08-04

Online:
2025-09-08

Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

The original version of this paper is available on https://www.scientific.net/KEM.1022.83.pdf

Ayan K. Biswas , Daniel J. Lichtenwalner , Brett Hull , Donald A. Gajewski and Satyaki Ganguly

Wolfspeed, Inc, 4600 Silicon Drive, Durham, NC 27703, USA

ayan.biswas@wolfspeed.com, daniel.lichtenwalner@wolfspeed.com brett.hull@wolfspeed.com, don.gajewski@wolfspeed.com, satyaki.ganguly@wolfspeed.com

Keywords: SiC MOSFETs, Accelerated Reverse Bias (ARB), Lifetime modeling, Gate Oxide Reliability, Accelerated HTRB.

Abstract

Robustness under blocking is an important reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, which typically employs multiple VDS stress values beyond the rated drain bias but below the avalanche voltage, is considered as the best practice for measuring the device lifetime in the blocking mode. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified modeling approach where qualification-like high temperature reverse bias (HTRB) or ARB test at a single stress voltage for a reasonable stress duration can be used to project gate oxide lifetimes under blocking.

Introduction

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Owing to its wider bandgap allows fabrication of unipolar power switches with voltage ratings more than ten times higher than is feasible for Si unipolar devices, with the same specific onresistance. Hence during off state while blocking high voltage, the electric fields experienced by SiC and the gate dielectric (typically ) are much higher in SiC vertical power MOSFET devices as compared to their Si counterparts [1]. As a result, reliability under blocking has become a hot topic for MOS based SiC power devices and is discussed in detail by industry standard bodies such as JEDEC. Although running only a single point high temperature reverse bias (HTRB) qualification test at or near maximum rated drain bias and at maximum rated junction temperature can fulfill the qualification requirements for blocking reliability, it does not provide information regarding device lifetime prediction for SiC-MOS devices during high voltage off-state stress. Like gate bias mediated TDDB, under high drain bias stress failures are typically due to gate oxide wear-out in the JFET region of the power device. In order to enable blocking lifetime extrapolation at operating condition, a modeling approach consistent with the E-model for gate oxide (Gox) lifetime can be used for accelerated reverse bias (ARB) stressing. For ARB stressing one would typically employ multiple stress values beyond the rated drain bias but below the avalanche voltage [2-5]. However, generating enough failure statistics within a reasonable timeframe in ARB tests can be challenging, especially for devices which are designed such that avalanche breakdown occurs at a lower drain voltage than is necessary to induce gate oxide wear-out failures in a tractable duration. In this paper we propose a simplified alternative modeling approach that can be used from ARB/HTRB test data from one stress drain voltage and reduced stress time, to project device lifetime under blocking at lower drain voltage values.

Experimental Data on Accelerated Reverse Bias (ARB) Test

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SiC power MOSFETs are designed with a safe margin between rated voltage and avalanche voltage which enables the accelerated reverse bias (ARB) test to be performed above the rated drain voltage, but below the avalanche voltage of the device. This margin is critical as it determines how much voltage acceleration can be generated above the rated voltage. In this regime of drain stress,
oxide electric field in the JFET gap can induce gate oxide wear-out failures. Figure 1 shows the results of an ARB test where three sets of Wolfspeed 1200 V rated packaged parts were stressed with values of and 1450 V at for nearly one year to gather failure statistics. The devices show relatively low gate and drain leakage until abrupt drain to gate/source short failure occurs, with little to no precursor signal, similar to what happens in a constant bias time dependent dielectric breakdown (TDDB) test.

[picture]

Fig.1. MTTF lifetime projection of 1200 V rated SiC MOSFETs under ARB condition from three groups of stressed parts at . Inset shows a cross-sectioned device with a gate oxide rupture after ARB stress right at the highest field point, in the center of the JFET region.

Fig.1. MTTF lifetime projection of 1200 V rated SiC MOSFETs under ARB condition from three groups of stressed parts at . Inset shows a cross-sectioned device with a gate oxide rupture after ARB stress right at the highest field point, in the center of the JFET region.

Failure analysis confirms that the ARB failure mechanism is gate oxide breakdown at the center of the JFET gap (inset in Fig. 1). This is expected because that is the location of the highest gate oxide electric field in an ARB test. There is no evidence of edge termination or SiC breakdown, which demonstrates that gate oxide wear-out is the primary failure mechanism. Therefore, from the failure distribution which followed Weibull statistics, lifetime projection at operating voltage is then performed by extracting fitting parameters via maximum likelihood estimation and employing a "linear E-model". The median time to failure (MTTF) plot is derived from the ARB dataset and indicated as in Fig. 1.

Lifetime Modeling for ARB

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Although the above mentioned method is the best possible approach to model ARB data, it has been extremely time consuming to take a certain percent of population to failure for all different drain bias values such that lifetime can be projected with a sufficiently high confidence level. Simply from the perspective of test-duration, conducting an ARB test similar to the one presented Fig. 1 for every qualification of a new product is not feasible. Therefore, we propose a modeling approach that allows one to project blocking lifetime within a reasonable amount of test duration while maintaining a high confidence level. Figure 2 portrays this alternative approach for off-state lifetime modeling utilizing the "linear E-model" and a single stress voltage failure data set obtained from a qualification type HTRB or ARB test running for a certain duration (preferably 1000 hours or more). Considering that a certain percentage ( ) of the population failed after is applied for hours, with a known Weibull slope ( ), MTTF or any other failure time percentile ( ) can be extrapolated ( ) at that condition as given by Eq. 1. From this test result, according to "linear E-model" a blocking lifetime curve can be drawn for any drain bias using Eq. 2.

However, such an estimation will still need the knowledge of either voltage acceleration or intercept . Estimation of is non-trivial and equally challenging as constructing lifetime curves from multiple drain biases. Conversely, the intercept represents the lifetime of a device when is extrapolated to 0 . At zero gate or drain bias the Gox lifetime is likely determined by the physics of diffusion and subsequent degradation mechanism. Hence the conjecture that at for a given device technology (identical oxide thickness, drift thickness, cell design etc.) and temperature likely should hold at least for a first order approximation. By using this argument, we propose to extract value by conducting TDDB test on the devices from the same product family with multiple voltages. Thus, the knowledge of value from a TDDB test, along with a known Weibull slope ( ) likely can be utilized to construct a blocking lifetime curve for any failure percentile from a single drain bias stress test data.

[picture]

Fig. 2. Schematic representation of blocking lifetime plot construction from a single stress for hours. Estimation of failure time for any failure percentage ( ) from stress time with a certain failure percentage ( ) and the knowledge of provides a means to construct the TTF extrapolation line.

Fig. 2. Schematic representation of blocking lifetime plot construction from a single stress for hours. Estimation of failure time for any failure percentage ( ) from stress time with a certain failure percentage ( ) and the knowledge of provides a means to construct the TTF extrapolation line.

Analysis of TDDB data for

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In the previous section, we argued at gate oxide lifetime should solely be determined by the physics of diffusion at a particular temperature and thereby making comparable to . A relevant question can be whether experimental data supports this claim. To address this, we extracted values from a significant number of TDDB tests conducted at multiple gate voltages ( ) on different sets of devices with similar voltage ratings, all with comparable gate oxide thicknesses. By extracting fitting parameters via maximum likelihood estimation and employing a "linear E-model", MTTF lifetimes for different products are plotted in Fig. 3. values projected from TDDB data fall within the range of hours. Notably, value ( hours) extracted from the year-long ARB test (as shown in Fig. 1) closely matches with the value obtained from TDDB testing on similar devices at , further corroborates this assumption.

[picture]

Fig. 3. MTTF ( ) lifetime plots for TDDB tests on different products having similar gate oxide thickness and similar voltage and resistance ratings.

Fig. 3. MTTF ( ) lifetime plots for TDDB tests on different products having similar gate oxide thickness and similar voltage and resistance ratings.

Discussion of Different Scenarios under ARB Test

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Fig. (4a-d) presents hypothetical scenarios of projecting MTTF from a 1200 V rated product, assuming zero failures after 1000 hours of stressing, for different , sample size and values. In Fig. 4(a), values are varied from to hours with a value of 1 and a sample size of 240 . In case of 0 failures out of 240 , the failure percentage ( ) at the stress condition is calculated using equivalent failure rate at a confidence level ( ), yielding a failure rate of . Substituting the value of and stress time hours into Eq. 1, is obtained, as indicated by the yellow circle. MTTF lines are drawn by connecting the yellow circle to different values. A higher value from positive gate bias TDDB suggests a longer intrinsic Gox lifetime, and thus a longer intrinsic Gox lifetime under used blocking condition (e.g. 800V) therefore can be achieved, as indicated by the red arrow. It is recommended that should be extracted by conducting TDDB tests at multiple voltages on the same group of devices whenever possible. Fig. 4(b) predicts MTTF for various stress voltages, values ranging from 1200 V to 1400 V with a value of hours and a value of 1 . With no failures in any of the three voltage scenarios values are extracted using Eq. 1, as shown by the yellow circles at and 1400 V . MTTF lines are drawn by connecting the value to the yellow dots. The model predicts that devices with no failures at 1400 V will have a longer MTTF lifetime under operating conditions compared to those with no failures at 1200 V , as indicated by the red arrow. Figure 4(c) illustrates the effect of increasing sample size on the lifetime plot, assuming zero failures in all cases. It is important to note here that a higher sample size does not necessarily lead to a proportionate increase in lifetime estimate under operating condition, as values remain constant at hours in this scenario. Finally, Fig. 4(d) shows the impact of different Weibull values, ranging from 1 to 2 , on lifetime projections. In case of ARB, the Weibull value should be validated with a longer test, as the value under blocking conditions may differ from that of gate bias-mediated TDDB test, especially since hot holes could contribute to the failure mechanism under ARB, as mentioned in Ref. [4].

[picture]

Fig. 4. MTTF ( ) lifetime plots are presented based on assumptions that 0 fails have been encountered after 1000 hours of stressing with (a) varying from to hours, , , sample size parts (b) three different stress conditions ranging from 1200-1400 V, hours, , sample size parts (c) variable sample sizes ranging from 240 to 1000, hours, , (d) varying from 1 to 2 while hours and sample size .

Fig. 4. MTTF ( ) lifetime plots are presented based on assumptions that 0 fails have been encountered after 1000 hours of stressing with (a) varying from to hours, , , sample size parts (b) three different stress conditions ranging from 1200-1400 V, hours, , sample size parts (c) variable sample sizes ranging from 240 to 1000, hours, , (d) varying from 1 to 2 while hours and sample size .

Shortcomings of this Method

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Fig. 5 shows certain shortcomings of this technique to project Gox lifetime under blocking from a single point data set. Consideration has been given to scenarios where blocking lifetime estimated from TDDB extracted value predicts favorable TTF numbers, but lifetime extracted from multiple stress voltages is influenced by an alternative failure mechanism, as shown in Fig. 5(a). In such cases, relying on a single data point may yield an overly optimistic off-state lifetime estimate. However, in such cases the dominant blocking failure mechanism likely will be unrelated to intrinsic Gox breakdown and should be tackled in a way beyond the scope of this study. This could be proven by appropriate failure analysis. Conversely, if the TDDB lifetime is adversely affected by a mechanism other than intrinsic Gox failures, then by virtue of lower value, the blocking lifetime estimation might get impacted and will project a rather pessimistic value. So, it is imperative to make sure that the value estimated from TDDB represents true intrinsic Gox failure mechanism. Interested readers may review Ref. [4] for a modeling work where extrinsic defects have been introduced to perform a defect mediated lifetime modeling under blocking conditions. Finally, this
paper focuses on the off-state reliability under stress with gate grounded. Similar analysis is possible for scenarios where negative (for n -channel MOSFET) works in tandem with for assessing blocking reliability.

[picture]

Fig. 5. Scenarios when using values from a TDDB test. a) Failure mechanism not related to intrinsic Gox breakdown, in which estimated lifetime is overly optimistic compared to full analysis with multiple stress voltages, b) Poor value estimated from TDDB for failures likely not related to intrinsic Gox breakdown can result a rather pessimistic blocking lifetime prediction.

Fig. 5. Scenarios when using values from a TDDB test. a) Failure mechanism not related to intrinsic Gox breakdown, in which estimated lifetime is overly optimistic compared to full analysis with multiple stress voltages, b) Poor value estimated from TDDB for failures likely not related to intrinsic Gox breakdown can result a rather pessimistic blocking lifetime prediction.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1022.83.pdf

In conclusion, we present a novel alternative modeling technique to project MOSFET intrinsic Gox lifetime under blocking from a single drain bias stress dataset with the aid of TDDB results done on a similar group of devices at the same temperature which is otherwise extremely time consuming or even impossible to model.

The authors would like to acknowledge the valuable discussion with J.W. McPherson in this regard.

References

The original version of this paper is available on https://www.scientific.net/KEM.1022.83.pdf

J. W. Palmour, L. Cheng, V. Pala, E. Van Brunt, D. J. Lichtenwalner, G-Y Wang, J. Richmond, M. O'Loughlin, S.-H. Ryu, S. T. Allen, A. A. Burk and C. Scozzie, Silicon Carbide Power MOSFETs: Breakthrough Performance from 900 V up to 15 kV , IEEE International Symposium on Power Semiconductor Device & IC's (ISPSD), (2014) 79-82.

D. A. Gajewski, B. Hull, D. J. Lichtenwalner, S.-H. Ryu, E. Bonelli, H. Mustain, G-Y Wang, S. T. Allen and J. W. Palmour, SiC Power Device Reliability, IEEE International Integrated Reliability Workshop, (2016) 29-34.

D. J. Lichtenwalner, S. Sabri, E. V. Brunt, B. Hull, S.-H. Ryu, P. Steinmann, A. Romero, S. Ganguly, D. A. Gajewski, S. Allen and J. W. Palmour, Accelerated Testing of SiC Power Devices, IEEE International Integrated Reliability Workshop, (2020) 1-6.

E. Van Brunt, D. J. Lichtenwalner, J. H. Park, S. Ganguly and J. W. McPherson, Lifetime Modeling of the MOS Interface in the HTRB Condition Under the Influence of Screw Dislocations, IEEE International Reliability Physics Symposium (IRPS), (2023) 1-7.

P. Moens, F. Geenen, M. Avramenko and G. Gomez-Garcia, On the Intrinsic and Extrinsic Reliability Challenges of SiC MOSFETs, IEEE International Reliability Physics Symposium (IRPS), (2024) 1-7.

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Keywords Index

4

4 H -sic Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

4 H -sic Mosfet Three Level Pulses to Investigate Gate Switching Instability

4h-silicon Carbide (sic) Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

A

A-face TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

Accelerated Htrb Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Accelerated Reverse Bias (arb) Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

B

Bottom Oxide Protection Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

C

C-v Curve SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Calibration TCAD Model Parameter Calibration Strategy for SiC MOSFET

Capacitance SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

D

Dft DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

E

Edge Termination SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Edge-termination Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Etched Jte Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

G

Gate Oxide Reliability Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Gsi Three Level Pulses to Investigate Gate Switching Instability

Gss Three Level Pulses to Investigate Gate Switching Instability

Guard Ring Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

I

Implantation Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Interface Traps Three Level Pulses to Investigate Gate Switching Instability

J

Junction Termination Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

L

Lateral Mosfet TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

Lifetime Modeling Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

M

Manufacture Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Mobility Model TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

Model Parameter TCAD Model Parameter Calibration Strategy for SiC MOSFET

Mosfet Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency; Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

P

Pece DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Porous 4h-sic DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Pulsed Power Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

S

Schottky Diode SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Short-circuit TCAD Model Parameter Calibration Strategy for SiC MOSFET

SiC Mosfet SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

SiC Mosfets Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

SiC Power Mosfet TCAD Model Parameter Calibration Strategy for SiC MOSFET

Silicon Carbide Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Simulation Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Surface Termination DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Surge Current SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

T

Tcad TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

Tcad Simulation Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension; TCAD Model Parameter Calibration Strategy for SiC MOSFET

Thermal Capacitance SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Threshold Voltage Three Level Pulses to Investigate Gate Switching Instability

Thyristor Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

Trench Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Trench-gate Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

V

Vth-drift Three Level Pulses to Investigate Gate Switching Instability

W

Wafer Thinning SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Authors Index

A

Adachi, K. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

B

Bashar, E. On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

Biswas, A. Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Breglio, G. SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Bu, J. On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

D

Daliento, S. SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Damcevska, J. SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Dimitrijev, S. SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Dixit, H. TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

F

Floros, K. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Fukui, Y. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

G

Gajewski, D. Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Gammon, P. On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

Ganguly, S. Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

H

Haasmann, D. SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Han, J. SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Hassdorf, R. Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

Hoffmann, K. Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

Hosseinzadehlish, M. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Hull, B. Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

I

Iijima, A. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Irace, A. SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

J

Jahdi, S. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Jang, S. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Jiang, Y. On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

K

Kagawa, Y. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Kim, D. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Kim, J. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency; TCAD Model Parameter Calibration Strategy for SiC MOSFET

Kim, S. TCAD Model Parameter Calibration Strategy for SiC MOSFET

Kim, Y. TCAD Model Parameter Calibration Strategy for SiC MOSFET

Kimura, Y. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Kono, K. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Kotra, K. Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

L

Laird, I. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Lee, C. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

Lee, H. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency; TCAD Model Parameter Calibration Strategy for SiC MOSFET

Lee, J. TCAD Model Parameter Calibration Strategy for SiC MOSFET

Lichtenwalner, D. TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs; Lifetime Modeling of MOS Based SiC Vertical Power Devices under High Voltage Blocking Stress

Liu, Y. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Lüdtke, I. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

M

Maresca, L. SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Matacena, I. SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Mellor, P. The Quadrant Operation of Generation SiC MOSFETs: Recovery Charge & Bipolar Degradation

Mudiyanselage, D. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

N

Nah, H. TCAD Model Parameter Calibration Strategy for SiC MOSFET

P

Perazzi, M. DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Pfusterschmied, G. DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

R

Renz, A. On the Characterization of -SiC PiN Diodes and JFETs for their Use in High-Voltage Bidirectional Power Devices

Riccio, M. SiC MOSFETs C-V Capacitance Curves with Negative Biased Drain

Ryu, S. TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

S

Scharnholz, S. Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension

Schmid, U. DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Scholten, D. Three Level Pulses to Investigate Gate Switching Instability

Scholze, A. TCAD Modelling of Anisotropic Channel Mobility in 4H-SiC MOSFETs

Sung, W. Optimizing 1.2 kV SiC Trench MOSFETs for Enhanced Performance and Manufacturing Efficiency

T

Tanner, P. SiC Schottky-Barrier Diode Without Ion-Implanted P-Type Regions

Tominaga, T. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

U

Uschmann, J. Three Level Pulses to Investigate Gate Switching Instability

Y

Yamamoto, F. Novel SiC MOSFET Edge-Termination Structure for Electric Field Relaxation Using an Oxide Film Along the Trench Surface

Yang, T. DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Z

Zellner, C. DFT Calculations on the Termination of -SiC Non-Polar Surfaces during Photoelectrochemical Pore Formation

Zuvic, M. Design Parameters Impact on Electrical Characteristics of 4H-SiC Thyristors with Etched Junction Termination Extension