Characteristics of MOSFETs

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Characteristics of MOSFETs

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Sócientific.Net

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

All rights reserved. No part of the contents of this publication may be reproduced, processed or transmitted in any form or by any means without the written permission of the publisher.

Trans Tech Publications Ltd
Seestrasse 24c
CH-8806 Baech
Switzerland
https://www.scientific.net

Volume1021 of
Key Engineering Materials
ISSN print 1013-9826
ISSN web 1662-9795

Full text available online at https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Distributed worldwide by
Trans Tech Publications Ltd
Seestrasse 24c
CH-8806 Baech
Switzerland
Phone: +41 (44) 9221022
e-mail: sales@scientific.net

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-04

Online:
2025-09-05

Preface

The original version of this paper is available on https://www.scientific.net/KEM.1021.-1.pdf

This special edition is devoted to recent scientific and engineering advances, as well as technological solutions, in the field of compound semiconductor power electronic devices, with emphasis on the unique properties and application potential of wide bandgap semiconductors. The contributions encompass applied research on device concepts and architectures, with particular attention to bipolar junction transistors, MOSFETs, and the characteristics of body diodes in power electronic structures.

The edition also highlights innovations in bonded substrate technologies and the design of effective high-voltage gate structures, both of which are central to improving next-generation power electronics' performance, reliability, and efficiency. By integrating perspectives from compound semiconductor development, device engineering, and system-level integration, this publication provides a comprehensive overview of the state of the art in the field of silicon carbide power electronics.

As a valuable resource for researchers, engineers, and practitioners, this special edition presents a balanced account of the scientific foundations together with the engineering and technological solutions that underpin the advancement and deployment of SiC-based power devices.

Table of Contents

Preface

Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Pierre Brosselard, Brenda Fosso-Sob, Dominique Planson, Pascal Bevilacqua, Camille Sonneville, Mihai Lazar, Bertrand Vergne, Sigo Scharnholz, Hervé Morel

Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Naoki Shikama, Kazuya Ishibashi, Hiroki Niwa, Takanori Tanaka, Hiroyuki Amishiro, Akifumi Imai, Katsutoshi Sugawara, Yasuhiro Kagawa, Akihiko Furukawa

Evaluation of Switching Performances and Short Circuit Capability of a

Luca Maresca, Vincenzo Terracciano, Alessandro Borghese, Marco Boccarossa, Michele Riccio, Giovanni Breglio, Stephan Wirths, Andrea Irace

Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Shane R. Stein, Suman Das, Ayan K. Biswas, Daniel J. Lichtenwalner, Sei Hyung Ryu

Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Pavan Vudumula, Yu Chieh Chien, Abdul Hannan Yeo, Lakshmi Kanta Bera, Umesh Chand, Voo Qin Gui Roth, Surasit Chung, Navab Singh, Yee Chia Yeo

Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Ahmad Abbas, Cyrille Le Royer, Romain Laviéville, Jérôme Biscarrat, Guillaume Gelineau, Frédéric Allibert, Edwige Bano, Philippe Godignon

Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Virendra Kotagama, Arne Benjamin Renz, Kyrylo Melnyk, G.W.C. Baker, Vishal Ajit Shah, Marina Antoniou, Peter Michael Gammon

Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Yuta Higashi, Seiji Ishikawa, Kunihide Oozono, Hiroshi Sezaki, Motoki Kobayashi, Hidetsugu Uchida, Mitsuo Okamoto, Shinsuke Harada, Kazutoshi Kojima, Tomohisa Kato, Yasunori Tanaka

-SiC VDMOSFET Having On-Current Improvement

Yuniarto Widjaja, Valerii Nebesnyi, Asen Asenov, Nikolas Xeni, Ismail Topaloglu, Djamel Bensouiah, Servin Rathi, Robert Young, Leo Laborie, Yunyi Qi, Martin Bell, David T. Clark

Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

Chengjun Shen, Saeed Jahdi, Mana Hosseinzadehlish, Phil Mellor, Konstantinos Floros, Ingo Lüdtke

Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

Mohamed Torky, Woongje Sung

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 1-6

doi: 10.4028/p-T0Vjdb

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-08-21

Revised:
2025-09-01

Accepted:
2025-09-01

Online:
2025-09-05

Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

Pierre Brosselard , Brenda Fosso-Sob , Dominique Planson , Pascal Bevilacqua , Camille Sonneville , Mihai Lazar , Bertrand Vergne , Sigo Scharnholz and Hervé Morel

INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale Lyon, CNRS, Ampère, UMR-5005, F-69621, France

Light, Nanomaterials, Nanotechnologies, L2n, UMR CNRS7076, Université de Technologie de Troyes, 10004, Troyes, France

ISL, French-German Research Institute of Saint Louis, 5 rue Général Cassagnou, 68301 Saint Louis, France

pierre.brosselard@insa-lyon.fr, brenda.fosso-sob@insa-lyon.fr, dominique.planson@insa-lyon.fr, pascal.bevilacqua@insa-lyon.fr, camille.sonneville@insa-lyon.fr, mihai.lazar@utt.fr,

Keywords: 4 H -SiC, Bipolar Junction Transistor, Electrical Characterization, High Voltage

Abstract

In this paper, the static and dynamic characterization of a High Voltage ( 10 kV ) Bipolar Junction Transistor (BJT) is presented. Using a high-voltage source in vacuum conditions, a breakdown voltage of 11 kV was measured. Results showed that both large and small BJTs exhibit similar on-state resistance per unit area and collector current density of 55 A.cm . The current gain increases with a decrease in temperature, indicating reduced charge carrier recombination at lower thermal energies. Also, BJT have been characterized in switching mode at 1 kV . The study concludes that 4 H -SiC BJT demonstrates promising electrical performance for high-efficiency applications in harsh environments.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

4H-SiC Bipolar Junction Transistors (BJTs) offer significant advantages for high-voltage and hightemperature applications due to their superior characteristics, including low on-state resistance and elevated breakdown voltage [1]-[2]. These devices are highly efficient in various sectors. However, their performance can be affected by temperature change. Therefore, it is very interesting to study its behavior in extreme conditions, especially in high-power applications [3]-[4]. After a short description of the BJT structure, electrical characterization in static mode for a temperature range from up to will be demonstrated. This work reports the switching characteristics of the BJT using a double source test bench which involves providing controlled input pulses to the base while monitoring the response at the collector.

BJT's Structure

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

The BJTs were designed and fabricated on a wafer with an epilayer of thick and doping concentration of (Fig.1). Mesa with JTE (Junction Termination Extension) and JTE rings has been implemented for the edge termination. Thermal oxidation followed by the deposition of several LPCVD (Low-Pressure Chemical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition) layers (yellow layer in Fig. 1) and also a thick polymide layer (brown layer in Fig. 1) is used for the device passivation. Three unique configurations of BJTs, each with varying finger length and active area, designed to enhance their electrical performance. The configurations include two distinct finger lengths of and , these lengths were paired with active area, specifically for large devices and for small

BJTs, as detailed in Table 1. A maximum breakdown voltage of 11 kV was obtained in vacuum conditions with a high-voltage source [5].

Fig.1. Cross-section of the studied BJT
Table 1. Summary of the different BJT configurations, square dies

Fig.1. Cross-section of the studied BJT Table 1. Summary of the different BJT configurations, square dies

Finger Length (μm) | Die area (mm²)
420 | 2.12
420 | 15.6
640 | 15.6

Experimental Setup for Static Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

The setup involves the static characterization of BJTs using a B1505A, capable of handling up to 20 A in pulsed mode for the collector, 1 A for the base, and 3 kV in blocking mode, alongside a Thermal Conditioner Thermonics T2500/300E for temperature control from up to . Three samples were characterized with their respective finger length and active area. Measurements include applying a voltage sweep V CE and measuring IC for different fixed values of IB from 0.1 A to 1 A to obtain the output characteristic curves. By analyzing these curves, we can assess the transistor behavior in different operating regions and extract key parameters like, current gain, b.

Results and Analysis of the static characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

The small and large BJTs exhibit similar on-state resistance per unit area as shown in Fig. 2 Both devices achieved approximately 55 A.cm for collector current density with comparable base-current densities, to , respectively corresponding to different base currents and 0.5 A respectively). This observation suggests that the active area does not significantly impact the electrical characteristics concerning current density. Therefore, regardless of the physical size of the BJTs, their performance in terms of current density remains the same.
From Fig.3, we can observe that the current gain, b , is very similar between large and small BJTs ( finger length, and finger length, ). A similar trend is noticed between large BJTs with different finger length ( and ), both having a area but there are measured on two different wafers.

Fig. 2. for different at for a small (open symbol) and large (closed symbol) BJT, finger length of

Fig. 2. for different at for a small (open symbol) and large (closed symbol) BJT, finger length of

Fig. 3. Extracted for 4 different BJTs (finger length and area) at

Fig. 3. Extracted for 4 different BJTs (finger length and area) at

Fig. 4. Extracted obtained with a B1505A (quasi static measurements) for the large BJT (finger length , from triangular symbol on Fig. 2) for a temperature range of to

Fig. 4. Extracted obtained with a B1505A (quasi static measurements) for the large BJT (finger length , from triangular symbol on Fig. 2) for a temperature range of to

Additionally, the current gain of the large BJTs tends to increase with decreased temperature as seen in Fig. 4. This increase is as a result of the reduced recombination rate of charge carriers due to lower thermal energy, which means fewer charge carriers recombine, more contribute to the current. It could be also due to higher ionization of p-type doping base. Consequently, a smaller base current is required to control a given collector current, effectively enhancing the transistor's amplification capacity. This implies that at lower temperatures, the BJTs become more efficient in amplifying the base current.

Experimental Setup for Switching Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

Fig. 5. Double pulse test schematic diagram for switching characteristics on the BJTs

Fig. 5. Double pulse test schematic diagram for switching characteristics on the BJTs

To investigate the switching characteristic of the BJTs, a double pulse test circuit was configured as per the provided schematic in Fig. 5. The setup includes a voltage supply (VIN from 100 V to 1000 V ) a base driver is connected to the base of the SiC BJTs. A fast recovery diode and an inductor are used to manage the switching transitions and energy storage respectively. The different voltages (Base, Collector and Emitter), the Base current using a current probe and the collector current using a shunt resistance are measured at each VIN step to analyze the BJT switching performance.

Results and Analysis of the Switching Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

Fig. 6 shows the behavior of and respect to time for the switching characteristics of the BJT samples. Ic exhibits a sharp rise as the BJT turns on due to the inductance charging, reaching higher peaks with increased However, the current starts dropping from its peak indicating that the base current is insufficient to maintain the BJT in saturation mode, leading to a transition towards the linear mode. This is evident in the VCE graph in Fig. 7 where V CE drops rapidly during the initial turn-on and then stabilizes at a higher voltage as the device exhibit saturation.

Fig. 6. Ic and versus time for various steps

Fig. 6. Ic and versus time for various steps

Fig. 7. Vee versus time for various VIN steps

Fig. 7. Vee versus time for various VIN steps

Fig. 8 shows how the current gain ( ) initially spikes, indicating strong carrier injection but then decreases as a reflection of Ic due to the linear mode.

Fig. 8. Extracted versus time for various VIN steps

Fig. 8. Extracted versus time for various VIN steps

Fig. 9. Extracted for 3 different BJTs (finger lengths)

Fig. 9. Extracted for 3 different BJTs (finger lengths)

Fig. 9 shows the variation of extracted versus time for the 3 different large BJTs. A similar is obtained between these 3 different BJTs. The values (17 and 18) are very similar to those obtained in the static mode (Fig. 3, 15 and 18). We can therefore conclude that the finger length and size have no impact on the current gain of the device even if it extracted in static or dynamic mode.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

This paper presents the static and dynamic characteristics of BJTs, which demonstrates promising electrical performance, making it suitable for high-efficiency applications in harsh environments and their performance improves at lower temperatures due to enhanced carrier dynamics. Similar extracted have been obtained for both static and dynamic mode even with different finger lengths and areas of the BJTs.

Acknoledgments

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

Authors thank the French Research National Agency (ANR) for financial support of HV-PhotoSw: ANR-18-CE05-0020-01

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.1.pdf

B. Asllani, P. Bevilacqua, H. Morel, D. Planson, L. V. Phung, B. Choucoutou, T. Lagier, and M. M. Guyennet "Static and Switching Characteristics of 10 kV -class Silicon Carbide Bipolar Junction Transistors and Darlingtons" Materials Science Forum Vol. 1004 (2020) pp 923-932

M. Nawaz, N. Chen, F. Chimento and L. Wang "Static and Dynamic Characterization of HighPower Silicon Carbide BJT Module" 2014 IEEE Energy Conversion Congress and Exposition (ECCE), Pittsburgh, PA, USA, 2014, pp. 2824-2831

M. Hosseinzadehlish, S. Jahdi, C. Shen, X. Yuan, I. Laird, O. Alatise, J. O. Gonzalez "Impact of Temperature and Base Bias Stress on the Static Characteristic of Silicon and 4H-SiC NPN Vertical BJTs" PCIM Europe 2023; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2023, pp. 1-9

M.M.R. Ahmed, N-A.Parker-Allotey, P.A. Mawby, M. Nawaz and C. Zaring "Characterization of the Static and Dynamic Behavior Of A SiC BJT" 2008 13th International Power Electronics and Motion Control Conference, Poznan, Poland, 2008, pp. 2472-2477

A. Ammar, M. Lazar, B. Vergne, S. Scharnholz, L. V. Phung, P. Brosselard, D. Tournier, C. Sonneville, C. Raynaud, M. Zielinski, and al. "Design Fabrication and characterization of 10 KV 4H-SiC BJT for Phototransistor Target. 2023 - Romanian Journal of Information Science & Technology - Vol.26, , pp 193-204

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 7-15

doi: 10.4028/p-47sFxF

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-05

Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

Naoki Shikama , Kazuya Ishibashi , Hiroki Niwa , Takanori Tanaka , Hiroyuki Amishiro , Akifumi Imai , Katsutoshi Sugawara , Yasuhiro Kagawa and Akihiko Furukawa

¹Power Device Works, Mitsubishi Electric Corporation,1-1-1 Imajuku-higashi, Nishi-ku, Fukuoka-shi, Fukuoka, 819-0192, Japan

Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki-shi, Hyogo, 661-8661, Japan

Shikama.Naoki@df.MitsubishiElectric.co.jp, Ishibashi.Kazuya@ak.MitsubishiElectric.co.jp, Niwa.Hiroki@dp.MitsubishiElectric.co.jp, Tanaka.Takanori@cb.MitsubishiElectric.co.jp, Amishiro.Hiroyuki@cb.MitsubishiElectric.co.jp, Imai.Akifumi@ys.MitsubishiElectric.co.jp, Sugawara.Katsutoshi@ea.MitsubishiElectric.co.jp, Kagawa.Yasuhiro@cj.MitsubishiElectric.co.jp, Furukawa.Akihiko@df.MitsubishiElectric.co.jp

Keywords: MOSFET, body diode, bipolar degradation, proton implantation, electrical characteristics

Abstract

We investigated how proton implantation influences electrical characteristics of the 4 H SiC MOSFETs. Bipolar degradation in SiC is one of the key issues to be solved for utilizing the bipolar operation in SiC power devices. Its suppression with the proton implantation technique has recently been reported. If we can apply such a new technique being involved for realizing reliable SiC MOSFETs, it would give us great merit to take advantage of the body diode. However, few study has been reported of proton implanted SiC MOSFETs, to our knowledge. Thus, we fabricated 4,000 chips, applied current stress to their body diodes and subsequently evaluated them to verify statistically any effectiveness on the suppression of the bipolar degradation as well as on the electrical performance of MOSFET in order to consider its technological applicability to their mass production process. We found that proton implantation not only has little influence on the static electrical characteristics of the MOSFETs but also improves the switching characteristics.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

Silicon carbide ( SiC ) is the candidate as an alternative material for Si in switching applications. An external Schottky barrier diode (SBD) has been used as a free-wheeling diode in anti-parallel configuration with a MOSFET in designing typical switching applications. Body diode has also been widely recognized and utilized as free-wheeling diode instead of SBD to realize cost reduction and shrinkage of the systems comprising of the SiC power devices.

Bipolar degradation in SiC is one of the key issues to be solved for utilizing the bipolar operation in SiC power devices like a body diode. The recombination energy of electron-hole pairs in the bipolar operation mode expands the stacking faults (SFs) from basal plane dislocations (BPDs). The typical method for its prevention has been reported [1] by using a heavily N-doped SiC epitaxial buffer layer. However, such a layer requires precise control of its thickness and uniform impurity doping throughout the wafer, which are often challenging. Therefore, there has been a need to establish any other methods for overcoming this troublesome issue.

It has been recently reported that the suppression of the expansion of the SFs could be realized by (proton) implantation [2-4]. The proton implantation as much as or more was shown to be effective. If we can apply such a new technique for the fabrication of the SiC MOSFETs, it would provide the way to take advantage of the body diode in the SiC MOSFET. It is important to verify that proton does not have a side effect on the electrical characteristics of the MOSFET.

However, few study has been reported on fabrication of proton implanted SiC MOSFETs, to our knowledge. Thus, we fabricated huge numbers (about 4,000 chips) of MOSFETs, applied current stress to their body diodes and evaluated them to discuss possibility for the mass production and verify the bipolar degradation statistically.

Method

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

Figs. 1 (a) and (b) show the cross-sectional schematic of the SiC MOSFETs with and without proton implanted layer. We used n-type wafers with an epitaxial conversion layer which was grown to convert BPDs to threading edge dislocations (TEDs), and a drift layer whose thickness was . The off-cut angle of the wafer was . Fig. 2 shows an experimental flow chart of the device fabrication and evaluation processes. It should be noted that the proton implantation was performed before the activation annealing process. The dose of proton are and . We also fabricated MOSFETs without proton for comparison. Number of the total measured chips was about 4,000 . After the device fabrication, continuous current stress (typically, and ) was applied to the body diodes to evaluate the prevention of the expansion of the SFs on the bipolar degradation. Typical one chip data were plotted for each condition in the following Figs. 3-6 since all measured samples showed the same trend.

Fig. 1. Schematics of SiC MOSFETs (a) with proton implanted layer and (b) without proton implanted layer.

Fig. 1. Schematics of SiC MOSFETs (a) with proton implanted layer and (b) without proton implanted layer.

Fig. 2. Flow chart of the experiment.

Fig. 2. Flow chart of the experiment.

Fig. 3. characteristics for the SiC MOSFETs with various proton dose of (a) at and (b) at . I and denote drain-source current and drain-source voltage, respectively.

Fig. 3. characteristics for the SiC MOSFETs with various proton dose of (a) at and (b) at . I and denote drain-source current and drain-source voltage, respectively.

Fig. 4. characteristics for the SiC MOSFETs with various proton dose of (a) at and (b) at .

Fig. 4. characteristics for the SiC MOSFETs with various proton dose of (a) at and (b) at .

Fig. 5. characteristics for the SiC MOSFETs with various proton dose of (a) at and (b) at . IsD and denote source-drain current and source-drain voltage, respectively.

Fig. 5. characteristics for the SiC MOSFETs with various proton dose of (a) at and (b) at . IsD and denote source-drain current and source-drain voltage, respectively.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

Figs. 3 (a) and (b) show the output characteristics of the MOSFETs measured at and , respectively. All the curves are almost overlapped, which indicates the output characteristics of the MOSFET with proton is compatible to that without proton. Figs. 4 (a) and (b) show the drain-source leakage characteristics of the SiC MOSFETs measured at and , respectively. The increase of the leakage current due to proton implantation is not observed. Figs. 5 (a) and (b) show the 3rd quadrant characteristics of the SiC MOSFETs measured at and , respectively. Although all the samples operated as body diodes properly, their behavior is slightly different. At room temperature, differential on-resistance of the samples with proton, as a whole, is higher than that of the sample without proton (Fig. 5 (a)).

Fig. 6. characteristics for the SiC MOSFETs of (a) without proton, (b) with a proton dose of and (c) with a proton dose of , respectively. The data of Figs. 5 are replotted from the view of the temperature dependence.

Fig. 6. characteristics for the SiC MOSFETs of (a) without proton, (b) with a proton dose of and (c) with a proton dose of , respectively. The data of Figs. 5 are replotted from the view of the temperature dependence.

At high temperature, quantitative difference between the samples with proton in the 3rd quadrant characteristics is clearly observed (Fig. 5 (b)), which implies that the effect of the proton is remarkable with the increasing of dose. Here, we suppose that the increase of the differential on-resistance of the samples with proton in the 3rd quadrant characteristics is insignificant as a switching device. It hardly affects the total loss because a body diode is conducted only in the dead time under normal pulse width modulation (PWM) operations. Figs. 6 (a)-(c) show the 3rd quadrant characteristics of the MOSFETs at each proton dose. The body diode without proton shows increase of the current as the temperature increases (Fig. 6 (a)). However, as the dose of proton increases, such an increase of the current is shown to gradually suppressed. Particularly, temperature dependence was almost suppressed with a proton dose of (Fig. 6 (c)). Generally, more forward current flows at high temperature than at room temperature due to two effects:(i) the increase of the carrier density (particularly, minority carrier density) and (ii) the reduction of forward voltage ( ) derived from the suppression of the potential barrier. As shown in Figs. 5 (a) and (b), the voltage, where current begins to flow, hardly depends on the dose of proton at each temperature. It implies that the latter effect is not suppressed, and the former effect is suppressed by proton implantation. This will be discussed later.

Fig. 7. The ratio of the degraded MOSFETs after current stress in each proton condition. The numbers of the tested samples are and 823 ( ), respectively.

Fig. 7. The ratio of the degraded MOSFETs after current stress in each proton condition. The numbers of the tested samples are and 823 ( ), respectively.

It is well known that the expansion of the SFs in the bipolar operation induces the increase of onresistance of the MOSFET [5]. We evaluated how the on-resistance of MOSFET changed by the current stress on the body diode (Fig. 7). We defined the samples as "degraded" ones whose onresistance increased over after the current stress. The ratio of the degraded MOSFETs is inclined to show lower value with increasing the dose of proton, which is consistent with the previous report that claims suppression of the expansion of SFs by proton implantation [2]. With a proton dose of , degraded MOSFET ratio becomes about , which is the half value of that without proton. This result suggests that the bipolar degradation would be more suppressed by further increase
in the proton dose. Here, it was reported that proton of more than hardly decreases the SFs density [2], which implies that proton of might be enough to prevent the SFs from being expanded.

We also evaluated switching characteristics of the body diode. Figs. 8 (a) and (b) show the reverse recovery characteristics of the body diode with and without proton at . The switching characteristics were measured with the double pulse testing method, and the supply voltage and switching drain-source current are 760 V and 380 A , respectively. The gate voltage of the upper arm and the lower arm are -5 V and , respectively. The of the sample without proton reaches zero at about and clear surge voltage was observed. By implanting proton, of the sample with proton reaches almost zero at , and the surge voltage became vague. Reverse recovery charge ( ) and surge voltage increase ( ) are defined as follows,

Fig. 8. Reverse recovery waveform of the body diode for (a) and (b) , respectively.

Fig. 8. Reverse recovery waveform of the body diode for (a) and (b) , respectively.

Table 1. Comparison of and estimated from the reverse recovery waveform of the body diode without proton and with a proton dose of (Figs. 8 (a) and (b)).

Proton | Qrr [μC] | ΔV [V]
w/o | 4.5 | 360
1×10¹⁴ cm⁻² | 1.9 | 14

where and are the times when becomes zero for the first time and the second time in the reverse recovery waveform, respectively. denotes the voltage that takes the largest value, and is the saturated voltage. As shown in Table 1, both and successfully decreased by and with a proton dose of , respectively. Our findings are that the implantation of proton not only has an effect on suppressing bipolar degradation but on reducing and , which is a great advantage for reducing recovery loss and safe operation of the MOSFETs.

Now the origin of these effect is discussed here. Secondary ion mass spectrometry (SIMS) measurement revealed that implanted proton disappeared after the thermal annealing [3], which suggests that the existence of the hydrogen is not intrinsic. Point defect is known to be generated when the proton is implanted to an n-type , whose typical one is center ( ) which acts as a lifetime killer [6-9]. Both experimental and theoretical research revealed that it is stable at high temperature [6,10]. We estimate that the recombination center derived from the point defect decreases the lifetime of carrier inside the epilayer, resulting in a decrease in . Such a hypothesis can explain well the result of the 3rd quadrant characteristics. Proton implantation could reduce the lifetime of carrier and suppress conductivity modulation in the bipolar operation mode, which increases differential on-resistance. The disappearance of the temperature dependence, as shown in Fig. 6 (c), could be attributed to the suppression of the carrier increase at high temperatures via the recombination center. Although further study by using a deep level transient spectroscopy (DLTS) measurement would be needed, we estimate that the generation of the point defect derived from the proton implantation would be the key that reduce the bipolar degradation effect as well as obtaining favorable recovery characteristics of the MOSFET.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

We fabricated huge numbers (about 4,000 chips) of proton implanted 4H-SiC MOSFETs, applied current stress to their body diodes and subsequently evaluated DC electrical characteristics and switching characteristics of them. We found that not only proton implantation has little influence except for the electrical characteristics as the 3rd quadrant characteristics on the DC characteristics but also it improves the switching characteristics. It could be related to the point defect introduced by proton implantation process. Evaluation of the on-resistance of the MOSFETs before and after the current stress on the body diode revealed that the increase of the resistance due to the expansion of the SFs could be suppressed. Establishing a suitable proton implantation condition will surely open the way for its introduction to the future mass production of the bipolar-tolerant and reliable SiC MOSFETs.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

We would like to thank H. Hatta of Mitsubishi Electric Corp. for his fruitful discussion and technical support of measurement.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.7.pdf

T. Tawara, T. Miyazawa, M. Ryo, M. Miyazato, T. Fujimoto, K. Takenaka, S. Matsunaga, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto and H. Tsuchida, J. Appl. Phys. 120, 115101 (2016).

M. Kato, O. Watanabe, T. Mii, H. Sakane and S. Harada, Sci. Rep. 12, 18790 (2022).

S. Harada, T. Mii, H. Sakane and M. Kato, Sci. Rep. 12, 13542 (2022).

M. Kato, S. Harada and H. Sakane, Jpn. J. Appl. Phys. 63, 020804 (2024).

M. Skowronski and S. Ha, J. Appl. Phys. 99, 011101 (2006).

T. Dalibor, G. Pensl, H. Matsunami, T. Kimoto, W. J. Choyke, A. Schöner and N. Nordell, Phys. Status Solidi A 162, 199 (1997).

T. Dalibor, C. Peppermüller, G. Pensl, S. Sridhara, R. P. Devaty, W. J. Choyke, A. Itoh, T. Kimoto and H. Matsunami, Inst. Phys. Conf. Ser. 142, 517 (1996).

P. B. Klein, B. V. Shanabrook, S.W. Huh, A. Y. Polyakov, M. Skowronski, J. J. Sumakeris and M. J. O'Loughlin, Appl. Phys. Lett. 88, 052110 (2006).

K. Danno, D. Nakamura and T. Kimoto, Appl. Phys. Lett. 90, 202109 (2007).

C. Zechner, M. Tanaka, K. Shimai, N. Zographos, S. Kanie and S. Tsuboi, J. Appl. Phys. 132, 035702 (2022).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 17-23

doi: 10.4028/p-Mc0tPH

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-12

Revised:
2025-06-23

Accepted:
2025-06-23

Online:
2025-09-05

Evaluation of Switching Performances and Short Circuit Capability of a

The original version of this paper is available on https://www.scientific.net/KEM.1021.17.pdf

Luca Maresca , Vincenzo Terracciano , Alessandro Borghese , Marco Boccarossa , Michele Riccio , Giovanni Breglio , Stephan Wirths , and Andrea Irace

Dept. of Electrical Engineering and Information Technologies, University Federico II, Naples, Italy

Hitachi Energy, Semiconductors, CH-5600 Lenzburg, Switzerland

luca.maresca@unina.it, vincenzo.terracciano@unina.it, alessandro.borghese@unina.it, marco.boccarossa@unina.it, michele.riccio@unina.it, breglio@unina.it, stephan.wirths@hitachienergy.com, handrea.irace@unina.it

Keywords: Gate All Around, SiC, Pillar, TCAD, Short-Circuit, Wide Bandgap Semiconductor.

Abstract

Silicon Carbide (SiC) is a leading material for power electronics due to its high critical electric field, rapid switching, and high-temperature capabilities. This study delves into the dynamic and thermal performance of a novel SiC power MOSFET, utilizing an innovative vertical Gate All Around (GAA) design. Through detailed 2D TCAD simulations in cylindrical coordinates, the device's behavior is analyzed across various pillar radii and temperatures. Results indicate that while reducing the pillar radius does not improve the on-resistance (Ron), a 500 nm radius is required to achieve Ron . Additionally, larger pillar radii significantly increase capacitance. The device exhibits strong switching performance comparable to commercial counterparts and benefits from the absence of a termination region. However, its short-circuit ruggedness is compromised, particularly in structures with smaller pillar radii, where delayed thermal runaway failure is observed. Notably, for a 20 nm radius, the temperature peak occurs on the Drain side, a deviation from typical behavior. Despite its advantages, the design's low short-circuit capability remains a limitation.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.17.pdf

The next generation of power electronic devices must deliver high energy efficiency and power conversion density to accommodate the market requirements. Silicon Carbide ( SiC ) is emerging as the leading semiconductor for these applications due to its superior critical electric field, fast switching speeds, and ability to operate at high temperatures. SiC's impressive performance, compared to traditional silicon ( Si ), drives ongoing efforts to improve SiC device quality. With its wide bandgap, high electron mobility, and excellent thermal conductivity [1], SiC offers significant advantages, although several technological challenges remain to fully harness its potential. In terms of device design, literature presents various approaches for creating high-voltage SiC MOSFETs, primarily focusing on either planar or trench gate designs for the active section. The bulk section typically utilizes either a constant doping profile drift layer or super-junction and semi-super-junction methods. However, all these designs require a termination region, which is crucial in determining the device's breakdown voltage (BV) and occupies a significant portion of the device area, thus contributing substantially to the overall cost. Moreover, the termination region introduces challenging aspects related to the passivation layers that may affect the reliability of the device.

In this work, the recently introduced SiC power MOSFET [2], based on an innovative vertical Gate All Around (GAA) concept, is further explored with a focus on its dynamic and thermal performances. The study begins with a thorough evaluation of the device's thermal behavior, providing crucial insights into its operational stability under various conditions. Following this, an extensive series of TCAD simulations is conducted to examine the device's performance during switching operations and under short-circuit conditions. These simulations aim to assess the potential advantages and limitations of the GAA design, contributing valuable data for optimizing future SiC power MOSFET technologies.

The Proposed Device

The original version of this paper is available on https://www.scientific.net/KEM.1021.17.pdf

A sketch of the proposed device is reported in Fig. 1a. The overall device is composed by many Ntype SiC cylindrical pillars surrounded by silicon dioxide (the single cell), in cellular parallel mode connection. The pillars are grown starting from a Si substrate, connecting all pillars to the same Drain region. The available technology, the selective epitaxial growth of SiC on masked Si bulk (See [3]), allows the growth of the . In this work it is assumed that the pillars are in , to evaluate the best performances with this design. The top P-Body layer is surrounded by the Gate oxide layer, connected to the Gate contact. In this work the Gate oxide in made by Silicon Dioxide to evaluate the performances of the device with standard materials. To the active area of the device contributes both the pillar and the surrounded oxide. Therefore, in this work the ratio among the pillar area and oxide area will be calculated from the geometry reported in Fig. 1b, where and Toxide1. Further design details are reported in Table I. The geometry of the single pillar (See Fig. 1b) allows a suitable TCAD simulation by using cylindrical coordinates, therefore a 2D mesh is considered to evaluate the performance of the 3D structure. Standard physical models are adopted to run numerical simulations and only fixed charges are considered at the interface. When the radius of the proposed structure is lower than tens of nanometers, a very accurate description of the channel mobility is mandatory [1], therefore the MLDA model is used to model the channel electron density by quantum mechanical equations [5]. The length of the Drift region (L) is to allow a Breakdown Voltage (BV) of about 1300 V , without the presence of a termination region. Finally, all the numerical results reported in this work refer to a structure where the Source region is connected to the P-Body region through an ohmic contact, laying on the symmetry axes.

Fig. 1 a) A sketch of the overall SiC GAA MOSFET design concept. b) A sketch of the TCAD structure and geometrical parameters.

Fig. 1. a) A sketch of the overall SiC GAA MOSFET design concept. b) A sketch of the TCAD structure and geometrical parameters.

Table 1. Design parameters

Toxide1 | 50 nm
Loxide1 | 0.7 μm
Toxide2 | 0.2 μm
Lch | 0.5 μm
Ldrift | 7 μm
Nd | 1.1*10¹⁶ cm⁻³
Pd | 4*10¹⁷ cm⁻³

Simulation Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.17.pdf

In Fig. 2 the sub-threshold slope and the threshold voltage, calculated starting from the , are reported for different radius at ambient temperature. A peculiar behavior of the Vth occurs: it decreases when the radius decreases until 25 nm , but it increases when the radius is lower than 25 nm . Therefore, the variation is not monotone. In the same way, the sub-threshold slope of the curve is not monotone: for a radius higher than 75 nm the slope increases, while it quickly decreases for lower pillar radii.

Both the peculiar behaviors are due to the balance between the oxide capacitance and the depletion capacitance in the channel region [1]. Simulations for a pillar radius of for and 450 K , show a weak dependence on the temperature.

Fig. 2 Sub-threshold slope and threshold voltage dependence on the pillar radius.

Fig. 2. Sub-threshold slope and threshold voltage dependence on the pillar radius.

In Fig. 3 the output curves are reported up to 500 V and it is visible as the reduction of the pillar radius does not improve the Ron. It is visible as even if the saturation current increases for high for a 20 nm pillar radius, this does not lead to the improvement of the Ron, since the Drain current is negligible compared to the Drain current for . The main reason comes from the fact that the more the pillar radius decreases, the more the section oxide area percentage increases (See Fig. 4). This leads to the reduction of the SiC section useful for the conduction. This leads to the increase of the resistance, that is inversely proportional to the section of the pillar.

Fig. 3 Output curves for pillar radius equal to and and .

Fig. 3. Output curves for pillar radius equal to and and .

The Ron dependence on pillar radius and temperature is detailed in Fig. 4, where in the inset the geometrical features of the device are reported. A pillar radius of 500 nm is mandatory to have Ron . As reported above, it is clear as the geometrical distribution of the pillars modifies the Ron dependence on the pillar radius. As an example, the more the oxide thickness is reduced, the more the Ron decreases, by keeping constant the area of the device.

Fig. 4 On-resistance value for different pillar radius for two temperatures. In the inset the geometrical distribution of the pillars to evaluate the Ron.

Fig. 4. On-resistance value for different pillar radius for two temperatures. In the inset the geometrical distribution of the pillars to evaluate the Ron.

In Fig. 5 the capacitances of the structure with 20 nm and are reported. It is visible as the capacitance strongly increases for a larger pillar radius. The active area is and Ion . The reduction of the pillar radius leads to an abrupt decrease of the overall capacitance.

Fig. 5 Ciss, Coss, and Crss values for pillar radius of 20 nm and .

Fig. 5. Ciss, Coss, and Crss values for pillar radius of 20 nm and .

On the other hand, for a pillar radius of 20 nm , the Miller plateau is much higher compared to one of . A complete overview of this effect is reported in Fig. 6. It is visible as for a very low pillar radius, both Eoff and Eon arise. For higher pillar radius values, the performances are comparable to the structure in [6]. This happens even if the static capacitances in Fig. 5 show higher values for higher radius.

Fig. 6 Turn-off and turn-on energy dependence on the pillar radius. .

Fig. 6. Turn-off and turn-on energy dependence on the pillar radius. .

Finally, the short circuit capability was evaluated through electro-thermal simulations. In Fig. 7 both the Drain current and the maximum temperature are reported for a pillar radius of 20 nm and . As expected, the structure does not show a short-circuit ruggedness, since the great portion of silicon oxide. For , even if the current turns off, the temperature does go to zero, leading to delayed thermal runaway failure. Both structures do not withstand a short circuit pulse with a duration of . For the pillar radius of 50 nm , the temperature abruptly arises to very high values.

Fig. 7 Short circuit waveforms for two pillar radius values.

Fig. 7. Short circuit waveforms for two pillar radius values.

An interesting effect occurs during the short circuit for the 20 nm pillar radius structure, where the temperature peak occurs on the Drain side instead of the P-Body side (See Fig. 8). The peak temperature for the small radius device occurs on the Drain side, while for the larger structure the temperature peak occurs below the P-Body region, as expected. Therefore, the proposed structure has switching performances comparable to commercial devices with similar rates and has the advantage of the absence of a termination region. On the other hand, the structure shows a very low short circuit capability.

Fig. 8 Temperature distribution at the end of the 1 ms pulse into the a) 50 nm structure and the b) .

Fig. 8. Temperature distribution at the end of the 1 ms pulse into the a) 50 nm structure and the b) .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.17.pdf

In conclusion, the SiC power MOSFET with a vertical Gate All Around (GAA) design shows strong switching performance and removes the need for a termination region. However, TCAD simulations highlight challenges, particularly with the device's on-resistance (Ron), which is highly dependent on the pillar radius, with a 500 nm radius necessary for . Additionally, larger pillar radii lead to increased capacitance, affecting performance. The device also shows limited short-circuit ruggedness, especially in designs with smaller pillar radii, where delayed thermal runaway failure is observed. Notably, for a 20 nm pillar radius, the temperature peak occurs on the Drain side.'

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.17.pdf

B. Jayant Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, 2010.

Maresca, Luca, et al., SiC GAA MOSFET Concept for High Power Electronics Performance Evaluation through Advanced TCAD Simulations, Solid State Phenomena 360 (2024): 75-80.

J. H. Edgar, et al., Selective epitaxial growth of silicon carbide on SiO 2 masked Si (100): The effects of temperature, Journal of applied physics 84.1 (1998): 201-204.

F. Udrea, et al., The FinFET effect in Silicon Carbide MOSFETs, 2021 33rd (ISPSD). IEEE, 2021.

Kato, T., et al., Enhanced performance of 50 nm Ultra-Narrow-Body silicon carbide MOSFETs based on FinFET effect, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2020.

G. Romano et al., A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs, IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 4, n. 3, 2016.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 25-33

doi: 10.4028/p-0dBoIR

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-12

Revised:
2025-08-01

Accepted:
2025-08-05

Online:
2025-09-05

Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1021.25.pdf

Shane R. Stein , Suman Das , Ayan K. Biswas , Daniel J. Lichtenwalner , and Sei-Hyung Ryu

Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

shane.stein@wolfspeed.com, suman.das@wolfspeed.com, ayan.biswas@wolfspeed.com, daniel.lichtenwalner@wolfspeed.com, sei-hyung.ryu@wolfspeed.com

Keywords: Charge pumping, field-effect mobility, gate stress, impact ionization, interface traps.

Abstract

The effects of positive and negative high voltage gate stress on the interface trap density and channel conductivity of lateral, Si -face 4 H -SiC MOSFETs is studied, and the possible physical mechanisms for interface trap generation are discussed. Charge pumping and measurements are used to measure the trap density and field-effect mobility, respectively. The time dependence of the channel degradation is evaluated for different stress voltages with oxide electric field exceeding . Positive stress is shown to generate acceptor traps which degrade the field-effect mobility, and the density of traps follows a universal dependence on the injected electron fluence into the gate oxide. In contrast, negative stress resulted in no degradation of the field-effect mobility even as interface trap density increased, indicating that only donor interface traps are created. Furthermore, the trap density during negative stress does not follow a universal dependence on the injected hole fluence, indicating that other mechanisms are responsible for the trap creation.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.25.pdf

To ensure long-term reliable operation of SiC power MOSFETs, it is critical to understand safe operating conditions and the effects of gate voltage stress on device performance and defectivity, during both operation and testing. Recently, the evolution of the threshold voltage ( ) of SiC MOSFETs during positive high voltage gate stress (HVGS), wherein the oxide electric field exceeds the threshold field for impact ionization, has been evaluated. It has been routinely observed that a large negative shift occurs when the gate is stressed at oxide fields over [1]-[3], which is attributed to the trapping of holes in the bulk of the gate oxide after being generated by impact ionization and/or anode hole injection [3]-[6]. More recently, the charge pumping (CP) technique [7], [8] was used to show that the interface trap density ( ) also increases during HVGS, thereby degrading the MOS interface [9]. In this work, we continue these investigations by studying the evolution of both and field-effect mobility ( ) during positive as well as negative HVGS on lateral test MOSFETs using and CP measurements, revealing the practical impact of HVGS on device performance and providing insight into the possible physical mechanisms responsible for the interface degradation.

Experimental Details

The original version of this paper is available on https://www.scientific.net/KEM.1021.25.pdf

The devices used for this study were lateral test MOSFETs fabricated on off-axis epitaxial wafers. The implanted acceptor concentration ( ) in the channel is and the MOS interface is formed on the Si face by thermal oxidation followed by NO annealing. The MOSFET channel length and width are and , respectively. This channel length was long enough to ensure the channel resistance was the dominant resistance during measurements to allow extraction of an accurate value for , but also short enough to avoid significant geometric current during CP measurements [7], [8]. A schematic cross section of the test MOSFET is shown in Fig. 1(a), along with an illustration of the gate voltage stress and measurements sequence in Fig. 1(b). Each MOSFET was stressed at a certain gate voltage sufficiently high to induce impact ionization in the oxide, which is well beyond the recommended operating conditions of the device (oxide field

Fig. 1. (a) Schematic cross-section of the lateral test MOSFETs used in this work. (b) Diagram of the gate voltage sequence during the HVGS experiment.

Fig. 1. (a) Schematic cross-section of the lateral test MOSFETs used in this work. (b) Diagram of the gate voltage sequence during the HVGS experiment.

) for a cumulative stress time of 30 minutes, which was interrupted periodically by a CP voltage level sweep with a pulse amplitude of 15 V followed by an sweep.

The field-effect mobility was calculated from the data by

where and are the MOSFET channel length and width, respectively, is the specific oxide capacitance, and is the drain-source voltage, which was 0.1 V during the measurements. Due to the high density of interface traps in SiC MOSFETs, the calculated is not the real mobility of the free electrons in the channel, but is a fraction of the real mobility determined by the fraction of electrons in the channel that are not trapped. This parameter thus represents the combined effects of electron immobilization and Coulombic scattering caused by interface traps, which determine the channel resistance.

The peak CP current ( ) is related to the interface trap density according to

where is the number of traps pumped per cycle, is the elementary charge, is the gate pulse frequency, is the interface trap energy distribution, and are the lower/upper energy bound of the energy range of interface traps measured which is determined by the rise/fall time and amplitude of the gate pulse waveform [7]. is therefore a fraction of the total which in our measurements includes interface traps within an energy range of about 2.9 eV across the middle of the bandgap.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.25.pdf

Positive High-Voltage Gate Stress. The CP - curves during positive HVGS for a stress voltage of +36 V are shown in Fig. 2(a). The corresponding curves are shown in Fig. 2(b). The peak increases significantly with stress time, indicating that new interface traps are being generated during the stress. This is accompanied by a decrease in the peak , which allows us to conclude that the generated interface traps include acceptor traps in the upper half of the bandgap which become negatively charged upon capturing electrons, reducing the free electron density in the channel and increasing the Coulombic scattering rate of the remaining free electrons. The CP curves also show a negative shift in the flatband voltage ( ) after the first stress interval which becomes nearly constant after the subsequent stress intervals. The same behavior is observed for in the curves as well.

Fig. 2. (a) CP curves taken after several time intervals during positive HVGS for a stress voltage of +36 V . (b) The corresponding field-effect mobility curves calculated from the sweeps.

Fig. 2. (a) CP curves taken after several time intervals during positive HVGS for a stress voltage of +36 V . (b) The corresponding field-effect mobility curves calculated from the sweeps.

This quickly saturating negative shift in and is attributed to a rapid accumulation of positive charge in the bulk of the gate oxide as holes generated by impact ionization and/or anode hole injection become trapped in the [3]-[6]. The apparent from the CP curves shows a continuous negative shift with additional stress time, in contrast to and the from the curves, which may result from an increase in donor interface traps [10]. The left side of the CP curves after stress also show an early rise in with a shallower initial slope, which can result from parallel recombination current [10], indicating the presence of nonuniform interface degradation during positive HVGS. The behavior of the CP curves after positive HVGS observed here are consistent with our previous observations [9].

Fig. 3. (a) The measured versus stress time during positive HVGS for different stress voltages and (b) the corresponding peak .

Fig. 3. (a) The measured versus stress time during positive HVGS for different stress voltages and (b) the corresponding peak .

Fig. 3(a) and 3(b) show the measured and peak , respectively, as a function of time during positive HVGS for three different gate stress voltages. The interface degradation measured by both parameters increases with both stress voltage and time. The time dependence obeys a power law with an exponent less than unity, similar to shift during bias temperature instability (BTI) [11], [12].

Fig. 4. (a) CP - curves taken after several time intervals during negative HVGS for a stress voltage of -36 V . (b) The corresponding field-effect mobility curves calculated from the sweeps.

Fig. 4. (a) CP - curves taken after several time intervals during negative HVGS for a stress voltage of -36 V . (b) The corresponding field-effect mobility curves calculated from the sweeps.

Fig. 5. (a) The measured versus stress time during negative HVGS for different stress voltages and (b) the corresponding peak .

Fig. 5. (a) The measured versus stress time during negative HVGS for different stress voltages and (b) the corresponding peak .

Negative High-Voltage Gate Stress. Fig. 4(a) and 4(b) show the CP and characteristics, respectively, during negative HVGS for a stress voltage of -36 V . ICP increases much less than during positive HVGS, and no degradation is observed. Both and exhibit a continuous negative shift with increasing stress time, which can be attributed to holes becoming captured by border traps as well as Fowler-Nordheim (F-N) injection and subsequent trapping in the bulk.

Fig. 5(a) and 5(b) show the measured and peak , respectively, as a function of time during negative HVGS for three different gate stress voltages. again shows a sublinear time dependence, but it increases much less compared to positive HVGS, and shows no degradation for any of the stress voltages apart from an initial decrease after the first stress interval.

To better visualize the stress voltage and time dependence of , the change in during positive and negative HVGS for each stress voltage are plotted versus stress time in logarithmic scale in Fig. 6. From these plots the time exponent of the power law can be readily extracted. During positive HVGS, the exponent decreases with higher stress voltage, in contrast to what would be expected for BTI effects. During negative HVGS, a voltage-independent time exponent of is obtained, which is close to what is commonly found for shift during BTI for both SiC and silicon MOSFETs [11]-[13]. This observation suggests that normal BTI mechanisms may be operating during negative HVGS. The stress voltage dependence of during negative HVGS can also be more clearly seen in the logarithmic scale of this plot.

Fig. 6. The change in versus stress time in logarithmic scale for (a) positive HVGS and (b) negative HVGS. increases as a power law in time with the shown exponents.

Fig. 6. The change in versus stress time in logarithmic scale for (a) positive HVGS and (b) negative HVGS. increases as a power law in time with the shown exponents.

Correlation of Trap Density and Mobility. In Fig. 3, and appear to be inversely correlated, inversely following the same voltage and time dependence during positive stress. In Fig. 5 , on the other hand, and do not appear to be correlated during negative stress. It is of interest to evaluate the correlation of and for each stress condition. This is shown in Fig. 7, where is plotted versus (normalized to the values before any stress) for each stress voltage for both positive and negative HVGS. For positive stress, follows a universal linear dependence on , irrespective of the stress voltage magnitude. The degradation during positive HVGS therefore seems to be caused directly by increased Coulomb scattering and trapping of channel electrons at newly created interface defects.

In Fig. 7(b), the relatively small changes in both and during negative HVGS make it difficult to conclude whether the same trend is followed as during positive HVGS. As can be seen in Fig. 7(c), when the scale is magnified shows no decrease after the initial stress interval and thus exhibits no correlation with . This observation indicates that the generated interface traps during negative HVGS must be donor traps, which are neutral of charge when the channel is in inversion and thus have no effect on free electron density or mobility in the channel.

Fig. 7. The change in peak plotted versus the change in for the different stress voltage magnitudes during (a) positive HVGS and (b) negative HVGS. The universal linear correlation for positive HVGS indicates that the degradation is a direct result of interface trap generation. (c) A magnified view of the negative HVGS data showing the lack of correlation between and .

Fig. 7. The change in peak plotted versus the change in for the different stress voltage magnitudes during (a) positive HVGS and (b) negative HVGS. The universal linear correlation for positive HVGS indicates that the degradation is a direct result of interface trap generation. (c) A magnified view of the negative HVGS data showing the lack of correlation between and .

Fig. 8. Energy band diagram of the MOS structure and the various carrier transport and generation/recombination processes occuring during (a) positive HVGS and (b) negative HVGS.

Fig. 8. Energy band diagram of the MOS structure and the various carrier transport and generation/recombination processes occuring during (a) positive HVGS and (b) negative HVGS.

Discussion of Possible Degradation Mechanisms. To understand the possible mechanisms for interface trap generation during HVGS that can be deduced from the above observations, it is helpful to review the physical processes electrons and holes undergo in the MOS structure during HVGS. These are illustrated in Fig. 8(a) for positive HVGS and 8(b) for negative HVGS.

During positive HVGS, (i) electrons are injected from the channel into the by F-N tunneling, (ii) the injected electrons are accelerated toward the gate electrode by the high oxide field, gaining kinetic energy, (iii) a small fraction of the accelerating electrons, which increases with oxide field, are able to reach an energy over 9 eV to cause impact ionization within the [5], generating electron-hole pairs, (iv) the generated holes transport back toward the interface, though some become trapped within the , and (v) recombination may take place near the interface or in the channel between the generated holes and the injected or channel electrons. Therefore, processes happening near the interface which could be responsible for trap generation during positive HVGS include electron F-N injection, hole transport, and electron-hole recombination.

During negative HVGS, holes are injected into the by F-N tunneling, then accelerate toward the gate electrode. However, in hole transport is believed to be much more dispersive and possibly even proceed via a hopping mechanism [5], [6], [14], such that the holes cannot obtain significant kinetic energy to generate electrons by impact ionization or anode electron injection. Therefore, during negative HVGS, hole F-N injection is the only physical mechanism taking place near the interface and the only apparent candidate for interface trap generation, other than the high electric field itself and the presence of accumulated holes in the channel.

To further deduce the responsible mechanisms for trap generation, the dependence of the measured on the calculated fluence of injected carriers due to F-N tunneling was evaluated. The F-N current is given by

where is the oxide electric field, is the reduced Planck's constant, is the injection barrier height for the carrier due to the band offsets (in volts), and is the tunneling effective mass of the carrier. For the calculation, a value of 2.75 V was used for electrons and 2.9 V for holes [13], and an value of was used for electrons and for holes [15], where is the electron rest mass. The fluence was then calculated by

It should be noted that the change in after each stress interval was also accounted for in the calculation of , though it did not significantly affect the qualitative features of the results.

Fig. 9. The measured change in versus the calculated fluence of carriers injected by FowlerNordheim tunneling into the from the channel during positive or negative HVGS for several stress voltage magnitudes. The generated trap density follows a universal dependence on the injected fluence for positive HVGS, but not for negative HVGS.

Fig. 9. The measured change in versus the calculated fluence of carriers injected by FowlerNordheim tunneling into the from the channel during positive or negative HVGS for several stress voltage magnitudes. The generated trap density follows a universal dependence on the injected fluence for positive HVGS, but not for negative HVGS.

Fig. 9 shows the measured plotted versus the calculated fluence for positive and negative HVGS for several stress voltage magnitudes. The during positive HVGS shows a universal dependence on the electron fluence, irrespective of the stress voltage used. The lack of a separate voltage dependence makes it unlikely for hot holes and electron-hole recombination to be the source of trap generation, since the density of holes arriving at the interface would depend not only on the number of injected electrons, but also on the avalanche multiplication rate (per injected electron), which would also depend on the gate voltage. Thus, the arriving hole density would not be directly proportional to . In addition, the recombination rate would be hole-limited because the hole density arriving at the interface must be lower than the injected electron density since only a small fraction of the electrons generate holes. The trap generation during positive HVGS therefore appears to be caused by the F-N electron injection itself.

In contrast, during negative HVGS does not appear to follow a universal dependence on the hole fluence. In particular, the dependence of on the stress voltage magnitude is too weak. It is also noteworthy that for a given fluence, the is much higher for negative HVGS than for positive HVGS. The defect generation during negative HVGS is therefore likely field-induced, as that seems to be the only remaining candidate.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.25.pdf

In summary, positive and negative HVGS was applied to lateral SiC test MOSFETs using several stress voltages and times, and the impact of each on and was studied. Positive HVGS was found to cause significantly more interface trap generation than negative HVGS, which was linearly correlated with the degradation in . No mobility degradation occurred during negative HVGS despite some increase in , indicating that the newly created traps were donors. When the change in is plotted versus the injected carrier fluence into the oxide via F-N tunneling, the generated trap density follows a universal dependence on the injected electron fluence during positive HVGS, irrespective of the stress voltage, but during negative HVGS the generated trap density did not follow a universal dependence on the injected hole fluence, indicating that other mechanisms are responsible for the trap creation. Lastly, CP was shown to be a valuable technique for characterizing interface trap density, as evidenced by the ability to directly correlate and during positive HVGS.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.25.pdf

J. Berens and T. Aichinger, "A straightforward electrical method to determine screening capability of GOX extrinsics in arbitrary, commercially available SiC MOSFETs," in 2021 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA: IEEE, Mar. 2021, pp. 1-5. doi: 10.1109/IRPS46558.2021.9405152.

A. K. Biswas et al., "Hole-Induced Threshold Voltage Instability Under High Positive and Negative Gate Stress in SiC MOSFETs," in 2024 IEEE International Reliability Physics Symposium (IRPS), Apr. 2024, pp. 1-5. doi: 10.1109/IRPS48228.2024.10529422.

F. Masin et al., "Non-monotonic threshold voltage variation in metal-oxidesemiconductor field-effect transistor: Investigation and modeling," Journal of Applied Physics, vol. 130, no. 14, p. 145702, Oct. 2021, doi: 10.1063/5.0057285.

D. J. DiMaria, E. Cartier, and D. Arnold, "Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon," Journal of Applied Physics, vol. 73, no. 7, Art. no. 7, Apr. 1993, doi: 10.1063/1.352936.

D. Arnold, E. Cartier, and D. J. DiMaria, "Theory of high-field electron transport and impact ionization in silicon dioxide," Phys. Rev. B, vol. 49, no. 15, pp. 10278-10297, Apr. 1994, doi: 10.1103/PhysRevB.49.10278.

D. J. DiMaria and J. W. Stasiak, "Trap creation in silicon dioxide produced by hot electrons," Journal of Applied Physics, vol. 65, no. 6, Art. no. 6, Mar. 1989, doi: 10.1063/1.342824.

G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. 31, no. 1, Art. no. 1, Jan. 1984, doi: 10.1109/T-ED.1984.21472.

A. Salinaro et al., "Charge Pumping Measurements on Differently Passivated Lateral 4H-SiC MOSFETs," IEEE Trans. Electron Devices, vol. 62, no. 1, Art. no. 1, Jan. 2015, doi: 10.1109/TED.2014.2372874.

S. R. Stein, J. Kim, S. Das, D. J. Lichtenwalner, and S. Ryu, "Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress," in 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA: IEEE, Apr. 2024, pp. 1-5. doi: 10.1109/IRPS48228.2024.10529394.

P. Heremans, J. Witters, G. Groeseneken, and H. E. Maes, "Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation," IEEE Trans. Electron Devices, vol. 36, no. 7, Art. no. 7, Jul. 1989, doi: 10.1109/16.30938.

D.K. Schroder, "Negative bias temperature instability: What do we understand?," Microelectronics Reliability, vol. 47, no. 6, Art. no. 6, Jun. 2007, doi: 10.1016/j.microrel. 2006.10.006.

J. H. Stathis, "The physics of NBTI: What do we really know?," in 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA: IEEE, Mar. 2018, p. 2A.1-1-2A.1-4. doi: 10.1109/IRPS.2018.8353539.

D. J. Lichtenwalner et al., "Reliability studies of SiC vertical power MOSFETs," in 2018 IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA: IEEE, Mar. 2018, p. 2B.2-1-2B.2-6. doi: 10.1109/IRPS.2018.8353544.

R. C. Hughes, "Time-resolved hole transport in a-SiO2," Phys. Rev. B, vol. 15, no. 4, pp. 20122020, Feb. 1977, doi: 10.1103/PhysRevB.15.2012.

R. K. Chanana, "Determination of hole effective mass in SiO 2 and SiC conduction band offset using Fowler-Nordheim tunneling characteristics across metal-oxide-semiconductor structures after applying oxide field corrections,"Journal of Applied Physics, vol. 109, no. 10, p. 104508, May 2011, doi: 10.1063/1.3587185.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 35-39

doi: 10.4028/p-4QkAFT

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-05

Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

Pavan Vudumula , Yu-Chieh Chien , Abdul Hannan Yeo , Lakshmi Kanta Bera , Umesh Chand , Voo Qin Gui Roth , Surasit Chung , Navab Singh , Yee-Chia Yeo

Institute of Microelectronics (IME), Agency for Science, Technology, and Research (A*STAR), Singapore 138634.

*E-mail: Vudumula_pavan_kumar@a-star.edu.sg, Chien_Yu_Chieh@a-star.edu.sg, channan_yeo@a-star.edu.sg, dLakshmi_kanta_bera@a-star.edu.sg,

Chand_Umesh@a-star.edu.sg, Roth_Voo@a-star.edu.sg, Surasit_chung@a-star.edu.sg, navab@a-star.edu.sg, Yeo_Yee_Chia@a-star.edu.sg,

Keywords: Channeling implant, Deep p-body, Single step implant

Abstract

In this work, TCAD simulation of SiC MOSFETs design with deep ( ) p-base using single step aluminum channeling implant along [0001] direction and JFET design using phosphorus implant is presented. The threshold voltage ( ) was around 3 V for both the devices. Improvements to the specific on-resistance ( ) reduction by , breakdown voltage (BV) enhancement by , miller plateau reduction by is reported. Furthermore, both the Baliga figure-ofmerit (BFOM) ( ) and high-frequency figure-of-merit (HFOM) ( ) with deep p-base/JFET implant are enhanced as compared to shallow p-base/JFET implant. This paper provides valuable insights into the advantages of a single-step channeling implant at room temperature, without the need for a hard mask. This approach offers a high throughput with a lowcost process for fabricating high-performance SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

4H-SiC MOSFETs are well-suited for hybrid electric vehicles (HEV) and pure electric vehicles (EV) with a voltage rating of 1.2 kV . This is attributed to their impressive BV, low , and fast switching speeds . These devices consist of box-shaped implantation profiles formed through multi-step processes, including the p -base, JFET, and regions. Aluminum is used for both the p -base and implantation, while phosphorus is used for the JFET and implantation [2]. The multi-step implantation for box profiles is commonly conducted utilizing hard masks at high temperatures ( ). Undoubtedly, this process entails several steps that inherently impede manufacturing throughput. Few studies have investigated the impact of deep p-body and deep JFET on and short circuit withstand time [3,4]. A recent study has shown that a well-defined box-type profile can be achieved through a single-step implantation with significant depth along the [0001] and [11 ] crystal orientations [5]. However, the box shape profile is more effective in the [0001] direction. The channeling implantation process performed at room temperature, allows the use of photoresists which eliminates the need for hard mask processes. This helps to streamline fabrication by eliminating several steps involved in hard mask patterning which could lead to significant cost reductions. This channeling implant has potential applications in SiC super junction devices too. However, there are little reports on the characteristics of deep p-body standard SiC MOSFETs using single-step implant. This study investigates the impact of a deep p -body using a single-step implant profile along [0001] and the corresponding JFET implant design using phosphorous channeling implant along [0001] in 1.2 kV MOSFETs in terms of its static and dynamic characteristics.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

Experimental data on aluminum channeled implantation with an energy of 300 keV and a dose of along the [0001] crystal direction show a nearly box-shaped profile up to a depth of [4]. This profile has been used for the p-body. To achieve a uniform JFET design, phosphorus implantation with optimized parameters (energy: , dose: ) is necessary. The implant profile is illustrated in Fig. 1.

Fig. 1 Simulated doping profile for deep channeling implantation along [0001] orientation with optimized JFET profile.

Fig. 1. Simulated doping profile for deep channeling implantation along [0001] orientation with optimized JFET profile.

Fig. 2 Schematic of (a) non-channeled p-base and (b) channeled single-step implanted p-base from TCAD simulation.

Fig. 2. Schematic of (a) non-channeled p-base and (b) channeled single-step implanted p-base from TCAD simulation.

The device cross-section of a 1.2 kV MOSFET with a non-channeled implant for a p-body depth of and a p-body depth of using channeling implant is depicted in Fig. 2 (a) and (b), respectively. These devices are simulated using TCAD with
, and a uniform epitaxy doping profile of . The extracted threshold voltage ( ) is approximately 3 V for both devices, and specific on-resistance ( ) from characteristics (Fig. 3 (a)) is lower with a JFET implant depth of compared to a shallow JFET implant depth of . This reduction is due to charge sustaining layer (CSL) with deep JFET implant, resulting in increased electron flow and thus a lower . Fig. 3 (b) demonstrates a improvement in blocking voltage for the p-body device with a depth of compared to the device with a depth of . Enhanced two-dimensional electric field distribution with deeper p-body compared to shallow p-base allows the device to sustain higher blocking voltages. Deep p-base better shields the channel and gate oxide from high drain bias due to the depletion in JFET.

Fig. 3 Simulated (a) output and (b) blocking voltage characteristics for SiC MOSFETs with nonchanneling (orange) and channeling (blue) implantation.

Fig. 3. Simulated (a) output and (b) blocking voltage characteristics for SiC MOSFETs with nonchanneling (orange) and channeling (blue) implantation.

Fig. 4 Blocking-state electric field distribution near breakdown for (a) non-channeling and (b) channeling p-base region in SiC MOSFETs.

Fig. 4. Blocking-state electric field distribution near breakdown for (a) non-channeling and (b) channeling p-base region in SiC MOSFETs.

Fig. 5 Simulated (a) gate charge and (b) switching characteristics with non-channeling and channeling p-base region in SiC MOSFETs.

Fig. 5. Simulated (a) gate charge and (b) switching characteristics with non-channeling and channeling p-base region in SiC MOSFETs.

The off-state electric field distributions near the breakdown regime for and for -base are shown in Fig. 4 (a) and 4 (b). Additionally, gate charge (Fig. 5(a)) and clamped inductive load switching simulations (Fig. 5 (b)) are performed using a mixed-mode SPICE environment to analyze the miller plateau and switching losses. The non-linear capacitance simulations with variations in drain bias, including input ( ), output ( ), and reverse transfer ( ) capacitances are shown in Fig. 6. An improvement in corresponds to the reduced gate-to-drain coupling with the deep p-base design, which induces an increased depletion width along the JFET region during the switching regime. and remain the same for both devices as the remaining regions remain unaltered with a cell pitch. Table 1 lists the performance metrics (BFOM, HF-FOM) and switching losses for both devices along with benchmarking results.

Fig. 6 Simulated non-linear input, output, and miller capacitances with drain bias with nonchanneling and channeling p-base region in SiC MOSFETs.

Fig. 6. Simulated non-linear input, output, and miller capacitances with drain bias with nonchanneling and channeling p-base region in SiC MOSFETs.

Table 1 Simulated electrical performance metrics ( BFOM and ) at and .

0.7 μm p-base 1.2 kV 4H-SiC MOSFET
2.0 μm p-base 1.7 kV 4H-SiC MOSFET
Benchmark [Ref. 3]

T (°C)
BV (V)
Ron,sp
(mΩ-cm²)
BFOM
(MV/cm²)
T (°C)
BV (V)
Ron,sp
(mΩ-cm²)
BFOM
(MV/cm²)

27
1208
2.4
608
27
1693
1.7
1686
WJFET = 0.9 μm
Lch = 0.5 μm
Ldrift = 10 μm
Ndrift = 8×10¹⁵ cm⁻³

150
1220
2.7
551
150
1700
2.0
1445

Qgd
(nC/cm²)
Ron,sp
(mΩ-cm²)
HF-FOM
(nC-mΩ)

Qgd
(nC/cm²)
Ron,sp
(mΩ-cm²)
HF-FOM
(nC-mΩ)

27
117
2.4
281
27
82
1.7
140

150
117
2.7
433
150
82
2.0
164
Electrical parameters:
Ron,sp = 4 mΩ-cm²
BV = 1560 V

Eon (mJ)
Eoff (mJ)

Eon (mJ)
Eoff (mJ)

27
2.1
0.8
27
1.7
0.8

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

In this study, we showed that the single-step channeling implantation is a highly promising method for realizing high BFOM and low in MOSFETs. In addition, the implementation of channeling implantation ensured a superior process throughput at a much lower cost than the standard multi-step implant process.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

This work was supported by the Science and Engineering Research Council of A*STAR (Agency for Science, Technology and Research) Singapore, under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.35.pdf

B. J. Baliga, Silicon Carbide Power Devices, World scientific (2006).

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology, John Wiley & Sons (2014).

D. Kim, N. Yun, A. J. Morgan, and W. Sung, "The effect of deep JFET and P-Well Implant of MOSFETs," IEEE J. Electron Devices Soc., vol. 10, 989-99 (2022).

D. Kim and W. Sung, "Improved short-circuit ruggedness for 1.2 kV 4H-SiC MOSFET using a deep p-well implemented by channeling implantation," IEEE Electron Device Letters, vol. 42, no. 12, 1822-1825 (2021).

M. K. Linnarsson, L. Vines, and A. Hallén, "Influence from the electronic shell structure on the range distribution during channeling of ions in ," J. Appl. Phys., 130, 075701 (2021).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 41-50

doi: 10.4028/p-4FJgLU

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-18

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-05

Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

Ahmad Abbas , Cyrille Le Royer , Romain Laviéville , Jérôme Biscarrat , Guillaume Gelineau , Frédéric Allibert , Edwige Bano , and Philippe Godignon

Univ. Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France

Soitec S.A., Parc technologique des fontaines, 38190 Bernin, France

Univ. Grenoble Alpes, USMB, CNRS, Grenoble INP, CROMA, France

ahmad.abbas@cea.fr, cyrille.leroyer@cea.fr, romain.lavieville@cea.fr,

jerome.biscarrat@cea.fr, guillaume.gelineau@cea.fr, frederic.allibert@soitec.com,

edwige.bano@grenoble-inp.fr, philippe.godignon@cea.fr

Abstract

In this work, we investigate the static electrical parameters of power diodes with various designs and architectures (Schottky, PiN, and JBS with hexagonal or stripes anode), fabricated on two types of 150 mm substrates (single crystal 4H-SiC reference and 3C-poly silicon carbide based substrates: ). I(V) measurements are carried out in both reverse and forward modes to assess the impact of designs and substrates. Non-destructive avalanche mode is reached with similar performance (leakage, ) observed for both substrates (due to identical drift layers and device structures). All diode designs on SmartSiC exhibit a larger current conduction and less resistance in the ohmic regime (compared to bulk), whatever the temperature (up to ). Partitioning model is also proposed for evaluating the substrate contribution on the measured specific resistance and on the observed SmartSiC gains.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

Bulk substrates growth requires a long, energy-intensive and costly process, which limits the availability of SiC substrates for devices production today. Consequently, 3C-poly silicon carbide based substrates ( pSiC ) are currently being considered as an alternative substrate for SiC power devices fabrication. By utilizing the SmartCut technology, a high-quality layer can be bonded (conductive bonding) on top of a thick polycrystalline SiC handle wafer [1]. The resulting SmartSiC substrates are engineered to achieve better device yield and to optimise conduction losses [2] because of the low resistivity poly-SiC layer, thanks to one order of magnitude lower resistivity values compared to mono-SiC. SmartSiC not only enhances electrical performance but also reduces manufacturing costs and environmental impact. It enables the reuse of donor wafers, yielding around 500 wafers per SiC boule, ten times more than standard methods [3]. In this work, we study the impact of temperature on the static electrical parameters of 1200 V power diodes with various designs and architectures (Schottky, PiN, JBS with hexagonal cells or stripes) fabricated on 150 mm bulk and based substrates (SmartSiC ).

Devices Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

Three power diodes architectures (Schottky, PiN, and JBS: Fig. 1a-b) have been fabricated through a process flow designed for 1200 V blocking voltage capability [4], with Al implanted p+ guard rings and a junction termination extension (JTE) annealed at to achieve the breakdown voltage target (Fig. 1c). Various anode and edge terminations have been designed and fabricated on both 4 H SiC bulk and SmartSiC substrates (Fig. 1d). The substrates have not been thinned and backside contact formation was performed using laser annealing [5].
I(V) measurements, conducted in both reverse and forward modes, are aimed at evaluating the impact of different designs and substrates.

Fig. 1. Description of the tested diodes samples (device designs: Schottky, PiN, and JBS). a) Top view, b) anode cross-section with c) edge termination cross-section at the diode periphery, d) Additionally, standard bulk and new substrates have been considered for building the diodes samples on these two types of epiwafers (with identical epi process, designed for 1200 V rating).

Fig. 1. Description of the tested diodes samples (device designs: Schottky, PiN, and JBS). a) Top view, b) anode cross-section with c) edge termination cross-section at the diode periphery, d) Additionally, standard bulk and new substrates have been considered for building the diodes samples on these two types of epiwafers (with identical epi process, designed for 1200 V rating).

Electrical Characteristics: Off-State

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

Off-state characteristics, shown in Fig. 2a, highlight various reference diode types that are reverse biased on single crystal (bulk) and epiwafers. Diodes on both epiwafers achieved non-destructive avalanche mode with similar leakage currents and avalanche voltages (VAV), attributed to the identical drift layers and device structures.

Fig. 2. a) Reverse I(V) curves (wafer median for bulk and SmartSiC ) for Schottky, JBS (hexagonal and stripes) and PiN. Anode surface is . b) Corresponding box plots of reverse leakage current densities J extracted at 1200 V (for PiN, JBS with stripes, and Schottky diodes on SmartSiC and bulk), c) examples of wafermaps for J @ 1200 V .

Fig. 2. a) Reverse I(V) curves (wafer median for bulk and SmartSiC ) for Schottky, JBS (hexagonal and stripes) and PiN. Anode surface is . b) Corresponding box plots of reverse leakage current densities J extracted at 1200 V (for PiN, JBS with stripes, and Schottky diodes on SmartSiC and bulk), c) examples of wafermaps for J @ 1200 V .

In Fig. 2b, the leakage current density is extracted at 1200 V (before avalanche). We observe similar leakage current distributions for both substrates (for PiN, JBS and Schottky diodes). Fig. 2c shows the wafer mapping of this leakage current level extracted for JBS (with stripes) on both bulk and SmartSiC substrates. Both substrate types reveal similar leakage current profile, with an increased leakage for a limited number of sites situated around the center and edges of the wafer, due to the presence of defects in these areas. It is also worth noting that the levels of reverse leakage current around the centre are slightly reduced for SmartSiC substrates. Wafer mapping and yield analysis indicated that defects contributing to off-state performance degradation, such as BPDs or TEDs, were minimally influenced by the substrate material [6].

Electrical Characteristics: On-State

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

Following the off-state study, forward mode measurements are carried out. I(V) characteristics of SmartSiC and bulk devices are compared. JBS diodes on SmartSiC exhibited superior current conduction and reduced resistance in the ohmic regime (Fig. 3a), demonstrating the impact of substrate resistivity. The specific differential resistance ( ) was extracted as illustrated in Fig. 3a. In Fig. 3b, decreases as the Schottky surface ratio increased for both bulk and SmartSiC , with a notable reduction in resistance observed in hexagonal configurations. All diodes fabricated on SmartSiC exhibited less resistance than their bulk counterparts.

Fig. 3. a) Example of JBS diodes I(V) measurements for bulk and SmartSiC (with specific differential resistance definition). b) Extracted Rdif for different JBS diode designs (+Schottky) as function of the Schottky surface ratio.

Fig. 3. a) Example of JBS diodes I(V) measurements for bulk and SmartSiC (with specific differential resistance definition). b) Extracted Rdif for different JBS diode designs (+Schottky) as function of the Schottky surface ratio.

Fig. 4 shows the JBS Ron-BV figure of merit for the studied JBS samples with a comparison to state-of-the-art diodes [7]. For breakdown voltage (BV) ratings between 1400 and 1600 V , we observe that the specific on-resistance (similarly extracted as ) is reduced and is closer to the theoretical limit of for the SmartSiC JBS compared to the bulk reference and also to state-of-the-art JBS devices (including commercial devices with thinned substrates) [7].

Fig. 4. JBS specific ON resistance versus breakdown voltage (for the investigated bulk and SmartSiC hexagonal JBS diodes, compared to state-of-the-art JBS diodes, including commercial products) [7].

Fig. 4. JBS specific ON resistance versus breakdown voltage (for the investigated bulk and SmartSiC hexagonal JBS diodes, compared to state-of-the-art JBS diodes, including commercial products) [7].

On-state resistance behaviour with temperature

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

The forward characteristics were further studied as a function of temperature. The observed conduction gain for the SmartSiC samples (compared to bulk) was investigated from to in Fig. 5 and Fig. 6.

Fig. 5 shows measurements for JBS diodes (with stripes) on bulk and SmartSiC epiwafers, with an observed exponential behaviour. The absolute difference between bulk and is (respectively ) at (resp. ).

Fig. 5. Impact of temperature ( ) on measured specific differential resistance ( ) for JBS diode (reference design with stripes). For both samples, the data can be fitted using an exponential model (as observed for results in [8], cf. Fig. 7).

Fig. 5. Impact of temperature ( ) on measured specific differential resistance ( ) for JBS diode (reference design with stripes). For both samples, the data can be fitted using an exponential model (as observed for results in [8], cf. Fig. 7).

In order to check if this advantage offered by SmartSiC exist also for the other diodes types, we perform similar comparison for the following designs:

JBS with stripes: three designs with various Schottky ratios

JBS with hexagonal cells

Reference Schottky diode

The following figures show extracted versus temperature for these five different diode designs on SmartSiC epiwafer (Fig. 6a) and on bulk epiwafer (Fig. 6b): again, an increasing trend with temperature can be observed for all samples. Besides a minor dispersion between the designs is also highlighted ( ). In Fig. 6c, the differential resistance gain, , between the two epiwafers is calculated and plotted against temperature. The gain offered by SmartSiC epiwafer compared to bulk counterpart is found to be independent on the diode design: (respectively ) at (resp. ).

Fig. 6. a-b) Comparison of for different diodes (JBS with three stripes designs; hexagonal cells JBS, and Schottky) for bulk and SmartSiC epiwafers, c) and corresponding differential resistance gain (bulk-SmartSiC) versus temperature showing identical trend for all diode designs.

Fig. 6. a-b) Comparison of for different diodes (JBS with three stripes designs; hexagonal cells JBS, and Schottky) for bulk and SmartSiC epiwafers, c) and corresponding differential resistance gain (bulk-SmartSiC) versus temperature showing identical trend for all diode designs.

Fig. 7 reveals that all device designs, regardless of epi or substrate (including additional 1700 V epiwafer with the same diode process [4], and literature reference [8]), follow the same predictive behaviour: values at exactly reflect at . This indicates that the model from Fig. 5 can be applied to all these various device/substrate/epi configurations (with very similar To parameter).

Fig. 7. Measured differential resistance at versus for various JBS designs (+Schottky) on different sites (for two wafers with same 1200 V epi, +1700 V bulk epiwafer). Ref [8] bulk data are in agreement with the observed trend.

Fig. 7. Measured differential resistance at versus for various JBS designs (+Schottky) on different sites (for two wafers with same 1200 V epi, +1700 V bulk epiwafer). Ref [8] bulk data are in agreement with the observed trend.

Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

The focus on this paper is to highlight on-resistance difference in the forward operation mode of unipolar 1200 V diodes fabricated on bulk and SmartSiC epiwafers. For the off-state characteristics depicted in Fig. 2, the findings suggest that for the same diode device and epi designs on bulk and SmartSiC , the off-state performance ought to be similar in terms of reverse leakage current levels and non-destructive avalanche breakdown. This also suggests that SmartSiC in the reverse mode
behaves similarly to bulk wafers, which also implies that the engineered substrate does not exhibit additional defects.

In the on-state, differential resistance ( ) has been comprehensively studied between Schottky and several JBS diode designs. The overall forward conduction current in Fig. 3 illustrates the advantage of using SmartSiC to reduce conduction losses with a less resistive handle substrate as reported in [9]. This confirms the influence of substrate resistivity on the on-state performance of power devices. The exponential temperature dependence of demonstrated in Fig. 5 to 7, coupled with the increased absolute difference at further highlight the SmartSiC substrate's stability at high-temperature, which is reported here for the first time.

Further calculations are performed to anticipate and compare the performance of against thinned bulk epiwafers. This requires a decomposition of the different resistance contributions of the diode. Fig. 8 presents the differential resistance partitioning model used, cf. Eq. 1. To avoid additional calculation terms that may emerge from the current spreading in JBS devices, Schottky diodes is preferred here. The three main contributors to the total differential resistance are the epilayer (drift + buffer), substrate, and contacts (anode and cathode) resistances. The resistivity of each layer (Eq. 2, Eq. 3, Eq. 4) is calculated according to Eq. 5 (sheet resistivity) and Eq. 6 (electron mobility). For the electron mobility, Arora model [10] was used with parameters calibrated from [11] for 4H-SiC and from [12] for 3C-poly SiC . The contribution of the contacts is calculated as the resistance contributions deducted from the extracted measured differential resistance.

Fig. 8. Vertical SiC diode differential resistance partitioning model is composed of three primary contributors: epilayer (comprises drift and buffer layers), contacts (anode and cathode), and substrates (bulk vs. SmartSiC ). Arora model [10] for electron mobility is used to calculate the resistivity of each layer and construct the final partition.

Fig. 8. Vertical SiC diode differential resistance partitioning model is composed of three primary contributors: epilayer (comprises drift and buffer layers), contacts (anode and cathode), and substrates (bulk vs. SmartSiC ). Arora model [10] for electron mobility is used to calculate the resistivity of each layer and construct the final partition.

partitioning is calculated for both and bulk epiwafers in addition to a thinned down version of the bulk substrate at and temperatures as shown in Fig. 9. It is observed that SmartSiC substrate ( , without thinning) exhibited lower resistance even compared to thinned bulk epiwafer. Furthermore, these calculations bring new insights on the extracted shown in Fig. 6c: the gain can be attributed to the substrate ( ) and partially to the back side contact ( , as the anode and epi components are identical for both samples.

Fig.9. RDIF partitioning calculations at a) and b) for Schottky diodes with same epi. For bulk epiwafer, is reduced with substrate thinning. SmartSiC substrate enables further reduction without thinning.

Fig.9. RDIF partitioning calculations at a) and b) for Schottky diodes with same epi. For bulk epiwafer, is reduced with substrate thinning. SmartSiC substrate enables further reduction without thinning.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

This study compares 1200 V 4H-SiC power diodes on two different substrate technologies (single crystal reference bulk and 3 C -poly silicon carbide based substrates: SmartSiC ). The reverse mode measurements demonstrate that substrate material has a minimal impact on defect propagation affecting off-state performance, as both bulk and SmartSiC exhibit similar nondestructive avalanche characteristics due to identical drift layers and device structures. The specific differential resistance ( ) decreases with an increase in Schottky surface ratio, with hexagonal configurations yielding the lowest resistance, particularly in samples. JBS diodes fabricated on SmartSiC showed superior current conduction and lower resistance in the ohmic regime, highlighting the significance of substrate resistivity. The results also reveal an exponential temperature dependence of , indicating that substrate properties, including thickness, play a crucial role in high-temperature device performance.
Overall, introducing SmartSiC enables to optimize device performance (reducing specific onresistance even at high temperature) while sustaining similar off-state behaviour compared to standard bulk. This study paves the way for further investigations related to dynamic performance and reliability/ruggedness to consolidate the SmartSiC position in power electronics.

Funding

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

This project has received funding from the Key Digital Technologies (KDT) under Grant Agreement No 101007237 (TRANSFORM). The KDT receives support from the European Union's Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

The authors would like to express their sincere gratitude to the other members of the research team: Dr. Julie Widiez, Saliou Gningue from CEA-Leti for data interpretation and assistance in electrical measurements; Dr. Séverin Rouchier and Dr. Walter Schwarzenbach from Soitec for substrates preparation and discussion on results. Their expertise and commitment were instrumental in the realization of our research objectives.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.41.pdf

E. Guiot, F. Allibert, J. Leib, T. Becker, W. Schwarzenbach, C. Hellinger, T. Erlbacher, and S. Rouchier, "Proven Power Cycling Reliability of Ohmic Annealing Free SiC Power Device through the Use of SmartSiC Substrate", MSF 1092, 201-207 (2023). https://doi.org/10.4028/p-777hqg

S. Rouchier, G. Gaudin, J. Widiez, F. Allibert, E. Rolland, K. Vladimirova, G. Gelineau, N. Troutot, C. Navone, G. Berre, D. Bosch, Y.L. Leow, A. Duboust, A. Drouin, J.M. Bethoux, R. Boulet, A. Chapelle, E. Cela, G. Lavaitte, A. Bouville-Lallart, L. Viravaux, F. Servant, S. Bhargava, S. Thomas, I. Radu, C. Maleville, and W. Schwarzenbach, " 150 mm SiC Engineered Substrates for High-Voltage Power Devices," MSF 1062, 131-135 (2022).

O. Bonnin, "SmartSiC : A Greener, Faster and Better Technology for SiC," Semicon Europa Conference, 2023. Olivier%20Bonnin.pdf

D. Clark et al., "CPD1 Clas-SiC Planar MPS/JBS diode Process Design kit", Clas-SiC Wafer Fab, 2021.

G. Gelineau, J. Widiez, E. Rolland, K. Vladimirova, A. Moulin, V.S. Prudkovskiy, N. Troutot, P. Gergaud, D. Mariolle, S. Barbet, V. Amalbert, G. Lapertot, K. Mony, S. Rouchier, R. Boulet, G. Berre, W. Schwarzenbach, and Y. Bogumilowicz, "Evaluation of Crystal Quality and Dopant Activation of Smart Cut - Transferred 4H-SiC Thin Film," MSF 1089, 71-79 (2023).

T. Kimoto, and H. Watanabe, "Defect engineering in SiC technology for high-voltage power devices," Appl. Phys. Express 13(12), 120101 (2020).

A. Gendron-Hansen, D. Sdrulla, B. Odekirk, A.S. Kashyap, and L. Starr, "4H-SiC 1200 V Junction Barrier Schottky Diodes with High Avalanche Ruggedness," MSF 924, 585-588 (2018). . 924.585

J. Millan, V. Banu, P. Brosselard, X. Jorda, A. Perez-Tomas, and P. Godignon, "Electrical performance at high temperature and surge current of 1.2 kV power rectifiers: Comparison between Si PiN, 4H-SiC Schottky and JBS diodes," in 2008 International Semiconductor Conference, (IEEE, Sinaia, Romania, 2008), pp. 53-59.

W. Schwarzenbach, S. Rouchier, G. Berre, R. Boulet, O. Ledoux, E. Cela, A. Drouin, A. Chapelle, S. Monnoye, H. Biard, K. Alassaad, L. Viravaux, N.B. Mohamed, D. Radisson, G. Picun, G. Lavaitte, A. Bouville-Lallart, J. Roi, J. Widiez, K. Abadie, E. Rolland, F. Fournel, G. Gelineau, F. Mazen, A. Moulin, C. Moulin, D. Delprat, N. Daval, S. Odoul, P. Sandri, and C. Maleville, "Engineered SiC materials for power technologies," in 2022 International Conference on IC Design and Technology (ICICDT), (IEEE, Hanoi, Vietnam, 2022), pp. 5556.

N.D. Arora, J.R. Hauser, and D.J. Roulston, "Electron and hole mobilities in silicon as a function of concentration and temperature," IEEE Trans. Electron Devices 29(2), 292-295 (1982).

K. Tian, J. Xia, K. Elgammal, A. Schöner, W. Kaplan, R. Karhu, J. Ul-Hassan, and A. Hallén, "Modelling the static on-state current voltage characteristics for a PiN diode," Materials Science in Semiconductor Processing 115, 105097 (2020).

A. Arvanitopoulos, N. Lophitis, K.N. Gyftakis, S. Perkins, and M. Antoniou, "Validated physical models and parameters of bulk 3C-SiC aiming for credible technology computer aided design (TCAD) simulation," Semicond. Sci. Technol. 32(10), 104009 (2017).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 51-58

doi: 10.4028/p-O4vzNM

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-13

Accepted:
2025-08-14

Online:
2025-09-05

Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

The original version of this paper is available on https://www.scientific.net/KEM.1021.51.pdf

V. Kotagama , A.B. Renz , K. Melnyk , G.W.C. Baker , V.A. Shah , M. Antoniou , P.M. Gammon

School of Engineering, University of Warwick, Coventry, UK

Arne.Renz@warwick.ac.uk, Kyrylo.Melnyk@warwick.ac.uk, Guy.W.C.Baker@warwick.ac.uk, Vishal.Shah@warwick.ac.uk, Marina.Antoniou@warwick.ac.uk, 9P.M.Gammon@warwick.ac.uk

Abstract

This paper investigates the charge balancing and performance optimization of two 1.2 kV rated Semi-Superjunction (SSJ) MOSFETs. Beginning with a conventional double trench MOSFET, SJ trenches are imposed in 2D (within the X-Y plane unit cell) and in 3D (trenches in Z-Y plane, perpendicular to the gate trench). The optimization of these structures focuses on the effects of ppillar doping, tilt angle, and z-plane pillar width and the trade-off between specific on-resistance , breakdown voltage (BV), implantation window, and gate reliability is assessed for each configuration. The 2D SSJ MOSFET, is the device that offers the highest breakdown voltage of those assessed ( 1781 V ) and the widest implantation window ( ), when implemented with a vertical trench sidewall, while this is a trade-off against achieving the lowest with a side wall angle. In the 3D SSJ MOSFET, a reduced p -pillar depth in the z -dimension, and hence a higher doping density, leads to a significant improvement in . The Z-plane p-pillars in the 3D device efficiently deplete its JFET region, causing the of the 3D devices to be higher than the 2D devices, and the breakdown voltage lower. However, this also results in very low electric field ( ), in the gate oxide, offering a safe alternative to the 2D devices ( ). Differences between the devices could be narrowed in the future with optimal JFET design.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.51.pdf

4 H -silicon carbide ( SiC ) metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are an efficient, fast-switching alternative to Silicon ( Si ) IGBTs in the class. This is primarily due to SiC's 9 times larger critical electric field and relatively high thermal conductivity [1] compared to Si. Recently, double trench MOSFET architectures [2] have come to the fore that deliver a narrow cell pitch, thereby reducing, in turn, specific on resistance, die size and switching losses, while this structure also protects the gate oxide from high electric fields in the off state and in fault states such as short circuit.

Until now, the fast-paced advancement of SiC production methods is yet to result in a commercialized superjunction (SJ) MOSFET. While a SiC SJ could further improve the trade-off between breakdown voltage (BV) and specific on-resistance ( ), from to [2], the multiepitaxial SJ fabrication process used is not commercially feasible in SiC processing. This is due to the high cost, growth complexity, defect sensitivity, and low yield of fabrication [4]. However, demonstrator SJ devices produced via a trench etch and epitaxy refill method [5] or a trench etch and sidewall implant [5,6], may offer a practical alternative. This is due to the more simplistic approach of reducing the number of epitaxial steps, providing better control over doping profiles and minimizing defect introduction. This leads to higher yields and lower production costs compared to multi-epitaxial methods.

To realize high-performing SJ structures in SiC devices, a high aspect ratio (trench depth divided by trench width) is required to uniformly distribute the electric field across the device. Achieving an optimal BV also depends on a precise dopant diffusion process that introduces a uniform P-doping layer, ensuring accurate charge balance between the alternating P - and N -doped regions. This enhances BV significantly without increasing device size or on-resistance, optimizing both performance and efficiency. However, in practice, this ideal case is difficult to achieve. The SJ structure faces implantation challenges as maintaining an exact doping concentration along the entire depth of a deep trench is technically complex. More critically, the sidewall plays a vital role in the performance of the SJ structure, as it is crucial to maintaining a constant doping concentration along the entire depth of a deep trench. This ensures effective charge balancing and electric field distribution. Typically, the doping variation can range between to depending on several factors, which leads to charge imbalance, reducing the maximum achievable BV and potentially degrading the device's overall performance and reliability [7]. In a prior study, the reduction of the strict SJ requirements of optimal trench aspect ratio and doping implantation window was explored on 1.7 kV SiC Schottky diodes [6]. This was done through a combination of varying sidewall tilt angles to expand the implantation window, and semi-Superjunction (SSJ) implementations to reduce the trench depth and fabrication costs.

In this study, the implementation of two practical SSJ topologies are compared in Sentaurus TCAD simulations. The starting point of the investigation is a 650 V rated double trench MOSFET benchmarked elsewhere [8], from which two SSJ MOSFET implementations are developed in the same thickness of epitaxy. A conventional, 2D SSJ implementation is produced entirely within the X-Y plane by extending the existing source trenches throughout the epitaxial region, implantations into the sidewalls resulting in a charge balanced SSJ. This is compared with a 3D implementation, in which a trench is etched in the X-Z plane, behind the active gate trench.

SJ technology is usually implemented at relatively high voltages. However, even at , a SSJ will be shown to facilitate lower drift region resistance contributions compared to the double trench MOSFET, while supporting a higher voltage rating. Were this to be paired with innovations that reduce the channel resistance [9], and the substrate resistance [10], this could lead to a highly efficient, low resistance MOSFET.

Simulated Structure

The original version of this paper is available on https://www.scientific.net/KEM.1021.51.pdf

The location of the SSJ p-pillar is explored in planes both parallel (X-Y, "2D device") and perpendicular (Z-Y, "3D Device") to the device active area, as seen in Fig.1. The SSJ SiC MOSFETs are developed using a trench etch and sidewall implantation. The device substrate consists of a substrate with a doping concentration of , that is assumed to have been thinned to 140 . The drift region has been split into three vertical sections; a N-bottom assist layer (NBAL) with a doping concentration of , a charge balanced, low resistance n -drift region, and finally then a low doped Junction Field Effect Transistor (JFET) region designed to fully deplete to protect the gate oxide. In prior literature, the NBAL structure has been shown to support the higher electric field spread at the base of the SJ by providing a gradual transition from the high-resistance substrate to the low resistance drift region [11].

Fig.1.a. A 2D (2D plane, parallel trench) SiC SSJ with varying P-pillar tilt ( ). Fig.1.b. A 3D ( plane, perpendicular trench) SiC SSJ with varying drift region width .

Fig.1. a. A 2D (2D plane, parallel trench) SiC SSJ with varying P-pillar tilt ( ). Fig.1.b. A 3D ( plane, perpendicular trench) SiC SSJ with varying drift region width .

For the 2D SSJ MOSFET, a n-Drift region with a fixed doping concentration of is grown. For the 3D SSJ MOSFET, a -drift region is also grown, however is varied from , and for a drift region width ( ) of , and half-cell, respectively. Above the drift region, a thick JFET region is grown with a fixed doping concentration of . Above this, a channel region and a contact region. A trench of is created to create the gate. For the 2D SSJ MOSFET, a trench of is created on the sides of the active region to implant a thin Pdoped layer of 5 nm for the SSJ. The trenches are wide enough to ensure a tilted implantation ( from vertical) can reach the entire trench sidewall. Where implemented, a sidewall angle of up to pivots from the device surface, effectively widening the lower drift region, but ensuring minimal impact on the gate structure. For the 3D SSJ MOSFET, deep source trenches are formed for the P -doping implantation of the source P -wells. Perpendicular, in the X -Z plane, a 6.8 deep trench allows for the implant of a thin P-doped layer of 5 nm for the SSJ. The SSJ trench width is fixed at for both 2D and 3D SSJ MOSFETs. All trenches are passivated with Silicon Dioxide ( ). All P -doped regions are formed using Aluminum ion implantation. The selection of the doping concentration is calculated through Gauss's Law based on a critical electric field of for [12].
The devices are simulated at room temperature using the "Sentaurus" module from the TCAD package Synopsys.

Table 1. Summary of key device design geometry and parameters.

Symbol
Definition
2D P-pillar tilt (°)
3D half-cell thickness
(μm)
Units

0, 2.5, 5, 7.5 10,12.5
0.5, 1, 2

tdepth
Drift region depth
8.6
8.6

tcell
Cell pitch
2
1, 2, 4 (z-axis) 2 (x-axis)

tsub
Substrate thickness
140
140
μm

dpillar
Drift region width
1
1, 2, 4

tpdop
P-pillar thickness
5
5
nm

ND
Drift region doping
1×10¹⁷
2×10¹⁷, 1×10¹⁷, 5×10¹⁶

NBAL
n-Bottom Assist Layer
doping
1.5×10¹⁶
1.5×10¹⁶
cm³

Nsub
Substrate doping
1×10¹⁹
1×10¹⁹

Vth
Threshold Voltage
~6.33
6.55, 7.04, 7.08
V

Ron,sp
Specific on-resistance
1.61, 1.51, 1.46, 1.34, 1.23, 1.15
1.52, 1.63, 2.36
mΩ.cm²

BVmax
Max. Breakdown
Voltage
1781, 1728, 1668,1591, 1520, 1431
1539, 1540, 1338
V

Fig.2. (left) Comparison of the 2D SiC SSJ with varying and 3D SiC SSJ with varying drift region width (dpillar) on the optimal SJ p-pillar doping required for charge balancing. Fig.3. (right) Tradeoff between the BV and Ron,sp for the 2D plane SiC SSJ with varying and 3D SiC SSJ with varying drift region width ( ).

Fig.2. (left) Comparison of the 2D SiC SSJ with varying and 3D SiC SSJ with varying drift region width (dpillar) on the optimal SJ p-pillar doping required for charge balancing. Fig.3. (right) Tradeoff between the BV and Ron,sp for the 2D plane SiC SSJ with varying and 3D SiC SSJ with varying drift region width ( ).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.51.pdf

Charge balancing simulations, shown in Fig. 2a, are carried out to analyze the effect that SJ p-pillar doping has on the implantation window, the allowable discrepancy from the optimum doping. The implantation window is defined in this study as the percentage difference between the optimal SJ Ppillar doping for maximum breakdown voltage and the minimum doping required to achieve a 1300 V breakdown voltage. For the 2D SSJ MOSFET, this shows a clear decreasing trend with increasing tilt angle, with a implantation window at at at at , at , and at . This implies that increasing the tilt angle reduces the processing window, making it more difficult to precisely control the implantation process to avoid breakdown voltage degradation. This could present challenges in manufacturing, particularly for devices
requiring higher tilt angles for other design constraints. For the 3D SSJ MOSFET, there is a slight increase in implantation window with dpillar by at to at . However, there is massive drop in implantation window to at . This suggests that a smaller offers a wider processing window, making the device more robust to doping variations, while larger widths significantly constrain the window, suggesting that larger structures require stricter control over the doping process to prevent performance loss. These implantation window changes are visualized in Fig.2.

In addition, each SSJ MOSFET is compared to the theoretical unipolar limit of , shown in Fig.3, to quantify the BV vs performance. The no tilt 2D SSJ MOSFET achieves a of lower than the original benchmarked double trench MOSFET. With increasing tilt angle, this improves further, a tilt angle of , reducing the by a further 6.3, 8.8, 16.3, 23.1, compared to no-tilt ( ). This is potentially due to reduction in JFET resistance as a larger JFET area is required for increasing tilt angle. As a result, these designs could offer significant advantages for applications at a 1.2 kV rating requiring lower conduction losses and higher efficiency while still maintaining a balance between BV and Ron,sp.

Fig.4. Electric field profiles along active region of devices (seen in fig.1) for the 2D (top) and 3D (bottom) SSJ MOSFET at breakdown voltage.

Fig.4. Electric field profiles along active region of devices (seen in fig.1) for the 2D (top) and 3D (bottom) SSJ MOSFET at breakdown voltage.

Fig.5. Electric field profiles along the gate oxide to below gate oxide depth (seen in fig.1) for the 2D (top) and 3D (bottom) SSJ MOSFET at 800 V voltage.

Fig.5. Electric field profiles along the gate oxide to below gate oxide depth (seen in fig.1) for the 2D (top) and 3D (bottom) SSJ MOSFET at 800 V voltage.

The 3D SSJ MOSFET shows an improvement in with reducing , the resistance is lower than the original benchmarked double trench MOSFET. This is lower compared to a of , due to the impact of a higher of at , compared to at a . This contributes to the reduction of the JFET resistance, which results in a total net decrease in for the 3D SSJ MOSFET. It can be noted that the 2D SSJ MOSFET with a tilt angle has the lowest due to the minimized JFET resistance. These results can be visualized in Fig.3.

The effect of the SSJ on both 2D and 3D MOSFETs on BV can be further analyzed through the electric field profile at the point of breakdown, shown in Fig.4. For the 2D device with a vertical sidewalls ( tilt), a flat electric field profile can be seen between the top ( ) and the bottom of the drift region, which is symbolic of a balanced SJ. As the tilt angle increases, three effects combine to reduce the total voltage supported. First, the increasing tilt angle causes the SJ region to become increasingly unbalanced, the charge imbalance becoming more pronounced in the centre, bottom of the drift region. With a tilt angle of and the electric field at the bottom of the SJ region, drops from to and , respectively. Second, a reduction in electric field at the bottom of the SJ region reduces the field supported within the NBAL region, so the field supported in the NBAL also reduces with increasing tilt angle. Thirdly. the electric field at the top of SJ region also reduces from for a tilt angle of , to 1.8 for a tilt angle of . These results explain the breakdown results seen, the maximum BV reducing with increasing tilt angle.

The electric field at the bottom of the 3D SSJ MOSFET decreases with at 2.5, at a of , and , respectively. There is also a similar decrease in electric field seen at the SSJ start, of , and for a of , and , respectively. There is also an impact of reducing electric field held within the NBAL region during breakdown with increasing , seen in Fig.4. These results also correspond with the breakdown results seen, with the charge balance effect weakening, causing the BV to reduce as increases.

The 2D SJ devices support a greater BV than the 3D SJ devices, as seen in Fig.2. This can be explained by comparing their electric field profiles in the JFET region, seen in Fig.4. The electric field profile in the JFET region of the 3D device is kept at a very low level, below . This occurs because the additional SJ pillars in the Z-X plane, result in the JFET region being surrounded on all four sides by regions. This results in a lateral depletion effect that is stronger than the vertical one, fully depleting this region. In contrast the JFET region of the conventional 2D device is confined on only two planes and a vertical field is allowed to penetrate this region.

This difference in electric field within the JFET region has an impact on gate reliability, which is a significant factor to consider for device design performance. The electric field held within the gate oxide at the operating voltage (assumed to be 800 V for these devices as they block ) significantly impacts the reliability, efficiency, and long-term stability of MOSFETs. Seen in Fig.5, the electric field in the gate oxide of the 3D device is much lower than the 2D device, due to the strong lateral depletion effect in the 3D JFET. The very low gate oxide electric field of is present for all the 3D SSJ MOSFET devices. For the 2D devices, a tilt angle of results in the minimum gate oxide electric field of for. The tilted device performs the worst in the dataset, with an electric field of .

Through all the devices in this investigation, the JFET doping was held constant at , as per the original benchmark device. This value proved to be relative low for the 3D device, its full lateral depletion offering maximum protection to the gate and preventing any electric field increase that would contribute to the total blocking voltage. Conversely, in the 2D device, the JFET doping appears too high, as the field was allowed to penetrate this region, adding a significant
contribution to the total voltage, while jeopardizing the oxide reliability. It is clear that in future studies the relative gap between these structures could be narrowed through JFET doping optimization.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1021.51.pdf

The paper presents an extensive analysis of charge balancing in SSJ MOSFETs, exploring the effects of a 2D vs 3D implementation, P -pillar doping and geometrical factors such as tilt angle on performance parameters and gate oxide electric field, and implantation window. For the 2D implementation, increasing the tilt angle up to reduces by effectively widening the JFET region. However, the increased tilt angle also narrows the implantation window and reduces the breakdown voltage as greater charge imbalance occurs. For the 3D SSJ MOSFET reducing the pillar depth allows for higher doping concentrations, significantly improving the . However, a narrow implantation windows reduce the practically of implementing such a design. The importance of the JFET region on gate oxide reliability and breakdown voltage was revealed as a key trade off in the two device implementations. In the 2D MOSFETs, a relatively weak lateral depletion from its two sides allowed field to penetrate to the gate, adding blocking voltage but increasing the field in the gate oxide. This could be optimised, using a tilt angle of but this remained 2.5 times higher than the 3D implementation, where a strong depletion on four sides of the JFET region fully prevented a vertical field building up and lowering BV. The findings provide an insight into optimizing SJ device design for better efficiency and reliability, highlighting the trade-offs between doping, geometrical structure, and performance metrics in SSJ MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.51.pdf

X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, "Review of silicon carbide power devices and their applications," IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 81938205, 2017.

P. Gammon, .

C. Wang et al., "Performance limit and design guideline of superjunction devices considering anisotropy of impact ionization," IEEE Electron Device Letters, vol. 43, no. 12, pp. 2025-2028, 2022.

M. Sometani et al, 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs, pp. 337-340.

G. Colston et al., "Epitaxial trench refill of by chlorinated chemistry," Applied Physics Letters, vol. 124, no. 19, 2024.

G. Baker et al., "Optimization of 1700-V 4H-SiC Semi-Superjunction Schottky Rectifiers With Implanted P-Pillars for Practical Realization," IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1924, 2022.

A. Afanasev, V. Ilyin, and V. Luchinin, "Ion Doping of Silicon Carbide in the Technology of High-Power Electronic Devices," Semiconductors, vol. 56, no. 13, pp. 472-486, 2022.

A. Renz et al., "The improvement of atomic layer deposited interfaces via a high temperature forming gas anneal," Materials Science in Semiconductor Processing, vol. 122, p. 105527, 2021.

Soitec, .

S. Ono, W. Saito, M. Takashita, S. Kurushima, K. i. Tokano, and M. Yamaguchi, "Design concept of n -buffer layer ( n -Bottom Assist Layer) for 600 V -class Semi-Super Junction MOSFET," in Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's, 2007: IEEE, pp. 25-28.

X. Zhou, Z. B. Guo, and T. P. Chow, "Performance limits of vertical and superjunction devices," in Materials Science Forum, 2019, vol. 963: Trans Tech Publ, pp. 693696.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 59-67

doi: 10.4028/p-5KX9qK

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-05

Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

Y. Higashi , S. Ishikawa , K. Ozono , H. Sezaki , M. Kobayashi , H. Uchida , M. Okamoto , S. Harada , K. Kojima , T. Kato and Y. Tanaka

Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki 305-8568, Japan

PHENITEC SEMICONDUCTOR Corp., 6833, Kinoko-cho, Ibara, Okayama 715-8602, Japan

SICOXS Corporation, 5-11-3, Shimbashi, Minato-ku, Tokyo 105-0004, Japan

a*higashi-phenitec@aist.go.jp, ishikawa-seiji@aist.go.jp, ckunihide-oozono@phenitec.co.jp, Hiroshi-sezaki@phenitec.co.jp, motoki.kobayashi.x2@smm-g.com, hidetsugu.uchida.x7@smm-g.com, mitsuo-okamoto@aist.go.jp, s-harada@aist.go.jp, ikazu-kojima@aist.go.jp, it-kato@aist.go.jp, kyasunori-tanaka@aist.go.jp

Keywords: Bonded substrate, DMOSFET, Static and dynamic characteristics, Bipolar degradation, High temperature reliability

Abstract

A novel substrate of bonded substrate is expected to solve issues such as decreasing the on-resistance, which has attracted much attention. Therefore, several studies have been conducted on the use of bonded substrates. In this study, we fabricated a DMOSFET on a bonded substrate and compared its static and dynamic characteristics with those on a single-crystal substrate. Consequently, the on-resistance of the DMOSFET fabricated on a bonded substrate was lower than that on a single-crystal substrate owing to the low resistivity of the polycrystalline substrate. Also, reverse recovery loss of the DMOSFET fabricated on a bonded substrate was lower than that on single-crystal substrate at high temperature due to low carrier lifetime in a drift layer. Additionally, we observed that the DMOSFET fabricated on a bonded substrate did not generate bipolar degradation despite the application of a forward-current stress of over . According to these results, we expected that the carrier lifetime in both drift layer and transfer layer was decreased on a bonded substrate.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

Power devices based on silicon carbide (SiC) are being increasingly developed. However, these devices still have issues such as on-resistance and long-term reliability. Recently, a novel substrate comprising an extremely thin (submicron) monocrystalline layer bonded to a polycrystalline 3C-SiC substrate, we called bonded substrate, was developed [1] [2]. However, there have been few studies on devices fabricated using bonded substrates, especially MOSFETs. This bonded substrate is expected to reduce the on-resistance of the vertical device and simplify the formation of the backside ohmic contact [3]. In addition, suppression of forward-bias degradation has been reported for PiN diodes [4], that is, the bonded substrate is expected to be effective as a body diode in MOSFET. Therefore, the purpose of this study was to verify the properties of a Double-implanted MOSFET (DMOSFET) fabricated on a bonded substrate. In this study, we fabricated a DMOSFET on a bonded substrate and compared its static and dynamic characteristics, suppression of forward bias degradation, and high-temperature reliability with those for monocrystalline substrate.

Experiment

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

1. Fabrication of bonded substrate

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

Figure 1 shows a flowchart of the bonded substrate ( ) manufactured by SICOXS. A polished monocrystalline substrate was implanted with proton and phosphorus ions. Subsequently, the monocrystalline substrate was directly bonded with the polished polycrystalline substrate, and the bonded one was thermally split into two. In these processes, the bonded substrate forms a thin monocrystalline layer, called the transfer layer, on top of the polycrystalline substrate. The transfer layer thickness is approximately and its doping concentration is the same as that of a conventional monocrystalline substrate. However, the doping concentration of the polycrystalline substrate is higher than that of the monocrystalline substrate. Thus, the bonded substrate has lower resistivity than the conventional monocrystalline substrate.

2. Fabrication of DMOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

Figure 2 shows the cross-sectional schematics of 1.2 kV -class DMOSFETs fabricated on a single-crystal substrate (mono-MOS) and a SICOXS's bonded substrate (bonded-MOS). The resistivity of the bonded substrate is approximately , which is approximately one-third of that of the single-crystal substrate. The fabrication conditions and device structures, including the drift layer, were identical. The drift layer thickness and concentration were and . The drift layers on both substrates were grown under the same conditions, such as temperature and gas flow. The DMOSFET structure was formed by conventional double-implantation technique in which the p -base and -contact region were implanted with aluminum ions, and the -source was implanted with phosphorus ions. The gate oxide film thickness was 50 nm , which was formed by high-temperature chemical vapor deposition and nitric oxide (NO) annealing, and phosphorus doped gate polysilicon was formed on the gate oxide film. The ohmic metals for the source and drain electrodes were Ni and , respectively. The chip size of the fabricated DMOSFET was , and its chip thickness was approximately ; without thinning process.

3. Measurement

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

The fabricated DMOSFETs were characterized by static current-voltage measurements and reverse recovery of the body diode. Furthermore, the forward voltage shift caused by the forward current stress and high temperature reliability were tested. Each testing conditions were shown in each experiment summary.

Fig. 1 Brief flowchart the bonded substrate[8]

Fig. 1. Brief flowchart the bonded substrate[8]

Fig. 2 Schematic cross-section of a DMOSFET

Fig. 2. Schematic cross-section of a DMOSFET

Results and Discussions

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

1. Static characteristics of DMOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

First, we evaluated the static characteristics of the MOSFET part in the fabricated DMOSFET at room temperature (RT) and . Fig. 3 shows the blocking characteristics. Both the mono-MOS and bonded-MOS exhibited similar blocking voltage ( ) over 1500 V at each temperature. On the other hand, the drain current (Id)-drain voltage (Vd) characteristics exhibited clear differences between mono-MOS and bonded-MOS, as shown in Fig. 4. At a drain current of 20A, the bondedMOS had and higher current than the mono-MOS at RT and , respectively. The suppressed on-resistance is primarily caused by low-resistivity polycrystals in the bonded substrates.

2. Static and dynamic characteristics of body diodes

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

Second, we evaluated the static characteristics of the body diodes in the fabricated DMOSFET on each substrate at RT and . Fig. 5 shows the forward current ( )-forward voltage ( ) characteristics of the body diode inside the fabricated DMOSFETs. At RT, almost no differences were observed between the two devices, despite the bonded substrate having a lower resistance. This means the low lifetime of minority carrier in the bonded-MOS. Furthermore, at high temperature, although decreases by the lifetime increasing, the bonded-MOS exhibited a higher than the mono-MOS. However, considering the dead time of inverter operation, the increase in conduction loss is negligible. This trend was similar to that of a PiN diode fabricated on a bonded substrate [4]. We believe that the lifetime of minority carriers in the drift layer is suppressed even at high temperatures compering to on a single-crystal substrate when the drift layer is grown on a bonded substrate.
Next, we examined the reverse-recovery characteristics because it was also influenced by the lifetime of minority carrier. Fig. 6 shows the reverse-recovery waveform of the body diode. The reverse recovery current ( ) exhibited almost no difference between mono-MOS and bonded-MOS at RT, which might be due to the dominant junction charge. In contrast, the Irr of the bonded-MOS was lower than that of mono-MOS at high temperature. These reverse-recovery charge ( ) values calculated by the integral of along time was less than that of mono-MOS. In other words, the recovery loss of bonded-MOS is less than that of mono-MOS at high temperature. This result also indicates that carrier lifetime of bonded-MOS is lower than that of mono-MOS.

Fig. 3 Dependence of the blocking characteristics of DMOSFETs on temperature

Fig. 3. Dependence of the blocking characteristics of DMOSFETs on temperature

Fig. 4 Dependence of the characteristics of DMOSFETs on temperature

Fig. 5 Dependence of the characteristics of DMOSFETs on temperature

Fig. 5. Dependence of the characteristics of DMOSFETs on temperature

Fig. 6 Reverse-recovery waveforms of the body diode

3. Forward current stress testing

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

Previous studies have demonstrated that forward-bias degradation was suppressed in a PiN diode fabricated on bonded substrate [4]. Therefore, we examined forward voltage shift ( ) of body diode. Forward current stresses of , and were applied on the body diodes using direct (DC) or alternating current (AC) and their were evaluated after the test. Fig. 7 shows the flowchart diagram of the forward current stress test and the definition of the forward voltage shift. Increased current stress was applied in four steps at . The degree of forward bias degradation was quantitatively defined as at a forward current of 60 A , as shown in right graph in fig. 7. Fig. 8 shows the characteristics before and after the forward current stress test. Almost no differences were observed between the MOSFETs before the stress testing; however, the mono-MOS had a clearly lower current than the bonded-MOS at the end of the testing. The summary of the changes by the forward current stress test is shown in Fig. 9. The increases with increased current stress in the mono-MOS, whereas it remained unchanged in the bonded-MOS even after testing at .

Fig. 7 Flowchart diagram of the forward-current stress test and definition of

Fig. 7. Flowchart diagram of the forward-current stress test and definition of

The increase in is generally caused by the expansion of Shockley stacking faults (SSFs). Thus, after the test, all materials constituting the device on the drift layer were removed, and SSFs were observed using photoluminescence (PL) imaging. Fig. 10 shows the PL imaging results with a 420 nm band-pass filter obtained for each sample. Numerous SSF expansions were observed over the entire area of the mono-MOS. However, SSFs were not observed in the bonded-MOS. These tendencies were the same as those of a PiN diode fabricated on a bonded substrate [5]. They confirmed that the SSFs expanded in the epitaxial layer and stopped above the transfer layer by TEM observation. It was suggested that proton implantation for the wafer splitting process might generate a large number of trap centers such as which decreased the lifetime and suppressed the SFF expansion in the transfer layer. On the other hand, decreasing of and were originated from the low carrier lifetime in the drift layer of the bonded-MOS. Therefore, we expect that the low carrier lifetime in the drift layer is caused by trap centers including the diffused from the transfer layer. Actually, increased with shortened carrier lifetime were measured by DLTS and -PCD in the drift layer on bonded substrate [6].

Fig. waveforms at the start and end of testing

Figure 6. Fig. waveforms at the start and end of testing

Fig. 9 Changes in the caused by forwardcurrent stress of the body diode

Fig. 9. Changes in the caused by forwardcurrent stress of the body diode

Fig. 10 PL imaging results after the stress testing (a band-pass filter of 420 nm is applied)

Fig. 10. PL imaging results after the stress testing (a band-pass filter of 420 nm is applied)

Fig. 10 PL imaging results after the stress testing (a band-pass filter of 420 nm is applied)

Fig. 10. PL imaging results after the stress testing (a band-pass filter of 420 nm is applied)

Table 1 Test conditions for HTRB and burn-in

Test item | Test Condition | Duration | Number of samples
HTRB | Ta= 175°C | 1000hr | 8(each 4)
VR = 1200V
Burn-in | Ta = 175°C | 1000hr | 6(each 3)
VGS = +20/-10V
| Ta = 175°C | 1000hr | 6(each 3)
| VGS = +22/-12V |  |

4. High Temperature Reliability

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

High temperature reliability was compared between the fabricated bonded-MOS and mono-MOS to confirm the long-term reliability characteristics. We conducted high-temperature reverse bias (HTRB) and burn-in tests for each fabricated device. Table 1 lists the test conditions. Before and after the tests, reverse leakage-current ( ) at a of 1.2 kV , breakdown voltage (BV) at of 0.2 A , gate leakage-current (IGSS) at of 22 V , and threshold voltage ( ) at of 10 V and of 18 mA were evaluated. In addition to the standard condition, severe gate voltages (V GS) were applied for burn-in test to confirm under more severe conditions. Figs. 11 and 12 shows the current-voltage characteristics at five different time points , and 1000 h by the two tests. The HTRB test results exhibited no significant differences between the two devices. In addition, the burn-in test results, including severe conditions, exhibited no significant differences, similar to the HTRB. These results were also similar to other reported reliability test results of DMOSFETs fabricated on monocrystalline substrate [7]. Therefore, we believe that the bonded-MOS has no issue concerning the high temperature reliability. It is necessary to investigate the long-term reliability at the bonded interface.

Fig. 11 Characteristic values (Idss, BV, Igss, Vth) after HTRB testing

Fig. 11. Characteristic values (Idss, BV, Igss, Vth) after HTRB testing

Fig. 12 Characteristic values (Idss, BV, IGss, V th) after burn-in testing

Fig. 12. Characteristic values (Idss, BV, IGss, V th) after burn-in testing

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

In this study, we have reported, for the first time, the superior characteristics of a DMOSFET fabricated on a bonded substrate. The bonded-MOS had clearly lower on-resistance than the mono-MOS because of the low resistivity of the polycrystalline substrate even though there were no difference in blocking voltage. On the other hand, the body diode in the bonded-MOS exhibited a higher and lower than that in the mono-MOS at high temperature. By the forward-current stress testing, the increased with increased current stress in mono-MOS, and its SSFs significantly expanded over the entire area, whereas the remained unchanged and no SSFs were observed in the bonded-MOS. Such superior characteristics of the body diode were due to the decreased carrier lifetime in both drift layer and transfer layer on the bonded substrate. Additionally, high-temperature reliability of bonded-MOS was the same as that of Mono-MOS. These results indicated that the bonded substrate has the potential to solve several issues of DMOSFETs fabricated on monocrystalline substrates.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

This study has been implemented under a joint research project of Tsukuba Power Electronics Constellations (TPEC). Y. Higashi and S. Ishikawa are assigned from Phenitec Semiconductor Corporation.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.59.pdf

S. Rouchier, G. Gaudin, J. Widiez, Materials Science Forum 1062, p. 131, 2022

H. Biard, S. Odoul, W. Schwarzenbach, I. Radu, C. Maleville, A. Potier, M. Ferrato, E. Guajioty Solid State Phenomena 344, p. 47, 2023

M. Kobayashi, H. Uchida, N. Hatta, S. Ishikawa, Y. Higashi, H. Sezaki, S. Harada, K. Kojima, Abstract of ICSCRM, 2024

N. Hatta, M. S. Ishikawa, K. Ozono, K. Masumoto, K. Yagi, M. Kobayashi, S. Kurihara, S. Harada, K. Kojima, Key Engineering Materials 948, p. 107, 2023

H. Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, S. Kurihara, S. Harada, K. Kojima, Proceeding of ICSCRM, p. 209, 2023

H. Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, Y. Higashi, K. Masumoto, S. Kurihara, S. Harada, K. Kojima, Abstract of ICSCRM, 2024

G. Wang, L. Yuan, X. Wang, Y. Zhang. R. Jia, Journal of Crystal Growth 606, 127086, 2023

Information on

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 69-74

doi: 10.4028/p-NADj0f

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-05

-SiC VDMOSFET Having On-Current Improvement

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

Y. Widjaja , V. Nebesnyi , A. Asenov , N. Xeni , I. Topaloglu , D. Bensouiah , S. Rathi , R. Young , L. Laborie , Y. Qi , M. Bell , D.T. Clark

VoltA Semiconductor, Inc., Cupertino, CA, USA

Semiwise Ltd., Glasgow, UK

Clas-SiC Wafer Fab Ltd., Lochgelly, UK

ª*ywidjaja@voltasemi.com, vn@voltasemi.com, asen.asenov@semiwise.uk, nikolas.xeni@semiwise.uk,

servin.rathi@clas-sic.com, robert.young@clas-sic.com, ileo.laborie@clas-sic.com,

Keywords: 1200 V , Silicon Carbide, Iow specific on-resistance, on-current improvement, p-well bias.

Abstract

We experimentally demonstrated on-current improvement on VDMOSFET fabricated in a standard 1200 V -rated based VDMOSFET. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A ratio between the on-current gain and the p -well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

SiC has been increasingly used in high-voltage, high-power applications due to its high critical electric field. Improvements in the on-current and specific on-resistance are continuously being sought after through various methods, such as process optimizations [1-3], cell topologies [4], and charge modulations [5]. In this work, we experimentally demonstrated on-current improvement on 1200 V-rated 4H-SiC based VDMOSFET.

Fig. 1(a) illustrates a schematic cross-sectional view of our device, which is fabricated in a standard 1.2 kV 4 H -SiC process. A breakdown voltage of 1500 V is obtained as shown in Fig. 1(b). Typical aluminum and nitrogen implants were used for -well and , respectively. These implants were activated by a high temperature annealing with a carbon cap layer. Gate dielectric was fabricated, including passivation of interface and oxide traps. The front ohmic contacts to were enabled via a self-aligned nickel silicidation. A power metal stack, consisting of , was used to form metallization. For the ohmic back contact, the deposited metal was laser annealed to form an ohmic contact followed by a solderable back metal stack.

Fig. 1.(a) Cross-sectional view of the 1.2 kV VDMOSFET device structure (b) Breakdown characteristic of typical 1.2 kV device

Fig. 1. (a) Cross-sectional view of the 1.2 kV VDMOSFET device structure (b) Breakdown characteristic of typical 1.2 kV device

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

In this work, separate contacts are formed for the p -well and source regions, allowing for independent biasing of the p -well and source regions. A positive bias is applied to the p -well region when the VDMOSFET is in the on-state and is removed when the VDMOSFET is in the off-state. In a conventional VDMOSFET, the p-well and source regions are shorted and typically connected to a common ground.

Fig. 2(a) shows the transfer curves measured from a test structure having a JFET width of with different voltage applied to the p -well region for different Vds. The ratio of the VDMOSFET drain current with and applied to the p -well region for a range of applied gate voltage is shown in Fig. 2(b). As shown in Figs. 2, the drain on-current with a positive bias applied to the p -well region is 2.5 x higher than a conventional VDMOSFET (with applied to the p -well region). The ratio of the drain on-current as a function of applied Vp bias is also shown in Fig. 2(c), indicating that the amount of current flow across the VDMOSFET can be controlled by both gate voltage Vg and p-well bias Vp.

Fig. 2. (a) Transfer curve of VDMOSFET for and 2 V with (solid) and (dashed) (b) Ratio of drain current with and applied, demonstrating the on-current gain with applied (c) Ratio of drain current at different applied Vp and for .

Fig. 2. (a) Transfer curve of VDMOSFET for and 2 V with (solid) and (dashed) (b) Ratio of drain current with and applied, demonstrating the on-current gain with applied (c) Ratio of drain current at different applied Vp and for .

Fig. 3(a) shows the associated p -well current, demonstrating that the large on-current gain does not require large p -well current. The ratio between on-current gain to the p -well current can be calculated to be and is shown in Fig. 3(b). Fig. 4 shows the corresponding transconductance (gm) curves. As the results show, both threshold voltage (Vth) shift and gm increase contribute to the on-current gain. When the VDMOSFET is turned off, the positive bias is removed and the off-state characteristics, including Vth, return to that with applied.

Fig. 3. (a) p -well current of VDMOSFET for with different applied Vp (b) Ratio of oncurrent gain (the difference between drain current with and ) and p -well current for .

Fig. 3. (a) p -well current of VDMOSFET for with different applied Vp (b) Ratio of oncurrent gain (the difference between drain current with and ) and p -well current for .

Fig. 4. Transconductance (gm) curves of VDMOSFET for Vd=2V with different applied Vp.

Fig. 4. Transconductance (gm) curves of VDMOSFET for Vd=2V with different applied Vp.

TCAD simulations are performed to study the underlying mechanisms of the drain on-current gain. The TCAD simulations are first calibrated to match the experimental results for the condition. When a positive bias is applied in the TCAD simulations, it similarly shows the on-current gain observed in experiments. Fig. 5 illustrates a comparison of the transfer curve from the TCAD simulations and the measurement results.

Fig. 5. Comparison of measured (solid) and TCAD simulation (dashed) results of VDMOSFET transfer curve for with different applied Vp .

Fig. 5. Comparison of measured (solid) and TCAD simulation (dashed) results of VDMOSFET transfer curve for with different applied Vp .

Fig. 6 shows the current density of the VDMOSFET with and , respectively. When a positive bias is applied, the conduction area encompasses the source junction area and no longer limited to the area of the channel region. The additional conduction paths are not limited by the channel mobility, as can be seen from the higher transconductance in Fig. 4.

Fig. 6. TCAD analysis of total current density with (a) and (b) .

Fig. 6. TCAD analysis of total current density with (a) and (b) .

The improvement in the current flow due to increased conduction area can reduce temperature rise due to current crowding. Therefore, although a higher current density is achieved with positive Vp bias, the short circuit capability is not expected to degrade. The additional current path through the source junction region may be considered as bipolar junction transistor (BJT) current. As previously reported, BJTs typically exhibit better short-circuit capability than MOSFETs. [6, 7]

Further process improvements on the conventional SiC VDMOSFET and JFET width optimization have resulted in lowering on-state resistance Rds,on to (Fig. 7). Using the p-well biasing technique described in this work, low Rds, on of can be achieved.

Fig. 7. Specific on-resistance for different JFET width and layouts.

Fig. 7. Specific on-resistance for different JFET width and layouts.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

The experimental results presented in this study highlight a significant advancement in the performance of 1200 V -rated 4H-SiC VDMOSFETs through the application of a positive bias to the p -well region. This technique led to more than a 2.5 x improvement in on-current while maintaining a low p-well current, with a remarkable ratio between on-current gain and p-well current. The TCAD simulations provided insights into the mechanisms responsible for this improvement, illustrating the expansion of the conduction area beyond the channel region when a positive bias was applied, thereby reducing the impact of channel mobility limitations. Additionally, the results showed that this technique could reduce the specific on-resistance to , a substantial improvement over conventional device. These findings underscore the potential of p-well biasing as a critical method for enhancing the performance of SiC-based power devices. Further research and process optimizations, for example in JFET width optimization and other design aspects, could unlock even greater performance gains, advancing the efficiency and capability of SiC devices in high-power applications.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.69.pdf

Uchida, K. et al., ISPSD 2015

Kim, D. et al. IEEE Journal of the Electron Devices Society 10 (2022), pp. 989-995.

Kim, J. J. et al., ISPSD 2024

Han, K. and Baliga, B. J. 2019 IEEE Transactions on Electron Devices, 66(5), 2321-2326.

Masuda, T. et al. 2020 Materials Science Forum. vol. 1004, pp. 758-763

Chen, C. et al. Microelectronics Reliability 55.9-10 (2015): 1708-1713

Sadik, D-P. et al. IEEE Transactions on Industrial Electronics 68.3 (2020): 2608-2616

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 75-83

doi: 10.4028/p-NJz1qy

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-05

Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

Chengjun Shen , Saeed Jahdi , Mana Hosseinzadehlish , Phil Mellor , Konstantinos Floros and Ingo Lüdtke

University of Bristol, Bristol, BS8 1UB, United Kingdom

Compound Semiconductor Applications Catapult, Newport, NP10 8BE, United Kingdom

chengjun.shen@bristol.ac.uk, saeed.jahdi@bristol.ac.uk, m.hosseinzadeh@bristol.ac.uk, fingo.ludtke@csa.catapult.org.uk

Keywords: Bipolar Junction Transistor, Static Performance, Vertical Devices, Temperature

Abstract

This paper compares the static properties for Silicon & SiC BJTs when connected in parallel, under various operating temperatures at various base currents and collector currents. This includes analysis of forward I-V characteristics, on-state resistance, DC gain, forward transfer characteristics and reverse leakage current to provide insights on paralleling of SiC & SiC BJTs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

For power applications with voltage requirements lower than 1700 V , SiC BJT can compete with SiC MOSFET because of the absence of gate oxide which could potentially have defects and charge traps [ 1,2 ] as well as its close static and dynamic power dissipation performance [ 3,4 ]. Challenges in fabrication of bipolar power devices are carrier lifetime in conductivity modulation and reverse recovery, bipolar degradation and avalanche ruggedness [5]. Key interests are on static and dynamic performance and electrothermal ruggedness at larger on-state currents and elevated temperatures.

Experimental Set-Up

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

This paper characterizes the static properties for two-paralleled SiC power BJTs GA04JT17-247 and compare with the similarly rated Silicon BJTs FJL6920 by means of extensive experiments. To conduct experiments, a B2902A Source/Measure Unit (SMU) is directly connected to either power Silicon or SiC BJTs through high-temperature test leads as shown in the Fig. 1. To connect in parallel, two discrete BJTs are directly connected to each other via their leads for minimal parasitic resistance and parasitic inductance. BJTs are placed in a TAS LTCL600 climatic test chamber, as also shown in Fig. 1 to adjust the operating temperature from to in steps of 25 degrees.

Fig. 1. Schematic and view of the experimental rig for static measurements of power BJTs.

Fig. 1. Schematic and view of the experimental rig for static measurements of power BJTs.

Output Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

To characterize the forward output characteristic, the Collector-Emitter current (Ice) is measured while sweeping the Collector-Emitter voltage (Vce) from 0 to 4 V in 0.04 V increments, with the fixed Base-Emitter current (Ibe) of and 30 mA used in each set of measurements between to . This setting is chosen to ensure the safe operation of both Silicon and SiC BJTs because of the low current rating of SiC BJT at high temperatures while enabling fair comparison between performance of the two devices both in single and paralleled configurations.

In terms of paralleled BJTs, the maximum was set to 1 V from the SMU since the sweeping of cannot continue at higher voltages. Fig. 2 show the output characteristics of the two-paralleled Silicon BJTs under various chamber temperatures. Under such low Collector-Emitter voltages, the increase of collector current with increasing temperature is associated with the increased stored charge in the drift region. This is because with increase of temperature additional carriers will be released intrinsically to contribute to the current conduction while the carrier lifetime also increases [6-8]. The mobility is reduced with temperature, however, the impact of the two aforementioned parameters is more pronounced in increasing the Collector-Emitter current. This in turn leads to increase of the DC gain ( ) with temperature in the Silicon BJT.

Fig. 2. Forward I-V characteristics for paralleled Silicon BJTs at IBase of 10 mA and 30 mA under different temperatures.

Fig. 2. Forward I-V characteristics for paralleled Silicon BJTs at IBase of 10 mA and 30 mA under different temperatures.

The comparison between the I-V curves of single Silicon BJT and paralleled Silicon BJTs can be found in Fig. 3. When parallel BJTs are conducting a current, the slight difference in device parameters, namely, the on-state resistance of the Base-Emitter region, can cause current mismatch where the low resistivity one carries more base current and thus more collector current. At high base currents, the base current imbalance between paralleled becomes worse. At high chamber temperatures, the higher current device is prone to higher junction temperatures and attracts more current since it is more difficult to extract heat. Both conditions produce a huge difference in collector current between two devices together with a huge difference in Collector-Emitter conduction resistance. Such current imbalance can lead to the smaller on-state resistance of paralleled Silicon BJTs than that of single BJT and thus the larger collector current as can be seen in Fig. 3.

Fig. 3. I-V characteristics for paralleled Silicon BJTs at different base currents at .

Fig. 3. I-V characteristics for paralleled Silicon BJTs at different base currents at .

For paralleled SiC BJTs as shown in Fig. 4, the decrease of collector current is also observed because of the significant incomplete ionization of acceptors at room temperature in the base region. This in turn leads to the surge of hole concentration at high temperatures and reduces the current gain. The incomplete sweep of Collector-Emitter voltage is due to the current reaches the SMU's limit.

Fig. 4. Forward I-V of parallel SiC BJTs at of 10 mA and 30 mA by temperature.

Fig. 4. Forward I-V of parallel SiC BJTs at of 10 mA and 30 mA by temperature.

Unlike the paralleled Silicon BJTs, the current gain in paralleled SiC BJTs reduces compared to its single device, as observed in Fig. 5. This is due to the fact the two devices are sharing the same base current supplied by a single base driver, and at lower base current the Collector-Emitter current drops more than expected due to reduced injection efficiency.

Fig. 5. Comparison of I-V characteristics for the single and paralleled SiC BJTs at different base currents under and .

Fig. 5. Comparison of I-V characteristics for the single and paralleled SiC BJTs at different base currents under and .

The instability problem of current gain in SiC BJT becomes worse when in parallel connection as the reduction of Emitter efficiency can occur in both SiC devices, where the difference of current gain between paralleled Silicon BJTs and paralleled SiC BJTs is about 28 at 1 V as shown in Fig. 6 while the current gain gap is approximately equal to 20.5 at 4 V . It must be noted that in the case of the paralleled device the base current is supplied by the same base driver and shared between the two paralleled devices, further reducing the base current supplied per device which as expected has led to further reduction of the DC current gain in the SiC.

Fig. 6. I-V characteristics of paralleled Silicon and SiC BJTs at of 10 mA at .

Fig. 6. I-V characteristics of paralleled Silicon and SiC BJTs at of 10 mA at .

Static DC Current Gain

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

In terms of current gain for paralleled devices as observed in Fig. 7, the current gain of paralleled Silicon BJT is slightly lower than that of single BJT under low temperatures but higher current gain under high temperatures. This is because the improvement in current gain becomes evident at high temperatures. In contrast, the paralleled SiC BJTs lead to the lower current gain.

Fig. 7. Common-Emitter current gain for Paralleled Silicon BJTs and SiC BJTs.

Fig. 7. Common-Emitter current gain for Paralleled Silicon BJTs and SiC BJTs.

On-State Resistance

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

Fig. 8 shows the on-resistance of two-paralleled Silicon BJTs under various temperatures at different collector currents. The parallel connection leads to reduction of on-resistance compared with Single Silicon BJT. A turn-around of measurements is seen in Silicon BJTs where the resistance first slightly increases with temperature between to at low base current and then drops with further increase of temperature. This is because at low base current and low temperature the impact of additional carrier generation by temperature is critical, however, as the temperature rises the role of reduced lifetime and mobility by scattering between carriers becomes more effective.

Fig. 8. On-state resistance for paralleled Silicon BJTs at ICE of 1 A & 3 A in different temperatures.

Fig. 8. On-state resistance for paralleled Silicon BJTs at ICE of 1 A & 3 A in different temperatures.

Fig. 9 shows the on-resistance of two-paralleled SiC BJTs under various temperatures at different collector currents. Parallel connection of SiC BJTs can reduce the on-resistance when compared with Single SiC BJTs. This is more pronounced in comparison with single Silicon BJT at low base current. Parallel-connected SiC BJTs introduce the stronger negative temperature dependence of onresistance, albeit it occurs only at low temperatures ranging from to .

Fig. 9. On-state resistance for paralleled SiC BJTs at Ice of 1 A and 3 A in different temperatures.

Fig. 9. On-state resistance for paralleled SiC BJTs at Ice of 1 A and 3 A in different temperatures.

The turn-around seen is similar to the Silicon BJT, where at low base current and low temperature the impact of additional carrier generation by temperature becomes more critical, though with the rise of temperature the role of reduced lifetime and mobility by scattering becomes more effective. The on-resistance of paralleled Silicon BJT is found to be smaller than that of paralleled SiC BJTs at a collector current of 1 A . The decrease of on-resistance with base current for paralleled Silicon BJTs, as shown in Fig. 10, indicates the gradual transition between the active mode and the quasi-saturation mode of operation. In general, parallel connection can promote the conductivity of both Silicon and SiC BJTs especially at elevated temperatures and at low base currents, where the on-resistance of single Silicon BJT at Ibase of 0.2 A under is reduced by when connected in parallel. In essence, the same trends seen for a single SiC BJT can be observed for the paralleled devices too, with the caveat that the base current is divided between two devices, leading to higher resistance per device and there is a slight decreasing trend with the base current.

Fig. 10. Comparison of the on-state resistance of paralleled Silicon and SiC BJTs at Ic of 3 A under and .

Fig. 10. Comparison of the on-state resistance of paralleled Silicon and SiC BJTs at Ic of 3 A under and .

Forward Transfer Characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

To characterize the forward transfer characteristic, the Collector-Emitter current (Ice) is measured while sweeping the Base-Emitter voltage ( ) from 0 to 4 V in 0.05 V increment while fixed Collector-Emitter voltage ( ) of 0.3 V is used. The temperature is increased from to and the forward characteristics are measured and plotted. Fig. 11 and Fig. 12 show the transfer characteristic measured for the Silicon BJT and SiC BJT under various chamber temperatures for paralleled devices. Both Silicon and SiC devices exhibit a lower built-in voltage at high temperatures since the intrinsic carrier concentration increases with temperature, while the temperature increase from to reduces the Base-Emitter voltage by 0.4 V in both cases of Silicon and SiC devices, though this has a more pronounced impact on the Silicon device due to its low base voltage.

Fig. 11. Forward transfer characteristics of paralleled Silicon & SiC BJTs in different temperatures.

Fig. 11. Forward transfer characteristics of paralleled Silicon & SiC BJTs in different temperatures.

Fig. 12. Transfer characteristics of Silicon vs. SiC BJTs in paralleled connection.

Fig. 12. Transfer characteristics of Silicon vs. SiC BJTs in paralleled connection.

Reverse Base-Emitter Leakage Current

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

To determine the voltage blocking capability of the Base-Emitter junction, the reverse BaseEmitter current ( ), which is also referred to as the Base-Emitter current ( ), is measured when sweeping the Base-Emitter voltage from 0 to 20 V in the negative direction. The collector terminal is open-circuited. The measurements are done between to for paralleled devices.

Fig. 13. Base-Emitter leakage current for paralleled Silicon and SiC BJTs in different temperatures.

Fig. 13. Base-Emitter leakage current for paralleled Silicon and SiC BJTs in different temperatures.

Fig. 13 and Fig. 14 show the reverse Base-Emitter current of Silicon BJT and SiC BJT under various chamber temperatures for paralleled devices. The positive temperature dependence of the breakdown voltage of Silicon BJTs can be explained by the fact that the movement of free carriers is restricted by the collision with atoms at high temperatures [9, 10], which in turn generates less electron-hole pairs and thus less leakage current, noting that in Silicon almost all dopants are ionized in room temperature.

Fig. 14. Base-Emitter leakage current of Silicon vs. SiC BJTs in paralleled connection.

Fig. 14. Base-Emitter leakage current of Silicon vs. SiC BJTs in paralleled connection.

Applications

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

In applications, current imbalance between paralleled BJTs can lead to reliability problems. Minor differences in the thermoelectrical parameters of the individual devices always exists even if they are fabricated in the same batch. The low-resistance device in parallel connection attracts more current, becomes hotter, and conducts even more current if it exhibits a PTC for current gain (or NTC for onresistance), while the cooler device conducts less [11]. Such positive feedback can result in thermal runaway until destruction. Here it is shown that the current gain of Silicon BJT has improved at high temperatures. Thanks to the parallel connection, the current gain and the conductivity of Silicon BJTs are further enhanced together with their temperature coefficient. However, SiC BJTs are favorable for long-term operation since the negative temperature coefficient counteracts the decrease of onresistance with temperature and thus suppresses the current imbalance between parallel devices.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

Parallel connection is found to promote both the conductivity and current gain for Silicon devices. This also leads to lower on-resistance in parallel SiC BJTs when compared with the single device whereas the current gain is reduced in parallel configuration. Nevertheless, SiC BJT may become preferable to be connected in parallel from the reliability point of view since the negative temperature dependence of on-resistance suppress the current imbalance and thermal runaway.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

This research article is based on the PhD dissertation/thesis by Chengjun Shen submitted to the University of Bristol in the UK, with online access link to the thesis available on: https://researchinformation.bris.ac.uk/ws/files/383491217/Final_Copy_2023_12_05_Shen_C_PhD.pdf, validated by collaboration with the Compound Semiconductor Applications Catapult (CSAC) in Newport, UK, funded as part of the EPSRC Catapult Network's 'Innovation Launchpad Network+' program with grant EP/W037009/1 and partly funded by the UK EPSRC grant EP/Y000307/1.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.75.pdf

S. Sundaresan, et al., "Static and switching characteristics of 1200 V SiC Junction Transistors with on-chip integrated Schottky rectifiers," Int. Sym. Pow. Semi. Dev., 2014, pp. 249252.

C. Shen, et al., "Impact of Carriers Injection Level on Transients of Discrete and Paralleled Silicon and 4H-SiC NPN BJTs," IEEE Open Journal of Industrial Electronics, vol. 3, pp. 6580, 2022.

R. Singh, S. Sundaresan, E. Lieser and M. Digangi, "1200 V SiC "Super" Junction Transistors operating at with extremely low energy losses for power conversion applications," IEEE Applied Power Electronics Conference (APEC), 2012, pp. 2516-2520.

S. Jahdi, et al., "The Impact of Temperature and Switching Rate on Dynamic Transients of High-Voltage Silicon and 4H-SiC NPN BJTs: A Technology Evaluation," in IEEE Transactions on Industrial Electronics, vol. 67, no. 6, pp. 4556-4566, June 2020.

E. Bashar, et al., "A Review of Short Circuit Performance in 650 V Power Devices: SiC MOSFETs, Silicon Super-junction MOSFETs, SiC Cascode JFETs, Silicon MOSFETs and Silicon IGBTs," PCIM Europe 2022, Germany, 2022, pp. 1-8.

X. Li, et al., "On the temperature coefficient of 4 h -sic bjt current gain," Solid-State Electronics, vol. 47, no. 2, pp. 233-239, 2003.

Y. Gerstenmaief, "A study on the variation of carrier lifetime with temperature in bipolar silicon devices and its influence on device operation," Int. Sym. Pow. Semi. Dev., 1994, p. 271274.

A. Udal, et al., "Investigation of charge carrier lifetime temperature dependence in 4 h -sic diodes," in Silicon Carbide and Related Materials 2006, vol. 556, no. 8, 2007, pp. 375378.

J. Baliga, "Fundamentals of Power Semiconductor Devices", Edition, Springer, 2019.

S.-L. Jang, et al., "Breakdown characteristics of emitter-base and collector-base junctions of silicon bipolar junction transistors," Solid State Electronics, vol. 35, no. 5, pp. 615-622, May 1992.

J. Hu, et al., "Comparative electrothermal analysis between sic Schottky and silicon pin diodes: Paralleling and thermal considerations," pp. 1-8, 2016.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/characteristics-of-mosfets/978-3-0364-1913-8

Key Engineering Materials, ISSN: 1662-9795, Vol. 1021, pp 85-93

doi: 10.4028/p-KEzKG7

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-14

Accepted:
2025-02-14

Online:
2025-09-05

Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

Mohamed Torky and Woongje Sung

¹College of Nanotechnology Science and Engineering, University at Albany, Albany, NY 12203, USA

mtorky@albany.edu, wsung@albany.edu

Keywords: Cost Analysis, Economic Feasibility, SiC Superjunction MOSFETs, Fabrication

Abstract

Vertical high-voltage superjunction (SJ) MOSFETs have emerged as a superior alternative compared to conventional SiC MOSFET or Si IGBT, as SJ MOSFETs present a better trade-off between specific on-resistance (Ron,sp) and breakdown voltage (BV). The fabrication of SJ devices requires precise, and multi-step processes, such as multi-epitaxial growth, trench-refill processes, and MeV implantations [3,4,5]. However, these methods increase the overall costs of SJ devices compared to their conventional counterparts, potentially undermining their benefits. This paper compares the chip costs of SJ and conventional MOSFETs at a wide range of BV and current ratings, evaluating the economic feasibility of SJ MOSFETs in . Our results highlight the potential improvements in SJ fabrication and design to enhance cost-effectiveness, particularly for medium-voltage applications ( ).

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

In medium-voltage applications (>3.3kV), SiC MOSFETs (Fig. 1(a)) and Si IGBTs (Fig. 1(b)) are the main devices used. Despite their prevalence, these MOSFETs encounter issues such as high conduction losses in SiC MOSFETs due to the dominance of drift region resistance at these voltage ratings, and significant switching losses in Si IGBTs because of their bipolar nature. To address these challenges, vertical high-voltage 4H-SiC superjunction (SJ) MOSFETs (Fig. 1(c)) offer a better solution, enhancing both conduction and switching performance by reducing drift region resistance while maintaining a unipolar conduction. SJ devices provide a superior trade-off between specific onresistance (Ron,sp) and breakdown voltage (BV) (Ron,sp ) compared to the traditional, uniformly doped vertical power devices (Ron,sp ), as illustrated in Fig. 2 [1]. However, the complex and expensive fabrication processes of SJ devices could limit their adoption over conventional devices. Therefore, estimating the costs of SJ and traditional devices is crucial to assess the advantages of superjunction devices at specific breakdown voltage and current ratings.

Fig.1. Schematic cross-section views of half unit cells of (a) conventional MOSFET, (b) IGBT and (c) SJ MOSFET.

Fig.1. Schematic cross-section views of half unit cells of (a) conventional MOSFET, (b) IGBT and (c) SJ MOSFET.

Superjunction Theory

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

The key design of SJ devices is the alternating charge-balanced P and N pillars, where these pillars introduce a lateral electric field across their sidewalls to ensure a rectangular-like electric field profile along the vertical direction [2]. The lateral electric field is responsible for terminating the charges in the pillars laterally and deplete all the charges before breakdown occurs. Once the charges in the pillars are depleted laterally, the vertical electric field starts to develop uniformly. Only the thickness of the pillars imposes the breakdown voltage capability of the device [2]. As shown in Fig. 2, decreasing the pillar width decreases the specific on-resistance offsets by enhancing the doping of the pillars to keep the pillar charge dose the same ( and lines).

Unlike conventional devices, ideally, the doping in the superjunction devices does not alter the effective critical electric field or the breakdown voltage providing that the dose is not higher than the optimal value and the charges in the pillars are balanced. Consequently, it is important to design the pillars width and doping to ensure the best trade-off between Ron,sp and BV. Based on Gauss' law, the optimal pillar charge dose used here is [2], ensuring an optimal Ron,sp without breakdown at the sidewalls of the pillars. Moreover, the drift region thickness of superjunction devices is shorter than that of conventional devices at the same breakdown voltage due to the rectangular-like electric field profile, reducing the overall resistance even further.

The fabrication of SJ devices necessitates precise processes involving multiple steps to ensure the desired charge-balanced pillars in terms of both doping and width, particularly for high voltage applications that require thicker pillars. Various techniques have been explored, including multiepitaxial growth [3], trench-refill processes [4], and a series of MeV implantations and epi-growth processes [5]. However, these methods contribute significantly to the overall cost of SJ devices, potentially outweighing their benefits compared to conventional devices with similar breakdown voltage and current ratings.

Fig.2. Ron,sp and breakdown voltage trade-off for conventional and superjunciton (SJ) devices with different SJ pillar widths.

Fig.2. Ron,sp and breakdown voltage trade-off for conventional and superjunciton (SJ) devices with different SJ pillar widths.

Devices Modeling and Economic Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

We construct our cost model referring to GE's previous study [5], leveraging their scalable devices that exhibit less performance degradation. Instead of using multi-epitaxial growth or trenchrefill processes, a epitaxial growth followed by MeV ion-implantation fabrication cycle can be employed. This reduces overall costs and mitigates process variation when compared to other methods. According to [6], only one fabrication cycle can yield a charge-balanced pillars resulting in breakdown voltage . We used a closed form set to calculate the performance parameters as a function of drift layer thickness for conventional MOSFETs developed by [7] assuming a punch through (PT) design which exhibits the best RoN,sp for a given BV compared to non-punch through (NPT) design. For SJ MOSFETs, we employed the simulation-based empirical formula developed by [8] for the blocking performance (BV). While for the conduction performance, we have used the JFET depletion approximation of the alternating pillars [9] as shown in Table 1 where is the resistivity of the pillars, is the pillar width, is the pillar vertical thickness, is the pillar width at the source side and is the pillar width at the drain side. The JFET depletion is assumed to be linear from the source to the drain where the voltage at the source is zero and the drain is 1 V . Additionally, we validate our static calculations through 2D Sentaurus TCAD simulations.

Table 1. Conventional and Superjunction MOSFETs design parameters [7,8,9]

Parameters | Conventional MOSFETs | Superjunction MOSFET
ND [cm⁻³] | 8.839×10¹⁹ BV-1.234 [7] | 10¹³/WP [9]
WD [μm] | 2.625×10⁻³ BV1.117 [7] | 2.15×10⁻³ BV1.1 * [8]
RON,SP [Ω.cm²] | 2.791×10⁻¹¹ BV2.296 [7] | WP/ρ(WPS-WPD) ln (WPS/WPD) WD [9]

Extracted and calculated from [8]

To estimate the active area for both MOSFETs, we have used Eq. (1), which is a thermal-based analysis according to the maximum power handling capability of the device [10],

where I is the current rating of the device, k is the specific thermal resistance assumed to be 0.068 , Ron,sp_300K is the specific on-resistance at room temperature, is temperature coefficient assumed to be is the maximum junction temperature and is the case temperature assumed to be 425 K and 300 K respectively. The model in Eq (1) has been plotted and matched with 1.2 kV SiC commercial MOSFETs for different current ratings [10]. The chip size is calculated by assuming a periphery of which is the ring around the edges of the active area and an edge termination (ET) width of 5 times the drift layer thickness ( ) as depicted in Eq. (2).

Since the active area is a function of RoN,sp with a square root dependence, and the edge termination width is a function of the drift region thickness, the total chip size is a function of BV as shown in Table 1. The active area is proportional to which in turn is proportional to
and for conventional and SJ MOSFETs respectively. Moreover, the edge termination width is a function of which has the same BV dependence of for both designs which means that the chip size due to the edge termination only has a dependence of . For this reason, at lower BV where the active area dominates the total chip size, the active area of conventional MOSFETs is increasing with a higher rate than that of SJ MOSFETs. However, at a relatively higher BV where the edge termination of SJ starts to dominate the chip size, the chip size of SJ MOSFETs starts to increase by instead of increasing the rate of SJ chip density as depicted in Fig. 3. In this figure, SJ-to-conv. MOSFET chip density curve has an inflection point where the rate of increase of chip density starts to decrease. The SJ design in Fig. 3 has a pillar width of assuming 10A current rating.

Fig. 3. Total chip size for conventional and superjunction MOSFET (left) and SJ-to-conventional MOSFET chip density assuming 10A current rating (right).

Fig. 3. Total chip size for conventional and superjunction MOSFET (left) and SJ-to-conventional MOSFET chip density assuming 10A current rating (right).

Based on the chip size of each MOSFET design, the price per chip is calculated using Eq. (3). For conventional MOSFETs, the substrate, epitaxial and fabrication costs are assumed to be , a and , respectively. While SJ MOSFETs incur an additional cost of and of an extra epi-growth operation and ion implantation of both P and N pillars, respectively [4]. Table 2 illustrates all the cost and design assumption for both designs.

Table 2. Cost Assumptions of Conventional and Superjunction MOSFETs

Assumptions
Conventional MOSFETs
Superjunction MOSFET

Substrate (Sub.) Cost
$1000
$1000

Epi Growth (Epi.) Cost
$50/μm
$50/μm +
$500 per additional epi-growth

Fabrication (Fab.) Cost
$1000
$1000

MeV Ion Implant
NA
$2500 per run (12μm pillar) (Variable)

Wafer Size
6-inch
6-inch

Gross Margin
0.5
0.5

Yield
0.8
0.6 (Variable)

Pillar Width
NA
5 μm [4] (Variable)

Current Rating
10A (Variable)
10A (Variable)

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

We developed multiple cost scenarios and design approaches to evaluate the economic feasibility of 4 H -SiC Superjunction (SJ) MOSFETs compared to conventional counterparts. The analysis covered three different fabrication cost scenarios (Cost #1, Cost #2, and Cost #3) and four chip design scenarios (Chip #1 to Chip #4) at varying breakdown voltage (BV) ratings, focusing on the crossover points where SJ MOSFETs become more cost-effective than conventional MOSFETs as illustrated in Table 3 and 4.

SJ Cost Scenarios: The baseline cost (Cost #1) assumes a fabrication cost of for implementing charge-balanced pillars, while Cost #2 and Cost #3 explore reduced fabrication costs of $2000 and per pillar, respectively.

SJ Chip Scenarios: The design scenarios varied pillar width and manufacturing yield. Chip #1 served as the baseline, with a pillar width and yield, while Chip #2 reduced the pillar width to . Chip #3 increased yield to , and Chip #4 combined the narrower pillar width and higher yield for optimal performance.

Table 3. Different cost scenarios for SJ MOSFETs

Scenarios
MeV Ion Implant plus Epi overgrowth
(12μm-thick Pillars) ($) [4]

SJ Cost #1
$3000 ($2500 implant + $500 epi overgrowth)

SJ Cost #2
$2000

SJ Cost #3
$1000

Table 4. Different chip design scenarios for SJ MOSFETs

Scenarios | Pillar Width, WP (μm) | Manufacturing Yield for SJ MOSFET
SJ Chip #1 | 5 | 0.6
SJ Chip #2 | 1 | 0.6
SJ Chip #3 | 5 | 0.8
SJ Chip #4 | 1 | 0.8

As shown in Fig. 4, the chip price is plotted against the breakdown voltage for all chip and cost scenarios. The BV crossover is defined as the BV point where both conventional and SJ MOSFETs prices are even. In the Chip #1 scenario, the breakdown voltage crossover occurs at approximately 8.5 kV , assuming a fabrication cost of for each SJ drift region pillar (Cost #3). For Chip #2, reducing the pillar width to (the technological limit) significantly increases the chip density of SJ MOSFETs, as the specific on-resistance decreases by compared to the width. This reduction leads to a decrease in active area, with the BV crossover point dropping to around 3.6 kV , assuming the same fabrication cost, representing a reduction in the crossover compared to Chip #1. In the Chip #3 scenario, where the yield is increased by (from 0.6 to 0.8 ), the crossover occurs at approximately 2.3 kV and 20 kV , assuming and fabrication costs, respectively. This results in a reduction in the BV crossover compared to Chip #1. For Chip #4, the crossover points are around 1.2 kV and 4.6 kV , assuming fabrication costs of and , respectively, though there is no crossover with Cost #1. Table 5 summarizes the breakdown voltage crossovers for different chip and cost scenarios, assuming a 10A current rating.

Fig. 4. Chip price and price per ampere for SJ MOSFETs with different design and cost scenarios compared to conventional MOSFETs assuming a current rating of 10A

Fig. 4. Chip price and price per ampere for SJ MOSFETs with different design and cost scenarios compared to conventional MOSFETs assuming a current rating of 10A

Table 5. BV crossover and chip price per ampere for different SJ chip design and cost scenarios at 10 A current rating.

Chip/Cost Scenarios (10A) | BV Crossover [kV] | Chip Price per Ampere [$/A]
| Cost #1 | Cost #2 | Cost #3 | Cost #1 | Cost #2 | Cost #3
SJ Chip #1 | - | - | 8.5 | - | - | 0.69
SJ Chip #2 | - | - | 3.6 | - | - | 0.15
SJ Chip #3 | - | 20 | 2.3 | - | 4.9 | 0.08
SJ Chip #4 | - | 4.6 | 1.2 | - | 0.22 | 0.05

Table 6. BV crossover and chip price per ampere for different SJ chip design and cost scenarios at 50A current rating.

Chip/Cost Scenarios (50A) | BV Crossover [kV] | Chip Price per Ampere [$/A]
| Cost #1 | Cost #2 | Cost #3 | Cost #1 | Cost #2 | Cost #3
SJ Chip #1 | - | 35 | 7.1 | - | 12.1 | 0.38
SJ Chip #2 | 34 | 9.2 | 3.5 | 11.2 | 0.64 | 0.12
SJ Chip #3 | 43 | 11 | 2.3 | 19.1 | 0.84 | 0.08
SJ Chip #4 | 9.3 | 3.9 | 1.2 | 0.65 | 0.14 | 0.05

Table 7. BV crossover and chip price per ampere for different SJ chip design and cost scenarios at 100A current rating.

Chip/Cost Scenarios (100A) | BV Crossover [kV] | Chip Price per Ampere [$/A]
| Cost #1 | Cost #2 | Cost #3 | Cost #1 | Cost #2 | Cost #3
SJ Chip #1 | - | 25 | 6.9 | - | 4.90 | 0.35
SJ Chip #2 | 20 | 8.6 | 3.4 | 3.09 | 0.52 | 0.12
SJ Chip #3 | 28 | 10 | 2.3 | 6.22 | 0.71 | 0.08
SJ Chip #4 | 8.7 | 3.9 | 1.2 | 0.54 | 0.14 | 0.05

Fig. 5. BV crossover for all chip and cost scenarios at different current ratings. No data denotes no crossover.

Fig. 5. BV crossover for all chip and cost scenarios at different current ratings. No data denotes no crossover.

At a 50A current rating as shown in Table 6, the breakdown voltage crossovers decrease across all chip scenarios at higher BV levels. This increase in SJ chip density is driven by the active area dominating the total chip size, rather than the edge termination. The dependence of the total chip size on the breakdown voltage is lower for SJ MOSFETs compared to conventional MOSFETs ( ) causing the crossover point to shift to the left, or decrease, at higher breakdown voltages. However, at lower BV values, the crossover point remains close to that of 10A, as the active area is already the dominant factor for both current ratings. While, at 100 A current as shown in Table 7, the BV crossovers decrease for Cost #1 scenario even more as the active area is relatively more dominating compared to 50A current rating. Fig. 5 sums up all the BV crossovers for different chip and cost scenarios at and 100 A ratings.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

The paper compares the economic feasibility of vertical high-voltage Superjunction (SJ) MOSFETs with conventional SiC MOSFETs, focusing on the trade-off between specific onresistance (Ron,sp) and breakdown voltage (BV). SJ devices offer superior performance, especially at higher voltages, by reducing drift region resistance and achieving a better RoN,sp at a given BV. However, their complex fabrication processes significantly raise production costs. The analysis shows that despite the improved performance of SJ MOSFETs, their higher fabrication costs often limit their economic competitiveness compared to conventional MOSFETs, particularly at lower breakdown voltages and high-current applications. To make SJ MOSFETs economically feasible, the cost per chip must decrease or their yield and chip density must improve. The study concludes that SJ MOSFETs become more cost-effective as the breakdown voltage increases, especially in highvoltage and high-current applications, depending on the specific design and fabrication scenario. In summary, while SJ MOSFETs outperform conventional MOSFETs in high-voltage applications, reducing their production costs or improving fabrication processes is essential for widespread economic feasibility.

References

The original version of this paper is available on https://www.scientific.net/KEM.1021.85.pdf

F. Udrea, G. Deboy, T. Fujihira, Superjunction Power Devices, History, Development, and Future Prospects, IEEE Trans. Electron Devices. 64 713-727 (2017)

M. Torky and T. Paul Chow, Determination of the effective critical breakdown field for Si, wide, and extreme bandgap semiconductor superjunction devices, AIP Adv. 14055306 (2024)

S. Harada et al., First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method, 2018 International Electron Devices Meeting (IEDM) 8.2.1-8.2.4 (2019)

R. Kosugi et al., Breaking the Theoretical Limit of 6.5 kV -Class 4H-SiC Super-Junction (SJ) MOSFETs by Trench-Filling Epitaxial Growth, 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) 39-42 (2019)

R. Ghandi, C. Hitchcock, S. Kennerly, M. Torky and T. P. Chow, Scalable ultrahigh voltage SiC superjunction device technologies for power electronics applications, 2022 International Electron Devices Meeting (IEDM) 9.1.1-9.1.4 (2022)

R. Ghandi, C. Hitchcock, S. Kennerly, Demonstration of 2 kV SiC Deep-Implanted SuperJunction PiN Diodes, Mat. Sci. Forum. 1062, 477-481 (2022)

S. B. Isukapati and W. Sung, An Efficient Design Approach to Optimize the Drift Layer of Unipolar Power Devices in 4H-SiC, IEEE J. Electron Devices Soc. 8 176-181 (2020)

M. Torky and T. Paul Chow, Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices, Mat. Sci. Forum. 1062 560-564 (2022)

X. Zhou, Z. Guo, and T. P. Chow, Performance limits of vertical and superjunction devices, Mat. Sci. Forum. 963 693-696 (2019)

W. Sung and B. J. Baliga, Design and Economic Considerations to Achieve the Price Parity of SiC MOSFETs with Silicon IGBTs, Mat. Sci. Forum. 858 889-893 (2016)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Keywords Index

1

1200 V SiC VDMOSFET Having On-Current Improvement

4

4 H -sic Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

B

Bipolar Degradation Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET; Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Bipolar Junction Transistor Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor; Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

Body Diode Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Bonded Substrate Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

C

Channeling Implant Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Charge Pumping Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Cost Analysis Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

D

Deep P-body Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Dmosfet Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

E

Economic Feasibility Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

Electrical Characteristics Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Electrical Characterization Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

F

Fabrication Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

Field-effect Mobility Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

G

Gate All Around Evaluation of Switching Performances and Short Circuit Capability of a

Gate Stress Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

H

High Temperature Reliability Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

High Voltage Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

I

Impact Ionization Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Interface Traps Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Iow Specific On-resistance SiC VDMOSFET Having On-Current Improvement

M

Mosfet Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

O

On-current Improvement SiC VDMOSFET Having On-Current Improvement

P

P-well Bias SiC VDMOSFET Having On-Current Improvement

Pillar Evaluation of Switching Performances and Short Circuit Capability of a

Proton Implantation Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

S

Short-circuit Evaluation of Switching Performances and Short Circuit Capability of a

SiC Evaluation of Switching Performances and Short Circuit Capability of a

SiC Superjunction Mosfets Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

Silicon Carbide SiC VDMOSFET Having On-Current Improvement

Single Step Implant Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Static And Dynamic Characteristics Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Static Performance Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

T

Tcad Evaluation of Switching Performances and Short Circuit Capability of a

Temperature Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

V

Vertical Devices Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

W

Wide Bandgap Semiconductor Evaluation of Switching Performances and Short Circuit Capability of a

Authors Index

A

Abbas, A. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Allibert, F. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Amishiro, H. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Antoniou, M. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Asenov, A. SiC VDMOSFET Having On-Current Improvement

B

Baker, G. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Bano, E. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Bell, M. SiC VDMOSFET Having On-Current Improvement

Bensouiah, D. SiC VDMOSFET Having On-Current Improvement

Bera, L. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Bevilacqua, P. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Biscarrat, J. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Biswas, A. Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Boccarossa, M. Evaluation of Switching Performances and Short Circuit Capability of a

Borghese, A. Evaluation of Switching Performances and Short Circuit Capability of a

Breglio, G. Evaluation of Switching Performances and Short Circuit Capability of a

Brosselard, P. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

C

Chand, U. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Chien, Y. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Chung, S. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Clark, D. SiC VDMOSFET Having On-Current Improvement

D

Das, S. Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

F

Floros, K. Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

Fosso-Sob, B. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Furukawa, A. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

G

Gammon, P. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Gelineau, G. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Godignon, P. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

H

Harada, S. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Higashi, Y. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Hosseinzadehlish, M. Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

I

Imai, A. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Irace, A. Evaluation of Switching Performances and Short Circuit Capability of a

Ishibashi, K. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Ishikawa, S. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

J

Jahdi, S. Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

K

Kagawa, Y. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Kato, T. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Kobayashi, M. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Kojima, K. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Kotagama, V. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

L

Laborie, L. SiC VDMOSFET Having On-Current Improvement

Laviéville, R. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Lazar, M. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Lichtenwalner, D. Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Lüdtke, I. Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

M

Maresca, L. Evaluation of Switching Performances and Short Circuit Capability of a

Mellor, P. Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

Melnyk, K. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Morel, H. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

N

Nebesnyi, V. SiC VDMOSFET Having On-Current Improvement

Niwa, H. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

O

Okamoto, M. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Oozono, K. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

P

Planson, D. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Q

Qi, Y. SiC VDMOSFET Having On-Current Improvement

R

Rathi, S. SiC VDMOSFET Having On-Current Improvement

Renz, A. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Riccio, M. Evaluation of Switching Performances and Short Circuit Capability of a

Roth, V. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Royer, C. Temperature Dependence of 1200 V -10A SiC Power Diodes: Impact of Design and Substrate on Electrical Performance

Ryu, S. Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

S

Scharnholz, S. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Sezaki, H. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Shah, V. Designs of 1.2 kV Rated Semi-Superjunction MOSFET on the 2D and 3D Planes for Practical Realization

Shen, C. Static Analysis of Temperature-Dependence of Paralleled High Voltage Vertical Silicon & SiC NPN BJTs

Shikama, N. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Singh, N. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Sonneville, C. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Stein, S. Impact of Positive and Negative High Voltage Gate Stress on Channel Degradation in SiC MOSFETs

Sugawara, K. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Sung, W. Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

T

Tanaka, T. Investigation on Effect of Electrical Characteristics of Proton Implanted 4H-SiC MOSFET

Tanaka, Y. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

Terracciano, V. Evaluation of Switching Performances and Short Circuit Capability of a

Topaloglu, I. SiC VDMOSFET Having On-Current Improvement

Torky, M. Economic Feasibility Analysis of Vertical High-Voltage 4H-SiC Superjunction MOSFETs Compared to Conventional Counterparts

U

Uchida, H. Superior Characteristics of Body Diode in DMOSFET Fabricated on 4H-SiC Bonded Substrate

V

Vergne, B. Electrical Characterization of HV (10 kV) Power 4H-SiC Bipolar Junction Transistor

Vudumula, P. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

W

Widjaja, Y. SiC VDMOSFET Having On-Current Improvement

Wirths, S. Evaluation of Switching Performances and Short Circuit Capability of a

X

Xeni, N. SiC VDMOSFET Having On-Current Improvement

Y

Yeo, A. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Yeo, Y. Impact of Single-Step Deep P-Body Implant on 1.2 kV 4H-SiC MOSFET

Young, R. SiC VDMOSFET Having On-Current Improvement