Defects and Characteristics of SiC

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Defects and Characteristics of SiC

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

All rights reserved. No part of the contents of this publication may be reproduced, processed or transmitted in any form or by any means without the written permission of the publisher.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-10

Online:
2025-09-10

Preface

The original version of this paper is available on https://www.scientific.net/SSP.376.-1.pdf

This special edition is devoted to studying and analysing the appearance of defects in silicon carbide structures and their impact on the performance and reliability of power electronics devices.

The contributions examine a wide range of structural imperfections, including prismatic dislocations, basal plane dislocations, and epitaxial defectivity, as well as the effects of lattice damage on materials and end device properties.

Other key topics, such as defect inspection techniques, their density and role in bipolar degradation, and strategies for reducing their influence, are also highlighted.

By integrating technological features of crystal and epitaxial layer growth, physics of defect occurrence processes and procedures for eliminating their effects, and device engineering, this edition provides a comprehensive overview of the current state of research and existing approaches to mitigating defect-related limitations in SiC-based technologies.

Table of Contents

Preface

Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Qian Yu Cheng, Kevin W. Kayang, Ze Yu Chen, Shan Shan Hu, Balaji Raghothamachar, Michael Dudley, Dilip Gersappe, Andrey Soukhojak, Sungchul Baek

Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Stephen A. Mancini, Seung Yup Jang, Ze Yu Chen, Balaji Raghothamachar, Michael Dudley, Woong Je Sung

Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Jimmy Thörnberg, Gennadi Polisski, Stella Giuffrida, Viviana de Luca, Alberto Catena, Marshall Wilson, Björn Magnusson

Defect Density Reduction in 4H-SiC (0001)
Epilayer via Growth-Interruption during Buffer Layer Growth

Shiv Kumar, Lakshmi Kanta Bera, Xuan Sang Nguyen, Wen Dong Song, An Min Amanda Lee, Xin Yi Li, Eng Soon Tok, Madurai Srinivasan Bharathi, Chilla Damodara Reddy, Umesh Chand, Surasit Chung, Navab Singh, Yee Chia Yeo

Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Kazuya Ishibashi, Naoki Shikama, Hiroki Niwa, Takanori Tanaka, Hiroyuki Amishiro, Akifumi Imai, Katsutoshi Sugawara, Yasuhiro Kagawa, Akihiko Furukawa

Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Jake Soto, Bruce Odekirk, Sergey Maximenko, Benjamin Rodgers, Matthew Fisher, Kevin Speer

Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

Ryo Hattori, Y. Yao, Yukari Ishikawa

High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Maëlle Le Cunff, François Rieutord, Didier Landru, Oleg Kononchuk, Nikolay Cherkashin

Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Firas Faisal, Nils Steller, Robin Karhu, Birgit Kallinger, Gennadi Polisski, Marshall Wilson, Alexandre Savtchouk, Liliana Gutierrez, Carlos Almeida, Dmitriy Marinskiy, Jacek Lagowski

How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Yasuyuki Igarashi, Kazumi Takano, Yohsuke Matsushita, Takuya Morita

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/defects-and-characteristics-of-sic/978-3-0364-1918-3

Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 1-9

doi: 10.4028/p-1KnpOd

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-02

Accepted:
2025-08-04

Online:
2025-09-10

Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

Qianyu Cheng , Kevin Kayang , Zeyu Chen , Shanshan Hu , Balaji Raghothamachar , Michael Dudley , Dilip Gersappe , Andrey Soukhojak , Sungchul Baek

Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794 U.S.A.

SK siltron css, 530011 Mile Road, Bay City, MI 48611 U.S.A.

qycheng96@hotmail.com, kevin.kayang@stonybrook.edu, zeyu.chen@stonybrook.edu, shanshan.hu@stonybrook.edu, balaji.raghothamachar@stonybrook.edu, michael.dudley@stonybrook.edu, dilip.gersappe@stonybrook.edu, andrey.soukhojak@sksiltron.com, sungchul.baek@sksiltron.com

Keywords: prismatic punched dislocation loop, inclusion, array of TED pairs, crystal growth.

Abstract

Indentation behavior induced by the presence of foreign inclusions in a PVT-grown 4HSiC wafer is investigated through synchrotron X-ray topography, which revealed the generation of dislocation arrays from the inclusion center along six directions. Grazing-incident topographs shows these dislocation arrays exhibit contrast configurations of opposite-signed TED pairs or BPD segments. This correlates with dislocation loops generated due to prismatic punching, and dislocation configuration variation is dependent on the position of prismatic loops with respect to the wafer surface. The stress induced by the inclusion embedded in the matrix is estimated from the difference in the thermomechanical properties, as the crystal is cooled from the growth temperature.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

Silicon carbide ( SiC ) is a wide bandgap semiconducting material that has gained significant attention owing to its exceptional electronic and physical properties, including high saturation velocity, high breakdown field, and excellent thermal conductivity. These attributes make SiC highly suitable for applications in power electronics, high-frequency devices, and harsh environments. As SiC is steadily replacing the traditional silicon devices in industries that require high-efficiency, highpower, and high-temperature operation, understanding and advancing SiC crystal growth with high quality is crucial for developing devices that meet the requirements of these advanced applications.

Prismatic punching can be induced through the formation and emission of dislocation loops of prismatic nature when a small particle with a strong contrast of thermomechanical properties vs. the host crystal forms an inclusion in the latter. The system behaves as an indentation punch that pushes prisms of the host crystal in the prismatic axis direction. The slip planes bounding the prism surface are displaced by the indenter with shearing stress, which can generate rings of dislocations through the Frank-Read mechanism [1-5]. Such prismatic punched dislocation loops were first discussed by Seitz in thallous halide crystals [1] and observed by Jones and Mitchell in silver chloride crystals [2] as well as in multiphase materials mainly with cubic structures [6-9]. Similar observations have also been reported in hexagonal crystals, such as ice [10]. An observation of the prismatic punching behavior has, however not yet been reported in published literature for hexagonal SiC.

In this study, many foreign inclusions are observed in a physical vapor transport (PVT)-grown off-axis wafer, generating arrays of dislocations that present similar configurations as prismatic punched dislocation loops. A better understanding of the mechanisms of prismatic punching in crystal through identification and characterization of the above dislocation arrays is the purpose of the reported work.

Experiment

The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

Synchrotron X-ray topography (XRT) experiments were conducted on a PVT-grown off-axis 6-inch 4H-SiC wafer. Transmission geometry topograph was recorded using synchrotron white beam X-ray in reflection, Si-face as the beam exit surface. For grazing-incidence geometry using synchrotron monochromatic beam, reflection topographs were recorded from the Si -face of the specimen at an energy of 8.99 keV , achieving an effective X-ray penetration depth range of 6-17 for BPDs [11]. reflection topographs were recorded from the Si-face of the specimen at an energy of 18 keV for reaching a deeper effective X-ray penetration depth, which is approximately for a screw type BPD. X-ray topography images were recorded on Agfa Structurix D3-SC films with approximately one resolution. The experiments were carried out at Beamline 1-BM of the Advanced Photon Source (APS) in Argonne National Laboratory (ANL).

The dislocation nature of defects observed topographically was confirmed by ray tracing simulations [12, 13]. The principle of ray tracing simulation is based on the orientation contrast mechanism [14], where the direction of local diffracted X-ray beams is calculated through the displacement field associated with the defect. The diffracted X-rays are then projected onto the recording plate. The distortion aroused by the presence of a dislocation within the crystal is revealed as dark or white contrast difference due to the superimposition or separation of diffracted X-rays resulting from the inhomogeneous intensity distributions. Ray tracing simulation presented in this study incorporated the effect of surface relaxation and photoelectric absorption for more precise contrast simulation [15-17].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

Hexagonal-shaped foreign inclusion features (Fig. 1a, 1e) are observed optically over the inner region of the wafer. Such inclusions are characterized by synchrotron X-ray topography. While transmission geometry topography reveals information about defects contained in the whole sample volume by having X-ray beams incident onto one surface and exit from the other, grazing-incident topography uses reflection geometry that focuses on revealing defect configurations from the wafer surface down to the effective X-ray penetration depth exclusively [11, 18]. reflection synchrotron white beam topograph recorded in transmission geometry revealed large dark strain contrast associated with each foreign inclusion feature observed optically (Fig. 1b). Whereas both and reflection synchrotron monochromatic beam topograph recorded in grazingincidence geometry shows only part of the inclusions have correlated contrast (indicated by blue arrows in Fig. 1c, 1d). Such observations suggest foreign inclusions are located at different depths within crystal thickness. Enlarged grazing-incidence topograph indicates inclusions present white or dark contrast with frequent observation of associated dislocation arrays (Fig. 1f). This variation in inclusion contrast configuration is analyzed by ray tracing simulation. Simulated contrasts of an inclusion positioned at different depths below the crystal surface were calculated by applying equations describing the displacement field of a spherical inclusion [19]:

where is the distance from the center of the inclusion to the medium, is the size of the inclusion, and relates to the atomic volume difference between the inclusion and the lattice. Simulation results reveal a gradual change from the strong white dotted center surrounded by a dark ring to a dark dominated contrast as the inclusion embeds deeper into the crystal (Fig. 2).

Fig. 1. Foreign inclusion features observed at the same region on a wafer through (a) optical microscopy; (b) transmission geometry X-ray topography; (c) grazing-incidence geometry X-ray topography; (d) grazing-incidence geometry X-ray topography. (e) Enlarged optical image of an inclusion feature. (f) Enlarged X-ray topograph showing the dark (Arrow 1) and white (Arrow 2) contrast of inclusions and the expansion of dislocation arrays from the inclusion center.

Fig. 1. Foreign inclusion features observed at the same region on a wafer through (a) optical microscopy; (b) transmission geometry X-ray topography; (c) grazing-incidence geometry X-ray topography; (d) grazing-incidence geometry X-ray topography. (e) Enlarged optical image of an inclusion feature. (f) Enlarged X-ray topograph showing the dark (Arrow 1) and white (Arrow 2) contrast of inclusions and the expansion of dislocation arrays from the inclusion center.

Fig. 2. Ray tracing simulation results of reflection synchrotron monochromatic beam grazingincidence topographic contrast of an inclusion located at the crystal surface and embedded at different depths below the surface. The location of the inclusion center with respect to the crystal is shown in the inset schematic diagram.

Fig. 2. Ray tracing simulation results of reflection synchrotron monochromatic beam grazingincidence topographic contrast of an inclusion located at the crystal surface and embedded at different depths below the surface. The location of the inclusion center with respect to the crystal is shown in the inset schematic diagram.

The prismatic punched dislocation loop is a well-known example of the nucleation of dislocations at stress concentrations. As shown in Fig. 3a, the indentation behavior of a foreign inclusion in 4H-SiC induces large shear stress, which activates prismatic punching and generates dislocation loops along six directions. Each loop consists of two basal plane dislocation (BPD) segments lying on the basal plane and two threading edge dislocation (TED) segments along the growth axis. The Burgers vector of the dislocation is along and is perpendicular to the prismatic loop. When a wafer is sliced from the boule, prismatic loops can be contained at varying depths within the wafer. As XRT is recorded on a wafer with reflection geometry, only volume from the sample surface to the X-ray effective penetration depth is imaged. This may contain only part of the prismatic punched dislocation loops within the imaged volume (Fig. 3b-d). Consequently, each set of prismatic punched dislocation loops aligned in the same direction may appear as arrays of TED pairs or BPDs on the topograph, depending on the intersection position of the dislocation loops relative to the wafer surface.

If the wafer is sliced across the middle of the prismatic loops (Fig. 3b), only a section of the threading segments along the growth axis is contained within the reflection XRT imaged volume, and prismatic loops will appear as pairs of opposite-signed TEDs (Fig. 4a). This is observed on grazingincident topographs in both and , 16 reflections with different penetration depths as the example shown in Fig. 4b and Fig. 4c, where small paired dotted contrasts with symmetric or asymmetric configuration are generating from the inclusion center. Ray tracing simulation is conducted to simulate the contrasts of opposite-signed TED pairs along six directions. Results indicate a symmetric configuration of opposite-signed TED arrays along horizontal directions (Fig. 4f, 4g) as both TEDs in the pair are with the same size and white contrast, whereas the inclined opposite-signed TED arrays in (fig. 4d, 4e) and (Fig. 4h, 4i) present asymmetric contrast with one larger white contrast TED and one smaller dark contrast TED in a pair. Such contrast configurations correlate well with actual topographic observations, thus verifying the composition of dislocation arrays associated with the inclusion.

If the wafer is sliced in a location where the reflection XRT imaged volume contains only the upper section of prismatic punched dislocation loops (Fig. 3c), dislocation segments along the basal plane as well as a short segment of threading-oriented dislocation on each side can be imaged (Fig. 5a). This corresponds to grazing-incidence topographic observation of BPD arrays generating from an inclusion if the effective X-ray penetration depth can only reach the dislocation segment on the basal plane (Fig. 5b). With a reflection that can focus deeper into the depth, two TEDs connecting a BPD in the arrays might be observable (Fig. 5c).

Finally, for wafer slicing position that intersects the lower portion of prismatic punched dislocation loops (Fig. 3d), grazing-incidence XRT can reveal prismatic loops as arrays of opposite-signed TED pairs, the visibility of BPD segment connecting two TEDs in a pair is determined by the effective X-ray penetration depth (Fig. 6a). As Fig. 6b shows, reflection XRT captured the generation of dotted contrast arrays from an inclusion, which corresponds to the configuration of opposite-signed TEDs as previously discussed. However, reflection XRT of the same region is recorded with a deeper penetration depth, which clearly reveals this array presents linear contrast corresponding to a BPD connecting two TEDs in a pair (Fig. 6c).

Fig. 3. Schematic diagrams showing (a) prismatic punched dislocation loops generating from an inclusion in along six directions, each loop consists of two BPD segments lying on the basal plane and two TED segments along the growth axis; (b-d) the intersecting position of one set of prismatic loops and the imaged volume of a reflection geometry X-ray topograph corresponding to the wafer surface position down the effective X-ray penetration depth at (b) across the middle of dislocation loops; (c) across the upper part of dislocation loops; (d) across the lower section of dislocation loops.

Fig. 3. Schematic diagrams showing (a) prismatic punched dislocation loops generating from an inclusion in along six directions, each loop consists of two BPD segments lying on the basal plane and two TED segments along the growth axis; (b-d) the intersecting position of one set of prismatic loops and the imaged volume of a reflection geometry X-ray topograph corresponding to the wafer surface position down the effective X-ray penetration depth at (b) across the middle of dislocation loops; (c) across the upper part of dislocation loops; (d) across the lower section of dislocation loops.

Fig. 4. (a) Schematic diagram showing a set of prismatic punched dislocation loops with their two threading segments along the -axis contained in the reflection XRT imaged volume. Grazingincidence synchrotron XRT presents corresponding contrasts of arrays of opposite-signed TED pairs in both (b) , and (c) reflections. Such dislocation configurations are verified by (d-i) ray tracing simulated contrasts of opposite-signed TED pairs along six directions.

Fig. 4. (a) Schematic diagram showing a set of prismatic punched dislocation loops with their two threading segments along the -axis contained in the reflection XRT imaged volume. Grazingincidence synchrotron XRT presents corresponding contrasts of arrays of opposite-signed TED pairs in both (b) , and (c) reflections. Such dislocation configurations are verified by (d-i) ray tracing simulated contrasts of opposite-signed TED pairs along six directions.

Fig. 5. (a) Schematic diagram showing a set of prismatic punched dislocation loops with their dislocation segment lying on the basal plane and two threading segments attached on each end contained in the reflection XRT imaged volume. Grazing-incidence synchrotron XRT presents corresponding contrasts of arrays of (a) BPDs in reflection with shallower effective X-ray penetration depth; (c) opposite-signed TED pairs in , 16 reflection with deeper penetration depth.

Fig. 5. (a) Schematic diagram showing a set of prismatic punched dislocation loops with their dislocation segment lying on the basal plane and two threading segments attached on each end contained in the reflection XRT imaged volume. Grazing-incidence synchrotron XRT presents corresponding contrasts of arrays of (a) BPDs in reflection with shallower effective X-ray penetration depth; (c) opposite-signed TED pairs in , 16 reflection with deeper penetration depth.

Fig. 6. (a) Schematic diagram showing a set of prismatic punched dislocation loops with their two short threading segments and the basal plane dislocation segment connecting in between contained in the reflection XRT imaged volume. Grazing-incidence synchrotron XRT presents corresponding contrasts of arrays of (a) TED pairs in reflection with shallower effective X-ray penetration depth; (c) TED pairs connected by BPDs in reflection with deeper penetration depth.

Fig. 6. (a) Schematic diagram showing a set of prismatic punched dislocation loops with their two short threading segments and the basal plane dislocation segment connecting in between contained in the reflection XRT imaged volume. Grazing-incidence synchrotron XRT presents corresponding contrasts of arrays of (a) TED pairs in reflection with shallower effective X-ray penetration depth; (c) TED pairs connected by BPDs in reflection with deeper penetration depth.

Since dislocation arrays expanding from an inclusion center present a similar contrast configuration as prismatic punched dislocation loops [2], stress induced by the presence of foreign inclusions within bulk crystal is estimated to evaluate the possibility of prismatic loop generation. The difference in thermomechanical properties between the foreign inclusion material and the host crystal can result in shear stress arising as the crystal is cooled from the growth temperature, which can reach approximately during bulk SiC growth in the PVT method [20]. The brittle-to-ductile transition temperature of SiC is roughly [21], below which the material undergoes cleavage fracture with no plastic deformation. Within this temperature range, , the thermal expansion coefficients of the foreign inclusion material [22] and along -axis [23] are and , respectively. Assuming the inclusion is infinitely stiff, the effective thermal misfit strain in the matrix due to the difference between the coefficients of thermal expansion of these two materials can be calculated as [24]:

Finally, the magnitude of shear stress induced by the presence of this foreign inclusion can be estimated according to the following equation [25]:

where is the shear modulus of . Literature indicates the shear modulus of at 1800 K within the range between the brittle-to-ductile to the maximum growth temperature is 175.2 GPa [26], which yields a corresponding shear stress of 0.965 GPa due to the presence of a foreign inclusion. Since dislocation nucleation at appreciable rates occurs only for stresses approaching the theoretical
strength of perfect crystals [27], and the high-temperature strength of SiC at a comparable temperature level of 1773 K is 0.5 GPa [28], the estimated shear stress induced by this inclusion is then found sufficient for the generation of dislocations.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

Prismatic punched dislocation loops are observed to be associated with inclusions on a PVT-grown 4H-SiC substrate wafer. Synchrotron X-ray topography in transmission geometry reveals inclusions are located at different depths within the crystal. The corresponding prismatic punched dislocation loops present contrast as arrays of opposite-signed TED pairs or BPDs along the directions on grazing-incidence synchrotron XRT. This contrast configuration variation depends on the intersecting position of prismatic loops and reflection XRT imaged volume corresponding to the wafer surface. Ray tracing simulation is conducted on contrasts of inclusion located at a depth of 0 from the crystal surface, as well as on arrays of opposite-signed TED pairs. Such simulated contrasts present an excellent correlation with actual topographic observations, which further confirmed the generation of prismatic punched dislocation loops from foreign inclusions in . Such prismatic loops are generated due to the indentation behavior of foreign inclusions that have a strong contrast of thermomechanical properties compared to SiC crystal, which induces large shear stress estimated at 0.965 GPa .

Acknowledgment

The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

Work supported by and samples provided by SK siltron css. The research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. DOE Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC0206CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence at the Advanced Photon Source.

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The original version of this paper is available on https://www.scientific.net/SSP.376.1.pdf

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The original version of this eBook is available on https://www.scientific.net/book/defects-and-characteristics-of-sic/978-3-0364-1918-3

Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 11-18

doi: 10.4028/p-BhoG5Q

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-05-23

Accepted:
2025-05-28

Online:
2025-09-10

Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

The original version of this paper is available on https://www.scientific.net/SSP.376.11.pdf

Stephen A. Mancini , Seung Yup Jang , Zeyu Chen , Balaji Raghothamachar , Michael Dudley , and Woongje Sung

¹College of Nanotechnology Science and Engineering, University at Albany, Albany NY, 12203, USA

Department of Material Science and Chemical Engineering, Stony Brook University, Stony Brook NY, 11794, USA

smancini@albany.edu, sjang3@albany.edu, zeyu.chen@stonybrook.edu, Balaji.raghothamachar@stonybrook.edu, Michael.dudley@stonybrook.edu, wsung@albany.edu

Keywords: 4H-Silicon Carbide (SiC), MOSFET, JBSFET, Design Approach, Basal Plane Dislocations (BPDs), Room Temperature Ion Implantation, Current Stress, X-Ray Topography

Abstract

Several devices of various cell architectures have been successfully fabricated by employing different implantation conditions, resulting in varying levels of Basal Plane Dislocation (BPD) densities across the different device designs. It was found that by utilizing devices designed with an orthogonal source layout as opposed to the traditional stripe pattern, the long-term reliability under sustained 3rd Quadrant current stress conduction can be greatly improved even in devices with medium BPD densities. In addition, the use of the unipolar current of the JBSFET can further enhance long-term reliability under sustained Quadrant current stress by mitigating stacking fault expansion, even in devices with a high BPD density.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.11.pdf

The wide bandgap of offers significant advantages over Silicon as a material of choice for high voltage power devices. This large bandgap, along with the ability to withstand high electric fields, allows for the creation of a thin and heavily doped epitaxial drift layer, resulting in a device with lower resistance when compared with silicon-based devices at voltage ratings greater than or equal to 600 V [1]. Although the material properties of 4 H -SiC are preferred for power device applications, the material itself provides unique challenges not encountered in silicon processing. For silicon processing, ion implantation can be performed at room temperature [2] however, for processing, the ion implantation process has been performed at elevated temperatures to mitigate the generation of Basal Plane Dislocation (BPDs) which can lead to device degradation under bipolar current stress [3]. This high temperature ion implantation requires the use of an oxide blocking layer rather than the use of the photoresist layer, adding further processing steps and increasing the overall processing complexity, cost, and time [4].

Studies have been conducted to develop methods that mitigate lattice damage, such as BPDs, from ion implantation damage while simultaneously performing the process at room temperature. It was found that by carefully controlling the implantation profile through a combination of energy and dose adjustments, BPD generation can be suppressed even at doses approximately 10 times greater than the previously reported critical dose of for Al ions at room temperature implantation [5,6]. Although the implantation profile is a vital component to consider in the mitigation of BPD formations, the proper architecture of the device active area is another essential consideration. By properly optimizing the active area cell architecture, potential BPD generation from the ion bombardment during RT implantation can be mitigated and thus stacking fault expansion can be suppressed. In this study, two MOSFETs with different cell layouts and a JBS-Diode integrated MOSFETs (JBSFETs) were examined under various aluminum ion implantation profiles to investigate the impact of cell architecture on BPD generation and subsequent ruggedness under continuous body diode current stress.

Device Design and Process Conditions

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Fig 1. displays the top view of the various device types utilized in this study. The P+ stripe MOSFET adopts a conventional vertical power MOSFET architecture, where the source regions consist of long uninterrupted implanted area in the y -direction to establish a contact to the P -Well. However, this approach leads to an excessively large cell pitch when compared to other design approaches. In the case of the Orthogonal P+ MOSFET cell structure, the overall cell pitch was reduced when compared to the traditional stripe architecture by isolating the implanted regions and placing them periodically in the orthogonal direction. This reduces the overall cell pitch, thus the overall specific on resistance ( ) is improved. For the JBSFETs, the Schottky openings also employ an orthogonal pattern as opposed to the traditional stripe type layouts. In this design, the dimensions of the ohmic area in between the Schottky contact areas measures , enabling greater conduction in the quadrant of operation without adversely affecting forward device characteristics of the JBSFET [7]. The optimal Schottky width to ensure sufficient current density while minimizing the leakage current was determined to be , which was integrated into the JBSFET structure. The current rating and size of the Stripe MOSFETs were 6 A and , respectively, and for the Orthogonal P+ MOSFET and JBSFET the current rating and size were 30 A and , respectively. In addition, the Stripe MOSFET utilized a floating field ring (FFR) edge termination whereas both the Orthogonal P+ MOSFET and JBSFET utilized a hybrid JTE edge termination [8]. A summary of the device parameters can be observed in Table 1.

Fig. 1. Top layout views of the Stripe MOSFET, Orthogonal MOSFET and the Spacing JBSFET employed within this study. Boundaries of the implanted areas are highlighted in yellow for each device active area cell.

Fig. 1. Top layout views of the Stripe MOSFET, Orthogonal MOSFET and the Spacing JBSFET employed within this study. Boundaries of the implanted areas are highlighted in yellow for each device active area cell.

Table 1. Parameter summary of the devices utilized within this study.

Device Type
Active Area
[mm²]
Current Rating
[A]
Cell Pitch
[ μm]
Schottky
Open [μm]
Edge
Termination

P+ Stripe
0.85
6
9.2
N/A
FFR

Ortho P+
4.5
30
5.4
N/A
Hybrid

JBSFET
4.5
30
8.4
2
Hybrid

For each device type, several different source implantation profiles were utilized, as shown in Fig. 2. The three different implantation profiles were designed to create devices with low, medium, and high BPD-generation throughout the device structure, allowing for the assessment of BPD effects on each device cell architecture. This was achieved by varying the doping concentrations (either medium (M) or high (H)) for both the surface (S) and the body (B) of the junction [5,6]. The low BPD-generating 'HSMB' profile has a total aluminum dose of (referred to as 9 x ), while the medium BPD-generating 'MSHB' profile had a total aluminum dose of (referred
to as 5 x ). Lastly the high BPD generating profile has a near uniform surface and body concentration with a total dose of and thus can be simplified to the ' 5 x RT Box' profile. All profiles were implanted at room temperature (RT); however, the medium damage 'MSHB' profile was also implanted at an elevated temperature of (HT) for comparison purposes. The remaining implantations steps (i.e. JFET, PWell, N+ and JTE) used all implanted at room temperature.

Fig. 2. Simulated aluminum concentration profiles utilized to form the implanted regions within the devices by varying the surface and body of the main junction. All profiles were implanted at room temperature; however, the 'MSHB' profiles were also implanted at an elevated temperature for comparison purposes.

Fig. 2. Simulated aluminum concentration profiles utilized to form the implanted regions within the devices by varying the surface and body of the main junction. All profiles were implanted at room temperature; however, the 'MSHB' profiles were also implanted at an elevated temperature for comparison purposes.

Results and Discussion

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The representative X-Ray topography maps, along with their corresponding BPD densities can be observed in Fig. 3 and Table 2 respectively. For the low and medium damage implantations, BPDs can be observed forming around both edge terminations and periphery regions in all three device architectures whereas negligible BPD generation is observed in the devices fabricated with the 5 xHT profile. Since all BPD generation can be observed along areas subjected to the P+ implantation, this defect generation was process related as opposed to being native to the wafer. For the low damage implantation, the estimated BPD density was and for the hybrid JTE and FFR edge terminations, respectively. For the medium damage implantation estimated BPD density was and for the hybrid JTE and FFR edge terminations respectively. In both implantation conditions, the FFR edge termination generated a greater amount of BPDs and no BPDs were observed originating within the active area [9]. For the high damage implantation, BPD generation can be observed around the edge terminations, and periphery regions, for the nominal MOSFETs and JBSFETs with a BPD density of approximately . However, for the P+ stripe MOSFET fabricated under the high damage implantation condition, BPD generation was observed throughout the entirety of the device, including the active area due to the greater amount of mismatch lattice stress between the PWell and P+ regions [10]. The BPD density for both the active area and FFR edge termination of the P+ Stripe MOSFET was too large and therefore, an exact density could not be determined.

Fig. 3. Representative X -Ray topography images of the stripe MOSFET, Nominal MOSFET, and Nominal JBSFET are presented under each of the no, low, medium, and high damage implantation conditions. BPD generation can primarily be observed within the edge termination, and periphery regions of the devices.

Fig. 3. Representative X -Ray topography images of the stripe MOSFET, Nominal MOSFET, and Nominal JBSFET are presented under each of the no, low, medium, and high damage implantation conditions. BPD generation can primarily be observed within the edge termination, and periphery regions of the devices.

Table 2. BPD density calculations of the active device and edge termination areas for each device fabricated utilizing the various implantation conditions.

Device
Area
Device
Design
BPD Densities for each Implantation Condition [cm⁻²]
MSHB 5x HT
HSMB 9xRT
MSHB 5xRT
5xRT Box

Active Area
P+ Stripe
~0
~0
~0
>10⁵

Ortho P+
~0
~0
~0
~0

JBSFET
~0
~0
~0
~0

Periphery and
Edge Termination
FFR
~0
0.5×10⁴
2.1×10⁴
>10⁵

Hybrid*
~0
0.2×10⁴
0.5×10⁴
2.5×10⁴

The static measurements and continuous body diode stress conditions used are depicted in Fig. 4. Initially, the devices underwent screening for their forward IV, forward blocking and Quadrant output characteristics. This was followed by a continuous 15 -minute body diode current stress at . To minimize the Quadrant channel current, a bias of -5 V was applied to the gate, effectively shutting off the channel and allowing the current to flow solely through the body diode of the device. This process was repeated until the device was stressed for a total of 90 minutes. The wafer temperatures were monitored to keep the devices at approximately for the entire duration of the body diode current stress cycle. This procedure was performed for each device type and implantation condition.

Fig. 4. Simplified schematic highlighting the measurement performed for each device analyzed within this study. Each sense condition consisted of a forward IV, forward blocking, and quadrant output measurement followed by a current for 15 minutes. This was then repeated until each device had been stressed for a total of 90 minutes.

Fig. 4. Simplified schematic highlighting the measurement performed for each device analyzed within this study. Each sense condition consisted of a forward IV, forward blocking, and quadrant output measurement followed by a current for 15 minutes. This was then repeated until each device had been stressed for a total of 90 minutes.

Forward Conduction Pre/Post Current Stress

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Fig. 5. Forward conduction characteristics of the stripe MOSFET, Orthogonal MOSFET, and JBSFET fabricated with different P+ profiles, before (Solid) and after (Dashed) the current stress analysis. Measurements were performed on wafer and at a gate bias of .

Fig. 5. Forward conduction characteristics of the stripe MOSFET, Orthogonal MOSFET, and JBSFET fabricated with different P+ profiles, before (Solid) and after (Dashed) the current stress analysis. Measurements were performed on wafer and at a gate bias of .

Fig. 5 shows forward conduction output characteristics both pre and post current stress for the various device types, respectively. Notably, even before current stress the 9xRT devices exhibited output characteristics similar to the 5xHT implanted devices, whereas non-linear pinching behaviors were observed within the 5 xRT and 5 xRT Box implanted devices [6]. However, after the current stress analysis, significant device degradation is evident in the 5x RT Box P+ Stripe MOSFET, 5x RT Box Orthogonal P+ MOSFET, and 5x RT P+ Stripe MOSFET. The on-resistance for the 5x RT Box P+ Stripe MOSFET, 5x RT Box Orthogonal P+ MOSFET, and 5x RT P+ Stripe MOSFET increased by , and respectively. In contrast, no discernible differences are observed in the remaining devices, likely due to their low BPD density within the active area or by leveraging the unipolar current within the JBSFET devices.

The forward blocking characteristics of the devices, both before and after the current stress measurements, are observed in Fig. 6. Leakage current and forward blocking behaviors remained relatively constant throughout all devices both before and after the current stress. However, it is noteworthy that the leakage current was significantly higher in the RT implanted P+ Stripe MOSFETs
before stress due to the use of the FFR edge termination [9]. This higher leakage current was also observed within the orthogonal P+ 5xRT device [6], and within the RT implanted JBSFETs due to integrated JBS diode [5]. Additionally, the 5x RT Box profile showed no blocking capabilities with all 3 device types even prior to the current stress. As a result, the combination of these already high leakage currents or no blocking capabilities led to minimal observable differences, unlike what was seen within the forward conduction.

Forward Blocking Pre/Post Current Stress

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Fig. 6. Forward blocking characteristics of the stripe MOSFET, Orthogonal MOSFET, and JBSFET fabricated with different P+ profiles, before (Solid) and after (Dashed) the current stress analysis. Measurements were performed on-wafer and at a gate bias of to minimize leakage through the channel.

Fig. 6. Forward blocking characteristics of the stripe MOSFET, Orthogonal MOSFET, and JBSFET fabricated with different P+ profiles, before (Solid) and after (Dashed) the current stress analysis. Measurements were performed on-wafer and at a gate bias of to minimize leakage through the channel.

Fig. 7 shows the quadrant output characteristics, both before and after the current stress for the various devices analyzed. Similar to the forward conduction results, device degradation is evident only with the output of the 5x RT Box P+ Stripe MOSFET, 5x RT Box Orthogonal P+ MOSFET, and 5x RT P+ Stripe MOSFET, following the current stress. The quadrant forward voltage drop ( ) increased by , , and for the 5 x RT Box P+ Stripe MOSFET, 5 x RT Box Orthogonal P+ MOSFET, and 5x RT P+ Stripe MOSFET respectively. Additionally, negligible changes were observed in the output characteristics of the remaining structures, due to their low BPD densities within the active area or the use of unipolar current as seen in the JBFET devices. Although no degradation is observed within the JBSFETs, the output of the integrated JBS diode was still hindered prior to the current stress due to the high presence of BPDs within the 5xRT and 5xRT Box implanted devices when compared to the 9xRT and 5xHT devices[5].

Quadrant Output Pre/Post Current Stress

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Fig. 7. 3rd Quadrant output characteristics of the stripe MOSFET, Orthogonal , and JBSFET fabricated with different P+ profiles, before (Solid) and after (Dashed) the current stress analysis.

Fig. 7. 3rd Quadrant output characteristics of the stripe MOSFET, Orthogonal , and JBSFET fabricated with different P+ profiles, before (Solid) and after (Dashed) the current stress analysis.

Table 3. shows the overall degradation of the various device architectures, for the forward IV and quadrant output respectively. All devices fabricated under the negligible and low damage implantation condition exhibited no observable degradation in the forward IV, forward BV, and quadrant output characteristics. Under the medium damage implantation, despite the presence of BPDs, the orthogonal P+ structure of the nominal MOSFET showed resilience to device degradation, and to a lesser extent in the high damage scenario, when compared to the traditional stripe MOSFET under the same fabrication condition. However, the JBSFETs showed no degradation even under the high BPD density implantation condition as the unipolar nature of the JBSFETs prevents the electron hole recombination utilizing BPDs and thus prevent device degradation through SF expansion.

Table 3. Percentage change in both and Quadrant for the various device architectures and implantation conditions after the current stress analysis.

Device
Type
Increase in Ron
Increase in 3rd Q Vf

5×HT
9×RT
5×RT
5×RT Box
5×HT
9×RT
5×RT
5×RT Box

P+ Stripe
~0%
~0%
16.5%
102%
~0%
~0%
2.5%
14.6%

Ortho P+
~0%
~0%
~0%
37.8%
~0%
~0%
~0%
8.6%

JBSFET
~0%
~0%
~0%
~0%
~0%
~0%
~0%
~0%

Summary

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Several device architectures have been successfully fabricated under various implantation conditions, resulting in a wide range of BPD densities within the devices. Even under high BPDgenerating implantations, the device and cell layout can be optimized to reduce the effects of device degradation. By utilizing the orthogonal source pattern, the BPD density within the active area can be suppressed, improving long-term reliability compared to the stripe MOSFET counterpart. However, by switching to a unipolar device, such as the JBSFET, device degradation can be heavily suppressed even in high BPD density devices, resulting in improved long-term reliability. While the implantation profile has proven to be a critical factor, careful consideration for the cell architecture was shown to be another vital factor in suppressing BPD generation and subsequent SF expansion. Therefore, proper control over both aspects is essential for fully implementing room temperature implantation, increasing device reliability and longevity, while simultaneously reducing processing complexity, cost, and time.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/SSP.376.11.pdf

This work was supported by the National Renewable Energy Laboratory ("NREL"), U.S. Department of Energy, the Advanced Manufacturing Office, DE-AC36-08GO28308. This research used resources of the Advanced Photon Source, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.11.pdf

B Jayant Baliga, Fundamentals of power semiconductor devices. New York, NY: Springer, 2008, Chap.3, pp. 91-155.

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A. Agarwal, H. Fatima, S.Haney, S.-H. Ryu, "A New Degradation Mechanism in High-Voltage SiC Power Mosfets". IEEE Electron Device Letters vol. 28, no. 7, pp.587-589, 2007. doi.: 10.1109/LED.2007.897861.

D. Kim, N. Yun and W. Sung, "Advancing Static Performance and Ruggedness of 600 V SiC MOSFETs: Experimental Analysis and Simulation Study," 2021 IEEE International Reliability Physics Symposium (IRPS), 2021, 10.1109/IRPS46558.2021.9405109.

S. A. Mancini et al., "Static Performance and Reliability of Diodes with Regions Formed by Various Profiles and Temperatures," 2022 IEEE International Reliability Physics Symposium (IRPS), 2022, pp. P62-1-P62-6, doi: 10.1109/IRPS48227.2022.9764538.

S. A. Mancini et al., "Investigation of Static Performances of 1.2 kV 4H-SiC MOSFETs Fabricated Using All 'Room Temperature' Ion Implantations," in IEEE Journal of the Electron Devices Society, vol. 12, pp. 150-158, 2024, doi: 10.1109/JEDS.2024.3359974.

S. A. Mancini et al., "Increased 3rd Quadrant Current Handling Capability of 1.2 kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances," 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2021, pp. 101-106, doi: 10.1109/WiPDA49284.2021.9645152.

W. Sung and B. J. Baliga, "A Near Ideal Edge Termination Technique for Devices: The Hybrid Junction Termination Extension," IEEE Electron Device Letters, vol. 37, no. 12, pp. 1609-1612, Dec. 2016, doi: 10.1109/led.2016.2623423.

S. A. Mancini et al., "Edge Termination Design Considerations for 1.2 kV 4H-SiC MOSFETs While Utilizing Room Temperature Ion Implantations," 2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), Charlotte, NC, USA, 2023, pp. 1-6, doi: 10.1109/WiPDA58524.2023.10382208.

Z. Chen et al, "Analysis of Basal Plane Dislocation Motion Induced by P+ Ion Implantation Using Synchrotron X-ray Topography" 2022 19th International Conference on Silicon Carbide and Related Materials (ICSCRM), September 2022, doi: 10.4028/p-4mo61y.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

*Hybrid BPD density was taken from the Nominal MOSFET structures.

The original version of this eBook is available on https://www.scientific.net/book/defects-and-characteristics-of-sic/978-3-0364-1918-3

Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 19-26

doi: 10.4028/p-jHPS8Y

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-13

Revised:
2025-05-26

Accepted:
2025-05-28

Online:
2025-09-10

Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

The original version of this paper is available on https://www.scientific.net/SSP.376.19.pdf

Jimmy Thörnberg , Gennadi Polisski , Stella Giuffrida , Viviana De Luca , Alberto Catena , Marshall Wilson , Björn Magnusson

STMicroelectronics Silicon Carbide AB, Ramshällsvägen 15, 60238 Norrköping, Sweden

Semilab, Coschützer Str. 70, 01705 Freital, Germany

STMicroelectronics Silicon Carbide AB, Stradale Primosole 50, 95121 Catania, Italy

STMicroelectronics Silicon Carbide Campus, Via Passo Martino - SP69, 95121

Catania, Italy

Semilab SDI, 12415 Telecom Dr., Tampa, FL 33637, USA

ajimmy.thornberg@st.com, gennadi.polisski@semilab.com, stella.giuffrida@st.com, viviana.deluca@st.com, alberto.catena@st.com, marshall.wilson@semilabsdi.com,

Keywords: 4 H -SiC, 200 mm , QUAD, Epitaxial, Defect Inspection, Electrical Deviation, EWS, MOSFET.

Abstract

Electrical Wafer Sorting (EWS) on wafers of are compared with electrical deviations and defectivity of initial epitaxial layers measured using Charge biased non-Contact Voltage imaging, QUAD (Quality Uniformity And Defects), and optical surface detection with PL-imaging, respectively. We successfully demonstrate an increased prediction rate in both KR (kill-ratio) and YI (yield-impact) compared to conventional PL-imaging. It is also shown that QUAD not only supplements PL-imaging but supersedes it predicting failure in some electrical test conditions. We therefore show that the combination of QUAD and PL-imaging results significantly improves the accuracy of device failure prediction by uniquely locating faults in the wafers, and thus, improving foresight of successful device fabrication.

Introduction

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Wide-bandgap semiconductor-based electronics are in constant development, with Silicon Carbide leading the way in next generation power devices. In particular within power electronics, SiC carries intrinsic advantages thanks to its higher thermal operation and lower switching losses compared to Silicon-based (Si) electronics [1]. However, the desirable properties of SiC comes with both a higher manufacturing cost and lower device-yield compared to the more conventional and malleable Si , owing to the complicated crystal growth process and subsequent manufacturing of SiC devices. Additionally, it is well known that the presence of surface and crystallographic defects impact the quality of epitaxial layers [2-4]. However, it is important to gauge the significance of each defect, to create models that can accurately predict the final device yield by adding additional layers to the conventional critical and non-critical classification [2-5]. Therefore, the importance of reliable metrology at an early stage of device making is, not only critical to improve yield prediction accuracy, but also to steer material to the appropriate application, and close feedback loops, ensuring improvement in the subsequent material growth and manufacturing.

Herein we follow up on the study conducted and presented in the prior year on the topic of linking epitaxial defectivity with surface voltage and photoluminescence (PL) mapping of epitaxially grown SiC-layers on substrates [6]. We combined the industry standard way of classifying topographical variations, reflectance, photoluminescence, and phase shift, by using optical surface detection systems, with surface voltage mapping using non-contact (CnCV) metrology
incorporating the "QUAD" (Quality Uniformity And Defects) method [7]. The QUAD technique uses whole wafer surface voltage mapping after charging the SiC surface to deep depletion. Electrically active defects are detected as cluster regions or spots with respect to the surrounding defect area. Applying a combined QUAD defect detection methodology, we have facilitated comparison to final EWS of SiC MOSFET devices using surface voltage contrast and in-die voltage values using a diebin map analysis. Die-bin map creation converts the surface voltage map into die grids, which in turn can be aligned to match various die-sizes of devices in production. This type of analysis gives the possibility to consider a die failed if the depletion voltage is below or the reverse bias leakage current is above a defined threshold value. By looking at the analogy of die failures related to some of the EWS parameters of the MOSFET, such as Gate and Drain leakage current (Igss, Idss), or Threshold Voltage (VTH), it is possible to compare QUAD wafer bin map results to EWS tests.

Experimental Details

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In this work, 7 wafers of with n-type SiC epitaxial layers were used. All substates were grown with a layer thickness of and a doping concentration of , on top of a thick buffer-layer with a doping concentration of . For the PL-mapping we used a KLA Candela 8520 and for surface voltage mapping we used a Semilab CnCV 210 [7-8]. With the CnCV tool we identified electrically active defects using the incorporated QUAD technique which involves whole wafer corona charging of SiC wafers to deep depletion followed by measurement of the surface voltage using a vibrating Kelvin Probe [6, 9]. Fig. 1 shows a QUAD map of depletion voltage. This map is then used to create a bin-die map using a particular device die size and depletion voltage threshold.

Following initial data acquisition, the wafers were used to produce n-channel MOSFET devices. To quantify yield and individual device failures, EWS results were used to check the functionality of each die by applying various conditions and evaluating the performance and electrical characteristics. Results from PL-mapping, QUAD and EWS are parsed and processed to a matching die-coordinate system, then spatially correlated, in order to see optically captured defectivity overlapping with reduced depletion voltage sites, and EWS results; see an example of one wafer in Fig. 2. With the results, yield impact was calculated using a method based on kill-ratio (KR) analysis, first published by M. Ono et al. [10] for Si integrated circuits using a four-category approach, later extended to SiC Trench-MOSFET devices by D. Baierhofer et al. [11], see Eq. 1.

Fig. 1. A QUAD map showing localized areas with lowered depletion voltage due to electrically active defects.

Fig. 1. A QUAD map showing localized areas with lowered depletion voltage due to electrically active defects.

Fig. 2. Example of wafer map with a) QUAD measured reduced depletion voltage sites, b) photoluminescence map and c) various electrical wafer sorting parameters map superimposed to form d) a combined map. Each color from the EWS map corresponds to different pass (white) or fail conditions (color).

Fig. 2. Example of wafer map with a) QUAD measured reduced depletion voltage sites, b) photoluminescence map and c) various electrical wafer sorting parameters map superimposed to form d) a combined map. Each color from the EWS map corresponds to different pass (white) or fail conditions (color).

Either the die shows good or bad electrical properties after EWS testing, denoted as or . In both cases it can either be, or not be, occupied by a defect or a reduced voltage site, subscripted as and ND, respectively, see Table 1.

Table 1. The four-category approach utilized in Eq. 1.

| Defect or Reduced Depletion Voltage Sites | No Defect or Reduced Depletion Voltage Sites
Good | GD | GND
Bad | BD | BND

Furthermore, yield-impact, , can be calculated using the :

Nominal yield-impact, , can be calculated using Poisson distribution yield model [12]:

Where KD and TD are the killer- and total-number of defects, or reduced depletion voltage sites. Fig. 2 shows an example of how the reduced depletion voltage sites and PL defects from the epitaxial layer are superimposed on the 650 V MOSFET grids matching the device positions. Utilizing the results from the 7 substrates in the previous study, we get a clear distribution of failures in nearly 12000 unique dies.

Experimental Results and Discussion

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In Fig. 3 a failure type distribution is shown of all dies failing any electrical test at EWS, where is the drain-source leakage current, defined by testing the maximum rating between drain and source, IGSS is the gate-source leakage current, similarly defined by applying a maximum rating between the gate and the source, and is the threshold voltage, defined by a minimum needed to create a conduction path between the source and drain terminal. Each failure type is defined by a subset of test conditions, for example Idss includes several VDS conditions, IGSS includes several VGs conditions and V several conditions. The defect types shown are the conventional ones, except the class "Epi Defect", which is a subset of defects in the epitaxial layer either too small or irregular to be accurately classified by the surface detection system, but significant enough to possibly cause parametric failure. On deep analysis, most of these are either small Triangles, Carrots or Micropits. Looking at the definable defects, see Fig. 3 a), Triangles and Stacking Faults are the most prominent, with the former causing more failures in tests and the latter causing more failures on the Idss and Igss tests. Triangles typically originate from substrate dislocations, like threading screw and basal plane dislocations, or surface roughness of the bare substrate. The distortion is thus mainly caused in the epitaxial layer, explaining why the failure cause by this type of defect is predominantly gate related. Stacking Faults in the epitaxial layer typically originate from Stacking Faults in the substrate. As the substrate acts as a drain in the device, a pronounced Idss failure due to this defect is not unlikely.

Fig. 3. Failure type distribution shown as a) distribution of defects for each failure test and b) distribution of failure types for each defect.

Fig. 3. Failure type distribution shown as a) distribution of defects for each failure test and b) distribution of failure types for each defect.

Particles appear to cause failures in all test types, but in Fig. 3 b) they only show failure in Igss and Idss tests. This is coincidently due to the die failing V th tests is not only occupied by a Particle, but also accompanied by at least one other defect. Looking at the total amount of failures, Bar Stacking Fault, Micropit and Scratches contribute very little. This does not imply they are nonsignificant, but rather that the sheer volume of Triangles and Stacking Faults causes more problems.

This is further highlighted in Table 2, showing that Bar Stacking Faults causes a higher rate of failure, , compared to Stacking Faults, . Similar for Micropit, with a low presence but high likelihood to cause failure, . Close to half of all the triangles and Micropits overlapped with depletion voltage leakage sites (QUAD), whereas less than of all the failed dies with a Stacking Fault, Bar Stacking Fault, Particle, or other smaller Epi Defect and showed electrical signature during QUAD measurements. Defects causing depletion voltage reduction during QUAD appear more likely to cause problems at EWS. Looking at the overall fail rate, Triangle defects are not only the most present defectivity, as seen in Fig. 3, but also causes the highest fail-rate, equal to a Micropit, as well as having the largest electrical signature as seen from QUAD, see Table 2.

Table 2. Fail rate of dies occupied by epitaxial defects and the ratio of those that are also occupied by a reduced depletion voltage site measured by QUAD.

| Triangle | Stacking Fault | Bar Stacking Fault | Micropit | Particle | Scratch | Epi Defect
Die Fail Rate | 42.69% | 15.89% | 25.97% | 44.68% | 18.11% | 32.00% | 35.33%
Overlapping QUAD Site | 43.37% | 8.21% | 5.00% | 42.86% | 13.04% | 25.00% | 8.04%

By applying the KR and YI model on the entire subset of defects and reduced depletion voltage sites, see Eq. 1-3, we can calculate the predication rate of both PL- and QUAD-mapping, see Table 3. Looking at all defects found through PL-mapping, the KR rate would be as low as . This is explained by the ratio of good to bad dies occupied by a Stacking Fault being too high. Examining Eq. 1, the numerator must be smaller than the denominator for the model to function and give sensible values. In essence, if a defect of a specific classification is more frequent on good dies than bad dies, the accuracy diminishes, and the model fails due false positives. If we remove Stacking Fault from the subset of all PL-Defects, we raise the KR of PL-Defects to . A similar trend can be seen for Particles, the occupancy of said defect on bad dies compared to good dies is very similar, so KR and YI are very low.

While the fail-rate, as seen in Table 2, gives a good estimate of what caused specific dies to go bad, the KR and YI, as seen in Table 3, gives a prediction on the entire population based on defects on both good and bad dies. Example: If defect X is present on all dies, good and bad, the fail rate would be . This is because defect X is on all bad dies, but it is also present on all good dies, so while fail rate is , the KR and YI would be very low due to false positives. Particles have a low KR at , even though looking at all the bad dies in the study, of them are occupied by a Particle. A wafer with plenty of particles post-epitaxy is thus unlikely to have a significant effect on YI. Both Triangles and Micropits show high KR, but Triangles, being more frequent, cause a higher YI. If a wafer was occupied by an equal number of Triangles and Micropits, the defects would have a similar effect on YI, but Triangles are 16x more frequent in the epitaxial layer than Micropits in this study and consequently the YI is of the Triangle defect is larger.

QUAD gives a significantly better accuracy on KR, , and is a better YI predictor, . Even if we refine the KR for all PL-Defects by removing false positives related to Stacking Faults, giving a KR of . Fig. 4 shows an overlay of a) EWS-QUAD and b) EWS-PL Defects that visually support the above calculation. The improved accuracy of QUAD is likely because it maps depletion voltage that is sensitive to the electrical behavior of defects in the epitaxial layer, as opposed to PL-mapping.

Fig. 4. Overlay EWS (Igss, Idss, Vth) failed die with a) QUAD detected defects using bin-die map and b) PL (Triangles, Stacking Faults, MicroPits) defects.

Fig. 4. Overlay EWS (Igss, Idss, Vth) failed die with a) QUAD detected defects using bin-die map and b) PL (Triangles, Stacking Faults, MicroPits) defects.

PL can be associated with electrical properties, as the excitation and recombination in effect is locally more likely to happen due to changes of the energy states, a more observable phenomena in mono-crystalline material since the event is isolated to crystal abnormalities (defects) but less relatable with parametric failures than localized reduced depletion voltage, which is observed at defective sites by QUAD.

Table 3. Kill-ratio and yield-impact of all QUAD sites, as well as PL-Defects and the respective classification, of the entire test-batch of MOSFET devices. The number of Stacking Faults causing device failure with respect to the total number of actual Stacking Faults is too small, making the Kill-ratio model unapplicable.

Kill-Ratio (%)
Yield Impact (%)
Nominal Yield Impact (%)

QUAD
36.81
5.20
6.01

All PL-Defects
10.61
2.71
5.64

Triangle
33.13
2.33
2.94

Stacking Fault
NA
NA
2.17

Bar Stacking Fault
12.92
0.07
0.14

Micro Pit
35.51
0.14
0.18

Particle
1.86
0.04
0.35

Scratch
25.23
0.06
0.09

Epi Defect
16.33
0.71
1.25

All PL-Defects
(no Stacking Fault)
22.51
3.00
4.27

In Fig. 5 the accuracy of PL- and QUAD-mapping is illustrated by calculating the ratio of bad dies each respective method successfully captures. For IDSS and IGSS related failures both methods can identify a similar quantity of bad dies while for VTH related failures QUAD-mapping seems more accurate, finding nearly more dies. The combined capture rate is calculated by looking only at uniquely found bad dies for each respective method. Here it is clear that both methods complement each other very well as the combined capture rate is significantly higher than for each method on its own. Worth noting is that both PL- and QUAD-mapping relies heavily on measurement conditions and recipe tuning.

Fig. 5. Rate of overlap with EWS tests for PL-mapping, purple bar, and CnCV QUAD-mapping, blue bar, and the combined capture rate of both methods, green bar, with bad dies measured by EWS. Combined capture rate is calculated from dies uniquely captured by either method.

Fig. 5. Rate of overlap with EWS tests for PL-mapping, purple bar, and CnCV QUAD-mapping, blue bar, and the combined capture rate of both methods, green bar, with bad dies measured by EWS. Combined capture rate is calculated from dies uniquely captured by either method.

The capture rate of either method can be improved marginally by further tuning of the tools and recipes used. In this study we replicated PL-imaging conditions used in a device production line, while QUAD tuning is still in implementation phase. The remainder of the EWS failures associated with neither PL-Defects or QUAD sites are attributed to device fabrication faults occurring between initial epitaxial growth and EWS testing. In essence, this means that roughly one half of the failures are due to defectivity in the epitaxial layer while major parts of the other half is related to the device fabrication process itself. Further work to also include a possible effect of dislocation could strengthen the conclusion of PL and QUAD-imaging as complementary techniques to verify the quality level of substrate and epitaxy.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.376.19.pdf

Comparison between PL- and QUAD-mapping of wafers post-epitaxy, used before manufacture of roughly MOSFETs devices from 7 wafers of , shows that QUAD-mapping is a valid alternative, and complement, to PL-mapping. The model used to calculate KR and YI shows a higher probability for QUAD to find dies that cause Idss, IGss and Vth, the more common failures at EWS. As supported by the KR calculations, the accuracy of QUAD-mapping is also better than the PL-mapping. QUAD is also able to improve on the prediction of yield-impact. The capture rate of these combined methods shows that each respective technique uniquely predicts failures of dies that the other one missed. This information can be used to not only to improve the capture rate for both methods, but most important to progress the overall accuracy of KR and YI of defects and depletion voltage leakage sites.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/SSP.376.19.pdf

ARCHIMEDES is supported by the Chips Joint Undertaking and its members, including the topup funding by National Authorities under Grant Agreement No 101112295.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.19.pdf

X. She, A.Q. Huang, O. Lucia, B. Ozpineci, Review of silicon carbide power devices and their applications, IEEE Transactions on Industrial Electronics, 64, 10 (2017) 8193-8205.

T. Kimoto, H. Watanabe, Defect engineering in SiC technology for high-voltage power devices, Applied Physics Express, 13 (2022).

T. Neyer, M. Domeij, H. Das, S. Sunkari, Is there a perfect SiC MosFETs Device on an imperfect crystal?, IEEE International Reliability Physics, (2021) 1-6.

H. Das, S. Sunkari, J. Justice, H. Pham, G. Park, Y.H. Seo, Statistical Analysis of Killer and NonKiller defects in SiC and the Impacts to Device Performance, MSF 1004 (2020) 458-463.

E. van Brunt, A. Burk, D.J. Lichthenwalner, R. Leonad, S.Sabri, D.A. Gajewski, A. Mackenzei, B. Hull, S. Allen, J.W. Palmour, Performance and Reliability Impacts of Extended Epitaxial Defects on 4H-SiC Power Devices, Silicon Carbide And Related Materials, 137142.

J. Thornberg, G. Polisski, E. Carria, M. Isacson, B. Magnusson, Epitaxial defectivity characterization combining surface voltage and photoluminescence mapping, ICSCRM, (2023).

M. Wilson, D. Greenock, D. Marinskiy, C. Almeida, J. D'Amico, and J. Lagowski, presented at CS Mantech Conference on Compound Semiconductor Manufacturing Technology, (2021).

M. Wilson, A. Findlay, A. Savtchouk, J. D'Amico, R. Hillard, F. Horikiri, J. Lagowski, ECS Journal of Solid State Science and Technology, 6, 11 (2017) 3129-3140.

M. Wilson, Compound Semiconductors, 25, 6 (2019).

M. Ono, H. Iwata, K. Watanabe, Accuracy of yield impact calculation based on kill ratio, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, (2002) 87-91.

D. Baierhofer, B. Thomas, F. Staiger, B. Marchetti, C. Förster, E. Erlbacher, Correlation of Extended Defects with Electrical Yield of SiC MOSTFET Devices, Defect and Diffusion Forum, 426 (2023) 11-16.

J. A. Cunningham, The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing, Transactions Semiconductor Manufacturing, 3, 2 (1990) 60-71.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 27-31

doi: 10.4028/p-CV0Eru

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-10

Defect Density Reduction in 4H-SiC (0001)
Epilayer via Growth-Interruption during Buffer Layer Growth

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

Shiv Kumar , Lakshmi Kanta Bera , Xuan Sang Nguyen , Wen Dong Song , An Min Amanda Lee , Xinyi Li , Eng Soon Tok , Madurai Srinivasan Bharathi , Chilla Damodara Reddy , Umesh Chand , Surasit Chung , Navab Singh and Yee Chia Yeo

Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR), Singapore 138634

Department of Physics, National University of Singapore, 2 Science Drive 3,

Abstract

In this paper, we have investigated the influence of growth-interruption during buffer layer growth on killer defect density in SiC epilayer grown over substrates. We have observed that the growth-interruption method reduces total killer defect density by . Implementing growth-interruption in the buffer layer is a novel approach to mitigate epitaxial defects such as in-grown stacking faults (SFs), triangular defects, and basal plane dislocations (BPDs) in the drift layer and provide an extra margin to bipolar degradation by terminating BPDs early in the heavily doped buffer layer. The defect reduction mechanism in the presence of hydrogen has been simulated using Kinetic Monte Carlo (KMC) simulations.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

SiC demonstrates excellent physical properties for power devices; however, defects in the epitaxial layer have a detrimental impact on their performance. Although a off-axis epitaxial layers have shown improved quality, but they still fail to meet the requirements for high-voltage devices due to low yield [1-5]. In the SiC epitaxial layer, various morphological defects exist, including triangles, carrots, pits, step bunching, stacking faults (SFs), BPDs, and downfalls. These defects can be classified into two types: process-induced defects formed during the epitaxial process and extended defects propagating from the substrate. Previous studies have used growth interruption in the drift layer [6-8]. To reduce total killer defect density in the epitaxial layer, it's essential to optimize the epitaxy growth process to prevent the propagation of BPDs and SFs into the drift layer. This study focuses on utilizing growth-interruption during the buffer layer to minimize the defects propagating from the substrate, as well as during the epitaxy growth process. The mechanism of defect reduction by hydrogen inclusion at the surface of the buffer layer during growth interruption and its subsequent interaction in growth has been investigated by Kinetic Monte Carlo (KMC) simulations.

Experiment

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

We used 150 mm Si -face 4H-SiC (0001) n-type substrates (Cree, Inc.) with off-oriented toward for epitaxy growth. Processing was started with RCA cleaning to remove surface particles. The epitaxial growth was carried out using a single-wafer CVD reactor, PE1O8 (ASM International N.V.), with growth rate and doping concentration . The source gases were trichlorosilane ( ) and ethylene ( ) with hydrogen ( ) as carrier gas. We kept the wafer in the reactor for the in-situ growth-interruption. We used KLA Candela 8520 for substrate and epitaxy defect inspection, FT-IR for the epitaxy thickness, Hg-CV for carrier concentration, and AFM for surface roughness measurement after epitaxy.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

In this study, we have used four substrates for epitaxy growth viz. G1:W1, G2:W2 (without interruption), and IG1:W3, IG2:W4 (with interruption growth). Epitaxy was done in consecutive runs to minimize process variation related to the reactor. The temperature, pressure, and ratio were kept constant throughout these runs. Fig. 1(a) shows the temperature profile for the growthinterruption process. The interruption temperature is slightly below the epitaxy growth temperature to minimize hydrogen etching. The epilayer thickness was measured at 32 points, with a 5 mm edge exclusion [Fig. 1(b)]. The results demonstrate that the uniformity across the wafer is better than .

Fig. 1. (a) Process sequence of the epitaxy for growth interruption experiments. (b) Thickness measurement of the epilayer across (inset shows the measured points map) the wafer with 5 mm edge exclusion. The thickness uniformity is better than across the wafer.

Fig. 1. (a) Process sequence of the epitaxy for growth interruption experiments. (b) Thickness measurement of the epilayer across (inset shows the measured points map) the wafer with 5 mm edge exclusion. The thickness uniformity is better than across the wafer.

Fig. 2(a) and (b) show the defect scan maps without and with the interruption-growth, respectively. We observed a reduction in total killer defect density compared to the growth without interruption [Fig. 2(c)]. This is attributed to the conversion of BPDs to TED due to growthinterruption. To better understand how interrupting the growth of the buffer layer can reduce defect density, we used an additional SiC substrate from the same supplier. We assessed the roughness immediately after -etching at the growth temperature ( ) and then at the interruption temperature ( ) [Fig. 2(e)]. AFM scans reveal that the substrate exhibits a smoother surface measured at the interruption temperature " I " compared to -etching at drift layer growth temperature "G" on a area.

Fig. 2. Candela 8520 defect scan maps (a) without and (b) with interruption growth. (c) Defect density without and with the interruption growth. (d) High-resolution images ( ) of typical SiC defects in different channels in Candela. (e) AFM images at the growth (G) and interruption (I) temperatures at the center of the substrate. (f) KMC simulations on the extension of SFs in the epilayer as a function of the thickness of the epitaxial layer.

Fig. 2. Candela 8520 defect scan maps (a) without and (b) with interruption growth. (c) Defect density without and with the interruption growth. (d) High-resolution images ( ) of typical SiC defects in different channels in Candela. (e) AFM images at the growth (G) and interruption (I) temperatures at the center of the substrate. (f) KMC simulations on the extension of SFs in the epilayer as a function of the thickness of the epitaxial layer.

This reduction in surface roughness leads to a decrease in surface free energy, which minimizes the disruption of intermolecular bonds and results in a significant reduction in defects during the subsequent growth of the second buffer layer. The mechanism of defect reduction by hydrogen (H) inclusion at the surface of the buffer layer during growth interruption and its subsequent interaction in growth has been investigated theoretically. We adopted the Kinetic Monte Carlo (KMC) simulations with a superlattice model [9] in which the neighboring atoms of the regular SiC lattice are considered part of the defective lattice, and vice versa. During the growth interruption process, it is assumed that H -atoms from the subsurface region diffuse into the epitaxial layer and can occupy in the defect sites due to the lower surface energy. When an H -atom occupies a defective lattice site, it prevents the formation of stacking faults (SFs) in that site. As the nearest neighbor to the defective site is the regular lattice, these atoms become part of the regular SiC lattice, limiting the extension of SFs. Figure 2(f) depicts the reduction in SF extension as the epitaxial layer thickness increases, with and without H -atoms. The results clearly show that the presence of H -atoms occupying potential SF extension sites can prevent the formation of SFs in the epitaxial layer. Both experimental and simulation results demonstrate that interrupting the growth process at an early stage during buffer growth significantly reduces defect density in the epilayer. We achieved a calculated epi-yield of based on die size.

Conclusion

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

In summary, growth interruption during buffer layer epitaxial growth for defect reduction in 4 H SiC was successfully performed. This led to the significant reduction of total killer defect density by . Moreover, we achieved defect-free usable area on a 150 mm substrate with a yield of based on die size.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

This work was supported by A*STAR (Agency for Science, Technology and Research, Singapore) under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.27.pdf

T. Kobayashi, K. Harada; Y. Kumagai, F. Oba, Y.-I. Matsushita, Native point defects and carbon clusters in 4H-SiC: A hybrid functional study, J. Appl. Phys. 125 (2019) 125701.

S. Wei, Z. Yin, J. Bai, W. Xie, F. Qin, Y. Su, D. Wang, The structural and electronic properties of Carbon-related point defects on 4H-SiC (0001) surface, Appl. Surf. Sci. 582 (2022) 152461.

F. Ren, J. C. Zolper, Wide energy bandgap electronic devices, World Scientific Publishing, Singapore, 2003.

T. Kimoto, J. A. Cooper, Fundamentals of Silicon Carbide Technology, Wiley, Singapore, 2014.

L. Zhao, Surface defects in 4H-SiC homoepitaxial layers, Nanotechnol. Precis. Eng. 3 (2020) 229.

R. E. Stahlbush, B. L. VanMil, R. L. Myers-Ward, K-K. Lew, D. K. Gaskill, C. R. Eddy Jr., Basal plane dislocation reduction in 4H-SiC epitaxy by growth interruptions, Appl. Phys. Lett. 94 (2009) 041916.

T. Rana, J. Wu, V. Pushkarav, I. Manning, A study of process interruptions during pre- and postbuffer layer epitaxial growth for defect reduction in 4H SiC, ICSCRM (2023) 950.

X. Gong, T. Xie, F. Hu, P. Li, S. Ba, L. Wang, W. Zhu, High-quality 4H-SiC homogeneous epitaxy via homemade horizontal hot-wall reactor, Coatings 14 (2024) 911.

M. Camarda, A. L. Magna, F. L. Via, J. Comput. Phys. 227 (2007) 1075.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 33-40

doi: 10.4028/p-MI3pHl

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-10

Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

Kazuya Ishibashi , Naoki Shikama , Hiroki Niwa , Takanori Tanaka , Hiroyuki Amishiro , Akifumi Imai , Katsutoshi Sugawara , Yasuhiro Kagawa and Akihiko Furukawa

Power Device Works, Mitsubishi Electric Corporation, 1-1-1 Imajuku-higashi, Nishi-ku, Fukuoka-shi, Fukuoka, 819-0192, Japan

Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki-shi, Hyogo, 661-8661, Japan

Ishibashi.Kazuya@ak.mitsubishielectric.co.jp, Shikama.Naoki@df.mitsubishielectric.co.jp, Niwa.Hiroki@dp.mitsubishielectric.co.jp, Tanaka.Takanori@cb.MitsubishiElectric.co.jp, Amishiro.Hiroyuki@cb.mitsubishielectric.co.jp, Imai.Akifumi@ys.MitsubishiElectric.co.jp,

Sugawara.Katsutoshi@ea.MitsubishiElectric.co.jp, Kagawa.Yasuhiro@cj.mitsubishielectric.co.jp, Furukawa.Akihiko@df.MitsubishiElectric.co.jp

Keywords: MOSFET, body diode, bipolar degradation, stacking fault, proton implantation

Abstract

Bipolar degradation is a well-known issue when using body diodes in SiC-MOSFETs. Recent studies suggest that (proton) implantation can effectively inhibit this degradation, but demonstrations on its suppression are still limited. Therefore, in this study, we have experimentally demonstrated how the expansion of Shockley-type stacking faults (SSFs) is suppressed by proton implantation. We fabricated a vertical SiC-MOSFET, in which protons were implanted into the middle depth of the drift layer. We then subjected the body diode to continuous current stress and performed photoluminescence (PL) analysis. Detailed PL image and emission spectral analysis of SSFs revealed that the proton-implanted layer can function as a recombination-enhancing layer during bipolar operation. Furthermore, it can be formed at any depth within the drift layer by controlling the energy, offering a significant advantage in the design of SiC-MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

Silicon carbide ( SiC ) is a desirable material for power devices due to its superior properties such as wide bandgap, high critical electric field, and high thermal conductivity. A body diode, which is a parasitic p-n diode within a MOSFET structure, is widely utilized as a free-wheeling diode. By using body diodes, it is possible to reduce costs and achieve miniaturization of systems that comprise SiC power devices, by eliminating the external free-wheeling diode. However, when using the body diode in SiC-MOSFETs, bipolar degradation is a key issue that needs to be considered. The recombination of electron-hole pairs during bipolar operation can lead to the expansion of Shockley-type stacking faults (SSFs), which can lead an increase in forward voltage, on-resistance [1-3], and/or drain-source leakage current. A well-known method for preventing the bipolar degradation is the growth of a highly nitrogen-doped epitaxial layer, which serves as a recombination-enhancing buffer within the drift layer [4]. On the other hand, in recent years, (proton) implantation has been reported to successfully inhibit the expansion of SSFs in SiC [5,6]. This technique could be a promising candidate, however, there are limited reports demonstrating this inhibitory effect. In this work, to gain a more detailed understanding of the suppression mechanism, we conducted a detailed defect analysis of a proton-implanted SiC-MOSFET in which SSFs expanded after the application of current stress.

Experimental Procedure

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

A vertical SiC-MOSFET was fabricated on a thick drift layer, which included a protonimplanted layer, as shown in Fig. 1. The drift layer was grown on a -off substrate with a diameter of 150 mm . Protons were partially implanted into the middle depth of the drift layer at a dose of , by partially shielding the device's active area using a silicon piece. Figure 2
shows the experimental flow. Proton implantation was performed just after the epitaxial growth. Following device fabrication, dies were cut from the wafer, and a continuous current stress test was carried out on each body diode of all the dies under conditions of at for a duration of 2 minutes. Subsequently, a photoluminescence (PL) inspection was performed after removing all materials on the SiC , such as metal/gate electrodes and . At last, Burgers vectors of partial dislocations bounding the SSFs were investigated using a transmission electron microscope (TEM) under two-beam excitation conditions, specifically and .

PL analysis after applying the current stress revealed multiple shape patterns of SSF expansion, such as triangular and bar-shaped, due to different Burgers vectors [7]. Additionally, there were some dies that were stressed without SSFs. In this paper, we focus on discussing the detailed analysis results of a specific single die, which exhibits bar-shaped SSFs originating from the proton non-implanted region and expanding across the proton-implanted region.

Fig. 1. Cross-sectional schematic diagram of the proton-implanted SiC-MOSFET.

Fig. 1. Cross-sectional schematic diagram of the proton-implanted SiC-MOSFET.

Fig. 2. Experimental flow. The proton implantation was performed just after the epitaxial growth but before the activation annealing.

Fig. 2. Experimental flow. The proton implantation was performed just after the epitaxial growth but before the activation annealing.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

Figures 3(a) and (b) show PL images of the expanded SSFs in the proton-implanted SiC-MOSFET after the continuous current stress test, and Fig. 4 presents a three-dimensional schematic diagram cut along a basal plane that includes specific SSF (SSF1). In the PL image taken at shown in Fig. 3(a), two bar-shaped SSFs which exhibit bright emission are observed. Moreover, in Fig. 3(b), Si- and C-core partial dislocations that form the outline of the SSFs can be seen as strong and weak emissions [2], which was taken at the infrared region ( ). These SSFs (SSF1 and SSF2) on different basal planes appear to overlap along the c-axis ([0001]), as illustrated in the schematic in Fig. 3(c). Both SSFs have their starting points ( and ') of expansion in the proton non-implanted region and expand in the [ ] direction. Since carrier recombination mainly occurs in the lightly nitrogen-doped region, the SSF expansion is restricted between the p-well ( PW )/drift layer and the drift/conversion layer interfaces, as shown in Fig. 4. In Fig. 3(a), we can see that the SSFs, indicated by the bright contrast, reach the boundary including points , and , and display a different characteristic feature in the lower region. It is revealed that the SSFs continue to expand even after entering the proton-implanted region. However, the line e-f emerges as a dark contrast near the center of the SSFs. This dark region has a width of about in the direction of the step flow ([11 ), which is the intersection with the SSFs. This width is attributed to the varying depths of the basal planes where and are formed. In this region, two intersection lines with the SSFs for a single proton-implanted layer coexist. Notably, the edge of , including points and , formed an incomplete shape in the left region of the line e-f. This region is deeper than the proton-implanted layer in the drift layer. These results suggest that when the expanded SSFs reached the proton-
implanted region, the SSF structure remained unchanged, while the dislocation motion was hindered only in the area deeper than the proton-implanted layer.

Fig. 3. PL images of the bar-shaped expanded SSFs in the proton-implanted SiC-MOSFET observed with different wavelengths. The wavelengths of the observation filters are (a) and (b) . (c) Schematic illustration of the two overlapped SSFs on different basal planes, with and as the respective starting points of expansion.

Fig. 3. PL images of the bar-shaped expanded SSFs in the proton-implanted SiC-MOSFET observed with different wavelengths. The wavelengths of the observation filters are (a) and (b) . (c) Schematic illustration of the two overlapped SSFs on different basal planes, with and as the respective starting points of expansion.

Fig. 4. Three-dimensional schematic diagram of the SSF in the proton-implanted SiC-MOSFET. The specific basal plane, including as discussed in Fig. 3 is shown. The red dashed line shown in the figure indicates the boundary between the proton-implanted region and the proton nonimplanted region.

Fig. 4. Three-dimensional schematic diagram of the SSF in the proton-implanted SiC-MOSFET. The specific basal plane, including as discussed in Fig. 3 is shown. The red dashed line shown in the figure indicates the boundary between the proton-implanted region and the proton nonimplanted region.

Figure 5(a) shows a planar TEM image of the bar-shaped expanded in the protonimplanted SiC-MOSFET, taken at near the c-axis ([0001]) incident condition. Figures 5(b) and (c) are planar TEM images taken under different two-beam excitation conditions and ,
respectively. All the images were taken at the same location, which includes the starting point (a' in Fig. 3) of the expansion of , as shown in the schematic illustration in Fig. 5(d). From these TEM images, it is estimated that is composed of three types of partial dislocations ( and ). These partial dislocations are part of the initial BPD, with and expanding after the application of current stress. Conversion of two different threading edge dislocations (TED and ) were confirmed at the end points ( and ) of . is converted from , and is converted from and , which are the partial dislocations bounding . Additionally, although the explanation and illustration are omitted, and are expanded from the initial BPDs which have the same type of dislocation structure. and are partial dislocations which correspond to the same positions on and , respectively. The same applies to and . The dislocation structure observed in this experiment is similar to the TED-BPD-TED structure reported by Ota et al., which is thought to be formed by the conversion from TED to BPD within the drift layer [8]. It is believed that the TED-BPD-TED structure observed in our experiment also formed within the drift layer after epitaxial growth and during the device fabrication process, and that its BPD segment was expanded into the bar-shaped SSF due to the current stress. The Burgers vector of the dislocation can be determined using the contrast rule , where the contrast of a dislocation is absent when its Burgers vector is perpendicular to the vector. In Fig. 5(b), the contrast of , , and disappeared at . In Fig. 5(c), and the contrast of and disappeared at . From them, Burgers vectors of each partial dislocation were predicted as follows: , , and have , and and have , respectively. Consequently, the structure of the initial BPDs of and were identified as , with a dislocation line direction .

Fig. 5. (a) Planar TEM image at the starting point of expansion of the bar-shaped SSF (SSF2) in the proton-implanted SiC-MOSFET taken at near the c-axis ([0001]) incident condition. (b), (c) TEM images taken at different two-beam excitation conditions and , respectively.
(d) Schematic illustration of .

Fig. 5. (a) Planar TEM image at the starting point of expansion of the bar-shaped SSF (SSF2) in the proton-implanted SiC-MOSFET taken at near the c-axis ([0001]) incident condition. (b), (c) TEM images taken at different two-beam excitation conditions and , respectively. (d) Schematic illustration of .

It has been reported that when the Burgers vector and dislocation line direction are identified, the expansion pattern of SSF can be uniquely determined from their combination and a type of dislocation loop [9]. In this case, the Burgers vector of the initial BPD was determined from the SSF expansion
pattern as , with the dislocation line direction . The structures of the initial BPD and SSF are schematically illustrated in Fig. 6.

Fig. 6. Schematic illustrations of (a) the initial BPD with Burgers vector , and the line direction , (b) the dissociated state, and (c) the expanded shape of SSF.

Fig. 6. Schematic illustrations of (a) the initial BPD with Burgers vector , and the line direction , (b) the dissociated state, and (c) the expanded shape of SSF.

Figures 7(a)-(f) show results of the PL spectra observed in various regions of the proton-implanted SiC-MOSFET. Figures 7(d) and (a) compare the results with and without proton implantation taken at the peripheral area of the MOSFET chip, where no Al ion implantation of the PW has been done. In Fig. 7(d), the PL peak corresponding to the band edge emission of decreased, and a broad peak ranging from 420 to 600 nm due to the implantation defects created by proton implantation was observed. Figures 7(e) and (b) compare the results with and without proton implantation in the active area. In Fig. 7(b), a broad peak due to the implantation defects created by Al ion implantation was observed. Interestingly, the broad peaks among the signals shown in Figs. 7(b), (d), and (e) are similar. Although not all defect levels in the band gap exhibit luminescence, these results suggest that some of the same luminescent defect levels were formed during the ion implantations of both Al and H . These are considered to correspond to the point defects that enhance carrier recombination. Figures 7(f) and (c) compare the results with and without proton implantation in the region where the SSFs exist. In Fig. 7(c), a clear peak corresponding to the Single SSF (1SSF) at was observed [10]. However, near the intersection of the SSFs and the protonimplanted layer (line e-f shown in Figs. 3 and 4), not only was the band edge emission inhibited, but the emission of the SSFs was also suppressed, leading to a reduction in their PL intensities, as shown in Fig. 7(f).

Figure 8 shows the comparison of the PL spectra observed in different regions which include SSFs in the active area of the proton-implanted SiC-MOSFET. The observation points , and share the same cross-sectional structure, but the positional relationship between the SSFs and the protonimplanted layer varies in each case, as illustrated in the schematic diagram in Fig. 9. At , the SSFs are located under the proton-implanted layer, while at , they are on the proton-implanted layer, and at , they are near the interface of the PW/drift layer. At , a clear peak corresponding to 1SSF can be observed. However, at both and , where the stacking faults are in contact with either the proton-implanted layer or the PW , the peak intensities are reduced. This suggests that defect levels, which inhibit recombination of electron-hole pairs and emission at the SSFs, were introduced in the proton implanted layer as well as the PW. From these results, it is inferred that point defects in the drift layer exist at high densities in both implanted layers, as schematically illustrated in Fig. 9. It is estimated that the proton-implanted layer enhances carrier recombination, leading to a lower density of excess carriers in the region deeper than the proton-implanted layer. Based on several reports suggesting that SSFs can contract with fewer injected carriers [11-14], It is hypothesized that the incomplete SSF shape observed deeper than the proton-implanted layer is a result of the contraction of the SSFs. In conclusion, we infer that the proton-implanted layer can function as a recombinationenhancing buffer during the bipolar operation, resulting in suppression of the expansion of SSFs.

Furthermore, it offers a significant advantage in device design of SiC -MOSFETs as this buffer layer can be formed at any depth within the drift layer by controlling the implantation energy.

Fig. 7. Comparison of PL spectra observed in various regions of the proton-implanted SiCMOSFET. (a) , (b) , and (c) are all observation points within the proton non-implanted region, respectively located at : the peripheral area, : the active area, : the active area with the SSFs.
(d) , (e) , and (f) are all observation points within the proton-implanted region, each having the same cross-sectional structure as , and , respectively, except for the presence of the proton-implanted layer in the middle depth of the drift layer. All data were obtained under the identical PL condition excited by He-Cd laser ( ) at room temperature, and the electronhole pairs created by the excitation light reach almost the entirety of the drift layer.

Fig. 7. Comparison of PL spectra observed in various regions of the proton-implanted SiCMOSFET. (a) , (b) , and (c) are all observation points within the proton non-implanted region, respectively located at : the peripheral area, : the active area, : the active area with the SSFs. (d) , (e) , and (f) are all observation points within the proton-implanted region, each having the same cross-sectional structure as , and , respectively, except for the presence of the proton-implanted layer in the middle depth of the drift layer. All data were obtained under the identical PL condition excited by He-Cd laser ( ) at room temperature, and the electronhole pairs created by the excitation light reach almost the entirety of the drift layer.

Fig. 8. Comparison of PL spectra observed in different regions with SSFs in the active area of the proton-implanted SiC-MOSFET. In , and , the positional relationship between the SSFs and the proton-implanted layer in the drift layer varies, as shown in Fig. 9. All data were obtained under the identical PL condition excited by He-Cd laser ( ) at room temperature, and the electron-hole pairs created by the excitation light reach almost the entirety of the drift layer. Each peak intensity is normalized by the peak of the band edge.

Fig. 8. Comparison of PL spectra observed in different regions with SSFs in the active area of the proton-implanted SiC-MOSFET. In , and , the positional relationship between the SSFs and the proton-implanted layer in the drift layer varies, as shown in Fig. 9. All data were obtained under the identical PL condition excited by He-Cd laser ( ) at room temperature, and the electron-hole pairs created by the excitation light reach almost the entirety of the drift layer. Each peak intensity is normalized by the peak of the band edge.

Fig. 9. Schematic diagram of the distribution of point defects introduced during the implantation process for proton-implanted SiC-MOSFET. Point defects in the drift layer are expected to exist at high densities in both the PW and the proton-implanted layer.

Fig. 9. Schematic diagram of the distribution of point defects introduced during the implantation process for proton-implanted SiC-MOSFET. Point defects in the drift layer are expected to exist at high densities in both the PW and the proton-implanted layer.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

In this work, we have investigated the effect of proton implantation on suppressing the expansion on SSFs in SiC-MOSFETs. We fabricated a three-dimensional structure in which protons were partially implanted into the middle depth of the drift layer in SiC-MOSFET, and experimentally demonstrated how the proton-implanted layer suppresses the SSF expansion. When the expanded SSFs reached the proton-implanted region, the SSF structure remained unchanged, while the dislocation motion was hindered only in the area deeper than the proton-implanted layer. Detailed PL images and spectra of the expanded SSFs suggest that the proton-implanted layer within the drift layer can function as a recombination-enhancing layer during bipolar operation. It is inferred that the primary mechanism of degradation suppression is due to the point defects introduced by proton implantation. We believe that proton implantation allows for the formation of a recombinationenhancing layer at any depth within the drift layer by controlling the energy, offering a significant advantage in the design of SiC-MOSFETs having highly reliable body diodes.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

The authors would like to thank Dr. S. Hayashi of Toray Research Center, Inc. for his technical support of TEM observation. We would also like to thank N. Kawabata, K. Miyazaki, A. Iijima, and Dr. K. Kawahara of Mitsubishi Electric for their insightful discussion and support of experiments.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.33.pdf

A. Galeckas, J. Linnros and P. Pirouz, Appl. Phys. Lett. 81, 883 (2002).

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T. Tawara, T. Miyazawa, M. Ryo, M. Miyazato, T. Fujimoto, K. Takenaka, S. Matsunaga, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto and H. Tsuchida, J. Appl. Phys. 120, 115101 (2016).

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A. Tanaka, H. Matsuhata, N. Kawabata, D. Mori, K. Inoue, M. Ryo, T. Fujimoto, T. Tawara, M. Miyazato, M. Miyajima, K. Fukuda, A. Ohtsuki, T. Kato, H. Tsuchida, Y. Yonezawa and T. Kimoto, J. Appl. Phys. 119, 095711 (2016).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 41-46

doi: 10.4028/p-QQ9CvK

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-06-06

Accepted:
2025-06-06

Online:
2025-09-10

Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

The original version of this paper is available on https://www.scientific.net/SSP.376.41.pdf

Jake Soto , Bruce Odekirk , Sergey Maximenko , Benjamin Rodgers , Matthew Fisher , Kevin Speer

Microchip Technology Inc., 2355 W. Chandler Blvd., Chandler, AZ, U.S.A.

benjamin.rodgers@microchip.com, matthew.fisher@microchip.com, kevin.speer@microchip.com

Keywords: SiC, epitaxial defects, quality standards, yield, reliability, photoluminescence, UVPL, UIS, unclamped inductive switching, avalanche, JBS diode

Abstract

Due to the lack of internationally accredited quality standards for silicon carbide (SiC) epiwafers, vendors provide defect maps using different metrology techniques and naming conventions, making it difficult to draw correlations between defect types and unclamped inductive switching (UIS) behavior. This study tested 1700 V rated Junction Barrier Schottky Diodes (JBS) using materials from five epiwafer suppliers and concluded that, without maps having industry-standardized defect names and showing precise locations, sizes, and shapes, device manufacturers cannot effectively predict UIS yield and reliability.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.41.pdf

The correlation between epitaxial (epi) material defects and diode UIS failures has not yet been clearly demonstrated. Historically, studies have focused on understanding general defect failure mechanisms of SiC MOSFETs [1,2,3], SiC device failure correlations [4,5], and studies of SiC diode design ruggedness . This study was unable to establish a direct epi defect UIS failure correlation because epiwafer vendors do not provide sufficiently detailed defect maps for analysis, and results herein strongly point toward epi material as a contributor to UIS JBS diode failures. For SiC to become pervasive in power electronics, epiwafer quality standards that are comprehensive and internationally recognized are essential. After all, epiwafers are literally the foundation upon which devices are built as well as constituting a large portion of device cost. To deliver the reliability, price, and quantities that end users require to transition from silicon to SiC , device manufacturers must be able to apply statistical methods to establish correlations between epiwafer quality, specific defect types, and performance (including long-term reliability) of finished devices.

Today's manufacturers of SiC power devices rely on crystal defect maps for such predictions; these defect maps are provided by epiwafer vendors. Unfortunately, the SiC community does not yet have quality standards to which epiwafer vendors must comply. Device manufacturers must reconcile different defect terminology reported by various mapping tools, often leaving defective device performance (or failure) a mystery. Some epiwafer defects go entirely unrecognized due to insufficient detectivity of production-scale metrology techniques. Capabilities exist to address these issues, but standards are needed. Using the unclamped inductive switching (UIS) test, this paper illustrates an example where existing capabilities should be used to elucidate defect-performance relationships so that standards may be established.

Experimental

The original version of this paper is available on https://www.scientific.net/SSP.376.41.pdf

The UIS test is standard industry practice for production verification of the avalanche energy rating of power devices [14]. The relevance of UIS testing is three-fold: First, designers rely on this metric to select devices that can survive avalanche breakdown given the operating conditions of their systems. Second, due to the high energy levels the device may see during avalanche, epiwafer defects that may be benign under normal conditions could precipitate critical failures during UIS testing.

Third, UIS testing to failure has proven valuable for appraising epiwafer quality due to its timeliness and low use of resources, as compared to extended lifetime stresses which can take months to complete.

In this work, five different turn-key epiwafer vendors ( A , B , C , D , E ) were used to fabricate 1700 V JBS diodes using Microchip's production fabrication process for Microchip part number MSC050SDA170B. Figure 1 shows portions of epiwafer defect maps provided by each of the five vendors; the reader can see how each supplier uses a different classification system. To objectively evaluate the epiwafer quality of each vendor, control wafers from Vendor A were processed with each run. Wafers were probed and sawn, and passing devices were assembled into TO-247 packages for characterization.

Fig. 1. Excerpts of epiwafer epi defect maps provided by five different vendors. Vendors A , B & E designate defects, but don't report the same defects. Vendors C & D are not clearly defined.

Fig. 1. Excerpts of epiwafer epi defect maps provided by five different vendors. Vendors A , B & E designate defects, but don't report the same defects. Vendors C & D are not clearly defined.

The UIS test circuit is shown in Figure 2. Measurements were taken using the ITC 55100C system with the ITC 55HVD1 high voltage diode adapter box [15] represented by the dotted square, which uses a MOSFET with higher breakdown voltage than the device under test (DUT) to channel the UIS energy into the DUT. The test voltage is set to 150 V to speed up the inductor charging time and reduce DUT heating.

Fig. 2. Circuit diagram of single-pulse UIS test bed.

Fig. 2. Circuit diagram of single-pulse UIS test bed.

Figure 3 shows typical UIS waveforms from the study. To begin, the MOSFET is in the ON state to charge the inductor to an energy level, , then the MOSFET is abruptly switched to the OFF state. Because the MOSFET in the ITC diode adapter box has a much higher blocking voltage rating than the JBS diode DUT, the DUT is forced into avalanche breakdown; this leads to a rise in junction temperature until the DUT undergoes catastrophic and permanent failure, as seen by the collapse of the DUT's cathode-anode voltage. The ITC tester contains an array of inductors ("selectable inductor" in Fig. 2) that allows a ramp of in even steps. To gather a multitude of failure data points, was incremented by 500 mJ until the part passes at 3 J ; beyond this value, increments are reduced to 100 mJ to the range, where failure is expected. The waveforms in Figure 3 show a device failing at 4 J , the critical value at which the device can no longer dissipate the delivered from the inductor; a failed DUT measures an electric short from anode to cathode.

Fig. 3. Typical UIS waveforms of this study, showing expected failure in the range of 4 J .

Fig. 3. Typical UIS waveforms of this study, showing expected failure in the range of 4 J .

Fig. 4. UIS failure distribution of tested devices across five epiwafer vendors. Black dots represent a single failure; box plot shows quartile distributions for each vendor. Numerical values are given in Table 1. Excerpts of defect maps provided by each vendor are shown in Fig. 1.

Fig. 4. UIS failure distribution of tested devices across five epiwafer vendors. Black dots represent a single failure; box plot shows quartile distributions for each vendor. Numerical values are given in Table 1. Excerpts of defect maps provided by each vendor are shown in Fig. 1.

Table 1. Numerical values of failure energy, , in Joules, corresponding to the box plot of Fig. 4.

Vendor | Min | 10% | 25% | Med | 75% | 90% | Max
A | 0.5 | 3.4 | 3.7 | 3.8 | 4.0 | 4.1 | 4.2
B | 2.5 | 3.0 | 3.4 | 3.8 | 3.9 | 4.0 | 4.0
C | 0.5 | 1.0 | 2.0 | 3.0 | 3.5 | 3.7 | 3.9
D | 3.0 | 3.5 | 3.6 | 3.8 | 3.9 | 4.0 | 4.0
E | 2.0 | 3.3 | 3.6 | 3.7 | 3.8 | 3.9 | 4.1

Discussion

The original version of this paper is available on https://www.scientific.net/SSP.376.41.pdf

Observing Figure 4 and the numerical data of Table 1 leads one to speculate there is a material quality issue that brings the average failure energy for Vendor C well below that for the other four vendorsespecially if the one outlier data point for Vendor A is ignored. In any case, speculation is the best one can do when using non-standardized defect maps provided by vendors. For high volume manufacturing, additional characterization is required to identify the defect type and precise position on the wafer. Historically, ultraviolet photoluminescence (UVPL) analysis has proven to offer high resolution and detectability and has clearly documented significant progress in improving materials [16] but is not easily deployed into a high volume manufacturing environment.

Fig. 5. Left - On-state resistance vs percent of MOSFET active area with trapezoidal defects. Right - Defect data points, as reported by epiwafer supplier, overlaid onto a high-detectability UVPL image to highlight defects not reported by the vendor. Legend - Rectangle trapezoidal, Star large pit, Dashed circles defects not reported in the provided map.

Fig. 5. Left - On-state resistance vs percent of MOSFET active area with trapezoidal defects. Right - Defect data points, as reported by epiwafer supplier, overlaid onto a high-detectability UVPL image to highlight defects not reported by the vendor. Legend - Rectangle trapezoidal, Star large pit, Dashed circles defects not reported in the provided map.

Systematic studies where crystal defects are structurally identified followed by a rigorous analysis of short- and long-term electrical performance is necessary to establish quality standards and defect classifications to which all epiwafer vendors and device manufacturers can subscribe. Previous work by device manufacturers to correlate epiwafer defects with device outcomes have warranted changes in SiC defect classifications. One such example is the impact of the "trapezoidal" defect, also called a "bar stacking fault" or "diagonal." Trapezoidal defects were long considered to have little or no impact on SiC MOSFETs and were classified as "non-killer." Figure 5 tells a different story, however, as there is a linear relationship between the percent of MOSFET active area spanned by trapezoidal defects and the MOSFET's on-state resistance [17], a finding also reported in [18]. By overlaying industry-generated epi defect maps onto high-detectability UVPL images (Fig. 5, right), Microchip identified a correlation between trapezoidal densities and increased on-state resistance. These results demonstrate that epiwafer defect maps can be used to effectively screen devices that pose a performance risk despite passing wafer-level electrical testing.

Epiwafer quality issues are further compounded when comparing total useable area (TUA) across epiwafer vendors, as there is no common baseline used in determining TUA with data provided in defect maps (see Fig. 1). The only existing standard related to TUA determination is found in SEMI M92-0423 [19], which states that TUA is "determined by a method agreed upon between the supplier and the customer." This may be perceived as a negotiation between two parties rather than an industry standard intended to establish a minimum bar for SiC product quality. Looking at the data, Vendor A recognizes "3Triangle" and "Large-pit" defects as killer defects, and TUA is calculated by excluding any area containing them. For the remaining four epiwafer vendors, it is unknown which defect types are excluded from TUA; indeed, the same crystal defect may be called a different name. Finally, the precise position, shape, and size of defects in vendor-provided defect maps are inadequate for predicting wafer-level yield.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.376.41.pdf

While capabilities exist to identify SiC epiwafer crystal defects and correlate them to device performance and reliability, industry-wide material quality standards are needed to further the successful commercialization of SiC power devices. As an example, this work analyzes UIS performance of 1700 V SiC JBS diodes made on epiwafers from five different vendors. Nonstandardized defect maps offer incomplete information on the type of defect, precise location, size, or shape. This leaves device manufacturers with unknown root cause and no direction toward a solution. The establishment of material standards will allow device manufacturers to have greater control over performance and reliability; to ensure a level, competitive playing field among material suppliers; and to drive continuous improvement in epiwafer quality and cost, ultimately benefiting end users and the SiC market.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.41.pdf

M. Chaturvedi, Electrically Active Defects in SiC Power MOSFETs, Energies 2023, 16, 1771 (2023)

D. Baierhofer, Correlation of Extended Defects with Electrical Yield of SiC MOSFET, Defect and Diffusion Forum, Vol. 426, pp 11-16 (2023)

A. Castellazzi, UIS Failure Mechanism of SiC power MOSFETs, IEEE WiPDA (2016)

L. Lai, Impacts of Silicon Carbide Defects on Electrical Characteristics of SiC devices, JAP 137, 060701 (2025)

L. Liu, A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4 H -SiC Trench Metal-Oxide Semiconductor Field-Effect Transistor Structures, Micromachines 2024, 15, 1772 (2024)

S. Palanisamy, Avalanche Ruggedness of SiC MPS Diodes Under Repetitive Unclamped-Inductive-Switching Stress, EE Power Technical Article April 15, 2020 (2020)

A. Gendron-Hansen, 4H-SiC Junction Barrier Schottky Diodes and Power MOSFETs with High Repetitive UIS Ruggedness (2018)

T. Basler, Avalanche robustness of SiC MPS, PCIM Europe (2016)

A. Konstantinov, Silicon carbide schottky-barrier diode rectifiers with high avalanche robustness, PCIM Europe (2015)

C. Yen, Avalanche ruggedness and reverse-bias reliability of SiC MOSFET with integrated junction barrier controlled schottky rectifier, IEEE ISPSD (2018)

L. Yang, Characterization of high-voltage SiC MOSFETs under UIS avalanche stress, 7th IET International Conference on Power Electronics, Machines and Drives (2014)

A Gendron-Hansen, 4H-SiC 1200 V Junction barrier Schottky diodes with high avalanche ruggedness, Material Science Forum Vol. 924 (2018)

I. Ji, Highly rugged -SiC power MOSFET, ISPSD (2017)

K. Chinnaswamy, P. Khandelwal, M. Trivedi, and K. Shenai, "Unclamped inductive switching dynamics in lateral and vertical power DMOSFETs," IEEE Industry Applications Conference, 1085 (1999).

ITC55X00C Unclamped Inductive Switching Tester User Manual, Rev 7.2. Integrated Technology Corporation, Tempe, Arizona, 2022, pp. 64.

R. Stahlbush, N. Mahadik, Defects in 4H-SiC Epi Affecting Yield & Reliability, IRPS (2022).

H. Das, A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability Material Science Forum, ISSN: 1662-9752, Vol. 1062, pp 406-410 (2022).

S. El Hageali, H. Guthrey, J. Soto, Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability, JAP, Vol. 134, Issue 7 (2023).

Specification for 4H-SiC Homoepitaxial Wafer, SEMI M92-0423, April 2023; available on and

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 47-54

doi: 10.4028/p-KMZo3u

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-11-13

Revised:
2025-05-19

Accepted:
2025-05-19

Online:
2025-09-10

Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

R. Hattori*1,a, Y. Yao , and Y. Ishikawa

Ceramic Forum Co. Ltd., Japan

Japan Fine Ceramic Center, Japan

Mie Univ., Japan

ªhattori@ceramicforum.co.jp, byao@icsdf.mie-u.ac.jp, , yukari@jfcc.or.jp

Keywords: phase contrast microscope, polarization, synergy, dislocation, SiC, TSD, TED

Abstract

We introduce a polarization superimposed phase contrast microscope (PS-PCM) for widegap semiconductor wafers as a new analytical technique that enables non-destructive and threedimensional characterization of threading dislocations; TSDs and TEDs in SiC epilayers and substrates, such as discrimination each other or detection of their inclination in the depth direction.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

SiC power devices are establishing themselves as highly effective energy converters owing to their splendid material features. However, further improvements in the production yield and their reliability are required to achieve that. The major killer defects in the epitaxial layer for SiC device operation are carrots, triangle defects, downfalls, half-loop-arrays, and micropipes [1-3]. Although their origins and formation mechanisms have not yet been fully clarified, most of them are thought to be related to the combination or decomposition of BPDs and TSDs extended from the substrate into the epitaxial layer. It has been confirmed that screw dislocations with large Burgers vectors become hollow cores and form micropipes [4]; however, it is still challenging to identify the screw dislocations with Burgers vectors of small: or mixed with " a " component [5] and has not been sufficiently verified. Therefore, a more detailed TSD related dislocation inspection is required.

For dislocation inspection, X-ray white beam topography [6], KOH etching technology [7], and transmission electron microscopy (TEM) are generally applied as reliable inspection methods. However, they have limitations for application because of their operational expertise or sample breaking for inspection. Rapid and simple operation dislocation analytical methods for epitaxial growth or device process manufacturing are monochromatic beam X-ray topography or polarization observation, but they have limitations in terms of depth resolution or ability to identify dislocation types. We developed a phase contrast microscope (PCM) designated for wide-gap semiconductor wafers as a three-dimensional nondestructive inspection tool discriminating TSDs and TEDs in SiC crystals [8]. The phase contrast images of TSD and TED are distinguishable enough for automatic classification with image processing. However, the phase contrast contrasts of dislocations are very sensitive to the uniqueness of each dislocation for a more detailed characterization of the dislocations.

In this paper, we propose a new technique that enables the identification of detailed features of TSDs and TEDs in SiC epitaxial layer by polarization superimposing on PCM optics. The principle of the PCM method is quite different from that of the polarization method; however, adding the polarization effect on PCM gives a further function for the dislocation inspection as a synergy effect, which is entirely different from adding two images.

Phase Contrast Microscopy for Wide-gap Semiconductor Wafers

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

PCMs are generally called "biological microscopes", widely used in microbial research and biocell structural analysis. Frederik Zernike, a Dutch Nobel prize physicist, developed PCM in 1932, which allows the observation of the internal structure of cells of moving microbes alive. However, semiconductor engineers were not familiar with phase-contrast microscopes. The primary reason for this was that semiconductor wafers such as Si and GaAs do not transmit visible light, so reflection microscopes were the mainstream for optical observation, and transmission microscopes were not familiar. However, wide-gap semiconductors such as SiC and GaN transmit visible light, making it possible to apply phase-contrast microscopes.

Figure 1 Optical system of Phase Contrast Microscope (PCM) for widegap semiconductor crystals

Figure 1. Figure 1 Optical system of Phase Contrast Microscope (PCM) for widegap semiconductor crystals

Fig. 1 shows the schematic view of the PCM optics developed for semiconductor application, which implements an autofocus (AF) system on the transparent wafers, PC controlled stage covering up to wafer, synchronized z-axis control system of objectives and condensers for wafer depth profiling, and image processing to extract and identify dislocations.

Figure 2 PCM image and KOH etch pits of the same position of thick epilayers.

Figure 2. Figure 2 PCM image and KOH etch pits of the same position of thick epilayers.

Fig. 2 shows the (a) PCM image and (b) KOH etch pit photo of the same position of slow-grown hour epilayer. Red arrows and white arrows indicate TSD and TEDs, respectively, which are in complete agreement in (a) and (b). This confirmed that the phase contrast image indeed detected the threading dislocations in the SiC crystal.

Another essential feature of the PCM method is the non-destructive tracking of the depth profile of dislocations inside the crystal by synchronous up/down of the focal positions of both the objective and condenser systems within the crystal.

Figure 3 Non-destructive depth profiling of micropipes from top to back of SiC substrate with PCM. PCM images focused on (a) the surface, (b) 100 mm below the surface, (c) 200 mm below the surface, and (d) the backside surface, as indicated in (e) a cross-sectional schematic diagram of the depth profiling.

Figure 3. Figure 3 Non-destructive depth profiling of micropipes from top to back of SiC substrate with PCM. PCM images focused on (a) the surface, (b) 100 mm below the surface, (c) 200 mm below the surface, and (d) the backside surface, as indicated in (e) a cross-sectional schematic diagram of the depth profiling.

Fig. 3 shows the depth profiling of the micropipes in the SiC substrate from (a) the top surface to (d) the backside, as described in (e) the cross-sectional view. We confirmed with SEM that there were actual holes on the top and backside surfaces that correspond to those MPs and that this kind of CPM contrasts should be MPs. Surface observation alone cannot provide conclusive evidence that this kind of defects are MPs, but depth profiling with CPM makes it possible to easily and non-destructively confirm which is MP [9-11].

Figure 4 Changes in TSD contrasts of PCM in response to the epitaxial growth rate.

Figure 4. Figure 4 Changes in TSD contrasts of PCM in response to the epitaxial growth rate.

However, it was confirmed that the PCM contrast of dislocations in the SiC epitaxial layer changed in response to the epitaxial growth rate, as shown in Fig. 4. The TSDs extend almost perpendicular to the growth surface with up to , but at faster growth rate than , they appear to be pulled in the down-step direction.

On the step-flow growth process, the bonds in the epi. growth reactor of each atomic step on the inclined surface repeatedly bonds laterally on each atomic terrace and overlaps, as a conclusion, which results in vertical growth. Higher growth experiences faster lateral stacking of bonds on the atomic terrace. We think such a lateral stacking process may affect TSD contrasts of the phase
contrast microscope (PCM). Some parts of this result are qualitatively consistent with the contents of JEITA EDR-4712/200, the Japanese standard on the optical inspection of SiC defects.

Faster-growth epitaxy is becoming widespread in recent years, for higher throughput in singlewafer growth with uniformity of the epitaxial layer within the wafer surface. To investigate the reality of the horizontal segment containing TSD in this fast-grown epilayer, depth profiling was performed at two locations.

Figure 5 PCM depth profiling of continuity of TSD in fast-grown epitaxial from TSD in the substrate of area-A and B (a) Focused on the epilayer surface, (b) below the surface (epi./sub. interface), and (c) below the surface (inside of substrate).

Figure 5. Figure 5 PCM depth profiling of continuity of TSD in fast-grown epitaxial from TSD in the substrate of area-A and B (a) Focused on the epilayer surface, (b) below the surface (epi./sub. interface), and (c) below the surface (inside of substrate).

Fig. 5 shows the depth-profiling of area-A and area-B of fast-grown ( ) -thick epilayer; (a) focused on epilayer surface, (b) below the surface (epi./sub. Interface), and (c) below the surface (inside of the substrate). In area A, one of two segments appearing on the surface annihilates in the substrate, which we think may be caused by some surface roughness at the early stage of epitaxy, and the other one is connected with TSD contrast in the substrate. In area B, four segments are connected to the inclined dislocations in the substrate.

As shown in Fig. 6, to investigate the dislocation connected below the segment, the segment site was sliced in the [11-20] direction, and the cross-section was observed TEM in [1-100] direction and two beam excitation conditions of and . Consequently, the dislocation was the complex dislocation containing burgers vector of c component and a component and inclined from the normal of epilayer surface, as described in Fig.7. Then, the direction of the inclination seems to vary for each dislocation.

Polarization Superimposed Phase Contrast Microscopy

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

Actual dislocations in epilayers and substrates take various forms, such as inclination, decomposition to partial dislocations, or mixing each other, and should appear in various optical features. To decipher the detailed characteristics of dislocations, we tried to superimpose the polarization effect on the PCM. Fig. 8 shows the optics of polarization superimposed PCM (PS-PCM). There are three options for polarizers: linear polarizers, right-handed circular polarizers, and lefthanded circular polarizers. As shown in the inset of Fig.8, the major setting angles of the polarizer and analyzer have many setting angles such as the [11-20] and [1-100] directions and the three a-axis of SiC crystal: , and .

Figure 8 Polarization superimposed PCM

Figure 6. Figure 8 Polarization superimposed PCM

Since the irradiation from the PCM condenser is condensing through a ring slit, the incident wavefront is not parallel to the wafer, and the contrast seen in the transmitted polarization image hardly appears.

Fig. 9 shows the PS-PCM images at the same position on the thick epilayer under various polarization conditions with (a) non-polarization as the reference, (b) cross-polarization with a polarizer in [1-100] and analyzer in [11-20], (c) cross-polarization with a polarizer in [11-20] and analyzer in [1-100], (d) right-handed circular polarizer and analyzer in a1, (e) right-handed circular polarizer and analyzer in a2, and (f) right-handed circular polarizer and analyzer in a3, where (a)~(f) with objective lens 10 x of the depth resolution of show selectively dislocations in the epilayer. (g) right-handed circular polarizer and analyzer in , (h) right-handed circular polarizer and analyzer in 2, and (i) right-handed circular polarizer and analyzer in 3, where (g) (i) with objective lens 4 x of the depth resolution of show dislocations both in the epilayer and in the substrate below the interface.

Yellow arrow contrast is TSD confirmed with KOH etch pit, and other contrasts may be TEDs. TED shows strong analyzer orientation dependence. Although further research is required to confirm whether it is related to the orientation of the Burgers vector of the dislocation, we think that the circularly polarized light irradiated on the dislocation is transmitted through it and polarized in the analyzer direction. By investigating the relationship between the direction of TED displacement and the transmitted light, it may be possible to estimate the direction of TED displacement from the dislocation contrast of PS-PCM.

The polarization direction dependence of dislocation phase contrast has been confirmed in various samples, but their interpretation has not yet been taken. Further investigation is required.

Figure 9 Polarization superimposed PCM images at the same position on the thick epilayer under various polarization conditions with (a) non-polarization as the reference.

Figure 7. Figure 9 Polarization superimposed PCM images at the same position on the thick epilayer under various polarization conditions with (a) non-polarization as the reference.

Discussion

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It is necessary to discuss how PCM or PS-PCM detects dislocations. Fig. 12 shows the cylindrical tube model for simulating elastic distortion around the dislocation core of TSD and TED [12]. In the model of elastic strain caused by dislocations, the stress diverges to infinity at the center of the dislocation core, so the region with a radius r 0 of about five times the Burgers vector from the dislocation core is considered hollow and excluded from the calculation. The birefringence image that appears in polarized light observation is due to the modulation of the dielectric function due to this elastic stress, and is reproduced by analyzing the crystal strain due to elastic stress.

Figure 10 TED and TED lattice image (left) and cylindrical tube model for elastic stress analysis (right)

Figure 8. Figure 10 TED and TED lattice image (left) and cylindrical tube model for elastic stress analysis (right)

On the other hand, the dislocation contrast in the PCM image is thought to be caused by the refractive index modulation in the inelastic stress region inside . However, the size of in TSD and TED is on the order of a few nm , and it is unclear whether it is effective for visible light optical systems. In addition, the analyzing-angle( ) dependence of dislocation appearance, as shown in Fig. 9 for circular polarized light irradiation, was not observed by birefringence images without the condenser for PCM. The synergistic effect of polarization on PCM may be the appearance of the uniqueness of each dislocation core's optical properties, rather than the crystal distortion effects.

Further research, such as analyzing the polarization characteristics of light passing near the dislocation core, may enable us to decipher the individual characteristics of the dislocation.

Conclusion

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

We developed a polarization superimposed phase contrast microscope (PS-PCM) for wide-gap semiconductor wafers and demonstrated that PS-PCM is sensitive to identifying the detailed uniqueness of dislocations in SiC crystals.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

This study was partially supported by the METI Monozukuri R&D Support Grant Program for SMEs Grant Number JPJ005698.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.47.pdf

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D. Hull and D.J. Bacon, chapter 4, Introduction to Dislocation, Elsevier

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 55-62

doi: 10.4028/p-8cyEua

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-02-17

Accepted:
2025-02-20

Online:
2025-09-10

High Temperature Evolution of Thin Films Confined between Two SiC Substrates

The original version of this paper is available on https://www.scientific.net/SSP.376.55.pdf

Maëlle Le Cunff , François Rieutord , Didier Landru , Oleg Kononchuk , Nikolay Cherkashin

Innovation, SOITEC, Parc Technologique des Fontaines, Chemin des Franques, 38190 Bernin, France

CEMES-CNRS and Université de Toulouse, 29 Rue Jeanne Marvig, BP 94347, 31055 Toulouse Cedex 4, France

maelle.le-cunff@soitec.com, francois.rieutord@soitec.com, didier.landru@soitec.com, oleg.kononchuk@soitec.com,

Keywords: SiC bonding, dewetting, confinement, surface reaction, interface reconstruction.

Abstract

We investigate the possibility to use silicon, titanium and tungsten as bonding materials between a SiC substrate and a SiC layer, a novel substrate for application in high-power electronics. By using transmission electron microscopy, scanning transmission electron microscopy and X-ray scattering techniques, we address the high temperature-induced phase and morphology changes in thin layers composed of these materials and at their interfaces with SiC. For all three materials, we show that the homogenous continuous film created after low temperature deposition transforms into a discontinuous structure following high temperature annealing. All layer's structures tend to reach an epitaxial relation with the SiC substrates. In contrast to Si layer which preserves its composition, both Ti and W layers are transformed into new phases which were identified. We evidence that these peculiar structural and compositional changes in the layers, which were studied as a function of annealing temperature and time, are related to mechanisms of SiC dissolution and transport of C, atoms at the interface. Potential chemical and structural reactions during interface reconstructions are discussed in relation to the experimental findings.

Introduction

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Silicon carbide is extensively utilized in power electronics due to its wide band gap and excellent thermal conductivity [1]. The process development of thin SiC layer assembly on SiC substrates of varying quality or doping levels is extremely important for electronic device applications. Since direct bonding of SiC to SiC presents challenges, an intermediate layer of conductive material can serve as an adhesive to allow their strong bonding. The fabrication of power devices at elevated temperatures necessitates a study of how bonding layers develop under these conditions. Although there is a wealth of research on the emergence of unconfined thin-film morphology [2] [3] [4], the behavior of confined thin films has received less attention. This study seeks to elucidate new mechanisms at play during the annealing of such structures.

Despite the well-documented success of bonding [5] [6], it doesn't satisfy the precise specifications for a conductive interface between the stacked substrates. Alternative conductive materials like silicon, titanium, and tungsten are being considered as viable options for bonding. We examined the structural and compositional changes of ultra-thin layers of amorphous , and W sandwiched between single crystal SiC layer and SiC substrate during hightemperature annealing. We focused on examining how isothermal annealing, whether exceeding or not the melting point of different materials, affects interface morphologies and the formation of new crystallinephases.

Experiments

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Atomic diffusion bonding (ADB) at room temperature is the method used to create bonded structures [7] [8]. Generally, this entails depositing thin films onto the two wafers using sputtering, followed by their bonding in vacuum. Two (0001) 4H-SiC single crystal wafers with a offcut were used in this work, each with distinct C - and Si-terminated surfaces. The C -face SiC substrate was implanted with ions. Thin films of amorphous Si , Ti or W were deposited on both substrates. Therefore, the thickness of the sandwiched thin film is doubled. Following ADB, the application of the SmartCut process [9] resulted in the transfer of a few hundred nanometers thick SiC layer on the Si-face substrate. During this initial procedure, the sandwiched structure was subjected to annealing at temperatures ranging from to . Subsequently, the film/SiC assembly substrates were sectioned into pieces and subjected to a second round of annealing at various temperatures, both above and below the corresponding melting temperatures of the bonding materials.

Scanning electron microscopy (SEM) was employed to characterize the interface morphology after the transferred SiC layers were removed via cleavage. Top-view SEM images were then analyzed using ImageJ software [10]. Atomic force microscopy (AFM) imaging was utilized for the estimation of the surface roughness of C-face and Si-face terminated substrates before ADB and after annealing, following the removal of the top layer. Structural studies of the interfaces and the materials were realized by cross-sectional transmission electron microscopy (TEM) by using the SACTEM-Toulouse (Tecnai-FEI) and Jeol2010 microscopes operating at 200 kV . High-resolution high angle annular dark-field scanning transmission electron microscopy (HR-HAADF-STEM) was applied for visualizing different crystal phases. The images were acquired at probe corrected JEOL JEM ARM 200F operating at 200 kV . Abstrain procedure [11] was employed to correct HR-HAADF-STEM images for distortions and calibration errors and strain measurements. Thin TEM lamellas were produced using a standard lift-out procedure on a FEI Helios Nanolab 600i focused ion beam (FIB). X-Ray diffraction (XRD) measurements were conducted at the BM32 beamline of the European Synchrotron Radiation Facility (Grenoble, FRANCE) offering valuable insights on the crystalline texture and strain in silicon and SiC layers.

Results

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Silicon Bonding: Annealing below Si Melting Point. The thick amorphous silicon films were deposited and bonded at room temperature [12]. Following the initial annealing step at temperatures ranging from to required for the SmartCut process, the Si films transitioned into a polycrystalline state. Top-view SEM images (Fig. 1) acquired after removing the top layer through cleavage, indicate the formation of pits at the interface. They have a density of . TEM cross-sectional images show that pits are exclusively present at the upper interface between Si and the transferred C -face SiC layer. These findings imply that the nucleation of pits may be influenced by the properties of the SiC surfaces, which differ in roughness and defectiveness.

SEM images show the fracturing of the Si films and the formation of voids (bright contrast spots) following the second anneal at a higher temperature (below the Si melting point). The voids' size enlarges with annealing temperature and their density remains approximately constant. Only of the pre-existing pits transform into voids, the others are healed. All these results point towards a dewetting of Si from the SiC surfaces.

Fig. 1. -tilted SEM images and bright-field cross-sectional TEM images of the interface in a 20 nm -thick Si film annealed at and .

Fig. 1. -tilted SEM images and bright-field cross-sectional TEM images of the interface in a 20 nm -thick Si film annealed at and .

At any temperature, it is observed that the silicon layers are in a polycrystalline state. However, the grains size increases with annealing temperature, and their structure tends to align epitaxially with that of the SiC substrates. Both X-ray diffraction (Fig. 2(a)) and TEM experiments (Fig. 2(b) and 2(c)) reveal that predominantly and Si planes align with SiC planes.

Fig. 2. (a) scan aligned on (0004) SiC planes for a 20 nm -thick Si film annealed at and ; (b) Bright-field cross-sectional ( TEM images and diffraction patterns after annealing ; (c) after annealing .

Fig. 2. (a) scan aligned on (0004) SiC planes for a 20 nm -thick Si film annealed at and ; (b) Bright-field cross-sectional ( TEM images and diffraction patterns after annealing ; (c) after annealing .

TEM measurements and X-ray reflectivity (XRR) data (not shown) demonstrate that the Si layer thickness expands from 20 nm to 30 nm following annealing at . An increase in Si film thickness correlates with void growth. The volume per surface fraction of voids corresponds to the amount of Si contributing to the increase in Si film thickness, thus indicating Si mass conservation. More details on the evolution of Si films morphology can be found in our work [13].

Silicon Bonding: Annealing Above Si Melting Point. Beyond the Si melting point, the interfaces lose their flatness (Fig. 3). Step bunching with high steps and large terraces manifests on both SiC inner surfaces. In contrast, the surface of the transferred SiC layer evidences shallower steps and terraces (Fig. 3(a), see the part not removed by cleavage). At the interface, liquid silicon has undergone dewetting, resulting in the formation of large Si filaments at the borders of steps. After annealing for 30 min , TEM images indicate the entrapment of silicon clusters between the steps of the two internal surfaces, surrounded by voids (Fig. 3(b)). All those results suggest that liquid silicon facilitates step bunching on internal SiC surfaces.

Fig. 3. (a) -tilted SEM image after annealing ; (b) Bright-field cross-sectional TEM image after annealing - 30 min ; (c) Bright-field cross-sectional TEM image after annealing .

Fig. 3. (a) -tilted SEM image after annealing ; (b) Bright-field cross-sectional TEM image after annealing - 30 min ; (c) Bright-field cross-sectional TEM image after annealing .

As the annealing temperature increases, we observe a closure of the interface through direct bonding of the two SiC surfaces starting from the contact points, while the step height remains constant (Fig. 3(c)). The percentage of contacts rises, leading to enhanced closure of the interface. From TEM images, the percentage of contacts has been estimated to be and for annealing temperatures of and , respectively. These findings suggest that the evolution of the interface is a thermally activated process facilitated by liquid silicon trapped at the interface.

Tungsten Bonding: Annealing below W Melting Point. In this part, structures bonded with thin 2 nm-thick tungsten layers are studied. The samples were annealed at a temperature of around . Figure 4(a) shows the SEM images of the upper W film surface once the top layer has been removed by cleavage.

Fig. 4. (a) -tilted SEM image of the interface once the top substrate has been removed by cleavage; (b) Bright-field cross-sectional TEM image of the interface; (c) Plan-view STEM image.

Fig. 4. (a) -tilted SEM image of the interface once the top substrate has been removed by cleavage; (b) Bright-field cross-sectional TEM image of the interface; (c) Plan-view STEM image.

We can clearly see the transformation of the continuous film into isolated nodules (see dark spots). The formation of isolated inclusions at the interface is evidenced both by bright-field crosssectional (1-100) TEM (Fig. 4(b)) and STEM plan view imaging (Fig. 4(c)). The nodules cover around of the surface and the rest is formed of contacts. The cross-sectional TEM image (Fig. 4(b)) reveals the presence of small steps at both SiC inner surfaces around the W-containing nodules. The surfaces are aligned with the (0001) SiC planes. The W-containing nodules have an average diameter of 55 nm , a thickness of 14 nm and a density of .

To conclude, as for Si thin layers, the homogeneous and continuous thin film after deposition transforms into a discontinuous structure after high temperature annealing. A strong dewetting of tungsten from SiC surfaces driven by the interfacial energies seems to occur and the full breaking of the tungsten film suggests very high interface energy between SiC and W . We also evidenced a reconstruction of internal surfaces by step bunching, associated with dissolution and transport of Si and C atoms.

Fig. 5. (a), (b) Cross-sectional ( ) TEM images of the nodule formed after annealing at for 30 min: (a) dark-field image taken with ; (b) bright-field image taken with ; (c) XRD scan aligned on (0004) SiC planes.

Fig. 5. (a), (b) Cross-sectional ( ) TEM images of the nodule formed after annealing at for 30 min: (a) dark-field image taken with ; (b) bright-field image taken with ; (c) XRD scan aligned on (0004) SiC planes.

Figure 5(a) and (b) show the cross-sectional TEM images of the nodules taken in dark-field two-beam conditions with (a) and (b). One can clearly see the appearance of one-fringe family pattern over the nodule with the different periods and inclinations. By measuring the fringe periodicity and orientation for at least two different , one can get the corresponding values of of the unknown structure and calculate the angle between corresponding diffraction vectors [14].

For , the average fringe period is measured of and the average angle of the fringes with respect to is . From these values, we get . For , the average fringe period is measured of and the average angle of that provides . The angle between and is calculated of . These crystallographic planes are found to be almost collinear with that of the structure indicating likely a hexagonal structure in the nodule. This study reveals the formation of the hexagonal phase nodules with relaxed structure as the Bravais lattice [15] gives the following values: and . X-ray diffraction measurements (Fig. 5(c)) confirm the formation of the phase in the nodules with the diffraction of the (0002) planes at . Those results indicate carbon dissolution at SiC surfaces and reaction with tungsten. The dissolution of SiC should release the same amount of Si. Thermodynamically, we should observe . However, detecting such a small quantity is challenging, as it may be dispersed in the form of thin shells or isolated nodules with a weak density.

Titanium Bonding. In this last part, the structures bonded with a 10 nm-thick titanium layers are studied. The samples were annealed at temperatures below Ti melting point and above .

Titanium Bonding: Annealing below Ti Melting Point. For annealing temperatures below the Ti melting point of , the intermediate layers preserve the form of a quasi-homogeneous layer. SEM images (Fig. 6(a)) show two different contrasts corresponding to the homogeneous layer (dark contrast) and trapped nodules (bright contrast). Those results suggest no dewetting of titanium from SiC surfaces but compositional transformations. Bright field TEM images (Fig. 6(b)) reveal a significant reconstruction of SiC internal surfaces by step bunching. The height of the steps varies between to 20 nm and the steps height is higher next to a nodule. TEM diffraction patterns (Fig. 6(c) and 6(d)) evidenced two distinct crystalline structures between the thin layer (zone (1)) and the nodules (zone (2)).

Fig. 6. (a) -tilted SEM image once the top layer has been removed by cleavage; (b) Bright-field cross-sectional image after annealing ; (c) Diffraction pattern of the thin layer; (d) Diffraction pattern of the nodules.

Fig. 6. (a) -tilted SEM image once the top layer has been removed by cleavage; (b) Bright-field cross-sectional image after annealing ; (c) Diffraction pattern of the thin layer; (d) Diffraction pattern of the nodules.

For both class of objects, an epitaxial relation with SiC substrates is satisfied. From the measured interplanar distances: in the nodule and in the in layer, the presence of pure titanium is evicted, new crystalline phases are created.

Titanium Bonding: Annealing Above Ti Melting Point. For a temperature above the Ti melting point ( ), the same interface morphology is observed with a more pronounced reconstruction of the internal SiC surfaces. Steps and terraces can be seen on top of the Ticontaining layer imaged by SEM once the transferred SiC film has been removed by cleavage (Fig. 7(a)) and on cross-sectional TEM images (Fig. 7(b)).

Fig. 7. (a) -tilted SEM image after annealing - 30 min ; (b) Bright-field cross-sectional TEM image; (c) HAADF STEM image of the thin layer; (d) Interplanar distances mapping along (0004) SiC planes; (e) Interplanar distances mapping along SiC planes.

Fig. 7. (a) -tilted SEM image after annealing - 30 min ; (b) Bright-field cross-sectional TEM image; (c) HAADF STEM image of the thin layer; (d) Interplanar distances mapping along (0004) SiC planes; (e) Interplanar distances mapping along SiC planes.

From TEM diffraction patterns (not shown), the same crystallographic phases and orientations are identified. Fig. 7(c) shows the high resolution HAADF STEM image of the thin layer, which was obtained from a stack of images where each image was corrected for distortions and calibration errors using the AbStrain procedure [11]. The eventual image of the thin layer shows a striking periodicity in the contrast of the atomic rows at the bottom of the intermediate layer. Those observations direct us towards MAX phases [16]. Thermodynamics indicates that is a stable MAX phase at these temperatures [17]. Interplanar distances values (Fig. 7(d) and (e)) together with EDX measurements (not shown) confirm such a hypothesis. We found and for the crystalline planes parallel to the ( 0001 ) SiC planes and ( ) SiC, in good accordance with Bravais lattice [18]. Above, the cubic TiC phase [19] is identified with
and and is confirmed with EDX measurements (not shown) that indicate a loss of silicon. Thick nodules are found rich in titanium and silicon only in good accordance with the diffusion of silicon at the interface. We measured twice more silicon than titanium and from the Ti-Si-C phase diagram [17], we can suggest the formation of TiSi2 in the nodules.

Discussions and Conclusions

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For all the three materials, we evidence specific structural and compositional transformations in the layers as a function of annealing temperature. We demonstrated that a homogeneous and continuous film created after deposition transforms into a discontinuous structure following high temperature annealing. Si and W layers dewet from the SiC internal surfaces by creation of voids or isolated nodules for temperatures below the melting point. On the contrary, Ti layers on SiC surfaces exhibit total wetting. Those results indicate the differences in the interfacial energies between Si , W, Ti and SiC. High interfacial energy values for and W/SiC favor dewetting.

In contrast to Si layers, both Ti and W layers react with SiC to form carbide or silicide phases which were identified. Interfacial chemical reactions can be at work below the melting point temperatures by dissolution of SiC internal surfaces. All the structures tend to reach an epitaxial relation with the SiC substrates. Si layers remain polycrystalline with some epitaxially oriented crystallites whereas and Ti :Si:C hexagonal alloys have a single crystal structure. Last, for the three materials, we show a strong interface evolution of SiC internal surfaces by step bunching and creation of contacts for tungsten and silicon bonding.

In conclusion, wafer-to-wafer bonding was successfully achieved with all the three interface materials. The evolutions and morphologies obtained are highly dependent on material properties such as interfacial energy with SiC, melting point and diffusivity at high temperature. The selection of a bonding material will therefore depend on the intended application and the interface properties required.

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The original version of this paper is available on https://www.scientific.net/SSP.376.55.pdf

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Z. Zhang, X. Duan, D. Jia, Y. Zhou and S. v. d. Zwaag, On the formation mechanisms and properties of MAX phases: A review, Journal of the European Ceramic Society, 41(7), (2021) 3851-3878.

D. Bandyopadhyay, The Ti-Si-C system (Titanium-Silicon-Carbon), Journal of Phase Equilibria and Diffusion, 25( 5), (2004) 415-420.

C. Rawn, E. Payzant, C. Hubbard, M. Barsoum and T. El-Raghy, Structure of Ti3SiC2, Materials Science Forum, 321, (2000) 889-892.

K. Nakamura and M. Yashima, Crystal structure of ( NaCl)-type transition metal monocarbides , a neutron powder diffraction study, Materials Science and Engineering B, 148(1), (2008) 69-72.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 63-69

doi: 10.4028/p-N8t06u

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Revised:
2025-08-08

Accepted:
2025-08-09

Online:
2025-09-10

Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

The original version of this paper is available on https://www.scientific.net/SSP.376.63.pdf

Firas Faisal , Nils Steller , Robin Karhu , Birgit Kallinger , Gennadi Polisski , Marshall Wilson , Alexandre Savtchouk , Liliana Gutierrez , Carlos Almeida , Dmitriy Marinskiy , Jacek Lagowski

Nexperia, Stresemannallee 101, 22529 Hamburg, Germany

Fraunhofer IISB, Department Materials, Schottkystraße 10, 91058 Erlangen, Germany

Semilab Germany GmbH, Coschützer Str. 70, 01705 Freital, Germany

Semilab SDI, 12415 Telecom Dr., Tampa, FL 33637, USA

marshall.wilson@semilabsdi.com, sasha.savtchouk@semilabsdi.com, liliana.gutierrez@semilabsdi.com, dmitriy.marinskiy@semilabsdi.com, kjacek.lagowski@semilabsdi.com

Keywords: SiC, epi, defect, non-contact, CnCV, EOL device, QUAD.

Abstract

In this work we present the results of a comparison between the non-contact corona-based QUAD (Quality, Uniformity and Defects) technique for inline mapping of electrically active defects in SiC epi and final wafer level electrical device data on merged PiN Schottky diodes. A new defect analysis method for the QUAD mapping is introduced that involves the creation of a die yield bin map using the in-die values of depletion voltage that facilitates the comparison to the wafer level final electrical device data. Excellent correlation of the QUAD wafer bin map results to the final wafer level electrical device data was observed, illustrating that QUAD mapping of defects in SiC epi can provide a powerful and convenient inline complement to UVPL measurements for determining which defects are electrically active and will impact device performance.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.63.pdf

There is a strong need in the rapidly growing SiC epi industry for detection of defects and corresponding device yield diagnostics. Optical and UVPL mapping are currently used for inline defect detection however it can be difficult to determine with these techniques which defects will be electrically active and actually detrimental to devices. To address this need Semilab SDI introduced the Quality, Uniformity, and Defect mapping (QUAD) mode in their CnCV (Corona noncontact Capacitance-Voltage) line of tools. In the QUAD technique, the surface voltage is mapped after corona charging the whole wafer surface into deep depletion. Electrically active defects are detected as spots or clustered regions compared with the area surrounding the defect. QUAD demonstrated the electrical activity of defects such as triangular, downfall and carrot type defects and the QUAD detected defects were then compared with UVPL measurements [1]. A considerable fraction of the UVPL defects were found to be not electrically active and thus the QUAD detected electrically active defects provide a powerful compliment to UVPL and optical mapping measurements [2].

To facilitate comparison to final electrical device data, a new QUAD defect analysis is introduced in this work. It converts the map into a die grid of user selected size and creates a die bin map using the in-die values of depletion voltage. In such a parametric analysis, the die will be considered failed if the depletion voltage falls below or the reverse bias leakage current is above a certain defined threshold value. This provides an analogy to die failures in final electrical tests on Schottky diodes when the breakdown (BD) voltage falls below or if the reverse bias leakage ( ) is above a defined threshold. In this way the QUAD wafer bin map results can be directly compared to final electrical device test results. The goal of the approach is to use QUAD as an early, after epi growth indication of electrical parameter-based die yield.

Experimental

The original version of this paper is available on https://www.scientific.net/SSP.376.63.pdf

The QUAD technique is a full wafer defect mapping mode in the CnCV metrology which is an adaptation of the corona-Kelvin noncontact electrical metrology extensively used in Si IC fabrication [3]. A description of the principles, apparatus and applications for wide bandgap semiconductors, including SiC, is given in a 2017 CnCV review paper [4]. The initial inline QUAD measurements were performed on n-type epitaxial on substrates from two different vendors. Macro and micro scale QUAD measurements were also made on those same samples after wafer level final Merged PiN Schottky diodes were fabricated.

The CnCV apparatus used in this work included whole wafer wire type corona charging for QUAD mapping. The negative corona charging used involves the deposition of negative ( ) ions to bias the n-type SiC epi samples into depletion [3].

The Kelvin probe used in the QUAD mapping measures the contact potential difference, , between the wafer and the vibrating reference electrode [4]. A probe pre-calibration is used to subtract the contribution due to the electrode work function. After such a correction, the is referred to as the surface voltage, , and in the case of measurement on bare SiC epi this measured surface voltage is equivalent to the depletion voltage. For macro scale QUAD mapping a 2 mm diameter Kelvin probe was used. Whole wafer mapping was performed in about 8 min for a 150 mm SiC wafer.

For the micro scale QUAD (mQUAD) maps used to examine depletion voltage values within individual device dies, a 8 mm diameter Kelvin Force Microscopy (KFM) probe was used. Further details regarding mQUAD measurements using KFM are described in references [5,6].

Electrical wafer level test data of breakdown voltage and reverse bias leakage were measured on Merged PiN Schottky diodes fabricated on the same SiC epi wafers initially measured with full wafer QUAD mapping. Ultraviolet photoluminescence (UVPL) results presented in this work were measured with a Lasertec SICA 88 tool.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.376.63.pdf

As an illustration of this new QUAD die bin map analysis, we present two examples of epi grown in the same reactor run on 150 mm substrates from two different vendors giving different device yield. QUAD map results after epi growth are compared to electrical wafer level test data of breakdown voltage and leakage on Merged PiN Schottky diodes. In Fig 1a and 1 b , the initial QUAD defect maps on the as grown SiC epi give a quick overall indication of defective regions on the Vendor A and B SiC epi samples. A smaller number of defective regions (low depletion voltage in red) are seen for the Vendor A sample while the Vendor B sample shows a large defective area covering most of the center of the sample. In both cases, there are some discrete defect locations that are detected by the original QUAD analysis based on contrast, however there are also larger clustered defect regions (red) near the wafer edge with defects not adequately resolved. The new QUAD die bin maps with a die size of the same surface voltage maps are given in Fig. 2a and 2b together with final electrical device results. The new analysis not only identifies the localized defects as electrically active defective dies but the clustered regions near the wafer edge for both samples are also identified as defective dies. In Fig. 2a and 2b, overlay die bin maps are shown of both QUAD failed defective dies (blue squares) identified by a depletion voltage threshold and wafer level test failed defective dies (open triangles) identified by falling below a BD voltage threshold or if reverse bias leakage is above a defined threshold. In each case there are regions of strong spatial correlation between the QUAD failed dies and the electrical device failed dies. This indicates the usefulness of the QUAD die bin map analysis in prognostics of device failures early in the process flow. One may also point out the presence of a certain number of device failed dies not observed in QUAD. Such dies may be indicative of process induced (or enhanced) defects not present in the as grown epi. UVPL defect maps were also measured on these samples in the present study in order to address correlation to the QUAD and electrical device failed die bin maps.

Fig. 1a. Vendor A initial QUAD map on the bare SiC epi showing localized defective regions with low depletion voltage along with larger clustered defective regions of low depletion voltage near the wafer edge.

Fig. 1. a. Vendor A initial QUAD map on the bare SiC epi showing localized defective regions with low depletion voltage along with larger clustered defective regions of low depletion voltage near the wafer edge.

Fig. 1b. Vendor B initial QUAD map on the bare SiC epi showing a high density of defective regions with low depletion voltage in the center and edge regions of the wafer.

Fig. 1. b. Vendor B initial QUAD map on the bare SiC epi showing a high density of defective regions with low depletion voltage in the center and edge regions of the wafer.

Fig. 2a. An overlay of the Vendor A initial QUAD failed die and the wafer level test device failed die bin maps based on a die size of .

Fig. 2. a. An overlay of the Vendor A initial QUAD failed die and the wafer level test device failed die bin maps based on a die size of .

Fig. 2b. An overlay of the Vendor B initial QUAD failed die and the wafer level test device failed die bin maps based on a die size of .

Fig. 2. b. An overlay of the Vendor B initial QUAD failed die and the wafer level test device failed die bin maps based on a die size of .

The initial Vendor A QUAD map in Fig. 2a gives a QUAD die yield of while the final electrical device die bin map based on breakdown voltage and reverse bias leakage thresholds gives a die yield of . The Vendor B QUAD map in Fig. 2b gives a QUAD die yield of and the final electrical device die bin map based on breakdown voltage and leakage thresholds gives an electrical device die yield of . Additional failed dies in the final electrical device results lowering the die yield can be attributed to process induced defects during the fabrication of the merged PiN Schottky diodes.

After the wafer level fabrication of the merged PiN Schottky diode devices, QUAD mapping was performed again on the samples. This is possible because the individual diodes are electrically isolated and the deposited corona charge will distribute across the metalized surface of each individual diode. This allows for a very interesting analysis of the evolution of process induced defects during the diode fabrication process. The Vendor A QUAD map after the device fabrication is shown in Fig. 3a. The QUAD map is converted to a failed die bin map and once again compared to the electrical test failed die bin map in Fig. 3b. Additional failed dies in the QUAD bin map now appear (shown as red squares) and correlate well with failed electrical test dies that were not detected in the initial QUAD map on the as grown SiC epi. These additional failed dies are most likely due to process induced defects enhanced or created during the device fabrication process.

For the Vendor A sample, macro QUAD mapping identified 194 out of 205 defective dies, giving a capture rate of . Future work will employ UVPL and optical imaging to analyze the nature of the defects contributing to die failures and to investigate the small fraction of failed dies undetected by QUAD. Potential factors include the need for further optimization of QUAD depletion voltage threshold criteria and depletion region probing depth. Refinements of these factors will be explored in a subsequent study.

Fig. 3b. An overlay of the test device failed die bin map and the Vendor A QUAD failed die bin map after wafer level device fabrication showing additional QUAD failed dies due to process induced defects as red squares.

Fig. 3. b. An overlay of the test device failed die bin map and the Vendor A QUAD failed die bin map after wafer level device fabrication showing additional QUAD failed dies due to process induced defects as red squares.

The isolated diodes on the final device wafer also allow for another very compelling investigation of the in-die depletion voltage retained on individual diodes using micro-scale QUAD (mQUAD) mapping with a Kelvin Force Microscopy (KFM) probe. With the mQUAD mapping the depletion voltage retained on each individual diode can be resolved. This allows for a unique and powerful analysis of the QUAD failed dies directly compared to the electrical test failed dies on a die by die basis. Such an example of this analysis is shown in Fig. 4 for the Vendor B sample. A full wafer macro QUAD failed die bin map after wafer level device fabrication along with the final electrical test failed die bin map is shown on the left hand side of Fig 4 . As an example of mQUAD mapping,
a region in the center of the wafer was mapped with a KFM probe after corona charging, shown in the upper right corner of Fig. 4. Each individual QUAD failed die, based on a retained depletion voltage threshold of -20 V , can then be compared to the electrical test failed dies, shown in the bottom right corner of Fig. 4. In this region 145 of the 154 electrical test failed dies were detected by the mQUAD mapping giving a capture rate in this region. Considering the promising nature of these results, future studies will aim to collect more comprehensive statistics of the mQUAD measurements across a larger number of wafers. mQUAD mapping on the wafer level merged PiN diode samples also opens the door to investigation of the electrical nature of both failed and good individual diodes by analyzing high resolution voltage distributions across the diodes in addition to depletion voltage decay transients that can help elucidate the relative electrical activity of particular defects such as triangular, stacking faults, etc. that result in a failed die.

Fig. 4. An overlay of the test device failed die bin map and the Vendor B QUAD failed die bin map after wafer level device fabrication. A region in the center was measured with mQUAD which clearly shows well defined low depletion voltage in the failed dies due to the electrically isolated merged PiN Schottky diode devices. The mQUAD map shows excellent correlation to the electrical test failed dies based on BD voltage and Ir criteria.

Fig. 4. An overlay of the test device failed die bin map and the Vendor B QUAD failed die bin map after wafer level device fabrication. A region in the center was measured with mQUAD which clearly shows well defined low depletion voltage in the failed dies due to the electrically isolated merged PiN Schottky diode devices. The mQUAD map shows excellent correlation to the electrical test failed dies based on BD voltage and Ir criteria.

The QUAD failed die bin results can also be compared to UVPL results. An example of this is shown in Fig. 5 for the Vendor A sample. There is a strong correlation of clustered stacking fault defects near the wafer edge to both QUAD failed dies and electrical test failed dies. However there are a large percentage of stacking fault defects in the remainder of the sample that do not cause electrical die failures. Diode devices are much less sensitive to stacking faults compared to MOSFET devices and typically a higher density of stacking faults within a die is necessary to cause diode failures [7]. QUAD mapping can be a strong complement to UVPL to help differentiate which of these defects will result in electrical device failure. Another advantage of the QUAD mapping is that it can effectively measure depletion voltage all the way to the wafer edge as demonstrated in Fig 5.

Using UVPL, QUAD failed die and electrical test failed die results the kill-ratio (KR) and yield impact for various defect types can be calculated using a method proposed by M. Ono et al. [8] and D. Baierhofer et al. [9]. This yield impact and kill ratio analysis, which can give an indication of how detrimental certain defect types are to the efficacy of a particular type of device, will be performed in future work on this project.

Fig. 5. An overlay of the test device failed die bin map, Vendor A QUAD failed die bin map after wafer level device fabrication and a UVPL map of polytype inclusions (triangles, downfall, carrot defects), particle inclusions and stacking faults (SF).

Fig. 5. An overlay of the test device failed die bin map, Vendor A QUAD failed die bin map after wafer level device fabrication and a UVPL map of polytype inclusions (triangles, downfall, carrot defects), particle inclusions and stacking faults (SF).

Conclusion

The original version of this paper is available on https://www.scientific.net/SSP.376.63.pdf

This work presents a comparison between the non-contact corona-based QUAD technique for inline mapping of electrically active defects in SiC epi and final wafer level electrical device data on merged PiN Schottky diodes. Excellent correlation between QUAD wafer bin maps and final device data was observed, demonstrating effectiveness of QUAD as an inline complement to UVPL measurements for identifying electrically active defects. mQUAD mapping with a KFM probe provides a detailed analysis of individual diodes, allowing direct comparison of QUAD and electrical test failures on a die-by-die basis.

References

The original version of this paper is available on https://www.scientific.net/SSP.376.63.pdf

V. Pushkarev, T. Rana, M. Gave, E. Sanchez, A. Savtchouk, M. Wilson, D. Marinskiy and J. Lagowski, Solid State Phenomena 342 (2023): 99-104.

M. Wilson, D. Greenock, D. Marinskiy, C. Almeida, J. D'Amico and J. Lagowski, CS Mantech 2021 Proceedings, Orlando, FL.

D.K. Schroder, Chapter 9: Charge-based and Probe Characterization, in: Semiconductor Material and Device Characteristics, Wiley-Interscience, Hoboken, New Jersey, 2006, p. 523.

M. Wilson, A. Findlay, A. Savtchouk, J. D'Amico, R. Hillard, F. Horikiri and J. Lagowski, ECS Journal of Solid State Science and Technology, 6(11) S3129-S3140 (2017).

M. Wilson, D. Greenock, D. Marinskiy, A. Savtchouk, A. Ross, C. Almeida, B. Schrayer, J. D'Amico and J. Lagowski, CS Mantech 2020 Proceedings, Orlando, FL.

M. Wilson, A. Savtchouk, A. Findlay, J. Lagowski, P. Edleman, D. Marinskiy, J. D'Amico, F. Korsos, N. Orsos and M. Csegazine Varga, Material Science Forum 858 (2016), pp. 353-356.

H. Das, S. Sunkari, J. Justice and D. Hamann, Materials Science Forum 1062 (2022), pp. 406410.

M. Ono, H. Iwata, K. Watanabe, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, (2002) 87-91.

D. Baierhofer, B. Thomas, F. Staiger, B. Marchetti, C. Förster, E. Erlbacher, Defect and Diffusion Forum, 426 (2023) 11-16.

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The original version of this eBook is available on https://www.scientific.net/book/defects-and-characteristics-of-sic/978-3-0364-1918-3

Solid State Phenomena, ISSN: 1662-9779, Vol. 376, pp 71-77

doi: 10.4028/p-H8wzJA

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Revised:
2025-05-16

Accepted:
2025-05-16

Online:
2025-09-10

How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

Yasuyuki Igarashi , Kazumi Takano ,

Yohsuke Matsushita , Takuya Morita

ITES Co., Ltd., 1-60 Kuribayashi, Otsu, Shiga 520-2151, Japan

yiga@ites.co.jp, kazumi_takano@ites.co.jp, yohsuke_matsushita@ites.co.jp,

Keywords: basal plane dislocation, single Shockley stacking fault, carrier lifetime, photoluminescence, UV irradiation, bipolar degradation, screening, recombination-enhanced dislocation glide.

Abstract

The reliability issue of the bipolar degradation in devices has not been completely eliminated. We have been proposing a screening method for latent defects causing this reliability issue utilizing UV irradiation, which we call the E-V-C (Expansion-Visualization-Contraction) method. This method is based on the property that the REDG (recombination-enhanced dislocation glide) mechanism that causes the bipolar degradation can be reproduced by UV irradiation. However, in order to apply this method as a screening method, accurate quantification of the correlation between current density in forward bias and UV irradiance is required. In this article, we estimated the extent to which the carrier lifetime of the sample affects the quantification of the correlation and found that it had a non-negligible degree of influence on the correlation. Then, we tried to find if there is a simple method for estimating carrier lifetime that can be incorporated in the screening process, and report on our attempts in progress.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

4H-SiC devices, which are widely used in products today, have been found to have a reliability issue of so-called bipolar degradation for more than 20 years. The degradation is caused by the nucleation and expansion of a 1SSF (single Shockley stacking fault), originating from BPD (basal plane dislocation) which exists in the epilayer or near the epilayer and the substrate (epi/sub) interface. The 1SSFs are expanded by the electron-hole recombination energy when excessive minority carriers are injected into the regions in the vicinity of the BPDs, which is called REDG mechanism. Various process improvements have been made to convert BPD to benign dislocation TED (threading edge dislocation) at the epilayer/substrate interface, which does not expand. However, it is known that at high current densities, expansion occurs from the BPD-to-TED conversion point, and the issue has not yet been fully resolved.

Since a TED-converted BPD is difficult to identify with existing mass-production inspection system, we have proposed the E-V-C method as a means of screening the latent defects, TEDconverted BPDs [1]. The E-V-C method is a technique to visualize and screen TED-converted BPDs by utilizing UV irradiation and PL observation, aiming for replacing the time-consuming "burn-in" screening usually conducted by overcurrent stress. In order to make the use of UV irradiation to be useful and practical as a screening method, it is required that the UV irradiation conditions must match the specifications of each product, specifically, the absolute maximum current rating of the product. This is because, if UV irradiance is unnecessarily intense, even devices that would not show any degradation within the rated current in normal usage will be screened out (overkill). Therefore, it is essential to derive an accurate quantitative correlation between the forward bias conditions and UV irradiation conditions. It has been reported that whether or not TED-converted BPD expands into a bar shaped stacking fault depends on whether the hole density near the conversion point exceeds a certain threshold during forward biasing [2]. In other words, the key parameter for deriving UV
irradiation conditions equivalent to forward bias conditions is the hole density in the vicinity of the conversion points. On this basis, the authors' team has been exploring the derivation of quantitative correlations [3].

The variable that determines the hole density is the current density in the case of forward biasing and the irradiance in the case of UV irradiation, so relating the two is the point. In addition to these variables, however, there are other parameters that affect the hole density and differ from sample to sample. They include the carrier lifetime of the drift layer in both forward bias and UV irradiation, and surface and interface recombination velocities of the drift layer in UV irradiation. In this article, we first estimated how much difference in correlation appeared when the carrier lifetime was varied. As a result, it was found that a certain amount of non-negligible difference in correlation appeared when the carrier lifetime was incorrectly estimated. This means that it is required to find a simpler method to estimate the carrier lifetime than the -PCD or TRPL method, which is commonly used, since it is not realistic to apply either of those methods to all wafers in production line. We referred to the literature that has evaluated the relationship between PL (photoluminescence) intensity and carrier lifetime [4]. In the latter part of this article, we report on our attempt to estimate carrier lifetime by PL intensity measurement. If the carrier lifetime can be estimated by PL intensity measurement, it can be applied to the production process.

Estimation of the Influence of Carrier Lifetime on the Correlation between Current Density and UV Irradiance

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

First, UV irradiation condition that is equivalent to forward biasing is derived. In the case of a PiN diode, the current flow inside the drift layer consists of hole injection from the anode diffusion layer and electron injection from the buffer layer (or substrate if there is no buffer layer), and the density of the excess minority carrier (hole) in the drift layer can be expressed as follows [5, 6].

where : distance from drift interface, J:current density
: recombination current density ratio in drift layer
: carrier lifetime in drift layer, : drift layer thickness
:ambipolar diffusion length, :elementary charge
: shape factor
Here, the shape factor is calculated by

where : hole current density ratio at drift/buffer interface
electron current density ratio at drift interface
hole mobility in drift layer, electron mobility in drift layer
here .

The electron current density at the drift interface and the hole current density at the drift/buffer interface can be expressed by the following equations using Eq. 1.

where : electron diffusion coefficient in layer
: hole diffusion coefficient in buffer layer
: electron diffusion length in layer
:hole diffusion length in buffer layer
layer thickness buffer layer thickness
layer acceptor density buffer layer donor density
Eventually, Eq. 2 to Eq. 5 become simultaneous equations in four unknowns concerning , , and , and B' can be obtained by a numerical solution method.

On the other hand, the calculation of the hole density generated by UV irradiation using a pulsed laser has been reported by the authors' team [3]. The hole density generated by a single UV pulse irradiation is given as a function of depth and time in the drift layer in the form of the Fourier series as follows.

where are spatial functions with parameters of drift layer width, surface/interface recombination velocities and ambipolar diffusion coefficient.
are time dependent terms with parameters of ambipolar diffusion coefficient and lifetime in drift layer.
are constants including initial hole density at and absorption coefficient of excitation source (laser light).
It is important to note that at time zero, immediately after irradiation, the hole density is described by

where is an absorption coefficient of excitation source (laser light) and

This means that the hole density depth profile at time zero does not depend on the carrier lifetime and the surface / interface recombination velocities. In other words, the hole density distribution at time zero immediately after irradiation is determined only by the injection amount and the absorption coefficient . The carrier lifetime and surface / interface recombination velocities only affect the rate of decay of hole density (decay curve). From the above, since the key parameter for deriving equivalent forward bias conditions with UV irradiation is the hole density in the vicinity of the conversion points, the UV irradiation condition is so determined that the hole density at the drift/buffer interface becomes the same between UV irradiation and forward bias.

Next, considering the lifetime dependence on the hole density, since the right side in Eq. 8 is independent of the lifetime, the variation range of the correlation can be estimated by examining the left side lifetime dependence.

We calculated the effect of carrier lifetime on the hole density on a 6 " wafer with PiN diodes. The profile of the wafer was: anode density thick , drift layer density thick , and buffer layer density thick . The injection current density was assumed , and depth profiles were calculated for carrier lifetime of , and . Fig. 1 shows the results calculated by using Eq. 1 (solid lines), together with the calculated values by using the 1D device simulator, AFORS-HET (dashed lines).

The results show that the hole density at the drift/buffer interface decreases by more than when the lifetime is reduced by to 130 ns and by more than when the lifetime is reduced by to 76 ns , indicating that knowing the lifetime of the drift layer is very important to improve the accuracy of the correlation Eq. 8.

Fig. 1. Depth profiles of hole density in drift layer.

Fig. 1. Depth profiles of hole density in drift layer.

Trial on the Estimation of Carrier Lifetime by PL Intensity Measurement

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

In the screening process in production, it is not practical to use the -PCD method or TRPL method to inspect all the wafers because of a significant cost impact. Since there was a report that investigated the correlation between PL intensity and lifetime of wafers [4], we examined whether the lifetime could be estimated by measuring PL intensity.

Experiment - I (Preliminary): Defect Expansion Rate of 1SSF vs. PL Intensity

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

According to the literature [4], the PL intensity of at 423 nm (related to band-to-band transitions) decreases almost in direct proportion to the shortening of the lifetime. Since the short lifetime means that there are many recombination centers in the drift layer, and the glide velocity of core (1SSF expansion rate) is also expected to become low, the relationship between the glide velocity and PL intensity at 380 nm (related to 4H-SiC band-to-band transitions) was investigated.

The profiles of the three wafers with PiN diodes used in the measurements are shown in Table 1. (Wafer-B is the wafer referred in the previous section to estimate the carrier lifetime dependence on
the hole density.) The glide velocity of the core in the direction was measured as the expansion velocity in the forward biased PiN diodes, and PL spectra were obtained from three points in the vicinity of the diodes. The excitation source was a 355 nm Nd:YAG laser, beam diameter . The measurement results of the glide velocity and the PL spectra are shown in Fig. 2 and Fig.3, respectively. The PL intensity was in the order of Wafer C , and the difference between Wafer B and C is consistent with the difference in expansion speed although it is not significant between the two. While Wafer A is inconsistent with the glide velocity data because the emission would be further stronger if the epi thickness of Wafer A were as thick as that of the other two. This may be due to the fact that the number of defects sampled from Wafer A was very small. Anyway, no clear correlation between defect expansion rate and PL intensity at 380 nm was obtained from this experiment.

Table 1. Sample preparation.

Wafer ID | Size | p⁺ anode | n- drift layer | n+ buffer layer
A | 4" | 3 × 10¹⁸ cm⁻³ | 5.4 μm, 5 × 10¹⁵ cm⁻³ | 0.5μm, 1 × 10¹⁸ cm⁻³
B | 6" | 3 × 10¹⁸ cm⁻³ | 9.1μm, 4 × 10¹⁵ cm⁻³ | 1.0μm, 1 × 10¹⁸ cm⁻³
C | 6" | 3 × 10¹⁸ cm⁻³ | 10.6μm, 7.7 × 10¹⁵ cm⁻³ | 1.0μm, 1 × 10¹⁸ cm⁻³

Fig. 2. core glide velocity range per wafer.

Fig. 2. core glide velocity range per wafer.

Fig. 3. PL luminescence peak for different wafers.

Fig. 3. PL luminescence peak for different wafers.

Experiment - II: Carrier Lifetime vs. PL intensity

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

PL spectrum was obtained on two wafers. Each wafer was evenly divided into four regions and energy filtered implanted with (Nitrogen) ions with different doses per region, and the carrier lifetime of each region was also measured by -PCD method. The measurement point of the PL spectrum and that of the lifetime are identical in each region. The excitation wavelength was , and one of the four regions was without implantation. The PL spectrum was measured by a 355 nm YAG laser with beam diameter . The measurement results are summarized in Table 2. An example of the obtained PL spectrum (Wafer ID:D) is shown in

Fig. 4, showing a peak at around , along with another peak at around 490 nm , which may be due to drift layer doping with ion implantation process because of absence of this peak in the PL spectrum from the non-doped region.

Fig. 4. PL spectrum for ion implanted wafer (Wafer: D).

Fig. 4. PL spectrum for ion implanted wafer (Wafer: D).

In -PCD measurement, the carrier lifetime decay curve can be divided into 1/e time region (fast decay) and time region (slow decay). Since the surface condition of the sample greatly affects the time, the lifetime was adopted as carrier lifetime here in this article. Fig. 5 shows a plot of PL intensity at versus carrier lifetime. As shown in the figure, although there was clear difference in PL intensity between wafers, PL intensity was almost constant within the same wafer regardless of the carrier lifetime variation, indicating that there is no correlation between PL intensity at and carrier lifetime. On the other hand, Fig. 6 plots the correlation between the lifetime and the PL intensity at around 490 nm , which is considered to be reflected by ion implantation. This shows a clear positive correlation between the lifetime and the PL intensity. The reason for the appearance of the peak at around 490 nm has not yet been scrutinized, and we would like to clarify its cause through further investigation.

In summary, contrary to initial expectations, it was difficult to estimate the carrier lifetime from the PL intensity at (reflecting band-to-band transitions of ), but a positive correlation between the PL intensity at around 490 nm and the carrier lifetime was observed.

Table 2. Doping profile, lifetime and PL intensity.

Wafer
ID
Doping Density [cm⁻³]
1/e Time
[ns]
1/e² Time
[ns]
PL Intensity
@ ~390nm
(arb.units)
PL Intensity
@ ~490nm
(arb.units)

D
<5 ×10¹⁴ (non-doped)
160
107.5
42500
1500

1.0 ×10¹⁵
112.5
337.5
38500
10300

5.0 ×10¹⁵
72.5
220
41500
7800

1.0 ×10¹⁶
60
172.5
40000
8500

E
<5 ×10¹⁴ (non-doped)
177.5
135
26300
2000

1.0 ×10¹⁵
177.5
395
22000
11800

5.0 ×10¹⁵
92.5
207.5
23500
9500

1.0 ×10¹⁶
60
200
26000
8800

Fig. 5. Lifetime VS. PL intensity at .

Fig. 5. Lifetime VS. PL intensity at .

Fig. 6. Lifetime VS. PL intensity at .

Fig. 6. Lifetime VS. PL intensity at .

Summary

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

We evaluated the influence of carrier lifetime on quantification of correlation between current density during forward biasing and UV irradiance. As a result, it was found that reflecting the samplespecific carrier lifetime in the correlation equation would surely improve the accuracy of the correlation. To do this for every sample in production line, a simpler method for estimating carrier lifetime is required. We are investigating the possibility of estimating the carrier lifetime by measuring the PL intensity, but no useful data were obtained so far from the PL intensity at 380-390 nm (band-to-band transitions of ). On the other hand, we found a clear positive correlation between carrier lifetime and PL intensity at around 490 nm , which seemed affected by ion implantation process. Further analysis is required to clarify the reason for the 490 nm peak of PL spectrum.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/SSP.376.71.pdf

The authors wish to thank Hitesh Jayaprakash, mi2-factory GmbH , for providing us the wafers for our PL observation and also providing us the carrier lifetime data of those samples.

References

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Keywords Index

2

200 Mm Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

4

4 H -sic Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

4h-silicon Carbide (sic) Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

A

Array Of Ted Pairs Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Avalanche Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

B

Basal Plane Dislocation How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Basal Plane Dislocations (bpds) Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Bipolar Degradation Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs; How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Body Diode Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

C

Carrier Lifetime How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Cncv Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Confinement High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Crystal Growth Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Current Stress Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

D

Defect Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Defect Inspection Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Design Approach Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Dewetting High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Dislocation Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

E

Electrical Deviation Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Eol Device Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Epi Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Epitaxial Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Epitaxial Defects Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Ews Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

I

Inclusion Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Interface Reconstruction High Temperature Evolution of Thin Films Confined between Two SiC Substrates

J

Jbs Diode Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Jbsfet Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

M

Mosfet Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs; Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers; Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

N

Non-contact Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

P

Phase Contrast Microscope Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

Photoluminescence Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards; How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Polarization Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

Prismatic Punched Dislocation Loop Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Proton Implantation Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Q

Quad Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers; Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Quality Standards Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

R

Recombination-enhanced Dislocation Glide How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Reliability Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Room Temperature Ion Implantation Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

S

Screening How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

SiC Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards; Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer; Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

SiC Bonding High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Single Shockley Stacking Fault How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Stacking Fault Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Surface Reaction High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Synergy Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

T

Ted Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

Tsd Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

U

Uis Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Unclamped Inductive Switching Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Uv Irradiation How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Uvpl Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

X

X-ray Topography Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Y

Yield Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Authors Index

A

Almeida, C. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Amishiro, H. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

B

Baek, S. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Bera, L. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Bharathi, M. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

C

Catena, A. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Chand, U. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Chen, Z. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers; Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Cheng, Q. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Cherkashin, N. High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Chung, S. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Cunff, M. High Temperature Evolution of Thin Films Confined between Two SiC Substrates

D

Dudley, M. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers; Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

F

Faisal, F. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Fisher, M. Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Furukawa, A. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

G

Gersappe, D. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Giuffrida, S. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Gutierrez, L. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

H

Hattori, R. Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

Hu, S. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

I

Igarashi, Y. How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Imai, A. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Ishibashi, K. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Ishikawa, Y. Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

J

Jang, S. Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

K

Kagawa, Y. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Kallinger, B. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Karhu, R. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Kayang, K. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Kononchuk, O. High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Kumar, S. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

L

Lagowski, J. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Landru, D. High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Lee, A. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Li, X. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Luca, V. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

M

Magnusson, B. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Mancini, S. Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Marinskiy, D. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Matsushita, Y. How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Maximenko, S. Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Morita, T. How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

N

Nguyen, X. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Niwa, H. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

O

Odekirk, B. Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

P

Polisski, G. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers; Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

R

Raghothamachar, B. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers; Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

Reddy, C. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Rieutord, F. High Temperature Evolution of Thin Films Confined between Two SiC Substrates

Rodgers, B. Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

S

Savtchouk, A. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Shikama, N. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Singh, N. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Song, W. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

Soto, J. Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Soukhojak, A. Punching of Prismatic Dislocation Loops from Inclusions in 4H-SiC Wafers

Speer, K. Challenges in Investigating UIS Material-Based Failures & Yield Prediction in the Absence of Robust -SiC Epiwafer Quality Standards

Steller, N. Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Sugawara, K. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Sung, W. Exploring the Influence of Implant Profile and Device Design on Basal Plane Dislocation Generation in 4H-SiC Power MOSFETs

T

Takano, K. How to Simulate Bipolar Degradation by UV Irradiation with High Accuracy

Tanaka, T. Dynamics of Stacking Fault Expansion in Implanted SiC-MOSFETs

Thörnberg, J. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers

Tok, E. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth

W

Wilson, M. Coherency between Epitaxial Defectivity, Surface Voltage, Photoluminescence Mapping and Electrical Wafer Sorting for 200 mm SiC Wafers; Non-Contact Full Wafer Imaging of Electrically Active Defects in 4H-SiC Epi with Comparison to End of Line Electrical Device Data

Y

Yao, Y. Polarization Superimposed Phase Contrast Microscope Inspection of Dislocations in SiC Epitaxial Layer

Yeo, Y. Defect Density Reduction in 4H-SiC (0001) Epilayer via Growth-Interruption during Buffer Layer Growth