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ISBN print: 978-3-0364-2125-4
ISBN eBook: 978-3-0364-3125-3
DOI book: 10.4028/b-QGc7q5
© 2026 Trans Tech Publications Ltd, All Rights Reserved

Defects Evaluation

Edited by

Sang Mo Koo
Hoon Kyu Shin

Defects Evaluation

Special topic volume with invited peer-reviewed papers only

Edited by
Sang Mo Koo and Hoon Kyu Shin

Scientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volumes 452 of
Defect and Diffusion Forum
ISSN print 1012-0386
ISSN web 1662-9507
(Pt. A of Diffusion and Defect Data - Solid State Data ISSN 0377-6883)

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp -1-0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2026-05-12

Online:
2026-05-18

Preface

The original version of this paper is available on https://www.scientific.net/DDF.452.-1.pdf

Silicon carbide (SiC) has established itself as one of the most high-performance semiconductor materials for next-generation power electronics devices. Its exceptional properties, including a wide bandgap, high critical electric field, superior thermal conductivity, and chemical stability, enable the creation of electronic components that also operate efficiently under extreme conditions. As SiCbased technologies continue to expand in electric vehicles, renewable energy systems, aerospace, and industrial power conversion, the quality and structural integrity of SiC crystals and epitaxial layers have become matters of paramount importance.

The performance and reliability of SiC devices are strongly influenced by crystallographic imperfections introduced during bulk crystal growth and epitaxial deposition. These include micropipes, threading screw and edge dislocations, basal plane dislocations, point defects, inclusions, voids, and surface-related imperfections, etc. Each of these defects can affect electrical characteristics, reduce the breakdown voltage, increase leakage currents, and limit the long-term stability of the final device.

This special edition is devoted to the identification, characterisation, and understanding of the effect of these critical imperfections. Emphasis is placed on advanced analytical techniques that provide essential insight into the origin, distribution, and evolution of defects, enabling continuous improvement in crystal growth processes and epitaxial technologies.

This publication aims to provide researchers and engineers with a deeper understanding of defect formation and characterisation, which is fundamental to achieving the material perfection required for the creation of reliable and efficient SiC -based electronic devices.

Table of Contents

Preface

The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Jimmy Thörnberg, Björn Magnusson

Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Wei Ning Qian, Fei Hong Huang, Ji Nan Li, Gan Feng, Yong Qiang Sun, Jian Hui Zhao, Jun Yong Kang

Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Christian Wißgott, Birgit Kallinger, Mathias Rommel

DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Lan Luo, Yu Zhong, Xiao Shuang Yang, Quan Xin Zhao, Peng Cui, Ying Xin Cui, Ming Sheng Xu, Xian Gang Xu, Ji Sheng Han

Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Zhen Xing Fu, Xiang Long Yang, Xiu Fang Chen, Xue Jian Xie, Li Sun, Hong Yu Shao, Wen Hao Han, Hong Xi Wang, Guo Jian Yu, Xian Gang Xu

DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Rosine Coq Germanicus, Gabriel Ferro

Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Nicolo Piluso, Cristiano Calabretta, Fabiana Vento, Ruggero Anzalone, Chiara Nania, Domenica Raciti, Antonio Rossitto, Alice Lombardo, Mario Coppola, Annalisa Cannizzaro, Andrea Severino, Giuseppe Arena, Matteo M. Salamone, Federico Giuffrida, Luca Barbisan, Parikshit Sharma, Jeff Per, Manoj Kumar Dayyala, Paola Parisi

Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Zimo Yuan, Alex Metreveli, Lasse Vines, Orazio Samperi, Misagh Ghezellou, Jawad Ul-Hassan, Anders Hallén

Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Li Sun, Xue Jian Xie, Xiu Fang Chen, Xiang Long Yang, Yan Peng, Xiao Bo Hu, Xian Gang Xu

High Quality P-Type 4H-SiC Growth by PVT Method

Shan Shan Hu, Hao Chi Wang, Ze Yu Chen, Kai Xuan Zhang, Yu Zhuo Li, Jian Pei Zhang, Balaji Raghothamachar, Michael Dudley, Douglas Dukes, Victor Torres

Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Hitesh Jayaprakash, Manuel Belanche, Constantin Csato, Florian Krippendorf, Ulrike Grossner, Michael Rueb

Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Kai Xuan Zhang, Ze Yu Chen, Shan Shan Hu, Jian Pei Zhang, Yu Zhuo Li, Dong Lin Wu, Hao Chi Wang, Balaji Raghothamachar, Michael Dudley, Andrey Soukhojak

Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Yu Zhuo Li, Jian Pei Zhang, Ze Yu Chen, Hao Chi Wang, Kai Xuan Zhang, Shan Shan Hu, Balaji Raghothamachar, Albert A. Burk Jr, Kanwar Singh, Muhammad Ali Johar, Nadeemullah A. Mahadik, Robert E. Stahlbush, Michael Dudley

Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Dong Lee, Kirby Schmidt, Muhammad Ali Johar, Shanthi Subramanian, Albert Burk, Andy Souzis

Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Cristiano Calabretta, Nicolo Piluso, Ruggero Anzalone, Enzo Fontana, Giovanni Maira, Gabriele Bellocchi, Mario S. Alessandrino, Fabiana Vento, Chiara Nania, Salvatore Adamo, Sonia Zappalà, Giuseppe D'Arrigo, Elisa Vitanza, Nella Bentivegna, Alfio Russo, Giuseppe Arena, Andrea Severino

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 1-7

doi: 10.4028/p-Wfgrr2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-04

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-18

The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Jimmy Thörnberg 1,a* and Björn Magnusson 1, b

1 STMicroelectronics Silicon Carbide AB, Ramshällsvägen 15, 60238 Norrköping, Sweden

a*jimmy.thornberg@st.com, b  bjorn.magnusson@st.com

Abstract

Results from optical defect inspections, and X-ray topography, on wafers from entire 4HSiC ingots provide a clear visualization on the positional dependance of bulk inclusions in ingots with respect to growth stages, looking to both density and size. It is also clear while studying the superpositioning of Laue-Bragg interference densities that the different categories of said defectivity generate new crystallographic defects, dislocations. These in turn lead to significant reductions in usability of wafers, and the lack of tracing such defects, cause an increased difficulty to predict the final device yield, as is displayed by growing epitaxial layers on materials heavily affected by bulk inclusions.

Keywords: 4H−SiC,200 mm, bulk inclusions, defect inspection, XRT, dislocations.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Wide-bandgap semiconductor-based electronics are constantly being developed, with 4H-Silicon Carbide (4H−SiC) leading the way in next generation power devices. Within power electronics, SiC carries intrinsic advantages with higher thermal operation and lower switching losses compared to Silicon-based electronics [1-2]. The fundamental understanding of 4H−SiC crystal growth is also expanding in-line with an increasing commercialization of 4H−SiC wafers, with more key actors and larger facilities ramping up production and thus, increasing the global availability. When scaling up, and larger amount of data becomes available, you realize the outliers is a significant part of the distribution.

Herein, we investigate a defect seemingly overshadowed by more typical and apparent defects, for example micropipes and dislocation. Expanding the understanding of 4H−SiC defectivity with novel results on Bulk Inclusion (BI) tracing and sizing, and the consequences following its presence. We deep-dive into the consequences of such defects, showing how they can affect yield in thin 4H−SiC bonded layer technology. The mere presence of them close to the wafer surface, depending on their size, causes traceable decorations in grown epitaxial layers and directly impacts device yield. We show the ability to pin-point them in the wafer volume (3D) using commercial optical defectivity inspection tools, sizing and, classifying them with respect to their impact on consecutive product or device steps. In addition, many commercial systems used today also have an interaction-volume in orders of several um in the surface sensitive channels, easily mis-bin the presence of such defects as surface contaminations, possibly giving rise to misrepresented yield approximations, unnecessary wafer scrap and, wafers being graded too low. A better understanding of BI will assist in superior yield approximation and material allocation with respect to how sensitive a product is to different sizes of BIs.

Experimental Details

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

In this work, defectivity data from several thousand 200 mm4H−SiCN+ production and development grade wafers, produced in-house, have been used to create accurate theoretical models for defect and dislocation visualization, with their spatial and volumetric dependance as a function of crystal growth stages. The optical defectivity inspection tools used were KLA Candela 8520 and, to verify and align results, a Lasertec SICA88. Specially developed recipes on the former were used to,
not only localize, but also sub-categorize bulk inclusions in ranges of 60 nm to more than 1μ m. The results are compared with conventional recipes that are tailored to include standardized defects with sizing and classification of surface contamination calibrated towards reference wafers with polystyrene latex (PSL) particles on the surface. For dislocation data, a handful of wafers per ingot were scanned using a Rigaku XRTmicron and post-processed using in-house developed recipes using XRT Toolbox software. Epitaxial growth was done using an ASM LPE108 single-wafer CVD reactor. Processing of data was done with in-house made analytical software using primarily Python and R.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Generally, during data acquisition in commercial inspection tools, contrast images are generated based on some inherent normalization rules set in the software by either supplier or user. A system can contain several light sources, and several receiving signal detectors, at various angles. The acquired dataset is further processed by filtering noise from signals, using once again, pre-set rules to find contrast points that could be potential defects. The selected contrast point then goes through a hierarchy of different binning rules, looking to the data from one or more signal detectors, and if all criterias are fulfilled, it gets binned as a defect. If it fails to fulfill all pre-set defects in a binning hierarchy, it is considered noise and becomes undefined. More modern tools utilize machine learning to execute similar logic as mentioned above.

Experienced users can tailor the above logic to find the flaws in the material that do not necessarily fall under what is conventionally tracked in production environments, and this is exactly what is done in this work. We have used a finely tuned recipe, which utilizes several non-standard optical properties from different light sources and signal detectors, to find and sub-categorize volumetric defects in individual 4H−SiC wafers. Post-processing of the data using mathematical models can then construct a 3D visualization of the results of entire ingots. An example of this can be seen in Fig. 1, highlighting BIs of various sizes in an R&D ingot, grown under conditions favoring BIs formation, by combining data from all wafers belonging to it, here showing small (green), medium (blue) and large (red), BIs with approximate sizes of <300 nm,>300 nm and >1μ m, respectively.

In Fig. 1 there is a clear dependance on both the planar position and size of BIs as a function of the lateral position in the ingot, which corresponds to different stages during the crystal growth process. The detailed explanation for this is quite complex and not within the scope of this work, several factors can play a part. Examples of this could be the crystal growth rate, growth thickness,

[picture]

Fig. 1. 3D picture of entire R&D ingot used to produce 200 mm test wafers, showing real positions and distributions of a) smaller (green), b) medium (blue) and large (brown) Bulk Inclusions. Note that Z -axis is not to scale and exaggerated to ease interpretation.

Fig. 1. 3D picture of entire R&D ingot used to produce 200 mm test wafers, showing real positions and distributions of a) smaller (green), b) medium (blue) and large (brown) Bulk Inclusions. Note that Z -axis is not to scale and exaggerated to ease interpretation.

[picture]

Fig. 2. Gradient of small (light blue), medium (blue) and large (brown) bulk inclusions in two separate regions, a)-c) green segment closer to seed and d)-f) red segment closer to the dome, moving from g ) dome to seed position.

Fig. 2. Gradient of small (light blue), medium (blue) and large (brown) bulk inclusions in two separate regions, a)-c) green segment closer to seed and d)-f) red segment closer to the dome, moving from g ) dome to seed position.

stoichiometry of powder changing as a function of growth-time and rate, deterioration of graphite parts and their respective coatings, variation in the magnetic field strength, temperature gradients and so forth. All of which can give rise to circumstances where particles land on the growth front, briefly interrupting it, to evaporate or impinge, and eventually get overgrown to form voids or inclusions.

In Fig. 2, defectivity plots of BIs for individual wafers, belonging to the ingot shown in Fig. 1, can be seen. In Fig. 2 a)-c) the density of small and medium BIs increases and propagates outward as we move closer to the seed, while the segment closer to the end of the growth cycle, the dome, shown in Fig. 2 d)-f), shows less small and medium BIs but with the addition of large BIs, propagating outward as we move further away from the seed and close to the dome, the end of the crystal growth cycle. It is clear looking at the density and gradient of the defects that portions of these would be well within

[picture]

Fig. 3. Illustration of commercial defectivity on bare 4H−SiC substrates, including Bulk Inclusions, as seen a) cross-view of wafer volume with approximate interaction depths of KLA Candela 8520 and Lasertec SICA88 scattering normal and b) top-view showcasing which features would be registered as topographical defects using standardized recipes.

Fig. 3. Illustration of commercial defectivity on bare 4 H − S i C substrates, including Bulk Inclusions, as seen a) cross-view of wafer volume with approximate interaction depths of KLA Candela 8520 and Lasertec SICA88 scattering normal and b) top-view showcasing which features would be registered as topographical defects using standardized recipes.

[picture]

Fig. 4. A wafer severely affected by small and medium inclusions scanned with KLA Candela 8520, showing surface defectivity scan as seen a) using standard recipe calibrated with a PSL wafer and b) same scan but adding logic to improve distinction between surface and volumetric artifacts with c) and d) only showing the defects with high likelihood of affecting final yield.

Fig. 4. A wafer severely affected by small and medium inclusions scanned with KLA Candela 8520, showing surface defectivity scan as seen a) using standard recipe calibrated with a PSL wafer and b) same scan but adding logic to improve distinction between surface and volumetric artifacts with c) and d) only showing the defects with high likelihood of affecting final yield.

the first 5−30μ m of a wafer surface, the interaction volume for the surface sensitive channels in commercial defect inspection tools, where the final inspection would be done for final grading. Many of these would give the same contrast signature as surface contaminations, even though they are inside the substrate volume, potentially causing wrongful classifications. While the ingot presented in this paper belongs to the outliers in terms of BIs density, this defectivity has been found in all major 4 H SiC N+ substrate suppliers at the time of writing.

Due to BIs size and position in the volume, it is difficult to accurately classify them, and they can even be mistaken for other defects. While this heavily depends on refractive index of the material, wavelength and angle of incidence of light sources, an example could be made for 4H−SiCN+ material with the tools used in this work, KLA Candela 8520 and Lasertec SICA88, having an interaction volume of roughly ~30μ m and ~5μ m, respectively, in the surface sensitive channels, see illustrative example in Fig. 3. A very common mis-binning is surface related defectivity, impurity particles or smaller voids, seen in Fig. 3 a) showing common defects as seen from a cross-view of a wafer volume and in Fig. 3 b) how different systems could misinterpret signals from BIs looking to the scattering normal channel, the surface sensitive channel most commonly used for cleanliness and surface condition determination.

The difficulty of distinguishing between the classification of surface contaminations and close-tosurface inclusions are exemplified in Fig. 4, showing a wafer that is highly affected by small and medium BIs. The center-symmetrical pattern of the distribution suggests crystallographic origin and not cleanliness related. However, automated grading systems will have difficulties making that distinction of the feature unless there is a well-trained image recognition module. Another approach is utilizing gaussian-filters specific to the ingot to assist in smoothing out the inclusion trends by removing such noise on post-scan data to get the real surface contamination.

[picture]

Fig. 5. Large Bulk inclusions (brown) as seen in a) an ingot b) projected to a 2D-plane with c) associated TSD maps. The green, orange and red rings in a) is a positional correspondence of the c ) green, orange and red ring around the TSD maps.

Fig. 5. Large Bulk inclusions (brown) as seen in a) an ingot b) projected to a 2D-plane with c) associated TSD maps. The green, orange and red rings in a) is a positional correspondence of the c ) green, orange and red ring around the TSD maps.

Fig. 5 highlights another potential detrimental effect of BIs, specifically those categorized as slightly larger ( >1μ m ). In Fig. 5 a) we see an ingot volume highlighting the larger BIs along with three segments, green, orange and red, with corresponding TSD data collected with XRT in Fig. 5 c). The final segment, encircled by red dash line in c), has a TSD distribution that perfectly coincides with the 2D projection of all large BIs in the ingot, seen in b). It is clear by superpositioning the 2D projection of large BIs, as seen in b), with XRT data, that >95% of them generate their very own TSD. This TSD then continues to propagate from the point of the BIs, to the end of the dome. For medium and small BIs, the conversion-rate appears much lower.

Furthermore, it was hypothesized that an inclusion close to the wafer surface could affect the epitaxial growth due to local changes in thermodynamic driven surface diffusion. The local surface directly perpendicular to a void, close to the surface, could have a higher state of Gibbs free energy than the surrounding landscape due to changes in thermal conductance contributed by the void, its interface, and/or if the void is occupied by a different material, for example pure C . To verify this, a slightly thicker epitaxial layer, using standard 1200 V device conditions, was grown on two wafers, see Fig. 6, with slightly different localization of large BIs, wafer A and B, as seen in Fig. 6 a) and d), respectively. Superpositioning of the epitaxial defects, seen in Fig. 6 b) and e), with corresponding BI map, shows that large BIs close to the surface, at ~30μ m depth or less, tends to decorate the epitaxial layer with micropits at a very high conversion-rate. For small and medium BIs, the conversion is less likely to happen and requires the inclusion to be closer to the surface. Additional work needs to be done to fully understand the relationship between the latter two.

In Fig. 6 c) and f) the TSD maps of the wafers are also shown, pre-epitaxial growth, highlighting another example of how well TSD generation can be associated with BIs. TSD continues to propagate as TSD in epitaxial layers, a known phenomenon, and can increase the likelihood of leakage current in electronic devices [3, 4]. Micropits generated from sub-surface BIs can degrade most devices, showing that such sub-surface defectivity can be detrimental for device yields. The effect on longevity could also be a concern but requires further investigations.

Another significant consequence of larger voids and inclusions in the volume of 4H−SiC is holegeneration in thin 4H−SiC layers bonded on carrier substrates, i.e. polycrystalline 3C−SiC. If the layer thickness of the final bonded mono-SiC material is equal to or less than that of the diameter of an inclusion, a hole will be generated, creating a pathway directly down to the carrier substrate [5]. While the consequences of this depend on the nature of the carrier substrate, consecutive epitaxial growth and device yield are certain to be compromised as the defectivity generated will behave like that of a micropipe.

[picture]

Fig. 6. Defectivity and dislocation maps of two wafers heavily affected by Bulk Inclusions seen before epitaxial growth, a) and d), after epitaxial growth, b) and e), and corresponding Threading-Screw Dislocation maps, c) and f).

Fig. 6. Defectivity and dislocation maps of two wafers heavily affected by Bulk Inclusions seen before epitaxial growth, a) and d), after epitaxial growth, b) and e), and corresponding Threading-Screw Dislocation maps, c) and f).

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Models based on empirical data pulled from thousand production and development grade wafers have been used to construct 3D visualization of BIs inside the volume. These aid in visualization of size, spatial and volumetric trends of BIs that can be directly linked to different crystal growth stages. The ability to pinpoint the defects sets the framework for which continuous studies can be done to understand the consequences on device yields. In this work it is already shown how BIs significantly affect dislocation generation, showing how all larger BIs ( >1μ m ) generate TSDs, and how BIs close to surface will decorate the epitaxial layers as micropits due to changes in the energy landscape on the surface above the BIs. The presence of BIs in commercial material is global, but the defect detection routines and procedures used today have not put emphasis on tracking this sort of defect yet. As the field progresses, pushes the limits of 4H−SiC crystal growth techniques, growth rates, thicknesses and, sizes, this type of defectivity will inevitably become more prominent.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

This study was conducted within the framework of the project ARCHIMEDES, receiving funding from the Key Digital Technologies Joint Undertaking (KDT JU) - the Public-Private Partnership for research, development, and innovation under Horizon Europe - and National Authorities under Grant Agreement No 101112295 funded by the European Union and Vinnova Sweden's Innovation Agency.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

X. She, A.Q. Huang, O. Lucia, B. Ozpineci, Review of silicon carbide power devices and their applications, IEEE Trans. Ind. Electron. 64, 10 (2017), pp. 8193-8205.

J. Guo, Y. Yang, B. Raghothamachar, T. Kim, M. Dudley, and J. Kim, Journal of Crystal Growth, 480 (2017) pp. 119-125.

L. Zhao, Nanotechnology and Precision Engineering, 3, 4 (2020), pp.229-234.

J. R. Huang, T.W. Chen, J.W. Lee, C.F. Huang, L.S Hong, A perspective on leakage current induced by threading dislocations in 4H-SiC Schottky barrier diodes, Materials Letters, 310 (2022) 131506.

E. Cela, W. Schwarzenbach, R. Shrestha, G. Bast, S. Shahidi, G. Simpson, DUV laser-based defect inspection of single-crystal 4H-SiC and SmartSiC engineered substrates for high volume manufacturing, ICSCRM 2024 conference, Session 10 (2024) Poster 2.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 9-14

doi: 10.4028/p-S58gNE

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

Weining Qian 1,2,a, Feihong Huang 2, b, Jinan Li2,c, Gan Feng 2, d, Yongqiang Sun 2,e, Jianhui Zhao 1,2,f and Junyong Kang 1,g*

¹College of Physical Science and Technology, Xiamen University, Xiamen, 361005, Fujian, China

2 Epiworld International Co., LTD, Xiamen 361101, Fujian, China

a  qianwn@epiworld.com.cn, b  huangfh@epiworld.com.cn, clija@epiworld.com.cn, d fengg@epiworld.com.cn, e sunyq@epiworld.com.cn, f zhaojh@epiworld.com.cn, g*jykang@xmu.edu.cn

Abstract

Surface pits in silicon carbide ( SiC ) epitaxial layers have a significant impact on various types of SiC devices, potentially causing electric field concentration and degrading device performance. The formation mechanism of surface pits remains unclear. In this work, the mechanism was investigated through the molten KOH etching experiments, and we confirmed that surface pits originate from dislocation defects in the substrate, particularly TSDs. The dislocations negatively impacted the step-flow growth of epitaxy, leading to pit formation. Further investigations into the effects of growth temperature, C/Si ratio, and epitaxial-layer thickness on pit formation revealed that low temperatures and silicon-rich conditions could effectively suppress pit formation. Both the density and size of surface pits increased significantly with the increase in epitaxial layer thickness. Therefore, this work proposes a model for the formation mechanism of surface pits, where the competition between step-flow growth and spiral growth is a key factor in controlling the size of surface pits.

Keywords: 150 mm4H−SiC, hot-wall reactor, surface pit.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

Compared to traditional silicon semiconductors, 4H−SiC offers revolutionary advantages in highvoltage and high-power applications, owing to its wide bandgap, high breakdown electric field, and high thermal conductivity [1]. With the accelerated popularization of new energy vehicles, the demand for 4H−SiC power devices in automotive applications has been increasing.

For the fabrication of 4H−SiC power devices, chemical vapor deposition (CVD) is one of the key technologies to conduct the homo-epitaxial growth. Nowadays, the defects in epitaxial layers remain a primary challenge in device fabrication, as epitaxial layer defects adversely affect the reliability of 4H−SiC power devices. With the continuous development of 4H−SiC epitaxial technology, killer defects (such as triangular defects and carrot defects) have been effectively controlled and significantly reduced [2,3]. However, the impact of non-killer defects (e.g., surface pits) on 4H−SiC devices has gradually become apparent, potentially increasing leakage current and causing long-term reliability issues [4,5]. Thus, understanding the formation mechanisms of surface pits and thus decreasing formation during the epitaxial process is crucial, which could effectively enhance device reliability.

In this work, we investigated the origin of surface pits and explored the influence of epitaxial process parameters on surface pit density during the growth of 4H−SiC epitaxial layers on 150 mm4∘ off-axis substrates using a hot-wall horizontal single-wafer reactor. By optimizing key process conditions (such as the carbon-to-silicon ( C/Si ) ratio and growth temperature), high-quality 4H−SiC epitaxial wafers with low surface pit defect density were successfully achieved, and the formation mechanism of surface pits was revealed. This research holds significant scientific and engineering value for advancing the large-scale application of 4H−SiC epitaxial materials in high-voltage and high-power devices, as well as for improving device reliability.

Experimental

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

The epitaxial growth was conducted using a horizontal hot-wall reactor. Trichlorosilane (TCS) and ethylene (C2H4) served as the silicon and carbon precursors, respectively. Hydrogen (H2) was used as both carrier and dilution gas, while nitrogen ( N2 ) was employed for n-type doping. Homoepitaxial growth was performed on commercial 150 mm,4∘ off-axis n-type 4H-SiC substrates with an off-cut orientation towards <11-20>. Substrates from the same manufacturer, ingot, and with closely matched lot numbers were selected for comparative experiments to eliminate performance variations caused by substrate quality differences. The TSD density of all substrates used was controlled within the range of 200−400 cm−2. The epitaxial process temperature varies between 1550∘C and 1650∘C, and the chamber pressure was maintained at 100 mbar . The introduced C/Si ratio was varied by C2H4 gas flow rate, while keeping the TCS flow rate constant.

A SICA88 instrument was used to analyze the number and distribution of pit defects with a 3 mm edge exclusion. Thickness of 4H−SiC epitaxial layer was evaluated by Fourier-Transform Infrared spectroscopy (FTIR) with 5−mm edge exclusion. These measurements were performed along the radial direction because the thickness showed concentric distribution.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

Molten potassium hydroxide (KOH) treatments were performed on the epitaxial layer to investigate the origin of surface pits. Defect inspections were conducted at identical locations on the same substrate, the same epitaxial wafer, and the epitaxial wafer after KOH treatment. Using the synchronous positioning function of SICA88, differences in defects at the same positions were compared. The correlation between pit defects on the epitaxial wafer and defects on the substrate was investigated, as illustrated in Fig.1. When examining the same location on the substrate (Fig.1(a)), no microscopic defects were observed at the position where pit defects appeared on the epitaxial wafer surface (indicated by arrows in Fig.1(b)). However, after KOH treatment, dislocation defects in the substrate were exposed at precisely the same position on the epitaxial wafer (Fig. 1 (c)). This indicated that the pit defects did not originate from surface microscopic defects of the substrate, but rather from dislocation defects in the substrate. The dislocation defects likely propagated from the substrate to the epitaxial layer during the epitaxial process, and common dislocation defects in the substrate include threading edge dislocations (TEDs), threading screw dislocations (TSDs), and basal plane dislocations (BPDs) [6]. Based on the morphological characteristics of the etched pit, the dislocation defect shown in Fig.1(c) was likely TSDs or TEDs, rather than the BPD [7]. Based on the differences in the Burgers vectors of TSDs and TEDs, their etched pit morphologies vary significantly. The etched pits formed by TSDs showed a hexagonal structure and they were considerably larger than those formed by TEDs [8]. Therefore, as illustrated in Fig.1, the pit defects on the epitaxial wafer originated from the TSD defects in the substrate. The step-flow growth (along the <11−20> direction) dominated the epitaxial growth of 4H−SiC. If TSDs are present in the 4H−SiC substrate, spiral growth (non-<11-20> direction) would occur at the TSD sites, resulting in the formation of surface pits.

According to the identification of the correlation between surface pits and substrate dislocations, the effects of growth temperature, C/Si ratio, and epitaxial layer thickness on the formation of surface pits were investigated to reduce pits density. Under a fixed C/Si ratio of 0.8,4H−SiC epitaxial layers with a thickness of 10μ m were grown at temperatures of 1570∘C,1590∘C,1620∘C, and 1650∘C, respectively. This was to investigate the effect of growth temperature on surface pit defects. The results, as shown in Fig.2(a), indicated that the density of surface pits decreased significantly with decreasing growth temperature. This might be because the low temperatures suppress the spiral growth of dislocations, thereby reducing the formation of surface pits. Moreover, we explored the role of the surface C/ Si ratio in pit formation. The growth temperature was fixed at 1570∘C, while C/Si ratios of 0.8,0.9,1.0, and 1.1 were employed during epitaxial growth of a 10μ m-thick epitaxial layer. The results presented in Fig.2(b) demonstrated that the surface pit density decreased as the C/Si ratio was reduced. The underlying mechanism is that a lower surface C/Si ratio suppresses the spiral growth of dislocations [9], thereby effectively reducing the formation of pit defects.

Additionally, the evolution of pit size as the thickness increases was studied to investigate the formation of pit defects. Under the conditions of a C/Si ratio of 1.0 and a growth temperature of 1570∘C, 4H-SiC epitaxial layers with varying thicknesses ( 6μ m,12μ m,30μ m, and 60μ m ) were prepared to investigate the influence of epitaxial thickness on surface pit defects. As revealed in Figs.2(c) and 2(d), both the density and size of surface pits increased significantly as the epitaxial layer thickness increased. Based on the detection resolution of the SICA88 surface defect inspection system, the number of pits within different surface size ranges was compared across layers of different thicknesses (see Table 1). The results showed a gradual increase in the total number of detected pit defects and the number of large-sized pits, with increasing epitaxial layer thickness. This indicated that pit defects enlarged progressively during epitaxial growth until they reached the resolution limit of the inspection equipment and became detectable. Given that the pit defects originated from TSDs in the substrate, it could be concluded that the initial density of TSDs in the substrate were the fundamental factor determining the final number of pit defects in the epitaxial layer.

Finally, based on the origin of surface pits and the effects of growth parameters on these pits, we proposed a model of the formation mechanism of surface pits (Fig.3) [10]. The formation of surface pits essentially stemmed from the competition between step-flow growth of dislocations and spiral growth of dislocations. The dynamic balance between these two growth directly determined the size of surface pits. This mechanism underlying the interaction between step-flow growth and spiral growth is similar to that of micropipes formation [11]. The size of pits along non-<11-20> direction increased when spiral growth of dislocations dominates. For the step-flow growth prevails, spiral growth of dislocation was suppressed, leading to a significant reduction in the size of pits non-<1120> direction. The size of pits along the non-<11-20> direction primarily determined the overall size of the pits. The pits with a size over the detection resolution of the SICA88 inspection system could be detected. Under low-temperature or silicon-rich growth conditions, the spiral growth at TSD dislocations was suppressed, which reduced the average size of the pits, thereby decreasing the density of surface pits.

[picture]

Fig. 1. The surface morphology of (a) the substrate and (b) the epitaxial wafer, and (c) the epitaxial wafer after KOH treatment. All surface morphologies were taken from the same location by SICA88.

Fig. 1. The surface morphology of (a) the substrate and (b) the epitaxial wafer, and (c) the epitaxial wafer after KOH treatment. All surface morphologies were taken from the same location by SICA88.

[picture]

Fig. 2. Effect of different (a) growth temperature, (b) C/Si ratio and (c) growth thickness on the pit defect density; (d) Size of pit defects at different growth thicknesses.

Fig. 2. Effect of different (a) growth temperature, (b) C/Si ratio and (c) growth thickness on the pit defect density; (d) Size of pit defects at different growth thicknesses.

Table 1. The number of pits versus their size on epitaxial layers with different thicknesses (by SICA88).

Thickness | Total number of pits | Number of pits (<100 μm²) | Number of pits (100~250 μm²) | Number of pits (250~1000 μm²)
6 μm | 53 | 42 | 11 | 0
12 μm | 236 | 182 | 47 | 7
30 μm | 6504 | 6237 | 241 | 26
60 μm | 32477 | 24909 | 7505 | 63

[picture]

Fig. 3. Schematic illustration of the proposed model of the formation mechanism of surface pits.

Fig. 3. Schematic illustration of the proposed model of the formation mechanism of surface pits.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

This work systematically investigated the origin of surface pits in 4H−SiC epitaxial layers and their dependence on epitaxial growth parameters. Experimental results indicated that surface pits primarily originate from TSDs in the substrate. There was a spiral growth during the epitaxial process, leading to the formation of surface pits. By adjusting growth conditions (e.g., reducing temperature or the C/Si ratio), the formation and expansion of pits could be effectively suppressed. Furthermore, as the epitaxial layer thickness increased, both the density and size of the pits gradually increased, indicating that the pits undergo continuous evolution during growth. Based on these findings, a mechanistic model was proposed, showing the role of competition between step-flow growth and spiral growth of TSD in regulating pit morphology. This work provided a theoretical understanding and practical guidance for optimizing the SiC epitaxial processes, especially suppressing surface pits. It would offer a significant value for improving the performance of SiC devices.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

S. Ranbir, A. C. James, SiC power Schottky and PiN diodes, IEEE Trans. Electron Devices. 49 (2002) 665-672.

K. Tsunenobu, M. Nao, M. Hiroyuki, Performance limiting surface defects in SiC epitaxial pn junction diodes, IEEE Trans. Electron Devices. 46 (1999) 471-477.

S. A. El Hageali, G. Harvey, J. Stevenm, et al, Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability, J. Appl. Phys. 134 (2023) 075704.

H. Fujiwara, H. Naruoka, M. Konishi, et al, Impact of surface morphology above threading dislocations on leakage current in 4H-SiC diodes, Appl. Phys. Lett. 101 (2012) 42104.

T. Katsuno, Y. Watanabe, T. Ishikawa, et al, Surface morphology of leakage current sources of 4H-SiC Schottky barrier diodes by atomic force microscope, Trans. Tech. Publications. 375 (2012) 717-720.

P. C. Chen, W. C. Miao, T. Ahmed, et al, Defect inspection techniques in SiC, Nanoscale Res. Lett. 17 (2022) 1-17.

T. Ohno, H. Yamaguchi, S. Kuroda, et al, Direct observation of dislocations propagated from 4H-SiC substrate to epitaxial layer by X-ray topography, J. Cryst. Growth 260 (2004) 209-216.

T. Katsuno, Y. Watanabe, H. Fujiwara, et al, New separation method of threading dislocations in 4H-SiC epitaxial layer by molten KOH etching, Mater. Sci. Forum 679 (2011) 298-301.

S. I. Nakamura, T. Kimoto, H. Matsunami, et al, Effect of Si ratio on spiral growth on 6 H SiC (0001), Jpn. J. Appl. Phys. 42 (2003) 846-848.

R. Karhu, M. Ghezellou, J. UI Hassan.The origin and formation mechanism of an inclined linelike defect in 4H-SiC epilayers. Phys. Status Solidi B 259 (2022) 2100512.

I. Kamata, H. Tsuchida, T. Jikimoto, K. Izumi. Influence of 4H-SiC growth conditions on micropipe dissociation. Jpn. J. Appl. Phys. 41 (2002) L1137.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 15-19

doi: 10.4028/p-d2PrxR

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-15

Accepted:
2026-01-31

Online:
2026-05-18

Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

C. Wißgott 1,a*, B. Kallinger 1, b and M. Rommel 1,c

1 Fraunhofer IISB, Schottkystraße 10, 91058 Erlangen, Germany

a  christian.wissgott@iisb.fraunhofer.de, b  birgit.kallinger@iisb.fraunhofer.de, c  mathias.rommel@iisb.fraunhofer.de

Keywords: charge carrier lifetime, photoconductivity decay, defect, statistical process control.

Abstract

The quality of the epitaxial layer plays an important role in the performance of modern power electronic devices. Minority carrier lifetime is known to be sensitive to defects like dislocations, stacking faults, and points defects. Therefore, in this work lifetime measurements by microwave detected photoconductivity decay are used to evaluate the quality of the epitaxial layer on various 4H−SiC substrates from different vendors. The stability of the measurement technique is shown by a daily release measurement. This allows for a reliable analysis of almost 300 typical 1,200 V epilayer stacks. It has been shown that the effective lifetime of these samples can be separated into two different ranges. The lifetime values of about 120 ns fit to theoretical calculations. The cause for the increased lifetime of about 250 ns in the second range has yet to be determined in further research. Furthermore, the lifetime maps were used to locate defects in the surface near regions.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

For many modern power electronic devices epitaxial growth on top of a silicon carbide ( SiC ) substrates represents an important first step. The quality of the layer can strongly influence the quality of the subsequent process steps and, therefore, the performance of the whole device [1]. Defects like dislocations, stacking faults, and extrinsic point defects, which might be transferred from the substrate to the epitaxial layer or form in the layer itself can strongly restrict the possible device yield [1,2]. Minority carrier lifetime is known to be sensitive to the presence of such defects, as well as to doping and thickness variations and surface and interface recombination [3]. Hence, lifetime measurements potentially offer a nondestructive and contactless way of monitoring the quality of the grown layer.

Experimental

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Conventional 4H−SiC substrates with a diameter of 150 mm and a 4∘ off-axis orientation towards [112―0] from different vendors were used for epitaxy in multiwafer planetary reactors (AIXTRON G5 WW C and G10-SiC epitaxy reactors). The total thickness of the layers ranged between 10 and 14 μm, with a typical thickness deviation across individual wafers <4%σ/ mean. The layers featured an n-type doping concentration between 8×1015 and 2×1016 cm−3 and a lateral doping deviation <6.5%σ/ mean across the wafer area, which is common for typical 1,200 V epilayer stacks. A buffer layer of 1μ m thickness and doping concentration of 1×1018 cm−3 is included. The carrier lifetime of almost 300 epitaxial wafers has been determined by microwave detected photoconductivity decay ( μ-PCD) measurements in a SEMILAB WT-2000. A laser pulse at a wavelength of 349 nm for 4 ns with 120 μJ per pulse and a raster size of 1 mm was used. An edge exclusion of 3 mm was applied to exclude edge effects.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

Stability of the Measurement Technique.

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To verify the stability of the measurement technique and the tool itself a daily release measurement was performed on the same wafer each morning. After calibrating the laser, the same four points in
the sample center were being measured. The mean values of these four measurement points for each day are depicted in Figure 1. In this statistical process control (SPC) chart the measured values are controlled by an upper and lower specification limit as well as an upper and lower control limit. The former has been defined as ±8% to the mean value over all measurements. A deviation of the measured values outside of these limits can be used to explain irregularities in the measurement data that might occur on specific days. The control limits are defined as three times the standard deviation σ over and under the target value and represent the hard limitation for the usability of the tool.

[picture]

Fig. 1. Statistical process control (SPC) chart of daily μPCD measurements in the center of the same SiC sample with mean value, upper / lower spec limit (USL / LSL) and upper / lower control limit (UCL / LCL).

Fig. 1. Statistical process control (SPC) chart of daily μ P C D measurements in the center of the same SiC sample with mean value, upper / lower spec limit (USL / LSL) and upper / lower control limit (UCL / LCL).

As can be seen in the SPC chart, in over 90 measurement days the spec limits have only been passed on a small number of days, while the control limits have never been breached. This confirms the reliable usage of this measurement process.

Statistical Overview of Lifetime Measurements.

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

Almost 300 epiwafers with 1,200 V epilayers have been analyzed using the μPCD technique. In Figure 2a) exemplary lifetime maps with a raster size of 1 mm for two samples with different lifetimes are presented. Qualitatively, they show the same radial dependence with higher carrier lifetimes in the center of the sample and a decrease towards the edges. However, the maximum value and the decline of lifetime is more pronounced for the sample on the right. Additionally, for all epiwafers, the lifetime has been averaged over the entire wafer area, and the results are statistically evaluated in the histogram in Figure 2b). These average lifetimes are divided in two different ranges: most samples exhibit an average carrier lifetime between 75 ns and 150 ns , while there is also a smaller number of samples with lifetimes around 250 ns . Both groups roughly resemble a Gaussian distribution, which is to be expected.

[picture]

Fig. 2. a) Exemplary lifetime maps with 1 mm raster size from two samples with different lifetimes; b) Histogram of the average lifetimes on different SiC wafers, measured by μPCD.

Fig. 2. a) Exemplary lifetime maps with 1 mm raster size from two samples with different lifetimes; b) Histogram of the average lifetimes on different SiC wafers, measured by μ P C D .

According to Klein [3] effective carrier lifetimes in epilayers are dependent on four different recombination processes: Shockley-Read-Hall (SRH), radiative, Auger, and surface recombination, as seen in Equation (1):

1τmeas =1τSRH+1τRad +1τAuger +1τSurf (1)

For 4H−SiC at the given doping concentrations the radiative and Auger contributions can be neglected [3], leaving τSRH  in the bulk and τSurf  at the surface and the interface between epilayer and substrate. Kimoto et al. [4] showed that bulk lifetimes in epilayers dominated by SRH recombination can be estimated using the Z1/2 concentration NZ as following:

τSRH=2·1013 cm−3NZμS(2)

The surface contribution can be approximated using the epilayer thickness d , the carrier diffusion coefficient D , and the surface recombination velocity S , as reported by Klein [3]:

1τSurf =(d2π2D+d2S)−1(3)

This results in the following Equation (4) for the measured carrier lifetime τmeas  :

1τmeas =1τSRH+1τSurf=NZ2×1013 cm−3μ S+(d2π2D+d2S)−1(4)

Using the values for these parameters in Table 1, the measured carrier lifetime τmeas  can be approximated to 120.4 ns at an epilayer thickness of 10μ m. This matches the left lifetime range in the histogram in Figure 2b). However, the cause for samples with lifetimes in the higher range could not be determined yet. A comparison between the average lifetime of the samples and their corresponding epilayer thickness, doping concentration, substrate resistivity, or substrate vendor did not result in any distinct correlation.

In fact, for some samples originating from adjacent regions of the same SiC ingot, which were coated side by side in the same epitaxy process and measured consecutively using the lifetime measurement tool, lifetime values were obtained that could be divided into the two different lifetime ranges.

Table 1. Parameters used to approximate the effective carrier lifetime in the measured samples.

Z1/2 concentration NZ | 5×10¹² cm⁻³ [5]
Epilayer thickness d | 10 μm
Carrier diffusion coefficient D | 4.2 cm²/s [6]
Surface recombination velocity S | 5×10³ cm/s [3]

Lifetime and Defect Comparison.

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

The most probable cause for difference in the lifetime of different samples are defects in the epitaxial layer. In Figure 3 the lifetime maps of three different wafers are shown. Additionally, for each wafer a mapping of defects, recorded with a Lasertec SICA88, is included. It is noticeable that areas with higher density of defects have a strongly decreased carrier lifetime. Particularly stacking faults and polytype inclusions seem to have a strong influence. In the close ups of the Differential Interference Contrast (DIC) images, it is also recognizable that these areas with higher ratio of defects have a rougher surface compared to other areas of the wafers.

[picture]

Fig. 3. Comparison of lifetime and defect maps as well as Differential Interference Contrast (DIC) images (recorded with Lasertec SICA88); average lifetime for each map is given.

Fig. 3. Comparison of lifetime and defect maps as well as Differential Interference Contrast (DIC) images (recorded with Lasertec SICA88); average lifetime for each map is given.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

The μPCD measurement technique offers a fast and non-destructive way of determining the effective lifetime of minority charge carriers in the epitaxial layer of 4H−SiC epilayer stacks. This can be used to gain information about the quality of the epilayers as well as the location and density of defects in the layer. With the use of the daily measurements the stability of the measurement tool can be controlled. Additionally, the lifetime values around 120 nm could be verified by theoretical calculations. However, the occurrence of the second lifetime range is still not fully understood. In further research the different types of defects and their density in samples from the different groups will be compared, to gather further insight into their impact on the charge carrier lifetime.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

D. Baierhofer, B. Thomas, F. Staiger, B. Marchetti, C. Förster, and T. Erlbacher, "Defect reduction in SiC epilayers by different substrate cleaning methods," Mater. Sci. Semicond. Process., vol. 140, p. 106414, Mar. 2022, doi: 10.1016/j.mssp.2021.106414.

J. Erlekampf et al., "Lifetime limiting defects in 4H-SiC epitaxial layers: The influence of substrate originated defects," J. Cryst. Growth, vol. 560-561, p. 126033, Apr. 2021, doi: 10.1016/j.jcrysgro.2021.126033.

P. B. Klein, "Carrier lifetime measurement in n-4H-SiC epilayers," J. Appl. Phys., vol. 103, no. 3, Feb. 2008, doi: 10.1063/1.2837105.

T. Kimoto, T. Hiyoshi, T. Hayashi, and J. Suda, "Impacts of recombination at the surface and in the substrate on carrier lifetimes of n-type 4H-SiC epilayers," J. Appl. Phys., vol. 108, no. 8, Oct. 2010, doi: 10.1063/1.3498818.

D. Kaminzky, B. Kallinger, P. Berwian, M. Rommel, and J. Friedrich, "Modelling of Effective Minority Carrier Lifetime in 4H-SiC n-Type Epilayers," MSF, vol. 858, pp. 341-344, May 2016, doi: 10.4028/www.scientific.net/MSF.858.341.

P. Grivickas, J. Linnros, and V. Grivickas, "Carrier diffusion characterization in epitaxial 4HSiC," J. Mater. Res., vol. 16, no. 2, pp. 524-528, Feb. 2001, doi: 10.1557/JMR.2001.0075.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 21-26

doi: 10.4028/p-7MIvaq

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-21

Accepted:
2026-02-23

Online:
2026-05-18

DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Lan Luo 1,a, Yu Zhong 1,2, b*, Xiaoshuang Yang 1,c, Quanxin Zhao 1, d, Peng Cui 1,e, Yingxin Cui 1,f, Mingsheng Xu 1, g, Xiangang Xu 1, h and Jisheng Han 1,i*

1Institute of Novel Semiconductors, State Key Laboratory of Crystal Materials, Shandong University, Jinan, 250100, China

2 Shandong Research Institute of Industrial Technology, Jinan, 250100, China

alan.luo@mail.sdu.edu.cn, b  yu.zhong@sdu.edu.cn, c  202434109@mail.sdu.edu.cn, d  202414092@mail.sdu.edu.cn, e  pcui@sdu.edu, f  cuiyingxin@sdu.edu.cn, g xums@email.sdu.edu.cn, h xxu2002@163.com, j j.han@sdu.edu.cn

Keywords: 4 H -SiC, SBD, DLTS, Characterization, Deep Level Defects, Measurement Parameters.

Abstract

This paper investigates the effect of DLTS measurement parameters on characterizing deep level defects in 4H-SiC Schottky barrier diode (SBD). By adjusting parameters such as the time window ( tW ), pulse time ( tP ), reverse voltage ( UR ), and pulse voltage ( UP ), the underlying mechanisms influencing defect peak positions, signal amplitudes, and peak broadening are analyzed. Experimental results reveal three deep level defects identified in 4H−SiC SBD: majority carrier traps T1 ( EC− 0.66 eV ) and T2(EC−1.0eV), along with minority carrier trap T3(EV+1.1eV). Parameter settings not only influence defect characterization sensitivity and concentration calculations but also reveal the dynamics of carrier capture and emission. Through the thorough analysis of the DLTS signal and behavior under different DLTS measurement conditions, the electronic properties and concentration profiles of deep level defects in 4H-SiC epitaxial layers are determined.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

4H-Silicon carbide (4H−SiC) is one of the remarkable wide bandgap semiconductor materials due to its extraordinary properties, such as high breakdown electric field, high electron saturation drift velocity, and high thermal conductivity. Consequently, it is extensively utilized in high-power, hightemperature, and high-voltage applications [1,2]. However, deep level defects are key factors affecting the performance of 4H−SiC devices, significantly reducing carrier lifetime, mobility, and device reliability [3].

Deep level transient spectroscopy (DLTS) is a powerful technique widely used for studying deep level defects in semiconductors [4,5]. It can determine critical defect parameters, such as energy level position in the bandgap, capture cross-section, and defect concentration (NT). Still, the accuracy and resolution of DLTS measurements highly depend on the settings of the measurement parameters. This paper aims to systematically analyze the effects of key DLTS measurement parameters on the characterization results of deep level defects of 4H−SiC, including the time window ( tw ), pulse time (tP), reverse voltage ( UR ), and pulse voltage ( UP ). The findings aim to provide a crucial experimental and theoretical basis for the precise analysis of deep level defects in 4H-SiC with DLTS measurements.

Experimental

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The sample used in this study is 4H−SiC Schottky barrier diode (SBD), with its structural schematic shown in Fig. 1(a). The device, fabricated by Guangzhou Summit Power Semiconductor Co., Ltd., has an active area of 3.24 mm2. The current-voltage (I-V) characteristics of the device demonstrated good rectification, with an ideality factor of 1.05 and a Schottky barrier height of 1.2 eV . Furthermore, capacitance-voltage ( C−V ) curve analysis indicates a doping concentration of 8.6×1015 cm−3 for the n-type epitaxial layer, as shown in Fig. 1(b).

DLTS measurements are conducted over the temperature range from 100 K to 700 K using a PhysTech FT-1230 HERA-DLTS. DLTS spectra are acquired under various conditions by adjusting measurement parameters, including tw,tP,UR, and UP. A typical diagram of the DLTS measurement parameters and resulting transient capacitance is shown in Fig. 1(b). The measurement procedure is as follows: the sample is initially maintained under UR. The UP is then applied to fill the traps in the space charge region with carriers. At the end of UP, the bias voltage reverts to UR, initiating the carrier emission process. The subsequent capacitance transient is recorded over a specified tw. The influence of these DLTS parameters on the derived defect characteristics in SiC is systematically analyzed.

[picture]

Fig. 1. (a) Schematic diagram of 4H−SiCSBD structure. (b) C−V characteristic of 4H−SiCSBD. (c) Diagram of the DLTS measurement parameters and transient capacitance signals generated during carrier emission.

Fig. 1. (a) Schematic diagram of 4 H − S i C S B D structure. (b) C − V characteristic of 4 H − S i C S B D . (c) Diagram of the DLTS measurement parameters and transient capacitance signals generated during carrier emission.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Effect of Time Window on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

In DLTS signals, peaks can be observed when the trap emission rates ( eT ) match the tw. Changing tw results in peak positions to shift with temperature, allowing the eT to be measured through temperature scanning. As shown in Fig. 2(a), all peaks shift towards lower temperatures with increasing tw. This shift occurs because a longer tw corresponds to a slower eT. Since the eT of a trap follows an exponential dependence on the inverse temperature, a slower eT is matched at a lower temperature [4].

eT=Nc,vσvthexp(−ΔEkBT)(1)

Where σ is the trap capture cross-section, vth  is the thermal velocity of carriers, ΔE is the activation energy of the trap, and Nc,v is the effective density of states in the conduction band or valence band.

Fig. 2(a) shows the DLTS spectra of 4H−SiC SBD measured under different tw. Three signal peaks are observed: a positive peak appearing in the temperature range from 280 K to 330 K , labeled T1; a positive peak appearing in the range from 450 K to 550 K , labeled T 2 ; and a negative peak appearing in the range from 570 K to 620 K , labeled T3. As tw increases, the amplitude of T1 peak remains essentially unchanged, while the amplitudes of T2 and T3 peaks decrease obviously. The peak amplitude of the DLTS signal is proportional to the NT. Fig. 2(b) shows defect information derived from Arrhenius plot fitting under different tW, including σ and NT. As tW increases, the NT of T 2 and T3 decreases. Shorter tw is more sensitive to defects with faster eT, whereas a longer tw primarily detects defects with slower eT. Consequently, if tW does not match the eT of defects contributing to T2 and T3 peaks, the signal amplitudes of the peaks decrease.

The deep level trap T1 is identified as a majority carrier trap with the energy level located 0.66 eV below the bottom of the conduction band (EC). It exhibits a symmetric Gaussian-shaped peak and a single-exponential emission kinetics and these are characteristics of point defects. The measured ΔE and σ of T1 are consistent with the fingerprint of the Z1/2 center, an intrinsic defect complex in n-type 4H−SiC. The Z1/2 center, which is commonly attributed to a carbon vacancy (VC) or related complex,
can act as a lifetime-killing recombination center and is commonly observed in DLTS spectra of asgrown 4H-SiC epitaxial layers [6].

T 2 is a majority carrier trap with the activation energy of at EC−1.0eV. It exhibits broad and asymmetric DLTS peaks, which suggests T2 is not related to the discrete point defects. T2 may correspond to envelope peaks formed by multiple defects with close energy levels or the extended defect [7,8].

T3 is a minority carrier trap with the energy level located 1.1 eV below the valence band top (Ev +1.1 eV ). The 4H−SiCSBD is a unipolar device where minority carriers are typically absent under reverse bias. However, the presence of the P+ region can serve as a source of minority carrier injection under specific measurement conditions. This injection makes the detection of the minority carrier traps such as T3 possible [9, 10]. T3 exhibits a broad and asymmetric DLTS peak, which is characteristic of interface states at the metal/SiC interface or extended defects rather than point defects. Extended defects in 4H−SiC, such as stacking faults, dislocation clusters, or basal plane dislocations, can introduce broad distribution of energy levels within the bandgap due to strain fields and localized electronic states. These defects act as minority carrier trapping centers and can significantly affect carrier recombination and device reliability.

[picture]

Fig. 2. (a) DLTS spectra and (b) defect information of 4H−SiCSBD under different tw.

Fig. 2. (a) DLTS spectra and (b) defect information of 4 H − S i C S B D under different t w .

Effect of Pulse Time on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Fig. 3(a) illustrates the effect of tp on the DLTS spectrum. As tp increases, the position and shape of T1 peaks remain unchanged, indicating that its trap filling saturates rapidly even at the shortest tp. This result is consistent with the data in Fig. 3(b) that the amplitude of T1 peak does not exhibit significant variation with tp, which is characteristic of the capture kinetics of a point defect. In contrast, as tp increases, the T2 and T3 peaks shift to higher temperatures, gradually broaden, and their amplitude continues to increase over the entire test range in agreement with the trend in Fig. 3(b). This behavior strongly suggests the presence of a more complex capture mechanism involving defects with a continuous energy distribution. This feature of T2 peak is typically regarded as the fingerprint characteristic of spatially extended defects such as dislocations, stacking faults, or defect clusters [11, 12]. The capture process in such defects is governed by a combination of factors. These include potential barriers around the defect core, carrier re-emission during capture, or a distribution of capture rates. These factors lead to the observed slow, non-exponential filling behavior. As a minority carrier trap, T3 exhibits amplitude saturation when tp exceeds 100 ms . However, it also demonstrates significant increase before saturation, suggesting it possesses non-point defect kinetic properties. These characteristics are associated with defect clusters or interface states at the metal /SiO2 interface.

The defect parameters extracted from Arrhenius plots under different tp are summarized in Fig. 3(c). As tp increases, the σ of all three defects shows no obvious change. For NT, along with the increase of tp, the values for T2 and T3 exhibit an upward trend, while T1 remains almost unchanged.

Therefore, the tp used in this work can reveal the kinetic characteristics of T2 and T3 and confirm their non-point defect nature. It should be noted that accurate quantification of the total concentration of extended defects like T2 and T3 requires measurements at longer tp to ensure complete trap filling.

[picture]

Fig. 3. (a) DLTS spectra of 4 H -SiC SBD under different tp, (b) amplitudes of DLTS peaks as a function of the logarithm of the tp, and (c) defect information extracted from Arrhenius analyses.

Fig. 3. (a) DLTS spectra of 4 H -SiC SBD under different t p , (b) amplitudes of DLTS peaks as a function of the logarithm of the t p , and (c) defect information extracted from Arrhenius analyses.

Effect of Reverse Voltage on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Fig. 4 shows the DLTS spectra and the corresponding defect information under different UR. As the absolute value of UR decreases (|UR|), the NT of three defects reduces due to the narrowing of the detection depletion region width. The depth of the depletion region width can be tuned by applying different UR values and in this way defect profile information can be obtained. The signal amplitudes of T2 and T3 peaks exhibit non-monotonic and irregular fluctuations with changing UR. This behavior indicates an uneven distribution of these defects, further corroborating their association with extended defects. Such distribution characteristics are typically observed in defect clusters or extended structural defects.

[picture]

Fig. 4. (a) DLTS spectra and (b) defect information of 4H−SiCSBD under different UR.

Fig. 4. (a) DLTS spectra and (b) defect information of 4 H − S i C S B D under different U R .

Effect of Pulse Voltage on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Fig. 5 shows the DLTS spectra and the derived defect information under different Up. As Up increases, the depletion region width of the diode becomes narrower during UP period. This reduction allows more carriers to inject into the detection region, thereby filling more deep level traps, resulting in an enhanced DLTS signal. For varied UP, traps located at different depth scan be filled due to the corresponding changes in band bending. This capability enables the analysis of the spatial distribution of defects along with the depth. When utilized in combination with UR,UP can be effectively employed to distinguish between the deep level defects in bulk material and the interface states [13].

[picture]

Fig. 5. (a) DLTS spectra and (b) defect information of 4H−SiCSBD under different UP.

Fig. 5. (a) DLTS spectra and (b) defect information of 4 H − S i C S B D under different U P .

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

In conclusion, this study employs DLTS to measure three deep-level centers in 4H-SiC SBDs. The effects of different measurement conditions on the deep-level defects at different energy levels are compared. The result indicates that tw corresponds to the emission rate of specific traps; it can be used to distinguish between point defects and the extended defects. As tp increases, the amplitude of deep level trap peaks gradually saturates. Therefore, a higher tp is recommended for more precise detection of defects at specific energy levels. Furthermore, by precisely controlling the UR and UP, the concentrations and depth distributions of defects in the epitaxial layer can be quantitatively determined, enabling the distinction between the bulk traps and the interface traps. This paper offers crucial experimental evidence and theoretical basis for the precise characterization of deep level defects and the optimization of DLTS measurement protocols.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

F. La Via, D. Alquier, F. Giannazzo, T. Kimoto, P. Neudeck, H. Ou, A. Roncaglia, S.E. Saddow, S. Tudisco, Emerging SiC Applications beyond Power Electronic Devices. Micromachines. 14 (2023) 1200.

M. Buffolo, D. Favero, A. Marcuzzi, C. De Santi, G. Meneghesso, E. Zanoni, M. Meneghini, Review and Outlook on GaN and SiC Power Devices: Industrial State-of-the-Art, Applications, and Perspectives. IEEE Transactions on Electron Devices. 71 (2024) 1344-1355.

I. Capan, 4H-SiC Schottky Barrier Diodes as Radiation Detectors: A Review. Electronics. 11 (2022) 532.

D.V. Lang, Deep-level transient spectroscopy: A new method to characterize traps in semiconductors. J. Appl. Phys. 45 (1974) 3023-3032.

L. Luo, Yu. Zhong, K. Y. Cheong, R. Zhang, T. Wang, D. Yuan, H. Linewih, S. Li,, Y. Cui, M. Xu, X. Xu, J. Han, The Principles and Applications of Electrical Characterization Techniques for Electrically Active Defects in 4H-SiC Devices. J. Phys. status solidi A. 222 (2025) 2400840.

T. Kimoto; J. A. Cooper, Characterization Techniques and Defects in Silicon Carbide, in Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, Wiley, Singapore, 2014, pp.125-187.

Y. He, G. Yan, X. Liu, Z. Shen. W. Zhao, L. Wang, F. Zhang, G. Sun, Y. Zeng, Investigation of Defect Levels of Al/Ti 4H-SiC Schottky structures by Deep Level Transient Spectroscopy, 2019 16th China International Forum on Solid State Lighting & 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS), Shenzhen, China, 2019, pp. 7-10.

H. J. Kang, J. H. Moon, W. Bahng, S. Lee, H. Kim, S. -M. Koo, D. Lee, D. Lee, H. -Y. Cho, J. Heo, H. J. Kim, Oxygen- and photoresist-related interface states of 4H-SiC Schottky diode observed by deep-level transient spectroscopy. J. Appl. Phys. 122 (2017) 094504.

J. Weber, H. B. Weber, M. Krieger, On deep level transient spectroscopy of extended defects in n-Type 4H-SiC, in 2016 European Conference on Silicon Carbide & Related Materials (ECSCRM), Halkidiki, Greece, 2016, pp. 1-1.

X. Gao, X. Wang, Y. Li, Z. Yang, M. Gong, M. Huang, Y. Ma, Comparing the effect between room temperature and low temperature heavy ion irradiation by deep level transient spectroscopy. Nucl. Instrum. Methods Phys. Res., B. 550 (2024) 165319.

L. Gelczuk, G. Jozwiak, M. Dabrowska-Szata, D. Radziewicz, Dislocation in latticemismatched InGaAs/GaAs heterostructures as a factor of optoelectronic device degradation. Proceedings of 2005 International Students and Young Scientists Workshop Photonics and Microsystems, 2005., Dresden, Germany, 2005, pp. 33-36.

L. Gelczuk, M. Dąbrowska-szata, Z. Synowiec, Electrically active defects in SiC Schottky barrier diodes. Mater Sci-Pol. 29 (2011) 70.

A. V. P. Coelho, M. C. Adam, H. Boudinov, Distinguishing bulk traps and interface states in deep-level transient spectroscopy. J. Phys. D: Appl. Phys. 44 (2011) 305303.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 27-31

doi: 10.4028/p-QD8ybH

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-10

Accepted:
2026-02-23

Online:
2026-05-18

Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

Z. X. Fu 1,a, X. L. Yang 1, b*, X. F. Chen 1,c*, X. J. Xie 1, d, L. Sun 1,e, H. Y. Shao 1,f, W. H. Han 1, g, H. X. Wang 1, h, G. J. Yu 2,i, X. G. Xu 1,j

1 State Key Laboratory of Crystal Materials, Institute of Novel Semiconductors, Shandong University, Jinan, 250100, China

2 Guangzhou Summit Crystal Semiconductor Co., Ltd, Guangzhou, 511462, China

af  uzhenxing1122@126.com, b  yangxI2016@sdu.edu.cn, c  cxf@sdu.edu.cn, d  xiexj@sdu.edu.cn,

e sdusunli@sdu.edu.cn, f 202114048@mail.sdu.edu.cn, g hwh@mail.sdu.edu.cn,

h202434144 @mail.sdu.edu.cn, YuGuojian@summitcrystal.com, j xxu@sdu.edu.cn

Abstract

H-SiC single crystals were grown under different temperature fields and nitrogen doping conditions by physical vapor transport method. The distributions of basal plane dislocation (BPD) in 4H−SiC single crystals under different growth conditions were studied by molten KOH etching and X-ray Topography (XRT). The results indicate that the BPDs in the crystals grown under convex temperature field are distributed at the edge. In comparison, the BPD distributions in crystals grown under a concave temperature field are relatively closer to the center. Furthermore, the BPDs distributions in nitrogen-doped crystals exhibit quadratic symmetry caused by prismatic slip. In contrast, no prismatic slip-induced slip bands were observed in the undoped crystals, and the BPD distributions in the undoped crystals are consistent with the shear stress distribution caused by basal plane slip.

Keywords: 4H−SiC,8-inch, BPD distribution, dislocations slip.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

As a representative of the third-generation semiconductors, silicon carbide ( SiC ) exhibits excellent physical and chemical properties, offering a wide range of research and application scenarios [1,2]. Dislocation is one of the main factors limiting crystal quality, among which BPDs could lead to positive voltage drift during device operation. Due to the large size of 8 -inch 4H−SiC crystals, it is difficult to control the temperature field [3,4]. During the growth process of 8 -inch crystals under different temperature fields, the distribution of thermal stress varies, which leads to differences in the distribution of BPDs within the crystal. In addition, nitrogen doping, as a method to adjust the resistivity of SiC crystals to adapt to different needs, changes the physical properties of SiC by replacing carbon atoms with nitrogen atoms[5]. Since the diameter of nitrogen atoms is smaller than that of carbon atoms, the occupation of carbon sites by nitrogen atoms affects lattice matching[6]. Nitrogen doping is found to facilitate the nucleation of BPDs and decrease the shear stress required for the nucleation of BPDs [7].

In this work, we grown 4H−SiC single crystals under different temperature fields and nitrogen doping conditions using the physical vapor transport (PVT) method. The distribution characteristics of BPD in the crystals under different conditions were studied through molten KOH etching and XRT.

Experiments

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

8 -inch 4 H -SiC single crystals were grown on seeds with 4∘ off-angle using the PVT method. The growth temperature of the crystals was maintained at 2000~2200∘C, and the growth pressure was set at 1~10mbar. Other growth conditions are as shown in the Table 1, with the temperature field and whether nitrogen is doped as variables.

Table 1. Growth Conditions of Different Crystals.

Grown crystals | Temperature fields | Doping
Crystal A | Convex | N-doped
Crystal B | Concave | N-doped
Crystal C | Convex | undoped

Wafers from the early growth stage of these crystals were selected and etched by molten KOH solution at 500∘C for 30 minutes. These wafers were labeled as Wafer A1, B1, and C1, respectively. The dislocation morphology of the etched samples was observed using an optical microscope. Adjacent wafers to the etched ones were observed by XRT with the diffraction vector g=11−20, which were labeled as Wafer A2, B2, and C2.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

The BPD distributions of crystals grown in different temperature fields and nitrogen doping conditions are shown in Fig. 1. The BPDs in Wafer A1 are distributed at the edges, while the BPDs in Wafer B1 are away from the edges and more closely distributed towards the center. The reason is that the thermal stress generated during crystal growth under a convex temperature field is mainly distributed at the edges, whereas under a concave temperature field, the stress near the center of the crystal increases compared to the convex temperature field, leading to a distribution of BPDs closer to the center.

The BPD distribution of Wafer C1 is shown in Fig. 1(c). The BPDs in Wafer C1 are also distributed at the edges similar to that in Wafer A. The difference is that the positions with the highest BPD density in Wafer C1 are at the ends of a straight line parallel to the [1-100] direction and passing through the center of the wafer. However, the positions with the highest BPD density in Wafer A1 are four other areas, which is consistent with the report by Lu et al [8]. Although Crystal B was grown under a different temperature field, the distribution of BPDs in wafer B1 also exhibits the same fourfold symmetry as in Wafer A1. This result indicates that nitrogen doping affects the distribution of BPDs in 4H−SiC.

[picture]

Fig. 1. BPD density distribution map of (a) Wafer A1, (b) Wafer B1 and (c) Wafer C1.

Fig. 1. BPD density distribution map of (a) Wafer A1, (b) Wafer B1 and (c) Wafer C1.

After etching, 12 areas on Wafer A1 were observed, and the results are shown in Fig. 2(a). The BPD directions at different locations exhibit a certain pattern: in each area, the BPD etch pits mainly have two directions, both of which are two out of [11-20], [1-210] and [-2110]. The distribution characteristics of the BPD directions show a 12-fold symmetry, similar to the pattern discovered by Hu et al [9]. Additionally, among the four high dislocation density locations corresponding to Fig. 1(a), the number of BPDs along the [11-20] direction is significantly higher than that along other directions. This indicates that the reason for the fourfold symmetry in BPD density distribution is due to an increase in the number of BPDs in the [11-20] direction at specific locations.

Lu et al. [10] have pointed out that the primary dislocation slip mode during the growth of 8 -inch 4 H -SiC crystals is prism slip. By observing 12 areas on Wafer A2 using XRT, as shown in Fig. 2(b), a large number of dislocation lines caused by prism slip were found in the 12 areas of Wafer A2, and the direction of these dislocation lines is consistent with the direction of BPD etch pits at the same positions in Wafer A1. Furthermore, a greater number of prism dislocation lines [11] were observed in the four positions with the highest BPD density. This indicates that in N-doped 4H-SiC crystals grown under convex temperature fields, prism slip is the main cause of BPD generation.

[picture]

Fig. 2. (a) Morphology of BPD etch pitson Wafer A1, (b) Prismatic dislocations on Wafer A2.

Fig. 2. (a) Morphology of BPD etch pitson Wafer A1, (b) Prismatic dislocations on Wafer A2.

Fig. 3(a) shows the optical microscope images of BPD etch pits in 12 areas of Wafer B1, with the selected 12 positions being closer to the center of the wafer. The BPDs direction in Wafer B1 exhibit a 12-fold symmetric distribution, and the BPD quantities show a fourfold symmetric distribution, same as those in Wafer A1. Moreover, the number of BPDs in the [11-20] direction is higher than others. Fig. 3(b) presents the XRT image of Wafer B2, where the distribution of prism dislocations are highly consistent with those of BPD. This indicates that in N-doped 4H−SiC crystals grown under concave temperature fields, the main cause of BPD generation is still prism slip.

[picture]

Fig. 3. (a) Morphology of BPD etch pits on Wafer B1, (b) Prismatic dislocations on Wafer B2.

Fig. 3. (a) Morphology of BPD etch pits on Wafer B1, (b) Prismatic dislocations on Wafer B2.

Fig. 4(a) shows the BPD etch pit images in 12 areas of Wafer C1, with the selected 12 areas being the same as those in wafer A1. The characteristics of BPD in Wafer C1 are completely different from the patterns observed in wafers A 1 and B 1 . The directions of BPD etch pits in Wafer C1 are random. Fig. 4(b) presents the XRT image of 12 areas in Wafer C2, where no prism dislocation lines were observed. This indicates that in undoped 4H−SiC crystals grown under convex temperature fields, prism slip has no contribution to the generation of BPD. Moreover, the BPD distribution shown in Fig. 1(c) is consistent with the results of basal plane slip reported by Lu et al., suggesting that in undoped 4H−SiC crystals, basal plane slip is the main cause of BPD generation.

[picture]

Fig. 4. (a) Morphology of BPD etch pits on Wafer C1, (b) Prismatic dislocations on Wafer C2.

Fig. 4. (a) Morphology of BPD etch pits on Wafer C1, (b) Prismatic dislocations on Wafer C2.

Crystals A and C grow under the same temperature field, but the causes of BPD generation are different. Nitrogen doping is the reason for this phenomenon. It is well known that the {0001} face is the close-packed surface of 4H−SiC, so basal plane slip occurs more easily than prism slip. Therefore, in crystal C , basal plane slip plays a dominant role in the generation of BPD. After nitrogen doping, the critical shear stress of the crystal decreases, leading to the occurrence of prism slip in crystal A, which then dominates, resulting in new characteristics in the BPD distribution.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

Three crystals were grown under different temperature fields and nitrogen doping conditions, and the characteristics of BPD distribution were observed. In the convex temperature field, the BPD
is mainly distributed at the edge of the crystal; while in the concave temperature field, the BPD distribution is closer to the center of the crystal, which is related to the stress distribution under different temperature fields. The BPD distribution in nitrogen-doped crystals shows fourfold symmetry in quantity and twelvefold symmetry in direction, which is related to prism slip; the BPD distribution in undoped crystals shows axial symmetry in quantity and no regularity in direction, which is related to basal plane slip.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

This work was supported by the National Natural Science Foundation of China (Grant No. U23A20569), the Key R&D Program of Shandong Province (2022ZLGX02) and the Taishan Scholars Program.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

X. X. Xiong, X. L. Yang, X. F. Chen, X. M. Li, X. J. Xie, G. J. Hu, Y. Peng, G. J. Yu, X. B. Hu, Y. H. Wang, X. X. Xu, J. Inorg. Mater. 38 (2023) 1371.

Musolino M, Xu X, Wang H, Rengarajan V, Zwieback I, Ruland G, Crippa D, Mauceri M, Calabretta M and Messina, Mater. Sci. Semicond. Process. 135 (2021) 106088.

G. J. Hu, G. L. Zhong, X. X. Xiong, H. D. Li, H. Y. Shao, L. B. Zhao, X. M. Li, X. L. Yang, X. F. Chen, X. J. Xie, Y Peng, G. J. Yu , X. B. Hu, X. G. Xu, Vacuum 222 (2024) 112961.

S. T. Zhang, G. Q. Fu, H. D. Cai, J. Z. Yang, G. F. Fan, Y. Y. Chen, T. Li and L. L. Zhao, Materials 16 (2023) 767.

Y. X Cui, X. B. Hu, K. Yang, X. L. Yang, X. J. Xie, L. F. Xiao and X. G. Xu, Cryst. Growth Des. 15 (2015) 3131-3136.

H. D. Li, X. L. Yang, X. C. Jiang, H. Y. Shao, G. J. Hu, X. M. Li, Y. Peng, X. F. Chen, X. B. Hu, X. J. Xie, G. J. Yu and X.G. Xu. Phys. Scr. 99 (2024) 0959a6.

B. Kallinger, P. Berwian, J.Friedrich, G. Müller, A. D. Webe, E. Volz, G. Trachta, E. Spiecker, B. Thomas, J. CRYST. GROWTH. 349 (2012) 43-49.

X. S. Liu, R. Wang, J. R. Zhang, Y. H. Lu, Y. Q. Zhang, D. R. Yang and X. D. Pi, J. Phys. D: Appl. Phys. 55 (2022) 334002.

S. O Lu, B. J Xu, Y. Z. Wang, H. Y. Chen, W. Hang, R. Wang, J. L. Yuan, X. D. Pi, D. R. Yang and X. F. Han, CrystEngComm. 26 (2024) 2143.

S. S. Hu, S. Fang, Y. F. Liu, Q.Y. Cheng, H. Y. Peng, Z. Y. Chen, Y. H. Gao, C. Gao, B.Raghothamachar and M. Dudley, Mater. Sci. Forum, 1089 (2023) 45-50.

S. O. Lu, B. J. Xu, L. L. Xuan, X. D. Pi, D. Yang and X. F Han, CrystEngComm, 26 (2024) 6244.

J.Q. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quas and I. Manning, J, Electron. Mater. 46 (2017) 2040.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 33-38

doi: 10.4028/p-epPB1m

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2026-01-14

Accepted:
2026-02-23

Online:
2026-05-18

DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

Rosine Coq Germanicus 1,a* and Gabriel Ferro 2, b

¹Normandie Univ, Ensicaen, Unicaen, CNRS, CRISMAT UMR6508, 6 Bvd Marechal Juin, Caen, France

2 Laboratoire des Multimatériaux et Interfaces, CNRS UMR5615, Université Claude Bernard Lyon1, 6 rue Victor Grignard, 69622 Villeurbanne, France

a* rosine.germanicus@unicaen.fr, b gabriel.ferro@univ-lyon1.fr

Keywords: 4 H -SiC, surface structuring, macrostepped morphology, AFM, SSRM, sMIM.

Abstract

Local electrical properties of a 4 H -Silicon Carbide SiC(0001) 4∘ off macrostepped surface, obtained after liquid Si melting in a SiC/Si/SiC sandwich configuration, are investigated by Atomic Force Microscopy (AFM) in both DC and RF modes. On the same sample, macrosteps that are wide enough for allowing spatial resolution of the signal from terraces and step risers, but also some unreacted areas with standard flat surface (without macrosteps) are characterized. Scanning Spreading Resistance (SSRM, DC mode) reveals homogeneous conductivity on the wide terraces of the 4H−SiC(0001) macrosteps. On unreacted areas, which contain many step risers, the resistance is found higher than on the wide terrasses but it is also noisier. In addition, the AFM-RF scanning Microwave Impedance Microscopy (sMIM) mapping confirms the previous results by revealing lower conductivity on the unreacted areas than on the terraces of the macrosteps. Based on these results, some points defects located at the step risers which contribute negatively to the electrical properties of 4H−SiC(0001) surface are identified and electrically characterized.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

In 4H-SiC(0001) MOSFETs, the channel mobility can be limited by the electrically active defects at the SiO2/SiC interface [1]. Some experimental studies suggest that these defects tend to localize at the step edges of the step-and-terrace surface structure generated by the use of 4∘ off-axis crystals [24]. The separation between the effect of step risers and terrasses was possible thanks to the demonstration of macrostepping control of 4H−SiC(0001)4∘ off surface using liquid Si melting in a SiC/Si/SiC sandwich configuration [5, 6]. These results were obtained by using spatially resolved optical responses, not directly related to the electrical properties of the presence of defects at the step risers. In fact, the local electrical impact of these defects remains to be characterized, a crucial factor that can contribute to elucidating and understanding the origin of the low channel mobilities in 4 H SiC MOSFETs.

In this paper, electrical properties of a 4H−SiC(0001)4∘ off macrostepped surface are investigated by Atomic Force Microscopy (AFM) to reveal local electrical properties as a function of the surface morphology. Two complementary AFM electrical modes are applied to explore the surface properties: the widely used Scanning Spreading Resistance (SSRM) mode, which is a DC mode [7], and the more original scanning Microwave Impedance Microscopy (sMIM) mode, which is a RF AFM-mode [8].

AFM Electrical Modes and the Macrostepped SiC Sample

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

AFM measurements were conducted on a Bruker ICON Dimension AFM, with Scanning Spreading Resistance (SSRM) mode and scanning microwave impedance microscopy (sMIM). SSRM is based on the local electrical conduction of the current between a conductive AFM tip and the sample when a VDC bias is applied. In fact, during this electrical contact mode, a conductive AFM
tip contacts the surface, forming a nano-Schottky junction. A logarithmic amplifier records the current from the tip through the sample to the back contact under an applied DC bias (Fig. 1). Using ultra-hard tips (like doped diamond tip) prevents tip deformation and ensures reliable data.

The scanning Microwave Impedance Microscopy (sMIM) is an AFM-RF mode, based on the interaction of an incident 3 GHz microwave signal with the studied surface [6]. The sMIM mode uses this incident RF microwave interacting with the surface, requiring no electrical contact with the AFM chuck. This mode simultaneously maps the surface topography and local electrical properties of the probed materials, producing four channels: topography, deflection, sMIM-C and sMIM-R signals (Fig. 2). The two sMIM signals correspond to the real and imaginary parts of the tip-sample admittance changes.

[picture]

Fig. 1. Schematic of a Scanning Spreading Resistance (SSRM) mode based on an AFM.

Fig. 1. Schematic of a Scanning Spreading Resistance (SSRM) mode based on an AFM.

[picture]

Fig. 2. Schematic of a scanning Microwave Impedance Microscopy (sMIM) mode based on an AFM.

Fig. 2. Schematic of a scanning Microwave Impedance Microscopy (sMIM) mode based on an AFM.

The fabrication procedure for obtaining a macrostepped surface is described in details in ref [4-6]. The sample is obtained from a SiC (wafer)/ Si(30μ m)/SiC (wafer) sandwich stack treated at 1550∘C for 1 h . The vertical thermal gradient naturally forming inside the stack generates a carbon transport through the 30μ m thick liquid Si , from the bottom SiC wafer (hot) to the top SiC wafer (cold). This leads to the formation of parallel macrosteps on the dissolved (cold) surface (Fig. 3.a). Note that it may leave some so-called unreacted areas, denoted A in Fig. 3.b, which correspond to local zone
where the surface did not evolve yet to macrosteps despite being subjected also to dissolution. Though longer treatment times than 1 h allows eliminating these unreacted areas, we used here only 1 h treatment in order to take advantage of the presence of both types of areas (unreacted (A) and macrosteps (B)) in the same AFM scans for proper comparison of their local electrical properties.

[picture]

Fig. 3. SiC macrostepped surface a) SEM view of the SiC surface after thermal treatment and b) 3D view of the AFM topography.

Fig. 3. SiC macrostepped surface a) SEM view of the SiC surface after thermal treatment and b) 3D view of the AFM topography.

Results: Electrical AFM Mappings

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

The AFM height profile (Fig. 4.a) along one line allows easy identification of such unreacted area (A) when comparing to the adjacent macrosteps (B) displaying regular altitude increase and decrease. In order to probe local resistance of the SiC , a conductive diamond coating tip is used in contact with the SiC surface (Fig. 4.a). Prior to SSRM scanning, electrical AFM spectroscopy tests were carried out to determine the optimum VDC values for measuring the current flowing through the nanoSchottky contact between the conductive tip and the sample in passing mode. For this sample an optimum VDC was determined at -7 V applied to the sample. Using this optimum value of VDC, the recorded SSRM mapping is shown in Fig. 4.b. A measured resistance profile line is reported in the SSRM map. While resistance is homogeneous on the wide terraces of the macrosteps (location B), the electrical signal is noisier for the unreacted area (A). In addition, the average resistance looks higher in area A than in area B. The pixel histogram analysis of the measured resistances, reported in Fig. 4.d, for both areas confirms this trend. For the macrosteps (B), the mean resistance is log(R)=7.1Ω with a standard deviation of 0.2Ω, whereas for areas unreacted the distribution of resistances shows an average resistance about log(R)=7.4Ω with a standard deviation of 0.3Ω. Some pixels indicate resistances of up to log(R)=8.5Ω. Note that, since the SSRM mode is performed in contact mode and, due to the sharp geometry of the 4H−SiC(0001)4∘ off macrostepped surface, the systematic resistance increase at step riser can be attributed to the effective tip-sample contact, which becomes very weak at the extremity of the step. The SSRM measurements indicate that, when the probe is positioned on zone A, the current flow between the tip and the sample is significantly hindered. The measured resistance comprises the tip resistance (approximately 103Ω ) and the resistance of the back contact between the sample and the AFM chuck. For the entire scanned area, these two contributions remain constant; thus, any variation in the measured resistance reflects differences in the local electrical properties. To confirm these results, sMIM method is also used.

[picture]

Fig. 4. DC electrical conduction by AFM-SSRM, VDC=−7 V is applied to the sample: a) topography of the scanned surface 25μ m×25μ m,512×512 pixels, b) measured log(R) cartography by SSRM and c) pixel histograms of log(R) on the areas A and B.

Fig. 4. DC electrical conduction by AFM-SSRM, V D C = − 7 V is applied to the sample: a) topography of the scanned surface 25 μ m × 25 μ m , 512 × 512 pixels, b) measured log ( R ) cartography by SSRM and c) pixel histograms of log ( R ) on the areas A and B.

[picture]

Fig. 5. RF electrical conduction by AFM-sMIM, a) topography of the scanned surface 20μ m×20μm,512×512 pixels, b) measured sMIM-C cartography.

Fig. 5. RF electrical conduction by AFM-sMIM, a) topography of the scanned surface 20 μ m × 20 μ m , 512 × 512 pixels, b) measured sMIM-C cartography.

When sMIM mapping is performed on the 4H−SiC(0001) macrostepped surface, unreacted areas (A) and macrosteps (B) can be also identified (Fig. 5.a). Based on the interaction of the incident microwave signal with the surface and subsurface of the material, sMIM is sensitive to the RF conductivities of a nanoscale volume of material beneath the shielded tip. In Fig. 5.b, the sMIM-C signal (imaginary part of the complex impedance, measured after a calibration step) is related to the relative electrical capacitance of the material underneath the AFM nano-waveguide tip. sMIM results shows that the unreacted areas (A) are less conductive than the terraces of the macrosteps (B) which correlates well with the SSRM results.

Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

From the results obtained, a clear correlation between the local electrical conduction properties both in DC (SSRM) and in RF (sMIM) based on an AFM is demonstrated: unreacted areas present a higher and noisier local resistance than the macrosteps. As schematized in Fig 6, the main difference between unreacted areas and macrosteps is the density of step risers at the surface: it is much higher on unreacted areas. Then step risers can contains defects that negatively affect the electrical properties of 4H−SiC surface.

[picture]

Fig. 6. Cross sectional schematic view of the 4H−SiC(0001)4∘ off macrostepped sample surface showing after liquid Si melting i) an unreacted area (A) with a high density of step risers and ii) macrosteps (B) with ideally no step riser except at their extremity.

Fig. 6. Cross sectional schematic view of the 4 H − S i C ( 0001 ) 4 ∘ off macrostepped sample surface showing after liquid Si melting i) an unreacted area (A) with a high density of step risers and ii) macrosteps (B) with ideally no step riser except at their extremity.

Conclusion

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

Local electrical properties of a 4 H -Silicon Carbide SiC(0001) 4∘ off macrostepped surface, obtained by structuring using a SiC/Si/SiC sandwich with a liquid Si interlayer, are probed with two AFM based modes. The DC mode, SSRM, reveals that the local resistance of the unreacted areas is higher and noisier compared to the macrostepped areas. The RF mode, sMIM, confirms this trend with a lower conductivity for the unreacted area. These investigations demonstrate the correlation between surface morphology of the 4 H -Silicon Carbide SiC(0001)4∘ off macrostepped and electrical behavior, providing complementary insight into local transport mechanisms of the SiC at the nanoscale.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

P. Fiorenza et al., "Electron trapping at SiO2/4H−SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis," Nanotechnology, vol. 29, no. 39, p. 395702, Jul. 2018, doi: 10.1088/1361-6528/aad129.

J. Woerle et al., "Two-dimensional defect mapping of the interface," Phys. Rev. Mater., vol. 3, no. 8, p. 084602, Aug. 2019, doi: 10.1103/PhysRevMaterials.3.084602.

M. Camarda, J. Woerle, V. Souliere, G. Ferro, H. Sigg, U. Grossner, and J. Gobrecht, Analysis of 4HSiC MOS Capacitors on macro-stepped surfaces, Mater. Sci. Forum, 897, (2017), 107110, doi: 10.4028/www.scientific.net/MSF.897.107.

N. Alyabyeva et al., "Nanoscale Mapping of Sub-Gap Electroluminescence from StepBunched, Oxidized 4H-SiC Surfaces," physica status solidi (b), vol. 260, no. 5, p. 2200356, 2023, doi: 10.1002/pssb. 202200356.

Y. Jousseaume et al., "Controlled Macrostepping of Si-Face off over a Large Area via Liquid Si-Induced Reconstruction," Materials Science Forum, vol. 1089, pp. 9-14, 2023, doi: 10.4028/p-5p6o3j.

Y. Jousseaume, P. Kumar, M. E. Bathen, F. Cauwet, U. Grossner, and G. Ferro, "Surface Structuring of Patterned Surfaces Using a SiC/Si/SiC Sandwich Approach," Materials Science Forum, vol. 1124, pp. 7-12, 2024, doi: 10.4028/p-auZ0OI.

P. Fiorenza et al., "Complementary Two Dimensional Carrier Profiles of MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy," Solid State Phenomena, vol. 358, pp. 45-49, 2024, doi: 10.4028/p-9EfKbt.

R. C. Germanicus, T. Phulpin, K. Niskanen, A. Michez, and U. Lüders, "AFM-sMIM Characterization of the Recombination-Enhancing Buffer Layer for Bipolar Degradation Free SiC MOSFETs," Solid State Phenomena, vol. 361, pp. 85-91, 2024, doi: 10.4028/p-hUPMo0.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 39-44

doi: 10.4028/p-SZxKD4

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

N. Piluso 1,a*, C. Calabretta 1, b, F. Vento 1,c, R. Anzalone 1, d, C. Nania 1,e, D. Raciti 1,f, A. Rossitto 1, g, A. Lombardo 1, h, M. Coppola 1,i, A. Cannizzaro 1,j, A. Severino 1,k, G. Arena 1,l, M. M. Salamone 2, m, F. Giuffrida 2,n, L. Barbisan 2,o, P. Sharma 2,p, J. Per 2,q, M. K. Dayyala 2,r, P. Parisi 2, s

1 STMicroelectronics, Str. Primosole 50, 95121 Catania, ITALY

2 KLA Corporation, 1 Technology Dr, Milpitas, CA 95035, USA

a*nicolo.piluso@st.com, b cristiano.calabtretta01@st.com, c fabiana.vento@st.com, d ruggero.anzalone@st.com, e chiara.nania@st.com, f domenica.raciti@st.com, g antonio.rossitto@st.com, h alice.lombardo@st.com, i mario.coppola@st.com, jannalisa.cannizzaro@st.com, kandrea.severino@st.com,  'giuseppe-ctn.arena@st.com, m matteo.salamone@kla.com, n federico.giuffrida@kla.com, luca.barbisan@kla.com, p parikshit.sharma@kla.com, qj jeff.per@kla.com, r manojkumar.dayyala@kla.com, s  paolo.parisi@kla.com

Abstract

A new design approach for 4H−SiC material is ongoing to improve the electrical performance of devices. As seen in silicon devices, multi-epitaxial growth enhances performance by reducing on-resistance (Ron). However, devices built on SiC face several challenges due to very low dopant diffusion (e.g., phosphorus and aluminum) and defect evolution during epitaxial growth. Monitoring defects like prismatic faults, stacking faults, partial dislocations, and micropipes, especially after regrowth, is essential to assess their impact on device performance. Defects with a high killer ratio must be closely tracked to understand their evolution. In this work, we will show a method for early-stage process characterization and defect root-cause identification through sensitive inspections, effective reviews, and accurate defect classification to detect critical defects in 4H−SiC material when more than one epitaxial step is considered.

Keywords: 4H−SiC, defects, metrology, high power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

The global semiconductor market is expected to grow significantly. Considering the expansion to 8" wafer size and strong dedicated investments, the silicon carbide ( SiC ) power device market will reach $9 B by 2028 [1]. This growth is driven by rising demand for efficient power electronics in electric vehicles (EVs), renewable energy systems (smart grids), IT infrastructures (AI, data centers), and other applications, thanks to the significant benefits over traditional silicon-based semiconductors. To achieve market leadership, semiconductor companies must quickly transition to high-volume manufacturing (HVM) with Zero Defect standards [2], preventing productivity bottlenecks during fab ramp-up. Sensitive inspection, effective review, and reliable AI-based defect classification during R&D and maturity phases are critical solutions for early detection of process flaws and killer defects, determining yield and accelerating time to result (T2R).

Coupling high-quality 4H−SiC substrates with an efficient epitaxial growth process is a promising approach to enhance the performance of power electronic devices [3,4,5,6]. Optical microscopy is the most widely used method for detecting defects in this technology, and defects are classified based on size, shape, and intensity. Typical macroscopic defects on SiC material (Figure 1), easily detectable due to their size and contrast, are considered killers for devices. More challenging defects, especially those smaller than 1μ m, require advanced characterization techniques such as inline defect detection and AI-based classification.

In Table 1, defects of interest are reported along with their typical electrical behavior. Micropipes act as conductive paths, increasing leakage current and decreasing blocking voltage. The
characteristic hole that permeates the entire material, from the substrate to the epitaxy, causes a reduction in breakdown voltage and allows unexpected current to flow through the device during reverse bias. Typical hard failures are localized in active regions.

Threading Screw Dislocation (TSD) with pits generates inhomogeneities on the surface and on the gate oxide in MOSFET devices. They can cause a slight increase in leakage current and a local reduction in breakdown voltage. Additionally, oxide instability during electrical stress tests is detected. Such defects can expand under reverse bias stress, leading to hard failure of the device during standard operation.

Stacking Faults (SFs) are crystallographic defects without optical counterparts, detectable only by photoluminescence techniques. A recent and exhaustive classification is reported in [7]. Most SFs cause only a very slight increase in leakage current and are not directly connected with hard device failure. Nevertheless, if SF density exceeds a critical value, which strongly depends on the device considered, leakage current issues can become severe. In MOSFET devices, SF density should be kept below 0.5 cm−2. Additionally, Single Shockley SF ( 1 SSF ) can expand via ultraviolet irradiation [8] and/or current flow, potentially inducing bipolar degradation and hard device failure.

Morphological and extended defects are recognized as responsible for electrical hard failures. Due to their typical size and shape, they are easily detected with optical methods and screened during the Front-End process flow.

In Figure 2, the high-sensitivity inspection mode is shown, and the results reveal an improved capture rate of sub-micron defects while confirming the macroscopic defects normally tracked by standard process control solutions. Another key element is the ability to perform 100% defect sampling classification, allowing precise correlation between the results from the final electrical test and the defect typology. In Figure 3, DefectWise® high-purity and high-accuracy, fully integrated classification technology is presented.

[picture]

Fig. 1. Collection of morphological defects detected on SiC Epitaxial layer.

Fig. 1. Collection of morphological defects detected on SiC Epitaxial layer.

Table 1. SiC defects of interest.

Defect | Technique | Typical Size | Risk/Typical Failure
Micropipe | Optical microscope | ~1 μm | HIGH Electrical Destructive Failure
Threading Screw Dislocation (with superficial pit) | Scanning electron microscopy X-Ray Topography Optical Microscope + PL | < 1 μm | MID/LOW High Leakage Current and/or Oxide instability
Stacking Faults | Photoluminescence | > 1 μm | LOW High Leakage Current and/or Oxide instability
Morphological Extended Defects (Carrots, Triangles, Particles) | Optical microscope | >> 1 μm | HIGH Electrical Destructive Failure

[picture]

Fig. 2. Enhanced detection of sub −1μ m defects in next-generation PMOS devices utilizing KLA's Corp's 20x high-sensitivity inspection mode on the 8935 inspector.

Fig. 2. Enhanced detection of sub − 1 μ m defects in next-generation PMOS devices utilizing KLA's Corp's 20x high-sensitivity inspection mode on the 8935 inspector.

[picture]

Fig. 3. Example of classification of common defects in SiC by using KLA's AI-based solution (DefectWise ® ).

Fig. 3. Example of classification of common defects in SiC by using KLA's AI-based solution (DefectWise ® ).

Experimental

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

Multi-epitaxial growth is a strategy used to improve device performance, particularly in minimizing on-resistance (Ron) [9,10,11], thanks to superjunction-like drift layers. While this approach is common in silicon devices, SiC devices face challenges due to the low diffusion coefficients of dopants (e.g., phosphorus and aluminum) and the evolution of crystal defects during the multi-epitaxial process [12,13,14].

In Figure 4, a sketch of the epitaxial stack sent for inspection is shown. The first thick epitaxial layer, generally ranging from 5 to 10μ m, underwent ion implantation and was then epitaxially regrown with a thin layer ranging from 1 to 2μ m. Dedicated inspections were conducted to explore the interface quality between the epitaxial layers. The results (not presented here) showed a smooth interface free from defects generated by ion implantation.

[picture]

Fig. 4. Sketch of epitaxial stack underwent to highly sensitive mode inspection.

Fig. 4. Sketch of epitaxial stack underwent to highly sensitive mode inspection.

In Figure 5, the typical increase in defectivity, depicted here as Defect Die percentage within a 5×5 mm grid, is shown. This increase is mainly due to the expansion of defects already present on the surface of the first epitaxial layer, new defects caused by surface contamination, and, to a minimal extent, dislocations propagated along the first epitaxial layer (e.g., basal plane dislocations) that convert into extended defects during the second epitaxial layer step (typically stacking faults and carrots).

[picture]

Fig. 5. Typical Increasing of Defect Die percentage (average ~4% ) due to multi step epitaxial layer by considering three different substrate quality levels.

Fig. 5. Typical Increasing of Defect Die percentage (average ~ 4 % ) due to multi step epitaxial layer by considering three different substrate quality levels.

Figure 6 shows the evolution of defects from Epil to Epi2. To define the killer ratio (KR) of structured defects, it is necessary to detect and monitor defects after regrowth. Studies on prismatic defects and complex (carrots) stacking faults (Figure 6 A, C) provide insights into how defects propagate and the potential degradation of device performance. Additional partial dislocations after regrowth (Figure 6 B, D) must be detected, classified, and monitored to assess their impact on final electrical performance and process flow. Despite the limited size increase after the regrowth process, micropipes (Figure 6E,F ) are known to have a KR close to 100%, and their evolution is fundamental to identifying crystallographic changes and quantifying the portion of the surface impacted by their enlargement.

[picture]

Fig. 6. Evolution of defects from the epitaxial layer (A, C, E) to thin epitaxial regrowth (Fig. B, D, F). In detail: evolution of prismatic (A→B), complex Stacking Faults (C→D) and micropipe (E→F).

Fig. 6. Evolution of defects from the epitaxial layer (A, C, E) to thin epitaxial regrowth (Fig. B, D, F ) . In detail: evolution of prismatic ( A → B ) , complex Stacking Faults ( C → D ) and micropipe ( E → F ) .

The most relevant results were the efficient detection of submicron defects by optical means in highsensitivity mode, as shown in Figure 7. Among all the submicron defects detected, the Threading Screw Dislocation (TSD) stands out due to the importance of screening such defects. Literature works [15] confirm that pits or nano-pits on the epitaxial surface, caused by the propagation of dislocations such as TSD, negatively affect device performance.

Usually, high leakage current in diode devices corresponds exactly with the presence of pits. In the case of MOSFET devices, the failure is even more severe, resulting in gate oxide breakdown and device burnout.

[picture]

Fig. 7. Sub-micron defects detected by High Sensitivity mode inspection and related optical (Left) and SEM (right) review.

Fig. 7. Sub-micron defects detected by High Sensitivity mode inspection and related optical (Left) and SEM (right) review.

The KLA 8935 high-throughput, high-sensitivity, top-side inspection system is designed for 150300 mm bare and patterned wafers. It features a high-resolution, high-numerical-aperture optical microscope paired with an LED light source. A key capability of the system is its concurrent brightfield (BF) and darkfield (DF) inspection, which significantly expands its range of applicable use cases. The 8935 can be integrated with the DefectWise® deep-learning AI solution, enabling realtime 100% defect classification with high purity and accuracy.
The Micro-SR™ fully automated optical review system operates in synergy with the 8 Series inspection systems. It is designed for high-throughput, high-resolution, high-quality image acquisition of sub-micron defects, supporting efficient defect review and analysis.
The eDR7380™ electron-beam wafer defect review and classification system provides highresolution images of defects and uses a machine-learning automatic defect classifier to produce an accurate defect Pareto. The data generated by the eDR7380 enables faster defect sourcing in development, quicker excursion detection, and more accurate, actionable data during production. The defect information produced by the eDR7380 helps accelerate time to market for multiple bare substrate types (SiC, GaN, glass, sapphire, POI piezoelectric-on-insulator, etc.) and device types (power, LED, photonics, RF, MEMS, etc.). Built on a flexible, configurable platform, the eDR7380 reviews and classifies a wide range of defect sizes and types for multiple wafer sizes ( 150−300 mm ) and wafer thicknesses (180−1500μ m).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

A new multi-epitaxial stack has been presented, and each layer is fully characterized. The use of higher magnification (20x) inspection mode significantly enhances the detection of sub-micron defects, while AI-based classification improves the accuracy and consistency of defect identification. This strategy enables effective tracking of defect evolution throughout the process.
Improvement in defect detection is mandatory in multi-epi technology because new defects triggered by the second epitaxial layer step can exhibit atypical and challenging characteristics from a metrology point of view, mainly due to the very low thickness of the second grown layer, which leads to very small defect sizes. TSDs that do not generate pits on the surface of the first epitaxial layer can do so on the surface of the second epitaxial layer, with a relatively small size ( <1μ m ). SFs can be generated starting from BPDs that propagate through the first epitaxy up to the surface and appear very small in photoluminescence channels ( <10μ m ).

Correlation between electrical testing and defect mapping highlights the importance of identifying high-impact defects, such as micropipes, which exhibit a strong killer ratio. The combination of highresolution inspection, inline review, and precise classification supports the fine-tuning of nextgeneration power MOSFET development. Overall, this approach accelerates time-to-result while ensuring compliance with demanding industry standards.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

https://www.yolegroup.com/product/report/sic-transistor-comparison-2023/.

R. Raina et al., Achieving Zero-Defects for Automotive Applications, 2008 IEEE International Test Conference, (2008), doi: 10.1109/TEST.2008.5483611.

D. Raciti, R. Anzalone, M. Isacson, N. Piluso, A. Severino, Defect and Diffusion Forum, Vol 434, pp 117-121.

N. Piluso, et. al., IEEE International Reliability Physics Symposium (IRPS), pp 1-5 (2025).

N. Piluso et. al., Materials Science Forum, 963, pp 91-96 (2019).

T. Kimoto, H. Watanabe, Applied Physics Express 12, 120101 (2020).

M. Na. et al, Materials Science in Semiconductor Processing 175 (2024) 108247.

I. Yukari, et. al., Journal of Applied Physics 123(22):225101 (2018).

R. Ghandi et. al., Proceedings of the International Symposium on Power Semic. Devices & ICs, (2023).

C. Ma et al., Chao Ma et al 2024 J. Semicond. 45111301.

K. Ryoji et al., 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD, IEEE, pp. 39-42, 2019.

RT. Leonard et al., Materials Science Forum, Trans Tech Publications Ltd, (2017).

C. Langpoklakpam et al., Crystals, Vol 12, n. 2, p. 245 (2022).

A. Severino et al., Materials Science Forum, 963, pp. 407-411 (2019).

T. Kimoto, Japanese Journal of Applied Physics 54, 040103 (2015).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 45-51

doi: 10.4028/p-xjp7QK

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Zimo Yuan 1,a, Alex Metreveli 1, b, Lasse Vines 2,c, Orazio Samperi 2, d, Misagh Ghezellou 3,e, Jawad Ul-Hassan 3,f and Anders Hallén 1, g

1 KTH Royal Institute of Technology, SE 16440 Kista, Sweden

2 Centre for Material Science and Nanotechnologies, University of Oslo, 0373 Oslo, Norway

3 Department of Physics, Chemistry and Biology, Linköping University, SE 58183 Linköping, Sweden

a  willinf347@gmail.com, b  alexmet@kth.se, classe.vines@fys.uio.no, d  oraziosa@smn.uio.no, e  misagh.ghezellou@liu.se, jawad.ul-hassan@liu.se, g  ahallen@kth.se

Keywords: boron, deep levels, SRH recombination, thermodynamics.

Abstract

In this paper, the temperature dependence of charge carrier lifetimes in n-type 4H-SiC epitaxial layers is studied in a temperature range of 300−500 K. It is assumed that shallow (B) and deep (D) boron-related defects are the dominating lifetime killers in as-grown epitaxial layers. The thermodynamic behavior of these two types of defects is obtained from DLTS measurements, and implemented in the Shockley-Read-Hall (SRH) model to calculate lifetimes, using Gibbs free energies to describe the accurate temperature dependence for capture and emission processes of the defects. Calculation results show that the lifetimes controlled by shallow boron defects increase with increasing temperature, while D-defects give the opposite temperature dependence. The theoretical results are also compared to measured data from 10kV4H−SiC PiN-structures, showing that the temperature dependence of the effective lifetime can be changed by proton implantations, which gives rise to additional Z1/2 defects that have similar temperature effects on lifetimes as D-related defects.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Charge carrier lifetime is an important parameter for bipolar 4H−SiC devices, since it has a large impact on device losses and switching speed [1]. It was previously acknowledged that the point defects, especially the carbon vacancies ( Z1/2 centers), have a dominant effect on controlling lifetimes in 4H−SiC. Recent research, however, has found that the measured lifetimes are not proportional to the abundance of Z1/2 at low concentration levels, suggesting that other defects might affect the lifetimes [2]. Boron-related defects [3,4] in the lower half of the 4H−SiC bandgap have recently been suggested to control the carrier lifetimes at low Z1/2 levels from deep level transient spectroscopy (DLTS) analyses, namely the shallow (B) and deep boron (D), respectively. These defects originate from boron contamination incorporated during growth, and can sometimes have higher concentrations than Z1/2 [5].

One way to assess the lifetime is by calculations using the Shockley-Read-Hall (SRH) model, in which the bandgap energies, trap concentrations and capture rates of traps are obtained from DLTS measurements. This method also allows the temperature dependence of lifetimes to be determined, but it is also important to use the correct thermodynamic model for the capture and emission processes. This means that the Gibbs free energy, ΔG=ΔH−TΔS, should be used, where H is the enthalpy, T is the absolute temperature and S is the entropy relevant for the carrier transitions [6, 7]. The correct temperature dependence of the carrier lifetime is essential for device modelling, since the 4H−SiC devices operate within a wide temperature range. Although the lifetimes of 4H−SiC devices can be measured experimentally by, for instance, open voltage circuit decay (OCVD) and photoluminescence (PL), there is a need to derive the lifetimes from physical models based on the different recombination centers in the material.

In this work, we extend the SRH model to study the temperature dependence of lifetimes theoretically, assuming that the boron-related defects, the B- and D-defects, are the lifetime killers.

Thermodynamically based properties of these defects are collected from DLTS measurements [2,8], and are implemented into the SRH model. The results will also be compared to experimental forward IV data of 10 kV 4H-SiC PiN diodes, including also proton implanted devices adding high local concentration of carbon vacancies.

Models

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Based on statistics of carrier capture and emission from deep bandgap states, the SRH model is used to calculate the total, effective charge carrier lifetime, τ, summed up over γ different types of defects present in the material [9,10]:

τ−1=∑j=1γ(n0+p0+Δn)NTjcnjcpjcnj(n0+Δn+nj)+cpj(p0+Δn+pj)(1)

where n0 and p0 are carrier concentrations at thermal equilibrium, Δn is the excess carrier concentration (assuming charge neutrality, Δn=Δp ) and NTj is the concentration of the jth  type of defect.

Capture coefficients cn and cp can be calculated using the thermal velocity v and capture cross section σ for electrons and holes, respectively:

cn,p=σn,pvn,p(2)

where the thermal velocities are obtained from the absolute temperature T and the effective masses mn* and mp*. The Boltzmann constant is designated by k :

vn,p=3kTmn,p*(3)

Concentrations nj and pj represent the carrier concentrations when the Fermi level is aligned with the energy position of corresponding defects, calculated with Eq. 4 and Eq. 5.

nj=NCexp(−EC−ETjkT)pj=NVexp(−ETj−EVkT)

(4)(5)

where NC and NV are the effective density of states in the conduction band and valence band, and are both temperature dependent. It should also be noted nj and pj are now calculated with the traps bandgap positions given by the Gibbs free energies in order to describe the proper thermodynamic behavior of electronic transitions from trap to band edges defects [6,7]. The Gibbs free energy G includes both the enthalpy H and entropy S of the electronic transitions and is given by Eq. (6).

ΔG=ΔH−TΔS(6)

Concentrations nj and pj are therefore stated as:

nj=NCexp(−HC−HTjkT)exp(SC−STjk)pj=NVexp(−HTj−HVkT)exp(STj−SVk)

(7)(8)

DLTS measurements offer the possibility to obtain defect parameters that can be implemented into the SRH model to calculate temperature-dependent lifetimes. Following Peaker et al. [11], the activation energy Ea and the apparent capture cross section, σa, can be extracted and, through capture
rate measurements, the capture energy barrier Eσ and the true capture cross section σ∞ can also be obtained.

The enthalpy for the given defect ΔH is calculated by:

ΔH=Ea−Eσ(9)

The entropy ΔS is calculated by:

ΔS=klog(σaσ∞)(10)

Concentrations nj and pj calculated with Gibbs free energies are thus available using Eq. (6), Eq. (9) and Eq. (10).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Figure 1 gives a simplified band diagram of 4H−SiC, with the energy positions of three significant traps that are active in the control of charge carrier lifetimes. The double acceptor trap, Z1/2, which has been proved to originate from carbon vacancies, is located about 0.67 eV [13] below the bottom of the conduction band. Two boron-related minority traps, shallow B and deep D -center, are closer to the valence band. It has been found that shallow boron, B , and the deep boron, D -center, are assigned to boron impurities occupying the silicon site and carbon site in the SiC lattice, respectively, which leads to completely different energy levels and thermodynamic properties. It should also be noted that associated DLTS peaks ( B1, B2,D1 and D2 ) from hexagonal and cubic sites [8,13] are both observed for these two traps, and they will be merged in this work. The energy positions of shallow B and D-centers summarized from the literature are also given in Fig. 1. Table 1 summarizes the recent measured trap parameters [8] that will be used in this work. Since the 4H−SiC lattice contains both hexagonal and cubic sites with slightly varying bandgap positions, and the two versions of the shallow boron, we have used the dominating level in these calculations. In this work, we mainly discuss B- and D-related defects, which correspond to the first and second type of defects in Eq. (1).

[picture]

Fig. 1. Three energy levels that are expected to compete for the control of the charge carrier lifetime in low doped 4H−SiC : the majority trap Z1/2 and the minority traps shallow B and D -centers. The energy positions of the dominating levels are given in the figure (not in scale).

Fig. 1. Three energy levels that are expected to compete for the control of the charge carrier lifetime in low doped 4 H − S i C : the majority trap Z 1 / 2 and the minority traps shallow B and D -centers. The energy positions of the dominating levels are given in the figure (not in scale).

Table 1. Thermodynamic parameters of shallow B and D-center.

Trap | Ea (eV) | Eσ (eV) | σa (cm²) | σ∞ (cm²)
B | 0.27 | 0.10 | 2.2×10⁻¹⁴ | 1.87×10⁻¹⁴
D | 0.57 | 0.05 | 3.93×10⁻¹⁴ | 1.04×10⁻¹⁶

A 10kV4H−SiC PiN diode is used as an example to study the lifetimes in the drift region. The diode has a 120μ m thick drift layer, with a doping concentration of 2×1014 cm−3. The SRH lifetimes for shallow B and D-center are computed under high and low injection, with an excess carrier concentration of 3×1016 and 1×1012 cm−3, respectively. The temperature range is from 298 to 498 K ,
covering a substantial part of the operation range of 4H−SiC devices. It should be noted that only the hole capture process of the minority traps has been measured, giving the hole capture cross section σp(σp=σa), enthalpy HTj−HV, and entropy STj−SV that can be used to calculate concentration pj, seen in Eq. (8). The electron transport to these defects has not been measured, and therefore we set σn=σp to estimate the electron cross section. The Gibbs free energy term in Eq. (7), GC−GTj, is assumed to be (GTj−GV)·(EC−ET)/(ET−EV). These assumptions do not affect the calculations, since the concentration nj for both B- and D-related defects are negligible within the previously mentioned temperature range.

To start with, we analyze the shallow B level. The term n1 is negligible due to large GC−GT1. The term p1 gives a concentration within the range of 1017 cm−3, far more than both Δn and n0. The approximate high-injection and low-injection SRH lifetime from shallow B, with concentration NT1, are therefore given by Eq. (11) and Eq. (12).

τB( high )≈1NT1cn1+cp1(1+p1Δn)cn1cp1τB( low )≈1n0NT1p1cn1

(11)(12)

Similarly, for the D-center as the second kind of defects with concentration NT2. With the parameters in Table 1, the term p2 is now about 10−20% of n0, meaning that p2 can also be neglected under a high injection. The corresponding approximate high-injection and low-injection lifetimes are given by Eq. (13) and Eq. (14).

τD( high )≈1NT2(1cn2+1cp2)τD( low )≈1n0NT2cn2n0+cp2p2cn2cp2

(13)(14)

Note that all the approximate lifetimes from Eq. (11) to Eq. (14) are separated to two terms, one constant term (including n0 and defect concentrations) and one temperature-dependent term. Figure 2 compares only the temperature-dependent terms for the shallow B and D-center. It can be seen that both the high-injection and low-injection term for shallow B are increasing with temperature, indicating that a higher temperature always increases the shallow B-related SRH lifetime, regardless of the injection level. Meanwhile, an opposite trend can be found for D-center.

[picture]

Fig. 2. The temperature dependent part of the SRH lifetimes of shallow B and D-center, at highinjection ( Δn=3×1016 cm−3 ) and low-injection ( Δn=1×1012 cm−3 ). (Note that the actual lifetime is not plotted, but just the temperature dependent part of equations 11-14, which also leads to different units for high and low injection levels.) Shallow B and D-center related defects have an opposite temperature dependence.

Fig. 2. The temperature dependent part of the SRH lifetimes of shallow B and D-center, at highinjection ( Δ n = 3 × 10 16 c m − 3 ) and low-injection ( Δ n = 1 × 10 12 c m − 3 ). (Note that the actual lifetime is not plotted, but just the temperature dependent part of equations 11-14, which also leads to different units for high and low injection levels.) Shallow B and D-center related defects have an opposite temperature dependence.

The effective SRH lifetime can now be calculated from Eq. (1). The temperature dependence of the effective lifetime is therefore strongly dependent on which type of trap dominates, i.e. the ratio of concentrations NT1 and NT2. Figure 3 shows the calculated high-injection effective lifetimes with different NT1/NT2, where NT2 is always set to a constant value ( 3×1012 cm−3 ). The concentration of Bdefects, NT1, has to be at least three times NT2 to counteract the temperature dependence of the Dcenter. A special trend is also observed when NT1 is equal to, or slightly higher than NT2, that the effective lifetime first increases and then decreases. The temperature when this happens is between 400 and 500 K .

[picture]

Fig. 3. Calculated effective SRH lifetimes with different concentrations of shallow B-related defects (NT1). The excess carrier concentration is 3×1016 cm−3. The effective lifetime decreases with increasing temperature when the D-defects have a higher concentration ( NT2 ) and increases with increasing temperature if B-defects dominate. When the ratio NT1/NT2 is between 1 and 2 (dotted lines), the effective lifetime will first increase and then slightly decrease as temperature increases.

Fig. 3. Calculated effective SRH lifetimes with different concentrations of shallow B-related defects ( N T 1 ) . The excess carrier concentration is 3 × 10 16 c m − 3 . The effective lifetime decreases with increasing temperature when the D-defects have a higher concentration ( N T 2 ) and increases with increasing temperature if B-defects dominate. When the ratio N T 1 / N T 2 is between 1 and 2 (dotted lines), the effective lifetime will first increase and then slightly decrease as temperature increases.

Figure 4 shows the lifetime as a function of injection level with the temperature as a parameter. The concentration of the B-defects is much higher ( 6.7 times) than D-defects, and the same trend described previously can be found when the injection level is higher than 1×1016 cm−3. On the lowinjection level side, the effective lifetime decreases from 298 to 398 K , and then increases. It can also be found that the low-injection effective lifetime is much higher than high-injection lifetime above 473 K , which is due to the large values of pj. From fitting measured forward bias IV characteristics with TCAD simulations, it is possible to estimate the change in lifetimes with temperature. The forward IV characteristics of 10 kV PiN diodes [14] used in this work are measured from 298 to 373 K , with a temperature step of 25 K . The diode is also modelled in Sentaurus TCAD.

Figure 5a shows the measured forward IV characteristics (solid lines) of a typical 10 kV diode. The characteristics are shifting to lower voltages, indicating an increase in lifetime with increasing temperature. This is partly due to a reduction of the bandgap at higher temperatures, but the charge carrier lifetimes are also adjusted in the simulations to fit the measured data (dotted lines). For this diode, the drift layer high-injection level lifetimes (the sum of the majority and minority lifetime) used in the simulations are 2.2,2.6,3 and 3.5μ s, corresponding to 298,323,348 and 373 K . This indicates that B -defect might be the dominant defect in the diode sample.

Figure 5b compares the measured IV characteristics of three samples, two of which have been irradiated with 2.5 MeV protons (dose: 1×109 and 1×1010 cm−2 ) to introduce the intrinsic defect Z1/2 in the drift layer with a local peak concentration around 40μ m into the drift layer.

[picture]

Fig. 4. Calculated effective SRH lifetimes with different temperatures and injection levels. The concentration of B- and D-defects are 2×1013 and 3×1012 cm−3, respectively. The low-injection effective lifetime rapidly increases when the temperature is over 448 K due to the rapid increase of p1/2.

Fig. 4. Calculated effective SRH lifetimes with different temperatures and injection levels. The concentration of B- and D-defects are 2 × 10 13 and 3 × 10 12 c m − 3 , respectively. The low-injection effective lifetime rapidly increases when the temperature is over 448 K due to the rapid increase of p 1 / 2 .

A similar trend of lifetimes as in Fig. 5a is found for the diode irradiated with lower dose, while increasing temperature does not seem to affect lifetimes very much for the sample irradiated with higher dose. A possible explanation for such different temperature effects is the compensation effect of majority traps Z1/2 introduced by proton implantation. The activation energy of Z1/2 is larger than that of D -center, yielding a similar temperature dependence as the D -center. Proton implantations create a considerable amount of Z1/2-related defects, and thus compensate the temperature effects from B-defects.

[picture]

Fig. 5. (a) Measured and simulated forward IV characteristics of the tested diode from 298 to 373 K . The simulations are used to estimate the lifetimes from the measured characteristics. Experimental results show that increasing temperature increases lifetimes. (b) The measured IV characteristics of diode samples with and without proton implantation (2.5MeV,1×109 and 1×1010cm−2 ), giving a strongly non-uniform distribution of defects in the drift layer with a Z1/2 peak concentration of 1×1014 cm−3[1]. The temperature effects are weaker for the samples treated with proton implantation, possibly due to local compensation of Z1/2.

Fig. 5. (a) Measured and simulated forward IV characteristics of the tested diode from 298 to 373 K . The simulations are used to estimate the lifetimes from the measured characteristics. Experimental results show that increasing temperature increases lifetimes. (b) The measured IV characteristics of diode samples with and without proton implantation ( 2.5 M e V , 1 × 10 9 and 1 × 10 10 c m − 2 ), giving a strongly non-uniform distribution of defects in the drift layer with a Z 1 / 2 peak concentration of 1 × 10 14 c m − 3 [ 1 ] . The temperature effects are weaker for the samples treated with proton implantation, possibly due to local compensation of Z 1 / 2 .

Conclusion

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

In this work, we have tried to analyze the temperature dependence of charge carrier lifetimes in a lightly-doped n -type 4H−SiC epitaxial layer. It has been assumed that boron-related defects, i.e. shallow B and D -centers, are dominating the lifetimes rather than the Z1/2 centers in as-grown epilayers. The parameters of B- and D-related defects are obtained from recent DLTS measurements, and thermodynamic properties are implemented to the SRH model to calculate accurate lifetimes. The calculations show that the temperature dependence of lifetimes controlled by B- and D-related defects are opposite, and the temperature dependence of the total effective lifetime is determined by the defects with a dominant concentration. The results are also compared to measured IV characteristics of devices with varying content of Z1/2, and these measurements indicate that MeV proton implantation can counteract the intrinsic temperature dependence of lifetimes in the epitaxial layer by introducing a considerable amount of Z1/2 defects.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Z. Yuan, et al. "Localized lifetime control of 10kV4H−SiC PiN diodes by MeV proton implantation." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

M. Ghezellou, et al. "The role of boron related defects in limiting charge carrier lifetime in 4HSiC epitaxial layers." APL Materials 11.3 (2023).

T. Knezevic, et al. "Boron-Related Defects in N-Type 4H-SiC Schottky Barrier Diodes." Materials 16.9 (2023): 3347.

V. J. B. Torres, I. Capan, and J. Coutinho. "Theory of shallow and deep boron defects in 4 HSiC." Physical Review B 106.22 (2022): 224112.

M. E. Bathen, et al. "Impact of carbon injection in 4H-SiC on defect formation and minority carrier lifetime." Materials Science in Semiconductor Processing 176 (2024): 108316.

O. Engström and A. Alm. "Thermodynamical analysis of optimal recombination centers in thyristors." Solid-State Electronics 21.11-12 (1978): 1571-1576.

P. T. Landsberg, C. Rhys-Roberts and P. Lal. "Auger recombination and impact ionization involving traps in semiconductors."Proceedings of the Physical Society 84.6 (1964): 915.

O. Samperi, L. Vines, A. Hallén and M. E. Fragalà, "Charge carrier capture by prominent defect centers in ." Diffusion and Defect Data, Solid State Data. Part A, Defect and Diffusion Forum, ISSN 1012-0386, E-ISSN 1662-9507, Vol. 434, s. 173-182 (2024).

W. Shockley and W. T. Read Jr. "Statistics of the recombination of holes and electrons". Physical Review 87.5 (1952), p. 835.

R. N. Hall. "Electron-hole recombination in germanium". Physical Review 87.2 (1952), p. 387.

A.R. Peaker, V.P. Markevich, J. Coutinho, "Tutorial: Junction spectroscopy techniques and deep level defects in semiconductors", J. Appl. Phys. 123, 161559 (2018).

N.T. Son, X.T. Trinh, L.S. Lövlie, B.G. Svensson, K. Kawahara, J. Suda, T. Umeda, J. Isoya, T. Makino, T. Oshima, and E. Janzén, „Negative-U System of Carbon Vacancy in 4H-SiC“, Phys. Rev. Lett. 109, 187603 (2012).

M. E. Bathen, et al. "Dual configuration of shallow acceptor levels in 4H-SiC." Materials Science in Semiconductor Processing 177 (2024): 08360.

K. Tian, J. Xia, K. Elgammal, A. Schöner, W. Kaplan, R. Karhu, J. Ul-Hassan, A. Hallén", Modelling the static on-state current voltage characteristics for a PiN diode", Materials Science in Semiconductor Processing 115 (2020): 105097.

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The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 53-57

doi: 10.4028/p-HPx5qU

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2026-01-13

Accepted:
2026-02-23

Online:
2026-05-18

Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

Li Sun 1,2,a Xuejian Xie 1,2, b*, Xiufang Chen 1,2,c*, Xianglong Yang 1,2, d, Yan Peng 1,2,e, Xiaobo Hu 1,2,f*, Xiangang Xu 1,2, g

1 State Key Lab of Crystal Materials, Shandong University, Jinan, 250100, PR China

2 Institute of Novel Semiconductors, Shandong University, Jinan, 250100, PR China

a sdusunli@sdu.edu.cn, b xiexj@sdu.edu.cn, c cxf@sdu.edu.cn, d yangx|2016@sdu.edu.cn, e pengyan@sdu.edu.cn, f xbhu@sdu.edu.cn, g xxu@sdu.edu.cn

Keywords: Micropipe, X-ray topography, defect characterization, SiC.

Abstract

Micropipe defects in silicon carbide (SiC) materials significantly degrade the performance of SiC materials and their applications in semiconductor devices. In this study, systematic methods were utilized to characterize different micropipes in 4H−SiC. X-ray topography was employed to investigate the morphology of micropipe defects in SiC substrates and quantify their associated lattice distortion fields. Meanwhile, white light interferometry mode microscopy and inner stain were utilized to thoroughly characterize their properties. It was found that micropipes were accompanied with different size and distortion areas in SiC substrate. This work will be served as a refined characterization of micropipes and give guidance for device application for SiC substrate.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

Silicon carbide ( SiC ) has shown revolutionary potential in the field of power semiconductor devices due to its excellent properties. Micropipe defects in SiC materials are hollow tubular line defects formed during crystal growth, typically extending along the <0001> crystal growth direction. These defects significantly degrade the performance of SiC materials and their applications in semiconductor devices, leading to detrimental effects such as reduced breakdown voltage, increased leakage current, and diminished carrier mobility. [1-4] Consequently, controlling micropipe defects is critically important during the preparation of large-diameter SiC single crystals.
The influence of micropipe area in SiC crystals on device performance is comprehensive, Large-area micropipes significantly exacerbate device failure risks, particularly in high-voltage, hightemperature, and high-frequency applications. With the gradual optimization of the growth process, the current micropipe density has been greatly reduced, and the characterization of micropipes is facing the requirement of more refinement. Current characterization methods for micropipes primarily rely on various microscopy techniques: polarized transmission microscope reveals stress variations induced by micropipes, while white-light interferometry precisely identifies their hollow core positions.
In this paper, the micropipe was characterized by orthogonal polarizing microscope, white light interference microscope, X-ray topography and inner stress meter. On the premise of accurately obtaining the position of micropipe, the influence of micropipe on the distortion range of crystal was studied synchronously, which will be of great significance to further improve the quality of SiC single crystal.

Materials and Methods

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

Sample fabrication: The samples were homemade 4H−SiC single crystal with an off-axis of 4∘, which were grown by physical vapor transfer method. The growth temperature was set at about 2000∘C~2200∘C, and nitrogen gas was introduced during the growth process to obtain nitrogen doped boule. The samples all went through chemical mechanical polish (CMP) processing to remove surface scratches and other processing defects.

Characterization: For X ray topography characterization, the images were taken by reflection geometry was performed on the Cu target (λ=1.54\AA) using diffraction vectors g→=0008, using the 1.2 kWCu/ Mo rotating anode target XRT system provided by Rigaku. White light interference images were taken by microscope fabricated by Sensofar. For inner strain, SV200 wafer stress detector was used by birefringence effect of polarized light.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

Fig. 1 presented an image of micropipes acquired using an orthogonal polarization microscope by transmission mode. The dark regions corresponded to areas free of micropipes on the substrate surface, while the bright areas arised from alterations in the optical path induced by the presence of micropipes. Fig. 1a and 1b depicted regions containing a single micropipe and double micropipes, respectively. Comparative analysis clearly reveals distinct imaging characteristics between these two configurations. In the single micropipe region, the micropipe exhibits an image with cubic symmetry, consisting of three bright and three dark zones arranged symmetrically around the micropipe center. In contrast, within the double micropipe region, the micropipe images displayed significant distortion due to mutual interaction. This observation indicated the presence of interaction between adjacent micropipes, leading to synchronous modification of the lattice distortion regions associated with their existence.

[picture]

Fig. 1. Comparison single micropipe and double micropipes in polarizing microscope.

Fig. 1. Comparison single micropipe and double micropipes in polarizing microscope.

X-ray topography (XRT) is an important means to characterize lattice defects, which can effectively characterize the influence range of defects on perfect lattice.[5-6] The Burgers vectors of micropipes (MPs) are expressed as b→MP=±nc(n=3~10), whereas those of threading screw dislocations (TSDs) in SiC substrates are b→TSD =±mc(m=1,2).[7] When identifying MPs in SiC substrate using XRT systems, both MPs and TSDs coexist. The distinction between MPs and TSDs in XRT imaging arised from the inequality ||b→MP|>|b→TSD|. Fig. 2 demonstrated the contrast between MPs and TSDs in SiC substrates under g→=0008 diffraction condition. The small black dots were TSD defects, the white hollow and relatively large black dots represented micropipes, and the white area in the middle was the atomic depletion area formed by the presence of micropipes, because it cannot be imaged in XRT. Fig. 2b showed the XRT image of the double micropipe position. Typically, the double micropipe was generally formed by micropipes with different spiral properties. Located at the upper and lower ends, the two MPs interacted and gave rise to an extensive distorted area in the center that cannot be imaged by XRT, corresponding to a region where the 4 H -SiC crystal structure was disrupted. Taking dark regions in XRT images as strain-affected areas, single and double micropipe were measured as 0.44 mm2 and 1.2 mm2, respectively.

[picture]

Fig. 2. Comparison single micropipe and double micropipes in XRT.

Fig. 2. Comparison single micropipe and double micropipes in XRT.

The white light interference mode of microscope is an effective means for micropipe recognition. The white light interference mode can effectively avoid the influence of the strain factory caused by the orthogonal polarization mode of transmission mode, and more directly reflect the intrinsic characteristics of micropipe. As illustrated in Fig. 3, micropipes exhibited diverse morphologies including elliptical and irregular configurations. By extracting major and minor axis dimensions from these morphological profiles, the corresponding micropipe areas were calculated, with results summarized in Table 1. The measurement range of micropipe dimensions in white light interference mode of microscope predominantly was within 5−10μ m. A synchronous statistical analysis of identical micropipes through XRT revealed that the central white spot areas corresponding to micropipes consistently approximate 10μ m. This comparative analysis demonstrates the feasibility of utilizing XRT as a direct characterization method for quantifying micropipe areas.

[picture]

Fig. 3. Micropipe image from White Light Interference Microscope.

Fig. 3. Micropipe image from White Light Interference Microscope.

Table 1. Comparison of micropipes size between White Light Interference Microscope and XRT.

Length/um |  | MP-1 | MP-2 | MP-3
Microscope | Major axes | 5.9389 | 11.0103 | 4.3960
Minor axes | 3.7758 | 11.5643 | 2.6325
XRT | Major axes | 18.4937 | 13.2033 | 18.2416
Minor axes | 10.6501 | 12.3507 | 17.2380

The distribution of micropipes in the same wafer was characterized by XRT and polarizing microscope. Fig.4a showed the XRT imaging of the 8-inch wafer. By adjusting the contrast, the distribution of micropipes in the picture can be clearly seen, as shown in the red box. It should be noted that there was a large bright color area in the lower right corner of the wafer, but according to the micropipe characteristics mentioned above, it can be determined that this position was not a micropipe, but should correspond to the rest of the defects, probably multi type defects. Similarly, in Fig. 4b obtained from transmission microscope , micropipe images appeared at the same position as in Fig. 4a. Comparatively, defects in the lower right corner was recognized as micropipes, which also proved that XRT was the most effective way to identify micropipes.

[picture]

Fig. 4. Micropipe distribution on whole wafer, (a)XRT and (b) transmission microscope.

Fig. 4. Micropipe distribution on whole wafer, (a)XRT and (b) transmission microscope.

To investigate the influence of micropipes on the overall stress distribution within the crystal, the wafer stress was mapped using an internal stress meter. Fig. 5a presented the resulting stress map, where the color intensity corresponded to the stress magnitude: darker shades indicate lower stress, while brighter regions signified higher stress. By comparing this stress map with the XRT image in Fig. 4a, it was evident that locations containing micropipes consistently exhibited significantly elevated stress levels.

[picture]

Fig. 5. Inner strain distribution on whole wafer.

Fig. 5. Inner strain distribution on whole wafer.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

In conclusion, this study presented a systematic investigation of micropipe defects in SiC crystals. By correlating XRT with white light interferometry, we directly revealed the lattice distortion caused by micropipes and demonstrate that the degree of distortion was correlated with the micropipe size. Consequently, the impact of micropipes on the crystal lattice varied significantly with their dimensions. In the characterization of the quality of SiC substrate, the size of micropipes also need to be considered apart from the distribution position of micropipes.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

Arora, Aman, et al. "Study on evolution of micropipes from hexagonal voids in 4H-SiC crystals by cathodoluminescence imaging." Microscopy and Microanalysis 27.1 (2021): 215-226.

Huang, Yu-Chun, et al. "Comparative Analysis of Defect Characteristics in Silicon Carbide Wafers of Different Grades." Sensors and Materials 36.5 (2024): 1797-1803.

Zhang, Xuexia, et al. "Effects of defects in a material on the breakdown behavior of a Schottky barrier diode." CrystEngComm 25.47 (2023): 6622-6626.

Li Y, Zhang Z, Song Q, et al. Surface micromorphology and nanostructures evolution in hybrid laser processes of slicing and polishing single crystal 4H-SiC[J]. Journal of Materials Science & Technology, 184 (2024): 235-244.

Fujie, F. et al. Synchrotron X-ray topographic image contrast variation of screw-type basal plane dislocations located at different depths below the crystal surface in . Acta Materialia 208(2021):116746.

Cheng, Q. et al. Analysis of dislocation configurations in SiC crystals through X-ray topography aided by ray tracing simulations. Materials Science in Semiconductor Processing 174(2024):108207.

Li, Jiajun, et al. Dislocations in 4H silicon carbide. Journal of Physics D: Applied Physics 55.46 (2022): 463001.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 59-64

doi: 10.4028/p-h1jN4u

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-19

Accepted:
2026-02-23

Online:
2026-05-18

High Quality P-Type 4H-SiC Growth by PVT Method

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

Shanshan Hu 1,a*, Haochi Wang 1, b, Zeyu Chen 1,c, Kaixuan Zhang 1, d, Yuzhuo Li1,e, Jianpei Zhang 1,f, Balaji Raghothamachar 1, g, Michael Dudley 1, h, Douglas Dukes 2,i and Victor Torres 2,j

1 Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794, USA

2 Pallidus, Inc., Albany, NY 12203, USA

a* shanshan.hu@stonybrook.com, b  haochi.wang@stonybrook.edu, c  zeyu.chen@stonybrook.edu, d  kaixuan.zhang@stonybrook.edu, e  yuzhuo.li@stonybrook.edu, f  jianpei.zhang@stonybrook.edu, 9balaji.raghothamachar@stonybrook.edu, h  michael.dudley@stonybrook.edu, i  douglas.dukes@pallidus.com, j  victor.torres@pallidus.com

Abstract

The fabrication of n -channel IGBTs is constrained by the low conductivity as well as poor quality of the p-type SiC substrate. This paper reports a 6-inch high quality p-type 4H−SiC wafer achieved by PVT method. The wafer was examined by synchrotron X-ray topography indicating average defect densities are on par or better than commercial 6-inch n-type wafers. Large areas of the wafer, especially the middle region of the wafer is characterized by very low density of BPDs. The extent of prismatic slip due to radial thermal gradients is also vastly reduced compared to typical ntype wafers.

Keywords: 4H−SiC,p-type, PVT growth.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

With outstanding electronic properties such as high breakdown field strength, high operating temperatures, high thermal conductivity, and high carrier saturation drift velocity, silicon carbide (SiC) is becoming the choice for fabrication of high-power electronic devices. Various device types such as diodes (JBS, SBD, PiN) and transistors (MOSFET, JFET, IGBT) have been developed chiefly on n -doped substrates. Among these, the SiC insulated gate bipolar transistors (IGBTs) have demonstrated great performance advantages and application prospects as high-voltage switches. Especially, n-channel IGBTs show superior performance than p-channel IGBTs due to higher mobility of electrons than holes but fabrication is preferable on p-doped substrates.

However, the fabrication of n -channel IGBTs is constrained by the low conductivity as well as poor quality of the p-type SiC substrate [1], which is essential for their device performance. Usually, p-type SiC is manufactured using an aluminum (Al)-containing compound placed in the SiC powder region as dopant. Since the vapor pressure of Al is significantly higher than that of the SiC gas species during crystal growth, the Al source is released excessively in the early stage of crystal growth and gets depleted for the later growth stage. As a result, it is hard to achieve stable and continuous p-type doping. In addition, the high concentration of Al at the seed/newly grown crystal interface affects the crystallization quality and leads to large defect nucleation. So far, Suo et al. [2] achieved 3-inch NAl co-doped p-type SiC crystals with regions having BPD etch pit density of 300 cm−2. 4-inch p-type 4H−SiC is obtained by Wang et al. [3] with dislocation etching pit density of 888.89 cm−2. Compared to actual BPD densities (total line length per unit volume), BPD etch pit densities (number per unit area) can be undercounted by a factor of 14 or greater for 4∘ offcut wafers[4]. Nevertheless, significant improvement in quality of p-type SiC wafers and further lowering of defect densities is necessary for development of devices such as n-channel IGBTs.

Synchrotron X-ray topography (XRT) is a powerful characterization technique widely applied in the semiconductor industry[5,6]. High-resolution images of the internal structure of a crystal can be generated through X-rays generated by a synchrotron radiation source non-destructively. Both synchrotron white beam X-ray topography (SWBXT) and synchrotron monochromatic beam X-ray
topography (SMBXT) are employed to obtain crystallographic defects and structural features. Transmission geometry and grazing incidence geometry are employed in SWBXT and SMBXT, respectively. Transmission geometry can expose the overall defect distribution, capturing defects throughout the crystal volume. Grazing incident geometry employs a very small incident angle (~2∘) and penetrates the sample only to a shallow depth below the surface.

In this study, 6-inch high quality p-type 4H-SiC wafers are achieved by PVT method. The wafers were examined by SWBXT in transmission geometries and SMBXT in grazing incidence geometries to map the defect content and distribution.

Experimental

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4∘ off-axis 150 mm PVT-grown 4H-SiC commercial wafers were imaged by synchrotron white beam X-ray topography (SWBXT) in transmission geometry at beamline 27-ID (HEX), National Synchrotron Light Source II at Brookhaven National Laboratory. Synchrotron monochromatic X-ray topography (SMBXT) in grazing incidence geometry images for samples was obtained at beamline 1-BM, Advanced Photon Source at Argonne National Laboratory. The energy of ~9.1KeV is used for SMBXT. As shown in Fig .1, X-ray beam enters one surface of the sample and exits from another surface in transmission geometry while X-ray incidences and exits sample from the same surface with an incident angle of ~2∘ in grazing incidence geometry. Images were recorded on the Agfa Structurix D3-SC films with resolution of ~1μ m for both geometries.

[picture]

Fig. 1. Diagrams showing (a) transmission geometry, and (b) grazing incidence geometry for X-ray topography.

Fig. 1. Diagrams showing (a) transmission geometry, and (b) grazing incidence geometry for X-ray topography.

Results and Discussion

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As shown in Fig. 2, the optical image of the high-quality p-type wafer exhibits a uniform blue color. Although such uniform coloration cannot be regarded as definitive proof of doping uniformity, it does qualitatively suggest a consistent distribution of aluminum dopants. Si face of the wafer is placed up. Facet is observed on the right side of the wafer with a darker blue color as marked by red arrows.

[picture]

Fig. 2. Optical image of a high quality p-type wafer showing uniform blue color across the whole wafer. Facet is observed on the right side of the wafer and marked by red arrows.

Fig. 2. Optical image of a high quality p-type wafer showing uniform blue color across the whole wafer. Facet is observed on the right side of the wafer and marked by red arrows.

The high quality p -type wafer is calculated to have average basal plane dislocation (BPD) density of ~2.2*104 cm−2, threading screw dislocation (TSD) density of ~1331 cm−2, and threading edge dislocation (TED) density of ~2163 cm−2. Fig. 3 illustrates the procedure used to determine the dislocation densities across the entire wafer. As schematically shown by Fig. 3(a), 9 regions that are evenly distributed across the wafer are selected for density measurement. In each region, a grazing incidence image with 112―8 reflection as shown by Fig. 3(b) with size of 2.34 mm×1.75 mm is acquired. The dislocation densities calculated from these images are then averaged to represent the overall density of the wafer. As marked by Fig. 3(b), in grazing incidence images, BPDs show linear white and black contrast, TSDs show large circular white contrast, and TEDs show small circular white or black contrast. The TSDs/TEDs number and total length of BPDs in each image can be manually counted. The densities of TSDs and TEDs are determined by dividing the total number of observed TSDs/TEDs by the image area ( 2.34 mm×1.75 mm ) while the density of BPDs is calculated by measuring the total length of BPD and normalizing by the imaged volume. Since the penetration depth of X-rays for grazing incidence geometry with 112―8 reflection is ~17μ m. The volume where the BPDs are imaged is 2.34 mm×1.75 mm×17μ m.

[picture]

Fig. 3. (a) Schematic showing evenly distributed 9 regions across the wafer selected for dislocation density calculation. (b) Representative SMBXT grazing incidence image with 112―8 reflection acquired in each of the 9 regions for dislocation density evaluation.

Fig. 3. (a) Schematic showing evenly distributed 9 regions across the wafer selected for dislocation density calculation. (b) Representative SMBXT grazing incidence image with 11 2 ― 8 reflection acquired in each of the 9 regions for dislocation density evaluation.

In SWBXT transmission image, the low BPD density regions show whiter contrast compared to those with high BPD density regions. As marked by Fig. 4(a) in SWBXT transmission image for the whole p-type wafer, the middle ~12.6 cm diameter region is characterized by very low density of BPDs. Fig. 4(b)-4(d) shows the grazing incidence images that are obtained in the regions marked by box 1,2,3 in Fig. 4(a). The white horizontal linear contrasts in Fig. 4(b)-(d) are artifacts that are induced due to phase contrast effects from the beryllium window which serves as a vacuum barrier for the storage ring while permitting X-rays to pass into the beamline with minimal absorption. As indicated in Fig. 4(b), in addition to BPDs, TSDs, and TEDs, TSD pairs are observed as marked by red arrows suggesting nucleation in form of pairs is one source of TSDs for p-type wafers. BPD density for box 1,2,3 is low in the range of 581−1123 cm−2. In fact, the middle ~12.6 cm diameter region is characterized to have average BPD density of 598 cm−2, TSD density of 1447 cm−2, and TED density of 1592 cm−2, on par or better than commercial 6-inch n-type wafers.

[picture]

Fig. 4. (a) SWBXT image for the whole p-type wafer indicating the middle 12.6 cm region has low BPD density with whiter contrast, and (b)(c)(d) SMBXT grazing incidence geometry images with 112―8 reflection showing the low density dislocation regions in box 1,2,3 in (a).

Fig. 4. (a) SWBXT image for the whole p-type wafer indicating the middle 12.6 cm region has low BPD density with whiter contrast, and (b)(c)(d) SMBXT grazing incidence geometry images with 11 2 ― 8 reflection showing the low density dislocation regions in box 1 , 2 , 3 in (a).

The extent of prismatic slip for p-type wafer is vastly reduced compared to typical n-type wafers. Only the right periphery region of the wafer shows obvious prismatic slip dislocations contrast in SWBXT image. Other regions are free or have very low density of prismatic slip. As shown by Fig. 5. Prismatic slip dislocations have dark linear contrast along [ 211―0 ] and [ 12―10 ] directions in SWBXT transmission image as marked by yellow dashed line. Such orientations of the prismatic slip dislocations follow the predicted pattern by Guo et al[7,8].

[picture]

Fig. 5. SWBXT image with transmission geometry for the right periphery region of high quality p-type wafer showing distribution of prismatic slip. The orientation of prismatic slip dislocations follow the pattern predicted by Guo et al[7,8].

Fig. 5. SWBXT image with transmission geometry for the right periphery region of high quality p-type wafer showing distribution of prismatic slip. The orientation of prismatic slip dislocations follow the pattern predicted by Guo et al[7,8].

Fig. 6 schematically marks the ranges of prismatic slip dislocations for a high quality p-type wafer and a commercial n-type wafer. The prismatic slip is observed only at the right ~1 cm periphery region for p -type wafer while at the whole periphery region with ~4.7 cm range on the left and ~3.7 cm range on the right for n-type wafer. Note that such observation emphasize the high quality that can be achieved in p-type wafers and does not imply that p-type doping in general results in lower prismatic slip dislocation densities than n-type doping.

[picture]

Fig. 6. Schematics showing distribution of prismatic slip for (a) p-type wafer, and (b) n-type wafer. Shaded red lines mark the region where prismatic slip is observed.

Fig. 6. Schematics showing distribution of prismatic slip for (a) p-type wafer, and (b) n-type wafer. Shaded red lines mark the region where prismatic slip is observed.

Summary

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A 6-inch high quality p-type 4H-SiC wafer was achieved by PVT method with stable and uniform Al doping. Synchrotron X-ray topography images indicate on par or better quality than commercial 6-inch n-type wafers with BPD density ~2.2*104 cm−2, TSD density ~1331 cm−2, and TED density ~2163 cm−2. Especially, the middle 12.6 cm diameter region has even lower BPD density of 598 cm−2. Prismatic slip dislocations are only observed at right ~1.0 cm periphery region of the wafer, vastly reduced compared to typical n-type wafers.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

This work was supported by Pallidus, Inc.. This research used resources of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. This research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

L. Han, L. Liang, Y. Kang, Y. Qiu, A review of SiC IGBT: models, fabrications, characteristics, and applications, TPEL. 36 (2021) 2080-2093.

H. Suo, K. Eto, T. Ise, Y. Tokuda, H. Osawa, H. Tsuchida, T. Kato, H. Okumura, Crystal growth and evaluation of nitrogen and aluminum co-doped N-type 4H-SiC grown by physical vapor transport, J. Cryst. Growth. 498 (2018) 224-229.

G. Wang, D. Sheng, Y. Yang, Z. Zhang, W. Wang, H. Li, Wafer-scale p-Type SiC single crystals with high crystalline quality, Cryst. Growth Des. 24 (2024) 5686-5692.

H. Wang, S. Sun, M. Dudley, S. Byrappa, F. Wu, B. Raghothamachar, G. Chung, E. K. Sanchez, S. G. Mueller, D. Hansen, Quantitative comparison between dislocation densities in offcut 4HSiC wafers measured using synchrotron x-ray topography and molten KOH etching, J. Electron. Mater. 42 (2013) 794-798.

B. Raghothamachar, M. Dudley, G. Dhanaraj, X-ray topography techniques for defect characterization of crystals, in: G. Dhanaraj, K. Byrappa, V. Prasa, M. Dudley (Eds.), Springer Handbook of Crystal Growth, Springer, 2010, pp. 1425-1451.

B. K. Tanner, D. K. Bowen, Characterization of Crystal Growth Defects by X-ray Methods, Springer Science & Business Media, New York, 2013.

J. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quast, I. Manning, Prismatic slip in PVT-grown 4H-SiC crystals, J. Electron. Mater. 46 (2017) 20402044.

J. Guo, Y. Yang, O. Y. Goue, B. Raghothamachar, M. Dudley, Study on the role of thermal stress on prismatic slip of dislocations in 4H-SiC crystals grown by PVT method, ECST 75 (2016) 163-168.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 65-71

doi: 10.4028/p-zY1ER5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-19

Accepted:
2026-02-28

Online:
2026-05-18

Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

Hitesh Jayaprakash 1,3,4,a*, Manuel Belanche 2, b, Constantin Csato 3,c, Florian Krippendorf 3,d , Ulrike Grossner 2,e , Michael Rueb 3, 

1 Ernst-Abbe-Hochschule Jena, Carl-Zeiß-Promenade 2, 07745 Jena, Germany

2 Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

3 mi2-factory GmbH, Hans-Knöll-Straße 6, 07745 Jena, Germany

4 Friedrich Alexander Universität, Cauerstrasse 6, 91058 Erlangen, Germany

a* hitesh.jayaprakash@eah-jena.de b  belanche@aps.ee.ethz.ch, c  constantin.csato@mi2-factory.com, d  florian.krippendorf@mi2-factory.com, e ulrike.grossner@ethz.ch, f michael.rueb@mi2-factory.com

Keywords: 4 H -SiC, DLTS, MCTS, energy filtered ion implantation.

Abstract

The extensive study of point defects in 4H−SiC over the past two decades has led to a comprehensive understanding of their influence on device performance. Specifically, the dominant defects Z1/2 and EH6/7 have been well-quantified and are now formally assigned to specific states of the carbon vacancy. Building upon this foundational knowledge, our study investigates the defect landscape created by the novel process of Energy-Filtered Ion Implantation (EFII). Using DLTS and MCTS measurements conducted within the temperature range of 50−650 K, we analyzed the trap levels created by 19 MeV Nitrogen implantation in as-grown 4H−SiC epitaxial wafer. The majority carrier (electrons) trap with DLTS measurements reveal the presence of prominent peaks associated with carbon complexes, labeled as ON0a ( Ec−0.586eV ) and ON0b / Z1/2 at ( Ec− 0.681 eV ), along with smaller peaks in the shallow region and a broader peak identified as EH6/7 at ( Ec−1.53eV ) as the deepest peak. Notably, the close proximity of the ON0b peak to the wellknown Z1/2 peak poses a significant challenge, preventing the definitive assignment of a defect structure to the known carbon complexes. On the contrary, minority carrier (holes) trap detection with MCTS reveal B-center at ( EV+0.24eV ) and ( EV+0.33eV ) and a negligible shallow peak at (EV+0.22eV) assigned as X center. There was no indication of D-center formation in the EFII implanted samples.

Introduction

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As an emerging power device technology, 4H−SiC has become a preferred material for high-power applications due to its robust physical properties. Although 4H−SiC is a widely used polytype, point defects are common in as-grown (CVD) material, with carbon vacancies typically observed and labeled as Z1/2 and EH6/7 [1]. These defects can also be generated by external processes such as ion implantation, which is a key step for creating carriers for current flow modulation. The presence of these point defects critically influences device performance, most notably through their direct impact on carrier lifetime [2]. Given that carrier lifetime dictates key device performance parameters like on-resistance ( Ron ) and switching speed in fabricated power devices such as diodes and MOS-FETs, addressing these defects would improve device performance. Carbon vacancies, in particular, are known to act as dominant recombination centers for electron-hole recombination [3]. Post ion im-plantation, a high-temperature annealing step, typically performed at 1700∘C to activate the dopants in an argon atmosphere, is effective at recovering the crystal lattice and removing most implantation-induced defects, a deeper understanding of the resulting defect structures is necessary, especially with the introduction of novel processing techniques.

Energy Filtered Ion Implantation (EFII) is a new technology that offers precision drift zone doping [4], making it a key enabler for a simplified approach for SiC Super-Junction devices by simply masking the implanted regions. However, the specific types of point defects generated by this novel technology remain unexplored. Therefore, this study aims to investigate the point defects and trap levels generated by 19 MeV Nitrogen implantation with this technique. EFII offers an implantation depth of approximately 8.5μ m in 4H−SiC for the afore-mentioned Nitrogen ion energy. The implanted samples were subsequently annealed at 1700∘C with carbon capping layer. Deep-Level Transient Spectroscopy (DLTS) and Minority Carrier Transient Spectroscopy (MCTS) measurements were per-formed on standard Schottky diodes fabricated on the implanted SiC samples to identify the peaks that correspond to trap levels existing between valance and conduction bands.

Experimental Approach

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The experimental approach involved the preparation and characterization of three 4H−SiC epitaxial wafers. A pristine wafer from Vendor A with a 10μ m as-grown epitaxial layer and a doping concentration of 5E15 cm-3 was used as a reference without additional processes before Schottky diode fabrication. Two additional wafers from Vendor B, which were unintentionally doped with nitrogen ( <5E14 cm−3 ) with 5μ m epitaxial layer thickness, were used for nitrogen ion implantation with EFII technology at an energy of 19 MeV . To implant different nitrogen concentrations, the wafers were divided into quadrants. The first wafer L was implanted with target concentrations of 1E14, 5 E 14 , and 1E15 cm−3, while the second wafer G was implanted with 1E15,5E15, and 1E16 cm−3 concentrations, with one quadrant on each wafer left un-implanted. Fig. 1a outlines the postimplantation process, all implanted samples were annealed at 1700∘C for 30 minutes in an argon ambient, where the surface was protected by a carbon capping layer formed by the pyrolysis of photo-resist. This layer was subsequently removed through O2 plasma ashing, followed by a sacrificial thermal oxidation at 1050∘C for 20 minutes to ensure complete carbon removal. The wafers were then cleaned with RCA and HF rinse. For the DLTS / MCTS measurements, Schottky diodes were fabricated by depositing a 100 nm nickel layer on the Si-face of the diced chips from each quadrant, with a semi-transparent contacts for MCTS measurements with optical excitation and a thicker central contact for DLTS measurements. The contact diameter for implanted wafer were 1 mm and for pristine (reference) sample was 1.5 mm .

[picture]

Fig. 1. Figure (a) illustrates post implant annealing steps for activation of dopants, and Figure (b) illustrates the calculated net-carrier density from the Tw vs UR=−1.5 plot measured for each sample to verify the implanted concentrations.

Fig. 1. Figure (a) illustrates post implant annealing steps for activation of dopants, and Figure (b) illustrates the calculated net-carrier density from the T w vs U R = − 1.5 plot measured for each sample to verify the implanted concentrations.

The measurement parameters were chosen to optimize the defect characterization and analysis of each sample. For the DLTS measurements, the period width, Up=0 V, ranged from 19.2 ms to 1.92 s , with an electrical pulse stepping from a reverse bias of tp=1 ms to -10 V up to a pulse voltage of UR=−1.5 V, with a pulse duration of 1/C2. In the case of MCTS measurements, the 365 nm LED
was pulsed for 300 ms while maintaining a reverse bias at V to -10 V , respectively for each sample. In order to capture the entire transient, the period width used ranged from 19.2 ms to 1.92 s .

Results and Discussions

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Fig. 1b shows the plots of 5E14 cm−3−1E16 cm−3 vs cm−3 of all implanted samples ranging from concentrations ND−NA. The highly linear nature of each plot shows the uniform doping concentration over depth, which is the intrinsic property of EFII implantation. The lowest implanted concentration 1E14 1700∘C,30 min and no implant regions were measured but the capacitance values were unrealistic due to very low doping levels. This linear slopes verifies the implanted Nitrogen concentrations to the net carrier density expected after activation annealing of the samples. The negligible variation of obtained net carrier concentration T6 value compared to the implanted Nitrogen concentration is due to the existing background doping and tolerances in dose measurement systems for each sample.

[picture]

Fig. 2. DLTS peak progression in (a) and (b) shows the influence of EFII implanted Nitrogen concentration, while MCTS peaks for wafers L and G are shown in (c) and (d), respectively.

Fig. 2. DLTS peak progression in (a) and (b) shows the influence of EFII implanted Nitrogen concentration, while MCTS peaks for wafers L and G are shown in (c) and (d), respectively.

Deep level Transient Spectroscopy.

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Analysis of the DLTS spectra revealed a total of ten dis-tinct deep-level defect peaks labeled in Fig. 2a and 2b corresponding to implanted wafers L and G respectively. Their corresponding energy levels and densities detailed in the Table 1. The data for the un-implanted ( Ec−0.681eV ) sample serves as an important baseline for measurements specific to each wafer used. This sample shows minimal defect signals, especially compared to the implanted samples. This highlights that the hightemperature annealing effectively mitigates or eliminates native defects or those introduced during wafer processing. The prominent peaks in the implanted samples are therefore a direct consequence of the nitrogen implantation, and not the annealing process itself.

The dominant peaks, designated as 6.28E12 cm−3, has an activation energy of ( Z1/2 ) with a density of T5, and is assigned to either ON0b or the well-known Ec−0.586eV defect. A closely related peak, 1.06E13 cm−3, was observed at ( T4 ) with a density of Ec−0.40eV, and is assigned to the ON0a which is a carbon complex found in samples that were subjected to carbon injection experiments [5,6]. Hence ON0a is suggested to be stable defect with di-interstitial carbon.

Table 1. The list of peaks observed in the Deep Level Transient Spectroscopy (DLTS) measurements between 1/C2 temperature range.

Peaks | Energy (eV) | Energy SD (eV) | σ (×10⁻¹⁵ cm⁻²) | Nt (×10¹³ | Assignment cm⁻³)
T₁ | Ec - 0.133 | 0.009 | 0.151 | 0.207 | SD1 / Ti [2, 7]
T₂ | Ec - 0.213 | 0.015 | 0.899 | 0.186 | E0.22 [8]
T₃ | Ec - 0.39 | 0.02 | 2.34 | 0.127 | E0.38 [6, 9]
T₄ | Ec - 0.40 | 0.088 | 0.205 | 0.164 | S1 / EH1 [10, 11]
T₅ | Ec - 0.586 | 0.129 | 3.32 | 1.061 | ON0a [6]
T₆ | Ec - 0.681 | 0.042 | 6.36 | 0.628 | ON0b / Z1/2 [2, 3, 6, 10, 11]
T₇ | Ec - 0.729 | 0 | 0.083 | 0.0393 | EH3 / S2 [11–13]
T₈ | Ec - 1.183 | 0.156 | 6.59 | 0.167 | EH4/5 [14] / ON2b [2, 13, 15]
T₉' | Ec - 1.391 | 0.066 | 4.10 | 0.368 | SD2 [16] / EH6 [7, 12, 13]
T₉'' | Ec - 1.532 | 0.112 | 9.9 | 0.764 | EH6/7 [2, 3, 7, 8, 13, 16]

In addition to these prominent carbon-related complexes, peak S1/EH1 associated with activation energy ( VSi ), assigned to T7 which could be Ec−0.729eV due to implantation process involved, due to their overlapping nature, accurate assignment is not possible. and S2 at ( (Ci)(VSi) ), assigned to T1 related to Ec−0.133eV. Other defects detected include T2 at ( (Ec−0.22eV) ) related to Titanium, T3 at Ec−0.39eV cited in [8] are material or vendor specific defects and E0.38 at ( Ci ), the previously observed ( T8 ) is the metastable defect related to mono (Ec−1.183eV). The deepest traps are (EH4/5) at (CAV) are assigned to Ec−1.391eV relating to the carbon anti-site vacancy (SD2/EH6) pair or ON 2 b , T9' at ( EH6/7 ) assigned to T9′′ which could be a [Titanium - Nitrogen] interaction trap as mentioned in [16] and the well-documented Ec−1.532eV defect ( cm−3 ) at ( 1700∘C ) with a density of 7.64E12 P1,P2 was measured. The carbon interstitial complexes observed in this study are expected to be formed due to the Nitrogen implantation process where the Carbon is kicked out from its site creating a vacancy which is then occupied by nitrogen at P3 activation anneal. This is proved by the net carrier density value measured which is close to the implanted nitrogen concentrations.

Minority Carrier Transient Spectroscopy

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A light pulse duration of 300 ms for hole trap filling was selected based on preliminary observations of the capacitance transients. This duration was empirically determined to ensure the charging process reached a steady state. Consequently, the combination of light intensity and pulse length employed in this experimental setup justifies the assumption of complete trap saturation within the probed volume. Furthermore, the use of semi-transparent contacts ensures that the photo-excited volume aligns closely with the volume electrically interrogated under reverse bias. Given these considerations, the calculated trap density provides a fair estimate of trap density for hole carriers. Beyond absolute quantification, this methodology facilitates a relative comparison across the samples, which remains a primary focus of this investigation. The MCTS measurements reveal three distinct peaks for the minority (hole) carriers as shown in Fig. 2c and 2d and listed in Table 2. Each peaks are labeled as, P1 and P2. Peak (Ev+0.259eV) at (Ev +0.171 eV ) which can be assigned to X relating to Al in the material was observed on all the samples, peak B′ at P3 assigned to the P3 defect, which is the shallow B -center on the shoulder of Peak Ev+0.294eV, and the dominant peak B′′ at [11,15,17] assigned to the 125 K−B′ defect is the deeper B-center which were resolved in both
experimental and theoretical studies B′′. Both boron peaks that overlap at Evv+0.881eV and Evv+0.893eV were separated based on hexagonal or pseudo cubic location of Boron in Silicon site. Influence of B" on Nitrogen implant concentration is witnessed in this study. An additional peak, P4, was observed in the pristine sample at ( 4H−SiC ) and ( 5E15 cm−3 ).

Table 2. The list of peaks observed in the Minority Carrier Transient Spectroscopy (MCTS) measure-ments between V temperature range.

Peaks | Energy (eV) | Energy SD (eV) | σ (×10⁻¹⁵ cm⁻²) | Nt (×10¹³ cm⁻³) | Assignment
P₁ | EV + 0.171 | 0.0211 | 1.226 | 0.154 | X [15]
P₂ | EV + 0.259 | 0 | 6.370 | 0.133 | B′ [11, 15, 17]
P₃ | EV + 0.294 | 0.0217 | 0.345 | 2.51 | B″ [11, 15, 17]
P₄ | EV + 0.881, EV + 0.893 | − | − | − | Found on Pristine Wafer only

Further, the pristine as-grown 50−650 K epitaxial layer with background doping of 1E16 cm−3 was subjected to identical DLTS and MCTS measurements. The deep level spectrum between EH4/5,EH6/7 are compared with the highest dose of Nitrogen implant with EFII of 50−200 K from another wafer. In Fig. 3a, it is evidently visible that the only difference in defect landscape being the Carbon complex (ON0a) peak at 250 K and the cm−3 at 520 K and 600 K respectively. The other shallow peaks between Z1/2 are material/vendor specific defects traps. The magnitude of DLTS signal indicates that the EFII process is not creating significant trap concentration at 1E16 1[15] Nitrogen concentrations and the signal value is in the same range of an operational SiC power devices. Sim-ilarly, in Fig. 3b, The MCTS signal show dominant peak of Deep Boron center (B’’) which is not a nitrogen related minority carrier trap. Notably, there are no other hole traps(D center) generated with nitrogen implantation using EFII process on all the EFII implanted samples. This indicates that the EFII process do not generate the lifetime killer D-center. The detected B centers could be due to the vendor specific Boron from reactors used for CVD growth. Overall, the estimated trap densities for the dominant peaks on implanted samples related to ON0a and carbon vacancy peak 3.4E12 cm−3 for pristine sample using the equation 1.8E12 cm−3 is NT=2·ND·(ΔC/Cref) and NT≪ND respectively. This indicates that the trap densities are in the standard operational range for power devices in 4H-SiC material.
4H−SiC when 50−650 K

[picture]

Fig. 3. (a) Comparision of DLTS peaks observed in the pristine crystal and the EH6/7 implanted Nitrogen. Similarly, (b) Comparision of MCTS peaks from same samples. Note: Wafers are from different vendors.

Fig. 3. (a) Comparision of DLTS peaks observed in the pristine crystal and the E H 6 / 7 implanted Nitrogen. Similarly, (b) Comparision of MCTS peaks from same samples. Note: Wafers are from different vendors.

Summary

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In this work we have detected and assigned the trap levels introduced in 200−300 K epitaxial grown material by performing Nitrogen implantation with Energy Filtered Ion Implantation technology, based on matching the defects activation energy and capture cross-section from earlier work, it is shown that there are no new defect signatures that were detected between 500−650 K in either DLTS or MCTS measurements. ON0a and 4H−SiC are the dominant electron traps detected in the DLTS spectra and Shallow B centers are the dominant hole traps detected in MCTS spectra. No D-center was found on any EFII implanted samples. The estimated trap densities of these defects are in the typical trap density range for SiC power device operation. However, further study on separating the overlapping signal peaks between the temperature range 4H−SiC and 4H−SiC can be performed to clearly understand the defect structure and create a foundation for further trap studies in ion implanted 4H−SiC samples.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

All Ion implantations were done at Ion Beam Center (IBC), Helmholtz-Zentrum DresdenRossendorfe.V. (HZDR) Dresden, Germany. The Activation anneal was performed at Fraunhofer Institut für In-tegrierte Systeme und Bauelemente technologie (IISB), Erlangen, Germany.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

Tsunenobu Kimoto. Fundamentals of Silicon Carbide Technology. Wiley-IEEE Press, (1st), November 2014.

J. Erlekampf, M. Rommel, K. Rosshirt-Lilla, B. Kallinger, P. Berwian, J. Friedrich, and T. Erlbacher. Lifetime limiting defects in epitaxial layers: The influence of substrate originated defects. Journal of Crystal Growth, 560-561:126033, April 2021.

Koutarou Kawahara, Giovanni Alfieri, and Tsunenobu Kimoto. Detection and depth analyses of deep levels generated by ion implantation in n - and p-type 4H-SiC. Journal of Applied Physics, 106(1):013719, July 2009.

Constantin Csato, Florian Krippendorf, Shavkat Akhmadaliev, Johannes Von Borany, Weiqi Han, Thomas Siefke, Andre Zowalla, and Michael Rüb. Energy filter for tailoring depth profiles in semiconductor doping application. Nuclear Instruments and Methods in Physics Research Sec-tion B: Beam Interactions with Materials and Atoms, 365:182-186, December 2015.

Marianne Etzelmüller Bathen, Margareta Linnarsson, Misagh Ghezellou, Jawad Ul Hassan, and Lasse Vines. Influence of Carbon Cap on Self-Diffusion in Silicon Carbide. Crystals, 10(9):752, August 2020.

Marianne Etzelmüller Bathen, Robert Karsthof, Augustinas Galeckas, Piyush Kumar, Andrej Yu. Kuznetsov, Ulrike Grossner, and Lasse Vines. Impact of carbon injection in on de-fect formation and minority carrier lifetime. Materials Science in Semiconductor Processing, 176:108316, June 2024.

Franziska C. Beyer. Deep Levels in SiC. Department of Physics, Chemistry and Biology, Linköping University, Linköping, 2011.

O. V. Feklisova, E. E. Yakimov, and E. B. Yakimov. Study of single-layer stacking faults in 4H-SiC by deep level transient spectroscopy. Applied Physics Letters, 116(17), April 2020.

Robert Karsthof, Marianne Etzelmüller Bathen, Augustinas Galeckas, and Lasse Vines. Conver-sion pathways of primary defects by annealing in proton-irradiated n -type . Physical Review B, 102(18):184111, November 2020.

M. E. Bathen, A. Galeckas, J. Müting, H. M. Ayedh, U. Grossner, J. Coutinho, Y. K. Frodason, and L. Vines. Electrical charge state identification and control for the silicon vacancy in 4H-SiC. npj Quantum Information, 5(1):111, December 2019.

Tihomir Knežević, Tomislav Brodar, Vladimir Radulović, Luka Snoj, Takahiro Makino, and Ivana Capan. Distinguishing the EH1 and S1 defects in n-type 4H-SiC by Laplace DLTS. Ap-plied Physics Express, 15(10):101002, September 2022.

J. Erlekampf, B. Kallinger, J. Weiße, M. Rommel, P. Berwian, J. Friedrich, and T. Erlbacher. Deeper insight into lifetime-engineering in 4H-SiC by ion implantation. Journal of Applied Physics, 126(4):045701, July 2019.

Takafumi Okuda, Giovanni Alfieri, Tsunenobu Kimoto, and Jun Suda. Oxidation-induced ma-jority and minority carrier traps in n - and p -type 4 H -SiC. Applied Physics Express, 8(11):111301, October 2015.

Marianne Etzelmüller Bathen, Robert Karsthof, Ulrike Grossner, and Lasse Vines. Stability, Evolution and Diffusion of Intrinsic Point Defects in 4H-SiC. Materials Science Forum, 1062:371-375, 2022.

Marianne Etzelmüller Bathen, Piyush Kumar, Misagh Ghezellou, Manuel Belanche, Lasse Vines, Jawad Ul-Hassan, and Ulrike Grossner. Dual configuration of shallow acceptor levels in 4H-SiC. Materials Science in Semiconductor Processing, 177:108360, July 2024.

A. A. Lebedev. Deep level centers in silicon carbide: A review. Semiconductors, 33(2):107130, February 1999.

Vitor J. B. Torres, Capan Ivana, and José Coutinho. Theory of shallow and deep boron defects in 4H-SiC. Physical Review B, 106(22), 2022.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 73-78

doi: 10.4028/p-kRPYG5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2026-01-06

Accepted:
2026-01-31

Online:
2026-05-18

Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

Kaixuan Zhang 1,a*, Zeyu Chen 1, b, Shanshan Hu 1,c, Jianpei Zhang 1, d, Yuzhuo Li1,e, Donglin Wu 1,f, Haochi Wang 1, g, Balaji Raghothamachar 1, h, Michael Dudley 1,i and Andrey Soukhojak 2,j

¹Department of Materials Science and Engineering, Stony Brook University, Stony Brook, NY 11794, USA

2 SK siltron css, 1317 Straits Dr, Bay City, MI 48706, USA

a  kaixuan.zhang@stonybrook.edu, b  zeyu.chen@stonybrook.edu, c  shanshan.hu@stonybrook.edu, d  jianpei.zhang@stonybrook.edu, e  yuzhuo.li@stonybrook.edu, f  donglin.wu@stonybrook.edu, g  haochi.wang@stonybrook.edu, hbalaji.raghothamachar@stonybrook.edu, i michael.dudley@stonybrook.edu, j andrey.soukhojak@sksiltron.com

Keywords: 4 H -SiC, x-ray topography, defect characterization.

Abstract

Silicon carbide (SiC) is valued for high-power and high-frequency devices, but its performance is limited by crystalline defects. We report a newly observed defect arrangement, termed the "galaxy" defect, in wafers from a PVT-grown 6-inch 4∘ off-axis boule. Optical microscopy revealed dense clusters of micron-sized inclusions, while synchrotron X-ray topography (XRT) showed associated dislocation networks. Transmission synchrotron XRT indicated threading dislocation clusters, and grazing images revealed high densities of basal plane dislocations, deflected Frank partials, and threading-edge-dislocation low-angle grain boundaries (TED-LAGBs). The defect evolved as growth progressed, producing increasingly complex dislocation structures. Based on the observation, we proposed a mechanism for the evolution of the defect involving the generation, evolution, and interaction between the inclusions and dislocations.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

Silicon Carbide has gained great interest for its high thermal conductivity, high saturation velocity, and high breakdown voltage and, therefore, its suitability to fabricate high-frequency, high-power electronic devices [1, 2]. It has been applied in various fields, including transportation and communication. However, the longevity and performance of SiC devices are hindered by defects within the substrate and epitaxial material. The observation of defects and understanding of their formation mechanism is critical for the improvement of crystal quality and, therefore, better device performance and production yield [3, 4]. Synchrotron X-ray topography is a widely adopted tool for effectively characterizing the defects within single crystals, revealing the detailed structure of defects via diffraction imaging from a synchrotron X-ray light source. Synchrotron XRT can be performed either in the transmission geometry, where whitebeam X-ray is used and images is taken through the whole wafer thickness and provide an overview of the distribution of defects in the crystal. Grazing incidence geometry XRT, on the other hand, uses monochromatic X-ray to image the top few microns from the sample surface, creating a more detailed image of the intersection of defects with the sample surface.
In this study, we report the observation of a new arrangement of defects that we name the "galaxy" defect, which was observed on wafers from the same PVT-grown 6-inch 4∘ off-axis boule. Optical microscopy images show a region of a highly dense cluster of micrometer-level inclusions. The samples are investigated mainly with a combination of optical microscopy, synchrotron white beam X-ray topography, and grazing-incidence synchrotron X-ray topography. The structure of the "galaxy" defect is revealed, and a model is proposed based on the experimental results and observations.

Experimental

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

PVT-grown, 4∘ off-axis 4H−SiC substrate wafers are characterized by a combination of optical microscopy and synchrotron X-ray topography. XRT images were recorded in both transmission and grazing-incidence geometry. The transmission images were recorded using (11-20), (1-100), and (1-1 0 1) reflections using a whitebeam synchrotron source at Beamline 27-HEX at the NSLS-II at Brookhaven National Laboratory. The grazing incidence images were recorded from the Si -face using the (1 1-2 8) at an energy of 9.1 keV at beamline 1-BM of the Advanced Photon Source at Argonne National Laboratory.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

The "galaxy" defect was observed on a series of 150 mm PVT-grown 4∘-offcut 4H−SiC epitaxial wafers from the same boule from slice 13 to slice 25, as illustrated in Fig. 1(a). They are observed near the edge of the wafer as shown in Fig. 1(b) and Fig. 1(c). Optical microscopy as a cluster of inclusions with diameters of a few microns, as shown in Fig. 1(d).

[picture]

Fig. 1. Illustration of the optical observation of the "galaxy" defect, including the location and the wafer numbers and their relevant locations (a); the location of the defect on the boule (b); optical transmission image of the defect on slice 18 (c); and optical transmission microscopy images of the "galaxy defect".

Fig. 1. Illustration of the optical observation of the "galaxy" defect, including the location and the wafer numbers and their relevant locations (a); the location of the defect on the boule (b); optical transmission image of the defect on slice 18 (c); and optical transmission microscopy images of the "galaxy defect".

Fig. 2(a) shows the Transmission XRT, while Fig. 2(b) shows the transmission optical images from the "galaxy" defect region of selected wafers from the boule containing the defect. Transmission XRT images show a dark contrast within the region of the inclusion. Individual defects could not be identified due to the possible high defect density within this region. Also, no individual contrast from the optically observed inclusions could be identified in the topography images. The defect region can be observed to initiate further from the wafer edge and move towards the edge. The cluster can be observed to split into two parts from slice 15. The optical image from slice 49 shows no optical contrast for the defect, while the XRT image shows a large network of prismatic slip dislocations and LAGB as a residual from the defect.

[picture]

Fig. 2. Whitebeam transmission XRT images from ( 1 1 - 20 ) reflection (a) and optical transmission images (b) from slice 13, 15, 17, 22, 25, and 49 showing the evolution of the "galaxy" defect.

Fig. 2. Whitebeam transmission XRT images from ( 1 1 - 20 ) reflection (a) and optical transmission images (b) from slice 13, 15, 17, 22, 25, and 49 showing the evolution of the "galaxy" defect.

Further analysis can also be performed with g·b analysis, identifying the direction of the Burgers vectors of BPDs in this region. The defect region can be observed to be much darker on the (1 1-2 0) reflection images compared to the (1-1 00) reflection images. While exact quantitative measurements were difficult due to the high defect density in this region. Qualitatively, around a third of the BPDs in this region are parallel or antiparallel to the step flow direction. Grazing-incidence geometry XRT was performed on the wafer series in order to further identify the defect structure within this region. The results from slice 13, slice 18, slice 25, and slice 49 are selected as representative and shown in Fig. 3. Although the defect density is still too high to investigate the detailed interaction of defects, contrast corresponding to BPD, TED, and TMD can be identified from the grazing image of slice 13 . A similar arrangement is observed on the grazing images from slice 18. The density of deflected dislocations is found to be higher on slice 18 compared to slice 13. As the growth proceeds to slice 25, a large LAGB network can be observed to form, which corresponds with the observation from the transmission images. The density of deflected dislocations between the inclusion cluster and the wafer edge is also found to increase.

[picture]

Fig. 3. Grazing-incidence XRT images from (1 1 - 28 ) reflection from the Si-face of the "galaxy" defect region from slice 13 (a), slice 18 (b), slice 25 (c), and slice 49 (d).

Fig. 3. Grazing-incidence XRT images from (1 1 - 28 ) reflection from the Si-face of the "galaxy" defect region from slice 13 (a), slice 18 (b), slice 25 (c), and slice 49 (d).

Further SEM and Raman spectroscopy were used to investigate the composition and origin of the inclusions. However, neither SEM nor Raman spectroscopy was able to identify contrast on the sample surface. Reflective optical microscopy was also not able to resolve any inclusion on the sample surface. The interaction thickness of these characterization methods might have been too low to intersect with any of the inclusions. These inclusions could be due to the transportation of carbon or SiC particles from the source material to the growth interface by drag and thermophoretic forces [5]. However, the exact identity and the origin of the inclusions related to the "galaxy" defect are still under investigation with planned TEM studies.
Based on the observations and XRT images, a model can be proposed for the formation and inclusion of the "galaxy" defect, as illustrated in Fig. 4. Previous studies have shown that TSD/TMD pairs could originate from inclusions during epitaxial growth [6, 7]. A high density of inclusions was observed inside the "galaxy" defect region, which would cause the generation of TSD/TMD pairs and therefore the high density of TSD/TMDs observed on the grazing images. As the location of the "galaxy" defect is very close to the wafer edge, the surface curvature in this area would be comparably high, which would promote the formation of macrosteps during the epitaxial process [8, 9]. These macrosteps could then deflect the TSD/TMDs into frank partials and possible stacking faults, which could be the cause of the high density of deflected dislocations between the inclusion region and the wafer edge [10].
The high density of inclusions in this region could also be the origin of the high density of TEDs. While the generation of TEDs is also possible near inclusions, the prismatic slip dislocation network near the "galaxy" suggests that the slipping of prismatic slip dislocations could also be contributing factor to the TEDs in this region [8, 11, 12]. The inclusions in these regions could also serve as blockages of the slipping of prismatic slips dislocations, causing them to re-propagate as TED and pile up near the "galaxy" defect region. It is then possible for the high density of TEDs from the prismatic slips with the same orientation to align themselves along the most energetically favorable arrangement, which would explain the formation of TED-LAGB as growth progresses [13]. In the meantime, the inclusions can also serve as pinning points for the movement of BPDs. Both the inclusions and the highly dense TSD/TMDs within this region could serve as pinning points for the movements of BPDs. This pinning effect could cause the multiplication of BPDs in this region via the Frank-Read source, providing a possible explanation for the high BPD density in this region [14].

[picture]

Fig. 4. Illustration of the proposed model for the "galaxy" defect based on experimental results and observations.

Fig. 4. Illustration of the proposed model for the "galaxy" defect based on experimental results and observations.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

In this study, we investigated a new defect arrangement in PVT-grown 4H-SiC wafer named "galaxy" defect, which was initially observed as micron-level inclusions. The defect arrangements within the
defect are revealed through a combination of optical microscopy, whitebeam synchrotron X-ray topography, and grazing incidence synchrotron topography. A model for the evolution of the defect is proposed based on the experimental results, where the inclusions serve as the origin of TSD/TMDs while also piling up TEDs by blocking prismatic slips and eventually forming TED-LAGB. The inclusions and the TSD/TMDs could be the pinning points causing the multiplication of BPDs in this region. The identification and characterization of the "galaxy" defect provides insights into defect interactions in SiC , which is essential for the improvement of the PVT process in producing 4H−SiC wafers with better quality.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

This research was supported by SK siltron css. This research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence at the Advanced Photon Source. This research used beamline 27-HEX of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DESC0012704.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

Dhanaraj, G., B. Raghothamachar, and M. Dudley, Growth and Characterization of Silicon Carbide Crystals, in Springer Handbook of Crystal Growth, G. Dhanaraj, et al., Editors. 2010, Springer Berlin Heidelberg: Berlin, Heidelberg. p. 797-820.

Codreanu, C., et al., Comparison of 3c SiC, 6h SiC and 4H SiC MESFETs performances. Materials Science in Semiconductor Processing, 2000. 3: p. 137-142.

St. G. Müller et al., Defects in SiC substrates and epitaxial layers affecting semiconductor device performance, The European Physical Journal Applied Physics, vol. 27, no. 1-3, p.29-35.

Tsunenobu Kimoto and Heiji Watanabe, Defect engineering in SiC technology for high-voltage power devices. Applied Physics Express, 2020. 13: p. 120101-1-3.

Z. Wang, Z. Wu, M. Ge, H. Bao, Z. Ma, J. Wu, Study on Carbon Particle Inclusions during 4HSiC Growth by Using Physical Vapor Transport System, Materials Science Forum, 954 (2019), 46-50.

D. Hofmann, E. Schmitt, M. Bickermann, M. Kölbl, P.J. Wellmann, A. Winnacker, Analysis on defect generation during the SiC bulk growth process, Materials Science and Engineering: B, 61-62 (1999), 48-53.

M. Dudley, X. R. Huang, W. Huang, A. Powell, S. Wang, P. Neudeck, M. Skowronski; The mechanism of micropipe nucleation at inclusions in silicon carbide. Appl. Phys. Lett. 75 (1999) 784-786.

Shanshan Hu, Yafei Liu, Qianyu Cheng, Zeyu Chen, Xiao Tong, Balaji Raghothamachar, Michael Dudley, Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals, Journal of Crystal Growth, 628 (2024), 127542.

M. Dudley, F. Wu, H. Wang, S. Byrappa, B. Raghothamachar, G. Choi, S. Sun, E. K. Sanchez, D. Hansen, R. Drachev, S. G. Mueller, M. J. Loboda; Stacking faults created by the combined deflection of threading dislocations of Burgers vector c and during the physical vapor transport growth of 4H-SiC. Appl. Phys. Lett. 98 (2011), 232110.

S. Hu, B. Raghothamachar, Z. Chen, K. Kayang, D. Gersappe, M. Dudley, V. Torres, D. Dukes, D. Lang, A. Martin, H. Briccetti, S. Griswold, T. Kegg, and N. Griffin, New Insights into the Occurrence of Prismatic Slip during PVT Growth of SiC Crystals, Materials Science Forum, 1156 (2025), 57-64.

J. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quast, and I. Manning, Prismatic Slip in PVT-Grown 4H-SiC Crystal, Journal of Electronic Materials, 46 (2017), 2040-2044.

Q. Shao, W. Geng, S. Xu, P. Chen, X. Zhang, R. Shen, H. Tian, X. Pi, D. Yang, and R. Wang, Nucleation of Threading Dislocations in 4H-SiC at Early Physical-Vapor-Transportation Growth Stage, Crystal Growth and Design (2023), 5204-5210.

Q. Cheng, Z. Chen, S. Hu, B. Raghothamachar, M. Dudley, Analysis of Threading Edge Dislocation Low-Angle Grain Boundary Network Distributions in Wafers Through Synchrotron X-ray Topography and Ray-Tracing Simulation. J. Electron. Mater. 54 (2025), 5037-5050.

H. Wang, F. Wu, S. Byrappa, B. Raghothamachar, M. Dudley, P. Wu, I. Zwieback, A. Souzis, G. Ruland, T. Anderson, Synchrotron topography studies of the operation of double-ended Frank-Read partial dislocation sources in 4H-SiC, Journal of Crystal Growth, 401 (2014), 423430.

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The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 79-85

doi: 10.4028/p-mYaQQ1

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-23

Accepted:
2026-02-23

Online:
2026-05-18

Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Y. Li 1,a, J. Zhang 1, b, Z. Chen 1,c, H. Wang 1, d, K. Zhang 1,e, S. Hu 1,f, Raghothamachar 1, g, A. A. Burk Jr 2, h, K. Singh 2,i, M. A. Johar 2,j, N. A. Mahadik 3,k, R. E. Stahlbush 3,I, M. Dudley 1, m

1 Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794 USA

2 Coherent, Inc., USA

3 U. S. Naval Research Laboratory, Washington DC, USA

a  yuzhuo.li@stonybrook.edu, b  jianpei.zhang@stonybrook.edu, c  zeyu.chen@stonybrook.edu, d  haochi.wang@stonybrook.edu, e  kaixuan.zhang@stonybrook.edu, f  shanshan.hu@stonybrook.edu, g  balaji.raghothamachar@stonybrook.edu, h  Albert.Burk@coherent.com, ikanwar.singh@coherent.com, jmuhammadali.johar@coherent.com, 

k  nadeem.mahadik@nrl.navy.mil, 'stahlbush@nrl.navy.mil, mmichael.dudley@stonybrook.edu

Keywords: Silicon Carbide, Thick Epitaxial Layer, X-ray Topography, 3C inclusions.

Abstract

Silicon carbide is a leading wide-bandgap semiconductor for high-voltage power electronics. For 6.5−10kV operation, thick epitaxial layers ( ≥60μ m ) are required to sustain depletion width and maintain uniform electric fields, placing a premium on low extended-defect densities in both substrate and epilayer. Thick epitaxial 4H-SiC layers of 60μ m and 110μ m were grown on 6inch substrates in a multi-wafer warm-wall reactor and evaluated by synchrotron X-ray topography in grazing-incidence (22-4 16) and transmission (11-20) geometries. Transmission imaging showed substrate dislocation content near the lower bound typically reported for 6-inch wafers. Notably, grazing-incidence topography (penetration depth >40μ m ) revealed no basal-plane dislocations propagating into the epilayers, consistent with efficient dislocation conversion at the substrateepilayer interface. The 3C-SiC inclusion density was ~30 per 6-inch wafer for 60μ m epilayers and ~60 per wafer for 110μ m epilayers; the average micropipes density varies from 0 to 5 for both 60 and 110 um epiwafers. Threading dislocation densities-screw, edge, and mixed-were on the order of 1.0−2.0×103 cm−2. These results establish thick 4H−SiC epilayers with suppressed basal-plane propagation and substantially reduced extended-defect content, providing a strong basis for reliable 6.5−10kV device fabrication.

Introduction

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Silicon carbide (4H−SiC) has emerged as a central wide-bandgap semiconductor for high-voltage power conversion because its large bandgap, high thermal conductivity, and high critical electric field enable compact drift regions that sustain high blocking voltages with low conduction loss. In the 6.510 kV class (e.g., planar MOSFETs and superjunction devices), thick and uniform drift layers (typically ≥60μ m ) are required to provide sufficient depletion width and a near-uniform electricfield distribution at breakdown, placing stringent demands on wafer-scale crystalline quality across both substrate and epitaxial layer [1,2].
Extended defects that are most consequential in this regime include basal-plane dislocations (BPDs), threading dislocations (screw/edge/mixed) (TSDs/TEDs/TMDs), micropipes, and 3C inclusions. For device reliability, a key objective in thick epitaxy is to suppress basal-plane-related degradation pathways, minimize threading dislocation densities to the low 103 cm−2 level across full 150 mm wafers, and eliminate high-leakage defects such as micropipes. [3-5]
Assessing these defect populations at the wafer scale with depth sensitivity is enabled by synchrotron X-ray topography (XRT). In off-axis 4H−SiC, grazing-incidence monochromatic topography
provides selective sensitivity to defects within the effective penetration depth near the surfaceparticularly for basal plane related defects and transmission geometries provide defect information primarily in the substrates.
In this work, thick epitaxial 4H-SiC layers of 60μ m and 110μ m were grown on 6-inch substrates using a multi-wafer warm-wall reactor and characterized by synchrotron XRT in complementary grazing-incidence ( g=22−416 ) and transmission ( g=11−20 ) geometries.

Experiment

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4∘ off-axis PVT-grown 150 mm 4H-SiC wafers with 60 and 110μ m-thick CVD epilayers were characterized using synchrotron monochromatic beam X-ray topography (SMBXT) in grazingincidence geometry with the 22−416 reflection at 18 keV , performed at beamline 1−BM of the Advanced Photon Source (APS), Argonne National Laboratory (experimental setup in Fig. 1a; Images were recorded on high-resolution X-ray films (Agfa D3sc). High-resolution X-ray diffraction (HRXRD) double- and triple-axis rocking curves and reciprocal-space maps (RSMs) of (0008) were measured on a Bede D1 diffractometer using CuK1(λ=1.54 A). Figure 1(c) shows the double-axis geometry for rocking curve measurement. The laboratory source operated at 40kV/30 mA; the beam was conditioned by a MaxFlux multilayer mirror and a channel-cut symmetric Ge(004) monochromator. [6]

[picture]

Fig. 1. Schematic of experiment setup of (a) Synchrotron x-ray topography with transmission geometry, (b) Grazing incidence geometry, (c) High resolution x-ray diffraction with double-axis and triple-axis scanning of (0008) reflection.

Fig. 1. Schematic of experiment setup of (a) Synchrotron x-ray topography with transmission geometry, (b) Grazing incidence geometry, (c) High resolution x-ray diffraction with double-axis and triple-axis scanning of (0008) reflection.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Grazing-incidence synchrotron X-ray topographs using the g=224―16 reflection as an effective penetration depth of about 45μ m, imaging the 60μ m and 110μ m thickness epi layer 4H-SiC wafers. The HRXRD was used as an effective tool to reveal the general quality of the thick epi layer SiC wafers.
Overall wafer quality analysis. Fig. 2 shows transmission and grazing incidence topographs from 60um and 110um thick epiwafers. For 60 um epi layer wafers, the grazing topographs exhibit few broad contours and for 110 um epi layer wafers which show greater number and narrower contours, indicating a higher lattice distortion level than 60 um epi layer wafers. The double-axis rocking curve of these wafers given by HRXRD also confirm these observations withs: the average FWHM of 60 um epi layer wafers is 11arcsec while that of the 110 um epilayer wafers is 13arcsec, which correlates with the higher lattice distortion observed on the grazing incidence topographs. For these thick epilayer wafers, the number of 3C inclusion (except the edge of the wafer) incidence is of the order of tens per wafer ( 20 per 150 mm wafer for 60μ m;≈50 per wafer for 110μ m ). Few micropipes ( 1 or 2) were detected throughout the wafers, including in the 110μ m epilayers. The threading dislocation (TSD/TMD and TED) densities are relatively low for both thickness epi-wafers. The transmission topography ( g=11−20 ) indicates the dense BPDs from the substrate and relatively low TED densities (under 100 cm−2 ). In grazing-incidence (22-4 16, 18keV;≈40μ m effective depth), no

BPD is observed within the epilayers except for localized features surrounding the 3C inclusions and the average TED density in grazing topography is 400 cm−2 for 60μ m epi layer and 500 cm−2 for 110 μm epi layer).

[picture]

Fig. 2. Synchrotron X-ray topography of a 6-inch diameter 4H-SiC wafer with a 110μ m epitaxial layer: (a) Grazing-incidence topography ( g=22−416 ) of 60 um epi layer wafer and (c) 110 um epi layer wafer, highlighting surface and near-surface defect distributions and revealing 3C-SiC inclusions as distinct white contrast features; (b) Transmission topography ( g=11−20 ), providing comprehensive defect visualization of defects in substrate through the epitaxial layer depth, where 3C-SiC inclusions appear as characteristic black contrast features.

Fig. 2. Synchrotron X-ray topography of a 6-inch diameter 4H-SiC wafer with a 110 μ m epitaxial layer: (a) Grazing-incidence topography ( g = 22 − 416 ) of 60 um epi layer wafer and (c) 110 um epi layer wafer, highlighting surface and near-surface defect distributions and revealing 3C-SiC inclusions as distinct white contrast features; (b) Transmission topography ( g = 11 − 20 ), providing comprehensive defect visualization of defects in substrate through the epitaxial layer depth, where 3C-SiC inclusions appear as characteristic black contrast features.

3C Inclusions, HLA, and ID. Overall, the 3C inclusions are few and occur mainly near the wafer edge; the interiors are largely inclusion-free. The enlarged grazing topographs ( g=22−416 ) show the 3C inclusions with BPD loops generated. The BPD will propagate along <1−100> directions. The average width of 3C inclusions in 60μ m-thick epi layer wafers is about 860μ m. BPD loops and Interfacial dislocations are generated around the 3C inclusions. The average length of BPD propagation along <1−100> is 1000 um . The 3 C inclusions and associated BPDs covered is about 0.5% throughout the wafer. In 110μ m-thick epilayer wafers, the average width of 3C inclusions is approximately 1500μ m, with BPD loops and interfacial dislocations forming around them. The basalplane dislocations propagate along the <1−100> direction with the average length of about 1400μ m; the coverage of 3C inclusions and associated BPD loops over the wafer is 1.7%. Interfacial dislocations are observed in some 3C inclusions in both 60um and 110um epi layer wafers; the halfloop arrays, however, is not observed on these wafers.

[picture]

Fig. 3. Topographs of 3C inclusions from: (a) to (c) 40 um epi layer wafers; (d) to (f) 60 um epi layer wafers; (g) to (i) 110 um epi layer wafers.

Fig. 3. Topographs of 3C inclusions from: (a) to (c) 40 um epi layer wafers; (d) to (f) 60 um epi layer wafers; (g) to (i) 110 um epi layer wafers.

BPD Conversions. During the epitaxial growth of 4H−SiC on off-axis substrates, defects can be either replicated from the substrate into the grown epi layer or converted into other kinds of defects. One of the most important conversions is the BPD converting to TED. BPDs significantly affect SiC crystal quality and device reliability, leading to issues such as forward-voltage degradation in SiCp−n diodes under long-term operation [7] and increased leakage current. The BPD conversion in the epi layer growth, therefore, is critical to decrease the BPDs in the epi layer. BPDs originating in the substrate intersect the stepped growth surface. Because the surface advances in step-flow mode, the dislocations interact with terraces and macro-steps. As the BPD approaches the surface, it experiences an image force arising from the nearby free surface; this force becomes comparable to the critical resolved shear stress for prism-plane glide. To minimize line energy, the BPD bends upward and out of the basal plane within the first few microns of epilayer growth. Once bent, the dislocation reorients and propagates vertically as a TED. Consequently, BPD density drops sharply while TED density rises across the interface. [8] [9].

[picture]

Fig. 4. Schematic of different kinds of defect movements during the epitaxial growth.

Fig. 4. Schematic of different kinds of defect movements during the epitaxial growth.

[picture]

Fig. 5. Topographs with (22-4 16) under high magnitude optical microscopy of the thick epi layer wafers. The red arrows show the TEDs (white dot contrast) along with BPD (black line contrast), indicating the examples of BPD conversions during the epitaxial growth.

Fig. 5. Topographs with (22-4 16) under high magnitude optical microscopy of the thick epi layer wafers. The red arrows show the TEDs (white dot contrast) along with BPD (black line contrast), indicating the examples of BPD conversions during the epitaxial growth.

"Zebra" feature defects in 60μ𝐦 Epi-Layer. A prominent "zebra" band is observed in the 60μ m 4H-SiC epilayer wafer. Transmission synchrotron topography reveals a region of BPDs forming a large strain-contour loop, while grazing-incidence topography of the same region shows dense TEDs but no BPDs, confirming BPD to TED conversion within the epilayer. The persistence of the zebrashaped contrast indicates that although the defect character has changed, the associated long-range strain/tilt field from substrate defect clusters has been elastically transferred into the epilayer. Previously, Liao et al. [10] reported butterfly defects, which originate from tightly bundled, oppositely signed BPDs forming lobes of tilt. The zebra shape defect observed differs in geometry, presenting instead as a large, loop-like strain field, whereas in the zebra shape defect, the entire defect region in transmission images is filled with dense BPDs, producing a much broader strain loop. Moreover, no well-defined LAGB nucleation site is observed for the zebra feature. However, the butterfly-type distortion field may represent a contributing condition, influencing the elastic strain environment that shapes the zebra band. Ongoing work is directed at clarifying this mechanism, disentangling the roles of substrate-induced dislocation clusters, macro-step overgrowth, and possible butterfly-like strain fields in the formation of this unique defect structure.

[picture]

Fig. 6. Synchrotron X-ray topography of zebra feature defect of g=22−416 grazing image (left) and g=11−20 transmission image. The grazing image shows the black band contours with dense TEDs; the transmission image shows the dense BPD loop formed.

Fig. 6. Synchrotron X-ray topography of zebra feature defect of g = 22 − 416 grazing image (left) and g = 11 − 20 transmission image. The grazing image shows the black band contours with dense TEDs; the transmission image shows the dense BPD loop formed.

Scratches induced TED arrays. Scratch-induced TED arrays are observed in 40μ m and 110μ m thick epilayers, originating from residual scratches on the substrate surface that were not completely removed during polishing. Such scratches contain subsurface damage in the form of BPD half-loops, which act as dislocation sources during epitaxial growth. As growth proceeds, the intersections of these half-loops with the advancing surface replicate into the epilayer: intersections aligned in screw orientation propagate as screw-type BPDs, while those away from screw orientation propagate as TEDs. Because scratches usually extend laterally across the surface, many BPD loops intersect along the same trace, giving rise to rows of TEDs aligned with the scratch orientation. Synchrotron X-ray topographs show these arrays as closely spaced dislocations following the scratch line, often
appearing as opposite-signed pairs in accordance with Burgers vector conservation. With continued growth, these TED arrays can evolve in configuration, sometimes transforming into low-angle grain boundary-like structures further into the boule, though their density generally decreases with depth. [7,11]

[picture]

Fig. 7. Grazing incidence X-ray topography at high-magnification optical microscopy show scratches induced TED arrays in the 40μ m (left) epi layer wafer and in the 110μ m (right) epi layer wafer.

Fig. 7. Grazing incidence X-ray topography at high-magnification optical microscopy show scratches induced TED arrays in the 40 μ m (left) epi layer wafer and in the 110 μ m (right) epi layer wafer.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Synchrotron X-ray topography and high-resolution X-ray diffraction confirm the excellent crystalline quality of the thick 4H−SiC epilayers studied. Nearly complete BPD → TED conversion was achieved, while zebra-shaped bands and scratch-induced TED arrays provide insight into dislocation evolution. Grazing-incidence imaging shows no detectable BPD propagation into the epilayers except at 3C inclusions; 3C-SiC inclusions number about 30 per 6 -inch wafer for 60−μm epilayers and ~50 for 110−μm epilayers. Only a few micropipes were observed, and threading dislocation densities were reduced to 200−400 cm−2. These results underscore the significant potential of these wafers for reliable, high-performance power electronic devices.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

This work has been funded, in part, by the Microelectronics Commons Program, a DOD initiative. The samples are provided by Coherent, Inc. This research used resources [or insert beamline if applicable] of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. This research used resources of the Advanced Photon Source, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

T. Kimoto, Material science and device physics in SiC technology for high-voltage power devices, Jpn. J. Appl. Phys. 54, 040103 (2015).

Y. Zhang, H. Peng, Z. Chen, and M. Dudley, Investigation of factors influencing the occurrence of 3C-inclusions for the thick growth of on-axis C-face 4H-SiC epitaxial layers, J. Cryst. Growth 512, 1 (2019).

K. Masumoto, K. Kojima, and H. Yamaguchi, Investigation of Factors Influencing the Occurrence of 3C-Inclusions for the Thick Growth of On-Axis C-Face 4H-SiC Epitaxial Layers, Materials 13, 4818 (2020).

M. Dudley, N. Zhang, Y. Zhang, B. Raghothamachar, S. Y. Byrapa, G. Choi, E. Sanchez, D. M. Hansen, R. Drachev, and M. J. Loboda, Characterization of 100 mm diameter 4H-silicon carbide crystals with extremely low basal plane dislocation density, Mater. Sci. Forum 645648, 291 (2010).

B. Raghothamachar, M. Dudley, Dislocations in 4H-SiC Substrates and Epilayers, in: P. Wellmann, N. Ohtani, R. Rupp (Eds.), Wide Bandgap Semiconductors for Power Electronics, Wiley VCH GmbH, Weinheim, 2022, pp. 169-198.

Z. Chen, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar, and M. Dudley, Analysis of strain in ion implanted by fringes observed in synchrotron X-ray topography, J. Cryst. Growth 627, 127535 (2024).

M. Dudley, N. Zhang, Y. Zhang, B. Raghothamachar, and E. K. Sanchez, Nucleation of c-axis screw dislocations at substrate surface damage during 4H-SiC homo-epitaxy, Mater. Sci. Forum 645-648, 295 (2010).

S. Ha, P. Mieszkowski, M. Skowronski, and L. B. Rowland, Dislocation conversion in 4H silicon carbide epitaxy, J. Cryst. Growth 244, 257 (2002).

H. Tsuchida, T. Miyanagi, I. Kamata, Y. Sugawara, et al., Investigation of basal plane dislocations in the 4 H -SiC epilayers grown on substrates, Mater. Sci. Forum 483-485, 97 (2005).

M.E. Liao, N. A. Mahadik, R. E. Stahlbush, A. Burk, U. Chakrabarti, I. Zwieback, X. Xu, and R. Rengarajan, Structural analysis of novel butterfly-shaped defects in 4H-SiC substrates, Proc. ICSCRM 2023 (2023).

Q. Cheng, H. Peng, B. Raghothamachar, and M. Dudley, Scratch-induced threading dislocations in thick 4H-SiC epilayers, Defect Diffus. Forum 434, 71 (2024).

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 87-91

doi: 10.4028/p-w9w53Z

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-29

Revised:
2025-12-20

Accepted:
2026-02-23

Online:
2026-05-18

Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

Dong Lee 1,a*, Kirby Schmidt 1,b, Muhammad Ali Johar 1,c, Shanthi Subramanian 1, d, Albert Burk 1,e and Andy Souzis 1,f

¹Coherent Corporation, 2251 Newlins Mill Road, Easton, PA 18045, USA

a* Dong.Lee@Coherent.com, b Kirby.Schmidt@Coherent.com, c muhammadali.johar@coherent.com, d Shanthi.Subramanian@Coherent.com, e Albert.Burk@coherent.com, f Andy.Souzis@coherent.com

Keywords: defects, dislocations, characterization, photoluminescence.

Abstract

The performance and reliability of silicon carbide ( SiC ) devices are critically dependent on the quality of epitaxial layers which in turn are influenced by substrate properties. The accurate classification of epitaxial defects coming from substrate crystal defects and surface defects is critical since these can adversely affect device performance. In this paper, two new methods of defect characterization in substrates and epitaxial layers are presented utilizing photoluminescence (PL) spectrum and carrier lifetime. These methods can be used to study the evolution of defects from substrates to epi and to better predict Epi yields.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

4 H polytype of silicon carbide (4H−SiC) is a semiconductor material finding increased use in power devices due to its wide bandgap, high breakdown voltage and high thermal conductivity [1]. The performance and reliability of silicon carbide ( SiC ) devices are critically dependent on the quality of epitaxial layers which in turn are influenced by substrate properties. The accurate classification of the device killer defects in epitaxial layers is critical for predictive capabilities [2]. In general, most epitaxial defects are inspected and classified by confocal differential interference contrast (DIC) microscopy technology. DIC scan images, combined with photoluminescence (PL) intensity, are used to classify defects into different defect bins for both substrates and epi. This study uses dynamic optical reflectance by pump-probe technology to identify dislocations in substrates and PL peak lambda and carrier lifetime based on band edge emission of each defect measured by Time Resolved PL (TRPL, 355 nm laser with 30 kHZ 600 ps pulse) to identify device killer defects in epi layers [3,4].

Experiments

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

4H-SiC substrates were scanned initially by standard Lasertec SICA88 to identify crystal and surface defects. Conventional method for dislocation detection and classification in SiC uses KOH based etching chemistries followed by etch pit classification. This method is destructive and can show variability due to different chemistries and the need to control etching conditions carefully. Nondestructive methods of dislocation detection can avoid the disadvantages of etching and are more conducive to correlation with post-Epi defects. Previously, non-destructive detection and classification of dislocations have been studied using Lasertec SICA PL images [5]. In the present study, threading screw dislocations (TSD), threading edge dislocations (TED) and basal plane dislocations (BPD) are identified using a new dynamic optical reflectance technique that employs pump-probe technology (similar to photo-reflectance). Results from a beta version of this tool were correlated with the X-ray topography (XRT) measurements. A large dataset of wafers was used for this study and tool reproducibility, and repeatability was verified. The optical approach is also faster compared to XRT and can detect TEDs as well. XRT data was collected using Rigaku's XRT micron system. Fig. 1 (a) and (b) shows the correlation between the two different measurements for TSD and BPD. The R2 factors are close to 0.753 for TSD and 0.923 for BPD. The optical method shows higher values for TSD due to some TED and TMD being identified as TSD. XRT BPD measures a volume density which is converted to a surface density whereas the dynamical optical measurement measures
the BPD signal at the surface which can also lead to discrepancy between the two measurements. The exact number of BPD on the surface is also affected by the accuracy of BPD counting in areas where there are high density clusters.

[picture]

Fig. 1. Dynamic pump-probe optical measurement and XRT TSD (a) and BPD (b) measurements show linear correlation.

Fig. 1. Dynamic pump-probe optical measurement and XRT TSD (a) and BPD (b) measurements show linear correlation.

Fig. 2 (a) shows TSD, TED and BPD identification from the optical measurement scan image. Map images were processed using computer vision for improved classification and counts. Fig. 2 (b) is the optical measurement BPD map and Fig. 2 (c) shows the XRT BPD map on the same wafer. The BPD defect distribution on the wafer is similar between the two techniques.

[picture]

Fig. 2. The scan image of the dynamic pump-probe optical measurement for TSD, TED, and BPD (a), and BPD map distribution by the dynamic optical measurement (b) and the corresponding BPD map distribution of XRT scan on the same wafer (c). The two different measurements show similar trends

Fig. 2. The scan image of the dynamic pump-probe optical measurement for TSD, TED, and BPD (a), and BPD map distribution by the dynamic optical measurement (b) and the corresponding BPD map distribution of XRT scan on the same wafer (c). The two different measurements show similar trends

Epitaxial films were grown on these substrates using multi-wafer chemical vapor deposition (CVD). These wafers were scanned using Lasertec SICA again to identify epitaxial defects. The epitaxial wafers were also scanned and analyzed using EtaMax MiPLATO-SiC for PL spectrum and carrier lifetime of epitaxial defects. First, substrate defects and epitaxial defects were compared to correlate and detect propagation of defects from the substrate surface to epitaxial layers. However, it was found that SFs (stacking faults) were not easy to trace down to substrate defects. Most substrate BPD were converted into TEDs and could not be identified through standard characterization methods.
Lasertec SICA is the standard technique used to characterize epitaxial defects. Epi defects are mostly classified by DIC images, and the majority of defects are stacking faults based on DIC images and PL intensity. Some SF defects overlap in DIC and PL images. However, it is difficult to identify specific killer defects as shown in Fig. 3. Epi BPD counts are minimal and quite different from substrate BPD distribution (not shown here). Poly type inclusions are identified through DIC images.

[picture]

Fig. 3. Lasertec SICA scan on an epi wafer shows various defects and needs to filter out as needed.

Fig. 3. Lasertec SICA scan on an epi wafer shows various defects and needs to filter out as needed.

This wafer was scanned again using EtaMax MiPLATO. Figure 4 shows the scanned data with classified SFs and polytype inclusions, associated spectrum and carrier lifetime. Analysis of epi defects with a peak lambda of 540 nm in the PL spectrum can reveal additional 3C poly type inclusions, which do not appear in DIC images. Polytype and some SF defects show a peak at 540 nm . The ratio of polytype inclusion from DIC detection to 3C defect using the 540 nm peak lambda ranges from 95/109 to 90/122. This implies that DIC based classification may miss some 3C poly type defects. Thus, defect classification based on peak lambda can result in improved killer defects identification for correlation with device performance. In addition, the 424 nm peak lambda in the PL spectra reveals all 1SSF. Most poly type inclusions and major defects are relatively well matched between SICA and MiPLATO-SiC as shown in Fig. 3 and 4.

[picture]

Fig. 4. EtaMax MiPLATO-SiC scan on an epi wafer shows various defects and classification based on PL peak lambda.

Fig. 4. EtaMax MiPLATO-SiC scan on an epi wafer shows various defects and classification based on PL peak lambda.

Individual defects were analyzed using 5 um spatial resolution for TRPL carrier lifetime as shown in Fig. 5. The area surrounding the defects has abrupt changes in spectrum and carrier lifetime. The carrier lifetime of normal epi area is longer than 70 ns and the carrier lifetime of most SF defect areas is about 20−60 ns.3C polytype inclusion related defect spots have the shortest lifetime as 20−40 ns. The carrier lifetime of substrate defects is shorter than 15 ns . These different carrier lifetimes of defects and materials enable dynamic PL to be more efficient in filtering out crystal defects than static PL imaging. Depending on epi structure and growth mechanism, band-edge carrier lifetime has some
differences. Relatively thicker structure has usually longer lifetime. These initial results show the potential advantage of utilizing carrier lifetime measurement to gain further insight into substrate and epi defects.

[picture]

Fig. 5. Time resolved photo luminescence (TRPL) shows the carrier lifetimes on defect areas with different peak lambda as shorter than the carrier lifetime of the defect free area.

Fig. 5. Time resolved photo luminescence (TRPL) shows the carrier lifetimes on defect areas with different peak lambda as shorter than the carrier lifetime of the defect free area.

Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

Lasertech SICA reveals typical SiC substrate defects and most of the epi defects. While Epi killer defects can be identified, it is not easy to correlate these killer defects to substrate defects. New metrology using pump- probe technology (TimeTech Spectra) and XRT (Rigaku) provide nondestructive mapping characterization of TSD, TED, and BPD on substrates. Spectroscopic PL characterization by Horiba's MiPLATO-SiC identifies all epi killer defects on various epi wafers, which can be correlated relatively well with substrate defects from SICA defects, TSD, TED, and BPD .
XRT section topography can be employed for detailed analysis by dissecting epitaxial wafers and tracing the origin of killer defects back to the substrate, as shown in Fig. 6. While this approach provides valuable insight, it is limited in capturing all killer defects across the wafer. Therefore, it serves best as a complementary, non-destructive technique for analyzing selected defects identified through XRT mapping.

[picture]

Fig. 6. XRT section topography tracks the killer defect from the top of thick epi film to the origin of substrate defect. The first three images are from Epi film and the next three images from substrate (proportional to propagational depths). This propagation indicates this defect as IGSF (In-Grown Stacking Faults), which originated from substrate and formed in the buffer layer during epi growth.

Fig. 6. XRT section topography tracks the killer defect from the top of thick epi film to the origin of substrate defect. The first three images are from Epi film and the next three images from substrate (proportional to propagational depths). This propagation indicates this defect as IGSF (In-Grown Stacking Faults), which originated from substrate and formed in the buffer layer during epi growth.

A combination of multiple characterization techniques enables more accurate detection and classification of killer defects. Using TRPL, the carrier lifetime of substrate and epi will be evaluated to confirm the formation and evolution of killer defects, like single Shockley SF (1SSF) from BPD. The evolution of defects from substrate to Epi is challenging and a subject of continued study.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

This study employs advanced metrology techniques for analyzing defects in both SiC substrates and epitaxial layers. We present results from a non-destructive optical method that accurately detects and classifies BPD, TSD, and TED in substrates. Additionally, PL spectroscopy and TRPL measurements demonstrate enhanced capability to distinguish among various types of epitaxial defects. Together, these techniques enable more effective correlation between substrate and epitaxial defects, supporting improvements in material quality and yield.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

Tsunenobu Kimoto, Material science and device physics in SiC technology for high-voltage power devices, Jpn. J. Appl. Phys. 54, 040103 (2015).

Chihiro Kawahara, Jun Suda, and Tsunenobu Kimoto, Identification of dislocations in 4H-SiC epitaxial layers and substrates using photoluminescence imaging, Jpn. J. Appl. Phys. 53, 020304 (2014).

Moonkyong Na, Wook Bahng, Hyundon Jung, Chanhyoung Oh, Donghyun Jang, and Soon-Ku Hong, Revisiting stacking fault identification based on the characteristic photoluminescence emission wavelengths of silicon carbide epitaxial wafers, Materials Science in Semiconductor Processing 175, 108247 (2024).

Moonkyong Na, Wook Bahng, Hyundon Jung, Chanhyoung Oh, Donghyun Jang, and Soon-Ku Hong, Observation of broad triangular Frank-type stacking faults and characterization of stacking faults with emission wavelengths below 430 nm in epitaxial layers, Appl. Phys. Lett. 124, 152109 (2024).

R. Leonard, M. Conrad, E. Van Brunt, J. Giles, E. Hutchins, and E. Balkas, From Wafers to Bits and Back again: Using Deep Learning to Accelerate the Development and Characterization of SiC, Materials Science Forum Submitted 1004 (2024) 321-327.

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The original version of this eBook is available on https://www.scientific.net/book/defects-evaluation/978-3-0364-3125-3

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 93-99

doi: 10.4028/p-uu09Dm

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-22

Accepted:
2026-03-21

Online:
2026-05-18

Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

C. Calabretta 1,a, N. Piluso 1, b, R. Anzalone 1,c, E. Fontana 1, d, G. Maira 1,e, G. Bellocchi 1,f, M. S. Alessandrino 1, g, F. Vento 1, h, C. Nania 1,i, S. Adamo 1,j, S. Zappalà 2,k, G. DˋArrigo 2,I, E. Vitanza 1, m, N. Bentivenga 1,n, A. Russo 1,o, G. Arena 1,p, A. Severino 1,q

1 STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy

2 CNR-IMM, VIII Strada 5, Z.I., 95121 Catania, Italy

a  cristiano.calabretta01@st.com, b  nicolo.piluso@st.com, c  ruggero.anzalone@st.com, denzo.fontana@st.com, e  giovanni.maira@st.com, f  gabriele.bellocchi@st.com, g santi.alessandrino@st.com, h fabiana.vento@st.com, i chiara.nania@st.com, j salvatore.adamo@st.com, k sonia.zappala@imm.cnr.it, 'giuseppe.darrigo@imm.cnr.it, m elisa.vitanza@st.com, n nella.bentivegna@st.com, o alfio-lip.russo@st.com, p  giuseppe-ctn.arena@st.com, q  andrea.severino@st.com

Keywords: altair, candela, defects, Em.Mi, EWS, HTRB, KOH, profilometr, SEM, TEM.

Abstract

The fabrication of high-quality 4H−SiC epitaxial layers for power semiconductor devices involves complex processes including bulk crystal growth, wafer slicing, polishing, and chemical vapor deposition (CVD) epitaxy with precise step-flow control on slightly off-cut Si-face substrates. Despite advances, intrinsic crystallographic defects such as threading dislocations, basal plane dislocations, and stacking faults remain significant challenges, propagating into epitaxial layers and degrading device performance and reliability. This study examines defect types and their impact on 4H-SiC wafers, emphasizing the transition from 150 mm to 200 mm substrates, which introduces increased defect densities and polytype inclusions. Comprehensive defect characterization using advanced microscopy, molten KOH etching, and electrical wafer sorting reveals strong correlations between physical defects-such as micropipes, carrot-like stacking faults, and triangular 3C−SiC inclusions-and device failures, particularly under reliability stress tests like High Temperature Reverse Bias (HTRB). The findings highlight the critical role of substrate quality, epitaxial growth conditions, and defect mapping in improving yield and device robustness. This work underscores the necessity of integrating multi-scale defect inspection and targeted reliability assessments to optimize 4H−SiC power device manufacturing and performance.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

The fabrication of standard 4H−SiC wafers typically involves multiple stages: initially growing a bulk SiC crystal, followed by slicing this crystal into individual wafers, polishing the wafer surfaces, and finally conducting epitaxial layer growth. At present, CVD remains the exclusive method for producing 4H−SiC epitaxial layers (epilayers) used in power semiconductor devices. Achieving highquality homoepitaxial layers that preserve the 4H−SiC polytype relies on a technique known as "stepflow control." This method uses substrates cut at a slight angle-generally a few degrees off the {0001} basal plane-allowing the atomic stacking sequence to replicate along the advancing atomic steps [1]. Currently, wafers with a silicon-terminated (Si-face) surface and a 4∘ off-cut are predominantly utilized in the manufacture of 4H−SiC Schottky barrier diodes (SBDs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). The standard CVD process employs hydrogen ( H2 ) as the carrier gas, silane ( SiH4 ) as the silicon precursor, and propane ( C3H8 ) as the carbon source. Alternatively, chlorine-containing gas mixtures-either by supplementing the standard gases with hydrogen chloride ( HCl ) or by using chlorine-based precursors-are also employed to modify growth conditions [2-3-4-5]. To meet device design requirements, the epitaxial layers must exhibit tightly controlled thickness and doping profiles, with uniformity maintained both
across individual wafers and between different wafers. One of the current industrial challenges is to develop techniques capable of producing 200 mm diameter 4H-SiC epilayers that combine excellent uniformity with minimal defect densities. Additionally, increasing the epitaxial growth rate or shortening the overall production cycle is desirable to boost manufacturing throughput.

Despite improvements, commercially available 4H−SiC substrates still contain significant densities of crystallographic defects, including threading dislocations and basal plane dislocations (BPDs). Threading dislocations are classified by their Burgers vectors: threading screw dislocations (TSDs) have Burgers vectors of either c or c+a, while threading edge dislocations (TEDs) possess Burgers vectors of a/3. Basal plane dislocations share the Burgers vector a/3[6−7−8]. Those threading dislocations with a c+a Burgers vector are often termed threading mixed dislocations (TMDs). During epitaxial growth, these dislocations propagate into the epilayer, with some altering their orientation or transforming into partial dislocations that generate Shockley Stacking Faults (SFs) [9] induce Frank-type stacking faults, prismatic defects, or complex stacking fault structures (commonly referred to as carrot-like defects) within the epitaxial layer, all of which impair electrical characteristics [1011].

Historically, micropipe defects were a major concern in SiC wafers, but advances have reduced their density to below 0.1 cm−2. Consequently, the focus has shifted toward dislocations and epitaxial growth-related defects, which now represent the primary obstacles to device reliability. While industrial inspection techniques efficiently detect most defects, dislocations remain challenging to identify comprehensively. Therefore, understanding the formation, propagation, and impact of these defects is vital, particularly regarding their role in device degradation after reliability stress.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

The role of extended crystallographic defects as electrically active centers promoting leakage current, electric field crowding, and premature breakdown in 4H−SiC power devices is well established [12]. Threading dislocations, micropipes, basal plane dislocations, and stacking faults have been shown to directly trigger degradation and catastrophic failure under high-voltage and hightemperature stress conditions. In the following, we experimentally correlate specific defect types with device failure modes observed after electrical stress.

The ongoing transition from 150 mm to 200 mm diameter SiC substrates introduces new challenges. Unlike 150 mm wafers, 200 mm substrates exhibit slightly increased densities of propagated stacking faults (bar-shaped SFs) and polytype inclusions [13-14].

In typical 150 mm commercial substrates, the density of TSDs ranges from about 2×102 cm−2, TEDs <1.5×103 cm−2, and BPDs <3×102 cm−2, while micropipe are nearly eliminated. In 8 inches the density of TSD is <2.5×102 cm−2, TED <2.5×102 cm−2, BPD<6×102 cm−2 and micropipes <0.1 cm−2.

Monocrystalline SiC substrates have been employed to investigate defect impacts on device performance. Reliability evaluations are indispensable in semiconductor manufacturing, designed to assess device robustness and longevity under various stress conditions. These tests are tailored to specific device technologies and anticipated failure modes. Among the standard reliability tests are High Temperature Reverse Bias (HTRB), High Temperature Gate Bias (HTGB), Dynamic Reverse Bias (DRB), and Body Diode Stress (BDS). These tests collectively inform lifetime and durability models.

Beyond process-induced electrical failures such as threshold voltage instability caused by suboptimal MOS interfaces [15], it is crucial to assess the influence of epitaxial defects on MOSFET device reliability. Failure analysis of 650 V MOSFETs post-reliability testing employs Emission Microscopy (Em.Mi.) to localize failure sites. Following localization, device layers are chemically stripped to expose the SiC surface, which is then subjected to molten KOH etching to reveal underlying defects. The etching process is conducted at 500∘C for 10 minutes, followed by optical microscopy for defect classification and correlation with electrical failures. This approach, optimized for n-type epitaxial layers with doping levels near 1.6×1016 atoms /cm3, provides reliable defect identification [16-17]. SiC wafers undergo comprehensive defect inspection using specialized inline metrology tools to identify defect-affected areas. These defects may be intrinsic to the material (e.g.,
carrots, comets, pits) or induced during processing. While process-related defects are linked to fabrication steps and screened accordingly, intrinsic defects require detailed classification to establish their correlation with device failure, quantified by the killer ratio.

[picture]

Fig. 1. (a-d) Altair images showing, a)micropipes, b-c-d) triangles, e) carrot, f) particle. g) Comparison demonstrating the overlap between the defect map output from Altair and the EWS map.

Fig. 1. (a-d) Altair images showing, a)micropipes, b-c-d) triangles, e) carrot, f) particle. g) Comparison demonstrating the overlap between the defect map output from Altair and the EWS map.

Key metrics such as Defective Die Percentage (DDP) and Total Usable Area (TUA) are employed to evaluate manufacturing yield and efficiency. Tools like Candela and Altair (KLA) utilize optical microscopy and scatter light methods, respectively, tailored for SiC inspection. Despite methodological differences, these tools generally show good agreement in defect detection, especially for surface and epitaxial defects including particles and micropipes. However, many buried substrate defects such as TSDs and BPDs evade detection by conventional methods, necessitating advanced techniques like X-Ray Topography (XRT), which is gaining recognition as a reliable, non-destructive tool for dislocation density measurement.

Material quality assessment often involves mapping device-sized grids to quantify defect impact via DDP after epitaxial growth. This metric predicts the expected failure rate per wafer. Testing wafers outside specification limits helps determine killer ratios for specific defect types.

Figure 1 reports many typical epitaxial defects detected through Altair inspection. Micropipes (Figure 1a), characterized as hollow-core screw dislocations, originate during ingot growth and extend through the wafer thickness, severely compromising device performance. Their evolution during Physical Vapor Transport (PVT) growth is intricate and not fully controlled. Attempts to mitigate micropipes via buffer layer optimization during epitaxial growth have not yielded significant reductions in device failure rates, especially concerning MOSFET blocking voltages. Consequently, micropipes remain a critical substrate-level issue. Triangular defects (TD) appear in three main morphological forms: TD-I, which features grains at its apex (Fig. 1b); TD-II, distinguished by micropits (Fig. 1c); and TD-III (Fig. 1d), characterized by a washboard-like surface texture. These defects arise from various causes, including foreign particles, micropipes within the substrate, and threading edge dislocations, all of which interfere with the epitaxial growth process. Comprehensive investigations employing techniques such as laser confocal microscopy, molten KOH etching, microwave plasma etching, Raman and photoluminescence spectroscopy, as well as high-resolution transmission electron microscopy, have shown that these defects consist of 3C-SiC polytype inclusions or Frank-type stacking faults. The interfaces between the 3 C and 4 H polytypes display both coherent and periodic arrangements, with twinning phenomena notably present in TD-III [18]. The development of these triangular defects is strongly associated with substrate flaws and irregularities in growth conditions, resulting in localized changes in polytype and stacking sequences. [19-20]. Complex stacking fault formations, historically termed carrot defects (Fig. 1e), mainly result from TSD propagation, though single or paired BPDs can also initiate such defects. This is supported by observations of BPD signatures following KOH etching of carrot defects. Fig. 1f reports the case of a particle embedded in the crystal at the end of epitaxial growth.

Aligning the Optical Microscopy (OM) map with Electrical Wafer Sorting (EWS) bins involves matching physical defects detected on the wafer surface, such as micropipes, stacking faults, and contamination, with the electrical test results assigned to each die. The colors on the EWS wafer map correspond to the different EWS bins, visually representing the electrical classification of each die. By ensuring both datasets share the same coordinate system and overlaying the OM defect map onto the colored EWS bin map, it becomes possible to identify correlations between defect locations and electrical performance variations or failures. This alignment facilitates effective root cause analysis, process improvements, and yield enhancement by directly linking specific physical defects to their electrical impact, thereby improving the quality and reliability of 4H−SiC power devices [21].

Both Candela and Altair (KLA) maps reveal elevated concentrations of epitaxial defects such as stacking fault complexes, topographic irregularities, and surface triangles adjacent to polytype regions. These defect clusters correlate strongly with EWS maps, where they cause catastrophic device failures as underlined by the superposition reported in Fig. 1g.

[picture]

Fig. 2. a) SEM image displaying a V-shaped feature on the surface of the TSD. b) AFM image in the same region c) SEM image providing a detailed view of the pit formed by the TSD. d) Crosssectional TEM image revealing the presence of the threading dislocation at the surface.

Fig. 2. a) SEM image displaying a V-shaped feature on the surface of the TSD. b) AFM image in the same region c) SEM image providing a detailed view of the pit formed by the TSD. d) Crosssectional TEM image revealing the presence of the threading dislocation at the surface.

Reliability testing, particularly HTRB, is extensively used to probe failure mechanisms and improve device robustness. HTRB involves applying reverse bias near maximum rated voltages and currents under elevated temperatures to stress device junctions, following JEDEC standards for power devices. In this study, devices were subjected to 520 V reverse bias at 140∘C for 30 hours. Devices failing this test underwent detailed failure analysis. Em.Mi. images highlighting failure locations postHTRB, with emission spots indicating regions of high leakage current within various device areas depending on electrical configuration. Emissions detected in IDSS mode often correspond to epitaxial layer defects.

Following device delayering, surface morphology was examined via SEM and AFM (Fig. 2(a-b)). High magnification SEM images in Em.Mi. hot spots reveal the pit V-shape typical of TSDs arising from substrate [22]. AFM identifies surface pitting consistent with step flow irregularities caused by threading screw dislocations during growth. These shallow depressions evidenced by AFM analysis of about 20 nm depth vary with growth conditions and can cause localized electric field crowding, degrading device performance and potentially leading to failure. SEM analysis particularly elucidated the emergence of a cone shape formed by the TSD as large as 3μ m (Fig. 2c) and cross TEM analysis observations TSDs in 4H-SiC crystals reveal that TSDs propagate roughly along the c-axis but often exhibit non-straight, winding dislocation lines with occasional deflections generating confirming the presence of surface pit. KOH etching at the die level confirmed the association between device failure and TSDs (Fig. 2d).

[picture]

Fig. 3. a) shows a die with the burn location highlighted in red, as identified by Em.Mi analysis in b). The optical profilometer image (c) reveals the hexagonal shape of the burn spot after molten KOH etching. The blue and red profiles illustrate the burn's lateral extent and increasing depth toward the center (d). Optical microscopy (e) captures the defect at various focal planes, clearly indicating that the burn originates from a micropipe, evidenced by the defocus observed at −24μ m.

Fig. 3. a) shows a die with the burn location highlighted in red, as identified by Em.Mi analysis in b). The optical profilometer image (c) reveals the hexagonal shape of the burn spot after molten KOH etching. The blue and red profiles illustrate the burn's lateral extent and increasing depth toward the center (d). Optical microscopy (e) captures the defect at various focal planes, clearly indicating that the burn originates from a micropipe, evidenced by the defocus observed at − 24 μ m .

Molten KOH etching is a cost-effective, destructive method for dislocation density assessment. Conducted at 500∘C in a nickel crucible, etching times are adjusted based on doping levels, differing between substrate and epitaxial layers. This technique effectively reveals dislocations that critically influence device reliability.

The detection of defects such as micropipes reveals that micropipe etch pits are significantly larger than those associated with threading screw dislocations (TSDs), primarily due to the larger Burgers vector of micropipes. Fig. 3 illustrates a hard device failure caused by a crystallographic defect. Leakage currents measured between drain-gate and gate-source terminals reveal short circuits. Em.Mi. pinpoints the emission site (Fig 3b), and subsequent chemical delayering exposes a hexagonal hole at the defect location. Optical profilometry analysis (Fig. 3c) further confirmed that these defects exhibit a hexagonal symmetrical structure aligned with the crystallographic axes. Profiling along marked lines (Fig. 3d) showed that the micropipe etch pits extend approximately 180μ m in diameter, with edge depths ranging from 2 to 7μ m, gradually tapering toward the center. In Fig. 3e Bright-field optical microscopy provided additional confirmation by revealing a distinct hole characteristic of micropipes when the focal plane was adjusted approximately 24μ m below the sample surface. Together, the hexagonal etch morphology and the observed subsurface hole definitively identify the defect as a micropipe determining localized high current density and thermal damage.

Conclusion

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

This comprehensive review underscores the critical importance of defect inspection in SiC wafer production, particularly focusing on the identification and characterization of killer defects that significantly impact device performance and yield. The article systematically categorizes the diverse crystallographic and surface defects inherent to SiC wafers, such as threading screw and edge dislocations, basal plane dislocations, micropipes, stacking faults, and polytype inclusions, detailing their origins, morphologies, and detrimental effects on various SiC power devices including MOSFETs, Schottky diodes, and p−n junctions. A broad spectrum of inspection techniques, ranging from destructive methods like KOH etching and transmission electron microscopy to advanced nondestructive optical and electron-based modalities such as photoluminescence, X-ray topography, Raman spectroscopy, and mirror projection electron microscopy are increasingly becoming essential in terms of their resolution, throughput, and applicability for in-line production environments. The review highlights the complementary nature of these methods and advocates for integrated inspection systems that combine high-resolution imaging with rapid scanning capabilities, enhanced by machine learning algorithms for automated defect classification and mapping.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

T. Kimoto, A. Ito, H. Matsunami, Step-controlled epitaxial growth of high-quality SiC layers, Phys. Status Solidi (b) 202 (1997) 247-262.

F. La Via, G. Galvagno, G. Foti, M. Mauceri, S. Leone, G. Pistone, G. Abbondanza, A. Veneroni, M. Masi, G.L. Valente, D. Crippa, 4H SiC epitaxial growth with chlorine addition, Chem. Vap. Depos. 12 (2006) 509-515.

F. La Via, G. Izzo, M. Mauceri, G. Pistone, G. Condorelli, L. Perdicaro, G. Abbondanza, L. Calcagno, G. Foti, D. Crippa, 4H-SiC epitaxial layer grown by trichlorosilane (TCS), J. Cryst. Growth 311 (2008) 107-113.

F. La Via, M. Camarda, A. La Magna, Mechanism of growth and defect properties of epitaxial SiC, Appl. Phys. Rev. 1 (2014) 031301.

G. Dhanaraj, M. Dudley, Yi Chen, B. Ragothamachar, B. Wu, H. Zhang, Epitaxial growth and characterization of silicon carbide films, J. Cryst. Growth 287 (2006) 344-348.

P.G. Neudeck, Electrical impact of SiC structural crystal defects on high electric field devices, Mater. Sci. Forum 338-342 (2000) 1161-1166.

T. Ohno, H. Yamaguchi, S. Kuroda, K. Kojima, T. Suzuki, K. Arai, Direct observation of dislocations propagated from substrate to epitaxial layer by X-ray topography, J. Cryst. Growth 260 (2004) 209-216.

Y. Sugawara, M. Nakamori, Y.-Z. Yao, Y. Ishikawa, K. Danno, H. Suzuki, T. Bessho, S. Yamaguchi, K. Nishikawa, Y. Ikuhara, Transmission electron microscopy analysis of a threading dislocation with a Burgers vector in , Appl. Phys. Express 5 (2012) 081301.

S. Ha, P. Mieszkowski, M. Skowronski, L.B. Rowland, Dislocation conversion in 4H silicon carbide epitaxy, J. Cryst. Growth 244 (2002) 257-266.

A. Agarwal, W. Sung, L. Marlino, P. Gradzki, J. Muth, R. Ivester, N. Justice, Wide band gap semiconductor technology for energy efficiency, Mater. Sci. Forum 858 (2016) 797-802.

A.R. Powell, J.J. Sumakeris, Y. Khlebnikov, M. Paisley, R. Leonard, E. Deyneka, S. Gangwal, J. Ambati, V. Tsevtkov, J. Seaman, A. McClure, C. Horton, O. Kramarenko, V. Sakhalkar, M. O'Loughlin, A. Burk, J. Guo, M. Dudley, E. Balkas, Bulk growth and large area SiC crystals, Mater. Sci. Forum 858 (2016) 5-10.

Stahbush, R. E., and Nadeemullah A. Mahadik. "Defects affecting SiC power device reliability." 2018 IEEE International Reliability Physics Symposium (IRPS). IEEE.

Manning, Ian, et al. "Advances in wafer development and production." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

Tsuchida, Hidekazu, and Takahiro Kanda. "Advances in fast crystal growth and defect reduction by high-temperature gas-source method." Materials Science in Semiconductor Processing 176 (2024): 108315.

Pande, Peyush, et al. "Electrical characterization of SiC MOS capacitors: A critical review." Microelectronics Reliability 112 (2020): 113790.

Fukunaga, K.; Suda, J.; Kimoto, T. Anisotropic Etching of Single Crystalline SiC Using Molten KOH for SiC Bulk Micromachining. Proc. SPIE 2006, 6109, 1-8. 32.

Yao, Y.; Ishikawa, Y.; Sugawara, Y.; Sato, K.; Shirai, T.; Danno, K.; Suzuki, H.; Sakamoto, H.; Bessho, T.; Dierre, B.; et al. Cross Sectional Observation of Stacking Faults in 4H-SiC by KOH Etching On Nonpolar Face, Cathodoluminescence Imaging, and Transmission Electron Microscopy. Jpn. J. Appl. Phys. 2014, 53, 1-8.

Yu, Jinying, et al. "Morphological and microstructural analysis of triangular defects in 4H-SiC homoepitaxial layers." CrystEngComm 24.8 (2022): 1582-1589.

Kimoto T 2016 Bulk and epitaxial growth of silicon carbide Prog. Cryst. Growth Charact. Mater. 62 329-5.

Yu, Jinying, et al. "Morphological and microstructural analysis of triangular defects in homoepitaxial layers." CrystEngComm 24.8 (2022): 1582-1589. 1.

Nania, Chiara, et al. "Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications." Solid State Phenomena 375 (2025): 43-47.

Chen, Po-Chih, et al. "Defect inspection techniques in SiC." Nanoscale Research Letters 17.1 (2022): 30.

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Keywords Index

#

3c Inclusions Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

4 H -sic DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes; Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

A

Afm DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Altair Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

B

Boron Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

C

Candela Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Characterization DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Charge Carrier Lifetime Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

D

Deep Level Defects DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Deep Levels Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Defect Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Defect Characterization Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Defects Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Dislocations Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Dlts DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

E

Em.mi Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Energy Filtered Ion Implantation Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Ews Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

H

Htrb Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

K

Koh Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

M

Macrostepped Morphology DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Mcts Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Measurement Parameters DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Micropipe Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

P

Photoconductivity Decay Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Photoluminescence Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Profilometr Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

S

Sbd DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Sem Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

SiC Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Silicon Carbide Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Smim DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Srh Recombination Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Ssrm DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Statistical Process Control Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Surface Structuring DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

T

Tem Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Thermodynamics Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Thick Epitaxial Layer Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

X

X-ray Topography Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Authors Index

A

Adamo, S. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Alessandrino, M. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Anzalone, R. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Arena, G. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

B

Barbisan, L. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Belanche, M. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Bellocchi, G. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Bentivegna, N. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Burk, A. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

C

Calabretta, C. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Cannizzaro, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Chen, X. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Chen, Z. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Coppola, M. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Csato, C. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Cui, P. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Cui, Y. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

D

D'Arrigo, G. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Dayyala, M. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Dudley, M. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Dukes, D. High Quality P-Type 4H-SiC Growth by PVT Method

F

Feng, G. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Ferro, G. DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Fontana, E. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Fu, Z. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

G

Germanicus, R. DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Ghezellou, M. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Giuffrida, F. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Grossner, U. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

H

Hallén, A. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Han, J. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Han, W. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Hu, S. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Hu, X. Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Huang, F. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

J

Jayaprakash, H. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Johar, M. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Jr, A. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

K

Kallinger, B. Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Kang, J. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Krippendorf, F. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

L

Lee, D. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Li, J. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Li, Y. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Lombardo, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Luo, L. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

M

Magnusson, B. The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Mahadik, N. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Maira, G. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Metreveli, A. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

N

Nania, C. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

P

Parisi, P. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Peng, Y. Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Per, J. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Piluso, N. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Q

Qian, W. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

R

Raciti, D. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Raghothamachar, B. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Rommel, M. Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Rossitto, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Rueb, M. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Russo, A. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

S

Salamone, M. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Samperi, O. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Schmidt, K. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Severino, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Shao, H. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Sharma, P. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Singh, K. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Soukhojak, A. Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Souzis, A. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Stahlbush, R. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Subramanian, S. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Sun, L. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Sun, Y. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

T

Thörnberg, J. The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Torres, V. High Quality P-Type 4H-SiC Growth by PVT Method

U

Ul-Hassan, J. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

V

Vento, F. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Vines, L. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Vitanza, E. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

W

Wang, H. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Wißgott, C. Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Wu, D. Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

X

Xie, X. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Xu, M. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Xu, X. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Y

Yang, X. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Yu, G. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Yuan, Z. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Z

Zappalà, S. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Zhang, J. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Zhang, K. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Zhao, J. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Zhao, Q. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Zhong, Y. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters