Design and Characteristics of MOSFETs

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Design and Characteristics of MOSFETs

Special topic volume with invited peer-reviewed papers only

Edited by

Prof. Victor Veliadis and Dr. Arash Salemi

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

All rights reserved. No part of the contents of this publication may be reproduced, processed or transmitted in any form or by any means without the written permission of the publisher.

Trans Tech Publications Ltd
Seestrasse 24c
CH-8806 Baech
Switzerland
https://www.scientific.net

Volume1023 of
Key Engineering Materials
ISSN print 1013-9826
ISSN web 1662-9795

Full text available online at https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Distributed worldwide by
Trans Tech Publications Ltd
Seestrasse 24c
CH-8806 Baech
Switzerland
Phone: +41 (44) 9221022
e-mail: sales@scientific.net

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-10

Online:
2025-09-10

Preface

The original version of this paper is available on https://www.scientific.net/KEM.1023.-1.pdf

This special edition presents recent results and advances in evaluating functional characteristics and designing silicon carbide (SiC) devices, which have growing applications in modern power electronics and integrated circuits.

The investigations cover a wide range of SiC -structures, including MOSFETs, bipolar junction transistors, PiN diodes, Schottky barrier diodes, etc., emphasising switching tests, analysis channel density and planar gate cell topologies.

Special attention is given to using advanced methodologies such as optical beam induced current (OBIC) analysis and TCAD for device operation modelling, performance evaluation, and design optimisation.

This special edition comprehensively overviews state-of-the-art technologies for designing structures and analysing functional characteristics of SiC-based devices and integrated circuits, which, in modern conditions of scientific and technological progress, have wide applications in many engineering and manufacturing fields.

Table of Contents

Preface

Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Dominique Planson, Camille Sonneville, Pascal Bevilacqua, Pierre Brosselard, Mihai Lazar, Sigo Scharnholz, Bertrand Vergne, Hervé Morel

Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Kyrylo Melnyk, Marco Boccarossa, Arne Benjamin Renz, Qinze Cao, Peter Michael Gammon, Vishal Ajit Shah, Luca Maresca, Andrea Irace, Marina Antoniou

A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

Ji Hun Lim, Arman Ur Rashid, Britt Brooks, Sei Hyung Ryu

A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

Skylar de Boer, Dinuth C.Y.B. Yapa Mudiyanselage, Seung Yup Jang, Adam Morgan, Woong Je Sung

Single-Event-Burnout in 4H-SiC Lateral RESURF Power MOSFET

Zhao Wen He, Wei Ji, T. Paul Chow

Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Jae Hoon Park, Siddarth Sundaresan, Aditi Agarwal, Vamsi Mulpuri, Steven Dail, Yu Dong, Nathaniel Walsh

A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

Xiaofan Ma, Mattias Ekström, Carl Mikael Zetterling

Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

Philip G. Neudeck, Christina M. Adams, Michael J. Krasowski, David J. Spry, Norman F. Prokop

Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

Servin Rathi, Leo Laborie, Y. Qi, Aled Murphy, Martin Bell, Robert Young, David T. Clark

Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

Antxon Arrizabalaga, Jesus Oliver

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 1-6

doi: 10.4028/p-0v5tyE

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Accepted:
2025-02-28

Online:
2025-09-10

Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1023.1.pdf

D. Planson , C. Sonneville , P. Bevilacqua , P. Brosselard , M. Lazar , S. Scharnholz , B. Vergne , H. Morel

Univ Lyon, INSA Lyon, Univ. Claude Bernard Lyon 1, Ecole Centrale Lyon, CNRS, Ampère, F-69621, France

Light, Nanomaterials, Nanotechnologies, L2n, UMR CNRS7076, Université de Technologie de Troyes, 10004, Troyes, France

French-German Research Institute of Saint-Louis (ISL), 5 rue du Général Cassagnou, 68300 Saint-Louis, France

dominique.planson@insa-lyon.fr, camille.sonneville@insa-lyon.fr, pascal.bevilacqua@insa-lyon.fr, pierre.brosselard@insa-lyon.fr, mihai.lazar@utt.fr, sigo.scharnholz@isl.eu, bertrand.vergne@isl.eu, herve.morel@insa-lyon.fr

Keywords: OBIC characterization, Bipolar diode, high voltage, device simulation, periphery protection

Abstract

This paper presents for the first time a comparison between experimental measurements of Optical Beam Induced Current (OBIC) and finite element simulations on high-voltage bipolar diodes. Two peripheral protection structures were chosen: a simple MESA protection and a MESA + JTE combination. Comparable experimental and simulated results were obtained in both cases.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.1.pdf

Bipolar components (diodes, transistors, thyristors) are essential for very high-voltage power electronics. Recently, an optical-controlled high-voltage BJT (Bipolar Junction Transistor) has been designed, fabricated and characterized. The BJTs were fabricated on a wafer using a thick epilayer with a doping concentration of and were designed to withstand a voltage of 10 kV . After electrical characterization, a breakdown voltage of about 11 kV was obtained [2].
PiN diodes have been integrated in the mask layout as part of this project to optically trigger highvoltage bipolar components (Fig. 1, right). In order to verify the effectiveness of their peripheral protection, different geometries were considered: MESA only, MESA combined with JTE, with and without supplementary 6 JTE rings, with round and square shapes. Previous studies have shown the efficiency of the micro-OBIC technic to assess the efficiency of peripheral protection by analyzing the 2D distribution map of currents within the device structure [3,4]. In this paper, we demonstrate that this technic can be used to characterize high-voltage bipolar diodes.

Experimental Results

The original version of this paper is available on https://www.scientific.net/KEM.1023.1.pdf

Device fabrication and characterization. Bipolar diodes were fabricated at the same time as the vertical bipolar transistors. Eleven mask levels are required to manufacture the components. No passivation was applied to the OBIC test diodes. The purpose of these diodes is to test the effectiveness of the peripheral protection of the transistor's base-collector junction. Figure 1 shows the mask of the test structures with the various peripheral protections, and also a picture of the 100 mm wafer with the components produced. Numerous test structures have been planned, but for the purpose of this paper, only 2 structures are studied in detail. The manufacturing process is described in [1]. These diodes have been characterized in a vacuum chamber up to a reverse voltage of 1000 V and exhibit a low leakage current as shown in Fig. 2, a prerequisite for OBIC characterization measurements in reverse.

Fig. 1. Image of the fabricated wafer with 9 OBIC designs (MESA, MESA+JTE, MESA+JTE+ 6 rings, round and square shapes).

Fig. 1. Image of the fabricated wafer with 9 OBIC designs (MESA, MESA+JTE, MESA+JTE+ 6 rings, round and square shapes).

Fig. 2. Leakage current versus reverse voltage for two periphery protections (MESA and MESA + JTE) in the vacuum chamber ( ).

Fig. 2. Leakage current versus reverse voltage for two periphery protections (MESA and MESA + JTE) in the vacuum chamber ( ).

Experimental OBIC measurements. Two types of circular diodes were chosen for illustration: a MESA diode and a MESA diode with JTE. Micro-OBIC measurements were carried out in air, limiting the reverse voltage applied to 400 V to avoid breakdown. Their cross-sectional view is shown in figure 3.

Fig. 3. Cross-sectionnal view of both vertical diode (MESA on the left and MESA+JTE on the right).

Fig. 3. Cross-sectionnal view of both vertical diode (MESA on the left and MESA+JTE on the right).

The OBIC (Optical Beam Induced Current) characterization technique has already been described in previous papers from our team [3, 4]. The 2D-maps OBIC show the evolution of the induced current within devices. These maps are shown in Fig. 4, where the junction is clearly evidenced. Blue colors represent the absence of signal, e.g. the outside of the diode and the metallization of the anode in the center of the figures.

Fig. 4. OBIC 2D-mapping of circular diodes with MESA (left) and with MESA combined with JTE (right) (under 100 V ). Experimental measurements of the OBIC current are expressed using a logarithmic scale (the displacement step in both direction is ). The dimensions of the area scanned are a square of for both structures.

Fig. 4. OBIC 2D-mapping of circular diodes with MESA (left) and with MESA combined with JTE (right) (under 100 V ). Experimental measurements of the OBIC current are expressed using a logarithmic scale (the displacement step in both direction is ). The dimensions of the area scanned are a square of for both structures.

OBIC measurements have also been studied on vertical lines (1D) as shown in Fig. 4, enabling much fa ster plotting as a function of the inverse voltage applied. These will be compared with the corresponding simulations in the next section. Fig. 6 (left) and Fig 7 (left) show the evolution of the experimental OBIC current with position for half a diameter of a diode protected by a single mesa (Fig. 3-left) and a MESA + JTE (Fig. 3-right). Experimental curves are plotted for voltages ranging from 0 to 300 V . The different zones are clearly visible: metallization, MESA, JTE, as shown in the simplified cross-section above the curves.
OBIC simulations. At the same time, finite element simulations were carried out with Sentaurus [5] in transient mode, taking into account the diode structure (Fig. 5) and the characteristics of the laser optical beam (position, penetration depth, Gaussian parameters, power density...). The wavelength is identical to that of the experimental laser beam ( 349 nm ), and the quantum yield is assumed to be unity. The beam is assumed to be continuous, and the displacement must be less than the mesh length. Figures 5 show how the two structures are entered into the simulator. For all simulations, only a few microns underneath the metallization is considered to focus on the peripheral protection in order to limit the number of mesh nodes and calculation time, which is already very long (several dozen hours). The same applies to the reduced thickness of the epitaxial layer ( instead of ), but this has no impact as the maximum reverse voltage applied is 300 V . The thickness of the substrate is also reduced for the same reason. However, the lateral dimensions are respected, as of course the doping of each layer.

Fig. 5. Cross-section of the periphery protection (only half-cell to limit calculation time) of both diode structures with MESA (left) and MESA+JTE (right) defined with Sentaurus / Synopsys [5]. The distance are expressed in .

Fig. 5. Cross-section of the periphery protection (only half-cell to limit calculation time) of both diode structures with MESA (left) and MESA+JTE (right) defined with Sentaurus / Synopsys [5]. The distance are expressed in .

The optical beam moves across the structure from the outside towards the metallization, with small displacements at a given voltage. In this way, the current can be calculated as a function of the position. Fig. 6 (right) shows the evolution of the simulated currents for half a diameter of diode protected with the MESA, at reverse voltage between 0 V and 300 V . These simulations are compared with the experimental measurements (Fig. 6 (left)). As it can be observed, both the experimental and simulated OBIC behavior are almost identical: the optically induced current increases and widens at the junction if the reverse voltage increases. The singularity observed (at the edge of the MESA) with measurements is also reproduced in simulations, due to the beam passing over the edge of the MESA. Signal decay outside the MESA is linked to the lifetime of the minority carriers. This parameter could be better adjusted in the future.

Fig. 6. Comparison between experimental measurements (left) and simulation (right) of the OBIC signal according to the diameter of the diode protected by MESA. The displacement step is . The same colors are used for the same voltage for both results up to 300 V .

Fig. 6. Comparison between experimental measurements (left) and simulation (right) of the OBIC signal according to the diameter of the diode protected by MESA. The displacement step is . The same colors are used for the same voltage for both results up to 300 V .

Finite element simulations were also carried out for MESA + JTE protection.

Fig. 7. Comparison between experimental measurements (left) and simulation (right) of the OBIC signal according to the diameter of the diode protected by MESA + JTE ( ). The displacement step is 500 nm . The same colors are used for the same voltage for both results up to 300 V .

Fig. 7. Comparison between experimental measurements (left) and simulation (right) of the OBIC signal according to the diameter of the diode protected by MESA + JTE ( ). The displacement step is 500 nm . The same colors are used for the same voltage for both results up to 300 V .

The simulated and experimental results are clearly similar. The length of the JTE is clearly visible, and the maximum current is close to the MESA and the junction. There is also an absence of current under the anode contact metal. The progressive increase in the experimental measurements is most probably linked to a charge density at the interface, unlike the simulated signal. This effect is not taken into account yet, and adjustments will be necessary.
Our results show that these TCAD simulations can be used to predict the experimental behavior of any structure.

Acknowledgements for French ANR contract HV-PhotoSwitch (ANR-18-CE05-0020-01).

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.1.pdf

This paper presents OBIC measurement and simulation results for 2 types of periphery protection: MESA and a combination of MESA + JTE. The OBIC measurements show that the good resolution of our test bench is capable of revealing the different zones of the protection and also the impact of the applied reverse voltage. In this paper, TCAD simulations have been developed for the first time for relatively high voltages. As illustrated, there is good agreement between experimental results and simulations with regards to JTE length and MESA structure. However, improvements could be future explored. The difference between the signals could come from the recombination current at the oxide/semiconductor interface that is not yet simulated.
In the future, the OBIC test bench will be adapted to a vacuum chamber, enabling characterization at higher reverse voltage, and thus revealing the full effectiveness of peripheral protection. It also could help to reach the optimal design of the JTE, even the additional JTE rings.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.1.pdf

P. Brosselard, D. Planson, D. Tournier, P. Bevilacqua, C. Sonneville, L. V. Phung, M. Lazar, B. Vergne, S. Scharnholz and H. Morel, Design and characterization of an optical 4H-SiC Bipolar Junction Transistor, Solid State Phenomena, Vol. 360 (2024) p 127-131

A. Ammar, M. Lazar, B. Vergne, S. Scharnholz, L. V. Phung, C. Sonneville, C. Raynaud, H. Morel, D. Planson and M. Zielinski, Optimized Junction Termination Extension and Ring System for 11 kV 4H-SiC BJT, IEEE (2022) International Semiconductor Conference (CAS), p. 191

C. Sonneville, D. Planson, L.-V. Phung, P. Bevilacqua, B. Asllani, Interest of using a micrometer spatial resolution to study SiC semi-conductor devices by Optical Beam Induced Current (OBIC), Materials Science Forum Vol. 1004 (2020) p. 290

D. Planson, C. Sonneville, P. Bevilacqua, L V Phung, B. Asllani, D. Tournier, P. Brosselard, 4H-SiC PiN diode protected by narrow fields rings investigated by the OBIC method, Materials Science Forum Vol. 1062 (2022) pp 341-345

Sentaurus Device User Guide Version V-2023.12,

F. Yin, W. D. Hu, B. Zhang, Z. F. Li, X. N. Hu, X. S. Chen, W. Lu, Simulation of laser beam induced current for HgCdTe photodiodes with leakage current, Opt Quant Electron (2009) 41:805-810

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 7-12

doi: 10.4028/p-Xtm1Pm

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-01

Accepted:
2025-08-04

Online:
2025-09-10

Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

Kyrylo Melnyk , Marco Boccarossa , A.B. Renz , Q. Cao , P.M. Gammon , V.A. Shah , L. Maresca , A. Irace , Marina Antoniou

University of Warwick, Coventry, United Kingdom

University of Naples Federico II, Naples, Italy

Kyrylo.Melnyk@warwick.ac.uk, Marco.Boccarossa@warwick.ac.uk, Arne.Renz@warwick.ac.uk, Q.Cao.2@warwick.ac.uk, eP.M.Gammon@warwick.ac.uk, 'Vishal.Shah@warwick.ac.uk, Luca.Maresca@unina.it, Andrea.Irace@unina.it,

Keywords: Superjunction, Semi-Superjunction, Trench MOSFET, Planar MOSFET, High Voltage.

Abstract

This study investigates a cost-effective semi-Superjunction (SSJ) solution for 3.3 kV silicon carbide (SiC) MOSFETs, comparing planar and trench configurations. The semi-SJ method, utilizing side-wall implantation and silicon oxide trench refill, offers a practical alternative to the more complex multi-epitaxial growth approach. Through TCAD simulations, the planar semi-SJ MOSFET (planar-SSJ) achieved a reduction in specific on-state resistance ( ) and a improvement in maximum blocking voltage compared to conventional planar MOSFET. The trench semi-SJ MOSFET (trench-SSJ), depending on the deep trench angle, can further reduce the specific on-state resistance by and improve the maximum blocking voltage by , while also providing a wider implantation window and a lower gate-oxide electric field.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

Silicon carbide ( SiC ) metal-oxide-semiconductor field-effect transistors (MOSFETs) are increasingly replacing silicon (Si) in high-switching applications within the blocking voltage range of 650 V to 1700 V [1]. In high-voltage SiC MOSFETs, especially those exceeding 3000 V , the thick drift region is the major contributor to on-state resistance, resulting in conduction losses comparable to or greater than those of silicon insulated-gate bipolar transistors (IGBTs) [2]. To overcome the 1D unipolar limit of SiC MOSFETs, Superjunction (SJ) and semi-Superjunction (SSJ) technologies have been introduced, offering an improved tradeoff between conduction losses and breakdown voltage (BV) [3,4]. Unlike in Si , the commercialization of these designs in SiC faces challenges due to the complexity of forming deep p-type pillars. Two main fabrication methods exist for SJ structures: 1. Multi-epitaxial growth with shallow aluminum (Al) implants to form the p-pillar, and 2. Side-wall Al implantation through deep trenches, which are then refilled with silicon oxide ( SiO 2 ) [1-5]. Both techniques have been experimentally demonstrated in [2,4,5], with the multi-epitaxial growth method being more complex due to potential misalignment issues and the requirement for multiple implantation steps. While multi-epitaxial growth enables the implementation of a full-SJ design, sidewall implantation is typically limited by implantation angles and trench depth, favoring a semi-SJ design [2,3]. Despite these limitations, side-wall implantation offers significant on-state performance improvements with simpler fabrication steps compared to the multi-epitaxial approach.

The authors have previously introduced cost-effective methods for fabricating Schottky barrier diodes (SBDs), optimizing a semi-SJ structure, enabling the SJ effect with minimal implantation depth and wide implantation window [3,6]. In this study, a 3.3 kV SSJ SiC MOSFET is proposed using these techniques, with the goal of reducing fabrication costs and improving on-state resistance. TCAD simulations were used to evaluate and compare the performance of a standard planar structure, a planar Semi-SJ MOSFET (planar-SSJ), and trench semi-SJ MOSFET (trench-SSJ) devices.

Structure Description

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

The half-cell pitch schematic of the planar, planar-SSJ and trench-SSJ MOSFET is shown in Fig. 1, with highlighted key parameters. The planar MOSFET structure was based on [7] and adjusted to match the on-state performance in [8]. The p-base depth (tbase) of , half-cell JFET opening (wjfet) of and half-cell pitch (witch) of is in both conventional and planarSSJ designs. The channel width of and drift doping concentration of across all three designs. The half-cell pitch in the trench-SSJ design is and based on the optimization results detailed in [3], the optimal depth of the source connected trench is and (half-cell) wide (ws), with a nitrogen ( N ) n-top layer doping concentration of in both planar and trench-SSJ configurations. Note, that the active trench is protected with the p-ring implanted through the bottom of the active trench, to protect the gate-oxide from high electric fields (EFs). The depth of the p-ring is fixed at with the peak doping concentration of . The side-wall p-implantation depth ( ) is and the doping concentration is part of the design optimization .

Fig. 1. (a) planar MOSFET, (b) planar-SSJ MOSFET and (c) trench-SSJ MOSFET.

Fig. 1. (a) planar MOSFET, (b) planar-SSJ MOSFET and (c) trench-SSJ MOSFET.

On-State Performance

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

The on-state and transfer characteristics are shown in Fig. 2 (a) and (b). The channel doping concentration was calibrated to result in threshold voltage ( ) of 3.5 V at . In both onstate and off-state simulations, the fixed charge density ( ) of and trap density extrapolated from [9] was modelled at the interface between and SiC . Note, that the on-state performance of the planar-SSJ device is not affected by the side-wall doping concentration, due to a small JFET effect along the semi-SJ region [3]. This is also true for the trench-SSJ configuration, where the pitch size is smaller compared to the planar solutions. The specific on-state resistance (Ron,SP) at is and for planar (wpitch ), Planar-SSJ ( ) and Trench-SSJ ( ) MOSFETs, respectively.

Fig. 2. Planar, planar-SSJ ( degrees) and trench-SSJ ( degrees) MOSFET (a) on-state characteristics and (b) transfer characteristics.

Fig. 2. Planar, planar-SSJ ( degrees) and trench-SSJ ( degrees) MOSFET (a) on-state characteristics and (b) transfer characteristics.

This represents a and reduction in specific on-state resistance for planar-SSJ and trench-SSJ designs compared to the conventional planar MOSFET. While the on-state improvement of the trench-SSJ compared with the planar-SSJ is small, due to the introduction of a p-ring at the bottom of the active trench. However, a narrower pitch compensates for this additional resistance and also enhances the off-state performance due to an improved charge balance, which will be discussed in the next section.

Off-State Performance

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

As described in [3,6], the blocking performance of the semi-SJ structure depends on the charge balance between the side-wall p -layer and the fixed n -top layer . It is also affected by the distance between deep trenches and the trench opening (ws). The trench angle ( degrees), shown in Fig. 1, causes uneven charge distribution in the semi-SJ region compared to ideal vertical p and -pillars . The conventional planar MOSFET has a maximum breakdown voltage (BV) of 4030 V. Fig. 3 (a) shows the BV of Planar-SSJ and Trench-SSJ designs as a function of the peak sidewall doping concentration, while Fig. 3 (b) presents the simulated reverse leakage current.

Fig. 3. (a) BV versus p-implantation doping concentration and (b) off-state performance of the conventional MOSFET versus planar-SSJ ( degrees) and trench-SSJ ( degrees) with the peak side-wall doping concentration: and , respectively.

Fig. 3. (a) BV versus p-implantation doping concentration and (b) off-state performance of the conventional MOSFET versus planar-SSJ ( degrees) and trench-SSJ ( degrees) with the peak side-wall doping concentration: and , respectively.

Fig. 4. EF distribution at 3.3 kV of: (a) Planar, (b) Planar-SSJ and (c) Trench-SSJ MOSFETs.

Fig. 4. EF distribution at 3.3 kV of: (a) Planar, (b) Planar-SSJ and (c) Trench-SSJ MOSFETs.

A high doping concentration of the p-implant increases the EF at the bottom of the trench, leading to breakdown, with the n -top layer ( ) remaining under-compensated at the surface. On the other hand, a lighter p-implant doping concentration increases the EF at the surface. As a result of the higher n-top doping concentration compared to the JFET doping in the planar MOSFET, this causes premature avalanche breakdown and a significant increase in the gate-oxide EF , the n-top layer at the surface is over-compensated. The maximum blocking voltage for angles degrees is achieved when the EF along the Y -axis (cutline in Fig. 1) in the semi-SJ region becomes flatter. According to [1], in a vertical semi-SJ structure ( degrees), a perfectly rectangular EF distribution indicates a charge-balanced condition. As illustrated in Fig. 3 (a), the BV of the Planar-SSJ is 4210 V and Trench-SSJ is 4285 V , when the peak side-wall doping concentration is and , respectively.

The EF distribution for all three designs can be seen in Fig. 4, where the side-wall doping concentration is and for the Planar-SSJ and Trench-SSJ, respectively. The higher EF at the bottom of the deep trench occurs in Planar-SSJ design, resulting in a poorer off-state performance compared to the Trench-SSJ. The n-top layer in the Planar-SSJ design is overcompensated and the narrower distance between deep trenches of the Trench-SSJ design, compared to in Planar-SSJ structure, improves the charge balance, resulting in a higher offstate performance and wider implantation window (see Fig. 3 (a)). Additionally, the gate-oxide EF through the cutline AA' (denoted in Fig. 1) at 3.3 kV is and for the planar, Planar-SSJ and Trench-SSJ MOSFET, respectively.

Fig. 5. (a) BV versus p-implantation doping concentration for Trench-SSJ with trench angle of 80 and 85-degrees; Trench-SSJ EF distribution recorded at 3.3 kV : (b) 80-degree trench angle ( ) and (c) 85-degree trench angle ( ).

Fig. 5. (a) BV versus p-implantation doping concentration for Trench-SSJ with trench angle of 80 and 85-degrees; Trench-SSJ EF distribution recorded at 3.3 kV : (b) 80-degree trench angle ( ) and (c) 85-degree trench angle ( ).

Increasing the trench angle to 85 degrees, while maintaining the same trench opening ( half-cell), improves charge balance and increases the ideal BV (see Fig. 5 (a)). The EF distribution in Fig. 5 (b) and (c) is more uniform with the 85-degree angle and shows better charge balance across the semi-SJ region. This results in a maximum BV of 4389 V , when the peak side-wall doping concentration is . Additionally, the EF at the bottom of the deep trench is reduced, lowering the EF in the deep trench oxide, which will positively impact long-term reliability. However, the 85-degree trench angle increases the JFET effect, resulting in a higher Ron,SP in the trench-SSJ configuration (from to ). The on-state resistance can be reduced by narrowing the deep trench opening, but this adjustment may lead to un-implanted trench corners due to implantation angle geometry .

The performance of both Planar-SSJ and Trench-SSJ with trench angle of 80 and 85 -degrees designs, compared to the conventional planar MOSFET, is summarized in Table 1.

Table1. Static performance comparison between conventional and SSJ designs.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

In 3.3 kV SiC MOSFET devices, high on-state resistance is primarily due to the low drift doping concentration and thick drift region. The semi-SJ method discussed in this study, involves side-wall implantation and silicon oxide trench refill, which is a cost-effective solution that requires only two additional steps beyond the conventional planar or trench MOSFET process flow. This study demonstrates that the Planar Semi-SJ MOSFET (Planar-SSJ) reduces Ron,sp from to (a reduction) and improves the maximum blocking voltage from 4030 V to 4210 V (a increase) , compared to the conventional planar MOSFET. The Trench Semi-SJ MOSFET (Trench-SSJ) further reduces to (a 52 % reduction) and improves the maximum blocking voltage to 4285 V (a increase), if the trench angle is 80 -degrees. Reduction of the trench angle to 85 -degrees has the trade-off between Ron,sp ( ) and maximum BV ( 4390 V ). Additionally, both 80 -degree and 85 -degree Trench-SSJ designs show a lower gate-oxide electric field compared to the conventional and Planar-SSJ structures, which could enhance long-term reliability without a significant compromise on the on-state performance.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

The AdvanSiC project has received funding from the European Union's Horizon Europe programme under grant agreement No 101075709. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union. Neither the European Union nor the granting authority can be held responsible for them.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.7.pdf

G. W. C. Baker et al., "Optimization of 4H-SiC Semi-Superjunction Schottky Rectifiers With Implanted P-Pillars for Practical Realization," in IEEE Transactions on Electron Devices, 2022.

X. Zhong, B. Wang and K. Sheng, "Design and experimental demonstration of 1.35 kV SiC super junction Schottky diode," 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD).

K. Melnyk et al., " 3.3 kV 4H-SiC Trench Semi-Superjunction Schottky Diode With Improved ON-State Resistance," in IEEE Transactions on Electron Devices, 2024.

M. Baba, T. Tawara, T. Morimoto, S. Harada, M. Takei and H. Kimura, "Ultra-Low Specific on-Resistance Achieved in 3.3 kV -Class SiC Superjunction MOSFET," 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD).

S. Harada et al., "First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method," 2018 IEEE International Electron Devices Meeting (IEDM), 2018.

K. Melnyk et al., "Design and Optimization of 3.3 kV Silicon Carbide Semi-Superjunction Schottky Power Devices," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024.

X. Chen et al., "Different JFET Designs on Conduction and Short-Circuit Capability for 3.3 kV Planar-Gate Silicon Carbide MOSFETs," in IEEE Journal of the Electron Devices Society, 2020.

H. Kono et al., " 3.3 kV all SiC MOSFET module with Schottky barrier diode embedded SiC MOSFET," PCIM Europe Conference, 2021.

S. Yu, M. H. White and A. K. Agarwal, "Experimental Determination of Interface Trap Density and Fixed Positive Oxide Charge in Commercial 4H-SiC Power MOSFETs," in IEEE Access, 2021.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 13-20

doi: 10.4028/p-fG2SXX

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-18

Accepted:
2025-08-27

Online:
2025-09-10

A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Jihun Lim , Arman Ur Rashid , Britt Brooks , and Sei-Hyung Ryu

Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

a*jihun.lim@wolfspeed.com, armanur.Rashid@wolfspeed.com, britt.Brooks@wolfspeed.com, sei-hyung.ryu@wolfspeed.com

Keywords: power MOSFET, SPICE simulation, physics-based modeling, switching behavior, TCAD

Abstract

Wide-bandgap silicon carbide (SiC) devices have shown great promise in power control systems due to its high efficiency and thermal stability. However, the absence of predictive compact models for SiC MOSFETs has hindered the validation of these benefits in power electronics applications through circuit simulations. To address this challenge, we introduce a physics-based SPICE model (PbSM) for SiC vertical power MOSFETs. This model is composed of basic subcircuit components that represent various regions in the MOSFET structure, which are physically modeled using a technology computer-aided design (TCAD) tool. By incorporating parasitic resistors into the PbSM, we incorporate the body effect within the MOS channel model with four terminals, thereby enhancing the capability of SPICE simulations. We include theoretical output ( ) and reverse transfer capacitances ( ) to simulate transient simulations based on a double-pulse test (DPT) setup. SPICE simulation results for static and dynamic characteristics have excellent agreement with the measured characteristics of a SiC MOSFET device, confirming the capability of the model in switching characteristics with voltage distribution across the multiple components. The PbSM shows the impact of parameter variations in switching performance, which promises valuable insights for modeling of the corner cases. Finally, the PbSM is computationally efficient, showing meaningful competitiveness compared to existing SPICE models for SiC power MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Silicon carbide (SiC) has garnered significant attention in various applications due to its unique physical and electrical properties, including use in heat to electricity conversion [1], high power radiofrequency electronics [2], and power MOSFETs for switching applications [3-5]. Particularly, in the realm of sustainable energy resources, SiC power MOSFETs offers efficient power delivery with distinct advantages such as low leakage current, high efficiency, and electrical stability at high temperatures. A DMOSFET structure facilitates unipolar current operation with the source and drain electrodes vertically across a free-standing SiC substrate [6]. However, the asymmetric structure between the electrodes shows the non-linear potential distribution within the vertical structure, which poses challenges to the applicability of the equations in lateral MOSFET structures.

While empirical compact models can represent device switching behaviors in acceptable manner [7, 8], their reasonability in simulation results remains questionable due to the lack of consideration for the non-linear distribution. This limitation restricts the applicability of these models in SiC power MOSFET circuits, such as DC(AC)-DC converters [9] and motor drives [10].

In this work, we introduce a physics-based SPICE model (PbSM) that includes sub-circuit component models representing the MOS channel, junction field-effect transistor (JFET) region, p-in body diode, capacitors, and parasitic resistors. Using a technology computer aided design (TCAD) tool, we developed the component model structures for the distinct components within a SiC power MOSFET. The MOS channel is modeled using BSIM3 [11], which addresses short channel effects observed in sub-micron channel length ( ). The JFET is represented as a simple resistor, with its resistivity range estimated by considering the junction depletion width ( ) as a function of gate and drain biases. The higher resistivity of p-type SiC compared to p-type Si necessitates the inclusion of p-well resistors in the PbSM, thereby enhancing reverse recovery predictions affected by the body
effect in the MOS channel model. Input, output, and reverse transfer capacitances ( , and , respectively) are modeled based on bias-dependent . The PbSM is validated by comparing static and dynamic behaviors with the measurements from a SiC MOSFET device. Finally, the PbSM demonstrates the capability to simulate and predict circuit behaviors with varying model parameters used in the components.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Low- and High-drain Voltage Operation of a SiC power MOSFET.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 1a) describes the simplified schematic of a SiC power MOSFET, modeled using a TCAD suite. The arrows illustrate the flow of electrons at a turn-on bias condition, passing through the MOS channel, spread (dashed-line arrows), drift (straight solid-line arrows), and substrate. The space charge region (SCR) is generated at the junction, and the is expressed by:

where is the electric charge, is the relative permittivity of is the permittivity of vacuum, and are the carrier concentration in p - and n-type regions, is the built-in potential, and is the bias dropped at the junction. The mainly relies on , which critically controls the conductivity of the spread region, where the current is distributed to the SiC substrate. Under reverse bias to the junction, the expansion of to the substrate reduces the depth of the drift region ( ). Thus, both the spread and drift regions are affected by the , being retreated as a JFET region. The substrate is far away from the edge of , thereby acting as a free-standing resistor. Overall, the electrons travel from the source to drain across different regions, implying that native MOSFET models in SPICE, which traditionally target symmetric planar MOSFETs, are not compatible with the vertical DMOSFET structure.

Fig. 1. a) Cross-section for a SiC power MOSFET. The arrows indicate the flow of electrons when the MOS channel is turned on. G/I: Gate insulator, SCR: Space charge region. b) TCAD simulations for characteristics under and . The gate voltage ( ) varies from 5 to 15 V . The blue box indicates the region of . c) characteristics with extended up to 800 V . The color-shaded regions indicate the enhanced via the increase of temperature in the saturation region. d) Illustration of voltage division ( ) in linear (top) and saturation (bottom) regimes across different regions of MOS channel (Ch), spread, drift, and substrate.

Fig. 1. a) Cross-section for a SiC power MOSFET. The arrows indicate the flow of electrons when the MOS channel is turned on. G/I: Gate insulator, SCR: Space charge region. b) TCAD simulations for characteristics under and . The gate voltage ( ) varies from 5 to 15 V . The blue box indicates the region of . c) characteristics with extended up to 800 V . The color-shaded regions indicate the enhanced via the increase of temperature in the saturation region. d) Illustration of voltage division ( ) in linear (top) and saturation (bottom) regimes across different regions of MOS channel (Ch), spread, drift, and substrate.

Figure 1b) represents the simulated characteristics using the TCAD structure. The gate voltages ( ) range from 7 V to 15 V , and the cell temperatures ( ) vary from to . At 10 V , the applied voltage is primarily dropped across the spread and drift regions. The reciprocal of the slopes determines the on resistance ( ). As increases, also rises due to the increased resistivity in the spread and drift regions. This leads to a positive shift in the boundary between linear and saturation regions. Figure 1c) shows the simulation with extended up to 800 V . In the saturation regime (out of the blue box), is proportional to due to the increase in field-effect mobility ( ) in the MOS channel, which is dominated by the Coulomb scattering near the interface of [12]. The slope of the curve is influenced by channel length modulation ( ) and JFET conductivity.

A steeper slope indicates lower output resistance, ( is the parameter related to the early voltage), resulting in higher sensitivity of to . It affects the operating points and the sharpness of switching on/off states. Thus, understanding CLM and JFET conductance at high is critical for analyzing the transient responses of the MOSFET. Based on the characteristics, Figure 1d) shows the distribution of applied (assuming strong inversion in the MOS channel) across the multiple regions in linear (top) and saturation (bottom) regimes. The ratio of voltage division ( ) across the different regions is strongly dependent on and the operation modes (linear versus saturation), highlighting the importance of interpreting the non-linear voltage distribution in SiC MOSFETs for analyzing their physics-based electrical characteristics.

Fig. 2. a) Schematic of the physics-based SPICE model (PbSM). b) Simulated characteristics of the MOS channel model using the SPICE and TCAD. c) Simulated characteristics of the JFET model using the TCAD. varies from 0 to -40 V , corresponding to the estimated in the MOS channel. The dashed arc arrow indicates the possible resistance (reciprocal of the slope) variation window. The 'turn-off' means zero when the spread region is pinched-off. d) Input ( ), output ( ), and reverse transfer ( ) capacitance models. The capacitances were calculated based on doping concentration and effective device area.

Fig. 2. a) Schematic of the physics-based SPICE model (PbSM). b) Simulated characteristics of the MOS channel model using the SPICE and TCAD. c) Simulated characteristics of the JFET model using the TCAD. varies from 0 to -40 V , corresponding to the estimated in the MOS channel. The dashed arc arrow indicates the possible resistance (reciprocal of the slope) variation window. The 'turn-off' means zero when the spread region is pinched-off. d) Input ( ), output ( ), and reverse transfer ( ) capacitance models. The capacitances were calculated based on doping concentration and effective device area.

SPICE Model with Sub-circuit Components.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 2a) shows the schematic of the PbSM. The MOS channel is modeled using BSIM3, integrated with parasitic resistors ( ) associated with metal contacts and -doped region. A JFET resistor ( ), representing the spread and drift regions, is connected to the MOS channel. The substrate, with relatively high carrier concentration, is modeled as a resistor ( ), which does not significantly influence the impedance of the circuit. The three capacitances - (gate to source), (gate to drain), and (drain to source) - are connected between the electrodes. The p-i-n diode is modeled by the Compact Model Coalition (CMC) diode model [13]. The gate resistor ( ) is connected to the gate and governs the interaction between the gate capacitance and parasitic inductance.

The components in the circuit are modeled using sub-circuit device models derived from a TCAD analysis performed on the SiC power MOSFET structure shown in Fig. 1a). Figure 2b) compares the characteristics of the four-terminal MOS channel device simulated using the TCAD and SPICE tools. The body bias was set to zero. The inset shows the schematic of the TCAD-based MOS channel
structure. The linear region is closely matched between the two models, indicating that the MOS channel model in the SPICE fits the transconductance to the TCAD results. The CLM is sensitive to , contributing to short channel effects such as drain-induced barrier lowering (DIBL), which are captured using key model parameters in BSIM3, as outlined in Table 1.

Table 1. BSIM3 model parameters with the effect on current-voltage characteristics.

Parameters | Effect
ETA0 | DIBL effect coefficient at the subthreshold region
U0, Ua, Ub | Coefficients for the field-effect mobility shape
RDSW | Effect of a parasitic resistance at low Vd
DELTA | Smoothness of the curvatures at non-linear region in Id-Vd
PCLM | Regulation of the early voltage due to channel length modulation
etc. | Other parameters such as VTH0 and doping-relevant values are estimated from the TCAD simulation.

In the saturation region, the is controlled by the model parameters of DELTA and PCLM. Modeling of this variation is important for representing the output conductance ( ) of a SiC MOSFET at high . The threshold voltage ( ) is defined using a model parameter, VTH0, in BSIM3. Physically, is expressed by:

where is the flat-band voltage and is the surface potential, and are the depletion and fixed charges in the MOS channel and gate oxide, respectively. BSIM3 has the limitations in modeling and interface traps, which affect the subthreshold region and not fully represented in BSIM3.

Figure 2c) presents the characteristics of the JFET, with the inset showing a schematic of the TCAD-based JFET, including its electrodes of gate, source, and drain. In this JFET, the potential difference between the source and gate corresponds to the voltage drop across the MOS channel ( ) in the SiC power MOSFET. The TCAD simulation estimates that the can reach up to 40 V . Accordingly, the JFET simulation varies from 0 V to -40 V , resulting in the arc-shaped variation in curves. The amplitude of is limited to less than 1.2 kA , reflecting the meaningful maximum operating current of the SiC power MOSFET, as shown in Fig. 1c). In the SPICE model, the is simplified as the reciprocal of the slope corresponding to in the JFET. However, it is worth noting that using a variable could improve the accuracy of the voltage division in the SPICE simulation.

Figure 2d) illustrates the modeled , , and , which are compared to experimental results using a SiC MOSFET device. As increases, the neutral portion of the spread area is reduced due to the expansion of the by the Eq. (1), leading to a general decrease in due to the reduction of the and . is simply modeled using the Eq. (1). The is composed of the gate oxide ( ) and SiC ( ) capacitances in parallel, expressed as:

where forms across the spread, drift, and substrate. When the becomes large enough to fully occupy the spread and drift regions, kink regions, marked by circles, appear. These kinks are caused by the addition of into , as well as non-linear doping profile across the regions. The overlapped regions between electrodes remain fixed during the simulation. For simplicity,
was set to a constant value, assuming strong inversion in the MOS channel. In a real MOSFET, reaches the threshold voltage, then becomes more crucial in determining the switching performance of the MOSFET, particularly during the gate voltage plateau period [14]. Currently, using a constant does not significantly impact the switching simulation.

SPICE Model Generation for a SiC MOSFET.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 3a) represents the characteristics with ranging from 9 V to 15 V , simulated by the SPICE model (red-dashed lines), and compared to TCAD results (solid lines) and measurements (symbols) for a SiC power MOSFET. The results align closely without significant discrepancies, although the subthreshold region, which is governed by traps at the gate oxide interface, is not yet accurately modeled. Figure 3b) extends the characteristics into the saturation regime, with up to 800 V . Due to power dissipation at high voltage and high current regions, measurements were not performed at this high range and TCAD simulation results were used instead of experimental values. The is unipolar and identical to the current flowing through the MOS channel model. Therefore, the slope at high corresponds to the saturation mode in the MOS channel mode, and balancing the voltage division in the PbSM is important for controlling the operation points. It is important to note that in the saturation region determines the sensitivity of and the sharpness of the transient response. This indicates that the modeling of as a function of remains a topic for future work. Figure 3c) shows the at the third quadrant, where the current paths through the body diode or MOS channel are precisely modeled to match the measurements. As discussed earlier, the subthreshold region in the MOS channel is not properly modeled yet, resulting in the mismatch at a . In addition, the reverse recover charges ( ) and time ( )are empirically modeled [13] at a .

Fig. 3. a) Simulated characteristics using the PbSM in the linear region, compared to the TCAD and measurements using a SiC MOSFET. b) Simulated characteristics of the PbSM with the extended up to 800 V , compared to the TCAD. c) Simulated characteristics of the PbSM , compared to the measurement. d) Double-pulse test (DPT) simulations (dashed lines) compared to measurements (symbols). The top and bottom graphs indicate the turn-on and turn-off status, respectively.

Fig. 3. a) Simulated characteristics using the PbSM in the linear region, compared to the TCAD and measurements using a SiC MOSFET. b) Simulated characteristics of the PbSM with the extended up to 800 V , compared to the TCAD. c) Simulated characteristics of the PbSM , compared to the measurement. d) Double-pulse test (DPT) simulations (dashed lines) compared to measurements (symbols). The top and bottom graphs indicate the turn-on and turn-off status, respectively.

Figure 3d) presents the transient performance of turn-on (top) and turn-off (bottom) from the SPICE simulation (solid line) and measurement (symbols) using the MOSFET. The dynamic switching behavior was characterized through a Double-Pulse Test (DPT) [15]. The DPT simulation was conducted using a circuit that includes the MOSFET SPICE model along with the parasitic components from the DPT setup [16]. The SPICE results closely match the measurements, including the increase in drain current with each subsequent gate pulse. The and values are very wellmatched, meaning the reasonable design of key factors such as , and . The measurement was conducted at , with the effect of reverse recovery considered negligible.

SPICE Corner Models via Parameter Variations.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Figure 4a) illustrates the generation of several SPICE models based on device parameter variations implemented in the PbSM . The turn on/off regions are particularly sensitive to these variations and the voltage division ratio among the different components. Figure 4b) shows the impact of device parameters on and . For example, a reduction of shortens the charging time, resulting in faster switching characteristics and decreased energy losses. An increase in requires a higher and lowers the switching speed, leading to an increase in , but conversely, a decrease in . These are directly influenced by manufacturing processes such as gate oxide thickness, ion implantation, and other critical dimensions. The PbSM captures the trend of energy loss variations based on these process variations. Using the DPT method, Figure 4c) demonstrates the turn-on (top) and turn-off (bottom) characteristics. It assumes the variation of the width in the spread region ( ), changing with an arbitrary variation range of . Compared to the turn-on, the discharging amount between the drain to source and gate becomes more important in the turn-off, and it results in the noticeable positive or negative shifts.

Fig. 4. a) Illustration of the impact of device parameter variations in the and different model generations. b) Impact of the parameters on and c) Example of switching performance variations via the change ( ) in the width in the spread region ( ). The simulation used the same DPT method in Fig. 3c), which are represented by the color contours. d) Change of the relative energy loss ( ) during the transient time in c ). The arrows mean the regions of on, conduction, and off status.

Fig. 4. a) Illustration of the impact of device parameter variations in the and different model generations. b) Impact of the parameters on and c) Example of switching performance variations via the change ( ) in the width in the spread region ( ). The simulation used the same DPT method in Fig. 3c), which are represented by the color contours. d) Change of the relative energy loss ( ) during the transient time in c ). The arrows mean the regions of on, conduction, and off status.

Figure 4d) illustrates the change of the relative energy loss ( ) during the transient time. It intuitively indicates reduced energy loss with a lower . The PbSM shows high sensitivity via individual parameter variations on switching performance. However, the relationships between different parameters are uncertain (can be strongly correlated or orthogonal), which can either amplify or counterbalance the min-max ranges in corner cases. Therefore, analyzing statistical data from manufacturing is crucial to reveal the correlations between device parameters and to project the corner models using the PbSM for SiC MOSFETs.

Evaluation of Computational Efficiency.

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

Table 2 presents a performance comparison between the existing model currently available on Wolfspeed website [17], which is more behavioral with empirical fitting, and the PbSM a SiC for power MOSFET. The test circuit is a interleaved boost converter, and transient simulation analysis was performed with a total circuit run time of 50 milliseconds using LTSpice. The circuit details are provided in the previous result [18]. Compared to the existing model, the iteration numbers for transient analysis decreased by approximately . The total number of transient points evaluated increased by about . Therefore, the computation points were not significantly different between the models. Notably, the clock time for the PbSM is only about higher than the behavioral model, indicating a relatively small computational penalty for additional capability of representing physical variability of the PbSM .

Table 2. Comparison of SPICE simulation computation between a previous model and PbSM .

Test items | PbSM | Existing model [18]
Total number of Newton iterations | 219,313,034 | 299,618,943
Iteration numbers for transient analysis | 219,313,024 | 299,618,933
Transient points evaluated | 105,924,496 | 109,740,265
Clock time | 5.1 hours | 3.2 hours

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

This work presents a SPICE model, named PbSM, for SiC power MOSFETs, designed using physics-based sub-circuit components such as the MOS channel, JFET, and parasitic resistors. The sub-micron is primarily modeled using BSIM3, which controls the onset of Miller plateau region. The JFET, representing the spread and drift regions, is currently modeled as a constant resistor, which does not compromise accuracy of switching simulations. The PbSM effectively distributes the applied voltage across the different components, aiding in the understanding of key model parameters that determines the characteristics. Physics-based and closely match measurements from a SiC MOSFET device, which are important for designing turn-on/off states. The PbSM simulations depict characteristics, with the linear region validated through comparison with measurements. Though the saturation region falls beyond the scope of validation, we identify that CLM and JFET conductivity are critical for regulating . A DPT circuit, designed using the PbSM, simulates switching behaviors that align closely with measurements across the turn on, conduction, and turn off regions. The PbSM is capable of tracking trends in physics-based variations of energy losses via parameter changes, paving the way for the generation of corner models that accounts for manufacturing process variations. Finally, we propose this model with the enhanced representations of device physics, providing a powerful tool for further investigation of SiC power MOSFET applications.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.13.pdf

. Lim, J., et al., Enhanced Photon Utilization in Single Cavity Mode Air-Bridge Thermophotovoltaic Cells. ACS Energy Letters, 2023. 8: p. 2935-2939.

. Pribble, W., et al. Applications of SiC MESFETs and GaN HEMTs in power amplifier design. in 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No. 02CH37278). 2002. IEEE.

. Sabri, S., et al. New generation 6.5 kV SiC power MOSFET. in 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA). 2017. IEEE.

. Gajewski, D.A., et al. SiC power device reliability. in 2016 IEEE International Integrated Reliability Workshop (IIRW). 2016. IEEE.

. Cooper, J.A., et al., Status and prospects for SiC power MOSFETs. IEEE Transactions on Electron Devices, 2002. 49(4): p. 658-664.

. Hsu, F.-J., et al. High efficiency high reliability SiC MOSFET with monolithically integrated Schottky rectifier. in 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). 2017. IEEE.

. Arribas, A.P., et al., Simple and accurate circuit simulation model for SiC power MOSFETs. IEEE Transactions on Electron Devices, 2015. 62(2): p. 449-457.

. McNutt, T., et al., Compact models for silicon carbide power devices. Solid-State Electronics, 2004. 48(10-11): p. 1757-1762.

. Shen, Z.J., SiC research beyond power MOSFET: What's next?[Happenings]. IEEE Power Electronics Magazine, 2021. 8(2): p. 14-23.

. Stella, F., et al. Advanced testing of SiC power MOSFET modules for electric motor drives. in 2017 IEEE International Electric Machines and Drives Conference (IEMDC). 2017. IEEE.

. Cheng, Y. and C. Hu, MOSFET modeling & BSIM3 user's guide. 1999: Springer Science & Business Media.

. Pérez-Tomás, A., et al., Field-effect mobility temperature modeling of metal-oxidesemiconductor transistors. Journal of applied physics, 2006. 100(11).

. Rashid, A.U., et al. Modeling of the Snappy, and Soft Reverse Recovery of SiC MOSFET's Body Diode. in 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). 2023. IEEE.

. Baliga, B.J., Fundamentals of power semiconductor devices. 2010: Springer Science & Business Media.

. Porpora, F., et al. Accurate Data-Driven Losses Modeling for SiC-Based Converters. in 2024 IEEE Applied Power Electronics Conference and Exposition (APEC). 2024. IEEE.

. SpeedVal Kit Half-Bridge Motherboard User Guide. Available from: rboard_User_Guide.pdf.

. Moxey, G. Modeling common topologies with Wolfspeed Silicon Carbide MOSFETs. Available from: .

. 100 KHZ 10KW Interleaved Boost Converter with full SiC MOSFET. Available from: roverview.pdf

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 21-27

doi: 10.4028/p-CF6aix

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-06-05

Accepted:
2025-06-05

Online:
2025-09-10

A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

Skylar de Boer , Dinuth C.Y.B. Yapa Mudiyanselage , Seung Yup Jang , Adam Morgan , Woongje Sung

College of Nanotechnology Science and Engineering, University at Albany, State University of New York, Albany, New York, 12203 USA

NoMIS Power Corporation, Albany, New York, 12203 USA

sdeboer@albany.edu, dyapamudiyanselage@albany.edu, sjang3@albany.edu, adam.morgan@nomispower.com, wsung@albany.edu

Abstract

A novel topological layout was developed to enhance the channel density of 1.2 kV 4H-SiC MOSFETs. The innovative "Ladder" MOSFET incorporates an additional JFET and channel region, arranged orthogonally within the layout. To ensure a fair comparison, identical design rules were applied to both the Nominal and Ladder MOSFETs, resulting in calculated channel densities of 0.30 and 0.41 , respectively. Comparative analysis was conducted using Synopsys Sentaurus TCAD simulations, where three dimensional (3D) structures for both designs were generated under the same implantation and process conditions, followed by simulations of static electrical characteristics. The results indicate that the Ladder MOSFET achieved approximately reduction in specific on-resistance ( ) compared to the Nominal MOSFET. Both MOSFET designs were subsequently fabricated, packaged, and evaluated, with the Ladder MOSFET demonstrating a reduction in when comparing the best-performing devices from each design.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

4H-SiC's superior material properties enable thinner, more heavily doped drift layers that can withstand high breakdown voltages, resulting in lower specific on-resistance ( ) and making unipolar devices more viable compared to silicon-based counterparts. Consequently, MOSFETs have emerged as a promising alternative to Si IGBTs, primarily due to their low and rapid switching capabilities [1]. The adoption of MOSFETs can enhance converter efficiency and reduce cooling requirements, facilitating high-frequency operation [2]. However, the anticipated reduction in for SiC MOSFETs has not fully materialized, largely due to poor channel mobility caused by high interface state density (Dit). Despite significant improvements in channel mobility through post-oxidation annealing in nitric oxide (NO) ambient [3] and the use of accumulation mode channels [4], the typical channel mobility in the SiC industry remains around for planar MOSFETs. As a result, channel resistance continues to be the dominant limiting factor for 1.2 kV 4H-SiC MOSFETs [5].

Increasing the channel density is an effective strategy in reducing the total channel resistance within the MOSFET, by increasing the number of current pathways during the on-state. As a result more current is allowed to flow, reducing the total of the device. Modifying the channel density is primarily achieved through innovative topological designs within the active region of the MOSFET. These designs have evolved considerably from the traditional stripe pattern, leading to several novel approaches. One approach involves isolating the implanted region by placing it periodically in the orthogonal direction in the unit cell layout. This allows for an overall reduction in cell pitch, and thus a reduction in Ron,sp due to the increased channel density [6]. Other approaches include using non-linear cell designs such as the square, hexagonal, or octagonal cell layouts which further increase channel density by using non-linear geometries [7]. However, these non-linear designs can lead to geometries within the unit cell that can negatively impact device performance. [8]. In this paper, a novel 'Ladder' design is presented which increases the channel density while maintaining a linear layout to prevent degradation with other device characteristics.

Device Design

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

The proposed Ladder MOSFET incorporates an additional JFET and channel region, inserted orthogonally within the layout, as illustrated in Fig. 1. The key benefit of this additional JFET and channel region is the large increase in channel density. The channel density is calculated by dividing the area of the gate overlap over the channel and region, and dividing it by the total unit cell area. The resulting channel density was calculated to be 0.30 for the nominal MOSFET and 0.41 for the ladder MOSFET. In order to fairly compare the Nominal and Ladder layouts the same design rules were used, with a channel length ( ) of and a half JFET width ( ) of . However, the ladder layout requires an increase in the half contact width (WC) from to to maintain the same JFET design.

Fig. 1. Comparison of Nominal and Ladder MOSFET layout designs, with Wc of and and cell pitches of and , for the Nominal and Ladder MOSFETs respectively.

Fig. 1. Comparison of Nominal and Ladder MOSFET layout designs, with Wc of and and cell pitches of and , for the Nominal and Ladder MOSFETs respectively.

3D TCAD Simulations

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

3D Synopsys Sentaurus TCAD simulations were employed to conduct a comparative analysis between the Nominal and Ladder MOSFET structures, as it is not possible to fully compare these two different device types only using 2D simulations. 3D doping profiles were generated under identical implantation and process conditions using SProcess [9] as depicted in Fig. 2 for both the Nominal and Ladder MOSFETs. To obtain an accurate implantation profile, fine box meshing had to be applied near the interface. However, this kind of fine meshing cannot be used in SDevice as the simulation would have difficulty converging. Thus, a larger adaptive meshing was developed to prepare the devices for simulation, leaving finer meshing near the interface in the channel region, while increasing the mesh size further down in the MOSFET.

Fig. 2. 3D unit cell structures generated for the (a) Nominal and (b) Ladder MOSFETs, using the same implantation and process conditions. The current density distribution is plotted for crosssections and at and . Notably, cross-section C-D illustrates the utilization of the additional ladder region by the current, thus validating the Ladder Design.

Fig. 2. 3D unit cell structures generated for the (a) Nominal and (b) Ladder MOSFETs, using the same implantation and process conditions. The current density distribution is plotted for crosssections and at and . Notably, cross-section C-D illustrates the utilization of the additional ladder region by the current, thus validating the Ladder Design.

Fig. 3. Simulated (a) output and (b) transfer characteristics for the Nominal and Ladder MOSFETs.

Fig. 3. Simulated (a) output and (b) transfer characteristics for the Nominal and Ladder MOSFETs.

Subsequently, forward and transfer characteristics were simulated using SDevice [10]. The forward characteristics were simulated by first sweeping the gate voltage ( ) to 20 V and then sweeping the drain voltage ( ) to 1.5 V . The specific on-resistance ( ) was calcualted to be and for the Nominal and Ladder MOSFETs, achieving a reduction in as seen in Fig 3 (a). In Fig 2. Cross sections A-B and C-D from the Nominal and Ladder MOSFETs, respectively, are shown with the total current density plotted at and . Cross-section C-D reveals that current flows through the additional conduction path created by the Ladder region. However, the current density is higher in the Ladder region's JFET compared to the nominal JFET because the Ladder's JFET region is shorter in the z-direction. The nominal JFET region extends continuously to the adjacent unit cell, while the Ladder region's JFET is only long. Although the resistance of the Ladder JFET is greater due to the narrower opening, the Ladder region still reduces overall because it provides a parallel current path to the nominal JFET. The threshold voltage ( ) was found to be 2.53 V and 2.33 V for the Nominal and Ladder MOSFETs, respectively, when assessed at and as seen in Fig 3 (b).

Experimental Results

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

Both Nominal and Ladder MOSFETs were fabricated on 1.2 kV rated epi-layer with SiC substrates at Clas-SiC Wafer Fab in the United Kingdom, employing identical process flows and implantation recipes. A self-align process was implemented to form the Pwell/Channel. No backside grinding was conducted to thin the substrate after fabrication. Subsequently, the wafers were diced, and from each, 15 Nominal and 10 Ladder MOSFETs were selected and packaged in TO-247s.

Fig. 4. Measured (a) output characteristics and (b) transfer characteristics for the fabricated Nominal and Ladder MOSFETs. The is 3.84 and when measured at and for the Nominal and Ladder MOSFETs, respectively. The is 2.44 V and 2.20 V when measured at and for the Nominal and Ladder MOSFETs, respectively.

Fig. 4. Measured (a) output characteristics and (b) transfer characteristics for the fabricated Nominal and Ladder MOSFETs. The is 3.84 and when measured at and for the Nominal and Ladder MOSFETs, respectively. The is 2.44 V and 2.20 V when measured at and for the Nominal and Ladder MOSFETs, respectively.

Fig. 5. A direct comparison of the Output, Transfer, and Blocking characteristics for 15 Nominal and 10 Ladder MOSFETs. The Ladder MOSFETs show a reduction in the with only a reduction in Vth. The Ladder MOSFET shows only a marginal increase in leakage current compared to the Nominal MOSFET with same breakdown voltage of 1570 V .

Fig. 5. A direct comparison of the Output, Transfer, and Blocking characteristics for 15 Nominal and 10 Ladder MOSFETs. The Ladder MOSFETs show a reduction in the with only a reduction in Vth. The Ladder MOSFET shows only a marginal increase in leakage current compared to the Nominal MOSFET with same breakdown voltage of 1570 V .

Comprehensive measurements of static electrical characteristics were conducted. At and Drain Current the for the best performing Nominal and Ladder MOSFETs was measured to be and , showcasing a notable reduction in for the Ladder MOSFET. The typical output characteristics of these selected MOSFETs are illustrated in Fig. 4. Overall, Ladder MOSFETs exhibited an average reduction of in compared to their Nominal counterparts, as evidenced in Fig. 5. Additionally, the average threshold voltage ( ) at and when was measured to be 2.49 V and 2.29 V for the Nominal and Ladder MOSFETs, respectively.

The improvement of achieved through the utilization of the Ladder MOSFET design is consistently sustained even at elevated temperatures, as depicted in Fig. 6. It is interesting to observe that the temperature coefficient of the Ladder MOSFET is smaller than that of Nominal MOSFET, which may be attributed to wider contact opening.

Fig. 6. Normalized on-resistance values at varying temperatures for a typical Nominal and Ladder MOSFET. The Ladder MOSFET exhibits a slightly better temperature coefficient.

Fig. 6. Normalized on-resistance values at varying temperatures for a typical Nominal and Ladder MOSFET. The Ladder MOSFET exhibits a slightly better temperature coefficient.

Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

The Ladder MOSFET consistently outperforms the Nominal MOSFET in terms of with both the simulated and experimental results, revealing that the Ladder layouts larger channel density results in a significant decrease in the . Fig 7. (a) depicts the current density at for both simulated and best-performing fabricated Nominal and Ladder MOSFETs. The transition to the Ladder design yields similar improvements in for both sets of MOSFETs, with reductions of and , for the simulated and fabricated devices respectively. Similarly, the transfer characteristics also show a similar trend between the simulated and fabricated MOSFETs. Fig 7. (b) shows the current density for the transfer measurement when and . The was found to be 2.53 V and 2.33 V for the simulated Nominal and Ladder MOSFETs and 2.46 V and 2.24 V for the best performing fabricated Nominal and Ladder MOSFETs.

Fig. 7. (a) Output characteristics and (b) transfer characteristics compared for the simulated and fabricated Nominal and Ladder MOSFETs. A comparable improvement in is observed with fabricated Ladder MOSFETs.

Fig. 7. (a) Output characteristics and (b) transfer characteristics compared for the simulated and fabricated Nominal and Ladder MOSFETs. A comparable improvement in is observed with fabricated Ladder MOSFETs.

The 3D simulation results closely mirror the trends observed with the fabricated MOSFETs, confirming the value of 3D TCAD simulations for predicting performance in novel device designs. This breakthrough enables new device concepts to be quickly assessed and optimized prior to fabrication, avoiding the high costs associated with fabricating different device splits. This method also enables the elucidation of trends and the identification of potential flaws in the layout early on. Overall, the use of 3D TCAD simulations makes device design more efficient and cost effective.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

This study presents a novel 'Ladder' MOSFET design for 1.2 kV 4 H -SiC MOSFETs. This new layout includes an additional JFET and channel region which significantly increases the channel density. Through both 3D TCAD simulations and experimental measurements, the Ladder MOSFET demonstrates superior compared to the Nominal design. Providing another avenue for further improving the efficiency of SiC power devices. Further work should focus on further optimizing the Ladder design, exploring its effect on dynamic characteristics and reliability, and investigating its impact on lower voltage devices where the channel and JFET resistances make up a larger share of the overall .

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

This work was supported in part by the Office of Energy Efficiency and Renewable Energy (EERE), U.S. Department of Energy, the Vehicle Technologies Program Office under Award DE EE0008710. The authors would also like to thank NoMIS Power Corporation and Clas-SiC Wafer Foundry for the fabrication of the devices.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.21.pdf

J. W. Palmour, L. Cheng, V. Pala, E. V. Brunt, D. J. Lichtenwalner, G.-Y. Wang, J. Richmond, M. O'Loughlin, S. Ryu, S. T. Allen, A. A. Burk, and C. Scozzie, "Silicon Carbide Power MOSFETs: Breakthrough Performance from 900 V up to 15 kV ," in Proc. 26th Int. Symp. Power Semiconductor Devices ICs, Jun. 2014, pp. 79-82. doi: 10.1109/ISPSD.2014.6855980.

F. F. Wang and Z. Zhang, "Overview of silicon carbide technology: Device, converter, system, and application," CPSS Transactions on Power Electronics and Applications, vol. 1, no. 1, pp. 13-32, Dec. 2016, doi: 10.24295/CPSSTPEA.2016.00003.

G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, Robert A. Weller, S.T. Pantelides, Leonard C. Feldman, O. W. Holland, M. K. Das, and John W. Palmour, "Improved Inversion Channel Mobility for MOSFETs Following High Temperature Anneals in Nitric Oxide," IEEE Electron Device Letters, vol. 22, no. 4, pp. 176-178, Apr. 2001. DOI: 10.1109/55.915604.

W. Sung, K. Han, and B. J. Baliga, "A comparative study of channel designs for SiC MOSFETs: Accumulation mode channel vs. inversion mode channel," in 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), May 28- June 1, 2017, pp. 375-378. DOI: 10.23919/ISPSD.2017.7988996.

D. Kim, N. Yun, S. Y. Jang, A. J. Morgan, and W. Sung, "An Inclusive Structural Analysis on the Design of 1.2 kV 4H-SiC Planar MOSFETs," IEEE Journal of the Electron Devices Society, vol. 9, pp. 804-812, Sep. 2021. DOI: 10.1109/JEDS.2021.3109605

W. Sung, K. Han and B. J. Baliga, "Optimization of the JFET region of 1.2 kV SiC MOSFETs for improved high frequency figure of merit (HF-FOM)," 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Albuquerque, NM, USA, 2017, pp. 238241, doi: 10.1109/WiPDA.2017.8170553

K. Han and B. J. Baliga, "Comparison of Four Cell Topologies for Accumulation- and Inversion-Channel MOSFETs: Analysis and Experimental Results," in IEEE Transactions on Electron Devices, vol. 66, no. 5, pp. 2321-2326, May 2019, doi: 10.1109/TED.2019.2905736.

D. Kim et al., "A Static, Switching, Short-circuit Characteristics of 1.2 kV 4H-SiC MOSFETs Comparison between Linear and (Bridged) Hexagonal Topology," 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Redondo Beach, CA, USA, 2021, pp. 9-13, doi: 10.1109/WiPDA49284.2021.9645098.

Synopsys Inc., SentaurusTM Process User Guide, ver. T-2022.03, March 2022.

Synopsys Inc., SentaurusTM Device User Guide, ver. T-2022.03, March 2022

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 29-37

doi: 10.4028/p-lmJvs5

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-10

Single-Event-Burnout in 4H-SiC Lateral RESURF Power MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

Zhaowen , Wei , and T. Paul Chow

Rensselaer Polytechnic Institute, Troy, New York 12180, U.S.A.

ahez5@rpi.edu, bjiw2@rpi.edu, chowt@rpi.edu

Abstract

Extensive experiments and simulations indicate that Single-Event ion bombardment Effects (SEE) can trigger a Single-Event Burnout (SEB) in 4H-SiC vertical power devices at lower than half of the rated breakdown voltage. This paper investigates the SEB robustness of a 1.2 kV 4 H SiC lateral RESURF MOSFET using a 3-D electrothermal device simulator (Sentaurus) with a reported heavy ion model based on high-fidelity radiation data. The maximum ratio of 0.67 is 2.2 times higher than the reported ratio of 0.3 for a vertical DMOSFET with the same voltage rating. The reason is due to the reduced surface field at the drain terminal and the orthogonality of the heavy ion and impact ionization paths, resulting in less efficient excess carrier generation. This highlights the potential of lateral power devices for use in radiation-hardened environments.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

4H-SiC vertical power devices have long been favored in high voltage, high power applications due to the better voltage and current handling ability from the vertical architecture [1]. However, extensive experiments and simulations indicate that single-event effects (SEE) can trigger a second breakdown in vertical power devices at lower than half of the avalanche breakdown voltage [2,3]. This mode of device failure, caused by the so-called second breakdown, known as the SingleEvent Burnout (SEB), is initiated by a high electric field and has been attributed to ion-induced mesoplasma formation deep within the semiconductor bulk, ultimately leading to catastrophic thermal failure (commonly known as thermal runaway) [3,4]. Due to the fundamental differences in electric field distribution between lateral and vertical power devices, Single-Event Effects (SEEs) in lateral devices may exhibit unique characteristics. However, SEE effects in lateral power devices have hardly been investigated. In this simulation-based study, we assess the SEB robustness of a 1.2 kV 4 H -SiC lateral RESURF power MOSFET and explore the SEEs originating from different heavy ion strike locations. We have found that the lateral RESURF MOSFET to be more robust than the vertical MOSFETs against SEB.

Target Device Modeling

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

The target lateral power MOSFET, optimized for 1.2 kV , incorporates the RESURF layer and field plate designs [5], as shown in Fig 1. It has gate oxide and a lateral p-type channel connecting the source and RESURF region. An N-type RESURF region, featuring a dose of and a thickness of , is implemented between the channel and the drain to support the blocking voltage. The optimum RESURF dose for SiC with maximized breakdown voltage is . It is decreased to to prevent gate oxide breakdown since it is limited by oxide breakdown instead of avalanching in SiC [5]. In addition, the dose of the p-type epitaxial region, which has a doping concentration of and a thickness of , must match the RESURF dose to balance the charges. The lateral diffusion length of source and drain implantation is . This gives the pitch of the device to be . The device width is set to equal to the pitch.

Fig. 1. (a) Structure of target lateral RESURF MOSFET. (b) 2-D schematic crosssection of the device with doping profile. (c) Device 3-D model in Sentaurus. (d) Refined meshing for the vertical strike at drain.

Fig. 1. (a) Structure of target lateral RESURF MOSFET. (b) 2-D schematic crosssection of the device with doping profile. (c) Device 3-D model in Sentaurus. (d) Refined meshing for the vertical strike at drain.

Fig. 2. Temperature dependent thermal conductivity of used in simulations. Si thermal conductivity is added for reference.

Fig. 2. Temperature dependent thermal conductivity of used in simulations. Si thermal conductivity is added for reference.

Fig. 3. Investigated vertical and lateral strike locations labeled on 3-D model and center 2D cut plane.

Fig. 3. Investigated vertical and lateral strike locations labeled on 3-D model and center 2D cut plane.

Modeling of Single-Event Burnout

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

SEB is inherently a highly localized thermal event resulting from the significant localized current generated by the ion-induced creation of electron-hole pairs as a heavy ion passes through the device. Hence, correct modeling of ion-induced electron-hole pairs spatial distribution is vital for accurate SEB simulations. The energy transfer of a single particle with sufficient energy to target the semiconductor lattice is defined as Linear Energy Transfer (LET), the amount of energy transferred per unit length of the particle path, and is a strong function of projectile energy, density, and ionization energy of the target semiconductor [7]. In the previous works [8, 9], the 4H-SiC Silver ion collision profile (Silver ion energy: 1289 MeV , Linear energy transfer (LET): ) based on Monte Carlo approach from high fidelity radiation data has been interfaced into Sentaurus TCAD

3-D device simulator. The selection of silver ions with a LET value of was explicitly intended to maintain consistency with established testing protocols for power devices [10], facilitating comparative analysis. Further, prior SEB experiments [11] on power devices reveal that SEB failure voltage is independent of heavy ion energy for high-energy particles with a LET value above .

Table 1. Important Simulation Parameters.

Parameter | Model | Value at 300K
Thermal Conductivity [13] | κ (T) = 1 / (3.57 · 10⁻³ + 3.93 · 10⁻⁴T + 1.86 · 10⁻⁶T²) | 3.46 Wcm⁻¹K⁻¹
Lattice Heat Capacity [14] | CL = 1.82 + 3.07 · 10⁻³T - 1.28 · 10⁻⁶T² + 2.16 · 10⁻¹⁰T³ | 2.63 JK⁻¹cm⁻³
Bandgap [15] | Eg(T) = 3.342 - 3.3 · 10⁻⁴T | 3.24 eV
Impact Ionization [16] | αe(F) = 1.12 · 10⁶ exp(-8.34 · 10⁶ / F) | -
αh(F) = 2.35 · 10⁶ exp(-8.9 · 10⁶ / F) | -

Table 2. Simulated SEB threshold voltage, peak lattice temperature (@1200V), and mesoplasma location for various strike sites.

Due to the thermal nature of SEB failure, temperature-dependent models of important material parameters based on experimental data, extrapolated from room temperature to the decomposition temperature of SiC , which is approximately 3000 K , are implemented in the simulation, summarized in Table 1. Among those parameters, thermal conductivity is the key factor of SEB failure due to the positive feedback from thermal generation and degradation of thermal conductivity [3]. Fig 2 shows the extrapolated degradation of SiC thermal conductivity up to 3000 K .

Due to the 3-D nature of SEE, a 3-D electrothermal device simulation with adiabatic boundary conditions is necessary to simulate ion-induced SEB. To accurately capture the effects of heavy ions, a refined mesh along the ion path is generated (Fig 1(d)). Static blocking simulation was first performed on the target 3-D lateral RESURF power MOSFET structure to obtain the solution of continuity equation of both electrons and holes in the off state when the drain of the device is under bias. This solution was then used as the initial boundary condition to the 3-D transient adiabatic simulation. Lattice temperature and carrier distributions during SEE were solved using the
continuity equation coupled with the temperature equation. Electrode contacts are set to 300 K as the thermal boundary condition. Failure is identified when the peak local lattice temperature anywhere in the device exceeds 3000 K , the decomposition temperature of . SEE in device oxide is not investigated in this work.

Fig. 4. 2-D lattice temperature cross-sections along ion path showing mesoplasma location at peak temperature/failure at 1200 V for (a) VS1, (b) VS5, (c) VS6, (d) VS2, (e) VS3, and (f) VS4. The initial mesoplasma positions for VS2, VS3, and VS4 are also indicated in (d), (e), and (f), respectively.

Fig. 4. 2-D lattice temperature cross-sections along ion path showing mesoplasma location at peak temperature/failure at 1200 V for (a) VS1, (b) VS5, (c) VS6, (d) VS2, (e) VS3, and (f) VS4. The initial mesoplasma positions for VS2, VS3, and VS4 are also indicated in (d), (e), and (f), respectively.

Fig. 5. Electric field (blue curves) and lattice temperature (red curves) time evolution for mid-drift region strike at 1200 V (a) at the surface. (b) along the ion path.

Fig. 5. Electric field (blue curves) and lattice temperature (red curves) time evolution for mid-drift region strike at 1200 V (a) at the surface. (b) along the ion path.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

The SEB robustness of the 1.2 kV 4H-SiC lateral RESURF MOSFET is comprehensively evaluated. As illustrated in Fig 3, various strike locations correspond to critical regions of the lateral MOSFET, including the source (VS1 and LS1), channel (VS2), drift region (RESURF) (VS3, VS4, and VS5), drain (VS6 and LS2), and mid epitaxial layer (LS3 and LS4).

Six vertical strikes at various sites from source to drain are studied. Table 2 summarizes the SEB threshold voltages and peak lattice temperature when the drain is biased at 1200 V for the studied vertical strikes. From Table 2, the peak lattice temperature increases as the strike location approaches the drain side. SEB failure occurs during a vertical strike at the drain. The SEB threshold voltage for VS6 is about 700 V (Fig 6 (a)), giving a Vseb/BV rate ratio of 0.58 . This is almost twice the reported Vseb/BV rate ratio of 0.3 for the 1.2 kV vertical DMOSFET [3]. In addition, as shown in Fig 4 (a)-(c), mesoplasma remains along the ion path in case VS1, VS5, and VS6, while it drifts away to (drift region/ drain well boundary) at SiC/oxide surface as the strike location is near the device terminals (Fig 4 (d)-(f)). This phenomenon is associated with lateral and vertical electric field interaction and is never seen in vertical power devices.

Fig. 6. (a) Peak lattice temperature transients for the vertical strike at the drain under applied drain voltages of , and 600 V . (b) 2D cross-sectional view of impact ionization at the failure point. (c) Time evolution of the vertical electric field along ion path, with lattice temperature at failure overlaid. (d) Carrier concentration profiles along the ion path at failure for a vertical strike at the drain at 1200 V .

Fig. 6. (a) Peak lattice temperature transients for the vertical strike at the drain under applied drain voltages of , and 600 V . (b) 2D cross-sectional view of impact ionization at the failure point. (c) Time evolution of the vertical electric field along ion path, with lattice temperature at failure overlaid. (d) Carrier concentration profiles along the ion path at failure for a vertical strike at the drain at 1200 V .

Fig. 7. (a) Peak lattice temperature transients for investigated lateral strikes at 1200 V . 2-D crosssection of lattice temperature at failure for (b) LS2. (c) LS1. (d) LS3 and LS4. The initial mesoplasma positions for LS3 and LS4 are also indicated in (d).

Fig. 7. (a) Peak lattice temperature transients for investigated lateral strikes at 1200 V . 2-D crosssection of lattice temperature at failure for (b) LS2. (c) LS1. (d) LS3 and LS4. The initial mesoplasma positions for LS3 and LS4 are also indicated in (d).

Fig. 8. Surface electric field time evolution with lattice temperature at failure overlaid for (a) LS1. (b) LS2.

Fig. 8. Surface electric field time evolution with lattice temperature at failure overlaid for (a) LS1. (b) LS2.

Fig. 9. Peak lattice temperature transients at 1200 V for (a) vertical strike at drain (b) lateral strikes near the surface with substrate grounded or floated. (c) Electric field profile at initial and peak lattice temperature/failure along the ion path for vertical strike at drain at 1200 V . (d) Electrostatic potential contours before strike at 1200 V when substrate is grounded or floated. 100 V for each contour.

Fig. 9. Peak lattice temperature transients at 1200 V for (a) vertical strike at drain (b) lateral strikes near the surface with substrate grounded or floated. (c) Electric field profile at initial and peak lattice temperature/failure along the ion path for vertical strike at drain at 1200 V . (d) Electrostatic potential contours before strike at 1200 V when substrate is grounded or floated. 100 V for each contour.

The time evolution (Fig 5 (a) and (b)) of the surface and vertical electric field profiles along the ion path for the mid-drift region strike at 1200 V is examined at three specific points in time: at (dashed blue curve), at (dotted blue curve), and at the time of failure or peak lattice temperature is reached (solid blue curve). The surface electric field profiles (Fig 5 (a)) initially show a semirectangular shape instead of a triangular one due to surface field modulation from the RESURF region and field plates. Four noticeable electric field peaks from left to right are below the SiC breakdown field of . These four electric field peaks, suppressed by gate and drain field plates, are associated with the high electric field regions at the gate and drain corners. On the other hand, the vertical electric field profile (Fig 5 (b)) initially shows a triangular shape with a peak location at the boundary of the n -type drift region and p -type epitaxial layer. At , a noticeable electric field dip can be seen at the strike location at due to the charge neutrality of generated electron-hole pairs. This leads to the collapse of the electric field in the lateral and vertical electric field profile after the strike. At , lattice temperature along the ion path (red dotted curve) peaks at from the surface where the electric field is low, indicating the mesoplasma location. As time progresses, the electric field (solid blue curve) recovers, followed by a drop in the lattice temperature (solid red curve). On the contrary, in Fig 5 (a), the surface electric field along the drift region (solid blue curve) drops, followed by an increase in surface lattice temperature (solid red curve). These suggest that
mesoplasma has shifted from the ion path towards the drain-side surface. Two lattice temperature peaks at the surface (red solid curve in Fig 5 (a)) reach peak temperature, where their locations are aligned with the surface electric field peaks at two corners of the drain field plate. This suggests the avalanche events at the drift region drain well boundary enhance the heating. Most heating at the interface is due to the low thermal conductivity of . Despite the aid from the avalanche at the drain side, heating is subtle since the final mesoplasma location is far from the ion path for the vertical strike at the mid-drift region. Heating becomes significant as the strike location approaches the drain. Mesoplasma stays along the ion path under a strong vertical electric field near the drain. As illustrated in Fig 6 (c), the device fails at the bottom drain junction ( from the surface). This is attributed to the shortening of the ionization path caused by mesoplasma modulation of the electric field, leading to significant impact ionization at the junction. At failure, the carrier distribution along the ion path (Fig ) confirms the mesoplasma location. Notably, this location aligns with the typical damage sites observed in experimental SEB results for SiC PiN diodes [12].

SEB failures occur for lateral strikes near the surface (LS1 and LS2). The SEB threshold voltage for lateral strikes near the surface is 800 V , yielding an impressive ratio of 0.67 . This device demonstrates superior robustness to lateral strikes compared to vertical strikes (Fig 6 (c)), attributed to the reduced surface electric field (Fig 8 (a) and (b)) provided by the RESURF regions and field plates. Notably, the failure location, shown in Fig 7 (b) and (c), for both lateral strikes near the surface is at (the drift region/ drain well boundary) on the oxide interface, which is the same peak lattice temperature position observed for the vertical strikes away from the drain (Fig 4 (d)-(f)). In addition, the device withstands both lateral strikes at a depth of from the SiC surface under the full blocking voltage but with significant lattice heating (Fig 7(a)). Like vertical strikes away from the terminals, mesoplasma shifts away from the ion path due to a more substantial vertical electric field influence. It reaches its peak temperature at the same position on oxide interface (Fig 7(d)). Despite having significant heating at the boundary between the drift region and the drain well near the SiC/oxide interface, SEB occurs in neither of the lateral strikes at a depth of under the full blocking voltage since the potential drop across the ion path is about half of 1200 V . The final mesoplasma site remains distant from the ion path.

The substrate floating effect on SEB is investigated for the previously mentioned failure cases of the drain vertical strike and lateral strikes near the surface. Fig 9 (a) and (b) show the simulated peak lattice temperature transients for the studied cases. The results indicate that floating the substrate can improve vertical drain strike SEB threshold voltage to the rated 1200 V but have minimal effect on the lateral strike cases. This is because floating the substrate effectively reduces the potential drop across the vertical ion path by half (Fig 9 (d)), decreasing the electric field along the ion path in the initial boundary condition (Fig 9 (c)). However, this has a minimal effect on the lateral electric field near the surface. Hence, SEB failure is limited by the lateral strikes near the surface. Substrate floating is commonly used in Silicon-on-Oxide (SOI) technology to reduce parasitic capacitances and leakage currents. 4H-SiC lateral SOI MOSFET may be viable for radiation-robust applications.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

Unlike vertical power MOSFETs, mesoplasma formation in lateral MOSFETs is driven by comparable vertical and lateral electric fields in the drift region. Based on the investigated vertical and lateral strikes at various sites, the drain region is susceptible to ion-induced SEB. The junction boundaries at the drain are expected to be the primary SEB failure sites due to the highly localized carrier avalanche in this region. Notably, the SEB threshold voltage from vertical strikes at the drain can be enhanced to the rated voltage by floating the substrate, resulting in a maximum achievable SEB threshold voltage of 800 V limited by lateral strikes near the surface for the target 1.2 kV 4 H SiC lateral RESURF MOSFET. This results in an impressive Vseb/BV rate ratio of times higher than the reported 0.3 for conventional vertical DMOSFETs with the same voltage rating [3]. This demonstrates superior SEB robustness compared to conventional vertical DMOSFETs, as the RESURF region and gate/drain field plates effectively reduce the electric field along the ion path. Additionally, lateral strikes occur less frequently than vertical strikes due to
the generally larger vertical radiation capture cross-section. Consequently, the likelihood of SEB failure in lateral devices is expected to be lower than in vertical devices. These findings predict the high potential of lateral power devices for use in radiation-hardened environments. While experimental validation remains forthcoming, our future publications will present experimental results to further substantiate these findings.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.29.pdf

B. J. Baliga, Fundamentals of Power Semiconductor Devices, New York, NY, USA: Springer, 2008, pp. 282.

C. Martinella et al., Microelectronics Reliability, vol. 128, p. 114423, 2022.

J. A. McPherson et al., IEEE Transactions on Nuclear Science, vol. 68, no. 5, pp. 651-658, May 2021.

J. A. McPherson et al., Materials Science Forum, vol. 1004, pp. 889-896, Trans Tech Publications Ltd, 2020.

S. Banerjee et al., IEEE Electron Device Letters, vol. 22, no. 5, pp. 209-211, May 2001.

K. Chatty et al., IEEE Electron Device Letters, vol. 21, no. 7, pp. 356-358, July 2000.

T. R. Weatherford, Int. J. High Speed Electron. Syst., vol. 13, no. 1, pp. 277-292, 2003.

P. J. Kowal et al., ANS RPSD 2018, LaGrange Park, IL, USA, 2018.

J. A. McPherson et al., IEEE Trans. Nucl. Sci., vol. 66, no. 1, pp. 474-481, Jan. 2019.

J.M. Lauenstein et al., NASA Goddard Space Flight Center, Greenbelt, MD, USA, Tech. Rep. GSFC-E-DAATN39790, 2014.

C. Martinella et al., Microelectronics Reliability, vol. 128, pp. 114423, 2022.

K. Liu et al., IEEE Transactions on Electron Devices, vol. 71, no.8, pp. 4891-4896, 2024.

O. Nilsson et al., High Temp. High Press., vol. 29, no. 1, pp. 73-79, Jan. 1997.

Y. S. Touloukian and E. H. Buyco, New York, NY, USA:IFI/Plenum, pp. 448-450, 1970.

M. Lades, Ph.D. dissertation, Dept. Elektrotechnik und Informationstechnik, Technische Universität München, München, Germany, 2000.

H. Niwa et al., Mater. Sci. Forum, vols. 778-780, pp. 461-466, Feb. 2014.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 39-46

doi: 10.4028/p-e2ZeVx

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-08-08

Accepted:
2025-08-08

Online:
2025-09-10

Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

PARK Jaehoon , SUNDARESAN Siddarth , AGARWAL Aditi , MULPURI Vamsi , DAIL Steven , DONG Yu , WALSH Nathaniel

Navitas Semiconductor, 3520 Challenger St, Torrance, CA 90503, USA

ajaehoon.park@navitassemi.com, siddarth.sundaresan@navitassemi.com, aditi.agarwal@navitassemi.com, vamsi.mulpuri@navitassemi.com, steven.dail@navitassemi.com, yu.dong@navitassemi.com, nathaniel.walsh@navitassemi.com

Keywords: Planar Gate SiC MOSFET, HEXFET.

Abstract

A set of novel features for the planar gate SiC MOSFETs with the hexagonal unit cell were investigated in terms of the and reliability (HTRB/HTGB) perspectives. The fabricated SiC MOSFETs with the proposed features improved the by compared to the SiC MOSFETs with the conventional striped unit cell. From the temperature coefficient perspective (RT Vs. ), the SiC MOSFETs with the proposed features were close to the same counterpart with the marginal difference of . The SiC MOSFETs with the proposed features showed tighter and spatial distributions in comparison to the SiC MOSFETs without the proposed features. Two batches of the SiC MOSFETs with select feature were tested for HTRB under the overstressed conditions. One batch passed the HTRB test and another batch had one failure at 600 hr with no further failure up until .

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

The idea of using the hexagons to layout the unit cells of discrete power MOSFETs dates to the year 1979 when International Rectifier announced its HEXFET for the first time in history [1]. The original HEXFET concept, which proved its significance to improve the trade-off relationship between and due primarily to the geometrical advantage of the hexagon with its highest close packing density, was implemented into the planar gate SiC MOSFETs with variations of the cell topology [2-5], where the SiC MOSFET with the hexagonal unit cell from Wolfspeed showed the significant improvement of compared to the conventional SiC MOSFETs whose unit cells are strip-patterned. The SiC MOSFETs that are based on the hexagonal unit cell designs, however, have a vulnerability within its JFET region which makes the SiC MOSFETs susceptible to the high drain bias. The vulnerability arises from the region where three hexagonal unit cells meet, where the JFET spacing becomes maximized, so the electric field exerted to the interface of the region reaches its maximum. One example of such a vulnerable region is depicted in Fig. 1, where the vulnerable region is named as the unshielded region. Any portion of the gate oxide layer of the MOS stack formed directly on top of the unshielded region can be exposed to the high electric field when the drain terminal is biased high enough, and the gate oxide layer stressed can be ruptured causing a permanent failure in the form of the gate-to-drain short. The concern on the unshielded region can be notable when it is needed to ensure the reliable operation of the SiC MOSFETs in the long term.

The purpose of this work is to propose a protective measure for the unshielded region of the SiC MOSFETs whose unit cells are hexagon based, while minimizing the trade-off with the . The proposed layout features were designed as layout elements that can be added to the existing or the POR hexagonal unit cells. The unit cells with the proposed features are compared to the conventional striped unit cell layout and to the hexagonal unit cell with the unshielded region only from the perspectives of the static performance and the long-term reliability. This work concludes with the results of hour-long, preliminary HTRB tests performed on the unit cell with the select feature proposed.

Fig. 1. Typical layout of the hexagonal unit cell with the unshielded region.

Fig. 1. Typical layout of the hexagonal unit cell with the unshielded region.

Design of the Unit Cell Layouts

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

Fig. 2 shows four layout variations used for this investigation. Fig. 2(a-c) show the hexagonbased unit cells, where Fig. 2(a), 2(b), and 2(c) are called Design A, Design B, and Design C, respectively. Fig. 2(d) shows a striped-based unit cell, and is named Design D. The three hexagonbased designs (Design A, Design B, and Design C) are identical from the layout perspective, except for extra layout features that are introduced in place of the unshielded region. Design A has the unshielded region without no such extra layout feature on top of the unshielded region. Unlike Design A, both Design B and Design C have new layout features that are placed in lieu of the unshielded regions. The main differences between Design B and Design C are the shapes of the p-type Shield region and the existence/non-existence of the p-type Bridge region, where the shield and bridge region are formed where the unshielded region used to exist.

Design B, as shown in Fig. 2(b), has a triangle-shaped shield region, which is connected to its three nearby PWELL hexagons via the three corners of its triangle, where the parameter "W" shown in the same figure depicts the amount of "contact" between the triangular shield and the PWELL hexagon. As the "W" increases, the area that connects the triangular shield and the PWELL hexagon become greater, and vice versa. We varied the dimension of the "W" parameter of Design B to observe the impacts of the parameter "W" on the overall static performances of the SiC MOSFETs. Varying the parameter "W" led to two sub variations of Design B family, which are Design B1 and Design B2, where the "W" of Design B1 is smaller than that of Design B2 as shown in Table 1. Table 1 shows various unit cell topologies used for this study with the values of the parameter "W"s. Except for the "W" used, both Design B1 and Design B2 share the same layout designs.

Design C, shown in Fig. 2(c), has a regular-hexagon-shaped shield region being connected to three nearby PWELL hexagons via three bridge regions, where the widths of the three bridge regions (denoted as the parameter, "W" in Fig. 2(c)) are identical, being equal to the dimension of a side of the regular hexagon of the shield region. Varying the parameter "W" led to two sub variations within Design C family, which are Design C1 and Design C2, where the "W" of Design C1 is less than the "W" of Design C2 by referring to Table 1. Except for the "W" used, both Design C1 and Design C2 share the same layout designs.

Fig. 2. Layouts of the unit cell topologies used for this investigation: (a) Design A, (b) Design B (with two sub variations of Design B1 and Design B2), (c) Design C (with two sub variations of Design C1 and Design C2), and (d) Design D.

Fig. 2. Layouts of the unit cell topologies used for this investigation: (a) Design A, (b) Design B (with two sub variations of Design B1 and Design B2), (c) Design C (with two sub variations of Design C1 and Design C2), and (d) Design D.

Table 1. Parameter "W" (normalized) and Channel densities (normalized) of various unit cell topologies. All "W" values are normalized to the "W" of Design B1. All channel densities are normalized to the channel density of Design D.

Design | Parameter "W" (normalized) | Channel densities (normalized)
Design A | 1.22 | 1.00
Design B1 | 0.70 | 1.01
Design B2 | 1.23 | 1.01
Design C1 | 0.75 | 1.14
Design C2 | 1.00 | 1.14

Device Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

All SiC MOSFETs of this investigation were fabricated using Navitas's proprietary GeneSiC "trench-assisted planar" SiC MOSFET architecture. The fabricated SiC MOSFETs were rated at 650 V and had a chip size of . All unit cell layouts ascribed in Fig. 2(a-d), including all sub variations of Design B and Design C families, were implemented into the fabricated SiC MOSFETs.

The SiC MOSFETs fabricated with Design B2 and Design C2 were decapped/stripped off to investigate the p-type regions on the bare SiC surfaces, and the results are shown in Fig. 3. Fig. 3 shows the top-down SEM images of Design B2 and Design C2 and the mask layouts used for each design for comparison purpose. The SEM images in Fig. 3 show the shield and/or bridge regions that were perfectly aligned to their PWELL regions. The perfect alignment of the PWELL/shield/bridge regions was made possible due to the use of one single ion implantation step that formed the three
regions at the same time. As shown in the SEM images, the intricate interaction of the processing steps for PWELL and N+ source region formation with the as-drawn sub-micron bridge and shield features resulted in additional features not explicitly present in the mask layouts. For instance, the N+ source regions may also be formed within the shield/bridge regions, as observed from the SEM images in Fig. 3. Further, these N+ source regions may or may not be connected to the N+ source region within the main PWELL hexagons, which results in changes to the effective channel width of the SiC MOSFETs. Table 1 shows the channel densities of all layout design variations per unit cell to their theoretical maximum from the perspectives of the layouts.

Fig. 3. The SEM images and the mask layouts of select hexagonal unit cells in (a) Design B2 and (b) Design C2. The red dotted lines shown in the mask layouts represent the channel regions formed around the corresponding shield regions.

Fig. 3. The SEM images and the mask layouts of select hexagonal unit cells in (a) Design B2 and (b) Design C2. The red dotted lines shown in the mask layouts represent the channel regions formed around the corresponding shield regions.

The whole process steps to fabricate all SiC MOSFETs of this work were identical except for the split on the ion implantation schedules that formed the PWELL regions. The geometrical differences (the hexagons vs. the stripes) of the patterned PWELL hard masks substantially altered the doping profiles of the PWELL regions especially at/near the SiC surface (due mostly to the well proximity effect), which caused the difference of the 's of the SiC MOSFETs from the same wafer (Wafer A) as shown in Fig. 5. All SiC MOSFETs with the hexagonal unit cells featured with Design A, Design B's, and Design C's from Wafer were , where the SiC MOSFETs with the striped unit cell, i.e., Design D, from the same wafer (Wafer A) had the 's of . The difference of the 's from the SiC MOSFETs from Wafer A made it impossible to compare the SiC MOSFETs with the hexagonal unit cells (Design A/B's/C's) to the SiC MOSFETs with the striped unit cell (Design D). The difference justified the need for the wafer split at the PWELL ion implantation schedules and the new wafer (named as Wafer B) was made to meet the V TH target of the SiC MOSFETs with Design D. The SiC MOSFETs with Design D from Wafer B showed 's of as shown in Fig. 5.

Device Characterization

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

The SiC MOSFETs with all Design B's and Design C's featured with the shield/bridge regions showed the median values around as shown in Fig. 4. A direct comparison of the SiC MOSFETs with Designs C1/C2 from Wafer A against the SiC MOSFETs with Design D from Wafer B, where their median values were close to , showed improvement of the , which was due mostly to the difference of the JFET effect that originated from the difference of the hexagonal geometry of the unit cells.

Fig. 4. Static performance of the fabricated SiC MOSFETs with all designs from all wafers.

Fig. 4. Static performance of the fabricated SiC MOSFETs with all designs from all wafers.

The SiC MOSFETs with Design A featured with no shield/bridge region showed the lowest at , which was less by and by than the 's of the SiC MOSFETs with Design D from Wafer B and the 's of the SiC MOSFETs with Design B1/B2/C1/C2, respectively. The significance of the differences (by the ) among the SiC MOSFETs with all hexagonal unit cell designs can be explained by the JFET effect that originated from existence/non-existence or the differences of the shapes/sizes of the shield/bridge regions.

The SiC MOSFETs with Design C1/C2 showed lower 's than the SiC MOSFETs with Design B1/B2, which was due primarily to the JFET effect mitigated.

The 's of all SiC MOSFETs in Fig. 4 is presented in the form of the spatial distribution of the (measured at the rated voltage) across the wafers, where the left and the right ends of the horizontal axis of the plot represents the center and the edge of the wafers, respectively. The SiC MOSFETs with Design D from Wafer A and Wafer B showed the best distributions across the wafers depicted as the flat lines/profiles. The SiC MOSFETs with all hexagonal unit cell designs
(Design A/B1/B2/C1/C2) showed that their 's varied substantially across the wafer (Wafer A). The SiC MOSFETs with Design B's and Design C's, which had the shield/bridge regions, showed considerably tighter 's in their spatial distributions over the SiC MOSFETs with Design A, which had no such shield/bridge region. The SiC MOSFETs with Design C's, which had the bridge regions comparing against the Design B's with no such bridge regions, showed the best performance from the spatial distribution standpoint.

Fig. 5 shows the trends of the 's of the SiC MOSFETs with respect to the temperature ( ) of select designs (Design A/B2/C2/D), where the was varied from the RT and . The temperature coefficients are summarized in Table 2. The SiC MOSFETs with Design A with no shield/bridge region showed the lowest temperature co-efficient (RT Vs. ) of 1.08 , which was far better (by ) than the SiC MOSFETs with Design D from Wafer B, where their are equal to . The lowest temp-co of Design A can be explained due to the less JFET resistance than that of Design D. The SiC MOSFETs with Design B2/C2 showed the temperature coefficients (RT Vs. ) of 1.21 and 1.20, respectively, which were close to the SiC MOSFETs with Design D from Wafer B with the marginal difference of . The SiC MOSFETs with Design B2/C2 showed a similar performance compared to the SiC MOSFEETs with Design D from Wafer B from the temperature coefficient (RT Vs. ) standpoint.

Fig. 5. vs. of Design D, Design B2, Design A, and Design C2 for the consideration of the temperature co-efficient.

Fig. 5. vs. of Design D, Design B2, Design A, and Design C2 for the consideration of the temperature co-efficient.

Table 2. temperature coefficients with different temperature ranges.

RDS,ON Temp Co. | Wafer | Design A | Design B2 | Design C2 | Design D
RT Vs. 150°C | Wafer A | 1.08 | 1.21 | 1.20 | 1.09
Wafer B | - | - | - | 1.18
RT Vs. 175°C | Wafer A | 1.13 | 1.33 | 1.32 | 1.20
Wafer B | - | - | - | 1.30

Fig. 6 shows the results of the preliminary HTGB test (up to 500 hr ) of the SiC MOSFETs with select designs (Design B2/C2/D). The SiC MOSFETs with Design B2/C2 featured with the shield/bridge regions showed less shifts and better tightness than the SiC MOSFETs with Design D in striped unit cell. The HTGB result suggests that the shield/bridge regions from Design B2/C2 provide better protection to the gate oxide layer of the MOS stacks in comparison to Design D. The Design B2 and Design C2 did not show significant differences from this preliminary HTGB test.

Fig. 6. The results of the 500 hr HTGB tests of the SiC MOSFETs with Design B2/C2/D.

Fig. 6. The results of the 500 hr HTGB tests of the SiC MOSFETs with Design B2/C2/D.

A series of preliminary reliability tests were conducted up to 2,000 hours using the -sized SiC MOSFETs with the hexagonal unit cells featured with Design C2, and Fig. 7 shows the results of the HTRB tests performed at ( over-stressed from the rated BV).

Fig. 7. The results of the hour HTRB test at conducted on the SiC MOSFETs with the hexagonal unit cell featured with Design C2.

Fig. 7. The results of the hour HTRB test at conducted on the SiC MOSFETs with the hexagonal unit cell featured with Design C2.

Two batches ( 80 devices per batch) were used for the test. We observed that the first batch #2329010201 had one failed device with at 600 hr and there was no additional failure at 1000 hrs . The second batch #2329010401) showed no failure until 1000 hours for all device parameters considered. Each batch showed two additional failures at 1330 hr and no further failures up until 2000 hours.

It should be noted that there is a four-sided JFET depletion effect in the shielded/bridged devices (Design B2/C2) while the stripe layout (Design D) only has a double-sided JFET depletion effect. This leads to a smaller at the center of the JFET region under the condition of the high drain bias, providing extra protection to the gate oxide portion of the MOS stack.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

The shield and bridge regions for the hexagonal unit cells for the SiC MOSFETs were investigated from the static performance and/or reliability standpoints in comparison to the SiC MOSFETs of the same kind without the shield/bridge regions or to the SiC MOSFETs with the striped unit cell. The SiC MOSFETs with the hexagonal unit cell featured with the select shield/bridge design showed a reduction of the by compared to the SiC MOSFETs with the striped unit cell, with a marginally similar performance in the temperature coefficient (RT Vs. ) by . The SiC MOSFETs with the select shield/bridge regions showed tighter spatial distributions of the and in comparison to the same type of SiC MOSFETs with no shield/bridge regions. Two batches of the SiC MOSFETs with the select design were tested under the over-stressed HTRB conditions, where the first batch passed the HTRB test and the second batch had one failure at 600 hr with no further failure until . The shield/bridge regions enables the four-sided JFET depletion effect within the JFET region reducing the electric field at the center of the JFET region, providing extra protection to the gate oxide of the MOS stack.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.39.pdf

International Rectifier, HEXFET Databook 1982-1983

K. Han and B. Baliga, "The 4H-SiC OCTFET: A new cell topology with improved high-frequency figures-of-merit," IEEE Electron Device Letters, vol. 40, no. 2, pp. 299-302, 2018.

K. Han, et al., "Comparison of Four Cell Topologies for Accumulation- and InversionChannel 4H-SiC MOSFETs: Analysis and Experimental Results," IEEE Transactions on Electron Devices, vol. 66, issue 5, pp. 2321-2326, 2019.

A. Agarwal, et al., "Impact of Cell Topology on Characteristics of 600 V 4H-SiC Planar MOSFETs," IEEE EDL, vol. 40, issue 5, pp. 773-776, 2019.

S. Zhu et al, "A New Cell Topology for 4H-SiC Planar Power MOSFETs and Comparison with Hexagonal and Octagonal Cell Topologies," IEEE WiPDA, 2022.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 47-52

doi: 10.4028/p-cQ6d4V

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-10-02

Revised:
2025-08-01

Accepted:
2025-08-04

Online:
2025-09-10

A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

Xiaofan Ma , Mattias Ekström , Carl-Mikael Zetterling

KTH Royal Institute of Technology, Isafjordsgatan 22, SE-164 40 Kista, Sweden

xiaofanm@kth.se, mekstr@kth.se, bellman@kth.se

Keywords: Silicon Carbide (SiC), Lateral PiN Diode, Semiconductor Device Manufacture, HighVoltage Semiconductor Diodes and Integrated Circuit.

Abstract

With its excellent thermal conductivity, high critical breakdown field strength, and high temperature tolerance, Silicon Carbide (SiC) is widely used in the fabrication of power devices. In recent years, many vertical high-voltage SiC PiN diodes with superior performance have been reported. However, since the cathode-anode voltage in these devices is vertically blocked in the semiconductor, the on-chip isolation between the devices is difficult to achieve. For this reason, the vertical power device is typically employed for high power densities in single-device packages or power modules. In contrast, effective isolation between lateral high-voltage devices can be achieved by using isolation structures, which enables monolithic integration with lateral PiN diodes, transistors, and resistors to achieve control, routing, and power density regulation in smart powerintegrated circuits (ICs). This work describes the design and fabrication process of a novel SiC high-voltage lateral PiN (HVLPN) diode with the addition of a lateral isolation structure with a thickness of to achieve sufficient isolation between breakdown voltages and devices, as well as a solution for the deep etching of the SiC over with a thick enough Hard Mask (HDM), which is required for the actual fabrication process.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

SiC devices have seen significant advancements in power applications due to their hightemperature temperature tolerance, high switching frequency, and superior efficiency to siliconbased devices [1,2]. One of the promising areas of development is the integration of power transistors with additional control, diagnostic, and protection functions. This concept, like smart discrete silicon de- vices, enhances performance by reducing internal parasitic impedance for faster switching and offering better robustness and reliability. These advancements make SiC devices ideal for applications in aerospace, nuclear energy, oil drilling, and automotive sectors, where power management robustness is crucial [3].

Power ICs using SiC are still in the developmental stages, but their potential is widely recognized for high-temperature operations. Several researchers have demonstrated the use of 4H-SiC bipolar technology to develop differential amplifiers, linear voltage regulators, and widebandgap voltage references that can operate at temperatures up to [4-6]. Moreover, digital ICs using 4H-SiC depletion-mode JFETs have shown short-term operational capacity at up to [7]. However, there are still challenges such as high gate leakage current at elevated temperatures. Current efforts are focused on integrating power transistors with SiC-based smallsignal circuits, to improve power IC performance in high-frequency power conversion applications [8].

The monolithic integration of power transistors and ICs is a primary emphasis in SiC device manufacturing. Monolithic integration denotes the combination of various functionalities - such as driving, diagnosing, and protecting - onto a singular chip [9]. This technology is essential for developing high- performance, dependable, and resilient power devices, particularly for rigorous applications like power converters and intelligent power circuits. Researchers have established the viability of co-integrating vertical and lateral SiC Bipolar Junction Transistors (BJTs) on a single wafer utilizing conventional power BJT methodologies [10]. This methodology also possesses the considerable potential for developing analog and logic circuits for power ICs.

Vertical devices are favoured in high-power density applications because they can effectively block voltage in a vertical orientation, facilitating high power density in single-device packages or modules [11]. Nonetheless, these devices encounter difficulties in attaining on-chip isolation. Lateral devices provide simpler isolation structures, rendering them appropriate for monolithic integration in smart power-ICs. Although lateral devices exhibit a lower power density than vertical devices, they are advantageous for incorporating supplementary functionalities, such as control and regulation, essential for power-IC applications [12]. This research introduces an innovative design of a SiC HVLPN with a thick blocking layer, with the fabrication process and simulation results showing a 1000 V diode for monolithic IC applications.

Device Structure and Simulation Results

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

The HVLPN structure is shown in Fig. 1(a). Fig. 1(b) illustrates the 3D structure of HVLPN. Based on the simulation results shown in Fig. 2(a), the typical diode behaviour shows a forward voltage of about 2.5 V . Fig. 2(b) shows a trench with a depth to was needed to achieve a breakdown voltage of about 1000 V . With a isolation trench around the device, combined with the deep blocking area, devices can be effectively blocked, which allows further research into the manufacture of ICs and opens up the possibility of combining power devices with logic and memory circuits. With a doping concentration of in the drift layer, the blocking layers need to be thick to achieve the breakdown voltage and sufficient isolation between devices. The simulation results of this novel structure were obtained with Sentaurus TCAD.

Fig. 1. (a) Schematic cross-sectional view of the SiC HVLPN simulated and fabricated in this work. The figure is not to scale in the -axis. (b) The 3D microscope picture of the HVLPN, photographed by Nikon L200ND microscope after mesa etch and HDM mask removed.

Fig. 1. (a) Schematic cross-sectional view of the SiC HVLPN simulated and fabricated in this work. The figure is not to scale in the -axis. (b) The 3D microscope picture of the HVLPN, photographed by Nikon L200ND microscope after mesa etch and HDM mask removed.

Fig. 2. (a) Forward I-V simulation results for the SiC HVLPN. (b) Breakdown voltage versus depth of trench between the anode and cathode implants. Simulation results from Sentaurus TCAD.

Fig. 2. (a) Forward I-V simulation results for the SiC HVLPN. (b) Breakdown voltage versus depth of trench between the anode and cathode implants. Simulation results from Sentaurus TCAD.

Fabrication Procedure

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

Fig. 3 shows the major processing flow. Fabrication of the physical devices was finished in KTH Electrum's cleanroom. The HVLPN can be fabricated with the same vertical power PiN fabrication process without an extra mask or processing step.

Fig. 3. Major process flow of HVLPN fabrication.

Fig. 3. Major process flow of HVLPN fabrication.

Initial wafers fabricating the HVLPN device comprise 2 epitaxial layers and an substrate. The N -drift layer was thick and doped at . The P-isolation layer was doped at . Phosphorus and aluminium are chosen as the implantation elements to form the region at the anode and the region at the cathode, respectively. After that, the implanted ions were activated by annealing in Ar ambient for 15 min with a protective carbon cap.

The trench between the anode and cathode was etched by reactive ion etching (RIE) using plasma- enhanced chemical vapour deposited (PECVD) as HDMs. The width of the trench varies from 1 um to 30 um , and its depth was set to 1 um and 2 um for different wafers. The trench isolation structure was also etched in the same way.

To obtain thick blocking layers, achieve 1000 V breakdown voltage and sufficient isolation between devices, deep SiC etching of more than is required for fabrication. Surface passivation is necessary to reduce the etching surface defects and increase the quality of the interface. The use of nickel ( Ni ) or chromium ( Cr ) as HDM materials for SiC Inductively Coupled Plasma (ICP) etching has been demonstrated to facilitate deep etching of SiC . Both Ni and Cr have been shown to exhibit high etch selectivity for SiC etching and surface integrity of the mask after etching. A lift-off technique was employed to pattern the mask to reduce micro-patterning. As shown in the processing flow diagram Fig. wafers are used for this work. At first, a layer of lift-off resist (LOR , MicroChem ) is spun on the wafer, followed by the
coating of a layer of photo-resist (SPR 700, MICROPOSIT ). The PR and LOR layers are patterned simultaneously by photo-lithography, and undercuts between these two layers are formed. Then a Cr , or heterogeneous metal layer, is formed by e-beam metal evaporation with a thickness of about 400 nm . Then the wafers are soaked in resist remover with ultrasonic washing until lift-off is finished. Eventually, the patterns are transferred to the metal HDM. SiC deep etching is performed with ICP using and . The etching selectivities were 55 and 40 for Ni and Cr masks, respectively. The ICP parameters for the SiC deep etching are shown in Table 1.

Fig. 4. Detailed processing flow of HDM patterning and SiC deep etching.

Fig. 4. Detailed processing flow of HDM patterning and SiC deep etching.

Table 1. SiC deep etching recipe.

ICP Parameters |
Pressure [mTorr] | 5
SF₆ flow rate [sccm] | 55
O₂ flow rate [sccm] | 10
Coil power [W] | 800
Platen power [W] | 75

About 20 nm of thermal oxide is grown at in dry oxygen. Then the sacrificial oxidation was stripped by BHF. The sacrificial oxidation after ICP etching helps to reduce etch surface defects. Polysilicon was deposited on the wafer. After that, the wafers were annealed in and then . The following post-oxidation annealing in has a positive effect on the interface.

After thick PECVD deposition, CMP planarization is used before the IC interconnect layers. After the CMP planarization, the contact holes on cathodes and anodes were opened with the RIE etching of , and the contact holes on isolation structures were opened with BHF wet etching. The self-aligned ohmic contacts were formed by sputtering 20 nm of Ni on the surface and then annealing at for 60 seconds and for another 60 seconds. Finally, 100 nm TiW and of Al were sputtered on the surface, patterned with lithography and then etched by using RIE to achieve metallization contact and measurement pads. Finally, the protective overglass layer was deposited with PECVD and then etched with RIE.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

As shown in Table 2, Ni HDM shows better etching selectivity under the same etching environment. A passivation layer of Ti between Ni and SiC can help to adhere to the Ni and reduce the surface stress of the Ni layer during evaporation, thus preventing flakes from appearing on the Ni surface. Fig. 1(b) also shows the microscope image after deep etching of SiC in the mesa region.

However, upon observation (Fig. 5(a)), it was found that this ICP etching would affect the already existing structure. Some irregular micro-peaks as high as 3 to appeared at the edge of the previously etched trench, and the reason for this phenomenon was speculated to be due to the anisotropy of the ICP etch at the edge of the trench.

Table 2. SiC deep etching results.

HDM | Ni | Cr
Mask thickness before etching [nm] | 362 | 409
Etch time [min] | 60 | 70
Mask thickness after etching [nm] | 206 | 114
SiC etch depth [nm] | 10855 | 12731
SiC etch rate [nm/min] | 181 | 182
Mask etch rate [nm/min] | 2.6 | 4.2
Etching selectivity | 69 | 43

In order to evaluate the electrical blocking effect, a contact hole to the p-type isolation layer is necessary, achieved here with BHF for etching. Due to the isotropic etching rate characteristic of BHF wet etching, the etched isolation contact hole shows transverse expansions up to three dozen wide around the periphery at the longitudinal etching depth of 13 to , as shown in Fig. 5(b). In this process, the etching rate of in BHF was approximately . Due to the instability of BHF wet etching, other alternatives may be considered in the future, such as dry etching using the ICP technique.

Fig. 5. (a) Micro-peaks formed on preexisting features after ICP etching. (b) Microscope image of the HVLPN with the isolation contact hole.

Fig. 5. (a) Micro-peaks formed on preexisting features after ICP etching. (b) Microscope image of the HVLPN with the isolation contact hole.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

The study introduces a new SiC-based HVLPN diode aimed at improving power ICs, particularly for high-temperature and high-power applications. Using a thick blocking layer and SiC deep etching technique, the design can achieve a breakdown voltage of 1000 V with forward voltage per- formance suitable for future monolithic integration of power transistors. The fabrication process used conventional power PiN methods, validating the potential of this diode for reliable, high-performance power electronics, and opening avenues for combining power devices with logic and memory circuits. Simulation results further confirm the effectiveness of the proposed structure.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.47.pdf

M. Kaneko, X. Chi, T. Kimoto, J. IEEE Trans. Electron Devices. 67 (2020) 3329-3334.

Y. Zhang, Y. Ou, J. Luo, et al, J. Semicond. Sci. Technol. 37 (2022) 075017.

L. Lanni, B. G. Malm, M. Östling, and C.-M. Zetterling, IEEE Electron Device Lett. 35 (2014) 428-430.

Y. Tian, L. Lanni, A. Rusu, and C.-M. Zetterling, IEEE Trans. Electron Devices. 63 (2016) 2242-2247.

S. Kargarrazi, H. Elahipanah, S. Rodriguez, and C.-M. Zetterling, IEEE Electron Device Lett. 39 (2018) 548-551.

R. Hedayati, L. Lanni, A. Rusu, and C.-M. Zetterling, IEEE Electron Device Lett. 37 (2015) 146-149.

P. G. Neudeck, D. J. Spry, L. Chen, N. F. Prokop, and M. J. Krasowski, IEEE Electron Device Lett. 38 (2017) 1082-1085.

S. Liang, J. Wang, L. Deng, et al. IEEE J. Emerging Sel. Top. Power Electron. 8 (2019) 24-30.

M. Alexandru, V. Banu, J. Montserrat, et al. J. ECS Transactions 58 (2013) 375.

Y. Gao, A.Q. Huang, A.K. Agarwal, et al. IEEE. 2008: 233-236.

T. Erlbacher, Lateral power transistors in integrated circuits, 1st ed., Springer, 2014.

M. Rose, H. J. Bergveld, J. IEEE Solid-State Circuits. 51 (2016) 1965-1974.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 53-58

doi: 10.4028/p-5hB3s2

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-12

Revised:
2025-02-10

Accepted:
2025-02-12

Online:
2025-09-10

Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

Philip G. Neudeck , Christina M. Adams , Michael J. Krasowski , David J. Spry , and Norman F. Prokop

NASA Glenn Research Center, 21000 Brookpark Rd, Cleveland, OH 44135 USA

Neudeck@nasa.gov, christina.m.adams@nasa.gov, michael.j.krasowski@nasa.gov, david.j.spry@nasa.gov, norman.f.prokop@nasa.gov

Keywords: High Temperature, Junction Field Effect Transistor (JFET), Integrated Circuit, SPICE

Abstract

This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated "IC Gen. 12" and "IC Gen. 13". Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n -channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

NASA Glenn Research Center has previously reported the world's first and only semiconductor integrated circuits (ICs) to demonstrate stable electrical operation for over a year at . However, these initial prototype 4 H -SiC Junction Field Effect Transistor-Resistor (JFET-R) chips were of limited circuit complexity (< 200 transistors per chip) and require detrimentally higher voltage, current, and power compared to functionally equivalent conventional-temperature silicon chips. Further upscaling of circuit complexity while reducing power consumption is clearly crucial towards realizing impactful infusion of SiC JFET-R ICs into extreme environment applications.

This work compares design layouts and circuit simulations of the next two planned SiC JFET-R IC prototype fabrication runs designated "IC Generation 12" and "IC Generation 13". These designs are based upon foundational mask layout and SPICE modeling guides posted online for these respective technologies [2].

JFETs & Resistors

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

Both Gen. 12 and Gen. 13 prototypes follow the same general fabrication flow as for earlier-generation NASA Glenn SiC JFET-R ICs [3]. However, IC Gen. 13 will employ stepper-based patterning that effectively eliminates alignment errors while enabling smaller feature sizes compared to contact mask aligner lithography layout rules employed for IC Gen. 12 design. Key technology parameters for these runs are summarized in Table 1. Both prototypes feature the same overall chip/die size of 5 mm x 5 mm and the same JFET gate length of . The gate length was not

Table 1. Key SiC JFET-R IC technology parameters.

Parameter
IC Gen. 12
IC Gen. 13*

Chip Dimensions
5 mm x 5 mm
5 mm x 5 mm

Resistor Width WR
2 μm
1 μm

Gate Length LG
3 μm
3 μm

JFET Threshold Voltage VT0
-9.4V (25°C, 1 cm)
-11.4V (25°C, 2 cm)
-12.1V (500°C, 2 cm)
-2.89V (25°C)
-3.47V (500°C)

JFET IDSS for VS = 0 (μA/μm)
76.8 (25 °C, 1 cm)
97.5 (25 °C, 2 cm)
35.75 (500 °C, 2 cm)
18.3 (25°C)
6.12 (500°C)

reduced for IC Gen. 13 design in
order to manage the combined risks of epilayer variations [4,5] and short-channel effects [6] adversely impacting JFET turn-off characteristics. Once improved reproducibility and uniformity of SiC JFET epilayers is achieved in the future, smaller gate lengths will become more practical with acceptably lower risk. The width of SiC n -mesa resistors was halved which enabled significantly smaller layout areas for realizing Gen. 13 integrated n-mesa resistors compared to same-value Gen. 12 resistors. Modest additional Gen. 13 resistor layout area efficiency was also facilitated by elimination of Gen. 12 resistor mesa layout shape restrictions [2].
Towards the goal of reducing JFET IC power consumption, IC Gen. 13 technical procurement specifications requested a thinner n-channel epilayer than for IC Gen. 12 [2]. The JFET electrical properties of the respective Gen. 12 and Gen. 13 prototypes calculated for zero substrate bias Vs are given in Table 1. The gate and n -channel epilayer doping and thickness profiles employed for these calculations are based upon the Secondary Ion Mass Spectroscopy (SIMS) measurements [7] (Fig. 1) conducted on selected procured Gen. 12 and Gen. 13 epiwafers [8]. Consistent with trends observed in prior JFET-R IC prototype generations [4,5], IC Gen. 12 SIMS results indicate a consequentially thicker n -channel near the wafer edge than near the wafer center. The JFET threshold voltage is therefore a function of device distance from the center of the wafer for IC Gen. 12, as can be seen by comparing calculated values for 1 cm and 2 cm distance from wafer center shown in Table 1 [9]. Remarkably however, SIMS results from IC Gen. 13 epi-wafers did not resolve any difference in n -epilayer thickness between the wafer center and wafer edge. As a result, IC Gen. 13 JFET SPICE models were accordingly updated as independent of device position on the wafer [10]. The significantly smaller magnitudes for calculated and saturation current Idss shown in Table 1 are a direct result of significantly thinner channel of Gen. 13 compared to Gen. 12.

Fig. 1. SIMS-profile comparison of IC Gen. 12 (dashed) vs. IC Gen. 13 (solid) gate [Al] and n -channel [ N ] epilayer profiles measured near wafer center.

Fig. 1. SIMS-profile comparison of IC Gen. 12 (dashed) vs. IC Gen. 13 (solid) gate [Al] and n -channel [ N ] epilayer profiles measured near wafer center.

All SPICE simulations were conducted using NASA-posted SPICE models in both LTSPICE [11] and T-SPICE [12]. It is important to note that the NASA SPICE models are first-order approximations of expected behavior (derived from combination of earlier JFET-R run results and device-physics calculations) that remain to be fully validated after Gen. 12/13 fabrication is completed. Figure 2 compares SPICE-simulated Gen. 12 and Gen. 13 JFET current vs. voltage (I-V) characteristics. Fig. 2a compares simulated drain current vs drain voltage characteristics with the bulk/substrate voltage . Both devices are "depletion-mode" in that negative gate voltage must be applied to turn off the transistor current flowing from source to drain. As expected, the thinner-channel Gen. 13 JFET exhibits lower Id as well as turn-off at less-negative applied gate voltage VG. Fig. 2b compares the SPICE-simulated Id vs turn-off characteristics at and for drain bias (i.e., in saturation), but with bulk/substrate bias set to respective negative power supply values for Gen. for Gen. 13) employed for IC operation. The y -axis of Fig. 2b is in order to (1) normalize current to gate width , and (2) illustrate as the x-intercept of the plots (since saturated . The non-negligible
substrate/body bias effect [4] shifts to less-negative values that values shown in Table 1. The shift in to more negative values as temperature increase is caused by reduction of pn junction built-in potential with temperature, which results in modest shrinkage of the depletion widths that modulate n-channel drain current conduction.

Fig. 2. Comparison of calculated IC Gen. 12 (green) vs. IC Gen. 13 (red) JFET I-V characteristics. (a) vs. for zero substrate bias. (b) ( vs. turn-off characteristics for Vs set to the technology's negative power supply value Vss ( -25 V for Gen. 12 and -10 V for Gen. 13).

Fig. 2. Comparison of calculated IC Gen. 12 (green) vs. IC Gen. 13 (red) JFET I-V characteristics. (a) vs. for zero substrate bias. (b) ( vs. turn-off characteristics for Vs set to the technology's negative power supply value Vss ( -25 V for Gen. 12 and -10 V for Gen. 13).

Logic Gates

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

Figure 3 shows the electrical schematic diagrams of Gen. 12 and Gen. 13 "base power" NOT logic gates. The circuit diagrams are essentially identical except that IC Gen. 13 features larger resistor values (enabled by more-compact resistor layouts) and smaller power supply voltages (enabled by smaller magnitude of JFET Vt). The more than 2-fold increase in Gen. 13 resistor values reflects a design choice to substantially reduce Gen. 13 logic gate power consumption relative to Gen. 12 (even at the expense/tradeoff of increased logic propagation delay) to help thermally manage higher number/density of gates in a Gen. 13 chip. The Fig. 4 mask layout drawings of the Fig. 3 NOT circuits confirm that 3 to 4 times as many Gen. 13 logic circuits can be packed into a comparable chip area than for Gen. 12. SPICE-simulated VIN vs. Vout DC transfer characteristics of these NOT logic gates at and are plotted in Fig. 5. Despite the large differences in quantitative transistor characteristics with temperature (Fig. 2), the logic voltage transfer curves exhibit insignificant temperature dependence consistent with prior NASA SiC JFET-R IC results .

Fig. 3. NOT logic gate schematic diagrams. JFET gate width/gate length is shown along with number of squares for each SiC resistor.

Fig. 3. NOT logic gate schematic diagrams. JFET gate width/gate length is shown along with number of squares for each SiC resistor.

Fig. 3. NOT logic gate schematic diagrams. JFET gate width/gate length is shown along with number of squares for each SiC resistor.

Fig. 3. NOT logic gate schematic diagrams. JFET gate width/gate length is shown along with number of squares for each SiC resistor.

Fig. 4. Comparison of IC Gen. 12 (top) and 13 (bottom) NOT logic gate IC layouts [2]. Almost 4fold smaller area is enabled for IC Gen. 13 via stepper-based lithography. See [2] for details.

Fig. 4. Comparison of IC Gen. 12 (top) and 13 (bottom) NOT logic gate IC layouts [2]. Almost 4fold smaller area is enabled for IC Gen. 13 via stepper-based lithography. See [2] for details.

Table 2 quantitively compares a variety of relevant performance benchmarks of the SPICEsimulated logic gates. The Gen. 13 circuit beneficially enables more than 10 -fold reduction in simulated maximum power consumption compared to Gen. 12 logic gate, but at the penalty of significantly reduced operating frequency/speed.

Fig. 5. Comparison of Gen. 12 and Gen. 13 Single Not Gate DC Transfer Curve at (dotted) and (solid).

Fig. 5. Comparison of Gen. 12 and Gen. 13 Single Not Gate DC Transfer Curve at (dotted) and (solid).

Complex ICs

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

With the performance trends of foundational JFETs, resistors, and logic circuits established, it is useful to benchmark the resulting impact on complex integrated circuits and systems. Table 3 quantitatively compares application-relevant circuit metrics obtained for the most complex circuits that were designed for implementation in both IC Gen. 12 and IC Gen. 13. In particular, Random Access Memory (RAM, using 6-transistor memory cells [1]), Read Only Memory (ROM, using single-transistor fabrication-mask programmed memory cells), Venus lander sensor digitization and control subsystem, and simple microprocessor [14] circuits were designed for implementation.

Table 3 quantitatively compares key metrics (at application-desired high ambient temperature) for these four higher complexity Gen. 12 and 13 circuits obtained during SPICE simulations and chip layout.

Table 2. Comparison of SiC JFET-R IC basic logic gate parameters.

Parameter
IC Gen. 12
IC Gen. 13
12/13 Ratio

Layout Area
11021 μm²
3016 μm²
3.65X

Power Supply
± 25 V
± 10 V
2.50X

Level Shifter Resistor
(MΩ)
0.229 (25°C, 2 cm)
0.880 (500°C, 2 cm)
0.430 (25°C)
1.672 (500°C)
0.53X
0.53X

Output High Voltage
VOH (V)
-2.89 (25°C, 2 cm)
-3.14 (500°C, 2 cm)
-0.46 (25°C)
-0.36 (500°C)
*
*

Output Low Voltage
VOL (V)
-10.8 (25 °C, 2 cm)
-10.8 (500 °C, 2 cm)
-4.64 (25°C)
-4.38 (500°C)
*
*

Noise Margin Low
NML (V)
4.5 (25 °C, 2 cm)
4.24 (500 °C, 2 cm)
2.95 (25°C)
2.37 (500°C)
1.53X
1.79X

Noise Margin High
NMH (V)
2.31 (25°C, 2 cm)
2.26 (500 °C, 2 cm)
0.93 (25°C)
1.34 (500°C)
2.48X
1.69X

Maximum Power
(mW)
5.14 (25°C, 2 cm)
1.45 (500 °C, 2 cm)
0.47 (25°C)
0.12 (500°C)
10.9X
12.1X

3-Stage Ring Osc.
Frequency (MHz)
3.70 (25°C, 2 cm)
0.99 (500 °C, 2 cm)
0.68 (25°C)
0.27 (500°C)
5.4X
3.7X

Table 3. Comparison of complex IC Gen. 12 and IC Gen. 13 SPICE circuit simulation results.

Benchmark IC | Performance Metric | IC Gen. 12 | IC Gen. 13 | IC Gen. 13 Improvement
Random Access Memory (RAM) | Storage Capacity | 248 (31×8) bits | 1024 (128×8) bits | 4.1X
500 °C Chip Power | 1.1 W | 0.33 W | 3.3X
Power per bit | 4.4 mW/bit | 0.32 mW/bit | 14X
Read Only Memory (ROM) | Storage Capacity | 2048 (128×16) bits | 5376 (256×21) bits | 2.6X
500 °C Chip Power | 0.9 W | 0.13 W | 6.9X
Power per bit | 0.44 mW/bit | 0.024 mW/bit | 18X
Microprocessor | # of Chips Needed | 2 | 1 | 2X
Data Bus Width | 8 | 16 | 2X
500 °C Circuit Power | 1.3 W | 0.15 W | 8.6X
Venus Lander Control Circuit | # of Chips Needed | 5 | 1 | 5X
460 °C Circuit Power | 0.6 W | 0.061 W | 10X

The numerical degree/ratio of Gen. 13 metric improvement over Gen. 12 is shown in the last column. For the memory IC designs, Gen. 13 technology more than doubles single-chip data storage capacity. This is simultaneously achieved while reducing power consumption to less than of the power needed to operate the corresponding Gen. 12 memory chips of much smaller data storage capacity. Likewise, Table 3 shows even larger degree ( ) of power consumption improvement for the Gen. 13 Venus lander and microprocessor circuits compared to Gen. 12 (despite the expansion of the microprocessor's data/address bus width from 8 bits to 16 bits). The Venus lander and the microprocessor circuits were too large to fit within maximum chip size using Gen. 12 layout rules. As a result, multiple chips are needed (as shown in Table 3) to implement these Gen. 12 circuits. In contrast, IC Gen. 13 enables highly advantageous monolithic single-chip implementation. Such "system on a chip" realization greatly reduces overall electronic system packaging requirements, functional cost, and other implementation barriers including technical risk. So long as other factors (such as IC robustness) are not compromised, the superior capabilities of IC Gen. 13 can be expected to pave the technical path for further maturation, manufacturing, and beneficial application infusions of durable SiC JFET ICs.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

Even though both IC Gen. 12 and IC Gen. 13 prototype designs employ the same physical JFET gate length and chip size , SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are: (1) IC Gen. 13 n-channel epilayers are both thinner and completely uniform across each wafer, and (2) the switch to stepper-based photolithography for IC Gen. 13 enables smaller layouts to be implemented for functionally identical circuit blocks. This simulation study confirms that SiC JFET-R IC Gen. 13 offers novel "system on a chip" beneficial capabilities to extreme environment applications.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

This work was conducted by The NASA John H. Glenn Research Center in Cleveland, OH USA with funding from the NASA Science Mission Directorate under the High Operating Temperature Technology (HOTTech) the NASA Aeronautics Research Mission Directorate under the Transformational Tools and Technologies (TTT) project. The authors are grateful for the supportive assistance of L. Greer, S. Rajgopal, G. Hunter, and D. Centeno-Gomez.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.53.pdf

P. Neudeck et al., Proc. 2018 IMAPS Int. High Temperature Electronics Conf. (HiTEC 2018), https://ntrs.nasa.gov/citations/20180003391

P. Neudeck, JFET IC Tech Guide,

D. Spry et al., "Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits", presented at 2016 IMAPS Int. High Temperature Electronics Conf. (HiTEC 2016),

P. Neudeck, D. Spry, L. Chen, Mat. Sci. Forum, vol. 828, pp. 903-907 (2016),

P. Neudeck, D. Spry, L. Chen, Proc. 2016 IMAPS Int. High Temperature Electronics Conf. (HiTEC 2016), pp. 263-271,

M. Mehta, P. Neudeck, J. Lawson, Materials Science Forum, vol. 1062, pp. 519-522,

SIMS conducted by Eurofins/EAG Laboratories

Epiwafers procured from Cree/Wolfspeed

P. Neudeck, "Technical Primer on Design and SPICE Modeling of Circuits for NASA Glenn SiC JFET IC Version 12 Prototype Wafer Run Part 1: SiC JFET Behavior and SPICE Modeling" (May 2019),

P. Neudeck, "Technical Primer on Design and SPICE Modeling of Circuits for NASA Glenn SiC JFET IC Generation 13 Prototype Wafer Run - Part 1: SiC JFET Behavior and SPICE Modeling" (Oct. 2023),

LTspice,

Tanner T-SPICE,

R. F. Pierret, in "Field Effect Devices", Ed., Modular Series on Solid State Devices Vol. 4, Addison-Wesley (1990), pp. 9-25.

M. Krasowski, C. Adams, et al. "Silicon Carbide One-Bit Microprocessor", presented at IEEE Space Mission Challenges for Information Technology - IEEE Space Computing Conference. Caltech, Pasadena, CA, USA - 18-21, July 2023.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

SIMS impurity concentration profiles indicate that IC Gen. 13 threshold voltage is independent of radial wafer position.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 59-64

doi: 10.4028/p-xOG2Gx

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-19

Accepted:
2025-08-19

Online:
2025-09-10

Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

S. Rathi , L. Laborie , Y. Qi , A. Murphy , M. Bell , R. Young , D. Clark

Clas-SiC Wafer Fab Ltd., Avenue Industrial Estate, Lochgelly, KY5 9HQ, UK

servin.rathi@clas-sic.com, leo.laborie@clas-sic.com, kelly.qi@clas-sic.com, robert.young@clas-sic.com, david.clark@clas-sic.com

Keywords: 4 H -SiC, 1700 V-VDMOSFET, Channel Length, Short Channel Effects, Breakdown Voltage.

Abstract

Shorter channel-length and thinner gate-oxide are required for the scaling of design pitch and improving device performance. We explored variations in the channel length and gate oxide thickness for 1700 V 4H-SiC based VDMOSFETs. A design of experiments was applied to cover multiple designs and process conditions. The final device results show that the shorter channel with thinner gate-oxide leads to better device performance including lower on-resistance, higher current and transconductance. However, an increase in the device leakage starts affecting the breakdown voltage thus limiting the scaling for given process conditions, such as Pwell and JFET implants.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

Higher breakdown voltage devices based on enable simplified circuit designs with simultaneous increase in efficiency and reduction in the size and weight of power converters and power systems. With 1700 V 4H-SiC MOSFETs both low and high-power applications like auxiliary power supply and multi-phase inverters offer unparalleled advantages in solar, traction, solid-state transformers and EV/HEV drives. [1,2] For reliable and efficient operation at high voltages, optimization for both device design and processing are required. In this work, variations in critical device parameters like channel doping, channel length ( ) and gate oxide thickness ( ) are studied for optimizing the design for any detrimental effects including short-channel effects on the device characteristics.

Fabrication and Measurements

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

Figure 1(a) shows a schematic of the 1.7 kV VDMOSFET fabricated on -SiC wafers with figure 1(b) showing the picture of the fabricated wafer along with the inset highlighting a field-shot which includes multiple devices and PCM (Process Control Monitor) structures. The key device parameters including channel length and gate oxide are marked as p -well and oxide in the schematic. The variations in the device characteristics were investigated on a design of experiment batch of wafers. For this investigation, channel length was varied from 0.5 to with a step-size of and the gate oxide thickness was varied from 50 nm and 65 nm . The variation in the channel length was implemented by varying the cell pitch while keeping the key parameters like JFET width, spacing similar for different designs.

The wafers were processed as follows: for and usual aluminum and nitrogen implants were used, respectively; implant activation through high temperature annealing; the gate oxide process involves oxide formation followed by post oxidation annealing to passivate interface and oxide traps; a nickel process was used to form the front ohmic; a power metal stack of deposition for the source and gate. While for the back contact, a laser annealing process forms an ohmic back contact before a solderable back metal stack is deposited.

For electrical characterization, Agilent B1505A power device analyzer was used for both wafersort and sweep measurements. The gate oxide thickness was also tracked both by inline optical and EOL (End of Line) measurements using PCM's. Other typical process control parameters like field effect mobility, gate breakdown voltages, specific contact resistance, sheet resistance for , poly layers were also measured using dedicated structures.

Fig. 1 (a) Cross-sectional view of the 1.7 kV VDMOSFET (b) image of a multi-project 150 mm processed SiC wafer with the inset showing a field-shot of the multi-designs 1.7 kV VDMOSFETs.

Fig. 1. (a) Cross-sectional view of the 1.7 kV VDMOSFET (b) image of a multi-project 150 mm processed SiC wafer with the inset showing a field-shot of the multi-designs 1.7 kV VDMOSFETs.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

Figure 2(a) and (b) show variation in the threshold voltage, , defined at a fixed drain current of 7.3 mA , and body-diode forward voltage, , at gate-source voltage, and -5 V , respectively, for different and considered in this study. With shortening of channel length, , from 0.8 to decreases gradually for both 50 and 65 nm gate-oxide ( ) in figure 2(a). This reduction in indicates towards the physical shortening of the channel length and/or manifestation of the short-channel effects (SCEs), which scales up for the lower . [3] The difference in at and -5 V , in figure 2(b) further confirms an increase in the channel leakage as is scaled from 0.8 to for both of 50 and 65 nm . Further, marginal lower values of both at and -5 V for 65 nm compared to 50 nm for similar channel length are likely due to variation in the ohmic properties. Such variations are typically linked to higher consumption of SiC for 65 nm GOX process and can be corrected by tweaking the related implant profiles. Other studies related to channel length scaling reports manifestation of similar SCEs in the range varying from 0.9 to , with critical channel-length depending on other device specs including Pwell doping and thickness of gate oxide. [3-8]

Though such channel current leakage at shorter channel can be optimized by increasing the associated Pwell doping, this is at the cost of higher on-resistance due to a decrease in the channel carrier mobility because of an increase in the coulomb scattering due to the heavier implant-dose. Therefore, a judicious optimization is required for such trade-off, depending on the end application and user requirements.

Fig. 2. (a) Box plot of threshold voltages measured at a fixed drain current of and (b) body-diode forward voltage, , for variations in the channel length and gate oxide of , 0.7 , and and , respectively.

Fig. 2. (a) Box plot of threshold voltages measured at a fixed drain current of and (b) body-diode forward voltage, , for variations in the channel length and gate oxide of , 0.7 , and and , respectively.

Fig. 3. (a) Output characteristics of different devices (b) plots output curves for device at different temperature, for both 50 and 65 nm gate oxide thickness.

Fig. 3. (a) Output characteristics of different devices (b) plots output curves for device at different temperature, for both 50 and 65 nm gate oxide thickness.

Figure 3(a) plots the output characteristics at gate voltage of 5 V , shows the advantage of shorter channel and thinner gate-oxide leading to higher current or lower on-resistance. Figure. 3(b) show output curves measured at different temperatures of 25,75 and . The increase in the drain current with temperature shows typical positive temperature coefficient at lower gate voltages due to higher carrier concentration in the channel overpowering current lowering due to mobility degradation. At higher gate voltages, drain current with temperature shows negative temperature coefficient as phonon scattering induced decrement in carrier mobility overcomes any corresponding increase in the drain current due to lowering of threshold voltage or increase in carrier concentration. Several other factors like bandgap narrowing at higher temperature and lowering of threshold voltage due to complex dynamics at the gate-oxide-SiC interface also play a key role in determining the current variation with temperature. [9,10]

Figure 4(a) and (b) plot the transfer and transconductance curves for various combination of , and . The channel-length scaling from 0.8 to for 50 nm gate-oxide show increase in both drain current and transconductance in figure. 4(a) while the advantage of thinner is evident in figure. 4(b) for both 0.5 and channel-length. Again, the left shift in both the drain current and transconductance curves agrees with the SCE (Short Channel Effect) theory, decreasing the threshold voltages, but still not by enough to reduce the peak transconductance values. [11,12]

Fig. 4. (a) Transfer characteristics of devices for different , the secondary y-axis plots the corresponding transconductance curves (b) Comparison of transfer characteristics of and devices for 50 and 65 nm gate oxide thickness, the secondary y-axis plots the corresponding transconductance curves.

Fig. 4. (a) Transfer characteristics of devices for different , the secondary y-axis plots the corresponding transconductance curves (b) Comparison of transfer characteristics of and devices for 50 and 65 nm gate oxide thickness, the secondary y-axis plots the corresponding transconductance curves.

Figure. 5(a) show variations in the drain current and transconductance with temperature ranging from 25 to . A similar increase in the drain current as seen in the output characteristics in figure. 3(b) can be seen in these transfer characteristics where the gate-oxide- SiC interface is the dominant criteria leading to this decrease in the threshold voltage and increase in the drain current. Variations in the threshold voltage plotted in figure 5(b) are based on the five-point sweep measurements carried out on wafers representing gate-oxide splits of 50 and 65 nm , while the data plotted in Figure 2 and Figure 6 is from spot-test measurements carried out at wafer level covering all devices, using an IP tester and automatic probe set-up. [13]

Fig. 5. (a) Transfer characteristics of devices for both and 65 nm at different temperatures, the secondary y -axis plots the corresponding transconductance curves (b) Variation in the threshold voltage with temperature ranging from 25 to for various and .

Fig. 5. (a) Transfer characteristics of devices for both and 65 nm at different temperatures, the secondary y -axis plots the corresponding transconductance curves (b) Variation in the threshold voltage with temperature ranging from 25 to for various and .

Fig. 6. (a) Device leakage current (IDSS) measured at 1700 V plotted in base Log scale and (b) Breakdown voltage (BVDSS) for different and devices.

Fig. 6. (a) Device leakage current (IDSS) measured at 1700 V plotted in base Log scale and (b) Breakdown voltage (BVDSS) for different and devices.

Figure 6(a) and (b) show variations in the device leakage current (IDSS) and breakdown voltages (BVDSS), respectively. The consequence of a higher leakage current in devices results in the lowering of BVDSS, measured at of leakage current, signifying the critical role of channel length in optimizing the device characteristics. It may be noted that the larger statistical variations for 65 nm process as seen in figures 2(a), 6(a), and 6(b) are more likely to be linked to the underlying wafer quality rather than any process variations. For the current process and implant parameters, the longer channel appears to be more robust and not affected by the short-channel effects while the channel length appears to be at the edge of usefulness when considering the high-voltage characteristics. Further, other device characteristics like on-resistance showed typical variations with and , while the gate-leakage current (IGSS) did not show any significant variation in 50 and 65 nm devices offering scope of further optimization.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

This design-of-experiments demonstrates the advantages of thinner gate-oxide and shorter channel length are limited by the device characteristics like IDSS and BVDSS for a given process environment. The results indicate that with appropriate implant adjustments for shorter channel and thinner gate-oxide could provide further device improvement while maintaining aggressive device pitch. However, any such improvements will be ultimately limited by the device leakage current, gate leakage current and related reliability issues, thus defining the lower and upper limits for scaling and respectively.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

This work was funded by UK Research and Innovation, UKRI, Innovate UK Project SiC-MAP [Grant number: 77743].

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.59.pdf

B. J. Baliga, Fundamentals of Power Semiconductor Devices. Cham: Springer International Publishing, 2019. doi: 10.1007/978-3-319-93988-9.

Information on 1700 v -sic-mosfets/

M. Noborio, Y. Kanzaki, J. Suda, and T. Kimoto, 'Experimental and Theoretical Investigations on Short-Channel Effects in 4H-SiC MOSFETs', IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1954-1962, Sep. 2005, doi: 10.1109/TED.2005.854269.

D. Kim, N. Yun, S. Y. Jang, A. J. Morgan, and W. Sung, 'Channel Design Optimization for MOSFET Achieving Inherent Unipolar Diode Quadrant Operation', IEEE J. Electron Devices Soc., vol. 10, pp. 495-503, 2022, doi: 10.1109/JEDS.2022.3185526.

T. Liu, S. Zhu, A. Salemi, D. Sheridan, M. H. White, and A. K. Agarwal, 'JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs', Solid State Electronics Letters, vol. 3, pp. 53-58, Dec. 2021, doi: 10.1016/j.ssel.2021.12.001.

S. Zhu, T. Liu, J. Fan, H. L. R. Maddi, M. H. White, and A. K. Agarwal, 'Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs', Materials, vol. 15, no. 17, p. 5995, Aug. 2022, doi: 10.3390/ma15175995.

K. Tachiki, T. Ono, T. Kobayashi, and T. Kimoto, 'Short-Channel Effects in SiC MOSFETs Based on Analyses of Saturation Drain Current', IEEE Trans. Electron Devices, vol. 68, no. 3, pp. 1382-1384, Mar. 2021, doi: 10.1109/TED.2021.3053518.

M. Rahimo, I. Nistor, and D. Green, 'Suppression of Short Channel Effects for a SiC MOSFET Based on the S-MOS Cell Concept', KEM, vol. 945, pp. 83-89, May 2023, doi: 10.4028/pg4w5h5.

H. L. R. Maddi et al., 'The Road to a Robust and Affordable SiC Power MOSFET Technology', Energies, vol. 14, no. 24, p. 8283, Dec. 2021, doi: 10.3390/en14248283.

H. Li et al., 'Analysis of Voltage Variation in Silicon Carbide MOSFETs during Turn-On and Turn-Off', 10, 2017, Energies; doi:10.3390/en10101456

S. Rathi et al., Solid State Phenomena vol. 360, pp. 183-187, 2024.

R Gupta et al., "Microwave performance enhancement in Double and Single Gate HEMT with channel thickness variation", vol. 47, pp. 779-794, June 2010 Superlattices and Microstructures, doi: /10.1016/j.spmi.2010.03.003

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-and-characteristics-of-mosfets/978-3-0364-1915-2

Key Engineering Materials, ISSN: 1662-9795, Vol. 1023, pp 65-70

doi: 10.4028/p-AGxS8Q

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-03-26

Accepted:
2025-03-26

Online:
2025-09-10

Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

The original version of this paper is available on https://www.scientific.net/KEM.1023.65.pdf

Antxon Arrizabalaga and Jesus Oliver

European Space Agency (ESA), Netherlands

antxon.arrizabalaga@esa.int, bjesus.oliver@esa.int

Keywords: Current measurement, layout, stray inductance, space electronics, SiC, high power.

Abstract

This work presents simple layout configurations for current sensing resistor networks to measure fast and high currents in SiC devices. The proposed layout reduces the inserted inductance in the switching loop when compared to coaxial shunts, which is key for the application of SiC devices in space. High inductance in the switching loop leads to dangerous overshoots during turnoff transients, that can block the adoption of SiC devices in space due to single event burnouts. After presenting the different proposed layouts, the inserted inductance of each one is measured with an impedance analyzer as well as performing switching tests. Applying field cancellation techniques in the layout of a simple parallel resistor network, the inserted inductance is reduced up to when compared to a coaxial shunt, while obtaining the same current sensing performance.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1023.65.pdf

The new space missions in the main space agencies will require high-power (HP) electronic systems [1], [2]. Following the trend in terrestrial HP electronics, space power industry is also looking to use SiC devices to achieve the required technical figures in such HP applications. However, SiC devices suffer severely from single event effects (SEE) in space applications, and need to derate their voltage considerably [3], [4], [5]. This is why controlling the voltage overshoot created by the layout stray inductance is key for the safe operation of SiC devices in space. All these makes the insertion of current measuring systems in space power converters very challenging with SiC .

SiC devices such as SiC MOSFETs have the unique characteristic of managing several tens or even hundreds of Amps at high switching speed and are required to do so in HP applications. This creates hard to measure high current derivatives, , in the switching loop of power electronic circuits. The current measurement in such systems should be high-current, high bandwidth and low inductance, to properly measure the current without creating dangerous overshoots in the switching transients. The preferred devices to measure fast currents on the range of several tens of Amps are the coaxial shunts, but they are expensive and bulky, inserting a considerable inductance, several nH , in the switching loop [6]. Surface mounted device (SMD) resistor networks are used in low current systems with excellent time response and minimum added inductance, achieving better performance than the coaxial shunts [6]. This is challenging in high currents, because bigger SMD footprints must be used, paralleling several resistors to meet the current rating, thus creating wider layouts with higher added inductance. Compensation networks can be used to improve the dynamic performance of parallel SMD networks [7], but the layout remains the most important factor, and has not been analyzed in such systems. This work compares the added inductance and the switching performance of three different layouts with the one of a coaxial shunt experimentally in a 30 A converter.

Proposed Layouts

The original version of this paper is available on https://www.scientific.net/KEM.1023.65.pdf

Parallel SMD. The first configuration is the simplest one, shown in Fig. 1(a), based on 10 SMD resistors placed in parallel. The objective is to divide the current between the 10 resistors, so their footprint can be smaller thus with lower self-inductance. In addition, paralleling the resistors divides the total network inductance.

Fig. 1. Proposed and tested layouts, (a) parallel SMD, (b) field cancellation and (c) radial configurations.

Fig. 1. Proposed and tested layouts, (a) parallel SMD, (b) field cancellation and (c) radial configurations.

Fig. 2. Direction of the current through the resistor network with field cancellation, forcing opposite currents.

Fig. 2. Direction of the current through the resistor network with field cancellation, forcing opposite currents.

Field cancellation. The second configuration takes advantage of the mutual inductance concept, which should be added to the self-inductance of each device in two-layer conductors [8]. Equation (1) represents the value of the mutual inductance, being and vacuum permeability and relative permeability of the insulation material, , and are length, width and thickness of the conductors, is the distance between them, k is the correction factor and is the angle between the current directions [9].

By forcing opposite current between subjacent devices, , mutual inductance is made negative, subtracting the mutual inductance between devices to the self-inductance [10]. As observed in Fig. 2, in where the direction of the current through the resistors is indicated, the subjacent currents are made opposite and transferred to the lower layer of the PCB with vias in the lower or upper end of the resistor.

Radial. The third configuration combines the field cancellation technique in the previous configuration, with the radial layout approach in [6], and is shown in Fig. 1(c). This approach intends to reduce the area required for the current sensing network, as well as embracing the coaxial connector used to extract the shunt signal, ideally reducing the layout inductance. This approach is successful in [6], at lower current, being able to integrate the SMD resistors in a very compact way, but at tens of Amps, and with the bigger device footprints, this approach needs to be tested.

Experimental Testing

The original version of this paper is available on https://www.scientific.net/KEM.1023.65.pdf

Setup. The three current sensing networks, as well as the coaxial shunt are tested using the double pulse testing (DPT). This test allows to evaluate the switching behavior of devices, as well as the layouts, and is the ideal test to compare the fast current sensing performance of the different configurations. The test, shown in Fig. 3, is done by charging an inductor to the desired current by keeping the device under test (DUT) on, then switching the DUT off to evaluate the turn-off. The test current is kept in the inductor recirculating it in a freewheeling diode, or the body diode in the case
two equal devices are used. Next, the DUT is turned on to evaluate the turn-on transition at the desired load current. The transient currents in the test are used to compare the different current measurement networks. The same setup is used, shown in Fig. 3(c), with the same layout for every tested board, being the only difference the current sensing network.

Fig. 3. DPT setup, (a) circuit diagram with the measured parameters (b) the voltage and current in the DUT terminals and (c) board and laboratory setup layout.

Fig. 3. DPT setup, (a) circuit diagram with the measured parameters (b) the voltage and current in the DUT terminals and (c) board and laboratory setup layout.

Impedance analysis. The impedance of all the current measurement networks is analyzed using the Bode 100 equipment. First, the current sensing network is isolated and measured alone. Fig. 4 shows the results, being Fig. 4(a) the impedance and Fig. 4(b) the inductance measurements. Focusing on the second one, it can be concluded that all the proposed SMD networks reduce the inserted inductance at high frequency, over 10 MHz , when compared to the coaxial shunt. As for the proposed layouts, the configurations with the field cancellation get the lowest inserted inductance. The results are analyzed at over 10 MHz due to the expected fast current rise and fall times, tens of nano seconds, leading to high frequency excitation in the switching loop.

To be able to validate the impedance measurement results, they must be compared to the switching test results. However, the switching test will show the inductance in the whole switching loop, so new impedance measurements are performed considering the whole switching loop, and shown in Fig. 5. As expected, the inductance of the whole switching loop is higher than the one of the isolated current sensing network. However, the trend in high frequency is the same, being the layouts with the field cancellation the ones with the least inductance.

Fig. 4. Impedance measurement of the current measurement network, (a) the impedance with magnitude and phase and (b) the inductance.

Fig. 4. Impedance measurement of the current measurement network, (a) the impedance with magnitude and phase and (b) the inductance.

Fig. 5. Impedance measurement of the whole switching loop, (a) the impedance with magnitude and phase and (b) the inductance.

Fig. 5. Impedance measurement of the whole switching loop, (a) the impedance with magnitude and phase and (b) the inductance.

To validate the testing setup and the impedance measurements, the difference between the switching loop inductance, , and the current measurement loop inductance, , calculated as , is calculated for all the configurations and shown in Fig. 6. The result are very similar for every configuration, as the calculated inductance is the inductance added by all the power components in the DPT setup, which are the same for all the current measurement networks. The maximum difference between any configuration at 25 MHz is only 1.2 nH , validating the testing setup and the impedance measurements.

Fig. 6. inductance calculation for the different proposed configurations.

Fig. 6. inductance calculation for the different proposed configurations.

Switching test. Finally, the DPT is executed with every current sensing network, and both the current and voltage waveforms are compared, Fig. 7. The study focuses on the turn-off transition, being the one causing the potentially dangerous overshoot for the SiC in space. First, it should be noted no difference is observed between the proposed networks and the coaxial shunt in the sensed current. As the measurements performed by the coaxial shunt are considered as the reference, the proposed networks are validated for a correct current sensing. However, and due to a difference in the inserted inductance, a different overshoot value is observed in the turn-off voltage. The overshoot value is defined by (2), being the total stray inductance in the switching loop, and the current derivative in the switching transition.

Using (2) and measuring the and the overshoot values in the switching waveforms, can be calculated, confirming the results obtained in the impedance measurements: the configurations with the field cancellation layout obtain the least overshoot thus insert the least inductance, repeating the trend in the measurements in Fig. 5(b).

Finally, the inductances calculated from the switching waveforms are compared with the ones measured in the impedance analysis, and shown in Table 1. Following the effective frequency theory, the measured inductance value should be given depending on the current fall or rise time [11]. In the turn-off, the current fall time is 12 ns , leading to 26.9 MHz . This frequency value is just used to identify the frequency for the impedance measurement. Accurate measured values for each waveform and configuration are used to calculate the inductance in the tun-off transition using (2). Both the measured inductance and the inductance calculated with the switching waveforms match, validating the measurements and calculations.

Table 1. Measured and calculated inductance of the current measurement networks.

Test | Coaxial shunt | Parallel SMD | Field cancellation | Radial | Unit
Measured [26.9 MHz] | 31.2 | 29.4 | 26.9 | 25.7 | nH
Turn-off [Waveforms] | 32.5 | 29.6 | 26.6 | 25.1 | nH

Fig. 7. Switching waveforms of the turn-off transition for the different configurations, highlighting the overshoot.

Analyzing the results in Table 1, it is seen the current sensing with parallel SMD network reduces the inserted inductance of the switching loop when compared to the coaxial shunt. However, applying the field cancellation technique to the same layout reduces the inductance when compared to the coaxial shunt, validating the field cancellation technique. Using the radial approach, the inductance reduction when compared to the coaxial shunt is , improving the layout even more. These results can easily be seen analyzing the highlighted overshoot in Fig. 7, with the best layouts obtaining the lowest overshoot.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1023.65.pdf

SMD resistor networks are proposed as current sensing networks for SiC devices in space, to avoid the overshoot generated by the high inserted inductance of the coaxial shunts. The current sensing performance of the proposed networks is validated through DPT, and by comparing the current waveforms obtained with the one sensed with the coaxial shunt. In addition, it is demonstrated the layouts using field cancellation techniques, forcing opposite current through subjacent resistors insert less inductance in the switching loop than the just parallel layout.

With the SiC devices being considered for the HP systems in space, the voltage they block should be monitored with care. In this aspect, the overshoot during the turn-off transitions due to the switching loop inductance can be dangerous. Using simple and low inductance current sensing networks to reduce the overshoot will contribute to the adoption of the SiC devices in space.

References

The original version of this paper is available on https://www.scientific.net/KEM.1023.65.pdf

Nasa, "NASA's lunar exploration program overview," 2020.

European Space Agency (ESA), "ESA lunar exploration journey." Accessed: May 14, 2024. [Online]. Available:

A. F. Witulski et al., "Single-event burnout mechanisms in SiC power MOSFETs," IEEE Trans Nucl Sci, vol. 65, no. 8, pp. 1951-1955, Aug. 2018, doi: 10.1109/TNS.2018.2849405.

R. A. Johnson et al., "Unifying concepts for ion-induced leakage current degradation in silicon carbide Schottky power diodes," IEEE Trans Nucl Sci, vol. 67, no. 1, pp. 135-139, Jan. 2020, doi: 10.1109/TNS.2019.2947866.

A. Witulski et al., "Single-event effects in silicon carbide high voltage power devices for lunar exploration," 2023.

Severin Klever and Rik W. De Doncker, "A High-Bandwidth and Low-Inductive Sensor for Measuring the Commutation Current of WBG Devices," in EPE'23 ECCE Europe, 2023.

Markus Meißner, Jan Schmitz, Felix Weiß, and Steffen Bernet, "Current measurement of GaN power devices using a frequency compensated SMD shunt," in PCIM Europe, 2019.

H. W. Johnson and M. Graham, High-speed digital design: A handbook of black magic. 1993.

H. Gui et al., "Methodology of low inductance busbar design for three-level converters," IEEE J Emerg Sel Top Power Electron, vol. 9, no. 3, pp. 3468-3478, Jun. 2021, doi: 10.1109/JESTPE.2020.2999403.

Niloofar Rashidi Mehrabadi, Igor Cvetkovic, Jun Wang, Rolando Burgos, and Dushan Boroyevich, "Busbar design for SiC-based H-bridge PEBB using 1.7 kV , 400 A SiC MOSFETs operating at 100 kHz ," in IEEE Energy Conversion Congress and Exposition (ECCE), IEEE, 2016.

Z. Chen, "Characterization and modeling of high-switching-speed behavior of SiC active devices," Master Thesis, Virginia Polytechnic Institute and State Univ., Blacksburg, USA, 2009.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Keywords Index

1

1700 V-vdmosfet Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

4

4 H -sic Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

B

Bipolar Diode Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Breakdown Voltage Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

C

Channel Length Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

Current Measurement Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

D

Device Simulation Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

H

Hexfet Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

High Power Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

High Temperature Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

High Voltage Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes; Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Highvoltage Semiconductor Diodes And Integrated Circuit A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

I

Integrated Circuit Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

J

Junction Field Effect Transistor (jfet) Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

L

Lateral Pin Diode A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

Layout Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

O

Obic Characterization Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

P

Periphery Protection Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Physics-based Modeling A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

Planar Gate SiC Mosfet Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Planar Mosfet Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Power Mosfet A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

S

Semi-superjunction Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Semiconductor Device Manufacture A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

Short Channel Effects Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

SiC Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

Silicon Carbide (sic) A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

Space Electronics Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

Spice Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

Spice Simulation A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

Stray Inductance Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

Superjunction Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Switching Behavior A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

T

Tcad A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

Trench Mosfet Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Authors Index

A

Adams, C. Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

Agarwal, A. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Antoniou, M. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Arrizabalaga, A. Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

B

Bell, M. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

Bevilacqua, P. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Boccarossa, M. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Boer, S. A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

Brooks, B. A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

Brosselard, P. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

C

Cao, Q. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Chow, T. Single-Event-Burnout in 4H-SiC Lateral RESURF Power MOSFET

Clark, D. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

D

Dail, S. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Dong, Y. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

E

Ekström, M. A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

G

Gammon, P. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

H

He, Z. Single-Event-Burnout in 4H-SiC Lateral RESURF Power MOSFET

I

Irace, A. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

J

Jang, S. A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

Ji, W. Single-Event-Burnout in 4H-SiC Lateral RESURF Power MOSFET

K

Krasowski, M. Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

L

Laborie, L. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

Lazar, M. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Lim, J. A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

M

Ma, X. A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application

Maresca, L. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Melnyk, K. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Morel, H. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Morgan, A. A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

Mudiyanselage, D. A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

Mulpuri, V. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Murphy, A. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

N

Neudeck, P. Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

O

Oliver, J. Fast High Current Sensing SMD Resistor Network Layout for Low Inductance Insertion

P

Park, J. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Planson, D. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Prokop, N. Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

Q

Qi, Y. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

R

Rashid, A. A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

Rathi, S. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

Renz, A. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Ryu, S. A Physics-Based SPICE Model for a SiC Vertical Power MOSFET

S

Scharnholz, S. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Shah, V. Cost-Effective Design and Optimization of a Semi-Superjunction 4H-SiC MOSFET Device

Sonneville, C. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

Spry, D. Design and Simulation of Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged Operation

Sundaresan, S. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Sung, W. A Novel 'Ladder' Design for Improved Channel Density for -SiC MOSFETs

V

Vergne, B. Matching Physical and Electrical Measurements (OBIC) to Simulation (FEM) on High Voltage Bipolar Diodes

W

Walsh, N. Investigation of Advanced Hexagonal Layouts for SiC MOSFETs

Y

Young, R. Optimizing Short Channel Designs in V 4H-SiC VDMOSFET

Z

Zetterling, C. A Novel Design of SiC High-Voltage Lateral PiN Diode for IC Application