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ISBN print: 978-3-0364-2131-5
ISBN eBook: 978-3-0364-3131-4
DOI book: 10.4028/b-b2SShW
© 2026 Trans Tech Publications Ltd, All Rights Reserved

Design of SiC Power Devices

Edited by
Sang Mo Koo
Hoon Kyu Shin

Design of SiC Power Devices

Special topic volume with invited peer-reviewed papers only

Edited by
Sang Mo Koo and Hoon Kyu Shin

𝐁𝐁 cientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volume 1055 of
Key Engineering Materials
ISSN print 1013-9826
ISSN web 1662-9795

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp -1-0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2026-05-14

Online:
2026-05-19

Preface

The original version of this paper is available on https://www.scientific.net/KEM.1055.-1.pdf

Silicon carbide (SiC) has emerged as a cornerstone material for next-generation power electronics, offering unprecedented opportunities to improve the efficiency, power density, and reliability of electrical energy conversion systems. Advanced electrical characteristics, superior thermal conductivity, and chemical and mechanical stability enable SiC semiconductor devices to operate at high voltages, elevated temperatures, and high switching frequencies. These attributes have positioned SiC at the forefront of technological developments in electric transportation, renewable energy systems, industrial automation, and aerospace applications.

The presented special edition considers the principles, methodologies, and innovative approaches that underpin the practice of developing advanced SiC-based power semiconductor structures. The edition explores concepts for a broad spectrum of devices based on SiC MOSFETs, including, for example, bidirectional power switches and Gate Turn-Off (GTO) thyristors.

Particular attention is given to the relationship between device architecture and electrical performance. Topics such as P -well doping, P -well boosting, edge termination, and Junction Termination Extension (JTE) are examined as essential design strategies for controlling the electricfield distribution, minimising leakage, and maximising breakdown voltage. Capacitance-voltage measurements and other characterisation techniques are discussed as powerful tools for evaluating doping profiles, interface quality, and charge distribution, while Technology Computer-Aided Design (TCAD) is presented as an indispensable framework for simulation, optimisation, and predictive device engineering.

The special edition also analyses on-state characteristics, switching behaviour, and highfrequency operation, emphasising the importance of balancing conduction efficiency with dynamic performance. This book provides a comprehensive perspective on the practice of designing SiC power devices and the strategies required to achieve superior performance and long-term reliability.

Intended for researchers, device engineers, and graduate students, this special edition offers both fundamental insights and practical guidance for the design of advanced power semiconductor devices. We hope that the contributions presented herein will stimulate further innovation and support the continued expansion of SiC power electronics into increasingly important industrial and societal applications.

Table of Contents

Preface

Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Marco Zignale, Patrick Fiorenza, Lucia Calcagno, Marina Antoniou, Filippo Giannazzo, Fabrizio Roccaforte

The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Jan Frederik Dick, Jannik Schwarberg, Mathias Rommel, Jörg Schulze

Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Jeff Joohyung Kim, Jae Hyung Park, Shane Stein, Daniel Lichtenwalner, Sei Hyung Ryu

High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

Shariare Hossain Rabbi, Justin Lynch, Stephen A. Mancini, Woongje Sung

Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Zhao Wen He, Giorgian Borca-Tasciuc, T. Paul Chow

Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Stephen A. Mancini, Dai Xin Chen, Seung Yup Jang, Andrew Binder, Richard Floyd, Robert Kaplar, Jack Flicker, Adam Morgan, Xiao Qing Song, Woongje Sung

Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Lan Luo, Yu Zhong, Peng Cui, Ziang Zhao, Lei Ge, Ying Xin Cui, Ming Sheng Xu, Xian Gang Xu, Ji Sheng Han, Yao Hao Wang

Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Seung Yup Jang, Skylar deBoer, Woongje Sung

Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Daichi Dansako, Tetsuya Abe, Kosuke Miyazaki, Toshikazu Tanioka, Yasuhiro Kagawa, Tetsuya Nitta

JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Zi Han Zhang, Lei Yuan, Kai Yu Chen, Xiao Wen Wang, Xue Song Liu, Tong Xiao Hou, Bo Peng, Gui Bao Wang, Mi Ao Yu, Ren Xu Jia, Yu Ming Zhang

2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Yuniarto Widjaja, Valerii Nebesnyi, Oleksandr Maistriuk, Asen Asenov, Nikolas Xeni, Tapas Dutta, Djamel Bensouiah, Servin Rathi, Leo Laborie, Robert Young, Yunyi Qi, David T. Clark

Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Hai Zhao Zhi, Si Rui Feng, Xiao Ping Wang, Xin Peng Lin, Yi Tian Jiang, Hao Lin Hu, Yu Xi Wan

Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Kailun Zhong, Vamsi Mulpuri, Vishank Talesara, Arash Salemi, Sumit Jadav, Siddarth Sundaresan

Study of SiC Thyristors with Integrated Temperature Sensors

Shu Hao Cheng, Kai Yu Chen, Zi Han Zhang, Xiao Wen Wang, Lei Yuan, Da Huo, Xue Song Liu, Tong Xiao Hou, Ren Xu Jia, Yu Ming Zhang

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 1-6

doi: 10.4028/p-9dcWT2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-15

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-19

Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

Marco Zignale 1,2,a, Patrick Fiorenza 1,b*, Lucia Calcagno 2,c, Marina Antoniou 3,d, Filippo Giannazzo 1,e, Fabrizio Roccaforte 1,f

1 CNR-IMM, Strada Ottava 5, 95121 Catania, Italy

2 Dipartimento di Fisica ed Astronomia, Università degli Studi di Catania, via Santa Sofia 64, 95121 Catania, Italy

3 School of Engineering, University of Warwick, Coventry, UK

a  marco.zignale@imm.cnr.it, b  patrick.fiorenza@imm.cnr.it, clucia.calcagno@ct.infn.it, d  marina.antoniou@warwick.ac.uk, efilippo.giannazzo@imm.cnr.it,  fabrizio.roccaforte@imm.cnr.it

Abstract

Silicon carbide ( SiC ) has emerged as a leading material for high-power applications. However, the high density of interface states (Dit) at the SiO2/SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4 H -SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based Dit  extraction algorithm. The results demonstrate that NO PDA effectively reduces Dit  not only near the conduction band edge but also towards the valence band, yielding improved channel mobility ( μFE ) and enhanced threshold voltage stability.

Keywords: silicon carbide, SiC, MOSFET, interface states, Dit.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

Silicon carbide has emerged as the reference material for high-power and high-voltage applications thanks to its superior physical properties. In 4H−SiC MOSFETs, these properties allow for enhanced voltage and current ratings as a consequence of the high critical electric field combined with intrinsically lower conduction resistance. A major challenge, however, arises from the relatively high density of interface states ( Dit ) at the oxide/semiconductor interface, which remains significantly larger with respect to Si . Interface states have been widely recognised as a critical factor that degrades fundamental device parameters, including the field-effect channel mobility ( μFE ) and the onresistance (RON)[1,2]. The impact of Dit  on conduction is strongly dependent on the processing of the SiO2/4H−SiC interface [3] and can be mitigated by post-oxidation annealing (POA) or post-deposition annealing (PDA) in NO ambient [4]. However, introducing nitrogen during PDA can create trapping states at the SiO2/4H−SiC interface, potentially negatively affecting the stability of the threshold voltage ( Vth  ) [5,6].

In this context, it is crucial to investigate the evolution of the Dit  not only near the 4H−SiC conduction band but also those close the valence band, as well as the near-interface oxide traps (NIOTs) that may form during prolonged PDAs in NO.

In this work, experimental and simulated capacitance-voltage ( C−V ) measurements were carried out on lateral MOSFETs subjected to PDAs of different duration in NO ambient [7], in order to investigate the electrical evolution of Dit  across the entire wide bandgap of the SiO2/4H−SiC system. Unlike MOS capacitors, which do not allow a complete evaluation of Dit  over the entire semiconductor band gap, lateral MOSFETs enable direct access to the full 4H−SiC band gap.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

This study is focused on lateral n -channel MOSFETs with the p -type body obtained by Al ion implantation into an n-type epitaxial layer with a doping concentration of approximately ND=9·1015 cm−3. The implantation process was optimised by adjusting both fluence and ion energy
to achieve a uniform doping profile within the body, resulting in a final concentration in the range of NA=2−3·1017 cm−3. The oxide layer was subsequently deposited by Low Pressure Chemical Vapour Deposition (LPCVD), with process parameters controlled to obtain an average thickness of about 55 nm , as confirmed by capacitance measurements of MOSFETs in the accumulation regime [7]. Postdeposition annealing (PDA) was then performed for different durations, specifically 10, 20, 50 and 120 minutes, with the aim of identifying an optimal processing window that maximises the passivation effect of the treatment while avoiding secondary effects, such as defect formation induced by prolonged exposure to high temperatures in a NO ambient.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

The MOSFETs were characterised by measuring capacitance-voltage ( C−V ) curves using a CASCADE Microtech probe station equipped with a Keysight B1505A parameter analyser. Figure 1 reports the C-V characteristics acquired at 1 kHz and room temperature, with the gate voltage swept from -20 V to +10 V , i.e. from accumulation to inversion.

[picture]

Fig. 1. C-Vs measured on the different MOSFETs subjected to different PDAs in NO.

Fig. 1. C-Vs measured on the different MOSFETs subjected to different PDAs in NO.

As shown in Figure 1, increasing the duration of NO annealing modifies the slope of the C−V curves. Although the overall shape of the experimental curves remains similar, differences emerge in the positive gate voltage region, where a progressive increase in the slope can be observed as the annealing time extends from 10 to 120 minutes. This behaviour indicates the effectiveness of postdeposition annealing in reducing the density of interface states near the conduction band. A corresponding shift of the minimum point of the C−V curves towards more negative gate voltages is also observed with increasing annealing duration. In addition, for gate voltages below -5 V , a slight variation in the slope can be observed, which may be attributed to changes in the interface states located close to the valence band. Taken together, these features suggest the evolution of the Dit  profile as a function of annealing in NO ambient.

Following the electrical characterisation of the MOSFETs, the density and distribution of interface states were evaluated using an analytical model. For this purpose, an in-house MATLAB algorithm was developed to extract the Dit  profile in MOSFET structures through an iterative procedure. The model, derived from the ideal C-V response of a MOS structure without interface states, accounts for their contribution as a function of energy level and density, thereby generating a modified C−V profile that reproduces the experimental data acquired. In particular, the model iterates on a set of pre-defined level with specific energy dispersion (exponential, Gaussian etc.) in order to achieve the best fit of the experimental C−V curves.

In order to simplify the analysis, the incorporation of traps was represented using analytical mathematical profiles such as Gaussian, exponential, or linear functions, which ensure mathematical continuity for any energy value within the bandgap and allow the construction of a trap density profile across the semiconductor band gap. As a reference for this modelling, discrete energy levels reported in the literature were incorporated, including bulk defects such as carbon clusters and silicon or carbon vacancies [8], as well as interface defects associated with the incorporation of NO molecules [9], as shown in Figure 2.

[picture]

Fig. 2. Discrete levels used to calculate the Dit profile in the whole SiO2 band gap.

Fig. 2. Discrete levels used to calculate the Dit profile in the whole S i O 2 band gap.

These assumptions came from the hypothesis that the bulk semiconductor levels can be mirrored at the interface with the Dit  insulating layer.

To provide a detailed description of the adopted approach, Table 1 summarises the main characteristics of the interface states considered in the iterative simulation. Both the trap type (donor or acceptor) and the mathematical distribution used for their representation (Gaussian, uniform, or exponential) are reported, together with their corresponding energy position within the bandgap and their relative weight. These centres were then combined to construct the overall 4H−SiC profile, which was subsequently used to evaluate the modifications induced by PDA across the 4H−SiC band gap.

Table 1. Mathematical functions associated to each discrete level for the fitting of the 4H−SiC curves.

Trap Type | Distribution Shape | Energy Position (from EV) [eV] | Length [a.u.]
Donor | Gaussian | 0.2 | 0.1
Donor | Uniform | 0.3 | 0.3
Donor | Uniform | 0.6 | 0.6
Donor | Uniform | 1.1 | 0.4
Donor | Uniform | 1.5 | 0.4
Acceptor | Uniform | 2.4 | 1.8
Acceptor | Exponential | 3.26 | 0.19
Acceptor | Exponential | 3.26 | 0.03

The constructed trap profiles were incorporated into the ideal C-V response of MOSFETs, allowing close agreement with the experimental measurements. As a representative case, Figure 3
presents the fitting of the C-V curve measured after 120 minutes of PDA, obtained through the MATLAB iterative loop simulation with a trap profile specifically developed for this condition. The good agreement between experiment and simulation highlights the capability of the adopted model to capture the contribution of interface states across the C−V bandgap.

[picture]

Fig. 3. Example of an experimental Dit  curve ( 120 min of PDA ) fitted by the iterative MATLAB loop.

Fig. 3. Example of an experimental D it curve ( 120 min of PDA ) fitted by the iterative MATLAB loop.

In particular, the use of an exponential trap profile near the conduction band of the semiconductor has a significant impact on the charge accumulated in these interface states and, consequently, on the total capacitance of the device. At high trap densities, the charge stored in the trap energy levels becomes non-negligible, leading to an increase in capacitance at fixed gate bias values and resulting in a modification of the final C-V curve. Similarly, donor-like traps introduced near the valence band induce variations in the 4H−SiC characteristics, especially for gate bias values below -5 V .

By extending the analysis to all NO PDA durations, the variations induced by the different annealing times could be identified as is shown in Figure 4. The results show that increasing the annealing time in NO reduces the exponential tail of the μFE profile near the Vth  conduction band edge, while also decreasing the states located below the mid-gap and close to the valence band edge.

[picture]

Fig. 4. Dit profiles obtained on the different MOSFETs subjected to different PDAs in NO.

Fig. 4. Dit profiles obtained on the different MOSFETs subjected to different PDAs in NO.

These combined experimental and simulated findings are consistent with an enhancement of the field-effect channel mobility ( 4H−SiC ) and a reduction of μFE instability when the PDA is sufficiently long, as previously reported [10].

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

The results presented in this work demonstrate that NO PDA treatments induce a progressive reduction of interface states not only close to the Vth  conduction band edge but also near the valence band. This finding contrasts with earlier studies that reported a detrimental effect near the valence bandgap edge [11]. The combined experimental and simulated analyses further confirm that sufficiently long PDA durations lead to an enhancement of the 4H−SiC and a reduction of SiO2/4H−SiC instability. Nonetheless, achieving a reliable improvement in interfacial transport properties requires a fine control of the PDA conditions in order to maximise the beneficial passivation effect while avoiding the onset of secondary mechanisms that could reintroduce defects or compromise threshold voltage stability.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

This work is supported by Horizon EU Advances in Cost-Effective HV SiC Power Devices for Europe's Medium Voltage Grids (AdvanSiC) Project Grant number 101075709. Some authors acknowledge the project iENTRANCE@ENL funded by the European Union - NextGenerationEU.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

Cabello, M., Soler, V., Rius, G., Montserrat, J., Rebollo, J., & Godignon, P. (2018). Advanced processing for mobility improvement in 4H-SiC MOSFETs: A review. Materials Science in Semiconductor Processing, 78, 22-31.

Fiorenza, P., Giannazzo, F., Frazzetto, A., & Roccaforte, F. (2012). Influence of the surface morphology on the channel mobility of lateral implanted ( 0001 ) metal-oxidesemiconductor field-effect transistors. Journal of Applied Physics, 112(8).

Roccaforte, F., Fiorenza, P., Greco, G., Nigro, R. L., Giannazzo, F., Iucolano, F., & Saggio, M. (2018). Emerging trends in wide band gap semiconductors ( SiC and GaN ) technology for power devices. Microelectronic Engineering, 187, 66-77.

Fiorenza, P., Giannazzo, F., Cascino, S., Saggio, M., & Roccaforte, F. (2020). Identification of two trapping mechanisms responsible of the threshold voltage variation in MOSFETs. Applied Physics Letters, 117(10).

Yano, H., Kanafuji, N., Osawa, A., Hatayama, T., & Fuyuki, T. (2014). Threshold voltage instability in 4 H -SiC MOSFETs with phosphorus-doped and nitrided gate oxides. IEEE Transactions on electron devices, 62(2), 324-332.

Lelis, A. J., Green, R., Habersat, D. B., & El, M. (2014). Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs. IEEE Transactions on Electron Devices, 62(2), 316-323.

Fiorenza, P., Bongiorno, C., Giannazzo, F., Alessandrino, M. S., Messina, A., Saggio, M., & Roccaforte, F. (2021). Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4 H -SiC MOSFETs subjected to different nitridations. Applied Surface Science, 557, 149752.

Kimoto, T., & Cooper, J. A. (2014). Fundamentals of silicon carbide technology: growth, characterization, devices and applications. John Wiley & Sons.

Shimizu, T., Akiyama, T., Nakamura, K., Ito, T., Kageshima, H., Uematsu, M., & Shiraishi, K. (2021). Reaction of NO molecule at interface: An ab initio study for the effect of NO annealing after dry oxidation. Japanese Journal of Applied Physics, 60(SB), SBBD10.

Fiorenza, P., Zignale, M., Camalleri, M., Scalia, L., Zanetti, E., Saggio, M., ... & Roccaforte, F. (2024). Impact of the NO annealing duration on the interface properties in lateral MOSFETs: The energetic profile of the near-interface-oxide traps. Materials Science in Semiconductor Processing, 169, 107866.

Chung, G. Y., Tin, C. C., Williams, J. R., McDonald, K., Di Ventra, M., Pantelides, S. T., ... & Weller, R. A. (2000). Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4 H polytype of silicon carbide. Applied Physics Letters, 76(13), 1713-1715.

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The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 7-14

doi: 10.4028/p-jgTu1m

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-29

Accepted:
2026-01-31

Online:
2026-05-19

The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

Jan Frederik Dick 1,a*, Jannik Schwarberg 1, b, Mathias Rommel 2,c and Jörg Schulze 1,2,d

1 Friedrich-Alexander-Universität Erlangen-Nürnberg, Chair of Electron Devices, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystraße 10, 91058 Erlangen, Germany

a*jan.dick@fau.de, b  jannik.schwarberg@fau.de, cmathias.rommel@iisb.fraunhofer.de,  djoerg.schulze@iisb.fraunhofer.de

Keywords: power semiconductor device concept, tunneling transistor, TFET, Power-TFET, high-frequency power electronics.

Abstract

With ever-increasing power conversion densities in electric power converters, the volume of the converter must shrink for a certain power rating, which in turn demands the reduction in size of the energy-storing passive component. Constant power rating of those systems and the reduction of size of passive components leads to a higher switching frequency of the semiconductor power switches. At high switching frequencies, dynamic losses in the power semiconductor device dominate the overall power losses. Consequently, novel device concepts that address dynamic power losses may be superior to conventional power devices, even though they might have a higher static on-state loss. In this paper, the concept of the power tunneling field-effect transistor (Power-TFET) employing tunneling between a highly p-type doped source region and a n-type accumulation channel is proposed and compared to an equivalent LDMOS in terms of static and dynamic losses. Devices fabricated in a 2μ m4H−SiC technology are measured and compared to evaluate the viability of the Power-TFET device concept. The fabricated Power-TFET shows high-voltage blocking capability and has a switchable tunneling junction with on- and off-state, despite showing high on-state resistance due to the tunneling through the wide bandgap of 4H−SiC. The alternative of tunneling through a switchable Schottky barrier is simulatively explored to solve the high on-state resistance of the pn-junction based Power-TFET.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

Many of the disciplines in semiconductor engineering have shown exponential development in their fields over the years. The most prominent example of such exponential growth is the integration density of integrated circuits and the scaling of the individual semiconductor devices in logic circuits, which was first described by Gordon Moore [1]. Analogous to Moore's law, there is also an exponential increase in the power conversion density over time in the field of power electronics [2]. The power conversion density describes the amount of electrical power transferred and converted in a set converter volume. To further increase the power conversion density, it is therefore mandatory to reduce the converter volume for a set power throughput. A reduction of the converter volume can mainly be achieved by two means. First, the energy storage components that need the most space in typical converter applications must shrink, which mandates higher frequency switching since the same power must be transferred through the smaller energy storage components [3] and second, smaller cooling solutions are required, which mandates lower power losses of the semiconductor devices at the same power throughput. In essence, semiconductor power devices need to become more efficient at higher switching frequencies for future applications. Every power device technology for a certain blocking voltage has a fundamental limit in terms of the efficiency that it can reach in a converter [4]. The efficiency is set by the static conduction losses during on-state and the dynamic losses that arise from switching. Consequently, the overall converter efficiency decreases with
increasing switching frequency [4]. In many power electronic applications that use metal oxide semiconductor field-effect transistors (MOSFET) or high electron mobility transistors (HEMT), the dynamic losses surpass the static losses already in the frequency range between 20 kHz and 100 kHz , which makes it impractical to surpass the 1 MHz mark without significant drawbacks in terms of dynamic power losses and therefore more complex and bulkier cooling [4].
A sensible solution for the shortcomings of the existing technologies is to search for device concepts that enable lower power consumption during hard switching processes. In this paper, the possibility of a tunneling field-effect transistor (TFET) for power applications (Power-TFET) is explored. The concept of the TFET has been developed over the past two decades [5] to find a steep-slope concept to replace the conventional MOSFET. The goal is to achieve higher efficiency of those integrated circuits by reducing the supply voltage necessary for reliable switching. Since the load at the output node of a complementary MOS (CMOS) logic gate is typically the input capacitance of the following CMOS logic gate, static losses are of smaller interest, and the dynamic losses are dominant. Bohr and Young have shown in their work that TFETs need less energy for switching and have a lower delay at the output node [6]. Considering this, the TFET may as well be a viable concept for a fast-switching power device.

The Tunneling Field-Effect Transistor as a Power Device Concept

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

A TFET, in its most basic form, is a pin-diode with a MOS gate adjacent to its intrinsic region. The MOS electrode controls the potential at the semiconductor interface such that carriers can tunnel from the source region into the now formed channel [7]. This works for n - and p -channel TFETs in the exact same way due to the ambipolar device behavior. A basic schematic of such a TFET is given in Fig. 1 a). For a power electronic device, such a TFET is not yet useful since only n-channel behavior is of interest due to the higher mobility of electrons. Additionally, a drift region must be added to contain the electric field at high blocking voltages. Therefore, the device structure shown in Fig. 1 b) is proposed. In comparison to the conventional TFET in Fig. 1 a), the gate is shortened to only cover the source-side junction of the central region to suppress the ambipolarity and prevent drain-side breakdown of the gate at high blocking voltages. The central intrinsic region is extended on the drainside to accommodate higher fields and lightly n-type doped for better conduction in on-state. A similar device structure was already proposed in a patent by Vandenderghe and Verhulst in [8], although not for power semiconductor device applications but for CMOS applications, where ambipolarity is suppressed.

[picture]

Fig. 1. Comparison of the a) TFET and d) MOSFET for logic applications with their power device counterparts in b) and e). Their respective internal resistances are shown, representing the static loss of each device. The channel is marked in grey in both cases. In c) and f) the input capacitances of Power-TFET and LDMOS are compared, representing the dynamic losses.

Fig. 1. Comparison of the a) TFET and d) MOSFET for logic applications with their power device counterparts in b) and e). Their respective internal resistances are shown, representing the static loss of each device. The channel is marked in grey in both cases. In c) and f) the input capacitances of Power-TFET and LDMOS are compared, representing the dynamic losses.

In Fig. 1 b), the static loss of the Power-TFET is compared with the static loss in on-state of an equivalent lateral power MOSFET shown in e). From the device structure it is apparent that the commonalities between the shown MOSFET and Power-TFET are mostly given by the resistances of the drift region Rdrift , source region RS, and drain region RD. However, the total channel resistance differs greatly. The channel of the MOSFET can be separated in two sections: First, the inversion channel resistance Rch  within the p-type doped body and second, the resistance of the accumulation channel RA at the overlap of the gate with the drift region. The channel of the Power-TFET can also be separated in two parts: First, a non-linear tunneling resistance at the junction RT and second, the accumulation channel resistance RA at the gate overlap with the drift region. Assuming the drift region overlap of the gate electrode is equal for the MOSFET and the Power-TFET than the accumulation channel resistance RA are also equivalent. We can therefore directly compare the MOSFETs inversion channel resistance with the tunneling resistance in the Power-TFET to evaluate the relative static losses. The inversion channel resistance Rch in a MOSFET at small drain-source voltage VDS is given in [9, p. 327] as follows:

Rch=LchwchμnCox( VG−Vth)(1)

Lch describes the channel length, wch the channel width, μn the inversion layer mobility of the electrons, Cox the specific oxide capacitance and VG−Vth  is the difference between the applied gate voltage and the threshold voltage.
The tunneling resistance in a TFET is non-linear, which is apparent by the non-linearity of the tunneling current in p+−n+junction. The inter-band tunneling current density JT in a p+−n+junction is given in [10] as:

JT( VT)=2 m*q3ε VT4π2ℏ2Egexp(−42 m*Eg323qϵℏ)=2 m*q3(Eg/q+VT)VT4π2ℏ2λEgexp(−4λ2 m*Eg323q(Eg/q+VT)ℏ)(2)

In this equation, m* is the effective mass, q the elementary charge, ℰ the electric field within the junction, VT is the externally applied voltage bias across the tunneling junction and Eg is the bandgap energy. A central assumption behind (2) is that the potential barrier is triangular and therefore the electric field is constant with the value ε≈(E g/q+VT)/λ, where λ is the width of the tunneling barrier. Since the electric field ε contained in (2) is also a function of VT, it appears quadratically in the leading factor of JT and it appears reciprocally in the exponent. While the channel resistance Rch of a MOSFET is constant with respect to the applied drain-source voltage in its on-state with small forward voltage drop, in the Power-TFET the on-current is non-linear and therefore at low voltage the differential on-resistance is high and drops at higher drain-source voltage bias. In fact, small current flow will already result in a sizable voltage drop across a Power-TFET. Depending on the material parameters contained in (2), it is possible that a Power-TFET can match the static current carrying capability of an equivalent MOSFET and therefore its static losses, but only within a high current density regime at operation points with low differential on-resistance.
The Power-TFET has benefits with respect to its dynamic losses. Dynamic losses arise especially from the charging and discharging of the input capacitance of the respective power device [9, p. 432]. Fig. 1 c ) and f) depict the capacitive parts of the gated region of c) a Power-TFET and f) a MOSFET, respectively. The total input capacitance for the Power-TFET can be written as follows:

Cin, Power-TFET =CGS+CGD(3)

CGS is the source-side overlap capacitance and CGD is the drain side accumulation capacitance overlapping the drift-region. For the equivalent MOSFET given here, the total input capacitance is given as follows:

Cin,MOSFET=CGS+CGB+CGD(4)

CGB is the body capacitance containing the inversion channel. Comparing the input capacitances from (3) and (4), we can see that the overlap capacitances of the source region and the drift region are equal for equivalent MOSFET and Power-TFET devices. The MOSFET has the additional channel capacitance, which is responsible for the establishment of the inversion channel. The reduced input capacitance of the Power-TFET does improve the dynamic power loss compared to those of the MOSFET, which makes it an interesting device concept for reduced dynamic loss.

The Lateral Homo-Junction 4H-SiC Power-TFET

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Device Geometry and Fabrication. To evaluate the device concept of the Power-TFET, lateral devices were implemented alongside laterally diffused MOSFETs (LDMOS) for reference on the 2μ m high-temperature CMOS platform by Fraunhofer IISB [11]. Schematic cross-sections of the two fabricated devices are shown in Fig. 1 b) and e). As substrates n-type 4H−SiC wafers are used with a 12μ m thick epitaxial layer, which is n-type doped with a concentration of 1015 cm−3. Further doping wells and contact regions were implanted. The n+and p+doped contact regions are doped with 5·1019 cm−3 respectively and the p-well forming the body of the LDMOS is doped with a concentration of 1017 cm−3. The gate MOS electrode consists of a 55 nm thick thermally grown SiO2 and a n+doped polycrystalline silicon electrode. The channel length of the LDMOS is 2μ m and the drift zone of both devices have a length of 12μ m. The gate-source and gate-drain overlap are each 1μ m respectively.
Static Electrical Characteristics. In Fig. 2 the transfer characteristics are shown at a drain-source bias of VDS=1 V. The LDMOS device shows the typical exponential subthreshold behavior with a distinct off-state at VGS=0 V and a distinct on-state at VGS=20 V spanning eleven orders of magnitude in current between off- and on-state. The Power-TFET in contrast shows the same low leakage current in off-state, but does only span six orders of magnitude if the gate is biased up to VGS=40 V. Furthermore, the Power-TFET shows a shallow and rounded transfer characteristic. The onset of the tunneling current is also shifted towards higher voltages compared to the LDMOS. Fig. 3 shows the comparison of the measured output characteristics of the Power-TFET and the reference LDMOS. The characteristics are plotted on separate current axis due to the significant difference in on-state current, such that the qualitative shape of the characteristics can be compared. Compared to the linear behavior of the LDMOS at small VDS, the Power-TFET exhibits the non-linear tunneling current with an immediate onset of the tunneling current above VDS=0 V. Both devices show a saturation behavior at high VDS .

[picture]

Fig. 2. Transfer characteristics of the 4H−SiC LDMOS and the 4H−SiC Power-TFET normalized on gate width.

Fig. 2. Transfer characteristics of the 4 H − S i C LDMOS and the 4 H − S i C Power-TFET normalized on gate width.

[picture]

Fig. 3. Scaled output characteristics normalized on gate width of the 4H−SiC LDMOS and the 4H− SiC Power-TFET for comparison of the characteristics' shape.

Fig. 3. Scaled output characteristics normalized on gate width of the 4 H − S i C LDMOS and the 4 H − SiC Power-TFET for comparison of the characteristics' shape.

The devices were also characterized with regard to their breakdown behavior, which is shown in Fig. 4. Since the devices discussed here are lateral devices that do not implement any doping structures to reduce surface electric field, the devices fail typically at the semiconductor-oxide interface and do not exploit the total breakdown capability of 4H−SiC. This also explains the variance in breakdown voltage shown in the inset in Fig. 4. Nevertheless, the devices show high-voltage capability with some Power-TFETs reaching a breakdown voltage of 600 V , beyond the capability of the LDMOS.

[picture]

Fig. 4. Comparison of the breakdown behavior of the devices in off-state. The inset shows the distribution of breakdown voltages of LDMOS and Power-TFET.

Fig. 4. Comparison of the breakdown behavior of the devices in off-state. The inset shows the distribution of breakdown voltages of LDMOS and Power-TFET.

Overall, the built devices show for the first time tunneling field-effect transistor behavior in 4H−SiC with a switched homo-junction with distinct off- and on-state and high blocking capability. Nevertheless, the on-current is too low for practical use and therefore the tunneling resistance and consequently the tunneling barrier must be optimized for the application.

Tunneling Barrier Design for Low Static Loss

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Design Considerations. The output and transfer characteristics illustrate well that the tunneling resistance is eight orders of magnitude larger than the channel resistance of the equivalent LDMOS at VGS=20 V and VDS=1 V and limits the on-current to values not appropriate for the application as power device. The large tunneling resistance results almost entirely from the large bandgap energy of 4H−SiC, which the carriers must tunnel through. Equation (2) illustrates this since the bandgap energy is in the denominator of the pre-factor of the tunneling current density and in the numerator of the negative exponent of the exponential function, both leading to a lowering of the tunneling current density. Consequently, the barrier height is the parameter to optimize. In literature, TFETs for logic applications on other material systems are shown that employ heterojunctions using materials with smaller bandgap energy directly at the tunneling junction for increased current and steeper subthreshold behavior [12, 13]. In 4H-SiC heteroepitaxy is not a viable method [14] because the materials available still have large bandgaps limiting the tunneling current [15, 16]. The alternative is to use a Schottky-barrier for tunneling in the tunneling transistor [17-19]. Here the metalsemiconductor combination yields the barrier height and can be chosen quite freely and is in most cases easily manufacturable by evaporation or sputtering with optional annealing steps for alloying thereafter. Consequently, a low barrier height yields the highest tunneling current density in on-state and the lowest tunneling resistance. Low barrier height of a Schottky barrier does also introduce a lot of leakage in blocking mode through thermionic emission and Fowler-Nordheim tunneling, worsening the efficiency of the device in blocking mode and therefore increasing static loss in offstate. This leakage current has also been observed in power Schottky rectifier diodes and has been suppressed by additional structures such as in junction barrier Schottky (JBS) diodes, which
implement additional p-implanted structures underneath the Schottky contact depleting it in thermodynamic equilibrium and therefore suppressing the leakage from the Schottky barrier [20]. Implementing both, the JBS diode structure for the depletion of the Schottky barrier and a MOS gate contact adjacent to the Schottky barrier, making it switchable, keeps the low leakage in off-state while achieving a high on-current in the on-state.
Simulative Evaluation of the Switchable JBS Diode. To confirm the function of the concept a technology computer aided design (TCAD) simulation using Synopsys Sentaurus [21] was performed. The geometry of the simulated device is chosen analogous to the lateral homo-junction Power-TFET described above and 4H−SiC is chosen as semiconductor material. A schematic crosssection is shown in the inset of Fig. 5. The p+doped region underneath the Schottky contact is used to deplete the Schottky junction, such that the leakage is minimal. The gate is attached to the metal semiconductor junction with a distance of 1μ m from the p+doped region. The semiconductor is recessed at the boundary of the Schottky-junction for 100 nm , such that the electric field control of the gate on the semiconductor directly underneath the metal is optimal. For the simulation a multitude of models are used given in Tab. 1.

Table 1. Models used for the TCAD simulation of the Schottky Power-TFET and the reference LDMOS [21].

Recombination: | Shockley-Read-Hall
| Auger
| Non-local tunneling model with non-local mesh
Mobility: | Doping dependence (Massetti)
| Field dependence normal to carrier movement (Lombardi)
| High field saturation (Caughey Thomas)
Incomplete Ionization: | 50% split of the shallow and deep nitrogen donor level in 4H-SiC
Material anisotropy: | Mobility
| Poisson
Interface Traps: | 5·10¹² cm⁻² at the semiconductor-oxide interface

[picture]

Fig. 5. Comparison of a simulated 4H−SiC LDMOS and a simulated 4H−SiC Schottky PowerTFET (cross-section shown in the inset). The channel established in the n-layer is shown in gray, which directly contacts the metal source contact. The contact potential at the Schottky junction is set to ϕm−HL=0.6 V.

Fig. 5. Comparison of a simulated 4 H − S i C LDMOS and a simulated 4 H − S i C Schottky PowerTFET (cross-section shown in the inset). The channel established in the n-layer is shown in gray, which directly contacts the metal source contact. The contact potential at the Schottky junction is set to ϕ m − H L = 0.6 V .

For the Schottky barrier height between the n -layer and the metal source contact, a value of ϕM−HL=0.6eV is chosen. The transfer characteristic of the device is shown in Fig. 5 and compared to a simulative representation of the abovementioned LDMOS simulated with the same models and parameters. The reference LDMOS in Fig. 2 shows overall a very similar behavior as the simulated LDMOS in Fig. 5. The values for the on-current and the onset of the subthreshold behavior fit well between simulation and measurement, hinting that the simulative results are reliable. The simulation shows the same leakage for both Schottky Power-TFET and LDMOS in off-state and at a gate bias of 20 V the Schottky Power-TFET achieves an on-current comparable to the on-current of the LDMOS. The transfer characteristic of the Schottky Power-TFET shows two distinct regions. First, a steep rise of current, which is the gate's influence on the depletion of the Schottky barrier by increasing the carrier concentration in the accumulation channel and thereby increasing the leakage at the Schottky barrier. Second, the Schottky barrier is getting thin and a significant tunneling current occurs due to the rising carrier concentration in the channel. This yields the rounded behavior of the second increase.

Conclusion

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The Power-TFET promises lower dynamic loss by reduction of the input capacitance since it does not implement a gate-body capacitance compared to an equivalent MOSFET. This benefit is only useful, if the static loss of the Power-TFET is comparable to those of a MOSFET. The direct comparison of a fabricated lateral MOSFET and a Power-TFET has shown that the Power-TFET lacks eight orders of magnitude in terms of on-current due to the tunneling barrier being the bandgap of 4H−SiC. It is simulatively shown that swapping the homo-junction for a JBS diode structure, where the gate switches a Schottky barrier with low barrier height can achieve both low leakage in off-state and the required on-current.

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The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 15-20

doi: 10.4028/p-1PUxT1

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-16

Accepted:
2026-03-08

Online:
2026-05-19

Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

Jeff Joohyung Kim 1,a*, Jae-Hyung Park 1,b, Shane Stein 1,c, Daniel Lichtenwalner 1, d, Sei-Hyung Ryu 1,e

Abstract

We have introduced a new 1200 V4H−SiC MOSFET as Wolfspeed's Gen4 MOSFET, which offers compatible Rds,on, improved dynamic switching energy losses, reduced Qrr, and enhanced short circuit withstand time performance. In this study, we examine the P-body effect resulting from multi-step ion implantation and its significant impact on both the static and dynamic characteristics of SiC MOSFETs, specifically focusing on body-diode reverse recovery, short circuit withstand time (Tscwt), and observed switching energy losses in the 1.2 kV 4H-SiC power MOSFETs within this Gen4 series. Our findings are expected to contribute valuable insights into optimizing the design and operation of SiC MOSFETs, ultimately supporting the needs of modern power electronic systems that demand greater performance and efficiency.

Wolfspeed, 4600 Silicon Drive, Durham, NC 27703, USAa  Jeff.Kim@wolfspeed.com, b  Jae-Hyung.Park@wolfspeed.com, c  Shane.Stein@wolfspeed.com, d  daniel.lichtenwalner@wolfspeed.com, e  sei-hyung.ryu@wolfspeed.com

Keywords: 4H−SiC MOSFET, Short Circuit Withstand Time, Double Pulse Test, Switching energy losses, Reverse recovery, Qrr.

Introduction

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Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) are recognized as advanced power semiconductor devices that enable a wide array of highly efficient, high-power electronic applications. This remarkable capability primarily arises from their wide bandgap characteristics, which enhance performance in demanding operational environments [ 1,2 ]. As the demand for higher efficiency and reliability in power electronic systems continues to grow, recent advancements in this field focus on minimizing the on-resistance (Rds,on) of these devices to significantly reduce conduction losses. However, achieving this goal often requires careful consideration of trade-offs between key design parameters, as elaborated in our previous reports [3, 4,5]. Based on our thorough analysis of these trade-off relationships, we have successfully launched a new 1200 V 4H-SiC MOSFET as Wolfspeed's Gen4 MOSFET. This device offers competitive Rds,on, improved switching energy losses, reduced Qrr, and notably enhanced short circuit withstand time performance. Such improvements are vital for applications in sectors such as renewable energy, electric vehicles, and industrial power systems, where performance and reliability are paramount [2 - 6]. This paper aims to explore the P-body effect resulting from the multi-step ion implantation process, which significantly impacts not only the static characteristics of SiC MOSFETs but also a range of dynamic characteristics. Among these are performance metrics related to body-diode reverse recovery, short circuit withstand time ( Tscwt  ), and the switching energy losses observed in the 1.2 kV 4H−SiC power MOSFETs that are part of Wolfspeed's Gen4 series. By understanding these effects, we can further optimize device performance and contribute to the next generation of high-efficiency power electronics.
1.2 kV 4 H SiC MOSFET structure and Experiment

[picture]

Fig. 1. Schematic cross-sectional view of 1.2kV4H−SiC Power MOSFETs.

Fig. 1. Schematic cross-sectional view of 1.2 k V 4 H − S i C Power MOSFETs.

Figure 1 illustrates a simplified cross-sectional view of a 1.2 kV SiC power MOSFET, clearly depicting the structural elements integral to its function. It highlights critical design parameters such as the width of the JFET ( WJFET  ), gate-drain capacitance ( Cgd ), gate-source capacitance ( Cgs ), and the influence of the n -drift region. These parameters play a crucial role in determining the overall performance of the device, impacting factors like switching speed and efficiency. In our experiments, we varied the P -well doping concentration at two distinct levels to comprehensively investigate the impact of P-well doping on the P-body effect. Specifically, we denote these configurations as High PW and Low PW, which differ in their implantation dose levels. This variation enables us to analyze how different doping concentrations influence device characteristics, such as on-resistance, switching behavior, and reliability. Furthermore, understanding these effects will provide valuable insights into optimizing the design of SiC MOSFETs for high-power applications. The outcomes of our study will contribute to enhancing the performance and efficiency of next-generation power semiconductor solutions.

Electrical Results

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[picture]

Fig. 2. (a) Id and Mobility comparison for two P-wells in lateral MOSFETs, (b) Nit between two P -wells for charge pumping test.

Fig. 2. (a) Id and Mobility comparison for two P-wells in lateral MOSFETs, (b) Nit between two P -wells for charge pumping test.

The experimental results, presented in Figures 2(a) and (b), depict the relationships between drain current ( Id ) and both the calculated field-effect mobility ( μFE ) and trap density (Nit). These were meticulously measured using the charge pumping (CP) method [5], applied specifically to lateral SiC

MOSFETs. These results expose the significant impact of P -well doping on the channel properties of the MOSFET. Notably, the High PW configuration exhibits a threshold voltage ( Vth  ) that is 80 mV higher than that of the Low PW configuration. In contrast, the field-effect mobility μFE is approximately 10% lower in the High PW samples. Additionally, the trap density Nit is found to be about 22% greater in samples with higher P -well doping. These findings suggest that the doping concentration of the P -well can significantly influence the channel properties through gate oxide surface effects, which extend beyond merely adjusting the channel Vth  due to a greater implantation dose of the P-well. The interplay between doping levels and channel characteristics is critical, as it governs the overall efficiency and performance of the MOSFET. Moreover, the increased trap density associated with higher doping concentrations may lead to greater charge trapping effects, potentially impacting the reliability of the device under high-frequency and high-temperature conditions. Understanding these interactions will not only aid in optimizing device design but also provide insights into the long-term stability and efficiency of SiC MOSFETs in various applications.

[picture]

Fig. 3. Static characteristic for two P -wells at 25 and 175∘C. (a) Normalized Rds, on versus Vth (b) BVdss versus Normalized Rds,on.

Fig. 3. Static characteristic for two P -wells at 25 and 175 ∘ C . (a) Normalized Rds, on versus Vth (b) BVdss versus Normalized Rds,on.

Figure 3 presents the static characteristics of the 1.2kV4H−SiC Power MOSFET at two temperatures: 25∘C and 175∘C. Within this figure, 3 (a) and (b) depict the normalized Rds ,on as a function of Vth, alongside the breakdown voltage (BVdss) versus Rds,on, respectively. As shown in Figure 3, the High PW configuration exhibits Rds, on values that are 9.32% and 13.24% greater than those of the Low PW configuration at 25∘C and 175∘C, respectively. Additionally, High PW also shows Vth values that are 5.4% and 1.8% higher than Low PW at 25∘C and 175∘C. Furthermore, High PW demonstrates around 115 V greater BVdss compared to Low PW at both temperature points, primarily as a result of JFET pinching influenced by the heavy doping of the P-well. The results clearly indicate that the High PW configuration exhibits higher values for Vth , Rds,on, and BVdss in comparison to the Low PW configuration, which is consistent with the findings presented in Figure 2. The trends observed suggest that higher P-well doping concentrations lead to enhanced threshold voltage and on-resistance characteristics. Moreover, the rate of increase in Rds, on at 175∘C, is noted to be less pronounced compared to the behavior exhibited at 25∘C when P -well doping increases. This behavior underscores that the variation in the doping profile of the P -well is more dominant in shaping the channel property characteristics, particularly at elevated temperatures. These findings have important implications for the operation and reliability of the device under varying temperature conditions. By gaining insight into these relationships, we can better optimize design parameters to enhance performance and mitigate potential thermal degradation in high-temperature applications. Ultimately, understanding the influence of P-well doping on these key characteristics will provide a pathway to developing more efficient and reliable SiC MOSFETs for demanding applications in the power electronics landscape.

In Figure 4, the measured normalized parasitic capacitance plots ( Ciss ,Coss , and Crss  ) for both doping configurations are presented. The results indicate that for the High PW configuration, Ciss  is approximately 5.5% higher compared to the Low PW configuration, while Crss is around 33% lower. These differences can be attributed to the higher levels of P -well doping, which positively influence the device characteristics. Additionally, the changes in these capacitances also account for the increased breakdown voltage (BVdss) observed in Figure 3(b).

[picture]

Fig. 4. C-V characteristics ( Ciss ,Coss ,Crss  ) for two P-wells at 25∘C.

Fig. 4. C-V characteristics ( C iss , C oss , C rss ) for two P-wells at 25 ∘ C .

[picture]

Fig. 5. Double Pulse Test (DPT) waveforms for two P-wells at 175∘C. (a) Turn on (b) Turn off.

Fig. 5. Double Pulse Test (DPT) waveforms for two P-wells at 175 ∘ C . (a) Turn on (b) Turn off.

[picture]

Fig. 6. Reverse recovery ( Qrr ) waveforms for two P -wells at 175∘C.

Fig. 6. Reverse recovery ( Q r r ) waveforms for two P -wells at 175 ∘ C .

Table 1. Normalized DPT and reverse recovery characteristics based on Fig. 5 and 6.

|  | Low PW | High PW
DPT | dI/dt on | 1 | 0.862
Eon | 1 | 1.055
di/dt off | 1 | 1.103
Eoff | 1 | 0.708
Reverse Recovery | dI/dt | 1 | 0.978
dIr/dt | 1 | 0.789
Irr | 1 | 0.969
Qrr | 1 | 1.203

Furthermore, Figure 5 illustrates the switching waveforms obtained from the double pulse test (DPT), which are essential for comparing the switching characteristics of MOSFETs with the High PW and Low PW doping levels during the Turn On process (Figure 5(a)) and the Turn Off process (Figure 5(b)). Additionally, Figure 6 presents the reverse recovery characteristics, providing a comparative analysis of the body diode performance for both doping samples. The normalized switching parameters, including dI/dt, switching energy losses ( Eon  and Eoff  ), and dIr/dt, are meticulously summarized in Table 1. The High PW configuration exhibits a lower dI/dt during the Turn On phase, accompanied by a higher Eon compared to the Low PW configuration. Conversely, during the Turn Off phase, the High PW configuration demonstrates a higher dI/dt while maintaining a lower Eoff  value. These observed behaviors can be attributed to the reduced channel mobility that arises from the increased levels of P -well doping. In terms of reverse recovery characteristics, the High PW configuration displays a lower dIr/dt and reverse recovery current ( Irr ), while also exhibiting a greater reverse recovery charge ( Qrr ) compared to the Low PW configuration. The heavily doped P-well influences the performance, contributing to a lower softness factor in the body diode, albeit at the cost of an increased Qrr value. Furthermore, it is noteworthy that the High PW configuration demonstrates a higher forward voltage drop ( Vsd ) across the body diode when the gate is fully turned off, although plots illustrating this aspect are not included here. These insights into the switching and recovery characteristics underscore the complex trade-offs associated with varying doping levels in MOSFET designs. Understanding these relationships is essential for optimizing device performance in specific applications, particularly where fast switching and efficient energy management are critical. The findings provide a solid foundation for future studies aimed at refining doping strategies and enhancing overall MOSFET performance in high-power and high-frequency applications.
Σ

Fig. 7. TscWT waveform ( Vds=800 V ) comparison at 175∘C for two P -wells.

In Figure 7, a comparison of short-circuit current waveforms is presented at a drain-source voltage (Vds) of 800 V . The findings indicate that the High PW configuration exhibited a peak drain current reduction of 10.5% during these events. This decrease in peak drain current during short-circuit incidents is associated with a remarkable improvement in the short-circuit withstand time ( Tscwt  ), which is observed to be 25% longer with the heavily doped P -well configuration. These results substantiate the notion that channel mobility, combined with the straggle effects associated with Pwell implantation due to elevated doping levels, plays a vital role in enhancing Tscwt  in these devices. The improved Tscwt  is critical for ensuring the reliability and robustness of the MOSFETs in demanding applications. Additionally, the reduction in peak drain current not only contributes to better thermal management during faults but also reduces the stress on the device, potentially prolonging its operational life. Overall, the relationship between P-well doping and short-circuit performance highlights the importance of optimizing doping strategies to achieve superior device reliability and performance under extreme conditions.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

This study explores the influence of P -well doping levels on the performance of 4H−SiC Power MOSFETs, revealing critical insights into operational efficiency and reliability. The results indicate notable differences between High PW and Low PW configurations in terms of threshold voltage ( Vth  ), field-effect mobility ( μFE ), and trap density (Nit). Specifically, the High PW configuration exhibits a higher Vth  and trap density, which corresponds to a reduction in μFE. These findings highlight the need for optimizing P -well doping concentrations to enhance device performance while managing associated effects. The static characteristics show that the High PW configuration has increased onresistance (Rds,on) and breakdown voltage (BVdss) compared to Low PW, with less sensitivity to temperature changes in Rds,on. Such insights are vital for ensuring stable performance in hightemperature applications. Additionally, our analysis of switching characteristics indicates that higher P-well doping results in trade-offs in dynamic performance. The High PW configuration experiences reduced peak drain current during short-circuit events, contributing to a significant improvement in short-circuit withstand time ( Tscwt  ). This enhancement is crucial for device reliability in demanding environments.

In conclusion, this research underscores the complex relationship between P -well doping and key MOSFET performance parameters. A deeper understanding of these interactions enables better optimization of device design and doping strategies, leading to more efficient and reliable SiC MOSFETs suitable for high-power and high-frequency applications. Future studies should continue refining doping techniques to further enhance device performance under diverse operational conditions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

J. W. Palmour et. al., IEEE ISPSD, 2014, 79-82.

P. Leteinturier et. al., 32nd ISPSD, 2020, pp. 5-9.

https: .

J. Kim et. al., Solid State Phenomena, 2024, Vol. 360, pp 189-193.

J. Kim et. al., ISPSD, 2024, pp. 148-151.

S. R. Stein et. Al., 2024 IEEE International Reliability Physics Symposium (IRPS), pp. 1-5.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 21-27

doi: 10.4028/p-6iQUYo

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-22

Accepted:
2026-01-31

Online:
2026-05-19

High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

Shariare Hossain Rabbi 1,a*, Justin Lynch 1, b, Stephen A. Mancini 1,c and Woongje Sung 1,d

¹College of Nanotechnology Science and Engineering, University at Albany, Albany, NY, 12203, USA

a  srabbi@albany.edu, b  jmlynch@albany.edu, c  smancini@albany.edu, d  wsung@albany.edu

Abstract

This paper reports on the comparative analysis of several 6.5 kV -rated 4H-SiC Junction Barrier Schottky integrated MOSFETs (JBSFETs) and 4H-SiC MOSFET to assess their forward conduction, 3rd  quadrant behavior, and blocking characteristics. Among different JBSFET architectures, the Island P+ JBSFET achieved nearly identical specific on-resistance ( Ron,sp ) to the nominal MOSFET while delivering superior 3rd  quadrant conduction and maintaining a high breakdown voltage. Further optimization of Schottky width demonstrated a trade-off between leakage suppression and 3rd  quadrant conduction efficiency that underscores the Island P+JBSFET 's potential as a reliable high-voltage SiC power device for next-generation applications.

Keywords: 4H−SiC, JBSFET, MOSFET, High Voltage, Power Devices, 3rd  Quadrant Conduction.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

4H−SiC has become a leading material for next-generation high-voltage power electronics owing to its wide bandgap and high critical electric field. These properties enable thinner and more heavily doped drift layers compared to traditional silicon devices, while still maintaining the same voltage blocking capability. Consequently, 4H−SiC power devices can achieve significantly lower onresistance at voltage ratings above 600 V , making them highly attractive for high-efficiency and highpower applications [1]. However, the approximately three times higher built-in potential across PN junctions in 4H-SiC results in a larger forward voltage drop in the intrinsic body diode of MOSFETs during 3rd  quadrant conduction. To mitigate this, external Junction Barrier Schottky (JBS) diodes are often co-packaged as a freewheeling diode [2,3]. While effective, the use of external diodes increases package area.

In high-voltage SiC power devices, the use of thick epitaxial drift layers leads to an increase in basal plane dislocation (BPD) density, thereby worsening bipolar degradation. As drift resistance ( Rdrift ) dominates in high-voltage devices, a relatively large JBS diode is required to effectively prevent body diode conduction. This is crucial, as bipolar current not only slows switching speed but also accelerates the growth of BPDs into stacking faults (SFs), which degrade the MOSFET's static characteristics [4]. To improve conduction efficiency, reliability, and area efficiency, the integration of the JBS diode directly into the MOSFET structure has been proposed, resulting in Junction Barrier Schottky integrated MOSFETs (JBSFETs) [5]. This architecture combines unipolar conduction with improved third-quadrant performance, greatly reducing dependency on the body diode and enhancing device robustness under high-stress conditions [6]. Moreover, this introduced Schottky path mitigates the BPD-induced degradation, which poses a critical reliability concern for SiC devices [7].

While JBSFETs may exhibit higher specific on-resistance ( Ron,sp ) due to increased cell pitch, structural innovations with efficiently integrated JBS diode enhance the forward conduction, achieving performance comparable to that of MOSFET [8]. Although such performance has been demonstrated in low-voltage devices, replicating this in high-voltage architectures remains challenging. Building on prior work where Stripe JBSFET showed reduced 3rd  quadrant forward voltage drop ( VF ) compared to nominal MOSFET [6], this study extends the technique to enhance the 3rd  quadrant conduction, while offering the same Ron,sp  for high voltage devices. A comparative analysis of JBSFET structures and MOSFET is presented, focusing on structural evolution, trade-offs
in Ron,sp,VF, and the role of Schottky width in reducing leakage current for enhanced high-voltage device reliability.

Device Design and Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

Fig. 1 illustrates the structural differences between the Stripe JBSFET, Island P+ JBSFET, and the Nominal MOSFET. The Nominal MOSFET, where a P+ source is placed in the orthogonal direction, within the linear topology of the unit cell [9], has a reduced cell pitch compared to the conventional stripe MOSFET approach, with a cell pitch of 6μ m. The Stripe JBSFET features a wide cell pitch of 11μ m to accommodate the integration of the linear Schottky region. The Schottky area is allocated in the x-direction along with the MOSFET cell by interrupting the p-well. The nature of the linear stripe pattern of the JBSFET structure creates long linear Schottky regions along with the MOSFET cell in the y-direction. In the Island P+ JBSFET, the Schottky opening is placed in the orthogonal direction, similarly to the MOSFET layout, and is shielded solely by the P -well in the X-direction [8]. As a result, a cell pitch of 6.8μ m was achieved for the Island P+ JBSFET. The structural parameters of each device design are summarized in Table 1.

[picture]

Fig. 1. Top layout views of the Nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET structures analyzed in this study.

Fig. 1. Top layout views of the Nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET structures analyzed in this study.

Table 1. Structural parameter summary of each device studied.

Device Type | Cell Pitch (μm) | Active Area [mm²] | Half JFET Width [μm] | Schottky Open in X-axis [μm] | Shielding in X-axis
Nominal MOSFET | 6 | 1.70 | 0.8 | N/A | N/A
Stripe JBSFET | 11 | 1.70 | 0.8 | 2 | P+
Island P+ JBSFET | 6.8 | 1.70 | 0.8 | 1.6 | P-well
5.2 | 0.32 | 0.4 | 0.8 | P-well

[picture]

Fig. 2. Top layout and cross-sectional views of the Schottky contact regions are presented for the Stripe JBSFET (left) and the Island P+ JBSFET (right), featuring Schottky widths ( WS ) of 2μ m and 1.6μ m, respectively, as indicated by the green arrows.

Fig. 2. Top layout and cross-sectional views of the Schottky contact regions are presented for the Stripe JBSFET (left) and the Island P+ JBSFET (right), featuring Schottky widths ( W S ) of 2 μ m and 1.6 μ m , respectively, as indicated by the green arrows.

Fig. 2 illustrates the Schottky region in the Stripe and Island P+ JBSFET featuring a Schottky width ( Ws ) of 2μ m and 1.6μ m, respectively. Cross-sectional views along the X-direction ( A−B and E-F) illustrate how the Schottky region is effectively shielded by the P+ region in the Stripe JBSFET and by the P -well region of the MOSFET in the Island P+ JBSFET. The exclusion of the P+region in the X-direction leads to a significant reduction in cell pitch, resulting in a compacted JBSFET design, which is slightly larger than that of the nominal MOSFET [8]. In the Y-direction (G-H), the Schottky region in the Island P+JBSFET is shielded by the P+ region. To ensure a fair comparison, all devices were fabricated with the same active area, JFET width, and channel length of 1.70 mm2,1.6μ m, and 0.5μ m, respectively. An additional Island P+ JBSFET was evaluated to investigate the impact of a reduced Schottky width (0.8μ m) and a corresponding cell pitch of 5.2μ m on device performance.

A 60μ m thick, 1×1015 cm−3 doped n-type epi-layer on a 4-inch, N+4H-SiC substrate was used to fabricate the JBSFETs, and the Nominal MOSFET. Aluminum ions were implanted to make the Pwell and P+, where the Nitrogen ions were implanted to make the N+ source, respectively. Implantation steps were followed by a 1650∘C10 min activation anneal with a carbon cap. A 50 nm thick gate oxide was formed, followed by a POA in nitric oxide ambient. An interlayer dielectric was deposited and etched using the reactive ion etch process by using the gate pad opening mask to open the ohmic and Schottky regions to avoid an additional mask layer. Ni was deposited on the frontside and patterned, followed by 2−min RTA at 1000∘C. Back-side metal contact was also formed by Ni deposition and the same RTA process. A Ti/Al stack was then deposited to form the Schottky contacts on the N-epitaxial drift layer and also as a top metal for the source metal and gate pad. Front-side was passivated by nitride and polyimide. Finally, a solderable metal stack was deposited on the backside.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

Fig. 3 shows the forward conduction of the Nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET. The specific on-resistance ( Ron,sp ), extracted at Ids=0.15 A and Vgs=20 V, is 42.9 mΩ· cm2 for the Stripe JBSFET, 39.9 mΩ· cm2 for the Island P+ JBSFET, and 39.7 mΩ· cm2 for the nominal MOSFET. Due to the reduced cell pitch of the Island P+ JBSFET, a specific on-resistance ( Ron,sp ) comparable to the MOSFET was able to be achieved while also reducing the Ron,sp by 7.5% when compared to the Stripe type JBSFET. Therefore, the adoption of the Island P+ cell architecture is successfully able to improve the JBSFET output characteristics for higher voltage applications,
similar to their lower voltage rating counterparts. Even though the ohmic region is reduced, the specific on-resistance ( Ron,sp ) of Island P+ JBSFET greatly improved due to the utilization of the entire channel region as a conduction path [8].

[picture]

Fig. 3. Representative output characteristics of the Nominal MOSFET, Stripe JBSFET, and Island P+JBSFE were plotted at gate biases of Vgs=0 V,10 V, and 20 V .

Fig. 3. Representative output characteristics of the Nominal MOSFET, Stripe JBSFET, and Island P + J B S F E were plotted at gate biases of V g s = 0 V , 10 V , and 20 V .

Fig. 4 shows the 3rd  quadrant characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFET, measured at a gate bias of Vgs=0 V and -5 V . With a Vgs=0 V, the forward voltage drops (VF), extracted at Ids=0.5 A, are 6.60 V for the nominal MOSFET, 2.55 V for the Stripe JBSFET, and 2.25 V for the Island P+JBSFET. A gate bias of Vgs=−5 V is applied to suppress channel conduction and isolate the body-diode and Schottky paths. Notably, despite the discontinuity of the Schottky region in the Island P+ JBSFET, the aggressive cell pitch design increases Schottky density,

[picture]

Fig. 4. The 3rd  quadrant characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFET structures were plotted at a gate bias of Vgs=0 V and -5 V .

Fig. 4. The 3 rd quadrant characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFET structures were plotted at a gate bias of V g s = 0 V and -5 V .

resulting in highly efficient unipolar current conduction and a substantial reduction in VF. These results confirm that Island P+ JBSFET exhibits a lower VF than the Stripe JBSFET and outperforms the MOSFET during the 3rd  quadrant operation.

Fig. 5 shows the forward blocking output characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFETs, measured at a gate bias of Vgs=−5 V to minimize any leakage through the channel. The Stripe JBSFET exhibits the highest leakage current due to the strong electric field beneath its large Schottky region [8], which leads to a soft breakdown. In contrast, the Island P+ JBSFET demonstrated significantly lower Leakage current, largely attributed to the fully surrounded Schottky contact, effectively shielding the contact during the blocking mode of operation [10]. However, the Island P+ JBSFET still demonstrated an increased leakage when compared to the nominal MOSFET. Both the nominal MOSFET and the Island P+ JBSFET exhibited avalanche breakdown at approximately 8.3 kV , confirming the superior blocking capability of the Island P+ design compared to the Stripe JBSFET.

[picture]

Fig. 5. Forward blocking output characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFETs were measured at a gate bias of Vgs=−5 V to minimize any leakage through the channel.

Fig. 5. Forward blocking output characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFETs were measured at a gate bias of V g s = − 5 V to minimize any leakage through the channel.

Due to the larger leakage current observed within the Island P+ JBSFET, further designs were investigated with the goal of suppressing the overall leakage current during the blocking mode of operation. For this, an alternative Island P+ design with a reduced Schottky width of 0.8μ m was investigated. The resulting forward blocking and 3rd  quadrant output characteristics for the Island P+ JBSFETs with Schottky widths ( Ws ) of 1.6μ m and 0.8μ m are compared in Fig. 6. By reducing the

[picture]

Fig. 6. The 3rd  quadrant (left) and the forward blocking (right) characteristics of the Island P+ JBSFET structure with WS=1.6μ m and 0.8μ m.

Fig. 6. The 3 rd quadrant (left) and the forward blocking (right) characteristics of the Island P + JBSFET structure with W S = 1.6 μ m and 0.8 μ m .

Schottky width to 0.8μ m, a significant decrease in the leakage current was observed, due to the increased shielding over the Schottky contact. However, this reduction also impacts 3rd  quadrant conduction and requires further optimization of Schottky width and process conditions to balance leakage performance with conduction efficiency.

[picture]

Fig. 7. The trade-off between specific on-resistance ( Ron,sp ) and forward voltage drop ( VF ) was analyzed for the Nominal MOSFET, Stripe, and Island P+ JBSFETs, with forward voltage drop extracted at Vgs=0 V and Ids=0.5 A.

Fig. 7. The trade-off between specific on-resistance ( R o n , s p ) and forward voltage drop ( V F ) was analyzed for the Nominal MOSFET, Stripe, and Island P+ JBSFETs, with forward voltage drop extracted at V g s = 0 V and I d s = 0.5 A .

Fig. 7 summarizes the trade-off between specific on-resistance ( Ron,sp ) and forward voltage drop (VF) for the nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET. The Stripe JBSFET structure demonstrates improved 3rd  quadrant performance but suffers from the highest Ron,sp , and leakage current. In contrast, the Island P+ design achieves the lower Ron,sp than the Stripe structure, which offers almost the same Ron,sp as the nominal MOSFET. The superior 3rd quadrant performance of the Island P+ structure is due to the design innovation that achieves a smaller cell pitch. Despite a slightly larger cell pitch than the MOSFET, the Island P+JBSFET demonstrates well-balanced performance in forward conduction, 3rd quadrant behavior, and leakage current, underscoring its strong potential as a next-generation high-voltage, reliable power device.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

This work compared 6.5 kV -rated 4H-SiC JBSFET architectures with a nominal MOSFET in terms of forward conduction, third-quadrant behavior, and blocking capability. The Stripe JBSFET improved third-quadrant conduction but suffered from the highest Ron,sp, leakage current, and cell pitch. In contrast, the Island P+ JBSFET achieved nearly identical Ron,sp to the MOSFET, superior third-quadrant performance, and a high breakdown voltage of 8.3 kV . Reducing Schottky width to 0.8μ m further suppressed leakage, though at the expense of third-quadrant conduction, emphasizing the need for design trade-offs. Overall, the Island P+ JBSFET offers the best balance of conduction efficiency, leakage suppression, and blocking robustness, highlighting its promise as a reliable highvoltage 4H−SiC power device. Future work will focus on optimizing Schottky width and process conditions, scaling to higher voltage ratings, and validating long-term reliability under dynamic switching stress.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

B Jayant Baliga, Fundamentals of power semiconductor devices. New York, NY: Springer, 2008, Chap.3, pp. 91-155.

R. Callanan, J. Rice, and J. Palmour, "Third quadrant behavior of SiC MOSFETs," in Proc. 28th Annu. IEEE Appl. Power Electron. Conf., Mar. 2013, pp. 1250-1253.

W. Sung and B. J. Baliga, "Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme," in IEEE Electron Device Letters, vol. 37, no. 12, pp. 1605-1608, Dec. 2016, doi: 10.1109/LED.2016.2618720.

A. Agarwal, H. Fatima, S. Haney, and S.-H. Ryu, "A New Degradation Mechanism in HighVoltage SiC Power MOSFETs," IEEE Electron Device Letters, vol. 28, no. 7, pp. 587-589, July. 2007. doi: 10.1109/LED.2007.897861

W. Sung and B. J. Baliga, "On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)," in IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 8206-8212, Oct. 2017, doi: 10.1109/TIE.2017.2696515.

N. Yun et al., "Comparative Study of 6.5 kV 4H-SiC Discrete Packaged MOSFET, JBSFET, and Co-Pack (MOSFET and JBS Diode)," 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vancouver, BC, Canada, 2022, pp. 249-252, doi: 10.1109/ISPSD49238.2022.9813639

R. E. Stahlbush, K. N. A. Mahakik, A. J. Lelis, and R. Green, "Effects of Basal Plane Dislocations on SiC Power Device Reliability," 2018 IEEE International Electron Devices Meeting (IEDM), Dec. 2018, doi: 10.1109/iedm.2018.8614623.

S. A. Mancini, S. Yup Jang, D. Kim and W. Sung, "Exploring Optimum Designs for 1.2 kV 4HSiC JBS Diode Integrated MOSFETs (JBSFETs)," 2022 IEEE 9th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), Redondo Beach, CA, USA, 2022, pp. 11-16, doi: 10.1109/WiPDA56483.2022.9955290.

A. Saha and J. A. Cooper, "A 4H-SiC Power DMOSFET Optimized for Low onResistance," in IEEE Transactions on Electron Devices, vol. 54, no. 10, pp. 2786-2791, Oct. 2007, doi: 10.1109/TED.2007.904577.

S. A. Mancini, S. Y. Jang, D. Kim and W. Sung, "Increased 3rd Quadrant Current Handling Capability of 1.2 kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances," 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Redondo Beach, CA, USA, 2021, pp. 101-106, doi: 10.1109/WiPDA49284.2021.9645152.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 29-36

doi: 10.4028/p-JFK9oG

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-28

Accepted:
2026-01-31

Online:
2026-05-19

Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

Zhaowen He a*, Giorgian Borca-Tasciuc b and T. Paul Chow c

Rensselaer Polytechnical Institute, Troy, New York 12180, U.S.A

a  hez5@rpi.edu, b  borcag2@rpi.edu, c  chowt@rpi.edu

Keywords: High Voltage, 4H-SiC, Power MOSFET, Bidirectional, Cryogenic.

Abstract

We have demonstrated an integrated 3.3 kV 4H-SiC vertical planar bidirectional (BD) conventional (Conv) power DMOSFET in common-drain (CD) configuration using two commercially available power DMOSFET dies and study its operation down to 77 K(−196∘C) to evaluate its cryogenic static and switching performance. The BD conduction and blocking are achieved down to 77 K . The measured specific on-resistance ( RON,sp ) of the BD MOSFET at room temperature (RT) is 26 mΩ - cm2, approximately twice that of the unidirectional device. It increases by 54% when cooled to 77 K due to a substantial increase in channel and possibly JFET on-resistance components. In addition, the extracted specific switching losses ( EON,sp and EOFF,sp ) increases by 33%(13%) at 195 K(−77∘C) and by 83%(88%) at 77 K , relative to their RT values. These increases are primarily attributed to the substantial rise in RON,sp at 77 K . As a result, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance under cryogenic operation, driven mainly by the significant increase in channel and JFET resistance components.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

Cryogenic-capable bidirectional (BD) AC-to-AC power switches are essential for extraterrestrial space missions as well as for superconducting and quantum computing applications. Also, these power switches enable more compact systems and improved integrations, critical for applications where mass, volume, and thermal management constraints are stringent. Compared to the Si counterparts, 4 H -SiC BD power DMOSFETs may be a good candidate for such applications owing to the wide bandgap of 3.26 eV , high critical electric field, and superior thermal conductivity.

[picture]

Fig. 1. Half-cell schematic cross-sections of vertical BD Conv DMOSFETs in (a) Commondrain (CD) configuration. (b) Common-source (CS) configurations.

Fig. 1. Half-cell schematic cross-sections of vertical BD Conv DMOSFETs in (a) Commondrain (CD) configuration. (b) Common-source (CS) configurations.

However, several studies have reported anomalous temperature dependence [1-3] of the specific onresistance (Ron,sp) in unidirectional (UD) commercial 4H-SiC DMOSFETs at cryogenic temperatures, potentially degrading on-state performance. In addition, switching performance degradation at low temperatures has also been documented in the literature [4,5]. These findings highlight the need to investigate and evaluate the cryogenic performance of high-voltage 4H−SiCBD conventional (Conv) DMOSFETs. In this paper, an integrated 3.3kV4H−SiCBD conventional (Conv) DMOSFET is demonstrated and studied down to 77 K(−196∘C) to evaluate its cryogenic static and switching performance.

Device Structure and Integration

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

The vertical BD power DMOSFET can be realized in either common-drain (CD) or commonsource (CS) configurations, as illustrated in Fig. 1. In the CD configuration, the drains of the two planar DMOSFETs are tied together, while the gate of the high-side transistor is biased with a floating power supply to keep the channel on. In the CS configuration, the sources and gates of both devices are connected. The CD configuration simplifies packaging for discrete unidirectional (UD) power transistors but requires separate gate drivers, whereas the CS configuration reduces driver count to one at the expense of more packaging complexity.

Traditional BD functionality is often achieved through hybrid package implementations (Fig. 2) using discrete devices [6]. For example, an anti-series connection of two MOSFETs is used to achieve this, which doubles the on-resistance (Ron) compared to a single device. To mitigate this increase, two identical anti-series pairs can be placed in parallel, but this quadruples the total chip area.

In addition, integrated BD DMOSFETs can be realized using a die-bonded approach (Fig. 2). In this method, two power device dies are bonded back-to-back in a BD package with a metallic interposer. As demonstrated in [7], two 1.2−kV 4H-SiC Conv DMOSFETs in a CD configuration achieve the same chip area as a UD device. This die-bonded approach retains the simplicity of hybrid packaging while enabling a more compact footprint for power module integration.

Monolithic implementations, often in CD configurations, further reduce device count and bondwire connections. In a true monolithic BD Conv DMOSFET, a shared drift region with dual gates enables bidirectional blocking, cutting RON roughly in half for high-voltage ( >3kV ) applications where drift resistance dominates. In 4H−SiC, this implementation was demonstrated in [8] with the BiDFET device (Fig. 2), which achieves a blocking voltage of ±1200 V. The BiDFET consists of two 1.2−kV vertical Conv DMOSFETs in a common-drain configuration, each integrated with a JBS diode. Two drift regions are employed-one for each blocking direction-connected through an N+ substrate and backside drain metallization. While this design benefits from full on-chip integration, it incurs penalties of doubled chip area and doubled specific on-resistance due to the dual drift regions.

[picture]

Fig. 2. Three approaches for implementing vertical BD Conv DMOSFETs in CD configurations.

Fig. 2. Three approaches for implementing vertical BD Conv DMOSFETs in CD configurations.

On the other hand, Chowdhury et al. [9] demonstrated a compact, vertical implementation of monolithic BD 4H-SiC IGBT with shared drift region via the double-sided lithography processes on a free-standing 4H-SiC substrate [10]. The initial prototype devices experimentally achieved blocking voltages of up to 7 kV . This work presents a promising approach for the vertical monolithic integration of 4H−SiCBD DMOSFETs. However, such implementation requires double-sided processes, which increases complexity and cost in fabrication and chip manufacturing.

In this work, the 3.3 kV 4H-SiC BD Conv DMOSFET prototype is vertically implemented in the CD configuration via integrated die-bonded approach using two commercially available Wolfspeed (CPM3-3300-R050A) SiC Gen3 MOSFET dies, as schematically shown in Fig. 3(a). Fig. 3(b) shows the BD DMOSFET chip in a customed BD package. This BD chip is fabricated by joining the drain metal contacts of the two dies using a commercially available nanoparticle silver paste, followed by a 200∘C sintering process. The custom package is constructed by sandwiching the BD die between two through-hole G10 substrates, sealed with silicone for mechanical and environmental protection. A 30μ m Parylene layer and hard baked photoresist layer are used to passivate the exposed die sides, surfaces, and bonding wires.

[picture]

Fig. 3. (a) Circuit schematics and schematic cross-section of the implemented 3.3kV4H−SiC Conv BD DMOSFET in Common-drain configuration. (b) Photo and cross-section of the custom BD DMOSFET package.

Fig. 3. (a) Circuit schematics and schematic cross-section of the implemented 3.3 k V 4 H − S i C Conv BD DMOSFET in Common-drain configuration. (b) Photo and cross-section of the custom BD DMOSFET package.

[picture]

Fig. 4. Temperature-dependent on-state characteristics. (a) Output I-V curves measured at 77, 195, and 300 K for VGS =0,8, and 18 V . (b) Transfer characteristics at VDS =0.1 V over the same temperature range. (c) Estimated specific on-resistance (Ron,sp) components-drift, channel, substrate, and others-extracted at 77,195,300, and 423 K . (d) Threshold voltage ( VT ) as a function of temperature, exhibiting a linear dependence with a temperature coefficient of −12mV/K.

Fig. 4. Temperature-dependent on-state characteristics. (a) Output I-V curves measured at 77, 195, and 300 K for VGS = 0 , 8 , and 18 V . (b) Transfer characteristics at VDS = 0.1 V over the same temperature range. (c) Estimated specific on-resistance (Ron,sp) components-drift, channel, substrate, and others-extracted at 77 , 195 , 300 , and 423 K . (d) Threshold voltage ( V T ) as a function of temperature, exhibiting a linear dependence with a temperature coefficient of − 12 m V / K .

Results and Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

On-state characteristics were measured using a Tektronix 370A curve tracer. An Agilent B1505A power device analyzer equipped with an N1268A ultra-high-voltage expander was used to characterize BVDSS. 

Inductive load switching is performed using a customized inductive load ( 12 mH ) double pulse test (DPT) setup (Fig.6) at 200 V and 5 A with a 100Ω gate resistance ( RG ). A 1.2−kV Rohm SiC commercial Schottky diode (SCS120KGC) was used as the flyback diode to suppress reverse recovery effects. The power supply was set to 200 V , and the gate pulse width was adjusted to achieve a switching current of 5 A . Because the CD configuration requires independent gate drivers, only one device was actively switched, while the other device's gate was held at 18 V .

Fig.4(a) shows the output I-V characteristics of our prototype BD MOSFET at 77(−196∘C),195(−77∘C), and 300 K(27∘C). The output I-Vs show symmetric BD conduction at all three testing temperatures. Extracted RON,sp of the BD device ( VGS=18 V ) at room temperature (RT) is 26 mΩ cm2, which is doubled of the RON,sp of the UD device ( 13 mΩ−cm2 ). Measured RON,sp increased by 54% at 77 K and decreased by 23% at 195 K , showing a "bathtub-shaped" temperature dependence. This is consistent with trends previously reported for UD commercial conventional 4H−SiC DMOSFETs [1,2]. Estimated major resistance components at 77,195,300, and 423 K(150∘C) are plotted in Fig. 4(c). The drift-region resistance component increases monotonically with temperature. Although significant carrier freeze-out occurs at 77 K , the drift resistance still decreases markedly to
21% of its room-temperature value, owing to approximately 20 times increase in bulk electron mobility, as estimated using the temperature-dependent model reported in [16]. On the other hand, estimated channel resistance component exhibits a well-known negative temperature coefficient due to mobility degradation from high interface trapping and increase in threshold voltage at cryogenic temperatures. Interestingly, estimated other lumped resistance components show a non-linear temperature dependence from 77 to 423 K . This non-linear temperature dependence could originate from non-linearity of JFET resistance component from the DMOS structure. According to a reported study of 4H−SiC JFET performance at cryogenic and high temperature [17], the JFET resistance increases with temperature above 200 K , primarily due to the temperature dependence of bulk mobility. Under cryogenic conditions, both [3] and [17] have shown that a shift in the JFET threshold voltage from channel pinch-off, along with carrier freeze-out in the quasi-neutral region, are responsible for the substantial rise in JFET resistance. Due to such reasons, this increase in JFET resistance is predicted to be more pronounced for smaller pitch planar DMOSFETs at 77 K [3]. Therefore, channel and JFET resistance components are likely to dominate in this device at cryogenic temperatures.

The transfer I-V characteristics at VDS=0.1 V are shown in Fig.4(b). Extracted threshold voltages are 7.2,6, and 4.1 V at 77,195 , and 300 K , respectively, exhibiting a monotonic decrease with temperature. To assess the temperature dependence, threshold voltages were extracted up to 423 K . A linear fit across the 77−423 K range yields a negative slope of −12mV/K, consistent with previously reported trends [2]. The ideal threshold voltages from 77 to 423 K , shown as the red curve in Fig. 4(d), were calculated assuming a fixed oxide charge density of 2e12 cm−2, yielding a slope of −2.5mV/K. The deviation between measured and ideal values becomes more pronounced at lower temperatures, suggesting that the discrepancy could originate from increased filled interface charge (Qit) at SiO2/SiC interface at lower temperatures.

[picture]

Fig. 5. (a) Blocking IVs at 77 and 300 K . (b) RoN,sp vs. BV trade-off comparison of the implemented 3.3−kV4H−SiC BD Conv DMOSFET at room temperature (RT) and 77 K . For reference, the authors' prior works on high-voltage 4H−SiC BD superjunction (SJ) [13] and charge-balanced (CB) [14] devices are included, demonstrating improved trade-offs compared to the Conv BD device reported in this work. Commercial high-voltage 4H−SiC UD DMOSFETs are also shown for benchmarking.

Fig. 5. (a) Blocking IVs at 77 and 300 K . (b) RoN,sp vs. BV trade-off comparison of the implemented 3.3 − k V 4 H − S i C BD Conv DMOSFET at room temperature (RT) and 77 K . For reference, the authors' prior works on high-voltage 4 H − S i C BD superjunction (SJ) [13] and charge-balanced (CB) [14] devices are included, demonstrating improved trade-offs compared to the Conv BD device reported in this work. Commercial high-voltage 4 H − S i C UD DMOSFETs are also shown for benchmarking.

[picture]

Fig. 6. Customized inductive load double pulse test (DPT) setup for switching characterization.

Fig. 6. Customized inductive load double pulse test (DPT) setup for switching characterization.

[picture]

Fig. 7. Switching waveforms at 77, 195, and 300 K of the implemented 3.3 kV BD Conv DMOSFET (a) Turn-on waveforms. (b) Turn-off waveforms.

Fig. 7. Switching waveforms at 77, 195, and 300 K of the implemented 3.3 kV BD Conv DMOSFET (a) Turn-on waveforms. (b) Turn-off waveforms.

The blocking I-V characteristics at RT and 77 K are shown in Fig. 5(a). Over 3.4 kV and 3.8 kV BD blocking is achieved at RT and 77 K , respectively. An anomalous increase in BV DSS is observed at 77 K . In both the literature [11] and our prior work [12] on commercial packaged UD 4H-SiC DMOSFETs, the BV DSS has consistently shown a positive temperature coefficient, as expected when breakdown is limited by the intrinsic avalanche mechanism. This behavior arises from the reduced ionization path length at elevated temperatures. Hence, better termination performance could be one of the possible explanations for this anomalous increase in BVDSS  at 77 K .

At 77 K , RON,sp increases by 54% while BVDSS improves by only ~10%, resulting in a degraded RON,sp  vs. BVDSS  trade-off for this device (Fig. 5(b)). Consequently, static performance of the testing device is expected to deteriorate under cryogenic operation.

Fig. 7 compares the switching performance of the implemented 3.3 kV BD Conv DMOSFET at 77, 195, and 300K. During turn-on (Fig.7(a)), the specific energy loss (EON,sp) increases from 0.6 mJ/cm2 at 300 K to 1.1 mJ/cm2 at 77 K , showing an 83% increase in turn-on losses at cryogenic temperatures. In addition, the turn-off waveforms (Fig. 7(b)) also show an increase in energy loss, with Eoff,sp rising from 0.8 mJ/cm2 at 300 K to 1.5 mJ/cm2 at 77 K , exhibiting an 88% increase. This increase in both turn-on and turn-off switching energy is attributed to significant increase of RON,sp at 77 K . Hence, VDS waveforms at 77 K during turn-on and turn-off exhibiting a noticeable slow tail and head while IDS is still high. Overall, the results demonstrate that while BD Conv DMOSFETs maintain functional
switching operation across the full temperature range, both turn-on and turn-off losses increase significantly at cryogenic temperatures, leading to a degradation in dynamic performance.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

An integrated 3.3 kV 4H-SiC vertical BD Conv DMOSFET is successfully demonstrated to maintain bidirectional conduction and blocking capability down to cryogenic temperatures. At 77 K , the channel resistance and possibly JFET resistance from DMOS structure becomes the dominant component, primarily due to inversion electron mobility degradation caused by increased Coulombic scattering. Consistent with UD 4H-SiC DMOSFETs, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance at 77 K , primarily due to the significant increase in channel and JFET on-resistance components.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

The authors would like to thank Wolfspeed, Inc. for providing the 3.3kV4H−SiC commercial Conv power DMOSFET dies used in the bidirectional implementation of this work.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

K. Hong et al., "Experimental investigations into temperature and current dependent on-state resistance behaviors of 1.2 kV SiC MOSFETs", IEEE Journal of the Electron Devices Society, no.7, pp. 925-930, 2019.

S. Chen et al., "Cryogenic and high-temperature performance of power MOSFETs ", 28th Annual IEEE APEC, 2013, pp. 1277-1283.

S. Chowdhury et al., "Comparative evaluation of commercial 1200 V SiC power MOSFETs using diagnostic IV characterization at cryogenic temperatures", Mat. Sci. Forum, vol 897, pp. 545-548, 2017.

Y. Wei et al., "Cryogenic performances comparisons among Si MOSFET, SiC MOSFET, cascode GaN, and GaN devices," IOP Conference Series: Materials Science and Engineering, vol. 1241, pp. 012042, 2022.

K. Tian et al., "Comprehensive characterization of the planar and trench gate MOSFETs from cryogenic to high temperature," IEEE Transactions on Electron Devices, vol. 66, no. 10, pp. 4279-4286, Oct. 2019.

J. Huber and J. W. Kolar, "Monolithic bidirectional power transistors," IEEE Power Electronics Magazine, vol. 10, no. 1, pp. 28-38, Mar. 2023.

C. Hitchcock and T. P. Chow, "Common-drain bidirectional 1200 V SiC MOSFETs," Materials Science Forum, vol. 1004, pp. 882-888, 2020.

K. Han et al., "Monolithic 4-terminal bi-directional field effect transistor (BiDFET) with integrated JBS diodes," Proc. 32nd Int. Symp. Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, Sept. 2020, pp. 242-245.

S. Chowdhury et al., "Operating principles, design considerations, and experimental characteristics of high-voltage bidirectional IGBTs," IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 888-896, Mar. 2017.

S. Chowdhury et al., "Characteristics of 4H-SiC P-i-N diodes on lightly doped free-standing substrates," Proc. 27th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), May 2015, pp. 353-356.

P. Steinmann et al., "Temperature dependence of avalanche breakdown in devices," Journal of Applied Physics, vol. 133, no. 23, pp. 235705, 2023.

Z. He et al., "Comparative performance evaluation and analysis of high voltage superjunction, charge-balanced, and conventional 4H-SiC DMOSFETs at cryogenic and high temperatures," Proc. 37th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), 2025.

Z. He et al., "Experimental demonstration and analysis of 4.5 kV bidirectional superjunction power DMOSFETs in 4H-SiC," Proc. 37th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), 2025.

Z. He et al., "Experimental comparative demonstrations and analysis of common-drain and common-source bidirectional charge-balanced power DMOSFETs switching," Proc. 36th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), 2024, pp. 140-143.

R. Ghandi et al., "Scalable ultrahigh voltage SiC superjunction device technologies for power electronics applications," Proc. IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 9-1.

S. Kagamihara et al., "Parameters required to simulate electric characteristics of SiC devices for n-type 4H-SiC," J. Appl. Phys., vol. 96, no. 23, pp. 5601-5606, 2004.

Cheng et al., "Cryogenic and high temperature performance of vertical junction field effect transistors (VJFETs) for space applications," Proc. Int. Symp. Power Semiconductor Devices and ICs (ISPSD), Santa Barbara, CA, USA, 2005, pp. 231-234.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 37-44

doi: 10.4028/p-2newLP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-17

Accepted:
2026-01-31

Online:
2026-05-19

Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

Stephen A. Mancini 11,a*, Daixin Chen 2,b, Seung Yup Jang 1,4,c, Andrew Binder 3,d, Richard Floyd 3,e, Robert Kaplar 3,f, Jack Flicker 3, g, Adam Morgan 4, h, Xiaoqing Song 2,i, Woongje Sung 1,j

1Department of Nanotechnology Science and Engineering, University at Albany, Albany, NY, 12203, USA

2 Department of Electrical Engineering and Computer Science, University of Arkansas, Fayetteville, AR, 72703, USA

3 Sandia National Laboratories, Albuquerque, NM, USA

4 NoMIS Power Corporation, Albany, NY, USA

a  smancini@albany.edu, b  daixinc@uark.edu, c  sjang3@albany.edu, d  abinder@sandia.gov, e rsfloyd@sandia.gov, f rjkapla@sandia.gov, g satcitt@sandia.gov,

h  adam.morgan@nomispower.com, i  songx@uark.edu, j  wsung@albany.edu

Keywords: 4H-silicon carbide (SiC), bi-directional switch, bi-directional MOSFET, common drain, monolithic integration, design approach.

Abstract

Several 1.2 kV 4H-SiC Bi-Directional MOSFETs (BiD-MOS) design approaches were successfully fabricated and evaluated based on their electrical characteristics. Both monolithic integration design approaches exhibited negligible differences in conduction, blocking, and switching characteristics when compared to their 2-Chip counterpart. However, during the short-circuit withstand time testing, severe gate oscillations were observed in the 2-Chip design, which was not an issue present in either monolithic configuration. As a result of its robust electrical behavior, monolithic integration emerges as a promising design approach for developing efficient and reliable Bi-Directional Switches.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

With the global shift toward electrification, the demand for highly efficient AC-AC and AC-DC converters capable of conducting current and blocking voltage in both forward and reverse directions is rapidly increasing. Conventional power conversion systems (PCS) that employ Bi-Directional switches typically rely on multiple MOSFETs and diode components, which introduce substantial switching losses and increase overall system complexity [1]. Therefore, implementing a single BiDirectional switch offers the potential to simplify the system architecture, reduce the total number of components, and improve both switching efficiency and overall device performance, making it an attractive solution for modern power electronics applications. In line with this approach, several demonstrations of 4H−SiC Bi-Directional Field Effect Transistors (BiDFETs) as monolithically integrated, single-chip devices have been reported [2,3]. However, when using vertical MOSFET technology, the larger chip area required for monolithic integration raises concerns about yield loss and manufacturing efficiency, motivating the exploration of more area-efficient alternatives [4]. While these designs offer promising reductions in chip area even when considering yield losses due to chip size [5], their electrical performance remains insufficiently characterized, leaving questions about trade-offs between integration, efficiency, and reliability. This study investigates the electrical performance of various Bi-Directional MOSFET (BiD-MOS) designs, providing a comprehensive assessment of the feasibility and advantages of monolithic integration for high-performance BiDirectional switching applications.

Device Design and Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

Fig. 1 shows the top and cross-sectional views of three BiD-MOS design approaches evaluated in this study. These include: (1) a 2-Chip solution using two discrete MOSFETs, (2) a monolithic design with two MOSFETs side-by-side on a single chip and matching the area of the 2-Chip solution, and (3) a monolithic design featuring a shared channel stop integrated within the edge termination to reduce die area [4,5]. These designs are referred to as the 2-Chip, Mono, and Mono SN+ BiD-MOS, respectively. The monolithic designs, fabricated as single chips on the wafer, are inherently restricted to the Common-Drain configuration. In contrast, the 2-Chip solution, being composed of separate device components, can be implemented in either Common-Source or Common-Drain form. To ensure a consistent basis for comparison, the 2-Chip solution was also evaluated in the CommonDrain configuration for this study.

[picture]

Fig. 1. Top layout and simplified cross-sectional views of the three Bi-Directional MOSFET (BiDMOS) design approaches examined within this study. The 2-Chip BiD-MOS approach utilizes two individual MOSFET components, whereas the Monolithically integrated BiD-MOS designs employ a single chip solution.

Fig. 1. Top layout and simplified cross-sectional views of the three Bi-Directional MOSFET (BiDMOS) design approaches examined within this study. The 2-Chip BiD-MOS approach utilizes two individual MOSFET components, whereas the Monolithically integrated BiD-MOS designs employ a single chip solution.

In addition to all devices adopting the Common-Drain configuration, the individual MOSFETs used in the monolithic BiD-MOS and the discrete MOSFET components shared the same design and layout. To maximize device performance, 2D electrical simulations were conducted to optimize both the active and edge termination regions. For the active area cell design, the channel length and JFET width were set to 0.5μ m and 1μ m, respectively. The subsequent active area of each MOSFET component was designed to be 0.44 mm2 to achieve the desired current rating. To achieve the 1.2 kV voltage rating, a Hybrid-JTE edge termination was employed to ensure reliable blocking behavior and low leakage current for all devices [6]. In the Mono SN+ design, the channel stop at the end of the termination was shared by both MOSFETs along their common side, thereby reducing die area by enabling the individual MOSFET components to be placed closer together.

The MOSFETs used in the 2-Chip design, along with all monolithic BiD-MOS designs, were fabricated on the same wafer at X-FAB, USA, under identical process conditions. To achieve the targeted 1.2 kV voltage rating, a 10μ m-thick N -type epitaxial drift layer with a doping concentration of 8×1015 cm−3 was grown on top of a heavily doped, N+4H−SiC substrate. Nitrogen and aluminum ion implantation were employed to form the JFET/ N+and P-Well/P +/JTE regions, respectively, followed by a 10 -minute activation anneal at 1650∘C. After the implantation steps, a 50 nm -thick gate oxide was then grown, followed by the deposition of polysilicon. Both layers were then patterned and etched to form the gate regions. This was followed by deposition and patterning of an interlayer dielectric (ILD), enabling the sequential formation of ohmic and gate contacts. A Ti/TiN/AlCu metal stack was subsequently deposited to establish ohmic contacts with the 4H−SiC substrate and the polysilicon gate. The metal stack was then patterned to form the gate and source pads within each device.

To complete the fabrication process, a thick SiN and polyimide layer was deposited and patterned to provide surface passivation. After fabrication, both the 2-Chip and monolithic BiD-MOS designs were packaged in a SOT-227 module for evaluation, as shown in Fig. 2.

[picture]

Fig. 2. Top views of the 2-Chip and Monolithic BiD-MOS design approaches (Top and bottom left, respectively) with the key device regions labeled. Due to the shared substrate limitations of the monolithic designs, both approaches utilize a common-drain configuration and are packaged inside a SOT-227 package (right) with the assistance of NoMIS Power.

Fig. 2. Top views of the 2-Chip and Monolithic BiD-MOS design approaches (Top and bottom left, respectively) with the key device regions labeled. Due to the shared substrate limitations of the monolithic designs, both approaches utilize a common-drain configuration and are packaged inside a SOT-227 package (right) with the assistance of NoMIS Power.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

The measured output of each BiD-MOS design approach in both the forward ( S2→ S1 ) and reverse (S2← S1) directions are shown in Fig. 3. For these measurements, the high-side gate (VG2−S2 for the forward direction and VG1−S1 for the reverse direction) was set to either 20 V or -5 V , while the opposite gate was gradually increased to allow current conduction either through both channel regions or through the body diode of the first MOSFET and the channel region of the second MOSFET. Regardless of the BiD-MOS conduction mode, each design approach exhibited nearly identical output characteristics. When both MOSFET channels were in the on-state ( VG2−S2=VG1−S1=20 V ), the average Ron  values were 169.8 mΩ,169.1 mΩ, and 166.1 mΩ for the 2-Chip, Mono, and Mono SN+ design approaches, respectively. Although minimal, it is important to note that the Mono design, and to a larger extent the Mono SN+ design, resulted in a slightly lower Ron  when compared to the 2-Chip solution counterpart.

[picture]

Fig. 3. Measured output characteristics for each BiD-MOS design approach in both the forward (S2→ S1) and reverse directions (S2← S1), with a gate bias of VG2−S2=20 V and VG1−S1=20 V applied for the forward and reverse directions, respectively (a), and with a gate bias of VG2−S2=−5 Vand VG1−s1=−5 V applied for the forward and reverse directions, respectively (b). Minimal differences between each BiD-MOS design are observed for each conduction mode of operation.

Fig. 3. Measured output characteristics for each BiD-MOS design approach in both the forward ( S 2 → S 1 ) and reverse directions ( S 2 ← S 1 ) , with a gate bias of V G 2 − S 2 = 20 V and V G 1 − S 1 = 20 V applied for the forward and reverse directions, respectively (a), and with a gate bias of V G 2 − S 2 = − 5 V and V G 1 − s 1 = − 5 V applied for the forward and reverse directions, respectively (b). Minimal differences between each BiD-MOS design are observed for each conduction mode of operation.

[picture]

Fig. 4. Simulated current density of the 2-Chip, Mono, and Mono SN+ BiD-MOS design approaches. Both monolithic designs demonstrate conduction through the common epitaxial drift and substrate layers, subsequently increasing the overall current flow.

Fig. 4. Simulated current density of the 2-Chip, Mono, and Mono SN+ BiD-MOS design approaches. Both monolithic designs demonstrate conduction through the common epitaxial drift and substrate layers, subsequently increasing the overall current flow.

To further examine the conduction behavior of the various BiD-MOS design approaches, simplified 2D electrical simulations were performed to highlight potential trends between the structures, as shown in Fig. 4. These simulations reveal that current conduction occurs primarily through the common drain of each BiD-MOS. However, for the Mono design, and more prominently for the Mono SN+ design, current conduction also occurs through the common epitaxial drift and substrate layers. Specifically, the current conduction through the epitaxial drift layer, substrate, and common drain is 0.74%,9.15%, and 90.11% for the Mono BiD-MOS, and 3.66%,32.22%, and 64.12% for the Mono SN+BiD-MOS, respectively, for these simulations. In contrast, due to the layout of the 2-Chip design, current conduction is restricted exclusively to the common drain. The presence of additional conduction pathways in the monolithic designs helps reduce current crowding and slightly improve conduction behavior, resulting in a 1.6% improvement between the Mono and 2-Chip designs. Furthermore, by bringing the MOSFET components closer together in the Mono SN+ design, the conduction pathway is shortened, and overall resistance is reduced, leading to a 7.8% improvement over the 2-Chip design.

The measured blocking characteristics of each BiD-MOS design in both the forward ( S2→ S1 ) and reverse ( S2← S1 ) directions are shown in Fig. 5. For these measurements, both the high- and lowside gates of the BiD-MOS were set to 0 V . All three BiD-MOS designs exhibited similar blocking behavior, with a breakdown voltage of approximately 1620 V and a leakage current below 1 nA at VS2−S1=1200 V. As illustrated in Fig. 6, the blocking capability of each BiD-MOS is determined by the edge termination structure of the low-side device, as this MOSFET operates in its forwardblocking mode. In contrast, the high-side device has no impact on blocking performance. Since all BiD-MOS designs employ the same edge termination, their blocking performance is nearly identical.

[picture]

Fig. 5. Typical measured blocking characteristics of each BiD-MOS design approach in both the forward ( S2→ S1 ) and reverse directions ( S2← S1 ) (a), along with the leakage current in the forward direction (b). Minimal differences between each BiD-MOS design approach are observed.

Fig. 5. Typical measured blocking characteristics of each BiD-MOS design approach in both the forward ( S 2 → S 1 ) and reverse directions ( S 2 ← S 1 ) (a), along with the leakage current in the forward direction (b). Minimal differences between each BiD-MOS design approach are observed.

[picture]

Fig. 6. Simulated electric field and electrostatic potential of the 2-Chip and Monolithic BiD-MOS design approaches during the blocking mode. In both cases, the blocking characteristics are governed by the edge termination of the low-side device, resulting in comparable blocking performance.

Fig. 6. Simulated electric field and electrostatic potential of the 2-Chip and Monolithic BiD-MOS design approaches during the blocking mode. In both cases, the blocking characteristics are governed by the edge termination of the low-side device, resulting in comparable blocking performance.

The switching characteristics of the various BiD-MOS designs were evaluated using a double-pulse test (DPT) setup, with the turn-on and turn-off waveforms shown in Fig. 7. For this analysis, the highside gate (VG2−S2 for the forward direction and VG1−S1 for the reverse direction) was set to 20 V , and switching was performed on the low-side component. Similar to the conduction and blocking measurements, only minimal differences were observed among the design approaches, with the resulting turn-on, turn-off, and total switching losses measuring approximately 0.81 mJ,0.69 mJ, and 1.50 mJ , respectively, for each design.

[picture]

Fig. 7. Measured turn-on (a) and turn-off (b) switching waveforms for each BiD-MOS design approach using a double-pulse test (DPT) setup. During the measurements, VG2−S2=20 V was applied, with the following parameters: gate resistance =10Ω, on-state gate voltage VG1−S1=20 V, off-state gate voltage VG1−S1=−5 V, switching current IS2−S1=50 A, and blocking voltage VS2−S1=800 V.

Fig. 7. Measured turn-on (a) and turn-off (b) switching waveforms for each BiD-MOS design approach using a double-pulse test (DPT) setup. During the measurements, V G 2 − S 2 = 20 V was applied, with the following parameters: gate resistance = 10 Ω , on-state gate voltage V G 1 − S 1 = 20 V , off-state gate voltage V G 1 − S 1 = − 5 V , switching current I S 2 − S 1 = 50 A , and blocking voltage V S 2 − S 1 = 800 V .

To further the evaluation of the various BiD-MOS design approaches, several Short Circuit Withstand Time (SCWT) tests were conducted. Unlike the previous analysis, a noticeable difference can be observed between the 2-Chip and monolithic design approaches, as seen in Fig. 8. Under modified test conditions of VS2−S1=100 V, with a 2μ s pulse, the 2-Chip BiD-MOS exhibited significant oscillations in the gate turn-off waveforms, which were absent in both monolithic configurations. These oscillations were consistent for all 7 measured 2-Chip BiD-MOS samples. Since the gate could not be properly turned off, the resulting SCWT for the 2-Chip approach was unable to be fully determined. However, under typical SCWT evaluation conditions (i.e. VD2−S1=800 V), the Mono and Mono SN+ designs demonstrated comparable SCWTs of 3.82μ s and 3.67μ s, respectively.

[picture]

Fig. 8. VG1−S1 waveforms during the SCWT test in which VS2−S1=100 V, SWCT pulse =2μ s, and VG2−S2=20 V were used (a), and typical SCWT test (i.e. VS2−S1=800 V, and VG2−S2=20 V ) for both monolithic BiD-MOS designs (b). Large oscillations are seen within the VG1−S1 turn-off waveform for the 2-Chip approach that is not present in either of the monolithic designs.

Fig. 8. V G 1 − S 1 waveforms during the SCWT test in which V S 2 − S 1 = 100 V , SWCT pulse = 2 μ s , and V G 2 − S 2 = 20 V were used (a), and typical SCWT test (i.e. V S 2 − S 1 = 800 V , and V G 2 − S 2 = 20 V ) for both monolithic BiD-MOS designs (b). Large oscillations are seen within the V G 1 − S 1 turn-off waveform for the 2-Chip approach that is not present in either of the monolithic designs.

The results of all measurements conducted for each BiD-MOS design are summarized in Table 1. In terms of conduction, blocking, and switching characteristics, the different approaches exhibited nearly identical performance. Under SCWT testing, however, the 2-Chip BiD-MOS showed pronounced gate oscillations that were not observed in the monolithic counterpart. This difference is hypothesized to arise from variations in parasitic inductance between the 2-Chip and monolithic designs, as parasitic inductance has been shown to negatively affect device SCWT [7,8]. However, further analysis is needed to confirm the root cause of these oscillations in the 2-Chip design.

Table 1. Summary of measurement results for the various BiD-MOS design approaches.

BiD-MOS Design Approach | Ron [mΩ] | Breakdown Voltage [V] | Leakage Current @1.2kV [nA] | Turn-On Loss [mJ] | Turn-Off Loss [mJ] | Total Switching Loss [mJ] | SCWT [μs]
2-Chip | 169.8 | 1640 | 0.73 | 0.81 | 0.67 | 1.48 | < 2*
Monolithic | 169.1 | 1620 | 0.52 | 0.83 | 0.71 | 1.54 | 3.82
Mono SN+ | 166.1 | 1640 | 0.46 | 0.79 | 0.69 | 1.48 | 3.67

*Due to high gate oscillations, the actual SCWT of the 2-Chip approach could not be determined.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

Several Common-Drain BiD-MOS design approaches were successfully fabricated and evaluated in terms of electrical performance. The static and switching characteristics were found to be nearly identical across the different designs. However, under the SCWT test, the 2-Chip approach exhibited reliability issues that were not observed in either monolithic counterpart. Given the unhindered electrical performance, monolithic integration emerges as a promising design approach for achieving an efficient and reliable Bi-Directional Switch.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-NA0003525.

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The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

W. Wheeler, J. Rodriguez, J. C. Clare, L. Empringham, and A. Weinstein, "Matrix converters: a technology review," IEEE Transactions on Industrial Electronics, vol. 49, no. 2, pp. 276-288, 2002.

K. Han et al., "Monolithic 4-Terminal A 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Integrated JBS Diodes," 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, 2020, pp. 242-245, doi: 10.1109/ISPSD46842.2020.9170064.

S. Y. Jang, S. B. Isukapati, J. Lynch, and W. Sung, "Demonstration of Cell-to-Cell Integrated 4H-SiC Lateral Bi-Directional Junction Field Effect Transistor (LBiDJFET)," IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA), pp. 400-404, 2021.

S. A. Mancini et al., "Monolithically Integrated , 20A 4H-SiC BiDFET Utilizing an Accumulation Mode Channel for Improved Output Characteristics," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 339-342, doi: 10.1109/ISPSD59661.2024.10579613.

S. A. Mancini et al., "Investigation on Design Approaches for Bi-Directional Field Effect Transistors (BiDFETs)," 2024 IEEE 11th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), Dayton, OH, USA, 2024, pp. 1-5, doi: 10.1109/WiPDA62103.2024.10773119.

W. Sung and B. J. Baliga, "A Near Ideal Edge Termination Technique for 4500 V 4H-SiC Devices: The Hybrid Junction Termination Extension," IEEE Electron Device Letters, vol. 37, no. 12, pp. 1609-1612, Dec. 2016, doi: 10.1109/led.2016.2623423.

G. Kampitsis, E. Batzelis, E. Gati, S. Papathanassiou and S. Manias, "Electro-thermal characterization of 1.2 kV normally-on SiC JFETs under hard switch fault," 2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe), Geneva, Switzerland, 2015, pp. 1-9, doi: 10.1109/EPE.2015.7309054.

B. Kakarla, T. Ziemann, R. Stark, P. Natzke and U. Grossner, "Short Circuit Ruggedness of New Generation 1.2 kV SiC MOSFETs," 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Atlanta, GA, USA, 2018, pp. 118-124, doi: 10.1109/WiPDA.2018.8569077.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 45-50

doi: 10.4028/p-CFg0Cb

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-21

Accepted:
2026-03-16

Online:
2026-05-19

Characteristics of High Current 4H-SiC Schottky Barrier Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1055.45.pdf

Lan Luo 1,a, Yu Zhong 1,b*, Peng Cui 1,c*, Ziang Zhao 1,d, Lei Ge 1,e, Yingxin Cui 1,f, Mingsheng Xu1,g, Xiangang Xu1,h, Jisheng Han 1,d,i* and Yaohao Wang 2,j

1 Institute of Novel Semiconductors, State Key Laboratory of Crystal Materials, Shandong University, Jinan, 250100, China

2 Summit Power Semiconductor Co., Ltd., Guangzhou, 511400, China

a  lan.luo@mail.sdu.edu.cn, b  yu.zhong@sdu.edu.cn, c  pcui@sdu.edu, d  202334091@mail.sdu.edu.cn, eleige@sdu.edu.cn, f  cuiyingxin@sdu.edu.cn, g  xums@email.sdu.edu.cn, i  j.han@sdu.edu.cn, j wangyaohao@summitpower.com

Keywords: 4 H -SiC, SBD, High Current, Large-area, Temperature.

Abstract

Silicon carbide (SiC) Schottky barrier diodes (SBDs) have become critical components in power electronics due to their excellent high-voltage, high-temperature tolerance, and fast switching capability. However, increasing the device area to improve current-carrying capability increases the total number of defects, which leads to an increase in reverse leakage current and a reduction in wafer yield. To improve current distribution uniformity within SiC module packaging, reduce system size and weight, and enhance the current-carrying capacity and high-temperature stability of a single SBD, this paper develops 750 V/100 A and 1200 V/100 A SiC SBDs on 6-inch wafers. For the 750 V/100 A device, the corresponding forward voltage drop (VF) at forward current (IF) of 100 A is 1.68 V . For the 1200 V/100 A device, the corresponding VF is 1.75 V . Calculation based on the current voltage characteristics shows that the ideal factors of 750 V/100 A and 1200 V/100 A devices are 1.01 and 1.04 , respectively, which are very close to 1 . It demonstrates excellent Schottky contact and a high-quality interface. The devices exhibit high-temperature stability, meeting the demands of high-temperature applications.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.45.pdf

In industrial power applications, there is a demand for 4H−SiC SBDs with the capability for a high current [1,2]. These devices have a great potential in fields such as new energy vehicles, switching power supplies, and industrial motor drives [3-5]. Considering the usage scenarios of these applications, enhancing power density is a key issue that assists in improving the system's efficiency. In a high-current module, using the high-current SiC SBDs contributes to the reduced number of chips, and it can increase the uniformity of the current distribution within the module packaging [6]. However, a challenge for high-current SiC SBDs is that increasing the active area to maintain high currents increases the likelihood of encountering material defects. This leads to an increase in reverse leakage current ( IR ) and ultimately reduces wafer yield [7, 8]. Therefore, this paper investigates the fabrication of two high-current SiC SBDs with specifications ( 750 V/100 A and 1200 V/100 A ).

In contrast to conventional ion implantation techniques, this paper proposes a design that employs an epitaxial etching process to fabricate the terminal P+ region. This method not only achieves excellent junction terminal protection but also significantly reduces manufacturing costs[9]. Consequently, the device ensures enhanced reverse blocking voltage capability and reduced IR. Static characteristic tests of 750 V/100 A and 1200 V/100 A SiC SBDs on 6-inch SiC wafers were conducted in the temperature range from room temperature to 240∘C. The devices present superior properties, including high current, low IR, and favorable capacitance characteristics. They maintain stable operation even under high-temperature conditions, thereby meeting the urgent demand for highperformance SiC power diodes in high-temperature and high-frequency power modules.

Experimental

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The schematic diagram of the 4H−SiCSBDs is shown in Fig. 1(a). The devices in this study were fabricated on 6 -inch n-type 4H−SiC single-crystal epitaxial wafers of high quality. The p-type terminal region was patterned by photolithography and inductively coupled plasma (ICP) etching, with its cross-sectional view shown in Fig. 1(b). The terminal protection was accomplished by employing polyimide/silicon nitride (SiN). A nickel (Ni) metal layer was deposited on the rear side of the wafer, followed by high-temperature annealing to form an ohmic contact with the SiC substrate. The titanium (Ti) and aluminum (Al) metal layers were deposited on the n-type SiC epilayer to establish the Schottky contact. Based on the aforementioned process, two large-area single-chip SiC SBDs with different specifications were successfully fabricated. The active region areas were 21.5 mm2 and 38.9 mm2 for the 750 V/100 A and 1200 V/100 A devices, respectively. Photographs of the fabricated samples are shown in Fig. 1(c) and 1(d). The yield of the 750 V/100 A and 1200 V/100 A SiC SBD is 85.4% and 76.4%.

[picture]

Fig. 1. (a) The schematic cross-section of the 4H−SiC SBD structure. (b) The cross-sectional view of the epitaxial etching termination area. (c) 750 V/100 A SiC SBD and (d) 1200 V/100 A SiC SBD fabricated in the 6 -inch SiC wafers.

Fig. 1. (a) The schematic cross-section of the 4 H − S i C SBD structure. (b) The cross-sectional view of the epitaxial etching termination area. (c) 750 V / 100 A SiC SBD and (d) 1200 V / 100 A SiC SBD fabricated in the 6 -inch SiC wafers.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.45.pdf

Forward characteristics at different temperatures

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The static characteristics and temperature stability of the devices are evaluated at various temperatures from 30∘C to 240∘C. The forward characteristic curves of the 750 V/100 A and 1200 V/100 A devices at low current are shown in Fig. 2(a) and 3(a), respectively. Test results indicate that under lower forward current (IF), the forward voltage (VF) of the device decreases with increasing temperature, exhibiting a negative temperature coefficient. This behavior is primarily attributed to the thermionic emission mechanism of the Schottky barrier, where electrons at higher temperatures possess greater energy and can more easily overcome the Schottky barrier. At low forward current, the current-voltage (I-V) characteristics of the SBD typically follow thermionic emission theory. Thus, the forward I-V characteristics can be used to derive the key parameters of SBDs. Calculations show that the Schottky barrier heights (SBH) of 1.31 eV and 1.14 eV for the 750 V/100 A and 1200 V/100 A devices, respectively, with ideal factors (n) of 1.01 and 1.04 , respectively, both very close to 1 . This indicates that current conduction in both devices is almost entirely dominated by thermionic emission, with the effects of interface states or tunneling effects being negligible, confirming the excellent quality of the Schottky contacts and interfaces.

[picture]

Fig. 2. Forward characteristic curves of 750 V/100 A SiC SBD at (a) low forward current, and (b) high forward current.

Fig. 2. Forward characteristic curves of 750 V / 100 A SiC SBD at (a) low forward current, and (b) high forward current.

The forward characteristic curves of the 750 V/100 A and 1200 V/100 A devices at high current are shown in Fig. 2(b) and 3(b), respectively. When VF=1.7 V, the forward current density of the 750 V/100 A SBD decreases from 476 A/cm2 at 30∘C to 259 A/cm2 at 240∘C. The forward current density of the 1200 V/100 ASBD decreases from 240 A/cm2 at 30∘C to 111 A/cm2 at 240∘C. Meanwhile, under the same IF,VF shows significant positive temperature coefficients, rising to 2.54 V(Δ VF=0.86 V) for the 750 V/100 A device and 3.19 V(Δ VF=1.44 V) for the 1200 V/100 A device at 240∘C. This phenomenon is primarily attributed to the increase in the intrinsic resistance of the SiC material and the significant decrease in carrier mobility with rising temperature. Calculation results indicate that at 30∘C, the 750 V/100 A SiC SBD exhibits a specific on-resistance ( Ron-sp  ) of 1.6 mΩ· cm2, while the Ron-sp  of the 1200 V/100 A SiC SBD is 3.3 mΩ· cm2. However, as the temperature increases from 30∘C to 240∘C, the Ron-sp  of the 750 V/100 A device significantly increases to 4.1 mΩ· cm2, while the Ron-sp  of the 1200 V/100 A device increases to 10.4 mΩ· cm2.

[picture]

Fig. 3. Forward characteristic curves of 1200 V/100 ASiCSBD at (a) low forward current, and (b) high forward current.

Fig. 3. Forward characteristic curves of 1200 V / 100 A S i C S B D at (a) low forward current, and (b) high forward current.

Reverse characteristics at different temperatures

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Fig. 4(a) and 4(b) show the reverse characteristics of 750 V/100 A and 1200 V/100 A SiC SBD devices at different temperatures. Test results indicate that the IR of devices is positively related to temperature. Under a reverse voltage ( VR ) of 750 V and room temperature, the IR of the 750 V/100 A device is 13.5μ A. As the temperature increases to 240∘C, the IR of the 750 V/100 A device increases to 1.3 mA . For the 1200 V/100 A device, IR is 14.8μ A at VR=1200 V and 30∘C; after the temperature rose to 240∘C, the IR increased to 1.8 mA . The increase in IR at high temperatures is primarily influenced by the combined effects of thermionic emission current, barrier height lowering, and tunneling current.

[picture]

Fig. 4. Reverse characteristic curves at different temperatures of (a) 750 V/100 ASiCSBD and (b) 1200 V/100 A SiC SBD.

Fig. 4. Reverse characteristic curves at different temperatures of (a) 750 V / 100 A S i C S B D and (b) 1200 V / 100 A SiC SBD.

Capacitance characteristics

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One of the main advantages of SiC SBDs is their ultra-fast switching speed and extremely low switching losses. This study conducted a detailed analysis of their capacitance characteristic. This characteristic is crucial for calculating and predicting the switching losses of the device in actual circuits. Capacitance characteristics are measured at a frequency of 1 MHz , and the results are shown in Fig. 5(a).

Capacitive charge (QC) and capacitance stored energy (EC) are core electrical parameters of SiC SBDs. Qc quantifies the total charge stored under reverse bias in SiC SBDs, which directly determines reverse recovery losses and dynamic turn-on response speed. EC quantifies the magnitude of energy stored through capacitive effects. It is used to evaluate capacitive discharge losses during switching cycles and the risks of circuit surge. Based on the integration results of the capacitance-voltage characteristics, Fig.5(b) and 5(c) show the characteristic curves of QC and EC versus voltage for the
750 V/100 A and 1200 V/100 A devices, respectively. The corresponding QC and EC values for specific VR are summarized in Table 1.

[picture]

Fig. 5. (a) Capacitance-voltage characteristics; (b) Capacitive charge curve; (c) Capacitance stored energy curve.

Fig. 5. (a) Capacitance-voltage characteristics; (b) Capacitive charge curve; (c) Capacitance stored energy curve.

Table 1. Capacitance, QC, and EC at specific voltages of 750 V/100 A and 1200 V/100 A devices.

Devices | Capacitance [pF] | QC [nC] | EC [μJ]
750V/100A (@VR = 400 V) | 347 | 220 | 29
1200V/100A ((@VR = 800 V) | 374 | 423 | 105

Summary

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This study successfully produces high-current SiC SBD devices rated at 750 V/100 A and 1200 V/100 A. Their electrical characteristics are analyzed in the temperature range of 30∘C to 240∘C. Test results indicate that the fabricated 4H-SiC SBDs exhibit excellent static characteristics, with an ideal factor approaching 1, demonstrating superior interface quality. They maintain good thermal stability even at elevated temperatures. Consequently, these SiC SBDs show significant application potential in high-voltage, high-power, high-temperature, and high-frequency fields.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.45.pdf

L. Jiang, W. Zou, Q. Zhang, Y. Chen, X. Yan, Y. Wang, S. Wang, Large-area vertical Schottky barrier diodes based on 4H-SiC epilayers: Temperature-dependent electrical characteristics, J. Nucl. Instrum. Methods Phys. Res., A. 1048 (2023) 167917.

I. -H. Ji, A. Mathew, J.-H. Park. N. Oldham, M. McCain, S. Sabri, E. Van Brunt, B. Hull, D.J. Lichtenwalner, D.A. Gajewski, J.W. Palmour, High Temperature and High Humidity Reliability Evaluation of Large-Area 1200 V and 1700 V SiC Diodes, 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023, pp. 1-4.

A. Battiston, L. Kefsi, M. Milosavljevic and A. Sabrie, High-Power / High-Voltage ( 250 kW / 750 V ) SiC-Based Inverter for Electric Vehicles Applications, 2021 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe), Ghent, Belgium, 2021, pp.111.

Y. Nomura, T. Funaki, T. Hanada and T. Nakamura, Power Conversion Efficiency Improvement of High Voltage Power Supply With SiC SBD Module, 2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe), Coventry, United Kingdom, 2022, pp. 1-6.

T. Kimoto, J. A. Cooper, Applications of Silicon Carbide Devices in Power Systems, in Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, John Wiley & Sons, Singapore, 2014, pp. 445-486.

G. Liu, Y. Wu, K. Li, Y. Wang, ChengZhan Li, Development of high power SiC devices for rail traction power systems, J. Cryst. Growth, 507 (2019) 442-452.

H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, T. Endo, Impact of surface morphology above threading dislocations on leakage current in 4HSiC diodes, J. Appl. Phys. Lett. 101(4) (2012) 042104.

T. Nakamura, T. Miyanagi, I. Kamata, H. Tsuchida, Comparison of Electrical Characteristics of 4H-SiC(0001) and (000-1) Schottky Barrier Diodes, J. Mater. Sci. Forum. 527-529 (2006) 927-930.

S. Dimitrijev and J. Han, U.S. Patent 10,971,580 B2. (2017).

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 51-56

doi: 10.4028/p-t04lTi

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-23

Accepted:
2026-02-26

Online:
2026-05-19

Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

Seung Yup Jang 1,a*, Skylar deBoer 1, b and Woongje Sung 1,c

¹College of Nanotechnology Science and Engineering, University at Albany, Albany NY, 12203, USA

a*  sjang3@albany.edu, b  sdeboer@albany.edu, c  wsung@albany.edu

Keywords: 4H-silicon carbide (SiC), lateral, bi-directional, MOSFET, 3D TCAD simulation.

Abstract

This paper presents the fabrication and characterization of a cell-to-cell integrated SiC lateral bi-directional MOSFET (L-BiD-MOSFET), with blocking performance analyzed through correlation of experimental results and 3D TCAD simulations. The fabricated devices exhibit a breakdown voltage of 600 V , notably lower than the 900 V predicted by 2D simulations. To address this discrepancy, 3D TCAD simulations were performed, which identified electric field crowding at the finger edges as the dominant factor limiting the breakdown voltage. To mitigate this effect, an extended P-top edge design was introduced, which increases the simulated breakdown voltage by more than 10%. Experimental results on devices incorporating the proposed design confirm improved breakdown capability, demonstrating good agreement with simulations. These results highlight the importance of accurate 3D simulation for edge effects in lateral structures. Overall, the proposed design strategy provides valuable guidance for the development of high-performance lateral bi-directional SiC power devices.

Introduction

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Bi-directional power devices, capable of conducting and blocking current in both forward and reverse directions, are essential building blocks for emerging applications such as current source inverters (CSIs) and matrix converters. Various approaches to implementing bi-directional power devices have been reported, including package-level integration and monolithic two-chip integration [1-3]. Recently, our research group successfully demonstrated a cell-to-cell integrated SiC lateral bi-directional power MOSFET (L-BiD-MOSFET) [4, 5]. Cell-to-cell integration not only enables exploration of novel device architectures but also provides considerable area savings by sharing the central drift region. Compared with vertical device structures, lateral structures offer a distinct advantage for cell-to-cell integration, as they can be realized through layout design without requiring complex backside processing.

However, lateral power device structures in wide-bandgap materials require careful electric-field management during high-bias blocking operation. Because these materials exhibit high critical electric fields, achieving a uniform field distribution within relatively small dimensions is essential. This challenge is further pronounced in lateral devices, which contain corner and edge regions where field crowding is more likely to occur. Without proper structural optimization, local field crowding can become severe, ultimately resulting in premature breakdown. In our previous study, the measured breakdown voltage of fabricated devices was lower than simulated predictions, highlighting the need for improved design strategies. To enhance the blocking performance of cell-to-cell integrated lateral bi-directional devices, it is therefore essential to examine layout designs using 3D TCAD simulations to capture electric field concentrations accurately [6, 7].

In this work, we correlate the measurement results of fabricated L-BiD-MOSFETs with 3D TCAD simulations. The 3D analysis reveals significant electric field crowding at finger edges, and we propose an extended P-top design to mitigate these effects, thereby improving breakdown voltage. Simulation results are compared with measured device performance, demonstrating the effectiveness of the proposed design and providing insights for further optimization of high-performance SiC lateral bi-directional devices.

Device Design and Fabrication

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Fig. 1(a) illustrates the schematic structure and symbol of the SiC L-BiD-MOSFET device. It features a common-drain configuration, in which two back-to-back connected MOSFET unit cells share the central n -drift region without a dedicated drain terminal. The sources and gates of the MOSFETs are labeled as Source1 (S1), Source2 (S2) and Gate1 (G1), Gate2 (G2), respectively. The interdigitated S1 and S2 fingers are shown in Fig. 1(b). It should be noted that finger edges are present for each S1 and S2 finger unless alternative isolation techniques, such as mesa etching, are employed.

[picture]

Fig. 1. (a) Cell structure of the common-drain SiC lateral bi-directional MOSFET (L-BiDMOSFET), with the 4-terminal symbol included. (b) Top-view layout showing the designed interdigitated finger structure of the device.

Fig. 1. (a) Cell structure of the common-drain SiC lateral bi-directional MOSFET (L-BiDMOSFET), with the 4-terminal symbol included. (b) Top-view layout showing the designed interdigitated finger structure of the device.

The L-BiD-MOSFET devices were successfully fabricated at Clas-SiC Wafer Foundry, UK. A 10 μm thick drift layer with N - type doping concentration of 1×1016 cm−3 on an N+4H-SiC substrate was used. Aluminum and Nitrogen ion implants were used to form the P-well / P+ source / P-top, and JFET / N+ source, respectively. At the conclusion of all the implantation steps, an activation anneal with a carbon cap was conducted. A 50 nm thick gate oxide was formed, followed by a post-oxidation annealing (POA). An N-type polysilicon was deposited and patterned for the formation of the gate. After, an interlayer dielectric (ILD) was deposited, patterned and etched to make ohmic contact regions. After the formation of ohmic contacts, the source and gate metal, based on Aluminum, were

[picture]

Fig. 2. Cross-sectional SEM images of the fabricated L-BiD-MOSFET. (a) Two interdigitated fingers (S1 and S2). (b) Enlarged view of the S1 finger.

Fig. 2. Cross-sectional SEM images of the fabricated L-BiD-MOSFET. (a) Two interdigitated fingers (S1 and S2). (b) Enlarged view of the S1 finger.

[picture]

Fig. 3. Measured and simulated output and blocking characteristics of the fabricated L-BiDMOSFET. The black curves correspond to the both-gates-on state (bi-directional conducting), while the red curves represent the both-gates-off state (bi-directional blocking). Simulations were performed using a 2D cross-sectional device structure.

Fig. 3. Measured and simulated output and blocking characteristics of the fabricated L-BiDMOSFET. The black curves correspond to the both-gates-on state (bi-directional conducting), while the red curves represent the both-gates-off state (bi-directional blocking). Simulations were performed using a 2D cross-sectional device structure.

deposited, patterned, and etched. For the passivation, Silicon Nitride was deposited, patterned, and etched.

Fig. 2 shows cross-sectional SEM images of the fabricated L-BiD-MOSFET devices. The symmetric finger structures are well defined and consistent with the design. It should be noted that the device was fabricated entirely using the foundry's baseline SiC planar MOSFET process.

The measured and simulated output and blocking characteristics are presented in Fig. 3. The curves correspond to two operating conditions: both gates on (VG1=VG2=20 V) and both gates off (VG1=VG2=0 V ). These results clearly demonstrate the bi-directional and symmetric conducting and blocking behavior of the device. The measured on-state characteristics show good agreement with the simulation results; however, the fabricated devices exhibit a breakdown voltage (BV) of approximately 600 V , which is lower than the 900 V predicted by the 2D TCAD simulations.

3D TCAD Simulation

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To investigate the discrepancy between the 2D simulation and the experimental results, we performed 3D TCAD simulations using Synopsys Sentaurus, focusing on the finger-edge structures that cannot be accurately captured in a 2D environment. Two edge designs were modeled (Fig. 4): (a) a conventional finger-edge structure, in which the P -top width is consistent with that of the finger

[picture]

Fig. 4. Top-view diagrams showing (a) the conventional and (b) the proposed finger-edge designs generated using 3D TCAD simulations.

Fig. 4. Top-view diagrams showing (a) the conventional and (b) the proposed finger-edge designs generated using 3D TCAD simulations.

body, and (b) a proposed structure, where the P -top is widened by 5μ m at the finger edge to mitigate electric field crowding under reverse bias. Identical implantation and process conditions were applied in SProcess [8] to generate 3D doping profiles for both structures.

Accurate device simulation required careful meshing optimization. While fine box meshing was initially applied near the interface to resolve implantation profiles, this approach led to convergence issues in SDevice simulations. To address this, we adopted an adaptive meshing strategy that preserved fine resolution in the critical interface region while gradually coarsening the mesh deeper into the MOSFET structure, enabling stable and reliable device simulations.

Results and Discussion

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As summarized in Table I, the 3D simulation of the conventional finger-edge structure under VS2 sweep conditions (outside high bias) yields a BV of 740 V -significantly lower than both the 2D simulation result and the BV obtained under the opposite bias condition (inside high bias). This confirms that the finger edge is the weak point with respect to electric field crowding in the outside high bias case, thereby preventing the BV from reaching the ideal 2D value.

The proposed finger-edge design achieves a notably improved BV of 818 V (about 10% increase), demonstrating that the extended P -top region effectively suppresses electric field concentration at the edge and consequently enhances the BV. The corresponding electric field distributions are shown in Fig. 5. As expected, the finger edge exhibits a stronger electric field during blocking mode; however, the proposed structure significantly mitigates this crowding. A slightly elevated-though reducedfield remains at the edge compared to the finger body, which likely accounts for the residual gap between the 3D and 2D simulated BVs.

Table 1. Simulated breakdown voltages for each structure and condition.

Bias Conditions | 2D Structure | 3D Conventional | 3D Proposed
VS1 Sweep | 903 V | 888 V | 883 V
VS2 Sweep | 901 V | 740 V | 818 V

[picture]

Fig. 5. Electric field distribution at a depth of 0.6μ m from the surface for (a)-(c) the conventional and (d)-(f) the proposed finger-edge designs. Bias conditions are VS1=700 V and VS2=0 V for (a) and (d), and VS1=0 V and VS2=700 V for (b), (c), (e), and (e). (c) and (f) show surface plots of the electric field at the 0.6μ m depth.

Fig. 5. Electric field distribution at a depth of 0.6 μ m from the surface for (a)-(c) the conventional and (d)-(f) the proposed finger-edge designs. Bias conditions are V S 1 = 700 V and V S 2 = 0 V for (a) and (d), and V S 1 = 0 V and V S 2 = 700 V for (b), (c), (e), and (e). (c) and (f) show surface plots of the electric field at the 0.6 μ m depth.

[picture]

Fig. 6. Measured blocking characteristics of the fabricated devices with conventional and proposed finger-edge designs. Simulated breakdown voltages for each structure are shown as dashed lines for comparison.

Fig. 6. Measured blocking characteristics of the fabricated devices with conventional and proposed finger-edge designs. Simulated breakdown voltages for each structure are shown as dashed lines for comparison.

Measurement results for the fabricated devices with the conventional and proposed finger-edge structures are presented in Fig. 6. The improvements observed experimentally show good correlation with the 3D simulation results, although a gap between the measured and simulated values still remains. This discrepancy appears to be common to both structures, suggesting a mismatch between the simulated and the actual fabricated devices.

Several possible causes can be considered. The most likely contributors are variations in the net P-top dose and width. Because the present design employs a P-top structure analogous to a singlezone junction termination extension (JTE), the BV is highly sensitive to these parameters [9]. Although the simulations reproduce the process flow and account for factors such as implant profiles and SiC consumption, discrepancies in the actual P+/P-top dimensions or in SiC surface consumption could lead to deviations between simulation and experiment. To address this, calibration through a series of split experiments varying dose and width will be required, and future designs should aim to be less sensitive to such variations. Additional factors may also play a role, including the influence of SiC/oxide interface states and structural differences in the implanted regions near corners.

Note that GaN lateral bi-directional power devices at the 600 V class have been demonstrated for nearly two decades and recently commercialized by several vendors [10,11]. Compared with GaNbased solutions, SiC L-BiD-MOSFETs can offer complementary advantages in applications where robust avalanche characteristics and high-temperature operation are emphasized. The use of a thermally grown SiO2 gate dielectric further supports stable MOS-gated device operation within SiC processing platforms. In addition, lateral SiC device structures can be oriented toward future integration with SiC CMOS technologies, enabling increased functionality at the chip level.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

In this work, we investigated and improved the blocking performance of a cell-to-cell integrated SiC lateral bi-directional MOSFET (L-BiD-MOSFET) through combined experimental characterization and 3D TCAD simulation. The fabricated devices exhibited a breakdown voltage of 600 V , notably lower than the 900 V predicted by 2D simulations, due to electric field crowding at finger edges. To address this limitation, an extended P -top edge design was proposed, which reduced field concentration and improved the simulated breakdown voltage by more than 10%. Experimental measurements of devices with the proposed design confirmed enhanced blocking capability, in good agreement with the 3D simulation results. The remaining gap between the measured and simulated breakdown voltages may be attributed to process and structural mismatches between the simulated and fabricated devices-particularly variations in the P-top dose and width, as well as differences in
the SiC /oxide interface states. These findings highlight the importance of accurate 3D TCAD analysis to capture edge effects that cannot be represented in 2D simulations. Overall, the proposed edgeengineering approach provides effective design guidance for advancing high-performance lateral bidirectional SiC power devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

The authors would like to thank Clas-SiC Wafer Foundry for the fabrication of the devices and Alexander Bialy at NY CREATES for providing the SEM image presented.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

K. Han, A. Agarwal, A. Kanale, B. J. Baliga, S. Bhattacharya, T-H. Cheng, D. Hopkins, V. Amarasinghe, J. Ransom, "Monolithic 4-Terminal 1.2kV/20 A 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Integrated JBS Diodes," The 32nd  International Symposium on Power Semiconductor Devices & ICs (ISPSD), pp 242-245, (2020).

S. A. Mancini, S. Y. Jang, A. Binder, R. Floyd, R. Kaplar, J. Flicker, S. Atcitty, A. J. Morgan, W. Sung, "Investigation on Design Approaches for Bi-Directional Field Effect Transistors (BiDFETs)," IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA), pp 1-5, (2024).

S. A. Mancini, D. Chen, S. Y. Jang, A. Binder, R. Floyd, R. Kaplar, J. Flicker, S. Atcitty, J. Lynch, A. J. Morgan, X. Song, W. Sung, "Comparative Analysis Between Monolithically Integrated 1.2 kV Bi-Directional MOSFETs and Bi-Directional JBSFETs," The International Symposium on Power Semiconductor Devices & ICs (ISPSD), pp 589-592, (2025).

S. Y. Jang, S. B. Isukapati, D. Kim, W. Sung, "First Demonstration of 600 V 4H-SiC Lateral Bi-Directional Metal-Oxide-Semiconductor Field-Effect Transistor (LBiDMOS)," The International Symposium on Power Semiconductor Devices & ICs (ISPSD), pp 5-8, (2023).

S. Y. Jang, S. A. Mancini, W. Sung, "600 V 4H-SiC Lateral Bi-Directional JBS Diode Integrated MOSFET (L-BiD-JBSFET)," The International Symposium on Power Semiconductor Devices & ICs (ISPSD), pp 335-338, (2024).

A. Shimbori, A. Q. Huang, "Design methodologies and fabrication of 4H-SiC lateral Schottky barrier diode on thin RESURF layer," Applied Physics Letters 120 (12), 122103 (2022).

A. Shimbori, A. Q. Huang, "Design Optimization and Surge Current Capability of Lateral Deep P JBS Diode on Thin RESURF Layer," IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA), pp 17-21 (2022)

Synopsys Inc., SentaurusTM Process User Guide, ver. T-2022.03, March 2022.

W. Sung, B. J. Baliga, "A near ideal edge termination technique for devices: The hybrid junction termination extension," IEEE Electron Device Letters, vol. 37 (12), pp 1609-1612 (2016).

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 57-61

doi: 10.4028/p-F5Vgsj

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-17

Accepted:
2026-02-26

Online:
2026-05-19

Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

D. Dansako a*, T. Abe b , K. Miyazaki c , T. Tanioka d , Y. Kagawa e  and T. Nitta f 

Power Device Works, Mitsubishi Electric Corporation,1-1-1, Imajuku-higashi, Nishi-ku, Fukuokashi, Fukuoka, 819-0192, Japan

a  Dansako.Daichi@dh.mitsubishielectric.co.jp, b  abe.tetsuya@dc.mitsubishielectric.co.jp, c  miyazaki.kosuke@dw.mitsubishielectric.co.jp, d  tanioka.toshikazu@eb.mitsubishielectric.co.jp, e  kagawa.yasuhiro@cj.mitsubishielectric.co.jp, f  nitta.tetsuya@ea.mitsubishielectric.co.jp

Keywords: edge termination, field limiting rings (FLRs), SBD embedded MOSFET, HV-H³TRB.

Abstract

In high-voltage class SiC devices, maintaining sufficient robustness against humidity and fabrication processes has become a major concern when minimizing the edge termination size. Previous research has shown that suppressing the maximum electric field on the SiC surface in the termination region improves durability in HV-H 3 TRB tests for 3.3 kV SBDs. In this study, we investigated the impact of the FLR design on the electric field distribution in the termination region. Simulation results showed that the termination length can be reduced without changing the maximum electric field on the SiC surface and the breakdown voltage. Furthermore, the fabricated 4.5 kV SiC SBD-embedded MOSFETs exhibited good reverse leakage characteristics, which were consistent with the simulation results.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Silicon carbide ( SiC ) is a promising material for power devices owing to its excellent properties such as a wide bandgap, a high critical electric field, and high thermal conductivity. Thus, 3.3 kV class SiC power devices are currently applied to railways [1], and 4.5 kV -class and higher devices are expected for HVDC and power grids [2-3]. However, as the power class becomes higher, the edge termination size increases, leading to larger chip sizes and higher manufacturing costs.

Previous research indicated that field limiting rings (FLRs) exhibit high robustness against Al implantation dose variations [4-5]. Furthermore, another study showed that reducing the maximum electric field on the SiC surface ( Esurface max  ) in the termination region improves durability in high voltage high humidity high temperature reverse bias (HV-H 3 TRB) test for 3.3 kV Schottky Barrier Diodes (SBDs) [6].

In this paper, we investigated the impact of the FLR design on the electric field distribution in the termination region using TCAD simulation and evaluated the fabricated 4.5 kV SiC SBD -embedded MOSFETs.

Simulation Setup

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Figure 1 shows a cross-sectional schematic of the simulated FLR region. The substrate and drift layer are n-type 4H−SiC(0001). The p-doped layer has a simulated Al implantation profile. Each FLR pitch ( PFLR  ) is uniform, and the ring spacing of the FLRs is designed to increase as it moves outward according to the outermost ring spacing (WN). Positions (x) and (y) indicate the innermost and outermost FLR positions, respectively.

[picture]

Fig. 1. Cross-sectional schematic of the simulated FLR region.

Fig. 1. Cross-sectional schematic of the simulated FLR region.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Figure 2 (a)-(c) show the simulated 2-D electric field distributions in the termination region. PFLR  is fixed at 9.0μ m.WN values are set to (a) 7.2μ m, (b) 4.5μ m, and (c) 1.8μ m. The applied DrainSource voltage is 3.6 kV , corresponding to typical HV-H 3 TRB test conditions. As WN decreases, the depletion layer extends further outward, causing the position of the maximum electric field to shift outward as well. The electric field distributions on the SiC surface and at the PN junction were investigated in detail. Figure 3 shows the extracted distributions. When WN is 4.5μ m,Esurface max  and the maximum electric field at PN junction ( EPN max  ) reach their minimum values of approximately 1.3 MV/cm and 2.3MV/cm, respectively. The position of the Esurface max  is further outward than that of EPN max , which is located at the center of the FLR. It is found that Esurface max  should be located slightly outward from the center of the FLR structure to suppress its value.

Figure 4 compares the light emission positions and the simulated EPN max  positions of PN diode TEGs with WN values of (a) 7.2μ m, (b) 4.5μ m, and (c) 1.8μ m when avalanche breakdown occurred. As WN decreases, the emission position shifted outward, and all emission positions correspond closely to the simulated EPN max  positions.

[picture]

Fig. 2. Simulated 2-D electric field distributions for termination region.

Fig. 2. Simulated 2-D electric field distributions for termination region.

[picture]

Fig. 3. Relation between electric field distribution and WN on (a) SiC surface (b) PN junction.

Fig. 3. Relation between electric field distribution and W N on (a) SiC surface (b) PN junction.

[picture]

Fig. 4. Comparison between light emission and simulated EPNmax position of PN diode TEGs.

Fig. 4. Comparison between light emission and simulated E P N max position of PN diode TEGs.

We investigated the WN at which Esurface max  is minimized when varying the PFLR  values. Figure 5 shows the relationship among WN,Esurface max  and BV . The optimal WN values vary according to PFLR, with values of 3.5,4.2, and 4.5μ m corresponding to PFLR  values of 5.0,7.0, and 9.0μ m, respectively. At these values, BV doesn't decrease and there is sufficient margin for variations in WN.

Furthermore, we investigated the dependence of Esurface max  and BV when varying FLR length with the optimal WN values. As shown in Fig. 6, by reducing PFLR  with the optimized WN values, the FLR length can be shortened while maintaining a low Esurface max  and an equivalent BV .

[picture]

Fig. 5. Relation among WN,Esurface max  and BV .

Fig. 5. Relation among W N , E surface max and BV .

[picture]

Fig. 6. Dependence of Esurface max  and BV when varying FLR length using the optimal WN values.

Fig. 6. Dependence of E surface max and BV when varying FLR length using the optimal W N values.

Figure 7 shows the relationship among Al dose, BV , and Esurface max  for the three termination designs (A-C), which have equivalent Esurface max  but different termination lengths. The parameters of terminations (A-C) are presented in Table 1. Even with a short FLRs length of 155μ m, a wide margin of Al dose ranging from 1.5 to 2.5×1013 cm−2 was confirmed. When the Al dose exceeds 2.5×1013cm−2, Esurface max  significantly increases. This increase is attributed to the electric field concentration at the outermost FLR.

We fabricated SBD-embedded MOSFETs with the three simulated terminations (A-C). Figure 8 shows typical reverse leakage current characteristics at 25∘C with Gate-Source voltage of -7 V . The experimental BV and reverse leakage characteristics exhibited no significant differences among the three termination designs. The experimental BV matched the simulated values of approximately 5.4 kV well.

[picture]

Fig. 7. Dependence of BV and Esurface max  on Al dose.

Fig. 7. Dependence of BV and E surface max on Al dose.

[picture]

Fig. 8. Reverse leakage current characteristics of fabricated SBDembedded MOSFET.

Fig. 8. Reverse leakage current characteristics of fabricated SBDembedded MOSFET.

Table 1. Parameters of selected three termination structures.

Termination structure | FLR length [μm] | PFLR [μm] | WN [μm]
A | 155 | 5 | 3.5
B | 205 | 5 | 3.5
C | 287 | 7 | 4.2

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

We investigated termination designs for 4.5 kV SiC devices from the points of cost-effectiveness, humidity-tolerance and process-robustness using simulation and fabricated 4.5 kV SiC SBDembedded MOSFETs. By optimizing WN, the electric field peak on the SiC surface shifts slightly outward from the center of the FLRs and Esurface max  reached its minimum value. By reducing the PFLR  with the optimized WN, the FLR length can be shortened while maintaining Esurface max  low and an equivalent BV . Even with a short FLR length of 155μ m, a wide margin of Al dose ranging from 1.5 to 2.5×1013 cm−2 was confirmed. Furthermore, the fabricated devices exhibited almost the same BV as the simulation and showed no difference in leakage characteristics.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Information on http://www.mitsubishielectric.com/news/2013/1225.html.

A. Q. Huang, Power Semiconductor Devices for Smart Grid and Renewable Energy Systems, Proceedings of the IEEE. 105 (2017) 2019-2047.

S. Sen, J. Tong, Z, Guo and A. Q. Huang, A Bottom Charge-Modulated Field Limiting Rings Termination With N-P-N Sandwich Epitaxial Wafers for 4H-SiC Devices, in Proc. APEC 2022, 957-961.

K. Ebihara, K. Kawahara, S. Hino, K. Sadamatsu, A. Nagae, Y. Nakao, H. Watanabe and S. Yamakawa, Investigation of the Robust Edge Termination Applied to 6.5 kV SiC MOSFET, Materials Science Forum, 924 (2018) 778-781.

J. Zhang, H.Luo, H.Wu, Z. Wang, B. Zheng and X. Chen, Design and optimization of cell and field limiting ring termination for 1200 V 4H-SiC Junction Barrier Schottky (JBS) Diodes, in Proc. ICEPT 2022, 1-5.

K. Ebihara, H. Niwa, T. Murakami, K. Fujiyoshi, Y. Nakata, S. Okimoto, K. Hatori and K. Nishikawa. Durable Edge Termination Design of SiC SBD against Humidity, in Proc. ISPSD 2024, pp.510-513.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 63-68

doi: 10.4028/p-Rd95Vt

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-04

Revised:
2025-12-12

Accepted:
2026-03-16

Online:
2026-05-19

JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Zihan Zhang 1,a, Lei Yuan 1,4, b*, Kaiyu Chen 2,c, Xiaowen Wang 2, d, Xuesong Liu 3,e, Tongxiao Hou 3,f, Bo Peng 1, g, Guibao Wang 4, h, Miao Yu 4,i, Renxu Jia 1,4,j and Yuming Zhang 1,k

1 Faculty of Integrated Circuit, Xidian University, Xi'an 710071, China

2 Alkaidsemi Electronic Technology Ltd., Shanghai, China

3 Beijing BJAST Holdings Co., Ltd., Beijing, China

4 Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, China

a 24251111422 @stu.xidian.edu.cn, b*yuanlei@xidian.edu.cn, cgary_chen@alkaidsemi.com, d  xiaowen_wang@alkaidsemi.com, e  xs6721@126.com, f  644988605@qq.com,

bboopeng @xidian.edu.cn,h  wangguibao@xidian.edu.cn, i  yumiao@xidian.edu.cn,  jrxjia@mail.xidian.edu.cn, k zhangym@xidian.edu.cn

Keywords: edge termination, silicon carbide (SiC), superjunction (SJ), junction termination extension (JTE), process robustness, charge-imbalance.

Abstract

A charge-imbalanced P-pillar distribution termination (D3) is proposed for 1500 V -class 4H−SiC superjunction (SJ) devices. By combining a junction termination extension (JTE)-based termination with gradually widened P-pillar spacing, the design effectively suppresses edge electric field crowding and enhances device reliability. TCAD simulations show that D3 achieves comparable blocking capability while exhibiting significantly improved robustness against charge imbalance, oxide charge density, and JTE dose deviations, demonstrating superior process margin and reliability. With relaxed process sensitivity and an efficient structure, D3 presents a promising approach for highvoltage 4H−SiC SJ device fabrication.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

With the evolution of electric vehicle voltage platforms from 400 V to 800 V and even 1000 V , the demand for higher-voltage power devices continues to grow [1, 2]. Among them, 1500 V silicon carbide ( SiC ) metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted increasing attention, since 1200 V devices provide insufficient voltage margin at the 1000 V platform, while 1700 V devices result in unnecessary cost and overdesign [1]. Nevertheless, the intrinsic tradeoff between breakdown voltage (BV) and specific on-resistance ( Ron,sp ) remains a major challenge in developing 1500 V SiC MOSFETs with high voltage capability, high current density, fast switching, and low power loss [3]. By employing charge compensation effect, superjunction (SJ) technology breaks the conventional BV~Ron,sp  trade-off, allowing for higher drift doping concentrations under high breakdown conditions and thus offering significant potential for low-loss, high-voltage device operation [4]. However, the charge balance in SJ devices, realized by periodically alternating heavily doped N-pillars and P-pillars, demands highly precise process control, significantly increasing fabrication complexity, especially in the termination region [5-8]. Notably, studies on SiC SJ terminations remain limited, and most using uniform P-pillar distributions, with few analyzing the impact of P -pillar distribution on termination performance [2,9,10].

In this work, we propose a novel charge-imbalanced P-pillar distribution structure for JTE-based 4H-SiC SJ terminations (D3) for 1500 V 4H-SiC SJ-MOSFETs. The design more effectively suppresses edge electric fields by gradually widening the P -pillar spacing, and achieves more efficient lateral depletion of the superjunction by JTE structure. We evaluate the impact of P -pillar distribution on the performance and process robustness of JTE-based 4H-SiC SJ terminations.

Design and Simulation

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Figures 1(c)-1(e) show three termination designs with different P-pillar distributions: D1 with uniform spacing (N/P balanced), D2 with a non-uniform distribution (N-rich center, P-rich edges), and D3 transitioning from P-rich to N-rich. It is worth noting that in JTE-based SJ terminations, the JTE region sustains the surface electric field while the SJ pillars support the bulk field, and their combined action provides effective protection for the MOSFET cell region. The top-view layout is shown in Figure 1(a). The corresponding breakdown voltages, shown in Fig. 1(b), all exceed 1700 V , satisfying the 1500 V voltage device requirement. The electric field distribution at 1500 V is shown in Fig. 2. D1 exhibits higher P-pillar utilization efficiency, with the P-pillars near complete depletion at the edge of the termination due to the relatively small uniform spacing.

[picture]

Fig. 1. SJ termination structures including (a) top-view layout, (b) reverse blocking performance, and (c) N/P balanced, (d) N-rich center with P-rich edges, and (e) P-rich to N-rich transition designs.

Fig. 1. SJ termination structures including (a) top-view layout, (b) reverse blocking performance, and (c) N/P balanced, (d) N-rich center with P-rich edges, and (e) P-rich to N-rich transition designs.

[picture]

Fig. 2. Electric field distributions of D1-D3 under 1500 V blocking voltage, showing higher termination efficiency for D1.

Fig. 2. Electric field distributions of D1-D3 under 1500 V blocking voltage, showing higher termination efficiency for D1.

Fig. 3 further analyzes the electric field distribution along different cutlines ( C1~C3 ) at a blocking voltage of 1500 V . Significant electric field peaks appear near the terminal surface at C 1 and C 2 in D1, exceeding the bulk field level, while a sharp field drop is observed at the edge (C3). Such insufficient redistribution of the bulk field induces edge field crowding, potentially threatening longterm reliability despite meeting the 1500 V blocking requirement. In D 2 , the electric field peak at C 1 and C2 degrade device reliability, even though their peaks are below the bulk field level. By comparison, D3 demonstrates a highly uniform field profile, indicating improved prospects for longterm device stability. In the D3 structure, the lateral charge-compensation gradient transitions gradually from a P -rich region near the source to an N -rich region toward the edge. This graded profile enables a smoother lateral depletion process, allowing the electric field to spread across a wider effective termination width rather than concentrating near the gate-oxide surface.

[picture]

Fig. 3. Electric field distributions along (a) C1, (b) C2, and (c) C3 cutlines under 1500 V drain bias for different termination designs.

Fig. 3. Electric field distributions along (a) C1, (b) C2, and (c) C3 cutlines under 1500 V drain bias for different termination designs.

Process Robustness Evaluation

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Breakdown Voltage Dependence on charge imbalance.

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

The reliance of SJ structures on precise charge balance makes them highly sensitive to process variation, posing a major challenge to device fabrication. Fig. 4(a) shows the impact of P-pillar dose errors on termination performance. It is observed that D3 maintains 1500 V blocking capability with an error window exceeding ±8%, showing a clear advantage, especially under P-rich conditions. The improved robustness is attributed to the widened P -pillar spacing at the edge, which reduces the effect of charge imbalance on termination performance.

Breakdown Voltage Dependence on oxide charge density.

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

The impact of oxide charge located at the SiO2/SiC cannot be ignored in the manufacturing of SiC devices [11]. The sensitivity of the termination blocking capability to the oxide charge density (Nox) is illustrated in Fig. 4(b), with the calculation range of Nox selected according to representative values
previously reported in the literature [12, 13]. Both positive and negative interface charges affect the BV, with higher densities markedly degrading the terminal blocking capability. For positive oxide charge, all three structures exhibit nearly identical blocking performance, while D3 shows a broader blocking range under negative oxide charge. With a tolerance window of 1.1×1013 cm−2 at 1500 V blocking, D3 achieves a 51% improvement compared with D1. The breakdown current distribution at a negative Nox of 5×1012 cm−2 is shown in Fig. 5. The breakdown location of D3 shifts inward compared to D1 and D2, indicating its potential to withstand higher negative oxide charge density.

Breakdown Voltage Dependence on JTE dose error.

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

The impact of JTE concentration variation on termination blocking capability was investigated in Fig. 4(c), considering the dose sensitivity of JTE structures. The blocking capability of D1 degrades markedly once the JTE dose exceeds the optimum. By contrast, D2 and D3 exhibit low sensitivity within a ±15% dose variation, thereby relaxing implantation accuracy requirements and resulting in a significantly wider tolerance window. Fig. 4(d) shows that under a 5% JTE dose deviation with a termination length of 140μ m, D1 suffers from pronounced edge field crowding, whereas D3 reduces the edge electric field by 92% along cutline C2, even though both designs exhibit comparable blocking capability.

[picture]

Fig. 4. Impact of (a) charge imbalance, (b) oxide charge density, and (c) JTE dose error on breakdown voltage for D1, D2, and D3, and (d) electric field distributions under a 5% JTE dose deviation.

Fig. 4. Impact of (a) charge imbalance, (b) oxide charge density, and (c) JTE dose error on breakdown voltage for D1, D2, and D3, and (d) electric field distributions under a 5 % JTE dose deviation.

[picture]

Fig. 5. Breakdown current density distribution of D1-D3 at Nox =−5×1012 cm−2, with D3 showing breakdown closer to the active region, indicating a higher tolerance to negative charge density.

Fig. 5. Breakdown current density distribution of D1-D3 at Nox = − 5 × 10 12 c m − 2 , with D3 showing breakdown closer to the active region, indicating a higher tolerance to negative charge density.

The enhanced robustness of D3 originates from the lateral P-rich to N-rich pillar arrangement, which promotes smoother lateral depletion and suppresses edge field concentration, thereby reducing the impact of charge imbalance, oxide charges, and JTE-dose variations.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

In this work, the impact of P-pillar distribution on JTE-based terminations for 4H-SiC SJ MOSFETs was systematically investigated. TCAD simulations of three representative designs (D1D3) demonstrated that the D3 structure with a non-uniform P-pillar distribution provides the most uniform electric field profile and superior robustness against process-induced variations, including superjunction charge imbalance, interfacial oxide charges, and JTE dose deviations. These results indicate that the D3 termination is a promising solution for high-voltage SiC SJ devices, offering both enhanced breakdown capability and improved process tolerance.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Information on https://www.componentbuy.com/newsroom/byd-unveils-1500v-sic-module-on-super-e-platform.

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M. Okada, S. Kyogoku, T. Kumazawa, J. Saito, T. Morimoto, M. Takei, S. Harada, Superior short-circuit performance of SiC superjunction MOSFET, C. International Symposium on Power Semiconductor Devices & ICs (ISPSD). (2020) 70-73.

Tawara, Takeshi, Kensuke Takenaka, Syunki Narita, Mitsuru Sometani, Kunihide Oozono, Shiyang Ji, Tadao Morimoto, Shinsuke Harada, Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs, J. Materials Science in Semiconductor Processing. 176 (2020).

Y. Kobayashi, S. Kyogoku, T. Morimoto, T. Kumazawa, Y. Yamashiro, M. Takei, S. Harada, High-temperature performance of 1.2 kV -class SiC superjunction MOSFET, C. International Symposium on Power Semiconductor Devices & ICs (ISPSD). (2019) 31-34.

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Feng, Gan, Jun Suda, Tsunenobu Kimoto, Space-modulated junction termination extension for ultrahigh-voltage pin diodes in 4H-SiC, J. IEEE transactions on electron devices. 59.2 (2011) 414-418.

D. Okamoto, H. Yano, K. Hirata, T. Hatayama, T. Fuyuki, Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide, J. IEEE Electron Device Letters. 31 (2010).

Dhar S, Feldman LC, Wang S, Isaacs-Smith T, Williams JR, Interface trap passivation for /(000̄̄) C-terminated 4H-SiC, J. Journal of Applied Physics. 98 (2005).

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 69-74

doi: 10.4028/p-q19NrM

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-26

Revised:
2026-01-29

Accepted:
2026-03-08

Online:
2026-05-19

2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Yuniarto Widjaja 1,a*, Valerii Nebesnyi 1, b, Oleksandr Maistriuk 1,c, Asen Asenov 1,2, d, Nikolas Xeni 2,e, Tapas Dutta 2,f, Djamel Bensouiah 2, g, Servin Rathi 3,h, Leo Laborie 3,i, Robert Young 3,j, Yunyi Qi 3,k and David T. Clark 3,1

1 Volta Semiconductor, Inc., Cupertino, CA, USA

2 Semiwise Ltd., Glasgow, UK

3 Clas-SiC Wafer Fab Ltd., Lochgelly, UK

a*ywidjaja@voltasemi.com, b vn@voltasemi.com, c om@voltasemi.com, dasen.asenov@semiwise.uk, enikolas.xeni@semiwise.uk, t  tapas.dutta@semiwise.uk, g  djamel.bensouiah@semiwise.uk, h  servin.rathi@clas-sic.com, ileo.laborie@clas-sic.com, j  robert.young@clas-sic.com, k  kelly.qi@clas-sic.com, 'david.clark@clas-sic.com 

Keywords: 3300 V , silicon carbide, low specific on-resistance, on-current improvement, p-well bias.

Abstract

We experimentally demonstrated a ~2x on-current enhancement in VDMOSFET fabricated in a standard 3300 V -rated 4H−SiC process. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A 5×103−104 ratio between the on-current gain and the p-well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC), have been increasingly utilized in high-voltage, high-power applications due to advantages in electrical and thermal properties over silicon. Low conduction losses is one of the requirements of power semiconductor applications and therefore there are many efforts to improve the on-current and specific on-resistance of SiC devices, for example through process improvements [1-3], cell topologies [4], and charge modulations [5]. Previously, we demonstrated a >2.5 x on-current improvement in 1200 V-rated 4HSiC based MOSFET through the application of p-well voltage [6]. 3300 V -rated devices have received significant interest for solid-state transformers, industrial and traction applications. In this work, we demonstrated a ~2x on-current enhancement resulting from p-well voltage biasing in 3300 V-rated 4H−SiC based VDMOSFET.

Fig. 1(a) illustrates a schematic cross-sectional view of our VDMOSFET device, which is fabricated in a standard 3.3kV4H−SiC process on 150 mm wafers. The details of the fabrication process are described in [7] and a breakdown voltage of 3950 V is achieved (Fig. 1(b)).

[picture]

Fig. 1. (a) Cross-sectional view of device structure, (b) Breakdown characteristic of a typical 3300 V device.

Fig. 1. (a) Cross-sectional view of device structure, (b) Breakdown characteristic of a typical 3300 V device.

Separate contacts are formed for the p-well and source regions, allowing for independent biasing of both regions (p-well contact is not shown in Fig. 1(a)). A positive bias is applied to the p-well region when the VDMOSFET is in the on-state and removed when it is in the off-state. In a conventional VDMOSFET, the p-well and source regions are shorted and typically connected to a common ground.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Fig. 2(a) shows the Id-Vg curves measured from a test structure having a JFET width of 15μ m for different Vp and drain voltage (Vd). The ratio of the drain current with Vp=2.2 V and Vp=0 V for a range of gate voltage ( Vg ) is shown in Fig. 2(b), demonstrating ~2x on-current when Vp=2.2 V is applied compared to conventional VDMOSFET (with Vp=0 V ). The ratio of the on-current as a function of applied Vp bias is also shown in Fig. 2(c), indicating that the current flow across the VDMOSFET can be controlled by both Vg and Vp. When the VDMOSFET is turned off, the positive Vp bias is removed and the off-state characteristics return to those with Vp=0V applied. In addition, the application of Vp bias has been shown to reduce both the variability of the threshold voltage and the time-dependent threshold voltage drift [8, 9].

[picture]

Fig. 2. (a) Id-Vg characteristics of VDMOSFET for Vd=1 V and 2 V with Vp=0 V (solid) and Vp=2.2 V (dashed), (b) Ratio of drain current with Vp=2.2 V and Vp=0 V applied, (c) Ratio of drain current at different applied Vp and Vp=0 V for Vd=2 V.

Fig. 2. (a) Id-Vg characteristics of VDMOSFET for V d = 1 V and 2 V with V p = 0 V (solid) and V p = 2.2 V (dashed), (b) Ratio of drain current with V p = 2.2 V and V p = 0 V applied, (c) Ratio of drain current at different applied Vp and V p = 0 V for V d = 2 V .

Kimoto and Watanabe have previously shown that the drift resistance accounts for ~80% of the on-resistance of 3300 V SiC power MOSFET [10]. The p-well current is measured to study whether the significant on-current gain can be attributed to the vertical BJT device. Fig. 3(a) provides the ratio of the on-current gain to the p -well current (i.e. the BJT gain). A high ratio of 5×103−104 is observed, demonstrating that the large current gain does not require a large p -well current. The improvement in the channel resistance is investigated by measuring the transconductance (gm). Fig. 3(b) shows a ~30% higher peak gm with Vp=2.2 V. The Id-Vg and gm show that threshold voltage (Vt) shift and gm contribute to the on-current gain.

[picture]

Fig. 3. (a) Ratio of current gain (the difference between drain current with Vp=2.2 V and 0 V ) and p well current for Vd=1 V and 2 V , (b) Transconductance (gm) for Vd=2 V with Vp=2.2 V and 0 V .

Fig. 3. (a) Ratio of current gain (the difference between drain current with V p = 2.2 V and 0 V ) and p well current for V d = 1 V and 2 V , (b) Transconductance ( g m ) for V d = 2 V with V p = 2.2 V and 0 V .

TCAD simulations are performed to further study the underlying mechanisms of the drain oncurrent gain. The TCAD simulations have been calibrated using the experimental results from the 1.2 kV4H−SiC process and adjusted to account for the differences between the 3.3 kV and 1.2 kV processes. Fig. 4 illustrates a comparison of the Id-Vg characteristics of the 3.3 kV device under Vp=0 V and Vp=2.2 V bias conditions. As shown in Fig. 4, TCAD simulations also show a ~2x oncurrent, consistent with the experimental results.

[picture]

Fig. 4. (a). TCAD simulation Id-Vg characteristics of VDMOSFET for Vd=1 V and 2 V with Vp=0 V (solid) and Vp=2.2 V (dashed), (b) TCAD optimization results showing drain current gain (left axis) and the ratio of current gain to p-well current (right axis).

Fig. 4. (a). TCAD simulation Id-Vg characteristics of VDMOSFET for V d = 1 V and 2 V with V p = 0 V (solid) and V p = 2.2 V (dashed), (b) TCAD optimization results showing drain current gain (left axis) and the ratio of current gain to p-well current (right axis).

Fig. 5(a) illustrates a cross section of the energy band diagram along the source/ p -well/drift region junctions with Vp=0 V and Vp=2.2 V bias applied. Applying a positive Vp bias lowers the energy barrier between the source and the p-well regions, increasing current flow through the p-well region. A comparison of the current density plots shows that a higher current density is observed throughout the source junction region and is not limited to only the area near the surface channel when a positive bias is applied to the p-well. Electron flow in the region away from the surface area is not limited by the poor channel mobility of SiC , and as a result, a higher effective mobility, μ eff is obtained, as observed by the higher transconductance shown in Fig. 3(b). This is similar to the effect of onresistance improvement through the formation of current spreading layer (CSL) or deep JFET layer shown by Jang et al. [11] and Kim et al. [12], respectively.

[picture]

Fig. 5. TCAD simulation results showing (a) the energy band diagram across the region indicated by the dashed line, and total current density in the VDMOSFET region enclosed by the box for (b) Vp=0 V and (c) Vp=2.2 V.

Fig. 5. TCAD simulation results showing (a) the energy band diagram across the region indicated by the dashed line, and total current density in the VDMOSFET region enclosed by the box for (b) V p = 0 V and (c) V p = 2.2 V .

TCAD simulations are also used to further optimize the 3.3 kV device. As shown in Fig. 4(b), a higher on-current can be achieved through further device structure optimizations, while maintaining 5×103−104 ratio between on-current gain and the p-well current. This is accomplished by further increasing the conduction area to encompass a larger portion of the source area.

The specific on-resistance is shown in Fig. 6 alongside selected 3.3 kV results [13-15] and our previous 1.2 kV results [6], demonstrating that the p-well biasing results approach the SiC limit [16].

[picture]

Fig. 6. Specific on-resistance vs. breakdown voltage, showing p-well boosting approaches the SiC limit.

Fig. 6. Specific on-resistance vs. breakdown voltage, showing p-well boosting approaches the SiC limit.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

A ~2x improvement in the on-current of 3300 V -rated 4H−SiC VDMOSFETs has been demonstrated. The current gain is achieved through the application of a positive bias to the p -well region. The application of the p -well bias does not result in significant increase in the p -well current, where a ratio of 5×103−104 between the on-current gain and the p-well current is observed. The specific on-resistance demonstrates that the p -well biasing yield results approaching the SiC limit. TCAD simulations are performed to understand the current boosting mechanism and to investigate further optimizations.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

The authors would like to thank Ian Widjaja for contributions to TCAD simulations, as well as Christopher Norwood, Kuk-Hwan Kim, and Valentin Abramzon for insightful discussions.

Author Contribution

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

YW: conceptualization (equal), writing - original draft (lead), formal analysis (lead), writing - review and editing (equal).

VN: conceptualization (equal), formal analysis, writing - review and editing (equal).
OM: formal analysis, writing - review and editing (equal).
AA: conceptualization (equal), formal analysis, writing - review and editing (equal).
NX: data curation (equal), investigation - simulation (equal), writing - review and editing (equal).
TD: data curation (equal), investigation - simulation (equal), writing - review and editing (equal).
DB: data curation (equal), investigation - simulation (equal), writing - review and editing (equal).

SR: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).
LL: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).

RY: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).
YQ: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).

DTC: data curation (equal), formal analysis, investigation - device layout, process, test (equal), writing - review and editing (equal).

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Uchida, Kosuke, et al. "The optimised design and characterization of 1200 V/2.0 mΩ cm24H SiC V-groove trench MOSFETs." 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2015.

Kim, Dongyoung, et al. "The effect of deep JFET and P-well implant of MOSFETs." IEEE Journal of the Electron Devices Society 10 (2022): 989-995.

Kim, Jeff Joohyung, et al. "Investigation into Relationship of the Switching Performance and Short-Circuit Withstand Time on 1.2 kV 4H-SiC Power MOSFETs." 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2024.

Han, Kijeong, and B. J. Baliga. "Comparison of four cell topologies for accumulationand inversion-channel MOSFETs: Analysis and experimental results." IEEE Transactions on Electron Devices 66.5 (2019): 2321-2326.

Masuda, Takeyoshi, et al. "Challenges in Extremely Low Specific On-Resistance with SiC SJVMOSFETs." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Widjaja, Yuniarto, et al. "1200 V 4H-SiC VDMOSFET Having> 2.5x On-Current Improvement." International Conference on Silicon Carbide and Related Materials (2024): 530531.

S. Rathi, D. Macdonald, A. Murphy, M. Bell, R. Young, and D. Clark, "Influence of Channel Length and Gate Oxide Thickness Variations in 3300 V 4H-SiC VDMOSFET." International Conference on Silicon Carbide and Related Materials (2023).

Franco, Jacopo, et al. "Reduction of the BTI time-dependent variability in nanoscaled MOSFETs by body bias." 2013 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2013.

Waltl, Michael, et al. "Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors." Microelectronics Reliability 168 (2025): 115693.

Kimoto, Tsunenobu, and Heiji Watanabe. "Defect engineering in SiC technology for highvoltage power devices." Applied Physics Express 13.12 (2020): 120101.

Jang, Seung Yup, et al. "Improved on-state resistance with reliable reverse characteristics in 1.2 kV 4H-SiC MOSFET by selective nitrogen implantation assisted current spreading layer." Japanese Journal of Applied Physics 59.4 (2020): 046501.

Kim, Dongyoung, et al. "The effect of deep JFET and P-well implant of MOSFETs." IEEE Journal of the Electron Devices Society 10 (2022): 989-995.

Palmour, John W., et al. "Silicon carbide power MOSFETs: Breakthrough performance from 900 V up to 15 kV ." 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014.

Zhang, Luyang, et al. "Comparison of a 3.3 kV SiC Hybrid-Channel Trench MOSFET and a Planar MOSFET." 2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe). IEEE, 2022.

Chen, Ximing, et al. "Different JFET designs on conduction and short-circuit capability for 3.3 kV planar-gate silicon carbide MOSFETs." IEEE Journal of the Electron Devices Society 8 (2020): 841-845.

Baliga, B. Jayant. "Fundamentals of Power Semiconductor Devices." Springer, Berlin (2008).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 75-83

doi: 10.4028/p-e0IRdP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-15

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-19

Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Haizhao Zhi 1,a*, Sirui Feng 1,b, Xiaoping Wang 1,c, Xinpeng Lin 1,d, Yitian Jiang 1,e, Haolin Hu 1,f and Yuxi Wan 1, g*

1 Shenzhen Pinghu Laboratory, No. 93, Xinxia Avenue, Pinghu Subdistrict, Longgang District Shenzhen, China

a  zhihaizhao@phlab.com.cn, b  fengsirui@phlab.com.cn, c  wangxiaoping@phlab.com.cn, dlinxinpeng@phlab.com.cn, ejiangyitian@phlab.com.cn, 'huhaolin@phlab.com.cn g  wanyuxi@phlab.com.cn

Keywords: SiC trench MOSFET, clamped PMOS, trench refill, single event burn-out.

Abstract

This study proposes a refilled PMOS SiC trench MOSFET (RPTMOS) design with integrated parasitic PMOS clamping transistors to mitigate single-event burnout (SEB) susceptibility. The configuration of the core epi-refill process to realize the proposed RPTMOS is also demonstrated. Through systematic TCAD simulations, we analyze the transient lattice temperature, electric field distribution, and current density dynamics under heavy-ion irradiation (LET =19.0MeV·cm2/mg, Drain DC Bias VD=500 V ). The optimized structure features a grounded parasitic PMOS clamp formed by the P-connect, P-bottom, and N-drift regions, which enables efficient hole extraction and suppresses electric field crowding at the gate oxide corner. Comparative simulations reveal that the proposed design reduces peak lattice temperatures and elevates the SEB withstand voltage by ~20%. Parametric studies further demonstrate that increasing the P-connect thickness ( 200\AA→400\AA ) significantly enhance radiation hardness, proves the pivotal contribution from the parasitic PMOS. The findings offering a viable pathway for radiation-hardened SiC power devices in aerospace and high-energy applications.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

SiC MOSFET are very attractive for irradiated power electronics applications[1]. One of the biggest threat to the SiC MOSFET operated under irradiation is the single-event-burnout (SEB) effect, which can cause permanent damage due to the incidence of high-energy particles. These particles generate electron and hole pairs along the incident path leading to local electrical field spike and serious thermal effect. Since the generated electrons could be drifted by the high drain bias, pumping out the holes in time become the critical reinforcement strategy to avoid SEB.

Many technologies have been developed to improve the anti-SEB capability. For instance, the N+N− junction within the deep P+ well of CoolSiC trench MOSFET to assist the hole extraction[2], adoption of semi-Superjunction[3], multi-buffer and multi-shield below p-well[4,5,6].

In this work, we proposed a refilled PMOS SiC trench MOSFET (RPTMOS), which protects the gate oxide[7] and help to pump out the irradiation-generated holes by the parasitic PMOS. The parasitic PMOSs are formed by a epi-refill process, which controls the flow rate of hydrogen chloride (HCl) gas during the trench re-fill process and grow a thin p -type region ( p -connect) on the side walls of trench. TCAD characterization reveals that the lateral thickness of the p-connect region should be maintained below 400\AA to achieve lower MOSFET on-resistance (Rds,on)[7]. We characterized the lattice temperature, electric field and current density etc. under heavy-ion strike with certain values of particle linear energy transfer (LET) and discovered that the parasitic PMOS plays a pivotal role during the SEB process.

Device Structure and Process

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Fabrication of the device follows our prior work [7], with key steps shown in Fig.1. Fig. 1 shows the main steps of realizing the RPTMOS.

As shown in Fig.1(a), from bottom to top, the epi-structure contains n+ substrate, n -buffer, n -epi (drift) layer, p-well layer, n+ source layer. The trench orientation in Fig.1(b), directed towards the reader, is aligned to the [11-20] crystal direction, with a deviation smaller than 0.2∘.

[picture]

Fig. 1. The fabrication process of the RPTMOS.

Fig. 1. The fabrication process of the RPTMOS.

The p-type epilayer is refilled in SiC trench, which can achieve a very thin layer ( <0.1μ m ) above the sidewalls of n-type trench[8] as shown in Fig.1(c), The addition of hydrogen chloride is to have a certain etching effect on the trench sidewall [9,10,11]. The final structure of the device is as shown in Fig.1(f) [7,11], the parasitic PMOS is labeled within the red rectangle.

SEB TCAD Simulation RESULT

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

TCAD simulation was carried out to investigate the RPTMOS's performance under high-energy particle irradiation. For trench-gate devices, the region adjacent to the gate oxide represents the most vulnerable area in trench-gate MOSFET[4]. The conditions depicted in Fig. 2 correspond to vertical heavy-ion irradiation at x=5.0μ m of the trench-gate device, where x=5.0μ m marks the boundary layer between the SiC P -connect region and the gate oxide. The standardized SEB irradiation parameters: B.DENSITY (electron-hole pair generation density) =1×1020 cm−3 and radius =0.05μ m. This yields a linear energy transfer (LET) value of 0.126pC/μm, which equates to 19.0MeV·cm2/mg [2]. Our study adopts this LET value ( 19.0MeV·cm2/mg ) for TCAD simulations of SEB. The SEB LET threshold for 1200 V SiC MOSFETs is approximately 10MeV·cm2/mg [12], thereby justifying the selection of 19.0MeV·cm2/mg here as a conservative yet representative value for SEB.

About the RPTMOS, during reverse blocking operation, the parasitic PMOS inherently clamps the electrical potential of the p -bottom region. Under reverse blocking conditions, the P-bottom, N-drift, and P -well regions collectively form an equivalent PMOS clamping transistor. With the polysilicon gate grounded, the elevated potential in the N-drift region beneath the P-well activates the PMOS clamp, with the p -connect region as a hole provider. The parasitic PMOS act as an accumulationmode PMOS[7].

[picture]

Fig. 2. The vertical distribution of the lattice temperature of the RPTMOS along x=4.99μ m under heavy-ion irradiation at x=5.0μ m at different transient time steps T1 - T7. The arrows point to the lattice temperature distribution within the RPTMOS.

Fig. 2. The vertical distribution of the lattice temperature of the RPTMOS along x = 4.99 μ m under heavy-ion irradiation at x = 5.0 μ m at different transient time steps T 1 - T 7 . The arrows point to the lattice temperature distribution within the RPTMOS.

The vertical axis of Lattice Temperature in Fig. 2 illustrates the transient lattice temperature distribution along the vertical y -axis at x=4.99μ m (corresponding to the central axis of the P -connect region that spans a lateral width of 200\AA ) across distinct time points ( T1−T7 ). Under drain bias of VD=500 V, the first temperature peak emerges at y=3.0μ m. The embedded subplots (left: magnified lattice temperature distribution near the gate oxide corner at T4=500ps; right: global lattice temperature distribution of the RPTMOS) reveal that this peak lattice temperature corresponds to the interface between the P -connect region and the P -bottom region in Fig.1(c). Between T4=500ps and T5=1 ns, the localized peak lattice temperature at this region exceeds 1500 K . Subsequently, in Fig.2, a secondary temperature peak emerges at y=11.0μ m, occurring between T4=500ps and T7=10 ns after heavy-ion irradiation. This peak corresponds to the temperature spike at the n+/n−junction between the N-drift region and the substrate. Many studies propose multilayer buffer structures to suppress this localized temperature rise[4,5,6].

[picture]

Fig. 3. The figure illustrates the current density distribution along x=4.99μ m of the RPTMOS under vertical heavy-ion irradiation at x=5.0μ m and drain voltage of VD=500 V at different transient time steps T1−T7.

Fig. 3. The figure illustrates the current density distribution along x = 4.99 μ m of the RPTMOS under vertical heavy-ion irradiation at x = 5.0 μ m and drain voltage of V D = 500 V at different transient time steps T 1 − T 7 .

Fig. 3 illustrates the current density distribution along the longitudinal tangent at x=4.99μ m for the trench-gate device under vertical heavy-ion irradiation at x=5.0μ m and a drain voltage of VD= 500 V . At T1=5ps, the hole current density reaches its maximum value near y=2.0μ m to 3.0μ m (marked by the white dotted box), predominantly discharged through the parasitic equivalent

PMOS clamping transistor. The inset subplot depicts the spatial hole current density distribution, demonstrating that the hole current constitutes the dominant component ( >2e+07 A/cm2 ) of the ioninduced current density at this stage.

[picture]

Fig. 4. The figure presents the electric field intensity distribution along x=4.99μ m of the RPTMOS under vertical heavy-ion irradiation at x=5.0μ m and drain voltage of VD=500 V at different transient time steps T1 - T7. The arrows indicates the evolution of local peak electric field intensity vs. each transient time steps T1−T7.

Fig. 4. The figure presents the electric field intensity distribution along x = 4.99 μ m of the RPTMOS under vertical heavy-ion irradiation at x = 5.0 μ m and drain voltage of V D = 500 V at different transient time steps T 1 - T 7 . The arrows indicates the evolution of local peak electric field intensity vs. each transient time steps T 1 − T 7 .

Fig. 4 presents the electric field intensity distribution along x=4.99μ m for the trench-gate device under vertical heavy-ion irradiation at x=5.0μ m and a drain voltage of VD=500 V. The arrows annotates the shift of the position of peak electric field intensity at different transient time steps T1 T7 within the RPTMOS at following heavy-ion irradiation. At T3=100ps, the peak electric field ( 3.3MV/cm ) localizes at y=3.0μ m (near the trench-gate bottom corner), accompanied by a mild electric field crowding ( ~0.6MV/cm) near y=11μ m(n+/n−junction).

The peak electric field at y=3.0μ m arises from the requirement for charge neutrality within the semiconductor. Specifically, heavy-ion irradiation induces localized lattice temperature elevation and generates a high density of electron-hole pairs. In the absence of the equivalent PMOS clamping transistor, holes accumulate at the gate oxide corner due to the lack of an efficient extraction path. Concurrently, electrons are retained to satisfy charge neutrality, leading to increased plasma density. This disrupts the space-charge region's shielding effect, resulting in electric field peaking at y=3.0μ m (the trench-gate bottom corner). Under these conditions, the combined effects of reduced critical breakdown field strength of the gate oxide at elevated temperatures and the high applied drain voltage render the gate oxide corner susceptible to dielectric breakdown due to severe electric field crowding.

In the RPTMOS proposed herein, the grounded equivalent PMOS clamping transistor integrated into the trench sidewall enables rapid extraction of excess holes. Furthermore, by reducing the electron concentration at the conduction band edge to maintain charge neutrality, part of the spacecharge shielding of the p -doping region is preserved, mitigating field crowding and suppressing rapid junction temperature escalation.

Simulation RESULT Discussions

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A comparative analysis of the transient distributions of lattice temperature, current density, and electric field along x=4.99μ m under vertical 19.0MeV·cm2/mg heavy-ion irradiation in Fig.24(vertical radiation incidence at x=5.0μ m, VD=500 V ) reveals the following:

At T1−T3, the y=3.0μ m vicinity first exhibits a current density peak of 2.3×107 A/cm2 at T1= 5 ps . This peak spans a broad y-axis range ( y=1.0−3.0μ m ), coinciding with the equivalent PMOS clamping transistor and P -well regions. By T2=20ps, the current density peak declines to
1.1×107 A/cm2. At T3=100ps, the current density peak further diminishes to ~4×106 A/cm2, representing an approximate order-of-magnitude reduction compared to T1. Concurrent observation of the lattice temperature profile shows that the peak temperature rises from ~500 K at T1 to ~650 K at T2 and further to 1260 K at T3. This decline in current density between T1 and T3 can be attributed to the increasing localized temperature near y=3.0μ m, which elevates the resistance of the equivalent PMOS clamping transistor, thereby suppressing hole extraction efficiency. The T3 time point coincides with the transient electric field intensity curve reaching its extreme at y=3.0μ m. This result arises from the high transient hole density coupled with inefficient extraction of the PMOS, which weakens the space-charge region's protective effect on the gate oxide corner. Beyond T3, the peak temperature near y=3.0μ m gradually decreases, primarily due to external thermal dissipation (simulated with a thermal conductivity coefficient α=1 W/cm·K ). As the heavy-ion irradiation is a single-event process with a Gaussian temporal charge generation profile (width Tc=2ps ), the massive hole extraction process concludes after T3. Consequently, the space-charge shielding effect is gradually restored, leading to reduced electric field peaking at y=3.0μ m and a further temperature decline to ~970 K by T7=10 ns.

[picture]

Fig. 5. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) of the RPTMOS(labeled as refill MOSFET) throughout the irradiation process under different heavy-ion incidence conditions and structural parameters.

Fig. 5. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) of the RPTMOS(labeled as refill MOSFET) throughout the irradiation process under different heavy-ion incidence conditions and structural parameters.

Furthermore, we compare the temporal evolution of the SiC peak temperature throughout the heavy-ion irradiation process in Fig.5. The black inverted-triangle curve in Fig. 5 corresponds to the aforementioned scenario (vertical 19.0MeV·cm2/mg ion strike at x =5.0μ m, incident at the gate oxide/ SiC interface, VD=500 V ), where the device peak temperature reaches 1770 K . As analyzed earlier, the limited lateral width ( 200\AA along the x -axis) of the equivalent PMOS clamping transistor introduces current-limiting effects under elevated lattice temperatures, reducing hole extraction efficiency and weakening field shielding. Therefore, the blue diamond-shaped curve in Fig. 5 corresponds to a P-connect x-axis thickness increased from 200\AA to 400\AA under VD=500 V, yielding a peak temperature of 1616 K-significantly lower than the 200\AA case 1770 K . This demonstrates that increasing the P -connect thickness enhances the device's radiation hardness, on the other hand, the thicker P-connect thickness suppresses the Rds,on, which is a trade-off. The black upright-triangle curve represents identical ion strike parameters compared to the black invertedtriangle curve with VD reduced to 400 V , resulting in a lower peak temperature 1336 K .

In Fig.5, the red square-shaped curve represents a scenario where the ion strike is offset by 100 nm from the gate oxide/semiconductor interface x=5.0μ m to x=4.9μ m, leads the peak temperature decreases to 824.6 K . This results validates that the gate oxide/semiconductor interface is the most SEB-sensitive region of SiC Trench MOSFET[2]. Under this condition, the RPTMOS(labeled as refill MOSFET in Fig.5) attains its peak temperature around T5=1 ns. The rightside inset subplot in Fig. 5 depicts the lattice temperature distribution of the RPTMOS at T5=1 ns.

Apart from the peak temperature at the n+/n−junction between the substrate and N -drift region, two additional hot-spots localize at the source and drain terminals of the parasitic PMOS clamping transistor is observed(pointed by arrow). It can be inferred that even for an ion strike's incident position offset to x=4.9μ m, the parasitic PMOS clamping transistor retains significant charge extraction capability for ion-generated electron-hole pairs compared to the main p−n junction formed by p -well and n -drift region in RPTMOS.

[picture]

Fig. 6. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) throughout the heavy-ion irradiation process between the RPTMOS(labeled as refill MOSFET) with baseline (BSL) SiC trench MOSFET(lacking the equivalent PMOS clamping transistor). The proposed RPTMOS design with P-connect thickness along the x-axis increased from 200\AA to 400\AA.

Fig. 6. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) throughout the heavy-ion irradiation process between the RPTMOS(labeled as refill MOSFET) with baseline (BSL) SiC trench MOSFET(lacking the equivalent PMOS clamping transistor). The proposed RPTMOS design with P-connect thickness along the x-axis increased from 200 \AA to 400 \AA .

Finally, we compare the temporal evolution of the SiC peak temperature throughout the heavy-ion irradiation process between the proposed RPTMOS(labeled as refill MOSFET in Fig.6) design with a baseline (BSL), lacking the equivalent PMOS clamping transistor, SiC trench MOSFET(labeled as BSL MOSFET in Fig.6) in Fig.6. Both devices share identical critical dimensions and doping profiles. In Fig.6, the brown cross-shaped curve represents the BSL MOSFET under vertical 19.0MeV·cm2/mg irradiation ( x=5.0μ m, VD=500 V ), exhibiting a peak temperature exceeding 2000 K , higher than the RPTMOS. Furthermore, the brown asterisk-shaped curve corresponds to the BSL MOSFET under Vd=400 V, yielding a peak temperature of 1548 K , still higher than the RPTMOS under identical conditions. For the RPTMOS, the SEB withstand voltage is improved by approximately 20%.

New SIC MOSFET Structure and Experimental Results

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Fig. 7 propose a novel SiC trench MOSFET structure[13]. Fig.7(b) provides a top-down perspective of the proposed SiC trench MOSFET structure corresponds to the B-B' horizontal crosssection of Fig.7(a) and 7(c). Regions with identical colors or patterns in Fig.7(a), 7(b), and 7(c) represent the same material compositions within the device.

[picture]

Fig. 7. This figure ilustrates a novel SiC trench MOSFET structure.

Fig. 7. This figure ilustrates a novel SiC trench MOSFET structure.

Compared to the previously described RPTMOS[7], an additional process step is introduced in the fabrication process shown in Fig.1(c): periodic selective regions along the trench direction are defined. As shown near the G-G' location in Fig.7(b)(top-down perspective of the new SiC MOSFET), an isotropic SiC etching process is applied to remove the thin p -connect region in this area, thereby forming a low on-resistance zone in the new SiC MOSFET.

[picture]

Fig. 8. SEM figure of the core epi-refill process from Fig.1(b) to Fig.1(c).

Fig. 8. SEM figure of the core epi-refill process from Fig.1(b) to Fig.1(c).

Moreover, we have successfully demonstrated the core epi-refill process from the structure in Fig. 1(b) to that in Fig. 1(c) using an 8-inch SiC wafer in our in-house 8-inch pilot line, as illustrated in Fig. 8. It is shown that a thin p-channel for the accumulation-mode p-MOS can be effectively fabricated through p-type epi-refill. By adjusting the HCl flow rate (optimum condition HCl1SiH4~ 20), we achieved the required process conditions to realize the configuration demanded by RPTMOS device. The trench aspect ratio was set at 13.0μ m:1.6μ m, with the trench direction (into the paper) aligned along the [11-20] crystal orientation, maintaining a misalignment of less than 0.2∘. The configuration of the n+ source contact and the p -well in the proposed RPTMOS is also depicted in Fig. 8. Additionally, the subfigure in Fig. 8 confirms that the epi-refill process enables a relatively uniform distribution across the wafer.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

This work demonstrates that integrating a parasitic PMOS clamping transistor into RPTMOS effectively mitigates SEB vulnerability by enhancing hole extraction and reducing field crowding. The parasitic PMOS clamp rapidly discharges ion-generated holes, preserving space-charge shielding and limiting peak electric fields at the gate oxide corner. Peak lattice temperatures near critical junctions (e.g., P-connect/P-bottom interface) are reduced by >230 K in the RPTMOS under 500 V drain DC bias, achieves a 20% higher SEB voltage than baseline MOSFET, highlighting its superiority in radiation-hardened applications. Furthermore, increasing the P-connect thickness ( 400 Å) lowers peak temperatures by around 10%, validating design flexibility and the pivotal contribution from the parasitic PMOS. Furthermore, we propose a novel SiC trench MOSFET structure with periodical epi-refilled p-connect structure, to better leverage the design advantages of RPTMOS. In addition, we successfully demonstrated the configuration of the core epi-refill process to realize the proposed RPTMOS.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Palmour, John W., et al. "Silicon carbide power MOSFETs: Breakthrough performance from 900 V up to 15 kV ." 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014, doi: 10.1109/ISPSD.2014.6855980.

Chen, De-Xin, et al. "TCAD Analysis of Single-Event Burnout Hardness for an Improved CoolSiC Trench MOSFET." IEEE Transactions on Electron Devices (2024), doi: 10.1109/TED.2024.3418727.

McPherson, Joseph A., et al. "Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022, doi: .

Wang, Ying, et al. "A comparative study of single-event-burnout for 4H-SiC UMOSFET." IEEE Journal of the Electron Devices Society 10 (2022): 373-378, doi: 10.1109/JEDS.2022.3158810.

Yang, Rui, et al. "An improved single-event effect performance SiC MOSFET of hole extraction pillar combined with multilayer P -shield structure." IEEE Transactions on Electron Devices 71.2 (2024): 1018-1023, doi: 10.1109/TED.2023.3346372.

Lu, Jiang, et al. "Impact of varied buffer layer designs on single-event response of power MOSFETs." IEEE Transactions on Electron Devices 67.9 (2020): 3698-3704, doi: 10.1109/TED.2020.3008398.

Zhi, Haizhao, et al. "A New Structure and Process Method for SiC Trench MOSFET." 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET). IEEE, 2024, doi: 10.1109/ISSET62871.2024.10779737.

R. Kosugi, S. Ji, K. Mochizuki, H. Kouketsu, Y. Kawada, H. Fujisawa, K. Kojima, Y. Yonezawa, and H. Okumura, "Strong impact of slight trench direction misalignment from [1120] on deep trench filling epitaxy for SiC super-junction devices" Jpn. J. Appl. Phys. 56, p. 04CR05, 2017, doi: 10.7567/JJAP.56.04CR05.

Ji, S., Kojima, K., Kosugi, R., Saito, S., Sakuma, Y., Tanaka, Y., ... & Okumura, H. (2015). "Influence of growth pressure on filling 4H-SiC trenches by CVD method." Japanese Journal of Applied Physics, 55(1S), 01AC04, doi:10.7567/JJAP.55.01AC04.

Tsunenobu Kimoto, James A. Cooper, "Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications", John Wiley & Sons, 2014.

H. Zhi, W. Zeng, Y. Wan, H. Hu, X. Wang. "A silicon carbide transistor, its manufacturing method and electronic device," C.N. Patent No. CN118352396B, April. 30, 2024.

Martinella, Corinna. "Single-event radiation effects in silicon carbide power MOSFETs." JYU dissertations (2021).

H. Zhi, X. Wan. "Silicon carbide device, manufacturing method of silicon carbide device and electronic device," C.N. Patent No. CN119767744A, April. 4, 2025.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 85-92

doi: 10.4028/p-uvfY1Y

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-18

Accepted:
2026-03-16

Online:
2026-05-19

Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

Kailun Zhong 1,a*, Vamsi Mulpuri 1, b, Vishank Talesara 1,c, Arash Salemi 1, d, Sumit Jadav 1,e and Siddarth Sundaresan 1,f

1 Navitas Semiconductor, 3520 Challenger Street, Torrance, CA 90503, USA

a* kailun.zhong@navitassemi.com, b  vamsi.mulpuri@navitassemi.com, c  vishank.talesare@navitassemi.com, darash.salemi@navitassemi.com, e  sumit.jadav@navitassemi.com, f  siddarth.sundaresan@navitassemi.com

Keywords: SiC MOSFET, on-resistance, avalanche, short-circuit, robustness, automotive, static characteristics.

Abstract

A comparative study of state-of-the-art commercial 1200 V trench-gate, planar-gate, and trench-assisted planar Silicon Carbide (SiC) MOSFETs is presented. The experimental study mainly focuses on disclosing the static and robustness characteristics of distinct SiC technologies targeting automotive applications under room and high temperatures. The benchmark study of static characteristics covers specific on-resistance ( RON,SP ), gate leakage ( IGSS ), drain leakage ( IDSS ), breakdown voltage ( BVDSS  ), and drain-induced barrier lowering (DIBL) effects. The avalanche robustness is investigated by the unclamping inductive switching (UIS) setup under 25∘C and 175 ∘C while the single-pulse and repetitive short-circuit capability is evaluated under hard switching fault (HSF) under 25∘C.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

Silicon carbide (SiC) power MOSFETs are promising switches for high-voltage, high-power, high-frequency, and high-temperature applications to replace legacy Silicon counterparts in existing applications, owing to wide bandgap, high breakdown electric field, and excellent thermal conductivity [1]. The adoption of 1200 V SiC MOSFETs into electric vehicles (EV) is increasingly popular because the superior efficiency, high power density, high-temperature operating capability, and faster switching speed contribute to longer driving range, shorter charging time, and more compact system design.

For automotive applications, the most important parameters of SiC power devices are lower onresistance to minimize the conduction losses, faster switching speeds to decrease the switching losses, high breakdown voltage to handle the high-voltage architecture, and wide operating temperature range to withstand harsh engine compartment conditions, contributing to the improved efficiency. In addition, the SiC power MOSFETs used for automotive applications can experience high voltage spikes and potential short circuits during motor control and power conversion, and their ability to withstand these events directly impacts the reliability and safety of the system, especially in demanding situations like rapid acceleration or sudden braking where large current surges can occur. The SiC MOSFETs with poor avalanche or short-circuit robustness could fail permanently, leading to system malfunction or even damage to other components.

Multiple manufacturers have released their latest generation of 1200 V silicon carbide (SiC) MOSFETs, which are qualified to AEC-Q101 standards for demanding automotive applications. These components are specifically designed to meet the requirements of high-power systems such as on-board chargers (OBCs), traction inverters, and e-compressor inverters [2]. These commercial 1200 V SiC MOSFETs adopt planar-gate, trench-gate, and trench-assisted planar technologies with their unique benefits and weaknesses as discussed in [3] and [4]. There are very limited studies making comprehensive benchmark between the state-of-the-art 1200 V SiC MOSFETs oriented towards automotive applications. However, the comparative study of various 1200 V SiC technologies
are valuable for the researchers and engineers in the field when understanding the device performance and choosing the most suitable SiC power devices for their applications.

In this work, the static and robust characteristics of commercial 1200 V trench-gate, planar-gate, and trench-assisted planar SiC MOSFETs from five mainstream manufacturers are characterized with side-by-side comparison.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

Table 1 summarizes the key information for the devices under test (DUTs). We selected the latest generation trench-gate SiC MOSFETs from two manufacturers: Manufacturer A (asymmetric trench technology) and Manufacturer B (double trench technology). We also included the latest generation trench-assisted planar SiC MOSFETs from Navitas, and the latest generation planar SiC MOSFETs from two other distinct manufacturers, D and E . The blocking voltage rating is 1200 V for all DUTs.

The current rating is extracted from the datasheets and used for on-resistance ( RDS,ON ) test. To make fair comparison, the active areas of DUTs are extracted by optical measurement after decapsulation. Trench-gate silicon carbide (SiC) MOSFETs exhibit a high static threshold voltage ( VGS,TH ) of 4.2−4.3 V at room temperature, while planar-gate SiC MOSFETs have a lower VTH of 2.62.7 V . This difference is due to the different crystal faces used: trench-gate devices are built on the aface, which has a lower interface trap density, leading to higher channel mobility and a larger VGS,TH [5]. Owing to the benefits of high VGS,TH, the trench-gate SiC MOSFETs can be driven using 0 V gate turn-off voltage ( VGS,OFF ) while planar-gate SiC MOSFETs recommend a negative VGS,OFF to avoid false turn-on. The trench-gate technologies show a higher temperature coefficient.

Table 1 also shows that trench-assisted planar technology offers several advantages over traditional planar technology, including lower RON,SP,QGD,QGD×RON,SP. While trench-gate technology offers a lower Ron,Sp, the trench-assisted planar technology delivers a superior FOM (Figure of Merit) considering both BVDSS and RON,SP(BVDSS2/RON,SP). Its performance surpasses that of planar-gate technology and is slightly inferior to trench-gate technology. The QGD and QGD×RON,SP

Table 1. Key information of devices under test from different manufacturers.

Manufacturer | A | B | Navitas | D | E
Technology | Asymmetric Trench | Double Trench | Trench-assisted Planar | Planar | Planar
Generation | Gen 2 | Gen 4 | Gen 4 | Gen 3 | Gen 4
Voltage Rating (V) | 1200 | 1200 | 1200 | 1200 | 1200
VGS,th (V) * | 4.3 | 4.2 | 2.6 | 2.7 | 2.6
BVDSS (V) at VGS = 0V * | 1486 | 1550 | 1696 | 1532 | 1609
Current Rating (A) | 56.7 | 42 | 70 | 74 | 84.3
RDS,ON (mΩ) at 25°C | 12.2 | 18 | 12.5 | 14 | 13
RON,SP (mΩ·cm²) at 25°C | 1.9 | 2.4 | 2.6 | 3.3 | 3
RDS,ON (mΩ) at 175°C | 28.9 | 43.1 | 25 | 29 | 23
Temperature coefficient | 2.15 | 2.40 | 2.07 | 2.11 | 1.94
BVDSS²/ RON,SP | 1.16E+06 | 1.00E+06 | 1.11E+06 | 7.11E+05 | 8.63E+05
QGD (nC) | 34 | 52 | 82 | 98 | 102
QGD x RON,SP (nC·mΩ·cm²) | 64.6 | 124.8 | 213.2 | 323.4 | 306
VGS,ON / VGS,OFF (V) | +18/0 | +18/0 | +18/-5 | +18/-3 | +15/-4

[picture]

Fig. 1. (a) IGSS−VGS curves under VDS=0 V, TC=175∘C, (b) IGSS at VGS=25 V with TC from 25∘C to 175∘C. (c) IDSS−VDS curves under VGS=0 V, TC=175∘C, (b) breakdown voltage, BVDSS, is defined at IDSS=100μ A and extracted from IDSS−VDS curves at TC from 25∘C to 175∘C.

Fig. 1. (a) I G S S − V G S curves under V D S = 0 V , T C = 175 ∘ C , (b) I G S S at V G S = 25 V with T C from 25 ∘ C to 175 ∘ C . (c) I D S S − V D S curves under V G S = 0 V , T C = 175 ∘ C , (b) breakdown voltage, B V D S S , is defined at I D S S = 100 μ A and extracted from I D S S − V D S curves at T C from 25 ∘ C to 175 ∘ C .

of planar-gate technology is obviously inferior to trench-gate technology, while that of trench-assisted planar-gate technology is better than pure planar-gate devices.

Gate leakage ( IGSS  ) and drain leakage ( IDSS  ) are critical parameters for device reliability. As depicted in Fig. 1, the device from Manufacturer B demonstrated a significantly higher IGSS at elevated temperatures compared to the other manufacturers. The device from Manufacturer E presented a high IGSS at VGS=25 V and TC=175∘C, which is attributed to utilizing a thinner gate oxide [6] and corresponds to a lower VGS,ON of 15 V in Table I. Furthermore, Manufacturer B also exhibited higher IDSS at low drain-source voltages, and a noticeable reduction in breakdown voltage (BV DSS) with increasing temperature. In contrast, the device from Navitas showed a robust BVDSS greater than 1700 V , indicating excellent immunity to high-voltage spikes.

The drain-induced barrier lowering (DIBL) effect, which influences the threshold voltage (V GS,TH), was also analyzed. The DIBL coefficient ( ΔVTH_dibl) was defined as the change in VGS,th as the drain-source voltage ( VDS ) increased from 3 V to 1200 V . As illustrated in Fig. 2, Manufacturer A's trench-gate device, despite having the highest initial VGS,TH, exhibited the largest reduction in VGS,TH across the tested voltage range. This figure also demonstrates that the other manufacturers show better control over threshold voltage stability at different voltages and temperatures.

The avalanche capability of the device under test (DUT) was characterized by using an unclamping inductive switching (UIS) setup in [7]. As shown in Fig. 3, a 1.0 mH inductor was utilized, and the inductor current was increased incrementally by approximately 1 A per step until either destructive or parametric failure was observed. The maximum current achieved just before failure was documented as the single-pulse avalanche current, designated as Ids,pk.

[picture]

Fig. 2. (a) Threshold voltage measured under different VDS,VTH_Dibl, at IDS=2.5 mA at TC=25∘C. (b) ΔVTH_DIBL  at IDS=2.5 mA with VDS from 3 V to 1200 V under TC=25∘C,125∘C,150∘C,175∘C.

Fig. 2. (a) Threshold voltage measured under different V D S , V T H _ D i b l , at I D S = 2.5 m A at T C = 25 ∘ C . (b) Δ V TH_DIBL at I D S = 2.5 m A with V D S from 3 V to 1200 V under T C = 25 ∘ C , 125 ∘ C , 150 ∘ C , 175 ∘ C .

Fig. 4 presents the normalized avalanche energy density ( EAS/ Active Area) and the normalized avalanche current density ( Ids,pk/ Active Area) for all DUTs at a junction temperature of 175∘C. The data indicates that the planar-gate and trench-assisted planar devices exhibited a superior energy handling capability per unit area compared to the trench-based devices, suggesting a more effective structural design for dissipating avalanche energy. This trend of greater robustness in planar devices is further supported by the data in Fig. 5, which illustrates the percentage change in these normalized parameters from 25∘C to 175∘C. The planar-gate and trench-assisted planar devices demonstrated a smaller reduction in avalanche energy and current density at elevated temperatures compared to the trench-gate devices. Notably, Manufacturer B, a double-trench MOSFET, showed the poorest avalanche performance among all tested technologies, suggesting a potential weakness in shielding at the bottom or corner of the gate trench.

[picture]

Fig. 3. UIS test circuit schematic [5].

Fig. 3. UIS test circuit schematic [5].

[picture]

Fig. 4. (a) normalized avalanche energy density ( EAS/ Active Area); (b) normalized avalanche current density ( Ids,pk/ Active Area).

Fig. 4. (a) normalized avalanche energy density ( E A S / Active Area); (b) normalized avalanche current density ( I d s , p k / Active Area).

[picture]

Fig. 5. Percentage change in normalized avalanche energy density and normalized avalanche current density from 25∘C to 175∘C.

Fig. 5. Percentage change in normalized avalanche energy density and normalized avalanche current density from 25 ∘ C to 175 ∘ C .

[picture]

Fig. 6. (a) Gate leakage characteristics of 1200 V SiC MOSFET from Manufacturer B tested at fresh status and after UIS fail at 25∘C with D-S short. (b) OBIRCH analysis of the decapsulated sample by applying 1 V/59μ A at gate with drain/source short to ground. (c) Zoom-in view of failure point beside gate pad.

Fig. 6. (a) Gate leakage characteristics of 1200 V SiC MOSFET from Manufacturer B tested at fresh status and after UIS fail at 25 ∘ C with D-S short. (b) OBIRCH analysis of the decapsulated sample by applying 1 V / 59 μ A at gate with drain/source short to ground. (c) Zoom-in view of failure point beside gate pad.

The parametric failure evidence of the device from Manufacturer B is explored from gate leakage characteristics as shown in Fig. 6(a). After UIS fail, IGSS  at VGS=−5 V and +18 V is 106 and 109 times higher than the values in the fresh status, respectively. The sample is further decapsulated without detecting destructive failure points. The optical beam induced resistance change (OBIRCH) analysis is conducted on the decapsulated die to find out the soft failure points located beside the gate pad, as shown in Fig 6 (b) and (c).

Single-pulse and repetitive short-circuit tests were conducted to evaluate the devices' fault tolerance. The single-pulse short-circuit test was used to quantify three critical parameters: the shortcircuit withstanding time (SCWT), the peak short-circuit current density ( Ids,pk ), and the short-circuit
energy density (ESC). As illustrated in Fig. 7, the device from Manufacturer B demonstrated the lowest Ids, highest SCWT, lowest normalized Ids,pk and highest normalized ESC. However, the other devices exhibited a much tighter range of SCWT, from 1.7 to 2.2μ s which are in acceptable range for the automotive applications.

A comparison of the UIS and SCWT results (Fig. 4 to 7) reveals a notable trade-off in Manufacturer B's design. The device's poor performance in the UIS test suggests susceptibility to gate oxide failure caused by electric field concentration at the trench corners. However, this structure appears to excel at thermal management and current limiting, resulting in a superior SCWT. This dichotomy highlights a fundamental design compromise in power semiconductors: optimizing for one type of fault tolerance often comes at the expense of another. Manufacturer B's design appears to have prioritized short-circuit robustness over avalanche capability.

[picture]

Fig. 7. (a) IDS waveforms during the single-pulse short-circuit test under VDS=800 V using VGS,ON/VGS,OFF and RG-total  shown in Table I. Comparison between five different manufacturers in terms of (b) short-circuit withstanding time (SCWT), (c) peak short-circuit current density ( Ids,pk/ active area) and short-circuit energy density ( ESC/ active area).

Fig. 7. (a) I D S waveforms during the single-pulse short-circuit test under V D S = 800 V using V G S , O N / V G S , O F F and R G -total shown in Table I. Comparison between five different manufacturers in terms of (b) short-circuit withstanding time (SCWT), (c) peak short-circuit current density ( I d s , p k / active area) and short-circuit energy density ( E S C / active area).

Furthermore, the repetitive short-circuit capability is investigated using a fixed VIN =800 V and a periodic gate driving scheme as shown in Fig. 8. The 1.4μ s gate driving pulse and 700 short-circuit shots are used by referring to literature [8]. The 20-second intervals are used to cool down DUTs and avoid self-heating effects during periodic short circuit tests. The intelligent LabVIEW control system can automatically capture IDS,VDS,VGS waveforms during every short-circuit shot. In addition, the IGSS and BVDSS  are monitored at 25∘C after every 100 short-circuit events to detect parametric failures.

The results, shown in Fig. 9, indicated that most devices, except for Manufacturer D, showed robust performance with no significant degradation in gate leakage or breakdown voltage. The device from Manufacturer D showed a marked increase in gate leakage and lost its blocking capability after the repetitive stress test, highlighting a potential reliability concern.

[picture]

Fig. 8. (a) Schematic of hard switching short-circuit testing setup with LabVIEW control system. Control schematic for (b) single-pulse and (c) repetitive short-circuit test.

Fig. 8. (a) Schematic of hard switching short-circuit testing setup with LabVIEW control system. Control schematic for (b) single-pulse and (c) repetitive short-circuit test.

[picture]

Fig. 9. (a) Ids,pk/ Active Area and (b) ESC/ Active Area, (c) IGSS under VGS=25 V, VDS=0 V at 25 ∘C, (d) percentage shift of BVDSS  at 25∘C after 1 to 700 repetitive short-circuit cycles under VDS= 800 V , gate driving pulse width of 1.4μ s.

Fig. 9. (a) I d s , p k / Active Area and (b) E S C / Active Area, (c) I G S S under V G S = 25 V , V D S = 0 V at 25 ∘ C , (d) percentage shift of B V DSS at 25 ∘ C after 1 to 700 repetitive short-circuit cycles under V D S = 800 V , gate driving pulse width of 1.4 μ s .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

This benchmark study comprehensively compares the static and robustness characteristics of five state-of-the-art commercial 1200 V SiC MOSFETs. The findings reveal a variety of performance trade-offs among different SiC technologies. Although trench-gate devices offer lower on-resistance at room temperature, planar-gate and trench-assisted planar devices demonstrate superior performance at higher temperatures and greater thermal robustness under avalanche conditions. Short-circuit tests also revealed significant differences in fault tolerance. This underscores the importance of thorough characterization beyond standard datasheet parameters, especially for highreliability automotive applications. The study confirms that while SiC technology is mature, significant variation still exists in the reliability and performance of commercially available devices.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

X. She, et al., "Review of Silicon Carbide Power Devices and Their Applications," in IEEE Trans. Ind. Electron., vol. 64, no. 10, pp. 8193-8205, Oct. 2017, doi: 10.1109/TIE.2017.2652401.

B. Shi, et al., "A review of silicon carbide MOSFETs in electrified vehicles: application, challenges, and future development," in IET Power Electron., vol. 16, no. 12, pp. 2103-2120, May 2023, doi: 10.1049/pel2.12524.

J. Wei et al., "Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures," in IEEE Trans. Power Electron., vol. 38, no. 7, pp. 8990-9005, Jul. 2023, doi: 10.1109/TPEL.2023.3265864.

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The original version of this eBook is available on https://www.scientific.net/book/design-of-sic-power-devices/978-3-0364-3131-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 93-98

doi: 10.4028/p-VQop5J

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-08

Revised:
2025-12-15

Accepted:
2026-02-26

Online:
2026-05-19

Study of SiC Thyristors with Integrated Temperature Sensors

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Shuhao Cheng 1,a*, Kaiyu Chen 2, b, Zihan Zhang 1,c, Xiaowen Wang 2, d, Lei Yuan 1,e*, Da Huo 1,f, Xuesong Liu 3, g, Tongxiao Hou 3, h, Renxu Jia 1,i, Yuming Zhang 1,j

¹Faculty of Integrated Circuit, Xidian University, Xi'an 710071, China

2 Alkaidsemi Electronic Technology Ltd., Shanghai, China

3 Beijing BJAST Holdings Co., Ltd., Beijing, China

a 13757758666@163.com, b gary_chen@alkaidsemi.com c 24251111422@stu.xidian.edu.cn, d xiaowen_wang@alkaidsemi.com, e yuanlei@xidian.edu.cn, f 22111213858@stu.xidian.edu.cn, q |xs6721@126.com, n 644988605@qq.com, i rxjia@mail.xidian.edu.cn, j zhangym@xidian.edu.cn

Abstract

SiC GTOs, with high current handling capability, are promising for high-voltage and highpower applications, but they also have temperature-related reliability issues, so real-time junction temperature monitoring is needed. In this paper, a novel 4H−SiC gate turn-off thyristor (GTO) structure with integrated temperature sensor is proposed. The proposed sensor is compatible with the SiC GTO process and allows for real-time temperature monitoring. TCAD simulation results show that the integrated sensor has a high sensitivity of 1.64mV/K and linearity of 0.99891 , the temperature sensor monitors the internal temperature of the GTO device in real time with an error of no more than 2 K during complete GTO switching. This new structure is conducive to enhancing the reliability of SiC thyristor applications and system miniaturization.

Keywords: 4H−SiC GTO, PiN diode, Temperature sensor, Real-time temperature monitoring.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Gate turn-off thyristors (GTOs) are high-power semiconductor devices commonly used in applications such as power converters, inverters, and pulsed power switches. They serve as key components in wind power systems to stabilize output power and current [1], and are widely employed in high-speed railways and high-voltage direct current (HVDC) transmission [2]. However, conventional silicon ( Si ) GTOs are constrained by the material's theoretical limits, which are inadequate for modern high-voltage systems. To address these limitations, silicon carbide ( SiC ) has emerged as a promising third-generation semiconductor material due to its wide bandgap, high thermal conductivity, and high saturation carrier velocity, leading to significant research interest in SiC-based GTOs for their superior current capability, high blocking voltage, and high-temperature and high-frequency operation.

Despite these benefits, SiC GTOs also present several reliability challenges, most of which are temperature-related [3-5]. It is evident that, under high-voltage and high-current switching conditions, effective thermal management is essential to prevent junction overheating. Thermal failure occurs when the junction temperature exceeds safe limits. Therefore, real-time temperature monitoring is essential, and since conventional physical methods are prone to inaccuracy and delay, integrated temperature sensors represent a promising direction for future developments.

Recent developments in SiC temperature sensors include PN junctions, PiN transistors, Schottky barrier diodes (SBDs), and body resistors. Among these, SiC PiN diode-based sensors exhibit high sensitivity ( 4.3mV/∘C ) and excellent linearity ( 0.9996 ) from room temperature up to 460∘C [6]. The low temperature dependence of the saturation current Is Is contributes to improved linearity. Additionally, a PTAT (Proportional to Absolute Temperature) structure using the voltage difference between two SiC PiN diodes can eliminate the influence of series resistance [7].

In this paper, a novel SiC GTO structure with an integrated temperature sensor is designed and investigated, offering advantages in process compatibility and compact layout. The paper first introduces the structure and operational principle of the proposed device. followed by an analysis of
the temperature sensor's linearity and sensitivity. Finally, the switching characteristics of the integrated SiC GTO are simulated, and the carrier behavior, temperature distribution, and dynamic temperature measurement process are examined across different operational phases, demonstrating its capability for real-time thermal monitoring.

Device Structure

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

In order to study the operation of the device during the switching process and to obtain the carrier and temperature distribution inside the device, the device structure was modeled using TCAD software. It should be noted that the 2D simulation simplifies the actual three-dimensional heat transfer; therefore, the following thermal and sensor response results are intended for qualitative analysis of trends and operational principles, rather than as quantitatively precise predictions. Fig. 1 shows the device cross-section of the integrated temperature sensor GTO. Terminal structures are generated by ion implantation at the same time as the gate ohmic contact region after the P -drift region etching is completed, which has a width of 8μ m, an injection depth of 1μ m and a doping concentration of 2×1017 cm−3, this terminal structure also serves as an isolation area for the temperature sensors at the same time. N+ substrate doping concentration of 1×1019 cm−3. The thickness of the P buffer layer was 2μ m and the doping concentration was 2×1017 cm−3. The thickness of the P -drift region was 30μ m and the doping concentration was 3×1015 cm−3. The thickness of the N-base region was 3μ m and the doping concentration was 2×1017 cm−3. The thickness of the P+ Anode region was 2μ m and the doping concentration was 1×1019 cm−3.

[picture]

Fig. 1. 4H-SiC GTO Integrated Temperature Sensor Structure.

Fig. 1. 4H-SiC GTO Integrated Temperature Sensor Structure.

The physical models used in the simulation process include: Shockley-Read-Hall recombination model, Auger recombination model, IncompleteIonization model, DopingDependence model, HighFieldSaturation model, BandGapNarrowing model, thermodynamic model [8-12].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Fig. 2 illustrates the current-voltage characteristics of the temperature sensor measured at different temperatures. The relationship between current and voltage follows Eq. 1 while qVd≫ηkT :

Vd=ηkTqln(IdIs)(1)

where η is the ideality factor, Is is the saturation current, and k is the Boltzmann constant. At low sensor currents, the voltage drop decreases as temperature increases, primarily due to the enhanced conductance modulation effect. Conversely, at high sensor currents, the influence of temperature on carrier mobility becomes dominant, leading to an increase in the sensor voltage drop with rising temperature.

[picture]

Fig. 2. I-V Characteristics of sensors at different temperature.

Fig. 2. I-V Characteristics of sensors at different temperature.

Fig. 3. V-T Characteristics of Temperature Sensors.

Fig. 3 shows the relationship between the temperature sensor voltage drop and temperature for a certain operating current Id. When the effect of temperature on the ideal factor and saturation current is not taken into account, there is an approximately linear relationship between the voltage drop Vd and the temperature.

Temperature sensors integrated on the GTO need to be compatible with the GTO process, the doping concentration, thickness and other parameters need to be kept constant, and only the operating current can be changed to adjust the linearity and sensitivity of two parameters. Sensitivity and linearity (R2) are two important parameters of temperature sensors that reflect their ability to monitor temperature.

The V-T characteristics of the sensors with different operating currents and the relationship between operating current and sensor sensitivity and linearity are shown in Fig. 4.

[picture]

Fig. 4. (a) Sensor V-T characteristics at different currents;(b) Relationship between sensor sensitivity and linearity at different currents.

Fig. 4. (a) Sensor V-T characteristics at different currents;(b) Relationship between sensor sensitivity and linearity at different currents.

From Fig. 4(b), it can be seen that the linearity and sensitivity of the sensor decreases with increasing operating current, The reason is that as the operating current increases the on-resistance of the sensor decreases and the reverse saturation current increases.

The integrated PiN temperature sensor has lower linearity and sensitivity parameters compared to the longitudinal PiN temperature sensor in [6] because of the need for compatibility with the GTO process. However, the sensitivity of the Schottky diode is 1.21mV/K compared to the Schottky diode sensor integrated in SiC MOS in [13] at the same operating current, whereas the sensitivity of the integrated PiN temperature sensor is better than the Schottky diode sensor at 1.54mV/K. It also has an advantage over Schottky diode temperature sensors with a maximum sensitivity of 1.18mV/K as mentioned in [14].

Simulation of an Integrated Temperature Sensor GTO Using Switching Circuits, Fig. 5 shows the switching characteristic test circuit of SiC GTO. The circuit system includes resistors R1 and R2, a GTO thyristor, a voltage source V2 and a current source I1 that generates a gate trigger signal.

[picture]

Fig. 5. Thyristor Switching Characteristics Simulation Circuit.

Fig. 5. Thyristor Switching Characteristics Simulation Circuit.

Fig. 6. GTO temperature change during switching.

While making the switching circuit connections to the GTO, a current source is also required to connect the temperature sensor, which operating current is set to 1 mA . The temperature variations during the switching process are shown in Fig. 6, and four time points during the switching process are selected to analyze the carrier distribution, the actual temperature of the device, the sensor detection temperature distribution.

During the switching process the thyristor experiences a complete operating state. At first a negative voltage is applied to the cathode and the device is in the blocking state, then a negative signal is applied to the gate and the device changes from the blocking state to the on state. Fig. 7 shows the temperature and carrier distribution before and after the GTO is turned on from T0 to T1.

[picture]

Fig. 7. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-on.

Fig. 7. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-on.

From the carrier distribution in Fig. 7, it can be seen that holes in the P+ anode region and electrons in the N+ substrate region arrive at the P -drift region during device turn-on to undergo conductance modulation to make the device voltage drop. From the distribution of holes, the PN junction formed by the N -base region and the P -drift region changes from reverse bias to forward bias, the device conducts, and the isolation region formed by the terminal structure can play a good role in isolation. Temperature changes during opening occur mainly in the isolated area of the sensor which are minimal.

The carrier distribution remains stable after GTO conducting. Temperature changes occur in the isolation zone are small at around 10 K , Fig. 8 shows the carrier and temperature distribution of the GTO during conduction from T1 to T2.

[picture]

Fig. 8. (a) Electron density (b) Hole density (c) Temperature distribution during device conduction.

Fig. 8. (a) Electron density (b) Hole density (c) Temperature distribution during device conduction.

During the change of the device from conducting to blocking, a positive signal needs to be applied to the gate to compound and extract the carriers in the drift region, The carrier and temperature distribution from T2 to T3 during turn-off is shown in Fig. 9.

[picture]

Fig. 9. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-off.

Fig. 9. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-off.

Carrier concentration in the drift region during turn-off decreases with gate extraction, The conductivity of the drift region decreases and the PN junction formed by the N-base and P-drift regions is reversely biased as seen from the distribution of holes, the device voltage drop increases. The temperature of the device varies greatly due to the high current and voltage to be withstood during turn-off.

During the switching simulation of the integrated temperature sensor GTO, the operating current of the sensor is constant at 1 mA and the variation of the sensor's voltage drop with time is shown in Fig. 10.

[picture]

Fig. 10. Sensor current and voltage over time.

Fig. 10. Sensor current and voltage over time.

[picture]

Fig. 11. Comparison of sensor measurements with actual device temperature.

Fig. 11. Comparison of sensor measurements with actual device temperature.

In Fig. 10, as the sensor current stable, its voltage also remains stable. The voltage varies with the temperature of the integrated sensor, due to the large temperature change during turn-off, the sensor voltage change during turn-off is also more pronounced.

Based on the voltage response of the sensor shown in Fig. 10 and the previously established V-T relationship from Fig. 3, the temperature extracted from the sensor closely matches the actual device temperature. As illustrated in the real-time monitoring results in Fig. 11, during the turn-on phase under low operating voltage, both the actual temperature change and the sensor voltage drop are minimal, leading to only a slight detected temperature variation. In contrast, the turn-off transition
subjects the device to high voltage and current, causing significant heating reflected by a sharp decrease in sensor voltage and a corresponding large temperature rise, with the peak temperature occurring during turn-off. After turn-off, as the device cools due to reduced current, the sensor voltage increases and the detected temperature declines. Throughout the entire process, the sensor demonstrates high accuracy in tracking device temperature, with errors not exceeding 2 K .

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

In this paper, an integrated PiN temperature sensor 4H−SiC GTO structure compatible with the junction termination process is simulated using TCAD simulation software. The effect of sensitivity and linearity of the sensor at different operating currents was simulated, its sensitivity was maximized to 1.64mV/K and linearity was maximized to 0.99891. The device was simulated using a switching circuit to analyze the changes in carrier and temperature distributions at different stages of operation to analyze and compare sensor measurements, the results show that the sensor is able to monitor the temperature change of SiC GTO throughout the switching cycle in real time, measurement errors do not exceed 2 K , realizing the goal of integrating a temperature sensor in the GTO. The structure monitors the temperature inside the device can avoid the generation of thermal failure which have a better development prospect.

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The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

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Keywords Index

#

3300 V 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

3D Tcad Simulation Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

4 H -sic Characteristics of High Current 4H-SiC Schottky Barrier Diodes

4h-sic Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

4h-silicon Carbide (sic) Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

A

Automotive Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Avalanche Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

B

Bi-directional Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Bi-directional Mosfet Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Bi-directional Switch Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Bidirectional Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

C

Charge-imbalance JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Clamped Pmos Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Common Drain Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Cryogenic Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

D

Design Approach Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

E

Edge Termination Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

F

Field Limiting Rings (flrs) Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

H

High Current Characteristics of High Current 4H-SiC Schottky Barrier Diodes

High Voltage Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

High-frequency Power Electronics The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Hv-h³trb Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

J

Junction Termination Extension (jte) JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

L

Large-area Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Lateral Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Low Specific On-resistance 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

M

Monolithic Integration Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Mosfet Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

O

On-current Improvement 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

On-resistance Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

P

P-well Bias 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Power Mosfet Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Power Semiconductor Device Concept The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Power-tfet The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Process Robustness JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

R

Robustness Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

S

Sbd Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Sbd Embedded Mosfet Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Short-circuit Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

SiC Mosfet Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

SiC Trench Mosfet Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Silicon Carbide 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Silicon Carbide (sic) JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Single Event Burn-out Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Static Characteristics Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Superjunction (sj) JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

T

Temperature Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Tfet The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Trench Refill Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Tunneling Transistor The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Authors Index

A

Abe, T. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Antoniou, M. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Asenov, A. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

B

Bensouiah, D. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Binder, A. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Borca-Tasciuc, G. Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

C

Calcagno, L. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Chen, D. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Chen, K. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Cheng, S. Study of SiC Thyristors with Integrated Temperature Sensors

Chow, T. Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Clark, D. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Cui, P. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Cui, Y. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

D

Dansako, D. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

deBoer, S. Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Dick, J. The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Dutta, T. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

F

Feng, S. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Fiorenza, P. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Flicker, J. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Floyd, R. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

G

Ge, L. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Giannazzo, F. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

H

Han, J. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

He, Z. Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Hou, T. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Hu, H. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Huo, D. Study of SiC Thyristors with Integrated Temperature Sensors

J

Jadav, S. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Jang, S. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Jia, R. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Jiang, Y. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

K

Kagawa, Y. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Kaplar, R. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Kim, J. Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

L

Laborie, L. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Lichtenwalner, D. Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Lin, X. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Liu, X. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Luo, L. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Lynch, J. High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

M

Maistriuk, O. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Mancini, S. High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction; Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Miyazaki, K. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Morgan, A. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Mulpuri, V. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

N

Nebesnyi, V. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Nitta, T. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

P

Park, J. Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Peng, B. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Q

Qi, Y. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

R

Rabbi, S. High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

Rathi, S. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Roccaforte, F. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Rommel, M. The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Ryu, S. Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

S

Salemi, A. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Schulze, J. The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Schwarberg, J. The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Song, X. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Stein, S. Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Sundaresan, S. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Sung, W. High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction; Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

T

Talesara, V. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Tanioka, T. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

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Wan, Y. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Wang, G. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Wang, X. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET; Study of SiC Thyristors with Integrated Temperature Sensors

Wang, Y. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Widjaja, Y. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

X

Xeni, N. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Xu, M. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Xu, X. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Y

Young, R. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Yu, M. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Yuan, L. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

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Zhang, Y. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Zhang, Z. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Zhao, Z. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Zhi, H. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Zhong, K. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Zhong, Y. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Zignale, M. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs