Epitaxial Layer Manufacturing

Edited by

Prof. Victor Veliadis

Dr. Arash Salemi

Epitaxial Layer Manufacturing

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Sócientific.Net

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

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Volume 1157 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

Full text available online at https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

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Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-04

Online:
2025-09-05

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1157.-1.pdf

This special edition collects recent research findings, some technological developments, and engineering practices in the field of substrate and epitaxial layer manufacturing for power electronic devices based on silicon carbide. The articles address specific aspects of epitaxial layer growth, crystal growth technologies, and substrate treatment processes, all critical to achieving the necessary structural integrity and electronic performance in advanced semiconductor devices.

The edition aims to provide a comprehensive resource for researchers, engineers, and practitioners involved in designing, developing, and manufacturing next-generation power electronic components. The articles cover both fundamental principles and applied methodologies, offering a balanced perspective on modern semiconductor technology.

Table of Contents

Preface

Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Min Kyu Kang, Gi Uk Lee, Ye Jin Choi, Gyeoung Jun Song, Na Kyeoung Kim, Mi Seon Park, Kwang Hee Jung, Won Jae Lee

Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Alexander Schrader, Nils Steller, Dennis Reimann, Firas Faisal

Epitaxial SiC Development for High Nitrogen Incorporation

Brenda L. VanMil, Charity H. Burgess, Haoran Wen, Farrokh Ayazi

The -SiC Epitaxy Study of Ammonia Doping

Yue Bin Han, Zhe Yang Li, Ying Xi Niu, Da Li, Hong Lei Yan, Jian Xin Shi

Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

Hiroyuki Nagasawa, Maho Abe, Takenori Tanno, Michimasa Musya, Masao Sakuraba, Shigeo Sato, Yukimune Watanabe, Maki Suemitsu

Predictive Doping and Thickness Analysis of a Multi-Wafer SiC Warm-Wall Epi Reactor for Improved Layer Cpks

Muhammad Ali Johar, Kanwar Singh, Albert Augustus Burk Jr.

Recent Advancement in Noncontact Wafer Level Electrical Characterization for WBG Technologies

Marshall Wilson, Alexandre Savtchouk, Liliana Gutierrez, Carlos Almeida, Jacek Lagowski

Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

Kohei Toda, Kazuya Kiritani, Daichi Dojima, Tadaaki Kaneko

The Application of Dynamical Thermal Annealing Processes after Mechanical Slicing as an Integrated Contactless SiC Wafering Method to Control Crystal Defects

Kohei Toda, Daichi Dojima, Yuta Nakajima, Hiroshi Mihara, Tadaaki Kaneko

Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth

Seung Jun Lee, Su Ho Kim, Chae Young Lee, Jong Hwi Park, Jung Woo Choi, Hyong Suk Lee, Jung Gyu Kim, Kap Ryeol Ku, Min Kyu Kang, Won Jae Lee

High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

Chae Young Lee, Su Ho Kim, Seung Jun Lee, Jong Hwi Park, Jung Woo Choi, Hyong Suk Lee, Jung Gyu Kim, Kap Ryeol Ku, Ye Jin Choi, Won Jae Lee

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 1-7

doi: 10.4028/p-Yddrs7

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-13

Revised:
2025-02-26

Accepted:
2025-02-28

Online:
2025-09-05

Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

Min-Kyu Kang , Gi-Uk Lee , Ye-Jin Choi , Gyeoung-Jun Song , Na-Kyeoung Kim , Mi-Seon Park , Kwang-Hee Jung , *Won-Jae Lee

1Department of Advanced Materials Engineering, Dong-Eui University, 176, Eomgwang-ro, Busanjin-gu, Busan, Korea

kminq980@gmail.com, dlrldnr7774@naver.com, dpwls9080@naver.com, ssjt1147@gmail.com, gjkwanghee@gmail.com, *hleewj@deu.ac.kr

Keywords: PVT, SiC, Crucible design, Source powder, Surface area, Computed tomography, Growth contribution, Powder consumption, Numerical simulation, Supersaturation

Abstract

An effective powder consumption is indispensable for enlarging the diameter and thickness of SiC crystals. We employed three types of filling designs for SiC source powder with different distances between the surface of the seed and the source powder. To maintain the shape of the designs, the SiC source powder was heat-treated in an Ar atmosphere at 680 torr within a temperature range of 1500 to . The SiC source powder consumption and contribution to growth in well-structured layouts increased due to the increase in the surface area of SiC source powder, despite its lower initial powder filling. The numerical simulation showed that the well-structured layouts with a higher surface area of SiC source powder have a higher partial pressure of Si and gases (supersaturation of these gas phases) near the seed region compared to the without well-structured layouts. The computed tomography (CT) analysis of the cross-section of SiC source powder after the growth run clearly showed that the source powder was previously sublimated at the region of the crucible wall, and recrystallization at the surface region of the source powder physically retarded the pathway of SiC source gases to the region of the SiC seed crystal. The newly designed well-structured layouts of the source powder have an economical advantage in achieving effective powder consumption during crystal growth.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

SiC single crystal has nearly 3 to 4 times higher thermal conductivity, breakdown voltage, and band gap energy compared to Si . Due to their superior physical properties, SiC has gathered the most attention as a power semiconductor material [1]. Physical vapor transport (PVT) method has more advantage for enlarging the diameter and thickness of SiC crystals compared with solution-base one. However, during the crystal growth, the recrystallization at the center region of SiC source powder occurs due to relatively lower temperature along the radial direction within crucible wall. The region of recrystallization of source powder interrupts sublimation from the SiC sources, such as and phases, toward the SiC seed crystal region [2]. This is the reason why the PVT method has the disadvantage of a low contribution to growth and consumption of the SiC source powder compared with other growth methods [3]. Despite these disadvantages of the PVT method, the current SiC wafer market is rapidly growing. Recently, the fabrication of SiC single crystals with 8 and 12inch diameters using by the PVT method is being actively introduced. To enlarge the diameter and thickness of the SiC crystal, it requires additional time and cost for growth. It is necessary to improve the efficiency of SiC source powder consumption in PVT growth. In this study, we proposed the fabrication process and design of SiC source powder in the graphite crucible to improve the efficiency of SiC powder consumption. 4-inch SiC single crystals were prepared by the PVT method adopted with several designs of the SiC source powder. The surface area of the powder, powder consumption, and contribution to growth, depending on the design of the SiC powder, were investigated before and after the SiC growth.

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

Fig.1. A Schematic diagram of three types of powder filling-design based on VR (Virtual Reactor, STR) 8.4: a) Design A with no well-structured layout, b) design B with a 104 mm depth of wellstructured layout, and c) design C with a 114 mm depth of well-structured layout.

Fig.1. A Schematic diagram of three types of powder filling-design based on VR (Virtual Reactor, STR) 8.4: a) Design A with no well-structured layout, b) design B with a 104 mm depth of wellstructured layout, and c) design C with a 114 mm depth of well-structured layout.

Figure 1 shows a schematic diagram of three types of powder filling-design in graphite crucible designed by VR (Virtual Reactor, STR) 8.4 software. The powder filling-design was classified as the distance from surface of the SiC seed crystal to the center of SiC source powder. Designs , and C have distances of , and 114 mm , respectively. In design A, physical interference due to powder recrystallization occurs from the formation of an interparticle cavity within the source powder caused by the radial temperature difference between the center (relatively low) and the nearby crucible wall (relatively high). On the contrary, designs B and C with well-structured layouts have more efficient powder consumption due to the increased surface area of the source powder placed near the crucible wall. Figure. 2 exhibits a fabrication process of well-structured layouts of SiC source powder. The fabrication process is as follows: 1) A base powder was filled into the graphite crucible. 2) A small inner graphite crucible was placed on the base powder to form the well-structured layouts. 3) The additional source powder was filled into the empty space of in 2 ) (between the inner and the outer crucible).

Fig.2. The fabrication process of well-structured layouts of SiC source powder (Design B and C ).

Fig.2. The fabrication process of well-structured layouts of SiC source powder (Design B and C ).

To sustain the structure, the heat treatment was conducted in an Ar atmosphere at 680 torr in the temperature range of for 10 hours. Design A did not carry out the heat treatment. In general, heat treatment of a typical SiC source powder is performed at , this temperature range is well known as the sintering temperature for SiC source powder. The sintering process leads to neck formation and the removal of internal pores, resulting in grain growth of the source powder [4]. The pores in the source powder act as paths for SiC source gases such as Si and . The grain growth could be directly linked to the improvement of SiC powder sublimation [5], however, the aspect of the SiC crystal could change with the use of different grain sizes of source powder, even under identical growth conditions. Since the neck formation was conducted at relatively lower temperatures between 1500 and , the grain growth was suppressed, and the minimal inter-grain bonding maintains the shape of the powder. 5) The inner crucible was removed after the heat treatment. Crystal growth using designs A, B, and C was carried out under identical growth conditions. SiC crystals were prepared in an Ar atmosphere of 5 torr at a temperature of approximately for 50 hours by the physical vapor transport (PVT) method. An n-type 4 H -SiC crystal was used as a seed crystal.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

Fig.3. The representative image of the SiC crystal grown using design C a), the measured points of thickness of the SiC crystal b), and the plot of thickness variations along the vertical and horizontal directions on the SiC crystal grown by each design.

Fig.3. The representative image of the SiC crystal grown using design C a), the measured points of thickness of the SiC crystal b), and the plot of thickness variations along the vertical and horizontal directions on the SiC crystal grown by each design.

crystals with a diameter of about 100 mm were grown. The growth rates for SiC crystals (maximum values) with design A, B, and C were , and , respectively. Figure 3a) shows the representative image of the SiC crystal grown by design C , and Fig. 3 b) shows the thickness plot along the directions [1-100] and [11-20] based on the primary flat of the SiC crystal grown using each design. The seven points of thickness were obtained along each direction. The thickness of SiC crystals grown using designs B and C is definitely higher than that of design A . The thickness range (mean thickness) was for design A, mm ) for design B , and ( 9.5 mm ) for design C , respectively. The SiC crystal adoption with designs A and B shows almost a flat surface; however, that of design C shows a convex shape. Design C, with a deeper well depth ( 114 mm ) shows a higher contribution to growth compared with design . This is directly related to an increase in the surface area of the powder. The factor for crystal growth of crystals using designs , and C is as shown in Table 1. Here, the powder consumption [%] and contribution of growth [%] were calculated by the weight usage of powder/total weight of powder and the weight of crystal/weight usage of powder, respectively. As shown in Fig. 4 a), the powder consumption increases with an increase in their surface area, even decreasing in the filling powder. Design A has a higher filling powder of in the crucible and a higher contribution to growth of after crystal growth. This means the SiC source powder was almost consumed and contributed to the growth. However, interestingly, the powder surface area
increases in designs B and C which have well-structured layouts compared to design A which does not have well-structured layout as shown in Fig. 4 b). Design A has a lower growth rate compared with that of the other designs. In contrast, designs B and C have a higher growth rate than design A , even though they have lower filling powder and contribution to growth as shown in Fig. 4 c ).

Table 1. The factors for crystal growth depending on each design.

Factors for crystal growth | Design A | Design B | Design C
Filling powder [g] | 1,202.6 | 919.9 | 845.1
Surface area of powder [mm²] | 2,704 π | 4,624 π | 5,264 π
Powder consumption [%] | 20 | 29 | 39
Growth rate [μm/h] | 126 | 208 | 214
Contribution to growth [%] | 98 | 88 | 90

Fig. 4. The plot of filling powder a) and surface area b) as functions of powder consumption depending on design. c) The plot of contribution to growth as a function of growth rate for each design.

Fig. 4. The plot of filling powder a) and surface area b) as functions of powder consumption depending on design. c) The plot of contribution to growth as a function of growth rate for each design.

In the crystal growth of SiC , one of the most important parameters is the supersaturation of sources near the seed region. Supersaturation with an appropriate level of SiC source allows for the stable growth of SiC single crystals. Chen et al. [6] studied the relationship between supersaturation and growth rate depending on growth pressure. Lower growth pressure leads to an increase in supersaturation; as a result, the growth rate increases. In general, the degree of supersaturation is about 0.0075 torr or less when the growth pressure is in the range of torr. Since crystal growth was performed at a growth pressure of 5 torr in this study, the degree of supersaturation increases as more energy is needed for the phase transition from solid to gas. This is why a sufficient amount of SiC source powder should be consumed to create supersaturation in the seed region. As a result, designs B and C have higher powder consumption of and , respectively; however, design A has lower powder consumption ( ) due to lower supersaturation, despite its higher contribution to growth. Figure 5 shows the partial pressure distribution of and gas phases and SiC source gas flow based on the crucible calculated by VR 8.4 software. In the crucible, the partial pressure of designs B and C was higher than that of design A , as shown in Fig. 5 (a) (c). Figures 5 d ) and e ) show the partial pressure of and in the nearby seed region for each design. Since designs B and C have higher partial pressure than design A , they show the same trend of
increased powder consumption depending on their powder surface area, as mentioned above at Fig. 4 b). Wang et al. [7] explained this behavior toward different partial pressures in the source powder by using Darcy's law and Van Goff's equation, which are related to the momentum equation and the driving force of gas phase shifting from a given point within the powder to the powder surface.

Fig. 5. The numerical simulation of partial pressure and SiC source gas flow for Si and gas phases. The half of left and right of crucible for each design , and , and c show the partial pressure of and , respectively. The partial pressures of Si d) and ) are plotted in the nearby seed region.

Fig. 5. The numerical simulation of partial pressure and SiC source gas flow for Si and gas phases. The half of left and right of crucible for each design , and , and c show the partial pressure of and , respectively. The partial pressures of Si d) and ) are plotted in the nearby seed region.

According to their research, since the temperature of the powder at the region of the crucible wall is consistently higher compared to that of the central region, the partial pressure is also high. However, the temperature of the powder at the surface region is relatively lower and the partial pressure is lower as well. This means that sublimation of the SiC source can theoretically occur through the surface of the given powder. The flow of SiC source gases (flux) is represented by the black arrows in Fig. 5 (a) (c). As a result, both the powder consumption and the partial pressure of the SiC source around the seed region increase with the surface area of the powder. Figure 6 shows the cross-sectional photographic images and CT (Computed Tomography) images of the remaining source powder after growth run. We found that the height of the source powder for all designs increases after growth run due to surface recrystallization. The final increase in height of the center region was for design A, for design B, and 15 mm for design C, respectively. In design A, the sublimation of the source powder occurred at the crucible wall, which had a relatively higher temperature, resulting in only porous carbon powder remaining (as shown in Fig. 6 b). This means source gases
can be previously sublimated at the crucible wall region. At the same time, source gases at the center of the powder were recrystallized on powder surface. The center region of the source powder is likely to recrystallize because this region is relatively lower than the other regions in the crucible. The concept of large sublimation of the source powder near the crucible wall and surface recrystallization of the center region of the source powder could be applied in designs B and C .

Fig. 6. The photographic images a), c), and e) and CT (Computed Tomography) images b), d), and f) of the remaining source powder after the growth run adopting with designs , and C .

Fig. 6. The photographic images a), c), and e) and CT (Computed Tomography) images b), d), and f) of the remaining source powder after the growth run adopting with designs , and C .

We can easily observe the path of source gases in the CT images for designs B and C despite the presence of a large recrystallization region within the source powder after growth, as shown in Fig. 6 d) and f). This leads to effective powder consumption both at the center of the powder and near the crucible. As a result, design C has an economic advantage in achieving higher powder consumption and a higher growth rate of crystals, even with its lower filling of powder, because the powder surface area is the highest. This increases the volume of source gases from the SiC source powder to the seed region. Sufficient supersaturation can form near the seed region, resulting in thicker SiC crystals.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

We prepared the 4 -inch crystals using three types of SiC source powder filling-design with well-structured layouts. The consumption of SiC source powder and the contribution to growth at the well designs increased due to the increase in the surface area of the SiC source powder, despite its lower initial powder filling. The numerical simulation revealed that designs B and C, which have well-structured layouts, exhibit a higher surface area of SiC source powder and a higher partial pressure (higher supersaturation at the seed region) of Si and gases near the seed region. The CT images for design A, which lacks a well-structured layout, showed that the source powder was previously sublimated at the region of the crucible wall, leading to recrystallization at the surface of the source powder due to variation in radial temperature. However, the path for source gases during grain growth can be clearly observed in the CT images for designs B and C, despite the presence of a large recrystallization region within the source powder. This leads to effective powder consumption both at the center of the powder and near the crucible. The new design with a well-structured layout for the source powder paves the way to achieving effective powder consumption in SiC crystal growth.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

This work was supported by Technology Innovation Program (Project Number : 1415185945, P0012451, 2024) funded by the Ministry of Trade, Industry and Energy.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.1.pdf

P. J. Wellmann, Review of SiC crystal growth technology, Semicond. Sci. Technol. 33 (2018) 103001

X. Liu, B. Y. Chen, L. X. Song, E. W. Shi, Z. Z. Chen, The behavior of powder sublimation in the long-term PVT growth of SiC crystals, J. Crys. Growth. 312, 9 (2010) 1486-1490

H. Norihiro, et al., High-speed, high-quality crystal growth of by high-temperature gas source method, Appl. Phys. Express. 7 (2014) 065502

T. Hidehiko, Silicon carbide powder and sintered materials, J. Ceram. Soc. Japan. 119, 3 (2011) 218-233

I.G. Yeo, et al., The quality investigation of crystals grown by a conventional PVT method with various SiC powders, TEEM. 11, 2 (2010) 61-64

Q. Chen, J. Yan, V. Prasad, Application of flow-kinetics model to the PVT growth of SiC crystals, J. Crys. Growth. 303 (2007) 357-361

X. Wang, D. Cai, H. Zhang, Increase of SiC sublimation growth contribution by optimizing of powder packaging, J. Crys. Growth. 305 (2007) 122-132

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The original version of this eBook is available on https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 9-16

doi: 10.4028/p-1uGwT1

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-02-26

Accepted:
2025-02-28

Online:
2025-09-05

Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

The original version of this paper is available on https://www.scientific.net/MSF.1157.9.pdf

Alexander Schrader , Nils Steller , Dennis Reimann and Firas Faisal

Nexperia Germany GmbH, Stresemannallee 101, 22529 Hamburg, Germany

alexander.schrader@nexperia.com, nils.steller@nexperia.com, dennis.reimann@nexperia.com,

Keywords: Epitaxy, CVD, Nitrogen Doping, Dopant Incorporation, Growth Parameters, C/Si Ratio, Site Competition, On-wafer Uniformity

Abstract

This study investigates the multifaceted relationships between key process parameters such as ratio, system pressure, temperature, and growth rate and their effects on nitrogen dopant incorporation in homoepitaxial layers on substrates. We focus on understanding how these growth parameters influence the in situ nitrogen incorporation during chemical vapor deposition (CVD) of epitaxial layers on 150 mm commercially available SiC substrates. Through a carefully designed experimental framework, which explores the interactions between each parameter and the C/Si ratio, we have shed light on a refined approach for epitaxial growth. This approach may not only stabilize the nitrogen dopant concentration across the wafer but possibly also reduces the formation of epitaxial defects.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1157.9.pdf

This study investigates the effects of key chemical vapor deposition process parameters as system pressure, temperature, growth rate, and ratio on nitrogen dopant incorporation in SiC epitaxy. The results demonstrate that increased system pressure and temperature promote nitrogen incorporation, while an elevated growth rate reduces doping efficiency. These trends are primarily driven by changes in the effective C/Si ratio near the wafer surface, which alters the balance between nitrogen and carbon incorporation due to site competition. Variations in the ratio interact differently with each parameter, affecting dopant distribution and defect formation.

This study provides a refined understanding of the interplay between growth conditions and dopant incorporation, offering insights for optimizing epitaxial growth processes for SiC. The findings highlight that optimizing these parameters can potentially lead to a more uniform dopant concentration profile across wafers, improving the quality of SiC substrates. However, further investigation is required to assess how these adjustments impact defect densities, such as stacking faults and pit defects, which could influence the performance of SiC-based electronic components. Additionally, understanding the molecular dynamics during epitaxial growth, including gas-phase reactions and precursor interactions with the SiC lattice, is essential. Future research using advanced
simulation models or in situ measurements will be critical in refining epitaxial growth processes on commercially available wafers.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.9.pdf

F. Yang, Modern Metal-Organic Chemical Vapor Deposition (MOCVD) Reactors and Growing Nitride-based Materials, in Nitride Semiconductor Light-Emitting Diodes (LEDs), Elsevier, 2014, pp. 27-65.

G. Ferro and D. Chaussende, A New Model for in situ Nitrogen Incorporation into 4H-SiC during Epitaxy, Scientific Reports 7 (2017) 43069.

G. Ferro and D. Chaussende, Revisiting the Site-Competition Doping of : Cases of N and Al, Materials Science Forum, Trans Tech Publ Ltd 1004 (2020) 96-101.

U. Forsberg, O. Danielsson, A. Henry, E. Janzen, Nitrogen Doping of Epitaxial Silicon Carbide, Journal of Crystal Growth 236 (2002) 101-112.

H. Saitoh, A. Manabe, T. Kimoto, Epitaxial Growth of with Large Off-Angles by Chemical Vapor Deposition, Materials Science Forum, Trans Tech Publ Ltd 527-529 (2006) 223226.

M. Zielinski, R. Arvinte, H. Peyre, p-type Doping of 4H- and 3C-SiC Epitaxial Layers with Aluminum, Materials Science Forum, Trans Tech Publ Ltd 858 (2016) 137-142.

J. Zhang, A. Ellison, A. Henry, E. Janzén, Nitrogen Incorporation during 4H-SiC Epitaxy in a Chimney CVD Reactor, Journal of Crystal Growth 226 (2001) 267-276.

D. J. Larkin, P. G. Neudeck, L. G. Matus, Site-Competition Epitaxy for Superior Silicon Carbide Electronics, Applied Physics Letters 65 (1994) 1659-1661.

Ö. Danielsson, U. Forsberg, E. Janzén, Predicted Nitrogen Doping Concentrations in Silicon Carbide Epitaxial Layers Grown by Hotwall Chemical Vapor Deposition, Journal of Crystal Growth 250 (2003) 471-478.

J. Olander, K. M. E. Larsson, Adsorption of N-containing Species onto SiC(0001) Surfaces: A Theoretical Study, Physical Review B - Condensed Matter and Materials Physics 67 (2003) 115306.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 17-22

doi: 10.4028/p-6BykPL

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-04-30

Accepted:
2025-05-01

Online:
2025-09-05

Epitaxial SiC Development for High Nitrogen Incorporation

The original version of this paper is available on https://www.scientific.net/MSF.1157.17.pdf

¹DEVCOM Army Research Laboratory, 2800 Powder Mill Road, Adelphi, MD 20783 USA

StethX Microsystems, Inc. 75 5th St NW, Suite 2180

Atlanta, GA 30308 USA

Keywords: high nitrogen doping, Silicon Carbide on Insulator (SiCOI), Young's Modulus

Abstract

SiCOI is used as a lower cost substrate for power electronics and enables fabrication of MEMS and photonics platforms. Modification of the mechanical properties of SiC through doping is a potential pathway for improving resonator performance. This effort aimed to develop growth parameters for growth of with nitrogen concentrations of with a smooth surface morphology for fabrication of SiCOI wafers for MEMS fabrication. Growth conditions that were investigated include substrate polarity, growth pressure, C/Si ratio, temperature, and carrier gas flow. Highly doped grown epiwafers contained particle defects which exhibited different morphologies for C - and Si-polarities.

Brenda L. VanMil, Charity H. Burgess, Haoran Wen, and Farrokh Ayazi

The original version of this paper is available on https://www.scientific.net/MSF.1157.17.pdf

Brenda.L.VanMil.civ@army.mil, charity.h.burgess.ctr@army.mil, haoran@stethxmicro.com, dayazi@stethxmicro.com

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1157.17.pdf

Silicon Carbide for SiC-on-insulator (SiCOI) has been established as a lower cost substrate for power electronics [1]. The structure of the SiCOI substrate allows for easy fabrication of undercut structures through the removal of the intermediate oxide layer with a buffered oxide etch for microelectromechanical systems (MEMS) [2] and photonics platforms [3]. Silicon carbide is of particular interest for improving MEMS resonator gyroscope performance over silicon devices due to small phonon Akhiezer dissipation and the in-plane isotropic hexagonal crystal lattice.

The modification of the dopant density provides a promising pathway to modify the temperature coefficient of frequency (TCF) to optimize the Q-factor for acoustic resonators. This has been demonstrated in silicon [4] and 3C-SiC [5]. The work in 3C-SiC by Sapienza et.al. noted that Young's modulus increases with increasing nitrogen incorporation in 3C-SiC grown on <111> silicon. They also observed enhancement of tensile stress for aluminum doped 3C-SiC grown on silicon. Subsequent work also correlated improvement in Young's modulus with a decrease in the density of stacking faults [6].

The work presented in this paper was conducted to grow as highly doped as possible so that in future work we can determine if it is possible to incorporate enough dopant to observe a similar effect in highly doped . The theoretical solubility limits for nitrogen and aluminum in 4H-SiC are and , respectively [7], [8]. The dopant of choice in this work was nitrogen, and not aluminum, as aluminum has a well-known memory effect. Epitaxial is typically not doped above the low dopant concentration, as nucleation of stacking faults occurs [9]. Many of the growth parameters that can be varied during hot-wall chemical vapor deposition (HWCVD) growth have been reported in the literature including substrate polarity, growth pressure, ratio, nitrogen flow and temperature over the typical (up to low ) doping range[10], while noting that Chen et.al. [11] did demonstrate doping up to on C-face .

In this work, we have varied these same parameters, and the carrier gas flow, over a larger range in an effort to incorporate nitrogen as close to the solubility limit as possible, in at least of epitaxial material, while maintaining a smooth surface morphology for fabrication of a SiCOI layer.

Methodology and Results

The original version of this paper is available on https://www.scientific.net/MSF.1157.17.pdf

This work was conducted with a well-used set of susceptor parts that were nearing the end of their lifetimes with the anticipation of developing a large n -type background. Note that this was confirmed. For a ratio of 1.3 before the growth campaign the background electron concentration was and was in the range at the end of the growth campaign. It is known that nitrogen incorporates at a higher rate for C -face substrates [10]. However, as we were not able to obtain epi-ready C-face wafers this work started with growth on Si-face substrates. We measured the C-face of a Si-face epi-ready wafer by AFM after the initial ramp up to growth temperature and hydrogen etch of the surface and observed a bilayer stepped surface, with an rms roughness of 0.21 nm , without polishing artifacts and decided this was sufficient to pursue the C-face work.

Samples were grown on -SiC substrates utilizing silane balance , ethylene , and 10 lpm of gas as the dopant in an LPE PE106 HWCVD system. Nitrogen concentrations ([N]) were determined on three samples, two Si-face and one C-face, grown with varying growth conditions using secondary ion mass spectroscopy (SIMS) (EAG Laboratories, Sunnyvale, CA). The samples were grown with a silane flow of 40 sccm for the two Si-face wafers and the C-face wafer was grown at 40 sccm for the C/Si ratio steps, but at 66.6 sccm for the rest of the steps to increase the growth rate for thick layer growth. Thicknesses were determined using the lengths of defects from particles, as the doping was too high for reflectance measurements. Surface profiles were acquired with a Keyence VK-X3100 3D surface profiler.
Nitrogen Incorporation Nitrogen concentrations are plotted in Fig. 1 on the same scale for various growth conditions. These plots elucidate trends for a narrow sampling of parameter space in this system which were specifically investigated to determine growth parameters which would reach [N] near the theoretical solubility limit. The legends indicate relevant growth parameters for each series as the parameter space is interdependent on the many variables explored here. All data points were taken in the carbon stable growth regime. This means that changing the silicon flow results in a change in growth rate. The inflection point to silicon stable occurs near for this apparatus. In Fig. 1.a) the [N] decreases with increasing C/Si, exhibiting the site competition effect [12]. Note that Arvinte et.al. have reported N incorporation in C and Si-face 4 H -SIC is similar for silicon stable growth for under . For the rest of the plots a ratio of 0.8 was selected, as decreasing the ratio further was detrimental to the surface morphology. Fig. 1.b) shows increasing nitrogen incorporation with increasing pressure, consistent with the trends up to in [9]. Fig. 1.c) shows that decreased with increasing temperature. Of note, at the growth rate is measurably lower than that measured at indicating at this temperature there is measurable etching in competition with the growth. Fig. 1.d) shows that for increasing nitrogen partial pressure (lower carrier gas flow) a higher is attained.

Uniform Epilayers Uniform, nominal epilayers were grown on a of a -off wafer to determine if the growth parameters that reached the highest would have a smooth surface morphology. For the Si -face growth, large triangular defects nucleated at the growth interface as shown in Fig. 2.a). The insets of Fig. 2 show the locations where a surface profile was taken for each defect, the profile is shown below the Nomarski micrograph. These defects affect large areas of the surface and extend above and below the epi-surface by a few micrometers. The growth conditions that resulted in a specular surface as observed by Nomarski micrographs, (except for the large defects) were a temperature of carrier gas flow of 80 slm and 400 mbar which should result in a of . These samples exhibited up to 20 nm steps by AFM, which could be removed with a chemo-mechanical polishing finish. Different variations of growth conditions that should result in higher [ N ] resulted in a rough surface with a high density of in-grown stacking faults. These in-grown stacking faults are the same as observed for high C/Si ratio growths and are found to nucleate at micropipes, mechanical damage or substrate defects [14].

Particle-nucleated defects on the C-face exhibited a different morphology as shown in Fig. 2 b). These are formed by large particles that likely fell from the susceptor before the start of the growth. The particles are up to in diameter, incorporate into the growing layer and affect morphology
along the step-flow growth direction. The growth conditions that resulted in a smooth surface (except for the large defects) were a temperature of carrier gas flow of 100 slm and 100 mbar which should result in a of . This wafer has 40 large defects over a 100 mm wafer. For growth conditions that should result in higher [N], a decrease in growth rate was observed with a large density of particles nucleating defects near the edge of the wafer. An example of this effect is shown in Fig. 3. These samples could be used to create SiCOI if the damaged outer area is removed before bonding.

Fig. 1. Nitrogen concentration is plotted for both Si -face and C -face growth based on a) ratio, b) system pressure, c) temperature and d) the carrier gas hydrogen flow. Note that the flow was 40 sccm for all Si -face points and for the C -face in b ). The C -face points for the rest had a flow of 66.6 sccm , resulting in higher growth rates.

Fig. 1. Nitrogen concentration is plotted for both Si -face and C -face growth based on a) ratio, b) system pressure, c) temperature and d) the carrier gas hydrogen flow. Note that the flow was 40 sccm for all Si -face points and for the C -face in b ). The C -face points for the rest had a flow of 66.6 sccm , resulting in higher growth rates.

Fig. 2. a) thick epilayer, Si- face growth with and b) thick epilayer C -face growth with . The insets show the line profile, along the [1120], step-flow growth direction, (red online) taken for thickness variation as plotted below the Nomarski image.

Fig. 2. a) thick epilayer, Si- face growth with and b) thick epilayer C -face growth with . The insets show the line profile, along the [1120], step-flow growth direction, (red online) taken for thickness variation as plotted below the Nomarski image.

Discussion

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Growth conditions were found for both the carbon and silicon face that incorporated nitrogen. These growth conditions had a low C/Si ratio that resulted in nucleation of silicon particles in the gas phase. The use of a well-used susceptor may have contributed to large particles which nucleate defects. These particles resulted in different polytype inclusion defects for the two faces. Growth parameters were found that minimized nucleation of particles and wafers were grown with nitrogen concentrations of for carbon face and for the silicon face. The characteristic defects are shown in Figure 1 a) for the carbon face and b) for the silicon face. The defect nucleating from the particles on the carbon face growth projects above the surface, so they can be polished away for SiCOI fabrication. The polytype inclusion nucleating from the particles on the silicon face growth both protrudes and is recessed from the surface and also covers a much larger area making SiCOI fabrication challenging. The growth rate was also observed to decrease for growth conditions with higher nitrogen incorporation.

Fig. 3 Image of a quarter of a -face wafer with decreased growth rate and particle issues near the edges of the sample.

Fig. 3. Image of a quarter of a -face wafer with decreased growth rate and particle issues near the edges of the sample.

Particle driven large morphological defects are the largest hindrance towards creation of commercial scale SiCOI with nitrogen concentrations above . In future work the SiCOI layers will be fabricated into BAW resonators and characterized to determine if their inherent material properties enhance the resonator performance metrics. If the highly nitrogen doped SiC exhibits sufficient gain for MEMS resonators manufacturers can dedicate a set of susceptor parts to the high nitrogen process to isolate the memory effect and reduce the effects of using older parts.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.17.pdf

G. Gelineau, C. Masante, E. Rolland, S. Barbet, L. Corbin, A. André, V. Amalbert, S. Caridroit, M. Delcroix, S. Huet, A. Moulin, V. Prudkovskiy, N. Troutot, S. Rouchier, L. Turchetti, K. Mony and J. Widiez, CEA-Leti, Univ. Grenoble Alpes, "Processing and electrical characterization of SiC-on-Insulator structures", ICSCRM 2023, (Sep 2023), Sorrente, Italy. ffcea-04557058

J. Yang, B. Hamelin, and F. Ayazi, J. of Microelectromechanical Systems, 29, (2020) 147382.

Lutong Cai, Jingwei Li, Ruixuan Wang, and Qing Li, Photonics Research 10, no. 4 (2022).

Ashwin K. Samarao and Farrokh Ayazi, IEEE Trans Electron Devices 59 (2012) 87-93.

S. Sapienza, M. Ferri, L. Belsito, D. Marini, M. Zielinski, F. La Via and A.Roncaglia, Micromachines (2021), 12, 1072. .

C. Calabretta, V. Scuderi, C. Bongiorno, A. Cannizzaro, R. Anzalone, L. Calcagno, M. Mauceri, D. Crippa, S. Boninelli, and F. La Via, Cryst. Growth Des., 22 (2022) 4996-5003 .

T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology, 1st ed.; John Wiley & Sons: Singapore, 2014.

Y.A. Vodakov, E.N. Mokhov, M.G. Ramm, A.D. Roenkov, Springer Proceedings in Physics. Washington, DC, USA: Third International Conference on Amorphous and Crystalline Silicon Carbide and Other Group IV-IV Materials; 1990, 56 (1992) 329-334.

T.A. Kuhr, JinQiang Liu, Hun Jae Chung and M. Skowronski, J. Appl. Phys. 92, (2002) 586371.

U. Forsberg, Ö. Danielsson, A. Henry, M.K. Linnarsson and E. Janzén, J. Cryst. Growth, 236 (2002) 101-112.

W. Chen, K.-y. Lee, and M. Capano, J. Cryst. Growth, 297 (2006) 265-71.

D.J. Larkin, P.G. Neudeck, J.A. Powell, L.G. Matus, Appl. Phys. Lett. 65 (1994) 1659.

R. Arvinte, M. Zielinski, T. Chassagne, M. Portail, A. Michon, P. Kwasnicki, S.Juillaguet and H. Peyre, Mat. Sci. Forum, 821 (2015) 149-52.

A.O. Konstantinov, C. Hallin, B. Pécz, O. Kordina and E. Janzén, J. Cryst. Growth, 178 (1997) 495-504.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 23-31

doi: 10.4028/p-1SGyRh

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-24

Accepted:
2025-04-04

Online:
2025-09-05

The -SiC Epitaxy Study of Ammonia Doping

The original version of this paper is available on https://www.scientific.net/MSF.1157.23.pdf

Yuebin Han , Zheyang , Yingxi Niu , Da , Honglei Yan , Jianxin Shi

SiCentury Semiconductor Technology (Suzhou) Co., Ltd, Jiangsu Province, 215021, China

Beijing Huairou Laboratory, Beijing, 101499, China

Beijing Institute of Smart Energy, Beijing, 102209, China

Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China

fkellyshi@sicentury.com

Keywords: Epitaxy; Ammonia; Nitrogen; Doping concentration; Uniformity; Deviation

Abstract

Silicon carbide ( SiC ) is one of the ideal electronic materials for producing hightemperature, high-frequency, and high-power electronic devices. In the past 20 years, with the continuous improvement of silicon carbide material processing technology, its application has been expanding. Unlike Si devices, SiC devices cannot be directly fabricated on crude wafers. Instead, epitaxial films need to be deposited and grown on SiC wafers, then the epitaxial films will be used to as the foundation for producing devices. The doping concentration performance of the epitaxial layer can determine the device performance, making it the most important indicator of the epitaxial layer quality. For a long time, nitrogen has been used as the dopant in the production of SiC epi-wafers. Due to the difficulty of nitrogen cracking and its adsorption in graphite, the concentration is prone to significant drift, resulting in a decrease in yield and low production efficiency. In this research a unique vertical epitaxial process was used to consecutively grow 108 -inch SiC substrates with nitrogen and ammonia as dopant separately. The concentration and thickness of the grown epitaxial films was measured and studied. The results indicate that compared to nitrogen as a dopant, the results of ammonia doping are significantly better in terms of intra-wafer concentration uniformity and interwafer consistency. Using nitrogen as the dopant, the doping concentrations uniformity of epi-layer ranges from to , and the deviation is between . As a comparison, using ammonia as the dopant, the doping concentration uniformity of epi-layer ranges from to , and the deviation is between . Meanwhile, the thickness performance is maintained at the same level. Therefore, ammonia as a dopant can solve the concentration drift problem that has long been a headache in large-scale production of SiC epitaxy, greatly improving production efficiency. Its advantages are obvious. This study analyzed the most significant reasons for the superior performance of ammonia gas as a dopant for 4 H SiC epitaxy compared to nitrogen.

Introduction

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SiC, as a typical representative of third-generation wide bandgap semiconductor materials, has the characteristics of high critical breakdown field strength, high thermal conductivity, high electron saturation drift velocity, large bandgap width, and strong radiation resistance . It can meet the requirements of the next generation of power electronic equipment for working under harsh conditions such as higher power, smaller size, and high temperature and radiation . It has the advantages of reducing size, decreasing power loss, and lower cooling requirements. SiC has become an essential material for high-end applications in power electronics, bringing revolutionary changes in fields such as new energy vehicles, photovoltaics, energy storage, rail transit, and smart grids . In the past few years, the popularity of electric vehicles has driven a continuous supply shortage of SiC power devices .

Different from the typical Si semiconductor manufacturing process, SiC devices must be processed on the epitaxial film. Therefore, silicon carbide epitaxial equipment plays a critical connecting role
in the whole industrial chain, and it is also the most complex and difficult to develop equipment in the whole industrial chain. The doping concentration performance of the epitaxial layer can determine device performance and is the most important indicator for measuring the quality of epi-wafers in epitaxial mass production. At present, SiC power devices are mainly produced from 6-inch wafers. The shipping standards for mainstream epitaxial manufacturers' 6-inch epitaxial wafers are: thickness uniformity , doping concentration uniformity , and defect density (triangle + downfall) . In the past 20 years, with the continuous improvement of epitaxial equipment and processes, the growth rate and quality of silicon carbide epitaxial films have been greatly improved, which has correspondingly promoted their widespread application in more fields. With the development of 8-inch wafer technology, the current shipping standards for 8 -inch epitaxial wafers are basically on par with 6-inch wafers.

Nitrogen has long been used as dopant for N-type doping in SiC research and industry due to its availability, low cost, and inherent safety. At the same time, the industry has had to withstand its significant drawback, which is, the tendency to drift and poor stability of doping concentration. When conducting batch epi-growth, the doping concentration will change from one epi-wafer to another, especially for equipment utilizing a horizontal process flow, which has a large range of variation and can easily exceed the set shipping standards. In order to avoid the epi-wafer scrap, resulting from doping concentration out of spec, epi-wafer manufacturers have had to test every epi-wafer and determine the adjustment plan for the next epi-wafer prior to proceeding the next epi-growth. Alternatively, based on the test results, adjustments can be made up to every 3 wafers, which leads to a significant decrease in production efficiency. Against the backdrop of the surging demand for SiC power chips, together with the tightening of shipping standards, the concentration drift of nitrogen doping has become an urgent issue that needs to be addressed. Analyzing the reasons, a speculation is that due to the high chemical stability of nitrogen, it is very difficult to crack, resulting in a very low proportion of active nitrogen atoms which can be doped. A large amount of nitrogen is adsorbed and accumulated in the cavity by graphite components. During the heating process of the next epigrowth, the newly introduced nitrogen and the accumulated and released nitrogen will gradually lift up the doping concentration. Contrarily, when ammonia was used as dopant, the doping process will be carried out in a more controlled way. In this research a vertical epitaxial equipment was used to consecutively grow 108 -inch SiC epi-wafers using nitrogen and ammonia as dopant separately. The concentration and thickness of the grown epi-layers were detected and studied, and the prospects of ammonia replacing nitrogen as dopant were investigated.

Experiment

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The homogeneous epitaxial growth experiment in this study was conducted in the SiC epitaxial CVD equipment developed by SiCentury Company. Here the process utilizes a vertical type, hotwall, 6/8-inch compatible, equipped with high-speed rotation technology. Previous studies and production practices have demonstrated the very good performance of this equipment using nitrogen as dopant on 6-inch and 8-inch SiC epitaxy. Figure 1 shows the schematic structure of its process chamber, which consists of a spray head, a hot wall, a tray rotating device, a side resistance heating system, and a bottom resistance heating system. The process gas is vertically injected into the chamber through the top spray head, and reaches the substrate surface through a hood to undergo epitaxial growth reaction. The substrate is heated by the bottom heaters and rotated by a high-speed rotating system. The SiC substrate is a double-side polished 4H SiC substrate, purchased from Tankeblue Company. SiC thin film was grown on a 4 H SiC wafer with a diameter of 200 mm on the Si surface. The reaction gases were TCS and , with flow rates of 850 and , respectively. and HCl gases were used for pre-etching and surface preparation. The carrier gas, purified by an purifier, flow rate is 120 slm and the reaction chamber pressure is 250 mbar . The temperature for epitaxial growth is . Table 1 summarizes the process growth conditions of this study.

Fig. 1. Schematic drawing of high-speed rotation vertical hot-wall CVD process chamber.

Fig. 1. Schematic drawing of high-speed rotation vertical hot-wall CVD process chamber.

Table 1. Table of epitaxial parameters.

Epi-growth Parameters | Set value | Unit
Temperature | 1650 | [°C]
Pressure | 200~400 | [mbar]
Rotation Speed | 400~600 | [r/min]
C/Si | 0.8~1.2 | —
Si/H₂ | 2.8% | —
Cl/Si | 3.2 | —

The thickness of the epitaxial film was measured using a ThermoFisher Nicolet IS50 Fourier transform infrared spectrometer (FTIR), the doping concentration was measured using a 4D CVMAP 92 A mercury probe tester, and the edge exclusion was 5.0 mm .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1157.23.pdf

Epitaxial Growth Results by Using Nitrogen as Dopant. Firstly, nitrogen was used as dopant to carry out 10 consecutive homogeneous epi-growth on 8-inch SiC wafers. During the growth period, the recipe was slightly adjusted based on the tested doping concentration results, especially in run # 5/6/7 where the nitrogen flow rate was reduced to ensure that the doping concentration met the shipping standards. The test results of 10 epi-wafers are as follows: the average doping concentration is , the uniformity of doping concentration ranges from to , with the average uniformity of , the deviation of the average concentration to the target value is between , and the average absolute deviation is ; The average thickness is , and the thickness uniformity ranges from to , with the average uniformity of . The deviation of the average thickness to the target value is between , and the average absolute deviation is
. Figures show the intra-wafer uniformity and deviation of 10 consecutive samples with doping concentration and thickness, respectively. Compared with the shipping standards for epiwafers mentioned in the introduction, it can be found that the uniformity of the experimental results has reached the standard of 6-inch epitaxial wafers, meeting the requirements for mass shipment. However, it can be found from Figure 3 that the fluctuation of doping concentration is relatively big, and in large-scale production, even slight production management deviation can easily lead to out of spec and scrap, subsequently affecting production efficiency.

Fig. 2. Doping Concentration Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 2. Doping Concentration Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 3. Doping Concentration Average Deviation of 10 Consecutive Runs ( as Dopant).

Fig. 3. Doping Concentration Average Deviation of 10 Consecutive Runs ( as Dopant).

Fig. 4. Thickness Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 4. Thickness Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 5. Thickness Average Deviation of 10 Consecutive Runs ( as Dopant).

Fig. 5. Thickness Average Deviation of 10 Consecutive Runs ( as Dopant).

Epitaxial Growth Results by Using Ammonia as Dopant. Then, ammonia was used as dopant to carry out 10 consecutive homogeneous epi-growth on 8 -inch SiC wafers, keeping the recipe completely unchanged. The test results of 10 epi-wafers are as follows: the average doping concentration is , the uniformity of doping concentration ranges from to , with the average uniformity of , the deviation of the average concentration to the target value is between , and the average absolute deviation is ; The average thickness is , and the thickness uniformity ranges from to , with the average uniformity of . The deviation of the average thickness to the target value is between , and the average absolute deviation is . Figures 6-9 show the intra-wafer uniformity and deviation of 10 consecutive samples with doping concentration and thickness, respectively. Compared with the shipping standards for epi-wafers mentioned in the introduction, it can be found that the uniformity has reached the level of 6-inch excellent epi-wafers, fully meeting the requirements for mass shipment. Data shows that there is basically no change in the performance of thickness, surface roughness, and surface defects of the epitaxial film in the two situations of nitrogen and ammonia as dopant, and the biggest difference is about doping concentration performance. The average uniformity of doping concentration is by using ammonia, which is significantly reduced from by using nitrogen as dopant, and the deviation is between by using ammonia, which is significantly decreased from by using nitrogen as the dopant. Therefore, it can be concluded that using
ammonia as dopant significantly increase the uniformity and reduce the deviation of doping concentration, which can solve the long-lasting concentration drift problem in SiC industry, greatly improve production efficiency, and is very beneficial to SiC mass production.

Fig. 6. Doping Concentration Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 6. Doping Concentration Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 7. Doping Concentration Average Deviation of 10 Consecutive Runs ( as Dopant).

Fig. 7. Doping Concentration Average Deviation of 10 Consecutive Runs ( as Dopant).

Fig. 8. Thickness Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 8. Thickness Uniformity of 10 Consecutive Runs ( as Dopant).

Fig. 9. Thickness Average Deviation of 10 Consecutive Runs ( as Dopant).

Fig. 9. Thickness Average Deviation of 10 Consecutive Runs ( as Dopant).

To investigate the impact of dopant to defect density, SICA88 was employed to measure the 10 epi-wafers by nitrogen and 10 epi-wafers by ammonia separately. The results show the average killer defect (carrot, triangle and downfall) density in both cases are and respectively, indicating that the dopants have almost no impact to defect density.

Analysis of Experimental Results. From the experimental results, it can be concluded that compared with using nitrogen as dopant, using ammonia as dopant, by comparing Figure 6 and Figure 2, it can be observed that the uniformity of the within-wafer doping concentration is significantly reduced from an average of to ; by comparing Figure 7 and Figure 3, it can be observed that the deviation of doping concentration has significantly decreased from an average of to . The significant improvements in these two aspects can be analyzed from the chemical characteristics and adsorption properties of ammonia gas.

Nitrogen molecules are bound by N-N triple bonds, which are very strong and difficult to break. The bond energy is as high as , so its cracking is very difficult. For instance, its decomposition temperature under atmospheric pressure is about . This determines that at a SiC epi-growth temperature of around , the proportion of nitrogen that can be decomposed into active nitrogen atoms is very low. The N-H bond energy in ammonia molecules is only , so its cracking is relatively much easier, with decomposition temperature of around . This means that at the epi-growth temperature of SiC around , the proportion of active nitrogen atoms is significantly increased when using ammonia vs. nitrogen as dopant. Because the graphite component inside the reaction chamber is a porous material with strong adsorption capacity. A large amount of nitrogen is adsorbed and accumulated in the cavity by graphite components. During the heating process of the next run, because of the addition of the newly introduced nitrogen and the accumulated released nitrogen, the doping concentration will gradually increase, which is often difficult to predict. As shown in Figure 3, in prior to adjusting the nitrogen flow rate, the concentration deviation gradually increases from Run #2 to Run #4, and from Run #7 to Run #10, which is the result of accumulation. Graphite is prone to adsorb more nitrogen than ammonia . Therefore, when using ammonia as dopant, the doping process in each epi-growth mainly depends on the active nitrogen atoms cracked during the epi-growth, without cumulative effects, in which good inter-wafer uniformity and inter-wafer consistency cand be relatively easily achieved compared with nitrogen. This is reflected that the concentration deviation of each run shown in Figure 7 is very small, showing there is no cumulative effect.

When nitrogen is used as dopant in epi-growth, the main reason for the deterioration of inter-wafer uniformity is the increasing doping concentration at the edge while the concentration remains stable in the center area. The increasing doping concentration at the edge is because new loose particles are
constantly generated at the edge of the tray during every epi-growth, which increases the adsorption of nitrogen and gradually increases the doping concentration at the edge area, while the center area remains flat and unchanged, resulting in the continuous increase of within-wafer uniformity. When ammonia is used as dopant, the adsorption at the edge points is weak, and the doping concentration at the edge area remains stable, resulting in a significant improvement in within-wafer uniformity.

The primary challenge in using ammonia doping process is to prevent blockages at both the inlet and exhaust ends. Special designs are required to achieve that at both ends. The design at the inlet end aims to prevent and HCl from contact and reacting at low temperatures. The design at the exhaust end aims to directly introduce the unreacted excessive into the exhaust treatment system, also avoiding contact HCl .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1157.23.pdf

The research results indicate that compared to nitrogen as dopant, the use of ammonia as dopant results is significantly better for within-wafer concentration uniformity and inter-wafer consistency. When using nitrogen as dopant to consecutively carry out 10 epi-growth, an average within-wafer uniformity of and mean concentration deviation of can be achieved. In comparison, when using ammonia as dopant to consecutively carry out 10 epi-growth, an average within-wafer uniformity of and mean concentration deviation of can be achieved. Clearly, the conclusion can be drawn that using ammonia as dopant significantly increases the uniformity and reduces the deviation of doping concentration. These significant improvements will contribute to solving the long-lasting concentration drift problem in SiC epitaxial production, greatly improving production efficiency, and is very profitable to large-scale production. The advantages of ammonia as dopant are obvious. The next step of research should focus on studying and verifying the performance of epi-wafers doped with ammonia in the chip manufacturing process and final device, paving the way for the large-scale use of ammonia as dopant in SiC epitaxial production.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1157.23.pdf

This work was supported in part by the Major Scientific and Technological Achievement Transformation Projects in Jiangsu Province under grant No. BA2022082. The authors would like to thank Trevor Norman for the grammar correction and valuable comments.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.23.pdf

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P.J. Wellmann, Review of SiC crystal growth technology, Semicond. Sci. Technol. 33 (2018) 103001.

X. She, A.Q. Huang, O. Lucìa, B. Ozpineci, Review of silicon carbide power devices and their applications, IEEE Trans. Ind. Electron. 64 (2017) 8193-8205.

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Yuebin Han, Yong Pu, Jianxin Shi & Honglei Yan. Epitaxial Growth Study of n-Type 4H-SiC Films by High-Speed Wafer Rotation Vertical Hot-Wall CVD Equipment, J Synth Cryst. 52(2023) 918-924.

Jingrui Han, Xiguang Li, Yongmei Li, et al. Substrate Preparation and Epitaxy for the Production of SiC wafers, J Synth Cryst. 53(2024) 1712-1719.

Huitao Gu, (2012). The Study of Removal of Low-concentration Ammonia from Nitrogen by Adsorption. (Doctoral dissertation, Dalian University of Technology).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 33-41

doi: 10.4028/p-BJgP7H

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-05-31

Accepted:
2025-05-31

Online:
2025-09-05

Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

The original version of this paper is available on https://www.scientific.net/MSF.1157.33.pdf

H. Nagasawa , M. Abe , T. Tanno , M. Musya , M. Sakuraba , S. Sato . Watanabe and M. Suemitsu

CUSIC Inc. 2-2-10 Chuo, Aoba, Sendai, Miyagi, 980-0021 Japan

RIEC, Tohoku Univ., 2-1-1 Katahira, Aoba, Sendai 980-8577, Japan

Grad. Sch. Eng., Tohoku Univ.,6-6 Aramaki Aza Aoba, Aoba, Sendai 980-8579, Japan

Seiko Epson Corp., 281 Fujimi, Fujimi-machi, Suwa-gun, Nagano 399-0293, Japan

michimasa.musya.a4@tohoku.ac.jp, sakuraba.masao@myad.jp, shigeo@tohoku.ac.jp,

Keywords: 3C-SiC, 4H-SiC, Heteroepitaxy, EBSD, TEM, Coherent Interface, Scanning Probe Microscopy, 2DEG, 2DHG

Abstract

To generate both two-dimensional electron gas ( 2 DEG ) and two-dimensional hole gas (2DHG) at will in SiC polytype heterojunctions, simultaneous lateral epitaxy (SLE) method has been extended to form epilayers of alternating stacks of 4 H - and 3C-SiC, which includes the first formation of single-domain on . The process starts with a spontaneous generation of mononuclear 3C-SiC on the atomically flat wide terrace on 4H-SiC, which expands parallel to the basal plane to form a single-domain 3C-SiC layer having the coherent interface with the underlying 4H-SiC layer. Step-controlled epitaxy is then applied using the adjacent steps to grow an alternative layer on top of the surface, forming another coherent interface. The crystal structure, the interface structure, and the carrier distribution of these stacked epilayers were analyzed. Finally, it is demonstrated that 2DEG occurs at the coherent interface between the 3C-SiC(111) Siand -faces and 2 DHG at the and faces.

Introduction

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Semiconductor devices based on polytype heterojunctions are an attractive application of SiC. Recently, a high electron mobility transistor (HEMT) utilizing the two-dimensional electron gas (2DEG) generated at the -SiC heterojunction has been demonstrated by Sazawa et al. [1,2]. To grow the desired 3C-SiC epilayer on the C-face of substrate suitable for 2DEG, they precisely tuned the off-orientation and the off-angle at proper values. This epitaxial growth technique, however, is not compatible with the wide-spread step-controlled epitaxy, a standard epitaxial growth in the SiC industry. Another limitation of their method is that only 2 DEG forms on the face and it is necessary to change the substrate to the Si-face to realize two-dimensional hole gas (2DHG). To overcome these limitations, we have extended our original growth method of simultaneous lateral epitaxy (SLE) [3,4] to be able to form epilayers of alternating stacks of and 3C-SiC. The conventional SLE is implemented by step-controlled epitaxy on groove patterned off-axis -face. The heterojunction obtained by this SLE, however, consists of a coherent interface between -face and -face, which generates 2DHG [5]. To generate 2DEG using SLE, the interface must consist of the -face and 3CSiC(111) Si-face [6]. To obtain both 2DEG and 2DHG at will, we have extended SLE to be able to form alternating stacks of epilayers of and .

To form single-domain 3C-SiC on 4H-SiC, 3C-SiC mononuclear ( ) must be generated spontaneously on the atomically flat wide terrace (WT) in the basal plane of , which is a necessary condition for eliminating the double-positioning boundary (DPB). When the width of the narrowest part of the WT exceeds a critical value for spontaneous nucleation , generates near
the center of the WT [3]. Contrary to the nucleation on the surface, the nucleation on the surface is practically impossible even if the surface is atomically flat. This is because the stacking sequence of is not uniquely determined on . The SiC layer on 3C-SiC should be formed by a similar manner of step-controlled epitaxy, with lateral expansion of existing 4H-SiC steps.

Fig. 1. Schematic section of alternating epitaxial growth of 4 H - and 3C-SiC: a) 3C-SiC nuclei ( ) are generated on atomically flat wide terrace (WT) and shift in the [0001] direction; b) Then, the 3C-SiC layers originating from and the surrounding layers expand in the [11 ] direction (downstream); c) Finally, a 4H-SiC layer is inserted between each 3C-SiC layer.

Fig. 1. Schematic section of alternating epitaxial growth of 4 H - and 3C-SiC: a) 3C-SiC nuclei ( ) are generated on atomically flat wide terrace (WT) and shift in the [0001] direction; b) Then, the 3C-SiC layers originating from and the surrounding layers expand in the [11 ] direction (downstream); c) Finally, a 4H-SiC layer is inserted between each 3C-SiC layer.

In this study, the nucleation sites of are arranged on misoriented substrate so that the stacking sequence originally contained in the substrate propagates laterally on layers as schematically shown in Fig. 1 a). It should be noted that each is shifted to a relative in the [0001] direction. Then, as shown in Fig. 1 b), the 3C-SiC layer originating from and surrounding the layer expand in the direction (downstream) by step-controlled epitaxy. Finally, a 4H-SiC layer can be inserted between each 3C-SiC layer (Fig.1 c). The above method produces two types of coherent interfaces simultaneously. One is a boundary between and -faces. The other is a boundary between and -faces. The crystal structure and carrier distribution of the SiC epilayer including each one of the coherent interfaces are analyzed in detail.

Experimental

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A wafer with a surface with Si -face tilted by 4 degrees in the direction relative to the (0001) plane was used as a substrate for SLE. Before the epitaxial growth, grooves of -depth were formed on the substrate surface by photolithography and dry etching techniques. All groove edges were deflected away from the [ ] direction forming vertices ( as the initial letter) in the [1120] direction, and this creates isolated zigzag-shaped plateaus (PL as the initial letter), as schematically shown in Fig. 2. The is generated near each on the PL, which is the most [0001] oriented portion on the PL, in a similar manner to the method disclosed by Larkin et al. [7]. Each PL and are arranged alternately in the [11 ] direction. For example, PL1 locates on the [ ] direction side (upstream) of , and locates on the [11 ] direction side (downstream) of PL2. In the epitaxial growth process described later, as shown in Fig. 1 b), the edge of grows laterally in the [11 ] direction, and it is possible to form a stacked layer of PL 1 on the layer originating . The spacing of adjacent in the [ ] direction ( P ), the width of groove ( S ), the displacement of in the [1120] direction (Z), and the width of PL (W) are varied independently to observe their effect on the stacked structure of SiC epilayer. In this study, we focus on the different behavior of the epitaxial growth in two characteristic areas, each of which contains grooves with varying dimensions. The dimensions of the three grooves in the first area (area-1) are , while those in the second area (area-2) are , and .

Fig. 2. Configuration of grooves formed on substrate: All groove edges were deflected away from the [1̄100] direction forming vertices in the [ direction, which creates isolated zigzag plateaus (PL) separated by grooves. The spacing of adjacent in the direction (P), the width of groove ( S ), the displacement of in the [ ] direction ( Z ), and the width of were varied.

Fig. 2. Configuration of grooves formed on substrate: All groove edges were deflected away from the [1̄100] direction forming vertices in the [ direction, which creates isolated zigzag plateaus (PL) separated by grooves. The spacing of adjacent in the direction (P), the width of groove ( S ), the displacement of in the [ ] direction ( Z ), and the width of were varied.

After the groove formation, to suppress the DPB generation, a specific cubic close-packed structure was exposed on the topmost surface of the substrate by Step-Alignment treatment, and then a slightly nitrogen doped -thick SiC layer was epitaxially grown on it.

The distribution of the crystal structures in the epilayer formed by SLE was evaluated using scanning electron microscopy (SEM) combining with electron backscatter diffraction (EBSD). The orientation relationship of each crystal plane of epilayer was determined by inverse pole figures (IPFs) of EBSD. The stacked structure and lattice image of the interface were observed using cross-sectional transmission electron microscopy (XTEM). The distribution of carriers in the epilayer was quantified using scanning microwave microscopy (SMM), and the conduction type of the carriers was identified by scanning capacitance microscopy (SCM).

Results and Discussion

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First, we focus on one of the SLE grown layers, area-1. In the SEM image shown in Fig. 3 a), the left half of each plateau (on the [1120] side) is occupied by a bright region about wide, and the remaining right half (on the side) is occupied by a dark region. The boundary between the bright and dark regions is a straight line parallel to the [ ] direction.

Fig. 3. SEM image and IPF maps in area-1: a) SEM image; b) IPF maps of the region surrounded by the dashed square in fig a).

Fig. 3. SEM image and IPF maps in area-1: a) SEM image; b) IPF maps of the region surrounded by the dashed square in fig a).

The IPF maps of the region surrounded by the dashed square in Fig. 3 a), which includes the boundary between the bright and dark regions, are shown in Fig. 3 b). It is obvious that the bright region corresponds to , and the dark region corresponds to . The map Z shows that the orientation of the and planes coincide. In addition, the orientation of 3C-SiC( ) and planes coincide in map X and the orientation of and planes coincide in map Y . It is clear that the layer corresponding to the bright region in Fig. 3 a) shares the same basal plane with the layer in the dark region and does not contain DPBs.

In Fig. 3 a), a WT can be found on the plateau adjacent to the downstream side of the groove. The shape of the WT is schematically represented in Fig. 4. When a virtual circle ( ) with the outer edges of the WT as tangents is overwritten, the diameter of corresponds to . The geometrically calculated is . The -wide groove is thought to act as an obstacle to the lateral growth of toward downstream, maintaining the WT width greater than .

Fig. 4. Schematic plan view of WT in area-1: When a virtual circle ( ) with the outer edges of the WT as tangents is overwritten, the diameter of corresponds to the critical value for spontaneous nucleation of 3C-SiC ( ).

Fig. 4. Schematic plan view of WT in area-1: When a virtual circle ( ) with the outer edges of the WT as tangents is overwritten, the diameter of corresponds to the critical value for spontaneous nucleation of 3C-SiC ( ).

Fig. 5 shows XTEM images of the ( ) cross section along the A-A' line overlayed in Fig. 3 a), which includes the boundary between and regions. The global image shown in Fig. 5 a) indicates that the layer is stacked on the layer forming an interface ( ) parallel to the basal plane. The angle at which the interface intersects the surface of the epitaxial layer corresponds to 4 degrees, the tilt angle of the substrate. Fig. 5 b), which is a high magnification lattice image, shows that the forms an atomically flat plane, and its stacking structure is uniform. As a result, the structure of the SiC epilayer in area-1 is shown schematically in Fig. 5 c ), in which the - and -faces bind each other forming a coherent interface in the basal plane.

Fig. 5. XTEM images and schematic structure of the SiC epilayer in area-1: a) Global image; b) Lattice image at the interface ( ); c) Schematic structure of stack.

Fig. 5. XTEM images and schematic structure of the SiC epilayer in area-1: a) Global image; b) Lattice image at the interface ( ); c) Schematic structure of stack.

Next, we focus on area-2. In the SEM image of the epilayer surface shown in Fig. 6 a), most of the area on the plateau exhibits a dark contrast . However, a bright line parallel to the [ ] direction can be found at a distance of about from the groove edge. The IPF maps in Fig. 6 b), which were observed in the same area as Fig. 6 a), show that single-domain is exposed in most of the area-2, but the L observed in Fig. 6 a) corresponds to , whose (111) plane orients in the same direction as that of plane.

Fig. 6. SEM image and IPF maps in area-2: a) SEM image; b) IPF maps.

Fig. 6. SEM image and IPF maps in area-2: a) SEM image; b) IPF maps.

Unlike in Fig. 3 a), the WT adjacent to the downstream side of the groove, whose width should exceed , cannot be found in Fig. 6 a). It is considered that the obstacle to the lateral growth of toward downstream disappears during the epitaxial growth in area-2. In other words, after the 3C-SiC layer has expanded on the WT, the upstream plateau consists of grows laterally on the 3C-SiC layer as explained in Fig. 1. Considering the remarkable difference in the shape of the grooves in area-1 and -2, the width of the groove is one of the important factors that define the formation of the multilayer structure and the thickness of the 3C-SiC intermediate layer.

Fig. 7. XTEM images and schematic structure of the SiC epilayer in area-2: a) Global image; b) Lattice image at the interface ( ) between the middle 3 C -SiC and the top 4 H -SiC layers; c) Lattice image at the interface ( ) between the bottom and the middle layers;
d) Schematic structure of stack.

Fig. 7. XTEM images and schematic structure of the SiC epilayer in area-2: a) Global image; b) Lattice image at the interface ( ) between the middle 3 C -SiC and the top 4 H -SiC layers; c) Lattice image at the interface ( ) between the bottom and the middle layers; d) Schematic structure of stack.

The XTEM images of the ( ) cross-section along the B-B' line superimposed in Fig. 6 a) is shown in Fig. 7. Two interfaces parallel to the basal plane can be found in the global image of Fig. 7 a). One interface ( ) is formed in the deeper part of the epilayer, which is the boundary between the bottom layer and the middle layer. The upper interface is the boundary between the middle 3C-SiC layer and the top 4H-SiC layer. Both interfaces are parallel to the basal plane and intersect the surface of each epilayer at an angle of 4 degrees, which is the same as the tilt angle of the substrate. High-magnification lattice image in Fig. 7 b) shows that the corresponds to coherent interface, because it shows an atomically flat and uniform stacking sequence. Also the is a coherent interface as seen in Fig. 7 c). As schematically shown in Fig. 7 d), the epilayer structure in area-2 consists of a 3C-SiC middle layer sandwiched between 4H-SiC layers, with the 3C-SiC( ) C -face and -face facing each other at the and the -face and 3 C -face each other at .

It is known that the coherent interface where the -face and -face are bound each other forms 2DHG with the sheet carrier density about [5], and the coherent interface where the -face and -face are bound forms high electron mobility 2DEG with the sheet carrier density above . These are considered to be caused mainly by positive or negative fixed charges induced by spontaneous polarization at the heterointerfaces, which is dependent on the degree of hexagonality in SiC polytypes [10]. Additionally, thanks to the large conduction band offset ( ), it is suggested that free electron accumulation in 2DEG can be effectively induced in the 3C-SiC layer [8]. Based on the above findings, it is considered that only 2DHG exists in the cross-section of area-1 (including only IF 0 ), while 2DEG and 2DHG coexist in the cross section of area-2 (including IF 1 and IF2).

Fig. 8. SMM images observed in area-1: a) Plane image; b) Cross-sectional image.

Fig. 8. SMM images observed in area-1: a) Plane image; b) Cross-sectional image.

Fig. 9. SCM images observed in area-1: a) Plane image; b) Cross-sectional image.

Fig. 9. SCM images observed in area-1: a) Plane image; b) Cross-sectional image.

Fig. 8 shows the SMM images observed in area-1. The observation was carried out so as to include the IF 0 . The intensity of the SMM signal depends on the carrier density, and darker and brighter colors indicates lower and higher carrier density, respectively. It should be noted that, due to the principles of SMM, the measured value is the density per volume, and the sheet carrier density cannot be obtained. As shown in the plane image shown in Fig. 8 a) and the cross-sectional image in Fig. 8 b), a carrier density of is found in the layer corresponding to , and in the layer corresponding to 3C-SiC. The difference in carrier density between the and layers may be influenced by the differences in activation rate or compensation of doped nitrogen. Notably, a carrier density of is observed along the line corresponding to . To identify the conduction type of the carriers observed above, the SCM images observed simultaneously with the SMM are shown in Fig. 9. Here, polarity and intensity of SCM signal are attributed to conduction type (p- or n-type) and carrier density, respectively. Figs a) and b) show the planar and cross-sectional images of the SCM, respectively. Those clearly show that the conduction type of the 3C-SiC and 4H-SiC layers is n-type, while it is p-type on the line corresponding to . This means that 2 DHG is generated exactly at the boundary between 3 C and .

Fig. 10. SMM images observed in area-2: a) Plane image; b) Cross-sectional image.

Fig. 10. SMM images observed in area-2: a) Plane image; b) Cross-sectional image.

Fig. 11. SCM images observed in area-2: a) Plane image; b) Cross-sectional image.

Fig. 11. SCM images observed in area-2: a) Plane image; b) Cross-sectional image.

The SMM images observed in area-2 are shown in Fig. 10. In the surface image (Fig. 10 a), a couple of bright lines (high carrier density regions) can be seen along the and intercepts on the surface. On the other hand, on the top 4 H -SiC epilayer and on the bottom 4 H SiC epilayer ( ), lower density regions (indicated by brown) can be seen, and carrier density is determined to be and , respectively. At the cross-sectional image (Fig. 10 b), carrier-depleted regions can be seen near the surface. Additionally, two higher carrier density regions (indicated by light yellow bands) can be identified at and , and they reach surface along the basal plane through the depleted region. The SCM image observed in the same area is shown in Fig. 11. In particular, the darkest color corresponds to the highest carrier density ( for for ). In the SCM surface image (Fig. 11a), the n-type region (shown in light blue or blue) and the p-type region (shown in orange) are clearly visible. The prominent n - and p -type regions correspond to the locations where and are exposed on the surface, respectively. Fig. 11 b) shows the SCM cross-sectional image. The light blue and orange lines parallel to the basal plane are thought to correspond to the 2DEG formed along and the 2DHG formed along IF , respectively. Considering the spatial resolution of the SCM, the actual local carrier density of the 2DEG and 2DHG is likely to be much higher than . In this way, we have successfully demonstrated that simultaneous formation of 2DEG and 2DHG can be realized on a -face.

Conclusion

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To generate 2DEG and 2DHG in the SiC polytype heteroepitaxial layers at will, multilayer epitaxial growth of and was demonstrated. Formation of a groove with a vertex in the [1120] direction was found to act as an efficient blocker against the step-controlled epitaxy of , and to obtain single-nucleus on the atomically flat wide terrace at predetermined location. This method also enables us to obtain a multilayer structure by conducting the step-controlled epitaxy of alternative , which prevents continuous nucleation on the layer obtained on . 2DHG is formed at the coherent interface between the 3C-SiC( and the -faces whilst 2 DEG is formed at the coherent interface between the 3 C - and the -faces. In this way, we have demonstrated a technology for forming multilayer structures at specific locations by SLE method. This technology opens the way to applications such as high-frequency devices using 2DEG and 2DHG as well as CMOS integrated circuits with resistance to high voltage, higher temperatures and strong radiation environments.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1157.33.pdf

The authors would like to express their sincere gratitude to Ceramic Forum Co., Ltd. for providing patterned SiC wafers and performing epitaxial growth on them, and to Dry Chemicals Co., Ltd. for performing the Step-Alignment treatment to obtain single-domain SiC epitaxial layers.

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The original version of this paper is available on https://www.scientific.net/MSF.1157.33.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 43-47

doi: 10.4028/p-7z0LLo

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-05

Predictive Doping and Thickness Analysis of a Multi-Wafer SiC Warm-Wall Epi Reactor for Improved Layer Cpks

The original version of this paper is available on https://www.scientific.net/MSF.1157.43.pdf

Muhammad Ali Johar , Kanwar Singh and Albert Augustus Burk Jr

Coherent Corp. 2251 Newlins Mill Rd. Easton, PA USA 18045

muhammadali.johar@coherent.com, Kanwar.singh@coherent.com, albert.burk@coherent.com

Abstract

Rapid progress in the growth of epitaxial layers allow device scientists/engineers to tighten the specifications of doping and thickness uniformities of SiC epitaxial films. Further, reducing the cost of SiC epitaxial layers is a continuing goal. A compelling approach is to choose a multi-wafer warm-wall epi reactor which has been shown to have very high wafer throughput. The precursors decompose upon heating by passing over hot reactor components, however, the precursor molecules crack before reaching the substrate and can form parasitic SiC coatings. Such coatings change the emissivity of reactor parts, changing their temperatures. The allowed vapor pressure in the gas phase is also a function of the chemical composition of these deposits. Consequently, the effective ratio at the wafer varies the nitrogen incorporation efficiency on the SiC epitaxial wafer. In this paper, we have reported an approach on how to minimize the effect of changing ratio on absolute layer doping and thickness over the full campaign. We analyzed the data, identified the pattern, and have used it to make predictions or decisions to keep the deviation within control limits. The nitrogen incorporation was analyzed as a function of cumulative coating on the reactor parts. The derived models were used to make the decisions for predictive doping by adjusting the flow rates of nitrogen precursors during upcoming campaigns at specific cumulative thickness of reactor parts coating. The same approach was also used for the adjustment of growth time to obtain the targeted epi layer thickness as a function of cumulative coating. Consequently, the predictive doping control resulted in the improvement of doping Cpk from 0.37 to and the predictive thickness control resulted in the improvement of thickness Cpk from 0.75 to 1.61 . This implies that the process is six sigma qualified and expected overall nonconformance was for doping. Moreover, the average 200 source contrast projected chip yield using a Lasertec system 88-HIT and the machine learning based PLDLZ recipe was by considering the Particle, Bump, Micropipe, ComplexSF, Polytype Inclusion, Particle Inclusion, and ScratchTrace as device killer defects. The average BPDs were on 150 mm wafers using a thick buffer layer. Initial results on 200 mm wafers are also presented.

Introduction

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The demand of electric vehicles has increased significantly over the last 5 years resulting in high demand of power electronic components such as MOSFETs, Schottky, and JBS diodes [1-5]. Silicon carbide (SiC) is outperforming other materials (Si and III-Nitrides) for high power electronic applications because of excellent physical, chemical, electrical, and thermal properties such as better thermal conductivity, low thermal expansion and excellent thermal shock resistance, low power and switching losses, high energy conversion efficiency, high operating frequency, high operating temperature, small die size for same power, long lifetime, and possibility of excellent thermal management. Further, the benefits include significant efficiency gains through miniaturization advancements, decreased cooling requirement with reduced cost. Within the last decade, high quality 150 mm SiC substrates have become available which, when combined with 150 mm epitaxy should further drive cost reduction, and multiwafer epi reactor serves the purpose of reducing the cost [6].

Over the last few years, the same effort is being implemented on 200 mm substrates and epitaxy to reduce the cost using multiwafer chemical vapor deposition (CVD).

In a typical warm wall or hot wall CVD reactor, the precursors of SiC are heated before reaching the substrate. As a result of the high temperature, the precursors decompose before reaching the substrate, and form the compounds which deposit on the reactor parts upstream, called parasitic deposits. The parasitic deposits are not 2D in geometry and are polycrystalline in nature, having a variety of textures. It is well known that the vapor pressure of material is function of the surface, this means that the vapor pressure of silicon and carbon precursors vary as a function of the coating on upstream reactor parts and local temperature, ultimately changing the vapor pressure leads to variation in decomposition of precursors which results in variation in carbon ratio. The nitrogen incorporation efficiency follows the trend of multi order polynomial as function of ratio [7]. Such variation in doping needs to be adjusted proactively by developing a statistical predictive model to achieve the desired doping in the epitaxial layer. These models help to predict the change in doping as function of cumulative coating on the reactor parts.

Experimental Methods

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To grow the epitaxial layer, double side polished N -type substrates with off-axis cut angle towards [11 ] were used. The diameter of the substrates was 150 mm and 200 mm . A multiwafer CVD tool was used to grow the epitaxial layer atop substrates. The precursors for , and Cl were trichlorosilane , ethylene , and hydrochloric acid , respectively. For the characterization of epitaxial films, FTIR was used to measure the thickness, Corona charge CV (CnCV) was used to measure the doping using non-contact mode, and the defectivity was evaluated by lasertech system 88-HIT. In total, 400 plus epi wafers were grown to analyze the doping incorporation efficiency versus cumulative coating. To summarize the data, Microsoft excel was used with JMP17 to analyze the data fitting the curves to get the trends of doping incorporation efficiency and growth rates as function of cumulative coating on reactor parts.

Results and Discussions

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The thickness target of epitaxially grown wafers was and the doping target was . The thickness reduced from 10.71 to 9.95 as function of cumulative coating as shown in Fig.1(a)

Fig. 1. (a) Average thickness and (b) average doping as function of cumulative coating of multi-wafer reactor without any adjustment for full campaign before PM.

Fig. 1. (a) Average thickness and (b) average doping as function of cumulative coating of multi-wafer reactor without any adjustment for full campaign before PM.

The goodness of the fit ( ) was 0.976 . The order polynomial equation for thickness change over cumulative coating is given in eq. (1)

Where, " " is predicted thickness of the film, " " is the target thickness of the film, " " and " " are the constants which remain constant for one reactor type and will change based on reactor design, growth rate, growth temperature, and growth pressure. " Tc " is the cumulative thickness of the reactor parts. " " is the limit of the critical cumulative thickness used in the order polynomial part of the equation only
For doping, the target was and the effect of cumulative coating on doping is shown in Fig.1(b). The doping increased as high as without any adjustment. The order polynomial equation to get the predicted doping as a function of cumulative equation is shown in eq. (2). The goodness of fit was 0.90 for the fit of doping trend.

Where, " " is the predicted doping. " " is the target doping. " ", " ", and " " are the constants for one reactor type and will change based on reactor design, growth rate, growth temperature, and growth pressure.

Fig. 2. (a) Three-way control chart of doping for full campaign ( ) and (b) process capability analysis histogram, nonconformance, and doping control limits.

Fig. 2. (a) Three-way control chart of doping for full campaign ( ) and (b) process capability analysis histogram, nonconformance, and doping control limits.

Following the early campaigns, the developed models shown in eq. (1) and eq. (2) were implemented and the thickness and doping were achieved very close to target. For further analysis, the Cpk were also calculated, and the predictive thickness control resulted in the improvement of thickness Cpk from 0.75 to 1.61 , and the improvement of doping Cpk was observed from 0.37 to . This approach helped us to make our process six sigma qualified. The standard process control (SPC) charts of doping are shown in Figs2(a) & 2(b) with target doping of . The average doping of the multi epi wafers grown in a single run was barely found outside the control limits as depicted from the Fig.2(a). The average moving range on means was with upper control limit of . The average doping of the full campaign was (target was
) with lower control limit (LCL) and upper control limit (UCL) of , , respectively, which are within the upper specification limit (USL) and lower specification limit (LSL) . The Nonconformance of the process was observed as .

Fig. 3. Chip Yield by LT SICA, Coherent chosen device killer defects: Particle, Bump, Micropipe, ComplexSF, Polytype Inclusion, Particle Inclusion, and ScratchTrace: excluded non-killer-defects; Unclassified, Black, Pit, SF, Vline, PL_Black, PL_White, PL_BPD, PL_SF, Chain, (a) chip yield using 200 source contrast, (b) histogram of defects at 200 source contrast with Vlines off, (c) chip yield using 0 source contrast, and (d) histogram of defects at 0 source contrast with Vlines off.

Fig. 3. Chip Yield by LT SICA, Coherent chosen device killer defects: Particle, Bump, Micropipe, ComplexSF, Polytype Inclusion, Particle Inclusion, and ScratchTrace: excluded non-killer-defects; Unclassified, Black, Pit, SF, Vline, PL_Black, PL_White, PL_BPD, PL_SF, Chain, (a) chip yield using 200 source contrast, (b) histogram of defects at 200 source contrast with Vlines off, (c) chip yield using 0 source contrast, and (d) histogram of defects at 0 source contrast with Vlines off.

An example of the defect evaluation of 150 mm wafers used in these experiments is shown in Fig.3. Fig.3(a) shows the chip yield ( ) against the device killer defects chosen by Coherent Corp. such as Particle, Bump, Micropipe, ComplexSF, Polytype Inclusion, Particle Inclusion, and ScratchTrace, which shows the chip yield of , however, the average chip yield ( ) of all epi wafers at 200 source contrast under the same criteria was and BPDs were below 25 . Fig.3(b) shows the histogram of all defects at 200 source contrast. Fig.3(c) shows the chip yield against the device killer defects chosen by Coherent Corp. at 0 source contrast which is . The histogram of all defects same map at 0 source contrast is shown in Fig.3(d).

Alongwith 150 mm epitaxial capability, the 200 mm epitaxy current best results were thickness uniformity, doping uniformity, and 200 source contrast chip yield ( ) was . More 200 mm results will be published in upcoming papers.

Summary/Conclusions

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In summary, we have developed an approach-based machine behavior to control the thickness, doping, and uniformity to increase the epi reactor yield and throughput for a multiwafer SiC epi reactor. The same process is implemented on our 150 mm and 200 mm epi process. Our results confirmed that our process is six sigma qualified and one can benefit from predictive doping and thickness control.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1157.43.pdf

For this effort, we acknowledge the support by Coherent SiC epi process engineers (Philip Frey, Rajat Jain, Troy Tomlinson, Mark Strzelecki and Rick Vega), our SiC epi equipment team (Martin Wilcox, Brad Howsare, Steve Nemeth, and Juan Sosa), and our SiC substrate team. We gratefully acknowledge partial funding for this work under AFRL under contract number "FA8650-17-2-1727 P00015", Jane Thompson contract monitor and Joseph Merrett technical advisor.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.43.pdf

O. Seok, I.H. Kang, H.W. Kim, J.H. Moon, M. Na, S. Kim, N.K. Kim, Y.-J. Kim, H.J. Jung, W. Bahng, 1.2 kV SiC trench MOSFETs with double p-base junctions, (n.d.).

A. Kanale, T.H. Cheng, K.J. Han, B.J. Baliga, S. Bhattacharya, D. Hopkins, 1.2 kV, 10 A, 4HSiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop, Mater. Sci. Forum 1004 (2020) 872-881. .

A. Koyama, Y. Kiuchi, T. Mizushima, K. Takenaka, S. Matsunaga, M. Sometani, K. Nakayama, H. Ishimori, A. Kimoto, M. Takei, T. Kato, Y. Yonezawa, H. Okumura, 20 kVClass Ultra-High Voltage 4H-SiC n-IE-IGBTs, Mater. Sci. Forum 1004 (2020) 899-904. .

A. Gendron-Hansen, C. Hong, Y.F. Jiang, J. May, D. Sdrulla, B. Odekirk, A.S. Kashyap, Commercialization of Highly Rugged 4H-SiC 3300 V Schottky Diodes and Power MOSFETs, Mater. Sci. Forum 1004 (2020) 822-829. MSF.1004.822.

D. Todo, H. Hanafusa, S. Higashi, Investigation on Electrical Characteristics of 4H-SiC Schottky-Barrier- Diodes after Silicon-Cap-Annealing, (n.d.).

A.A. Burk, D. Tsvetkov, M.J. O'Loughlin, S. Ustin, L. Garrett, A.R. Powell, J. Seaman, N. Partin, Latest SiC Epitaxial Layer Growth Results in a High-Throughput WarmWall Planetary Reactor, Mater. Sci. Forum 778-780 (2014) 113-116. .

L.B. Rowland, A.A. Burk, C.D. Brandt, Nitrogen Doping Efficiency During Vapor Phase Epitaxy of , Mater. Sci. Forum 264-268 (1998) 115-118. .

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Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 49-56

doi: 10.4028/p-qU8rgR

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-06-03

Accepted:
2025-06-03

Online:
2025-09-05

Recent Advancement in Noncontact Wafer Level Electrical Characterization for WBG Technologies

The original version of this paper is available on https://www.scientific.net/MSF.1157.49.pdf

Marshall Wilson , Alexandre Savtchouk , Liliana Gutierrez , Carlos Almeida , and Jacek Lagowski

Semilab SDI, 12415 Telecom Dr., Tampa, FL 33637, USA

marshall.wilson@semilabsdi.com, sasha.savtchouk@semilabsdi.com, cliliana.gutierrez@semilabsdi.com, carlos.almeida@semilabsdi.com

ejacek.lagowski@semilabsdi.com

Abstract

A breakthrough high throughput WBG semiconductor dopant monitoring method has recently been introduced based on the novel concept of sweeping the electrical bias by near UV illumination-induced photoneutralization of corona charge. As originally discovered for , the doping determination can be realized using the value of the photoneutralization time constant. In the present work this procedure is tested for with a larger energy gap of 4.8 eV , using a correspondingly deeper UV range. Such deep UV application to the AlGaN/GaN HEMT structure resulted in the development of a new measurement principle capable of increasing the HEMT wafer measurement throughput 10 times compared to previous corona noncontact metrology. The new principle involves a linear illumination-induced corona charge bias sweep. Combined with surface voltage monitoring, it provides a means for fast and precise determination of the pinch-off voltage, , the AlGaN electrical thickness, and the 2D electron gas density.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1157.49.pdf

Wide bandgap (WBG) semiconductor technology is the primary answer to the growing demands of high-power electronic devices. The continually advancing production of WBG epitaxial wafers and structures requires a cost effective, fast feedback metrology, enabling precise wafer level monitoring of epitaxial properties, e.g., dopant concentration, depth profile, uniformity and run to run reproducibility. Our development of such a noninvasive WBG metrology has been based on the adaptation of a Si IC production proven electrical characterization method [1], realized with corona charge, , biasing of the surface and measuring the surface voltage, V , with a vibrating Kelvin probe. The commercial tool, CnCV (Corona noncontact Capacitance Voltage), initially intended for SiC, was introduced by Semilab SDI in 2017 [2]. With a continuously refined performance, the applicability of the CnCV tool expanded to other WBG semiconductors, including AlGaN/GaN HEMT structures and as discussed in this work. The technique can also be applied to other WBG material with a bandgap above such as GaN, AlN, BN and diamond.
A noncontact characteristic in CnCV is generated using differential capacitance, and the doping is determined from vs. V. Rapidly growing mass production of WBG wafers has created a special demand for increasing the throughput in CnCV measurements. In standard CnCV , the multi-step charge deposition and the wafer transfer back and forth for voltage measurement limits the measurement speed and wafer throughput.
New breakthrough improvements of throughput were initiated in 2023 with the discovery of the Kinetic mode [3]. This mode utilizes illumination-induced photoneutralization of the coronadeposited surface charge instead of multi-step deposition. Doping determination using the Kinetic mode is based on the discovery that the photoneutralization time constant, , provides a measure of the dopant concentration. The values can be adjusted by illumination intensity to a fraction of a second range, producing a fast dopant measurement and a corresponding enhancement of the monitoring throughput [3]. Both CnCV and Kinetic are considered quasi-static techniques with measurement frequencies in the 1 to 2 Hz range. Recent advancements in the noncontact
characterization and especially the measurement speed and throughput reported in this work include applications of the Kinetic mode to and to a new method for characterization of AlGaN/GaN HEMT structures.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1157.49.pdf

Two measurement applications addressed in the present study include: 1. Dopant concentration, ND, in epitaxial, n-type , and 2. Electrical parameters of HEMT structures with a two-dimensional electron gas, 2DEG.
The measurements were performed in a CnCV tool enabling the standard multi-step corona charging based characterization and the novel Kinetic mode characterization. For the latter one the CnCV tool was modified by the addition of a short wavelength ultra-violet LED light source with a peak wavelength of 255 nm (photon energy about 4.9 eV ), suitable for generation of free electron-hole pairs in and in a barrier layer of the HEMT structure used in this study.
The schematic illustration of the experimental apparatus is shown in Fig. 1. The measured wafer is placed on a moveable stage. The key elements include: (a) the corona charge, , deposition station, (b) the surface voltage, V , measuring Kelvin probe 2 mm in diameter and (c) the LED sources of UV illumination. The illumination can be performed under the probe simultaneously with measuring of V or at a separate location.

Fig. 1. Schematic illustration of the measurement bay apparatus used for the present study.

Fig. 1. Schematic illustration of the measurement bay apparatus used for the present study.

In the comparative study performed in this work, the novel measurements with an illuminationinduced charge sweep and the standard CnCV measurements were performed on the same wafer locations. Accordingly, the CnCV apparatus included wafer prealigning and robotic handling for precise and repeatable wafer positioning. These elements are not shown in Fig. 1.
An enclosure for the measurement bay is used to prevent stray light from reaching the wafer and interfering with the precise illumination induced corona charge sweep. Further details of the hardware arrangement and the CnCV technique are available in references [1-3].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1157.49.pdf

Kinetic mode doping characterization in . The measuring sequence used for is similar to previously described measurements on n-type SiC [3]. Accordingly, as the first step, a single negative corona charging to deep depletion V is performed in the dark. Subsequently, the charged
region is positioned under the Kelvin probe and the surface voltage (i.e. the depletion voltage in this case) is briefly measured in the dark as a verification of the deposited charge stability. It is followed by UV illumination with a wavelength of 255 nm causing photoneutralization of the corona charge. The illumination is realized in short 10 ms pulses with the voltage value monitored after each pulse. The resulting depletion voltage decay is shown in Fig. 2 together with the photoneutralization Kinetic plot used for determination of the time constant, .
The process of charge photoneutralization in the deep depletion condition is illustrated in Fig. 3. The effect is caused by photons generating electron-hole pairs within the depletion layer, . The positive holes drift to the surface in the depletion electric field and neutralize the negative corona ions. The depletion layer shrinks during illumination in response to the charge photoneutralization. The shrinking depletion layer decreases the generation of free carriers. It also decreases the depletion layer electric field and affects the drift of photogenerated carriers. As a result, the decay of the depletion voltage is nonlinear and fitting for the determination of the time constant, , is performed with the function. The time constant, , obtained from the inverse slope constitutes a doping index, i.e, a measure of doping in arbitrary units [3]. After calibration is performed for a given illumination condition (wavelength and photon flux), the value is transformed into the actual dopant concentration as where is the calibration function [3]. In Fig. 2 the procedure gives .

Fig. 2. Kinetic charge photoneutralization characteristic for n-type b- with 10 ms light pulses .

Fig. 2. Kinetic charge photoneutralization characteristic for n-type b- with 10 ms light pulses .

Fig. 3. Illustration of the corona charge photoneutralization.

Fig. 3. Illustration of the corona charge photoneutralization.

In CnCV tools the calibration of vs. can be performed using actual dopant concentration measured with the standard 1/C method. This capability is used in the present application of the Kinetic mode to -type .
The results in Fig. 2, Fig. 4, and Fig. 5 confirm the applicability of the Kinetic mode for doping measurement in . The high precision of the measurement is demonstrated by repeatability with a average of obtained in 10 repeats as seen in Fig. 4. In addition, the results in Fig. 5 show a 9 pt wafer scan completed with the Kinetic mode in only 3 min . This includes wafer loading and unloading and it would correspond to a throughput of about 20 wafers per hour, meeting industry requirements. The Kinetic results in Fig. 5 show agreement with standard CnCV doping measurements with the method on the same wafer sites. The standard measurement time of 12 mins corresponds to a throughput of only 5 wafers per hour.

Fig. 4. Kinetic mode repeatability of for n type .

Fig. 4. Kinetic mode repeatability of for n type .

Fig. 5. 9pt scan across the diameter of a n-type wafer comparing novel Kinetic mode and standard CnCV results.

Fig. 5. 9pt scan across the diameter of a n-type wafer comparing novel Kinetic mode and standard CnCV results.

Characterization of AIGaN/GaN structure. The HEMT structure is schematically illustrated in Fig. 6 for the initial state (A) and after negative corona charging (B), respectively. The corresponding energy band diagrams are shown in Fig. 7. The initially populated 2DEG is a consequence of the strong piezoelectric polarization induced by a lattice mismatch between the top layer and the underlying GaN channel layer [4]. A strong electric field created by polarization directs free electrons from the AlGaN to the 2DEG. The AlGaN barrier layer with a large energy gap, about 4 eV , becomes depleted of free carriers and it can retain, very well, the negative corona charge deposited on the surface. The prescribed large dose negative corona deposition on the surface is used to depopulate the 2DEG as illustrated in Fig. 6B and Fig. 7B. This is the first biasing step in the active layer characterization cycle.

Fig. 6. AlGaN/GaN structure in the initial state (A) and with the 2 DEG depopulated by negative corona charge (B).

Fig. 6. AlGaN/GaN structure in the initial state (A) and with the 2 DEG depopulated by negative corona charge (B).

Fig. 7. The energy band diagram of AlGaN/GaN structure corresponding to Fig. 6.

Fig. 7. The energy band diagram of AlGaN/GaN structure corresponding to Fig. 6.

After that, the standard CnCV method uses a positive multi-step corona charging sequence repopulating the 2DEG back to the initial condition. The surface voltage is measured after each charging step. Corona charging cannot be performed under the Kelvin probe. Accordingly, the incremental charging sequence includes wafer transfer to the Kelvin probe and back to the charging position. The resulting AlGaN/GaN characteristic is shown in Fig. 8. It provides a means to determine the active layer parameters. However, it is too slow for industrial needs.
The novel approach replaces the positive charging sequence with a rapid illumination-induced photoneutralization of the negative corona charge. The advantage of illumination is that it can be realized under the probe simultaneously with the surface voltage measurement. The results shown in Fig. 9 are obtained 20 times faster than the standard results in Fig. 8.
The results in Fig. 8 and Fig. 9 show a striking similarity. This demonstrates that for the AlGaN/GaN HEMT structure the time of illumination in the photoneutralization sweep is equivalent to the corona charge density, , in the multi-step return of the 2DEG to the initially populated condition. This similarity is supported by the modeling of the photoneutralization process illustrated in Fig. 10. A significant difference compared to the deep depletion case in Fig. 3 is that the AlGaN barrier layer thickness is constant during the process, unlike the shrinking depletion width.
In the model in Fig. 10, the photons with 4.9 eV energy absorbed in the AlGaN barrier layer with a 4 eV energy gap generate electron hole pairs, . The positive holes are directed to the surface and neutralize the corona ions . The free electrons drift to the interface and increase the population of 2D electron gas, .
The thickness of the depleted AlGaN barrier layer (about 20 nm ) does not change during the charge sweep. Accordingly, the generation rate of electron-hole pairs in the barrier remains constant. In addition the strong polarization field assures effective carrier drift during the entire process. The above conditions lead to a linear illumination-induced charge sweep unique for the AlGaN/GaN HEMT structure and different than the exponential charge sweep in the surface depletion layer used for the doping measurement.

Fig. 8. Standard CnCV sequential corona charging results illustrating the extraction of AlGaN/GaN HEMT parameters.

Fig. 8. Standard CnCV sequential corona charging results illustrating the extraction of AlGaN/GaN HEMT parameters.

Fig. 9. Novel charge sweep results illustrating the extraction of AlGaN/GaN HEMT structure parameters.

Fig. 9. Novel charge sweep results illustrating the extraction of AlGaN/GaN HEMT structure parameters.

Fig. 10. Illumination-induced neutralization of corona charge on the AlGaN/GaN surface and corresponding repopulation of the 2 DEG .

Fig. 10. Illumination-induced neutralization of corona charge on the AlGaN/GaN surface and corresponding repopulation of the 2 DEG .

The much shorter measurement time in Fig. 9 is a consequence of the rapid illumination-induced charge sweep, about 20 times faster than the charge-transfer-measure sequence in Fig. 8. In both techniques the pinch-off voltage is determined as the intercept voltage between the different slope lines and the results are very similar. The low slope line corresponds to the depleted 2DEG while the high slope corresponds to the populated 2DEG, respectively. This procedure for determining the pinch-off voltage is adopted from the HEMT characterization with mercury probe CV described by E. Tucker et al. [5]. The determination of the AlGaN layer thickness using the slope value of the charge-voltage line, (i.e. the structure capacitance, Снемт) in the range where the 2DEG is populated is also adopted from ref [5]. The capacitance of the AlGaN layer, , and that of the 2DEG, , are connected in series. For a sufficiently large 2DEG population, , the CalGan dominates the total capacitance which becomes a measure of the AlGaN thickness.
In the novel method, a calibration quantifying the time of the linear sweep vs. corona charge is used in the determination of the capacitance and the corresponding AlGaN thickness. The new measurement of the pinch-off voltage, , is calibration free.
The results of repeated Kinetic mode measurements of the pinch-off voltage are given in Fig. 11. These results indicate a relative value of in ten repeats. This can be treated as an indication of the good precision of the measurement.
In the actual Kinetic mode measurement cycle, the calibration can be performed using the precise insitu measured value of the negative corona charge, , in the first 2DEG depopulating step. The calibration factor where is the sweep time interval required to return the 2DEG to the initial precharging condition. This initial condition in the method is defined by the initially measured surface voltage value, .
The calibration factor depends on the specific illumination condition, the photon flux and the wavelength. In the novel characterization approach, increasing the photon flux provides a practical means for increasing the speed of the measurement and the wafer measurement throughput.
The enhanced speed of the measurement is especially beneficial for whole wafer uniformity testing, such as the 49 pt map shown in Fig. 12. This map can be obtained in 20 minutes compared to the 3.5 hours required in the previous standard CnCV testing of the wafer uniformity.

Fig. 11. Kinetic mode measurement repeatability for HEMT structure.

Fig. 11. Kinetic mode measurement repeatability for HEMT structure.

Fig. 12. 49pt Kinetic mode pinch-off voltage, , map for HEMT. There is an order of magnitude improvement in throughput for the Kinetic mode compared to standard CnCV.

Fig. 12. 49pt Kinetic mode pinch-off voltage, , map for HEMT. There is an order of magnitude improvement in throughput for the Kinetic mode compared to standard CnCV.

It is a quite unique feature of the new technique that the capacitance-voltage characteristic in arbitrary units can be generated by differentiation of the ( ) data set as . Using the calibration factor , the is converted to the actual capacitance, , enabling a direct quantitative comparison with standard C-V measurement results. Such a comparison presented in Fig. 13 demonstrates excellent agreement between the novel and standard method and confirms the validity of the novel high throughput AlGaN/GaN structure characterization. According to recent studies, this technique of capacitance determination can be extended to doping measurements on other wide bandgap material such as SiC including multilayer epi structures [6].

Fig. 13. CV characteristics from both the a) Standard CnCV and b) novel illumination-induced charge sweep methods for the AlGaN/GaN HEMT structure Q-V and til-V results in Figs. 8 and 9.

Fig. 13. CV characteristics from both the a) Standard CnCV and b) novel illumination-induced charge sweep methods for the AlGaN/GaN HEMT structure Q-V and til-V results in Figs. 8 and 9.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1157.49.pdf

A high throughput noncontact electrical characterization technique based on sweeping of the electrical charge bias by UV illumination is found applicable for high precision doping measurement of large energy gap b- . The most recent advancement of the technique is demonstrated for AlGaN/GaN HEMT structures wherein the time of the UV illumination-induced charge sweep, til, is found to constitute a unique charge index and together with the surface voltage gives the derivative capacitance of the active layer as . Upon in-situ calibration these quantities and corresponding voltage characteristics provide a novel means for determination of the critical active layer parameters such as thickness and with wafer testing throughput as high as 20 wafers per hour.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.49.pdf

D.K. Schroder, Chapter 9: Charge-based and Probe Characterization, in: Semiconductor Material and Device Characteristics, Wiley-Interscience, Hoboken, New Jersey, 2006, p. 523.

M. Wilson, A. Findlay, A. Savtchouk, J. D'Amico, R. Hillard, F. Horikiri and J. Lagowski, "Review-Recent Advancement in Charge- and Photo-Assisted Non-Contact Electrical Characterization of SiC, GaN, and AlGaN/GaN HEMT," ECS Journal of Solid State Science and Technology, 6(11) S3129 (2017).

M. Wilson, J. Lagowski, C. Almeida, B. Schrayer, and A. Savtchouk, "Semiconductor doping characterization method using photoneutralization time constant of corona surface charge", US Patent Granted US12027430B1, Publication Date July 2, 2024.

H. Umeda, Chapter 19.2: GaN Epitaxy on Si Substrate, in: Wide Bandgap Semiconductors for Power Electronics vol. 2, Wiley-VCH GmbH, Weinheim, Germany, 2022, p. 563.

E. Tucker, F. Ramos, S. Frey, R. Hillard, P. Horváth, G. Zsákai, and A. Márton, "Characterization of AlxGa1-xN/GaN High Electron Mobility Transistor Structures with Mercury Probe Capacitance-Voltage and Current-Voltage," Phys. Status Solidi A, 2100416 (2022).

M. Wilson, J. Lagowski, I. Shekerov, C. Almeida, B. Schrayer, L. Gutierrez and A. Wincukiewicz, "Wide Bandgap Semiconductor Characterization Based on Capacitance Characteristics Acquired Using Corona Surface Charge Neutralization by UV Radiation Pulses," US Patent Pending 02695-0058001, submitted May 2025.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 57-62

doi: 10.4028/p-3NYGzu

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-04-16

Accepted:
2025-04-16

Online:
2025-09-05

Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

The original version of this paper is available on https://www.scientific.net/MSF.1157.57.pdf

Kohei Toda , Kazuya Kiritani , Daichi Dojima , and Tadaaki Kaneko

Kwansei Gakuin University, 1, Gakuen Uegahara, Sanda, Hyogo, 669-1330, Japan

QureDA Research, Inc., 1, Gakuen Uegahara, Sanda, Hyogo, 669-1330, Japan

E-mail: k.toda@kwansei.ac.jp, k.kiritani@kwansei.ac.jp, d.dojima@kwansei.ac.jp, dkaneko@kwansei.ac.jp

Keywords: Surface planarization, Sublimation etching, Lapping, Macro step bunching, Step tension, CMP-free, Sub-surface damage

Abstract

In this study, we developed two planarization mechanisms, macroscopic and microscopic, controlled by adjusting the C/Si ratio during Dynamic AGE-ing (DA) sublimation etching. Using these mechanisms, we planarized rough wafers without the use of chemical mechanical polishing (CMP). Macro planarization forms macro step bunching (MSB) using high C/Si ratio DA etching, straightens the steps using step tension, and removes scratch marks caused by mechanical processing. Microscopic planarization involves debunching these MSBs using low C/Si ratio DA etching. It was observed that debunching progressed more quickly on wafers before CMP finishing due to the higher density of MSBs with ramified structures, which serve as starting points for debunching. The rate at which the MSB is shortened by step debunching increases with rising temperature, reaching about at . By utilizing these mechanisms, we achieved highquality planarization (initial ) to for 6-inch 4H-SiC wafers that had not undergone CMP. Furthermore, by performing DA sublimation growth on this planarized wafer, we achieved an in-grown stacking fault (IGSF) density of and a basal plane dislocation (BPD) to threading edge dislocation (TED) conversion ratio of 99.95 %.

Introduction

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In the manufacturing of wafers, mechanical processing is expensive and introduces SSD due to abrasive contact during processing from SiC boules to wafers [1]. SSD leads to BPD propagation and IGSF formation during epitaxial growth, which impair device reliability [2, 3]. To remove SSD and achieve a surface roughness of , a stepwise process involving slicing, grinding/lapping, and CMP is commonly employed. In the later stages of the machining process, the higher the precision required, and thus the higher the cost. In addition, it has been reported that SSD is not completely removed even after CMP. Therefore, developing a process that can replace the later stages of the machining process with and remove SSD is a significant breakthrough.

Alternatives to CMP, such as plasma etching, efficiently remove damaged layers by preferentially etching weakly damaged areas [4,5]. However, this results in surfaces with and large undulations, which can promote BPD propagation and IGSF formation in the epitaxial layer. Thermal etching, utilizing sublimation at high temperatures, is another non-contact method considered for replacing mechanical polishing.

To control surface morphology using thermal processes, understanding the step terrace structure of surfaces is essential. wafers are cut with a off-cut in the [11-20] direction from the (0001) plane to induce step-flow growth, forming step terrace structures. The minimum step height after thermal processing is 0.5 nm (half-unit cell height), but steps with a full unit cell height of 1 nm are more stable. MSBs with many steps bunched together increase surface roughness. Hydrogen etching, a common thermal etching method in CVD process, increases MSB with etching
depth [6]. Once formed, MSBs are stable and difficult to debunch. Therefore, replacing the machining process with a thermal process while ensuring sufficient flatness is challenging.

We previously reported for the first time that MSBs can be debunched into steps of about 1 nm in height by thermal sublimation etching on on-axis and off-axis substrates under controlled C/Si ratio and high temperature environment. The sublimation process called Dynamic AGE-ing (DA) enables precise control of surface morphology, achieving both flat and MSB-formed surfaces, regardless of etching depth and grown layer thickness at temperatures between [7]. The DA sublimation etching and growth of single crystal SiC wafer is performed in a quasi-closed polycrystalline SiC container, driven by a slight temperature gradient. It can etch more than of material while maintaining surface flatness, effectively planarizing rough wafer surfaces. Thus, SSD introduced by machining process can be removed, and the surface can be planarized simultaneously.

By varying temperature, pressure, and C/Si ratio in DA, different surface morphologies can be achieved, enabling macroscopic and microscopic planarization. Macroscopic planarization occurs at high temperatures above and high pressures above 1 kPa or under SiC-C phase-equilibrium environment (PE) with high C/Si ratio, forming large step bunching with heights of several tens to hundreds of nanometers. As these large steps sweep across the surface, they effectively planarize rough surfaces by slicing, glinding, and DP [8]. Microscopic planarization performed under SiC-Si PE with low C/Si ratio can debunch MSBs of several 10 nm to 1 nm . We have reported that using the DA process with SiC-Si PE, CMP-finished and MSB-formed surfaces with Ra can be reduced to . We have also reported that wafers after mechanical slicing with Ra can be reduced to by a process combining DA process in a high temperature and pressure environment, SiC-C PE, and SiC-Si PE [9].

One issue with replacing machining process with DA is the undefined initial surface roughness range that can achieve . To define and expand this controllable range, it is essential to elucidate the physical mechanisms of macroscopic and microscopic planarization and to control the surface accordingly. In this study, to elucidate the mechanism of planarization in thermal sublimation etching, we observed the MSB decomposition process by forming MSBs on surfaces in different initial machining states and debunching by slight DA etching with SiC-Si PE.

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1157.57.pdf

For the macroscopic planarization experiment, we used off n-type substrates cut into small pieces of , which had undergone CMP finishing ( ) and DP ( nm ) finishing. DA method with SiC-Si PE and SiC-C PE under ultra-high vacuum was conducted at temperatures of process times. In the experiment to observe the MSB decomposition rate, an inverted mesa structure (depth: , width: ) was created on a substrate where MSBs had formed, using a 532 nm pulsed laser. A -inch DP-finished wafer polished with loose abrasives was used to investigate defect reduction. The surface morphology of microscopic areas from several tens of nanometers to several microns was evaluated by SEM, macroscopic areas of several millimeters by laser microscopy, and the entire wafer surface by Laser light scattering (LLS). The surface roughness value Ra was calculated from AFM images ( . The etch-pit method was used molten alkali as the defect detection method. After measuring the etch pits using an optical microscope, crystal defects were detected using an object detection AI.

Results

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Figs. 1 (a), (b) and Figs. 2 (a), (b) show SEM and laser microscope images of the CMP- and DPfinished substrates, respectively. SEM and laser microscope images revealed that the CMP-finished substrate was very flat ( ), whereas the DP-finished substrate was a rough surface ( . SEM and laser microscope images after DA etching with SiC-Si PE on the CMP- and DPfinished substrates are shown in Figs. 1 (c)-(f) and Figs. 2 (c)-(f). A flat surface with a height of about 1 nm was observed on the CMP-finished substrate after DA etching with SiC-Si PE. On the other hand, MSB was observed on the DP-finished substrate, which was confirmed by laser microscopy
and showed residual scratch marks. The surface morphology of the substrate was hardly changed after additional DA etching with SiC-Si PE.

Next, SEM and laser microscope images of DA etching with SiC-C PE on the CMP- and DPfinished substrates are shown in Figs. 1 (g), (h) and Figs. 2 (g), (h). On these substrates, MSBs with a height of approximately 10 nm were observed. DA etching with was used to debunch MSBs formed on CMP- and DP-finished substrates by DA etching with SiC-C PE. MSBs formed on the CMP-finished substrate remained after DA etching with SiC-Si shown in Figs. 1 (i) and (j). On the other hand, MSBs formed on the DP-finished substrate were not observed after DA etching with SiC-Si PE, resulting in a flat surface with steps of about 1 nm in height across the entire substrate area Figs 2 (i) and (j). The results suggest that the surface morphology of the initial substrate makes a difference in the ease of debunching of the MSBs. Fig. 1 (k) and Fig. 2 (k) show that the optimal treatment method depends on the initial surface morphology. For very flat surfaces such as CMPfinished substrates, DA etching with is optimal. On the other hand, for rough surfaces such as DP-finished substrates, it was indicated that a flat surface can be obtained by uniformly roughening the entire surface with MSB prior to DA etching with SiC-Si PE.

We investigated the differences in MSBs formed in SiC-C PE due to the different initial substrates. SEM images of DA etching with SiC-C PE on the CMP- and DP-finished substrates are shown in Figs. 3 (a) and (b). MSB formed on the DP-finished substrate showed many ramified structures. On the other hand, no ramified structure was observed in the MSBs formed on the CMP-finished

Fig. 1. (a)-(j) SEM and laser microscope images of (0001) substrates after CMP and DA etching under various SiC-Si and SiC-C PE. (k) the dependence of the etching depth on surface roughness of CMP-finished surface.

Fig. 1. (a)-(j) SEM and laser microscope images of (0001) substrates after CMP and DA etching under various SiC-Si and SiC-C PE. (k) the dependence of the etching depth on surface roughness of CMP-finished surface.

Fig. 2. (a)-(j) SEM and laser microscope images of (0001) DP-finished substrates and after each DA etching under SiC-Si and SiC-C PE conditions. (k) The dependence of DA etching depth on surface roughness of DP-finished substrate.

Fig. 2. (a)-(j) SEM and laser microscope images of (0001) DP-finished substrates and after each DA etching under SiC-Si and SiC-C PE conditions. (k) The dependence of DA etching depth on surface roughness of DP-finished substrate.

substrate. The ramified structure is considered to affect MSB decomposition. Therefore, we performed DA etching with SiC-Si PE (etching depth: ) on the substrates containing MSBs with and without ramified structures. The same locations were observed using SEM on these substrates before and after the treatment. (Figs. 4 (a)-(d)). The MSBs with ramified structures are decomposed starting from the structures, which MSBs shortened toward . On the other hand, most of the MSBs without the structures remained after DA etching. It is noted that MSBs without the structures were also decomposed as a rare case.

To investigate the frequency of MSB decomposition, we observed 200 MSBs formed on DPfinished substrates at the same locations before and after DA etching with SiC-Si PE (etching depth: ). Among these, there were 68 MSBs with ramified structures, of which 46 decomposed, indicating that of these steps bunching decomposed. In contrast, among the 132 MSBs without ramified structures, 25 decomposed due to SiC-Si PE, showing that of these steps bunching

Fig. 3. SEM image of MSB formed on (a) CMP-finished substrate by DA etching with SiC-C PE and (b) DP-finished substrate with by DA etching SiC-C PE.

Fig. 3. SEM image of MSB formed on (a) CMP-finished substrate by DA etching with SiC-C PE and (b) DP-finished substrate with by DA etching SiC-C PE.

Fig. 4. SEM images of substrates with MSBs before and after DA etching with SiC-Si PE. (a), (b) MSB with ramified structure. (c), (d) MSBs without ramified structure.

Fig. 4. SEM images of substrates with MSBs before and after DA etching with SiC-Si PE. (a), (b) MSB with ramified structure. (c), (d) MSBs without ramified structure.

Fig. 5. (a) SEM image of the MSBs formed edges by a laser. (b) SEM image of the same location as in (a) after DA etching with SiC-Si PE. The MSB decomposition rate to [1-100] with respect to (c) etching temperature and (d) etching depth.

Fig. 5. (a) SEM image of the MSBs formed edges by a laser. (b) SEM image of the same location as in (a) after DA etching with SiC-Si PE. The MSB decomposition rate to [1-100] with respect to (c) etching temperature and (d) etching depth.

decomposed. Therefore, it was found that when the MSB has an edge, such as the ramified structure, the decomposition of the MSB progresses sequentially from the edge toward the <1-100> direction.

To investigate the temperature dependence of MSB decomposition, a laser was applied to the MSBformed substrate to create an edge on the MSB, which was then DA-etched with SiC-Si PE. Figs. 5 (a) and (b) shows SEM images of the same location before and after DA etching with SiC-Si PE, where the laser was applied. The relationship between the MSB decomposition rate toward [1-100] direction and temperature is shown in Fig. 5 (c), and the relationship between MSB decomposition length and etching depth is shown in Fig. 5 (d). MSB decomposition proceeded faster at higher temperatures and with increasing etching depth.

We have reported an epitaxial defect-free process for CMP-finished substrates by controlling the surface morphology before and after epitaxial growth [7]. This approach required a pre-growth surface roughness of , which posed challenges for DP-finished substrates. The planarization process in this study removed the scratch marks from the substrates, making it possible to fabricate the very flat surface consisting of steps with a height of about 1 nm . Therefore, using the planarization process described above, we attempted surface planarization and epi-defect reduction on the DP-finished -inch wafers. Figs. 6 (a)-(c) shows the AFM, SEM, and LLS images of the DPfinished wafer. Scratch marks were observed on the wafer ( ). Figs. shows the AFM, SEM, and LLS images of the wafer after the planarization process in this study. The processed wafers were observed to have a flat surface with and no scratch marks. This shows that these planarization processes can be adapted to wafers. After the planarization, DA growth in SiC-C PE was performed to create epi-defect-free grown layer. Fig. 7 (a) shows the BPD distribution on a DP-finished 6-inch wafer before DA process. The density was . Fig. 7 (b) and (c) show the BPD and IGSF distributions after DA planarization process and DA growth. The BPD and IGSF densities were and , respectively. of BPDs were successfully converted into TED. The defect density was less than that of direct DA growth on the CMP-finished wafer as shown in Fig. 7 (d) and (e) (BPD density: , IGSF density: ).

Fig. 6. (a) Laser light scattering (LLS), (b) SEM, and (c) AFM images of the DP-finished 6-inch wafer. (d) LLS, (e) SEM, and (f) AFM images of the wafer after DA planarization process.

Fig. 6. (a) Laser light scattering (LLS), (b) SEM, and (c) AFM images of the DP-finished 6-inch wafer. (d) LLS, (e) SEM, and (f) AFM images of the wafer after DA planarization process.

Fig. 7. (a) BPD map visualized by KOH melt etching of DP-finished inch . (b) BPD and (c) IGSF maps of the wafer after DA planarization process and DA growth. (d) BPD and (e) IGSF distributions when DA growth was performed directly on the CMP-finished wafer.

Fig. 7. (a) BPD map visualized by KOH melt etching of DP-finished inch . (b) BPD and (c) IGSF maps of the wafer after DA planarization process and DA growth. (d) BPD and (e) IGSF distributions when DA growth was performed directly on the CMP-finished wafer.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1157.57.pdf

In this study, macroscopic and microscopic planarization mechanisms were established through the controlled adjustment of the C/Si ratio during DA sublimation etching. Utilizing these approaches, we were able to planarize rough wafers without CMP . Macroscopic planarization was achieved by inducing MSB via DA etching with high C/Si ratio and eliminated scratch marks resulting from machining process. Microscopic planarization was accomplished by DA etching with low C/Si ratio. MSB debunching process occurred more rapidly on wafers prior to CMP, a phenomenon attributed to the higher density of MSBs with ramified structures that serve as initiation sites to debunch. Moreover, the rate at which the MSBs were shortened by step debunching increased with temperature, reaching approximately at . By employing these mechanisms, high-quality planarization was achieved for -inch wafers, reducing the roughness ( to 0.18 nm without CMP. Furthermore, DA sublimation growth on these planarized wafers resulted in an IGSF density of and a BPD to TED conversion ratio of 99.95 %.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1157.57.pdf

This work was supported by Toyota Tsusyo Corporation for technical support and EpiQuest, Inc. for equipment support.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.57.pdf

H. Sako, H. Matsuhata, M. Sasaki, M. Nagaya. T. Kido, K. Kawata, T. Kato, J. Senzaki, M. Kitabatake and H. Okumura, Micro-structural analysis of local damage introduced in subsurface regions of wafers during chemo-mechanical polishing, J. Appl. Phys. 119 (2016) 135702.

T. Hosoi, K. Konzono, Y. Uenishi, S. Mitani, Y. Nakano, T. Nakamura, T, Shimura and H, Watanabe, Investigation of Surface and Interface Morphology of Thermally Grown SiO2 Dielectrics on 4H-SiC (0001) Substrates. Mater. Sci. Forum. 679 (2011) 342-345.

K. Toda, D. Dojima, K. Kojima, H. Mihara, S. Mitani and T. Kaneko, Suppression of In-grown SF Formation and BPD Propagation in 4H-SiC Epitaxial Layer by Sublimating Sub-surface Damage before the Growth, Solid State Phenom. 344 (2023) 9-14.

Information on

M. A. Mathews, A. R. Graves, D. R. Boris, S. G. Walton, C. D. Stinespring, Plasma assisted remediation of SiC surfaces, J. Appl. Phys. 135 (2024) 153301.

Y. Ishida, T. Takahashi, H. Okumura, K. Arai, S. Yoshida, Origin of giant step bunching on 4H-SiC (0001) surfaces, Mater. Sci. 600 (2009) 473-476.

D. Dojima, K. Tayake, K. Shigematsu, K. Toda, and T. Kaneko, Macro Step Bunching/Debunching Engineering on off (0001) to Control the BPD-TED Conversion Ratio by Dynamic AGE-ing , Defect and Diffusion Forum (2024) 165-172.

T. Kaneko, presented at the International Conference on Silicon Carbide and Related Materials (Tu-P-09), Kyoto International Conference Center, Kyoto, Japan, 2019(unpublished).

K. Toda, D. Kakutani, D. Dojima, Y. Nakajima, H. Mihara, and T. Kaneko, A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes, Mater. Sci. Forum. (2024) 77-84.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 63-68

doi: 10.4028/p-QKqx1y

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-05-19

Accepted:
2025-05-19

Online:
2025-09-05

The Application of Dynamical Thermal Annealing Processes after Mechanical Slicing as an Integrated Contactless SiC Wafering Method to Control Crystal Defects

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

Kohei Toda , Daichi Dojima , Yuta Nakajima , Hiroshi Mihara and Tadaaki Kaneko

Kwansei Gakuin University, 1, Gakuen Uegahara, Sanda, Hyogo, 669-1330, Japan

QureDA Research, Inc., 1, Gakuen Uegahara, Sanda, Hyogo, 669-1330, Japan

k.toda@kwansei.ac.jp, d.dojima@kwansei.ac.jp, yuta_nakajima@qureda-research.com, dhiroshi_mihara@qureda-research.com, ekaneko@kwansei.ac.jp

Abstract

We have developed a novel, material-lossless silicon carbide (SiC) wafer manufacturing process that eliminates the need for conventional grinding and polishing. Utilizing a thermal sublimation growth and etching technique called Dynamic AGE-ing (DA), we simultaneously performed thermal sublimation etching and growth on both the Si-face and C-face of single-crystal SiC wafers. This study investigated the impact of surface undulations-arising during DA planarization of as-sliced wafers with varying slicing qualities-on the densities of basal plane dislocations (BPDs) and in-grown stacking faults (IGSFs) in the epitaxial layers. Our findings demonstrate that larger pre-growth surface undulations correlate with higher BPD and IGSF densities in the DA-grown layers. By optimizing the initial wafer quality and DA process conditions, we achieved epitaxial layers with low defect densities (BPD density of and IGSF density of ) without any material loss. This advancement offers a significant breakthrough in SiC device manufacturing, potentially reducing material costs and enhancing device performance by suppressing killer defects in the epitaxial layers.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

In improving the yield of devices using high-cost materials, it is crucial to reduce material loss during wafer surface planarization processes and suppress killer defects in the epitaxial growth process. Generally, wafers sliced from SiC boules undergo mechanical processing such as lapping, grinding, and chemical mechanical polishing (CMP) to enhance flatness and remove subsurface damage (SSD) introduced due to contact between the surface and abrasive grains during slicing. In this process, approximately (about ) of material loss occurs when producing a thick wafer, necessitating efforts to reduce this loss.

Moreover, while CMP-finished wafers exhibit extremely high flatness with , elastic strain that decreases exponentially over several micrometers across the entire wafer remain as SSD. We have reported that this elastic strain causes the formation of in-grown stacking faults (IGSF) and the propagation of basal plane dislocations (BPD) into the epitaxial growth layer [1]. These defects lead to the deterioration of electrical properties during device operation [2]. Therefore, a thermal process that can achieve flatness equivalent to CMP-finished wafers from as-sliced SiC wafers without material loss, and further enable the growth of epitaxial layers without killer defects, would represent a significant breakthrough in SiC device manufacturing processes.

We are attempting to develop a novel, material-lossless SiC wafer manufacturing process that is free from grinding and polishing, using a thermal sublimation growth and etching process called Dynamic AGE-ing (DA) [3]. DA is a process capable of simultaneously performing thermal sublimation etching or growth on both sides (Si-face and C-face) of a single-crystal SiC wafer (Fig. 1). The single crystal SiC wafer is placed inside a semi-closed polycrystalline SiC container, and heating it forms a phase equilibrium (PE) environment inside. Under this environment, a slight

Fig. 1. Schematic diagram of simultaneous control of both sides (Si-face, C -face) of SiC wafer by DA. Since the amount of DA-etching on the Si-face and the amount of DA-growth on the C-face are equivalent, the total thickness of the wafer remains the same before and after DA.

Fig. 1. Schematic diagram of simultaneous control of both sides (Si-face, C -face) of SiC wafer by DA. Since the amount of DA-etching on the Si-face and the amount of DA-growth on the C-face are equivalent, the total thickness of the wafer remains the same before and after DA.

temperature gradient serves as the driving force, causing sublimation growth on the higher temperature side of the wafer and sublimation etching on the lower temperature side. The notable aspect of this method is that by etching one side (Si-face) while simultaneously growing the backside (C-face) at the same rate, it is possible to eliminate material loss during the process. There are three types of DA process conditions depending on the SiC wafer surface planarization method: DA annealing, which maximizes the self-organization effect under high temperature ( ) and high back pressure ( ); SiC-C PE, which utilizes macro step bunching (MSB); and SiC-Si PE, which can debunch step bunching to the full unit cell height of , which is 1 nm . Here, SiC-C PE and represent environments with high C/Si ratio and low C/Si ratio, respectively, controlled by the introduction of Si supply materials [4].

We have demonstrated that by sequentially applying these processes-DA-annealing, SiC-C PE, and SiC-Si PE-a multi wire saw (MWS) as-sliced SiC wafer with an initial roughness of can be planarized to after DA-annealing, then to after SiC-C PE etching, and finally to after etching [3]. On the other hand, when using a CMP-finished surface as the initial surface, a surface flatness of Ra can be achieved after DA-etching in a SiC-Si PE environment [4]. In this case, using DA-growth, we have demonstrated a BPD-to-TED conversion rate of and an IGSF density of within an area of [2,4]. The cause of the large Ra after the planarization process when using a mechanically as-sliced SiC wafer as the initial surface is the undulations that appear on the SiC surface [3].

We refer to macro-scale uneven structures with a periodicity of several micrometers perpendicular to the steps as undulations. Undulations can form locally wide (0001) terraces, potentially causing two-dimensional nucleation that leads to defect formation. However, the cause of undulations occurring during the DA planarization process on MWS as-sliced SiC wafers and the extent of their impact on epitaxial growth remain unclear.

Therefore, in this study, we performed DA planarization processes and DA-growth on three assliced wafers (loose abrasive) with different MWS slicing qualities to investigate how the undulations present on the pre-growth surface, which depend on the initial substrate, affect the BPD and IGSF densities in the epitaxial growth layer. Furthermore, to verify the extent to which terrace length adversely affects DA-growth, we conducted DA-growth on CMP-finished low off-angle substrates and examined the growth modes that emerge.

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

In this study, we used 3 -inch and 6 -inch as-sliced wafers with a off-cut toward the [1120] direction (designated as Wafers , and C ) as samples. These wafers were sliced using a multiwire saw with loose abrasive. To measure the surface morphology of the Si -face of these wafers, we employed the laser light scattering method [5], atomic force microscopy (AFM), and scanning electron microscopy (SEM). To flatten these as-sliced wafers, we performed three DA processes (Fig. 2). First, we conducted DA-annealing (Step-1) in a high-temperature ( ) and high
backpressure ( ) environment. Next, a DA-etching process (Step-2) in SiC-C PE was performed on the Si-face at and a back pressure of . Subsequently, the DA-etching process (Step3) in SiC-Si PE was carried out under the same conditions. At this stage, AFM measurements were performed to confirm the undulations on the Si-face. Finally, we conducted DA-growth (Step-4) on the Si-face of these wafers to fabricate an epitaxial growth layer free of BPDs and IGSFs. The conditions were SiC-C PE at and a back pressure of . For the measurement of BPD and IGSF densities, we used UV photoluminescence (PL) imaging (light source: Hg-Xe lamp, excitation wavelength: 313 nm , detection filter: band-pass filter) and KOH etching ( , 6 min 20 s ). An electronic caliper was used for wafer thickness measurements.

To investigate the growth modes of DA-growth on low off-angle substrates, we used CMPfinished substrates with off-angles of on-axis, , and . DA-growth was performed in SiC-Si PE and SiC-C PE at temperatures of and , with a back pressure of . A Nomarski differential interference contrast (DIC) microscope was used to observe the surface morphology of these substrates.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

Figs. 2 (a)-(c) shows the Si-face mapping images of Wafer A, B, and C obtained by laser light scattering method. The mode values of light scattering intensity for Wafer A, B, and C were 217 mV , 3983 mV , and 3819 mV , respectively. The higher its intensity, the greater the surface roughness Ra [5]. Therefore, Wafer A is assumed to have a smaller surface roughness than Wafer B and C. After the planarization process (Step-1, 2, 3) by DA-annealing and DA-etching was performed on these three as-sliced SiC wafers, the surface of the Si -face was measured by AFM. The cross-sectional height profiles of each wafer are shown in Figs. 2 (e)-(g). The undulation was observed on the surface of these wafers. The peak-to-valley of Wafer A, B, and C are , and 21.6 nm , respectively. The surface of Wafer A is estimated to have the smallest undulation. On the other hand, in the microscopic view shown in Figs. 2 (g)-(i), these wafers have a flat surface covered with steps of 1 nm in height.

Fig. 2. (a)-(c) Mapping images of the Si-face of Wafer A, B, and C obtained by laser light scattering method. Cross-sectional height profiles (d)-(f) and SEM images (g)-(i) of the Si- face of Wafer A, B, and C after DA-etching with SiC-Si PE (Step-3).

Fig. 2. (a)-(c) Mapping images of the Si-face of Wafer A, B, and C obtained by laser light scattering method. Cross-sectional height profiles (d)-(f) and SEM images (g)-(i) of the Si- face of Wafer A, B, and C after DA-etching with SiC-Si PE (Step-3).

Then, DA-growth under SiC-C PE (Step-4) was performed on these wafers to investigate the BPD and IGSF density of the epitaxially grown layers. The defect densities of the DA-grown layers on Wafer , and C measured in the central 1inch range of the wafer were , and , respectively. The relationship between the defect densities and the peak-to-valley values of the surfaces of the Si-face after DA-etching under SiC-Si PE (Step-3) is shown in Fig. 3. According to this graph, if the undulation of the surface before its growth is large, it causes a larger BPD/IGSF density in the DA-grown layer.

Figs. 4 (a) and (b) show PL images of Wafer A before and after DA-growth under SiC-C PE (Step4). These images are in the same area. BPD observed before DA-growth is no longer observed after the growth (Step-4). The BPD and IGSF distributions of the DA-grown layer on Wafer A are shown in Figs. 4 (c) and (d), respectively. It is noted that 5 mm from the edge of the wafer is excluded. The BPD and IGSF densities for the entire wafer were and , respectively. The epitaxial layer with low defect density can be grown on as-sliced SiC wafer with loose abrasive (Wafer A) without material loss by integrating the macroscopic-scale planarization function and the microscopic surface control function of the DA process.

Fig. 3. The relationship between BPD and IGSF density of DA-grown layer and peak-to-valley after DA-etching under SiC-Si PE (Step-3).

Fig. 3. The relationship between BPD and IGSF density of DA-grown layer and peak-to-valley after DA-etching under SiC-Si PE (Step-3).

Fig. 4. (a), (b) PL images of Wafer A after DA-etching under SiC-Si PE (Step-3) and DA-growth under SiC-C PE (Step-4). (c) BPD and (d) IGSF distributions of DA-grown layer on Wafer A.

Fig. 4. (a), (b) PL images of Wafer A after DA-etching under SiC-Si PE (Step-3) and DA-growth under SiC-C PE (Step-4). (c) BPD and (d) IGSF distributions of DA-grown layer on Wafer A.

Fig. 5 shows the variation of total thickness of Wafer A by DA-annealing and DA-etching for planarization, and DA-growth for epitaxial growth. The wafer total thickness increased by about 20 from to before and after these DA processes. It indicates that material loss, such as occurs in conventional machining processes for planarization, has been completely suppressed in the DA process.

Then, Fig. 6 shows Nomarski differential interference contrast (DIC) microscope images of the Si-face of on-axis and , and off-cut 4 H -SiC substrates after DA-growth at temperatures of and in both SiC-Si PE and SiC-C PE environments. Substrates with smaller offcut angles have wider terraces formed by the steps on their surfaces; therefore, during epitaxial growth under conditions with short diffusion lengths, heteropolytypes are more likely to be incorporated due to two-dimensional nucleation. Since DA-growth in SiC-C PE does not result in the incorporation of heteropolytypes even on the wide terraces of on-axis substrates, it is considered to have a very long diffusion length. Even under such growth conditions with a long diffusion length, epitaxial growth layers with high densities of BPDs and IGSFs were formed on substrates like Wafer B and C, which had large undulations after DA-etching under SiC-Si PE (Step-3). This suggests that the undulations on the SiC surface before epitaxial growth induce BPD propagation and IGSF formation into the grown layer. Therefore, it is considered that in as-sliced wafers with better surface quality after slicing, or in wafers that have undergone further mechanical processing such as lapping or grinding, it is possible to fabricate epitaxial growth layers with sufficiently low defect densities using this process.

Fig. 5. The Variation of total thickness of Wafer A during DA Processes.

Fig. 5. The Variation of total thickness of Wafer A during DA Processes.

Fig. 6. Nomarski DIC microscope images of Si-face of on-axis, off 4 H -SiC substrates after DA-growth (Temperature: ) under SiC-Si or SiC-C PE.

Fig. 6. Nomarski DIC microscope images of Si-face of on-axis, off 4 H -SiC substrates after DA-growth (Temperature: ) under SiC-Si or SiC-C PE.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

In this study, we introduced a novel, contactless silicon carbide ( SiC ) wafer manufacturing process that eliminates material loss and minimizes crystal defects by utilizing the Dynamic AGE-ing (DA) sublimation growth and etching method. We sequentially applied DA-annealing, SiC-C phase equilibrium etching, and phase equilibrium etching to as-sliced SiC wafers, achieving significant planarization without the need for grinding or polishing. Our investigation revealed a quantitative correlation between the peak-to-valley ( ) undulation heights after DA planarization, and the defect densities in epitaxial layers after DA-growth. Specifically, Wafer A had the LLS intensity of 217 mV , the P-V of 8.2 nm , and the defect density of . Wafer B showed the LLS intensity of 3983 mV , the P-V of 11.8 nm , and the defect density of , while Wafer C exhibited the LLS intensity of 3819 mV , the P-V of 21.6 nm , and the defect density of . These results demonstrate that higher initial surface roughness leads to larger surface undulations after planarization, which correlate with increased defect densities in the epitaxial layers. By optimizing the initial surface quality through improved slicing techniques that reduce LLS intensity after Step 1 and carefully controlling the DA process conditions, we successfully fabricated epitaxial layers with low defect densities (BPD density of and IGSF density of ) without any material loss on to the MWS sliced inch wafer. The total wafer thickness increased by approximately after the DA processes, confirming the absence of material loss. This innovative, material-lossless DA process holds significant promise for enhancing the yield and performance of SiC -based devices. Our findings highlight the importance of initial wafer quality and provide valuable insights into reducing material costs and suppressing killer defects in epitaxial layers, representing a substantial advancement in SiC device manufacturing technology.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

The authors would like to express their gratitude to Toyota Tsusho Corporation for funding and technical support, to EpiQuest, Inc. for support with the process equipment.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.63.pdf

K. Toda, D. Dojima, K. Kojima, H. Mihara, S. Mitani, and T. Kaneko, Suppression of In-Grown SF Formation and BPD Propagation in 4H-Sic Epitaxial Layer by Sublimating Sub-Surface Damage before the Growth, Solid State Phenomena 344 (2023) 9-14.

R. Stahlbush, N. Mahadik, P. Bonanno, J. Soto, B. Odekirk, W. Sung, and A. Agarwal, Defects in 4 H -SiC epilayers affecting device yield and reliability, IEEE International Reliability Physics Symposium (IRPS) (2022) 65-1-65-6

K. Toda, D. Kakutani, D. Dojima, Y. Nakajima, H. Mihara, and T. Kaneko, A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes, Mater. Sci. Forum 1124 (2024) 77-84.

D. Dojima, K. Tayake, K. Shigematsu, K. Toda, and T. Kaneko, Macro Step Bunching/Debunching Engineering on off (0001) to Control the BPD-TED Conversion Ratio by Dynamic AGE-ing , Defect and Diffusion Forum 434 (2024) 165-172.

D. Dojima, D. Dansako, M. Maki, K. Toda, and T. Kaneko, 4H-SiC Full Wafer Mapping Image of CMP-Finished Sub-Surface Damage by Laser Light Scattering, Solid State Phenomena 343 (2023) 43-50.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 69-73

doi: 10.4028/p-LSSn44

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-13

Accepted:
2025-08-14

Online:
2025-09-05

Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

Seung Jun Lee , Su Ho Kim , Chae Young Lee , Jong Hwi Park , Jung Woo Choi , Hyong Suk Lee , Jung Gyu Kim , Kap Ryeol Ku , Min Kyu Kang and Won Jae Lee

Senic, 17-15, 4sandan 7-ro, Jiksan-eup, Seobuk-gu, Cheonan-si, Chungcheongnam-do, Korea

Department of Advanced Materials Engineering, Dong-Eui University, 176, Eomgwang-ro, Busanjin-gu, Busan, Korea

sjlee@senic.co.kr, shkim@senic.co.kr, cylee@senic.co.kr, djhpark@senic.co.kr, ejwchoi@senic.co.kr, hslee@senic.co.kr, ikminq980@gmail.com, Jleewj@deu.ac.kr

Keywords: Optimizing Heat Transfer, Physical Vapor Transport (PVT), Temperature Gradient, Polytype Stabilization, Hot Zone

Abstract

At the high growth temperatures of the PVT method, thermal radiation from the graphite crucible surface to the seed region is the dominant mode of heat transfer. In this study, we propose a newly designed crucible structure with a thinner graphite wall compared to the conventional design for SiC crystal growth. The SiC ingot grown using the conventional crucible exhibited the smallest thickness variation (flat top surface) between the center and the edge of the ingot, accompanied by polytype inclusions, which led to an increase in defect density. In contrast, SiC ingots grown using the newly designed crucibles (Design A and Design B) showed a convex top surface and a significantly lower defect density due to the improved heat transfer efficiency. Thinning the graphite crucible wall helps maintain a relatively higher temperature at the seed edge region, thereby effectively enhancing thermal radiation in the radial direction inside the crucible. These results indicate that thermal radiation in the radial direction can be achieved through appropriate optimization of the graphite wall thickness.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

Recently, commercially available SiC power devices such as MOSFETs and Schottky barrier diodes (SBDs) have been fabricated on 6-inch -type 4H-SiC substrates. To further improve device performance and manufacturing yield, the development of large-diameter, high-quality SiC substrates is essential [1-3]. In high-quality epitaxial growth, such substrates must possess a low defect density, suppressed polytype inclusions, and minimal wafer bow. Achieving these characteristics requires precise control of the temperature gradient and the ratio of the vapor phase in the crystal growth region. In the physical vapor transport (PVT) method for SiC crystal growth, a non-optimized heat transfer design in the upper crucible assembly can cause instability in the crystal shape, leading to the formation of various dislocations and polytype inclusions in the grown ingot.

In this work, we aimed to optimize the heat transfer design in the growth zone by varying the lateral wall thickness of the graphite crucible in the upper crucible region, including the seed crystal area. During crystal growth, the temperature at the edge of the seed crystal is generally higher than that at the axial (center) region, primarily due to enhanced thermal radiation at high growth temperatures. This thermal radiation is the dominant heat transfer mechanism under such conditions, facilitating the transport of vapor species such as , and toward the center of the crucible. Consequently, this condition often leads to the formation of a slightly convex growth front in the SiC
ingot [4-5]. In this study, we propose a heat transfer design that promotes polytype stability and enables precise control of defect density during crystal growth.

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

Figure 1 shows schematic diagrams of two crucible designs placed inside the graphite insulation: (i) the conventional crucible and (ii) a newly designed crucibles with a relatively thinner wall. In the new design, the wall thickness was reduced to (Design A) and (Design B) of that of the conventional crucible . SiC crystal growth experiments using these three crucible configurations were carried out at a growth temperature of approximately under an argon atmosphere at pressures ranging from 1 Torr to 40 Torr. A 6-inch, c-face ( ) 4 H -SiC wafer was employed as the seed crystal.

Fig. 1. Schematic diagram of two crucible designs placed inside graphite insulation: (a) the conventional design ( wall thickness) and (b) newly designed crucibles with reduced wall thickness of (Design A) and (Design B) relative to the conventional one.

Fig. 1. Schematic diagram of two crucible designs placed inside graphite insulation: (a) the conventional design ( wall thickness) and (b) newly designed crucibles with reduced wall thickness of (Design A) and (Design B) relative to the conventional one.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

As shown in Table 1, UV fluorescence (UVF) images and photographs of SiC ingots grown using the three crucible designs are presented. The bluish regions observed at the upper and lower parts of the ingots are artifacts caused by optical interference. The UVF image of the ingot grown with the conventional crucible design reveals polytype inclusions (orange regions) on the left side. In contrast, ingots grown using both design A and design B (with relatively thinner walls) exhibited a clear suppression of polytype inclusions. The measured thickness deviation between the center and edge of the ingot grown with the conventional design was only 0.42 mm , indicating a relatively flat surface profile. In comparison, ingots grown with designs A and B displayed convex surfaces with significantly higher thickness deviations of 1.21 mm and 2.34 mm , respectively. The reduction in the graphite crucible wall thickness enhances the temperature at the seed edge region, as thermal radiation dominates heat transfer at the growth temperature ( ). Thinner crucible walls in designs A and B allow increased radial thermal radiation toward the seed crystal, which, in turn, promotes sublimation of vapor species toward the crucible center. Consequently, a more uniform temperature
gradient is established, leading to the formation of convex-shaped SiC crystals and improved polytype stability.

To evaluate the defect density of the grown SiC crystals, chemical etching was carried out in molten KOH at for 5 minutes. Figure 2 presents etched surface images (Nikon, Eclipse LV150) of selected areas near the crystal facets for ingots grown with each crucible design. As summarized in Table 2, substrates obtained from the newly designed crucibles exhibited a lower defect density compared with those from the conventional design.

Table 1. UVF images and ingot shapes of crystals grown using the conventional crucible and the newly designed crucibles (Design A: 95%, Design B: 90% wall thickness).

Insulator density ratio | Conventional (100%) | Design A (95%) | Design B (90%)
UVF image | [Image of circular pattern with green center, orange/red spots on left, and blue edges] | [Image of circular pattern with green center, minimal defects, and blue edges] | [Image of circular pattern with green center and blue edges]
Ingot shapes | [Image of cylindrical ingot cross-section] | [Image of cylindrical ingot cross-section] | [Image of cylindrical ingot cross-section]
Thickness deviation (center-edge) | 0.42 mm | 1.21 mm | 2.34 mm

This improvement is attributed to the optimized radial heat transfer in the thinner-walled crucibles. In particular, maintaining a relatively higher temperature at the seed edge region reduced the generation of threading screw dislocations (TSDs), likely by mitigating dislocation transformation processes at the seed-growth interface.

Fig. 2. Etch pit images of crystal ingots grown using the conventional crucible and modified designs (Design A: 95%, Design B: 90% wall thickness) for EPD evaluation.

Fig. 2. Etch pit images of crystal ingots grown using the conventional crucible and modified designs (Design A: 95%, Design B: 90% wall thickness) for EPD evaluation.

Table 2. Etch pit density (EPD) for grown SiC crystal substrates for conventional and newly designed designs. (Design A: 95%, Design B: 90% wall thickness)
* TSD : Threading Screw Dislocation, TED : Threading Edge Dislocation, BPD : Basal Plane Dislocation

| Conventional | Design A | Design B
TSD [ea/cm²] | 1,680 | 980 | 500
TED [ea/cm²] | 5,200 | 3,000 | 2,000
BPD [ea/cm²] | 5,140 | 12 | 90

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

6-inch 4H-SiC crystals were grown at approximately under an argon atmosphere at Torr. Both a conventional crucible design and newly developed crucible designs (Design A and Design B) with reduced graphite wall thickness were employed. The newly designed crucibles had relatively thinner walls, with thickness ratios of (Design A) and (Design B) relative to the conventional design. The SiC ingot grown using the conventional design exhibited a flat surface, the presence of polytype inclusions, and a relatively higher defect density. In contrast, ingots grown with the newly designed crucibles showed a convex surface profile, suppression of polytype inclusions, and a significant reduction in defect densities such as basal plane dislocations (BPDs) and threading screw dislocations (TSDs). These improvements are attributed to optimized control of thermal radiation within the hot zone, which is critical for achieving high-quality SiC crystal growth.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

This work was supported by Technology Innovation Program (Project Number: 1415185945, Project Name: Development of next-generation power semiconductor based on Si -on- SiC structure), (Project Number: 00402234, Project Name: Development of highly flat, highly clean large area polished SiC single crystal wafers by utilizing advanced process technology for power semiconductor application) funded by the Ministry of Trade, Industry and Energy.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.69.pdf

A. R. Powell, J. J. Sumakeris, Y. Khlebnikov, M. J. Paisley, R.T. Leonard, E. Deyneka, S. Gangwal, J. Ambati, V. Tsevtkov, J. Seaman, A. McClure, C. Horton, O. Kramarenko, V. Sakhalkar, M. O'Loughlin, A. A. Burk, J. Q. Guo, M. Dudley, E. Balkas, Bulk growth of large area SiC crystals, Materials Science Forum 858 (2016) 5-10.

E. Y. Tupitsyn, A. Arjunan, R. T. Bondokov, R. M. Kennedy, T. S. Sudarshan, A study of 6Hseeded 4H-SiC bulk growth by PVT, Mater. Sci. Forum 483-485 (2005) 21-24.

A. Kumar, M. S. Aspalli, SiC : an advanced semiconductor material for power devices, IJRET, Vol. 3 (2014) 248-252.

M. Arzig, M. Salamon, T. C. Hsiao, N. Uhlmann, P. J. Wellmann, Influence of the growth interface shape on the defect characteristics in the facet region of single crystals, Journal of Crystal Growth 532 (2020) 125436.

Z.G. Herro, B.M. Epelbaum, M. Bickermann, P. Masri, A. Winnacker, Effect increase of single-crystalline yield during PVT growth of SiC by tailoring of temperature gradient, Journal of Crystal Growth 262 (2004) 105-112.

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The original version of this eBook is available on https://www.scientific.net/book/epitaxial-layer-manufacturing/978-3-0364-1910-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1157, pp 75-79

doi: 10.4028/p-g5fd2K

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-15

Accepted:
2025-08-15

Online:
2025-09-05

High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

Chae Young Lee , Su Ho Kim , Seung Jun Lee , Jong Hwi Park Jung Woo Choi , Hyong Suk Lee , Jung Gyu Kim , Kap Ryeol Ku , Ye Jin Choi and Won Jae Lee

Senic, 17-15, 4sandan 7-ro, Jiksan-eup, Seobuk-gu, Cheonan-si, Chungcheongnam-do, Korea

Department of Advanced Materials Engineering, Dong-Eui University, 176, Eomgwang-ro, Busanjin-gu, Busan, Korea

cylee@senic.co.kr, shkim@senic.co.kr, sjlee@senic.co.kr, djhpark@senic.co.kr, ejwchoi@senic.co.kr, hslee@senic.co.kr,

Keywords: 6-inch SiC growth, Physical vapor transport (PVT), High-quality, cooldown rate, cooling stage.

Abstract

Thermoelastic stress generated within SiC crystals during the cooling process can induce various types of dislocation defects. In this study, a newly designed cooling protocol was proposed to investigate the correlation between cooldown rate and defect formation in single crystals. Three distinct cooldown rates, , and less than , were applied to assess their impact on the development of thermoelastic stress and resulting crystal quality. Notable variations in ingot color and surface morphology were observed depending on the applied cooldown rate. Dislocation types, including basal plane dislocations (BPDs), threading edge dislocations (TEDs), and threading screw dislocations (TSDs), were quantified through etch pit density (EPD) measurements after molten KOH etching at for 14 minutes. The results indicate that higher cooldown rates led to an increase in BPD density due to enhanced plastic deformation, while lower cooldown rates resulted in higher TED and TSD densities, likely due to increased thermal stress. These findings demonstrate that precise control of the cooldown rate is critical for suppressing thermoelastic stress and minimizing defect densities in SiC crystal growth.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

Defect reduction during the growth of 6-inch 4H-SiC single crystals remains a critical challenge for the fabrication of high-reliability SiC power devices. Among the various crystallographic defects introduced during physical vapor transport (PVT) growth, basal plane dislocations (BPDs) are of particular concern due to their detrimental impact on the performance and long-term reliability of SiC-based devices, including MOSFETs and JFETs [1, 2]. During the PVT growth, BPDs, which lie perpendicular to the c -axis of the SiC crystal, exhibit limited propagation into the grown crystal. In contrast, other crystallographic defects originating from the seed crystal such as threading edge dislocations (TEDs), threading screw dislocations (TSDs), and micropipes (MPs), readily propagate along the growth direction, thereby extending into the epitaxial layers.

The temperature gradients in both the radial and axial directions of the graphite crucible significantly influence the crystal quality and polytype stability during growth. Furthermore, thermoelastic stresses including plastic deformation and thermal stress within the grown crystal contribute to the formation of various dislocation defects during the cooling stage [ 3,4 ]. Therefore, precise control of the cooldown rate is essential for managing the density of BPDs. Understanding the relationship between the cooldown rate during the cooling stage and defect formation is essential for the growth of high-quality SiC single crystals [5, 6]. In this study, a newly designed growth process incorporating varied cooldown rates was proposed to enhance the crystalline quality of 4 H SiC single crystals.

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

single crystals were grown at temperatures ranging from 2300 to under a growth pressure of 20 Torr in and Ar atmospheres. Seed crystals were prepared using off-axis c-face substrates cut from the same ingot. In the heating stage, the growth temperature was stabilized within , and the growth pressure was precisely regulated in the range of Torr. A newly designed growth protocol incorporating different cooldown rates during the cooling stage was introduced. Three cooldown conditions were investigated: (1) a rapid cooldown rate of , (2) a moderate rate of , and (3) a slow rate of less than . Following the growth run, the 6 -inch wafers were processed using standard semiconductor fabrication techniques. The surface of the SiC substrates was etched in molten KOH at for 14 minutes to reveal crystallographic defects. Etch pit density (EPD) was evaluated using optical microscopy (OM) after the etching process.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

Dislocation defects such as TSDs and TEDs originating from the seed crystal may either diminish during growth or propagate into the grown SiC ingot. In particular, BPDs, which lie perpendicular to the c -axis of the SiC crystal, tend to increase due to plastic deformation induced during the cooling stage. An insufficient temperature gradient during this stage can exacerbate BPD formation by inducing simultaneous tensile and compressive stresses within the crystal. As shown in Fig. 1 (b), radial cracks were observed after external grinding in crystals grown under conventional cooldown conditions ( ) without pressure control during cooling. When the growth pressure is abruptly increased to atmospheric levels during the cooldown phase, convective heat transfer distorts the thermal gradient, further promoting defect generation. The pressure range during this transition spans from 20 Torr to atmospheric pressure.

Fig. 1. Photographic images of the SiC crystal grown under a conventional cooldown rate of , illustrating the surface condition before (a) and after (b) external grinding.

Fig. 1. Photographic images of the SiC crystal grown under a conventional cooldown rate of , illustrating the surface condition before (a) and after (b) external grinding.

Figure 2 denotes a schematic diagram of the SiC crystal growth process employed in this study. Prior to the pre-heating stage, a vacuum is applied to remove residual impurities from the growth chamber. The pressure is then restored to atmospheric levels for the subsequent heating process. This procedure is adopted to prevent seed crystal detachment and unintended sublimation that may occur if heating is initiated under vacuum conditions, which could compromise control over the initial temperature gradient, an essential factor for stable and reproducible crystal growth.

The region highlighted in light red indicates the cooling stage. Key parameters influenced during this stage include the cooldown rate, pressure control, type of inert gas, and material density. The growth temperature and pressure were kept constant across all growth runs, including the conventional process illustrated in Fig. 2. The newly developed cooldown protocol consists of three conditions: (1) a cooldown rate of , (2) , and (3) less than . In
the case of the conventional cooldown condition, a maximum cooldown rate of was achieved by optimizing the thickness and density of the graphite insulation.

Fig. 2. Schematic diagram of the SiC crystal growth process. The reddish-shaded region indicates the cooling stage, and the inset highlights the key parameters associated with this stage.

Fig. 2. Schematic diagram of the SiC crystal growth process. The reddish-shaded region indicates the cooling stage, and the inset highlights the key parameters associated with this stage.

Figure 3 shows images of SiC ingots grown under three different cooldown rates during the cooling stage: (a) , (b) , and (c) less than . Significant variations in color and surface morphology were observed depending on the applied cooling conditions. A horizontal crack was identified in the SiC ingot (Fig. 3 (a)) grown with a cooldown rate of following the external grinding process. In contrast, surface carbonization (Fig 3. (c)) was observed in the ingot grown under a cooldown rate of less than . The most uniform and smooth surface morphology (Fig. 3 (b)) was achieved with a cooldown rate of .

Fig. 3. Photographic images of SiC ingots grown under different cooldown rates: (a) , (b) , and (c) less than

Fig. 3. Photographic images of SiC ingots grown under different cooldown rates: (a) , (b) , and (c) less than

Figure 4. denotes optical microscopy (OM) images of the etched surfaces of three SiC substrates, BPDs, TSDs, TEDs, and overall etch pit density (EPD), prepared under different cooldown rates during the cooling stage. Under the relatively high cooldown rate condition of (a) , a significant increase in BPDs was observed, primarily attributed to plastic deformation during the cooling stage. In contrast, the extremely slow cooldown condition of (c) less than , resulted in elevated densities of TEDs and TSDs, likely due to increased thermal stress. Notably, the SiC crystal grown under a moderate cooldown rate of (b) , exhibited the lowest overall defect densities, including BPDs and TEDs, with comparatively fewer TSDs, indicating optimal thermal and mechanical stability during cooling as shown in Table. 1.

Although the cooldown rate of (equivalent to ), which resulted in low defect density in the present study, is comparable to the cooldown rate over 70 hours reported in a previous study [6], the outcomes differ significantly. This discrepancy is presumed to arise from differences in the density and thickness of the graphite insulations used in the two studies. As
summarized in Table 1, the defect densities of the SiC substrates were evaluated based on etch pit density (EPD) measurements. The EPD values for SiC crystals grown under cooldown rates of (a), (b), and less than (c) were , and , respectively.

Fig. 4. Optical microscopy (OM) images of the etched surfaces of three SiC substrates grown under different cooldown rates (a) , (b) , and (c) less than during the cooling stage, showing the distributions of BPDs, TSDs, and TEDs, respectively.

Fig. 4. Optical microscopy (OM) images of the etched surfaces of three SiC substrates grown under different cooldown rates (a) , (b) , and (c) less than during the cooling stage, showing the distributions of BPDs, TSDs, and TEDs, respectively.

Table 1. Obtained values of basal plane dislocations (BPDs), threading screw dislocations (TSDs), threading edge dislocations (TEDs), and overall etch pit density (EPD), prepared under different cooldown rates (a) ~ (c) during the cooling stage.

Defect density
Cooldown rate (a)
10~30 °C/min
Cooldown rate (b)
1~5 °C/min
Cooldown rate (c)
Less than1 °C/min

BPD [ea/cm²]
12,400
440
300

TSD [ea/cm²]
80
160
1,740

TED [ea/cm²]
1,680
1,200
14,460

Etch pit density
[ea/cm²]
14,160
1,800
16,500

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

6-inch 4H-SiC single crystals were grown using the physical vapor transport (PVT) method under three different cooldown rates applied during the cooling stage. In crystals grown under the conventional cooldown condition ( ) without growth pressure control, radial cracks were observed after external grinding. The cooldown rate was found to have a significant influence on the color and surface morphology of the ingots. A relatively high cooldown rate resulted in an increased density of basal plane dislocations (BPDs), primarily due to enhanced plastic deformation. Conversely, extremely low cooldown rates led to a higher density of threading edge dislocations (TEDs) and threading screw dislocations (TSDs), likely caused by increased thermal stress. These results highlight the importance of precisely controlling the cooldown rate during the cooling stage to achieve high-quality SiC crystal growth.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

This work was supported by Technology Innovation Program (Project Number: 1415185945, Project Name: Development of next-generation power semiconductor based on Si -on-SiC structure), (Project Number: 00402234, Project Name: Development of highly flat, highly clean large area polished SiC single crystal wafers by utilizing advanced process technology for power semiconductor application) funded by the Ministry of Trade, Industry and Energy.

References

The original version of this paper is available on https://www.scientific.net/MSF.1157.75.pdf

A. Agarwal, H. Fatima, S. Haney, S.H. Ryu, A new degradation mechanism in high-voltage SiC power MOSTETs, IEEE Electron Device Lett. 28 (2007) 587-589.

V. Veliadis, H. Hearne, E.J. Stewart, M. Snook, W. Chang, J.D. Caldwell, H.C. Ha, N. ElHinnawy, P. Borodulin, R.S. Howell, D. Urciuoli, A. Lelis, C. Scozzie, Degradation and full recovery in high-voltage implanted-gate SiC JFETs subjected to bipolar current stress, IEEE Electron Device Lett. 33 (2012) 952-954.

N. Ohtani, M. Katsuno, H. Tsuge, T. Fujimoto, M. Nakabayashi, H. Yashiro, M. Sawamura, T. Aigo, T. Hoshino, Behavior of basal plane dislocations in hexagonal silicon carbide single crystals grown by physical vapor transport, Jpn. J. Appl. Phys. 45 (2006) 1738-1742.

M. Dudley, Y. Chen, X.R. Huang, R.H. Ma, Aspects of dislocation behavior SiC, Mater. Sci. Forum 600 (2008) 261-266.

E. Schmitt, T. Straubinger, M. Rasp, A.D. Weber, Defect reduction in sublimation grown SiC bulk crystals, Superlattices Microstruct. 40 (2006) 320-327.

J. Steiner, M. Roder, B. D. Nguyen, S. Sandfeld, A. Danilewsky and P. J. Wellmann, Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC, Materials, 12 (2019) 2207(1)-2207(8).

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Keywords Index

2

2deg Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

2dhg Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

3

3c-sic Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

4

4h-sic Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

6

6-inch SiC Growth High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

C

C/si Ratio Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Cmp-free Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

Coherent Interface Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

Computed Tomography Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Cooldown Rate High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

Cooling Stage High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

Crucible Design Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Cvd Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

D

Dopant Incorporation Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

E

Ebsd Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

Epitaxy Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Epitaxy; Ammonia; Nitrogen; Doping Concentration; Uniformity; Deviation 08db5901-5a62-4bb8-87fa-4fd1d5c44360

G

Growth Contribution Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Growth Parameters Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

H

Heteroepitaxy Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

High Nitrogen Doping Epitaxial SiC Development for High Nitrogen Incorporation

High-quality High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

Hot Zone Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth

L

Lapping Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

M

Macro Step Bunching Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

N

Nitrogen Doping Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Numerical Simulation Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

O

On-wafer Uniformity Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Optimizing Heat Transfer Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth

P

Physical Vapor Transport (pvt) Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth; High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

Polytype Stabilization Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth

Powder Consumption Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Pvt Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

S

Scanning Probe Microscopy Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

SiC Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Silicon Carbide On Insulator (sicoi) Epitaxial SiC Development for High Nitrogen Incorporation

Site Competition Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Source Powder Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Step Tension Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

Sub-surface Damage Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

Sublimation Etching Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

Supersaturation Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Surface Area Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Surface Planarization Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

T

Tem Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

Temperature Gradient Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth

Y

Young's Modulus Epitaxial SiC Development for High Nitrogen Incorporation

Authors Index

A

Abe, M. Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

Almeida, C. Recent Advancement in Noncontact Wafer Level Electrical Characterization for WBG Technologies

Ayazi, F. Epitaxial SiC Development for High Nitrogen Incorporation

B

Burgess, C. Epitaxial SiC Development for High Nitrogen Incorporation

C

Choi, J. Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth; High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

Choi, Y. Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth; High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

D

Dojima, D. Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing; The Application of Dynamical Thermal Annealing Processes after Mechanical Slicing as an Integrated Contactless SiC Wafering Method to Control Crystal Defects

F

Faisal, F. Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

G

Gutierrez, L. Recent Advancement in Noncontact Wafer Level Electrical Characterization for WBG Technologies

H

Han, Y. 08db5901-5a62-4bb8-87fa-4fd1d5c44360

J

Johar, M. Predictive Doping and Thickness Analysis of a Multi-Wafer SiC Warm-Wall Epi Reactor for Improved Layer Cpks

Jr., A. Predictive Doping and Thickness Analysis of a Multi-Wafer SiC Warm-Wall Epi Reactor for Improved Layer Cpks

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Kaneko, T. Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing; The Application of Dynamical Thermal Annealing Processes after Mechanical Slicing as an Integrated Contactless SiC Wafering Method to Control Crystal Defects

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Kiritani, K. Active Planarization Method from Rough Surface of -off -SiC (0001) Controlled by Step Bunching and Debunching Mechanism Using Dynamic AGE-ing

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Lagowski, J. Recent Advancement in Noncontact Wafer Level Electrical Characterization for WBG Technologies

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Lee, G. Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Lee, H. Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth; High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

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Lee, W. Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth; Optimization of Heat Transfer Design for High Quality 4H-SiC Ingot Growth; High-Quality SiC Crystal Growth by Cooldown Rate Control at Cooling Stage

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Reimann, D. Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

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Savtchouk, A. Recent Advancement in Noncontact Wafer Level Electrical Characterization for WBG Technologies

Schrader, A. Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

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Song, G. Filling-Design Effect of Powder Source in the Crucible on SiC Single-Crystal Growth

Steller, N. Nitrogen Dopant Incorporation into Epitaxial -SiC and the Influence of CVD Growth Parameters

Suemitsu, M. Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

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Tanno, T. Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

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VanMil, B. Epitaxial SiC Development for High Nitrogen Incorporation

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Watanabe, Y. Formation of Alternating Epilayers of and 3C-SiC by Simultaneous Lateral Epitaxy

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