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ISBN print: 978-3-0364-2129-2
ISBN eBook: 978-3-0364-3129-1
DOI book: 10.4028/b-e8AH67
© 2026 Trans Tech Publications Ltd, All Rights Reserved

Interface, Dielectrics and
Ohmic Contact in SiC Power Devices

Edited by
Sang Mo Koo
Hoon Kyu Shin

Interface, Dielectrics and Ohmic Contact in SiC Power Devices

Special topic volume with invited peer-reviewed papers only

Edited by
Sang Mo Koo and Hoon Kyu Shin

Scientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volume 1192 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

Full text available online at https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp -1-0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2026-05-18

Online:
2026-05-20

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1192.-1.pdf

The progress in the area of silicon carbide ( SiC ) power electronics has been driven not only by the intrinsic advantages of this wide-bandgap semiconductor but also by advances in the engineering of interfaces, dielectric layers, and electrical contacts. While SiC offers exceptional properties for high-voltage and high-temperature operation, the performance and reliability of practical devices depend critically on the quality of the SiC/ oxide interface, the stability of gate dielectrics, and the formation of low-resistance, thermally robust ohmic contacts. These technological elements form the foundation of high-performance SiC MOSFETs, CMOS circuits, and other advanced devices.

The presented special edition focuses on the latest engineering and technological developments in the interface components of the SiC device. The publication explores gate dielectrics and gate stacks fabricated using techniques such as chemical vapour deposition and atomic layer deposition, with particular emphasis on MOS capacitors as fundamental structures for evaluating dielectric integrity and interface properties. Advanced treatments, including surface conditioning and decoupled plasma nitridation, are presented as effective approaches for reducing interface trap densities and optimising channel mobility in both planar and trench MOSFET architectures.

The formation of reliable electrical contacts is another central theme of this edition. Ohmic, Schottky, and backside metallisation contacts are examined with respect to annealing temperature, contact geometry, and interfacial reactions. Parameters such as contact resistivity, contact front resistance, contact end resistance, and backside contact resistance are discussed as critical indicators of device efficiency and manufacturability.

This edition provides a comprehensive perspective on the technologies that govern charge transport across interfaces and contacts in SiC devices and is intended for researchers, process engineers, and graduate students engaged in the development of next-generation wide-bandgap electronics.

We hope that the contributions presented in this edition will advance future research on interface and contact phenomena, the optimisation of fabrication processes, and the continued improvement of reliable and efficient SiC power devices.

Table of Contents

Preface

Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Chia Lung Hung, Patrick Rabinzohn, Andrii Vozny, Tatiana Ivanova, Mikko Söderlund, Yi Kai Hsiao, Hao Chung Kuo

Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

Bongmook Lee, Veena Misra

Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Wei Chen Yu, Chia Lung Hung, Wei Cheng Lin, Wei Ting Lin, Tejender Singh Rawat, Yi Kai Hsiao, Tian Li Wu, Hao Chung Kuo

Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Harsha Vardhan Manchineni, Andre Wachowiak, Thomas Mikolajick

Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Maximilian Szabo, Tom Becker, Michael Jank, Tobias Erlbacher

Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Masao Sakuraba, Tatsunori Oki, Satoshi Watanabe, Shigeo Sato, Iori Morita, Tetsuya Ueno, Seima Sato, Hiroyuki Nagasawa, Yukimune Watanabe, Maki Suemitsu

Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Koushik Ramadoss, Joshua Holt, Lucien Date, Safdar Muhammad, Jesse Kalliomaki, Fernanda Albrechtvechietti, William Charles, Athena Pang, Shubhendra Jain, Benjamin Briggs, Ludovico Megalini, Michael Chudzik, Dallas Morisette, James A. Cooper

Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Heng Wang, Yang Ming Du, Ji Shu, Peng Wei Zhou, Ying Chen Yang, Kevin J. Chen

Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Xinkai Tian, Arne Benjamin Renz, Kyrylo Melnyk, Mustafa Akif Yildirm, Marco Boccarossa, Luca Maresca, Andrea Irace, James A. Gott, Nereus S. Agbo, Paul Taylor, Marina Antoniou, Philip Andrew Mawby, Peter M. Gammon

High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

Johannes Ziegler, Dick Scholten, Holger Bartolf, Jörg Schulze

Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Marilena Vivona, Salvatore Ethan Panasci, Marco Zignale, Valerio Votadoro, Salvatore di Franco, Emanuela Schilirò, Giuseppe Greco, Raffaella Lo Nigro, Patrick Fiorenza, Filippo Giannazzo, Fabrizio Roccaforte

NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Paolo Badalà, Corrado Bongiorno, Salvatore Sanzaro, Anna Bassi, Simone Rascunà, Gabriele Bellocchi, Massimo Boscaglia, Antonino La Magna, Alessandra Alberti

Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Maximilian Ley, Julian Kauth, Mathias Rommel, Björn Fischer, Alexander May, Jörg Schulze

Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Motoki Kobayashi, Seiji Ishikawa, Yuta Higashi, Hiroshi Sezaki, Mitsuo Okamoto, Shinsuke Harada, Kazutoshi Kojima

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 1-7

doi: 10.4028/p-BBnM7g

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-17

Revised:
2025-12-09

Accepted:
2026-03-08

Online:
2026-05-20

Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

Chia-Lung Hung 1,a*, Patrick Rabinzohn 2,b, Andrii Vozny 2,c, Tatiana Ivanova 2,d, Mikko Söderlund 2,e, Yi-Kai Hsiao 1,f and Hao-Chung Kuo 1, g

1 Semiconductor Research Center, Hon Hai Research Institute, Taiwan, R.O.C.

2 BENEQ Oy, Olarinluoma 9, 02200 Espoo, Finland

a  kevin.cl.hung@foxconn.com, b  patrick.rabinzohn@beneq.com, c  andrii.voznyi@beneq.com, d  tatiana.ivanova@beneq.com, e  Mikko.Soderlund@beneq.com, f  jason.yk.hsiao@foxconn.com, ghao-chung.kuo@foxconn.com

Keywords: 4 H -SiC, Atomic Layer Deposition, Density of interface states, Embedded CMOS, SiO2, Specific on-state resistance, Trench UMOSFET

Abstract

This paper presents process integration of atomic layer deposition (ALD) SiO2 as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance ( Ron,sp ). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO2 gate oxide into trench UMOSFET. The Ron,sp of the fabricated device can be reduced to 2.3 mΩ−cm2, accompanied by a very low density of interface states ( Dit  ) of approximately 5.36×1010eV−1 cm−2. Another feature of this ALD SiO2 solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

SiC power MOSFET are replacing Si devices in the blocking voltage range from 600 to 6500 V with substantial energy saving in various electric systems courtesy to their low on-resistance and fast switching. This trend is now often supported by trench UMOSFET. In particular significant attention has been paid to monolithic SiC power IC [1] due to its fast-switching capabilities and suitability for harsh environment applications. However, a major challenge remains in achieving a conformal gate oxide thickness on both the UMOSFET and CMOSFET. The strong crystal face dependence of the oxidation rate [2] must be carefully considered in device fabrication. The industry trend has shifted from thermal oxidation to deposition techniques, with ALD offering best quality, superior conformality and precise control of thickness at low temperatures, while also enabling interface engineering using plasma-based processes.

Nobel Fabrication Process for Embedded CMOS and UMOSFET

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

In this paper, we propose a novel fabrication process for embedding the low voltage (LV) CMOS circuit and high voltage (HV) trench UMOSFET simultaneously on a SiC substrate as presented in Figure 1. Began with the RCA clean process with a nitrogen-doped ( 5×1015 cm−3 ), 4-degree tilted epitaxial layer (15μ m) grown on a heavily doped SiC substrate. A multiple ion implantation process

[picture]

Fig. 1. Cross-sectional scheme for LV and HV device integration

Fig. 1. Cross-sectional scheme for LV and HV device integration

was executed in a high-temperature ( 500∘C ) implanter, including the p -bottom shielding (PBS), p plus ( p+), guard ring (GR), n-plus ( n+), p-well (PW), and side-wall protection (SP) implantations. Among the implantation steps, the PBS and SP processes further utilized the spacer on hard mask sidewall (SHMS) technique to precisely control the lateral doping profile, ensuring a balance between Ron,sp  and breakdown voltage (BV). An implantation hard mask was patterned for the PBS and SP layers, a side wall spacer was then formed on the lateral side wall of the hard mask. High energy ion implantation was executed to the desired junction depth to form the bottom and side wall protection structures for the PBS and SP, respectively. The implanted dopants were activated by 1750∘C thermal annealing with carbon cap. Trench formation was achieved by first patterning a hard mask on SiC, followed by reactive ion etching (RIE) to create the desired depth and profile, resulting in trenches with a width of 1μ m and a depth of 1.5μ m. The sacrificial oxidation followed by the deep trench etching was conducted to repair the side wall damage region induced by the trench etching. A raised CVD field oxide layer of 0.2μ m was subsequently patterned to create the isolation region within the CMOS circuit area. Gate dielectrics were formed under three different conditions for comparison: LPCVD SiO2 deposition followed by nitrogen ( N2 ) annealing at 1000∘C, ALD SiO2 deposition with TDMAS and O3 as precursors followed by nitric oxide (NO) annealing at 1250∘C, and dry thermal oxidation followed by NO annealing at 1250∘C. The ALD SiO2 dielectric stack includes in-situ plasma preclean and a 5 nm interfacial layer deposited by advanced PEALD Atomic Layer Annealing (ALA) [3] prior a thick high-quality SiO2 thermal ALD layer thus tailoring the SiC/ dielectric interface, enhancing leakage current, breakdown voltage, and overall quality of the SiC/SiO2 interface.

[picture]

Fig. 2. TOF-ERDA composition analysis of the ALDSiO2 stack [33.7+/−0.5%Si,66.2+/−0.5%O,<1%C,H<0.3%, N<BDL ]

Fig. 2. TOF-ERDA composition analysis of the A L D S i O 2 stack [ 33.7 + / − 0.5 % S i , 66.2 + / − 0.5 % O , < 1 % C , H < 0.3 % , N < B D L ]

[picture]

Fig. 3. Current density-electric field and Capacitance-voltage Plot

Fig. 3. Current density-electric field and Capacitance-voltage Plot

[picture]

Fig. 5. SEM cross section of trench UMOSFET with (a) PBS implantation (b) without PBS implantation

Fig. 5. SEM cross section of trench UMOSFET with (a) PBS implantation (b) without PBS implantation

Fig. 4. (a) Simulated trench UMOSFET with PBS implantation and (b) without PBS implantation

High purity of the ALDSiO2 dielectric stack was confirmed after NO annealing on Figure 2. Current density-electric field and Capacitance-voltage characteristics of MOS test capacitors using the ALD SiO2 dielectric stack are shown on Figure 3. These characteristics are accompanied by a nearly ideal VFB of - 0.69 V , a 0.1 V hysteresis and −6.6×1010 cm−2 charge trapping at the SiO2/SiC interface. Heavily phosphorus-doped polysilicon with a thickness of 1μ m was formed using the deposition-etching-deposition (DED) technique to ensure effective gap filling and conductivity in both the trench UMOSFET and CMOS devices. An inter-metal dielectric (IMD) layer was deposited and subsequently patterned to define the source and gate contact regions, facilitating device interconnections. Nickel silicide ( NiSi ) and titanium/titanium nitride ( Ti/TiN ) was employed for the metal contact in the source and gate contact region, respectively. Pure aluminum (Al) was deposited and subsequently patterned to establish top metal region. Finally, a passivation layer consisting of 0.2 μm of oxide and 0.7μ m of nitride was deposited using PECVD tool. Additionally, a 10μ m polyimide layer was applied to protect the entire chip area, except for the opening region on the electrical pad for probing the power device. This completes the fabrication of the SiC trench UMOSFETs and CMOS circuits on the wafer. The simulated and fabricated UMOSFET are shown in Figures 4 and 5, respectively.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

Figure 6 presents the SEM cross-sectional image of trench UMOSFETs utilizing LPCVD SiO2, ALD SiO2, and thermal SiO2 as gate dielectrics. The gate oxide thickness on the trench sidewall is thinnest for LPCVD SiO2, attributed to its poor step coverage. In contrast, the thickness at the trench

[picture]

Fig. 6. SEM cross section of trench UMOSFET with (a) LPCVD SiO2 (b) ALD SiO2 (c) Thermal SiO2

Fig. 6. SEM cross section of trench UMOSFET with (a) LPCVD S i O 2 (b) ALD S i O 2 (c) Thermal S i O 2

Table 1. Gate Oxide Thickness Comparison

Gate Oxide Condition | LPCVD SiO₂ | ALD SiO₂ | Thermal SiO₂
Post Oxide Annealing | N₂ 1000°C | NO 1250°C | NO 1250°C
Oxide Thickness@ Trench Side Wall | 28.35 nm [SEM] | 45.3 nm [SEM] | 48.8 nm [SEM]
Oxide Thickness@ Trench Bottom | 25 nm [SEM] | 43.7 nm [SEM] | 11.1 nm [SEM]
Oxide Thickness@ Trench Mesa | 48 nm [CV] | 41 nm [CV] | 15 nm [CV]
Mesa Normalized to Side Wall | 169 % | 91 % | 31 %

[picture]

Fig. 7. CV characteristics of MOSCAP with different gate oxide and annealing

Fig. 7. CV characteristics of MOSCAP with different gate oxide and annealing

Fig. 8. Density of interface states versus energy distribution with different gate oxide and annealing
bottom reveals that thermal SiO2 exhibits only 10 nm compared to the other two deposition methods due to the lower anisotropic thermal oxidation rate at the trench bottom. Table 1 summarizes the gate oxide thickness across three different regions surrounding the trench for the three gate oxide formation methods. ALD SiO2 demonstrates the best step coverage and conformality among the options, indicating a high potential for integrating CMOS circuits into trench UMOSFET power chips. Figure 7 illustrates the CV characteristics of the planar MOS capacitor built on the mesa region under various gate oxide and annealing conditions. The ALD SiO2 exhibits behavior similar to that of the thicker thermal SiO2. In contrast, the LPCVDSiO2 reveals a larger flat band shift and distortion, attributed to accumulated Dit  at the interface. Additionally, the thinner thermal SiO2 raises significant concerns regarding leakage and reliability issues. The Hi−LoCV method was conducted to extract the Dit  in this work. The Dit  at 0.2 eV from the conduction band edge is measured to be 5.36×1010eV−1· cm−2 for ALD SiO2, 6.30×1010eV−1· cm−2 for thermal SiO2, and 6.80×1012eV−1· cm−2 for LPCVD SiO2, as shown in Figure 8. As expected in-situ plasma preclean and deposition of the ALA SiO2 interfacial layer strongly improved Dit  of the Si -face on SiC . Figure 9 presents the transfer characteristics of the planar NMOSFET and PMOSFET utilizing ALD SiO2 as the gate oxide. The extracted threshold voltages ( Vth  ) are found to be 2 V for the NMOSFET and 5.3 V for the PMOSFET. The subthreshold swing (S.S) are 203 and 287mV/ Dec for the NMOSFET and PMOSFET, respectively. The output characteristics of the NMOSFET and PMOSFET exhibit typical linear and saturation behavior as demonstrated in Figure 10. To demonstrate the integration of the CMOS
circuits with power trench UMOSFET by utilizing the ALD SiO2 as the gate dielectric, we also fabricate an inverter circuit composed of both NMOSFET and PMOSFET in this work. Figure 11 presents the transfer characteristics of the fabricated inverter circuit, showing a high noise margin (NMH) of 6.3 V and a low noise margin (NML) of 10.5 V . The observed asymmetry between NMH and NML is attributed to the Vth  mismatch between the NMOSFET and PMOSFET, as previously discussed. The PBS implantation was introduced to the thermal SiO2 wafer to provide protection for the ultra-thin oxide at the trench bottom and corners. Figure 12 illustrates the transfer characteristics of the trench UMOSFET, with the Vth  determined at a gate voltage (VG) corresponding to a current

[picture]

Fig. 9. Transfer characteristics of NMOSFET and PMOSFET with ALD SiO2 as gate dielectric

Fig. 9. Transfer characteristics of NMOSFET and PMOSFET with ALD S i O 2 as gate dielectric

[picture]

Fig. 10. Output characteristics of NMOSFET and PMOSFET with ALD SiO2 as gate dielectric

Fig. 10. Output characteristics of NMOSFET and PMOSFET with ALD S i O 2 as gate dielectric

[picture]

Fig. 11. Transfer characteristics of CMOS inverter with ALDSiO2 as gate dielectric

Fig. 11. Transfer characteristics of CMOS inverter with A L D S i O 2 as gate dielectric

[picture]

Fig. 12. Transfer characteristics of UMOSFET with different gate oxide and annealing

Fig. 12. Transfer characteristics of UMOSFET with different gate oxide and annealing

of 1 mA . The Vth  values are found to be 2 V for ALDSiO2 and 4.8 V for thermal SiO2. In contrast, the LPCVD SiO2 exhibits an abnormally high Vth , attributed to the elevated Dit  accumulated at the SiO2/SiC interface. In addition to the varying effects of the gate oxide, the higher Vth  observed in the trench UMOSFET with thermal SiO2 is also influenced by the PBS implantation effect. The merged PBS implant profile with the p -well on the left side wall of the trench, resulting from an alignment error as depicted in Figure 5(a), contributes to the higher Vth and the lower conduction observed current. Figure 13 shows the output characteristics of the trench UMOSFET with ALD SiO2 as the gate dielectric. Finally, the benchmark comparison of our work with other studies [4~6] is presented in Figure 14, highlighting a Ron,sp of 2.3~2.7 mΩ· cm2 and a BV of 1755~2349 V achieved in this study. Figure 15 presents the BV characteristics of the fabricated UMOSFET and floating GR. The
wider BV range was attributed to the leakage current originating in the UMOSFET cell region, which likely stemmed from the corner and bottom of the trench structure being inadequately protected by the SP and PBS.

[picture]

Fig. 13. Output characteristics of UMOSFET with ALD SiO2 as gate dielectric

Fig. 13. Output characteristics of UMOSFET with ALD S i O 2 as gate dielectric

[picture]

Fig. 14. Benchmark comparison of other studies with this work

Fig. 14. Benchmark comparison of other studies with this work

[picture]

Fig. 15. BV characteristics of the fabricated UMOSFET and GR in this work

Fig. 15. BV characteristics of the fabricated UMOSFET and GR in this work

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

We have successfully demonstrated the monolithic integration of CMOS circuits with power trench UMOSFETs by utilizing ALD SiO2 as the gate dielectric, owing to its superior step coverage and conformality. In-situ plasma preclean of the SiC surface and deposition of a 5 nmALASiO2 interfacial layer strongly improve Dit.  The Dit  of the ALDSiO2 can reach 5.36×1010eV−1· cm−2, which is comparable to or even better than that of thermal SiO2 observed so far. The NMH and NML of the fabricated inverter circuit are 6.3 V and 10.5 V , respectively. The asymmetry between NMH and NML can be further improved through Vth  adjustment or optimization of the channel width design in future work. The Vth  of the ALDSiO2 trench gate oxide UMOSFET is 2 V , and the Ron,sp can be reduced to 2.3 mΩ· cm2 due to the ultra-lower Dit  at the SiO2/SiC interface. The BV of the fabricated ALD SiO2 trench MOSFET and the guard ring is within 1755~2349 V, which is good enough for the 1700 V application. The enabling capability of ALD for the monolithic integration versus thermal oxide and LPCVD, which are just not capable due to conformality across the mesa and trench regions. Future work will require the optimization of the ALDSiO2 process, as well as the SP and PBS implantation processes.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

The authors would like to express their gratitude to Kosuke San from SAMCO for providing support with the SiC trench process, and to Professor Bing Yue Tsui from NYCU for supplying the measurement instruments.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

M. Okamoto, et al., First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer, ISPSD 2021.

T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, 2nd ed. (Wiley-IEEE Press, 2014) p. 214.

A. Voznyi et al., ALD deposited dielectric stack with engineered interface using in-situ Atomic Layer Annealing for high-performance SiC MOSFET, ICSCRM 2024.

C. L. Hung, et al., Enhancing Characteristics of SiC VDMOSFETs: Strategic Integration of Cell Design and Process Optimization, IEEE Trans. Electron Devices, 71, 6228, 2024.

N. J. Yeop, et al., A Novel 1700V 4H-SiC Double Trench MOSFET Structure for Low Switching Loss, J. IKEEE, 25, 15, 2021.

A. T. Hajjiah, et al., Novel SiC-trench-MOSFET with reduced oxide electric field, IEEE. ICSICT, 2004.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 9-13

doi: 10.4028/p-rMav12

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-08

Revised:
2025-12-09

Accepted:
2026-03-16

Online:
2026-05-20

Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

Bongmook Lee 1,a* and Veena Misra 2, b

¹College of Engineering, SUNY Polytechnic Institute, Utica, NY 13502, USA

2 Department of Electrical Engineering, North Carolina State University, Raleigh, NC

aleeb1@sunypoly.edu, b  vmisra@ncsu.edu

Abstract

This study investigates the electric dipole effect at Al2O3/SiO2 interfaces deposited by Atomic Layer Deposition (ALD) on 4H-silicon carbide (SiC) substrates for threshold voltage ( VT ) modulation. By incorporating an ultrathin 3 nmAl2O3 layer onto ALD-deposited 30 nmSiO2, they created an electric dipole that produces a 0.65±0.15 V positive shift in threshold voltage after N2O post-deposition annealing. The dipole-induced voltage shift was validated through both MOS capacitor measurements and lateral MOSFET characterization. Importantly, the threshold voltage enhancement occurred without degradation in field-effect mobility, demonstrating that the dipole effect does not introduce additional scattering centers. This technique offers an effective approach for threshold voltage tuning in alternative semiconductor devices where thermal SiO2 growth is not feasible, addressing critical challenges in SiC power electronics that require high threshold voltages (>3 V) for reliable operation.

Keywords: atomic Layer deposition, 4H−SiC power device, dipole effect, VT modulation, VFB modulation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

Electric dipole effects at high-permittivity dielectric (high-k)/ SiO2 interfaces have been reported for various dielectrics, including HfO2,Al2O3,LaOx, and Y2O3 on Silicon as well as Silicon Carbide substrates [1-4]. For example, a dipole-induced voltage shift of up to 0.57 V has been observed for Al2O3 on thermally grown SiO2 on Si [2]. Such dipole effects can lead to either positive or negative flatband or threshold voltage shifts, depending on the properties of the high-k dielectric within the stack. Consequently, dipole engineering provides a means to modulate the threshold voltage of metal-oxide-semiconductor field-effect transistors (MOSFETs) [2]. Traditionally, dipole effects of high-k dielectrics have been investigated on thermally grown SiO2 on silicon. However, it is particularly interesting to explore these effects on alternative substrates where threshold voltage control remains challenging, such as in silicon carbide (SiC) MOSFETs. In SiC devices, enhancing channel mobility via nitrogen-based post-oxidation annealing often forces a trade-off between mobility and threshold voltage. For reliable power electronics applications, a sufficiently high threshold voltage ( >3 V ) is typically required. In this work, we report a Vt enhancement method based on the dipole effect of Al2O3/SiO2 stacks deposited by atomic layer deposition (ALD) on 4H−SiC. ALD dielectrics are particularly attractive as gate dielectrics due to their excellent film quality, uniformity, precise thickness control, and low-temperature processing [5]. Here, we demonstrate for the first time the dipole effect in Al2O3/SiO2 stacks deposited entirely by ALD on 4H−SiC.

The origin of the dipole effect is generally attributed to energy band bending at the high- k/SiO2 interface. This effect can arise from either (i) the electronegativity difference between the cations in the two oxides or (ii) differences in oxygen areal density across the interface [3,4]. As a result, the threshold voltage/flatband voltage ( VT/VFB ) shift induced by the dipole effect does not introduce additional interface states or Fermi-level pinning [3,4]. Importantly, unlike charge-induced Vt/VFB shifts, the dipole-induced shift does not generate new scattering centers, and its magnitude is independent of both the SiO2 and high-k dielectric thicknesses. Thus, the dipole effect can be modeled as an intrinsic band bending at the high-k/SiO2 interface, which produces a constant flatband shift for a given dielectric stack. Accordingly, the expression for the MOS capacitor flatband voltage must be
modified under the assumption that any anomalous VT/VFB shift is caused by the dipole effect. The general expression for the flatband voltage of a MOS capacitor is given as:

VFB=Φms−qεox∫0EOTxρ(x)dx+ dipole (1)

In this framework, Φms represents the work function difference between the gate and the substrate, εox is the relative permittivity of SiO2,x denotes the distance from the gate, EOT is the effective oxide thickness of the dielectric stack, and ρ(x) corresponds to the fixed charge density within the dielectric layers or at the interfaces [6]. In the calculation, only fixed charges are considered; these may be located at the SiO2/SiC interface, within the bulk of the SiO2, at the high-k /SiO2 interface, within the bulk of the high-k dielectric, or at the gate/high-k interface. For high-quality SiO2, the bulk charge density can typically be neglected. Any charge or dipole at the dielectric/gate interface can be accounted for by using an experimentally determined effective gate work function. Therefore, in all subsequent equations, Φms should be regarded as the effective work function difference between the gate and the substrate. For a Al2O3/SiO2 dual-layer stack, the flatband voltage equation can be modified as follows:

VFB=Φms−qεox(QSiO2EOT+QAl2O3EOTAl2O3+ρAl2O3EOTAl2O32)+ dipole (2)

Here, QSiO2 and QAl2O3 represent the fixed charge densities at the SiO2/SiC interface and the Al2O3/SiO2 interface, respectively. In the derivation, the bulk charge density within the high-k layer is assumed to be uniform. From Equation (2), it follows that, in the absence of any bulk charge, the flatband voltage should exhibit a linear dependence on EOT. Our experimental results indicate that high- kAl2O3 contains a negligible amount of bulk charge; therefore, the bulk charge term in Equation (2) can be ignored in the following discussion. To verify the presence of a dipole effect, the charge densities QSiO2 and QAl2O3 must be extracted. When the Al2O3 thickness is fixed, Equation (2) can be simplified and written as:

VFB=Φms−qεox(QSiO2EOT+QAl2O3EOTAl2O3)+ dipole (3)

With Equation (3), the fixed charge density at the ALDSiO2/SiC2 interface can be extracted by varying SiO2 thickness while the Al2O3 thickness is fixed.

VFB=Φms−qεox(QSiO2+QAl2O3)EOT+qεoxQAl2O3EOTSiO2+ dipole (4)

Similarly, using another set of capacitors with varying Al2O3 thickness, the fixed charge density at the ALDAl2O3/SiO2 interface can be extracted using Equation (4).

Experiments

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MOS capacitors were fabricated on n-type, Si-face ( 0001 ) 4H-SiC substrates with a nitrogen doping concentration of ND=6×1015/cm3. Following surface cleaning in solvents and diluted hydrofluoric (HF) acid, the samples were immediately transferred to an ALD system for SiO2 deposition at 150∘C. Variation in SiO2 thickness across the MOS capacitors was achieved by wet etching in diluted HF . For the dual-layer capacitors, an ALDAl2O3 layer was subsequently deposited at 200∘C after the SiO2 etching step. Post-deposition annealing (PDA) was carried out in a rapid thermal anneal (RTA) system at 900∘C in pure N2O ambient. The gate electrode was formed by RF sputtering of tantalum nitride (TaN) capped with tungsten (W). A post-metallization anneal (PMA) in N2 ambient was then performed to mitigate sputter-induced damage. The capacitance-voltage ( C−V ) characteristics were measured using an HP 4284A precision LCR meter. Flatband voltage and effective oxide thickness (EOT) were extracted from the 1MHzC−V curves with the CVC program, using 4H−SiC material parameters [7]. Lateral MOSFETs were fabricated on Al-doped ( NA=5×1015 cm3 Si-face (0001) 4H-SiC substrates. Source and drain regions were formed by phosphorus
implantation followed by activation annealing. After field oxide deposition and patterning, the samples underwent the same surface cleaning, ALD dielectric deposition, PDA, and TaN/W gate electrode deposition and patterning steps used for the capacitors. Contact holes were etched in HF solution prior to the N2O PDA. The source/drain ohmic contacts were formed by nickel silicide after the gate stack fabrication. Finally, MOSFET characteristics were measured using a Keithley 4200 semiconductor parameter analyzer.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

The C−V characteristics of MOS with ALDSiO2 and Al2O3/SiO2 dielectrics are shown in Fig. 1 (a). The C-V curves measured at different frequencies exhibit minimal frequency dispersion. The flatband voltage and effective oxide thickness of the MOS capacitors were extracted to evaluate the dependence of VFB on oxide thickness. The effective work function of TaN gate electrode on Al2O3 and SiO2 dielectrics was individually extracted from measured capacitor C−V data of MOS capacitors with single-layer Al2O3 and SiO2. The effective work function of TaN on ALD SiO2 and ALD Al2O3 is 4.47±0.01eV and 4.56±0.04eV, respectively. As shown in Fig. 1 (b), VFB values of capacitors with only ALDSiO2 and those with dual-layer stacks both show a linear dependence on oxide thickness, indicating a negligible amount of bulk fixed charge in the oxide. The linear fitting line of the dual-layer devices shows a significantly higher y-intercept than that of the ALD SiO2 samples, suggesting the existence of a dipole. The positive slopes of the linear fits indicate negative effective fixed charges, consistent with prior observations in ALDSiO2 dielectrics [8]. Table 1 summarizes the extracted charge density and interface state density. Based on calculations, the dipole-induced VFB shift is estimated to be 0.65±0.15 V. The addition of Al2O3 reduces the gate leakage due to the incorporation of a high-k layer in the oxide stack.

[picture]

Fig. 1. (a) C-V characteristics of MOS Capacitors and (b) Flatband voltage vs. oxide thickness of MOS Capacitors with 30 nm ALD SiO2 and ALD Al2O3/SiO2 after 900∘CN2O PDA. Both sets of samples contain ALD SiO2 with various thicknesses.

Fig. 1. (a) C-V characteristics of MOS Capacitors and (b) Flatband voltage vs. oxide thickness of MOS Capacitors with 30 nm ALD S i O 2 and ALD A l 2 O 3 / S i O 2 after 900 ∘ C N 2 O PDA. Both sets of samples contain ALD S i O 2 with various thicknesses.

Figure 2 (a) shows the average flatband voltage for ALDSiO2 and Al2O3/SiO2 dielectrics after postdeposition annealing (PDA) at 900∘C and 1000∘C. The Al2O3/SiO2 stack maintains a higher flatband voltage compared to SiO2 indicating the persistence of the interface dipole between Al2O3 and SiO2. Figure 2 (b) presents the gate leakage characteristics, where the incorporation of an Al2O3 layer effectively suppresses gate leakage in the low- and moderate-field regions. These results confirm that the Al2O3/SiO2 dielectric stack provides superior electrical performance, offering both enhanced flatband voltage stability and reduced leakage current relative to a single SiO2 dielectric.

Table I. Extracted parameters from MOS capacitor with ALD SiO2 and Al2O3/SiO2 after 900∘C PDA.

Dielectric | Parameters
Charge Density superscript number | D mathematical formula at mathematical formula - superscript number

[picture]

Fig. 2. (a) Average flatband voltage after two different PDA temperatures and (b) Gate leakage characteristics of MOS capacitors with single SiO2 and dual Al2O3/SiO2 dielectrics.

Fig. 2. (a) Average flatband voltage after two different PDA temperatures and (b) Gate leakage characteristics of MOS capacitors with single S i O 2 and dual A l 2 O 3 / S i O 2 dielectrics.

[picture]

Fig. 3. Ids-Vgs curves and mobility of MOSFETs with ALD SiO2 and Al2O3/SiO2.

Fig. 3. Ids-Vgs curves and mobility of MOSFETs with ALD S i O 2 and A l 2 O 3 / S i O 2 .

Lateral MOSFETs were fabricated to validate the MOS capacitor results. As shown in Fig. 3, the lateral MOSFET with an ALDAl2O3/SiO2 dual-layer gate dielectric exhibits a threshold voltage that is 1.24 V higher than that of the device without Al2O3, accompanied by an increase of 1.5 nm in effective oxide thickness (EOT) due to the additional Al2O3 layer. Considering the effect of the negative fixed charge, the increase in EOT from the Al2O3 layer accounts for approximately 0.6 V of the observed VT shift. The remaining increase in VT is therefore attributed to the dipole effect.

Importantly, no degradation in field-effect mobility or subthreshold swing was observed. These results demonstrate that the ALDAl2O3/SiO2 dual-layer stack is an effective approach to increase the threshold voltage of SiO2-based devices without compromising device performance. Furthermore, the findings confirm that the dipole does not introduce additional scattering centers at the SiC/dielectric interface compared to devices with only ALD SiO2. In addition, the ALD-deposited dual-layer stack can be extended to other alternative semiconductor substrates to induce a positive threshold voltage shift.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

We have demonstrated the existence of an electric dipole at the Al2O3/SiO2 dual-layer stack deposited by ALD on 4H−SiC substrates. After N2O post-deposition annealing, the dual-layer stack exhibits a dipole-induced voltage of 0.65±0.15 V. Lateral MOSFET results further confirm that the incorporation of Al2O3 induces a positive threshold voltage shift of 1.24 V , accompanied by suppressed gate leakage and without degradation in mobility or subthreshold swing. These results highlight that Al2O3/SiO2 stacks not only enable threshold voltage tuning but also improve dielectric properties. This approach provides an effective pathway to achieve a positive threshold voltage in 4H-SiC MOSFETs and can be extended to other wide bandgap semiconductor devices where thermal oxidation of SiO2 is not feasible.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

T. -H Kil, M. Noguchi, H. Watanabe, and K. Kita, "Impact of Al2O3/SiO2 interface dipole layer formation on the electrical characteristics of 4H-SiC MOSFET," IEEE Electron Device Letters, 43 (1), 2022.

P. D. Kirsch et al, "Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning," Appl. Phys. Lett., vol. 92, no. 9, pp. 092 901, Mar. 2008.

K. Kita and A. Toriumi, "Origin of electric dipoles formed at high-k/ interface," Appl. Phy. Lett., vol. 94, no. 13, pp. 132 902, April. 2009.

B. Lee, S. Novak, D. Lichtenwalner, X. Yang, and V. Misra, "Investigation of the origin of modulation by capping layer approaches for NMOS application: Role of La diffusion, Effect of host high-k layer, and interface properties," IEEE Transactions on Electron Devices, Vol. 58, no. 9, pp. 3106-3115, 2011.

S. M. George, "Atomic layer deposition: An overview," Chem. Rev., vol. 110, no. 1, pp. 111131, Jan. 2010.

R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, "A capacitance-based methodology for work function extraction of metals on high- ," IEEE Electron Device Lett., vol. 25, pp. 4202004.

J. R. Hauser and K. Ahmed, "Characterization of ultra-thin oxides using electrical C-V and IV measurements," in Proc. AIP Conf., 1998, pp. 235-239.

X. Yang, B. Lee, and V. Misra, "Electrical characteristics of deposited by Atomic Layer Deposition on 4H-SiC after nitrous oxide anneal," IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2826-2830, 2016.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 15-20

doi: 10.4028/p-48Kf9g

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-23

Accepted:
2026-02-26

Online:
2026-05-20

Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

Wei-Chen Yu 1,a*, Chia-Lung Hung 1,b, Wei-Cheng Lin 2,c, Wei-Ting Lin 1,d, Tejender Singh Rawat 1,e, Yi-Kai Hsiao 1,f, Tian-Li Wu 2, g and Hao-Chung Kuo 1,2,h

1 Hon Hai Research Institute, Hsinchu city, Taiwan, R.O.C.

2 National Yang Ming Chiao Tung University, Hsinchu city, Taiwan, R.O.C.

a* wayne.wc.yu@foxconn.com, b kevin.cl.hung@foxconn.com, c wclin.st11@nycu.edu.tw, d  bruce.wt.lin@foxconn.com, ètejender.s.r@foxconn.com,  9tlwu@nycu.edu.tw, hao-chung.kuo@foxconn.com

Keywords: SiC MOSFETs, gate oxide, ALD, hysteresis, CV characteristics, NO annealing.

Abstract

This work investigates the impact of different gate oxide fabrication schemes on the electrical characteristics of 4H−SiC planar MOSFETs. Three processes with a target thickness of 50 nm were implemented: (1) thermal oxidation with NO annealing at 1350∘C (actual thickness: 52 nm ), (2) ALD-grown oxide with NO annealing at 1250∘C (actual thickness: 43 nm ), and (3) a stacked 20 nm thermal/ 30 nm ALD oxide structure with NO annealing at 1250∘C (actual thickness: 47 nm ). Electrical characterization included IdVg,CV, and IgEox measurements. Results show that Condition 1 exhibits the lowest leakage and best uniformity, and demonstrates strong oxide integrity without soft breakdown events. In contrast, Condition 2 and 3 show increased leakage, higher variability, and evidence of soft breakdown, suggesting greater interfacial weakness likely due to incomplete passivation of ALD-related defects at the lower annealing temperature. However, a surprising trend was observed in the CV analysis: Condition 2's flat band voltage ( VFB ) is closest to the ideal 0 V , indicating a lower fixed charge density than Condition 1[1], which has the most negative VFB(≈−2 V). The hysteresis results further highlight differences, with Condition 3 showing the largest hysteresis window ( ΔVth =0.13 V ). These findings suggest that while the ALD process coupled with a lower-temperature NO anneal (Condition 2) can effectively reduce fixed charges, it does not fully eliminate interfacial defects responsible for increased leakage and soft breakdown. Our results underscore the complex trade-offs in different fabrication schemes, emphasizing that careful interface engineering beyond conventional NO annealing is required to ensure reliable performance in SiC MOSFETs.

Introduction

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Wide bandgap semiconductors such as 4H−SiC have enabled significant progress in high-power and high-temperature electronics, offering advantages in efficiency and miniaturization compared to traditional Si devices [2]. However, the performance and reliability of SiC MOSFETs remain constrained by the quality of the gate oxide and the SiC/SiO2 interface. Unlike Si MOSFETs, where decades of process optimization have led to highly controlled interface states, the SiC/oxide system still suffers from high interface trap density ( Dit ), charge trapping, and threshold voltage instability. While thermal oxidation followed by nitric oxide (NO) annealing remains the industrial standard [3], alternative approaches such as atomic layer deposition (ALD) or composite dielectric stacks are actively investigated [4]. These three specific schemes, thermal, ALD, and stacked oxides were selected in this study to compare the trade-offs between the superior interface quality of hightemperature thermal oxides, the low-temperature deposition benefits of ALD, and the potential synergistic effects of a combined stack. Each oxide scheme affects key device parameters such as threshold voltage ( Vth  ), leakage current, channel mobility, and long-term reliability. Therefore, systematic evaluation of different oxide processes is critical for advancing SiC MOSFET performance.

This work investigates three gate oxide formation schemes applied to lateral n -channel 4H−SiC planar MOSFETs. Both capacitance voltage (CV) and current voltage ( IdVg ) characteristics were measured to capture interface-related effects such as hysteresis and trap activity, in addition to standard parametric testing of leakage and breakdown reliability.

Experimental

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The baseline process flow for lateral n -channel 4 H -SiC MOSFETs is shown in Figure 1. Only the gate oxide formation step differs among the three experimental conditions:

Condition 1: 50 nm thermal oxidation +NO annealing at 1350∘C for 1 hr (actual thickness: 52 nm ).

Condition 2: HF surface clean +50 nm thermal ALD +NO annealing at 1250∘C for 1 hr (actual thickness: 43 nm ).

Condition 3: 20 nm thermal oxidation +30 nmALD+NO annealing at 1250∘C for 1 hr (actual thickness: 47 nm ).

[picture]

Fig. 1. Baseline thermal oxidation process flow after implantation and activation.

Fig. 1. Baseline thermal oxidation process flow after implantation and activation.

Electrical characterization:

CP testing: threshold voltage (Vth), leakage (IDSS), and body diode forward drop (VSD). Good die rate was defined as the % of dies falling within median ±3σ.

IdVg sweeps: measured with Vd fixed at a small bias, gate bias swept forward/reverse. Vth extracted at Id=1×10−5 A. Hysteresis window defined as ΔV th between sweeps.

CV sweeps: small-signal AC capacitance measurement across accumulation and inversion, forward/reverse bias. Frequency dispersion and stretch-out analyzed for trap effects.

IgEOX test: oxide integrity verified by gate leakage breakdown measurement.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

Electrical Properties

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

Tables 1 and 2 summarize statistical results.

Condition 1 shows the highest Vth (2.49 V), lowest leakage (I DSS: 6.1E-5 A), and best uniformity.

Condition 2 and 3 demonstrate comparable VSD but increased leakage and higher σ, suggesting greater variability.
These differences indicate that ALD-based oxide processes may introduce additional interfacial issues not fully addressed by conventional NO annealing. Furthermore, the variations in Vth and leakage across these schemes are expected to influence the carrier mobility and channel resistance. While not directly measured here, the increased variability in Condition 2 and 3 potentially stems from a higher density of near-interface traps ( Nit ) which can enhance Coulomb scattering, thereby impacting the overall MOSFET conduction performance.

Table 1. Gate oxide thickness and error for Each Gate Oxide Process Condition.

Experiment | Condition 1 | Condition 2 | Condition 3
Ideal = 50 nm | Measure | Error | Measure | Error | Measure | Error
Thickness (nm) | 52 | 4.0% | 43 | 14.0% | 47 | 6.0%

Table 2. Summary of Electrical Performance and Yield for Each Gate Oxide Process Condition.

Experiment | Condition 1 | Condition 2 | Condition 3
Item | Median | RateGood die STDEV | Median | RateGood die STDEV | Median | RateGood die STDEV
Vth (V) | 2.49 | 100.0% 0.06 | 2.13 | 100.0% 0.06 | 2.28 | 97.2% 0.10
IDSS (A) | 6.1E-05 | 100.0% 6.00E-05 | 1.0E-04 | 88.9% 1.10E-03 | 2.9E-04 | 83.3% 1.70E-03
VSD (V) | 3.42 | 100.0% 0.04 | 3.24 | 100.0% 0.04 | 3.24 | 100.0% 0.04

𝐈𝐝𝐕𝐠Characteristics and Hysteresis

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Representative IdVg curves for the three conditions, measured at a drain bias of VDS=0.1 V, are shown in Figure 2. All devices exhibit complete channel switching behavior. Extracted hysteresis windows are:

Condition 1: ΔV th =0.10 V

Condition 2: ΔV th =0.11 V

Condition 3: ΔV th =0.13 V

Although all shifts are relatively small, the trend clearly indicates that Condition 3 has more active trap states, consistent with its stacked oxide scheme [4]. This increased hysteresis in the stacked structure may be attributed to a higher density of near-interface traps ( Nit ) and border traps, which are often formed at the transition interface between the thermal and ALD layers. Condition 1, with hightemperature NO passivation, shows the most stable switching characteristics, indicating effective reduction of shallow traps at the SiC/SiO2 interface.

[picture]

Fig. 2. (a) Forward and reverse IdVg curves for three conditions. (b) Curves for Condition 1. (c) Curves for Condition 2. (d) Curves for Condition 3.

Fig. 2. (a) Forward and reverse I d V g curves for three conditions. (b) Curves for Condition 1. (c) Curves for Condition 2. (d) Curves for Condition 3.

CV Characteristics

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

Figure 3 shows the CV results measured on dedicated MOS capacitor structures, which reveals distinct electrical characteristics, directly correlated with the oxide layer properties.

[picture]

Fig. 3. CV Curves for 3 Conditions.

Fig. 3. CV Curves for 3 Conditions.

The accumulation capacitance ( Cox ), measured at positive gate bias, inversely correlates with the oxide thickness. Our results show that Condition 2, with a measured thickness of 43 nm , exhibits the highest capacitance ( 8.5×10−8 F/cm2 ). In contrast, Condition 1, at 52 nm , has the lowest capacitance ( 7.1×10−8 F/cm2 ), and Condition 3, at 47 nm , falls in between ( 7.8×10−8 F/cm2 ). This data confirms the expected relationship between oxide thickness and capacitance [5].
The flat band voltage ( VFB ), a key indicator of fixed charge density, shows a surprising trend. The CV curve for Condition 2 is positioned closest to the ideal 0 V( VFB≈−1 V), suggesting it has the lowest positive fixed charge density among the three. Condition 1's curve is the most negatively shifted ( VFB≈−2 V ), indicating a higher concentration of positive fixed charges, despite being a thermal oxidation process. Condition 3's VFB is intermediate ( VFB≈−1.5 V ). This suggests that the NO annealing process at 1250∘C for the ALD film (Condition 2) is more effective at reducing fixed charges than the 1350∘CNO annealing for the thermal oxide (Condition 1). The lower fixed charge in Condition 2 may be attributed to reduced thermal-induced stress compared to the 1350∘C process. In conclusion, while Condition 2 demonstrates the lowest fixed charge density and highest capacitance due to its thinner film, its interface quality is not optimal [6]. This is evidenced by the increased frequency dispersion and stretch-out observed in the CV characteristics, pointing to a higher
density of interface traps ( Dit ) in the ALD-based samples. Conversely, Condition 1 and Condition 3 show better interface quality but suffer from higher fixed charge densities. These results highlight the complex trade-offs between different fabrication processes in achieving optimal electrical properties for MOS devices.

Oxide Reliability (IgEox)

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

Figure 4 compares the gate leakage and breakdown characteristics of the three process conditions.

Fig. 4. IgEox Curves for 3 Conditions.

An examination of the initial leakage current reveals a distinct difference. At low electric fields, Condition 2 exhibits a slightly higher initial leakage current compared to Conditions 1 and 3. This observation strongly suggests that defects are present not only within the bulk of the pure ALD film but, more importantly, at the direct interface between the ALD layer and the SiC substrate. Such an interface, formed without an intervening thermal oxidation layer, may contain a higher density of dangling bonds and defects that act as easy pathways for current, even under low-stress conditions [7]. Specifically, the interface chemistry of ALD films on SiC often suffers from residual carbon clusters or sub-oxides (e.g., SiOx ) formed during the initial deposition stages, which are not effectively removed by the 1250∘C NO anneal.
The breakdown behavior also highlights the critical role of the interface. Condition 3, which combines a thermal oxide layer with an ALD layer, shows the weakest performance, experiencing a hard breakdown at a relatively low electric field of approximately 10MV/cm. This premature failure can be attributed to the combined effects of defects from both processes, creating a vulnerable interface at the junction of the thermal oxide and ALD layers, leading to an early breakdown.
In contrast, while the pure thermal oxide in Condition 1 and the pure ALD film in Condition 2 ultimately fail at a higher electric field, their breakdown characteristics differ. Condition 2's curve is notably smooth and free of significant steps, indicating a high-quality, uniform dielectric with superior integrity. Condition 1, however, shows several soft breakdown events sudden increases in leakage current before its final hard breakdown. Despite these soft breakdown events, the ultimate hard breakdown voltage for both Condition 1 and 2 is remarkably close, both occurring around 11.5 to 12MV/cm. The soft breakdown events in Condition 1 and the increased leakage in Conditions 2 and 3 likely stem from localized defect-assisted tunneling. In the ALD-based samples, this is intensified by the high density of near-interface traps ( Nit ) that facilitate trap-assisted tunneling (TAT) at lower fields, acting as precursors to breakdown.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

This study systematically compared three gate oxide schemes in 4H-SiC planar MOSFETs, revealing nuanced trade-offs in their electrical performance.

Condition 1 (thermal + high-temp NO): This scheme demonstrates the best overall device uniformity and lowest leakage current. The IgEox curve confirms its superior dielectric integrity, showing no soft breakdown events. However, its CV curve is the most negatively shifted, indicating the highest concentration of positive fixed charges among the three.

Condition 2 (ALD + low-temp NO): While this process results in the highest capacitance and the most ideal flat band voltage ( VFB closest to 0 V ), it exhibits slightly higher initial leakage and shows evidence of increased trap activity. This suggests that while the low-temperature NO anneal effectively passivates fixed charges by reducing thermal stress, it is not sufficient to fully mitigate the near-interface traps ( Nit ) and carbon-related defects responsible for gate leakage and soft breakdown.

Condition 3 (stacked thermal/ALD + low-temp NO): This stacked structure demonstrates the weakest oxide reliability, with the earliest hard breakdown and the largest hysteresis window ( ΔVth  ), pointing to the highest trap activity likely at the stacked oxide interface.
In conclusion, our results highlight that no single process provides a clear advantage across all electrical metrics. While ALD-based approaches offer flexibility for future scaling, achieving stable and reliable performance requires dedicated interface engineering to address both fixed charges and trap-assisted conduction mechanisms. Future work should explore optimized pre-cleaning, alternative passivation chemistries, or modified stack architectures to improve the reliability of ALD-based gate oxides.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

C. Kim, et al., Appl. Phys. Lett. 100, 082104 (2012).

M. Östling, R. Ghandi, and C.-M. Zetterling, in Proceedings of the 23rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) (IEEE, 2011), pp. 10-17.

P. Jamet, S. Dimitrijev, and P. Tanner, J. Appl. Phys. 90, 5058 (2001).

S. Li, J. Luo, and T. Ye, ECS J. Solid State Sci. Technol. 12, 053006 (2023).

S.K. Sinha and S. Chaudhury, IEEE Trans. Nanotechnol. 12, 958 (2013).

A.B. Renz, et al., Mater. Sci. Semicond. Process. 122, 105527 (2021).

P. Deák, et al., J. Phys. D: Appl. Phys. 40, 6242 (2007).

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The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 21-28

doi: 10.4028/p-0EmUTi

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-05

Accepted:
2026-03-16

Online:
2026-05-20

Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

Harsha Vardhan Manchineni 1,2,a*, Andre Wachowiak 2, b and Thomas Mikolajick 1,2,c

¹NaMLab gGmbH, Nöthnitzer Str. 64a, Dresden, Saxony, 01187, Germany

2 Chair of Nanoelectronics, TU Dresden, Dresden, Saxony, 01187, Germany

a*Harsha.Manchineni@namlab.com, b Andre.Wachowiak@namlab.com, c  Thomas.Mikolajick@namlab.com

Abstract

The increased demand for SiC power MOSFETs requires gate dielectrics with low defect densities and high reliability under high electric field and temperature conditions. In this work, we examine how oxidant chemistry and deposition temperature affect the electrical properties of Al2O3/SiO2 bilayer dielectrics formed in n-type 4H−SiC MOS capacitors. These structures consist of a thin SiO2 interfacial layer, over which Al2O3 is deposited via ALD using three different oxidants at a temperature of 150−350∘C. Electrical characterization shows that the choice of oxidant influences the flat band voltage shift and leakage current density, with a process-dependent trade-off between optimizing each parameter. These findings highlight that precise control of oxidant chemistry during ALD is essential for balancing flat band voltage stability with leakage suppression, and that multilayer-specific conduction models are critical for accurately predicting high electric field leakage characteristics in advanced SiC gate stacks.

Keywords: 4H−SiC MOS capacitors, MOSFET, bilayer gate dielectric, Al2O3/SiO2 stacks, atomic layer deposition (ALD), oxidant chemistry, flat band voltage shift, conduction mechanisms, interface trap density, dielectric strength, high electric field barrier suppression.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

Silicon carbide (SiC) has emerged as a leading wide-bandgap semiconductor for high-voltage and high-power electronic devices due to its large critical electric field ( ~3MV/cm ), high electron saturation velocity ( ~2×107 cm/s ), and superior thermal conductivity ( ~3.7 W/cm·K ) [1, 2]. These intrinsic material properties enable the fabrication of compact devices with reduced specific onresistance and enhanced efficiency compared to silicon-based power devices [3]. A unique advantage of SiC compared to other wide band gap materials is its ability to form a silicon dioxide (SiO2) through thermal oxidation, enabling the development of SiC MOSFETs with a well-established dielectric system [4]. Thermally grown SiO2/SiC interfaces currently exhibit the lowest interface state density (Dit ) among alternative dielectrics on SiC[5]. However, the Dit  at the SiO2/SiC interface remains one order of magnitude higher than that of conventional SiO2/Si interfaces, leading to mobility degradation, threshold voltage instabilities, and long-term reliability concerns [6-7, 15].
Furthermore, the reliance on SiO2 as a gate dielectric in SiC -based devices constitutes a fundamental limitation that hinders the full exploitation of SiC's superior intrinsic properties. Due to the relatively low dielectric constant of SiO2(κ≈3.9), nearly 2.5 times smaller than that of 4H−SiC(κ≈9.7), a significant portion of the applied bias drops across the oxide rather than the semiconductor, resulting in elevated electric fields within the dielectric [5, 15]. To address this imbalance, high- κ dielectrics have been widely investigated. High-k dielectrics offer several advantages: their higher dielectric constant reduces the equivalent oxide thickness (EOT) while lowering the electric field in the dielectric for a given applied voltage [8, 15]. The significant advantages of using aluminum oxide (Al2O3) are its large bandgap, the large band offsets to SiC, and the high breakdown electric field compared to other high-k dielectrics. [8]. Nevertheless, the direct deposition of high-k dielectrics on SiC surfaces typically introduces higher defect densities than thermal SiO2, mainly due to dangling bonds, oxygen vacancies, and interface reaction products formed during deposition [9, 16]. These
interfacial traps cause charge trapping/detrapping dynamics, manifesting as detrimental threshold voltage shifts in MOSFETs.
A promising strategy to mitigate these challenges uses hybrid gate stacks, where a thin interfacial SiO2 layer (1−2 nm) is thermally grown on SiC , followed by deposition of a thicker high-k dielectric such as Al2O3 by atomic layer deposition (ALD) [6, 9]. This stack architecture leverages the superior interface quality of SiO2 with the enhanced dielectric properties of Al2O3. However, introducing an additional SiO2/ high-k interface creates another potential defect plane, and its structural and electrical properties are strongly influenced by ALD process conditions such as oxidant chemistry, precursor reactivity, and deposition temperature. For instance, oxidants can significantly alter the defect density and chemical bonding at the interface, while deposition temperature dictates the film's density, hydroxyl incorporation, and stoichiometry [10-12]. In addition to interface quality, understanding the conduction mechanisms governing leakage currents is critical for assessing dielectric robustness. Several leakage pathways are typically observed in SiC MOS capacitors with high-k or hybrid dielectrics, including Schottky emission (SE), Poole-Frenkel emission (PFE), trap-assisted tunneling (TAT), and Fowler-Nordheim (FN) tunneling [13, 14]. The dominant leakage mechanism can be extracted by analyzing temperature-dependent leakage current measurements and fitting the respective conduction mechanism models, providing insights into trap distributions and dielectric reliability.
In this work, we systematically study the influence of different ALD oxidants (like O2-plasma, water, Ozone) and deposition temperatures on the dielectric properties of Al2O3/SiO2/SiC stacks, and examine the conduction mechanisms responsible for the observed leakage currents. The breakdown electric field, leakage current density, and conduction mechanisms are analyzed to assess capacitors.

Experimental Methods

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Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated on n-type 4H-SiC substrates with a 2 nmSiO2 interfacial layer. A 20 nmAl2O3 film was deposited by ALD using trimethylaluminum (TMA) as the aluminum precursor and three different oxidants (A, B, C), with deposition temperatures between 150∘C and 350∘C. Following dielectric deposition, a 10 nm TiN layer was deposited by reactive sputtering under ultra-high vacuum to serve as the gate electrode. Then, post-deposition annealing at 480∘C for 1 min in an argon ambient was performed, which kept the Al2O3 film in an amorphous state. The electron-beam evaporation of 10 nmTi/30 nmPt circular pads (diameter varying from 100 to 200μ m ) achieved final contact metallization through a precision shadow mask. Device isolation was performed via dry etching to define the active capacitor regions. A schematic of the test structure is shown in Fig. 1.

Fig. 1. Cross-section schematic of the fabricated MOS capacitor on n-type 4H−SiC with a 2 nmSiO2 interlayer, 20 nm ALD-deposited Al2O3, TiN gate, and Ti/ Pt contacts used for electrical characterization.

Electrical characterization employed a Keithley 4200A-SCS parameter analyzer. Capacitance Voltage ( C−V ) measurements were conducted in dual-sweep mode (from depletion to accumulation and vice versa) to assess the flat band voltage shifts ( ΔVfb ), using an AC modulation frequency of 100 kHz with an amplitude of 25 mV . Current-voltage (I-V) measurements were carried out over a bias range extending into accumulation until dielectric breakdown, with additional temperaturedependent I-V measurements performed from 25∘C to 150∘C to elucidate charge transport
mechanisms and thermal activation effects. The reported leakage current density (AVG J throughout the paper) and ΔVfb represent the average value of five MOSCAP devices.

Results and Discussions

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When MOSCAPs on n-type 4H−SiC are biased in accumulation (at gate voltages higher than the flat band voltage (Vfb) ), electrons from the SiC conduction band can be captured by interface traps or near-interface oxide traps at the SiO2/SiC interface. In addition, carriers may tunnel through the gate dielectric and get trapped in bulk oxide traps within the dielectric layer [4, 17-19]. The capture of these negative charges perturbs the electric field distribution across the MOS structure, producing a positive ΔVfb, resulting in a shift of C−V characteristics. Such trapping is a critical reliability concern, as it can directly translate into threshold voltage instability in MOSFETs and degrade long-term device performance [8]. This trapped charge is often quasi-permanent due to a lack of minority charge carriers: the emission time constants of the responsible traps are much longer than the measurement timescale, strongly preventing detrapping during standard C−V sweeps [18,20]. For thermally grown SiO2 on 4H−SiC, the ΔVfb magnitude is typically small ( ΔVfb≈0.8 V in our measurements). Nevertheless, still quasi-permanent, as evidenced by subsequent sweeps reproducing the initial sweep's reverse branch (see Fig. 2). This behavior is consistent with deep electron traps possessing long emission time constants, e.g., with high emission activation energies, leading to incomplete detrapping within the experimental time window [17,19,21].

[picture]

Fig. 2. Normalized capacitance-voltage characteristics of a 15 nm thick pure SiO2 dielectric on 4 H SiC with a TiN top electrode, showing a 0.8 V positive ΔVfb after three successive measurements. Arrows represent the direction of the sweep. Inset: schematic of the fabricated MOS capacitor test structure.

Fig. 2. Normalized capacitance-voltage characteristics of a 15 nm thick pure S i O 2 dielectric on 4 H SiC with a TiN top electrode, showing a 0.8 V positive Δ V f b after three successive measurements. Arrows represent the direction of the sweep. Inset: schematic of the fabricated MOS capacitor test structure.

Incorporating a high-k dielectric such as Al2O3 can increase the observed ΔVfb compared to pure SiO2. The oxidant chemistry during ALD determines Vfb stability among the other process parameters [10]. Our measurements for a fixed deposition temperature (Fig. 3) reveal that the leakage current density and the ΔVfb vary significantly with the used oxidant. The Vfb of the ideal MOSCAP is expected to be ~1 V due to the work function difference between the TiN electrode and the n-type 4H-SiC [22]. The difference in Vfb observed during the initial upsweep between the MOSCAPs for different oxidants compared to the ideal expectation most likely arises from different amounts of fixed charges located at the interfaces or within the bulk of the Al2O3 layer [8, 14] (Fig. 3A). Oxidant C might act more aggressively on the interface since it causes the highest initial shift in the MOSCAPs. Furthermore, an additional offset in Vfb can also stem from dipole formation at the high- k/SiO2 interface, irrespective of the electrode material, as reported by Iwamoto et al. [22].
Furthermore, a much smaller ΔVfb is observed in our MOSCAPs when oxidant A(ΔVfb~0.4 V) is used compared to oxidants B and C(ΔVfb>2 V) (Fig. 3A). The reduced ΔVfb for oxidant A can be attributed to electron detrapping from bulk or near-interface traps and escaping to the top electrode during the measurement, reducing ΔVfb. This interpretation is based on observed higher leakage current characteristics for oxidant A compared to oxidants B and C (Fig. 3B), which indicate
enhanced pathways facilitating charge carrier transport in the Al2O3 film deposited using oxidant A . While no compromise seems evident for obtaining low ΔVfb and low leakage current, a trade-off emerges: lowering the ΔVfb can often lead to higher leakage current, and vice versa, solely by altering the oxidant chemistry [10]. For oxidants B and C , the influence of deposition temperature on the electrical performance of MOSCAPs is low (Fig. 4). In contrast, by using oxidant A, the MOSCAP exhibited a pronounced improvement in leakage characteristics and dielectric strength within the 200−250∘C window, suggesting optimal film quality and reduced defect density in this regime. However, this temperature range did not coincide with the minimal ΔVfb  observed near 300∘C (Fig. 4).

[picture]

Fig. 3. A. Normalized capacitance-voltage characteristics of MOSCAPs with Al2O3, deposited with different oxidants ( A,B,C ). Numbers indicate the average ΔVfb measured in the initial dual sweep (arrows indicate the sweep direction). B. Average leakage current density for Al2O3 films deposited with different oxidants (A, B, C) as a function of applied electric field. Stars and numbers denote the corresponding dielectric breakdown electric field strength ( EBD ) of Al2O3 films for different oxidants.

Fig. 3. A. Normalized capacitance-voltage characteristics of MOSCAPs with A l 2 O 3 , deposited with different oxidants ( A , B , C ). Numbers indicate the average Δ V f b measured in the initial dual sweep (arrows indicate the sweep direction). B. Average leakage current density for A l 2 O 3 films deposited with different oxidants (A, B, C) as a function of applied electric field. Stars and numbers denote the corresponding dielectric breakdown electric field strength ( E B D ) of A l 2 O 3 films for different oxidants.

[picture]

Fig. 4. A. Flat band voltage shift ( ΔVfb ), B. Average leakage current density at 4MV/cm, and C . Breakdown electric field for Al2O3 films deposited using oxidants A,B, and C as a function of the deposition temperature in Al2O3 ALD deposition.

Fig. 4. A. Flat band voltage shift ( Δ V f b ), B. Average leakage current density at 4 M V / c m , and C . Breakdown electric field for A l 2 O 3 films deposited using oxidants A , B , and C as a function of the deposition temperature in A l 2 O 3 ALD deposition.

To further evaluate leakage behavior, temperature-dependent I-V measurements were performed on Al2O3 films deposited at 300∘C using different oxidants (Fig. 5). Among the three, Al2O3 films deposited with oxidant A exhibited the highest leakage with minimal temperature dependence. In contrast, pronounced temperature sensitivity was observed when oxidants B and C were used, particularly beyond 5MV/cm, where leakage current increased by nearly an order of magnitude between 25∘C and 150∘C. Simultaneously, the dielectric breakdown electric field decreased by approximately 3MV/cm over the same temperature range. At low electric fields ( <2MV/cm ), the leakage current density approached the resolution limit of the parameter analyzer, preventing quantitative comparison. Notably, this low-leakage regime terminated at different electric field strengths for each oxidant, likely due to the initial Vfb differences between the oxidants discussed previously. For example, in the case of oxidant C , the leakage onset occurred near 3MV/cm (Fig. 5).

In the moderate electric field regime ( 2−5MV/cm ), leakage current exhibited a rather low temperature dependence. This suggests that thermally activated processes are less dominant in this range.

[picture]

Fig. 5. Average leakage current density as a function of electric field for Al2O3 films deposited at 300∘C using oxidants A,B, and C in ALD and measured at 25∘C to 150∘C.

Fig. 5. Average leakage current density as a function of electric field for A l 2 O 3 films deposited at 300 ∘ C using oxidants A , B , and C in ALD and measured at 25 ∘ C to 150 ∘ C .

To gain deeper insight into the underlying charge transport mechanism. We fitted the measured current using established conduction models with some free parameters to evaluate the conduction mechanism responsible for the observed leakage [13, 14, 23, 24]. The methodology for this calculation is detailed in [13]. This fitting procedure enabled the extraction of free model parameters. In the moderate electric field regime, the calculated current from the TAT model (analytical expression is mentioned in [23]) closely matched experimental data (see Fig. 6), confirming that TAT is the primary conduction mechanism under these conditions with the following argumentation. Since FN tunneling becomes significant only at high electric fields and PFE is highly temperature dependent, both mechanisms can be discounted as a major contributor. Electrode-limited SE can be ruled out as a major contributor due to the large conduction band offset between the SiO2 interlayer and SiC. Moreover, since the electrode was the same in our experiments and using different oxidants during the deposition of Al2O3 produced distinct leakage current levels, SE can also be excluded as the primary mechanism in this electric field range [13,24]. As a result, we attribute the leakage current in the moderate electric field regime mainly to TAT, which aligns with previous studies on high-k and Al2O3 gate stacks with SiO2 interlayer [13, 14]. The extracted model parameters and calculated results for all three oxidants are shown in Fig. 6, offering quantitative insights into trap characteristics and how they depend on oxidant chemistry. According to the calculation results, the high leakage level for oxidant A is governed by the highest TAT trap density ( Nt ) for traps having an energy of 0.8 eV below the conduction band of the dielectric (Fig. 6A). The absolute Nt values from our calculations might be underestimated by several orders of magnitude, as evidenced in the literature [23]. However, they indicate how the Nt can vary by changing the oxidant chemistry during the ALD deposition.
At high electric fields exceeding 5MV/cm, our MOSCAPs exhibit a pronounced increase in leakage current beyond a certain threshold at a given temperature when oxidants B and C are used, ultimately leading to dielectric breakdown as mentioned earlier. In this regime, none of the conventional conduction models in our simulations yielded physically reasonable parameter values across all tested mechanisms (SE, PFE, FN, TAT). Consequently, the applied models cannot meaningfully reproduce the leakage characteristics with their significant measurement temperature dependence. One plausible explanation is that most analytical formulations of conduction mechanisms are derived for singlelayer dielectric systems. However, the gate stack in our experiments comprises a bilayer (SiO2/Al2O3), where each dielectric has a different band offset relative to 4H−SiC. This structural complexity can significantly alter carrier transport, as carriers may experience sequential barriers and/or mixed conduction pathways not captured by single-layer models.

[picture]

Fig. 7. Simulated energy-band diagrams of the Al2O3/SiO2 bilayer dielectric stack on n-type 4H−SiC under zero external electric field and close-up at average electric fields of 2.5 and 5.0MV/cm.

Fig. 7. Simulated energy-band diagrams of the A l 2 O 3 / S i O 2 bilayer dielectric stack on n-type 4 H − S i C under zero external electric field and close-up at average electric fields of 2.5 and 5.0 M V / c m .

It is therefore plausible that the observed leakage might arise from a combination of bulk-limited and electrode-limited conduction processes, potentially involving multi-step tunneling or hopping conduction through defect states distributed across both layers [25]. Our band-diagram simulations (Fig. 7) show that at high electric fields (above ~5MV/cm ), the electric field-induced band bending becomes so pronounced that the Al2O3 barrier is almost completely suppressed, enabling enhanced carrier injection by direct tunneling through the 2 nmSiO2 layer. This could explain the increase in leakage after 5MV/cm for oxidants B and C. However, our calculation approach was hindered by the lack of a simple analytical expression for direct tunneling through a trapezoidal barrier with a changing electric field. Furthermore, the observed significant temperature dependence of the leakage characteristic in the high electric field region for oxidants B and C may also indicate charge carrier transport through a combination of carrier injection and a bulk trap-related conduction mechanism with thermally activated processes.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

This study investigates how oxidant chemistry and deposition temperature affect the electrical performance and leakage characteristics of Al2O3/SiO2 bilayer gate stacks on n-type 4H−SiC MOS capacitors. Electrical tests with C−V and temperature-dependent I−V measurements show that oxidant chemistry greatly influences the ΔVfb and leakage current density, with a trade-off between these factors. The impact of the deposition temperature was minimal. Trap-assisted tunneling is identified as the primary conduction process in the moderate electric field range, while PooleFrenkel, Schottky emission, and Fowler-Nordheim tunneling are ruled out. At higher electric fields, simple single-layer dielectric models do not fully explain the leakage behavior, likely due to the complex band alignment of the bilayer system. Band diagram simulations reveal significantly high electric field barrier suppression in Al2O3, suggesting a combination of bulk- and electrode-limited conduction with thermally activated processes. These results emphasize the important role of oxidant chemistry in improving device reliability and highlight the need for modeling methods that consider multilayer dielectric stacks in SiC power electronics.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

This work was co-financed by the European Union and from tax revenues on the basis of the budget adopted by the Saxon State Parliament in Project: LeistungsSchaltEr, no 100687609.

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The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 29-37

doi: 10.4028/p-C8ENIb

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-20

Accepted:
2026-02-26

Online:
2026-05-20

Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

The original version of this paper is available on https://www.scientific.net/MSF.1192.29.pdf

M. Szabo 1,a*, T. Becker 1, b, M. Jank 1,c and T. Erlbacher 2, d

1 Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Schottkystraße 10, 91058, Erlangen, Germany

2 Nexperia Germany GmbH, Stresemannallee 101, 22529 Hamburg, Germany

a* maximilian.szabo@iisb.fraunhofer.de, b  tom.becker@iisb.fraunhofer.de, c michael.jank@iisb.fraunhofer.de, d Tobias.Erlbacher@nexperia.com

Keywords: 4H-SiC, capacitors, metal-oxide-semiconductor (MOS), trench, trench sidewall capacitance, linear component separation.

Abstract

This work proposes a linear, area-based component separation method to extract an effective trench sidewall capacitance from C−V measurements of 4H−SiC UMOS capacitors. Devices were fabricated with two gate-oxide schemes LPCVD TEOS and low-temperature oxidation of LPCVD polysilicon and characterized by I-V and C-V measurements. Planar capacitors show breakdown strength above 9MV/cm. Least-squares decomposition of layout-dependent capacitances enabled the separation of mesa, sidewall and bottom contributions. Additionally, this applying this approach revealed trench-pitch dependent depletion and larger wafer-level thickness variation for the polysilicon-oxidation flow. Reconstruction errors up to 20% indicate that spacing-dependent depletion, corner curvature, fringe and field-oxide capacitances exceed the simple parallel-capacitor model.

Introduction

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Reducing the on-state resistance ( RDS(on) ) of silicon carbide ( SiC ) metal-oxide-semiconductor fieldeffect transistors (MOSFETs) remains a major driver for research and development. State-of-the-art SiC trench MOSFETs (UMOSFETs) reduce RDS( on ) by increasing the channel width per unit area and lowering internal series resistance. Consequently, channel resistance becomes more dominant, and low channel mobility remains as a limiting factor for these devices. High channel resistance is mainly caused by the high density of interface traps ( Dit ) present at the SiO2/SiC interface. Sophisticated optimization processes have been developed to reduce these interface traps. These include preoxidation etching in hydrogen atmosphere [1], high temperature oxidation, post-oxidation annealing in N2 and NO[2,3], as well as the use of chemical vapor deposition (CVD) [1,2], low- pressure chemical vapor deposition (LPCVD) [3], and low-temperature oxidation of polycrystalline silicon [2]. Most of the processes have only been evaluated on planar MOS capacitors (MOSCaps) as the measurement and evaluation of Dit  for the UMOS relevant trench sidewall is a challenge. Results from planar devices do not transfer to trench devices one-to-one due to different crystal orientations and the possibility of etch-induced interface modifications. In this work, we investigate the behavior of Trench MOSCaps (UMOSCaps) with gate oxides fabricated by LPCVD and low-temperature oxidation of undoped LPCVD polysilicon. We propose a method to extract an effective sidewall capacitance and an effective Dit, enabling qualitative comparison between gate-oxide fabrication methods. We also investigate the breakdown behavior of the gate oxides.

Device Fabrication

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The MOSCap fabrication process Fig 1 (a) follows the processing of a SiC-UMOS closely [4]. The structure of the UMOSCaps is depicted in Fig. 1 b. To fabricate both samples an n-type epitaxy layer with a thickness of 12.79±0.34μ m and a nitrogen concentration of 9.55*1015±0.34*1014 cm−3 suitable for 1.2 kV class UMOSFETs, was grown on commercial six inch 4H-SiC substrates. A 1.5μ m thick CVDSiO2 hard mask was deposited and patterned by stepper lithography and structured
by dry etching. Subsequently, SiC trenches with a target depth of 1.3μ m were etched using an ICP dry etching process described by Rusch et al. [5]. The trench depth was measured by structured illumination microscopy over the full wafer and was 1.23±0.01μ m for sample 1 and 1.21±0.01μ m for sample 2 (Fig. 1 (d)). A high-temperature H2 reshape was applied to round the trench top and bottom corners, mitigating field crowding and premature gate-oxide breakdown [4]. Trench geometry was confirmed by focused-ion-beam (FIB) cross-section SEM measurement (Fig. 1 (c)). The measurement of 1.27μ m indicated that structured illumination microscopy underestimated the trench depth by approximately 50 nm . This difference between FIB-SEM and microscopy must be considered when using the optical measurement for further wafer level evaluation.

[picture]

Fig. 1. a) Process flow for UMOSCaps. b) Schematic of fabricated devices. c) FIB-SEM cross-section of a 1μ m wide trench on sample 1 after trench reshape process. d) Wafer map of trench depth measured by structured illumination microscopy on sample 1. e) FIB-SEM cross-section of a final device on sample 1 (LPCVD TEOS oxide). f) FIB-SEM cross-section on a final device on sample 2 (oxidized LPCVD polysilicon).

Fig. 1. a) Process flow for UMOSCaps. b) Schematic of fabricated devices. c) FIB-SEM cross-section of a 1 μ m wide trench on sample 1 after trench reshape process. d) Wafer map of trench depth measured by structured illumination microscopy on sample 1. e) FIB-SEM cross-section of a final device on sample 1 (LPCVD TEOS oxide). f) FIB-SEM cross-section on a final device on sample 2 (oxidized LPCVD polysilicon).

Two approaches to form the gate oxide were used. For sample 1 a sacrificial oxide was grown after the trench reshape process and removed in buffered oxide etch. SiO2 was then deposited by low pressure CVD at a temperature of 710∘C and a pressure of 0.133 mbar using TEOS as a precursor which was subsequently densified at 900∘C to form a layer with 87.7±0.4 nm thickness [3]. For sample 2, undoped polysilicon with a thickness of 32.5±0.4 nm was deposited and oxidized at 850∘C for 8 h in O2 atmosphere. This process was based on a work reported by [2]. Both wafers underwent NO annealing at 1300∘C for 1 h ; post-anneal oxide thicknesses were 94.5±0.6 nm (sample 1 Fig. 1 (e)) and 66.6±0.8 nm (sample 2 Fig. 1 (f)) measured by ellipsometry. In situ phosphorus-doped polysilicon was deposited by LPCVD as the gate electrode and patterned by dry etching to form pads of 1.0 mm2,0.5 mm2, and 0.316 mm2. A 600 nm TEOS oxide was deposited as a field oxide and contact windows were opened by dry etching. Frontside metallization consisted of 100 nm Ti and 3μmAl sputtered onto the frontside and patterned. On the backside, a NiAl contact was sputtered and laser-annealed to form an ohmic contact to the SiC substrate, followed by Al backside metallization [6].

Results and Discussion

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Breakdown Evaluation.

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To evaluate the gate oxides, current voltage measurements (I-V) were done on 40 devices per design. The applied voltage was ramped from 0 V to 100 V and the measurement was stopped at a current compliance of 10 mA . Fig 2 (a) shows the averaged curves of the measurements. Because of the different gate oxide thicknesses of the two gate oxide processes and the variance in the oxide thickness on the trench sidewall, bottom and mesa (Fig. 1 (e) (f)) the current is plotted over the electric field on the trench mesa. To calculate this field the average oxide thickness on the wafer after NO annealing measured via ellipsometry is used (Sample 194.5 nm and Sample 266.6 nm ). The planar designs show a high breakdown field of above 9MV/cm for both gate oxides. Sample 2 shows an earlier onset of Fowler-Nordheim tunneling which might suggest a reduced oxide quality or additional thickness variation in the planar devices.

[picture]

Fig. 2. Leakage current of planar and trenched devices at room temperature and for trenched devices at 175∘C. The electric field is calculated for a) the planar mesa top and b) for the planar devices in the mesa top and for the trenched devices in the smallest oxide thickness.

Fig. 2. Leakage current of planar and trenched devices at room temperature and for trenched devices at 175 ∘ C . The electric field is calculated for a) the planar mesa top and b) for the planar devices in the mesa top and for the trenched devices in the smallest oxide thickness.

For the trench devices the breakdown electric field is significantly lower than for the planar devices. This is mainly caused by the difference in oxide thickness at the trench bottom and trench corners that can be observed for both sample 1 and sample 2. The electric field for the trench capacitors becomes closer to that of the planar devices when calculating with the lowest oxide thickness measured via FIB-SEM. For sample 1 this is the trench bottom with 58.7 nm and for sample 2 the top corner with 54.1 nm . However, the breakdown fields using this approach are slightly larger than for the planar devices which is not expected. This overestimation occurs because the simple calculation does not include field crowding effects that occur on the corners of the trench. Here, only one representative trench was measured by FIB-SEM meaning so it is also possible that even lower oxide thickness is present in the device. Moreover, for a given current value, the current density in the UMOSCap is lower than the current density in the planar MOSCap with identical metallization area.

Capacitance-Voltage measurements.

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Full-wafer high-frequency capacitance measurements ( C−V ) at 100 kHz were performed at room temperature. Depicted in Fig. 3 (a) are the forward and backward capacitance curves for 40 devices on both samples for planar MOSCaps (Table 1, design 1) and UMOSCaps (Table 1, design 3), normalized with respect to the accumulation capacitance. No hysteresis can be observed regardless of design and oxide process. When comparing the absolute values of planar MOSCaps on sample 1 and sample 2, an increased spread of Cox can be observed for the polysilicon oxidation process. Most likely this scheme yields a higher variation in layer thickness over the wafer than the TEOS process. For the planar devices the difference in flat-band voltage can be attributed to the different oxide thickness of both samples as well as different interface properties. For the trench devices, several
distinct slopes can be observed in depletion and weak inversion. This is particularly apparent for the devices on sample 2. The steeper slopes at approx. -6.2 V and -2.9 V are attributed to the different oxide thickness that occurs on the trench mesa, bottom and sidewall.

[picture]

Fig. 3. a) Normalized capacitance-voltage measurements at 100 kHz for trenched and planar designs with 40 devices respectively and the two different gate oxide processes. b) Capacitance-voltage measurements at 100 kHz for all 12 different designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide).

Fig. 3. a) Normalized capacitance-voltage measurements at 100 kHz for trenched and planar designs with 40 devices respectively and the two different gate oxide processes. b) Capacitance-voltage measurements at 100 kHz for all 12 different designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide).

However, the steeper slopes at approx. -10.8 V (sample 2) and -7.7 V (sample 1) are caused by the extension of the space charge region into the trench sidewalls until the trench area is fully depleted and the space charge region starts to extend beyond the trench structure into the semiconductor [7]. This causes a change in effective capacitor surface area leading to in an abrupt reduction in capacitance. This effect is commonly used as the shielding effect in double UMOS transistors and is sensitive to the distance between two trenches [4]. Fig. 3 b) shows representative CV curves of the designs listed in table 1 on one stepper field in the center of sample 1.

Linear Component Separation.

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In this work we expand on work reported by Lim [4], Banzhaf [7] and Guo et al. [8] which all investigated SiC UMOSCaps. The capacitance of a trench MOS capacitor is simplified to consist of three parallel capacitors: the capacitance on the top of the trench Cm, the trench sidewall Cs and the trench bottom Cb. The total capacitance C is the sum of these three contributions:

C(V)=AmCm(V)+AsCs(V)+AbCb(V).(1)

Here, Am,As and Ab, represent the effective areas of the trench top, sidewall, and bottom, respectively. The knowledge about the effective areas allows for determination of the different capacitances by solving a linear system of equations. It is possible to extend this model by adding additional terms in case of significant corner rounding at the trench top and bottom, which has not been done in the scope of this work. A variation of the trench depth might be necessary to increase the accuracy of the method when trying to extract the influence of trench rounding. When no trench depth variation is included in the evaluated devices the influence of the rounding cannot be isolated from the trench sidewall because the area of the rounding is correlated to the trench sidewall area. It should also be mentioned that the behavior of a curved MOSCap is not equivalent to a planar structure and additional considerations to deal with the electrostatics (e.g. field crowding) of such a component must be considered when adding this to the model [9]. In addition to this, the real devices also include a fourth capacitance component which is caused by the field oxide depicted in Fig. 1 (b). Because of the low contribution to the overall capacitance ( <4 %) and insufficient variation of this parameter from design to design, this component is neglected in the investigation. Table 1 lists the different designs that are evaluated. Three different types of designs are used. Planar designs where no trench is etched, recess designs where one large continuous trench is etched, and trench designs were several trench stripes
with the same trench width and spacing (mesa width) are etched. The analytical calculation of the corresponding areas for the designs is described in literature [4,7]. For this calculation, the device areas are taken from the mask layout as drawn, the trench width is confirmed by focused-ion-beam (FIB) cross-section SEM measurements (Fig. 1 (c)), and wafer-level trench depth is measured by structured illumination microscopy (Fig. 1 (d)) which is verified by focused-ion-beam cross-section SEM measurements (Fig. 1 (c)). The area calculation is corrected by the top and bottom corner rounding measured by FIB-SEM. As described earlier, there is some measurement error for the wafer level measurements. For the following investigations, the trench depth measured by FIB-SEM on a device in the wafer center is used and it is assumed that the trench depth does not change from device to device as they are close together on the wafer. For future wafer level measurements, the accuracy of the optical trench depth measurement must be improved and a method to accurately determine the trench depth of each device such as optical critical dimension scatterometry should be considered to increase the accuracy of the method.

Table 1. Sizing of fabricated devices.

Design | Type | Area [mm²] | Trench width [μm] | Mesa width [μm] | Effective area [10³ μm²]
|  |  |  |  | Sidewall | Mesa | Bottom
1 | Planar | 1 | 0 | 1000 | 0 | 100 | 0
2 | Recess | 1 | 996 | 2 | 0.36 | 0.72 | 99.12
3 | Trench | 1 | 1 | 1 | 133.83 | 20.71 | 19.81
4 | Trench | 1 | 1 | 2 | 79.24 | 49.39 | 15.39
5 | Planar | 0.5 | 0 | 707 | 0 | 50 | 0
6 | Recess | 0.5 | 703 | 2 | 0.25 | 0.51 | 49.38
7 | Trench | 0.5 | 1 | 1 | 66.47 | 10.62 | 9.84
8 | Trench | 0.5 | 1 | 2 | 39.34 | 24.88 | 7.64
9 | Planar | 0.316 | 0 | 562 | 0 | 31.6 | 0
10 | Recess | 0.316 | 558 | 2 | 0.20 | 0.40 | 31.11
11 | Trench | 0.316 | 1 | 1 | 42.04 | 6.72 | 6.20
12 | Trench | 0.316 | 1 | 2 | 24.91 | 15.72 | 4.81

With the effective areas shown in Table 1 and equation 1 an overdetermined system of linear equations is formed which is then solved pointwise for every applied voltage. At least three different trench MOSCap designs with different area ratios are needed to solve the system of linear equations. Because of process variation, it is beneficial to increase the accuracy of the estimation by forming an overdetermined system of equations which is then solved by fitting a least-squares solution to the linear matrix equation. This yields an effective per-area capacitance for the trench mesa, trench sidewall, and trench, as bottom depicted in Fig. 4 for both, sample 1 and sample 2.

[picture]

Fig. 4. Capacitance per area over voltage for trench mesa, bottom and sidewall calculated by linear component separation for the two different gate oxides.

Fig. 4. Capacitance per area over voltage for trench mesa, bottom and sidewall calculated by linear component separation for the two different gate oxides.

For sample 1, the area-related oxide capacitance of the trench sidewall is larger than both the mesa and bottom capacitances. This suggests that the oxide thickness of the trench sidewall is lower than the oxide thickness of both the mesa and the bottom. As can be seen in Fig. 1 (e) this clearly is not the case. Sample 2 shows a similar effect even though here the oxide thickness of the sidewall is significantly larger than at the mesa and bottom. Some of this behavior can likely be attributed to the combination of trench sidewall and corner rounding to one capacitance. Previously, we suggested that the different slopes in the C-V curves are caused by the different oxide thicknesses. In the simple component separation, however, all curves show these different slopes. The curve for the mesa should not show this effect as no thickness variation caused by the trench geometries occurs. This leads to the conclusion that the three different components are not sufficiently separated. To verify the accuracy of the method the theoretical C-V curves for different designs are calculated using Eq. 1 (Fig. 5 (a) dashed lines) by multiplying the corresponding areas for sidewall, mesa and bottom listed in Table 1 with the calculated effective per area capacitance depicted in Fig. 4. When comparing them to the actual measurements (Fig. 5 (a) solid lines), good alignment can only be seen for the fully trench recessed devices (designs 2, 6 and 10). Fig. 5 (b) shows the relative error between the measurements and modelled capacitance of all 12 designs. It can be observed that the different design types (planar, recess, 1μ m trench /1μ m mesa and 1μ m trench /2μ m mesa) show characteristic error curves.

[picture]

Fig. 5. a) Measured capacitance-voltage characteristics at 100 kHz (solid lines) for all 12 designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide), compared with the corresponding curves reconstructed from the linearly separated mesa, sidewall, and bottom capacitances (dashed lines, using Eq. (1) and the areas in Table 1). b) Relative error between reconstructed and measured capacitances as a function of gate voltage for all designs, illustrating the systematic, design-dependent deviation of the simple parallel-capacitor model.

Fig. 5. a) Measured capacitance-voltage characteristics at 100 kHz (solid lines) for all 12 designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide), compared with the corresponding curves reconstructed from the linearly separated mesa, sidewall, and bottom capacitances (dashed lines, using Eq. (1) and the areas in Table 1). b) Relative error between reconstructed and measured capacitances as a function of gate voltage for all designs, illustrating the systematic, design-dependent deviation of the simple parallel-capacitor model.

The largest error is observed for the devices with 1μ m trench and 2μ m mesa widths at -7.2 V where the curve calculated via linear component separation underestimates the actual capacitance of the devices by up to 20%. Close to the voltage the error curves of the designs with 1μ m trench width and 1μ m mesa width show a minimum. This leads to the conclusion that there is another effect which the linear component separation assigns to the trench sidewall but is caused by the difference in mesa width. This effect is the previously described extension of the space charge region into the trench sidewalls. Because this effect does not only depend on the area of the different capacitance components but on the spacing of the trenches the simple linear combination of parallel capacitors cannot model this behavior and therefore ascribes the corresponding capacitance to the trench sidewall. A more refined compact model could represent the lateral extension of the depletion region between neighboring trenches by an additional series capacitance that depends on trench pitch and doping, while keeping the oxide-related contributions as parallel capacitors. Corner and field-oxide effects could likewise be represented by separate capacitance elements. However, introducing these additional components would substantially increase the number of unknown parameters. A calibrated TCAD simulations model might allow for a robust extraction of the depletion capacitance. In addition to this the influence of the corner rounding could also be more accurately be described through TCAD simulations.

Density of interface states.

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For the evaluation of the density of interface states manual high and low frequency measurements (quasistatic and 1 MHz ) and manual measurements at 100 kHz for the Terman Dit  determination method equivalent to the full wafer C-V measurements on four devices per wafer were done. Fig. 6 (a) shows the density of interface states for design 1 (planar) and design 3 ( 1μ m trench/ 1μ m mesa) on sample 1. The measured values are in good agreement with previously reported results for planar MOSCaps using LPCVD TEOS oxides annealed in NO [3]. The differences between the high-low method and the Terman method are well reported [9]. However, because of measurement time and setup requirements of the low frequency measurement for the high-low method, it is not suitable for wafer level measurements. When applying the high low-method to the trench devices and assuming a constant surface potential and no variation of the oxide thickness the difference between the planar structures and the trench devices is not too large [10]. The Terman method shows an increased deviation between the trench and planar designs.

[picture]

Fig. 6. a) Average interface state density determined by the high-low and Terman methods for four devices per design for planar and trench MOSCaps on sample 1. b) Calculated effective Dit  for the trench sidewall, mesa and bottom with the Terman method.

Fig. 6. a) Average interface state density determined by the high-low and Terman methods for four devices per design for planar and trench MOSCaps on sample 1. b) Calculated effective D it for the trench sidewall, mesa and bottom with the Terman method.

An effective Dit  for the three calculated capacitance components for design 3 is evaluated for sample 1 and sample 2. Overall, these values are not quantitatively accurate as many influences that were previously described are not included in this model. The extracted quantities should therefore be regarded as effective Dit  values, which also contain these parasitic effects. The behavior of the mesa top and trench bottom follows the Terman evaluation for the planar devices, while the trench sidewall follows the trenched devices. Sample 1 shows a lower effective Dit  for the trench sidewall leading to the conclusion that between the two compared oxide processes the LPCVD TEOS oxide is better suited for fabricating UMOSFETs. However, because of the different SiO2 thickness distributions and the model errors of up to 20%, this apparent difference cannot be interpreted as a rigorous quantitative statement about the physical Dit  at the trench sidewall.

Summary and Outlook

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In this work, we demonstrate a linear component separation approach to extract effective sidewall capacitances from 4H-SiC UMOSCaps fabricated with LPCVD TEOS and polysilicon oxidation. While planar MOSCaps exhibit good breakdown performance trench devices show reduced breakdown strength attributed to non-uniform oxide thickness and corner field crowding.

It was possible to separate the capacitance-voltage measurement with the proposed linear component separation. However, significant systematic deviations between measured and reconstructed capacitances indicate that the simple parallel capacitor model inadequately captures the complex electrostatic behavior of trench structures. The observed errors correlate with design geometry, suggesting that mesa spacing-dependent depletion, field oxide contributions, and trench corner effects cannot be neglected. Future improvements should incorporate physics-based models for lateral depletion behavior and an expansion from point wise solving the linear matrix equation to form a linear system of functions and solving for these functions. Integration with TCAD simulations could provide deeper insights into the underlying physics and enable development of more accurate analytical models.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.29.pdf

T. Keita et al., Formation of high-quality SiC(0001)/SiO2 structures by excluding oxidation process with H2 etching before SiO2 deposition and high-temperature N2 annealing, Appl. Phys. Express. 13 (2020) 121002.

T. Kobayashi et al., Design and formation of interfaces via Si deposition followed by low temperature oxidation and high-temperature nitridation, Appl. Phys. Express 13 (2020) 091003.

M. Lim et al., Pre-Deposition Interfacial Oxidation and Post-Deposition Interface Nitridation of LPCVD TEOS Used as Gate Dielectric on 4H-SiC, MSF. 1004 (2020) 535-40.

M. Lim, Modeling and Verification of Trench MOS Integration using Trench-FirstTechnology, Ph.D. dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2023.

O. Rusch et al., Increasing 4H-SiC Trench Depth by Improving the Dry Etch Selectivity towards the Oxide Hard Mask, SSP 359 (2024) 193-200.

C. Hellinger et al., Low-Ohmic Nickel Contacts on N-Type 4H-SiC by Surface Roughness Dependent Laser Annealing Energy Density Optimization, SSP 359 (2024) 113-118.

C. Banzhaf, Entwicklung und Charakterisierung von Trench-Gate-Strukturen für 4H-SiC Leistungs-MOSFETs, Shaker Verlag, Aachen, 2016.

Z. Guo et al., Extraction of the Trench Sidewall Capacitances in an n-Type 4H-SiC Trench Metal- Oxide-Semiconductor Structure, IEEE Trans. Electron Devices vol. 68, no. 6 (2021) 2879-2885.

N. Yoshida et al., Extraction of interface state density at interfaces based on impedance measurements with different temperatures, Thin Solid Films 557 (2014) 237-240.

C. Banzhaf et. al., Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures. MSF, 740-742. (2013) 691-694.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 39-45

doi: 10.4028/p-Am6ufR

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-14

Revised:
2025-12-24

Accepted:
2026-02-26

Online:
2026-05-20

Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

Masao Sakuraba 1,2,a*, Tatsunori Oki 2,5,b, Satoshi Watanabe 1,6,c, Shigeo Sato 1,2, d, Iori Morita 1,e, Tetsuya Ueno 2,f, Seima Sato 2, g, Hiroyuki Nagasawa 3, h, Yukimune Watanabe 4,i and Maki Suemitsu 3,j

1 Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, Japan

2 Graduate School of Engineering, Tohoku University, 6-6 Aramaki Aza Aoba, Aoba-ku, Sendai 980-8579, Japan

3 CUSIC Inc., 2-2-10 Chuo, Aoba, Sendai, Miyagi, 980-0021, Japan

4 SiCure, 3−4−10 Meieki, Nakamura-ku, Nagoya, 450-0002, Japan

5 Tokyo Electron Miyagi Ltd., 1-1 Techno-Hills, Taiwa-cho, Kurokawa-gun, Miyagi 981-3629, Japan

6 CIES, Tohoku Univ., 468-1 Aramaki Aza Aoba, Aoba-ku, Sendai 980-8572, Japan

a*  sakuraba.masao@myad.jp, b  tatunori32@gmail.com, c  satoshi.watanabe.e2@tohoku.ac.jp,

d shigeo@tohoku.ac.jp, e iori.morita.c6@tohoku.ac.jp, f ueno.tetsuya.t2@dc.tohoku.ac.jp,

s  sato.seima.q2@dc.tohoku.ac.jp, h  nags@cusic.co.jp, 'y.watanabe@sicure.jp, j  suemitsu@cusic.co.jp

Abstract

C}-\mathrm{SiC}) with a moderate band gap and a large electron affinity is expected to have superior long-term stability against performance degradation. We have fabricated Al-gate MOS diodes in 3C-on- 4H−SiC and 4H−SiC regions on a simultaneous lateral epitaxy (SLE) wafer. Here, evaluation results of their high-frequency differential capacitance-voltage (C-V) characteristics are reported and, from suggested band diagrams, carrier transport involved in the phenomena are considered. In the case of n−-type 3C-on-4H-SiC MOS diode, increase in capacitance due to fast modulation in the inversion layer charge (hole) concentration can be confirmed in the negative bias below -5 V. 2dimensional hole gas ( 2 DHG ) is considered at the Si -face 3C/4H heterointerface negatively charged by spontaneous polarization and is expected to be an effective supply source of holes. Especially in the case of p-type 3C-on-4H-SiC MOS diode, it is considered that injection of holes from neutral p type region into the heterointerface induces compensation of the fixed charges and lowering of the electron barrier at conduction band, and then, electron injection through the barrier causes the fast response of inversion-layer modulation. Appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as "a deep acceptor level" and "2DHG confined by fixed charges". These findings are believed to contribute to building new production platforms of high-performance power semiconductor devices utilizing the polytype heterostructure of SiC .

Keywords: 3C−SiC,4H−SiC, polytype heterostructure, heterointerface, spontaneous polarization, 2 dimensional hole gas (2DHG), metal-oxide-semiconductor (MOS) capacitor, carrier transport.

Introduction

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Metal-oxide-semiconductor (MOS) transistors using 3C-SiC, which have moderate band gap ( 2.4 eV ) and large electron affinity compared to that of 4H−SiC, are expected to have superior long-term stability against performance degradation due to leakage current in the gate insulator in addition to high blocking voltage, low interface trap density and higher n-channel mobility than 300 cm2/(V−s)

[picture]

Fig. 1. Optical micrographs of (a) n−-type and (b) p-type Al-gate MOS diodes using the SLE wafer, (c) schematic cross-sections for a stripe between periodically arranged trenches. SLE trench interval, widths for 3C-SiC stripe, 4H-SiC stripe and length of Al gate square are 150μ m,70μ m, 80μ m and 50μ m, respectively.

Fig. 1. Optical micrographs of (a) n − -type and (b) p -type Al-gate MOS diodes using the SLE wafer, (c) schematic cross-sections for a stripe between periodically arranged trenches. SLE trench interval, widths for 3C-SiC stripe, 4H-SiC stripe and length of Al gate square are 150 μ m , 70 μ m , 80 μ m and 50 μ m , respectively.

at 25∘C [1-3]. Recently, a simultaneous lateral epitaxy (SLE) method has been developed in which 3C−SiC and 4H−SiC are simultaneously epitaxially grown along the basal plane and produced 3 C -on4H polytype heterostructure SiC wafers (SLE wafers) [4-6]. In this presentation, we will report on the fabrication of Al-gate MOS diodes in 3 C -on- 4H−SiC and 4H−SiC regions on a single SLE wafer (Fig. 1) and the evaluation results of their high-frequency differential capacitance-voltage (C-V) characteristics.

Experimental

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One piece cut out from a SLE wafer produced from Si -face 4H−SiC(0001) wafer with off angle of 4∘ along [11 2―0 ] (Fig. 1) was used as an n-type SLE wafer (carrier concentration of about 1016 cm−3 ),  and the other was used as an SLE wafer with a pn junction after high-temperature ion implantation ( 500∘C,Al ions) and heat treatment ( 1700∘C,5 min, Ar atmosphere) to make a 500 nm -thick surface p-type layer (carrier concentration of about 2×1017 cm−3 ). Here, a 24−30 nm-thick thermal oxide ( SiO2 ) film was formed by H2−O2 pyrogenic wet oxidation (1050∘C,4 h). Subsequently, about 100 nm -thick Al film was deposited on the surface, and resist patterns were formed on each area of 3C−SiC and 4H−SiC by photolithography using direct laser drawing exposure method, and Al gate electrodes were formed by wet etching. Finally, about 100 nm -thick Al film was deposited on the back surface and H2 sintering was performed at 400∘C ( 95% N2+5%H2, atmospheric pressure). C−V characteristics of the MOS diodes were measured at room temperature and 50−400kHz for the small amplitude signal superimposed on the gate voltage sweep.

Results and Discussion

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The evaluation results of their C-V characteristics are shown in Fig. 2 and, from suggested band diagrams shown in Figs. 3-6, carrier transport involved in the phenomena are considered. Here, following the advanced research on 3C/4H−SiC polytype heterostructure with spontaneous polarization [7-11], discontinuity at conduction band and negative fixed charges at the 3C/4H heterointerface have been included in the band diagrams. In Figs. 4-6, we are assuming situations in which a depletion layer exists inside far away from the MOS interface in relation to heterointerface and/or the pn junction, and stretching/shrinking of the width of the depletion layer are causing charging/discharging of the depletion layer capacitance ( CD ). Therefore, we added CD in the inset pictures of equivalent circuit.

n−-type 4H-SiC Region.

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In the case of n−-type 4 H -SiC MOS diode (Fig. 2 (a)), the C -V curve indicates that free electrons accumulate at the SiO2/4H−SiC interface in the positive bias (Fig. 3 (b)),

[picture]

Fig. 2. C-V characteristics of the MOS diodes at room temperature and 50−400kHz for the small amplitude signal superimposed on the gate voltage.

Fig. 2. C-V characteristics of the MOS diodes at room temperature and 50 − 400 k H z for the small amplitude signal superimposed on the gate voltage.

while the capacitance decreases monotonically in the negative bias, suggesting the expansion of the depletion layer (Fig. 3 (a)). Here, the depletion is observed near 0 volts, and the flat band voltage is estimated to be about +3 V .

n−-type 3C-on-4H-SiC Region.

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In the case of n−-type 3C-on-4H-SiC MOS diode (Fig. 2 (b)), free electrons accumulate at the SiO2/3C−SiC interface at around 0 V and in the positive bias, while increase in the capacitance due to fast change in the inversion layer charge (hole) concentration can be confirmed in the negative bias below -5 V . The latter indicates a fast response of minority carrier (hole) concentration at the SiO2/3C−SiC interface, although 3C−SiC has a sufficiently wide band gap to suppress carrier generation at room temperature. It has been reported that 2 -dimensional hole gas ( 2 DHG ) is formed at the Si -face 3C/4H heterointerface negatively charged by a spontaneous polarization [7-8] (Fig. 4). Therefore, it is considered that 2DHG can act as an effective supply source of holes. In contrast, on the C -face 3C/4H-SiC heterointerface, formation of a 2 -dimensional electron gas (2DEG) with channel mobility as high as 780 cm2/(V−s) has been observed [9-11].

p-type4H𝐇-SiC Region.

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In the case of p-type 4H-SiC MOS diode (Fig. 2 (c)), holes are considered to accumulate at the SiO2/4H−SiC interface in the negative bias (Fig. 5 (a)), while a monotonic decrease in the capacitance can be confirmed in the positive bias, suggesting the expansion of the depletion layer (Fig. 5 (b)). In
addition, since no increase in capacitance is observed in the positive bias, it is believed that conversion from n−-type to p-type by Al ion implantation is successful, and a high-quality pn junction ( pn isolation structure) is formed.

p-type 3C-SiC Region.

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In the case of p-type 3C-SiC MOS diode (Fig. 2 (d)), a drastic increase in the capacitance in the positive bias is clearly observed, indicating not only fast response of the minority carrier (free electron) concentration at the SiO2/3C−SiC interface but also the drastic change of band alignment. From the suggested band diagram shown in Fig. 6 (b), it is considered that (1) holes are injected from the p-type 3C-SiC, (2) the injected holes neutralize the fixed negative charges at the Si-face 3C/4H heterointerface [7-8] and causes (3) barrier lowering to enhance free electron transport from the n−type 4H−SiC (similarly to "parasitic bipolar effect"). When we assume that most of holes in the ptype 3C-SiC layer are injected into the 2DHG, the sheet density is estimated as high as about 1×1013cm−2 from the implanted p-type dopant dose. Additionally, reported sheet hole density of 2DHG induced by spontaneous polarization ( 9.7×1012 cm−2[7] ) is almost the same order. Therefore, neutralization by compensation can be considered to occur effectively at the heterointerface. Here, it can be suggested that a structure of n−-type 4H−SiC/2DHG/n−-type 3C−SiC acts as an npn heterojunction bipolar transistor with high current gain due to a wider-gap emitter and a narrower-

[picture]

Fig. 3. Suggested band diagram of the MOS diode on n−-type 4H−SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 3. Suggested band diagram of the MOS diode on n − -type 4 H − S i C region of SLE wafer under (a) negative and (b) positive bias.

[picture]

Fig. 4. Suggested band diagram of the MOS diode on n−-type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 4. Suggested band diagram of the MOS diode on n − -type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

gap base, in which holes are supplied from p-type 3C-SiC through the depleted n−-type 3C-SiC to 2DHG. On the other hand, in a negative bias of -5 V or less, holes accumulate at the SiO2/3C−SiC interface as shown in Fig. 6 (a), and the flat band voltage is estimated to be about -7 V . It is considered that the conversion from n−-type to p-type by ion implantation is successful in 3C−SiC as well as 4 H SiC . For example, the holes in 2DHG below the gate electrode are considered to move away out of the electrode area ( 50μ m2 ) due to horizontal electric field caused by applying positive gate voltage. Based on such phenomenology, the holes in 2DHG should move because the band bending changes. Here, we assume that "slow modulation of 2DHG" (shown in Figs. 4 and 6) includes two phenomena such as "wide-range horizontal movement of holes during entering/exiting the electrode area along the 2DHG" and "capture/release in the deeply-confined state at the 2DHG". Because the phenomena seemed to be not so quick due to wide range and deepness, it is considered that the modulation might be slow and induce the frequency dependence.

[picture]

Fig. 5. Suggested band diagram of the MOS diode on p-type 4H−SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 5. Suggested band diagram of the MOS diode on p -type 4 H − S i C region of SLE wafer under (a) negative and (b) positive bias.

[picture]

Fig. 6. Suggested band diagram of the MOS diode on p-type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 6. Suggested band diagram of the MOS diode on p -type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

Frequency Dependence of Capacitance

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

From overview of all the C-V curves, frequency dependence of capacitance is found especially in Fig. 2 (b-d). As such frequence dependence can be seen generally in trap and release process of carrier at specific state, it can be imagined that the larger activation energy results in the slower response. In our case, acceptor level of Al atom doped in 4H−SiC and 3C−SiC is reported to have relatively large
activation energy such as 0.25−0.26eV [12-13], while donor level of N atom doped in 4H−SiC and 3C-SiC has as low activation energy as 0.0653 eV and 0.124 eV in 4H−SiC and 0.018−0.047eV in 3C-SiC [14-15]. Therefore, appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as "a deep acceptor level" and "2DHG confined by fixed charges". Here, during modulation of depletion layer thickness by small-amplitude signal at high frequency for capacitance measurement, holes in the trap and release process at deep acceptor level especially at edge of the depletion layer will contribute to frequency dependence. Additionally, because similar relation can be also imagined between holes and the negative fixed charges at Si-face 3C/4H heterointerface, "2DHG confined by fixed charges" will also contribute to frequency dependence in supplying/receiving holes (Figs. 4 and 6). In another typical case of n−-type 4H-SiC region (Fig. 2. (a)), due to shallow donor level without heterointerface, frequency dependence is considered to become small. Thus, it is suggested that frequency dispersion of capacitance is large in Fig. 2 (b-d) and significant especially at negative bias in Fig. 2 (d) with coexisting effect of the Al doped region and 3C/4H heterointerface. For the detailed contribution of each process, further research is needed. Additionally, it should also be noted that frequency dependence in both the accumulation and inversion capacitance of C−V characteristics can be observed if the series resistance is high [16]. Therefore, concerning the actual effect of series resistance as well as contribution of interface traps at the SiO2/SiC, further investigations are necessary.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

By fabrication of Al -gate MOS diodes in 3 C -on- 4H−SiC and 4H−SiC regions on an SLE wafer, evaluation results of their high-frequency C-V characteristics are reported and, from suggested band diagrams, carrier transport involved in the phenomena are considered. In the case of n−-type 3C-on-4H-SiC MOS diode, increase in capacitance due to fast modulation in the inversion layer charge (hole) concentration can be confirmed in the negative bias below -5 V. 2-dimensional hole gas ( 2 DHG ) is considered at the Si -face 3C/4H heterointerface negatively charged by spontaneous polarization and is expected to be an effective supply source of holes. Especially in the case of p-type 3C-on-4H-SiC MOS diode, it is considered that injection of holes from neutral p-type region into the heterointerface induces compensation of the fixed charges and lowering of the electron barrier at conduction band, and then, electron injection through the barrier causes the fast response of inversionlayer modulation. Appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as "a deep acceptor level" and "2DHG confined by fixed charges". These phenomena can be useful sometimes, but they can also be a hindrance if they are used improperly. Strategy of elimination or utilization for such phenomena will be important for breakthroughs in the novel semiconductor device development. These findings are believed to contribute to building new production platforms of high-performance power semiconductor devices utilizing the polytype heterostructure of SiC.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

This work was partly supported by Grant-in-Aid for Scientific Research(C) (No. 24K08267) from the JSPS in Japan and the Cooperative Research Project Program of the Research Institute of Electrical Communication, Tohoku University.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

M. Bakowski, A. Schöner, P. Ericsson, H. Strömberg, H. Nagasawa, M. Abe, Development of 3C-SiC MOSFETs, J. Telecomm. Information Technol. 2 (2007) 49-56.

F. Ciobanu, G. Pensl, H. Nagasawa, A. Schöner, S. Dimitrijev, K.-Y. Cheong, V.V. Afanas'ev, G. Wagner, Traps at the Interface of Structures, Materials Science Forum 433-436 (2003) 551-554.

H. Uchida, A. Minami, T. Sakata, H. Nagasawa, M. Kobayashi, High Temperature Performance of 3C-SiC MOSFETs with High Channel Mobility, Materials Science Forum 717-720 (2012) 1109-1112.

H. Nagasawa, Japanese Patent, JPB6795805B (May 15, 2020): Chinese Patent, ZL 20218 0032148.1 (April 27, 2021).

H. Nagasawa, Y. Cho, M. Abe, T. Tanno, M. Musya, M. Sakuraba, Y. Sato, S. Sato, SNDM Study of the MOS Interface State Densities on the Stacked Structure, Solid State Phenomena 362 (2024) 33-40.

H. Nagasawa, M. Abe, T. Tanno, M. Musya, M. Sakuraba, S. Sato, Y. Watanabe, M. Suemitsu, Formation of Alternating Epilayers of and by Simultaneous Lateral Epitaxy, Materials Science Forum 1157 (2024) 33-41.

M.V.S. Chandrashekhar, C.I. Thomas, J. Lu, M.G. Spencer, Electronic properties of a SiC polytype heterojunction formed on the Si face, Appl. Phys. Lett. 90 (2007) 173509 (3 pages).

H. Sazawa, A. Nakajima, S. Kuboya, H. Umezawa, T. Kato, Y. Tanaka, P-Channel HFET Utilizing 2D Hole Gas in Si-Face 3C/4H-SiC Heterostructure, IEEE Electron Device Lett. 45 (2024) 1562-1565.

V.M. Polyakova, F. Schwierz, Formation of two-dimensional electron gases in polytypic SiC Heterostructures, J. Appl. Phys. 98 (2005) 023709 (6 page).

M.V.S. Chandrashekhar, C.I. Thomas, J. Lu, and M.G. Spencer, Observation of a two dimensional electron gas formed in a polarization doped C -face heteropolytype junction, Appl. Phys. Lett. 91 (2007) 033503 (3 page).

H. Sazawa, H. Yamaguchi, High-mobility 2D electron gas in carbon-face 3C-SiC/4H-SiC heterostructure with single-domain 3C-SiC layer, Appl. Phys. Lett. 120 (2022) 212102 (4 page).

A. Koizumi, J. Suda, T. Kimoto, Temperature and doping dependencies of electrical properties in Al-doped 4H-SiC epitaxial layers, J. Appl. Phys. 106 (2009) 013716.

T. Sugiura, N. Takahashi, R. Sakota, K. Matsuda, N Nakano, Piezoresistive Thermal Characteristics of Aluminum-Doped P-Type 3C-Silicon Carbides, J. Electron Devices Soc., 10 (2022) 547-553.

H. Matsuura, T. Kimoto, H. Matsunami, Nitrogen Donor Concentrations and Its Energy Levels in Uniquely Determined by a New Graphical Method Based on Hall-Effect Measurement, Jpn. J. Appl. Phys. 38 (1999) 4013-4016.

F. Li, Y. Sharma, V. Shah, M. Jennings, A. Pérez-Tomás, M. Myronov, C. Fisher, D. Leadley, P. Mawby, Electrical activation of nitrogen heavily impla nted 3C-SiC(1 0 0), Appl. Surf. Sci. 353 (2015) 958-963.

R. Omar, B. A. Mohamed, M. Adel, Effects of series and parallel resistances on the C-V characteristics of silicon-based metal oxide semiconductor (MOS) devices, Eur. Phys. J. Plus 130 (2015) 80.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 47-52

doi: 10.4028/p-8XxBpT

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-16

Revised:
2025-12-16

Accepted:
2026-02-26

Online:
2026-05-20

Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

Koushik Ramadoss 1,a*, Joshua Holt 2, b, Lucien Date 3,c, Safdar Muhammad 4, d, Jesse Kalliomaki 4,e, Fernanda Albrechtvechietti 4,f, William Charles 5, g, Athena Pang 2,h, Shubhendra Jain 5,i, Benjamin Briggs 5,j, Ludovico Megalini 2,k, Michael Chudzik 2,I, Dallas Morisette 1, m and James Cooper 1,n

1 School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA

2 Applied Materials, 3325 Scott BIdv., Santa Clara, CA 95054, USA

3 Applied Materials, Kapeldreef 75, Leuven, BEL 3001, Belgium

4Applied Materials, Masalantie 365, 02430, Masala, Finland

5 Applied Materials, 1 Broadway, Cambridge, MA 02142, USA

a*kramado@purdue.edu, b Joshua_Holt@amat.com, c lucien_date@amat.com,

d  safdar_muhammad@amat.com, e  jesse_kalliomaki@amat.com,

f fernanda_albrechtvechietti@amat.com, g william_charles@amat.com, h Athena_Pang@amat.com,

iShubhendra_Jain@amat.com, jbenjamin_briggs@amat.com, kludovico_megalini@amat.com, 

I  michael_chudzik@amat.com, m  morisett@purdue.edu, ncooperj@purdue.edu 

Abstract

In this work, we demonstrate a novel oxidation-free gate oxide process consisting of a twostep surface preparation treatment, followed by atomic layer deposition of SiO2 and a post-deposition anneal in nitrogen. The surface treatment includes a 1300∘C anneal in hydrogen and dilute silane, followed by decoupled plasma nitridation (DPN). Long channel MOSFETs fabricated with this process show a 1.5 X improvement in peak field effect mobility compared with devices utilizing a standard thermal oxide and NO anneal. The MOSFETs had a positive threshold voltage, low gate leakage, and a breakdown field above 8MV/cm.

Keywords: atomic layer deposition, decoupled plasma nitridation, MOSFET, H2 etching.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

Silicon carbide (SiC) is a wide gap semiconductor that is being rapidly adopted in power electronic applications due to its high critical electric field, high thermal conductivity, the availability of highquality large area substrates, and maturing fabrication technology. However, SiC MOSFETs exhibit poor performance due to a high density of interface states, leading to low channel mobility ( <5% of bulk mobility). To mitigate this, various studies have been conducted using deposited gate oxide processes to avoid thermal decomposition of the substrate. These processes include atomic layer deposition (ALD) [1], plasma enhanced CVD [2] [3], and a process we call "poly-ox", wherein a thin film of Si is deposited by chemical vapor deposition (CVD), followed by oxidation of the Si film at a sufficiently low temperature to avoid oxidation of the underlying SiC [4] [5]. Alternatively, other nitridation techniques including nitrogen plasma [6] [7] [8], N2O [9] and high temperature nitrogen anneals [4] have been explored as an alternative to the NO anneal to maximize the nitrogen coverage and improve interface properties. But these methods have negative side-effects such as the incorporation of nitrogen throughout the bulk of the oxide [4], or lead to only marginal improvements in interface properties. In this study, we use an Applied Materials TM  Centura TM  DPN (decoupled plasma nitridation) process in conjunction with an Applied Materials TM  Picosun TM  P300B ALD tool to form an oxidation-free SiO2 gate oxide. Decoupled plasma nitridation is a remote plasma process, capable of directly nitriding the SiC surface within a few tens of seconds, and is therefore particularly suitable for high-volume manufacturing [10] [11] [12] [13] [14]. Optimization of the DPN parameters allows the introduction of a tunable concentration of nitrogen as high as ~1.5×1021/cm3 in a sharply
defined peak at the SiC/SiO2 interface, making the traditionally hours-long and expensive NO or N2O post-deposition nitridation process unnecessary. When combined with a hydrogen + dilute silane surface pretreatment process as described previously [5] [2] [15], MOSFETs formed by this process show a 1.5 X enhancement in peak channel mobility compared to standard MOSFETs prepared by thermal oxidation and NO annealing, as well as a positive threshold voltage, low gate leakage, and a breakdown field greater than 8MV/cm.

Device Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

Our oxidation-free gate dielectric process was demonstrated using long-channel MOSFET templates consisting of an n-type 4H−SiC substrate with a 9.0×1015 cm−3n-type epilayer and ion implanted p -body regions having a surface aluminum concentration of 1.6×1016 cm−3, confirmed by SIMS analysis. The source and drain regions consist of highly doped n+regions implanted with nitrogen. The DPN-based process flow used to form the gate oxide is shown in Fig. 1. Before forming the gate oxide, the substrates were first RCA cleaned and subjected to H2 etching in a hot walled CVD furnace (1300∘C,900mbar,10slmH2) for 6 min . During the final 3 minutes of this anneal, a 5%SiH4/H2 mixture was added at a flow rate of 100 sccm , for a silane concentration of 0.05%. This last silane step is critical to minimize and passivate interface defects [5] [2] [15]. Subsequently the samples were subjected to the DPN process with a remote plasma to incorporate nitrogen into the SiC surface, similar to that formed by a post-deposition anneal in NO. A 48 nm thin film of silicon dioxide was then deposited using an Applied Materials Picosun P300B ALD system, and densified by annealing in a N2 ambient at 1200∘C for 30 min . The final MOSFETs were formed with n-type polysilicon gates doped by 800∘C,60 s diffusion from a Filmtronics P509 spin-on phosphorus source, Ni source and drain ohmic contacts formed by rapid thermal annealing at 800∘C for 120 s , and Al top metal pads were deposited and patterned for electrical contacts. The gate poly was also encapsulated by a 300 nm thick PECVD SiO2 prior to the formation of ohmic contacts. The channel length and width are 140μ m and 110μ m respectively. In our experiments, a control sample was prepared by thermal oxidation of SiC in dry O2 followed by NO annealing at 1175∘C for 2 hrs . to give about 50 nm of SiO2 for comparison.

[picture]

Fig. 1. Process flow diagram for DPN based gate oxide process.

Fig. 1. Process flow diagram for DPN based gate oxide process.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

The transfer characteristics of a typical MOSFET fabricated in this manner are shown in Fig 2a.

[picture]

Fig. 2. Transfer characteristics (a) and field-effect mobility (b) as a function of gate voltage for MOSFETs formed by the DPN process in comparison with a standard thermal + NO process.

Fig. 2. Transfer characteristics (a) and field-effect mobility (b) as a function of gate voltage for MOSFETs formed by the DPN process in comparison with a standard thermal + NO process.

The device shows a sharper increase in drain current with a positive but somewhat reduced threshold voltage ( Vth ~1 V ) in comparison to the control sample with a 50 nm thick thermally grown gate oxide and NO anneal. The field effect mobility (Fig. 2b) of a DPN treated device shows a significant 1.5 X improvement ( ~38 cm2/Vs ) as compared to the control sample ( ~25 cm2/Vs ). This increased mobility, reduced threshold voltage, and a sharper turn-on characteristic are all consistent with a significant reduction in the interface state density. It is important to note that these measurements were done on an ion implanted channel with NA=1.6×1016 cm−3. While this p-type doping concentration may be insufficient for practical power devices, it still allows a direct comparison of parameters for the MOSFETs fabricated with the two different gate oxide methods.

[picture]

Fig. 3. a) Normalized CV characteristics of DPN treated circular MOSCAP device (diameter =225μm) compared with Thermal + NO control. b) Comparison of leakage current and oxide breakdown fields for DPN treated device and Thermal + NO control.

Fig. 3. a) Normalized CV characteristics of DPN treated circular MOSCAP device (diameter = 225 μ m ) compared with Thermal + NO control. b) Comparison of leakage current and oxide breakdown fields for DPN treated device and Thermal + NO control.

The high frequency CV characteristics (at 100 kHz in dark conditions) are shown for the DPN treated MOSCAPs (Fig 3a). The normalized CV data shows minimal hysteresis, and a -0.8 V shift in the CV curve compared to the control sample. This shift is consistent with that of a reduction in negative interface charges (interface + fixed charge) of q*3.45×1011C/cm2 and is also consistent with the higher mobility shown in Fig 2b. The DPN treated MOSCAPs also exhibit low leakage current and a high breakdown field ( >8MV/cm ) (Fig. 3b), although somewhat lower breakdown field than the thermal+NO control sample. While nearly ideal breakdown fields have been observed in ALD deposited SiO2 films [16], it is not uncommon for such films to have somewhat lower
breakdown fields than thermal oxides. Further optimization of our process is required to achieve an oxide breakdown field comparable to traditional thermal+NO oxides. Fig. 4 shows a transmission electron microscopy (TEM) cross-section image and electron energy loss spectroscopy (EELS) map across the interface. The image indicates that the N2 is preferentially incorporated at the interface during the DPN treatment with small distribution into the oxide bulk.

[picture]

Fig. 4. TEM micrograph of DPN treated device showing SiO2 thickness of 48 nm . The EELS map of various elements (Nitrogen, Silicon, Oxygen, Carbon) across the device cross section is also shown.

Fig. 4. TEM micrograph of DPN treated device showing S i O 2 thickness of 48 nm . The EELS map of various elements (Nitrogen, Silicon, Oxygen, Carbon) across the device cross section is also shown.

[picture]

Fig. 5. Depth profiles of nitrogen atom concentration near SiC−SiO2 interface and in the bulk SiO2. The peak concentration at the interface is slightly higher than Thermal + NO control.

Fig. 5. Depth profiles of nitrogen atom concentration near S i C − S i O 2 interface and in the bulk S i O 2 . The peak concentration at the interface is slightly higher than Thermal + NO control.

To quantify the concentration of N2 near the interface and in the bulk oxide, depth profiling was performed using SIMS as shown in Fig. 5. The results indicate high concentration of N2 near the interface for DPN treated samples with small amount of N2 present in the bulk of the oxide as well. Further experiments are required to optimize the conditions of DPN treatment and post ALD deposition anneal to further improve the device performance.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

In summary, we have demonstrated a gate oxide process that reduces the interface defect density to yield a 1.5 X improvement in peak channel mobility while maintaining a small positive threshold voltage. The effectiveness of the DPN process in nitriding the SiC surface in a very short time enables a high-throughput fabrication process and is therefore particularly suitable for high-volume manufacturing of SiC devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

The authors would like to thank the support from the Margot A. and Carl J. Johnson Foundation for financial support. This work was done in part at the Birck Nanotechnology Center, Purdue University. We also acknowledge the assistance from Clas-SiC Wafer Fab.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

R. P. Ramamurthy, D. T. Morisette, V. Amarasinghe and L. C. Feldman, "Thermal-oxidationfree dielectrics for SiC power devices," in 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2017.

K. Tachiki, M. Kaneko and a. T. Kimoto, "Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of H 2 etching, SiO 2 deposition, and interface nitridation," Applied Physics Express, vol. 14, p. 031001, 2021.

M. Yakut, A. Roy, F. Arith, A. Whitworth, A. Alexander, J. Gryglewicz, J. Sheriff, S. Olsen, K. Vasilevskiy and a. A. O'Neill, "Increasing Mobility in 4H-SiC MOSFETs with Deposited Oxide by In-Situ Nitridation of SiC Surface," Solid State Phenomena, vol. 359, pp. 157-162, 2024.

T. Kobayashi, T. Okuda, K. Tachiki, K. Ito, Y.-i. Matsushita and a. T. Kimoto, "Design and formation of SiC (0001)/SiO2 interfaces via Si deposition followed by low-temperature oxidation and high-temperature nitridation," Applied Physics Express, vol. 13, p. 091003, 2020.

K. Ramadoss, A. Samal, D. T. Morisette and a. J. A. Cooper, "High Mobility SiC MOSFETs Using an Oxidation-Minimizing Process," in Poster presented at 21st International Conference on Silicon Carbide and Related Materials, 2024.

X. Zhu, A. C. Ahyi, M. Li, Z. Chen, J. Rozen, L. C. Feldman and a. J. R. Williams, "The effect of nitrogen plasma anneals on interface trap density and channel mobility for MOS devices," Solid-State Electronics, vol. 57, no. 1, pp. 76-79, 2011.

Modic, Y. Sharma, Y. Xu, G. Liu, A. Ahyi, J. Williams, L. Feldman and a. S. Dhar, "Nitrogen Plasma Processing of SiO2/4H-SiC Interfaces," Journal of Electronic Materials, vol. 43, p. 857-862, 2014.

D.-K. Kim, Y.-S. Kang, K.-S. Jeong, H.-K. Kang, S. W. Cho, K.-B. Chung, H. Kim and a. M.H. Cho, "Effects of spontaneous nitrogen incorporation by a surface caused by plasma nitridation," Journal of Materials Chemistry C, vol. 3, pp. 5078-5088, 2015.

T. Kimoto, H. Kawano, M. Noborio, J. Suda and a. H. Matsunami, "Improved Dielectric and Interface Properties of MOS Structures Processed by Oxide Deposition and N 2 O Annealing," Materials Science Forum, Vols. 527-529, pp. 987-990, 2006.

H. N. Al-Shareef, A. Karamcheti, T. Y. Luo, G. Bersuker, G. A. Brown, R. W. Murto, M. D. Jackson, H. R. Huff, P. Kraus, D. Lopes, C. Olsen and G. Miner, "Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation," Applied Physics Letters, vol. 78, pp. 3875-3877, 2001.

Materials, "TSMC Qualifies Applied Materials' Gate Stack System for Its Leading-Edge 65nm Transistor Processes," Applied Materials, Inc, 5 May 2005. [Online]. Available: .

S. W. Lim, T.-Y. Luo and a. J. Jiang, "Mechanism of Silicon Dioxide Decoupled Plasma Nitridation," Japanese Journal of Applied Physics, vol. 45, p. L413, 2006.

M. Tian, K. Chen, C. Wang, T. Guan, Q. Sun and a. D. W. Zhang, "Decoupled Plasma Nitridation (DPN) and Postnitridation Annealing (PNA) Treatment for Metal Boundary Effect Reduction," IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 2233-2237, 2024.

P. Fiorenza, G. Lorito, L. Vigo, L. Date, J. Holt, M. Vivona, G. Cautiero, A. Cockburn, L. Megalini, M. Chudzik and a. F. Roccaforte, "Decoupled Plasma Nitridation of SiC surface for Interface States Density reduction in MOS Capacitors," in Poster presented at 22nd International Conference on Silicon Carbide and Related Materials, 2025.

T. Kimoto, T. Kobayashi and a. K. Tachiki, "SiC semiconductor device manufacturing method and SiC semiconductor device". United States Patent Application No. 2023/0307503 A1, 28 Sep 2023.

X. Yang, B. Lee and V. Misra, "Electrical Characteristics of SiO2 Deposited by Atomic Layer Deposition on 4H-SiC After Nitrous Oxide Anneal," IEEE Transactions on Electron Devices, vol. 63, p. 2826, 2016.

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The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 53-57

doi: 10.4028/p-2GRnYr

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-01-31

Online:
2026-05-20

Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

Heng Wang 1,a, Yangming Du 1, b, Ji Shu 1,c, Pengwei Zhou 1, d, Yingchen Yang 1,e and Kevin. J. Chen 1,f*

1 The Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, China

a  hwangfz@connect.ust.hk, b  eeyangmingdu@ust.hk, c  eejayshu@ust.hk, d  pzhouan@connect.ust.hk, e  yyangfx @connect.ust.hk, f  eekjchen@ust.hk

Abstract

In this work, we present a process flow to optimize the SiC/SiO2 gate interface quality for SiC power MOSFETs. The process incorporates high-temperature N2/H2 pretreatment, followed by LPCVD SiO2 deposition and NO post-deposition annealing (PDA). By tailoring the pretreatment conditions, a substantially improved SiC/SiO2 interface with reduced interface trap density ( Dit  ) can be achieved. Furthermore, the gate oxide quality is also characterized by measuring the leakage current and time-dependent dielectric breakdown (TDDB). The results indicate a noticeable improvement in the average breakdown field ( Eox ), thanks to the enhanced SiC surface condition achieved by the N2/H2 pretreatment.

Keywords: 4H−SiC MOS capacitor, SiC/SiO2 interface, high temperature pretreatment, interface trap density, gate leakage current.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

Despite the on-going commercialization, the 4H−SiC power MOSFET still suffers from the traprich SiC/SiO2 MOS gate interface, which affects the field-effect MOS channel mobility, threshold voltage stability, and device lifetime. Attempts to improve the SiC/SiO2 MOS gate interface should continue for improved device performance and reliability. Carbon-related defects (i.e., the carbon clusters) generated during the thermal oxidation process of SiC are identified as a predominant contributor to the high Dit  level [1].

Preventing the thermal oxidation of SiC surface during which the high oxidation temperature (~1,200∘C) could lead to carbon accumulation at the interface, e.g., replacing thermal oxide with deposited oxide (at lower temperature), has been experimented to eliminate the carbon-related defects, thereby improving the quality of SiC/SiO2 interface [2-3]. Nevertheless, carbon-related defects can still form during sacrificial oxidation process. Therefore, an appropriate pretreatment prior to the gate oxide deposition is needed to remove the existing carbon-related defects, thereby obtaining a highquality SiC surface for the subsequent gate oxide deposition process.

In this work, we present a process flow that integrates high temperature N2/H2 pretreatment, LPCVD SiO2 deposition, and NO post deposition annealing (PDA) to optimize the quality of SiC/SiO2 interface. The hydrogen-containing pretreatment enables effective removal of the carbonrelated defects through a layer-by-layer etching process of the defective layers at the SiC surface, preparing a high-quality SiC surface [4]. The LPCVD deposition at 420∘C effectively avoids the thermal oxidation of SiC and the associated carbon clusters, and the subsequent NO PDA further passivates the interface states, pursuing a high-quality SiC/SiO2 gate interface for improved device performance.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

SiC/SiO2 MOS capacitors were fabricated on an n-type 4H−SiC(0001) epilayer (donor density: 1×1016 cm−3 ) grown on a n-type substrate [Fig. 1]. The fabrication process starts with a surface pretreatment in a furnace under a gas atmosphere of 95% N2 and 5%H2 at atmospheric pressure. Compared with the pretreatment etching by pure H2[2−3], such N2/H2 gas composition is compatible with standard industrial furnace with high level of safety. Subsequently, a gate oxide layer of ~55 nm was deposited by LPCVD at 420∘C. Afterwards, NO PDA was performed at 1250∘C for 70 min for interface passivation. Finally, circular Al front electrode (diameter: 400μ m ) and Al back contact were deposited and sintered. Following device fabrication, electrical measurements ( C−V and I−V ) and material characterization were performed to evaluate the impact of the proposed process and gain insights into the underlying physical mechanisms.

[picture]

Fig. 1. Procedure and schematic of the proposed fabrication process of MOS capacitors.

Fig. 1. Procedure and schematic of the proposed fabrication process of MOS capacitors.

Results and Discussion

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To evaluate the quality of SiC/SiO2 interface, Dit  near the conduction band edge ( Ec ) is extracted from the C-V results by using high ( 100 kHz )-low (quasi-static) method. Fig. 2 (a) shows the Dit  distribution profiles of samples pretreated in N2/H2 mixture gas at 1350∘C for different treatment time duration. The lowest Dit  level is obtained in the 30 -min sample. Further prolonging the pretreatment time to 40 min leads to a noticeable increase of Dit , especially in shallow levels close to Ec. The results could be attributed to the layer-by-layer etching process of the SiC defective surface layers by H2. With 30 -min pretreatment, a clean Si -rich layer is exposed with the lowest level of Dit, but further extending the pretreatment time to 40 min exposes the underlying C -rich layer that inherently leads to higher density of Dit . In addition, two Nitrogen-based treatments, i.e., the N2/H2 pretreatment and the NO PDA, could both introduce Nitrogen atoms to passivate the SiC/SiO2 interface and improve its quality. The XPS C 1s spectra of samples without pretreatment and with a 30− min pretreatment were analyzed and compared. The C-C/C-Si ratio decreases from 0.038 to 0.026 after pretreatment, indicating an effective reduction of carbon clusters on the SiC surface due to the N2/H2 pretreatment.

The temperature dependence of the Dit  level during the 30−minN2/H2 pretreatment is also investigated [Fig. 2 (b)]. Samples pretreated at 1350∘C exhibits the lowest Dit  level. At higher temperature ( 1350∘C ), the accelerated etching and passivation reactions outweigh the trap generation from Si−C bond breaking, so the trap removal and passivation process dominants.

[picture]

Fig. 2. Energy distribution of Dit  extracted from samples with different pretreatment (a) time duration and (b) temperature.

Fig. 2. Energy distribution of D it extracted from samples with different pretreatment (a) time duration and (b) temperature.

The layer-by-layer etching process of H2 is verified by the AFM image of the SiC surface selective region pretreatment experiment [Fig. 3]. A layer of SiO2 is deposited and patterned to expose a selected SiC surface region to the N2/H2 pretreatment. After the 30−minN2/H2 pretreatment at 1350∘C, a Si−C bilayer of ~0.5 nm is removed from the SiC surface, exposing the Si-rich surface to improve the quality of SiC/SiO2 interface.

[picture]

Fig. 3. AFM image after selective region N2/H2 pretreatment.

Fig. 3. AFM image after selective region N 2 / H 2 pretreatment.

Any performance benefit introduced by optimizing the fabrication process should come without a penalty in the gate oxide reliability. Most reliability-relevant characteristics including the leakage current and time-dependent dielectric breakdown of the gate oxide from samples with and without the pretreatment ( 1350∘C for 30 min ) were compared. Both the leakage current and the breakdown electric field indicate the N2/H2 pretreatment does not negatively affect the gate oxide quality [Fig. 4 (a)]. Based on the statistical distribution of oxide breakdown electric field in Fig. 4 (b), the devices with N2/H2 pretreatment show a noticeable increase in the average Eox, indicating a better SiC surface was prepared for gate oxide deposition. The relatively large dispersion in the Eox distribution under both conditions is primarily attributed to intrinsic process-induced variations in oxide quality.

[picture]

Fig. 4. (a) Insulating properties of MOS capacitors with and without the pretreatment. (b) Statistical chart of Eox for the two samples.

Fig. 4. (a) Insulating properties of MOS capacitors with and without the pretreatment. (b) Statistical chart of E o x for the two samples.

TDDB test was further performed at room temperature to evaluate the reliability of the gate oxide pretreated at 1350∘C for 30 min [Fig. 5 (a)]. The stress electric field is 8MV/cm,8.25MV/cm, and 8.5MV/cm, with the corresponding Weibull slope (β) value of 0.98,1.16, and 0.94 . This value is relatively low in comparison to that of thermal oxide [5], which is attributed to the compromised quality of the LTO. To project the lifetime of the fabricated MOS capacitors, t63% is plotted against the applied gate electric field, as shown in Fig. 5 (b). From the projection, the lifetime of these devices can reach 10 years at room temperature with a maximum operating electric field of 6.74MV/cm.

[picture]

Fig. 5. (a) Weibull distributions of devices failures at various electric fields; (b) Ten-year lifetime predictions by choosing 63% failure rate.

Fig. 5. (a) Weibull distributions of devices failures at various electric fields; (b) Ten-year lifetime predictions by choosing 63 % failure rate.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

To conclude, the discussed process that integrates N2/H2 pretreatment, gate oxide deposition, and NO post deposition annealing demonstrated effective improvement of the SiC/SiO2 interface by removing the thermal-oxidation-related carbon clusters and the associated Dit.  Meanwhile, the quality of the gate oxide is not compromised by the pretreatment process, which could be further improved by optimizing the deposition method and conditions.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

This work is supported by Hong Kong RGC Strategic Topics Grant under STG3/E-602/23-N.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

Z. Wang, Z. Zhang, S. Liu, C. Shao, J. Robertson, and Y. Guo, Impact of carbon-carbon defects at the SiO2/4H−SiC(0001) interface: a first-principles calculation, Journal of Physics D: Applied Physics 55.2 (2021): 025109.

K. Tachiki, M. Kaneko, and T. Kimoto, Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of etching, deposition, and interface nitridation, Applied physics express 14.3 (2021): 031001.

K. Tachiki, M. Kaneko, T. Kobayashi, and T. Kimoto, Formation of high-quality SiC structures by excluding oxidation process with etching before deposition and high-temperature annealing, Applied physics express 13.12 (2020): 121002.

S. Glass, F. Reis, M. Bauernfeind, J. Aulbach, M. R. Scholz, F. Adler, L. Dudy, G. Li, R. Claessen, and J. Schäfer, Atomic-Scale Mapping of Layer-by-Layer Hydrogen Etching and Passivation of SiC (0001) Substrates, The Journal of Physical Chemistry C 120.19 (2016): 10361-10367.

B. Tsui, Y. Huang, T. Wu, and C. Chien, Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes, Microelectronics Reliability 123 (2021): 114186.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 59-65

doi: 10.4028/p-UxdeG4

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-20

Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

The original version of this paper is available on https://www.scientific.net/MSF.1192.59.pdf

X. Tian 1,a*, A. B. Renz 1, b, K. Melnyk 1,c, M. A. Yildirm 1, d, M. Boccarossa 2,e, L. Maresca 2,f, A. Irace 2, g, J. A. Gott 3, h, N. S. Agbo 4,i, P. Taylor 4,j, M. Antoniou 1,k, P. A. Mawby 1,1, P. M. Gammon 1,m

1 School of Engineering, University of Warwick, Coventry, United Kingdom

2 University of Naples Federico II, Naples, Italy

3 Warwick Manufacturing Group, University of Warwick, Coventry, UK

4 Dynex Semiconductor Ltd., Lincoln, UK

a* Xinkai.Tian@warwick.ac.uk, b Arne.Renz@warwick.ac.uk, c Kyrylo.Melnyk.1@warwick.ac.uk, d Mustafa.Yildirim@warwick.ac.uk, e marco.boccarossa@unina.it, f luca.maresca@unina.it, g  andirace@unina.it, hJ.Gott@warwick.ac.uk, iNereus.Agbo@dynexsemi.com, jPaul.Taylor@dynexsemi.com, kMarina.Antoniou@warwick.ac.uk, IP.A.Mawby@warwick.ac.uk, mP.M.Gammon@warwick.ac.uk.

Abstract

We investigate the physical and electrical characteristics of the Al-doped or undoped HfO2/SiO2 gate stacks on 4H−SiC by testing MOSCAP chips fabricated in house. A clear reduction in accumulation capacitance ( Cox ) with increasing chuck temperature from room temperature up to 523 K is observed, with Al-doping playing a key role and aligning with temperature-dependent Landau ferroelectric theory. Chips annealed at 1100∘C in N2 ambient show the highest Cox decrease rates while maintaining functional MOS interfaces with acceptable flatband voltage, hysteresis, and Dit profiles. TCAD simulations on a double trench MOSFET model, based on the extracted data indicate improved electro-thermal performance, demonstrating that Al -doped HfO2/SiO2 gate stacks are a promising approach for enhancing 4H−SiC power devices.

Keywords: Al-doped HfO2, ferroelectricity, paraelectricity, high-k dielectrics, crystallisation, accumulation capacitance, temperature-dependence, Dit  profile, short-circuit ruggedness.

Introduction

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Silicon Carbide ( SiC ) has several material advantages over silicon ( Si ) in power electronics applications, such as its wider bandgap, higher breakdown voltage, and higher operating temperatures of SiC devices. Hence, they could be used for making more efficient power-dense 4H−SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with lower on-resistances (Ron). Problems surrounding reliability under harsh conditions are still a challenge in 4H−SiC technology in this field. Short-circuit (SC) withstand time has been one of the challenges extensively researched, as the withstand times in 1.2kV4H−SiC MOSFETs have been low compared to their lower-rated 650 V counterparts [1]. Through Landau's theory of the temperature dependence of the dielectric constant and accumulation capacitance ( Cox ) in ferroelectric materials [2], the solution proposed was the integration of a ferroelectric hafnium oxide (HfO2)/ silicon dioxide (SiO2) gate-stack as the gate dielectric, which led to decreased peak current leakage and peak device temperature, resulting in improved electro-thermal behaviour of the device [3, 4]. This is based on the ferroelectric/paraelectric capacitance model from Landau's theory, where the dielectric permittivity increases up to when the operation temperature ( T ) reaches the Curie-Weiss temperature ( TCw ), but then decreases when T is above the TCw [2]. Research in ferroelectricity of HfO2 has shown that doping the HfO2 layer with different dopants, such as Si or aluminium (Al) could enhance the ferroelectric property of HfO2 [5, 6]. Therefore, the investigation will involve doped- HfO2/SiO2/4H−SiC MOS capacitor (MOSCAPs) chips.

In this study, the electrical performance and structural properties of the atomic layer deposited (ALD) Al-doped HfO2/SiO2/4H−SiC will be investigated. The focus will be on the Cox  change rate at increasing chuck temperatures against room temperature (RT) for the validity of Landau's theory. Flatband voltage ( VFB ), hysteresis and density interface traps ( Dit ) at RT are also investigated for studying the electrical reliability and integrity of the MOS interface.

Methodology

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For the fabrication of the MOSCAP chips in this investigation, seven 1 cm×1 cm chips have been cleaved from a 10μ m thick wafer consisting of an epitaxially grown light nitrogen-doped ( 1×1016cm−3 ) drift layer on top of a heavy nitrogen-doped ( >1×1020 cm−3 ) 4H-SiC substrate. The cleaved chips then underwent standard RCA cleaning with an: HF(10%)/RCA1/HF(10%)/RCA2/HF(10%), cleaning cycle. For the deposition of the HfO2/SiO2 gate-stack, 6 nm of SiO2 was deposited followed by 30 nm of doped/undoped HfO2 on top. Oxygen plasma is the oxidant of choice along with bis(diethylamido)silane (BDEAS) and tetrakis(dimethylamido)hafnium (TDMAHf) as Si and Hf precursors. This is all done by plasma-enhanced ALD (PE-ALD) at 200∘C with the Ultratech Fiji G2 PE-ALD system. For Al -doped HfO2 layers ALD cycles ratios of 1:19 and 1:29 of the Al2O3:HfO2 have been used to produce the Al−HfO2/SiO2/4H−SiC MOSCAP chips. Post deposition annealing (PDA) was done on the chips in nitrogen ( N2 ) ambient for one hour leading to a following list of MOSCAP chips produced:

Undoped HfO2/SiO2/4H−SiC MOSCAP chips annealed in a quartz furnace at 900∘C, 1000∘C, or 1100∘C.

Al-doped: HfO2/SiO2/4H−SiC MOSCAP chips annealed at 900∘C,1000∘C, or 1100∘C.

500 nm thick aluminium contacts were deposited on the top and bottom of the chips by means of metal sputtering to complete the fabrication of the devices. The top contacts were circular with a surface area of 1.26×10−3 cm2. The bottom surface of the chip was dry etched for the formation of the ohmic contact, before the bottom contact was deposited.

High-low frequency variant ±10 V capacitance-voltage (C-V) sweeps were conducted on at least 15 MOSCAP devices on each chip, with the average VFB, hysteresis and Dit  were extracted at room temperature (RT) (293 K). Dit  profiles of each MOSCAP device are extracted by the high-low frequency method with 100 Hz being the lowest frequency and 1 MHz being the highest frequency, using an Agilent E4980A LCR meter. High frequency C-V sweeps at varying probe station chuck temperature points (between 293 K - lowest and 523 K - highest) were performed on the MOSCAP chips; VFB, hysteresis and Cox(at+10 V) measurements were obtained at those various temperature points. A previously characterised ALD−SiO2/4H−SiC MOSCAP served as a reference for comparative electrical benchmarking. Grazing-incidence X-ray diffraction (GIXRD) measurements are conducted on the HfO2 surface for determining the crystal phase of the HfO2 film after a PDA; further structural analysis and the layer thicknesses have been verified by scanning transmission electron microscopy (STEM).

[picture]

Fig. 1. A TEM scan verifying the thickness of (a) deposited stacked dielectric as well the (b) element composition.

Fig. 1. A TEM scan verifying the thickness of (a) deposited stacked dielectric as well the (b) element composition.

[picture]

Fig. 2. SEM images of a unannealed (left) and N21100∘C annealed (right) MOS structure.

Fig. 2. SEM images of a unannealed (left) and N 21100 ∘ C annealed (right) MOS structure.

[picture]

Fig. 3. GIXRD measurements of the undoped/doped HfO2 films on SiO2/4H−SiC.

Fig. 3. GIXRD measurements of the undoped/doped H f O 2 films on S i O 2 / 4 H − S i C .

Physical Characterisation

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The STEM analysis of the N21100∘C annealed gate-stack MOS interface cross-section, shown in fig. 1, has confirmed the thicknesses of each insulator in the gate stack. Some crystallinity could be observed in the HfO2 layer from the STEM analysis. This detected crystallinity is like the crystallinity detected on HfO2 layers annealed on Si [9]. Comparative SEM conducted on an as-deposited layer of
HfO2 and then a N21100∘C annealed (both on separate chips of SiO2/4H−SiC ), have been done as shown in fig. 2. Fig. 2 depicts the grains of the annealed HfO2 to be greater than that of the asdeposited HfO2. Similar trends have also been seen on as-deposited or 700∘C annealed 500 nm thick HfO2 films on Si , where the method of deposition was by electron beam evaporation [10]. GIXRD results of fig. 3, show that for all the chips that underwent a high temperature PDA, a monoclinic crystal phase has been detected on the HfO2 film, which is synonymous with paraelectric properties of HfO2 [5]. Thus, links with the paraelectric phase of the ferroelectric theory could be established, especially the Cox decrease at higher chuck temperatures.

Electrical Results

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Fig. 4 shows normalised high-frequency C-V sweep results of a MOSCAP device taken from a 1:19 Al-doped HfO2/SiO2/4H-SiC chip annealed at 1100∘C in N2 at varying chuck temperatures. All recorded capacitance values have been referenced to the Cox  at RT. A Cox  (at +10 V ) decreased by 15%

[picture]

Fig. 4. Normalised Capacitance-Voltage sweep of a device on an Al2O3:HfO2 1:19 Aldoped MOSCAP chip.

Fig. 4. Normalised Capacitance-Voltage sweep of a device on an A l 2 O 3 : H f O 2 1:19 Aldoped MOSCAP chip.

[picture]

Fig. 5. Cox change vs chuck temperature results for all the PDA Al-doped HfO2/SiO2 gate-stack and SiO2 benchmark MOSCAP chips.

Fig. 5. C o x change vs chuck temperature results for all the PDA Al-doped H f O 2 / S i O 2 gate-stack and S i O 2 benchmark MOSCAP chips.

[picture]

Fig. 6. Cox change vs Chuck Temperature on retested MOSCAP devices.

Fig. 6. C o x change vs Chuck Temperature on retested MOSCAP devices.

[picture]

Fig. 7. (a) Hysteresis and (b) VFB results at varying chuck temperatures.

Fig. 7. (a) Hysteresis and (b) V F B results at varying chuck temperatures.

has been recorded as the chuck temperature rose from RT to 523 K . This result partially supports Landau's theory of temperature dependence on Cox in ferroelectric materials, especially in the paraelectric phase [2]. Fig. 5 shows the average Cox  change rate for all Al-doped gate stack MOSCAP chips in comparison to the ALD−SiO2 benchmark chip [7] at rising chuck temperatures (in 50 K increments). These results show that, regardless of the deposition cycles for the Al-doped HfO2, the PDA temperature of 1100∘C leads to the most favourable trends in Cox reduction rate with rising chuck temperatures; Hence, the doped MOSCAP chips annealed at 1100∘C have been taken further for further study. Cox change rate for the benchmark MOSCAP chip has been close to zero regardless of chuck temperature level. Moreover, high-frequency C-V sweeps, even with smaller chuck temperature increments of 25 K , have been conducted on a new set of MOSCAP devices on chips annealed at 1100∘C (fig. 6), further confirming the decreasing Cox trend (Fig. 5). This experimentally confirms a similar trend, also observed in silicon-on-insulator MOSFET devices [8].

Fig. 7a and 7b show the average hysteresis and VFB results at varying chuck temperature points for the MOSCAP chips. At all chuck temperature levels, the VFB is shown to be closer to the ideal VFB of ΦMS than that of the ALD-SiO2 2 benchmark. The hysteresis for the MOS interfaces is calculated using Eq. (1); therefore, a positive value indicates that negative charge is trapped in the MOS interface, but a negative value indicates that positive charge is trapped. Fig. 4b shows that positive
charges are trapped in the interface for the Al-doped gate stacks at all chuck temperature points, whereas negative charges are trapped for the ALD- SiO2 benchmark interface.

 Hysteresis =VFB( Acc. → Inv. )−VFB( Inv. → Acc. )(1)

Fig. 8 shows the RT Dit profile results of the Al-doped/undoped gate stacks and the ALD- SiO2 benchmark. The Dit  profile results are lower than 1012eV−1 cm−2 even when at 0.2 eV . Such results confirm that Al-doped gate-stacks can also make functional 4H−MOS interfaces.

TCAD Simulations Based on Experimental Results

The original version of this paper is available on https://www.scientific.net/MSF.1192.59.pdf

SC TCAD simulations have been conducted on a double trench MOSFET [11] employing similar methods for temperature-dependent dielectric constant ( ε ) curve fitting of the N2,1100∘C annealed 1:19 (Al2O3:HfO2)/SiO2 gate-stack and SC testing parameters, as of [3]. Fig. 9 shows the curve results of the curve fitting for the ε vs chuck temperature based on the electrical characterisation results. Given that no changes have been made on the design dimensions of the double trench MOSFET device, except for the gate insulator, it shows that there is improved electro-thermal performance when the temperature-dependent gate-stack has been adopted over the SiO2 gate insulator. Fig. 10 shows the responses of the MOSFET drain current ( ID ) and the maximum lattice temperature ( Tmax ) when under SC stress. Besides the lower peak Id and TMAX for the MOSFET that adopted the temperature-dependent ε gate-stack, the SC withstand time (SCWT) also increased by 2μ s.

[picture]

Fig. 8. Dit  profile results of the MOS interfaces of different gate insulator options.

Fig. 8. D it profile results of the MOS interfaces of different gate insulator options.

[picture]

Fig. 9. Dielectric constant ( ε ) vs Chuck temperature curve fit.

Fig. 9. Dielectric constant ( ε ) vs Chuck temperature curve fit.

A comparative Tmax  in the TCAD MOSFET lattice model switching from the SiO2 (fig. 11a) to the doped gate-stack (fig. 11b) have recorded a decrease in lattice temperature from 1286 K to 1229 K .

[picture]

Fig. 10. Simulated SC Id and Tmax for the DT MOSFET with constant SiO2 (red) and temperature dependent HfO2/SiO2 gate-stack gate insulator (blue).

Fig. 10. Simulated SC Id and Tmax for the DT MOSFET with constant S i O 2 (red) and temperature dependent H f O 2 / S i O 2 gate-stack gate insulator (blue).

[picture]

Fig. 11. Lattice temperature distribution in the simulated TCAD double trench MOSFET model with (a) constant SiO2 or (b) temperature dependent HfO2/SiO2 gate stack.

Fig. 11. Lattice temperature distribution in the simulated TCAD double trench MOSFET model with (a) constant S i O 2 or (b) temperature dependent H f O 2 / S i O 2 gate stack.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1192.59.pdf

Ferroelectric/Paraelectric properties of HfO2 on SiO2/4H−SiC have been investigated for the first time both physically and electrically on various materials/electrical characterisation methods. The physical characterisation through GIXRD and SEM reveals that the doped/undoped HfO2 layers that underwent a high-temperature PDA all exhibit a monoclinic (P21/c) crystal phase, which may justify the Cox  decrease against the rising chuck temperature. Chips that underwent a PDA of 1100∘C in N2 ambient led to the highest rates of Cox decreases between −13% and −18% from RT to 523 K . Furthermore, the VFB/ hysteresis vs chuck temperature, and RT Dit  profile results, all show that the gate-stack could still lead to functional and efficient MOS interfaces for 4H−SiC power MOS devices. Simulation results on a TCAD double trench MOSFET model, based on experimental data of this study, show improved electro-thermal performance when utilising the gate-stack as an alternative.

This study demonstrated that Al -doped HfO2/SiO2 gate-stacks could be a viable gate insulator option in SiC power devices. Further investigations into the stability of pure-ferroelectric property of HfO2 should be conducted in the future, with some changes to be made to the HfO2 doping ratios and the PDA process step thermal budget during the fabrication process of future gate-stack MOSCAP chips. The suitability of those gate stacks for MOSFET device integration will also encompass Dit (for channel mobility) and voltage breakdown (for gate leakage) parameters, as the polycrystalline nature of high temperature PDA HfO2 could sometimes lead to current leakage through the HfO2 layer [12].

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.59.pdf

G. Kampitsis, S. Papathanassiou, S. Manias, "Comparative evaluation of the short-circuit withstand capability of 1.2 kV silicon carbide (SiC) power transistors in real life applications", Microelectronics Reliability, Volume 55, Issue 12, Part B, (2015), pp. 2640-2646, ISSN 00262714, https://doi.org/10.1016/j.microrel.2015.09.012.

G.A. Salvatore et al., "Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory," in IEEE TED, vol. 58, no. 9, pp. 3162-3169, Sept. 2011.

M. Boccarossa et al., "The Ferro-Power MOSFET: Enhancing Short-Circuit Robustness in Power Switches With a Ferroelectric Gate Stack," in IEEE Access, vol. 13, pp. 59264-59274, 2025, doi: 10.1109/ACCESS.2025.3555931.

M. Boccarossa et al., "Substantial Improvement of the Short-circuit Capability of a 1.2 kV SiC MOSFET by a HfO2/SiO2 Ferroelectric Gate Stack," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 88-91, doi: 10.1109/ISPSD59661.2024.10579678.

Mueller, S., Mueller, J., Singh, A., Riedel, S., Sundqvist, J., Schroeder, U. and Mikolajick, T. (2012), Incipient Ferroelectricity in Al-Doped Thin Films. Adv. Funct. Mater., 22: 24122417. .

Park, M.H., Lee, Y.H., Kim, H.J., Kim, Y.J., Moon, T., Kim, K.D., Müller, J., Kersch, A., Schroeder, U., Mikolajick, T. and Hwang, C.S. (2015), Ferroelectricity and Antiferroelectricity of Doped Thin -Based Films. Adv. Mater., 27: 1811-1831. .

X. Tian et al., "The Impact of Varying the High-Temperature Post-Deposition Anneal Time or Temperature Ramp Rates on ALD-SiO2/4H-SiC Interfaces," 2024 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe), Cardiff, United Kingdom, 2024, pp. 1-5, doi: 10.1109/WiPDAEurope62087.2024.10797374.

Jiseok Kim, Siddarth A. Krishnan, Sudarshan Narayanan, Michael P. Chudzik, Massimo V. Fischetti, "Thickness and temperature dependence of the leakage current in hafnium-based Si SOI MOSFETs", Microelectronics Reliability, vol. 52, Issue 12, 2012, pp. 2907-2913, ISSN 0026-2714, .

Zhang, XY., Hsu, CH., Lien, SY. et al. Temperature-Dependent HfO2/Si Interface Structural Evolution and its Mechanism. Nanoscale Res Lett 14, 83 (2019). .

Kant, S., Kumar, V.S.R.S.P., Kumar, M. et al. Surface wettability, morphology and optical characteristics of HfO2 films grown systematically by electron beam evaporation. Appl. Phys. A 129, 172 (2023). .

K. Melnyk et al., "Analysis and Performance Trade-Offs of State-of-the-Art 4H-SiC Trench MOSFET Technology," 2024 IEEE ECCE, Phoenix, AZ, USA, 2024, pp. 6764-6770.

M.A. Yildirim et al., "Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing," MSF, vol. 1158, pp. 67-74, Sept. 2025, doi: 10.4028/p-q2iyst. Available: .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 67-74

doi: 10.4028/p-1Pi4j8

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-21

Accepted:
2026-01-31

Online:
2026-05-20

High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

Johannes Ziegler 1,4a*, Dick Scholten 2,b, Holger Bartolf 1,c and Jörg Schulze 3,4,d

1 Robert Bosch GmbH, Mobility Electronics, 72762 Reutlingen, Germany

2 Robert Bosch GmbH, Corporate Research, 71272 Renningen, Germany

3 Fraunhofer IISB, 91508 Erlangen, Germany

4 Chair of Electron Devices (LEB), FAU Erlangen-Nürnberg, 91508 Erlangen, Germany

ajohannes.ziegler2@de.bosch.com, b  dick.scholten@de.bosch.com, c  holger.bartolf@de.bosch.com,  djoerg.schulze@iisb.fraunhofer.de

Abstract

In this paper, we study high-temperature H2, N2, and H2/N2 surface conditioning processes prior to the SiO2 deposition as a promising approach for SiO2/4H−SiC interface preparation in metal-oxide-semiconductor field-effect transistors (MOSFET). A thorough electrical analysis is presented, consisting of temperature-dependent transfer characteristics as well as reliability studies regarding bias temperature instabilities (BTI) and dielectric breakdown behavior. Especially N2-containing surface pretreatments were found to greatly suppress electron traps, whereas hole trapping is enhanced. Finally, X-ray photoelectron spectroscopy (XPS) was utilized to elucidate the elemental surface composition after the different annealing procedures. The obtained results are in good agreement with the electrical characterization and complement already published results regarding the formation of surface reconstructions on 4H−SiC through H2 and H2/N2 annealings.

Keywords: SiO2/4H−SiC, MOSFET, Surface Conditioning, Transfer Characteristics, Channel Mobility, Threshold Voltage, PBTI, NBTI, TZDB, TDDB, XPS, Surface Reconstruction.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

Within the recent years, the SiC power MOSFET market has been massively grown. The wide bandgap of the 4H−SiC material comes along with a high breakdown field strength, offering the possibility of shrinking the drift zone thickness and ultimately its resistance contribution. Together with other superior physical properties like a high thermal conductivity, 4H−SiC is expected to continuously replace Si -based devices in high-voltage, energy-efficient power electronics application. A fundamental building block of every MOSFET device is the oxide-semiconductor interface. Despite the ongoing efforts to improve the SiO2/4H−SiC interfacial quality, the resulting channel mobility remains below expectation. Hence, metal-oxide-semiconductor (MOS) channel engineering is still a highly interesting matter of applied research.

With progressing scientific achievements in the field of SiO2/4H−SiC interface improvement, it is nowadays common knowledge, that thermal oxidation of 4H−SiC creates various defect states, located at different energetic levels. Exchanging a thermally grown by a deposited SiO2 gate oxide, however, turned out to yield a more abrupt material transition, if combined with an appropriate post-deposition annealing (PDA) process [1]. Hence, low pressure chemical vapor deposition (LPCVD) became the method of choice for high-quality gate oxide formation in 4H−SiC MOSFETs. Along with the transition to deposited gate oxides, the investigation of appropriate surface pretreatment processes prior to the dielectric deposition gained growing scientific interest. In this regard, especially H2-based, high-temperature surface conditioning in combination with a deposited SiO2 gate oxide was recently shown to offer a substantial increase in the channel mobility [2,3]. Even if the physical origin of the remarkable performance improvement is not yet fully understood, it is speculated, that mobilitylimiting defects are heavily reduced by H2 conditioning together with avoiding substrate oxidation.

The surface configuration of H2-annealed Si -face ( 0001 ) 4H−SiC is a matter of scientific interest since decades. Within the published studies, several hints to explain the recently shown mobility improvement can be found. Typically, upon H2 annealing, highly ordered silicate adlayers have been
observed, which provide an atomically sharp, epitaxial material transition to the underlying 4H−SiC [4]. Such silicate layers are expected to provide a well-suited seed layer for subsequent SiO2 deposition. However, it was found out, that the resulting surface reconstruction leaves behind an unsaturated bond per unit cell, which forms a mid-gap interface state. In this regard, researchers discovered an even more promising surface structure by adding a N2 annealing subsequent to the H2 treatment [5]. Such a combined H2/N2 surface treatment was proven to form an epitaxial silicon oxynitride ( SiON ) adlayer in a self-limiting manner, which potentially serves as an ideal insulator/ 4 H SiC transition due to the absence of dangling bonds. Even if first attempts to transfer those theoretical predictions to simple MOS capacitor devices have been published by Rozen et al. [6], to the best of our knowledge, there exists no successful demonstration on 4H−SiC MOSFET devices. In this work, we close this gap by investigating the effect of high-temperature H2, N2 and H2/N2 surface conditioning processes on the electrical performance of lateral 4H−SiC MOSFETs. Besides a thorough evaluation of the resulting transfer characteristics, reliability aspects of the processed gate oxides are discussed. Finally, the electrical results are correlated with XPS analysis.

Experimental

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To study the effect of different high-temperature surface conditioning processes, we fabricated lateral, long channel MOSFET devices on epitaxial n-type layers, grown on conventional 4∘-off axis ( 0001 ) 4H−SiC6′′ substrates. A schematic cross section of the MOSFET devices is shown in Fig. 1 together with the detailed process chain of the investigated gate formation procedures. To prepare the wafers for the variation in high-temperature surface conditioning, three subsequent ion implantation steps were conducted. In a first step, Al was implanted as a p-type dopant to create the channel region. Subsequently, a surrounding p-type border was implanted with a higher Al dose, which later serves as ohmic contact, connecting the channel region to ground potential during electrical characterization. Finally, highly doped n -type source and drain regions were formed by implanting ionized N atoms. Except the ion implantation steps, device fabrication took place in the corporate research cleanroom of the Robert Bosch GmbH. Following the implantation block, dopant activation was conducted by the state-of-the-art process of high-temperature annealing with the wafer surface being covered by a C capping.

[picture]

Fig. 1. Schematic cross section of the fabricated long channel MOSFET devices. Process chain and details regarding the gate stack formation including the surface conditioning procedures are given on the right side together with the respective sample nomenclature.

Fig. 1. Schematic cross section of the fabricated long channel MOSFET devices. Process chain and details regarding the gate stack formation including the surface conditioning procedures are given on the right side together with the respective sample nomenclature.

Prior to the surface conditioning processes, the wafers were cleaned to subsequently grow a sacrificial oxide layer, which is removed in a wet buffered oxide etch (BOE) solution. Right after, the wafers were processed according to the fabrication scheme, shown in Fig. 1. As a baseline for comparing the electrical results, a reference sample without additional surface treatment, denoted as " SiO2 ", was fabricated. All other samples underwent a dedicated high-temperature surface conditioning process, namely H2, N2 and a combination thereof. The respective processing conditions in terms of temperature profile over time and gas ambient are schematically provided in Fig. 1. All pretreatment processes were performed ex-situ to the subsequent LPCVD SiO2 formation. However,
the anticipated surface passivation layers upon H2 and H2/N2 annealing are published to be very stable against air exposure [4,5]. After the surface conditioning processes, all wafers were put together and processed nominally the same. SiO2 gate dielectrics were deposited by means of LPCVD and annealed in NO ambient at moderate temperatures to avoid reoxidation of interfacial layers. An insitu P doped LPCVD poly-Si layer was subsequently deposited as gate electrode material. Following a dry etching step to structure the poly- Si , a thick SiO2 insulation layer was formed to encapsulate the MOS stack, again via a LPCVD process. Afterwards, electrical contacts to the source, drain, gate and bulk regions had to be defined. Starting with the ohmic contacts to the 4H−SiC, the insulation layer was selectively etched in dedicated areas, followed by NiSi formation via sputtering and rapid thermal annealing (RTA) at elevated temperatures. Finally, to ensure a reliable needle contact to the MOSFET terminals during electrical characterization, thick Al contact pads were formed.

The fabricated MOSFET devices were electrically characterized in a Cascade Microtech probe station. A Keithley 2636 sourcemeter was connected to the probe station to record transfer characteristics and perform BTI, time-zero dielectric breakdown (TZDB) and constant voltage timedependent dielectric breakdown (TDDB) analysis. For analyzing the atomic surface configuration, XPS characterization was carried out in a PHI Quantera II equipment. Si2p, C1s, O1s and N1s core level spectra were acquired by using a monochromatic AlKαx-ray source with a take-off angle of 45∘. The resulting diameter of the analyzed area is roughly 200μ m.

Results and Discussion

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Fig. 2 a)-c) present the transfer characteristics of our devices. In Fig. 2 a), the linear drain current ID curve traces of one exemplary device per wafer are shown. The gate voltage VG was swept in 0.1 V steps from -5 V to +25 V and vice versa. The drain voltage VD was set to 0.3 V . To better compare the turn-on characteristics of the differently processed MOSFETs, a logarithmic illustration of ID in the voltage range 0 V<VG<4 V is given in Fig. 2 b ). Out of the results in Fig. 2 a ) and b), the peak field-effect mobility μFE, threshold voltage Vth  and sub-threshold hysteresis ΔVsub-th  are extracted and shown as box plots in Fig. 2 c) for a statistics of 16 devices per wafer.

[picture]

Fig. 2. a) Linear transfer characteristics of one exemplary MOSFET device per wafer with a channel length L=20μ m and width W=300μ m. The measurements were done at room temperature. An extrapolation in the linear curve regime is sketched by dashed lines to indicate the Vth  extraction. The ID−VG turn-on behavior is shown in b ) in logarithmic scale. The current level to extract ΔVsub-th  between up- and down-sweep direction is illustrated by the dashed line. The characteristic MOSFET parameters μFE,Vth  and ΔVsub-th  are derived for 16 devices per sample and shown as box plots in c). The dashed lines indicate the reference level of the SiO2 wafer.

Fig. 2. a) Linear transfer characteristics of one exemplary MOSFET device per wafer with a channel length L = 20 μ m and width W = 300 μ m . The measurements were done at room temperature. An extrapolation in the linear curve regime is sketched by dashed lines to indicate the V th extraction. The I D − V G turn-on behavior is shown in b ) in logarithmic scale. The current level to extract Δ V sub-th between up- and down-sweep direction is illustrated by the dashed line. The characteristic MOSFET parameters μ F E , V th and Δ V sub-th are derived for 16 devices per sample and shown as box plots in c). The dashed lines indicate the reference level of the S i O 2 wafer.

Comparing all wafers, a substantial μFE improvement of up to 2.2 times the reference value as well as a reduced ΔVsub-th  value is observed for both wafers, which have been processed with N2-containing surface conditioning. Furthermore, the N2−SiO2 and H2/N2−SiO2 devices turn on with a significantly steeper ID−VG slope, as shown in Fig. 2 b). Those aspects clearly reveal a superior SiO2/4H−SiC
interface quality after N2-containing surface pretreatment. Comparing the N2−SiO2 to the H2/N2−SiO2 sample, the N2-alone process seems to be even more effective to boost the MOSFET's performance. Interestingly, in contrast to the published results [2,3], the H2 surface conditioning process just marginally improves μFE, while energetically deeper interface states are even slightly increased, as ΔVsub-th  is enlarged and the onset of ID increase is delayed, as compared to the SiO2 reference wafer.

To get further insights regarding the SiO2/4H−SiC interface quality upon the investigated pretreatment processes, the temperature dependence of Vth  and μFE was evaluated by measuring the transfer curves between 25∘C and 175∘C in 25∘C steps. The corresponding results are elucidated in Fig. 3 a) and b), respectively.

[picture]

Fig. 3. a) Temperature-dependent Vth  for one exemplary device per sample. b) The corresponding μFE values show a different TC, which can be explained by considering the temperature dependence of μC,μSR and μOP. A qualitative drawing of the scattering contributions is given in c). While μSR and μOP are assumed to be comparable between the wafers, especially μC strongly depends on the interface preparation and is therefore significantly improved for the N2−SiO2 sample.

Fig. 3. a) Temperature-dependent V th for one exemplary device per sample. b) The corresponding μ F E values show a different TC, which can be explained by considering the temperature dependence of μ C , μ S R and μ O P . A qualitative drawing of the scattering contributions is given in c ) . While μ S R and μ O P are assumed to be comparable between the wafers, especially μ C strongly depends on the interface preparation and is therefore significantly improved for the N 2 − S i O 2 sample.

Regarding Vth , a distinct difference between the devices with N2-containing pretreatment and the SiO2 sample is observed in Fig. 3 a). Already at room temperature, the N2−SiO2 and H2/N2−SiO2 samples show a lower Vth  value, which can be explained by the steeper ID−VG turn-on behavior as a result of a reduced interface trap density around the conduction band edge. The Vth  gap, however, decreases with increasing temperature. The more stable Vth  temperature behavior of the N2−SiO2 and H2/N2−SiO2 samples is another indication for the improved interface characteristics. The superior interfacial quality additionally shows up in the μFE trend in Fig. 3 b). Whereas the samples with lower μFE exhibit a positive temperature coefficient (TC) of μFE, the behavior clearly reverses for the wafers, which were processed with N2-containing surface conditioning. A qualitative explanation for this observation is given in Fig. 3 c ), where the temperature dependence of the dominant scattering mechanisms, namely Coulomb scattering μC, surface roughness scattering μSR and optical phonon scattering μOP, is sketched [7]. The bulk mobility μC is omitted as it is known to be significantly larger than the other contributions. According to Matthiessen's rule, the lowest value dominates the overall μFE behavior. In the case of the SiO2 and H2−SiO2 sample, Coulomb scattering, which has a positive TC, limits μFE . As the interface quality gets remarkably improved by N2-containing pretreatment, the contribution of μC decreases, such that the overall μFE takes over the negative TC from μOP. Similar behavior is typically only reported on non-polar surfaces like (11-20) or (0-33-8), where the SiO2/4H SiC interface quality is inherently much better [3,8].

During long-term operation of a MOSFET, the stability of important parameters like Vth  is crucial. To compare the devices' Vth  stability with differently processed gate oxides, high-temperature gate bias (HTGB) analysis was performed at 175∘C and a gate bias of +20 V and -11 V , respectively. Prior to each Vth  readout, a preconditioning pulse according to Fig. 4 a) was applied to reduce the contribution of fully reversible trap charging/discharging on the shift in Vth . The resulting ΔVth  drift signal is shown in Fig. 4 b) and c) for positive BTI (PBTI) and negative BTI (NBTI) stress. For each
sample and stress bias, six devices were analyzed. The respective measurement data is given together with the averaged values per sample and accumulated stress time t.

[picture]

Fig. 4. a) Schematic explanation of the HTGB measurement procedure. Prior to every Vth  readout, a preconditioning pulse is applied to reduce the ΔVth  drift contribution of fully reversible trap charging/discharging. Note that even if the preconditioning pulse plateau phases are short (~0.1 s), they can add up a parasitic BTI stress. ΔVth  drift signals are shown in b) for PBTI and c) for NBTI stress at 175∘C. The measurement data points of six devices per wafer and stress bias are shown together with the averaged values.

Fig. 4. a) Schematic explanation of the HTGB measurement procedure. Prior to every V th readout, a preconditioning pulse is applied to reduce the Δ V th drift contribution of fully reversible trap charging/discharging. Note that even if the preconditioning pulse plateau phases are short ( ~ 0.1 s ) , they can add up a parasitic BTI stress. Δ V th drift signals are shown in b) for PBTI and c) for NBTI stress at 175 ∘ C . The measurement data points of six devices per wafer and stress bias are shown together with the averaged values.

In terms of PBTI in Fig. 4 b), a significantly lower ΔVth  drift is observed for the samples with N2− containing pretreatment. Hence, we speculate, that at least a part of the mobility-limiting interface traps, which are remarkably reduced for the N2−SiO2 and H2/N2−SiO2 samples, can also trap electrons (quasi-) permanently. In contrast, however, interface nitridation prior to the gate oxide deposition seems to contribute to enhanced hole trapping during NBTI stress, as shown in Fig. 4 c ). Such behavior is similarly observed for heavily nitrided SiO2/4H−SiC interfaces upon prolonged NO PDA at high temperatures [9]. The SiO2 as well as the H2−SiO2 sample, on the other hand, show negligible ΔVth  drift during NBTI stress. Even a small positive ΔVth  is observed until t≈103 s, which is assumed to be caused by the parasitic PBTI stress contribution originating from the preconditioning pulse.

Besides the stability of Vth , securing a reliable gate oxide operation over lifetime is indispensable. First evaluations in this regard were done by means of TZDB and constant voltage TDDB analysis. The corresponding results are shown in Fig. 5 a)-c). In Fig. 5 a) the gate leakage current normalized to the device area was recorded by increasing VG with a constant ramp of 0.5 V/s until dielectric breakdown occurred. Per Wafer, ten MOS capacitor devices, built on the n-type doped epi surface, are shown together with a fitted curve, assuming an ideal Fowler-Nordheim (FN) gate leakage behavior. For the calculation of the electric field E, the resulting oxide thicknesses after device processing were considered by performing capacitance-voltage ( C−V ) measurements. The oxide's dielectric constant was assumed to be εr=3.9 for all samples. Compared to the SiO2 reference sample, all pretreatment processes contribute to a narrower distribution of the breakdown field strength EBD. The highest EBD around 11MV/cm is reached for the H2−SiO2 sample, while especially the N2−SiO2 and H2/N2−SiO2 samples show a distinct shift of the gate leakage curves, attributed to a lower energetic FN tunneling barrier ΦB. The shown ΦB values were calculated by considering an effective electron mass of m*=0.42m0[10]. Similar lowering of ΦB was already reported for prolonged interface nitridation via NO PDA [10]. Additionally, at high gate oxide fields, a more pronounced deviation from the ideal FN curve shape is observed for both samples with N2-containing surface conditioning. While at moderate E-fields in the oxide, the leakage current is predominantly governed by FN tunneling, at higher fields, electrons have sufficient energy to generate holes by anode hole injection from the poly-Si electrode and/or impact ionization in the oxide near the anode. The generated holes drift towards the SiO2/4H−SiC interface, get trapped and hence, enhance the electric field, which further reduces the FN tunneling barrier for electrons [11]. In logical consequence, electron and hole injection amplify each other, leading to a deviation from the ideal FN current
behavior in the high E-field regime. The gap between the measured and fitted current is more pronounced for the N2−SiO2 and H2/N2−SiO2 samples. As the bulk SiO2 is assumed to have comparable quality for all samples, the current enhancement at higher fields is expected to originate from increased hole trapping near the SiO2/4H−SiC interface. This conclusion is supported by the observations from NBTI stress analysis, where N2-containing pretreatment was shown to create interfacial defect states, that capture holes during NBTI as well as high-field TZDB characterization.

To investigate a potential impact of the differences in ΦB and hole trap density on the TDDB characteristics, MOS capacitor devices from the SiO2 and N2−SiO2 samples were stressed at three different E-fields at a temperature of 140∘C. For each stress field and sample, eight devices were analyzed. Fig. 5 b) shows the respective leakage current evolution over time, while c) illustrates the time-to-breakdown tBD data together with the t63% values, which we extracted by assuming a Weibull distribution. Interestingly, at least in the investigated E-field range, the resulting tBD values are nearly the same for both samples, even if the initial gate leakage current is significantly higher for the N2 SiO2 devices due to lower ΦB and stronger leakage current enhancement. However, as can be seen by the humps in Fig. 5 b), the chosen E-field values are still in a range, where significant hole injection occurs, which can lead to an overestimation of the gate oxide lifetime. Hence, additional TDDB analysis at lower stress fields would need to be performed to reliably exclude a detrimental effect of N2 pretreatment on the gate oxide lifetime at typical operation conditions.

[picture]

Fig. 5. a) TZDB measurements of ten MOS capacitor devices per sample at room temperature. At moderate E-fields, the measurement curves are reproduced by assuming FN-governed electron tunneling through the SiO2. The calculated ΦB values, extracted from the fit, are given. b) Constant voltage TDDB measurements of eight MOS capacitor devices per sample and stress field at 140∘C. The stress time tBD, when dielectric breakdown occurs, is detected and plotted in c) over the E-field. The t63% values are calculated by assuming a Weibull distribution.

Fig. 5. a) TZDB measurements of ten MOS capacitor devices per sample at room temperature. At moderate E -fields, the measurement curves are reproduced by assuming FN-governed electron tunneling through the S i O 2 . The calculated Φ B values, extracted from the fit, are given. b) Constant voltage TDDB measurements of eight MOS capacitor devices per sample and stress field at 140 ∘ C . The stress time t B D , when dielectric breakdown occurs, is detected and plotted in c) over the E -field. The t 63 % values are calculated by assuming a Weibull distribution.

In the attempt to correlate the electrical results with compositional surface characterization, we performed XPS analysis. Additional samples were prepared by annealing epitaxial n-type wafers with the same H2, N2 and H2/N2 processes as utilized for the electrical MOSFET devices. A bare 4H−SiC epi wafer was added as reference. The XPS core level spectra were acquired ex-situ to the annealing processes. The corresponding results are presented in Fig. 6 a)-f). In Fig. 6 a), the elemental surface composition is evaluated by weighting the integrated signal intensity of the Si 2 p , C1s, O1s and N1s core level peaks. For all elemental components, three different measurement spots were analyzed. Even if this simple integration method contains some uncertainties regarding the exact compositional values, Fig. 6 a) clearly reveals the formation of O- and N-containing adlayers after all hightemperature surface treatments. While the O-content in the Ref. sample stems from a thin, native oxide layer as well as potential adsorbates from air exposure, the fraction of O and N atoms at the surface remarkably increases for all annealed surfaces by substituting C atoms in the uppermost atomic layers. Regarding the interfacial N coverage, it is often reported, that a higher N amount enhances the μFE of a MOSFET, while especially the device's reliability has to be taken with caution [9]. Interestingly, in terms of μFE and PBTI drift, the N2−SiO2 sample reveals the best electrical
performance, even if its interfacial N density seems to be reduced, compared to the H2/N2−SiO2 sample. Note that the elemental surface composition could be also affected by further MOS stack and device fabrication and might be slightly different in a fully processed MOSFET device. However, also the N binding configuration might have an impact on the defect passivation. As aforementioned in the introductory section, especially for H2[4] and H2/N2[5] treatment of 4 H -SiC surfaces, the formation of epitaxial surface reconstructions is reported. The published structures are shown in Fig. 6 e) and f) for H2 and H2/N2, respectively. Both structures consist of an uppermost SiO layer, which is either directly bonded to the 4H−SiC surface or connected via a bridging SiN interlayer. In case of the H2 treatment, one dangling bond per unit cell is left behind, while the H2/N2 treatment ideally passivates the surface.

[picture]

Fig. 6. a) Elemental surface composition for the investigated samples was calculated by weighting the integrated Si2p, C1s, O1s and N1s signal intensities. The corresponding core level spectra are shown in b) for Si2p, c) for O1s and d) for N1s for three measurement spots per sample. Energetic positions of the peaks are indicated by dashed lines. The published surface configurations after e) H2 [4] and f) H2/N2 [5] treatments of 4H−SiC are schematically drawn.

Fig. 6. a) Elemental surface composition for the investigated samples was calculated by weighting the integrated Si2p, C1s, O1s and N1s signal intensities. The corresponding core level spectra are shown in b) for Si2p, c) for O1s and d) for N1s for three measurement spots per sample. Energetic positions of the peaks are indicated by dashed lines. The published surface configurations after e) H 2 [4] and f) H 2 / N 2 [5] treatments of 4 H − S i C are schematically drawn.

To discuss the potential formation of such surface reconstructions in our experiments, the detailed XPS core level spectra of Si2p, O1s and N1s are given in Fig. 6 b)-d). All spectra were corrected to the theoretical binding energy of the Si 2 p peak in an ideal 4H−SiC crystal. As compared to the reference sample, Fig. 6 b) shows a pronounced shoulder of different shape for the samples with hightemperature surface conditioning. SiO surface components are typically observed towards higher binding energies, whereas SiN bonds are known to energetically lie between the SiO and SiC component [5]. Those considerations are in line with our measurements, where an increased intensity in the SiN region is observed especially for the N2 and H2/N2 surface treatment. Interestingly, the intensity increase of the Si2p spectra for the H2 and H2/N2 sample towards higher binding energy nearly perfectly overlap. This observation is in agreement to the energetical position of the O1s peak in Fig. 6 c), which is identical for both samples. Hence, it is speculated, that the O atoms are similarly bound in both configurations. The H2/N2 sample, however, contains an additional, N-related contribution in Fig. 6 b). Those observations promote the hypothesis, that similar surface adlayers, as shown in Fig. 6 e) and f), are created by the H2 and H2/N2 annealings in our experiment. In contrast, the N2 treatment seems to form a slightly different adlayer, as compared to the H2/N2 treatment. The O1s peak for the N2 sample is slightly shifted, pointing towards a different Si -O binding configuration. The N1s peak, however, seems to have a similar binding energy.

Summarizing the XPS analysis, our observations are in good agreement with published considerations and our electrical data. The N2-containg pretreatments were shown to efficiently suppress mobility-limiting traps by passivating the surface. H2 treatment, in contrast, leaves behind one dangling bond per unit cell, which could be a potential explanation for the less pronounced μFE improvement after this annealing. However, the reliability of SiO2 gate dielectrics upon N2-containing surface conditioning has to be taken with caution, as the resulting surface configurations, even if they slightly differ from each other, were shown to be prone to hole trapping.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

In this work, we investigated the impact of high-temperature H2, N2, and H2/N2 surface conditioning processes on the electrical performance of lateral SiO2/4H−SiC MOSFETs and correlated the results with compositional XPS surface analysis. Especially N2-containing surface treatments were shown to greatly suppress electron trapping states around the conduction band edge, leading to a remarkably improved conductivity of the gate-controlled 4H−SiC/SiO2 interface. However, similarly to heavily NO-nitrided SiO2/4H−SiC interfaces, hole traps arise, which could have a detrimental effect on the device's reliability during long-term operation. In contrast to recently published results regarding H2 treatments, its beneficial effect on μFE could not be reproduced to the same extent.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

This work has received funding from the IPCEI ME/CT project. The IPCEI ME/CT project itself is supported by the Federal Ministry for Economic Affairs and Energy on the basis of a decision by the German Parliament, by the Ministry for Economic Affairs, Labor and Tourism of BadenWürttemberg based on a decision of the State Parliament of Baden-Württemberg, the Free State of Saxony on the basis of the budget adopted by the Saxon State Parliament, the Bavarian State Ministry for Economic Affairs, Regional Development and Energy and financed by the European Union NextGenerationEU.

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The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 75-80

doi: 10.4028/p-0waUsG

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-20

Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

Marilena Vivona 1,a*, Salvatore Ethan Panasci 1, b, Marco Zignale 1,c, Valerio Votadoro 1, d, Salvatore Di Franco 1,e, Emanuela Schilirò 1,f, Giuseppe Greco 1, g, Raffaella Lo Nigro 1, h, Patrick Fiorenza 1,i, Filippo Giannazzo 1,j, Fabrizio Roccaforte 1,k

1 CNR-IMM, Strada VIII n.5, Zona Industriale, I-95121, Catania, Italy

Abstract

In this work, the electrical properties of Mo2C/4H−SiC Schottky contacts were studied at different annealing temperatures. In particular, the Schottky barrier height was derived by currentvoltage measurements on as-deposited and 400∘C and 700∘C-annealed contacts. The Schottky barrier height was comparable for the as-deposited and 400∘C-annealed Mo2C/4H-SiC contact (0.94 and 0.96 eV , respectively), while it increased ( 1.07 eV ) for the 700∘C-annealed Mo2C/4H−SiC one. For the sample annealed at 700∘C, the electrical characterization of the diodes was combined with the study of the surface and interface electrical properties, by Kelvin-probe force microscopy (KPFM) and frequency dependent capacitance-voltage measurements ( C−f−V ) and discussed assuming a Mo/4H−SiC Schottky contact ( ΦB=1.39eV ) as a reference. The KPFM measurements revealed a similar value of the surface potential, thus suggesting that the work function of the metal is the same in both cases. On the other hand, a higher density of interface state was obtained by C−f−V for the Mo2C/4H-SiC system. This latter can explain the reduction of the Schottky barrier height observed for this system.

a* marilena.vivona@imm.cnr.it, b salvatoreethan.panasci@imm.cnr.it, c marco.zignale@imm.cnr.it, d valerio.votadoro@cnr.it, e salvatore.difranco@imm.cnr.it, f emanuela.schilirò@imm.cnr.it,
jilippo.giannazzo@imm.cnr.it, kfabrizio.roccaforte
*corresponding author

Keywords: Mo2C/4H-SiC interface, Schottky contact, electrical characterization.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

The Schottky-barrier diode (SBD) on 4H-SiC is a well-established technology, currently employed in several power electronics applications within the medium-to-high voltage range [1]. Although the advantages (namely fast switching, low forward voltage drop, high temperature operations) of using 4H-SiC-SBD are undoubted, further technological optimizations are still necessary to fully exploit the potential of 4H−SiC [2]. To this end, various approaches have been explored to improve the properties of the metal /4H−SiC interface, which underpins the performance of the SBDs, with particular attention to the metal choice and its interaction with 4H−SiC during thermal annealing for the Schottky contact formation [3]. In recent years, molybdenum (Mo) has attracted interest due to its good thermal stability and ability to form contacts with low Schottky barrier height, which is beneficial for minimizing the conduction power losses [4]. However, a wide variability in the Schottky barrier height has been observed in Mo/4H−SiC Schottky contacts, depending on several factors, such as surface passivation treatments [5], temperature of the metal deposition [6] and metal stack composition [7], with the ΦB varying between 1.0 and 1.5 eV . Recently, we investigated Mo/4H−SiC Schottky contact subjected to annealing treatments up to 950∘C, observing a reduction of the ΦB from 1.42 eV to 1.29 eV upon annealing at 950∘C, without any evidence of interface reaction between metal and semiconductor [8]. In that case, the reduction of ΦB was associated with
the enlargement and preferential orientation of the metal grains, as demonstrated by X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM) [8]. Nevertheless, based on the ternary phase diagram of the Mo-Si-C system, solid-state reactions can occur between Mo and both silicon ( Si ) and carbon ( C ), leading to the formation of carbides and silicides. This tendency opens the possibility to further explore and tune the Schottky barrier properties to 4H−SiC, potentially broadening the range of achievable ΦB values. As an example, Mo-based contacts containing C have been recently investigated, either deposited in laminated layers or obtained from Mo-C alloyed targets [7,9], demonstrating stable electrical characteristics even at high annealing temperature. However, the origin of this electrical behavior is not fully clear yet.
In this paper, the behavior of the Schottky barrier height ΦB in Mo-carbide /4H−SiC contacts was investigated, as a function of the annealing temperature. The electrical characterization of the diodes was combined with the study of the surface and interface electrical properties, by Kelvin-probe force microscopy (KPFM) and frequency dependent capacitance-voltage (C-V-f) measurements, to get information on the surface potential and the energy of interface state density (Nss). While similar values of surface potential were found for the Mo2C and Mo/4H−SiC contacts, the higher level of Nss in the Mo2C/4H−SiC can explain the reduction of the Schottky barrier in this contact compared to a Mo/4H−SiC one.

Experimental Details

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The starting material for this study consisted in a 4H−SiC epitaxial layer with a n-type doping concentration of 1.5×1016 cm−3 grown onto a n+-doped substrate. Schottky diodes were fabricated starting from the deposition of a large-area back-side Ohmic contact by sputtering 100 nm-thick Ni layer, followed by a rapid thermal annealing (RTA) treatment in a furnace at 950∘C in N2 for 60 s [10]. Then, for the front-side Schottky contact, 100 nm -thick film was sputtered from a Mo2C target. The contact pads were defined by optical photolithography and lift-off processing steps. Rapid thermal annealing (RTA) treatments were carried out in a furnace for 10 min in N2 atmosphere at temperatures of 400∘C and 700∘C. For comparison, 80 nm -thick Mo/4H-SiC contacts were fabricated in the same manner. The electrical characteristics of a set of contacts were investigated by means of current-voltage (I-V) and capacitance-frequency-voltage (C-f-V) measurements in a KarlSuss MicroTec probe station equipped with a parameter analyzer. Kelvin Probe Force Microscopy (KPFM) measurements were carried out in PeakForce Tapping Mode Amplitude Modulation (AM)KPFM with a Dimension Icon system by Bruker. Silicon tips with a triangular geometry (nominal radius of 5 nm ) were employed to evaluate the variation of the surface potential of the contact.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

Firstly, we investigated the electrical characteristics under forward bias for a set of as-deposited, 400∘C and 700∘C annealed Mo2C/4H−SiC contacts. The related current density-voltage (J-V) curves are reported in Figs.1a, 1b and 1c, respectively.

[picture]

Fig. 1. Forward J−V curves of the a) as-deposited, b) 400∘C and c) 700∘C-annealed Mo2C/4H−SiC Schottky contacts.

Fig. 1. Forward J − V curves of the a) as-deposited, b) 400 ∘ C and c) 700 ∘ C -annealed M o 2 C / 4 H − S i C Schottky contacts.

The J-V characteristics exhibited good reproducibility, with the 700∘C-annealed sample showing a more extended linear region. The Schottky barrier height values, extrapolated from a fit of the linear part of the J-V curves, according to the thermionic emission (TE) model [11], are reported in Fig.2. As one can see, the as-deposited and 400∘C-annealed Mo2C/4H-SiC contact showed similar barrier height, with ΦB=0.94±0.02eV and ΦB=0.96±0.04eV, respectively. After thermal treatment at 700∘C, the barrier increased up to 1.07±0.04eV.

To understand the origin of the barrier reduction, we investigated the surface potential, which is linked to the work-function of the contact material. The surface potential mapping was performed by KPFM, carried out on both the Mo (reference) and Mo2C contacts. Specifically, 4H−SiC was employed as a reference to evaluate the variation on the surface potential of the contact material with respect to the semiconductor. Figs. 3a and 3b show the histograms of surface potential values extracted from the KPFM maps.

[picture]

Fig. 2. Schottky barrier height ( ΦB ) for the as-deposited and annealed Mo2C/4H−SiC contacts.

Fig. 2. Schottky barrier height ( Φ B ) for the as-deposited and annealed M o 2 C / 4 H − S i C contacts.

[picture]

Fig. 3. Histograms of the KPFM surface potential values associated to the maps for a) Mo/4H−SiC and b) Mo2C/4H−SiC contacts. 4H−SiC was taken as reference.

Fig. 3. Histograms of the KPFM surface potential values associated to the maps for a) M o / 4 H − S i C and b) M o 2 C / 4 H − S i C contacts. 4 H − S i C was taken as reference.

These surface potential distributions were fitted by Gaussian functions to derive the peak corresponding to the average surface potential values. Noteworthy, a surface potential variation of 0.16 eV was observed for Mo and 4H−SiC while is of 0.19 eV for Mo2C and 4H−SiC one. This corresponds to very similar surface potential values for Mo and Mo2C, differing by only ~0.03eV. Such a small variation alone cannot account for the difference observed in the Schottky barrier height between the two contacts. Hence, we extended the investigation to the interface electrical properties by a C-f-V study [12]. This technique enables the evaluation of the density of interface states (Nss) in Schottky diodes from capacitance measurements as function of the frequency (f) and forward bias (V). In fact, at low frequencies, the measured capacitance contains contributions from both the spacecharge region (Csc) and the interface states (Css), whereas at high frequencies only the space-charge capacitance contributes [13]. This can be expressed according to the following eqs. 1 and 2, where the total capacitance is given by a parallel of Csc and Css at low frequencies whereas the total capacitance can be approximated to only Csc at high frequencies [14]:

Clf=CSC+CSS( at low frequency )Chf≈CsC( at high frequency )

(1)(2)

From the difference between the two cases, CSS is derived. This term is proportional to the NSS, as given in eq. 3 [15]:

CSS=qANSSarctan(ωτ)ωτ(3)

with ω=2πf (f varying between 1 kHz and 1 MHz ), q the elementary charge, A the device area, and τ a time parameter depending on the thermal velocity of carriers, the cross-section of interface states and the doping concentration.

The NSS derived according to eq.3, results of 2.2×1010eV−1 cm−2 for Mo/4H−SiC contact and of 9.5×1013eV−1 cm−2 for Mo2C/4H−SiC. This high difference in the density of interface state can be at the base of the reduction of the Schottky barrier occurred in Mo2C contacts.

[picture]

Fig. 4. C−f−V characteristics for 700∘C annealed Mo and Mo2C/4H−SiC contacts.

Fig. 4. C − f − V characteristics for 700 ∘ C annealed Mo and M o 2 C / 4 H − S i C contacts.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

The electrical characterization of Mo2C/4H−SiC Schottky contacts demonstrated a Schottky barrier height around 0.95 eV for the as-deposited and 400∘C-annealed contact and of 1.07 eV for the 700∘C-annealed contact, the latter exhibiting a more extended linear region. The Mo2C/4H−SiC contact properties were compared with those of a reference Mo/4H−SiC contact, fabricated under same processing conditions, with surface and interface electrical properties investigated by Kelvinprobe force microscopy and capacitance-frequency-voltage study, respectively. The study indicated comparable surface potential values (derived by Kelvin-probe force microscopy) for the two systems, whereas a higher density of interface state was extracted for the Mo2C/4H−SiC contact. This latter finding accounts for the reduction in Schottky barrier height observed in the Mo2C/4H−Si contact.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

This work was carried out in the framework of the MicroTech_for_Green project, funded by Ministero delle Imprese e del Made in Italy (MIMIT) under IPCEI Microelettronica 2, using the facilities of the Italian Infrastructure Beyond-Nano. The authors S.E.P. and V.V, would like to thank the European Union (NextGeneration EU), through the MUR-PNRR project infrastructure for Energy Transition and Circular Economy @ EuroNanoLab iENTRANCE@ENL (IR00000027) for financial support.

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The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 81-87

doi: 10.4028/p-LlTen7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-15

Revised:
2025-12-22

Accepted:
2026-02-26

Online:
2026-05-20

NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

Paolo Badalà 1,a*, Corrado Bongiorno 2, b, Salvatore Sanzaro 1,c, Anna Bassi 1, d, Simone Rascunà 1,e, Gabriele Bellocchi 1,f, Massimo Boscaglia 1, g, Antonino La Magna 2, h and Alessandra Alberti 2,i

1 STMicroelectronics, Zona Industriale Stradale Primosole, 50-95121 Catania, Italy

2 CNR-IMM, Zona Industriale Strada VIII, 5-95121 Catania, Italy

a * paolo.badala@st.com, b  corrado.bongiorno@imm.cnr.it, c  salvatore.sanzaro@st.com, d  anna.bassi@st.com, e  simone.rascuna@st.com, f  gabriele.bellocchi@st.com, ¹  massimo.boscaglia@st.com, h  antonino.lamagna@imm.cnr.it, ialessandra.alberti@imm.cnr.it 

Keywords: laser annealing, ohmic contact, silicide, 4H-SiC.

Abstract

Laser annealing is considered an enabling process for a new generation of SiC power devices, since it allows the formation of ohmic contacts on very thin wafers, significantly reducing their total ON resistance. Ni silicide and Ti silicide ohmic contacts have been widely investigated and reported in literature, exploring in detail the role of laser features, metal thickness and thinning process. Nevertheless, adding a small amount of Si to the contact layer could represent an opportunity to increase process options. In this work, a NiSi alloy has been used as a contact metal to study the role of the addition of Si to Ni in the reaction process under UV laser irradiation. Morphological and structural properties of the reacted layers have been investigated by means of Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD) analyses. The electrical characterization of reacted contacts has been performed by measuring their Sheet Resistance ( Rs ) by Four Point Probe (FPP) method and, at device level, by measuring the forward voltage drop ( Vf ) of Schottky Barrier Diodes (SBDs) fabricated on 150 mm -diameter 4H−SiC wafers. Furthermore, a comparison has been made between Ni and NiSi alloy under the same irradiation conditions. It has been found that adding Si to Ni in the contact metal layer moves the silicide reaction forward, driving the strong relationship observed between structural, morphological and electrical properties of the reacted contacts.

Introduction

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Silicon carbide has attracted increasing attention in recent years for power electronics and detectors applications, thanks to its excellent physical properties, which allow for obtaining higher breakdown voltage, higher switching frequency, lower resistance, higher heat dissipation, and smaller devices [1-6]. Laser annealing process has been widely adopted in silicon carbide device fabrication, for dopant activation [7,8] and ohmic contact formation [9, 10]. In particular, among the alternative processes to Rapid Thermal Annealing (RTA) for silicide formation [11-13], laser annealing, thanks to its limited heat diffusion, is the most suitable one for the formation of ohmic contact on thin wafers, therefore allowing to significantly reduce the total ON resistance of SiC power devices [14]. Ohmic contacts on SiC based on Ti silicide [15, 16] and Ni silicide [17-28] have been already deeply investigated, and the reaction process has been also studied in detail from a theoretical point of view [29-31]. Nevertheless, the behavior of a NiSi alloy as a contact material under laser irradiation has not completely described and understood so far. In this work, the role played by the addition of a small amount of Si to Ni of the contact layer, in the ohmic contact formation by means of excimer UV laser annealing, has been investigated. A comparison between Ni and NiSi alloy under the same irradiation conditions is reported.

Experimental Setup

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Schottky Barrier Diode (SBD) devices have been fabricated on 150 mm -diameter 4H-SiC wafers, thinned at 180μ m. A 100 nm NiSi alloy layer has been deposited by sputtering in Ar ambient, at a base pressure of 1×10−3mbar, on the ground face of the wafers. Wafers have then been irradiated on the backside by using an excimer UV laser, with pulse duration of 160 ns and wavelength of 308 nm . Structural properties of the reacted layers have been characterized by means of X-Ray Diffraction (XRD) analyses, using a Bruker AXS D8 DISCOVER diffractometer, working with a Cu−Kα source and a thin film attachment. Morphology of reacted layers has been investigated by means of Transmission Electron Microscopy (TEM) analyses, using a JEOL-JEM microscope working at 200 keV . The electrical characterization of reacted contacts has been performed by measuring their Sheet Resistance ( Rs ) by Four Point Probe (FPP) method and, at device level, by measuring the forward voltage drop ( Vf ) at nominal current of Schottky Barrier Diodes (SBDs), by using a semiconductor device parameter analyzer (Agilent B1500A) and a high-power curve tracer (Sony Tektronix 371A).

Results and Discussion

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It has been reported [17] that the typical Rs curve, as a function of laser fluence, shows an increase of Rs values for low laser fluences, due to the initial intermixing between metal layer and Si , and then a rapid drop of Rs to a final plateau, above a threshold fluence. In particular, the value of threshold fluence depends on contact material and its thickness, number of laser pulses, and SiC roughness.

[picture]

Fig. 1. Comparison between threshold fluence for the Rs drop of Ni and NiSi alloy, as a function of number of laser pulses. Fixed the laser conditions, the threshold fluence of NiSi alloy is lower than that of Ni .

Fig. 1. Comparison between threshold fluence for the R s drop of Ni and NiSi alloy, as a function of number of laser pulses. Fixed the laser conditions, the threshold fluence of NiSi alloy is lower than that of Ni .

As shown in Fig. 1, the threshold fluence at which the Rs drop is observed decreases with the increasing number of laser pulses, both for Ni and NiSi alloy, but the threshold fluence of NiSi alloy is lower than that of Ni , at the same number of laser pulses. This could mean that, fixed the laser annealing conditions, the addition of Si to Ni moves the reaction forward.

[picture]

Fig. 2. Forward voltage drop ( Vf ) at nominal current ( I0 ) of Schottky Barrier diodes annealed at 3.8 J/cm2 with two pulses. As a reference, the Vf of diodes treated with RTA is reported.

Fig. 2. Forward voltage drop ( V f ) at nominal current ( I 0 ) of Schottky Barrier diodes annealed at 3.8 J / c m 2 with two pulses. As a reference, the V f of diodes treated with RTA is reported.

This hypothesis is confirmed by the measurement of Vf of SB diodes. As reported in Fig. 2, in fact, NiSi sample annealed at 3.8 J/cm2 with two pulses shows a Vf significantly lower than the Ni sample annealed at the same conditions, and even lower than that of a Ni sample treated by Rapid Thermal Annealing (RTA), reported as a reference.

[picture]

Fig. 3. XRD pattern, acquired in grazing incidence configuration, of NiSi alloy sample after laser annealing at 3.8 J/cm2, two pulses, and corresponding deconvoluted component peaks.

Fig. 3. XRD pattern, acquired in grazing incidence configuration, of NiSi alloy sample after laser annealing at 3.8 J / c m 2 , two pulses, and corresponding deconvoluted component peaks.

Structural properties of Ni and NiSi alloy samples, annealed at 3.8 J/cm2 with two pulses, have been characterized by XRD, performed in grazing incidence configuration. Fig. 3 shows the XRD pattern of the annealed NiSi sample and the deconvoluted contributions of the main peaks. The extracted quantitative fractions reveal the predominant presence of Ni3Si2 and NiSi phases, with lower contribution of Ni2Si and NiSi2.

Fig. 4. Comparison between XRD patterns, acquired in grazing incidence configuration, of Ni and NiSi alloy samples annealed at 3.8 J/cm2, two pulses.

The same approach has been adopted to characterize the annealed Ni sample, revealing the presence of Ni3Si,Ni31Si12,Ni2Si and Ni3Si2 phases. The comparison between NiSi alloy and Ni annealed samples, reported in Fig. 4, shows the presence of Si-rich phases in NiSi alloy sample, confirming that adding Si to Ni moves the reaction ahead, fixed the laser annealing process parameters. In fact, the Ni−Si reaction starts at the interface between Ni and SiC and moves from Ni− rich phases towards Si-rich ones. As the silicide reaction moves forward, the electrical behaviour of ohmic contact improves, as shown by Sheet Resistance and Forward Voltage measurements reported in Fig. 1 and Fig. 2.

[picture]

Fig. 5. Cross sectional TEM analysis of NiSi alloy sample annealed at 3.8 J/cm2, two pulses. The reacted material shows an interfacial layer, a Ni -Si network region, and a graphite layer on top (a). HR-TEM micrographs show the presence of NiSi2 regions and C -clusters in the Ni -Si network area (b), and the presence of stacking faults in the interfacial layer with 4H−SiC (c).

Fig. 5. Cross sectional TEM analysis of NiSi alloy sample annealed at 3.8 J / c m 2 , two pulses. The reacted material shows an interfacial layer, a Ni -Si network region, and a graphite layer on top (a). HR-TEM micrographs show the presence of N i S i 2 regions and C -clusters in the Ni -Si network area (b), and the presence of stacking faults in the interfacial layer with 4 H − S i C (c).

The morphology of NiSi alloy sample annealed at 3.8 J/cm2 with two pulses has been investigated by cross-sectional TEM analyses (Fig. 5). As visible in Fig. 5a, the reacted material shows an interfacial layer, a Ni-Si network region, and a graphite layer on top. NiSi2 regions and C -clusters are included in the Ni-Si network area, as shown by cross-sectional High-Resolution TEM micrograph reported in Fig. 5b. The presence of stacking faults in the interfacial layer with 4H−SiC has been revealed by HR-TEM (Fig. 5c).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

The silicide reaction between a NiSi alloy and 4H−SiC under excimer UV laser annealing has been investigated, with the aim of finding an alternative to Ni and Ti for the ohmic contact formation on thin SiC wafers, enlarging the range of process options. It has been found that, fixed the laser annealing conditions, the addition of Si to Ni in the contact metal layer moves the silicide reaction forward. Moreover, a strong relationship has been observed between the electrical behavior of the annealed contacts and the structural and morphological properties of the reacted layers. Exploring the role of Si content in the NiSi alloy, by changing the composition of starting material, could shed additional light on the reaction process. NiSi alloy could represent a valuable opportunity for the formation of ohmic contacts on SiC by laser annealing.

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The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

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S. Rascunà, P. Badalà, C. Tringali, C. Bongiorno, E. Smecca, A. Alberti, S. Di Franco, F. Giannazzo, G. Greco, F. Roccaforte, M. Saggio, Morphological and electrical properties of Nickel based Ohmic contacts formed by laser annealing process on n-type 4H-SiC, Materials Science in Semiconductor Processing, 97 (2019) 62-66.

C. Berger, D. Alquier, M. Bah, J.F. Michaud, Electrical, morphological and structural properties of Ti ohmic contacts formed on n-type by laser thermal annealing, Materials Science in Semiconductor Processing, 151 (2022) 106983.

C. Berger, D. Alquier, J.F. Michaud, Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC, Materials Science Forum, 1062 (2022) 219-223.

P. Badalà, S. Rascunà, B. Cafra, A. Bassi, E. Smecca, M. Zimbone, C. Bongiorno, C. Calabretta, F. La Via, F. Roccaforte, M. Saggio, G. Franco, A. Messina, A. La Magna, A. Alberti, interaction and silicide formation under excimer laser annealing for ohmic contact, Materialia, 9 (2020) 100528.

Z. Zhou, W. He, Z. Zhang, J. Sun, A. Schöner, Z. Zheng, Characteristics of Ni-based ohmic contacts on n-type 4H-SiC using different annealing methods, Nanotechnology and Precision Engineering, 4 (2021) 013006.

P. Badalà, E. Smecca, S. Rascunà, C. Bongiorno, E. Carria, A. Bassi, G. Bellocchi, S. Castorina, C. Tringali, A. La Magna, A. Alberti, Structural and electrical characterization of Ni-based ohmic contacts on 4H-SiC formed by solid-state laser annealing, Materials Science Forum, 1062 (2022) 417-421.

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P. Badalà, I. Deretzis, S. Sanzaro, F.M. Pennisi, C. Bongiorno, G. Fisicaro, S. Rascunà, G. Bellocchi, A. Bassi, M. Boscaglia, D. Pagano, P. Vasquez, M. Enachescu, A. Alberti, A. La Magna, Ni-Silicide Ohmic Contacts on Formed by Multi Pulse Excimer Laser Annealing, Solid State Phenomena, 344 (2023) 15-22.

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P. Badalà, C. Bongiorno, P. Fiorenza, G. Bellocchi, E. Smecca, M. Vivona, M. Zignale, M. Massimino, I. Deretzis, S. Rascunà, M. Frazzica, M. Boscaglia, F. Roccaforte, A. La Magna, A. Alberti, Electrical and structural properties of ohmic contacts of SiC diodes fabricated on thin wafers, Solid State Phenomena, 359 (2024) 97-103.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 89-96

doi: 10.4028/p-U2bkIl

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-23

Revised:
2026-01-07

Accepted:
2026-01-31

Online:
2026-05-20

Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1192.89.pdf

Maximilian Ley 1,a*, Julian Kauth 1,b, Mathias Rommel 1,c, Björn Fischer 2,d, Alexander May 1,e, and Jörg Schulze 1,3,f

1 Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Schottkystraße 10, 91058 Erlangen, Germany

2 Infineon Technologies AG, Am Campeon 1-15, 85579 Neubiberg, Germany

3 Chair of Electron Devices, Friedrich-Alexander-Universität Erlangen-Nürnberg, Cauerstraße 6, 91058 Erlangen, Germany

a  maximilian.ley@iisb.fraunhofer.de, b  julian.kauth@iisb.fraunhofer.de, c  mathias.rommel@iisb.fraunhofer.de, d  bjoern.fischer@infineon.com, e  alexander.may@iisb.fraunhofer.de, f  joerg.schulze@fau.de

Keywords: TLM Test Structure, Contact Length, TCAD, 4H-SiC, Contact end Resistance, Sheet Resistance, Specific Contact Resistivity, Transfer Length, Simulation Analysis, Ohmic Contact

Abstract

Accurate characterization of low-resistance ohmic contacts on 4H−SiC is crucial for device development, but is complicated by the limitations of the standard Transfer Length Method (TLM). TLM test structures are widely used for extracting the specific contact resistivity ( ρC ) between metal and semiconductor layers, as well as the sheet resistance of doped layers. The contact formation process itself, particularly the annealing step, modifies the SiC layer under the contact. This results in a sheet resistance below the contact ( RSK ) that deviates from the sheet resistance of interest between the contacts ( RSH ), which invalidates a key assumption of the standard TLM evaluation of a constant RSH throughout the whole TLM test structure. This study uses 2D TCAD simulation of TLM test structures to investigate the influence of the contact length L, while using an advanced evaluation method for extracting ρC with the help of a third contact. Consequently, it is necessary to measure the contact end resistance RCE, which is derived from the potential at the end of the TLM contact. The findings provide a deeper understanding of the TLM technique's robustness and offer valuable guidelines for optimizing TLM test structures to ensure accurate characterization of ohmic contacts on 4H−SiC.

Introduction

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In recent years, 4 H -Silicon Carbide (4H−SiC) has emerged as a leading semiconductor material for high-power, high-frequency, and high-temperature electronic devices, owing to its superior material properties, including a wide bandgap, high critical electric field, and excellent thermal conductivity [1]. The overall performance and energy efficiency of these devices are critically dependent on the quality of the metal-semiconductor interface, specifically the formation of low-resistance ohmic contacts. However, achieving such contacts on 4H−SiC is challenging compared to silicon, primarily due to three factors: Its wide bandgap creates a large Schottky barrier, its chemical inertness complicates surface preparation, and there is a lack of metals with suitable work functions [2]. To characterize and optimize ohmic contacts, the Transfer Length Method (TLM) has become an industry-standard technique [2]. The standard TLM evaluation allows for the extraction of the specific contact resistivity (ρC) and the sheet resistance ( RSH ) of the semiconductor layer between the contacts [3]. The accuracy of these extracted parameters is highly dependent on the design of the TLM test structure and the assumptions made during the analysis [4,2].
This work presents a systematic simulation-based study using TCAD Sentaurus [5] to investigate and quantify the impact of the contact length L on the extraction of contact front resistance RCF and contact end resistance RCE in 4H-SiC TLM test structures. Scenarios where RSK and RSH differ are analyzed, exploring the conditions where the regular TLM analysis comes to its limits.

Standard TLM Evaluation and Parameter Extraction

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According to the standard TLM evaluation, the total resistance RT measured between two adjacent ohmic contacts is linearly dependent on the spacing di between them, as described by the following equation [4]:

RT=(RSH/Z)d+2RCF(1)

Here, RCF is the contact resistance, RSH is the sheet resistance of the doped semiconductor layer, and Z is the contact width of the TLM test structure. The standard model relies on the assumption of a uniform sheet resistance ( RSH=RSK ) [6, 7]. In this work, ideal material properties and interfaces are assumed in the simulation, resulting in a linear relationship between RT and di (i.e., with a coefficient of determination R2=1 ), this criterion is not always matched in real measurements. The analytical procedure begins by determining RT from simulated current-voltage (I-V) characteristics for a range of different contact spacings di. The resistance values are then plotted as a function of d, as shown in Fig. 1. A linear regression applied to this data allows for the extraction of key parameters: The slope of the fit yields RSH/Z, the y -axis intercept corresponds to 2RCF, and the x -axis intercept corresponds to −2LT.LT is the distance after which the potential under the contact drops to 1/e, i.e., it describes

[picture]

Fig. 1: Graphical representation of the standard TLM evaluation. The total resistance RT is plotted against the contact spacing d. The sheet resistance RSH is extracted from the slope of the linear fit, while the contact resistance RCF and transfer length LT are determined from the y - and x -axis intercepts, respectively.

Fig. 1. Graphical representation of the standard TLM evaluation. The total resistance R T is plotted against the contact spacing d . The sheet resistance R S H is extracted from the slope of the linear fit, while the contact resistance R C F and transfer length L T are determined from the y - and x -axis intercepts, respectively.

the length of the contact that mainly contributes to the current flow and is calculated by the following equation:

LT=RCF·Z/RSH(2)

The specific contact resistivity ρC, which is a measure of the contact quality independent on geometry, can be calculated either through the coth, which considers the potential distribution under the contact, or by an approximation, which is only valid for long contacts (L≫LT) [4]:

ρC=RCF·LT·Z/coth(L/LT)ρC=RSH·LT2(3)

TLM Evaluation with Contact End Resistance

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To account for the discrepancy between RSK and RSH, the evaluation can be extended by additionally measuring the contact end resistance RCE[8].RCE describes the resistance at the trailing edge of the

TLM contact. The contact front resistance RCF and the contact end resistance RCE can be derived as [4]:

RCF=V(x=0)I(x=0)=RSKρCZcoth(L/LTk)=ρCLTkZcoth(L/LTk)RCE=V(x=L)I(x=0)=VCEI=RSKρCZ1sinh(L/LTk)=ρCLTkZ1sinh(L/LTk)

(4)(5)

Here, L is the contact length, and LTk is the transfer length defined as LTk=ρcRSK. Note that LTk is the true transfer length under the contact, which may differ from the apparent transfer length LT extracted from the standard TLM plot, as LT is derived assuming RSK=RSH. The ratio of RCE to RCF depends only on L relative to LTk :

RCERCF=1cosh(L/LTk)(6)

This relationship, in combination with Eq. 4 and 5, allows the determination of LTk,ρC, and RSK.LTk can be calculated by rearranging the resistance ratio equation:

LTk=Larcosh(RCF/RCE)(7)

With LTk known, ρC is calculated without the implicit assumption of RSK=RSH, which does not account for a differing RSK :

ρc=LTk·Z·RCEsinh(L/LTk)(8)

Finally, RSK is determined using the definition of LTk :

RSK=ρCLTk2(9)

The advanced analysis with RCE enables a more accurate determination of ρC and an insight into the impact of the contact fabrication on the underlying semiconductor layer.

Simulation Methodology

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A three-contact TLM test structure is investigated in 2D using Synopsys TCAD Sentaurus, using standard physics models for 4H−SiC, including models for doping-dependent mobility and incomplete ionization of dopants. The simulated structure, depicted in Fig. 2, consists of a p-type doped layer on a lightly doped n -type epitaxial layer with a background concentration of 1×1015 cm−3. The doping of the p-type implanted layer is fixed to a concentration of 1×1019 cm−3. The specific contact resistivity is set to ρC=0.5 mΩ cm2. To investigate the impact of the contact processing, the sheet resistance directly under the contacts RSK  was independently controlled by varying the net active doping concentration within the top 100 nm of this implanted layer. This setup allows for a systematic study of the effects of a non-uniform sheet resistance ( RSK≠RSH ). RCE is determined by measuring the potential at contact C 3 . This potential is identical to the potential of the trailing edge ( x=L ) of the currentcarrying contact C2 relative to the leading edge ( x=0 ) of C2, where the current injection takes place. Contact C3 is modeled as a floating voltage probe by constraining its current to zero. The resistance value of RCE is independent on the spacing di between the contacts, but strongly dependent on L and the sheet resistance of the layers under the contact. Current-Voltage (I-V) characteristics (Fig. 3) are simulated across a range of contact lengths L and contact spacings di by sweeping the voltage and measuring the current between the contacts C 1 and C 2 . This approach addresses a significant limitation of the standard TLM evaluation: The assumption of a uniform sheet resistance ( RSH=RSK ), which is often invalid in practice. For instance, forming nickel silicide ( NixSiy ) contacts to n -type SiC

[picture]

Fig. 2: Cross-section and top view schematic of the simulated device for a TLM test structure with a third contact, which serves as a voltage probe.

Fig. 2. Cross-section and top view schematic of the simulated device for a TLM test structure with a third contact, which serves as a voltage probe.

[picture]

Fig. 3: I-V characteristic for two different di and L for determining the resistance values for the standard TLM evaluation (left) and RCE  (right).

Fig. 3. I-V characteristic for two different d i and L for determining the resistance values for the standard TLM evaluation (left) and R CE (right).

selectively consumes silicon [9], while forming TiAl-based contacts to p-type SiC consumes SiC to form TixSiCy[10]. Both processes alter the stoichiometry and doping profile, leading to a discrepancy ( RSK≠RSH ) that can cause errors in the extracted ρC.
The measurement of RCE enables the separation of the sheet resistances RSK from RSH, leading to a more accurate determination of ρC[11]. However, the ability to accurately measure RCE depends on the geometric design. The contact length L must be carefully chosen relative to the contact length [3] as shown in the simulation data presented in the following sections. The simulation results are normalized to a standard device width of Z=1μ m, which corresponds to the contact width. RSK is controlled independently of RSH  by defining a separate net doping concentration in that region. This idealized approach allows for a direct investigation of the impact of the RSK/RSH ratio on the extracted parameters, decoupled from the complex and process-specific physics of contact formation.
The simulation procedure is designed to extract RCF and RCE. To determine RCF, the total resistance RT between adjacent contacts is simulated for several structures with systematically varied contact
spacings di.RCF is then extracted from the y -intercept of a linear fit of RT versus d and RSH from the slope of the same plot, consistent with the standard TLM analysis:

RT=VCF(d)/I(d)(10)

To determine RCE, the current I between C 1 and C 2 is measured, and the potential difference between the current-carrying contact C 2 and the floating contact C 3 is recorded. RCE is then calculated by:

RCE=VCE/I(11)

The entire procedure is repeated for different L and RSK/RSH to analyze their combined influence on the extracted parameters.

Discussion of Simulation Results

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Fig. 4 compares the ideal case ( RSK=RSH ) with a uniform sheet resistance across the TLM test structure with a more realistic scenario where the sheet resistance under the contact is higher ( RSK>RSH ). The specific contact resistivity ρC and sheet resistance values extracted from these linear fits show

[picture]

Fig. 4: Standard TLM evaluation plot: R is shown in dependence on di for different contact lengths L, for L=5μ m also the case of RSK>RSH is shown.

Fig. 4. Standard TLM evaluation plot: R is shown in dependence on d i for different contact lengths L , for L = 5 μ m also the case of R S K > R S H is shown.

good agreement with the input parameters of the simulation for the ideal case, confirming the validity of the model and the extraction methodology.
When RSK>RSH, the total measured resistance increases, resulting in a significantly larger yintercept. A standard TLM analysis would erroneously attribute this entire increase to a higher RCF, leading to an inaccurate calculation of the specific contact resistivity ρC. These simulations underscore the necessity of measuring RCE to correctly separate the different resistance contributions. As seen in Fig. 4, using a contact length L shorter than LT results in a higher extracted RCF. Meanwhile, increasing L reduces the contact resistance only up to a certain limit, with similar y -axis intercepts observed for L=5μ m and L=20μ m in Fig. 4).

Impact of contact length L on extracted resistances. L has a significant effect on the extracted values of RCE. This relationship is illustrated in Fig. 5, which shows the simulated resistances as a function of L. The data reveals a design trade-off for accurate parameter extraction. While RCF remains largely independent of the contact length for L>LT,RCE shows a strong dependence.

For short contacts ( L≈LT ), RCE is easily measurable, but becomes sensitive to manufacturing variations in L. In contrast, for long contacts (L≫LT),RCE diminishes exponentially and approaches zero. Thus, a correct extraction of RCE is not possible due to measurement limitations. The observed trend

[picture]

Fig. 5: Dependence of RCF and RCE on the contact length L shown for different RSH and RSK.RCE is approaching zero and thus not measurable for large L. Meanwhile, RCF  shows an asymptotic approach to a fixed value for large L. The distance between contact C2 and C3 is equal to the one between C1 and C2 in this simulation, the value of RCE is independent of the spacing di.

Fig. 5. Dependence of R C F and R C E on the contact length L shown for different R S H and R S K . R C E is approaching zero and thus not measurable for large L . Meanwhile, R CF shows an asymptotic approach to a fixed value for large L . The distance between contact C2 and C3 is equal to the one between C1 and C2 in this simulation, the value of R C E is independent of the spacing d i .

in Fig. 5 reveals a fundamental trade-off. For L≫LT the current transfer is essentially completed well before the physical end of the contact. Consequently, VCE (and thus RCE ) becomes vanishingly small. In an experimental setting, this small voltage would be lost in the measurement noise, making an accurate extraction of RCE  impossible. Without a reliable RCE  value, the separation of RSK  from RSH  is not possible. For short contacts, small absolute variations represent large percentual variation in L, making the extracted values of RCE highly susceptible to manufacturing tolerances, leading to poor statistical reproducibility across a wafer. Consequently, an effective design requires a L comparable to the contact's specific LT. This is a critical consideration for 4H−SiC, where LT can vary significantly (e.g., LT≈0.5μ m for contacts to n-type SiC vs. LT≈4μ m for contacts to p-type SiC - this data was extracted by using the standard TLM evaluation) [12].
Comparison between ρC values from both analyses. To quantify the error introduced by the standard TLM evaluation, we compared ρC obtained from the two different sets of equations explained in the previous section: For the standard analysis, ρC is calculated using the standard TLM evaluation with and without the approximation for the coth according to Eq. 3, which assumes a uniform sheet resistance ( RSK=RSH ). In contrast, for the TLM analysis with RCE,ρC is calculated using the more comprehensive model that incorporates the measured RCE, as described in Eq. 8.
The results are plotted in Fig. 6. For the more realistic scenario with RSK>RSH, the standard analysis significantly overestimates the true ρC (grey dotted line). In contrast, the TLM analysis with RCE, which accounts for the non-uniformity, extracts ρC more accurately. This result confirms that the RCE measurement is essential for the accurate characterization of real ohmic contacts. For the case of RSK=RSH, both methods yield similar results as expected.

[picture]

Fig. 6: ρC determination with different evaluation routines are shown. The ρC determination with RCE is more accurate for RSK>RSH, while there is no significant difference for the ideal case of RSK=RSH.

Fig. 6. ρ C determination with different evaluation routines are shown. The ρ C determination with R C E is more accurate for R S K > R S H , while there is no significant difference for the ideal case of R S K = R S H .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1192.89.pdf

Through 2D TCAD simulations, this work has quantitatively demonstrated that the contact length L is a critical design parameter for the accurate characterization of 4H−SiC ohmic contacts using RCE, i.e., the determination of ρC and the decoupling of RSK and RSH. This implies that TLM test structures must be carefully designed: L must be within the range of the transfer length. This makes L a critical design parameter, as LT is not a fixed value. Contacts to n - and p -type 4 H -SiC require different L, as their respective processing conditions and contact schemes yield significantly different transfer lengths LT. LT strongly depends on the contact material and the semiconductor doping. Therefore, an optimized TLM design for different contacts and materials is required. Measuring RCE  is essential for correctly determining the specific contact resistivity ( ρC ) in realistic scenarios where the sheet resistance is nonuniform ( RSK≠RSH ). Adopting these guidelines will enable the design of more accurate TLM test structures.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.89.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/interface-dielectrics-and-ohmic-contact-in-sic-power-devices/978-3-0364-3129-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 97-103

doi: 10.4028/p-t0ptSI

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-26

Accepted:
2026-02-26

Online:
2026-05-20

Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1192.97.pdf

M. Kobayashi 1,a*, S. Ishikawa 2,b, Y. Higashi 2,c, H. Sezaki 3,d, M. Okamoto 2,e, S. Harada 2,f and K. Kojima 2, g

1 Sumitomo Metal Mining Co., Ltd., 5-11-3, Shimbashi, Minato-ku, Tokyo 105-0004, Japan

2 Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki 305-8568, Japan

3 PHENITEC SEMICONDUCTOR Corp., 6833, Kinoko-cho, Ibara, Okayama 715-8602, Japan

a*motoki.kobayashi.x2@smm-g.com, b  ishikawa-seiji@aist.go.jp, chigashi-phenitec@aist.go.jp, d  hiroshi-sezaki@phenitec.co.jp, e  mitsuo-okamoto@aist.go.jp, f  s-harada@aist.go.jp, 9kazu-kojima@aist.go.jp

Keywords: bonded substrate, low-resistivity polycrystalline layer, backside contact resistance, SIMS, hall measurement, circular TLM, threshold resistivity.

Abstract

In this study, 4H−SiC bonded substrates (bonded- SiC ) with an average resistivity of 2.431.5 mΩ· cm were prepared, and attention has been directed toward the relationship between the resistivity of bonded- SiC and the contact resistance at the backside where metal Ti/Ni was applied. A circular transmission line model (cTLM) was used to accurately measure the backside contact resistance. A linear correlation was found between ρC and the resistivity of bonded-SiCs at room temperature (RT). This result indicates the existence of a threshold resistivity at which the specific contact resistance ( ρC ) in the range of 2.2×10−6 to 1.5×10−5Ω· cm2 can be achieved without contact annealing; it also indicates that the temperature dependence of ρC between 17.4 and 34.4 mΩ· cm of the resistivity on bonded-SiCs is eliminated. This phenomenon can occur because ρC is dominated by tunneling current above the nitrogen concentration at the threshold resistivity, which is driven by the high nitrogen concentration and sufficient carrier activation in the polycrystalline portion (polycrystalline layer) of bonded-SiCs. These are important properties resulting from a polycrystalline layer with a 3C structure in bonded-SiC.

Introduction

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The 4H−SiC bonded- SiC ( SiCkrestTM ) consists of a thin monocrystalline 4H−SiC layer with a thickness of less than 1μ m, which is bonded to an n-type low-resistivity polycrystalline 3C-SiC substrate via surface-activated bonding. Fig. 1 shows (a) the photogram and (b) the schematic structure of SiCkrest TM. Some features of this substrate, for example, no unstable interlayer at bonded interface, which is shown in this cross-sectional transmission electron microscope (TEM) image, enables to apply various high temperature process of SiC . And the polycrystalline layer exhibits a low resistivity of under 10 mΩ· cm, which is significantly lower than that of the 4H−SiC monocrystalline substrate. This hybrid structure can be applied to the same epitaxial growth and device processes as conventional 4H−SiC bulk substrates [1,4]. In addition, compared with traditional 4H-SiC bulk substrates, it has reduced on-state resistance [1] and suppressed forward bias degradation in PiN diodes [2, 3] and a significant decrease in switching loss within the body-diode of MOSFETs [4].

In a previous study, this low-resistivity bonded-SiC not only reduced the on-resistance of SBD but also provided a low-resistance backside contact without the need for contact annealing and reduced temperature dependence [5]. However, the effect of resistivity on the necessity for contact annealing and the temperature dependence of ρC remains unclear because the resistivity of the bonded- SiCs tested in our previous research was only 10 mΩ· cm. In this study, bonded-SiCs with an average resistivity ranging from 2.4 to 31.5 mΩ· cm were prepared, and attention has been directed toward the relationship between the resistivity of the bonded- SiC and the contact resistance at the grinded
backside where metal Ti/Ni was applied. A cTLM was used to accurately measure the contact resistance. The relationship between the resistivity of the bonded- SiC and the backside contact resistance was clarified, and the mechanism underlying such a relationship was investigated.

[picture]

Fig. 1. (a) the photogram and (b) the schematic structure of SiCkrest TM and TEM image of bonded interface.

Fig. 1. (a) the photogram and (b) the schematic structure of SiCkrest T M and TEM image of bonded interface.

Experimental

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Fig. 2 presents the resistivity of the bonded-SiCs prepared in this study, which possessed an average resistivity ranging from 2.4 to 31.5 mΩ· cm compared with 10 mΩ· cm of the previous study. The polycrystalline layer of the bonded-SiCs with different resistivities was prepared by changing the nitrogen concentration through chemical vapor deposition. he resistivity of the bonded-SiCs was evaluated by using Eddy current measurements, whereas the nitrogen concentration in the polycrystalline layer was analyzed by using secondary-ion mass spectrometry (SIMS), and the carrier concentration was determined through Hall measurements, as shown in Fig. 3 (a). Fig. 3 (b) shows the measurement position within a substrate of the resistivity, nitrogen concentration, and carrier concentration. Resistivity and ρC were measured at 37 points across the entire surface and five points, respectively. Other analyses were performed at the same position (see Fig. 3 (b)) within the substrate for accurate comparison.

[picture]

Fig. 2. Resistivity of the bonded-SiCs prepared in this study.

Fig. 2. Resistivity of the bonded-SiCs prepared in this study.

[picture]

Fig. 3. (a) Evaluation items and methods for bonded- SiCs and polycrystalline layers.
(b) Measurement position within a substrate in this study.

Fig. 3. (a) Evaluation items and methods for bonded- SiCs and polycrystalline layers. (b) Measurement position within a substrate in this study.

cTLM was used to accurately measure the ρC [6, 7]. Fig. 4 illustrates (a) the process flow, (b) schematic structure, and (c) a split table of the cTLM samples. Three types of samples were tested in this study: (1) 4H−SiC monocrystalline substrate (mono- SiC ) with contact annealing, (2) bonded- SiCs with contact annealing, and (3) bonded-SiCs without contact annealing. I-V measurements were conducted using an Agilent 4156C, with the temperature controlled at RT, 75∘C,125∘C, and 175∘C using a hot plate.

[picture]

Fig. 4. (a) Process flow, (b) schematic image of the cTLM structure, and (c) split table for cTLM samples in this study.

Fig. 4. (a) Process flow, (b) schematic image of the cTLM structure, and (c) split table for cTLM samples in this study.

Results and Discussion

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Relationship between the resistivity of the bonded substrate and theρ𝐂

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Fig. 5 illustrates the relationship between the resistivity of bonded- SiCs and ρC at RT. Both measurements were conducted at the same locations on the substrate (center and four peripheral positions) to accurately investigate the correlation between resistivity and ρC. This result indicates a linear correlation between the resistivity of bonded-SiCs and ρC when the resistivity is 17.4 mΩ· cm or lower at RT. Even without contact annealing, at the lowest resistivity point in the substrate, the resistivity of the bonded-SiC is 1.9 mΩ· cm, whereas ρC is approximately 2.2×10−6Ω· cm2 at RT, which is equivalent to an ohmic contact to a mono-SiC using n+doping and high-temperature annealing [6]. Furthermore, as indicated by the symbols ■ and • for ρC without and with annealing, respectively, no difference in ρC between the two was observed for any resistivity values of
17.4 mΩ· cm or less. However, for resistivity values exceeding 17.4 mΩ· cm,ρC increased and varied across the substrate without contact annealing.

Fig. 6 shows the distribution of ρC within a substrate (Fig. 5 (a) and (b)). Bonded-SiCs with resistivities of approximately 17 and 34 mΩ· cm showed minimal variations in ρC with annealing. By contrast, bonded-SiCs with a resistivity near 34 mΩ· cm without annealing exhibited a significant variation in ρC similar to mono- SiC because of unstable silicide formation with a backside metal.

[picture]

Fig. 5. Relationship between the resistivity of bonded-SiCs and ρC at RT. The symbols ■ and • indicate ρ𝐂 without and with annealing, respectively.

Fig. 5. Relationship between the resistivity of bonded-SiCs and ρ C at RT. The symbols ■ and • indicate ρ 𝐂 without and with annealing, respectively.

Fig. 6. Distribution within a substrate of ρ𝐂 : (a) bonded-SiCs with a resistivity near 17 mΩ· cm, as plotted in Fig. 5 (a); (b) bonded-SiCs with a resistivity near 34 mΩ· cm, as plotted on Fig. 4 (b); and (c) mono-SiC.

Fig. 7 (a) shows the temperature dependence of ρC for mono- SiC with annealing and bonded- SiCs without annealing, as well as for bonded- SiCs as a function of resistivity. Mono- SiC showed a strong temperature dependence in the previous study [5], whereas bonded-SiCs exhibited no temperature dependence at 17.4 mΩ· cm or less and a weak negative temperature dependence at 34.4 mΩ· cm. Fig. 7 (b) presents the relationship between the resistivity of bonded-SiCs and ρC at RT,175∘C, and the difference ( ΔρC ) between RT and 175∘C. In mono- SiC and bonded- SiCs with a resistivity of 34.4 mΩ· cm or more, ΔρC indicates a negative value (negative temperature characteristic).

These results indicate the existence of a threshold resistivity at which the ρC in the range of 2.2×10−6 to 1.5×10−5Ω· cm2 can be achieved without contact annealing; it also indicates that the temperature dependence of ρC between 17.4 and 34.4 mΩ· cm is eliminated.

[picture]

Fig. 7. (a) Temperature dependence of ρ𝐂 of bonded- SiCs(𝐦) and mono- SiC(•). Resistivity varies from 2.6 to 34.4 mΩ· cm for the bonded-SiCs. (b) Relationship between the resistivity of bondedSiCs and ρC at RT, 175∘C, and the difference ( ΔρC ) between RT and 175∘C.

Fig. 7. (a) Temperature dependence of ρ 𝐂 of bonded- S i C s ( 𝐦 ) and mono- S i C ( • ) . Resistivity varies from 2.6 to 34.4 m Ω · c m for the bonded-SiCs. (b) Relationship between the resistivity of bondedSiCs and ρ C at RT, 175 ∘ C , and the difference ( Δ ρ C ) between RT and 175 ∘ C .

Analysis of a polycrystalline layer of a bonded substrate

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Fig. 8 presents the results of SIMS and Hall measurements, illustrating (a) the relationship between the resistivity of bonded-SiCs and nitrogen concentration and (b) the relationship between nitrogen concentration and carrier concentration, as compared with mono-SiC. The nitrogen concentration in bonded-SiCs correlates with the resistivity of the polycrystalline layer and is one order of magnitude higher than that in mono-SiC with similar resistivity (see Fig. 8 (a)). This is due to the low carrier mobility in the polycrystalline layer; however, it is easy to increase the nitrogen concentration by an order of magnitude in the polycrystalline layer. Furthermore, the nitrogen and carrier concentrations in the polycrystalline layer of bonded-SiCs were nearly identical, indicating that the nitrogen in the polycrystalline layer was nearly 100% activated (see Fig. 8 (b)). Yu et al. have presented the relationship between ρC and donor concentration (ND) [8], and it is known that ρC depends on carrier concentration. Below, we discuss the effect of high carrier concentration in polycrystalline bonded SiC on ρC.

[picture]

Fig. 8. Relationship between (a) the resistivity of bonded- SiCs and nitrogen concentration and between (b) nitrogen concentration and carrier concentration in the polycrystalline layer of bondedSiCs as compared with mono-SiC.

Fig. 8. Relationship between (a) the resistivity of bonded- SiCs and nitrogen concentration and between (b) nitrogen concentration and carrier concentration in the polycrystalline layer of bondedSiCs as compared with mono-SiC.

Fig. 9 (a) presents the band diagram for the ohmic contact of mono- SiC as reported [6, 9]. For mono-SiC, n+doping with a concentration exceeding 1×1019 cm−3, combined with high-temperature annealing, can provide low-resistance ohmic contact to 4 H mono-SiC. n+doping increases the Fermi level ( EF ) of the mono-SiC above its conduction band energy ( EC ), resulting in a thin Schottky barrier. Considering that the conduction between mono-SiC and a metal is dominated by tunneling current, extremely low-resistance ohmic contact can be achieved. In this case, the carrier transport mechanism is known as field emission.

Fig. 9 (b) illustrates the band diagram for a polycrystalline layer of bonded-SiC with ohmic contact, as predicted based on results in this study. As shown in Fig. 7, the ρC of the polycrystalline layer on bonded-SiC exhibited no temperature dependence below the threshold resistivity, indicating that tunneling current is the dominant conduction mechanism between the polycrystalline layer and the backside metal. By contrast, the ρC on mono-SiC shows temperature dependence, indicating that thermally excited current and tunneling current contribute to the conduction. In this case, the mechanism underlying current transport through the barrier is known as thermionic field emission. Similarly, above the threshold resistivity, ρC of the polycrystalline layer on bonded-SiC exhibits temperature dependence, indicating that thermally excited current becomes dominant alongside tunneling current in the conduction between the polycrystalline layer and the backside metal.

Furthermore, a linear correlation exists between the resistivity of bonded- SiCs and ρC below the threshold resistivity (Fig. 5). Similar to the mechanism underlying the ohmic contact of mono-SiC
(Fig. 9 (a)), a high nitrogen concentration in the polycrystalline layer leads to a thinner barrier width and increased tunneling current. Thus, ρC is primarily determined by the resistivity of the polycrystalline layer of bonded-SiC. Considering that ρC is primarily governed by ND and barrier height (ϕB)[8], when tunneling current dominates the ohmic contact, the current depends on ND. In addition, the polycrystalline layer has a high nitrogen concentration (Fig. 8), with nearly 100% activation, resulting in a carrier concentration of 1.5×1020 cm−3 (at a resistivity of 2.6 mΩ· cm ). This value is an order of magnitude higher than the n+doping concentration required for mono-SiC tunnel ohmic contacts ( ≥1×1019 cm−3 ). Therefore, the EF value of the polycrystalline layer can be close to or above Ec , which is similar to the band structure of n+doped mono-SiC ohmic contact [6]. Under these conditions, a large number of electrons exist above the conduction band, which could be a key factor that increases tunneling current. These results also support that, above the nitrogen concentration at the threshold resistivity, tunneling current is the dominant conduction mechanism between the polycrystalline layer and the backside metal.

As shown in Fig. 9, by simplifying the equation presented by Yu et al. [8], ρC is proportional to exp(ϕB/N). In order to analytically model a linear relationship between ρC and resistivity of the polycrystalline layer of bonded-SiC, it is necessary to clarify the relationship between carrier concentration and resistivity; however, this has not yet been achieved. Additionally, the formation of Ti/Ni silicide in the backside contact affects both the ϕB at the silicide interface and the thickness of the natural oxide layer (tunneling distance) at the interface. However, since the contact between the polycrystalline layer and Ti/Ni is ohmic, it is difficult to measure the barrier height, and thus the influence of ϕB has not been separated. These remain issues to be addressed in future work.

[picture]

Fig. 9. Band diagrams of the (a) tunnel ohmic contact of 4H−SiC using n+doping and the hightemperature annealing [6] and (b) ohmic contact of 3C-SiC polycrystalline with a backside metal.

Fig. 9. Band diagrams of the (a) tunnel ohmic contact of 4 H − S i C using n + doping and the hightemperature annealing [6] and (b) ohmic contact of 3C-SiC polycrystalline with a backside metal.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.97.pdf

In this study, bonded-SiCs (SiCkrest TM ) with an average resistivity of 2.4−31.5 mΩ· cm were prepared. The relationship between the resistivity of the bonded-SiCs and the backside contact resistance was clarified, and the mechanism underlying such a relationship was investigated.

In the polycrystalline layer of bonded-SiC, the correlation between the resistivity of bonded-SiCs and ρC indicates the existence of a threshold resistivity at which low ρC can be achieved without contact annealing; it also indicates that the temperature dependence of ρC is eliminated. This phenomenon is attributed to the dominance of tunneling current above the nitrogen concentration at the threshold resistivity, which is driven by a high nitrogen concentration and sufficient carrier activation in the polycrystalline layer of bonded-SiCs. These are important properties resulting from a polycrystalline layer with a 3C structure in bonded-SiC.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1192.97.pdf

This paper was produced as part of a joint research project of Tsukuba Power Electronics Constellations. The co-authors, S. Ishikawa and Y. Higashi, are affiliated with PHENITEC Semiconductor Corp.

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Keywords Index

#

4 H -sic Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

4h-sic Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation; NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

A

Ald Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Atomic Layer Deposition Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

B

Backside Contact Resistance Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Bonded Substrate Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

C

Capacitors Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Circular Tlm Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Contact End Resistance Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Contact Length Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Cv Characteristics Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

D

Density Of Interface States Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

E

Embedded Cmos Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

G

Gate Oxide Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

H

Hall Measurement Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Hysteresis Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

L

Laser Annealing NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Linear Component Separation Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Low-resistivity Polycrystalline Layer Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

M

Metal-oxide-semiconductor (mos) Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

N

No Annealing Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

O

Ohmic Contact NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

S

Sheet Resistance Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

SiC Mosfets Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Silicide NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Sims Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Simulation Analysis Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Sio2 Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Specific Contact Resistivity Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Specific On-state Resistance Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

T

Tcad Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Threshold Resistivity Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Tlm Test Structure Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Transfer Length Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Trench Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Trench Sidewall Capacitance Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Trench Umosfet Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Authors Index

A

Agbo, N. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Alberti, A. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Albrechtvechietti, F. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Antoniou, M. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

B

Badalà, P. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Bartolf, H. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

Bassi, A. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Becker, T. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Bellocchi, G. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Boccarossa, M. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Bongiorno, C. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Boscaglia, M. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Briggs, B. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

C

Charles, W. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Chen, K. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Chudzik, M. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Cooper, J. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

D

Date, L. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Du, Y. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

E

Erlbacher, T. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

F

Fiorenza, P. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Fischer, B. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Franco, S. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

G

Gammon, P. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Giannazzo, F. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Gott, J. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Greco, G. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

H

Harada, S. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Higashi, Y. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Holt, J. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Hsiao, Y. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Hung, C. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

I

Irace, A. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Ishikawa, S. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Ivanova, T. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

J

Jain, S. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Jank, M. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

K

Kalliomaki, J. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Kauth, J. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Kobayashi, M. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Kojima, K. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Kuo, H. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

L

Lee, B. Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

Ley, M. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Lin, W. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

M

Magna, A. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Manchineni, H. Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Maresca, L. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Mawby, P. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

May, A. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Megalini, L. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Melnyk, K. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Mikolajick, T. Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Misra, V. Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

Morisette, D. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Morita, I. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

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Nagasawa, H. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Nigro, R. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

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Okamoto, M. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Oki, T. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

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Panasci, S. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Pang, A. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

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Rabinzohn, P. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Ramadoss, K. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Rascunà, S. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Rawat, T. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Renz, A. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Roccaforte, F. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Rommel, M. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

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Sakuraba, M. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Sanzaro, S. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Sato, S. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Schilirò, E. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Scholten, D. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

Schulze, J. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Sezaki, H. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Shu, J. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Suemitsu, M. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Szabo, M. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Söderlund, M. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

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Taylor, P. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Tian, X. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

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Ueno, T. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

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Vivona, M. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Votadoro, V. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Vozny, A. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

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Wachowiak, A. Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Wang, H. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Watanabe, S. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Watanabe, Y. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Wu, T. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

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Yang, Y. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Yildirm, M. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Yu, W. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

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Zhou, P. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Ziegler, J. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

Zignale, M. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC