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ISBN print: 978-3-0364-2127-8
ISBN eBook: 978-3-0364-3127-7
DOI book: 10.4028/b-vcgO2k
© 2026 Trans Tech Publications Ltd, All Rights Reserved

Material Characterisation and Devices Processing

Edited by
Sang Mo Koo
Hoon Kyu Shin

Material Characterisation and Devices Processing

Special topic volume with invited peer-reviewed papers only

Edited by
Sang Mo Koo and Hoon Kyu Shin

Scientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volume 1191 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp -1-0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2026-05-13

Online:
2026-05-19

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1191.-1.pdf

The rapid development of wide-bandgap semiconductor technologies has transformed the landscape of modern electronics, enabling devices to operate under conditions once beyond the reach of conventional materials. Silicon carbide (SiC) and gallium nitride (GaN) have emerged as the base of this technological revolution due to their exceptional electrical, thermal, and mechanical properties. Their wide band gaps, high breakdown electric fields, superior thermal conductivity, and excellent radiation resistance make them indispensable for power electronics, high-frequency systems, aerospace applications, and use in harsh-environment devices.

This special edition brings together fundamental and applied aspects of semiconductor materials science with advanced device fabrication and characteristics evaluation techniques. Particular attention is devoted to the analysis of radiation-induced defects, carrier removal rates, and charge-carrier lifetimes, which play critical roles in determining the performance and reliability of electronic materials and devices. The diagnostic approaches are explored to provide deeper insight into the physical mechanisms governing material behaviour and final devices.

The edition also addresses features of key stages of device processing, including wafer processing, channel implantation, PN-junction formation, and the fabrication of SiC-MOSFET structures. Electrical characteristics, including breakdown voltage, high-voltage reverse current, and carrier transport properties, are examined in detail, highlighting the relationships among material quality, technological conditions, and device performance. Together, these topics establish a comprehensive framework for understanding how advanced characterisation techniques and precise processing technologies enable the development of modern reliable and high-efficiency semiconductor devices.

By harmoniously integrating recent advances from materials science, semiconductor physics, and electronic engineering, this book is intended to serve as a valuable resource for researchers, engineers, and graduate students working in wide-bandgap semiconductors and power device technology. We hope that the contributions presented herein will support advanced next-generation electronic systems for energy, transportation, and space applications.

Table of Contents

Preface

Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Alexander A. Lebedev, Klavdia S. Davydovskaya, V.V. Kozlovski, Michael E. Levinstein, D.A. Malevsky, Andrey E. Nikolaev, Alexey V. Sakharov, N.S. Solonitsyn

Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Lin Dong, Qi Qi Wu, Stefan Nufer

Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

László Makai, Julien Körfer, Zsombor Pap, Bálint Fodor, Mathias Rommel

A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Christian Stefan Gruber, Gregor Pobegen, Jürgen Smoliner

Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Robin Karhu, Volker Häublein, Marshall Wilson, Mathias Rommel, Birgit Kallinger

Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Saverio de Luca, Alfio S. Mancuso, Annamaria Muoio, Enrico Sangregorio, Francesco La Via

A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Han Wei Chen, Chiao Yang Cheng, Wei Liang Lai, Yew Chung Sermon Wu, Bing Yue Tsui

Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Nicola Rinaldi, Luigi di Benedetto, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Mohamed Torky, Justin Lynch, Nick Yun, Stephen Mancini, Miguel Hinojosa, Aivars Lelis, Woongje Sung

Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Minori Matsuoka, Daiki Soda, Kosuke Miyazaki, Toshikazu Tanioka, Kazuya Tojima, Akira Kiyoi, Yasuhiro Kagawa, Tetsuya Nitta

4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Virginia Boldrini, Marica Canino, Marco Pieruccini, Vincenzo Carrano, Heinz C. Neitzert, Luigi di Benedetto, Claudio Santonastaso, Raffaele Buompane, Maria Lucia Mitsou, Nicola Casali, Ravi Prakash Yadav, Matthias Laubenstein, Cristian Degli Esposti Boschi, Alfredo Rubino, Alba Formicola, Lucio Gialanella

Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Shui You Zheng, Xing Jun Luo, Hua Xing Jiang

Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Dinuth C.Y.B. Yapa Mudiyanselage, Skylar deBoer, Stephen A. Mancini, Justin Lynch, Seung Yup Jang, Adam J. Morgan, Woongje Sung

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 1-6

doi: 10.4028/p-71tmVu

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-30

Revised:
2025-12-16

Accepted:
2026-03-21

Online:
2026-05-19

Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

A.A. Lebedev 1,a, K.S. Davydovskaya 1, b, V.V. Kozlovski 1,2,c, M.E. Levinstein 1,d, D.A. Malevsky 1,e, A.E. Nikolaev 1,f, A.V. Sakharov 1,g, N.S. Solonitsyn 1, h

¹A.F.Ioffe Institute Russian Academy of sciences, Polytechnic 26, 194021, St. Petersburg, Russian Federation

2 Peter the Great St. Petersburg State Polytechnical University, Polytechnic 29, St. Petersburg, 195251, Russian Federation

a shura.lebe@mail.ioffe.ru, b Davidovskaya.Klava@mail.ioffe.ru, c VKozlovski@spbstu.ru, d  melev@nimis.ioffe.rssi.ru, e  Dmalevsky@scell.ioffe.ru, f  aen@mail.ioffe.ru, 9  Val@beam.ioffe.ru, n  nikitasolonicyn@mail.ru

Keywords: GaN, SiC, radiation resistance, irradiation temperature, protons, resistance, C-V characteristics.

Abstract

In this paper, the radiation resistance of GaN and SiC is compared. The effect of the irradiation temperature on the carrier removal rate in both semiconductors during proton irradiation is considered. It was found that in GaN , as well as in SiC , the rate of carrier removal decreases with increasing irradiation temperature. The dependence of the GaN sample resistance on the radiation dose was also calculated based on a model previously proposed to describe a similar dependence for SiC. Based on the experimental data obtained, it is concluded that the processes of radiation compensation in GaN and SiC are similar.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

It is known that, like SiC , GaN is considered a promising material for manufacturing power semiconductor devices [1-3]. Compared with silicon carbide, gallium nitride has a larger forbidden gap, greater mobility, and a larger critical breakdown electric field. However, it has less structural perfection and worse thermal conductivity. From our point of view, it is also necessary to compare the radiation resistance of these two materials. While a large amount of work has already been done on this topic for SiC , many issues remain unclear for GaN . For example, the effect of irradiation temperature on the rate of carrier removal or the mechanism of radiation compensation. The purpose of this study was to partially fill the existing knowledge gap about GaN.

Samples and Research Methods

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

For the research, gallium nitride layers with a thickness of d=2 microns grown on sapphire substrates using the MOVPE method were used. The initial concentration of ( Nd−Na)0 at room temperature was 1.8×1017 cm−3. To carry out volt-farad measurements on the surface of the epitaxial layers, hightemperature Schottky diodes with a diameter of ~600 microns were formed using electron beam sputtering of Pt(50 nm)/Au(150 nm). Ohmic contacts were formed by spraying Ti/Al/Ti/Au metals (30 nm/150 nm/60 nm/150 nm) after surface treatment in argon plasma. The irradiation was carried out with protons with an energy of 15 MeV with a maximum dose of 1×1015 cm−2. The irradiation temperature is 200∘C. After each radiation dose, the volt-farad and volt-ampere characteristics were measured.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

Effect of irradiation temperature on the rate of carrier removal in GaN

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

The parameter carrier removal rate ηe is often used to assess radiation resistance.

ηe=[(Nd−Na)0−(Nd−Na)]ΔD,(1)

Where (Nd−Na)0 is the initial concentration of uncompensated donors in the semiconductor before irradiation, (Nd−Na) is the concentration of uncompensated donors after irradiation; 4D is the radiation dose. Based on the measurements of the capacitance-voltage characteristics (CVC) using formula (1), the values ( ηe ) for irradiation with protons under the specified experimental conditions were calculated. All obtained experimental data, as well as literature data for irradiation at room temperature and for SiC are presented in the table 1.

Table 1. Temperature dependence of the carrier removal rate for SiC and GaN .

T, K | 300 |  | 500 |
Material | SiC [4] | GaN [5] | SiC [4] | GaN, current work
ηc, cm⁻¹, protons | ~ 60 | 150 | 13 | ~ 70

As can be seen from the Table, the radiation resistance of GaN is some what inferior to the radiation resistance of SiC . At the same time, the nature of the temperature dependence of the carrier removal rate is similar for both semiconductors - heating to 2000C leads to a decrease in the values of ηe by about 3-4 times for SiC and 2-4 for GaN . Thus, the conducted studies have shown that in GaN , as well as in SiC, there is a significant decrease in the rate of carrier removal in the case of irradiation at elevated temperatures. This result is important for GaN as a promising material for creating hightemperature electronics devices.

Analysis of the temperature dependence of the GaN resistance on the radiation dose

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

Let us now consider the effect of the radiation dose on the resistance of the sample base. We will use the model that we previously developed for SiC analysis [6].

Table 2. Parameters and concentrations of DL arising in n-GaN after proton irradiation [7-10].

Energy level position | Fluence, cm⁻²
0 | 1.0 × 10¹² | 3.9 × 10¹² | 7.2 × 10¹² | 1.1 × 10¹³
Deep level concentration, cm⁻³
Ec – 0.13 eV | 0 | 2.9 × 10¹⁴ | 9.0 × 10¹⁴ | 1.7 × 10¹⁵ | 2.5 × 10¹⁵
Ec – 0.16 eV | 0 | 2.5 × 10¹⁴ | 1.0 × 10¹⁵ | 1.5 × 10¹⁵ | 3.0 × 10¹⁵
Ec – 0.25 eV | 1.7 × 10¹⁴ | 2.7 × 10¹⁴ | 5.4 × 10¹⁴ | 6.9 × 10¹⁴ | 1.3 × 10¹⁵
Ec – 0.6 eV | 2.8 × 10¹⁵ | 3.0 × 10¹⁵ | 3.7 × 10¹⁵ | 4.0 × 10¹⁵ | 3.6 × 10¹⁵
Ec – 0.72 eV | 6.2 × 10¹⁴ | 1.0 × 10¹⁵ | 2.3 × 10¹⁵ | 2.4 × 10¹⁵ | 3.9 × 10¹⁵
Ec – 1.25 eV | 3.9 × 10¹⁴ | 5.1 × 10¹⁴ | 5.9 × 10¹⁴ | 7.1 × 10¹⁴ | 7.7 × 10¹⁴

There are a number of studies where the parameters of the deep levels (DL) that occur when n-GaN is irradiated with protons have been determined. The results are presented in table 2.
Consider n-GaN, doped with Si, which is most often used to produce n-type conductivity in gallium nitride. Silicon donor levels have an activation energy of 15MeV[11]. We will assume that all
radiation defects formed after irradiation are acceptors. Then levels with an energy of 0.13−0.25 MeV will not affect the concentration of electrons in the base at room temperature, since all charge carriers captured by them will be ionized almost instantly into the conduction gap. The remaining GU levels can be conditionally divided into two groups, according to the ratio of the probability of capture and ionization of the carrier at this level.

Acceptor A 1 , which is an average of Ec−0.6eV and Ec−0.72eV levels. This level will capture electrons from the conduction zone, which will be partially ejected back into the zone.

Acceptor A2 with an activation energy equal to 1.25 eV . This level will only capture electrons, and there will be no reverse ionization from it at room temperature.
The schematic arrangement of these levels in the GaN forbidden gap is shown in Fig. 1. The parameters of deep acceptors A1 and A2 and the rate of their introduction are summarized in Table 3.

[picture]

Fig. 1. Diagram of the location of the main types of levels in the upper half of the GaN forbidden gap during proton irradiation.

Fig. 1. Diagram of the location of the main types of levels in the upper half of the GaN forbidden gap during proton irradiation.

Table 3. Parameters of deep levels in case of proton irradiation.

Level | Ionization energy, eV | Concentration before irradiation, cm⁻³ | Concentration after irradiation, cm⁻³ | Carrier removal rate, cm⁻¹
A1 | 0.66 | 3.42 · 10¹⁵ | 4 · 10¹⁵ | 580
A2 | 1.25 | 3.9 · 10¹⁴ | 5.1 · 10¹⁴ | 120

The total concentration of electrons in the conduction band will be considered as the sum of the contributions of levels D and A1. The calculation for each level was performed according to (2) [12]:

n=2(Nd−Na)1+gNaNc·eεd+[(1+gNaNc·eεd)2+4g(Nd−Na)eεdNc]1/2(2)

where Nc is the effective density of states in the conduction band, g=1 is the level degeneracy factor, Ed is the activation energy of the level, and εd is the reduced value of the activation energy calculated by formula (3):

εd=EdkT(3)

R=Le·n·μ·S(4)

where L is the length of the diode base, e is the electron charge, μ is the mobility of charge carriers, and S is the contact area.
As the radiation dose increases, electrons from the donor level D will move to the acceptor levels A 1 and A2. After full compensation of the donor level, the residual conductivity of the sample will be due to the electrons ionized from the A1 level. The dependence calculated by formulas (2) - (4), as well as experimental data from [13] are shown in Fig. 2.

[picture]

Fig. 2. Dependence of GaN resistance on the dose of proton irradiation at a temperature of T=300 K : experiment [13]: 1-Irradiation 0.6 MeV H; 2-Irradiation of 3 MeV 7Li; Calculated dependences 3 - without taking into account changes in mobility; 4 - taking into account changes in mobility.

Fig. 2. Dependence of GaN resistance on the dose of proton irradiation at a temperature of T = 300 K : experiment [13]: 1-Irradiation 0.6 MeV H; 2-Irradiation of 3 MeV 7Li; Calculated dependences 3 - without taking into account changes in mobility; 4 - taking into account changes in mobility.

When irradiated with protons with an energy of 0.6 MeV , the dependence practically coincides with the experiment, however, there are inconsistencies at intermediate radiation doses of ~1014 cm−2. The values of GaN resistance at low and high doses of proton irradiation practically coincide with the experiment.

A parameter that can affect the angle of inclination of the resistance curve depending on the radiation dose may be the mobility of charge carriers, which decreases with increasing radiation dose due to the introduction of defects in the crystal structure. There are no direct experimental data on this dependence, but in [14] the authors investigated the change in the mobility of gallium nitride charge carriers after irradiation during isochronous annealing. As the annealing temperature increased, the mobility of the irradiated gallium nitride sample increased, therefore, the mobility of charge carriers decreases during irradiation. Using the values of the mobility of the n -GaN sample carriers after irradiation, as well as after isochronous annealing, the curve of the resistance dependence on the dose of proton irradiation was calculated, taking into account the change in mobility.

The calculation results are also shown in Fig. 2.

Taking into account the change in carrier mobility, the coincidence with the course of experimental dependence becomes more satisfactory and has only small deviations at intermediate doses.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

The conducted studies have shown the similarity of radiation compensation processes in SiC and GaN. In both materials, a decrease in the rate of carrier removal is observed with an increase in the irradiation temperature. It was shown in SiC that this is due to an increase in the mobility of primary radiation defects with increasing temperature and an increase in the probability of their recombination. It can be assumed that a similar process takes place in GaN.

It was also shown that the dependence of GaN resistance on radiation dose is well described by the model developed for SiC. This model assumed that radiation compensation is caused by the transition of electrons to deep acceptor levels. Thus, it is obvious that such a compensation mechanism is also implemented for GaN.

Conflict of Interest

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

The authors declare that they have no conflict of interest.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

X. Liu, P. Zou, H. Wang, Yu. Lin, J. Wu, Z. Chen, X. Wang, Sh. Huang. Vertical GaN Schottky barrier diode with record high figure of merit ( 1.1GW/cm2 ) fully grown by hydride vapor phase epitaxy," IEEE Trans. Electron Dev. 70, (2023) 3748.

M. Matys, K. Kitagawa, T. Narita, T. Uesugi, J. Suda, T. Kachi. Mg-implanted vertical GaN junction barrier Schottky rectifiers with low on resistance, low turn-on voltage, and nearly ideal nondestructive breakdown voltage, Appl. Phys. Lett., 121, 203507 (2022).

D. Khachariya, Sh. Stein, W. Mecouch, M. Hayden Breckenridge, Sh. Rathkanthiwar, S. Mita, B. Moody1, P. Reddy, J. Tweedie, R. Kirste, K. Sierakowski, G. Kamler, M. Bockowski, E. Kohn, S. Pavlidis, R. Collazo, Z. Sitar. Appl. Phys. Express, Vertical GaN junction barrier Schottky diodes with near-ideal performance using Mg implantation activated by ultra-highpressure annealing, 15 (2022) 101004.

S.Y .Davydov, K.S. Davydovskaya, V.V. Kozlovski, A.A .Lebedev. Effect of proton and electron irradiation on the parameters of gallium nitride Schottky diodes, Semiconductors, 58, (1), 45-47, (2024).

V.V. Kozlovski, A.E. Vasil'ev, A.A. Lebedev, E.E. Zhurkin, M.E. Levinshtein, A.M. Strelchuk, D.A. Malevsky, A.V. Sakharov, and A. E. Nikolaev, Journal of Surface Investigation: X-ray, Synchrotron and Neutron Techniques, 18(6) (2024) 1577-1581.

A.A. Lebedev, V.V. Kozlovski, K.S. Davydovskaya, R.A. Kuzmin, M.E. Levinshtein, A.M. Strel'chuk, Features of the Carrier Concentration Determination during Irradiation of WideGap Semiconductors: The Case Study of Silicon Carbide, Materials 15 (2022) 8637.

S.A. Goodman et al. Electrical characterization of defects introduced in n-GaN during high energy proton and He-ion irradiation //MRS Online Proceedings Library (OPL). 537 (1998) G6. 12.

M. Hayes et al. Electrical defects introduced during high-temperature irradiation of GaN and AlGaN, Physica B: Condensed Matter, 340 (2003) 421-425.

Z. Zhang et al. Impact of proton irradiation on deep level states in n-GaN, Applied Physics Letters, 103 (2013) 042102.

Z. Zhang et al. Proton irradiation effects on deep level states in Mg-doped p-type GaN grown by ammonia-based molecular beam epitaxy, Applied Physics Letters, 106 (2015) 22104022104.5.

W Götz. et al. Activation energies of Si donors in GaN, Applied Physics Letters. V. 68, №. 22 (1996). 3144-3146.

K.V. Shalimova, Semiconductor Physics; Energoatom: Moscow, Russia, 1985.

A.I. Titov, P.A. Karaseov, S.O. Kucheev, Model for electrical isolation of GaN and ZnO by light-ion bombardment, Semiconductors, 38 (2004) 1215-1222.

S. O. Kucheyev et al. Effect of irradiation temperature and ion flux on electrical isolation of GaN. Journal of applied physics. 91 (2002) 4117-4120.

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The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 7-14

doi: 10.4028/p-gydQM7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2026-01-26

Accepted:
2026-02-23

Online:
2026-05-19

Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Lin Dong 1,a*, Qiqi Wu 2, b and Stefan Nufer 1,c

1 Robert Bosch GmbH, Tübinger Straße 123, 72762 Reutlingen, Germany

2 Robert Bosch GmbH, 333 Fuquan (N.) Road, Shanghai 200335 P.R. China

a Lin.Dong2@de.bosch.com, b  Qiqi.WU@cn.bosch.com, c  Stefan.Nufer@de.bosch.com

Keywords: wafer warpage analysis, mechanical stress, photoelastic measurements, 200 mm SiC wafer technology.

Abstract

Controlling wafer warpage is critical for SiC power device fabrication on 200 mm substrates. Residual mechanical stress in bare SiC wafers is a major contributor to bow and warp. In this study, photoelastic measurements were employed to reveal distinct stress levels among wafers from different vendors, which reflect differences in crystal growth and wafering processes. By decomposing the stress into radial and tangential components, two dominant stress distribution modes-symmetric and asymmetric-were identified. The results demonstrate a clear correlation between residual mechanical stress and wafer warpage in 200 mm SiC substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Bosch is continuously expanding its semiconductor business in silicon carbide ( SiC ) chips by significantly expanding manufacturing facilities and scaling up 200 mm wafer production lines [1]. This growth is accompanied by the establishment of a diversified supplier portfolio, following a multi-sourcing and multi-location strategy. From a technical perspective, in addition to a deep understanding of substrate quality and supplier maturity, front-loaded requirements engineering is essential for ensuring the scalability of production.

In recent years, Bosch has focused on improving crystal defect characteristics; however, the large diameter wafer warpage control during the device manufacturing is now gaining increased attention. The overall shape of a substrate is typically defined by its bow and warp. As the wafer diameter increases from 150 mm to 200 mm , the influence of gravity on bow and warp values becomes more pronounced. According to SEMI standards for silicon wafers, which typically include diameters of 200 mm and 300 mm , the effects of gravity on bow and warp values can be estimated through experimental or mathematical methods [2-3]. However, for SiC wafers, particularly with the industry's initial adoption of 200 mm wafers, these topics have not been extensively explored.

The warpage of a wafer results from the overall mechanical stress state within the material, which can be induced during various manufacturing steps. Notably, the residual mechanical stress in the wafer due to SiC crystalline growth and wafering process can be a primary contributor to excessive bow and warp during device fabrication. Therefore, it is highly important to investigate residual mechanical stress in 200 mm SiC bare substrates and its impact on wafer warpage. We aim at establishing a monitoring method suitable for series production to control stress in incoming SiC wafers. Photoelastic measurement is a suitable method for assessing the stress levels in crystalline materials such as SiC and silicon wafers [4]. This paper focuses on Bosch's in-depth investigation of residual mechanical stress in SiC substrates and the stress-warpage correlation.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

We have investigated the warpage behavior and mechanical stress of multiple 200 mm n-type (0001) 4∘ off-cut 4H−SiC bare wafers produced from different vendors. The typical wafer thickness is 350±25μ m. To ensure that the surface stress due to the sub-surface damage does not influence the measurements, the Si-face of all samples underwent chemical-mechanical polishing (CMP), and
the C-face was treated either by CMP or fine lapping. The wafer bow and warp measurements were conducted using E+H and FRT metrology tools, which employ 2-rod and 3-point supports, respectively.

Photoelastic stress analysis was performed using the Raphael Optech SV200 and ilis StrainScope Stepper 200, both of which enable non-destructive visualization of internal stress distributions [5-6]. Figure 1(a) shows the schematic diagram of the optical path. Light emitted from the source S0 ( 630 nm for Raphael, 590 nm for ilis) first passes through a linear polarizer with a vibration direction along the y -axis. It then enters a quarter-wave plate Q(π/4,δ), whose fast axis is oriented at 45∘ to the polarizer, introducing a phase retardation δ to generate circularly polarized light. This light subsequently passes through the sample M(θ,ϕ), where θ denotes the optical axis orientation and ϕ represents the phase retardation induced by internal stress. Finally, the transmitted light reaches the polarization-sensitive camera Pi(β), which analyzes the polarization state at angle β(=0∘,45∘,90∘ and 135∘ ) and records the intensity distribution. As described in Fig. 1(b), prior to photoelastic stress measurements, the sample holder was adjusted to ensure that the light beam propagated along the wafer's c -axis direction by considering 4 H -SiC refractive index ( n=2.63 ) and off-cut angle to eliminate the natural birefringence phenomenon of 4H−SiC crystal. During the measurement, the whole sample area was scanned along a pre-determined path. The optical phase difference between ordinary and extraordinary light, along with the optical axis orientation ( θ ) was recorded. The stress was then calculated based on the stress-optic law below:

n1−n2=C(σ1−σ2).(1)

where n1 and n2 are the refractive index of fast and slow birefringence axis, respectively, and C is the photoelastic constant, which is −2.82×10−12 Pa−1 in this study [7]. σ1 and σ2 represent the principal stresses along the fast and slow axes. The fast axis corresponds to the direction of lower refractive index, while the slow axis corresponds to higher refractive index - thus n1<n2. Given C<0, this implies σ1>σ2.

[picture]

Fig. 1. (a) Schematic diagram of the instrument's optical path; (b) Schematic drawing of light beam alignment with the [0001] crystallographic orientation of 4H−SiC.

Fig. 1. (a) Schematic diagram of the instrument's optical path; (b) Schematic drawing of light beam alignment with the [0001] crystallographic orientation of 4 H − S i C .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Photoelastic Stress Analysis. We first compared wafer stress results obtained from the Raphael Optech SV200 and the ilis StrainScope Stepper 200. Table 1 presents the measured stress values for the same group of SiC samples using both instruments. The observed deviation between the two tools correlates with ingot and most likely due to different beam alignment at the two measurements. Therefore, the results are highly comparable, indicating good consistency between the two measurement systems. Additionally, we also compared the photoelastic stress distributions obtained from the two instruments and confirmed that all key stress features were consistently reproduced in both maps.

To assess the stress characteristics of incoming substrates from various vendors, Figure 2 presents photoelastic stress distributions across 200 mm4H−SiC wafers supplied by six different vendors. Although the investigation included a baseline of at least three wafers from three different ingots for
each supplier, with the sampling for two of the six suppliers being significantly more extensive, it was noted that wafers from a single source could still exhibit variations in stress patterns due to different growth runs or processing batches. Therefore, the wafers depicted in Fig. 2 are representative examples chosen to illustrate the most characteristic stress profile for each vendor. The stress levels vary significantly among vendors, both in terms of average stress values and spatial distribution. This variation reflects the influence of different crystal growth conditions, wafering techniques, and postprocessing treatments employed by each supplier. Some wafers exhibit relatively uniform stress distributions, while others show pronounced asymmetries or localized stress concentrations. To better understand these patterns, the stress maps were further analyzed and grouped based on their symmetry characteristics. Despite the differences in stress patterns, the wafers can be broadly classified into two distinct groups. Figure 3 shows two typical stress distributions of 200 mm SiC wafers. In first column of average stress mapping, the top wafer exhibits an axisymmetric stress profile with the central region predominantly dark blue (stress near 0 MPa ) transitioning to yellow and red at the wafer periphery (reaching approximately 20 MPa ), indicative of a uniform thermal gradient and controlled cooling process. The white arrows in the average stress maps, representing the direction of the fast birefringence axis and principal stress, are constantly aligned along radial or tangential orientations, suggesting a highly symmetric stress field probably resulting from optimized crystal growth parameters, such as a low thermal gradient. In contrast, the bottom wafer displays an asymmetric stress distribution, with significant stress concentrations across both central and edge regions, and white arrows indicating a non-axisymmetric stress field. This asymmetry, potentially arising from non-uniform temperature gradients during growth or cooling, may elevate the risk of defects such as basal plane dislocation (BPD) or even cracking.

Table 1. Comparison of wafer stress results from Raphael Optech SV200 and ilis StrainScope Stepper 200, showing near-identical measurements.

Sample | Average Stress (MPa) | Comparison Stress Ratio (ilis/Raphael)
Raphael Optech SV200 | ilis StrainScope Stepper 200
Ingot A / Wafer #08 | 2.90 | 2.91 | 1.00
Ingot A / Wafer #06 | 2.66 | 2.68 | 1.01
Ingot A / Wafer #03 | 2.46 | 2.50 | 1.01
Ingot B / Wafer #31 | 3.52 | 3.70 | 1.05
Ingot B / Wafer #29 | 3.38 | 3.54 | 1.05
Ingot C / Wafer #13 | 1.67 | 1.80 | 1.07

[picture]

Fig. 2. Photoelastic stress distributions of representative 200 mm4H−SiC wafers from six vendors (one wafer per vendor). Color scale indicates stress levels from 0 MPa (blue) to 10 MPa (red). Average values for each map are also indicated.

Fig. 2. Photoelastic stress distributions of representative 200 m m 4 H − S i C wafers from six vendors (one wafer per vendor). Color scale indicates stress levels from 0 MPa (blue) to 10 MPa (red). Average values for each map are also indicated.

In order to further understand the nature of the stress pattern variation, the stress is decomposed into radial and tangential components based on the optical axis orientation (shown in the white arrows in Fig. 3). It is well known that light propagating along the c -axis of a stress-free 4H−SiC crystal exhibits no birefringence, as the ordinary and extraordinary refractive indices are equal, resulting in isotropic optical behavior due to the crystal's axial symmetry [8]. However, when mechanical stress is applied to 4H−SiC, the crystal lattice becomes distorted, breaking its axial symmetry and inducing birefringence, as the refractive indices for ordinary and extraordinary rays diverge, leading to polarization-dependent optical behavior.

The stress components along the radial ( σr ) and tangential ( σt ) directions of the wafer are derived from the principal stresses (σ1,σ2) along the birefringence axes, using the angle θ between the fast birefringence axis and the radial direction, given by the following equations [9]:

σr=σ1cos2θ+σ2sin2θσt=σ1sin2θ+σ2cos2θτrt=(σ2−σ1)sinθcosθ

(2a)(2b)(2c)

Since photoelastic measurements can only determine the absolute difference between σ1 and σ2, we assume σ2≈0 to simplify the calculation. Since σ1>σ2 and σ2≈0, σ1 represents a tensile stress. Furthermore, as the measured θ values in our samples are close to 0∘ or 90∘, the equations can be approximated as:

σr≈σ1cosθσt≈σ1sinθτrt≈0

(3a)(3b)(3c)

The tangential tensile stress maps in Fig. 3 for both symmetric and asymmetric wafers exhibit a pronounced ring-like distribution at the wafer periphery (red, up to 20 MPa ), tapering to the center (dark blue, near 0 MPa ), suggesting that the tangential stress is not the primary factor for the asymmetry. It is speculated that during the cooling phase of crystal growth, a uniform peripheral contraction occurs that generates the tangential tensile stress to balance central expansion.

However, the radial tensile stress maps highlight the key difference: the symmetric pattern (top right figure) shows negligible radial stress throughout (near 0 MPa , average 0.416 MPa ). In contrast, the asymmetric pattern (bottom right figure) exhibits significant radial tensile stress in the central region (average 1.513 MPa ), reflecting anisotropic lattice bending or cooling irregularities that disrupt radial equilibrium and introduce non-uniform stress distribution. These contrasts underscore that the symmetric profile arises from optimized crystal growth with uniform thermal fields, while asymmetric profile, potentially stemming from uneven growth or cooling process or imperfect seed quality, manifests primarily through radial stress variations, elevating risks of multiplication of BPDs or cracking.

[picture]

Fig. 3. Comparison of stress mapping in 200 mm SiC wafers with symmetric (top row) and asymmetric (bottom row) stress patterns. From left to right: average stress, tangential tensile stress, and radial tensile stress. The arrows in the average stress maps represent the direction of the fast birefringence axis, which also corresponds to one of the principal stress directions. Average values for each map are also indicated.

Fig. 3. Comparison of stress mapping in 200 mm SiC wafers with symmetric (top row) and asymmetric (bottom row) stress patterns. From left to right: average stress, tangential tensile stress, and radial tensile stress. The arrows in the average stress maps represent the direction of the fast birefringence axis, which also corresponds to one of the principal stress directions. Average values for each map are also indicated.

Incoming Wafer Warpage Inspection and Stress Correlation. Figure 4 illustrates a comparison of bow and warp measurements for identical 200 mm SiC wafers using E+H metrology with 2-rod support and FRT metrology with 3-point support. The FRT results consistently show significantly higher bow and warp values, primarily due to increased gravitational deformation under the 3-point support configuration. This setup subjects the wafer to greater gravitational loading, resulting in more pronounced bending. Notably, all bow values recorded by FRT are negative, indicating a consistent downward curvature and underscoring the sensitivity of wafer geometry to support mechanics and measurement conditions. In contrast, the E+H metrology system provides more stable support, with its 2-rod configuration positioned closer to the wafer center, effectively lowering gravitational effects. As a result, bow values remain near zero and warp values are lower compared to those measured by FRT.

Finally, to establish a reliable monitoring method for incoming 200 mm4H−SiC wafers, we investigated the correlation between residual mechanical stress and various warpage parameters measured by either FRT metrology tool or E+H metrology tool. Interestingly, we found that only the warpage parameters significantly influenced by gravitational deformation, i.e., those measured using the FRT tool, showed a meaningful correlation with wafer stress. In contrast, bow and warp values obtained using the E+H tool with fewer gravitational effects, exhibited insufficient variation across wafers with different stress levels, making it difficult to establish a clear correlation.

The influence of gravity on wafer warpage measurements has been extensively discussed in the silicon industry [2-3, 10]. As an external force, gravity induces additional bending in the wafer, analogous to the mechanical deformation caused by process-induced stress during device fabrication. The effect of gravity also depends on the wafer's intrinsic curvature: it enhances bending in concave wafers and reduces it in convex wafers. To characterize this gravity-induced deformation, we reference the "z_gravity" concept described in SEMI standard MF1390-0218 for silicon wafers, introducing the term "sag value" in this paper [2].

The sag value is defined as the average of bow measurements taken with the wafer oriented both Si-face up and C-face up, using the FRT tool with 3-point support. Mathematically, it is expressed as:

 Sag = bow Si-up + bow C−up2,(4)

where bowsi-up and bowc-up refer to the three-point bow values taken with the Si -face and C -face facing upward, respectively. This method captures the full extent of gravitational influence on wafer warpage. Unlike single-side bow measurements (typically Si -face up), the sag value provides a more comprehensive representation of the wafer's bending behavior, accounting for both orientations. This dual-side approach enables more effective screening of wafers with different shapes and stress profiles.

[picture]

Fig. 4. Comparison of (a) bow and (b) warp measurements for identical 200 mm4H−SiC wafers using the FRT metrology tool with a 3-point holder and the E+H metrology tool with a 2-rod holder; (c) schematic illustration of the 3-point and 2-rod holder configurations.

Fig. 4. Comparison of (a) bow and (b) warp measurements for identical 200 m m 4 H − S i C wafers using the FRT metrology tool with a 3-point holder and the E+H metrology tool with a 2-rod holder; (c) schematic illustration of the 3-point and 2-rod holder configurations.

Figure 5(a)-(c) illustrates the correlation between absolute sag value and stress in 200 mm4H−SiC wafers. The dataset is divided into two groups based on the typical stress patterns identified in Fig. 3. Blue circles represent wafers with symmetric, ring-like stress patterns, while orange squares correspond to wafers exhibiting asymmetric stress distributions.

In Fig. 5(a), two distinct correlation trends are observed: for a given sag value, wafers with asymmetric stress patterns tend to exhibit higher average stress than those with symmetric patterns. As discussed previously, the stress components can be decomposed into radial and tangential tensile stresses. In wafers with symmetric stress patterns, the stress is primarily tangential and concentrated near the wafer periphery. In contrast, wafers with asymmetric stress patterns show significant radial tensile stress concentrated near the wafer center, which contributes comparably to the overall stress. This distinction explains why, in Fig. 5(b), a unified trend between sag value and tangential tensile stress is observed, regardless of stress pattern type. Conversely, Fig. 5(c) shows no significant correlation between sag value and radial tensile stress for either group, suggesting that radial stress has a limited influence on sag. While the underlying mechanism remains under investigation, we hypothesize that the spatial distribution of stress components-particularly a peripheral tangential field-governs gravity-induced bending by constraining basal-plane curvature. Accordingly, our future work will (i) develop a mechanics-based model that couples the measured stress components to the observed sag, and (ii) directly correlate the Fig. 5(b) metric (tangential tensile stress) with BPD distributions via molten KOH etching and/or X-ray topography on the same 200 mm wafers, to
establish quantitative stress-dislocation-warpage relationships. This is consistent with prior observations connecting residual stress, BPD distributions, and basal-plane bending in SiC growth [11].

[picture]

Fig. 5. Correlation between absolute sag value and stress in 200 mm SiC wafers. (a) Average stress vs. sag value; (b) Tangential tensile stress vs. sag value; (c) Radial tensile stress vs. sag value. Blue circles represent wafers with symmetric ring-like stress patterns, while orange squares indicate asymmetric stress patterns.

Fig. 5. Correlation between absolute sag value and stress in 200 mm SiC wafers. (a) Average stress vs. sag value; (b) Tangential tensile stress vs. sag value; (c) Radial tensile stress vs. sag value. Blue circles represent wafers with symmetric ring-like stress patterns, while orange squares indicate asymmetric stress patterns.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

In this study, we investigated the mechanical stress and warpage behavior of 200 mm bare 4H−SiC wafers. Photoelastic measurements were employed to quantify residual stress, revealing significant variation among wafers from different vendors-an indication of differing levels of process maturity in crystal growth and wafering. The stress distributions were classified into two dominant types: symmetric and asymmetric. By decomposing the stress into tangential and radial components based on the optical axis orientation, we attributed these patterns to distinct stress mechanisms. In the analysis of wafer warpage, we demonstrated that the metrology setup-particularly the support method-plays a critical role in the measured bow and warp values due to gravitational deformation. To better capture this effect and correlate it with residual stress, we introduced the sag value as a representative metric for gravity-induced wafer bending. Our results show a clear correlation between sag value and average stress, with distinct trends for symmetric and asymmetric stress patterns. Interestingly, tangential tensile stress exhibited a unified correlation with sag value, independent of stress pattern type, while radial tensile stress showed no significant correlation. These findings suggest that warpage measurements influenced by gravity, such as those captured by the sag value, can serve as an effective and non-destructive method for monitoring the mechanical properties of incoming SiC wafers.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

We gratefully acknowledge Dr. Christian Kranert and M. Sc. Paul Wimmer from Fraunhofer IISB Germany for the insightful discussions that inspired this work. The results are part of IPCEI ME/CT project which is supported by the Federal Ministry for Economic Affairs and Energy on the basis of a decision by the German Parliament, by the Ministry for Economic Affairs, Labor and Tourism of Baden-Württemberg based on a decision of the State Parliament of Baden-Württemberg, the Free State of Saxony on the basis of the budget adopted by the Saxon State Parliament, the Bavarian State Ministry for Economic Affairs, Regional Development and Energy and financed by the European Union - NextGenerationEU.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Information on https://www.bosch-semiconductors.com/stories/silicon-carbide-chip-production-preparing-for-the-future/.

SEMI MF1390-0218, Semiconductor Equipment and Materials International (2023).

SEMI 3D12-1020, Semiconductor Equipment and Materials International (2015).

E. Gamarts, P. Dobromyslov, V. Krylov, S. Prisenko, E. Jakushenko, V. I. Safarov, Characterization of stress in semiconductor wafers using birefringence measurements, J. Phys. III 3 (1993) 1033.

Information on .

Information on .

M. Herms, G. Irmer, S. Spira, M. Wagner, The photoelastic constant of (0001) 4H silicon carbide determined by scanning infrared polariscopy, Phys. Status Solidi A 218 (2021) 2100198.

M. Fukuzawa, K. Kanamoto, Photoelastic characterization of residual strain distribution in commercial off-axis SiC substrates, J. Electron. Mater. 49 (2020) 5161-5166.

J.M. Gere, B.J. Goodno, Mechanics of materials, 7th ed., Cengage Learning, 2009, pp.538-566.

H. Liu, X. Zhu, R. Kang, Z. Dong, X. Chen, Three-point-support method based on position determination of supports and wafers to eliminate gravity-induced deflection of wafers, Precision Eng. 46 (2016) 339-348.

T. Ailihumaer, H. Peng, B. Raghothamachar, M. Dudley, G. Chung, I. Manning, E. Sanchez, Relationship between basal plane dislocation distribution and local basal plane bending in PVTgrown 4H-SiC crystals, J. Electron. Mater. 49 (2020) 3455-3464.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 15-20

doi: 10.4028/p-CYfCa5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-19

Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

László Makai 1,a*, Julien Körfer 2, b, Zsombor Pap 1,c, Bálint Fodor 1, d, Mathias Rommel 2,e

1 Semilab Co. Ltd., Prielle K. u. 2, 1117 Budapest, Hungary

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystr. 10, 91058 Erlangen, Germany

a  aszlo.makai@semilab.hu, b  julien.koerfer@iisb.fraunhofer.de, c  zsombor.pap@semilab.hu, d  balint.fodor@semilab.hu, e  mathias.rommel@iisb.fraunhofer.de

Keywords: spectroscopic ellipsometry, thin oxide layer measurements, backside reflection, brewster's angle.

Abstract

The measurement of thin silicon dioxide ( SiO2 ) layers on silicon carbide ( SiC ) substrates is crucial because these layers serve a variety of critical functions in electronic and optoelectronic devices. Silicon carbide's superior electrical and thermal properties make it a preferred material for high-power, high-frequency, and high-temperature applications. When deposited on SiC , thin SiO2 films act as preconditioning layers, and as gate oxides, precise measurement of these oxide layers is important to ensure both optimal functionality and extended device longevity. This paper presents the essential considerations that should be addressed when Silicon-Oxide layers on SiC substrate are measured by spectroscopic ellipsometry to avoid backside artifact and enhance sensitivity in their thickness measurements. The methodology demonstrated enables reliable detection of layer thicknesses down to less than 1 nm , with a discrimination of less than ±0.5 nm. During ellipsometry data evaluation, parametric models are applied to describe the anisotropic backside reflections. Incorporating additional parameters, such as the substrate thickness, can yield deeper insights into the sample. However, this added complexity can render the modeling approach impractical for routine industrial applications, even though it remains scientifically valuable. Overall, this study emphasizes the combined importance of using a microspot system and optimizing the incidence angle to overcome the inherent challenges of measuring thin SiO2 films on 4H−SiC.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

The accurate characterization of ultrathin silicon dioxide ( SiO2 ) layers on silicon carbide ( SiC ) substrates is essential due to their pivotal role in the performance and reliability of electronic and optoelectronic devices. Owing to its outstanding electrical and thermal characteristics, SiC is widely used in high-power, high-frequency, and high-temperature applications [1]. When thin SiO2 films are formed on SiC , they function as gate dielectrics or surface conditioning layers, making precise thickness measurement a key factor in ensuring device efficiency and long-term stability.
Previous studies [2] have shown that spectroscopic reflectometry often lacks the necessary sensitivity to accurately measure SiO2 layers thinner than 50 nm , and especially those below 10 nm . In addition, monitoring the efficiency of SiO2 hard mask etching is key to checking if the oxide has been totally removed or if there is any (very) thin oxide left because this could hinder a subsequent process step. In contrast, spectroscopic ellipsometry (SE) is a highly sensitive, absolute measurement technique that analyzes changes in the polarization state of light upon reflection from a sample surface. In this study, SE measurements were carried out using the Semilab SE-2000 system [3], and data analysis was performed with the Semilab SEA software.
This study presents the practical consideration to successfully apply Spectroscopic Ellipsometry sensitivity on the measurement of the ultrathin SiO2 layers on 4H−SiC substrates.

Measurement Principles and Sensitivity Optimization

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

The results of spectroscopic ellipsometry are typically presented as a pair of spectra: Ψ, which represents the amplitude ratio of the Fresnel reflection coefficients for p - and s-polarized light, and Δ, which denotes the phase difference between these two polarization components.
The Brewster's angle of a bulk material sample is defined as the angle of incidence at which the reflected and refracted light beams are perpendicular to each other. This angle depends on the refractive index of the material and plays a critical role in optical measurements.
When the angle of incidence (AOI) approaches the Brewster's angle of the 4H−SiC substrate, spectroscopic ellipsometry (SE) achieves high sensitivity. At this angle, the p-polarized component of the reflected light is significantly reduced, and ideally, a sharp 180∘ phase shift ( Δ ) occurs when the layer thickness is 0 nm . As the layer thickness increases, the slope of the phase change ( Δ ) gradually flattens (see Fig. 1), enabling precise detection of ultrathin layers. Therefore, selecting an incidence angle close to the Brewster's angle is essential for accurate thin-film thickness measurements.

[picture]

Fig. 1. D sensitivity for SiO2 layer thickness around Brewster's angle: a. for SiC at 70∘AOI, b. for Si at 75∘AOI.

Fig. 1. D sensitivity for S i O 2 layer thickness around Brewster's angle: a. for SiC at 70 ∘ A O I , b. for Si at 75 ∘ A O I .

Measuring thin SiO2 films on SiC surfaces becomes more complex due to the anisotropic properties of the substrate [4]. These properties can introduce backside reflections that appear as interference fringes in the spectroscopic data. As an example, a measurement on a 2.9 nmSiO2 layer on a 4H−SiC substrate measured at 75∘ angle of incidence is presented. In this case the angle of incidence is not ideal for the measurement as it is further away from the Brewster's angle of 4H−SiC, which is 70∘ for the refractive index 2.747.

Backside Reflection and Anisotropy Correction

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

In practice, the spectral interference pattern depends on the difference between the ordinary and extraordinary refractive indices and the thickness of the substrate. As shown in Fig. 2 there are spectral ranges where the interference pattern vanishes due to the peaks in the extinction coefficient (k) spectra which is responsible for light absorption.

The modeling of the ellipsometry spectra affected by anisotropic backside reflection requires the backside reflection correction feature of the SEA software. The optical dispersion for the anisotropic substrate is obtained from the literature [4]. The modeled ellipsometric spectra of anisotropic samples were calculated using the 4×4 Berreman matrix method [5, 6]. Accurate modeling of ellipsometric spectra in the presence of anisotropic backside reflections requires careful consideration of the optical
behavior of the substrate. To account for the complex behavior of light within the substrate, including multiple internal reflections and wave interference, advanced modeling techniques are employed. These approaches ensure that both coherent and incoherent contributions to the reflected signal are properly represented, enabling a more precise interpretation of the measured spectra.

[picture]

Fig. 2. Y spectrum of a 2.9 nmSiO2 on SiC structure with model fit. The inset shows the ordinary and extraordinary refractive index of 4H−SiC.

Fig. 2. Y spectrum of a 2.9 n m S i O 2 on SiC structure with model fit. The inset shows the ordinary and extraordinary refractive index of 4 H − S i C .

Although accounting for anisotropic backside reflection yields scientifically meaningful results for modeling such samples, it is not practical from an industrial perspective. Implementing this correction necessitates incorporating the substrate thickness into the model and fitting it during lateral mapping. This approach not only increases analysis time but may also reduce sensitivity to thin layer thickness due to parameter correlation. Excluding the backside-reflected light from the measured intensity would enable a more robust model with enhanced sensitivity to thin oxide layers.

Microspot System and Instrumental Enhancements

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

To effectively address this issue, a precisely configured microspot system is essential for reducing or eliminating backside reflections, thereby minimizing spectral interference. The microspot system of the Semilab SE-2000 achieves this by employing the so-called knife-edge method.
The principle of this method is based on the optical separation of frontside, and backside reflected light, ensuring that the backside reflection does not reach the detector. In specific configurations, the system can be adjusted so that only the backside reflected light is detected, while the frontside reflection is excluded.
The implementation of the knife-edge method is based on the SE-2000 microspot system which reduces the measurement spot size by projecting the light source onto the sample, achieving a minification. Using the identical optical configuration in the reverse way at the detection side, it magnifies not only the measurement spot, but also the distance between the frontside reflected light and the virtual position of the backside reflected light. (Fig. 3).

[picture]

Fig. 3. Schematic drawing shows how the SE-2000 microspot system helps exclude the backside reflection. The layer and substrate thicknesses are not to scale.

Fig. 3. Schematic drawing shows how the SE-2000 microspot system helps exclude the backside reflection. The layer and substrate thicknesses are not to scale.

The effect of the microspot system on the backside reflection removal could be improved if we further reduce the spot size. In a projection-based system, it could be accomplished either by decreasing the focal length ratio of the focusing objective and the collimation optic or by minimizing the object size. The object size could be reduced by introducing a pinhole in front of the lamp which reduces the area from which the light of the source is used.

Experimental Results and Sensitivity Demonstration

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

The investigated sample in this study was a native oxide layer on 4H−SiC. The instrument used was an SE-2000 spectroscopic ellipsometer equipped with an automatic goniometer and an Ultra Microspot option. In practice, the Ultra Microspot employs a pinhole in front of the light source to further decrease the measurement spot size and mitigate unwanted reflections.
Fig. 4. shows measurement and fitted spectra of a 1.2 nm thick SiO2 layer on 4H−SiC along with two simulated spectra using the same model but varying the layer thickness by ±0.5 nm. The measurement in this case applies both the above-mentioned methods for improving the measurement quality. The 70∘ incidence angle provides sensitivity for even small thickness changes and the microspot system, along with the ultra-microspot pinhole, effectively reduces the backside effect to the noise level.

[picture]

Fig. 4. Measured native oxide layer on 4H−SiC surface with fitted thickness of d=1.201 nm and simulated curves for layers with d±0.5 nm. The dashed and dotted curves apparently present the sensitivity of the Brewster's angle conditions for small changes in thickness

Fig. 4. Measured native oxide layer on 4 H − S i C surface with fitted thickness of d = 1.201 n m and simulated curves for layers with d ± 0.5 n m . The dashed and dotted curves apparently present the sensitivity of the Brewster's angle conditions for small changes in thickness

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

This study demonstrates that spectroscopic ellipsometry enables highly sensitive measurement of ultrathin oxide layers on 4H−SiC substrates. However, due to the material's high transparency, elevated refractive index, and the limited thickness of the substrate, specific methodological enhancements are required to ensure measurement robustness. These include the suppression of anisotropic backside reflections and the optimization of measurement geometry-particularly by aligning the incidence angle near the Brewster's angle of the sample. With these improvements, spectroscopic ellipsometry holds strong potential to become a standard process control technique for wide-bandgap materials, even in applications where precise monitoring of thin oxide layers is critical.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

T. Kimoto "Material science and device physics in SiC technology for high-voltage power devices" 2015 Jpn. J. Appl. Phys. 54040103.

J. Koerfer, M. Rommel, A. Fuchs, O. Rusch. "Improvement of Reflectance Spectroscopy for Oxide Layers on 4H-SiC". SSP;358:109-14.

L. Makai, T. Lehto, B. Fodor, P. King; "Breakthrough instruments and products: Investigation of atomic layer deposited layer by spectroscopic ellipsometry from the deep-UV to the mid-IR in one instrument." Rev. Sci. Instrum. 92 (11): 119501.

R. Ahuja et al "Optical properties of 4H-SiC". J. Appl. Phys. 91: 2099-2103.

D. W. Berreman, "Optics in Stratified and Anisotropic Media: -Matrix Formulation," J. Opt. Soc. Am. 62, 502-510 (1972).

H. Fujiwara, Spectroscopic Ellipsometry: Principles and Applications, (Wiley, 2007).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 21-28

doi: 10.4028/p-apC4NR

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-29

Accepted:
2026-02-23

Online:
2026-05-19

A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

Christian Stefan Gruber 1,2,a*, Gregor Pobegen 1,b and Jürgen Smoliner 2,c

1 Kompetenzzentrum für Automobil- und Industrieelektronik GmbH, Europastraße 8, 9524 Villach, Austria

2 Technische Universität Wien, Institute of Solid State Electronics, Gußhausstraße 25-25a, 1040 Wien, Austria

a* christianstefan.gruber@k-ai.at, b gregor.pobegen@k-ai.at, cjuergen.smoliner@tuwien.ac.at

Keywords: recombination lifetime, minority charge carrier lifetime, effective lifetime, scanning electron microscope, electron beam induced current, time-resolved EBIC.

Abstract

We present a new method to potentially map the effective minority charge carrier lifetime by means of a chopped electron beam induced current in a scanning electron microscope using a digital lock-in amplifier. While previous authors have been mainly interested in measuring the diffusion length and some even the minority charge carrier lifetime using line-scans, we show that this method could be extended to measure the lifetime locally in the cross section of a given device. In our case, we use a simple SiC pn-junction. The decrease of current with increasing chopping frequency of the electron beam makes a direct measurement of the effective lifetime possible. Inspired by optical beam induced current (OBIC), this novel approach has great potential to measure the minority charge carrier lifetime locally and is going to help device and process engineers to develop the next generation of SiC power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

The effective minority charge carrier lifetime is a crucial parameter that influences a plethora of device characteristics, most notably reverse recovery and in consequence, the switching speed of a power device. For future optimization in both device and process engineering, this raises the question and the need to accurately measure the effective lifetime not only of an entire device, which may be seen as an integrated measurement of all local lifetimes combined, but locally. Existing optical methods include time-resolved photoluminescence [1], time-resolved photoconductance [2] measurements but none of these methods reach sub-micron resolution. A scanning electron microscope (SEM) outperforms optical excitation setups by orders of magnitude in terms of spot size. Thus, a scanning electron microscope can be used in order to obtain the effective minority charge carrier lifetime with great spatial resolution.
The phenomenological process of recombination may be split up into the following physical processes: Shockley-Read-Hall, radiative, Auger-Meissner and surface recombination [3].
These recombination effects can also be written in terms of their corresponding lifetime: Shockley-Read-Hall (SRH) τAug ,radiative τrad  and Auger-Meissner τAug  lifetime. Surface recombination τsur  also needs to be considered:

1τeff=1τSRH+1τrad+1τAug+1τsur(1)

In terms of their physics, SRH describes the recombination of electron-hole pairs through deep level impurities or traps. The energy that is set free during the process is mediated by phonons. Radiative recombination describes a direct band-to-band transition, whose energy is set free by a photon. For intrinsic SiC (without doping), radiative recombination however is unlikely due to its indirect band gap. Radiation may however be emitted through optical transitions of point defects in the crystal. Auger-Meissner recombination is a three-particle process. When an eh-pair recombines, the transition
energy is given off to an outer shell electron, resulting in the ionization of the atom. Surface recombination is a phenomenon that occurs at semiconductor interfaces to other media (such as air or other dielectrics). The crystal lattice is abruptly disturbed. Dangling bonds at this interface become traps for eh-pairs [3] and lead to rapid recombination and short lifetimes near the surface.
Accounting for all recombination processes separately needs labor-intensive measurements, while usually the effective carrier lifetime τeff  is sufficient in most cases to optimizate the device according to the need of the device engineer and subsequently the application.

Theory

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In our effective lifetime measurements, we use the well-known technique called electron beam induced current (EBIC). An incident electron beam on a semiconductor sample creates electron hole pairs. If an electric field is present (like the electric field of a depletion region), the eh-pairs are separated efficiently and can be measured in an external electrical circuit (see Fig. 2). EBIC is used in many applied fields such as failure analysis or defect characterization. Theoretically, it can best be described by the diffusion equation [4] for minority carriers in a n -doped material (same considerations apply for a p-doped material):

Dp∂(pn−pn0)∂x2−pn−pn0τp=∂pn−pn0∂t(2)

Here, Dp is the diffusion coefficient, pn−pn0 the excess carrier concentration and τp the effective carrier lifetime. Steady-state EBIC is by far the most common technique. Therefore, in steady-state, the right-hand side of Eq. 2 is 0 and we get the well-known solution IEBIC∝exp(−xLp), where Lp=Dpτp is the diffusion length. Since in the following analysis, we are concerned with a frequency-dependent approach, the excess carrier concentration oscillates with a given frequency, thus making a time-dependent approach necessary [4]:

u(x)=(pn−pn0)eiωt(3)

u(x) is the general solution to the diffusion Eq. 2 may now be rewritten:

d2udx2−1Lp(1+iωτp)u(x)=0(4)

This differential equation may be solved, yielding the following general solution (using ω=2πf )

u(x)=Aexp(xLp(β+iγ))+Bexp(−xLp(β+iγ))(5)

with

β,γ=12±1+1+(2πfτp)2(6)

The coefficient A is zero, because far away from the junction, EBIC should be null. The phase γ has a minus sign, such that the phase becomes zero in steady-state ( f=0 ). This short mathematical derivation already gives some interesting theoretical insights into the semiconductor material and the EBIC signal and its corresponding phase. This relationship between EBIC, phase and distance are plotted in Fig. 1. With an increase of the beam blanking (chopping) frequency of the electron beam, the EBIC signal is expected to decrease, while the phase becomes more negative. From this decrease in EBIC, the effective carrier lifetime τp may be determined. The same information can be obtained from the phase γ.

[picture]

Fig. 1. Theoretical EBIC signal prediction of a carrier lifetime of 1μs for increasing distance x from the depletion region scaled by the diffusion length L . Solid lines denote the current, dashed lines are the phase prediction for different frequencies. The higher the chopping frequency, the smaller the EBIC signal response with increasing distance (left scale), following Eq. 5. Simultaneously, the phase (right hand scale, dotted straight lines) becomes more negative with increasing frequency.

Fig. 1. Theoretical EBIC signal prediction of a carrier lifetime of 1 μ s for increasing distance x from the depletion region scaled by the diffusion length L . Solid lines denote the current, dashed lines are the phase prediction for different frequencies. The higher the chopping frequency, the smaller the EBIC signal response with increasing distance (left scale), following Eq. 5. Simultaneously, the phase (right hand scale, dotted straight lines) becomes more negative with increasing frequency.

Plotting the EBIC response in the frequency domain is another method to determine the effective lifetime, as is depicted in Fig. 1. Fig. 1 neglects the surface contribution to the EBIC signal. In a real experiment, the EBIC signal is affected by surface recombination, altering the minority charge carrier lifetime. This surface effect can however be accounted for quantitatively, using the technique of Pang et. al. [5]. This method may be altered to use different acceleration voltages for the electron beam (probing depths) as interpolation points to determine the diffusion coefficient and the surface recombination velocity locally.

Another well-known method is time-resolved cathodoluminescence (same principle as time-resolved photoluminescence), which is however limited to measure the radiative carrier lifetime only.

Method

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While the previous analysis has been performed by numerous authors [6, 7, 8] using time-resolved EBIC in the 1980s and very recently by Vasco et. al. [9], local measurement and comparison near the depletion region of minority charge carrier lifetime using the frequency-EBIC method on device level has not been done to our knowledge. After background subtraction at a particular position x, we compare the normalized data of a low and high frequency domain EBIC to deduce the local effective lifetime anywhere in the device:

r=log(I500kHz)log(I20kHz)=−x1Lp2±1+1+(2πf500kHzτp)2−x1Lp2±1+1+(2πf20kHzτp)2(7)

We expect τp to be in a range of roughly 10−7−10−6 s far away from the depletion region, such that the product f20kHzτp is negligible (the error being around 0.2% for a lifetime of 1μs ), such that we can write:

r=121+1+(2πf500kHzτp)2(8)

One could potentially measure the steady state EBIC with a regular DC-EBIC amplifier instead. However, using two different measurement instruments can yield erroneous results in the magnitude (such as offsets and differences in the amplification factor). From an application standpoint, low frequencies also require long averaging times, since lower frequencies have longer periods. To average over the same number of periods thus requires more time. In consequence, the beam needs to dwell at point (xi,yi) until the lock-in amplifier has successfully done its averaging and returned the signal into the SEM before the beam may move to position ( xi+1,yi ). Otherwise, the lock-in signal becomes a mix of EBIC at ( xi,yi ) and ( xi+1,yi ) which is generally undesired.

Eq. 8 can easily be rewritten in terms of τp :

τp=(2r2−1)2−12πf500kHz(9)

This derivation has one flaw: The diffusion length Lp as well as the lifetime τp are considered constants with respect to x in the analytical solution made by McKelvey. Here, first the diffusion Eq. 2 is solved with constant Lp and τp, but we then change our view and assume it to be dependent on x.

Experimental Setup

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In our experiment, a Thermo Fisher Apreo 2 with a Zurich Instruments HFLI Lock-In Amplifier was used. The blanking capability of the Thermo Fischer Apreo 2 SEM is limited by a 20 ns rise/fall time, which gives a highest usable frequency of 100 MHz . The usable frequency range is much lower due to parasitic capacitances in the cables and measurement electronics. The setup is depicted in Fig. 2: A reference signal of the lock-in amplifier was fed into the beam blanking electronics of the SEM. The beam is thus blanked at a desired frequency f. The chopped beam hits the sample and creates eh pairs which diffuse towards the nanoprobing needle or chuck on the back of the sample. This EBIC shown in (c) is then measured in the lock-in amplifier. Meanwhile, it is always possible to obtain a secondary electron image such as from the separated Everhardt-Thornley detector (ETD) as depicted in (b).
As shown in Fig. 2 (d), one could potentially sweep all available frequencies to obtain the entire lowpass filter behavior of a certain position. Since this procedure is quite laborious, it is sufficient to pick two suitable EBIC images taken at two different carefully chosen frequencies (ideally one low frequency and one large one without neglecting the limitations of the SEM, cables and lock-in amplifier).

Results

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Our sample is a high bandgap SiC diode. The most important physical properties are summarized in Table 1. The depletion layer thickness and electric field were calculated from the available doping concentrations and voltage drop.

Table 1. Physical properties of the investigated SiC pn-junction.

p-region doping concentration (cm⁻³) | 10¹⁸ (Al)
p-region thickness (nm) | 400
epitaxial layer doping concentration (cm⁻³) | 10¹⁶ (N)
epitaxial layer thickness (nm) | 5000
Voltage drop (V) | 2.93

Within the depletion region, speaking of a minority charge carrier lifetime originating from a diffusion current is misleading. In the depletion region, this process is not dominated by diffusion but by a drift current. When an eh-pair is generated in the depletion region, the electric field and not a diffusion current accelerates the electrons and holes towards their respective oppositely charged junction boundaries (much like in a plate capacitor). In this analysis, we talk of this time as the transit time t from the generation of a charged carrier to the border of the depletion region and not as the minority carrier lifetime.
Using the mobilities μp,n of electrons and holes in SiC ( 900 and 100 cm2Vs respectively), the transit time through the depletion region can be computed easily. The velocity v=μE [10] can also be rewritten in terms of v=w/t, w being the depletion width. We computed a transit time in the range of picoseconds. Even though these calculations are at best approximate, one can deduce that these transit times are much smaller than the effective minority carrier lifetimes measured in the following analysis. It can thus be assumed that when an eh-pair is generated in the depletion region, it is first swept across the depletion region before it can be measured as current in the external circuit, as majority carriers. The effective minority charge carrier lifetime of generated minority charge carriers on their path towards the depletion region is what we can measure in this analysis, not when carriers are generated within the depletion region. A possible subject for further investigation is bias dependence of EBIC: One could apply a small forward bias (not greater than the built-in voltage) or reverse bias to the junction, such that the depletion region shrinks or expands. That way, the minority charge carrier lifetime closer or further away from the abrupt pn-junction could be analyzed, bearing in mind that the voltage drop only occurs at the depletion region boundary. These experiments have however not been performed yet and will be investigated in the future.

[picture]

Fig. 2. Schematic of the experimental setup: a) The beam is blanked by the reference signal of the lock-in amplifier. If the eh-pairs are generated close enough to the depletion region, they can diffuse to the respective contact pads/back metallization respectively, and be recorded by the lock-in amplifier. Simultaneous measurements (b) of secondary electrons (SE) in the Everhardt-Thornley Detector (ETD) and (c) EBIC is common to yield secondary electron and EBIC images from the scanning of the electron beam over a region of interest. d) Frequency dependence of the EBIC current at position X1. As stated, we refrain from performing an entire sweep of frequencies, but rather compare a low and high frequency EBIC image, which is sufficient to create effective lifetime maps.
By stacking two EBIC images on top of each other, the ratio r and subsequently τp can be obtained from Eq. 9, as depicted in Fig. 3. While strictly only two frequency-dependent EBIC (fEBIC) images are necessary to obtain the minority charge carrier lifetime, some line scans were obtained to show the characteristic decrease of EBIC with increasing frequencies.

Fig. 2. Schematic of the experimental setup: a) The beam is blanked by the reference signal of the lock-in amplifier. If the eh-pairs are generated close enough to the depletion region, they can diffuse to the respective contact pads/back metallization respectively, and be recorded by the lock-in amplifier. Simultaneous measurements (b) of secondary electrons (SE) in the Everhardt-Thornley Detector (ETD) and (c) EBIC is common to yield secondary electron and EBIC images from the scanning of the electron beam over a region of interest. d) Frequency dependence of the EBIC current at position X1. As stated, we refrain from performing an entire sweep of frequencies, but rather compare a low and high frequency EBIC image, which is sufficient to create effective lifetime maps. By stacking two EBIC images on top of each other, the ratio r and subsequently τ p can be obtained from Eq. 9, as depicted in Fig. 3. While strictly only two frequency-dependent EBIC (fEBIC) images are necessary to obtain the minority charge carrier lifetime, some line scans were obtained to show the characteristic decrease of EBIC with increasing frequencies.

[picture]

Fig. 3. Frequency-dependent normalized EBIC current (at 10kHz,20kHz,100kHz and 500 kHz ) and the respective minority charge carrier lifetime (in red) of line-scans using Eq. 9. The bump in lifetime close to zero is a result of computing a value close to log(1)=0.

Fig. 3. Frequency-dependent normalized EBIC current (at 10 k H z , 20 k H z , 100 k H z and 500 kHz ) and the respective minority charge carrier lifetime (in red) of line-scans using Eq. 9. The bump in lifetime close to zero is a result of computing a value close to log ( 1 ) = 0 .

Summary and Outlook

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We have shown that the effective minority charge carrier lifetime can be computed locally in the cross section of a device which may provide valuable information of recombination characteristics. Here, we only use line-scans to measure the lifetime locally, however this technique can be extended to measure the lifetime anywhere in a device, since this technique does not require the knowledge of x or L. While this novel technique has great potential to be used in future failure analysis and device optimization techniques, there are still some unsolved challenges to overcome until this method is ready to be fully automated. Once this method runs smoothly everywhere in the cross section, we will be using different accelerating voltages to compute both the diffusion coefficient and the surface recombination velocity locally.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

This work was funded by the Austrian Research Promotion Agency (FFG, Project No. 914019).

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

Li, Z., Liu, A., Basnet, R., Black, L. E., Macdonald, D., & Nguyen, H. T. (2025). Applications of time-resolved photoluminescence for characterizing silicon photovoltaic materials. Semiconductor Science and Technology, 40(4), 045015.

Sanders, A., & Kunst, M. (1991). Characterization of silicon wafers by transient microwave photoconductivity measurements. Solid-state electronics, 34(9), 1007-1015.

D. K. Schroder, Semiconductor Material and Device Characterization, third ed., John Wiley & Sons, Hoboken, 2006.

J. P. McKelvey, Solid state and semiconductor physics, Robert E. Krieger Publishing Company, Malabar, 1966.

S. Pang, A. Rohatgi, A new methodology for separating Shockley-Read-Hall lifetime and Auger recombination coefficients from the photoconductivity decay technique, Journal of applied physics, 74 (1993) 5554-5560.

T. Fuyuki, H. Matsunami, Determination of lifetime and diffusion constant of minority carriers by a phase-shift technique using an electron-beam-induced current, Journal of Applied Physics, 52 (1981) 3428-3432.

J. Pietzsch, Measurement of minority carrier lifetime in GaAs and with an intensity-modulated electron beam, Solid-State Electronics, 25 (1982) 295-304.

N. Honma, C. Munakata, H. Itoh, T. Warabisako, Nondestructive Measurement of Minority Carrier Lifetimes in Si Wafers Using Frequency Dependence of ac Photovoltages, Japanese Journal of Applied Physics, 25 (1986).

S. Bustillos-Vasco, N. Baier, C. Lobre, C. Cervera, N. Péré-Laperne, A. Evirgen, O. Gravrand, Use of Electron Beam-Induced Current Technique to Characterize Transport Properties of Narrow-Gap-Energy Materials for IR Detection, Journal of Electronic Materials, 53 (2024) 5850-5857.

S. M. Sze, Y. Li and K. K. Ng, Physics of Semiconductor Devices, third ed., John Wiley & Sons, Hoboken, 2007.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 29-35

doi: 10.4028/p-iPd033

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-20

Accepted:
2026-02-23

Online:
2026-05-19

Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1191.29.pdf

Robin Karhu 1,a*, Volker Häublein 1, b, Marshall Wilson 2,c, Mathias Rommel 1, d and Birgit Kallinger 1,e

1 Fraunhofer IISB, Schottkystrasse 10, 91058 Erlangen, Germany

2 Onto Innovation, 12415 Telecom Dr., Tampa, FL 33637, USA

a* robin.karhu@iisb.fraunhofer.de, b volker.haeublein@iisb.fraunhofer.de, c  marshall.wilson@semilabsdi.com, d  mathias.rommel@iisb.fraunhofer.de, ebirgit.kallinger@iisb.fraunhofer.de 

Keywords: oxide, CV measurement, LPCVD TEOS, thermal oxide.

Abstract

An area of increasing interest for SiC device processing is the processing and qualification of silicon oxides. In this article a contactless corona CV (CnCV) measurement procedure is evaluated as a way to gain more knowledge about the different processes related to oxides. A 21-point measurement pattern is used to gain information about uniformity of oxide properties. Two different types of oxides have been considered, low pressure chemical vapor deposited (CVD) oxides using tetraethylorthosilicate (TEOS) and thermally grown oxides. The two different groups have received different combinations of pre- and post-processing steps prior to measurements. As expected, low pressure CVD (LPCVD) and thermally grown SiO2 without any post oxidation annealing (POA) showed significantly different electrical characteristics compared to the wafers that did get a POA. This difference could clearly be distinguished by CnCV , meaning that individual process steps can be analyzed without the fabrication of any test structures on the wafers. As the individual process steps can be analyzed, the uniformity of the individual steps can be accessed. Using a 21-point pattern it was possible to show that there is a non-uniformity in the LPCVD process used prior to the POA. This makes the CnCV technique suitable for in-line characterization and process monitoring.

Introduction

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As silicon carbide technology continues to mature, higher demands are put on each of the processing steps. One area where increased monitoring is desired is that of different oxide layer formation steps that take place during device fabrication. This is due to the wide variety of different oxides that are used. This could be chemical vapor deposition (CVD) oxide to be used as hard mask [1], a thermal oxide to be used as a gate oxide for SiC MOS devices [2], or an atomic layer deposited (ALD) oxide for special applications [3]. What further complicates oxide qualification is that additional processing might affect the properties of the final oxide. The gate oxide quality of a MOS transistor is, e.g., also dependent on the surface quality of the substrate, implying that gate oxide optimization also depends upon the activation anneal after the ion implantation. So, if certain oxide properties are desired, a good understanding of the processing steps and their effect on the oxide is required. Hence, inline control measurements for oxide properties are needed which are quick and do not require any test structure. This study aims to investigate the influence of different processing steps on oxide characteristics using a contactless corona-based capacitance voltage ( CnCV ) technique to characterize the oxides [4]. The CnCV technique uses a corona spot charging device and a Kelvin probe to perform a CV measurement of the oxidized wafers. From these measurements it is possible to extract the equivalent oxide thickness (EOT), total dielectric charge ( Qtot ), flatband voltage ( VFB ), and the distribution ofinterface trap densities ( Dit  ) which can be calculated up to about 0.8 eV from the band edge. The CnCV technique can be used on bare oxides and does not require any test structures. This makes CnCV a strong candidate for inline process monitoring as the contactless nature enables fast measurements without the need of manufactured test structures and the wafers can be returned into the processing line afterwards. The CnCV technique is explained in detail in reference [4].

Experimental

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Six 150 mm4H−SiC homoepitaxial wafers with epitaxial layer thickness between 10.8−12.3μ m have been considered in this work. The epitaxial layers are doped using nitrogen to a net doping concentration of 8.4-8.9 ·1015 cm−3. The wafers received one of two types of oxides, either a silicon oxide realized by a low-pressure chemical vapor deposition (LPCVD) process using TEOS followed by a densification step in inert atmosphere at 900∘C or a thermally grown dry oxide. The LPCVD TEOS deposition took place at a temperature of about 700∘C and the thermal dry oxides were grown at about 1300∘C. The wafers received different combinations of pre- and post-oxide treatments. The pretreatment was a time coupled HF dip where the wafer is dipped in HF immediately prior to loading into the LPCVD reactor or furnace. The post process was a post oxidation anneal (POA) at 1300∘C in a nitrogen monoxide (NO) atmosphere. All processes generated oxides with a thickness between 50−60 nm. The wafer processing is summarized in Table 1.

Table 1. Summary of the wafer processing used in this work. The first column is the wafer "Wafer" identification number. The second column "Time coupled HF dip" indicates whether the wafer got the time coupled HF dip pre-oxide treatment or not. The third column "Oxide" indicates what type of oxide the wafer received. The fourth column "Post oxidation anneal" indicates whether the wafer received the post oxidation anneal in NO atmosphere or not.

Wafer | Time coupled HF dip | Oxide | Post oxidation anneal
1 | Yes | LPCVD TEOS | No
2 | Yes | LPCVD TEOS | Yes
3 | No | LPCVD TEOS | Yes
4 | Yes | Thermal dry oxide | No
5 | Yes | Thermal dry oxide | Yes
6 | No | Thermal dry oxide | Yes

Reproducibility of Measurements

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The wafer used in this study on reproducibility is a wafer that got the same oxide processing steps as wafer 4 in Table 1. The initial voltage ( Vinit  ) measurement by the Kelvin probe depends on the potential of the surface. Vinit  is obtained without applying any charge to the wafer. Thus, it is possible to map Vinit  without affecting later measurements that involve charging the wafer. Vinit  can change drastically depending on what the wafer has been exposed to prior to the measurement, such as charge left on the surface from a previous CnCV measurement or surface absorbed contaminants from water or isopropyl alcohol. The lack of control of the surface absorbed contaminants makes it difficult to reproduce a surface condition. This causes variations in the measured Vinit.  In the following section a demonstration of the reproducibility is shown without perfect restoration of the wafer surface between measurements. To fairly assess the reproducibility of the measurements, the wafer was partially dipped in deionized water and then dried on a hotplate at 95∘C for 10 minutes before each consecutive measurement. In Figure 1 an example is shown; the lower part of the wafer has been dipped in deionized water and the measurement point is marked. A ten-time repeat of the measurement is presented in Table 2. From Table 2 Vinit  was measured between 0.13−0.29 V. This uncertainty adds to the uncertainty of Qtot  as Qtot  is the amount of charge required to reach VFB from Vinit.  To compare Qtot  between the different measurements the Qtot  values have been corrected to the Vinit  of the first
measurement. These are the Qtot  values that we will consider in this paper. Qit  differs from the more widely used Dit in that Dit is evaluated at a specific position in the bandgap, in this case at an energy level of 0.3 eV below the Fermi level ( EF ) (see Figure 2). Qit is obtained by integrating the Dit spectrum between 0.05−0.3eV and for the evaluation of the reproducibility of the measurements Qit  has been considered instead of the more widely used Dit . In Figure 2 the Dit  spectra for each consecutive measurement overlap almost perfectly. Notice that the Dit  spectra in Figure 2 has been translated to represent the energy below the conduction band, the Dit at EF−0.3eV values in Table 2 can be found at about 0.49eV(0.3eV+EF) below the conduction band in Figure 2. In Table 2 the sigma/mean values for the different properties can be seen. For VFB sigma/mean value is 1.56%, for Qit 2.18%, and for EOT it gives 0.15%. Later in this paper it will be shown that these sigma/mean results are sufficient to resolve most of the processes considered.

[picture]

Fig. 1. A map showing the distribution of Vinit  of the wafer used in the reproducibility test.

Fig. 1. A map showing the distribution of V init of the wafer used in the reproducibility test.

Table 2. Summary of the ten consecutive measurements done to test the reproducibility.

Measurements: | Vinit [V] | Vfb [V] | Dit at Ef-0.3eV [10¹¹cm⁻²eV⁻¹] | Qit [10¹¹ q/cm²] | Qtot [10¹¹q/cm²] | Qtot corr. to same Vinit [10¹¹q/cm²] | EOT [Å] | Nd [10¹⁵ cm⁻³]
1 | 0.18 | 2.13 | 3.01 | 1.99 | -6.18 | -6.18 | 540 | 9.93
2 | 0.24 | 2.16 | 3.42 | 2.08 | -6.23 | -6.26 | 537 | 10.1
3 | 0.21 | 2.14 | 3.13 | 1.99 | -6.22 | -6.21 | 540 | 10.1
4 | 0.17 | 2.15 | 3.12 | 2.01 | -6.29 | -6.23 | 540 | 9.88
5 | 0.25 | 2.11 | 3.24 | 2.02 | -6.04 | -6.18 | 539 | 10.0
6 | 0.16 | 2.19 | 3.39 | 2.14 | -6.47 | -6.28 | 539 | 10.0
7 | 0.22 | 2.10 | 3.27 | 2.07 | -5.99 | -6.17 | 540 | 9.87
8 | 0.29 | 2.22 | 3.33 | 2.05 | -6.09 | -6.22 | 539 | 9.83
9 | 0.14 | 2.15 | 3.18 | 2.01 | -6.31 | -6.19 | 539 | 9.96
10 | 0.13 | 2.18 | 3.00 | 2.00 | -6.56 | -6.32 | 539 | 9.92
Average: | 0.20 | 2.15 | 3.21 | 2.04 | -6.24 | -6.22 | 539 | 9.96
Standard deviation: | 0.05 24.6 | 0.03 1.56 | 0.141 | 0.0444 | 0.172 | 0.0470 | 0.79 0.15 | 0.0785
1σ/Mean: | 1% | % | 4.40% | 2.18% | 2.76% | 0.76% | % | 0.79%

[picture]

Fig. 2. Dit  spectra for all of the consecutive measurements numbered #1−#10. The measurements have been made at the site marked in Figure 1.

Fig. 2. D it spectra for all of the consecutive measurements numbered # 1 − # 10 . The measurements have been made at the site marked in Figure 1.

Measurements

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The measurements of the six wafers have been performed in a 21-point pattern as shown in Figure 3. This allows for analysis of the uniformity of oxide properties across the wafers. In Figure 4 the VFB values for each wafer have been plotted for each measurement point. One of the LPCVD TEOS and one of the thermal oxide wafers exhibit significantly higher VFB values than the other four wafers. These are the two wafers that did not get the POA, i.e., wafers 1 and 4. Among the other four wafers it can be seen in the insert that the LPCVD TEOS group together, wafer 2 and 3, and the thermal oxide wafers group together, wafers 5 and 6 . But no significant systematic difference is detected between wafers 2 and 3, and wafers 5 and 6. In Figure 4 b) an outlier can be seen at the center of wafer 6 . This comes from accidental charge left at this measurement spot during the experimental setup.

[picture]

Fig. 3. Explanation of the measurement pattern used for all measurements.

Fig. 3. Explanation of the measurement pattern used for all measurements.

[picture]

Fig. 4. The flatband voltage, VFB, of all six wafers. a) measurements along the x -axis, b) measurements along the y -axis.

Fig. 4. The flatband voltage, V F B , of all six wafers. a) measurements along the x -axis, b) measurements along the y -axis.

In Figure 5 the EOT data is presented, exhibiting several similarities with the results presented in Figure 4, namely, that the two outlier wafers are wafer 1 and 4, the two wafers that did not receive the POA. This increase in EOT for the other wafers is expected as the POA is performed in a NO atmosphere that slightly adds to the EOT thickness. Another similarity between Figure 4 and 5 is that the two LPCVD TEOS wafers 2 and 3 group together and the two thermal oxide wafers 4 and 5 also group up together. One interesting observation is that the LPCVD TEOS process used resulted in concave thickness profiles, both along the x - and y -axis. This is different from the thermally grown oxides that resulted in convex thickness profiles. The shape of the oxide thickness profiles was not changed significantly with the processing steps considered in this work.

[picture]

Fig. 5. EOT of all six wafers, a) along the x-axis, b) along the y-axis.

Fig. 5. EOT of all six wafers, a) along the x -axis, b) along the y -axis.

Figure 6 contains the Qit  results across the wafers. The trends are much the same as in Figure 4 and 5, the two outlier wafers are wafer 1 and 4, the two wafers that did not receive the POA. This is in line with current understanding of POA in NO atmosphere, as it is densifying the oxide and reducing the density of interface traps [5]. Once again, the other two LPCVD TEOS wafers, 2 and 3, do not have any systematic difference from each other. The same is true for the two remaining thermally oxidized wafers, 4 and 5.

[picture]

Fig. 6. Qit of all the six wafers, a ) along the x -axis, b ) along the y -axis.

Fig. 6. Q i t of all the six wafers, a ) along the x -axis, b ) along the y -axis.

Figure 7 shows a collection of Dit  spectra from wafers 1 and 5 . Every color used is a separate Dit  spectrum for each measurement site in Figure 3. All the spectra overlap very well and indicate that the interface traps are very uniformly distributed across the wafers.

[picture]

Fig. 7. Dit  spectra of all the 21 measurement points plotted in the same graph. Every color corresponds to a different measurement site. a) wafer 1, b ) wafer 5 .

Fig. 7. D it spectra of all the 21 measurement points plotted in the same graph. Every color corresponds to a different measurement site. a) wafer 1 , b ) wafer 5 .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.29.pdf

Six 150 mm homoepitaxial SiC wafers received silicon oxide layers through different combinations of processing steps. These wafers were measured at 21 points using the CnCV measurement technique. The resulting profiles for VFB, EOT and Qit  were discussed and although there are a lot of similarities, significant differences became evident. Outlying wafers are always the two wafers that did not receive the POA. This is expected as the POA is supposed to have a large impact on the enhancement of oxide properties. The LPCVD TEOS and the thermal oxides show differences that can be resolved in these measurements. An example is the behavior of the EOT values across the wafers in Figure 5, where the LPCVD TEOS oxides show a concave shape and the thermal oxides show a convex shape even with the pre- and post- processing steps considered in this work. When looking at the wafers that differ only on whether they received the time coupled HF dip or not (wafers 2 and 3 for the LPCVD TEOS case and wafers 5 and 6 for the thermally grown oxides), these wafers could not be systematically distinguished from each other. This could mean that the time coupling between the HF dip and the oxidation is less strict than previously expected, or that the oxide processes considered in this work are not very sensitive to any natural oxide formed prior to the oxide process. A big benefit of the large number of measurement sites, i.e., 21points, is that a lot of
information about uniformity is gained. Looking at the LPCVD TEOS oxides in Figure 4 for example, the VFB of wafer 1 has a weak concave profile along the x -axis, while VFB is lowest closest to the wafer flat and highest at the opposite side of the wafer along the y -axis. As the measurement method is contactless, this enables the wafers to be returned to production after measurement. In the future more processing steps should be considered to see if this method is suitable to either monitor oxide processing or process development.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.29.pdf

Y-H Tseng, B-Y Tsui, J. Vac. Sci. Technol. A 1 November 2016; 34 (6): 061305.

Dev Alok, P. K. McLarty, B. J. Baliga, Appl. Phys. Lett. 23 May 1994; 64 (21): 2845-2846.

C. Kim, J. H. Moon, J. H. Yim, D.H. Lee, J.H. Lee, H. H. Lee, H. J. Kim, Appl. Phys. Lett. 20 February 2012; 100 (8): 082112.

M. Wilson, A. Findlay, A. Savtchouk, J. D'Amico, R. Hillard, F. Horikiri, J. Lagowski, ECS Journal of Solid State Science and Technology, 6 (11) S3129-S3140 (2017).

H. Li, S. Dimitrijev, H. B. Harrison, D. Sweatman, Appl. Phys. Lett. 14 April 1997; 70 (15): 2028-2030.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 37-42

doi: 10.4028/p-lyf5Sy

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-29

Revised:
2025-12-24

Accepted:
2026-02-23

Online:
2026-05-19

Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

S. De Luca 1,a*, A. S. Mancuso 1,2,b, A. Muoio 1,c, E. Sangregorio 1,d and F. La Via 1,e

1 CNR-IMM, sede di Catania Strada VIII 5 - Zona Industriale I-95121 Catania, Italy

2 Università degli Studi di Catania, Via S. Sofia n. 64, 95123 Catania, Italy

a saverio.deluca@cnr.it, b alfio.mancuso@phd.unict.it, c annamaria.muoio@cnr.it, d  Enrico.Sangregorio@imm.cnr.it, e  francesco.lavia@cnr.it

Keywords: 4 H -SiC detectors, OBIC (Optical Beam Induced Current) technique, electric field characterization, Synopsis TCAD simulations.

Abstract

Silicon carbide ( SiC ) is a wide-bandgap semiconductor that has attracted considerable attention for the development of advanced electronic and sensing devices. Thanks to its combination of high breakdown field, excellent thermal conductivity, and chemical stability, SiC enables operation in conditions where conventional semiconductors fail. In this study, the Optical Beam Induced Current (OBIC) technique will be employed to analyze the electric field distribution within the structure of SiC bipolar diodes featuring varying epitaxial layer thicknesses. To create OBIC signal we have used ultraviolet laser beam. We have tested bipolar diodes with both 10μ m and 100μ m epilayer thicknesses. We have obtained several OBIC signals by re-scanning the same location at different reverse voltages applied to the same SiC diode. Also, Synopsis TCAD simulations of the electric field are reported for both diodes. In these simulations it is possible to observe the increase of the electric field at the edge of the devices that are observed by the OBIC measurements. In conclusion, OBIC technique aids in optimizing device design and improving overall performance.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

Silicon carbide ( SiC ) is a wide-bandgap semiconductor known for its outstanding characteristics, making it especially suitable for high-voltage and harsh-environment applications [1-3]. Compared to conventional silicon (Si)-based power devices, SiC consistently demonstrates superior performance [4]. For this reason, 4H-SiC-based devices are increasingly considered as a promising solution to meet the rising demand for high blocking voltages, with requirements ranging from about 3 kV for train electronics to more than 10 kV for electrical distribution networks. In this context, a new generation of 4H−SiC power devices has been developed at CNR-IMM in collaboration with ASM company, aiming to meet the needs of next-generation high-voltage applications. The new-designed devices were tested using the Optical Beam Induced Current (OBIC) technique, a characterization technique that relies on the current generated by an ultraviolet laser ( 325 nm ) to study the electric field in the device at different voltages. The results were compared to numerical simulations performed using the Synopsys Sentaurus TCAD simulation toolkit [5].

Tested Devices

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

The devices investigated in this work are 4H−SiC bipolar diodes developed by CNR-IMM with the support of ASM company. Two types of diodes were fabricated, primarily differing in the thickness and doping concentration of the epitaxial layer to optimize their performance for different blocking voltage ranges. The device designed to operate at 3 kV was grown on n-type 4H−SiC substrates with an epitaxial layer of 10μ m thickness and a doping concentration of 1015 cm−3, while the device designed to operate at 10 kV was fabricated on the same substrate material but featured a thicker
epitaxial layer of 10μ m with a lower doping concentration of 1014 cm−3. In both cases, the P+/N junction was established by epitaxially grown a P+layer on top of the N−epitaxial layer, with a doping concentration of 1018 cm−3. A large active area of 2,25 cm2 was designed for both devices, allowing them to sustain currents on the order of several amperes. To ensure stable operation at high voltages, special edge termination structures were implemented to shape the electric field at the device periphery, preventing premature breakdown. Specifically, a P−Junction Termination Extension (JTE) and a N+Field Stop guard ring was realized through ion implantation to close the field lines and so confine the electric field inside the active area of detectors. The design of the devices, including the active region and the edge termination, is illustrated in Fig. 1, which shows a schematic lateral cross-section of the 4H−SiC bipolar diodes.

[picture]

Fig. 1. Lateral cross-section of the 4H−SiC diode, illustrating the active region (on the left) and the edge termination structure (on the right), including the P−JTE and the N+Field Stop Guard Ring.

Fig. 1. Lateral cross-section of the 4 H − S i C diode, illustrating the active region (on the left) and the edge termination structure (on the right), including the P − JTE and the N + Field Stop Guard Ring.

Experimental Setup and OBIC Technique

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

To create electron-hole pairs inside the semiconductor, a 325 nm UV laser beam was used, as shown in Fig. 2 (a), where the structure of the used bipolar diode with a Junction Termination Extension (JTE) has been reported. The laser beam has been focused by 10 x and 40 x objectives, and the resulting spot diameters size were of the order of 10−5 mm respectively. The focused laser beam was moved on the surface of the device with steps of 2 microns. Both 10 and 100μ m bipolar diodes were tested under revers bias conditions, with voltages in the range of 10−200 V. The voltage was provided and measured by a Keithley 2450 and 2470 SMU (Source Measurement Unit). The OBIC signals were then mapped in 2-directions ( X and Y ) or along one line using a dedicated LabSpec6 software. Fig. 2 (b) shows the OBIC signal generated during a linear laser scan of the device. Four distinct regions can be identified, arising from the different interactions between the laser and the various layers of the material.

[picture]

Fig. 2. (a) Schematic representation of experimental set-up and UV laser used to generate carriers (electron-hole pairs). (b) OBIC signal obtained along a straight line of the entire device.

Fig. 2. (a) Schematic representation of experimental set-up and UV laser used to generate carriers (electron-hole pairs). (b) OBIC signal obtained along a straight line of the entire device.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

The intensity of the photo-generated current is linked to the intensity of the average electric field and therefore to the reverse voltage applied to the detector under test. In Fig. 3. (a) the four different regions can be better observed. Until 50μ m the OBIC is about zero because the laser is outside the active region of the device (Region 1), this signal represents the background current of the detector. Starting from 50μ m an increase of the OBIC signal is observed, as the laser is irradiating the edge structure of the device (Region 2). Close to 200μ m a large decrease of the current is observed as the laser beam reaches the Al metallization layer (Region 3). Then, starting from about 230μ m, a large flat region is visible in correspondence of the anode of the device (Region 4). In this case, the intensity of OBIC is lower with respect to the edge of the device (Region 2) because the thin silicide layer on the top of the P+epitaxial layer produces a reduction of the laser intensity that arrives in the depleted layer, due to its high reflectivity. The same behavior has been observed on the other side of the detector, as shown in Fig. 2 (b).
OBIC signals were acquired at different reverse biases (up to 200 V ) by re-scanning the same location with the laser. The increased electric field caused by an increase in reverse voltage results in an increase of the OBIC signal at the same location, as observed in Region 2 of Fig. 3 (a). Here, using a 10 V reverse bias, the induced current obtained by the laser scan decreases towards the edge of the device (going throws Region 1). This result is linked to a low electric field induced by the reverse polarization. As the reverse bias increases to 50 V , a box-like OBIC signal suggests a uniform electric field in this region. By increasing even more the reverse bias, a small peak of the OBIC current is observed close to the edge of Region 2, suggesting a higher value of the field in this region. The same behavior is observed in the thicker diode (Fig. 3. b), where the OBIC peak is visible already at 50 V . By the amplitude of the OBIC signal in Region 2, the lateral depletion width was calculated at different tensions, the results are reported in Fig. 4 (b).

[picture]

Fig. 3. (a) Photo-current produced by UV laser in 10μ m (a) and 100μ m (b) epilayer thickness SiC detectors along the four regions close to the device edge at different reverse biases. The different amplitude of induced currents depends on the different filters used for the two detectors.

Fig. 3. (a) Photo-current produced by UV laser in 10 μ m (a) and 100 μ m (b) epilayer thickness SiC detectors along the four regions close to the device edge at different reverse biases. The different amplitude of induced currents depends on the different filters used for the two detectors.

o connect experimental data with the structures of the new detectors, several simulations were carried out using Synopsys Sentaurus TCAD for both 10 and 100μ m epitaxial layer devices. Fig. 4 (a) shows the electric field distribution of the 100μ m epitaxial layer device at 500 V . Under these conditions, the simulation reveals a high-intensity electric field point (marked by a red circle) at the boundary between Region 2 and Region 1, responsible for the induced current peak observed experimentally.
Fig. 4 (b) compares the experimental and simulated lateral depletion widths of the boundary region for both devices as a function of the square root of the applied reverse bias. In both cases, experimental and simulated data follow a linear trend up to ~170μ m, where saturation of the lateral depletion occurs. The simulated depletion width of the 10μ m device shows a better agreement with the corresponding experimental data compared to the 100μ m device. This discrepancy may be related to the different objectives used during the characterization of the two devices.

[picture]

Fig. 4. (a) Simulated electric field distribution of the 100μ m epitaxial layer device at 500 V , showing the peak close to the edge of Region 2 (red circle) and the lateral depletion region. (b) Comparison between simulated and experimental lateral depletion widths for the 10μ m and 100μ m epitaxial layers devices as a function of the square root of the applied reverse bias.

Fig. 4. (a) Simulated electric field distribution of the 100 μ m epitaxial layer device at 500 V , showing the peak close to the edge of Region 2 (red circle) and the lateral depletion region. (b) Comparison between simulated and experimental lateral depletion widths for the 10 μ m and 100 μ m epitaxial layers devices as a function of the square root of the applied reverse bias.

Finally, to highlight the correlation between the OBIC signal and the electric field within the device, the mean electric field and the induced current at different reverse bias were evaluated at specific x positions. Fig. 5 reports the simulated mean electric field (averaged along the y direction) and the corresponding experimental induced current measured at different reverse biases for the 100μ m epitaxial layer device at x=150μ m. The electric field was averaged over the first 20μ m from the surface, corresponding to the laser interaction volume. As the reverse bias increases, the induced current rises, reflecting the increase in the mean electric field, which enhances carrier drift velocity and reduces recombination losses. Once a 100% charge collection efficiency (CCE) is reached, further increases in the applied bias, and thus in the internal electric field, do not result in a higher induced current, since all generated carriers are already collected. This behavior explains the exponential correlation observed in Fig. 5.

[picture]

Fig. 5. Simulated mean electric field vs induced current obtained in the plateau area in Region 2 (position x=150μ m ) at different reverse bias for 100μ m epitaxial layer device. The electric field was averaged along y line for the first 20 microns of depth from the surface. This is the penetration thickness of the used UV-laser.

Fig. 5. Simulated mean electric field vs induced current obtained in the plateau area in Region 2 (position x = 150 μ m ) at different reverse bias for 100 μ m epitaxial layer device. The electric field was averaged along y line for the first 20 microns of depth from the surface. This is the penetration thickness of the used UV-laser.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

Several measurements and simulations were performed on a new generation of 4H−SiC devices. The electric field distribution within SiC bipolar diodes under reverse bias was characterized using the Optical Beam Induced Current (OBIC) technique with a spatial resolution of 5−10μ m. This approach enabled the investigation of the edge structure of high-voltage P+/N diodes through the analysis of OBIC signals. The experimental results were compared with TCAD simulations, and optimization of the simulation parameters is in progress to reduce the mismatch with the experimental data at low bias for both devices. Future work will focus on the characterization of the 100μ m epitaxial layer device using a 349 nm UV laser, in order to gain deeper insight into the electric field distribution within the thick epitaxial region.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

K. Shenai et al., IEEE Trans. Electron. Dev. 36 (9) (1989) 1811-1823.

C. Raynaud et al., Diam. Relat. Mater. 19 (2010) 1-6.

T. Mizushima et al., Proc. Int. Symp. Power Semicond. Dev. IC's (2014) 277-280, 10.10.1109/ ISPSD.2014.6856030. WBGS Young, ICSCRM Michael, J. Appl. Phys. 00, 5050 (2021).

S. Tudisco et al., Sensors 18.7 (2018): 2289.

Synopsys Sentaurus TCAD Ver. J-2014.09, Synopsys, Inc., Mountain View, CA, USA. (2014). Available online: .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 43-47

doi: 10.4028/p-3U7wdg

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-14

Accepted:
2026-03-08

Online:
2026-05-19

A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Han-Wei Chen 1,a*, Chiao-Yang Cheng 2, b, Wei-Liang Lai 3,c, Yew-Chung Sermon Wu 3, d, Bing-Yue Tsui 1,e*

1 Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C

2 The Academy of Innovative Semiconductor and Sustainable Manufacturing, National Cheng Kung University, Tainan, Taiwan, R.O.C

3 Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C

a  weich.ee12@nycu.edu.tw, b 11408019 @gs.NCKU.edu.tw, c  a2289063@gmail.com,

d  sermonwu@nycu.edu.tw, e  bytsui@nycu.edu.tw

Keywords: Super-junction, Schottky barrier diode, Epitaxial growth, DLTS, SIMS, AFM, Molten KOH.

Abstract

The impact on doping profile, surface roughness and defect production of each process step for a suggested Multiple epitaxy and implantation (MEI) process for Super-junction has been investigated through Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. Results show that the suggested process can possibly reduce the cost of the original fabrication and speed up the process.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Super-junction (SJ) is known to alleviate the tradeoff between breakdown voltage and specific on-resistance by applying the concept of charge balance [1]. However, the most common fabrication method of SJ structure, Multiple Epitaxy and Implantation (MEI), is time-consuming and costly due to the process complexity [2−3]. On the other hand, hydrogen pretreatment is applied before epitaxial growth, in which the surface is etched and implanted atoms (usually aluminum) may precipitate into the epitaxial chamber. In this work, we examine each step of the MEI process and propose suggestions to simplify the process.

Device Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Fig. 1 shows the main process steps of the experiment, representing one cycle of the MEI process. First, two 4H−SiCn-type epi-wafers with a 11−μm-thick-epi-layer and nitrogen doping concentration of 8.0×1015 cm−3 were prepared. Al ion implantation with energy up to 2.5 MeV was carried out with high energy implanter on half of the wafers, with the expectation that no Al atoms would be distributed within the surface layer of 0.3μ m. Next, one wafer was coated with photoresist and baked to form a carbon cap (C-cap) on the SiC surface. Afterwards, the wafer underwent a 1700∘C postimplantation annealing (PIA) process for 30 minutes, followed by sacrificial oxidation (to a thickness of 35 nm ) after C-cap removal. Surface etching of approximately 0.2μ m by H2 treatment was performed and the subsequent n-type epi-layer with thickness of 2.5μ m and the same doping concentration was grown on both wafers. Table. 1 lists the sample IDs and split conditions. The quality of the regrown epi-layer was analyzed by Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. For DLTS analysis, the samples underwent further process. After a 400−nm-thick PECVD SiO 2 layer was deposited as field oxide, active areas were defined by photo lithography and wet etching processes. Next, Ti/TiN/Al stack were sputtered and patterned, with backside metal deposited in the following step. Finally, the samples were annealed at 500∘C for 5 minutes in vacuum and SBD were fabricated.

Table I. Samples ID and process conditions.

Sample | Al implantation | Annealing
I-A | Yes | Yes
NI-A | No | Yes
I-NA | Yes | No
NI-NA | No | No

[picture]

Fig. 1. Process steps, schematic wafer structure and the cross section of Schottky barrier diode (SBD).

Fig. 1. Process steps, schematic wafer structure and the cross section of Schottky barrier diode (SBD).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Fig. 2 shows the depth profile of the I-NA and I-A samples obtained by SIMS. The results are also compared to TCAD simulations. Through the figure, it can be seen that whether or not PIA was performed, the regrown epi-layer did not affect the Al distribution. No Al in the regrown epi-layer was detected, indicating that after neglecting the low-energy ion implantation step, no Al atoms escape into the epitaxial chamber. Fig. 3 shows the surface roughness ( Rq ) of the four samples measured by AFM. It is expected that implantation without annealing and sacrificial oxidation would increase Rq, which could influence the subsequent epitaxial growth. However, the results show that the Rq values of the four samples are similar, indicating that skipping the annealing and sacrificial processes does not make a significant difference from this perspective.

[picture]

Fig. 2. Secondary Ion Mass Spectrometry (SIMS) depth profiles of Al in the I-NA and I-A samples.

Fig. 2. Secondary Ion Mass Spectrometry (SIMS) depth profiles of Al in the I-NA and I-A samples.

[picture]

Fig. 3. Atomic Force Microscopy (AFM) surface morphology of the four samples.

Fig. 3. Atomic Force Microscopy (AFM) surface morphology of the four samples.

The results of DLTS measurements for the samples are shown in Fig. 4. All samples exhibit a similar and weak Z1/2 signal, and the defect concentration is approximately 6.85×1012 cm−3. The NINA sample shows another signal at 400 K , which is assumed to be RD1/2 with defect density of 3.28×1013 cm−3 and may have been generated during epitaxial growth process [4-5]. To verify this assumption, additional samples with epitaxial layers grown using the same equipment were also fabricated into SBDs and examined by DLTS (Fig. 5). It was found that samples exhibited the RD1/2 signal did show a defect density of 1.2×1012~3.8×1012 cm−3. The following epitaxial might have increased the defect density in the second growth step. On the other hand, the I-NA sample shows a strong signal at 440~460 K. Since the samples underwent Al implantation, we assume the signal originates from ON1 and ON2a[6]. Last, the I-A sample shows an abnormal signal peaked at 500 K . Compared with the previous sample, we suppose that annealing and sacrificial oxidation may have converted the defect into new ones due to the high-temperature process, resulting in a signal combining ON2a and ON2 b [7-9]. Since the defect concentrations in some samples of I-A and I-NA are similar, if PIA is skipped and the MEI cycle is continued, the overall defect concentration will not be affected, although the defect type may be altered [10].

[picture]

Fig. 4. Deep Level Transient Spectroscopy (DLTS) spectra of the NI-NA, I-NA, and I-A samples.

Fig. 4. Deep Level Transient Spectroscopy (DLTS) spectra of the NI-NA, I-NA, and I-A samples.

[picture]

Fig. 5. Deep Level Transient Spectroscopy (DLTS) spectra of other samples with epitaxial growth from the same equipment.

Fig. 5. Deep Level Transient Spectroscopy (DLTS) spectra of other samples with epitaxial growth from the same equipment.

Fig. 6 shows the optical images of the molten KOH -etched surfaces. For I-NA sample, the densities of threading edge dislocations (TEDs) and threading screw dislocations (TSDs) are 1153 cm−2 and 192 cm−2, respectively; on the other hand, for I-A sample, the density of TEDs and TSDs are 1077 cm−2 and 153 cm−2. These values are comparable to that of typical SiC epitaxial wafers. There is no significant difference in the densities of TEDs between the two samples, indicating that the dislocations are nearly independent of the annealing process in the MEI cycle. However, there is a noticeable difference in the densities of TSDs. The difference can be attributed to the variations in substrate quality. The most influential step affecting the quality of the epitaxial layer is still the regrowth process.

[picture]

Fig. 6. Image of SiC surface after molten KOH etching of (a) I-NA sample and (b) I-A sample.

Fig. 6. Image of SiC surface after molten KOH etching of (a) I-NA sample and (b) I-A sample.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

In this work, we examined the impact of each process step of the MEI process on the quality of the subsequent epi-layer. From SIMS analysis, skipping the low-energy implantation prevents Al escape into the epitaxial chamber during growth of the subsequent n-epi layer, thereby avoiding contamination and the following maintenance of the chamber. Moreover, surface roughness and the dislocation density in the subsequent epi-layer are independent of whether PIA is performed. Through DLTS, results indicate that PIA may induce defect transformation, but the slightly increased deeplevel defects can be mitigated by the subsequent epitaxial process. The influence of these defects on the electrical characteristics on devices should be further investigated. Nevertheless, if p-pillar ion implantation and subsequent epitaxy can be performed sequentially, the cost and process complexity could be significantly reduced.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

This work was supported by the National Science and Technology Council, Taiwan, R.O.C. under the contract No. NSTC 113-2218-E-A49-018. Experimental processes were helped by Diodes Inc. and Nano Facility Center of National Yang Ming Chiao Tung University.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

T. Fujihira, Jpn. J. Appl. Phys. 36 6254, (1997).

M. Baba et al., 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), (2021), 83-86.

S. Harada et al., 2018 IEEE International Electron Devices Meeting (IEDM), 2018, 8.2.1-8.2.4.

M. Kato et al., J. Appl. Phys., 100, 5, 053708, (2006).

L. Ottavianil, Materials Science Forum. 457-460, 509-512, (2004).

P. Kumar et al, Materials Science in Semiconductor Processing, 174, 108241, (2024).

P. Kumar et al., J. Appl. Phys., 135, 18, 185704, (2024).

M. E Bathen et al, Materials Science in Semiconductor Processing, 176, 108316, (2024).

T. Okuda et al, Appl. Phys. Express 8 111301, (2015).

H F Xiong et al, J. Semicond. 45 072502, (2024).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 49-53

doi: 10.4028/p-4zjeaP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-09

Accepted:
2026-02-26

Online:
2026-05-19

Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

Nicola Rinaldi 1,a*, Luigi Di Benedetto 1, b, Mathias Rommel 2,c, Alexander May 2, d, Leander Baier 2,e, Rosalba Liguori 1,f, Alfredo Rubino 1, g and Gian Domenico Licciardo 1,h

¹Department of Industrial Engineering, University of Salerno, Via Giovanni Paolo II, 132, Fisciano, Italy

2 Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystraße 10, Erlangen, Germany

a  nrinaldi@unisa.it, b  Idibenedetto@unisa.it, c  mathias.rommel@iisb.fraunhofer.de, d alexander.may@iisb.fraunhofer.de, e leander.baier@iisb.fraunhofer.de, f rliguori@unisa.it, g arubino@unisa.it, h gdlicciardo@unisa.it

Abstract

The effects of 673 K temperature anneal on a 4H−SiC CMOS NOT logic gate have been investigated. After an annealing at 673 K for 30 minutes in ambient atmosphere, a shift of threshold logic voltage, VM, towards higher input voltage by 6.67%, and a hysteresis reduction are observed. Both effects can be related to MOSFETs electrical behavior after the same thermal annealing. The threshold voltage of NMOSFET, VTH, N, increases by 6.67%, whereas PMOSFET one reduces by 11.15%, allowing the VM increase. NMOSFET shows a reduction of its trans-characteristic hysteresis, △VH, by −33.3%, as well as PMOSFET one, that is by −20.4%, explaining the hysteresis reduction of NOT gate. Moreover, a more reproducible NOT transfer characteristics is obtained after the 673 K annealing.

Keywords: 673 K annealing, NOT logic gate, 4H−SiC lateral MOSFETs, 4H−SiC CMOS technology.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

Wide band-gap semiconductors are suitable for harsh environment thanks to their intrinsic physical properties [1]. Among them, 4 H polytype of Silicon Carbide, 4H−SiC, has emerged, with the development of lateral devices and integrated circuits, ICs [2]. JFET and BJT based technologies have been demonstrated for high temperature applications with several integrated circuits [3,4]. However, the process easiness allows the CMOS technology to emerge. This one has proven promising with complex ICs able also to operate up to 773 K [5-7], with the integration of novel devices [8] or conventional lateral temperature sensors [9,10].
Although demonstration of circuits and devices up to very high temperature, i.e. 773 K , have been already done, there is still a lack of knowledge about the reliability of circuit performance, like the repeatability of the results after different temperature anneals.
In this paper, we investigate the static room temperature performances of a 4H−SiC CMOS NOT logic gate after several temperature anneals, which have been heated in ambient atmosphere environment at 673 K for 30 minutes. In addition, we relate the NOT gate electrical behavior after thermal annealing to MOSFET one.

Device Structure and Experimental Set-Up

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NOT logic gate has been fabricated in 4H−SiC CMOS Fraunhofer IISB's Technology [7]. The process starts with the epitaxial grow of a 1015 cm−3 n-type layer on a 4 H -SiC n-type 350μ m4∘ offaxis (0001) substrate. Aluminum and Nitrogen ion implantation, followed by 1973 K,30 minutes, thermal annealing is performed for n -type and p -type doped regions. A doping concentration of 1017cm−3 and 1016 cm−3 is obtained for p -well and n -well regions, respectively. Whereas a doping concentration of 5·1019 cm−3 is for high doped p+and n+regions. A 55 nm thick gate oxide is thermally grown at 1300∘C and a post-oxidation annealing is performed at 1300∘C in NO
environment to reduce the SiO2/4H−SiC interface state density. All these process steps result in gate oxide capacitance, Cox=62.8nF/cm2. Gate electrode is made by depositing a 500 nm thick n-type PolySilicon. NiAl and Ti/Al are used for n-type and p-type contact respectively, whereas a Ti/Pt metal layer stack is used for the two lines of metal interconnections. More detailed information regarding process steps is in [7].
The NOT logic gate is made by a NMOSFET with channel width, WN=6μ m, and a PMOSFET with channel width, WP=44μ m, both with channel length, L=6μ m.
Measurements have been made at room temperature, i.e. T=298 K, with a Keithley SCS-4200, a SUSS PM5 probe station and with Signatone Corporation manipulators. Each temperature anneals consists of heating the devices in ambient atmosphere at 673 K for 30 minutes with a 630 W G.Maier Elektrotechnick GmbH hotplate.

Results and Discussion

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NOT logic gate Characteristics.

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The NOT logic gate is supplied by VDD=20 V and transfer characteristics at T=298 K after multiple 673 K temperature anneals are reported in Fig.1.a). It can be observed that after first 673 K temperature anneal, a shift of threshold logic voltage, Vm, of +6.67% and a reduction of hysteresis voltage, from ΔVH=0.2 V to ΔVH=0.15 V, are observed, as shown in Fig.1.a)-b). Moreover, a reduction of High Noise Margin, NMH, of −6.74% and an increase of Low Noise Margin, NMl, of +6.95%, can be calculated (see Fig.1.c)). Whereas, after the second 673 K temperature anneal, almost the same values of Vm and NML are reached, with a variation of 0.94% and 1% with respect to the first 673 K anneal, and the same value of NMH is observed in Fig.1.c).
Then, a 673 K thermal annealing shows an improvement of NOT performances and a more stable and repeatable transfer characteristic.

[picture]

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T=298 K and VDD=20 V. b) Threshold logic voltage and c) Noise Margins variations.

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T = 298 K and V D D = 20 V . b) Threshold logic voltage and c) Noise Margins variations.

[picture]

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T=298 K and VDD=20 V. b) Threshold logic voltage and c) Noise Margins variations.

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T = 298 K and V D D = 20 V . b) Threshold logic voltage and c) Noise Margins variations.

The effects of the thermal annealing on NOT gate, i.e. shift of its transfer characteristics towards higher voltage and its hysteresis reduction, are related to electrical behaviors of individual devices. Indeed, we analyzed the transfer characteristics in linear region of a NMOSFET and a PMOSFET.

MOSFETs Characteristics.

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Trans-characteristics, at ∣ Vds ∣=0.1 V, of NMOSFET and PMOSFET, both with W=18μ m and L=6μ m, before and after the first 673 K temperature anneal are in Fig.2.a) and in Fig.3.a), respectively. After the thermal annealing, we observe an increase of NMOSFET threshold voltage, Vth, n , extracted according to the extrapolation in linear region method [11], by 6.93% and a reduction of PMOSFET threshold voltage, Vth, p , by −11.15%. This phenomenon can be related to the release of fixed oxide charge, allowing a shift of the flat band voltage towards higher values. Moreover, a reduction of the hysteresis of NMOSFET and PMOSFET characteristics by - 33.3% and −20.4%, respectively, can be observed, which agrees with the reduction of the NOT gate hysteresis. In this case, thermal energy supplied by 673 K annealing could reduce the density of acceptor like slow border traps [12], leading to the hysteresis reduction.
Subthreshold Slope, SS, is obtained from the slope of Ids - Vgs curves, under subthreshold conditions at VDS=0.1 V [13] and same SS is observed for NMOSFET, (see Fig.2.c).
Finally, field effect channel mobility is extracted from trans-characteristics in Fig.2.a) and Fig.3.a) according to [14]:

μCH=dIDSdVGS|VDS=0.1VLVDSCoxW(1)

and, also in this case, same maximum channel mobility, μCH, N peak =19.4 cm2/Vs, was observed (see Fig.2.d). In contrast, the PMOSFET shows a SS reduction of −23.8% and an increase of the channel mobility maximum, μCH,P peak of 4.1% (see Fig. 3.c and d)), which can be related to a reduction of SiO2/4H−SiC interface defects density [15] and, therefore, to a decrease of the associated scattering [16].
Moreover, substituting extracted NMOSFET threshold voltage values before and after thermal annealing, see Fig. 2.b) and Fig.3.b), and the channel mobility peaks, see Fig.2.d) and Fig.3.d), in the following equation of Vm [17]:

VM=VTH,N+r(VDD−|VTH,P|)1+r(2)

where:

r=μCH, P peak COXWPLμCH, N peak COXWN, we obtain a △VM=0.84 V, almost near to the experimental one of 0.6 V,

Fig.1.b), allowing to explain the Vm shift towards higher value.

Fig. 2. a) Trans-characteristic of NMOSFET before and after 673 K temperature anneal. b) The inset shows the extracted Vth,n. In c) Subthreshold Slope and d) field-effect channel mobility.

[picture]

Fig. 3. a) Trans-characteristic of PMOSFET before and after 673 K temperature anneal. b) The inset shows the extracted Vth,p. In c) Subthreshold Slope and in d) field-effect channel mobility.

Fig. 3. a) Trans-characteristic of PMOSFET before and after 673 K temperature anneal. b) The inset shows the extracted Vth,p. In c) Subthreshold Slope and in d) field-effect channel mobility.

Summary

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Analysis of NOT logic gate transfer characteristics after multiple 673 K temperature anneals have been done and its electrical behavior linked to single lateral MOSFETs ones. In particular, the Vm shift towards a higher input voltage value is due to the Vth,n increase by 6.93% and Vth,p decrease by 11.15%. Whereas the NOT transfer characteristics hysteresis reduction can be related to both MOSFETs' hysteresis reduction after the thermal annealing. Then, a 30 minutes 673 K thermalannealing seems to improve the overall devices and circuits performances, improving, also, the repeatability of NOT gate characteristics after multiple temperature anneals.

Author Contributions

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Conceptualization, N.R and L.D.B; methodology N.R.; validation N.R., L.D.B, L.B and A.M; formal analysis N.R. and L.D.B; investigation N.R., L.D.B, M.R, and L.B; data curation N.R. and L.B.; writing-original draft N.R, L.D.B.; M.R., R.L., and G.D.L; writing-review and editing, N.R, L.D.B., M.R., R.L, and G.D.L; project administration A.R. and M.R.; funding acquisition A.R. All authors have read and agreed to the published version of the manuscript.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, John Wiley & Sons, 2014.

J. Romijn, S. Vollebregt, L.M. Middelburg, B.E. Mansouri, H.W. van Zeijl, A. May, T. Erlbacher, G. Zhang, P.M. Sarro, Integrated digital and analog circuit blocks in a scalable silicon carbide CMOS technology." IEEE Transactions on Electron Devices 69.1 (2021): 410.

M. Kaneko, M. Nakajima, Q. Jin, T.Kimoto, SiC complementary junction field-effect transistor logic gate operation at 623 K . IEEE Electron Device Letters 43.7 (2022): 997-1000

L. Lanni, B.G. Malm, M. Östling, C.M. Zetterling, Lateral pnp transistors and complementary SiC bipolar technology. IEEE electron device letters 35.4 (2014): 428-430.

Z. Dong, Y. Bai, C. Yang, Y. Tang, J. Hao, X. Li, X. Tian, X. Liu, Impact of Temperature on Digital Integrated Circuits in a 4H-SiC CMOS Technology. IEEE Transactions on Electron Devices (2024).

N. Rinaldi, R. Liguori, A. May, C. Rossi, M. Rommel, A. Rubino, G.D. Licciardo and L. Di Benedetto, A 4H-SiC CMOS oscillator-based temperature sensor operating from 298 K up to 573 K, Sensors, 23 (2023) 24, 9653.

J. Romijn, S. Vollebregt, L. M. Middelburg, B. El Mansouri, H. W. van Zeijl, M. Alexander, T. Erlbacher, G. Zhang, and P. M. Sarro, Integrated digital and analog circuit blocks in a scalable silicon carbide cmos technology, IEEE Transactions on Electron Devices, 69 (2021) 1, 4-10.

L. Di Benedetto, G. Licciardo, T. Erlbacher, A. Bauer, and A. Rubino, A 4h-sic uv phototransistor with excellent optical gain based on controlled potential barrier, IEEE Transactions on Electron Devices, 67 (2019) 1154-159.

N. Rinaldi, M. Rommel, A. May, R. Liguori, A. Rubino, G. D.Licciardo, L. Di Benedetto, Analysis of a 4 H -SiC lateral PMOSFET temperature sensor between , IEEE Sensors Letters (2025).

N. Rinaldi, M. Rommel, A. May, R. Liguori, A. Rubino, G. D. Licciardo, L. Di Benedetto, A 4H-SiC NMOSFET-based temperature sensor operating between 14 K and 481 K , IEEE Electron Device Letters (2024).

A. Ortiz-Conde, F.J.G. Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, Y.Yue, A review of recent MOSFET threshold voltage extraction methods. Microelectronics reliability 42.4-5 (2002): 583-596.

A. Vasilev, M. Jech, A. Grill, G. Rzepa, C. Schleich, S. Tyaginov, A. Makarov, G. Pobegen, T.Grasser, M. Waltl, TCAD Modeling of Temperature Activation of the Hysteresis Characteristics of lateral 4H-SiC MOSFETs, IEEE Transactions on Electron Devices 69.6 (2022): 3290-3295.

Y. Taur, T.H. Ning, Fundamentals of modern VLSI devices, Cambridge university press, 2002.

N. Arora, Mosfet modeling for VLSI simulation: theory and practice, World Scientific, 2007.

S.M. Sze, K.K. Ng, Physics of semiconductor devices. John wiley & sons, 2007.

V. Uhnevionak, A. Burenkov, C. Strenger, G. Ortiz, E. Badel-Pereira, V.Mortet, F. Cristiano, A.J. Bauer, P.Pichler. Comprehensive study of electron scattering mechanisms in MOSFETs, IEEE Transactions on Electron Devices 62.8 (2015): 2562-2570.

J. M. Rabaey, C. Anantha, N. Borivoje. Digital integrated circuits. Vol. 2. Englewood Cliffs: Prentice hall, 2002.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 55-60

doi: 10.4028/p-4kesV3

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-23

Accepted:
2026-03-16

Online:
2026-05-19

Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

Mohamed Torky 1,a*, Justin Lynch 1,b, Nick Yun 1,c, Stephen Mancini 1,d, Miguel Hinojosa 2,e, Aivars Lelis 2,f and Woongje Sung 1, g

¹Department of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203, U.S.A

2 U.S. Army Research Laboratory (ARL), Adelphi, MD 20783 U.S.A

a*mtorky@albany.edu, b  jmlynch@albany.edu, c  nyun@albany.edu, d  smancini@albany.edu, e miguel.hinojosa4.civ@army.mil, f aivars.j.lelis.civ@mail.mil, 9 wsung@albany.edu

Keywords: ultra-high-voltage, ion implantation, lateral straggle, TCAD simulation, edge termination techniques.

Abstract

Achieving reliable breakdown in ultra-high-voltage ( >10kV ) SiC devices is limited by edge termination design, where low epitaxial doping ( ~4×1014 cm−3 ) results in lateral straggle to be more prominent, therefore necessitating wider spacing between Aluminum implants in conventional floating field rings (FFRs). This study introduces a background doping modulation (BDM) scheme, incorporating a moderately doped N-type confinement region within P+ rings, enabling tighter spacing without added process complexity for high-voltage MOSFETs. Fabricated BDM-FFRs achieved >13kV breakdown ( 30% higher than conventional FFRs), with leakage current <10nA at 10 kV , while reducing termination area by 18.6%. Therefore, the BDM-FFR demonstrates a scalable, and high-performance edge termination approach for next-generation ultra-high-voltage SiC devices.

Introduction

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Wide bandgap semiconductors such as silicon carbide ( 4H−SiC ) have emerged as the most promising candidates for next-generation high-voltage and high-efficiency power devices. The materials' superior material properties, wide bandgap, high critical electric field, and excellent thermal conductivity enable devices capable of blocking voltages beyond 10 kV while operating with reduced conduction and switching losses. Such performance is critical for high-voltage direct current (HVDC) transmission, traction inverters, grid integration of renewable energy, and pulsed power systems [1]. Despite significant progress in device fabrication, the realization of reliable and reproducible breakdown voltages (BV) in ultra-high-voltage ( >10kV ) devices remains challenging. A major limitation is the design of edge termination structures, which must suppress electric field crowding at the active area to achieve close-to-theoretical breakdown performance [2]. Conventional termination schemes-including floating field rings [3], junction termination extension (JTE) [4], and a hybrid combination of both designs [5] are widely adopted. In ultra-high-voltage SiC devices, the drift layer is typically thick ( >100μ m ) and lightly doped ( ~4×1014 cm−3 ), which strongly impacts edge termination design. The low doping makes the lateral dopant straggle more prominent, degrading electric field control in conventional FFR structures and requiring wider ring spacing. To accommodate lateral and vertical depletion, the termination width must generally exceed five times the epi thickness, making it a dominant factor in total chip size. A proposed background doping modulation (BDM) ensures a reduced edge termination design that can significantly minimize the lateral straggle, reducing the chip size and hence the chip cost, through improving the blocking characteristics with small spacings.

Edge Termination Theory and Background

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The ideal breakdown voltage of a one-dimensional p-n junction is determined by the peak electric field within the device, influenced by drift layer thickness and doping. Once the peak electric field
reaches the critical electric field of SiC , avalanche breakdown occurs. However, in real devices, field crowding at the active area limits the actual breakdown to ~70−80% of the theoretical value. To mitigate this, edge termination structures are implemented to spread the depletion region laterally and smooth out the electric field distribution. Among various approaches, floating field rings (FFRs) are particularly attractive for high-voltage applications due to their simplicity, scalability, and compatibility with both diode and MOSFET structures. They consist of multiple concentric P+ implanted rings surrounding the active region. The rings gradually drop the potential from the active junction edge to the device periphery, thereby reducing the peak field. However, the effectiveness of FFRs depends critically on ring spacing and dopant profiles, which are strongly influenced by the low doped background.

In 4H-SiC with very low background doping, implanted dopants undergo significant lateral diffusion and straggle [6]. This smearing of ring edges compromises the field distribution and requires increased spacing between rings ( ≥1μ m ). For devices with a hundred rings, this can cause the termination width to extend to nearly 1 mm , which is prohibitive for compact high-current devices. Furthermore, too-small spacing can lead to premature breakdown due to field crowding at ring corners, while too-large spacing results in incomplete field modulation and premature breakdown due to field crowding at the cylindrical junction in the active area [2].

In 10 kV -class SiC devices, edge terminations can occupy ~80% of chip area for a 1 A -rated device and ~50% for a 10 A-rated device, as shown in Fig. 1, reducing current density, increasing cost per ampere, and limiting scalability. To address these issues, this work proposes a novel approach by adding N-type doping within the FFR structure, resulting in background doping modulation (BDM-FFR). By intentionally pre-doping a moderately N-type region before the implantation of the floating field rings, the lateral straggle is suppressed, enabling tighter ring spacing without field crowding [7]. This results in more compact termination, higher breakdown voltage, and reduced leakage current compared to conventional FFR designs.

[picture]

Fig. 1. Edge termination percentage as a function of breakdown voltage for different current ratings.

Fig. 1. Edge termination percentage as a function of breakdown voltage for different current ratings.

Fig. 2 and 3 show the structural differences between the conventional and proposed FFRs. It should be noted that the proposed BDM-FFRs do not require high energy implantation as the primary goal is to accomplish narrow spacing design between P+ concentric rings without increasing the electric field at their corners. Notably, this additional N-type implantation can coincide with the JFET region in standard MOSFET process flows, allowing seamless integration of the proposed structure without adding process complexity. In the case of Schottky or JBS diodes, however, an additional implantation step would be required.

[picture]

Fig. 2. (a) Top and (b) cross-sectional views of conventional FFRs.

Fig. 2. (a) Top and (b) cross-sectional views of conventional FFRs.

[picture]

Fig. 3. (a) Top and (b) cross-sectional views of the proposed BDM-FFRs.

Fig. 3. (a) Top and (b) cross-sectional views of the proposed BDM-FFRs.

Edge Termination Fabrication

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PiN diodes with three different edge terminations designs were fabricated on a 6-inch wafer with a drift layer thickness of 125μ m and N-type doping concentration of 4×1014 cm−3 enabling >10kV blocking capabilities. Nitrogen implantation was used for implanting the background doping modulation (BDM) layer, while high temperature aluminum and nitrogen implantation was used for the P+ rings and the channel stop as shown in Fig. 2 and 3. After implantation, dopants are activated thermally at 1605∘C for 10 min . with a carbon cap. Three different edge termination designs were fabricated; one PiN diode has BDM-FFR with a ring width of 5μ m and a spacing of 0.8μ m. The other two PiN diodes have a conventional FFR design with a ring width of 3μ m and a spacing of 1 μm and 1.5μ m respectively to account for the lateral straggle due to the low doped background.

Table 1. Structural parameters for BDM-FFR, FFR1 and FFR2 devices.

Structural Parameters | BDM-FFR | FFR 1 | FFR 2
BDM | Yes | No | No
W [μm] | 5 | 3 | 3
S₀ [μm] | 0.8 | 1 | 1.5
Si [μm] | 0.03 | 0.1 | 0.05
n | 100 | 100 | 120
L [μm] | 728.5 | 895 | 897

Table 1 illustrates the structural parameters for BDM-FFR and the two conventional FFRs. The nth  spacing between rings as a function of ring number is given by,

Sn=S0+(n+1)Si(1)

where S0 is the initial spacing, n is the number of rings and Si is the spacing increment. Fig. 4 illustrates the simulated doping profiles of both the BDM ( N -type) and P+ rings where the BDM doping is a 2×1016 cm−3 box profile.

[picture]

Fig. 4. BDM (N-type) and P+ implantation profiles used in our study from Sentaurus TCAD simulation.

Fig. 4. BDM (N-type) and P+ implantation profiles used in our study from Sentaurus TCAD simulation.

Results and Discussion

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As shown in Fig. 5 (a) and (b), cross-sectional imaging using Focused Ion Beam (FIB) and SEM confirmed the effectiveness of BDM with a minimal lateral straggle. BDM-FFR rings exhibit sharp boundaries with negligible lateral straggle even at increased depth, while conventional FFRs suffer from substantial smearing and overlap between adjacent rings. Conventional FFRs suffer from lateral straggle with 43% increase in the P+ width, which has been validated by TCAD simulation as shown in Fig. 6. Consequently, we designed the spacings of the conventional FFRs as illustrated in Table 1 to account for the lateral straggle at the expense of the edge termination width.

[picture]

Fig. 5. SEM FIB cross-sectional view for (a) BDM-FFR and (b) conventional FFRs. Numbers inside parentheses denote the designed spacings.

Fig. 5. SEM FIB cross-sectional view for (a) BDM-FFR and (b) conventional FFRs. Numbers inside parentheses denote the designed spacings.

[picture]

Fig. 6. Sentaurus simulation cross-sectional schematic showing the lateral straggle between (a) BDM-FFR and (b) conventional FFRs.

Fig. 6. Sentaurus simulation cross-sectional schematic showing the lateral straggle between (a) BDM-FFR and (b) conventional FFRs.

Wafer-level electrical characterization was performed using Keithley high-voltage probe stations. The breakdown voltage was defined at a leakage current of 100μ A, and leakage characteristics were measured up to 10 kV . Fig. 7 shows the blocking characteristics of FFR1, FFR2, and BDM-FFR. The BDM-FFR achieved a blocking voltage of 12.5 kV , approximately 24% higher than conventional FFR devices, which have a breakdown voltage of 10 and 10.7 kV , respectively. These results demonstrate the improved field control and reduced corner crowding afforded by the BDM-FFR technology, as it has wider rings and controlled spacings between rings due to the minimized lateral straggle. At 10 kV , BDM-FFR exhibited leakage currents of only 2 nA , three orders of magnitude lower than FFR1, which has a leakage current of 8μ A, and a 91% lower leakage in the case of FFR2, which has a leakage of 23 nA . The high leakage in FFR1 is attributed to insufficient ring separation (1μ m), leading to premature conduction and leakage paths. Although the P+ ring width of the BDMFFR is 5μ m compared to conventional FFRs, the termination length (L) of BDM-FFR is only 728.5 μm, compared to ~895μ m for conventional FFRs, an 18.6% total area reduction. This reduction in total area is crucial for scaling to high-current devices where chip area directly impacts cost and manufacturability. The confinement layer limits lateral dopant struggle, thereby stabilizing potential distribution across the rings. This enables narrow ring spacing without excessive electric field concentration at ring corners, leading to higher BV and lower leakage. Table 2 shows the blocking characteristics for the three devices.

[picture]

Fig. 7. Blocking characteristics of BDM−FFR, FFR 1 and FFR 2.

Fig. 7. Blocking characteristics of B D M − F F R , FFR 1 and FFR 2.

Table 2. Blocking voltage and leakage current for BDM-FFR, FFR1 and FFR2.

Blocking Performance | BDM-FFR (S₀ = 0.8 μm) | FFR 1 (S₀ = 1.0 μm) | FFR 2 (S₀ = 1.5 μm)
BV @ IAK = 10⁻⁵ A [V] | 12.5 | 10 | 10.7
IDSS @ VDS = 10 kV [A] | 2×10⁻⁹ | 8.1×10⁻⁶ | 2.3×10⁻⁸

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

This work demonstrates a novel background doping modulation (BDM) edge termination for ultra-high-voltage ( >10kV ) 4H-SiC power devices. By introducing a confinement layer beneath P+ floating field rings, lateral straggle is suppressed, enabling tighter designs with tight ring spacing. Compared to conventional FFRs, BDM-FFR achieved a breakdown voltage of 12.5kV(24% improvement), leakage currents <10nA at 10 kV , and termination width reduction of ~18.6%. These results provide clear evidence that BDM offers a scalable, manufacturable, and high-performance solution for edge termination in next generation SiC power devices. Future work will extend this approach to devices beyond 15 kV and explore integration in power modules for high-current applications.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

The authors would like to thank ADI for fabricating the devices. We also would like to thank Alexander Bialy and Cobert Johnson from NY CREATES for helping in taking FIB and SEM images in Fig. 5.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

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B. J. Baliga, Fundamentals of Power Semiconductor Devices. New York, NY, USA: Springer, 2008, Chap. 3, pp. 91-162.

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W. Sung, E. V. Brunt, B. J. Baliga, A. Q. Huang, A New Edge Termination Technique for High-Voltage Devices in 4H-SiC-Multiple-Floating-Zone Junction Termination Extension, IEEE Transaction on Electron Devices, 32 (7) (2011) 880-882.

W. Sung, B. J. Baliga, A Near Ideal Edge Termination Technique for 4500V 4H-SiC Devices: the Hybrid Junction Termination Extension (Hybrid-JTE), IEEE Transaction on Electron Devices, 37 (12) (2016) 1609-1612.

J. Lynch, N. Yun, W. Sung, Design Considerations for High Voltage SiC Power Devices: An Experimental Investigation into Channel Pinching of 10 kV SiC Junction Barrier Schottky (JBS) Diodes, 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China, (2019) 223-226.

N. Yun, D. Kim, J. Lynch, A. J. Morgan, W. Sung, M. Kang, A. Agarwal, R. Green, A. Lelis, Developing 13-kV 4H-SiC MOSFETs: Significance of Implant Straggle, Channel Design, and MOS Process on Static Performance, IEEE Transaction on Electron Devices, 67 (10) (2020) 4346-4353.

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The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 61-67

doi: 10.4028/p-S3kheK

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-19

Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Minori Matsuoka 1,a*, Daiki Soda 1, b, Kosuke Miyazaki 1,c, Toshikazu Tanioka 1, d, Kazuya Tojima 1,e, Akira Kiyoi 2,f, Yasuhiro Kagawa 1, g and Tetsuya Nitta 1, h

1 Power Device Works, Mitsubishi Electric Corporation,1-1-1 Imajuku-higashi, Nishi-ku, Fukuoka-shi, Fukuoka, 819-0192, Japan

2 Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki-shi, Hyogo, 661-8661, Japan

a* Matsuoka.Minori@db.mitsubishielectric.co.jp, b Soda.Daiki@dc.MitsubishiElectric.co.jp, c Miyazaki.Kosuke@dw.MitsubishiElectric.co.jp, d Tanioka.Toshikazu@eb.MitsubishiElectric.co.jp,

e Ishibashi.Kazuya@ak.MitsubishiElectric.co.jp, f Kiyoi.Akira@ay.MitsubishiElectric.co.jp,

9  Kagawa.Yasuhiro@cj.mitsubishielectric.co.jp, h  Nitta.Tetsuya@ea.MitsubishiElectric.co.jp

Keywords: MOSFET, body diode, activation annealing, carbon vacancy, reverse recovery charge, electrical characteristics.

Abstract

A body diode is commonly employed as a free-wheeling diode to reduce costs of SiC components instead of an external Schottky barrier diode. However, one of the key issues is higher reverse recovery loss due to bipolar charge contribution to reverse recovery charge. In this study, we investigated the impact of high-temperature annealing on the characteristics of MOSFETs as a costeffective approach to introduce minority carrier lifetime killers. The trap densities of Z1/2 center and EH6/7 center can be controlled by activation annealing temperature. Qrr of 1900∘C measured at 150∘C was significantly decrease by 67% compared to that of 1750∘C attributed to the 89% suppression of Qbip . However, reverse leakage current increased adversely with the activation annealing temperature. Ron  and Vth  increased with the activation annealing temperature. The trade-off of the annealing temperature worsened slightly compared to that of the doping concentration. It is still possible that high-temperature annealing represents a cost-effective approach to improve the reverse recovery characteristics of the body diode.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Silicon carbide ( SiC ) is a suitable material for power devices due to its superior properties such as wide bandgap, high critical electric field, and high thermal conductivity. A body diode is a parasitic p-n diode within a MOSFET structure. In typical switching applications, a body diode is commonly employed as a free-wheeling diode to reduce costs of SiC components instead of an external Schottky barrier diode. The use of the body diode can contribute to cost reduction in SiC components and system miniaturization. However, there are several issues related to the use of the body diode. One of the key issues is a higher reverse recovery loss due to the contribution of bipolar charge ( QBIP ) to the reverse recovery charge ( Qrr ). The recovery current when using the body diode is larger than that when using an external Schottky barrier diode. This is attributed to the fact that QBIP is significantly large due to the body diode being a bipolar device. One measure to reduce the reverse recovery loss is introducing minority carrier lifetime killers. It is known that Z1/2 center is the most representative carrier lifetime killer in n-type 4H−SiC[1]. Z1/2 center and EH6/7 center [2] are identified as traps caused by carbon vacancies [3]. Methods for generating carbon vacancies include electron irradiation [4,5], proton irradiation [6,7], and high-temperature annealing [8]. Electron irradiation and Proton irradiation need additional processes and equipment, while high-temperature activation annealing can potentially introduce carrier lifetime killers without additional processes or equipment, making it cost-effective. This is because the activation of the ion implantation layers needs annealing at temperatures above 1600∘C, allowing for the simultaneous introduction of lifetime killers [9]. Few
studies have reported on the reverse recovery loss of the body diode related to high-temperature activation annealing. Therefore, we investigated the effect of the activation annealing temperature on electrical characteristics of SiC-MOSFETs.

Experiment

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Figure 1 shows the cross-sectional schematics of fabricated SiC planar MOSFETs with 1.7 kV rating on n-type 4H−SiC(0001) wafer. The off-cut angle of the wafer is 4∘. Figure 2 illustrates the MOSFETs fabrication processing flow. After the ion implantation process, these MOSFETs were annealed in Ar atmosphere with a carbon cap. The processing temperatures were set at 1750∘C, 1800∘C and 1900∘C, respectively. The duration at the set temperature was the same. Subsequently, the gate oxidation and the metallization were carried out. The fabricated MOSFETs were evaluated for the trap density of Z1/2 center and EH6/7 center around the PN junction measured by deep level transient spectroscopy (DLTS). Afterwards, we measured the reverse recovery characteristics, reverse leakage current characteristics, and on-state characteristics of the MOSFETs. Typical data were plotted for each activation annealing temperature in the following Figs. 3-8 ,10.

[picture]

Fig. 1. Cross-sectional schematic diagram of the planar SiC-MOSFET.

Fig. 1. Cross-sectional schematic diagram of the planar SiC-MOSFET.

[picture]

Fig. 2. The MOSFETs fabrication processing flow. The activation annealing temperatures were set at 1750∘C,1800∘C and 1900∘C, respectively.

Fig. 2. The MOSFETs fabrication processing flow. The activation annealing temperatures were set at 1750 ∘ C , 1800 ∘ C and 1900 ∘ C , respectively.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Figure 3 shows the trap densities of Z1/2 center and EH6/7 center calculated from DLTS spectra. DLTS measurement conditions are as follows: reverse bias of -30 V , pulse bias of -15 V and a rate window of 192 ms , with G-S shorted. The DLTS spectrum has two peaks at positions of 300 K and 678 K , which are related to the Z1/2 center and EH6/7 center. The defect densities at 1900∘C are significantly increased compared to 1750∘C and 1800∘C. Figures 4 shows the dependence of trap densities on the activation annealing temperature. The trap densities of both Z1/2 center and EH6/7 center increase exponentially with the activation annealing temperature, reaching approximately 1014/cm3 at 1900∘C. These results suggest that the trap densities of Z1/2 center and EH6/7 center can be efficiently controlled by adjusting annealing temperature.

[picture]

Fig. 3. Trap density calculated from DLTS spectrum.

Fig. 3. Trap density calculated from DLTS spectrum.

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Fig. 4. Dependency of activation annealing temperature on trap density.

Fig. 4. Dependency of activation annealing temperature on trap density.

Figures 5(a) and 5(b) show the typical reverse recovery waveforms at 25∘C and 150∘C. The reverse recovery characteristics were measured with the double pulse testing method, and the supply voltage and switching drain-source current are 900 V and 265 A/cm2, respectively. The gate voltages of the upper arm and the lower arm are -7 V and −7/+15 V, respectively. At 25∘C, there is almost no difference among the three waveforms, and the reverse recovery currents are independent of the activation annealing temperatures. On the other hand, at 150∘C, the reverse recovery current decreases dramatically from 176 A/cm2 to 131 A/cm2 between 1750∘C and 1900∘C. The reverse recovery charge ( Qrr ) is defined in accordance with JEP201 published by JEDEC as follows,

Qrr=QBIP+QOSSQrr=−∫t0t1Jbddt

(1)(2)

where t0 is defined as the moment when the current density reaches zero, and t1 is defined as the point when the drain voltage reaches 98%. The reverse recovery charge ( Qrr ) was then calculated from the current density between these two time points.

[picture]

Fig. 5. Typical reverse recovery waveforms of the body diode current Jbd  (a) at 25∘C and (b) at 150∘C.

Fig. 5. Typical reverse recovery waveforms of the body diode current J bd (a) at 25 ∘ C and (b) at 150 ∘ C .

Figures 6(a) and 6(b) show the composition of Qrr for each annealing temperature (a) at 25∘C and (b) at 150∘C. The capacitive charge ( Q oss) is independent of the activation annealing temperature. At 25∘C,Qrr and QBIP of 1900∘C is reduced by 13% and 51% compared to that of 1750∘C, respectively. At 150∘C,QBIP  is reduced significantly with the activation annealing temperature. Qrr  of 1900∘C is reduced by 67% compared to 1750∘C attributed to the 89% suppression of Qbip . This suggests that the carrier lifetime of 1900∘C is significantly decreased at 150∘C. Therefore, high-temperature annealing represents an effective method to improve the reverse recovery characteristics of the body diode.

[picture]

Fig. 6. Composition of Qrr for each annealing temperature (a) at 25∘C and (b) at 150∘C.

Fig. 6. Composition of Q r r for each annealing temperature (a) at 25 ∘ C and (b) at 150 ∘ C .

Figures 7(a) and 7(b) show the typical reverse leakage waveforms at 25∘C and 150∘C. A sourcegate voltage ( VGS ) of -7 V is applied. The reverse leakage current increases adversely with the activation annealing temperature both at 25∘C and 150∘C. The reverse leakage current characteristics are nearly the same at 1750∘C and 1800∘C, while the reverse leakage current at 1700 V increases by an order of magnitude at 1900∘C.

[picture]

Fig. 7. Typical reverse leakage characteristics for the SiC -MOSFETs with various activation annealing temperature of VGS=−7 V (a) at 25∘C and (b) at 150∘C.

Fig. 7. Typical reverse leakage characteristics for the SiC -MOSFETs with various activation annealing temperature of V G S = − 7 V (a) at 25 ∘ C and (b) at 150 ∘ C .

To confirm the impact of the Z1/2 center and EH6/7 center on the reverse recovery characteristics, TCAD simulations were conducted in three different cases. Figure 8(a)-(c) show simulation results of reverse recovery waveform at 150∘C (a) with only Z1/2 center, (b) with only EH6/7 center and (c) with both Z1/2 center and EH6/7 center. The trap density, energy and cross-section obtained from DLTS are utilized to simulation parameters as shown in Table 1. In the simulation utilizing with only Z1/2 center (Fig. 8(a)), both the reverse recovery current and the reverse recovery time decrease with increasing the activation annealing temperature. The reverse recovery current and the recovery time in the simulation utilizing only EH6/7 center (Fig. 8(b)) show no significant dependence on the activation annealing temperature. In the simulation utilizing Z1/2 center and EH6/7 center (Fig. 8(c)), the reverse recovery waveforms exhibited a trend similar to those obtained with the Z1/2 center. This trend is also consistent with the measured reverse recovery characteristics. Therefore, we speculate that reverse recovery current is strongly dependent on the density of Z1/2 center.

Table 1. Simulation parameters obtained by DLTS.

trap | Energy [eV] | σe [cm²]
Z1/2 | EC-0.63 | 1.66e-15
EH6/7 | EC-1.44 | 3.39e-16

[picture]

Fig. 8. Simulation results of reverse recovery waveform at 150∘C (a) with Z1/2 center, (b) with EH6/7 center and (c) with Z1/2 center and EH6/7 center.

Fig. 8. Simulation results of reverse recovery waveform at 150 ∘ C (a) with Z 1 / 2 center, (b) with E H 6 / 7 center and (c) with Z 1 / 2 center and E H 6 / 7 center.

Figure 9(a)-(c) show the simulation results of the reverse recovery waveform at 150∘C (a) with Z1/2 center, (b) with only EH6/7 center and (c) with both of Z1/2 center and EH6/7 center. In the simulation utilizing only Z1/2 center (Fig. 9(a)), the reverse leakage current shows slightly dependence on the activation annealing temperature. The reverse leakage current in the simulation utilizing only EH6/7 center (Fig. 9(b)) increases with activation annealing temperature. In the simulation utilizing Z1/2 center and EH6/7 center (Fig.9(c)), the reverse leakage current exhibit a trend like those obtained with the EH6/7 center alone. This trend is also consistent with the measured reverse leakage current characteristics. Therefore, we speculate that the reverse leakage current is strongly dependent on the density of EH6/7 center.

[picture]

Fig. 9. Simulation of off-state I-V characteristics at 150∘C (a) with Z1/2 center, (b) with EH6/7 center and (c) with Z1/2 center and EH6/7 center.

Fig. 9. Simulation of off-state I-V characteristics at 150 ∘ C (a) with Z 1 / 2 center, (b) with E H 6 / 7 center and (c) with Z 1 / 2 center and E H 6 / 7 center.

Figure 10(a) and (b) shows trade-off between on-resistance Ron  and threshold voltage Vth  of 25∘C (a) at 25∘C and (b) 150∘C. Ron  and Vth  increase with high-temperature annealing because the net accepter concentration increases. However, there is a slight difference between the trade-off of the activation annealing temperature and that of doping concentration. It suggests that there are other factors that contribute to the increase in on-resistance.

[picture]

Fig. 10. Trade-off of activation annealing temperature and doping concentration between threshold voltage Vth  at 25∘C and on-resistance Ron  (a) at 25∘C and (b) at 150∘C.

Fig. 10. Trade-off of activation annealing temperature and doping concentration between threshold voltage V th at 25 ∘ C and on-resistance R on (a) at 25 ∘ C and (b) at 150 ∘ C .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

We investigated the impact of high-temperature annealing on the characteristics of MOSFETs as a cost-effective approach to introduce carrier lifetime killers for reverse recovery suppression. The trap densities of Z1/2 center and EH6/7 center were controlled up to approximately 1014/cm3 through the activation annealing temperature. Qrr of 1900∘C was reduced compared to that of 1750∘C, attributed to the significant suppression of QBIP . However, the reverse leakage current increased adversely with the activation annealing temperature. The trade-off between Ron  and Vth  of annealing temperature worsened slightly compared to that of doping concentration.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

K. Danno, T. Hori and T. Kimoto, Impacts of growth parameters on deep levels in n-type 4HSiC, J. Appl. Phys. 101, 053709 (2007).

N. T. Son, X. T. Trinh, L. S. Løvlie, B. G. Svensson, K. Kawahara, J. Suda, T. Kimoto, T. Umeda, J. Isoya, T. Makino, T. Ohshima, and E. Janze, Negative- System of Carbon Vacancy in -SiC, Phys. Rev. Lett. 109, 187603 (2012).

G. Alfieri and T. Kimoto, Resolving the level in 4H-SiC by Laplace-transform deep level transient spectroscopy, Appl. Phys. Lett. 102, 152108 (2013).

P. Dong, Y. Qin, X. Yu, X. Xu, Z. Chen and L. Li, Electron Radiation Effects on the PiN Diodes Characteristics: An Insight from Point Defects to Electrical Degradation, IEEE Access. 7, 170385 (2019).

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A Castaldini, A Cavallini and L Rigutti Assessment of the intrinsic nature of deep level by compensation effects in proton-irradiated 4H-SiC, Semicond. Sci. Technol. 21 (2006) 724728.

P. Hazdra and S. Popelka, Optimization of SiC Power p-i-n Diode Parameters by Proton Irradiation, IEEE Access. 65, 4483 (2018).

E. Saito, J. Suda and T. Kimoto, Control of carrier lifetime of thick n-type 4H-SiC epilayers by high-temperature Ar annealing, Appl. Phys. Exp. 9, 061303 (2016).

M. Spera, D. Corso, S. Di Franco, G. Greco, A. Severino, P. Fiorenza, F. Giannazzo and F. Roccaforte, Effect of high temperature annealing ( ) on the morphological and electrical properties of p-type implanted 4H-SiC layers, . Mater. Sci. Semicond. Proc. 93 (2019) 274-279.

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The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 69-73

doi: 10.4028/p-5ozE8T

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-15

Revised:
2025-12-23

Accepted:
2026-02-26

Online:
2026-05-19

4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

Virginia Boldrini 1,a, Marica Canino 1, b*, Marco Pieruccini 1,c,Vincenzo Carrano 2, d, Heinz C. Neitzert 2,4,e, Luigi Di Benedetto 2,f, Claudio Santonastaso 3,4,5,g, Raffaele Buompane 3,4,h, Maria Lucia Mitsou 3,4,i, Nicola Casali 6,j, Ravi Prakash Yadav 6,k, Matthias Laubenstein 7,I, Cristian Degli Esposti Boschi 1, m, Alfredo Rubino 2,n, Alba Formicola 6,o, Lucio Gialanella 3,4,p

1 CNR - ISMN Bologna Section, Via P. Gobetti 101, 40129 Bologna, Italy

2 Dip. Ingegneria Industriale Università degli Studi di Salerno - Salerno, Italy

3 Dip. Matematica e Fisica, Univ. della Campania "L. Vanvitelli" - Caserta, Italy

4 Istituto Nazionale di Fisica Nucleare, Sezione di Napoli - Napoli, Italy

5 RIKEN Nishina Center, Wako, Saitama, Japan

6 INFN - Dip. di Fisica "G. Marconi" Piazzale Aldo Moro 2, 00185, Roma, Italy

7 INFN - Lab. Naz. del Gran Sasso, Via G. Acitelli 20, Assergi - L'Aquila, Italy

a  virginia.boldrini@cnr.it, b  mariaconcetta.canino@cnr.it, c  marco.pieruccini@cnr.it,

d vcarrano@unisa.it, e neitzert@unisa.it, f Idibenedetto@unisa.it, g claudio.santonastaso@riken.jp, h raffaele.buompane@unicampania.it, imarialucia.mitsou@unicampania.it,

j  nicola.casali@roma1.infn.it, k  raviprakash.yadav@roma1.infn.it, 'matthias.laubenstein@Ings.infn.it,

m cristian.degliespostiboschi@cnr.it, n arubino@unisa.it, a alba.formicola@roma1.infn.it, plucio.gialanella@unicampania.it

Abstract

This study presents the design, fabrication, and electrical characterization of 4H−SiCp+/n diodes employed to provide a high electric field able to induce Stark effect in 7Be atoms implanted in the space charge region. Indeed, a variation in the half-life of the 7Be radioactive decay is expected to be achieved by applying an electric field of the order of 106 V/cm, which can be produced by reverse-biasing 4H−SiC diodes close to the breakdown voltage. A set of diodes of area ranging between 2.12×10−3 cm2 and 9.88×10−3 cm2 was designed and fabricated to reach breakdown voltages up to 1000 V . When tested under reverse current limitation set equal to 300 nA , over 50% out of 24 devices could withstand reverse bias exceeding 800 V . This work reports on the characteristics of one diode of 9.88×10−3 cm2 area, implanted with 7Be and subject to continuous reverse-bias at 750 V for 107 days. Electrical characterization conducted before, during, and after long-term polarization highlighted an increase in the reverse current generation due to implantation-related defects, which however does not affect the breakdown voltage. These considerations lead to the conclusion that the electric field acting on the implanted 7Be remains stable over time, confirming the suitability of 4H−SiC diodes for both induction and measurement of 7Be lifetime variations.

Keywords: 4H−SiC,p+/n diodes, high voltage reverse current, Be ion implantation, radioactive decay.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

This work focuses on a novel application of 4H−SiC diodes, i.e. their use to provide the electric field required to demonstrate the Stark effect in the radioactive decay of 7Be atoms implanted in the depletion region of a p/n junction. Indeed, a precise measurement of the 7Be half-life in 4H−SiC resulted in ( 53.284±0.016 ) days at zero bias [1]; this value can vary by applying a high reverse bias resulting in an electric field of the order of 106 V/cm[2].4H-SiC represents the material of choice to
conduct such experiment thanks to its high critical electric field and to its tolerance to ion implantation processes. Electrical characterizations, performed by current-voltage (I-V) and capacitance-voltage (C-V) at different fabrication stages, as well as after a high number of radioactive decay events, allow to demonstrate the suitability of 4H−SiC diodes as environment to host ion implanted 7Be atoms while maintaining their blocking capabilities under prolonged high reverse bias operation. Furthermore, identifying the mechanisms of reverse current conduction enables the assessment of electric field stability and sets the basis for result interpretation.

Experimental

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p+/n diodes were realized starting from a 4H−SiC wafer purchased from II-VI, with a 6μ m thick, 1×1016 cm−3 n-type doped epitaxial layer and 2μ m buffer layer. The epitaxial layer thickness and doping were determined by Synopsys TCAD Sentaurus simulations to obtain the required electric field in the 7Be implanted region of around 1MV/cm at -750 V . Al ion implantation followed by 1950∘C30 min annealing led to the formation of the anode and JTE regions extending 350 nm below the sample surface with 5×1019 cm−3 and 1.25×1017 cm−3Al concentration respectively. The front side ohmic contact was made by thin Ti,Al, and Ni layers alloyed in vacuum at 1100∘C for 5 min . A first round of characterization by I-V and C-V was performed in the as-made diodes to select the diode exhibiting the lowest current at 900 V reverse bias, but it is not reported in this work. The chosen device had an anode area equal to 9.88×10−3 cm2.
High energy 7Be ion implantation was performed at the Tandem Accelerator Laboratory, DMF, University of Campania. The beam energy during the implantation was modulated to obtain a boxshaped depth profile with 1×1016 cm−37Be concentration extending between 2.8μ m and 4μ m below the sample surface. A double AZ10XT photoresist layer was used as mask to selectively implant 7Be in the inner region of the diode in a circular area of 960μ m diameter. At 750 V reverse bias the electric field value in the region comprising 7Be is expected to be (1.3±0.2)MV/cm. The diode layout is shown in Fig. 1.

[picture]

Fig. 1. Layout of the epitaxial layer. The horizontal axis scale is in micron, while the vertical axis is not in scale. The grey area represents the 7Be implanted region.

Fig. 1. Layout of the epitaxial layer. The horizontal axis scale is in micron, while the vertical axis is not in scale. The grey area represents the 7 B e implanted region.

750 V reverse bias was applied for 107 days at Gran Sasso National Laboratories (LNGS, Italy) on the wire-bonded device to measure the 7Be decay time in a high electric field. The current flowing through the diode was continuously monitored throughout the progress of the experiment. Finally, IV and C−V curves were acquired after the experiment.

Results and Discussion

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The high-voltage I-V curves measured in the as-made diodes (called first round measurements) and at the end of the experiment (final measurements), i.e. after 7Be ion implantation and 107 days of reverse bias operation, are shown in Figure 2. Figure 3 shows the corresponding C-V curves at 100 kHz (a) together with the ND vs W plot (b). The final forward I-V characteristics (Fig. 2a) shows a
single exponential slope over more than 6 decades even if with an increase of recombination current, while the reverse bias, though experiencing an increase following the 7Be implantation and the longterm reverse bias, maintains its blocking behaviour. After 107 days a current reduction is observed. For 4H−SiC PiN diodes it has been demonstrated that displacement damage caused by irradiation (thus likely also by ion implantation), can induce an increase in carrier recombination due to lifetimekiller defects (affecting forward I-V characteristic), an increase in generation current (causing reverse leakage), the compensation of n-type region due to acceptor centers and a decrease in carrier mobility caused by scattering [3,4]. After Be implantation the observed increase in reverse current can be ascribed to charge generation at centers within the bandgap induced by defects, but a fairly preserved blocking capability.

[picture]

Fig. 2. Forward (a) and reverse (b) current flowing in the as-made diodes (first round, black circles) and after 7Be ion implantation and 107-days continuous polarization at -750 V (final, red squares); high voltage reverse current density in as-made diodes, after 7Be ion implantation (blue triangles) and after long-term bias.

Fig. 2. Forward (a) and reverse (b) current flowing in the as-made diodes (first round, black circles) and after 7 B e ion implantation and 107-days continuous polarization at -750 V (final, red squares); high voltage reverse current density in as-made diodes, after 7 B e ion implantation (blue triangles) and after long-term bias.

[picture]

Fig. 3. C-V curves measured (a) in the as-made diodes (first round, black open circles), after 7Be ion implantation (*different device and different implantation sequence, blue triangles), and 107 days continuous polarization at -750 V (final, red squares); calculated doping concentration in the depletion layer width (b).

Fig. 3. C-V curves measured (a) in the as-made diodes (first round, black open circles), after 7 B e ion implantation (*different device and different implantation sequence, blue triangles), and 107 days continuous polarization at -750 V (final, red squares); calculated doping concentration in the depletion layer width (b).

Fig. 3a shows the C-V curves of the diode under study in the final round (black open circles) and at the final stage of the experiment (red circles), together with the C−V curve of a p+/n diode with the same geometry in the as-implanted stage (blue triangles); the latter underwent a different 7Be ion
implantation sequence, achieving a higher 7Be concentration (i.e. 4×1016 cm−3 ), so that the C−V curves of the implanted diodes are not directly comparable. Nevertheless, it is apparent that the capacitance undergoes a decrease after the 7Be ion implantation process. Fig 3b shows the doping profile in the depletion region calculated from the C−V curves. The region probed by the measurement is expected to correspond to a depth comprised between 1.5μ m and 3.5μ m below the sample surface, under the hypothesis of an Al implant tail as long as 1μ m. The first round of measurements yields doping values in the as-grown diodes close to the nominal concentration. The apparent donor profile at the final stage shows a decrease close to the junction, that tends to approach the nominal value while probing deeper inside the space-charge region. It is worth to remark that the quantitative analysis of the C-V curve of the as-implanted diodes was carried out by considering the whole diode area, whereas the 7Be ion implantation is restricted to a selected portion of the diode area. Consequently, the reported concentration has only a qualitative validity. Since the location featuring dopant deactivation is shallower than the 7Be projected range, the observed capacitance decrease is not related either with ion implantation damage induced by nuclear scattering at the 7Be projected range, nor to compensation by 7Be. More likely, it can be attributed to the deactivation occurring close to the junction, where the Al implant tail results in lighter net doping. In this region, even a small amount of irradiation defects can induce a non-negligible capacitance decrease. Indeed, this phenomenon was observed in particle- [5, 6] and light-ion [7] irradiated 4H-SiC detectors.

These considerations show that the actual electric field acting on 7Be remains stable and close to its expected value, as i) the capacitance variation occurs after 7Be ion implantation; ii) the calculated epitaxial layer doping levels in the 7 Be region do not show any dramatic change between the first round of measurements and the final stage.

Conclusion

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We reported the design, fabrication, and electrical characterization of 4H−SiCp+/n diodes suitable to provide a high electric field that can induce Stark effect in 7Be atoms implanted in the space charge region. One diode with the best rectifying behaviour at 900 V reverse bias was chosen for the final experiment. I-V measurements showed a single slope forward current with low recombination and a low reverse leakage with a principle of breakdown at 900 V with a current of 3 nA . Such behaviour ensured the possibility of polarizing the device at 750 V thus achieving an electric field of about (1.3±0.2)MV/cm in the region were 7Be will be implanted. After 7Be ion-implantation and a continuous reverse bias at 750 V for 107 days, the repeated I-V and C-V measurements showed that the electrical properties of the device weren't changed substantially. A slight increase in carrier recombination was seen under forward bias, while under reverse bias we observed a higher generation current due to defects left by 7Be ion-implantation. The breakdown voltage didn't visibly lower and since C−V measurements demonstrated a drop in the doping concentration close to the junction but reducing while entering deeper in the space-charge region, it can be affirmed that the actual electric field acting on 7Be remains close to its expected value. This proofs the suitability of 4H−SiC diodes as host material to probe the Stark effect possibly affecting 7Be.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

This work was supported by the Italian Ministry of Research under the PRIN ASBeST Contract No. 2020WN3PBE_003. The authors are grateful to the personnel of ISMN clean room for assistance in process design and execution: Michele Bellettato, Filippo Bonafè, Fabrizio Tamarri, Michele Sanmartin.

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The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

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P. Hazdra; P. Smrkovský; J. Vobecký; A. Mihaila, Radiation Resistance of High-Voltage Silicon and 4H-SiC Power p-i-n Diodes, IEEE TED 68 (2021) 202-207. DOI: 10.1109/TED.2020.3038713.

J.M. Rafí, G. Pellegrini, P. Godignon, S. Otero Ugobono, G. Rius, I. Tsunoda, M. Yoneoka, K. Takakura, G. Kramberger, M. Moll, Electron, Neutron, and Proton Irradiation Effects on SiC Radiation Detectors, IEEE TRANSACTIONS ON NUCLEAR SCIENCE 67 (2020) 2481. DOI: 10.1109/TNS.2020.3029730.

R.L. Gao, X. Du, W.Y. Ma, B. Sun, J.L. Ruan, X. Ouyang, H. Li, L. Chen, L.Y. Liu, X.P. Ouyang, Radiation tolerance analysis of PIN diode detectors for neutron Irradiation, Sensors and Actuators A 333 (2022) 113241. DOI: 10.1016/j.sna.2021.113241.

D. Pellegrino, L. Calcagno, M. Zimbone, S. Di Franco, A. Sciuto, Correlation between Defects and Electrical Performances of Ion-Irradiated 4H-SiC p-n Junctions, Materials 14 (2021) 1966. DOI: .

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 75-79

doi: 10.4028/p-9L9dhm

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-22

Accepted:
2026-02-26

Online:
2026-05-19

Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

Shuiyou Zheng 1,a, Xingjun Luo 2, b and Huaxing Jiang 1,c,*

1 School of Microelectronics, South China University of Technology, Guangzhou, China

2 South China Normal University, Guangzhou, China

a  miwater_friend@mail.scut.edu.cn, b  luoxingjun@m.scnu.edu.cn, c hxjiang@scut.edu.cn;

*corresponding author

Keywords: SiC, Junction Termination Extension, Channeling Implantation, Breakdown Voltage, Process Window.

Abstract

This work reports enhanced high-voltage blocking capability and an enlarged process window for junction termination extension (JTE) in SiC power devices using a hybrid random and channeling implantation for p-type doping (Al), compared with conventional random-only implantation. A three-step hybrid implantation process has been developed to replace a nine-step random implantation, achieving a similar doping profile and equivalent breakdown voltage in the JTE while significantly increasing fabrication productivity and reducing cost. Moreover, TCAD studies reveal that when using the same number of steps and ion energies as the conventional random implantation method, the JTE realized by the channeling-incorporated hybrid approach enables an increased breakdown voltage and a widened dose window in SiC devices. This is attributed to a deeper Al distribution with a lower average concentration, which effectively alleviates electric field crowding.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

The JTE structure is widely employed in SiC power devices to enhance off-state performance and reliability, but its effectiveness critically depends on implantation dose and depth [1,2]. To avoid sharp peaks in the electric field at both the main junction and the edge of the JTE, a deep and uniform dopant profile with a relatively low doping concentration is preferred for the JTE design. However, achieving this with conventional random-only implantation requires costly and time-consuming highenergy multi-step processes. While channeling implantation has offered great potential for creating a deep doping profile in SiC [3,4], its specific application to JTE structures has been underexplored. In this work, combining experimental investigation with TCAD simulation, we propose a hybrid random and channeling implantation technique for JTE formation. Compared with multi-energy random implantation, this hybrid approach achieves a significantly enhanced breakdown voltage and an enlarged process window.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

All samples in this study were fabricated on 4∘ off-axis 6-inch 4H-SiC substrates. A cross-sectional schematic of the fabricated PiN diode with a single-zone JTE design is illustrated in Fig. 1. The epitaxial layer has a thickness of 12μ m and a doping concentration of 1×1016 cm−3. The key fabrication steps are as follows: The P+anode and JTE region were formed via ion implantation. Specifically, random implantation was performed at an elevated temperature, while channeling implantation was conducted at room temperature. After implantation, all samples underwent hightemperature annealing for dopant activation. Subsequent steps included inter-layer dielectric (ILD) deposition, ohmic contact formation, pad metallization, silicon nitride (SiN) passivation, and polyimide coating.

Three groups of devices were fabricated: the first group (Reference sample, denoted as Ref.) employed a nine-step random implantation process with different energies for each step for the JTE; the second (denoted as Condition A) and third (denoted as Condition B) groups utilized a hybrid scheme consisting of two random implantation steps and one channeling implantation step for the JTE formation. The implantation energy for all groups ranged from 120 keV to 2300 keV . For both Conditions A and B , the energies of the two random implantations were 120 keV and 2300 keV , respectively, while the channeling implantation employed an intermediate energy. The total implantation doses were designed to satisfy Condition A < Ref. < Condition B. The electrical characterization of all fabricated devices was subsequently performed using a Keysight B1505A power device analyzer.

[picture]

Fig. 1. Cross-sectional schematic of the fabricated SiC diodes with JTE in this work.

Fig. 1. Cross-sectional schematic of the fabricated SiC diodes with JTE in this work.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

The aluminum (Al) distribution in the JTE implantation regions of the three samples was characterized using secondary ion mass spectrometry (SIMS). As shown in Fig. 2, the depth profiles of Al under all three implantation conditions exhibit nearly consistent dopant concentration distributions.

[picture]

Fig. 2. Comparison of Al depth profiles of SIMS measurement in the JTE structures using random and hybrid implantation.

Fig. 2. Comparison of Al depth profiles of SIMS measurement in the JTE structures using random and hybrid implantation.

Notably, electrical characterization results (Fig. 3(a)) demonstrate that diodes with the JTE structure fabricated using the hybrid implantation scheme exhibit competitive breakdown voltages and
comparable leakage currents to those of the reference. The average breakdown voltages for Conditions A and B, calculated from 18 devices per group, are 1643 V and 1717 V , respectively, both surpassing the reference value of 1630 V (Fig. 3(b)). These results confirm that the incorporation of channeling implantation significantly simplifies the JTE fabrication process without compromising the electrical performance.

[picture]

Fig. 3. (a) Measured reverse I-V characteristics for SiC diodes with different JTE implantation conditions; (b) Breakdown voltage distribution of SiC diodes ( 18 devices per group). Hollow squares denote the mean values, labeled with their respective average voltages of 1630 V,1643 V, and 1717 V .

Fig. 3. (a) Measured reverse I-V characteristics for SiC diodes with different JTE implantation conditions; (b) Breakdown voltage distribution of SiC diodes ( 18 devices per group). Hollow squares denote the mean values, labeled with their respective average voltages of 1630 V , 1643 V , and 1717 V .

Channeling implantation can produce a deep and uniform box-like profile [5], which aligns well with the deep and homogeneous doping distribution required for an effective JTE structure. To further investigate the potential of channeling implantation in optimizing JTE performance, a comparative TCAD simulation study was performed using the device structure shown in Fig. 1. Both implantation schemes maintain the same total dose and implantation energy, with detailed parameters summarized in the table inserted in Fig. 4. In the hybrid scheme, channeling implantation was applied at 370 keV , while random implantation was used at other energies. As illustrated in Fig. 4, despite the same total dose and implantation energy, the hybrid implantation scheme results in a much deeper profile with a lower Al concentration compared to the random implantation approach.

[picture]

Fig. 4. Comparison of simulated Al doping profiles under random-only and hybrid implantation conditions with the same number of implantation steps, energy values, and total dose, along with a detailed summary of the implantation schemes.

Fig. 4. Comparison of simulated Al doping profiles under random-only and hybrid implantation conditions with the same number of implantation steps, energy values, and total dose, along with a detailed summary of the implantation schemes.

Fig. 5 presents the simulated reverse breakdown voltage characteristics of the diodes with JTE using the aforementioned two implantation schemes. The hybrid implantation scheme achieves a much higher breakdown voltage in the device along with a wider dose window for the JTE. This improvement can be attributed to its distinctive dopant distribution characteristics: on the one hand, the deeper implantation profile effectively mitigates electric field crowding at the main junction edge (shown in Fig. 6(a)), thereby increasing the breakdown voltage and extending the lower end of the dose window; on the other hand, under the same total dose, the hybrid scheme yields a lower peak Al concentration, which helps suppress the electric field at the JTE periphery-as validated by the twodimensional electric field distribution shown in Fig. 6(b). As the dose increases, the random implantation scheme suffers from a rapid decrease in breakdown voltage due to a sharp rise in the JTE peripheral electric field. In contrast, the hybrid implantation maintains superior breakdown performance owing to its improved field distribution, thereby extending the upper end of the dose window. In summary, the hybrid implantation scheme facilitates enhanced breakdown voltage and broader process tolerance by producing a deeper and uniform dopant distribution with a low peak concentration.

[picture]

Fig. 5. Simulated results of breakdown voltage as a function of JTE dose in SiC p-n diodes with random and hybrid implantation.

Fig. 5. Simulated results of breakdown voltage as a function of JTE dose in SiC p-n diodes with random and hybrid implantation.

[picture]

Fig. 6. Simulated electric field distributions at 1.2 kV reverse bias in diodes with JTE formed by random-only and hybrid implantation: (a) near the main junction edge, and (b) near the JTE edge.

Fig. 6. Simulated electric field distributions at 1.2 kV reverse bias in diodes with JTE formed by random-only and hybrid implantation: (a) near the main junction edge, and (b) near the JTE edge.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

This study systematically investigates the impact of hybrid implantation technology on the reverse blocking capability of the junction termination extension in 4H−SiC power devices. The proposed approach was thoroughly validated through experimental measurements and TCAD simulations. The results demonstrate that, compared to conventional random-only implantation, the hybrid implantation scheme offers two key advantages: first, with the same maximum implantation energy, it achieves a higher breakdown voltage and a wider dose window; second, in deep JTE applications, the hybrid scheme significantly simplifies the implantation process without degrading the breakdown voltage, thereby effectively reducing manufacturing costs. These findings confirm the potential of hybrid implantation technology to enhance both the electrical performance and cost effectiveness of SiC power devices, providing a reliable and efficient approach for the design of high-performance JTE structures.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

This work was financially supported in part by Guangzhou Municipal Science and Technology Bureau, China under grant 2025A04J5383 and in part by Guangdong Basic and Applied Basic Research Foundation, China under grant 2023A1515011054.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

N. Yun and W. Sung, "Detailed analysis on determining effective dose for various JTE-based edge terminations utilized on 4H−SiC power devices", IEEE Transactions on Electron Devices. 69, 3826 (2022).

B.J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

R. Wada, T. Nagayama, N. Tokoro, T. Kuroi, H. Das, S. Sunkari, and J. Justice, "The exceptional advantages of channeling implantation into to make abrupt deep profiles", Japanese Journal of Applied Physics, 61, SC1033 (2022).

D. Kim, S. de Boer, J. Lynch, S. Jang, A. Morgan, and W. Sung, "Enhancing 1.2 kV 4H-SiC MOSFET Performance and Ruggedness Through Deep P-Well Technology", IEEE International Electron Devices Meeting, p. 1-4 (2024).

Scholze, A. V. Suvorov, D. J. Lichtenwalner, S. Rogers, H. Dixit, and S. H. Ryu, "Calibration of Aluminum Ion Implantation Monte-Carlo Model for TCAD Simulations in ", Solid State Phenomena, 359, 47-51 (2024).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/material-characterisation-and-devices-processing/978-3-0364-3127-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 81-88

doi: 10.4028/p-9BUJBo

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-15

Accepted:
2026-02-26

Online:
2026-05-19

Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

Dinuth C. Y. B. Yapa Mudiyanselage 1,a*, Skylar deBoer 1, b, Stephen A. Mancini 1,c, Justin Lynch 2, d, Seung Yup Jang 2,e, Adam J. Morgan 2,f, Woongje Sung 1,g

¹College of Nanotechnology, Science, and Engineering, University at Albany, State University of New York, Albany, New York, USA

2 NoMIS Power Corporation, Albany, New York, USA

a* dyapamudiyanselage@albany.edu, b sdeboer@albany.edu, c smancini@albany.edu, djustin.lynch@nomispower.com, e  seungyup.jang@nomispower.com, f adam.morgan@nomispower.com, 9 wsung@albany.edu

Keywords: 4 H -SiC MOSFET, N+ source, ion implantation depth, contact resistance, and lateral ion straggle.

Abstract

The heavily doped N+ source region in 4H−SiC MOSFETs is a critical design parameter, as its depth and the profile strongly influence contact resistivity and conduction efficiency. This work investigates the impact of varying N+ implantation depth on the electrical performances of 1.2 kV MOSFETs in both Nominal (linear cell) and Hexagonal (HEXFET) architectures. By varying implantation energy at a fixed dose, three junction depths were obtained: 0.22μ m (shallow), 0.24μ m (moderate), and 0.27μ m (deep). Transfer Length Method (TLM) measurements revealed a significant reduction in source contact resistivity with increasing depth, from 3.91×10−5Ω· cm2 (shallow) to 1.22×10−6Ω· cm2 (deep). For Nominal MOSFET design, electrical measurements confirmed a corresponding decrease in specific on-resistance ( Ron,sp ), from 3.05 to 2.89 mΩ· cm2. However, deeper implants introduced greater lateral straggle, shortening the effective channel length and reducing the threshold voltage ( Vth  ) from 2.25 V to 1.96 V . The channel barrier potential lowering associated with lateral straggle increased leakage current in the blocking mode, resulting in reduced breakdown voltage (BV). For Nominal MOSFETs, BV decreased from 1610 V in the shallow split to 1470 V in the deep split, while HEXFETs exhibited sharper BV degradation due to their higher channel density. To address this limitation, optimized JFET doping was introduced, restoring the BV of the deep split to 1560 V in the Nominal architecture. These results demonstrate that although increased N+ depth improves conduction by lowering contact resistance, careful co-optimization with P-well and JFET design is necessary to suppress high leakage current during blocking mode.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

4H-SiC has emerged as the leading wide bandgap semiconductor for advanced power electronics, offering a wide bandgap of 3.26 eV , a high critical electric field of approximately 3 MV/cm, and excellent thermal conductivity. These material advantages enable MOSFETs with significantly lower conduction and switching losses compared to silicon, while also supporting high temperature and high frequency operation. Today, 4 H -SiC MOSFETs are used in a broad range of automotive, industrial, and renewable energy applications, with 1.2 kV devices serving as a key voltage class for converters, motor drives, and charging systems [1-3]. To further develop these applications toward higher efficiency, it is essential to pursue an optimal and area efficient design. A primary strategy involves reducing conduction losses within a given area, commonly expressed as the specific on-resistance ( Ron,sp ). The Ron,sp of a MOSFET originates from several components, including channel resistance, JFET region resistance, drift layer resistance, and contact resistance. While each constituent can be individually optimized to lower Ron,sp, careful consideration is necessary since these parameters are interdependent and often governed by trade-off relationships [4].

The heavily doped N+ source region plays an important role in forming a low resistance ohmic contact to the source electrode. Prior studies have shown that optimizing the implantation profile and dimensions of the N+ source can reduce the overall resistance in 4H−SiC power devices [5,6]. The depth of the N+ source can be considered as an important design parameter. From a fundamental standpoint, electrical resistance is inversely proportional to the effective cross-sectional area available for current flow. Extending the N+ junction deeper into the semiconductor increases the effective current carrying cross-section beneath the source contact, which mitigates current crowding near the surface and lowers the overall contact resistance. Consequently, a deeper N+ source enhances carrier injection by widening the conduction path, thereby directly contributing to the reduction of Ron,sp. To create a deeper N+ profile, a higher ion implantation energy is used. However, by employing a higher implantation energy, the lateral straggle of the implanted region increases [7]. Although this has been shown for other implantations, the effects on the N+ source region have yet to be studied in sufficient detail. Therefore, this study undertakes a comprehensive evaluation of N+ implantation depth and its implications on electrical performance of 1.2 kV 4 H -SiC MOSFETs.

In this study, 1.2kV4H−SiC MOSFETs were fabricated with three distinct N+ junction depths by varying the nitrogen ion implantation energy. Electrical characterization included Transfer Length Method (TLM) measurements to extract contact resistivity, as well as static characteristics measurements to assess conduction and blocking behaviors. Complementary TCAD simulations and SEM cross-sectional imaging were employed to validate the physical junction depths and to analyze the influence of lateral straggle on channel potential. Strategies such as JFET optimization are further explored with deep N+ split as a means of reducing the leakage current during the blocking mode.

Design and Fabrication

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Three 4H−SiC wafers were employed for this study, incorporating both linear (Nominal) and hexagonal (HEXFET) device layouts, as shown in Fig. 1(a) and Fig. 1(b). The fabrication sequence included ion implantations to form the JFET, P-well, N+ source, P+ body, and Junction Termination Extension (JTE) regions, followed by a high-temperature activation anneal to electrically activate dopants and repair implantation induced lattice damage. All implantation parameters and subsequent process steps were kept identical across the wafers, with the only variation being the N+ source implantation depth, adjusted by implant energy to achieve shallow, moderate, and deep N+ junction profiles. Here, Fig. 2(a) shows the TCAD simulated cross section of the device structures with three N+ source depths, while Fig. 2(b) depicts the corresponding SEM cross sections from the fabricated devices with N+ split.

[picture]

Fig. 1. Top-view of the cell layout for (a) Nominal MOSFET and (b) HEXFET device.

Fig. 1. Top-view of the cell layout for (a) Nominal MOSFET and (b) HEXFET device.

[picture]

Fig. 2. (a) TCAD simulated, and (b) SEM cross-sections of shallow, moderate and deep N+ configurations. Depths: Shallow - 0.22μ m, Moderate −0.24μ m, and Deep - 0.27μ m.

Fig. 2. (a) TCAD simulated, and (b) SEM cross-sections of shallow, moderate and deep N+ configurations. Depths: Shallow - 0.22 μ m , Moderate − 0.24 μ m , and Deep - 0.27 μ m .

Lower implant energies yielded shallower N+ junction depths, whereas higher energies yielded progressively deeper profiles. The N+ Implant doses remained the same for all 3 wafers. Following the thermally grown gate oxide, polysilicon was deposited and patterned, after which an interlayer dielectric (ILD) was deposited. Contact etching was then performed. Nickel was subsequently deposited and annealed to form low resistance ohmic contacts through nickel silicidation. This was followed by metal deposition for interconnection, and finally a passivation layer was deposited and patterned to complete the device fabrication. The same set of photomasks was used for all three wafers, as the only variation in this study was the N+ implantation energy. The fabrication process was conducted at Clas-SiC wafer fab in United Kingdom.
Fig. 3 (a) shows the TCAD simulated vertical doping profiles extracted along the A-B cutline indicated in Fig. 2(a). The junction depths were approximately 0.22μ m,0.24μ m, and 0.27μ m for the shallow, moderate, and deep implants, respectively. The lateral doping distribution across the channel region (C-D cutline) is shown in Fig. 3(b).

[picture]

Fig. 3. (a) Vertical doping profile (across A-B cutline), and (b) Lateral doping profile (across C-D cutline) of shallow, moderate, and deep N+ source conditions.

Fig. 3. (a) Vertical doping profile (across A-B cutline), and (b) Lateral doping profile (across C-D cutline) of shallow, moderate, and deep N+ source conditions.

[picture]

Fig. 4. Resistance versus pad spacing extracted from TLM structures for shallow, moderate, and deep N+ implant splits.

Fig. 4. Resistance versus pad spacing extracted from TLM structures for shallow, moderate, and deep N+ implant splits.

As the implantation energy (or depth) increases, the lateral spread of the doped region becomes more pronounced, resulting in the N+ junction extending further into the channel region. This progressive extension is clearly observed when comparing the shallow, moderate, and deep implant splits. This will be discussed in detail in the next section.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

TLM measurements were carried out to evaluate the source contact resistivity for each N+ depth condition. Fig. 4 shows the resistance versus pad spacing plots for the shallow, moderate, and deep implant splits. A clear trend is observed, where the extracted contact resistivity decreases significantly with increasing N+ source depth. Specifically, values of 3.91×10−5Ω· cm2,2.40×10−6Ω· cm2, and 1.22×10−6Ω· cm2 were obtained for the shallow, moderate, and deep splits, respectively. The observed improvement is consistent with the expectation that higher implantation energy increases the crosssectional area with the depth, creating a more effective current carrying cross-section beneath the contact. This enhancement ultimately contributes to the reduction of the overall device resistance.

Figure 5(a) shows the trade-off relationship between Ron,sp  and Vth  for Nominal and HEXFET architectures under different N+ depths. Here, Ron,sp was extracted at drain to source current (Ids)=15 A and gate to source voltage (Vgs)=20 V. For Nominal devices, Ron,sp decreased from 3.05 mΩ· cm2 (shallow) to 2.96 mΩ· cm2 (moderate) and further to 2.89 mΩ· cm2 (deep), corresponding to reductions of 3.0% and 5.3% relative to the shallow condition. For HEXFET devices, Ron,sp decreases from 2.71 mΩ·cm2 (shallow) to 2.63 mΩ· cm2 (moderate) and 2.52 mΩ· cm2 (deep), representing 3.0% and 7.0% reductions, respectively. The greater improvement in HEXFETs reflects their higher channel density compared to that of the nominal design. These results clearly demonstrate that greater N+ junction depth plays a decisive role in lowering Ron,sp.

Similarly, a consistent downward trend in threshold voltage is observed with increasing depth. Here, Vth  was extracted at drain to source current (Ids)=10 mA while sweeping Vgs=Vds. For Nominal devices, Vth  decreases from 2.25 V (shallow) to 2.10 V (moderate) and 1.96 V (deep), representing reductions of 6.7% and 12.9%, respectively. For HEXFET devices, Vth  shifts from 2.20 V (shallow) to 2.03 V (moderate) and 1.88 V (deep), corresponding to reductions of 7.7% and 14.5%. This behavior is attributed to the extension of the N+ junction toward the channel region with increasing depth, which effectively shortens the channel and reduces the required gate bias to initiate conduction through the channel. The extension of N+ happens due to a phenomenon called lateral straggle. Lateral straggle in ion implantation refers to the sideways spread of implanted ions as they penetrate
into the semiconductor. During implantation, ions undergo multiple collisions with lattice atoms, which causes their trajectories to deviate from the vertical direction. As a result, the dopant distribution extends laterally in addition to its intended vertical depth profile. In this case, the phenomenon causes the N+ source region to extend toward the channel as implant energy increases, as shown in Fig. 3(b). This lateral extension shortens the effective channel length and lowers the effective acceptor concentration near the N+ end of the channel region, which reduces the Vth .

Figure 5(b) shows the relationship between breakdown voltage (BV) and threshold voltage ( Vth  ) for the N+ depth splits. A clear reduction in BV is observed as the N+ junction depth increases. Here, BV was extracted at Ids=100μ A and Vgs=0 V. For Nominal devices, BV decreased from 1610 V in the shallow split to 1470 V in the deep split. In HEXFET devices, the degradation is more pronounced, with BV dropping from 1560 V to 1015 V . Here in both the device types, the BV was dictated by the increased leakage current rather than avalanche breakdown. This behavior is strongly correlated with the reduction in Vth  discussed in the previous section, as both parameters are influenced by the lateral straggle. The underlying mechanism is further illustrated in the simulated channel potential distributions shown in Fig. 6.

[picture]

Fig. 5. Trade-off relationship between (a) Ron,spvs.Vth(b)BV vs. Vth of N+ depth split. The cross marks denote the average value of each population. The Ron,sp and BV decrease with N+ depth.

Fig. 5. Trade-off relationship between (a) R o n , s p v s . V t h ( b ) B V vs. V t h of N + depth split. The cross marks denote the average value of each population. The R o n , s p and BV decrease with N+ depth.

[picture]

Fig. 6. Channel potential distribution at Vds=1200 V of the N+ Split. The leakage current increases with barrier lowering in the channel region.

Fig. 6. Channel potential distribution at V d s = 1200 V of the N + Split. The leakage current increases with barrier lowering in the channel region.

[picture]

Fig. 7. TCAD simulated leakage current density during blocking mode operation (at Vds=1200 V ).

Fig. 7. TCAD simulated leakage current density during blocking mode operation (at V d s = 1200 V ).

With deeper implants, the N+ region extends closer to the channel, which reduces the channel potential depth (from 0.89 V to 0.76 V ). This lowering of the channel potential barrier promotes increased leakage current in the off state, thereby limiting the BV of the device. The results highlight the inherent trade-off between conduction and blocking characteristics that arise when employing deeper N+ source implants. Fig. 7 shows TCAD simulated leakage current density during the blocking mode operation (at Vds=1200 V ). Increased leakage with deep N+ can be clearly seen here.

To mitigate the high leakage current observed with the deep N+ condition, another wafer was fabricated with same N+ depth however, the JFET region doping was reduced this time. In this case, the shallowest JFET implant dose was reduced by 55% compared to the baseline condition. All other process parameters were identical between initial deep N+ and the new deep N+ with optimized JFET wafers. Figure 8 compares the deep N+ split before and after this adjustment. For Nominal devices, BV improves from 1470 V to 1560 V , while Vth  increases from 1.96 V to 2.16 V . A slight increase in Ron,sp  is also observed. Average values of each wafer employed in this study are summarized in table 1.The recovery mechanism is as follows: lowering the JFET doping reduces the net donor concentration including at the surface, thereby increasing the net acceptor concentration in the channel region. This shift raises the local channel potential and restores the channel barrier, which suppresses off-state leakage and supports a higher blocking voltage. Further, co-optimization of both p-well and JFET is required to bring the Ron,sp  down to the original value or further down while maintaining the same blocking performance.

[picture]

Fig. 8. Deep N+: BV vs. V th comparison with optimized JFET. V th and BV increase with the reduced JFET doping compared to the original deep N+ condition. Cross denotes the average of the population.

Fig. 8. Deep N+: BV vs. V th comparison with optimized JFET. V th and BV increase with the reduced JFET doping compared to the original deep N+ condition. Cross denotes the average of the population.

Table I. Average electrical characteristics of Nominal MOSFET and HEXFET devices.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

The impact of N+ source implantation depth on the performance of 1.2kV4H−SiC MOSFETs was systematically investigated through a combination of electrical measurements, TCAD simulations, and SEM cross-section validation. TLM structures confirmed that deeper N+ junctions reduce contact resistivity by nearly two orders of magnitude, which directly lowered the source contact contribution to the total device resistance. This reduction translated into measurable improvements in Ron,sp  with Nominal and HEXFET devices exhibiting decreases of approximately 5% and 7%, respectively, when comparing shallow and deep splits. The improvement is attributed to enhanced current spreading beneath the source electrode and a larger effective conduction cross-section provided by deeper implantation. In parallel, threshold voltage exhibited a reduction with increasing implant depth, decreasing from 2.25 V to 1.96 V in Nominal devices. TCAD profiles reveal that the shift originates from the extension of the N+ junction into the channel region, due to lateral straggle which shortens the effective channel length and reduces the effective acceptor concentration near the channel. BV was strongly influenced by deeper N+, decreasing from 1610 V to 1470 V in Nominal devices and from 1560 V to 1015 V in HEXFETs as the junction depth increased. Channel potential distributions confirmed that the extension of the N+ region lowers the channel barrier, which promotes higher leakage and limits blocking capability. To counteract this degradation, the JFET doping was reduced in deep N+ devices, which increased the effective P -well influence in the channel region and restored the channel barrier. This process modification successfully improved BV from 1470 V to 1560 V in Nominal devices, with only a minor increase in Ron,sp and a modest upward shift in Vth. Overall, the results demonstrate that deeper N+ implants are highly effective in reducing contact resistance and Ron,sp, but they introduce fundamental trade-offs in Vth and BV due to dopant redistribution into the channel region. These findings highlight the importance of co-optimizing N+ source depth with Pwell and JFET engineering to balance conduction efficiency with robust blocking capability. Such design strategies are essential for advancing 1.2 kV 4H-SiC MOSFET technology toward higher performance and reliability in next generation power electronic systems.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

This work was supported in part by the Air Force Research Lab (AFRL), U.S. Department of Defense, Wright-Patterson Air Force Base under Contract FA2391-23-C-CB001. The authors gratefully acknowledge Alexander Bialy, Senior SEM Technician at the College of Nanotechnology, Science and Engineering, University at Albany (SUNY), for providing the SEM cross-sections used in this study.

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Keywords Index

#

200 Mm SiC Wafer Technology Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

4 H -sic Detectors Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

4 H -sic Mosfet Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

A

Activation Annealing Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Afm A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

And Lateral Ion Straggle Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

B

Backside Reflection Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Body Diode Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Breakdown Voltage Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Brewster's Angle Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

C

C-v Characteristics Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Carbon Vacancy Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Channeling Implantation Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Contact Resistance Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Cv Measurement Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

D

Dlts A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

E

Edge Termination Techniques Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Effective Lifetime A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Electric Field Characterization Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Electrical Characteristics Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Electron Beam Induced Current A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Epitaxial Growth A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

G

Gan Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

I

Ion Implantation Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Ion Implantation Depth Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Irradiation Temperature Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

J

Junction Termination Extension Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

L

Lateral Straggle Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Lpcvd Teos Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

M

Mechanical Stress Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Minority Charge Carrier Lifetime A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Molten Koh A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Mosfet Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

N

N+ Source Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

O

Obic (optical Beam Induced Current) Technique Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Oxide Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

P

Photoelastic Measurements Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Process Window Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Protons Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

R

Radiation Resistance Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Recombination Lifetime A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Resistance Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Reverse Recovery Charge Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

S

Scanning Electron Microscope A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Schottky Barrier Diode A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

SiC Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC; Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Sims A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Spectroscopic Ellipsometry Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Super-junction A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Synopsis Tcad Simulations Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

T

Tcad Simulation Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Thermal Oxide Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Thin Oxide Layer Measurements Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Time-resolved Ebic A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

U

Ultra-high-voltage Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

W

Wafer Warpage Analysis Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Authors Index

B

Baier, L. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Benedetto, L. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Boldrini, V. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Boschi, C. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Buompane, R. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

C

Canino, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Carrano, V. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Casali, N. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Chen, H. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Cheng, C. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

D

Davydovskaya, K. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

deBoer, S. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Dong, L. Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

F

Fodor, B. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Formicola, A. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

G

Gialanella, L. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Gruber, C. A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

H

Hinojosa, M. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Häublein, V. Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

J

Jang, S. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Jiang, H. Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

K

Kagawa, Y. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Kallinger, B. Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Karhu, R. Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Kiyoi, A. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Kozlovski, V. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Körfer, J. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

L

Lai, W. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Laubenstein, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Lebedev, A. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Lelis, A. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Levinstein, M. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Licciardo, G. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Liguori, R. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Luca, S. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Luo, X. Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Lynch, J. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

M

Makai, L. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Malevsky, D. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Mancini, S. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Mancuso, A. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Matsuoka, M. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

May, A. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Mitsou, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Miyazaki, K. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Morgan, A. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Mudiyanselage, D. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Muoio, A. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

N

Neitzert, H. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Nikolaev, A. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Nitta, T. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Nufer, S. Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

P

Pap, Z. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Pieruccini, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Pobegen, G. A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

R

Rinaldi, N. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Rommel, M. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry; Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements; Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Rubino, A. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

S

Sakharov, A. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Sangregorio, E. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Santonastaso, C. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Smoliner, J. A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Soda, D. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Solonitsyn, N. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Sung, W. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

T

Tanioka, T. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Tojima, K. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Torky, M. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Tsui, B. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

V

Via, F. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

W

Wilson, M. Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Wu, Q. Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Wu, Y. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Y

Yadav, R. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Yun, N. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Z

Zheng, S. Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation