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ISBN print: 978-3-0364-2130-8
ISBN eBook: 978-3-0364-3130-7
DOI book: 10.4028/b-yS1XPs
© 2026 Trans Tech Publications Ltd, All Rights Reserved

Performance Analysis of SiC Power Devices

Edited by
Sang Mo Koo
Hoon Kyu Shin

Performance Analysis of SiC Power Devices

Special topic volume with invited peer-reviewed papers only

Edited by
Sang Mo Koo and Hoon Kyu Shin
Scientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volume 1057 of
Key Engineering Materials
ISSN print 1013-9826
ISSN web 1662-9795

Full text available online at https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp -1-0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2026-05-18

Online:
2026-05-21

Preface

The original version of this paper is available on https://www.scientific.net/KEM.1057.-1.pdf

Silicon carbide (SiC) has transformed the field of power electronics by enabling semiconductor devices that can operate at higher voltages, temperatures, and switching frequencies than siliconbased devices. As SiC technologies mature, a detailed understanding of device performance, reliability, and failure mechanisms has become essential for advancing research and its industrial implementation.

This special edition is devoted to investigations into the characterisation and interpretation of the electrical and thermal behaviour of modern SiC power devices. Particular emphasis is placed on SiC MOSFETs, Schottky diodes, and Junction Barrier Schottky (JBS) diodes, whose performance is strongly influenced by material quality, device architecture, and processing conditions. Topics such as Hall mobility, gated Hall measurements, gate oxide properties, gate dielectrics, and trench formation are examined to elucidate the relationship between interface quality and carrier transport.

A central focus is the reliability of gate structures under demanding operating conditions. Negative-bias gate stress, gate leakage, Fowler-Nordheim current, tunnelling phenomena, deep oxide traps, and bias temperature instability are discussed in detail, together with advanced diagnostic methods including charge pumping and Technology Computer-Aided Design (TCAD). These approaches provide insight into defect generation, threshold-voltage shifts, and long-term degradation mechanisms that affect device robustness.

The edition also addresses dynamic performance and application-oriented characteristics, including switching losses, dynamic losses, gate capacitance, parasitic capacitance, reverse recovery behaviour, and short-circuit reliability. Additional attention to explore ion-implanted phototransistors and emerging CMOS technologies based on SiC, highlighting the expanding role of wide-bandgap semiconductors beyond conventional applications.

This special edition presents the results of an evaluation of SiC power device performance and is intended as a valuable resource for researchers, engineers, and graduate students engaged in power semiconductor development and their reliability analysis. We hope that the knowledge presented in this volume will support continued innovation and accelerate the deployment of highly efficient and reliable SiC -based electronic systems.

Table of Contents

Preface

Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Suman Das, Daniel J. Lichtenwalner, Shane R. Stein, Sei Hyung Ryu

Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Andrei Konstantinov, Shagufta Naureen, Sergey Reshanov, Jang Kwon Lim

Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Yang Liu, Lei Yuan, Xue Song Liu, Tong Xiao Hou, Bo Peng, Ren Xu Jia, Yu Ming Zhang

1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Tommaso Stecconi, Roger Stark, Paula Reigosa, Nick Schneider, Coris Li, Leon Liang, Lars Knoll

Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Ilaria Matacena, Luca Maresca, Alessandro Borghese, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento

Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Shane R. Stein, Suman Das, Daniel J. Lichtenwalner, Sei Hyung Ryu

Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

Luigi di Benedetto, Nicola Rinaldi, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Nicola Rinaldi, Luigi di Benedetto, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Jenny Damcevska, Sima Dimitrijev, Daniel Haasmann, Philip Tanner, Fan Peng Zeng, Lan Luo, Ying Xin Cui, Yu Zhong, Ji Sheng Han

Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Pei Chun Liao, Kung Yen Lee, Ruei Ci Wu, Yan Yu Wen, Po Yu Cheng, Wei Xiang Wang

Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Hojung Lee, Justin Lynch, Stephen A. Mancini, Skylar deBoer, Miguel Hinojosa, Aivars Lelis, Woongje Sung

Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Dick Scholten, Johannes Ziegler, Wolfgang Feiler

Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Takeshi Tawara, Kensuke Takenaka, Syunki Narita, Shinsuke Harada

Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Boglárka Dikó, Oleg Rusch, Julien Körfer, Zsófia Kiss, Attila Sütő, Emeric Balogh

Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Kyrylo Melnyk, Arne Benjamin Renz, Mustafa Akif Yildirim, Nikolaos Iosifidis, Qin Ze Cao, Jose Ortiz-Gonzalez, Vishal A. Shah, James A. Gott, Peter Michael Gammon, Marina Antoniou

An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

Giorgian Borca-Tasciuc, T. Paul Chow

Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Giorgian Borca-Tasciuc, Reza Ghandi, Collin W. Hitchcock, Tat Sing Paul Chow

Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Marvin Gloth, Drinas Kelmendi, Hamed Azimi, Benjamin Weigt, Tobias Erlbacher

Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Ruei Ci Wu, Kung Yen Lee, Pei Chi Liao, Pei Chun Liao, Jui Chi Chu

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 1-5

doi: 10.4028/p-AOAv5u

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-28

Revised:
2025-12-08

Accepted:
2026-03-08

Online:
2026-05-21

Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Suman Das 1,a, Daniel J. Lichtenwalner 1, b*, Shane R. Stein 1,c and Sei-Hyung Ryu 1,d

1 Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

a  suman.das@wolfspeed.com, b  daniel.lichtenwalner@wolfspeed.com, c  shane.stein@wolfspeed.com, d  sei-hyung.ryu@wolfspeed.com

Keywords: gated Hall, Hall mobility, interface traps, Coulomb scattering, surface phonon, surface roughness, mobility modeling.

Abstract

Gated Hall measurements of lateral MOSFET devices can be used to directly measure the inversion layer free carrier density and carrier Hall mobility. From this measurement the total number of charged interface traps ( NIT ) can be extracted. This provides useful insight into the degree of Coulomb scattering expected. By obtaining gated Hall data from 4∘ off-axis Si-face ( 0001 ) 4H−SiC MOSFETs with varied p -well doping levels, mobility limiting components can also be estimated. For these samples it is observed that interface trapped charge is almost half of the total inversion charge, and thus Coulomb scattering dominates at low Vgs or low transverse (or normal) effective field; while phonon scattering may dominate at moderate effective field, and surface roughness only limits mobility at gate fields higher than the rated usage, or at doping levels much higher than 2×1018 cm−3.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Although the oxide reliability and threshold stability of Si-face (0001) 4H−SiC MOSFETs is relatively good using the established thermal oxidation and NO anneal process [1], it is known that improvements in channel mobility are possible [2], and better measurements of channel properties can be helpful to fully understand the limits of performance. Gated Hall measurements have been found to be a useful way to extract not only carrier mobility (Hall mobility), but also the free carrier density (carriers/ cm2 ) and total trapped charge ( NIT  ) [3-7]. When performing gated Hall measurements on samples with varied p-well doping levels, the mobility limiting components can more accurately be extracted. This enables a more complete understanding of the interface properties, regarding the limiting factors controlling the inversion-layer channel mobility.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Figure 1(a) shows a top view and Fig. 1(b) shows a schematic cross-section of the fabricated MOS gated Hall bar. The Hall bar is fabricated on a Si-face (0001) 4∘ off-axis 4H−SiC n-type wafer with low doped n -type epilayers, on uniform Al-doped implanted p -well layers ( 1 um in depth) with doping values of 2×1017,4×1017,1×1018 and 3×1018 cm−3. This is a long channel ( Lch=1 mm, Wch=200um ) lateral MOSFET with Hall voltage contacts, designed to minimize errors due to geometric effects [8]. The gate oxide is a typical thermal oxide passivated with a NO anneal. All samples have the same P+ and N+ doped regions, the same activation anneal, and the same gate oxidation process. The only difference between samples is the implanted Al p -well concentrations.

DC Hall measurements are performed at room temperature using a Lakeshore FastHall system with a gate bias option and a 1 Tesla permanent magnet. The Vgs is stepped from the threshold ( VT ) value to a Vgs above device use fields to cover a wide range of data for each of the samples measured. As the VT increases for higher doped samples, a narrower data range is obtained as doping increases. The Vgs has been converted to effective normal field as described by Noguchi [5], using η=1/3, and a Hall scattering factor of unity used for mobility and free carrier calculations from the Hall data.

[picture]

Fig. 1(a). Top-view schematic of a gated Hall MOSFET. Lchan =1 mm, and Wchan =200 um.

Fig. 1. (a). Top-view schematic of a gated Hall MOSFET. L chan = 1 m m , and W chan = 200 um.

[picture]

Fig. 1(b). Schematic cross section of a gated Hall MOSFET along the channel length. In gated Hall only inversion charge (dotted line) is measured as a function of Vgs.

Fig. 1. (b). Schematic cross section of a gated Hall MOSFET along the channel length. In gated Hall only inversion charge (dotted line) is measured as a function of Vgs.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Figure 2 shows the measured (a) field-effect ( μFE ) and (b) Hall mobility ( μHall  ) for different pwell doping concentrations at room temperature. The difference between μFE and μHall  occurs due to the high density of interface traps, and the assumption in the field-effect calculation that the carrier concentration is determined only by oxide thickness and dielectric constant (disregarding trapped charge). Gated Hall allows the free charge (Ns or nfree ,cm−2 ) to be measured as a function of Vgs. The interface trapped charge ( NIT  or ntrap ,cm−2 ) is then determined by subtracting the measured free charge from the total inversion charge. The total charge at the interface is obtained using a split C−V measurement between G to S−D keeping the B contact grounded. A typical split C−V measurement at 5 kHz is shown in Fig. 3, from which integration shows the total channel charge on the right y -axis (after subtracting gate to N+ overlap capacitance). The total charge density ( ntotal  ) measured is consistent with the value calculated from the measured Tox and Cox. The occupied trapped charge density ( ntrap  ) for all samples is plotted in Fig. 4, obtained from the gated Hall measured value of nfree  (data points) subtracted from the measured total charge (ntotal ). In order to show the data together more clearly, the Vgs is scaled by the Vt. It appears that a slight increase in ntrap  is observed as doping increases. This could be a result of the fermi level change with doping, resulting in more filled traps at a given Vgs - Vt. Of note is that the charged interface trap density is similar to that of the free carriers, and even up to the rated Vgs use conditions nearly half of all inversion layer carriers are trapped.

To observe the overall effect of all scattering mechanisms at the channel, the Hall mobility can be modeled from the individual mobility limiting components, namely the bulk mobility limiting factors (μBulk), Coulomb limited mobility ( μC ), surface phonon limited mobility ( μPh ), and surface roughness limited mobility ( μSR ). The Coulomb limited mobility can then be calculated from the measured Hall mobility using Mattheissen's rule:

1μC=1μHall −1μBulk +1μPh+1μSR(1)

The field ( Eeff  ) dependence of μPh and μSR are taken from previous observations in literature [3,5,9,10]. Values for the bulk mobility are chosen based on the doping levels, and the surface phonon limiting term is taken as being close to that of other reports [4,5] using the ideal exponent ( Eeff−0.33 ). The surface roughness limiting term was chosen such that it corresponds closely to the ideal functional form ( Eeff−2 ). All prefactors are adjusted such that the data for all doping levels is fit well, and the extracted coulomb scattering term follows a power law relationship to Ns or nfree [5].

In Fig. 5 the Hall mobility versus effective normal field (Eeff) is plotted for the sample with 2×1017 cm−3p-well doping. The red dotted line is the fit to the data considering all the scattering components.

[picture]

Fig. 2. Comparison of (a) the field-effect mobility measured from Id-Vgs curves, and (b) the Hall mobility. The field-effect mobility will be lower when there is trapped charge, due to the way that the field-effect mobility is calculated.

Fig. 2. Comparison of (a) the field-effect mobility measured from Id-Vgs curves, and (b) the Hall mobility. The field-effect mobility will be lower when there is trapped charge, due to the way that the field-effect mobility is calculated.

The Coulomb limiting values have been extracted as discussed above, shown by green dots and fit empirically using a logarithmic function of Eeff  (maintaining a power law function of Ns). The data can be fit nicely using almost the same surface phonon scattering term as used by others [4,5], with a slightly lessened effect of surface roughness, which is process-dependent. For each sample, the Coulomb scattering term is obtained as described above, and is different for each p-well doping.

Figure 6 shows the effect of these scattering mechanisms on the samples with different doping concentrations. The values of μPh and μSR used are identical for all samples; however, the values of μBulk  and μC change due to doping. We observe that the μC drops with increasing p-well concentration. This holds for a fixed temperature; all data shown is at room temperature. The data overall indicates that for these samples, at low Vgs near Vt and above, Coulomb scattering effects limit the channel mobility. This is not surprising due to the high NIT  measured directly from these gated Hall devices. At higher Vgs values surface phonon effects dominate for samples with doping <2×1018 cm−3. Only at Vgs or Eeff  values above typical use values, or for samples with doping much higher than 2×1018 cm−3, do surface roughness effects come into play for these samples.

[picture]

Fig. 3. Split C-V from G to S-D with Base grounded. Frequency is low ( 5 kHz ) to measure most of the interface charge.

Fig. 3. Split C-V from G to S-D with Base grounded. Frequency is low ( 5 kHz ) to measure most of the interface charge.

[picture]

Fig. 4. Calculated trap levels ntrap  from the measured Hall free carriers and ideal charge ntotal . Doping has only a small effect on ntrap  levels.

Fig. 4. Calculated trap levels n trap from the measured Hall free carriers and ideal charge n total . Doping has only a small effect on n trap levels.

[picture]

Fig. 5. Graph showing how the Coulomb scattering effects ( μC ) can be obtained from the measured Hall mobility, fixing the terms for bulk, surface phonon, and surface roughness.

Fig. 5. Graph showing how the Coulomb scattering effects ( μ C ) can be obtained from the measured Hall mobility, fixing the terms for bulk, surface phonon, and surface roughness.

[picture]

Fig. 6. Graph showing how the mobility limiting terms affect all doping levels, and how the mobility limiting effects are Eeff  dependent.

Fig. 6. Graph showing how the mobility limiting terms affect all doping levels, and how the mobility limiting effects are E eff dependent.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Gated Hall measurements of Si -face 4H−SiC MOSFETs with NO -annealed thermal gate oxide show clearly that Coulomb and surface phonon effects dominate in limiting the channel mobility at low and medium Vgs or Eeff values. Surface roughness effects are minimal in these samples and are only observed to limit the channel mobility at very high Vgs or Eeff  values, or for samples with doping levels much higher than 2×1018 cm−3. The high interface trap density is the main mobility limiting effect (Coulomb effects) that could be improved if the interface passivation were improved or near interface oxide traps were reduced.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, R.K. Chanana, R.A. Weller, S.T. Pantelides, L.C. Feldman, O.W. Holland, M.K. Das, J.W. Palmour, IEEE Elec. Dev. Lett. 22 (2001) pp. 176-178.

D.J. Lichtenwalner, S. Ryu, B. Hull, S. Allen, and J.W. Palmour, Materials Science Forum Vol. 1090 (2022) pp 93-100.

H. Naik and T.P. Chow, Materials Science Forum Vols. 679-680 (2011) pp 633-636.

T. Ohashi, Y. Nakabayashi, and R. Iijima, IEEE Trans. Elec. Dev. Vol. 65 (2018) pp. 27072713.

M. Noguchi, T. Iwamatsu, H. Amishiro, H. Watanabe, N. Miura, K. Kita, and S. Yamakawa, Jpn. J. Appl. Phys. Vol. 58, 031004 (2019).

S. Das, Y. Zheng, A. Ahyi, M.A. Kuroda and S. Dhar, MDPI Materials, Vol. 15 (2022) pp.19-25.

S. Das, D.J. Lichtenwalner, S.R. Stein and S. Ryu, ICSCRM 2024 Raleigh NC (in press).

J. Lindemuth, Hall Effect Measurement Handbook, Lakeshore Cryotronics, Inc. ISBN 978-1-73470-780-9, ed. B. Dodrill (2020).

S. Takagi et al., IEEE Trans. Electron Dev. 41 (1994) pp. 2357-2362.

S. Potbhare, N. Goldsman, G. Pennington, A. Lelis, and J.M. McGarrity, J. Appl. Phys. 100, 044515 (2006).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 7-12

doi: 10.4028/p-h2cCpq

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-29

Revised:
2025-12-08

Accepted:
2026-01-31

Online:
2026-05-21

Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

Andrei Konstantinov 1,a, Shagufta Naureen 1, b, Sergey Reshanov 1,c and Jang-Kwon Lim 2, d*

1 II-VI Kista AB, Electrum-207, 16440 Kista, Sweden

2 RISE AB, Electrum-236, 16440 Kista, Sweden

a Andrei.Konstantinov@cohetent.com, b Shagufta.Naureen@coherent.com, c  Sergey.Reshanov@cohenent.com, d* * Jang-Kwon.Lim@ri.se

*corresponding author

Abstract

Visible light emission was observed for negative-bias gate stress of n -channel power MOSFETs in 4H−SiC. The emission intensity is approximately proportional to the current through the gate oxide; and its pattern follows the configuration of active MOSFET channels. We relate the emission to recombination of the electrons injected from the gate into the oxide with valence-band holes from SiC at the surface states at the SiC -to-oxide interface. The gate leakage imaging technique may be helpful for locating different types of gate oxide current crowding, which crowding might cause enhanced wear-out of the gates and early device failure.

Keywords: 4H−SiC,SiC−MOSFET, gate stress, gate leakage.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

Reliability of gate oxides in silicon carbide power MOSFETs has significantly improved in recent years. However, it might take further effort to reach the same reliability level as that offered by silicon power devices. A significant roadblock comes from limited set of available efficient tools. Reliability-related device development techniques are often based on statistical analysis of failures under lengthy stress. An option for direct imaging the gate leakage could enhance development of reliable SiC MOSFETs. In this work we demonstrate a prospective approach based on imaging visible light emission from the gate oxide interface to SiC under negative bias gate stress conditions.

Visible light emission from the interface of gate oxide to SiC was first reported for lateral SiC MOSFETs by Macfarlane and Stahlbush from the NRL [1,2], who employed pulsed gate biasing to form an inversion channel with subsequent release of the interface-trapped electron charge. This excitation technique is similar to well-known charge pumping. Depending on the voltages of high and low gate-bias levels, visible light emission spectra correspond to either bulk recombination in SiC or to recombination at the oxide interface states. A recent series of spectral and imaging studies applied the Macfarlane-Stahlbush technique to SiC power MOSFETs; which summary can be found in [3].

In this study we report visible light emission upon negative and positive gate bias stress; we discuss emission mechanisms and potential practical applications of gate current imaging.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

Power MOSFET wafers were processed at a foundry with a target rated voltage of 1200 V . The MOS-channels were formed by thermal oxidation, which was followed by a nitridation anneal and by a deposition of polysilicon gates. Imaging analysis was done after removing the backside contact to observe the emission through the SiC crystal using an inverted microscope with a cooled panchromatic CCD camera from Hamamatsu. Negative gate-to-source bias was applied to maintain a gate current of 100μ A. Low-magnification ( 2× objective) emission image of a power MOSFET displayed in Fig. 1(a) shows a fairly uniform gate current density. No emission comes from the gate
pad or from the gate runner. The CCD readouts were proportional to the gate current for the same exposure time. High-magnification ( 40× objective) image shown in Fig. 1(b) reveals certain details of the active structure of the device.

[picture]

Fig. 1. Backside-imaged power MOSFET emission for negative-bias gate stress at a gate current of 100μ A at low (a) and high magnification (b).

Fig. 1. Backside-imaged power MOSFET emission for negative-bias gate stress at a gate current of 100 μ A at low (a) and high magnification (b).

In order to locate the regions of peak light emission, reflected-light micrograph was taken through the wafer backside. Backside reflected light image of Fig. 2(a) is complemented by two aligned inserts, showing the polysilicon gate outline and the gate emission. The peak light intensity follows the outline of the p-wells, although some emission also comes from the regions above vertical n-JFETs. Those regions are shown on a schematic cross-section in Fig. 2(b). Certain nonuniformity of emission is observed at microscopic-scale, which origin is yet unclear; it might come from step bunching of the SiC surface, or from process-related fluctuations of the p-well width.

[picture]

Fig. 2. Backside-imaged reflection micrograph with aligned insets for gate polysilicon configuration and for emission (a) and the cross-section of MOSFET unit cell (b); and positive gatebias emission image for gate current of 200μ A (c).

Fig. 2. Backside-imaged reflection micrograph with aligned insets for gate polysilicon configuration and for emission (a) and the cross-section of MOSFET unit cell (b); and positive gatebias emission image for gate current of 200 μ A (c).

Light emission was also observed for a positive gate bias, however, its intensity was much weaker than for the negative gate polarity. Shown in Fig. 2(c) is a medium-magnification ( 10× objective) image for a positive-bias at gate current of 200μ A. The CCD readout for a negative gate bias at 100μ A were 25 times higher with the same objective, implying a 50× higher emission yield per charge carrier passed through the gate oxide. At high magnification ( 40× objective) the image quality was very poor due to too low light intensity.

We made a comparison of the stress-induced emission with that due to the charge-pumping using the conditions reported by Macfarlane and Stahlbush [1]. A square-wave gate-to-source bias with high and low levels of +8 V and -8 V respectively was applied to the MOSFET gate with the source grounded. Alternating gate polarity results in a recombination of free carriers of the gateinduced channel with the opposite-polarity charge trapped at the surface states during the preceding half-period. Light emission could be recorded even with a relatively low pulse frequency of 100 kHz . Negative-bias stress was done after the charge pumping to compare the pattern of light emission between the two techniques. High negative DC bias was applied to the gate of a test MOSFET to drive the same current density as that used for imaging a large area power MOSFET.

[picture]

Fig. 3. Emission of a small-area test MOSFET under charge pumping (a), under negative-bias stress (b), and partial overlay of the two emission images (c).

Fig. 3. Emission of a small-area test MOSFET under charge pumping (a), under negative-bias stress (b), and partial overlay of the two emission images (c).

Emission images of a small-area test MOSFET are shown in Fig. 3. The active region of the test MOSFET followed the same design rules as the high-power MOSFET. Fig. 3(a) corresponds to the charge pumping mode, and emission is assigned red color. Emission image for the negative-bias stress is shown in Fig. 3(b). A partial overlay of the two emission images is shown in Fig. 3(c), in which portions of emission in Figs. 3(a) and 3(b) were electronically removed to leave an overlay in the central area only. The charge pumping yields more uniform emission with no enhancement in the p-well regions. It is also not as grainy as that from DC stress. Overall configuration is identical; both types of emission come from the MOSFET p-wells and from the vertical JFETs.

We will now discuss the light emission mechanism. Shown in Fig. 4(a) is the band alignment of the MOSFET under the conditions of negative-bias gate stress. High-field carrier transport in silicon dioxide is governed by conduction-band electrons, which are driven by electric field from the gate to towards the interface to SiC . The holes of the SiC valence band are driven to the same interface, at which point they recombine with the electrons. Recombination results in light emission from the same interface traps as that for the charge-pumping studied in [1-3].

[picture]

Fig. 4. Electron band diagram for negative-bias gate stress (a), gate-to-source electrical characteristics (b).

Fig. 4. Electron band diagram for negative-bias gate stress (a), gate-to-source electrical characteristics (b).

The dependence of gate current on absolute value of gate-to-source bias is plotted in Fig. 4(b) for positive and negative gate bias conditions. High negative gate bias results in a very strong charging of the oxide interface, as is seen in Fig. 4(b): prolonged negative bias results in a voltage shift of 10-20 Volt. Such interface charging is quite typical for the negative-bias SiC MOSFET stress as was reported in multiple publications [4,5]. The positive charge captured at or next to the interface can often be neutralized by positive gate bias, however high and/or prolonged negative gate bias may result in a permanent shift of the threshold voltage of the MOSFET.

[picture]

Fig. 5. Electron band diagram for positive-bias gate stress (a), and the fraction of holes in total oxide current for silicon and SiC for positive-bias gate stress (b).

Fig. 5. Electron band diagram for positive-bias gate stress (a), and the fraction of holes in total oxide current for silicon and SiC for positive-bias gate stress (b).

For positive gate polarity the charge trapping is not as pronounced. Electrical characteristics are in this case governed by electron tunneling from the surface accumulation or inversion layer in SiC to the oxide. The carriers that tunneled though the barrier travel over the oxide to the gate, and this process should not cause any light emission unless some holes are generated on the path. Such generation of holes is well-known for silicon MOSFETs at very high electric fields in the oxide. Its dominant mechanism is related to impact ionization by hot electrons in the oxide at the anode [6], as shown schematically in Fig. 5(a).

In silicon MOSFET technology, holes generated in the gate oxide are often measured using a charge separation experiment, which utilizes a lateral n-channel MOSFET on a p-type substrate. Weineberg et al. [7] detected the generation of holes in the oxide by measuring the p-substrate current of a planar n-MOSFET at positive bias at the gate. The substrate current is zero if no ionization events occur in the oxide or next to the anode. The substrate current shows up as the gate-to source bias is increased to cause ionization. Plotted in Fig. 5(b) are the data of Weinberg et al. [7] for hole generation in silicon MOSFETs as a function of the gate current density and oxide thickness. A similar charge separation experiment was reported for 4H−SiC by Sometani et al. [8], the data of which are also plotted in the figure. The power MOSFET is not suitable for charge separation because the p-bodies are shorted to the source. It is nevertheless possible to roughly estimate the hole current fraction from the ratio of emission efficiency for positive and negative gate bias conditions, which number is around 0.02 , as discussed above. This data point shown in Fig. 5(b) is in reasonable agreement with published results of charge separation experiments for silicon and for SiC .

Early gate leakage of a power MOSFET represents a significant reliability issue, especially if the gate current is highly localized. Gate-oxide current flow in a power MOSFET may result in wear-out of the oxide, which wear-out rate is governed by the current density. Inspection of MOSFET electroluminescence due to gate stress might therefore be a useful means of detecting crowding of the gate current, which may cause early failure. An example image from examination of a problematic design using this technique is shown in Fig. 6. The MOSFET sample under study was obtained from an external vendor. Fig. 6(a) shows a low-magnification emission image under negative gate-to-source bias for a portion of high-power MOSFET. No emission occurs from the gate pad, which is physically in the bottom part of the image. Regions of very strong emission are observed around the periphery of the active region. High-magnification emission image of the left bottom corner is shown in the insert to Fig. 6(a).

The ledged region of bright emission in the chip corner coincides with a pattern, observed through the substrate in reflected light, Fig. 5(b). Marked with a dashed line is the edge of the gate poly that yields a lighter tone due to reflection. The small dark squares are the locations of Ohmic
contacts. The gate intersects a ledged pattern, which appears to be an imprint of the mask used for subcontact p+ implant. Heavy p -type doping of this ledged region is confirmed by SEM inspection that was done after removing all metals and dielectrics from the top side of the SiC MOSFET chip. The potential-contrast SEM image in Fig. 6(c) indeed shows high p-type doping in the ledged region, which brighter tone corresponds to high p -type doping. Similar gate overlaps with p+ were found next to the gate pad and to the gate runner in the middle part of the device, Fig. 6(a).

[picture]

Fig. 6. Images of a MOSFET from external vendor in electroluminescence (a), in backside-reflected light (b), and in potential-contrast SEM (c).

Fig. 6. Images of a MOSFET from external vendor in electroluminescence (a), in backside-reflected light (b), and in potential-contrast SEM (c).

Crowding of the gate current in the power MOSFET shown in Fig. 6 therefore occurs due to overlapping of the gate oxide with a heavily doped p-type region. Heavily doped p-type SiC has a lower barrier to hole injection into the oxide than the p-well or the n-type JFET. Deterioration of oxide quality due to heavy p-type doping might also contribute to gate current crowding.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

To summarize, we demonstrated the feasibility of imaging the gate leakage pattern in a vertical 4H-SiC power MOSFET using a negative-bias gate stress. For devices having nearly uniform flow of the gate current, the emission occurs from the p-wells and from the vertical JFETs of the MOSFET structure. The emission mechanism is believed to be similar to the light emission due to charge pumping [1-3]; it is related to recombination of electrons and holes at the traps at oxide-SiC interface. Electrons passing though the oxide recombine with valence-band holes from SiC at the interface states. The new imaging technique provides a straightforward means of detecting weak spots of the gate oxide having high density of leakage current, which weak spots may compromise device reliability.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

P. J. Macfarlane, and R. E. Stahlbush, "Characterization of light emission from 4H and 6H SiC MOSFETs," MRS Online Proceedings Library 640, 49 (2000).

R. E. Stahlbush, P. J. Macfarlane, J. R. Williams, G. Y. Chung, L. C. Feldman, K. McDonald, "Light emission from 4H SiC MOSFETs with and without NO passivation," Microelectronic engineering, 59 (2001), pp. 393-398.

M. W. Feil, H. Reisinger, A. Kabakow, et al., "Electrically stimulated optical spectroscopy of interface defects in wide-bandgap field-effect transistors," Communications Engineering 2, 5 (2023).

L. Anoldo, E. Zanetti, W. Coco, A. Russo, P. Fiorenza, and F. Roccaforte, "4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses". Materials, 17(8), 1908 (2024).

T. Liu, S. Zhu, S. Yu, et al., "Gate Leakage Current and Time-Dependent Dielectric Breakdown Measurements of Commercial 1.2 kV 4H-SiC Power MOSFETs," 2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Raleigh, NC, USA, 2019, pp. 195-199.

D. J. DiMaria, E. Cartier, D. A. Buchanan, "Anode hole injection and trapping in silicon dioxide," Journal of Applied Physics, 80 (1996), pp. 304-317.

Z. A. Weinberg, M. V. Fischetti, "Investigation of the -induced substrate current in silicon field-effect transistors," Journal of Applied Physics, 57 (1985), pp. 443-452.

M. Sometani, D. Okamoto, S. Harada, et al., "Temperature-dependent analysis of conduction mechanism of leakage current in thermally grown oxide on ," Journal of Applied Physics, 117, 024505 (2015).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 13-17

doi: 10.4028/p-0rgVLc

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-05

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-21

Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

Yang Liu 1,a*, Lei Yuan 1, b*, Xuesong Liu 2,c, Tongxiao Hou 2, d, Bo Peng 1,e, Renxu Jia 1,f and Yuming Zhang 1, g

1 Faculty of Integrated Circuit, Xidian University, Xi'an 710071, China

2 Beijing BJAST Holdings Co., Ltd., Beijing, China

a*23111110095@stu.xidian.edu.cn, b  yuanlei@xidian.edu.cn, c  xs6721@126.com,

d  644988605@qq.com, eboopeng@xidian.edu.cn, f  rxjia@mail.xidian.edu.cn, ²  zhangym@xidian.edu.cn

Keywords: bipolar phototransistor, ultraviolet, far-UVC detection.

Abstract

The far-UVC band ( 200−240 nm ) is highly attractive for germicidal and solar-blind detection. To address limited surface carrier collection in epitaxial SiC phototransistors, we designed fully ion-implanted lateral phototransistors by combining transistor physics with CMOS-compatible processing. The lateral base width was systematically varied from 1 to 8μ m to investigate its influence on carrier transport and gain. A narrower base significantly enhanced photocurrent amplification, with the 1μ m device reaching 100.7 A/W at 200 nm and 60.0 A/W at 240 nm , while maintaining amplification up to the ~380 nm cutoff. Moreover, dark currents remained as low as 10−11 A, confirming the advantage of structural engineering for high-performance far-UVC SiC phototransistors.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

Applications such as astronomical detection, biomedical imaging, and solar-blind communication demand highly efficient ultraviolet detectors operating in the Far-UVC band [1-3]. Silicon carbide (SiC), owing to its wide bandgap, inherently possesses wavelength selectivity for ultraviolet detection. Moreover, its low intrinsic carrier concentration enables photodetectors fabricated from this material to exhibit exceptionally low dark current levels. Beyond these advantages, highperformance UV detectors are also expected to demonstrate excellent responsivity, that is, the capability to amplify weak optical signals. In this respect, bipolar phototransistors (BPTs) and avalanche photodiodes (APDs) offer significant benefits over conventional photodiodes, metal-semiconductor-metal (MSM) detectors, and other similar device architectures. While APDs are particularly suited for ultra-high-sensitivity detection, phototransistors present advantages in terms of compatibility with integrated design and operation under low bias voltages.

SiC epitaxial technology is comparatively mature and cost-effective, making it a long-standing preferred choice for fabricating not only photodetectors but also power and compact electronic devices. Numerous research groups have successfully demonstrated SiC-based bipolar phototransistors employing multiple epitaxial growth steps. However, from the perspective of quantum efficiency, these devices still struggle to achieve effective optical signal amplification [46]. With the advancement of SiC device technology, ion implantation has been increasingly adopted in device fabrication, gradually narrowing the gap between ion-implanted photodetectors and their epitaxial counterparts [7].

In this work, we report for the first time the design and implementation of several ion-implanted phototransistor architectures realized through CMOS-compatible processes. We provide a comprehensive evaluation of their optoelectronic performance, including dark current density, responsivity, quantum efficiency, and detectivity, and further elucidate how device structure influences these parameters.

This class of detectors effectively overcomes the long-standing limitation of SiC phototransistors in achieving practical optical signal amplification, while simultaneously revealing a set of effective design guidelines for the structural optimization of SiC-based phototransistors.

Device Structure and Process Design Based on Phototransistor Operation

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

The operating principle of a bipolar phototransistor relies on the separation of photon-generated electron-hole pairs by the reverse-biased base-collector (BC) junction. Under the influence of the electric field, holes drift into the base region. The accumulation of holes raises the base potential at the base-emitter (BE) junction, driving it into forward bias. This, in turn, facilitates electron injection from the emitter into the base, thereby realizing bipolar amplification. Consequently, the BC junction must sustain a stable photocurrent to ensure effective forward biasing of the BE junction. Once the concentration of separated holes is insufficient to maintain this condition, the device can no longer operate in the amplification mode.

In epitaxially grown structures, this limitation is often observed due to the exponential attenuation of photons within semiconductors, with the penetration depth strongly dependent on wavelength. For materials such as silicon operating in the infrared regime, the photon penetration depth can extend to several hundred micrometers. Hence, in Si-based infrared detectors, strategies such as stacking multiple epitaxial layers and extending the space-charge region are commonly employed to maximize photon absorption and collection [8]. In contrast, the design logic for ultraviolet detection is fundamentally different. For instance, at a wavelength of 244 nm , the penetration depth in SiC is only about 0.7μ m [9]. As a result, when the depth of the epitaxially formed space-charge region approaches or falls below this value, only a negligible fraction of photons can reach the reverse-biased depletion region. The correspondingly scarce hole population generated in this case is insufficient to maintain forward amplification in the phototransistor.

However, phototransistor structures formed by ion implantation can effectively address this issue. In this case, photons can directly reach the surface depletion region without significant attenuation, thereby substantially increasing the photocurrent generated at the base-collector (BC) junction and making it easier for the phototransistor to enter the amplification regime. Although this concept holds clear advantages in principle, several process-related considerations require special attention.

[picture]

Fig. 1. (a) Top-view optical micrograph; (b) Schematic diagram of the device structure (half unit); (c) The relationship between incident optical power density and wavelength used during the testing process.

Fig. 1. (a) Top-view optical micrograph; (b) Schematic diagram of the device structure (half unit); (c) The relationship between incident optical power density and wavelength used during the testing process.

First, in a conventional ion-implanted BJT structure, the BC buried junction is typically located relatively deep inside the substrate. To mitigate this, we attempt to utilize the N-type region within the P-well as the collector, while designating the epitaxial layer as the emitter. Second, because the near-surface BC junction generates a large photocurrent, amplification must also be achieved through a surface BJT configuration. Consequently, the design focus shifts from realizing a vertically thinbase BJT via implantation energy to constructing a laterally narrow-base BJT. On this basis, we fabricated four types of phototransistors with lateral base widths of 1,2,4, and 8μ m, respectively. Third, the surface oxide inevitably contains a certain amount of fixed charges, which may influence
surface recombination and leakage current [10,11]. To minimize such effects, we employed the highest-quality oxide deposition process available to us, avoiding wet oxidation techniques that are prone to introducing large densities of interface charges. In summary, the actual device structure of our designed phototransistor is illustrated in Fig. 1.

Test Methods and the Impact of Lateral Base Width Variation on Device Performance

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

The electrical characteristics of the devices were measured using a Keysight B1500A semiconductor parameter analyzer. Optical excitation was provided by an EQ-77 white light source driven by a laser, with the output wavelength selected through a monochromator. The optical power incident on the device was controlled by adjusting the distance ( d1−d4 ) between the optical fiber and the sample, as illustrated in Fig. 1c. The corresponding optical power density was calibrated using a commercial Si-based photodetector (Zolix OPE-B3-UV), which had been previously calibrated by the National Institute of Metrology, China, to ensure measurement accuracy.

The dark current characteristics and the comparison of dark current density are shown in Fig. 2. It can be observed that the four devices exhibit generally consistent trends, with slight variations in the absolute magnitude of the dark current. Specifically, when the applied bias is below 4 V , the dark current remains relatively low, but increases significantly once the bias exceeds this threshold. This behavior can be attributed to base punch-through: under reverse bias of the BC junction, the collector is a heavily doped region. As the applied bias increases, the depletion region extends deeply into the base and rapidly connects with the depletion region of the BE junction, resulting in a sharp increase in current. This phenomenon is a direct consequence of swapping the emitter and collector roles in the device design. Within the bias range below 4 V , the dark current densities of the four devices show minimal differences, all close to the measurement limit ( 10−10−10−11 A ). The slightly higher dark current in the device with a 1μ m lateral spacing is mainly attributed to the enhanced tunneling current caused by the abrupt doping gradient across the short distance [12], whereas increasing the spacing to 2μ m effectively suppresses this effect.

[picture]

Fig. 2. Dark current characteristics for different CE spacings and bias.

Fig. 2. Dark current characteristics for different CE spacings and bias.

The responsivity comparison and variation trends are illustrated in Fig. 3. First, under identical optical power density and excitation wavelength, the responsivity increases as the lateral base width decreases. In particular, devices with 2−8μ m base widths exhibit a significant reduction in responsivity compared to the 1μ m device. This can be explained by the fact that a narrower base width in the surface BJT enables more effective amplification. It can be anticipated that base widths around 1μ m or even smaller could deliver stronger amplification; however, such scaling introduces a trade-off with the punch-through effect under operating bias, as discussed previously. Moreover,
the difference in responsivity is more pronounced at 200 nm compared to 280 nm excitation (Fig. 3b and 3c).

Second, for the same device under identical wavelength excitation but varying optical power densities, it is clearly observed that responsivity increases as the optical power density decreases ( d 1 to d4). This result indicates that the near-surface BJT structure is more favorable for weak light detection.

Third, under constant optical power density but different excitation wavelengths, the responsivity at 200 nm is generally higher than at longer wavelengths. This suggests that the device is particularly well-suited for short-wavelength detection in the far-UVC region, as the shallower penetration depth of shorter-wavelength photons allows them to be more effectively absorbed and utilized by the surface BJT structure.

[picture]

Fig. 3. (a) Spectral response under varying collector-emitter (CE) spacings. (b-d): Responsivity comparison of different UV light excitation.

Fig. 3. (a) Spectral response under varying collector-emitter (CE) spacings. (b-d): Responsivity comparison of different UV light excitation.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

The key performance metrics of the devices under 200 nm illumination are summarized in Table 1. It can be seen that under low-light conditions, the device with a collector-emitter spacing ( dce ) of 1μ m achieves a detectivity ( D* ) of 33.4×1013 Jones, whereas under high illumination intensities, the device with dce=2μ m exhibits better detectivity. The responsivity of the 1μ m device reaches 100.7 A/W at 200 nm and 60.0 A/W at 240 nm , and photocurrent amplification is maintained across the entire spectral range up to the cutoff wavelength of approximately 380 nm .

Table I. Comparison of Key Parameters of Different PTs under 200 nm UV Illumination.

These results collectively demonstrate that careful optimization of the device structure, particularly the lateral base width, plays a critical role in balancing responsivity, dark current, and detectivity in ion-implanted SiC phototransistors. Our study provides important insights for the future design of high-performance photodetectors targeting the far-UVC spectral region.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

Li, Jiaqi, Zhou, Yue, Yi, Xiangyu, et al., Current Optics and Photonics 1, 196-202 (2017).

G. Wang, K. Wang, C. Gong, et al., IEEE Photonics J. 10, 1-13 (2018).

D. Guo, Y. Su, H. Shi, et al., ACS Nano 12, 12827-12835 (2018).

Y. Wang, W. Li, W. Xu, et al., IEEE Electron Device Lett. 45, 617-620 (2024).

Y. Wang, W. Li, D. Zhou, et al., IEEE Trans. Electron Devices 1-8 (2022).

C. Sun, H. Guo, L. Yuan, et al., IEEE Trans. Electron Devices 70, 2342-2346 (2023).

C. D. Matthus, T. Erlbacher, A. J. Bauer, et al., "Comparative Study of UV-Sensors with Ion Implanted and Epitaxially Grown p-Emitter," in 2018 22nd International Conference on Ion Implantation Technology (IIT) (IEEE, 2018), pp. 110-113.

R. Cariou, J. Benick, F. Feldmann, et al., Nat Energy 3, 326-333 (2018).

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, 1st ed. (Wiley, 2014).

S. Asada, T. Kimoto, and J. Suda, IEEE Trans. Electron Devices 64, 3016-3018 (2017).

S. Asada, J. Suda, and T. Kimoto, IEEE Trans. Electron Devices 65, 4786-4791 (2018).

G. P. Li, E. Hackbarth, and T.-C. Chen, IEEE Trans. Electron Devices 35, 89-95 (1988).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 19-27

doi: 10.4028/p-6BmS4C

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-15

Accepted:
2026-03-21

Online:
2026-05-21

1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Tommaso Stecconi i1,a*, Roger Stark 1, b, Paula Reigosa 1c, Nick Schneider 1, d, Coris Li2,e, Leon Liang 2,f and Lars Knoll 1, g

1 SwissSEM Technologies AG

Dammweg 23, 5600, Lenzburg, Switzerland

2 Sun.King Pacific Semiconductors Technology(Zhejiang) Co., Ltd

NO. 56 Jinji Road, Huimin Street, Jiashan County, Jiaxing City, Zhejiang Province, 314100, China

a*tommaso.stecconi@swiss-sem.com, broger.stark@swiss-sem.com, c  paula.reigosa@swiss-sem.com, d  nick.schneider@swiss-sem.com, e  coris.li@swiss-sem.com,

Keywords: SiN, high-k, dynamic losses.

Abstract

This paper presents a comprehensive electrical evaluation of a 1.2 kV SiC vertical MOSFET incorporating a novel SiN gate dielectric. Compared to a reference device with thermally grown SiO2, the proposed MOSFET achieves superior static performance and lower dynamic losses. Notably, the reduced losses stem from a lower gate-drain capacitance (CGD). Furthermore, the novel MOSFET demonstrates superior thermal and electrical stability of the threshold voltage. All these findings underscore the potential of higher-k dielectrics to simultaneously optimize both static and dynamic performances in SiC power MOSFETs, paving the way for more efficient high-voltage power switches.

I. Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Crystalline SiC MOSFETs, with their higher thermal conductivity and wider bandgap, deliver superior electrical performance at high frequencies compared to Si-based power switches [1]. However, integrating crystalline SiC as the transistor bulk material introduces notable processing challenges. Specifically, the growth of a SiO2 layer on SiC substrates generates interface and oxide traps, which degrade the device's electrical performance [2]. To mitigate these issues, high-k dielectrics offer a promising alternative by potentially reducing interface trap concentration [3] and improving threshold voltage stability [4]. However, these static-performance gains may come at the cost of degraded gate leakage [5] and lower threshold voltage [6]. Moreover, the impact of the high-k gate dielectric on dynamic performances is not yet fully explored. In this work, we present a novel SiC MOSFET with a SiN gate dielectric that outperforms a reference device with SiO2 gate oxide in both static and dynamic performances.

II. Electrostatic Properties

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Two vertical MOSFET devices, sharing the same process flow, except for the gate-dielectric fabrication, are compared. The first split, labeled as " SiO2 ", features a thermally grown gate-oxide layer in mixed O2 and N2 environment. The second split, labeled as " SiN ", incorporates a SiN gate dielectric layer deposited by Low Pressure Chemical Vapor Deposition (LPCVD). The SiN film is made 62.5% thicker than the SiO2 layer to reduce gate leakage. Fig. 1 shows the input capacitance (Ciss ) vs. gate-source voltage ( VGS ) graph. At VGS=15 V,Ciss  saturates to a value approximately equal to the gate-dielectric capacitance (Cox). We can express Cox as:

Cox=Akε0tox(1)

Where A is the gate area, k is the dielectric constant, ε0 is the permittivity of free space, and tox is the gate dielectric thickness. After taking the ratio of (1), we obtain:

kSiN=1.84·kSiO2,(2)

which aligns well with reported values in literature for Si3 N4 [7].

[picture]

Fig. 1. Area normalized input capacitance ( Ciss,sp  ) of the SiO2 (blue) and SiN (orange) MOSFETs measured as VGs ranges from -3 to 15 V .

Fig. 1. Area normalized input capacitance ( C iss,sp ) of the S i O 2 (blue) and SiN (orange) MOSFETs measured as V G s ranges from -3 to 15 V .

The higher dielectric constant determines a higher Ciss  and hence superior control of the channel carrier density with VGs. This can be observed in Fig. 2 (a), where we plot the subthreshold drain current ( ID ) vs. VGS, under a low drain-source bias (VDS) of 20 mV . We calculate the average inverse subthreshold slope (STS−1) up to VGS=6 V, showing STS −1SiN=660mV/ dec , compared to STS −1SiO2=750mV/ dec. To calculate the threshold voltage ( Vth  ), the Id vs. VGS measurement is repeated on planar MOSFET structures. We extract the transconductance (gm), defined as:

gm=ΔIDSΔVGS(3)

and we trace the x -axis intercept of the ID/(gm)1/2 curves, as outlined by the method [8].

[picture]

Fig. 2. (a) Subthreshold Id-VGS characteristics of the SiO2 (blue) and the SiN (orange) MOSFETs, measured at VDS=20mV. The average inverse subthreshold slope (STS−1) values are displayed in the graph. (b) Transconductance ( gm ) of both devices, measured at VDS=10 V while sweeping VGS from 0 to 15 V .

Fig. 2. (a) Subthreshold Id-VGS characteristics of the S i O 2 (blue) and the SiN (orange) MOSFETs, measured at V D S = 20 m V . The average inverse subthreshold slope ( S T S − 1 ) values are displayed in the graph. (b) Transconductance ( g m ) of both devices, measured at V D S = 10 V while sweeping VGS from 0 to 15 V .

We obtain Vth SiN=6.9 V and Vth SiO2=6.7 V, demonstrating a higher- k MOSFET with higher threshold voltage than the SiO2 reference. In Fig. 2 (b), the gm of the vertical MOSFETs is compared in the highpower regime under VDS=10 V, with VGS swept from 0 to 15 V . The SiN MOSFET exhibits an 11% higher peak gm value, determined by the higher CoxSiN.
In Fig. 3, the voltage hysteresis ( ΔVhyst  ) of the two splits is compared using bidirectional VGS sweeps at VDS=20mV. The SiO2 and SiN splits exhibit ΔVhyst =31 and ΔVhyst =17mV, respectively, indicating improved turn-on/turn-off switching stability with the novel SiN gate dielectric.
Fig. 4 benchmarks the static performance of our SiC devices, including our baseline product "m23", against three competing 13 mΩ,1.2kV-rated SiC MOSFETs. The x-axis represents the Vas values measured by forcing a 10 mA current under the VGD=0 V condition (Vth ,10 mA). The y -axis shows the on-state resistance values extracted at VGS=18 V for ID, on =100 A ( RDS, on  ).

[picture]

Fig. 3. Voltage hysteresis ( ΔVhyst  ) measured by bidirectional Id-VGs sweeps for currents up to Id,compliance =100 mA, performed at 10 V/s of sweep rate.

Fig. 3. Voltage hysteresis ( Δ V hyst ) measured by bidirectional Id-VGs sweeps for currents up to Id,compliance = 100 m A , performed at 10 V / s of sweep rate.

[picture]

Fig. 4. Y -axis: On-state resistance ( RDS,on ) measured at VGS=18 V and ID,on=100 A. X -axis: Threshold voltage ( Vth ,10 mA ), defined as VGS measured while forcing a 10 mA current with VGD=0 V. The compared splits include our SiO2 (blue), our SiN (orange), our m23 product (green), and three other 1.2 kV -rated, 13 mΩ - commercial MOSFETs (grey). Transparent colors represent cold ( 25∘C ) data, while opaque colors correspond to hot (175∘C) measurements.

Fig. 4. Y -axis: On-state resistance ( R D S , o n ) measured at V G S = 18 V and I D , o n = 100 A . X -axis: Threshold voltage ( V th , 10 m A ), defined as V G S measured while forcing a 10 mA current with V G D = 0 V . The compared splits include our S i O 2 (blue), our SiN (orange), our m 23 product (green), and three other 1.2 kV -rated, 13 m Ω - commercial MOSFETs (grey). Transparent colors represent cold ( 25 ∘ C ) data, while opaque colors correspond to hot ( 175 ∘ C ) measurements.

The results are compelling:

Our vertical MOSFETs achieve the best RDS, on 175∘C, ranging between 21 and 26 mΩ.

Our SiN vertical MOSFET demonstrates superior thermal stability of the threshold voltage ( Vth ,10 mA ), with only a 500 mV shift from 25∘C to 175∘C (all the other samples exhibit approximately a 1 V reduction). The high Vth,10 mA is beneficial for short-circuit-safe-operating-area (SCSOA) capability.

Table I. Summary of the static properties of the SiO2 and the SiN vertical MOSFETs, including blocking performance and gate leakage (IG,leak). The breakdown voltage (BVDS) is defined at ID=250μA with VGS=0 V, while the gate leakage current ( IG, leak  ) is measured at VGS=15 V.

Table I.

III. Dynamic Properties

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

In the MOSFET turn-on and turn-off processes, a large fraction of the switching losses is dissipated during the Miller Plateau phase [9]. At this stage, the speed of the output voltage (VDS) transition is governed by the gate-drain component of the gate capacitance ( CGD ) [9,10].
Fig. 5 shows a simplified model of the MOSFET gate capacitance, highlighting the CGd component in red. Under an applied drain voltage (VD), a depletion region of width wdep forms in the drift region, with:

[picture]

Fig. 5. Gate capacitance model of the vertical MOSFET, highlighting the gate-drain component ( CGD ) in red, which is given by the series combination of Cox,dep  and Cdep. Cox, dep  is determined by the coupling between gate and oxide/semiconductor interface. Cdep  arises from the charge modulation in the JFET and drift region. For increasing Vd voltages, the width of the depleted region (wdep) increases.

Fig. 5. Gate capacitance model of the vertical MOSFET, highlighting the gate-drain component ( C G D ) in red, which is given by the series combination of C ox,dep and C dep. C ox, dep is determined by the coupling between gate and oxide/semiconductor interface. C dep arises from the charge modulation in the JFET and drift region. For increasing V d voltages, the width of the depleted region (wdep) increases.

Cdep=εSiwdep(VD,Cox)[9].(4)

For sufficiently high Vd such that:

VD≫qεSiND2Cox2 [9], (5)

where q is the elementary charge, εSi is the silicon permittivity and ND is the doping concentration, the depletion region width ( wdep ) can be approximated by:

[picture]

Fig. 6. (a) wdep  and (b) Cdep  simulated qualitative trends as functions of VD and gate oxide capacitance, from a nominal Cox value up to ten times higher (10·Cox). Both x - and y -axis are represented in log scale, to highlight the square root dependence to VD. These trends assume sufficiently high VD, as per Eq. (5).

Fig. 6. (a) w dep and (b) C dep simulated qualitative trends as functions of V D and gate oxide capacitance, from a nominal C o x value up to ten times higher ( 10 · C o x ) . Both x - and y -axis are represented in log scale, to highlight the square root dependence to VD. These trends assume sufficiently high V D , as per Eq. (5).

wdep≈2εSiVDqND−εSiCox(6)

From (6), wdep  is proportional to VD, with a correction term equal to −εSiCox.
Fig. 6 (a) illustrates the qualitative trend of the depletion width ( wdep  ) as a function of increasing Vd, under the high VD approximation of Eq. (5). The trends are shown for different gate oxide capacitances, from a nominal Cox value up to ten times nominal ( 10·Cox ). The effect of a higher oxide capacitance is to induce a wider wdep , especially at lower VD voltages. Since the depletion capacitance ( Cdep  ) is inversely proportional to wdep  (Eq. (4)), a higher oxide capacitance results in lower Cdep  values, as depicted in Fig. 6 (b).
Finally, CGd is the series combination of Cox,dep and Cdep , with Cox,dep independent from Vd [9]. Fig. 7 presents the CGD values experimentally measured for a drain-to-gate voltage ( VDG ) swept from 10 to 800 V , for both the SiO2 and the SiN MOSFETs. For Vdg>50 V, CGd shows the same log-log trend as Cdep  from Fig. 6 (b), so, in this range, CGD is mainly determined by the Cdep  term. The SiN split exhibits a 5% lower CGD value on average in the VDG range between 10 to 800 V .
The SiO2 and SiN vertical MOSFETs were assembled on DBC substrates in the half-bridge configuration, comprising of one MOSFET on the high-side and one on the low-side, and measured according to the double-pulse testing (DPT) sequence, as described in [9].

[picture]

Fig. 7. CGD of the SiO2 (blue) and SiN (orange) MOSFETs measured by sweeping the gate-to-drain voltage (VDG) from 10 to 800 V .

Fig. 7. C G D of the S i O 2 (blue) and SiN (orange) MOSFETs measured by sweeping the gate-to-drain voltage (VDG) from 10 to 800 V .

Fig. 8 (top), (center) and (bottom) show the turn-on waveforms at 125∘C of the gate-source voltage (VGS), drain-source voltage (Vds) and drain current (Id), respectively, at a stray inductance (Ls) of 50 nH,RG=40Ω, and 800 V of DC link voltage. Before the Miller Plateau is reached, the SiO2 MOSFET shows a slower dID/dt rate, due to the higher Ciss  value. When the Miller Plateau is reached, the SiN MOSFET shows a faster dVDS/dt rate, due to the lower average CGD from 800 V to few V.
By reducing the RG values, a faster turn-on process is achieved and, consequently, lower dynamic losses. Fig. 9 presents the turn-on switching losses ( Eon ) measured for RG=10,20 and 40Ω. The SiN MOSFET exhibits comparable losses at lower di/dt rates, demonstrating a superior turn-on performance.
Fig. 10 (top), (center) and (bottom) show the turn-off waveforms at 125∘C of the gate-source voltage (VGS), drain-source voltage (VDS) and drain current (Id), respectively, at a stray inductance (Ls) of 50nH,RG=40Ω, and 800 V of DC link voltage. The lower CGD of the SiN MOSFET determines a faster Vds voltage ramp up, which in turns enables an earlier fall of the drain current Id, yielding lower energy losses. For RG=10Ω, large oscillations exceeding 20 V build up at the gate

[picture]

A. Center: VDS turn-on waveform. Bottom: Id turn-on waveform.

Figure 9. A. Center: VDS turn-on waveform. Bottom: Id turn-on waveform.

[picture]

Fig.9. Turn-on dID/dt and switching losses (Eon) for RG=10,20 and 40Ω.

Fig.9. Turn-on d I D / d t and switching losses ( E o n ) for R G = 10 , 20 and 40 Ω .

node (not shown). The peak amplitude of the VGS oscillations ( ΔVGSpeak  ) was measured and plotted in Fig. 11 against the turn-off losses ( Eoff  ), for RG=10,20 and 40Ω. The SiN MOSFET exhibits lower ΔVGSpeak  at lower Eoff, proving a superior turn-off performance. The voltage oscillations observed at the drain node with RG=10Ω are comparable in the two splits: VDS,peak SiO2=995 V and VdS,peak SiN= 1007 V (not shown).

IV. Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

We have presented a 1.2 kV rated vertical SiC MOSFET incorporating a SiN gate dielectric that outperforms a reference device with SiO2 gate oxide in both static and dynamic performances. Notably, the SiN split demonstrates superior STS −1, gm,ΔVhyst ,ΔVth 25→175∘C, while also delivering lower Eon and Eoff losses at comparable switching conditions. The reduced dynamic losses are attributed to the lower gate-drain capacitance ( CGD ) observed with the SiN gate dielectric.

[picture]

Fig. 10. Top: VGS turn-off waveform, from +15 to -5 V , at T=125∘C, using Rg=40Ω and ID,on= 150 A . Center: Vds turn-off waveform. Bottom: Id turn-off waveform.

Fig. 10. Top: V G S turn-off waveform, from +15 to -5 V , at T = 125 ∘ C , using R g = 40 Ω and I D , o n = 150 A . Center: Vds turn-off waveform. Bottom: Id turn-off waveform.

[picture]

Fig. 11. Turn-off oscillations peak amplitude vs. losses ( Eoff  ) for RG=10,20 and 40Ω.

Fig. 11. Turn-off oscillations peak amplitude vs. losses ( E off ) for R G = 10 , 20 and 40 Ω .

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Baliga, B. Jayant. "Silicon carbide power devices: Progress and future outlook." IEEE Journal of Emerging and Selected Topics in Power Electronics 11.3 (2023): 2400-2411.

Pantelides, Sokrates T., et al. "Si/SiO2 and SiC/SiO2 interfaces for MOSFETs-challenges and advances." Materials science forum. Vol. 527. Trans Tech Publications Ltd, 2006.

Wirths, Stephan, et al. "Vertical power SiC MOSFETs with high-k gate dielectrics and superior threshold voltage stability." 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2020.

Hosoi, Takuji, et al. "Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics." 2012 International Electron Devices Meeting. IEEE, 2012.

T. Hatayama, S. Hino, N. Miura, T. Oomori and E. Tokumitsu, "Remarkable Increase in the Channel Mobility of SiC-MOSFETs by Controlling the Interfacial SiO2 Layer Between Al2O3 and SiC," in IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2041-2045, Aug. 2008, doi: 10.1109/TED.2008.926647.

Arith, F., et al. "Increased mobility in enhancement mode 4 H -SiC MOSFET using a thin SiO 2/Al 2 O 3 gate stack." IEEE Electron Device Letters 39.4 (2018): 564-567.

Lorenz, H., et al. "Characterization of low temperature SiO2 and Si3N4 films deposited by plasma enhanced evaporation." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 9.2 (1991): 208-214.

Ghibaudo, Gérard. "New method for the extraction of MOSFET parameters." Electronics letters 24.9 (1988): 543-545.

Baliga, B. Jayant. Fundamentals of power semiconductor devices. Springer Science & Business Media, 2010

Stark, Roger, et al. "Accuracy of three interterminal capacitance models for SiC power MOSFETs under fast switching." IEEE Transactions on Power Electronics 36.8 (2021): 93989410.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 29-34

doi: 10.4028/p-IkqQM7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-23

Accepted:
2026-03-08

Online:
2026-05-21

Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

llaria Matacena 1,a*, Luca Maresca 1, b, Alessandro Borghese 1,c, Michele Riccio 1, d, Andrea Irace 1,e, Giovanni Breglio 1,f and Santolo Daliento 1, g

1 Department of Electrical Engineering and Information Technology, University of Naples Federico II, Naples, Italy

ailaria.matacena@unina.it, bluca.maresca@unina.it, calessandro.borghese@unina.it, d michele.riccio@unina.it, e a.irace@unina.it, f breglio@unina.it, g daliento@unina.it

Keywords: capacitance measurements, capacitance peak, transconductance, gate capacitance.

Abstract

SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

SiC MOSFETs are gradually replacing their Si counterparts in various applications, thanks to their higher performance. Besides being a wide bandgap material, SiC also exhibits a higher thermal conductivity [1], supplanting Si in power industry. Although SiC technology has experienced huge progress in last decades, there are some open challenges that have to be addressed. Among them the high defect density at SiC/SiO2 interface is a crucial feature that has to be investigated since it can negatively influence important parameters, such as threshold voltage instability [2], channel mobility [3] and leakage current, affecting the performance of the overall device. Interface traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. Due to the importance of SiC/SiO2 interface defect density [4], several techniques have been investigated to characterize such interface. Among these, the most used methods are based on the measurement of impedance, and more in detail capacitance varying with voltage. These techniques are extensively employed across a wide spectrum of applications, including semiconductor devices and solar cells [5]-[13], as well as batteries [14]. The method is non-destructive and it enables a rapid characterization process. In the literature, most investigations on power devices have focused on MOS structures, where the low-high frequency capacitance technique can be applied [15]-[19]. In such structures, the capacitance response strongly depends on the applied frequency [20], and this dependence provides valuable insight into the nature of defects and traps within the device under test. Specifically, the inversion charge can follow the applied excitation only at sufficiently low frequencies, due to the limited thermal generation of carriers in the depletion region. Consequently, in the inversion regime, the capacitance behavior is primarily governed by the inability of the inversion charge to respond to high-frequency signals. However, this condition is strictly valid for MOS capacitors.

In MOSFETs, the situation differs because, in the inversion region, the channel is replenished with carriers from the Source and Drain. As a result, the capacitance in inversion does not exhibit significant variation between low and high frequency, rendering the low-high frequency method unsuitable for these devices [21]. Therefore, it becomes essential to conduct a precise analysis of the capacitance associated with MOSFETs. This can be achieved using numerical frameworks capable of characterizing the SiC/SiO2 interface properties [22]-[26]. Capacitance measurements are typically
performed at the Gate terminal, with the Drain connected and the Source terminal tied to reference [27]-[29].

In our previous works [25], [30]-[33], we explored non-standard C−V measurement approaches on commercially available planar SiC MOSFETs. In those studies, experimental data were obtained by applying a small-signal AC excitation at the Gate while maintaining a fixed DC bias at the Drain, with the Source grounded. The resulting capacitance revealed an anomalous peak in the inversion region, attributable to both the interface properties and the channel region.

In this work, we investigate the correlation between the capacitance peak observed in the nonclassical C-V characteristics and the transconductance behavior of SiC MOSFETs. To this end, the C−V curves are analyzed under the described measurement configuration, while the derivative of the Id D -V GS  characteristics is evaluated to extract the device transconductance. The experimental findings are confirmed by numerical results obtained using the Sentaurus TCAD environment. The remainder of the paper is organized as follows: the experimental setup is described in the next section, while the TCAD numerical setup is discussed in a separate section. Finally, the main conclusions are summarized in the last section.

Experimental Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

Experimental results are obtained on two different 1.2 kV planar SiC MOSFETs commercially available using the setup shown in Fig. 1i. The presented curves are obtained by measuring the capacitance arising between Gate and Source terminals, while a DC bias is applied to Drain terminal, VDS. The excitation consisted of a DC sweep from -10 V to +10 V with a superimposed small-signal AC component (Fig. 1ii) applied to the Gate of the device under test. A fixed DC bias (Fig. 1iii) was applied to the Drain, while the Source was grounded. The measured Gate capacitance with the Drain biased at fixed positive values is reported as a red line in Fig. 2 for the first device considered. The capacitance exhibits the classical behavior in accumulation and depletion. Conversely, in the inversion region, when Vds ≠0 V, a sharp peak emerges. Capacitance obtained on the other device under test is reported in Fig. 3 in red. In this plot, there a several capacitance curves obtained with increasing Vds. These curves exhibit the same behavior found in Fig. 2. In the inversion region, capacitance shows an unexpected peak whose amplitude increases with higher Vds. In previous studies, the peak profile was attributed to traps located in the channel region beneath the SiC/SiO2 interface [22]. Since interface traps in the channel affect this region physical properties, they have considerable impact on ID−VGS characteristics. Hence for the devices under test, we also measured the transfer characteristics, with the aim of investigating the relation between the capacitance peak and the transconductance behavior. The derivative of the ID−VGS characteristics, i.e. the transconductance, for both the device under tests are reported in Fig. 2 and Fig. 3 as blue curves. Experiments show that the derivative of ID−VGS characteristics, obtained for the same VDS imposed in the C−V measurements, shows a maximum at the same voltage where the capacitance peak occurs, for both studied devices.

[picture]

Fig. 1. i) Experimental setup; ii) applied Gate voltage; iii) applied Drain voltage.

Fig. 1. i) Experimental setup; ii) applied Gate voltage; iii) applied Drain voltage.

[picture]

Fig. 2. Experimental C-V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red line, left y-axis) and corresponding transconductance (blue line, right y -axis).

Fig. 2. Experimental C-V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red line, left y-axis) and corresponding transconductance (blue line, right y -axis).

[picture]

Fig. 3. Experimental C−V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red lines, left y-axis) and corresponding transconductance (blue lines, right y -axis).

Fig. 3. Experimental C − V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red lines, left y-axis) and corresponding transconductance (blue lines, right y -axis).

Numerical Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

The consistency of the experimental findings was further investigated through numerical simulations carried out within the Synopsys Sentaurus TCAD framework. The simulated device structure is depicted in Fig. 4, where the geometrical layout and material parameters were carefully defined to reproduce the actual device under test. In particular, the channel region was modeled by incorporating reduced carrier mobility and defect-related effects, thus reflecting the physical non-idealities typically observed in this region. To investigate the capacitive response, an AC small-signal analysis was performed under various biasing conditions, with a DC potential applied to the Drain terminal while the Gate voltage was swept across the operating range. This approach enabled the extraction of capacitance characteristics, which are strongly influenced by the transport properties of the channel. The resulting C-V curves are reported in Fig. 5 as red traces for different channel doping values. The numerical current-voltage curves were also obtained in the same circumstances. The obtained derivative of the numerical Id-VGS characteristics is also shown in Fig. 5 in blue. Observing curves in Fig. 5, it is possible to see that the capacitance and transconductance peaks occur at the same voltage. These results demonstrate excellent agreement with the experimental measurements. In particular, the capacitance peak (blue traces), obtained for different sets of channel parameters, appears at the same bias voltage at which the corresponding transconductance (red traces) exhibits its maximum value. Simulation findings indicate that the Cgs peak coincides with the gm maximum in terms of both peak value and corresponding voltage, revealing a strong relation of both parameters in accordance with [34].

[picture]

Fig. 4. Sketch of the TCAD structure. The structure is not to scale.

Fig. 4. Sketch of the TCAD structure. The structure is not to scale.

[picture]

Fig. 5. Numerical C-V curves obtained with a positive VDS (red curves, left y -axis) and corresponding transconductance (blue lines, right y-axis) from structure of Fig. 4.

Fig. 5. Numerical C-V curves obtained with a positive V D S (red curves, left y -axis) and corresponding transconductance (blue lines, right y-axis) from structure of Fig. 4.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

In this work, we performed non-classical C−V measurements on commercially available planar SiC MOSFETs. Experimental results were obtained by measuring the capacitance arising between Gate and Source terminals, while a fixed DC bias is applied to Drain terminal. The capacitance measured in this configuration showed a non-negligible peak. The arising peak appeared more prominent as the applied Drain voltage increases and its shape is related to the traps in the channel region under the SiC/SiO2 interface. Since interface traps in the channel affect this region physical properties, they have considerable impact on ID−VGS characteristics. Hence for the devices under test, transfer characteristics were also measured, with the aim of investigating the relation between the capacitance peak and the transconductance behavior. Experiments showed that the derivative of ID−VGS characteristics, obtained for the same VDS imposed in the C−V measurements, exhibits a maximum at the same voltage where the capacitance peak occurs, for both studied devices. In order to better understand experimental outcomes, a numerical analysis was performed in Sentaurus TCAD environment. Numerical curves presented exhibited the same experimental behavior: the capacitance peak obtained for different channel properties occurs at the same voltage where the transconductance reaches its maximum. This correlation highlights the direct link between the channel transport properties and the observed capacitance behavior, confirming that the adopted characterization technique is directly related to transconductance and it could be able to give information about channel properties.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

C. Raynaud, et al., Comparison of trapping-detrapping properties of mobile charge in alkali contaminated metal-oxide-silicon carbide structures, Applied physics letters 66, no. 18: 23402342, (1995).

D. Peters et al., Investigation of threshold voltage stability of SiC MOSFETs, ISPSD, (2018).

V. V. Afanasev, et al., Intrinsic interface states, physica status solidi (a) 162, no. 1: 321-337, (1997).

Lancellotti, L., Lisi, N., Veneri, P. D., Bobeico, E., Matacena, I., & Guerriero, P. (2019, July). Graphene-on-Silicon solar cells with graphite contacts. In 2019 International Conference on Clean Electrical Power (ICCEP) (pp. 199-203). IEEE.

Gobbo, C., Di Palma, V., Trifiletti, V., Malerba, C., Valentini, M., Matacena, I., ... & Tseberlidis, G. (2023). Effect of the interface on the charge extraction in Cd -free kesterite solar cells. Energies, 16(10), 4137.

Sonnet, A. M., Hinkle, C. L., Heh, D., Bersuker, G., & Vogel, E. M. (2010). Impact of semiconductor and interface-state capacitance on metal/high-k/GaAs capacitance-voltage characteristics. IEEE transactions on electron devices, 57(10), 2599-2606.

Lancellotti, L., Bobeico, E., Della Noce, M., Veneri, P. D., & Matacena, I. (2018, June). Work function determination of transparent contact for a: -Si heterojunction solar cells. In 2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC/I&CPS Europe) (pp. 1-5). IEEE.

Matacena, I., Guerriero, P., Lancellotti, L., Alfano, B., De Maria, A., La Ferrara, V., ... & Daliento, S. (2023). Impedance spectroscopy analysis of perovskite solar cell stability. Energies, 16(13), 4951.

Westerhoff, U., Kurbach, K., Lienesch, F., & Kurrat, M. (2016). Analysis of lithium-ion battery models based on electrochemical impedance spectroscopy. Energy Technology, 4(12), 16201630.

Matacena, I., Lancellotti, L., Daliento, S., Alfano, B., De Maria, A., La Ferrara, V., ... & Guerriero, P. (2023). Impedance Spectroscopy of Perovskite Solar Cells With SnO 2 Embedding Graphene Nanoplatelets. IEEE Journal of Photovoltaics.

Turut, A. (2020). On current-voltage and capacitance-voltage characteristics of metalsemiconductor contacts. Turkish Journal of Physics, 44(4), 302-347.

Matacena, I., et al. "Capacitance-Voltage Investigation of Encapsulated Graphene/Silicon Solar Cells." IEEE Transactions on Electron Devices (2023).

Gaberšček, M. (2022). Impedance spectroscopy of battery cells: Theory versus experiment. Current Opinion in Electrochemistry, 32, 100917.

Chang, Yao-Wen, et al. "Charge-based capacitance measurement for bias-dependent capacitance." IEEE Electron Device Letters 27.5 (2006): 390-392.

Almora, Osbel, et al. "On Mott-Schottky analysis interpretation of capacitance measurements in organometal perovskite solar cells." Applied Physics Letters 109.17 (2016).

Gobbo, Carla, et al. "Effect of the interface on the charge extraction in Cd -free kesterite solar cells." Energies 16.10 (2023): 4137.

Matacena, Ilaria, et al. "Forward bias capacitance investigation as a powerful tool to monitor graphene/silicon interfaces." Solar Energy 226 (2021): 1-8.

Heerens, W-C. "Application of capacitance techniques in sensor design." Journal of physics E: Scientific instruments 19.11 (1986): 897.

Schroder, D.K. Semiconductor Material and Device Characterization, 3rd ed.; Wiley: Hoboken, NJ, USA, 2006.

Hu, Chenming Calvin. "Modern Semiconductor Devices for Integrated Circuits." Part I: Electrons and holes in a semiconductor (2011).

I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, S. Daliento, & A. Castellazzi, (2022). SiC MOSFET CV Characteristics with Positive Biased Drain. In Materials Science Forum (Vol. 1062, pp. 653-657). Trans Tech Publications Ltd.

L. Maresca et al. Influence of the MOSFET Interface Traps Distribution on C V Measurements Evaluated by TCAD Simulations. IEEE Journal of Emerging and Selected Topics in Power Electronics 9.2 (2019): 2171-2179.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2022, June). Experimental Analysis of CV and IV Curves Hysteresis in SiC MOSFETs. In Materials Science Forum (Vol. 1062, pp. 669-675). Trans Tech Publications Ltd.

Matacena, Ilaria, et al. "SiC MOSFET CV Curves Analysis with Floating Drain Configuration." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

Matacena, Ilaria, et al. "Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Wei, Jiaxing, et al. "Interfacial damage extraction method for SiC power MOSFETs based on CV characteristics." 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). IEEE, 2017.

Tsuji, Katsuhiro, et al. "Measurement of MOSFET CV curve variation using CBCM method." 2009 IEEE International Conference on Microelectronic Test Structures. IEEE, 2009.

Jouha, Wadia, et al. "Physical study of SiC power MOSFETs towards HTRB stress based on CV characteristics." IEEE Transactions on Device and Materials Reliability 20.3 (2020): 506511.

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Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2023, July). SiC MOSFETs Biased CV Curves: A Temperature Investigation. In Materials Science Forum (Vol. 1091, pp. 31-36). Trans Tech Publications Ltd.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2024). Frequency Investigation of SiC MOSFETs CV Curves with Biased Drain. Solid State Phenomena, 360, 145-149.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2022, July). SiC/SiO 2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain. In 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp. 1-5). IEEE.

I. Matacena, A. Irace, S. Daliento and L. Maresca, "Investigation on Gate Capacitance Peak in SiC MOSFETs With Biased Drain," in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2025.3638294.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 35-41

doi: 10.4028/p-JdLnD2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-18

Accepted:
2026-01-31

Online:
2026-05-21

Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

Shane R. Stein 1,a*, Suman Das 1, b, Daniel J. Lichtenwalner 1,c and Sei-Hyung Ryu 1,d

1 Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

a* shane.stein@wolfspeed.com, b suman.das@wolfspeed.com, c  daniel.lichtenwalner@wolfspeed.com, d  sei-hyung.ryu@wolfspeed.com

Keywords: bias temperature instability, threshold voltage, hysteresis, charge pumping, triple sense method, interface traps, border traps.

Abstract

Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently can determine device lifetime. Most studies of BTI in SiC MOSFETs have characterized the threshold voltage ( VT ) but not the interface trap density ( Nit ), leaving uncertainty about the relative contributions of carrier capture and trap creation to the VT shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we measure Nit during positive bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in VT and hysteresis using the triple-sense method [1], [2] for comparison with the Nit changes to evaluate whether the changes in Nit are responsible for the VT and/or hysteresis changes, and demonstrate the utility of the technique for reliable characterization of VT and hysteresis in SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

In SiC MOSFETs, the VT shift with an applied gate bias consists of two components: (i) a fast, reversible hysteresis wherein VT rapidly shifts back or forth by a finite amount in response to a negative or positive gate bias, and (ii) a quasi-permanent shift of the hysteresis envelope itself with prolonged gate bias [3], [4]. The hysteresis is believed to result from the capture of electrons or holes in interface and border traps. When a sufficiently positive voltage is applied to the gate to form an inversion channel, electrons which accumulate at the interface are captured by these traps and the negative trapped charge shifts VT positively. Conversely, when a sufficiently negative voltage is applied to the gate to accumulate holes at the oxide-semiconductor interface, the positively charged holes become trapped and shift VT negatively. For interface traps, the capture rate during inversion and accumulation is very fast compared to emission, so VT responds rapidly to the change in gate bias, resulting in the observed hysteresis. On the other hand, the physical mechanism responsible for the quasi-permanent VT shift component is less clear. Generally, the candidate mechanisms are either carrier capture (particularly in border traps), or the creation of new interface traps which can then become charged and contribute to the VT shift [5]. Many studies have been published which carefully characterize and model the VT shift according to one mechanism or the other [6], but there is a lack of reports directly measuring the trap density to help confirm or rule out the role of interface trap generation in the VT shift.

Charge pumping (CP) has been demonstrated to be an effective and versatile technique for measuring Nit for both silicon [7] and SiC [8], [9] MOSFETs. Advantages of this technique are that it can be used on a fully fabricated MOSFET (as long as the source and body contact are separated) undergoing the same process conditions as a production MOSFET and containing a p-type body, and it measures Nit across most of the semiconductor bandgap, including both donor and acceptor traps on each side of the bandgap, and only excluding traps very close to the band edges. This makes the technique especially useful for measuring the density of traps that affect VT, which are located deeper than the Fermi level position when the gate is biased near VT.

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Fig. 1. (a) Bias sequence of the triple-sense method. (b) ID−VGS curves corresponding to the three VGS of the triple-sense method after a cumulative stress time of 1000 s .

Fig. 1. (a) Bias sequence of the triple-sense method. (b) I D − V G S curves corresponding to the three V G S of the triple-sense method after a cumulative stress time of 1000 s .

For the purpose of this study, it is also necessary to compare the Nit measured by CP with the VT and the hysteresis as a function of BTS duration. Since the VT shift for SiC MOSFETs consists of the two components mentioned above, it is critical to have a proper VT measurement technique to capture the full VT behavior during BTS, or at least a conditioning step to establish a repeatable MOS interface charge state after each BTS interval. The triple-sense method has been demonstrated to be an optimal method for this purpose [1], [2]. As the name implies, the method uses three gate voltage ( VGS ) sweeps after each bias stress interval to obtain three VT sense measurements. A diagram of the bias sequence and the corresponding ID−VGS curves for the triple-sense method are shown in Fig. 1. In the case of a positive gate bias stress, the first sweep is a down-sweep starting from inversion with minimal delay time after the stress interval to minimize VT relaxation due to electron emission from the interface/border traps, the second sweep is an up-sweep starting from accumulation in order to rapidly charge the interface positively by hole capture, and the third sweep is final down-sweep starting from inversion to negatively charge the interface again. VT,1 obtained from the first sweep thus represents the combined effects of the negative trapped charge that exists during channel inversion and any additional time-dependent electron trapping during the bias stress interval preceding the first sweep, and VT,2 and VT,3 represent the lower and upper ends of the quasi-permanent hysteresis envelope, respectively, after resetting the interface charge condition with the accumulation bias at the beginning of the second VGS sweep. Therefore, by using three VGS sweeps and corresponding VT measurements, the triple-sense method can capture all aspects of VT shift during BTS.

The purpose of this study is to provide insight into the physical mechanisms responsible for the quasi-permanent VT shift in SiC MOSFETs during BTS. Specifically, the goal is to clarify whether interface traps are generated during BTS and, if so, whether they are responsible for the observed VT shift. To accomplish this, CP is used to measure Nit, and the triple sense method is used to characterize the quasi-permanent VT shift and hysteresis, after each BTS interval. Finally the magnitudes of the VT and hysteresis shifts are compared with the Nit changes to evaluate whether they are caused by the Nit changes.

Experimental Details

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The devices studied are lateral test MOSFETs fabricated on 4∘ off-axis 4H−SiC epitaxial wafers, with an implanted acceptor concentration of 2×1017 cm−3 in the channel, a thermal gate oxide formed on the Si face followed by NO annealing, and a channel length and width of 2μ m and 200 μm, respectively. For the BTS, the device temperature was set to 175∘C, and a gate voltage well beyond the recommended operating voltage was applied in order to accelerate the VT shift, which corresponds to an oxide electric field of 7.3MV/cm. At the same time, this bias is low enough to avoid the onset of additional degradation mechanisms such as impact ionization in the oxide which occur at even higher electric fields [9], [10]. For the triple-sense sequence, VGS was swept down from

15 V to 0 V for the first and third sweep, and swept up from -8 V to 4 V for the second sweep. After each triple-sense sequence the CP sweep is performed using the constant-amplitude method, with a gate pulse amplitude of 15 V , a rise/fall time of 1μ s, and a high/low time of 10μ s.

Results and Discussion

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Fig. 2 shows the ID−VGS characteristics resulting from the triple-sense measurements throughout the BTS experiment. The ID−VGS curve shifts toward more positive voltages with increasing gate stress time ( tstress  ), and this is accompanied by an increase in the hysteresis between sweep #2 and sweep #3. The increase in hysteresis suggests that an increase in interface and/or border trap density is taking place during the BTS.
By choosing a reference current level to define VT, each VT from the triple-sense method can be plotted versus tstress  to evaluate the VT shift and calculate the hysteresis. Fig. 3(a) shows each VT and the calculated hysteresis (Vhyst ) versus tstress  using a reference current of 10 nA . From this plot the full

[picture]

Fig. 2. (a) Triple-sense sweep #3 for each BTS interval from 0 s to 1000 s of cumulative stress time. (b) Sweep #2 and #3 before and after the entire BTS duration, from which both the quasi-permanent VT and hysteresis can be seen to have increased.

Fig. 2. (a) Triple-sense sweep # 3 for each BTS interval from 0 s to 1000 s of cumulative stress time. (b) Sweep #2 and #3 before and after the entire BTS duration, from which both the quasi-permanent V T and hysteresis can be seen to have increased.

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Fig. 3. (a) Each VT of the triple-sense method versus stress time using a reference current of 10 nA , and the calculated hysteresis from the difference of VT,2 and VT,3. (b) The quasipermanent VT and hysteresis shifts (referred to the initial values before stress) as a function of stress time. The shifts can be fit to a power law, as is routinely done for BTI measurements.

Fig. 3. (a) Each V T of the triple-sense method versus stress time using a reference current of 10 nA , and the calculated hysteresis from the difference of V T , 2 and V T , 3 . (b) The quasipermanent V T and hysteresis shifts (referred to the initial values before stress) as a function of stress time. The shifts can be fit to a power law, as is routinely done for BTI measurements.

VT behavior can be seen as it evolves during the BTS. VT,1 is highest value as it contains the maximum contribution of electron trapping effects on VT with minimal relaxation after each stress interval. VT,2 is the lowest value since it results from the up-sweep starting in accumulation which conditions the interface to a positive charge state. VT,3 lies between VT,1 and VT,2 since it results from a down-sweep from inversion which conditions the interface to a negative charge state but comes after the accumulation conditioning of the up-sweep which effectively resets the interface condition after the preceding stress interval. The difference between VT,1 and VT,3 can then be attributed to any charge trapping occurring during the bias stress interval which responds quickly enough to be eliminated during the accumulation conditioning of the up-sweep; i.e., by recombination during hole capture. VT,2 and VT,3 together then form the hysteresis envelope, and the shift that each experiences in common can be attributed to the charge trapping or trap generation occurring during the bias stress interval which is too slow to respond or be eliminated during the accumulation conditioning. For this reason, this shift is labelled "quasi-permanent," and it is the VT shift that is most relevant during typical MOSFET operation in switching applications.

Fig. 3(b) shows the quasi-permanent shift of VT,2 and VT,3 over time, as well as the change in hysteresis. Most of the shift is common between VT,2 and VT,3, but there is also a small increase in the hysteresis as the two VT values slowly diverge with time. Since the triple-sense sweep and timing parameters are constant along the BTS duration, any change in hysteresis should be related to a change in trap density. This is where CP measurements can provide additional insight by characterizing Nit during BTS as well.

The change in Nit as a function of tstress  measured by CP is shown in Fig. 4 . The CP measurements confirm that additional interface traps are indeed generated during the BTS, which is consistent with the observed increase in hysteresis from the triple-sense measurements. The Nit change is quite small compared to the typical values measured for SiC MOS devices [8], [9], [11], which is also consistent with the fact that the hysteresis change is small relative to the quasi-permanent VT shift.

To characterize the change in Nit further, the rise and fall times of the charge pumping gate pulse were varied in order to modulate the upper and lower bounds of the energy window of interface traps measured within the SiC bandgap and thus extract the interface trap density energy distribution ( Dit ) close to the valence band edge ( EV ) and close to the conduction band edge ( EC ) [9]. Since this procedure is more time intensive, it was performed once before the BTS experiment and once after the total 1000 s duration, to compare the Dit profile before and after stress. Furthermore, to extend the energy range of the Dit distribution that could be extracted, the procedure was repeated at two measurement temperatures: 25∘C and 125∘C.

The resulting Dit profile on each side of the bandgap before and after the BTS is shown in Fig. 5. The baseline Dit distribution is consistent with previous observations for Si-face SiC MOSFETs [12], [13], [14], with a uniform and relatively low Dit near EV, and an exponential increase near EC. After

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Fig. 4. The change in interface trap density as a function of bias stress time, which also follows a power law similar to the VT shift.

Fig. 4. The change in interface trap density as a function of bias stress time, which also follows a power law similar to the V T shift.

[picture]

Fig. 5. The extracted Dit profile before and after 1000 s of positive bias-temperature stress (a) in the lower half of the bandgap near the valence band edge and (b) in the upper half of the bandgap near the conduction band edge, obtained by modulating the rise and fall times of the gate voltage pulse during charge pumping.

Fig. 5. The extracted D i t profile before and after 1000 s of positive bias-temperature stress (a) in the lower half of the bandgap near the valence band edge and (b) in the upper half of the bandgap near the conduction band edge, obtained by modulating the rise and fall times of the gate voltage pulse during charge pumping.

the BTS, Dit increases a small amount evenly on both sides of the bandgap, which means both acceptor and donor interface traps are generated during the BTS.

With both VT and Nit having been measured as a function of stress time, it is now of interest to compare these quantities to evaluate their correlation. To make a quantitative comparison, the quantity Vit=qNit/Cox was calculated, where q is the elementary charge and Cox is the specific oxide capacitance of the MOSFET. This quantity represents the total expected gate voltage shift between accumulation and inversion due to the interface trap density measured by CP. In other words, it is the expected hysteresis based on the measured Nit value.

Fig. 6(a) shows the change in VT,3 and the change in Vit plotted together versus tstress  for comparison. In the plot, ΔVT,3 is plotted for four different choices of reference current used to extract VT, which is seen to have minimal impact on the extracted ΔVT,3. The magnitude of ΔVT,3 is about 3× greater than ΔVit, indicating that the VT shift is caused primarily by factors other than the creation of interface traps, such as electron capture in border traps within the oxide.

[picture]

Fig. 6. The change in Vit plotted versus stress time alongside (a) the change in VT,2 and (b) the change in hysteresis, for comparison of the interface trap density changes measured by CP with the quasi-permanent VT and hysteresis changes measured with the triple-sense method. ΔVT,2 and ΔVhyst  are each plotted for four different choices of reference current used to extract VT.

Fig. 6. The change in V i t plotted versus stress time alongside (a) the change in V T , 2 and (b) the change in hysteresis, for comparison of the interface trap density changes measured by CP with the quasi-permanent V T and hysteresis changes measured with the triple-sense method. Δ V T , 2 and Δ V hyst are each plotted for four different choices of reference current used to extract V T .

In Fig. 6(b), the change in hysteresis and the change in Vit are plotted together versus tstress  for comparison. The choice of reference current used to measure VT is seen to have a significant impact on the ΔVhyst  extracted. This can be interpreted as a result of the different amounts of band bending which occur depending on the current level used, which changes the energy range of the interface trap distribution causing the hysteresis. For the lower current levels, ΔVit and ΔVhyst  converge with increasing time, indicating that the generated interface traps measured by CP are responsible for the increase in hysteresis during the BTS.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

In summary, using CP measurements and the triple-sense method, we have been able to deduce certain facts about the physical mechanisms responsible for BTI in SiC MOSFETs. First, CP measurements revealed that interface traps are generated during positive BTS. Second, the quasipermanent VT shift during sBTS was significantly greater than the voltage shift caused by the generated Nit, which allows us to conclude that the VT shift is not primarily caused by interface trap creation, but by other effects such as charge capture by border traps. Lastly, the hysteresis envelope widened during the BTS, and the magnitude of the change was equal to the voltage shift due to the generated Nit, from which we can conclude that the generated interface traps are responsible for the increase in hysteresis. These insights into the physical mechanisms responsible for BTI are valuable for enabling the modeling and prediction of BTI related degradation and parameter shifts in SiC MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

D. J. Lichtenwalner, "Demonstration of the Benefits of Measuring SiC MOSFET BTI using a Triple Sense Method," in 2025 IEEE International Reliability Physics Symposium (IRPS), Mar. 2025, pp. 1-5. doi: 10.1109/IRPS48204.2025.10983888.

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T. Aichinger, G. Rescher, and G. Pobegen, "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs," Microelectronics Reliability, vol. 80, pp. 68-78, Jan. 2018, doi: 10.1016/j.microrel.2017.11.020.

J. H. Stathis, S. Mahapatra, and T. Grasser, "Controversial issues in negative bias temperature instability," Microelectronics Reliability, vol. 81, pp. 244-251, Feb. 2018, doi: 10.1016/j.microrel.2017.12.035.

T. Grasser et al., "The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction-Diffusion to Switching Oxide Traps," IEEE Trans. Electron Devices, vol. 58, no. 11, Art. no. 11, Nov. 2011, doi: 10.1109/TED.2011.2164543.

G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. 31, no. 1, Art. no. 1, Jan. 1984, doi: 10.1109/T-ED.1984.21472.

A. Salinaro et al., "Charge Pumping Measurements on Differently Passivated Lateral 4H-SiC MOSFETs," IEEE Trans. Electron Devices, vol. 62, no. 1, Art. no. 1, Jan. 2015, doi: 10.1109/TED.2014.2372874.

S. R. Stein, J. Kim, S. Das, D. J. Lichtenwalner, and S. Ryu, "Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress," in 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA: IEEE, Apr. 2024, pp. 1-5. doi: 10.1109/IRPS48228.2024.10529394.

F. Masin et al., "Non-monotonic threshold voltage variation in metal-oxidesemiconductor field-effect transistor: Investigation and modeling," Journal of Applied Physics, vol. 130, no. 14, p. 145702, Oct. 2021, doi: 10.1063/5.0057285.

T. Hatakeyama et al., "Impact of crystal faces of in structures on interface trap densities and mobilities," Appl. Phys. Express, vol. 12, no. 2, Art. no. 2, Feb. 2019, doi: 10.7567/1882-0786/aaf283.

H. Yoshioka, T. Nakamura, and T. Kimoto, "Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance," Journal of Applied Physics, vol. 111, no. 1, Art. no. 1, Jan. 2012, doi: 10.1063/1.3673572.

G. Rescher, G. Pobegen, T. Aichinger, and T. Grasser, "On the subthreshold drain current sweep hysteresis of 4H-SiC nMOSFETs," in 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA: IEEE, Dec. 2016, p. 10.8.1-10.8.4. doi: 10.1109/IEDM.2016.7838392.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 43-47

doi: 10.4028/p-3xeuTP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-09

Accepted:
2026-03-16

Online:
2026-05-21

Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

The original version of this paper is available on https://www.scientific.net/KEM.1057.43.pdf

Luigi Di Benedetto 1,a*, Nicola Rinaldi 1, b, Mathias Rommel 2,c, Alexander May 2, d, Leander Baier 2,e, Rosalba Liguori 1,f, Alfredo Rubino 1, g and Gian Domenico Licciardo 1, h

¹Department of Industrial Engineering, University of Salerno, Via Giovanni Paolo II, 132, Fisciano, Italy

2 Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystraße 10, Erlangen, Germany

a  Idibenedetto@unisa.it, b  nrinaldi@unisa.it, c  mathias.rommel@iisb.fraunhofer.de,

d alexander.may@iisb.fraunhofer, e leander.baier@iisb.fraunhofer.de, f rliguori@unisa.it, g arubino@unisa.it, h gdlicciardo@unisa.it

Keywords: cryogenic temperatures, NOT logic gate, 4H-SiC lateral CMOS technology.

Abstract

In this paper, the electrical characterizations of a 4H−SiC CMOS NOT logic gate are performed in the temperature range from 300 K down to 100 K and the results are analyzed. The integrated circuit is fabricated with the Fraunhofer IISB 4H-SiC 2μ m CMOS technology and the lateral NMOSFET and PMOSFET have channel form factor of 6/6 and 44/6, respectively. The circuit is supplied with a 20 V . The curves show a reduction of the threshold voltage from 8.96 V to 6.85 V reducing the temperature from 300 K to 100 K and an ever-widening region in the High side (NMOSFET in saturation and PMOSFET in triode regime) compared to the Low side (NMOSFET in triode and PMOSFET in saturation regime). However, the noise margins are still wide enough for practical applications, making the circuit still useful. The behavior can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. Finally, analysis also focuses on the power dissipation during the transition of the output voltage from high (low) to low (high).

Introduction

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Nowadays, 4H-Silicon Carbide semiconductor devices are largely used in power electronics or for high-temperatures applications [1]. Its widespread availability permitted the fabrication of highquality substrates together with the improvements of the oxidation and of the ion implantation processes provided the basis for the development of new technologies, like 4H−SiC Complementary Metal Oxide Semiconductor, CMOS [2]. Indeed, 4H-SiC CMOS Integrated Circuits have been demonstrated to operate up to 873 K [3] or to allow integration of other devices, like diodes [3] or UV [4] sensors, opening new application fields. On the other hand, electronics for space explorations needs good radiation hardness, reducing the shielded package, and capability to operate at temperatures lower than 150 K . Moreover, the possibility of a single device to operate from 800 K down to 100 K with such huge temperature range is interesting both for scientific and for industrial purposes. Actually, only a few papers showed the operability of 4H−SiC devices at cryogenic temperatures from single vertical diodes [5] to power MOSFETs [6] as well as about lateral 4H−SiC MOSFETs [7-8]. However, there are lacks of information about the understanding of 4H−SiC device performances at low temperatures, like the effects of the incomplete ionization of Aluminum or of the interface trap density [9], and experimental results needs for an in-depth analysis.

In this context, our paper shows the electrical performance of a 4 H -SiC CMOS NOT logic gate, which is the core circuit for digital electronics. It has been measured in the temperature range from 300 K down to 100 K with the aim to analyze and understand the limits of 4H−SiCCMOS technology at cryogenic temperatures.

Fabrication Process and Experimental Set-Up

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The Fraunhofer IISB 4H−SiC2μ m CMOS technology [2] is used to fabricate the NOT logic gate, where the channel width of the NMOSFET, MN, and PMOSFET, MP, are 6μ m and 44μ m, respectively, whereas the channel length is even to 6μ m for both devices. In Fig. 1 a simplified crosssection of the device structures is reported. On a 4H−SiC n-type 350μ m4∘ off-axis (0001) substrate, a n-type epitaxial layer is grown with doping concentration of 1015 cm−3 and thickness of 10μ m. Selective doping regions are made through ion implantations of Aluminum and Nitrogen dopant atoms, respectively, for p-type and n -type regions and doping concentrations of 5·1019 cm−35,1017cm−3,1016 cm−3 are for high doping regions, p-type and n-type wells. After ion implantation, thermal activation annealing at 1973 K for 30 minutes is made. Then, thermal gate oxide of 55 nm -thick is grown and post-annealed at 1573 K in NO ambient and covered with n-type high doped poly-silicon. The resulting gate capacitance, Cox, is equal to 62.8nF/cm2. Silicide of Ti/Al and NiAl are formed on p+and n+-regions, respectively, and Ti/Pt is used as metal stack layers.

Measurement set-up consists of a HP 4145A for the electrical characterization and of a closed cycle cryo-system attoDRY800xs [10] and the temperature is monitored with a Cernox RTDs temperature sensor [11]. The samples are bonded on special PCB and positioned on the sample holder in order to cool down from 300 K to 100 K with a temperature step of 25 K .

[picture]

Fig. 1. A cross-section view of the 4H−SiC CMOS device structures.

Fig. 1. A cross-section view of the 4 H − S i C CMOS device structures.

Experimental Measurements and Discussion of the Analysis

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In Fig. 2 VIN -Vout characteristics are shown with a supply voltage, VDD, of 20 V and by varying the temperature from 100 K to 300 K with a step of 25 K . At 300 K the CMOS NOT has a threshold voltage, VM, of 8.96 V and, hence, is not fully complementary, i.e., VM≠VDD/2, because NMOSFET is more conductive than PMOSFET.

Observing the curves, the reduction of the temperature modifies the transfer-characteristics both shifting toward lower VIN  and decreasing the gain in the transition region. Indeed, in Fig. 3 we report VM as function of the temperature and it changes from 8.96 V at r.t. to 8.53 V at 200 K and to 6.85 V at 100 K , which is a reduction of −23.55% respect to r.t. It is worth to note that at 100 K the value of VM is still valid as NOT logic gate. Further, the high output voltage, Voh , is 19.98 V from 300 K to 150 K , but decreases to 19.95 V at 125 K and to 19.64 V at 100 K , whereas the low output voltage, VOL, is nearly 0 V . On the other hand, the variations of the VM and of the gain cause a significative reduction of VIL and VIH values: from 300 K to 100 K , VIH decreases from 9.89 V to 7.17 V and VIL from 8.18 V to 5.5 V . In Tab. 1 the main parameters of the NOT logic gate are reported for different temperatures.

[picture]

Fig. 2. VIN −VOut  characteristics from 100 K to 300 K with a T-step of 25 K . The inset shows Voltage Transfer Characteristics for the estimation of the Noise Margin and the NOT logic gate

Fig. 2. V IN − V Out characteristics from 100 K to 300 K with a T-step of 25 K . The inset shows Voltage Transfer Characteristics for the estimation of the Noise Margin and the NOT logic gate

[picture]

Fig. 3. Threshold voltage, VM, and High and Low Noise Margin, NMH and NML, as function of the temperature measured at VDD=20 V.

Fig. 3. Threshold voltage, V M , and High and Low Noise Margin, N M H and N M L , as function of the temperature measured at V D D = 20 V .

Table 1. Parameter of the Voltage-Transfer Characteristic of the 4H−SiC CMOS NOT logic gate as function of the temperature at VDD=20 V.

T [K] | VIL [V] | VIH [V] | VOL [V] | VOH [V] | VM [V] | NML [V] | NMH [V]
100 | 5.5 | 7.17 | ~0 | 19.64 | 6.85 | 5.5 | 12.47
150 | 7.11 | 8.54 | ~0 | 19.96 | 8.02 | 7.11 | 11.44
200 | 7.75 | 9.21 | ~0 | 19.98 | 8.53 | 7.75 | 10.77
250 | 8.06 | 9.62 | ~0 | 19.98 | 8.81 | 8.06 | 10.22
300 | 8.18 | 9.89 | ~0 | 19.98 | 8.96 | 8.18 | 10.09

Moreover, in the inset of Fig. 2 the area related to the High Noise Margin, NMH, increases compared to that of Low Noise Margin, NML, and in Fig. 3 their values are reported. They are defined as NMH=VOH−−VIH and NML=VIL−VOL. At 300 KNMH and NML are worth, respectively, 10.09 V and 8.18 V and, then, they have different behaviour with the reduction of the temperature: indeed, NMH increases to 10.77 V at 200 K and to 12.47 V at 100 K , whereas NML reduces to 7.75 V at 200 K and to 5.5 V at 100 K . In Tab. 1 detailed results are also reported. In both cases, their values make still useful the circuit for practical applications.

The temperature behavior of the Voltage-Transfer characteristic of NOT logic gate can be ascribed to the reduction of the conductivity of the PMOSFET and to the still valid operation of the NMOSFET down to 100 K . Indeed, in [7] 4H-SiC lateral PMOSFET diode-connect temperature sensors vary their characteristics around 175 K due to a significative reduction of the field-effect channel mobility, μCH,P : at a current of 1μ A,μCH,P is equal to 5.59 cm2/V/s at T=300 K and decreases to 0.2 cm2/V/s at 150 K , and to 0.07 cm2/V/s at T=100 K. Being μCH,P proportional to free/trapped carrier ratio, such reduction of μCH,P is related to the reduction of the free/trapped carriers ratio with the temperature, because the Fermi level moves toward the valence band [12]. On the other hand, NMOSFET field-effect channel mobility, μCH,N, decreases from 4.25 cm2/V/s at 300 K to 2.9 cm2/V/s at 150 K , but then increases to 3.38 cm2/V/s at 100 K at a current of 1μ A [8].

Finally, Static power dissipation is analyzed through the supply current, IDD, that is normalized with that at r.t., IDD,300 K, and it is reported as function of VIN  in Fig. 4. IDD reduces with the temperature and at 200 K is one order lower than 300 K until to have more than two orders of magnitude at 100 K . This advantageous reduction of the power dissipation is expected when electronic circuits operate at cryogenic temperatures [13].

[picture]

Fig. 4. Normalized supply currents, IDD/IDD,300 K, respect to 300 K as function of the input voltage for temperatures from 100 K to 275 K with a T-step of 25 K and measured at VDD=20 V.

Fig. 4. Normalized supply currents, I D D / I D D , 300 K , respect to 300 K as function of the input voltage for temperatures from 100 K to 275 K with a T-step of 25 K and measured at V D D = 20 V .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.43.pdf

In this paper the voltage transfer characteristics of 4H−SiC CMOS NOT logic gates are measured from r.t. down to 100 K showing the operability of the circuit in cryogenic temperature range. Indeed, although a reduction of the threshold voltage and of the low noise margin is evident, the values are still valid for its functionality as logic gate. Also, the expected reduction of the supply current during the transition from high (low) to low (high) output values is confirmed. The worsening of the static characteristic is mainly ascribed to the reduction of the field-effect channel mobility of PMOSFET. To have a complete understanding of the 4H−SiC CMOS NOT logic gate, dynamic characterizations are necessary as well as a long-term performance need to be addressed.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.43.pdf

P. G. Neudeck, D. J. Spry, L. Chen, N. F. Prokop, and M. J. Krasowski, Demonstration of 4hsic digital integrated circuits above 800∘C, IEEE Electron Device Letters, 38 (2017) 8, 10821085.

"Fraunhofer Institute for Integrated Systems and Device Technology (IISB)," .

J. Mo, J. Li, Y. Zhang, J. Romijn, A. May, T. Erlbacher, and S. Vollebregt, A highly linear temperature sensor operating up to in a 4 H -SiC CMOS technology. IEEE Electron Device Letters, 44 (2023) 6, 995-998.

L. Di Benedetto, G.D. Licciardo, T. Erlbacher, A.J. Bauer, and A. Rubino, A 4H-SiC UV phototransistor with excellent optical gain based on controlled potential barrier, IEEE Transactions on Electron Devices, 67 (2019) 1, 154-159.

C. D. Matthus, L. Di Benedetto, M. Kocher, A. J. Bauer, G. D. Licciardo, A. Rubino, and T. Erlbacher, Feasibility of p-i-n Diode for Sensitive Temperature Measurements Between 20.5 K and 802 K, IEEE Sensors Journal 19 (2019) 8, 2871-2878.

Y. Wei, M.M. Hossain, and H. A. Mantooth. Comparisons and evaluations of silicon and wide band gap devices at cryogenic temperature, IEEE Transactions on Industry Applications 59 (2022) 2, 1982-1994.

N. Rinaldi, M. Rommel, A. May, R. Liguori, A. Rubino, G.D. Licciardo, and L. Di Benedetto, Analysis of a lateral PMOSFET temperature sensor between . IEEE Sensors Letters, 9 (2025) 3, 2501504.

N. Rinaldi, M. Rommel, A. May, R. Liguori, A. Rubino, G. D. Licciardo, L. Di Benedetto, A 4H-SiC NMOSFET-based temperature sensor operating between 14 K and 481 K , IEEE Electron Device Letters, 45 (2024) 11.

L. Di Benedetto, N. Rinaldi, G.D. Licciardo, R. Liguori, A. Rubino, A. May, and M. Rommel, Performance and Understanding of 4H-SiC Electron Devices at Low Temperature Range. 2024 IEEE International Semiconductor Conference (2023) 23-28.

Information on .

Information on .

X. Chi, K. Tachiki, K. Mikami, M. Kaneko, and T. Kimoto, Different temperature dependence of mobility in n-and p-channel 4H-SiC MOSFETs. Japanese Journal of Applied Physics, 62 (2023), 110906.

R. M. Fox, and R.C. JAEGER, MOSFET behavior and circuit considerations for analog applications at 77 K . IEEE Transactions on electron Devices, 34 (1987) 1, 114-123.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 49-54

doi: 10.4028/p-5MC2iz

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-18

Accepted:
2026-01-31

Online:
2026-05-21

Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

Nicola Rinaldi 1,a*, Luigi Di Benedetto 1, b, Mathias Rommel 2,c,

Alexander May 2, d, Leander Baier 2,e, Rosalba Liguori 1,f, Alfredo Rubino 1, g and Gian Domenico Licciardo 1, h

¹Department of Industrial Engineering, University of Salerno, Via Giovanni Paolo II, 132, Fisciano, Italy

2 Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystraße 10, Erlangen, Germany

a* nrinaldi@unisa.it, b Idibenedetto@unisa.it, c mathias.rommel@iisb.fraunhofer.de, d  alexander.may@iisb.fraunhofer.de, eleander.baier@iisb.fraunhofer.de, f  rliguori@unisa.it, g  arubino@unisa.it, h  gdlicciardo@unisa.it

Abstract

Experimental analysis of 4H−SiC lateral MOSFETs characteristics up to 773 K is shown. The reduction of threshold voltage, VTH, and the increase of the field effect channel mobility, μCH, with temperature cause an increase of MOSFET current up to 623 K . However, when scattering with lattice vibration starts to be predominant, μCH decreases with an abrupt drop at 773 K , reducing MOSFET current. Channel resistance, RCH, decreases with the temperature up to the range between 523 K and 573 K , implying possible thermal instability effects. However, when the temperature increases over this range, the thermal scattering predominates and RCH again increases, ensuring thermal stability of MOSFETs.

Keywords: high temperature, 4H−SiC lateral MOSFETs, 4H−SiC CMOS technology.

Introduction

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Electron devices capable of operating at high temperature condition are required for harsh environment applications. To this aim, wide band-gap semiconductors are the most suitable [1]. 4HSiC CMOS technology is emerging among others, such as JFET [2, 3] and BJT ones [4], thanks to the ease of manufacturing and the possibility of easily achieving complementarity, necessary requirement for integrated circuits, ICs, design. However, there is still a lack of knowledge about electrical behaviour of single lateral NMOSFETs and PMOSFETs under high temperature operation, which is a starting point to understand and to improve technology performances and applications. Experimental characteristics of 4 H -SiC lateral MOSFETs have been shown up to 773 K [5, 6], however they are limited to devices with wide channel width, i.e. W=100μ m and W=150μ m, which are unusual for ICs design. Also, sensors based on diode connected MOSFETs have been shown up to 873 K [7], but the analysis is not supported by key physical parameters, like threshold voltage, VTH, and channel mobility, μCH. Moreover, in [8] experimental characteristics of 4H-SiC lateral MOSFETs have been analyzed in a limited temperature range, i.e. up to 573 K , and the effects of interface state defects are evaluated through numerical simulation tools. However, in [5-8] no considerations regarding thermal stability of devices through the extracted channel resistance have been provided. In this paper, we experimentally investigate the I-V characteristics of 4H−SiC lateral MOSFETs up to 773 K , through the extraction of physical parameters like VTH and μCH. Moreover, thermal stability analysis has been done through the extracted channel resistance.

Device Structure and Experimental Set-Up

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Lateral MOSFETs have been fabricated in 4H-SiC CMOS Fraunhofer IISB's Technology [9]. A 1015 cm−3 Nitrogen doped epitaxial layer is grown on a SiC n-type 350μ m4∘ off-axis ( 0001 ) substrate. Aluminum and Nitrogen ion implantation, followed by a 1973 K,30 min, thermal annealing in Argon environment is performed for p -type and n -type doped regions. Resulting in a p -well with a doping
concentration of 1017 cm−3 and in a n -well with 1016 cm−3, whereas source and drain regions have a 5·1019 cm−3 doping concentration. The gate oxide is thermally grown at 1300∘C and a post-oxidation annealing in NO environment is performed at 1300∘C to reduce the interface state density. It results in a 55 nmSiO2 thick gate oxide with an oxide capacitance, Cox, of 62.8nF/cm2. A 500 nm n-type PolySilicon is deposited for the gate electrode, and a further 400 nm -thick oxide is deposited to gate electrode isolation. NiAl and Ti/Al are used for n-type and p-type contact materials. SiO2/Si3 N4/SiO2 stack is deposited by plasma enhanced chemical vapor deposition (PECVD) to isolate metals layers. These are made by Ti/Pt to allow high temperature operation [10]. Fabricated NMOSFET and PMOSFET have both channel width, W=24μ m, and channel length, L=6μ m.
Measurements have been performed in ambient atmosphere by heating the devices with a 630W G.Maier Elektrotechnick GmbH hotplate and measuring with a Keithley SCS-4200, a SUSS PM5 probe station and with Signatone Corporation manipulators equipped with Tungsten high temperature probe tips.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

High Temperature Characteristics.

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

I-V-T characteristics have been performed in T∈[298;773] with a ΔT=50K. The output characteristics, at |VGS|=20 V, of lateral NMOSFET and PMOSFET are shown in Fig.1.a)-b), respectively, whereas trans-characteristics, at |VDS|=0.1 V, are in Fig. 1.c)-d), both devices have W=24μ m and L=6μ m.

[picture]

Fig. 1. Output characteristics, |VGS|=20 V, of a) NMOSFET and b) PMOSFET, and trans-characteristics, |VDS|=0.1 V of c) NMOSFET and d) PMOSFET. Both with L=6μ m and W=24μ m, VBS=0 V, and T∈[298;773] with ΔT=50 K.

Fig. 1. Output characteristics, | V G S | = 20 V , of a) NMOSFET and b) PMOSFET, and trans-characteristics, | V D S | = 0.1 V of c) NMOSFET and d) PMOSFET. Both with L = 6 μ m and W = 24 μ m , V B S = 0 V , and T ∈ [ 298 ; 773 ] with Δ T = 50 K .

NMOSFET current increases with temperature by 100% up to 573 K and for VGS=VDS=20 V. Then, it increases by only 3.6% in T∈[623;723]K (see Fig.1.a)) and at T=773 K it decreases, as can be also observed in IDS−VGS characteristics of Fig. 1.c). Similarly, as shown in Fig.1.b), PMOSFET current increases up to T=573 K by 125% at VSG=VSD=20 V, then it reduces at T=773 K by −2.67%.

To explain MOSFET electrical behavior, key physical parameters, like threshold voltage and channel mobility have been extracted and their temperature behavior linked to MOSFET ones.

Threshold Voltage.

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

VTH has been extracted, for both NMOSFET and PMOSFET, from the trans-characteristics of Fig.1.c)-d) with the extrapolation in linear region method [11]. Both MOSFETs show a non-linear reduction with temperature increase, as shown in Fig. 2. The non-linearity can be explained through VTH  equation [12]:

VTH=φms+2ψB+4εSiCqNAψBCox+qQfCox+qDit(T)Cox(1)

where φms is the work function difference between the n -type Polysilicon and SiC, ψB the difference between the Fermi potential with respect to the midgap, εSiC the 4H−SiC dielectric permittivity, q the elementary charge, NAp-well doping concentration, Qf the fixed charge, and Dit(T) the temperature dependent interface defects. The high density of SiO2/4H−SiC interface defects and their temperature dependence introduce non-linearity [13-15], being directly linked to VTH through Eq.1.

[picture]

Fig. 2. VTH−T dependence for NMOSFET and PMOSFET in T∈ [298;773] with ΔT=50 K.

Fig. 2. V T H − T dependence for NMOSFET and PMOSFET in T ∈ [298;773] with Δ T = 50 K .

Channel Mobility

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

μCH has been extracted from trans-characteristics of Fig.1.c)-d) according to:

μCH=dIDSdVGS|VDS=0.1VLVDSCoxW(2)

Both NMOSFET and PMOSFET show an increase of field effect channel mobility peak up to T=523 K, then it starts to decrease (see Fig.3). Indeed, it increases up to μCH,N peak =21.75 cm2/Vs and μCH,P peak =8.25 cm2/Vs for NMOSFET and PMOSFET, respectively, whereas a minimum value is observed at T=773 K, with μCH,N peak =14.28 cm2/Vs and μCH,P peak =6.78 cm2/Vs. This behaviour can be explained in this way: the reduction of interface trapped charge with temperature causes a reduction of Coulomb scattering, allowing the channel mobility increase [16], but when the thermal scattering starts to be dominant the channel mobility decreases [12].

[picture]

Fig. 3. Extracted channel mobility for a) NMOSFET and b) PMOSFET, at |VDS|=0.1 V in Tϵ[298;773]K.

Fig. 3. Extracted channel mobility for a) NMOSFET and b) PMOSFET, at | V D S | = 0.1 V in T ϵ [ 298 ; 773 ] K .

The combined effect of VTH-reduction and μCH-increase with temperature causes a MOSFETs current increase up to T=623 K. However, when the reduction of channel mobility, due to thermal scattering starts to dominate, |IDS| reduces, as can be seen at T=773 K of Fig.1.c)-d).

Channel Resistance.

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

The current thermal behaviour explains channel resistance, RCH, temperature behaviour, which is shown in Fig.4. RCH has been extracted for both NMOSFET and PMOSFET from the output characteristics of Fig.1.a)-b) at |VDS|=0.1 V, by subtracting parasitic series resistance contribution, due to the implanted regions and contact resistance [17]. n-Channel resistance reaches a minimum at T=573 K of 11.5kΩ, whereas p-Channel resistance minimum of 36kΩ is at T=523 K. such reduction implies an increase of the current with temperature, in those applications where a bias voltage is applied, and therefore a possible self-heating effect can induce a thermal instability of the devices. However, the further increase of resistance at higher temperatures, as shown in Fig.4, reduces the thermal-run-away of the current, allowing a thermally stable device.

[picture]

Fig. 4. RCH−T of a) NMOSFET and b) PMOSFET in Tϵ[298;773]K, at |VGS|=20 V and |VDS|=0.1 V.

Fig. 4. R C H − T of a) NMOSFET and b) PMOSFET in T ϵ [ 298 ; 773 ] K , at | V G S | = 20 V and | V D S | = 0.1 V .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

Experimental analysis of 4H−SiC lateral MOSFET is shown between 298 K and 773 K . The MOSFET current temperature behavior can be related to the VTH and μCH temperature dependence. The current increases up to T=623 K and it stays almost constant in T∈[623;723]K. However, |IDS| starts to abruptly decrease when scattering carriers with lattice vibration becomes predominant on channel mobility, which abruptly decreases. Analysis of RCH−T behavior shows that possible self-heating problems could be due to decrease of RCH with temperature. However, the RCH increase at higher temperature guarantees the thermal stability of MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

[1] P. G. Neudeck, R.S. Okojie, L.Y. Chenl. High-temperature electronics-a role for wide bandgap semiconductors?. Proceedings of the IEEE 90.6 (2002): 1065-1076.

Spry, D. J., Neudeck, P. G., Chen, L., Lukco, D., Chang, C. W., & Beheim, G. M. (2016). Prolonged demonstration of 4 H -SiC JFET ICs with two-level interconnect. IEEE Electron Device Letters, 37(5), 625-628.

M. Kaneko, M. Nakajima, Q. Jin, T.Kimoto, SiC complementary junction field-effect transistor logic gate operation at 623 K . IEEE Electron Device Letters 43.7 (2022): 997-1000.

L. Lanni, B.G. Malm, M. Östling, C.M. Zetterling, Lateral pnp transistors and complementary SiC bipolar technology. IEEE electron device letters 35.4 (2014): 428-430.

Z. Dong, Y. Bai, C. Yang, Y. Tang, J. Hao, X. Li, X. Tian, X. Liu, Impact of Temperature on Digital Integrated Circuits in a CMOS Technology. IEEE Transactions on Electron Devices (2024).

J. Mo, Y. Niu, A. May, M. Rommel, C. Rossi, J. Romijn, G. Zhang, S. Vollebregt, An analog to digital converter in a SiC CMOS technology for high-temperature applications. Applied Physics Letters 124.15 (2024).

J. Mo, , A.May, M.Rommel, S. Vollebregt, G. Zhang, Temperature Sensing Elements for Harsh Environments in a CMOS Technology. IEEE Transactions on Electron Devices (2024).

H. Wang, P. Lai, A. Abbasi, M.M. Hossain, A. Faruque, H.A. Mantooth, Z. Chen. Characterization of Silicon Carbide Low-Voltage -Channel MOSFETs at High Temperatures. IEEE Journal of the Electron Devices Society (2024).

N. Rinaldi, M. Rommel, A. May, R. Liguori, A.Rubino, G.D. Licciardo, L. Di Benedetto, A 4H-SiC NMOSFET-based temperature sensor operating between 14 K and 481 K ." IEEE Electron Device Letters (2024).

R.M. Tiggelaar, R.G.P Sanders, A.W. Groenland, J.G.E. Gardeniers, Stability of thin platinum films implemented in high temperature microdevices, Sensors and Actuators A: Physical 152.1 (2009): 39-47.

A. Ortiz-Conde, F.J.G. Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, Y.Yue, A review of recent MOSFET threshold voltage extraction methods. Microelectronics reliability 42.4-5 (2002): 583-596.

S.M. Sze, K.K. Ng, Physics of semiconductor devices. John wiley & sons, 2007.

G.D. Licciardo, L. Di Benedetto, S. Bellone, Modeling of the interface-trapped charge as a function of the surface potential in vertical-DMOSFET. IEEE Transactions on Electron Devices 63.4 (2016): 1783-1787.

S. L. Rumyantsevet, M.S. Shur, M.E. Levinshtein, P.A. Ivanov, J.W. Palmour, A.K. Agarwal, B.A. Hull, S.H. Ryu. Channel mobility and on-resistance of vertical double implanted 4H-SiC MOSFETs at elevated temperatures. Semiconductor science and technology 24.7 (2009): 075011.

S. Harada, R. Kosugi, J.Senzaki, S. Suzuki, W.J. Cho, K. Fukuda, K. Arai. Temperature dependences of channel mobility and threshold voltage in 4 H -and 6 H -SiC MOSFETs. MRS Online Proceedings Library 640.1 (2000): 37.

V. Uhnevionak, A. Burenkov, C. Strenger, G. Ortiz, E. Badel-Pereira, V.Mortet, F. Cristiano, A.J. Bauer, P.Pichler. Comprehensive study of electron scattering mechanisms in MOSFETs, IEEE Transactions on Electron Devices 62.8 (2015): 2562-2570.

M. Rommel, A. May, L. Baier, N.Böttcher, M. Jank, Investigation of Ohmic Contacts and Resistances of a 4 H -SiC CMOS Technology up to 550 Degrees C. Journal of Microelectronics and Electronic Packaging 21.4 (2024): 73-79.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 55-62

doi: 10.4028/p-HeV6Em

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-28

Accepted:
2026-02-26

Online:
2026-05-21

Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Jenny Damcevska 1,2,a*, Sima Dimitrijev 1,2,b, Daniel Haasmann 1,2,c, Philip Tanner 1, d, Fanpeng Zeng 3,e, Lan Luo 3,f, Yingxin Cui 3, g, Yu Zhong 3, h and Jisheng Han 1,3,i

¹Queensland Quantum and Advanced Technologies Research Institute, Griffith University, Nathan, Brisbane, QLD, 4111, Australia

2 School of Engineering and Built Environment, Griffith University, Nathan, Brisbane, QLD, 4111, Australia

3 Institute of Novel Semiconductors, 27 Shanda Nan Lu, Central Campus, Shandong University, Jinan, Shandong 250100, China

a* jenny.damcevska@griffithuni.edu.au, b s.dimitrijev@griffith.edu.au, c d.haasmann@griffith.edu.au, d  p.tanner@griffith.edu.au, e  202420644@mail.sdu.edu.cn, f  lan.luo@mail.sdu.edu.cn, g  cuiyingxin@sdu.edu.cn, h  yu.zhong@sdu.edu.au, j  j.han@sdu.edu.cn

Keywords: merged PN Schottky diode, non-repetitive surge current, repetitive surge current, Schottky barrier diode, silicon carbide, surge current.

Abstract

The repetitive peak forward surge current ( IF,RM ) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the nonrepetitive peak forward surge current value ( IF,SM ) in datasheets, which is generally determined from derated measured peak currents that cause diode failures. Consequently, it is assumed that IF,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine IF,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature does not exceed the maximum device rating, which is 175∘C for the commercially available devices analysed in this study.

Introduction

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Silicon carbide Schottky diodes have become indispensable in modern power electronics due to their superior material properties compared to conventional silicon devices. Their wide energy gap, high critical electric field, and excellent thermal conductivity enable fast switching, low reverse recovery charge, and high efficiency operation at elevated voltages and temperatures [1,2]. These characteristics make SiC Schottky diodes particularly attractive for applications in renewable energy systems, electric vehicles, and high-frequency power conversion, where energy efficiency, reliability, and compact form factors are paramount. A practically important parameter for ensuring the reliability of SiC Schottky diodes in such demanding applications is the repetitive peak forward surge current, IF,RM. This parameter governs how devices perform under repeated surge or inrush conditions, such as those encountered during startup transients, short-circuit events, or highly dynamic load changes. However, despite its importance for robust circuit designs, no standardized method or criterion currently exists for specifying this imperative parameter. Manufacturers predominantly present the non-repetitive peak forward surge current, IF,SM, in datasheets. When IF,RM values are provided by manufacturers, details regarding the criterion or method used to establish its value are not specified. As a result, variations in datasheet specifications among vendors make it difficult to meaningfully compare device robustness or to design circuits with reliable surge performance. Therefore, datasheet IF,RM values cannot be assumed to represent thermally safe repetitive operation,
as they are not derived using a disclosed or standardized physical criterion. At present, the only standardized procedures for surge-current rating are defined by JEDEC for silicon rectifier diodes [3], and no equivalent standardized method exists for specifying repetitive surge current capability in SiC Schottky diodes.
To address this gap, a consistent criterion for determining IF,RM is required. Therefore, in this study, we perform a comparative analysis based on a recently proposed method and criterion for IF,RM in SiC Schottky diodes that ensures that the maximum junction temperature rating of 175∘C is not exceeded [4]. In this way, the surge current capability is directly referenced to a fundamental thermal reliability limit. This was achieved using a comprehensive dataset comprising both TO-220 and TO-247 devices with blocking voltages of 650 V,1200 V, and 1700 V , and encompassing two structural types: merged PN Schottky (MPS) diodes and homogeneous-current Schottky barrier diodes (SBDs). By systematically evaluating repetitive surge currents in commercially available SiC Schottky diodes, this work demonstrates both the applicability and the necessity of the proposed method and criterion for determining IF,RM. The analysis further highlights variations in vendor datasheet practices and establishes a standardized framework for assessing repetitive surge current capability in SiC Schottky diodes. As a result, this study provides researchers and circuit designers with a practical and reliable tool for benchmarking device performance and ensuring robust, thermally safe power-electronic designs.

Surge Current Ratings and Reliability Considerations in SiC Schottky Diodes

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In 4H-SiC Schottky diodes, the surge current capability constitutes a key parameter in assessing the robustness and long-term reliability in practical power electronic applications, which is specified in terms of both IF,SM and IF,RM. The IF,SM parameter represents the maximum current a diode can withstand during a single short-duration high-current pulse, arising from fault conditions or inrush currents, such as charging of bulk capacitors and inductive load energization. By contrast, IF,RM specifies the maximum current permissible during repetitive, short-duration high-current pulses, which are typically encountered in electronic circuits during normal operation, such as switching transients or recurring fault conditions.
The IF,SM parameter is evaluated in the literature by progressively increasing the peak of a single surge-current pulse until device failure or a defined degradation criterion indicative of surge limit is reached, which is then derated to assure consistent functionality under specified conditions [5-9]. The evaluation is typically performed using a half-sine wave pulse of either 10 ms duration at 50 Hz or 8.3 ms at 60 Hz . The IF,RM parameter is evaluated under identical half-sine wave conditions; however, to ensure reliable operation and prevent cumulative thermal overstress, a peak surge current level below the destructive threshold defined by IF,SM is selected and applied repetitively with sufficient cooling intervals [10-13]. An important consideration for repetitive surge current events is their reliance on the time-dependent transient thermal impedance, which determines the cumulative junction-temperature rise when cooling between pulses is insufficient, ultimately becoming the dominant reliability constraint. However, under standardized test conditions with sufficient cooling intervals, the cumulative thermal effect is effectively mitigated.
Together, the IF,SM and IF,RM ratings provide critical benchmarks for the safe design and reliable operation of SiC Schottky diodes, as they define the operating limits and tolerance for both singleevent and repetitive surge current conditions. While IF,SM sets the destructive single-event limit, IF,RM is practically important and serves as a critical parameter for circuit designers in preventing premature failure and ensuring long-term operation in practical applications. This practical importance is highlighted by experimental studies demonstrating that repetitive surge current stress can induce forward-voltage drift and progressive degradation in SiC Schottky-based devices, including JBS and MPS diodes, even when the applied current remains below the single-surge destructive limit. Reported mechanisms include stacking-fault-mediated bipolar degradation associated with minoritycarrier injection in JBS/MPS structures [11], as well as aluminum metallization melting and electromigration driven by repeated high-current thermal stress [11, 13]. Therefore, these parameters are indispensable for ensuring device robustness in practical applications such as power converters,
motor drives, and automotive systems, where surge currents frequently occur during switching, inrush, or fault conditions. Accordingly, it is essential that both IF,SM and IF,RM are clearly defined and supported by an appropriate method and criterion for SiC Schottky diodes, as each plays a critical role in device reliability.

Criterion for Repetitive Peak Forward Surge Current

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Given the critical importance of the IF,RM parameter, the analysis within this paper is based on a recently proposed method and criterion for repetitive peak surge current [4]. The foundation of the proposed criterion is defined by the condition that the surge current pulse does not exceed the isothermal I−V characteristic measured at the device's maximum rated junction temperature, which is 175∘C for commercially available devices [14-17]. This ensures that the junction temperature ( Tj ) of the packaged device remains within its specified thermal limit under repetitive surge current conditions. Figure 1 illustrates the method used in [4] by mapping the surge current measurements (loops) to the isothermal I−V characteristics measured at 175∘C.

[picture]

Fig. 1. Mapping of surge-current loops to isothermal I−V′s at 175∘C for vendor C (a) and vendor A (b).

Fig. 1. Mapping of surge-current loops to isothermal I − V ′ s at 175 ∘ C for vendor C (a) and vendor A (b).

Experimental Scope and Device Dataset

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A comparative analysis was conducted across four commercial vendors (Vendors A-D) for both TO220 and TO-247 packaging with the maximum temperature rating of 175∘C. The devices include two structural types-merged PN Schottky (MPS) diodes, represented by Vendors A-C, and homogeneous-current Schottky barrier diodes (SBDs), represented by Vendor D-with TO-220 devices rated at 650 V and 1200 V and TO-247 devices rated at 650 V,1200 V, and 1700 V . This selection of vendors, package types, and voltage ratings establishes a representative dataset, allowing the proposed criterion to be systematically applied and the results benchmarked against the corresponding datasheet specifications.

Criterion-Based Analysis of Repetitive Surge Current Capability: TO-220 SiC Schottky Diodes

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Assessment of Datasheet-Based Surge Current Specifications

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Tables I and II summarize the surge-current data for the TO-220 SiC Schottky diodes from three commercial vendors (Vendors A-C), along with the corresponding comparative analysis. A key limitation in relying on commercial datasheets to assess the surge current capability of SiC Schottky diodes is that the IF,RM parameter is not always specified, as demonstrated by Vendor B in Table I. In such cases, it is common practice to approximate the repetitive surge current as 70% of the specified IF,SM value ( 0.7IF,SM in Table I). However, the derated IF,SM values show poor correlation with the stated IF,RM values, signifying that IF,SM is not an adequate and reliable indication of IF,RM when it is not provided in datasheets. For Vendor A, the 650 V devices exhibit an IF,RM/IF,SM ratio of
0.66 ; however, at 1200 V this ratio decreases significantly to 0.45 , indicating a pronounced reduction in repetitive surge current capability with increasing blocking voltage. The devices from Vendor C show a wider range of IF,RM/IF,SM ratios at 1200 V , ranging from 0.57 to 0.70 . Thus, at 650 V the only available determination is 0.66 (as Vendor B does not specify the IF,RM parameter), whereas at 1200 V the ratios vary considerably between 0.45 and 0.70 across vendors. Therefore, in the absence of a standardized method for extracting IF,RM, these variations illustrate the lack of consistency in the IF,SM derating criterion used to define the IF,RM parameter. Consequently, for vendors that do not report IF,RM values (e.g., Vendor B), reliance on datasheet specifications alone is problematic due to the inconsistencies observed across manufacturers. At 1200 V , Vendor A specifies an IF,RM/IF,SM ratio of 0.45, whereas Vendor C reports ratios between 0.57 and 0.70 for devices with the same blocking voltage. This up to 55% variation in repetitive surge current capability across vendors demonstrates that datasheet IF,RM values are not based on a consistent criterion. Therefore, the absence of standardization and the observed variability further demonstrate that repetitive surge current capability cannot be reliably estimated by simply applying a universal de-rating of IF,SM.

Table I. Comparison of surge-current data for TO-220 SiC Schottky diodes from three different vendors.

Criterion-Based Determination of Repetitive Surge Current Capability

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

To illustrate the importance of the recently proposed criterion for specifying repetitive surge current, the peak surge current ( Ipeak  in Table II) was measured at Tj=175∘C and Tc=25∘C following the same surge current measurement method in [4]. To establish a tolerance margin, Ipeak  is derated to 90% so that the repetitive surge current is defined as IF,RM(175∘C)=0.9Ipeak . In Table II, these values for the repetitive surge current are benchmarked against the available IF,RM specifications in datasheets. The comparison shows that using 0.9Ipeak  yields IF,RM values in good agreement with most IF,RM specifications reported in manufacturer datasheets. Nonetheless, in the case of Vendor A, the datasheet IF,RM value for one 1200 V diode is slightly overrated, whereas the datasheet values for all three 650 V diodes are consistently underrated. This trend is further illustrated in Fig. 1, which maps surge-current loops to isothermal I−V characteristics at 175∘C for representative 1200 V/5 A devices from Vendor C (Fig. 1a) and Vendor A (Fig. 1b). For Vendor C (Fig. 1a), the datasheet IF,RM of 26A lies below the measured peak surge current (Ipeak =29 A), while the criterion-based estimate (0.9Ipeak =26 A) aligns exactly with the datasheet value, indicating an accurate specification. In contrast, for Vendor A (Fig. 1b), the datasheet IF,RM of 31.8A exceeds both the measured peak surge current ( Ipeak =28 A ) and the criterion-based estimate ( 0.9Ipeak =25 A ), indicating an overrated specification. For the Vendor A 1200 V/5 A TO-220 diode, the datasheet IF,RM of 31.8 A exceeds the
criterion-based value of 25 A derived from measurements at Tj=175∘C. This indicates that the datasheet permits repetitive surge operation beyond the thermally defined limit of the device. In this case, the commonly assumed approximation IF,RM≈0.7IF,SM would yield 49A, nearly double the thermally constrained value, illustrating that IF,SM-based derating can significantly overestimate safe repetitive operation.
The ratio IF,RM(175∘C)/IF,SM in Table II shows that the repetitive surge current typically lies between 60−90% of the non-repetitive surge current, reflecting how much of the single-event surge capability can be safely sustained under repetitive conditions at the maximum junction temperature of 175∘C. This approach also captures vendor- and voltage-dependent variations, with certain high-voltage devices exhibiting reduced margins ( 0.36−0.41 ). This variability among vendors and devices illustrates that device-specific behavior must be accounted for, and that a simple universal derating of IF,SM is insufficient for reliably determining IF,RM. Therefore, even in the presence of variation among vendors and devices, the proposed method provides a consistent framework for determining IF,RM with a safety margin that ensures adherence to the device's maximum thermal limits.

Table II. Repetitive peak surge current, IF,RM(175∘C), based on a recently proposed criterion for TO-220 SiC Schottky diodes for three different vendors.

Criterion-Based Analysis of Repetitive Surge Current Capability: TO-247 SiC Schottky Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Assessment of Datasheet-Based Surge Current Specifications

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

The comparative analysis was extended to TO-247 SiC Schottky diodes, which are widely used in high-power, high-temperature applications owing to their superior thermal and current-carrying capabilities, thereby providing an important benchmark for evaluating surge current behavior across different vendors. Tables III and IV summarize the surge-current data for the TO-247 SiC Schottky diodes for three commercial vendors (Vendors A, B, and D), along with the corresponding comparative analysis.
The comparison in Table III highlights distinct vendor-dependent practices for specifying IF,RM, demonstrating a lack of consistency in how manufacturers define the repetitive surge current capability, as reflected by the wide variation in IF,RM/IF,SM ratios (0.42-0.90) across vendors and voltage classes. Moreover, the commonly assumed derating of IF,SM by 0.7 does not align with datasheet values for IF,RM, leading in some cases to overestimation (e.g., Vendor A, 1700V) and in others to underestimation (e.g., Vendor D, 1200 V ). For 1200 V/20 A TO- 247 devices, Vendor B specifies an IF,RM/IF,SM ratio of 0.42 , while Vendor D reports a ratio of 0.90 , highlighting more than
a twofold discrepancy in repetitive surge current capability for devices with identical ratings. These discrepancies, as observed in the TO-220 analysis, demonstrate that a simple universal derating of IF,SM is insufficient for reliably determining IF,RM, since in some cases this approach can be misleading and may result in operation beyond the device's thermal limits.

Table III. Comparison of surge-current data for TO-247 SiC Schottky diodes from three different vendors.

Criterion-Based Determination of Repetitive Surge Current Capability

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

The comparison illustrated in Table IV reinforces the vendor-dependent variability in repetitive surge current specification. As in the previous case, the peak surge current ( Ipeak  ) was measured at Tj=175∘C and Tc=25∘C, and then derated to 0.9Ipeak  to specify the repetitive peak surge current, IF,RM(175∘C). These values were then benchmarked against the datasheet specifications where available. Overall, Table IV confirms the same trends identified for the TO-220 packaged devices: vendor- and voltage-dependent variations exist, and datasheet specifications may either underrate or overrate actual surge current device performance. For example, Vendor A specifies an IF,RM value for its 1700 V/25 A diode that is greater than the measured Ipeak , even though the latter was obtained at the device's maximum junction temperature. For Vendor A's 1700 V/25 A TO- 247 diode, the datasheet IF,RM of 117A exceeds the criterion-based value of 104A obtained at Tj=175∘C. Similarly, for Vendor D's 650 V/20 A diode, the datasheet IF,RM(128 A) exceeds the measured peak surge current at 175∘C (99A), again indicating disagreement with a thermally constrained definition of IF,RM. This implies that the device could repeatedly sustain surges beyond its rated thermal limit. A similar issue is observed for Vendor D's 650 V/20 A diode, where the datasheet IF,RM likewise exceeds the measured Ipeak , again suggesting repetitive operation beyond safe thermal limit. By contrast, applying the proposed method-first determining the maximum surge current that can be handled within the 175∘C junction temperature limit, and then derating this value by 10%-ensures that IF,RM remains below the destructive threshold and maximum device ratings. Furthermore, the observed variation in the IF,RM(175∘C)/IF,SM ratio highlights the device-specific thermal behavior arising from structural design, blocking voltage, and current ratings. In this case, the results confirm the need for a standardized method and criterion to ensure that repetitive surge current capability is defined within the thermal limits of the device.

Table IV. Repetitive peak surge current, IF,RM(175∘C), based on a recently proposed criterion for TO-247 SiC Schottky diodes for three different vendors.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

The repetitive peak forward surge current ( IF,RM ) is a critical reliability parameter for SiC Schottky diodes, as it defines safe operation under repeated surge events and ensures robust circuit designs. Despite its importance, no standardized method or criterion currently exists, and manufacturers typically report only the non-repetitive peak forward surge current ( IF,SM ), which is based on destructive single-pulse measurements and provides limited guidance for repetitive operation. In this study, we perform a comparative analysis based on a recently proposed criterion for determining IF,RM, where the measured peak surge current at Tj=175∘C and Tc=25∘C ( Ipeak  ) is derated by 10% ( 0.9Ipeak  ) to maintain operation within the device's maximum thermal limit of 175∘C. Analysis across multiple vendors and voltage classes shows that this approach yields IF,RM values that are largely consistent with datasheet specifications, while avoiding the inconsistencies associated with unstandardized reporting or reliance on a universal derating of IF,SM. The results demonstrate that the proposed criterion provides a reliable and broadly applicable specification for IF,RM, enabling meaningful benchmarking across vendors, ensuring compliance with maximum thermal ratings, and supporting robust, thermally safe circuit designs. These findings highlight the lack of standardization in current datasheet practices and establish the importance of adopting a unified measurement method for repetitive surge current capability in commercial SiC Schottky diodes.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, Wiley-IEEE Press, Singapore, 2014.

B.J. Baliga, Wide Bandgap Semiconductor Power Devices: Materials, Physics, Design and Applications, Woodhead Publishing, Cambridge, 2019.

JEDEC Standard Silicon Rectifier Diodes JESD282B.02, JEDEC Solid State Tech. Assoc, Arlington, VA, USA, 2023, pp. 1-162.

J. Damcevska, S. Dimitrijev, D. Haasmann, and P. Tanner, IEEE Access. 13 (2025) 153987 153992.

J. Wu, N. Ren, K. Sheng, Design and experimental study of 1.2 kV 4H-SiC merged PiN Schottky diode, Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), Shanghai, China, (2019) 203-206.

V. Banu, M. Berthou, J. Montserrat, X. Jordá, P. Godignon, Surge current robustness improvement of SiC junction barrier Schottky diodes by layout design, Romanian J. Inf. Sci. Technol. 20 (2017) 369-384.

V. Banu, X. Jordá, J. Montserrat, P. Godignon, J. Millan, P. Brosselard, Accelerated test for reliability analysis of SiC diodes, Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), Barcelona, Spain, (2009) 267-270.

R. Radhakrishnan, N. Cueva, T. Witt, R.L. Woodin, Analysis of forward surge performance of SiC Schottky diodes, Mater. Sci. Forum. 924 (2018) 621-624.

B. Zhang, et al., The surge current failure and thermal analysis of Schottky barrier diode, IEEE Trans. Electron Devices. 71 (2024) 1-6.

J. Wu, N. Ren, H. Wang, K. Sheng, 4H-SiC merged PiN Schottky diode with improved surge current capability, IEEE J. Emerg. Sel. Top. Power Electron. 7 (2019) 1496-1504.

X. Huang, G. Wang, M.C. Lee, A.Q. Huang, Reliability of SBD/JBS diodes under repetitive surge current stress, Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Raleigh, NC, USA, (2012) 2245-2248.

J. León, et al., Temperature effects on the ruggedness of SiC Schottky diodes under surge current, Microelectron. Reliab. 54 (2014) 2207-2212.

S. Palanisamy, J. Kowalsky, J. Lutz, T. Basler, R. Rupp, J. Moazzami-Fallah, Repetitive surge current test of SiC MPS diode with load in bipolar regime, Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), Chicago, IL, USA, (2018) 367-370.

D. Bisewski, M. Myśliwiec, K. Górecki, R. Kisiel, J. Zarębski, Examinations of selected thermal properties of packages of SiC Schottky diodes, Metrol. Meas. Syst. 23 (2016) 451-459.

Wolfspeed Inc., C3D Series Silicon Carbide Schottky Diodes, Datasheet, Wolfspeed Inc., Durham, NC, USA, 2022.

Infineon Technologies AG, CoolSiC Schottky Diode 1200 V Series, Datasheet, Infineon Technologies AG, Neubiberg, Germany, 2023.

GeneSiC Semiconductor Inc., GD20MPS12H 1200 V 20 A SiC Schottky MP Diode, Datasheet, GeneSiC Semiconductor Inc., Dulles, VA, USA, 2022.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 63-68

doi: 10.4028/p-a2X5vs

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-19

Accepted:
2026-03-16

Online:
2026-05-21

Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

Pei-Chun Liao 1,a, Kung-Yen Lee 1,2, b*, Ruei-Ci Wu 3,c, Yan-Yu Wen 1, d, Po-Yu Cheng 2,e and Wei-Xiang Wang 2,f

1 Graduate School of Advanced Technology, National Taiwan University, Taiwan

2 Department of Engineering Science and Ocean Engineering, National Taiwan University, Taiwan

3 SiCEV Electronics Co., Ltd., Taiwan

a  d13k44005@ntu.edu.tw, b*kylee@ntu.edu.tw, cricky_wu@sicev.com.tw, df10525134@ntu.edu.tw, er13525108@ntu.edu.tw, fr13525037@ntu.edu.tw

Keywords: silicon carbide (SiC), split-gate MOSFET (SG-MOSFET), short-circuit reliability, draininduced barrier lowering (DIBL), gate oxide field crowding.

Abstract

This work investigates the short-circuit (SC) reliability of Split-Gate (SG) versus planar 4H-SiC MOSFETs through TCAD simulations. While SG-MOSFETs effectively reduce gate-drain capacitance and improve switching performance, SG-MOSFETs exhibit enhanced short-circuit failure effects. Structural optimization-such as thicker drift regions, extended gate lengths, and narrowed JFET widths-can improve SC withstand time (SCWT). However, SG-MOSFETs suffer from intensified electric field crowding and enhanced drain-induced barrier lowering (DIBL), leading to greater post-SC leakage and thermal instability. Results suggest SG-MOSFETs require careful field and oxide engineering to ensure reliability under fault conditions.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

Silicon carbide (SiC) MOSFETs are widely adopted for high-power and high-frequency applications due to their superior thermal conductivity, breakdown voltage, and switching efficiency [1,2]. However, their robustness under short-circuit (SC) conditions remains a critical reliability concern. [3-6] has gained particular attention. During SC events, the device must withstand large current surges under high drain bias without undergoing catastrophic failure. The short-circuit withstand time (SCWT) is a standard metric for assessing device survival under fault scenarios. Planar SiC VDMOSFETs are mature and reliable, but recent efforts have focused on Split-Gate (SG) MOSFETs [7], which reduce parasitic gate-drain capacitance ( Cgd ) and gate charge ( Qgd ) , thus lowering switching loss.

Although prior studies report similar SCWT for SG and planar structures [8, 9], the impact of SGinduced electric field redistribution, especially at oxide corners-has not been fully characterized. Additionally, physical factors such as gate length and JFET width may affect both conduction loss and SC robustness. This study uses TCAD to compare SG and planar 4H-SiC MOSFETs under SC conditions, focusing on how design parameters impact SCWT, peak current, and failure mechanisms. The analysis reveals SG-specific vulnerabilities, particularly in oxide stress and DIBL-induced leakage, highlighting the need for structural and electrostatic optimization.

Methodology

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

To assess the short-circuit behavior of SG and planar 4H-SiC MOSFETs, two-dimensional TCAD simulations were conducted using Synopsys Sentaurus. A half-bridge circuit was modeled, in which one MOSFET was pulsed to create SC conditions while the other remained off. Gate voltage ranged from 0 to 15 V , and drain voltage was set at 600 V or 1000 V .

Key physical models included drift-diffusion transport, Shockley-Read-Hall and Auger recombination, and avalanche generation to accurately simulate high-field, high-temperature effects. It should be noted that the TCAD 2D electrothermal simulations employed in this study provide a
qualitative indication of the temperature increase within the device. While they effectively capture relative trends and mechanisms, they may not fully represent the complex 3D thermal dissipation paths present in a packaged device.

Both SG and planar device structures were constructed with variable parameters: drift layer thickness, gate length, and JFET width. The drift region was uniformly doped at 5×1015 cm−3. Shortcircuit performance was evaluated by extracting transient peak drain current, maximum lattice temperature, and SC withstand time (SCWT). Gate charge curves were analyzed to calculate Qgd, and the high-frequency figure of merit (HF-FOM) [10] was used to assess switching efficiency. Electric field and conduction band profiles under SC stress were also examined to assess field crowding and DIBL-induced reliability concerns.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

The simulated SC responses of planar and SG-MOSFETs reveal how structural differences influence device robustness. Emphasis was placed on the interaction between parasitic capacitances, conduction paths, and electrothermal effects that define SCWT. Fig. 1 presents the schematic crosssections of both device types. The planar VDMOSFET employs a continuous polysilicon gate overlapping the JFET region, which inherently results in higher Cgd and Qgd. In contrast, the SGMOSFET introduces a split-gate structure that reduces the gate-to-drain overlap, thereby lowering Cgd and improving switching performance.

[picture]

Fig. 1. Cross-sections of (a) planar VDMOSFET and (b) SG-MOSFET.

Fig. 1. Cross-sections of (a) planar VDMOSFET and (b) SG-MOSFET.

As shown in Fig. 2, increasing the drift region thickness significantly affects SC behavior. A thicker drift layer introduces greater series resistance, which limits the peak drain current during SC and delays thermal buildup. This extends SCWT by reducing the rate of self-heating. For instance, devices with a 15μ m drift layer show lower current peaks and slower temperature rise compared to those with 10μ m, resulting in several microseconds of additional SCWT. However, this improvement comes with increased Ron,sp , highlighting a trade-off between fault tolerance and conduction loss. Designers must therefore balance SC reliability against efficiency requirements when adjusting drift thickness.

[picture]

Fig. 2. Simulated SC drain current and maximum lattice temperature versus time for different epitaxial thicknesses.

Fig. 2. Simulated SC drain current and maximum lattice temperature versus time for different epitaxial thicknesses.

Fig. 3 explores how gate length impacts Ron,sp and HF-FOM in SG-MOSFETs. Shorter gates reduce Cgd and Qgd, improving switching speed and lowering HF-FOM. However, they also weaken carrier accumulation in the JFET region, increasing Ron,sp and degrading conduction efficiency.

[picture]

Fig. 3. Simulated Ron,sp and HF-FOM relationship for different extended gate lengths.

Fig. 3. Simulated R o n , s p and HF-FOM relationship for different extended gate lengths.

Fig. 4 shows that narrowing the JFET width effectively reduces peak drain current during SC events, resulting in extended SCWT. For example, reducing the JFET width from 2.2μ m to 1.4μ m nearly doubles the SCWT, as the narrower current path limits surge current and delays thermal failure. However, excessive narrowing increases Ron,sp and can degrade overall conduction performance. Moreover, tighter current confinement enhances electric field stress near the oxide interface, raising concerns about long-term reliability. These results indicate that while reducing JFET width is a viable strategy for improving SC tolerance, it must be balanced against static and dynamic performance penalties.

As shown in Fig. 5, reducing JFET width below 1.4μ m causes a sharp rise in Ron,sp due to severe conduction constriction. While this improves SCWT, the gain is offset by degraded conduction efficiency. These findings emphasize that JFET scaling must avoid extremes, moderate narrowing is beneficial, but excessive reduction compromises both electrical and thermal stability.

[picture]

Fig. 4. Simulated SC drain current versus time with different JFET widths of SG-MOSFET. ( Vds= 1000 V ).

Fig. 4. Simulated SC drain current versus time with different JFET widths of SG-MOSFET. ( V d s = 1000 V ).

[picture]

Fig. 5. Simulated relationship between JFET width, Ron,sp, and reverse oxide electric field.

Fig. 5. Simulated relationship between JFET width, R o n , s p , and reverse oxide electric field.

Fig. 6 compares the SC current waveforms of SG and planar MOSFETs under identical bias conditions. Both exhibit similar SCWT, confirming that the split-gate structure does not compromise baseline SC survivability. However, post-SC behavior reveals critical differences. The SG-MOSFET demonstrates a more abrupt thermal runaway once failure initiates. This is attributed to its altered field distribution and lower Qgd, which while beneficial for switching, result in faster energy accumulation and less thermal buffering during SC events. These results suggest that while SCWT remains comparable, the failure of SG-MOSFETs are more abrupt and thermally aggressive than the planar MOSFET.

[picture]

Fig. 6. Simulated SC drain current versus time comparison between planar VDMOSFET and SGMOSFET. (a) Vds=600 V (b) Vds=1000 V.

Fig. 6. Simulated SC drain current versus time comparison between planar VDMOSFET and SGMOSFET. (a) V d s = 600 V (b) V d s = 1000 V .

Fig. 7 presents the electric field distribution under SC conditions at 1000 V . The planar MOSFET shows a relatively uniform field profile, with peak intensity near the drain junction. In contrast, the SG-MOSFET exhibits strong field crowding at oxide corners adjacent to the split gate. This localized enhancement raises the maximum oxide field ( Eox,max ), increasing the likelihood of oxide degradation and triggering early failure mechanisms. The elevated field also intensifies susceptibility to DIBL, further contributing to leakage current growth and thermal instability. These results explain the more rapid failure escalation observed in SG-MOSFETs post-SCWT.

[picture]

Fig. 7. Simulated electric field distributions under SC conditions ( Vds=1000 V ).

Fig. 7. Simulated electric field distributions under SC conditions ( V d s = 1000 V ).

Fig. 8 shows conduction band profiles under SC stress. In the planar MOSFET, the conduction band maintains a stable barrier between source and drain, which helps limit leakage current even at high drain bias. In contrast, the SG-MOSFET exhibits a more pronounced band lowering near the JFET region-indicative of stronger DIBL effects. This band lowering accelerates leakage current growth beyond the SCWT threshold, compounding thermal stress and promoting rapid thermal runaway. While the split-gate design improves switching performance, it inherently compromises electrostatic control, making SG-MOSFETs more vulnerable under extreme SC conditions.

[picture]

Fig. 8. Simulated conduction band energy profiles ( Vds=1000 V ).

Fig. 8. Simulated conduction band energy profiles ( V d s = 1000 V ).

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

This study presents a comparative TCAD analysis of SG- and planar 4H−SiC MOSFETs under short-circuit stress. While both achieve similar SCWT, SG-MOSFETs are more prone to post-SC degradation due to intensified oxide field and DIBL. Structural tuning-such as increased drift thickness, optimized gate length, and moderately narrowed JFET width—can effectively reduce Qgd, limit peak SC current, and improve HF-FOM. However, these benefits must be balanced against increased electric field stress and conduction losses. Future design strategies should prioritize field control near oxide corners to enhance SG-MOSFET reliability in high-stress environments.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

P. Samanta and K. C. Mandal, "Hole injection and dielectric breakdown in 6H-SiC and 4HSiC metal-oxide-semiconductor structures during substrate electron injection via FowlerNordheim tunneling," Solid-State Electronics, vol. 114, pp. 60-68, 2015.

S. Singh, T. Chaudhary, and G. Khanna, "Recent advancements in wide band semiconductors (SiC and GaN) technology for future devices," Silicon, vol. 14, no. 11, pp. 5793-5800, 2022.

T.-T. Nguyen, A. Ahmed, T. Thang, and J.-H. Park, "Gate oxide reliability issues of SiC MOSFETs under short-circuit operation," IEEE Transactions on Power Electronics, vol. 30, no. 5, pp. 2445-2455, 2014.

M. Okawa et al., "First demonstration of short-circuit capability for a 1.2 kV SiC SWITCHMOS," IEEE Journal of the Electron Devices Society, vol. 7, pp. 613-620, 2019.

G. Romano et al., "Short-circuit failure mechanism of SiC power MOSFETs," in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015: IEEE, pp. 345-348.

G. Romano et al., "A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 4, no. 3, pp. 978-987, 2016.

A. Agarwal, K. Han, and B. J. Baliga, " 2.3 kV 4H-SiC accumulation-channel split-gate planar power MOSFETs with reduced gate charge," IEEE Journal of the Electron Devices Society, vol. 8, pp. 499-504, 2020.

H. Liu, J. Wei, Z. Wei, S. Liu, and L. Shi, "Experimental comparison of a new 1.2 kV 4H-SiC split-gate MOSFET with conventional SiC MOSFETs in terms of reliability robustness," Electronics, vol. 12, no. 11, p. 2551, 2023.

K. Shin, D. Kim, M. Kim, J. Park, and C. Han, "Enhanced Short-Circuit Robustness of 1.2 kV Split Gate Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors for HighFrequency Applications," Electronics, vol. 14, no. 1, p. 163, 2025.

B. J. Baliga, Advanced power MOSFET concepts. Springer Science & Business Media, 2010.z

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 69-74

doi: 10.4028/p-Ncz2vl

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-17

Accepted:
2026-02-26

Online:
2026-05-21

Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

Hojung Lee 1,a*, Justin Lynch 1,b, Stephen A. Mancini 1,c, Skylar deBoer 1,d, Miguel Hinojosa 2,e, Aivars Lelis 2,f and Woongje Sung 1, g

¹College of Nanotechnology Science and Engineering, University at Albany, Albany NY, 12203, USA

2 U.S. Army Research Laboratory (ARL), Adelphi, MD 20783 U.S.A.

a*hlee36@albany.edu, b  jmlynch@albany.edu, c  smancini@albany.edu, d  sdeboer@albany.edu, e  miguel.hinojosa4.civ@army.mil, f  aivars.j.lelis.civ@army.mil, 9  wsung@albany.edu

Abstract

This study investigates the influence of active cell geometry on the static performance of 10−kV 4H-Silicon Carbide (SiC) Junction Barrier Schottky (JBS) diodes. Two types of diodes were fabricated and characterized, one with a hexagonal cell and the other with a stripe cell. While forward conduction characteristics were comparable, the reverse leakage current of the hexagonal cell was more than two orders of magnitude lower than that of the stripe cell at 8 kV . 3D TCAD simulations revealed that this discrepancy stems from strong electric field concentrations both at the bottom corners of the P+junctions and at the center of the Schottky contact in the stripe structure. These localized fields reduce the Schottky barrier height and enhance electron injection. In contrast, the hexagonal cell exhibited a more uniform electric field distribution in both regions, effectively suppressing leakage current. These findings underscore the critical role of active cell geometry in achieving robust reverse blocking performance in ultra-high-voltage SiC JBS diodes by clarifying the physical mechanisms contributing to leakage current behavior.

Keywords: 4 H -silicon carbide (SiC), 10−kV 4H-SiC junction barrier schottky (JBS) diodes, 3D TCAD simulations, cell geometry, reverse leakage, electric field.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

Silicon carbide ( SiC ) has emerged as a leading material platform for next-generation high-voltage power semiconductor devices, owing to its outstanding material properties such as wide bandgap, high critical electric field, high thermal conductivity, and excellent radiation hardness [1]. These attributes allow SiC devices to operate with significantly lower conduction and switching losses compared to their silicon counterparts, making them highly suitable for demanding applications that require compactness, efficiency, and reliability [2]. In particular, SiC is widely adopted in power conversion systems for electric grids, renewable energy infrastructure, and defense systems where voltage ratings often exceed the limits of conventional silicon-based technology [3]. For applications operating at voltages beyond 10 kV , it becomes especially important to minimize reverse leakage current and maintain robust blocking capability to ensure reliable and long-term operation.

Key design parameters that influence the reverse blocking performance of SiC devices include epitaxial layer doping and thickness, edge termination structures such as JTE or floating field rings, and the geometry of the active cell layout [4-7]. Among these, the active cell geometry is a particularly critical factor, as it affects both forward and reverse behavior by shaping the electric field distribution and carrier injection dynamics under bias. Therefore, a well-optimized cell structure is essential for achieving low leakage current without degrading forward conduction characteristics.

In this study, we investigate the effect of active cell layout on the static performance of 10−kV4H SiC junction barrier Schottky (JBS) diodes. Devices were designed and fabricated with two different active cell structures, one with a hexagonal pattern, which exhibits an enclosed geometry, and the other with a stripe pattern. Their forward and reverse characteristics were experimentally evaluated, and 3D TCAD simulations (Synopsys Sentaurus) were performed to analyze the electric field distribution in each structure.

The results demonstrate that the hexagonal layout effectively reduces field concentration and suppresses reverse leakage current while maintaining comparable forward conduction behavior.

Device Design and Simulation

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

To investigate the impact of active cell geometry on the static performance of ultra-high-voltage SiC JBS (Junction Barrier Schottky) diodes, two types of devices were designed and fabricated, one employing a hexagonal cell layout and the other a stripe cell layout. Both structures were configured with identical design parameters for a fair comparison, specifically setting the P+region width ( Lpp ) to 2.0μ m and the Schottky contact width ( Lsch  ) to 3.0μ m. Fig. 1 illustrates the top and cross-sectional views of each design, extracted directly from the GDS layout.

[picture]

Fig. 1. Schematic top and cross-sectional views of 10−kVSiCJBSdiodeswithtwodifferentactive cell geometries, (a) hexagonal and (b) stripe layouts. Both designs share identical cell dimensions, with the P+region width (Lpp) set to 2.0μ m and the Schottky region width (Lsch) set to 3.0μ m.

Fig. 1. Schematic top and cross-sectional views of 10 − k V S i C J B S d i o d e s w i t h t w o d i f f e r e n t a c t i v e cell geometries, (a) hexagonal and (b) stripe layouts. Both designs share identical cell dimensions, with the P + region width ( L p p ) set to 2.0 μ m and the Schottky region width ( L s c h ) set to 3.0 μ m .

The devices were fabricated on a 6-inch, n-type 4H-SiC wafer with an epitaxial drift layer engineered for 10 kV blocking capability. A Surface region was first formed through nitrogen ion implantation at room temperature. This step was performed prior to the P+region formation to locally increase the carrier concentration beneath the Schottky contact for improved current spreading, and to suppress excessive lateral straggle of the subsequent P+implantation, thereby enabling precise definition of the Schottky contact width ( Lsch  ). The P+regions were then formed via high-temperature aluminum ion implantation, followed by high-temperature activation annealing. A Ni metal layer was deposited on both the front and back sides of the wafer, and Rapid Thermal Process (RTP) was carried out to simultaneously form a P+ohmic contact on the front side and an N+ohmic contact on the back side. Subsequently, Ti was deposited on the front side as part of the top metal stack, forming a Schottky contact with the n-type drift layer in regions not implanted with aluminum ions. Finally, metal layers were deposited on both the front and back sides to complete the device fabrication.

To analyze the underlying physical mechanisms responsible for differences in device behavior, 3D TCAD simulations were performed using Synopsys Sentaurus. Both the hexagonal and stripe designs were modeled with full 3D structures incorporating the same design dimensions used in the fabricated devices. Fig. 2 shows the simulated geometries of the hexagonal and stripe designs, while Fig. 3 presents the doping profile used for the P+junction regions. The implantation model used in the simulation was pre-calibrated using actual SIMS (Secondary Ion Mass Spectrometry) data obtained from fabricated devices, in order to closely replicate the realistic junction depth and dopant concentration profile of the P+implantation. The simulations were configured to evaluate forward and reverse characteristics, with particular focus on electric field distribution and current conduction paths under reverse bias conditions.

[picture]

Fig. 2. Simulated geometries of 10−kVSiCJBSdiodeswith(a)hexagonaland(b)stripeactivecell designs. Each set shows the 3D isometric view (left), top view (top right), and cross-sectional view (bottom right) of the modeled structure used in the TCAD simulation.

Fig. 2. Simulated geometries of 10 − k V S i C J B S d i o d e s w i t h ( a ) h e x a g o n a l a n d ( b ) s t r i p e a c t i v e c e l l designs. Each set shows the 3D isometric view (left), top view (top right), and cross-sectional view (bottom right) of the modeled structure used in the TCAD simulation.

[picture]

Fig. 3. Simulated Surface N and P+ion doping profile used in the TCAD simulation.

Fig. 3. Simulated Surface N and P + ion doping profile used in the TCAD simulation.

Results and Discussion

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The electrical characteristics of the fabricated 10−kV SiC JBS diodes with hexagonal and stripe active cell designs were experimentally evaluated under both forward and reverse bias conditions. Fig. 4 shows the forward I-V characteristics, which represent the average response of approximately 20 devices for each structure. At a forward current of 0.5 A , the forward voltage drop was measured to be 3.70 V for the hexagonal cell and 3.48 V for the stripe cell, corresponding to a difference of 0.22 V . While this indicates a slight increase in conduction loss for the hexagonal design, both structures still maintain comparable forward behavior within typical operating margins for 10 kV class SiC diodes. This result confirms that the impact of active cell geometry on forward conduction behavior was effectively minimized within the tested current range.

In contrast, a significant difference was observed in reverse leakage characteristics, as illustrated in Fig. 5. Due to limited reverse yield, representative single-device measurements are shown. Under a reverse bias of 8 kV , the leakage current was measured to be 4.0×10−8 A for the hexagonal cell and 1.0×10−5 A for the stripe cell. This demonstrates that the hexagonal design achieves more than two orders of magnitude reduction in leakage current compared to the stripe layout, highlighting the importance of cell geometry in optimizing reverse blocking performance for ultra-high-voltage applications.

[picture]

Fig. 4. Statistical comparison of forward voltage drop for hexagonal and stripe active cells. Box plots reflect approximately 20 wafer-level measurements per structure, with median voltage drop values of 3.70 V for the hexagonal design and 3.48 V for the stripe design.

Fig. 4. Statistical comparison of forward voltage drop for hexagonal and stripe active cells. Box plots reflect approximately 20 wafer-level measurements per structure, with median voltage drop values of 3.70 V for the hexagonal design and 3.48 V for the stripe design.

[picture]

Fig. 5. Representative reverse I-V characteristics of 10−kV SiC JBS diodes based on single-device measurements. At a reverse bias of 8 kV , the leakage current was 4.0×10−8 A for the hexagonal design and 1.0×10−5 A for the stripe design, showing a difference of more than two orders of magnitude.

Fig. 5. Representative reverse I-V characteristics of 10 − k V SiC JBS diodes based on single-device measurements. At a reverse bias of 8 kV , the leakage current was 4.0 × 10 − 8 A for the hexagonal design and 1.0 × 10 − 5 A for the stripe design, showing a difference of more than two orders of magnitude.

To investigate the physical mechanisms behind this discrepancy, 3D TCAD simulations were carried out for both designs. Fig. 6 shows the electric field distributions under reverse bias conditions. The left-hand side presents isometric views of the electric field distribution, while the top and bottom images on the right provide surface plots of the electric field at critical locations, the bottom of the P+ junction ( ABCD plane) and the surface center of the Schottky region ( A′B′C′D′ plane), respectively. The simulation results clearly reveal that the electric field is more uniformly distributed in the hexagonal design, while strong field crowding is observed at the P+junction corners and Schottky surface in the stripe structure.

[picture]

Fig. 6. Simulated electric field distributions under reverse bias conditions for 10−kVSiC JBS diodes (a) Hexagonal active cell design and (b) Stripe active cell design. Each subfigure shows a 3D isometric view (left), an electric field surface plot at the bottom of the P+junction (ABCD plane, top right), and a surface field plot near the surface region ( A′B′C′D′ plane, bottom right).

Fig. 6. Simulated electric field distributions under reverse bias conditions for 10 − k V S i C JBS diodes (a) Hexagonal active cell design and (b) Stripe active cell design. Each subfigure shows a 3D isometric view (left), an electric field surface plot at the bottom of the P + junction (ABCD plane, top right), and a surface field plot near the surface region ( A ′ B ′ C ′ D ′ plane, bottom right).

Quantitative analysis of the electric field profiles is provided in Fig. 7, which compares the 1D vertical electric field distribution along the drift depth at representative high electric field locations. The peak electric field at the P+junction bottom corner was 2.02MV/cm for the hexagonal cell and 2.25MV/cm for the stripe cell. Similarly, at the surface center of the Schottky region, the local electric field was 1.13MV/cm for the hexagonal design and 1.43MV/cm for the stripe. These results indicate that the stripe geometry induces stronger electric field peaks at both the P+junction corner and the Schottky surface center. This increased field concentration may lead to enhanced electron tunneling or field-assisted thermionic emission, effectively narrowing the barrier width.

[picture]

Fig. 7. Simulated 1D vertical electric field distributions along the drift depth for the hexagonal and stripe JBS diode structures under reverse bias. (a) Electric field at the P+junction bottom corner and (b) Electric field at the surface center of the Schottky region. The hexagonal design exhibits lower peak electric field values at both locations compared to the stripe design.

Fig. 7. Simulated 1D vertical electric field distributions along the drift depth for the hexagonal and stripe JBS diode structures under reverse bias. (a) Electric field at the P + junction bottom corner and (b) Electric field at the surface center of the Schottky region. The hexagonal design exhibits lower peak electric field values at both locations compared to the stripe design.

These field-enhanced mechanisms are likely to facilitate increased electron injection from the Schottky contact into the drift layer through tunneling or field-assisted thermionic emission, which aligns with the elevated leakage current observed in the stripe device. In contrast, the hexagonal cell structure results in a more uniform electric field distribution and inherently provides better shielding of the Schottky surface by the surrounding P+regions due to its enclosed layout [8]. This shielding effect reduces the electric field intensity at the Schottky interface, thereby suppressing Schottky barrier lowering and limiting unwanted carrier injection. As a result, the hexagonal design achieves significantly lower reverse leakage current with minimal impact on forward conduction performance. A summary of the key simulation and measurement results is presented in Table 1, clearly illustrating the relationship between active cell geometry, electric field behavior, and reverse leakage characteristics.

Table 1. Summary of measured electrical characteristics and simulated peak electric fields for hexagonal and stripe JBS diode designs.

Active Cell

Forward Voltage

Drop [V,

measured]

Reverse Leakage

Current [A,

measured]

Peak Electric

Field at mathematical formula

junction bottom

corner [MV/cm]

Peak Electric

Field at Schottky

surface [MV/cm]

Hexagonal | 3.70 | superscript number | 2.02 | 1.13
Stripe | 3.48 | superscript number | 2.25 | 1.43

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

This study investigated the effect of active cell geometry on the electrical performance of 10−kV4H−SiC junction barrier Schottky (JBS) diodes by comparing hexagonal and stripe cell layouts. Both structures were designed with identical process parameters and fabricated on 6 -inch 4H−SiC wafers. Experimental measurements revealed that while forward characteristics were similar between the two designs, the hexagonal cell exhibited significantly reduced reverse leakage current, over two orders of magnitude lower than that of the stripe cell at 8 kV reverse bias. To understand this improvement, 3D TCAD simulations were conducted, showing that the hexagonal design suppresses peak electric field intensity both at the P+junction corner and Schottky surface center. This reduction in electric field mitigates Schottky barrier lowering and minimizes electron injection under reverse bias. These results suggest that the hexagonal active cell layout is a promising design choice for enhancing the reverse blocking performance of ultra-high-voltage SiC JBS diodes without compromising forward conduction efficiency.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

T. Kimoto and J. A. Cooper, Fundamentals of silicon carbide technology: growth, characterization, devices and applications., John Wiley & Sons, 2014.

S. Y. Jang, J. Kim, H. Lee and K. S. Kim, "Improved on-state resistance with reliable reverse characteristics in 1.2 kV 4H-SiC MOSFET by selective nitrogen implantation assisted current spreading layer", Japanese Journal of Applied Physics, vol. 59, no. 4, May 2022.

R. J. Callanan, A. Agarwal, A. Burk, M. Das, B. Hull, F. Husna, A. Powell, J. Richmond, S. Ryu and Q. Zhang, "Recent Progress in SiC DMOSFETs and JBS Diodes at Cree", in Proc. IEEE Annu. Conf. Ind. Electron., pp. 2885-2890, 2008.

A. Mihaila, R. A. Minamisawa, L. Knoll, V. K. Sundaramoorthy, E. Bianda, H. Bartolf, G. Alfieri, M. Rahimo, "On the Influence of Active Area Design on the Performance of SiC JBS Diodes", Mater. Sci. Forum, vols. 897, pp. 471-474, May 2017.

L. Liu, J. Wu, H. Xu, Z. Zhu, N. Ren, J. Zhang, K. Sheng, "The Impact of the Hexagonal and Circular Cell Designs on the Characteristics and Ruggedness for 4H-SiC MPS Diodes", IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1226-1232, Mar 2022.

B. Asllani, H. Morel, L.V. Phung, D. Planson, " 10 kV Silicon Carbide PiN Diodes-From Design to Packaged Component Characterization", Energies 12(23), 4566, 2019.

J. Lynch, N. Yun and W. Sung, "Design Considerations for High Voltage SiC Power Devices: An Experimental Investigation into Channel Pinching of 10 kV SiC Junction Barrier Schottky (JBS) Diodes", in Proc. 31st Int. Symp. Power Semiconductor Devices ICs (ISPSD), pp. 223226, May 2019.

S. A. Mancini, S. Y. Jang, D. Kim and W. Sung, "Increased 3rd Quadrant Current Handling Capability of 1.2 kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances", in Proc. IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), pp. 101-106, 2021.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 75-80

doi: 10.4028/p-ux3mDr

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-17

Revised:
2025-12-08

Accepted:
2026-01-31

Online:
2026-05-21

Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

D. Scholten 1,a*, J. Ziegler 2,b, W. Feiler 2,b

1 Advanced Technologies and Micro Systems, Robert Bosch GmbH, Germany,

2 Mobility Electronics, Robert Bosch GmbH, Germany

a  dick.scholten@de.bosch.com, b  johannes.ziegler2@de.bosch.com, c wolfgang.feiler@de.bosch.com

Keywords: 4 H -SiC MOSFET, Fowler-Nordheim current, gate leakage.

Abstract

We show that various commercially available silicon carbide MOSFETs exhibit significant gate leakage current at gate voltages below - 20 V . With prolonged negative bias stress, this leakage current reduces by several orders of magnitude. Literature [ 1−4 ] suggests that this current is due to hole current from the silicon carbide and explain the current reduction by the discharge of neutral electron traps at the SiC/SiO2-interface. However, measurements on n+-doped SiC -MOSCAPs, where we avoid hole current, exhibit similar gate leakage behavior, indicating that there might be an alternative explanation. Further measurements show that the threshold voltage is not significantly impacted by the negative gate bias stress, indicating that the channel region is not involved in the gate leakage current and its reduction due to trapping effects. Devices with a floating source do not show leakage, and we therefore conclude that the origin of the gate leakage is in the source region. An analytical calculation is used to show that field enhancement at the edges of the polysilicon gate electrode, assuming a corner radius below 10 nm , may explain the onset voltage of the gate leakage current at negative bias. Alternatively, gate oxide damage from the polysilicon etching process may also explain the leakage current. The reduction of the onset voltage of the gate leakage with prolonged negative voltage gate stress, may be explained by significant electron trapping due to the high local current density at the poly-silicon gate electrode corner.

Introduction

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The minimum rated gate voltage of commercial SiC MOSFETs typically ranges between -15 V and -4 V . Lower gate voltages may be employed for accelerated testing, such as in time-dependent dielectric breakdown (TDDB) with negative gate voltage, threshold voltage drift under negative gate bias, or bipolar dynamic gate switching stress. However, at very low gate voltages, typically below -15 V , several studies report significant gate leakage currents that decrease with continued negative gate voltage stress [ 1−4 ]. To evaluate the impact of the gate leakage on the accelerated reliability tests, a comprehensive understanding of its root cause is necessary. The prevailing hypothesis in these studies suggests that this current is a hole current from the silicon carbide towards the gate electrode. The reduction of hole current with continuing negative bias stress is explained by neutral near-interface traps that discharge electrons, thereby increasing the barrier height for holes.

In this paper, we investigate the location of the gate leakage and focus on the corners of the polysilicon gate electrode. Fig. 1 shows a schematic cross section of a typical planar and a typical trench MOSFET, where the edges of the poly-silicon gate electrode are indicated by the dashed circles.

We will show the gate leakage for negative gate voltage from different commercially available devices and compare that with results measured from SiC MOSCAP testing structures. To estimate the impact of the gate electrode geometry, we will present a calculation method to estimate the field enhancement factor from the radius of curvature of the poly-silicon edges.

[picture]

Fig. 1. Schematic cross sections of different typical SiC MOSFET cell concepts. Dashed circles indicate poly-silicon corners at the gate electrode opposite the source region. Plum and blue colored arrows indicate leakage current paths as proposed in literature and in this work. a) planar cell concept. b) trench cell concept.

Fig. 1. Schematic cross sections of different typical SiC MOSFET cell concepts. Dashed circles indicate poly-silicon corners at the gate electrode opposite the source region. Plum and blue colored arrows indicate leakage current paths as proposed in literature and in this work. a) planar cell concept. b) trench cell concept.

Gate Voltage Ramp Measurements

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We utilized commercially available SiC MOSFETs from four different vendors and applied bidirectional gate voltage ramps with varying maximum voltage values, as illustrated in Fig. 2, where the ramp order is indicated by the legend. All measurements were performed at room temperature. The onset of gate leakage with positive gate voltage ramp was significantly higher for Vendor C. Assuming that this is due to higher gate oxide thickness and desiring to have similar oxide electric fields for all vendors, we extended the voltage ramps for vendors C by 5 V .

We started by ramping up and down to a positive maximum gate voltage twice. The figure shows that the FN-current for positive gate bias is stable for all devices. The leakage current for all subsequent voltage ramps with negative gate bias shows clear reduction of current for each further gate bias ramp.

[picture]

Fig. 2. Absolute value of gate leakage current during different subsequent voltage ramps measured on devices from 4 different vendors. Note that for vendor C , we used 5 V higher values for the maximum gate voltage.

Fig. 2. Absolute value of gate leakage current during different subsequent voltage ramps measured on devices from 4 different vendors. Note that for vendor C , we used 5 V higher values for the maximum gate voltage.

The gate leakage current under negative bias appears to converge to a curve similar to the forward Fowler-Nordheim (FN) curve, but with opposite polarity, as negative voltage stress continues. We therefore propose that the gate leakage current under negative bias is an FN current characterized by an initially low barrier or a high local electric field at the barrier. Continued negative gate voltage stress shifts the onset of the current to significantly lower voltages, either by increasing the barrier or reducing the local electric field. Before and after each gate voltage ramp, we measured the threshold voltage, as shown in Fig. 3. The change in threshold voltage was significantly smaller than the shift in the onset of gate leakage. Compare for example, the shift in gate leakage onset ΔVonset  for the device from Vendor C of about - 13 V in Fig 2 with the change in threshold voltage of <50mV, as shown in Fig. 3. This indicates that the charging or discharging of near-interface traps in the channel region cannot account for the shift in the onset of gate leakage at negative bias.

[picture]

Fig. 3. Threshold voltage before and after each voltage ramp shown in Fig. 2.

Fig. 3. Threshold voltage before and after each voltage ramp shown in Fig. 2.

Gate Leakage of a Planar MOSCAP on an𝐧+-Doped SiC Epilayer

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

To test if hole current causes leakage at moderate negative bias, we measured the leakage current in an n+-doped SiC MOSCAP. The gate oxide thickness was 80 nm , and the substrate contained a uniform doping profile with a depth of 200 nm and an aluminum doping concentration of 8×1018 cm−3. We ramped the voltage of the top electrode from 0 V to +70 V to -50 V to 0 V and observed similar gate leakage behavior to that in commercial SiC MOSFETs, as shown in Fig. 4. We see an onset of gate leakage beyond -25 V and corresponding hysteresis, while at positive bias, we do not see significant hysteresis. At moderate negative gate bias in the range of this onset, we do not expect significant hole current from the n+-doped silicon carbide, as we do not expect inversion. Without hole current we can rule out the hypothesis from literature described above.

[picture]

Fig. 4. Gate leakage of a planar MOSCAP on an n+-doped SiC epilayer. a) Schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to +70 V to -50 V and back to 0 V .

Fig. 4. Gate leakage of a planar MOSCAP on an n + -doped SiC epilayer. a) Schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to +70 V to -50 V and back to 0 V .

Gate Leakage of a MOSFET with Either the Source or the Drain Terminal Floating

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We measured the leakage current at negative gate bias for a device from Vendor A with either the source electrode or the drain electrode floating, as shown in Fig. 5b, demonstrating that the leakage current does not originate from the drain.

[picture]

Fig. 5. Gate leakage of a MOSFET with either the source or the drain terminal floating. a) schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to -40 V and back to 0 V of a device from vendor A with either drain or source electrode floating.

Fig. 5. Gate leakage of a MOSFET with either the source or the drain terminal floating. a) schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to -40 V and back to 0 V of a device from vendor A with either drain or source electrode floating.

Analytical Calculation of the Field Enhancement Factor at the Poly-Silicon Corner

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Fig. 6a, shows calculated equipotential lines for a square edge close to an infinite surface. By associating the infinite surface with the SiC/SiO2-interface and one of the equipotential lines with the edge of the poly-silicon gate electrode, we estimate the field enhancement at a rounded corner of a SiC MOSFET gate electrode. The electric field was calculated using conformal mapping with a complex function

f(z)=f(x+iy)=u+iv.(1)

We use the Schwarz-Christoffel Transformation,

f(z)=ez+1+12log[ez+1−1ez+1+1](2)

adapted from [5], to map the equipotential lines of the electric field of an infinite parallel plate capacitor in two dimensions to a similar capacitor that has a 90∘ bend in the top plate away from the bottom plate, as depicted in Fig. 6a by the black line inside the superimposed poly-silicon area.

The field line roughly corresponding to the minimum radius of curvature of all the equipotential lines, is indicated in the figure by the line exiting from the poly-silicon corner. We calculated the radius of curvature of this field line by the following formula.

R=|(1+(dvdu)2)32d2vdu2|(3)

Fig. 6b displays the radius of curvature of the field line from Fig. 6a versus the field enhancement factor, defined as the field at the corner relative to the field between parallel plates far from the corner. Note that at large radii of curvature, the field enhancement factor decreases below 1 due to the increased distance between the corner and the plane compared to the region distant from the corner.

Based on the presented data, we propose the following hypothesis: With a corner radius of approximately 3 nm , the onset of FN current is expected to occur roughly twice as early as in the case of parallel plates. Typical polysilicon etching or reoxidation processes can cause corner radii well below 10 nm , which aligns with our simplified model explaining the early onset. Although some manufacturers seem to use polysilicon reoxidation to increase the distance between the SiC -interface and the poly-silicon corner by up to 50%, a corner radius well below 10 nm would still cause significant gate leakage as indicated by the steep slope of the field enhancement factor below 10 nm radius shown in Fig. 6b.

[picture]

Fig. 6. a) Edge of poly-silicon electrode in a planar SiC-MOSFET superimposed with calculated equipotential lines using conformal mapping with the Schwarz-Christoffel Transformation. b) Calculated field enhancement factor at the corner of the poly-silicon against the radius of curvature.

Fig. 6. a) Edge of poly-silicon electrode in a planar SiC-MOSFET superimposed with calculated equipotential lines using conformal mapping with the Schwarz-Christoffel Transformation. b) Calculated field enhancement factor at the corner of the poly-silicon against the radius of curvature.

Oxide Damage at the Edge of the Polysilicon Electrode

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

Etching polysilicon to define the extent of the electrode might cause damage to the oxide surface not masked by the polysilicon [6]. Oxide damage at the corner of the polysilicon might lower the barrier for electron emission from the gate electrode and thus explain the leakage current at negative gate bias, possibly in combination with geometric field enhancement.

Leakage Current Reduction with Prolonged Gate Bias Stress

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Due to the anticipated high electron current density at the poly-silicon corners, we also assume that local electron trapping is significantly enhanced, leading to a reduction of the electric field at the corners and consequently a decrease in FN current with continued electron current stress. The leakage current is therefore self-limiting. The trapping rate might also be enhanced due to the oxide damage at the edge of the polysilicon as explained in the previous section.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

Fiorenza, Patrick, Antonino La Magna, Marilena Vivona, and Fabrizio Roccaforte. "Near Interface Traps in SiO2/4H−SiC Metal-Oxide-Semiconductor Field Effect Transistors Monitored by Temperature Dependent Gate Current Transient Measurements." Applied Physics Letters 109, no. 1 (July 4, 2016): 012102. https://doi.org/10.1063/1.4955465.

Anoldo, Laura, Edoardo Zanetti, Walter Coco, Alfio Russo, Patrick Fiorenza, and Fabrizio Roccaforte. "4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed HighTemperature Reverse Bias and Negative Gate Bias Stresses." Materials 17, no. 8 (April 20, 2024): 1908. .

Shi, Limeng, Jiashu Qian, Michael Jin, Monikuntala Bhattacharya, Shiva Houshmand, Hengyu Yu, Atsushi Shimbori, Marvin H. White, and Anant K. Agarwal. "Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-Oxide-Semiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress." Electronics 13, no. 22 (November 18, 2024): 4516. .

Hiroki Nemoto, Dai Okamoto, Xufang Zhang, Mitsuru Sometani, Mitsuo Okamoto, Tetsuo Hatakeyama, Shinsuke Harada, Noriyuki Iwamuro and Hiroshi Yano. "Conduction mechanisms of oxide leakage current in p-channel 4H-SiC MOSFETs" Japanese Journal of Applied Physics, volume 59, number 4 (March 30, 2020): 044003. .

See .

Ohmori, T., and T. Makabe. "In Situ Measurement of Plasma Charging on SiO2 Hole Bottoms and Reduction by Negative Charge Injection during Etching." Applied Surface Science 254, no. 12 (April 2008): 3696-3709. .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 81-87

doi: 10.4028/p-Q9p090

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-22

Revised:
2025-12-21

Accepted:
2026-02-26

Online:
2026-05-21

Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

Takeshi Tawara 1,a*, Kensuke Takenaka 1, b, Syunki Narita 2,c and Shinsuke Harada 1, d

1 National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba West, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

2 Fuji Electric Co., Ltd., 4-18-1 Tsukama, Matsumoto, Nagano 390-0821, Japan

a*tawara-takeshi@aist.go.jp, btakenaka-kensuke@aist.go.jp, ,narita-syunki@fujielectric.com, d  s-harada@aist.go.jp

Keywords: superjunction, MeV implantation, body diode, reverse recovery.

Abstract

MeV-SJ-MOSFET with short tapered SJ columns was developed by high-energy (MeV) Al ion implantation and was evaluated for the reverse recovery characteristics and the body diode reliability compared to those of Multiepi-SJ. MeV-SJ alleviated the increase in on-resistance at elevated temperatures regardless of short SJ columns and exhibited soft reverse recovery characteristics due to the short tapered SJ shape. MeV-SJ also suppressed the body diode degradation more than Multiepi-SJ. It was considered that the carrier lifetime of drift layer of MeV-SJ may be decreased by non-radiative defects.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

A 1.2 kV SiC semi-SJ-MOSFET formed by multi-epi process (repetition of epitaxial growth and ion implantation of medium-energy ( keV )) has advantages of a low specific on-resistance ( RonA ), soft reverse recovery and suppression of bipolar degradation of the body diode even at a high temperature [1-3]. However, due to the low diffusion coefficients of dopant atoms, the cost of Multiepi process is relatively high because of a large repetition number [4]. Recently MeV ion implantation process (deep ion implantation at MeV energies) was proposed to address the cost issue [5,6], but there are no detailed studies. In this study, we investigated the reverse recovery and bipolar degradation of the body diode of SJ-MOSFET formed by the MeV ion implantation process.

Experiment

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N-type epitaxial layers were grown on a 4H−SiC commercial substrate, followed by Al ion implantation at room temperature (R.T.) up to 8.0 MeV to form the SJ structure. A trench-MOSFET with 2.5μ m depth short tapered p-columns ( MeV -SJ) was fabricated. The tapered shape was employed to enhance the soft reverse recovery. For comparison, a trench-MOSFET (UMOS) and a trench-MOSFET with 5.2μ m depth SJ columns formed by multiepi method (Multiepi-SJ) were also fabricated. MeV-SJ and Multiepi-SJ have an identical design of the drift epitaxial layers. Crosssectional schematics and SEM micrographs of devices are illustrated in Figs. 1 and 2, respectively. The fabricated devices were mounted in TO-247 PKG, and their static and dynamic characteristics were evaluated. Reverse recovery characteristics were evaluated using a double pulse test method, where the same type of devices were used for the MOSFET and the body diode. The load inductance was 1 mH , the gate resistance was 75Ω and the junction temperature was 175∘C. Then we evaluated bipolar degradation of the body diode under a maximum current stress of 1500 A/cm2 for 5 min at 175∘C. Finally, implantation defects were investigated by cathodoluminescence (CL) at 28 K [7].

Results & Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

1. Static characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

Typical static characteristics at R.T. and 175∘C are summarized in Table. 1. Blocking waveforms are displayed in Fig. 3. MeV-SJ has a lower breakdown voltage for the shorter SJ columns than Multiepi-SJ, but shows a stable avalanche breakdown. Temperature dependences of specific onresistance ( RonA ) are presented in Fig. 4. Multiepi-SJ and MeV -SJ show lower RonA and weaker temperature dependence than UMOS, which originates from the high doping density of their drift layers.

[picture]

Fig. 1. Cross-sectional schematics of devices.

Fig. 1. Cross-sectional schematics of devices.

[picture]

Fig. 2. Cross-sectional SEM micrographs of devices.

Fig. 2. Cross-sectional SEM micrographs of devices.

Table I. Typical static characteristics.

[picture]

Fig. 3. Blocking waveforms.

Fig. 3. Blocking waveforms.

[picture]

Fig. 4. Temperature dependences of Specific on-resistance.

Fig. 4. Temperature dependences of Specific on-resistance.

2. Reverse recovery characteristics

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First, we investigated the effect of the shape of SJ columns on the reverse recovery characteristics. The reverse recovery waveforms of 1.2 kV class SJ-MOS were simulated by Sentaurus TCAD simulation for the two SJ column shapes (SJ-straight and SJ-taper) and UMOS in the chopper circuit where the same type of devices were used in MOS and body diode. The results are depicted in Fig. 5. SJ-straight show large dV/dt and dir/dt values, while SJ-taper shows smaller values. In SJ devices, the dir/dt drastically changes when the output capacitance ( Coss  ) rapidly decreases due to the full
depletion of SJ columns [8,9]. The tapered shape of SJ columns alleviates the abrupt change of Coss  caused by the pinch-off of SJ columns, resulting in the soft recovery waveform.

[picture]

Fig. 5. Simulated reverse recovery waveforms of devices with different SJ column shapes.

Fig. 5. Simulated reverse recovery waveforms of devices with different SJ column shapes.

Second, we present the measured reverse recovery waveforms in Fig 6. MeV-SJ presents soft recovery waveforms by the short tapered columns. Then the current dependences of reverse recovery charge ( Qrr ) are shown in Fig. 7. The dependence for MeV -SJ is very weak, indicating that the carrier injection is suppressed at elevated temperatures similar to Multiepi-SJ. The smaller Qrr value of MeV SJ arises from the small junction capacitance for short SJ columns. The measured Coss−Vds characteristics are presented in Fig. 8 (a). MeV-SJ exhibits small Coss  without second sharp decline caused by the pinch-off of SJ columns. The simulated Coss −Vds curves in Fig. 8 (b) are in good agreement with the measured Coss −Vds curves. The depletion layer at Vds of 20,50 and 120 V are depicted in Fig. 8 (c). The depletion layer of Multiepi-SJ is expanding laterally and pinched off causing the drastic change of Coss  at around 100 V while that of MeV -SJ is expanding vertically, which leads to the gradual change of Coss.

Then the turn-on and turn-off waveforms of each device are presented in Fig. 9 and 10, respectively. The dV/dt of MeV-SJ is also smaller that that of Multiepi-SJ and there are no clear differences in Turn-off waveforms.

[picture]

Fig. 6. Reverse recovery waveforms at 175∘C.

Fig. 6. Reverse recovery waveforms at 175 ∘ C .

[picture]

Fig. 7. Qrr dependencies on load current.

Fig. 7. Q r r dependencies on load current.

[picture]

Fig. 8. (a) Measured and (b) simulated Output capacitance characteristics and (c) the depletion layer of each device.

Fig. 8. (a) Measured and (b) simulated Output capacitance characteristics and (c) the depletion layer of each device.

[picture]

Fig. 9. Turn-on waveforms.

Fig. 9. Turn-on waveforms.

[picture]

Fig. 10. Turn-off waveforms.

Fig. 10. Turn-off waveforms.

3. Body diode reliability

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Body diode reliability was evaluated with the current stress test up to 1500 A/cm2 at 175∘C. The Vf variations after each current stress are presented in Fig. 11. MeV-SJ shows higher durability than Multiepi-SJ. We observed the PL image with a wavelength of 420 nm after the 1500 A/cm2 stress test. Most devices show the bar-shaped single Shockley Stacking Faults (bar-shaped SFs) in chips. The typical width of bar-shaped SFs is 60μ m in Multiepi-SJ and 30μ m in MeV-SJ. Those values equivalent to the depth of 4μ m and 2μ m considering the substrate off-angle of 4∘. Bar-shaped SFs of MeV−SJ are assumed to stop expanding in the buffer layer.

[picture]

Fig. 11. (Upper) ΔVf dependences on current stress and (Lower) PL images ( λ=420±5 nm ) after the current stress of 1500 A/cm2.

Fig. 11. (Upper) Δ V f dependences on current stress and (Lower) PL images ( λ = 420 ± 5 n m ) after the current stress of 1500 A / c m 2 .

The simulated hole density profile of MeV -SJ under the current stress of 1500 A/cm2 at 175∘C is presented in Fig. 12 where the carrier lifetime of both drift layer consisting of SJ columns and buffer layer is changed from 1 ns to 100 ns . As described in Ref. 7, the Al implantation to form SJ columns decreases a carrier lifetime in the drift layer. In Fig. 12, the dotted line indicates the expansion threshold of bar-shaped SFs at the buffer/substrate interface as reported in Ref. 10, which is 1e16 cm−3. If the hole density exceeds the threshold, bar-shaped SF would expand from epi/substrate interface. In the case of the lifetime of 1ns, there is no region of hole density over the threshold near the epi/substrate interface and no bar-shaped SFs would expand. On the other hand, for the lifetime of 100 ns , the hole density exceeds the threshold in the whole drift layer and a bar-shaped SF would expand to the surface. However, in the case of the lifetime of 5 and 7.5 ns , there is a local region of hole density under the threshold. A bar-shaped SF expanding from epi/substrate interface would stop at the region and become narrow as reported in Ref. 11. The region of high hole density near the epi/substrate interface is supported by the excess electron injection into the buffer region from the substrate side and extends with increasing the drift layer lifetime. From these results, the lifetime in drift region of MeV-SJ would be smaller than that of Multiepi-SJ.

[picture]

Fig. 12. Simulated hole density profile of devices with different lifetimes of drift layer.

Fig. 12. Simulated hole density profile of devices with different lifetimes of drift layer.

Finally, we investigated ion implantation defects using CL imaging. First the typical CL spectra are presented in Fig. 13(a). CL spectrum of Multiepi-SJ and MeV-SJ have different intensities but similar peaks in each device region. The cross-sectional images of the Ll line which is a well-known implantation defect, are shown in Fig. 13 (b). The intensity is standardized by the near the band edge intensity. The L1 intensity of Multiepi-SJ is stronger than that of MeV-SJ in SJ and buffer region.

This would be caused by the extensive thermal history of Multiepi-SJ where the epitaxial growth is repeated. The L1 line intensity is reported to increase under high-temperature annealing [12]. On the other hand, these results cannot explain the higher body diode reliability of MeV -SJ. The nonradiative defects that are not detected in CL may affect the suppression of bipolar degradation.

[picture]

Fig. 13. (a) CL spectra of devices. (b) Cross-sectional SEM micrographs and CL images of normalized L1 line luminescence and those line profiles.

Fig. 13. (a) CL spectra of devices. (b) Cross-sectional SEM micrographs and CL images of normalized L 1 line luminescence and those line profiles.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

Even short SJ columns of 2.5μ m can mitigate the increase of on-resistance at high temperatures because of high doping concentration of the drift layer. Short tapered SJ columns soften the reverse recovery waveform by mitigating the abrupt change of Coss.  MeV-SJ suppresses the body diode degradation more than Multiepi-SJ due to the short carrier lifetime of the drift region. MeV-SJ with short tapered SJ columns has the advantage of high reliability of the body diode and soft reverse recovery compared with Multiepi-SJ.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

This study was implemented under a joint research project of Tsukuba Power Electronics Constellations (TPEC). Specifically, T. Tawara and K. Takenaka were assigned from Fuji Electric Co., Ltd. Authors specially thanks to Mr. T. Morimoto of AIST and Mr. K. Oozono of PHENITEC SEMICONDUCTOR Corp. for prototyping and helpful discussions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

S. Harada, Y. Kobayashi, S. Kyogoku, T. Morimoto, T. Tanaka, M. Takei, and H. Okumura, IEDM2018 (2018) 181.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 89-94

doi: 10.4028/p-V4pYXX

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-21

Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Boglárka Dikó 1,a, Oleg Rusch 2,b, Julien Körfer 2,c, Zsófia Kiss 1,d, Attila Sütő 1,e and Emeric Balogh 1, f *

1 Semilab Semiconductor Physics Lab. Co. Ltd., Hungary

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Germany

a  boglarka.diko@semilab.hu, b  oleg.rusch@iisb.fraunhofer.de, c  julien.koerfer@iisb.fraunhofer.de,

d zsofia.kiss@semilab.hu, e attila.suto@semilab.hu, f emeric.balogh@semilab.hu

Keywords: trench MOSFET, OCD, critical dimension metrology, ellipsometry, reflectometry.

Abstract

Silicon carbide (SiC) MOSFETs are widely utilized in power device applications for their numerous advantages, and the device's properties can be further optimized through the implementation of trench structures. The formation of the trench structure is a multi-step process, in which it is important to monitor the result of each step and ensure that the structure meets the desired requirements. OCD (optical critical dimension) metrology can provide a fast, non-destructive solution for this purpose. In this article, an OCD analysis of structures at two different process steps is presented and compared with the results from the electron microscopy images. OCD results show high sensitivity to the geometrical dimensions of the structure and produce a good correlation with the electron microscopy images. This metrology can provide a means to detect subtle structural differences without causing any damage to the sample.

1 Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Silicon Carbide (SiC) MOSFETs are extensively researched and widespread in power device applications owing to their many advantages, and trench structures can further improve their properties. The vertical channel in trench MOSFETs increases integration density, heat dissipation and channel mobility, simultaneously reducing on-resistance, enabling the production of more efficient devices with lower power consumption [1,2].

Trench structures are fabricated in a multi-step process, involving different etching steps [3]. Trench formation in SiC is usually carried out using dry etching processes. During the process, SiO2 serves as a masking material, and the shape of the hard mask (HM) has a significant influence on the shape of the final SiC trench [1]. A certain sidewall angle (~90∘) is required for trenches to obtain high charge carrier mobility, to minimize the interface states between the SiC sidewall and the gate oxide, and to avoid cavities during the subsequent polysilicon filling. In addition to the shape, the depth of the trenches is also a critical parameter for obtaining the length of the channel that allows the desired properties to be achieved [1,2]. There are many process steps in which it is important to monitor whether the structure meets the requirements for an optimal trench MOSFET device.

Optical critical dimension metrology (OCD) offers a fast, non-destructive, non-contact method for investigating the geometrical parameters of the structure (sidewall angle (SWA), depth, critical dimension (CD) parameters, etc.). We present the advantages and results of OCD evaluation of two types of structures (hard mask trench on SiC substrate and SiC trench with a hard mask on top). The investigated structures are analyzed by scanning electron microscopy (SEM) as well, which allows us to compare the parameter values obtained by the two methods and to validate the OCD analysis results. It is important to highlight that OCD measures average results within the measurement spot (50μ m), and therefore, local variation in trench geometry can make direct SEM comparison challenging.

2 Methods

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2.1 Evaluation method

OCD metrology, also known as Model-Based Dimension (MBD) metrology or scatterometry, allows the geometric parameters and shape of the investigated structure to be characterized rapidly and non-destructively [4]. Measurements used by OCD, such as reflectometry and ellipsometry, can be sensitive to buried structures as well, which are traditionally not measurable by non-destructive techniques. This is an indirect, model-based method; thus, an accurate theoretical model of the trench structure has to be built for accurate evaluation. This requires some prior knowledge of the structure, including the shape and nominal dimensions of the trench structure and the optical constants of constituent materials. Furthermore, a successful OCD evaluation requires the measurement spot to cover a periodically repeating structure with a sufficient number of periods [5]. Evaluation is done by modelling the light-matter interaction of the measurement beam with the sample structure. Most commonly, the Rigorous Coupled-Wave Analysis (RCWA) [6] method is applied for this purpose, and it was also used in this study. The geometrical parameters are extracted by an algorithm which finds the trench parameters that produce the best match between simulated and measured spectra. With an optimized evaluation algorithm, this allows fast full-wafer mapping and tight process control in many steps of the process. To accurately model SiC, the optical anisotropy of the material has to be considered in RCWA [7]. To further increase accuracy, the instrumentation properties (like detector resolution and focusing optics properties) were taken into account [8].

In this study, Spectroscopic Polarized Reflectometry measurements were performed on the wafers to characterize the trenches. The sample under investigation is illuminated with light of two polarizations: parallel to the plane of incidence ( p -polarization) and perpendicular to it ( s polarization) and reflectance is measured independently for both polarizations. Extraction of the geometrical dimensions of the trenches is then done with a dedicated software which performs the simulation of the measurement and parameter fitting. With an optimized evaluation recipe, the evaluation can be done in seconds, allowing the characterization of the trench dimensions to be performed on each die on the wafer, or even at multiple sites within a single device.

2.2 Investigated structures and SEM measurements

Several samples were fabricated according to the process described in Rusch et al. [1]. In the first example (Fig. 1.), the wafer has already gone through the HM etching process and the characterization of the dimensions of the oxide mask is performed. The HM defines the shape and width of the final trench; therefore, this process step is critical to monitor.

The second example (Fig. 2.) is a case of SiC trench etch monitoring right before hard mask removal. The presented optical method allows the monitoring of both the SiC trench etch depth and the remaining HM thickness; therefore, in this step, it is possible to contain the etch process.

The samples were prepared for SEM measurements by FIB milling to reveal the cross-section of the trenches. SEM images were taken at 10k,50k and 100 k magnifications, aligned at a 52∘ angle to the surface normal. This angle was accounted for in the measurements and the SEM images shown are scaled accordingly for visual comparison with OCD evaluation.

[picture]

Fig. 1. SEM image of SiO 2 hard mask trench on SiC .

Fig. 1. SEM image of SiO 2 hard mask trench on SiC .

[picture]

Fig. 2. SEM image of SiC trench with a SiO2 mask on top.

Fig. 2. SEM image of SiC trench with a S i O 2 mask on top.

3 Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

3.1 OCD analysis of hard mask etched SiC samples

The comparison of the SEM and OCD analysis results was performed at three different points on the wafer. For one of the sites, Fig. 3. shows the measured and fitted reflectance spectra derived from RCWA simulation based on the modelled structure. For the same site, the SEM image and the OCD model for the SiO2 hard mask trench are shown in Fig. 4. The trench is modelled with a trapezoidal shape in the OCD model. The results show very good agreement with the structure observed in the electron microscopy image. The agreement of the results, and the good match between the measured and modelled spectra for both polarizations show the accuracy of the theoretical model and reliability of the evaluation algorithm. It is important to note here as well that the OCD evaluation represents an average over the entire measurement spot, rather than the parameters of a single trench as in the SEM measurement. Therefore, the comparison should be interpreted accordingly.

[picture]

Fig. 3. Measured and fitted reflectance spectra of HM trench.

Fig. 3. Measured and fitted reflectance spectra of HM trench.

[picture]

Fig. 4. SEM image and trench structure resulting from the OCD evaluation −SiO2 hard mask trench on SiC .

Fig. 4. SEM image and trench structure resulting from the OCD evaluation − S i O 2 hard mask trench on SiC .

Considering the results of the three sites on the wafer, a strong correlation can be observed between the extracted and SEM parameter values. Fig. 5. shows the relation between these values for the trench bottom CD (BCD), top CD (TCD), and SiO2 wall sidewall angle (SWA) parameters. The diagrams confirm that accurate structural modelling allows the extraction of reliable structural parameters by OCD analysis, in a fast and non-destructive way.

The HM sidewall angle, for example, is a key parameter, as it significantly influences the shape of the final SiC trench. Knowing this value allows us to be aware of whether the desired structure has been achieved and whether it is worthwhile to proceed with the SiC trench formation process.

[picture]

Fig. 5. Trench BCD, TCD, and Wall SWA - relationship between SEM and OCD analysis results.

Fig. 5. Trench BCD, TCD, and Wall SWA - relationship between SEM and OCD analysis results.

3.2 OCD analysis of SiC trench samples with an oxide mask on top

In this case as well, the comparison was performed at three different points on the wafer. The measured and simulated spectra at one measurement points are shown in Fig. 6. This OCD model is built from a total of 6 trapezoids to describe the shape of the SiC trench wall and that of the remaining HM oxide on top and redeposited on the wall. Similar to the HM trench, very good agreement was observed between the structure obtained from the OCD analysis and that derived from the SEM images (Fig. 8.). The shape of the trench also closely follows the form observed in the electron microscopy image (Fig. 7.).

[picture]

Fig. 6. Measured and fitted reflectance spectra of SiC trench with an oxide mask on top.

Fig. 6. Measured and fitted reflectance spectra of SiC trench with an oxide mask on top.

[picture]

Fig. 7. SEM image and trench structure resulting from the OCD evaluation -SiC trench with an oxide mask on top.

Fig. 7. SEM image and trench structure resulting from the OCD evaluation -SiC trench with an oxide mask on top.

[picture]

Fig. 8. Trench BCD , TCD , and oxide mask TCD - relationship between SEM and OCD analysis results.

Fig. 8. Trench BCD , TCD , and oxide mask TCD - relationship between SEM and OCD analysis results.

3.3 Full wafer and micro-mapping of trench dimensions

OCD analysis enables fast evaluation of the structural parameters across the wafer at multiple measurement points. Fig. 9 shows the measured SWA, trench TCD, and height maps of the HM trench across the entire wafer. These maps provide insight into how the structure changes and where the desired trench shape has been successfully achieved.

[picture]

Fig. 9. Wall SWA, trench TCD, and HM height maps across the wafer −SiO2 hard mask trench on SiC.

Fig. 9. Wall SWA, trench TCD, and HM height maps across the wafer − S i O 2 hard mask trench on SiC.

In addition to the wafer-scale maps, it is also possible to scan specific regions of the wafer at a smaller scale, providing insight into structural variations at the microscale. Fig. 10. presents maps of the parameters shown in the wafer-scale maps but measured over a selected 3.4×2.4 mm region of the wafer using a 200μ m step size. This represents the active area of a single trench MOSFET device. Even within such a small region, the distribution of the parameters can be characterized, providing feedback for process control and verification.

[picture]

Fig. 10. Wall SWA, trench TCD, HM height maps with a 200μ m step −SiO2 hard mask trench on SiC.

Fig. 10. Wall SWA, trench TCD, HM height maps with a 200 μ m step − S i O 2 hard mask trench on SiC.

In a similar manner, the SiC trench wafer was also characterized using these approaches. The parameter distributions of trench TCD and height are shown at macro (Fig. 11) and micro (Fig. 12) scales in the following figures. The thickness of the residual oxide mask was roughly uniform on a millimeter scale, so only the full wafer map is presented for this parameter.

[picture]

Fig. 11. Trench TCD, trench height, and HM height maps across the wafer −SiO2 hard mask trench on SiC .

Fig. 11. Trench TCD, trench height, and HM height maps across the wafer − S i O 2 hard mask trench on SiC .

[picture]

Fig. 12. Trench TCD and trench height maps with a 200μ m step −SiO2 hard mask trench on SiC .

Fig. 12. Trench TCD and trench height maps with a 200 μ m step − S i O 2 hard mask trench on SiC .

4 Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Silicon carbide trench devices are fabricated in a multi-step process during which it is essential to monitor whether the structure is indeed forming according to the requirements.

We presented the evaluation of the structural parameters of two types of structures (hard mask trench on SiC substrate and SiC trench with a hard mask on top) using a non-contact, non-destructive and fast method. The results obtained from the OCD analysis for three sites were compared with electron microscope images taken at the same sites on the wafer.

OCD shows high sensitivity to structure details and the results show good correlation with the SEM parameter values proving the reliability of the OCD measurement. We presented wafer maps evaluated by OCD analysis to show the variation of parameters across the wafer, and we also investigated the parameter changes on the scale of a single device.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Oleg Rusch, Kevin Brueckner and Tobias Erlbacher, Solid State Phenomena, 359, 193-200 (2024).

Xiaoyu Tan, Guoming Lin, Ankuan Ji and Yuanwei Lin, Materials Science in Semiconductor Processing, 188, 109172 (2025).

Tsunenobu Kimoto and James A. Cooper, Fundamentals of Silicon Carbide Technology (2014).

Morten Hannibal Madsen and Poul-Erik Hansen, Surf. Topogr.: Metrol. Prop., 4, 023003 (2016).

Richard Silver et al., Metrology, Inspection, and Process Control for Microlithography XXI, 6518, 65180U, (2007).

M. G. Moharam and Thomas K. Gaylord, J. Opt. Soc. Am., 71, 811-818 (1981).

John M. Jarem, Proc. SPIE 4467, Complex Mediums II: Beyond Linear Isotropic Dielectrics, (9 July 2001).

Thomas A. Germer and Heather J. Patrick, Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76381F (2010).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 95-101

doi: 10.4028/p-4rcL7P

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-20

Accepted:
2026-03-08

Online:
2026-05-21

Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1057.95.pdf

Kyrylo Melnyk 1,a*, Arne Benjamin Renz 1,b, M. A. Yildirim 1,c, N. Iosifidis 1,d, Q. Cao 1,e, J. Ortiz Gonzalez 1,f, V. A. Shah 1, g, J. A. Gott 2, h, P. M. Gammon 1,i and Marina Antoniou 1,j

1 University of Warwick, Coventry, United Kingdom

2 Warwick Manufacturing Group, Coventry, United Kingdom

a*Kyrylo.Melnyk@warwick.ac.uk, b Arne.Renz@warwick.ac.uk, c Mustafa.Yildirim@warwick.ac.uk, d Nikos.losifidis@warwick.ac.uk, e Q.Cao.2@warwick.ac.uk, f J.A.Ortiz-Gonzalez@warwick.ac.uk, 9 Vishal.Shah@warwick.ac.uk, h J.Gott@warwick.ac.uk, iP.M.Gammon@warwick.ac.uk, j  Marina.Antoniou@warwick.ac.uk

Keywords: superjunction, semi-superjunction, planar MOSFET, body diode, reverse recovery.

Abstract

This study investigates static and dynamic behavior of a 3.3 kV semi-Superjunction (SJ) MOSFET, compared with a conventional planar MOSFET. The semi-SJ was designed using a costeffective trench side-wall implantation and SiO2 refill fabrication method and evaluated through TCAD simulations. The optimized semi-SJ MOSFET designs, reduces Ron by 19% and increases BV by 500 V compared with the planar MOSFET, while maintaining a comparable reverse recovery charge ( QRR ). The proposed semi-SJ design demonstrated the best RON×QRR figure of merit (17.8 mΩ·μC), outperforming the conventional planar MOSFET design ( 19.7 mΩ·μC ).

Introduction

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The 4H−SiC MOSFETs are widely adopted in industrial and automotive applications due to their superior efficiency and performance compared with Si IGBTs [1]. In the 3.3 kV voltage class, further improvements in device performance can be achieved through Superjunction (SJ) technology, which lowers on-state resistance (Ron) while enabling higher breakdown voltage (BV) [2]. However, the introduction of alternating n - and p -pillars increases output capacitance [3-5], make it essential to assess SJ devices not only in terms of static performance but also dynamic behaviour such as reverse recovery.
In inverter and converter systems, the intrinsic body diode of the MOSFET can replace an external freewheeling diode, offering system-level cost benefits [6,7]. A drawback, however, is that thirdquadrant operation of the body diode may induce bipolar degradation, such as stacking fault expansion driven by electron-hole recombination [8]. While recent advances in 1.2 kV and 3.3 kV devices have helped mitigate this concern [6], reverse recovery remains an important performance factor. Schottky diodes have been shown to suppress reverse recovery effectively, with reductions in turn-on losses of up to 45% reported for the 3.3 kV class [7], but this improvement comes at the expense of an additional device component. Moreover, experimental studies on trench MOSFETs with full and semi-SJ structures, fabricated through multi-epitaxy and p-implantation, indicate that SJ concepts can increase reverse recovery charge ( QRR ) compared to conventional non-SJ devices [4,5].
This work investigates the body diode and reverse recovery behavior of a 3.3 kV semi-SJ MOSFET compared with a conventional planar MOSFET using TCAD. The proposed device is designed using a cost-effective trench etching and side-wall implantation method, without requiring multiple epitaxy steps and with only two additional implantation schedules compared with the planar process [2,9].

Design Description

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[picture]

Fig. 1. Schematic of the (a) planar and (b) semi-SJ designs; (c) SEM image of the fabricated planar MOSFET active area.

Fig. 1. Schematic of the (a) planar and (b) semi-SJ designs; (c) SEM image of the fabricated planar MOSFET active area.

The proposed semi-SJ design (Fig. 1 (b)) is based on the fabricated 3.3 kV planar MOSFET, with dimensions and SEM of the active area shown in Fig. 1 (a) and (c). The planar MOSFET features a 32.5μ m epitaxial layer doped at 3×1015 cm−3 and a simulated 1.5μ m JFET region at 8×1015 cm−3. All structures feature a 6.6μ m cell pitch, 50 nm gate-oxide, and 0.7μ m channel length (Lch). The JFET width (Wsfet) is 1.8μ m in the planar device and adjusted to 1.4μ m in both semi-SJ designs. Additionally, the deep trench opening and depth are 2.8μ m and 6.9μ m, incorporating 0.25μ m sidewall and 0.5μ m bottom p-implants. The trench dimensions are based on the process developed in [9] with the tilt angle ( θ) of 6∘. The semi-SJ also includes an n-type charge-balance layer ( NCB ), varied between 2×1016 cm−3 and 3×1016 cm−3 as an optimization parameter.

On-State and Off-State Performance

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[picture]

Fig. 2. (a) Measured and simulated on-state characteristics of the conventional planar MOSFET; simulated planar and semi-SJ MOSFET: (b) on-state comparison and (c) transfer comparison.

Fig. 2. (a) Measured and simulated on-state characteristics of the conventional planar MOSFET; simulated planar and semi-SJ MOSFET: (b) on-state comparison and (c) transfer comparison.

The room-temperature on-state characteristics of the conventional 3.3 kV planar MOSFET are shown in Fig. 2 (a) for VGS =18 V and 15 V , with the simulated TCAD results. The conventional planar device achieves Ron of 64 mΩ (measured) and 57 mΩ (simulated). Compared to the simulated planar MOSFET, the semi-SJ designs achieve Ron of 46 mΩ(−19%) and 44 mΩ(−23%) for NCB=2×1016 cm−3 and 3×1016 cm−3, respectively, as shown in Fig. 2 (b). All simulated designs were calibrated to a

[picture]

Fig. 3. (a) Side-wall p-type doping concentration versus BV; EF distribution at 3.3 kV : (b) planar, (c) semi-SJ ( NCB=2×1016 cm−3,5×1017 cm−3 side-wall), (d) semi-SJ ( NCB=3×1016 cm−3, 7×1017 cm−3 side-wall).

Fig. 3. (a) Side-wall p-type doping concentration versus BV; EF distribution at 3.3 kV : (b) planar, (c) semi-SJ ( N C B = 2 × 10 16 c m − 3 , 5 × 10 17 c m − 3 side-wall), (d) semi-SJ ( N C B = 3 × 10 16 c m − 3 , 7 × 10 17 c m − 3 side-wall).

measured threshold voltage ( VTH ) of 3 V at 9 mA , with transfer characteristics shown in Fig. 2 (c). The side-wall implantation doping concentration as a function of breakdown voltage (BV) for the semi-SJ designs is shown in Fig. 3 (a). The simulated off-state performance of the conventional planar MOSFET is 4 kV , which is denoted as the dashed line in Fig. 3 (a). In comparison, the semi-SJ design with the NCB=2×1016 cm−3 achieves BV of 4.5 kV when the side-wall doping concentration is 5×1017 cm−3, while the design with NCB=3×1016 cm−3 achieves BV of 4.4 kV when the side-wall doping concentration is 7×1017 cm−3. Additionally, the semi-SJ MOSFET with NCB=2×1016 cm−3 maintains BV above 4 kV over a wider implantation range ( 4×1017−7×1017 cm−3 ), while the NCB=3×1016 cm−3 design has a slightly narrower implantation window ( 6×1017−8×1017 cm−3 ).
The electric field (EF) distributions of planar and semi-SJ designs are shown in Fig. 3(b)-(d). The trench angle required for side-wall implantation in semi-SJ designs introduces a charge imbalance above and below the trench midpoint [2,10]. Therefore, as illustrated in Fig. 3 (c) and (d), the n-type layer becomes charge overcompensated below the trench midpoint, shifting the maximum EF toward the trench-bottom p-type implant, with the effect becoming stronger at higher n-top doping concentrations ( NCB=3×1016 cm−3 ).

Third-Quadrant Performance

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The measured reverse conduction of the fabricated 3.3 kV planar MOSFET is shown in Fig. 4 (a) for Vgs values between -5 V and 0 V . As reported in [1,11], third-quadrant conduction below Vth is a combination of the MOS channel, the body diode, and the parasitic BJT current components. At Vds =−3 V and VGS=0 V, the lower conduction voltage drop indicates that current is primarily unipolar, enabled by the body effect and positive fixed charge ( QF ) at the SiC/SiO2 interface. This is confirmed by the current distribution in Fig. 4 (b) and (d) simulated with the QF=7×1011 cm−2, which shows high electron density conduction through the channel. At VDS=−3 V and VGS=−5 V, the simulated electron and hole distribution in Fig. 4 (c) and (e) shows that electron current through the parasitic npn BJT dominates, while a smaller hole component is injected at the body diode junction to provide the base drive (see Fig. 4 (c)) [11].
The simulated reverse conduction at VGS=0 V and -5 V for the semi-SJ structures, compared with the planar benchmark, are shown in Fig. 5 (a) and (b). At VGS=−5 V, the semi-SJ device exhibits

[picture]

Fig. 4. (a) Measured body diode reverse conduction characteristics; hole current density (VDS=−3 V) : (b) VGS=−5 V and (c) VGS=0 V; electron current density (VDS=−3 V) : (d)VGS=−5 V and (e) VGS=0 V.

Fig. 4. (a) Measured body diode reverse conduction characteristics; hole current density ( V D S = − 3 V ) : (b) V G S = − 5 V and (c) V G S = 0 V ; electron current density ( V D S = − 3 V ) : ( d ) V G S = − 5 V and (e) V G S = 0 V .

[picture]

Fig. 5. Simulated third-quadrant characteristics at VGS : (a) 0 V , (b) -5 V ; Hole density distribution at VDS=−4 V and VGS=−5 V : (c) planar, (d) semi-SJ ( NCB=2×1016 cm−3 ), (e) semi-SJ (NCB=3×1016 cm−3).

Fig. 5. Simulated third-quadrant characteristics at V G S : (a) 0 V , (b) -5 V ; Hole density distribution at V D S = − 4 V and V G S = − 5 V : (c) planar, (d) semi-SJ ( N C B = 2 × 10 16 c m − 3 ), (e) semi-SJ ( N C B = 3 × 10 16 c m − 3 ) .

the highest forward voltage (VF) drop, reaching 4.3 V at 50 A , compared with 3.7 V for the planar device. A similar trend is observed at higher current densities when VGS=0 V. The reduced conductivity modulation in the semi-SJ design is confirmed by the simulated hole current density distributions in Fig. 5 (c-e), where significantly fewer holes are injected into the drift region compared to the planar MOSFET. Reducing the NCB to 2×1016 cm−3 improves reverse conduction, lowering the VF to 4.1 V at 50 A and potentially improved reverse recovery performance.
Body Diode Reverse Recovery Performance

To evaluate the dynamic performance of the

[picture]

Fig. 6. Simulated output capacitance (Coss) of planar, semi-SJ and full-SJ designs.

Fig. 6. Simulated output capacitance (Coss) of planar, semi-SJ and full-SJ designs.

behavior.
The body diode performance was simulated using a double-pulse test at 1.7 kV and the load inductance of VDS=400 V, with results shown in Fig. 7 (a) and (b). Note, that parasitic source and drain inductances were set as 5 nH and 10 nH , respectively. The high-side switch was biased at p−n and the gate resistance of the low-side switch ( VDs=50 V ) was set to NCB=2×1016 cm−3 and 3×1016 cm−3. The simulated diode forward current ( 68μH ) was fixed at 27 A .

[picture]

Fig. 7. Simulated planar and semi-SJ MOSFET reverse recovery current at: (a) VGS=−5 V, RG 5 V and (b) 15Ω.

Fig. 7. Simulated planar and semi-SJ MOSFET reverse recovery current at: (a) V G S = − 5 V , R G 5 V and (b) 15 Ω .

Table 1. Reverse recovery characteristic of planar and semi-SJ designs.

Parameter: | Planar | Semi-SJ (NCB=2×10¹⁶ cm⁻³) | Semi-SJ (NCB=3×10¹⁶ cm⁻³)
| RG=15Ω | RG=5Ω | RG=15Ω | RG=5Ω | RG=15Ω | RG=5Ω
tRR (ns) | 63 | 37.3 | 42 | 31.4 | 42 | 32.7
QRR (nC) | 357 | 346 | 417 | 386 | 507 | 463
IRRM (A) | 9.6 | 13.8 | 16.1 | 19.6 | 20.2 | 23.3
dIRR/dt (kA/μs) | 0.25 | 1.1 | 1.1 | 2.6 | 1.8 | 3.5
ESW (μJ) | 512 | 437 | 577 | 523 | 730 | 648

The summary and comparison of switching characteristics can be seen in Table 1, where the SemiSJ shows a comparable reverse recovery charge ( 5Ω ) compared to a conventional planar MOSFET. For IF, the planar device results in the RG=15Ω of 346 nC , while the semi-SJ with the VGS= shows the RG=5Ω, VGS=−5 V of 386 nC , corresponding to a QRR increase. Increasing the RG=5Ω concentration to QRR in the Semi-SJ structure leads to a NCB=2×1016cm−3 increase in QRR compared to the planar device.
Additionally, the semi-SJ designs show higher peak reverse current and steeper dIRR/dt during recovery, due to increased stored charge and capacitance. These results are consistent with previous reports on SiC SJ MOSFETs [4,5], where the increased pn-junction area increases Coss (see Fig. 6) and increases the reverse recovery losses.
Based on the 10% figure of merit with NCB switching results, the semi-SJ with 3×1016 cm−3 offers a balanced trade-off 30%, outperforming the planar MOSFET design QRR(463nC) and offering lower fabrication cost compared to other SJ technologies. The comparison between static and dynamic performance of all investigated devices is summarized in Table 2.

Table 2. Static and dynamic performance comparison between conventional and semi-SJ designs.

Parameter: | Planar | Semi-SJ (NCB=2×10¹⁶ cm⁻³) | Semi-SJ (NCB=3×10¹⁶ cm⁻³)
RON (mΩ) | 57 | 46 [- 19 %] | 44 [- 23 %]
BV (kV) | 4 | 4.5 [+ 12.5 %] | 4.4 [+ 10 %]
Implantation window (cm⁻³) | - | 4-7×10¹⁷ | 6-8×10¹⁷
RON× QRR (mΩ.μC) | 19.7 | 17.8 | 20.3

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.95.pdf

This work investigated the third-quadrant conduction and reverse recovery behavior of a 3.3 kV semiSJ design, with static characteristics benchmarked against a fabricated planar MOSFET. The optimized semi-SJ device achieved a balanced trade-off between conduction and switching performance. With an n-top ( RON×QRR ) doping concentration of RG=5Ω, the optimized semi-SJ reduced Ron by NCB=2×1016cm−3 and increased the maximum BV by 500 V compared with the planar MOSFET. This design also achieved the best (17.8 mΩ·μC) figure of merit at (19.7 mΩ·μC), outperforming the planar device with the Ron NCB of 2×1016 cm−3. These results demonstrate that semi-SJ devices, designed with a cost-effective side-wall implantation fabrication method, provide a promising solution for high-voltage SiC MOSFETs with competitive static and body diode reverse recovery characteristics.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.95.pdf

R. Zhang et al., "Third Quadrant Conduction Loss of 19% SiC MOSFETs: Impact of Gate Bias Control," in IEEE Transactions on Power Electronics, vol. 36, no. 2, pp. 2033-2043, Feb. 2021.

M. Boccarossa et al., "A 3.3 kV SiC Semi-Superjunction MOSFET with Trench Sidewall Implantations," Micromachines, vol. 16, no. 2, p. 188, 2025.

G. W. C. Baker et al., "Optimization of 1700-V 4H-SiC Semi-Superjunction Schottky Rectifiers With Implanted P-Pillars for Practical Realization," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1924-1930, April 2022.

S. Harada et al., "First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2018, pp. 8.2.1-8.2.4.

M. Baba et al., "Ultra-Low Specific on-Resistance Achieved in 3.3 kV -Class SiC Superjunction MOSFET," 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, 2021, pp. 83-86.

J. Qian et al., "An investigation of body diode reliability in commercial 1.2 kV SiC power MOSFETs with planar and trench structures,"Micromachines, vol. 15, no. 2, p. 177, 2024.

M. A. Karout et al., "Impact of Diode Technology on the Switching Performance of 3.3 kV SiC MOSFETs," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 108-111.

W. Cao et al., "SiC superjunction MOSFET with Schottky diode for improving short-circuit and reverse recovery ruggedness," Micro and Nanostructures, vol. 191, p. 207847, 2024.

Q. Z. Cao et al., "Device fabrication of SiC superjunction trench MOSFETs with Schottky diode using ICP and RIE processes," Materials Science Forum, vol. 1159, pp. 21-29, Sep. 2025.

K. Melnyk et al., " 3.3 kV 4H-SiC Trench Semi-Superjunction Schottky Diode With Improved ON-State Resistance," in IEEE Transactions on Electron Devices, vol. 71, no. 9, pp. 55735580, Sept. 2024.

Y. Chen et al., "Novel Cell-Level Insights into Third Quadrant Current Paths of Power SiC MOSFET," 2024 IEEE Energy Conversion Congress and Exposition (ECCE), Phoenix, AZ, USA, 2024, pp. 6754-6758.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 103-110

doi: 10.4028/p-bGig86

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-08

Accepted:
2026-01-31

Online:
2026-05-21

An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

Giorgian Borca-Tasciuc 1,a* and T. Paul Chow 1, b

¹Rensselaer Polytechnic Institute, Troy, New York 12180, U.S.A.

a*borcag2@rpi.edu, b chowt@rpi.edu

Keywords: analytical modeling, reverse recovery, P-i-N diodes.

Abstract

We generalize a recent Si P-i-N reverse-recovery (RR) model to more accurately capture 4H-SiC diode behavior by adding deep-acceptor-limited anode injection, strong recombination (due to >100 x shorter optimized high-level lifetimes compared to Si ), and improved modeling of the depletion layer dynamics. Closed-form expressions for the growth of the depletion layer are derived, enabling analytical estimates for QRR, tRR, and JPR. The model is validated against Sentaurus RR simulations of optimized 4H-SiC P-i-N diodes spanning BV =6−17kV and di /dt=10 A/μs−10kA/μs, achieving an average reduction in error of >90% for estimations of key switching performance parameters (QRR,tRR,JPR). By correctly capturing the dependence of QRR on di/dt, the model enables better estimates for the high-level lifetime ( τHL ) directly from the RR waveforms. The differential form enables straightforward utilization of the model to analyze non-idealized RR waveforms. Overall, the generalized model reveals a more favorable QRR−VF trade-off than implied by the unmodified Si model and improves first-order device optimization prior to full design.

Introduction

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Bipolar P-i-N junction diodes have a distinct BV-VF trade-off compared to unipolar Schottky diodes due to conductivity modulation, in which the concentration of mobile carriers in the drift region can be increased well beyond the background doping. 4H-SiC P-i-N diodes are expected to have a lower VF than 4H-SiC Schottky barrier diodes past 10 kV . Recent advancements in reducing the lifetimekilling Z1/2 defect and in suppressing the bipolar degradation phenomenon have eliminated some of the major impediments to realizing optimized 4H−SiCP−i−N diodes [1,2]. However, bipolar devices have a trade-off between the static and dynamic performance, as the on-state losses can be reduced at the expense of increasing the switching losses through an increase in QRR by increasing the degree of conductivity modulation. The total loss is minimized by trading off between the two losses. An analytical model allows a good first-order optimization of this trade-off before further refinement.
In [3], an analytical model is recently proposed to model the dynamics of SiP−i−N diode reverse recovery (RR) and estimate key switching performance parameters such as QRR, the snappiness factor tB/tA, and the reverse recovery time tRr. However, several material aspects of SiC limit the applicability of this model: (1) the necessity of using deep acceptors reduces the injection efficiency of the anode, and (2) carrier recombination significantly reduces QRR due to the >100x reduction in the optimized high-level lifetime compared to Si . We thus generalize the model in [3] in order to increase its applicability to include SiC. We have evaluated the improvement in our model by performing simulations and evaluating the reduction in error obtained by the new model compared to the model in [3], and obtained substantial improvements in accuracy. The model indicates (and simulations confirm) that 4H−SiCP−i−N diodes have an improved BV−VF trade-off than implied by the previous model. Our new model is expected to have applicability in enabling the design of competitive SiC P-i-N diodes and in improving the estimation of material parameters from the RR waveform.

Methodology

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On-State.

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Due to Aluminum being a deep-acceptor in 4H−SiC,<10% of electrically active acceptors are ionized at room temperature (RT). The space-charge neutrality equation can be used to determine the free hole concentration:

p+ND+−n−NA−=0

where:

p=NVexp−EF−EVkT,n=NCexp−EC−EFkT,NA−=NA1+gAexpEA−EFkT,ND+=ND1+gDexpEF−EDkT

An acceptable approximation of the solution to this transcendental equation for the hole-density in anode is given by:

p0P+=Nζ2(1+4NANζ−1)

where:

Nζ=NVexpEA−EVkT

Equivalent expressions can be obtained for the free electron concentration n0N+ in the cathode, with EA−EV replaced by EC−ED, and NA replaced by ND which will give satisfactory approximations if 100% donor activation cannot be assumed. Bandgap narrowing is modeled by assuming that:

EA−EV=ΔEA0−αNA13

The parameter of interest is average carrier concentration na in the drift region. Using [3], this can be written as:

JF=JSP+n(−d)2+2qnadτHL+JSN+n(+d)2JSP+=qDnP+p0P+LnP+tanh(WP+LnP+)JSN+=qDpN+n0N+LpN+tanh(WN+LpN+)

DnP+,DpN+ are the diffusion coefficients in the anode and cathode; LnP+,LpN+ are the diffusion lengths in the anode and cathode; and WP,WN are the thicknesses of the anode and cathode, respectively. The thickness and high-level lifetime of the drift region is given as t=2d and τHL. n(−d) and n(+d) are the plasma concentration at the anode and cathode, and are given by the catenary carrier distribution:

n(x)=τHL2qLa(cosh(xLa)sinh(dLa)−Bsinh(xLa)cosh(dLa))

Where La=DaτHL is the ambipolar diffusion length in the drift region, and B=μn−μpμn+μp.

Thus, given the forward current density and the structural and material parameters of the P−i−N diode, the plasma carrier concentration na can be derived.

[picture]

Fig. 1. Effect of aluminum acceptor level on (a) hole concentration and (b) anode injection efficiency.

Fig. 1. Effect of aluminum acceptor level on (a) hole concentration and (b) anode injection efficiency.

[picture]

Fig. 2. Schematic representation of the drift region and modeled parameters during reverse recovery.

Fig. 2. Schematic representation of the drift region and modeled parameters during reverse recovery.

Dynamic Switching.

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Figure 2 gives a schematic overview of the parameters solved by the dynamic switching equations. During the RR, holes are extracted at the anode and electrons are extracted at the cathode. The growth of the depletion region at the P+side is due to electrons in the plasma moving towards the cathode, leaving behind a depletion layer in which the holes are extracted towards the anode at saturation velocity. Given the small nature of dn(x)dx in the plasma, it can be assumed that electrons in the plasma are driven towards the cathode by drift. As the total current is given by:

J=JF−at=q(μn+μp)n(x,t)E

We can approximate the electric field by assuming n(x,t)≈na(t) where na(t) is the average carrier density of the plasma at time t and thus derive:

E=JF−atqna(t)(μn+μp)

Thus, the electron current component, Jn=qμnnE becomes:

Jn=μnμn+μp(JF−at)n(x,t)na(t)

Again, assuming n(x,t)≈na(t), this simplifies to:

Jn=μnμn+μp(JF−at)

We now apply a charge control approach to derive dxndt. During an infinitesimal time step, the charge extracted at the boundary of the P+/n - depletion region with the plasma is:

Qn=Jndt=μnμn+μp(JF−at)dt

During this infinitesimal time step, the depletion region grew dxn. Thus, the charge removed, assuming n(x,t)≈na(t) is:

Qn=dxpqna(t)

This yields, for dxp/dt :

dxpdt=−μnμn+μpJF−atqna(t)

An acceptable approximation for na(t), the average plasma concentration within the region that remains conductivity-modulated, can be made by assuming that na(t) only changes through recombination. Thus, na(t)=nae−tτHL, where na is simply the static value of the average carrier concentration of the plasma in the on-state. This yields the final formula for the growth of the depletion region at the P+/n−region:

dxpdt=−μnμn+μpJF−atqnae−tτHL

Similar arguments made for the N+/n−depletion region yield:

dxndt=−μpμn+μpJF−atqnae−tτHL

[picture]

Fig. 3. Simulated depletion layer formation with μn/μp=2.5 along with model predictions.

Fig. 3. Simulated depletion layer formation with μ n / μ p = 2.5 along with model predictions.

An interesting observation is that this model predicts that the ratio of the depletion region widths xp/xn asymptotically approaches μn/μp, regardless of whether the diode is a P+−n−N+diode or a P+-p−N+diode. This effect can be seen in Figure 3, where RR was simulated with an exaggerated μn/μp to demonstrate the two-sided depletion formation.
The above-derived differential equations have the solution:

xp(t)=CpτHL[(JF+aτHL)(exp(t1,pτHL)−exp(tτHL))−a(t1,pexp(t1,pτHL)−texptτHL)],t>t1,pxn(t)=CnτHL[(JF+aτHL)(exp(t1,nτHL)−exp(tτHL))−a(t1,nexp(t1,nτHL)−texptτHL)],t>t1,n

Where Cp=μn(μn+μp)qna and Cn=μp(μn+μp)qna. The variables t1,p and t1,n denote when the depletion regions start growing at the P+/n−side and the N+/n−side, respectively. At t=t1,p, there is no voltage across the P+/n−junction, and equivalently for t=t1,n. Electric-field dependent mobilities, μn(E) and μp(E) can be used in the differential equations if the carriers in the plasma begin approaching their saturation velocity during the switching.

We now find the time t1,p and t1,n when the depletion region begins growing on each side. At time t1,p, the carrier concentration at the anode/drift-region boundary is 0 . Let b be the distance from the anode where the on-state equilibrium carrier concentration remains undisturbed. Then, at time t1,p current right at the anode is driven purely by diffusion. Using these assumptions and the previous derivations result in the following equations for the hole current exiting the anode at time t1,p, where γ=dndx|x=−d :

Jp(t1,p)=μpμn+μp(JF−at1,p)=qDPdndx≈qDpn(−d)−γbb

The total charge removed, utilizing the current zero-crossing t0=JFa and approximating the removed charge using a triangle, is:

Q1,P=∫t0t1,p(JF−at)dt=12bqn(−d)

Thus, two equations are derived for two unknowns, t1,p and b. Combining the two equations yield a rather unwieldly cubic polynomial, whose positive real root is the time the voltage across the P+/n− junction is equal to zero. Equivalent arguments yield t1,n. We utilize t1=min(t1,p,t1,n), as the moment the depletion layer begins growing on one side, the voltage will promptly cross zero.
We now have all the terms to derive a straightforward expression for the voltage supported across the P−i−N diode during the RR:

VAK(t)=VP(t)+VN(t)

Where VP(t) is the voltage supported across the P+/n−junction and VN(t) is the voltage supported across the N+/n−junction. Using Poisson's equation, VP(t) and VN(t) can be straightforwardly derived from xn(t) and xp(t) :

VP(t)=12ϵs(at−JFvsat,p+qND)xp(t)2VN(t)=12ϵs(at−JFvsat,n+qND)xn(t)2

The peak reverse current is obtained by solving for VAK(t2)=VS. To model the final phase of the RR , consider the charge remaining in the drift region once JPR is reached:

Qr≈qnaexp(−tτHL)(2d−xn(t2)−xp(t2)−hn−hp)

Here, hp and hn are the slopes of the carrier profile at the boundary of the P+/n−depletion region of the plasma, and at the boundary of the N+/n−depletion region and the plasma, respectively. The expression for these are derived from the diffusion current at the boundary of the plasma at time t2 :

Jn=μnμn+μpJPR=qDndndx≈qDnnaexp−tτHLhn

The expression for hp is equivalent. At this point, we assume that recombination is negligible in extracting the remaining charge. This is a justifiable assumption as once the large peak reverse current is reached, it becomes more efficient at removing charge than recombination. Our simulations confirm this assumption. A tail-like decay is still seen in the final phase of inductive switching, but this is due to the decay of the diffusion gradient as carriers exit the conductivity-modulated region, not due to carrier recombination. With this assumption in hand, we can write:

12JPRtb=Qr

And thus, the total reverse recovery charge, QRR can be written as:

QRR=12(t2+tb−t0)JPR

The expression for tb assumes a linear decay of the current from JPR to 0 . A satisfactory waveform for the current decay can be derived by assuming for t>t2 :

J(t)=JPRexp(−t−t2τb),t>t2

The current-decay time constant τb, capturing the effects of the decay of the gradients driving diffusion, can be defined using:

∫t2∞J(t)=Qr

[picture]

Fig. 4. Errors in model predictions for (a) QRR, (b) JPR, (c) tRR, and (d) t1. Error displayed in logscale.

Fig. 4. Errors in model predictions for (a) Q R R , (b) J P R , (c) t R R , and (d) t 1 . Error displayed in logscale.

Model Verification

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

TCAD Sentaurus is used to perform simulations in order to verify the model. Optimized 4H−SiC p-i-n diodes are designed with differing mid-region thicknesses varying from 50μ m to 150μ m by 25μ m increments, yielding breakdown voltages (BV) between 6 kV and 17 kV . Inductive-load RR simulations are performed on the optimized diodes, varying the ramp rate between 10 A/μs and 10kA/μs and the reverse voltage from 1/8 to 1/2 the BV. The key switching parameters ( QRR,sp,JPR, tRR,t1 ) are extracted and quantitatively compared with the model predictions using the prediction error (xtrue −xpredicted xtrue ). The mean absolute percentage error (MAPE) is used to aggregate the errors across the different switching reverse voltage. The model described in [3] is used as a baseline.
As is visible in Figure 3, the model makes substantial improvements over the Si RR model. Both JPR and QRR are accurate always accurate within 20% across the 60 tested scenarios and are almost always within 10%. The average errors are 8.8% for QRR ( 94% reduction), 3.7% for JPR ( 93% reduction), 9.2% for tRR ( 84% reduction), and 5.3% for t1 ( 90% reduction). This testifies to the degree of relative as well as absolute accuracy of the new model. Figure 4 provides a qualitative comparison of the new model, the simulation results, and the model described in [3].
The increase in the error of tRR with increasing ramp rate arises from the increased role of recombination in removing the remaining charge ( Qr ) in the final phase.

[picture]

Fi.
mulated waveforms vs model predictions.

Figure 5. Fi. mulated waveforms vs model predictions.

The new model can be used to make accurate QRR−VF curves, as is seen in Figure 6(a). Usage of the model in [3] provides an excessively pessimistic Qrr. Thus, the performance of the 4H−SiCP−i−N diode is significantly better than predicted by [3]. Figure 7(b) demonstrates that the model can also reproduce the dependence of QRR  on di/dt. The same τHL extracted in [4] using the slope of the IF−QRR  curve also gives a reasonable fit for the QRR−di/dt curve. As current waveforms during switching often deviate from the idealized form assumed for modeling, the differential forms can be used with J(t) substituting for JF−at when using the model for device characterization.

(a)

(b)

Table 1. Important parameters utilized in RR simulations.

EA0 | α | NA | ND | EC-ED | μn,max | μp,max
0.265eV[5] | 3.6E-8eV/cm | 1E19cm⁻³ | 1E19cm⁻³ | 0.1eV | 950cm²/V-s | 125cm²/V-s

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

We generalized the classical Si reverse-recovery framework presented in [3] by including reduced anode injection efficiency due to utilization of deep acceptors, recombination during RR, and twosided depletion growth. We utilize the model to predict RR in optimized 4H−SiCP−i−N diodes, deriving closed-form relations for depletion growth and analytical estimates of QRR, tRR, and JPR that match Sentaurus RR across BV=6−17kV and di/dt=10 A/μs−10kA/μs, reducing errors by >90% versus the unmodified Si model. The model predicts an improved Qrr−VF trade-off than the previous model, extending the regions in which 4H−SiCP−i−N diodes become competitive. The model reproduces the dependence of QRR on di/dt seen in empirical RR measurements. The differential form of the model enables utilization of the model with a measured (non-idealized) RR current waveform to analyze the stored charge in the drift region. Thus, the model expands the viable design space for SiC P-i-N diodes by guiding τHL and drift-layer sizing against VF−QRR and can be utilized to obtain additional insight into measured RR waveforms, accelerating device design and characterization.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

M. Kato, O. Watanabe, T. Mii, H. Sakane, S. Harada, "Suppression of stacking-fault expansion in 4H−SiC PiN diodes using proton implantation to solve bipolar degradation," Sci. Rep. 12 (2022) 18790.

T. Okuda, G. Alfieri, T. Kimoto, J. Suda, "Oxidation-induced majority and minority carrier traps in n- and p-type 4H-SiC," Appl. Phys. Express 8 (2015) 111301.

B.J. Baliga, Fundamentals of Power Semiconductor Devices, 2nd ed., Springer, Cham, 2019.

K. Nakayama, S. Ogata, T. Hayashi, T. Hemmi, A. Tanaka, T. Izumi, K. Asano, D. Okamoto, Y. Tanaka, T. Mizushima, M. Yoshikawa, H. Fujisawa, K. Takenaka, M. Takei, Y. Yonezawa, K. Fukuda, H. Okumura, "High voltage and fast switching reverse recovery characteristics of 4H-SiC PiN diode," Mater. Sci. Forum 778-780 (2014) 841-844.

A. Koizumi, J. Suda, T. Kimoto, "Temperature and doping dependencies of electrical properties in Al-doped 4H-SiC epitaxial layers," J. Appl. Phys. 106 (2009) 013716.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 111-118

doi: 10.4028/p-Xxkc5I

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-08

Accepted:
2026-02-26

Online:
2026-05-21

Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

Giorgian Borca-Tasciuc 1,a*, Reza Ghandi 2, b, Collin W. Hitchcock 2,c and Tat-Sing Paul Chow 1, d

¹Rensselaer Polytechnic Institute, Troy, New York 12180, U.S.A

2 GE Aerospace Research, Niskayuna, New York 12309, U.S.A.

ab  borcag2@rpi.edu, b  ghandi@ge.com, c  collin.hitchcock@ge.com, d  chowt@rpi.edu

Keywords: Reverse Recovery, Dynamic Breakdown, Charge-Balance, Superjunction

Abstract

We report an anomalous reverse-recovery (RR) of the body diode in a 3.3kV4H−SiC superjunction (SJ) DMOSFET: at 77 K , QRR,sp increases by 1.4×−3.5× versus room temperature and 5× versus 195 K , and JPR increases by >2×, while trRR changes by only <30 ns. A clear dependence of QRR,sp on the ramp rate at 77 K indicates the QRR,sp is not due to additional depletion charge. Currentcontrolled negative resistance (CCNR) is also observed solely for the SJ body diode at 77 K . The voltage waveforms strongly suggest the additional QRR,sp is due to dynamic breakdown of the SJ due to transient charge imbalance of the pillars caused by delayed hole emissions of the deep acceptors. The anomalous behavior is qualitatively reproduced in simulation. We also benchmark a 3.3 kV Charge Balance (CB) 4H-SiC DMOSFET along with the SJ device from 77-423 K using an inductive double-pulse test. For T>77 K the switching for both devices is dominated by the depletion capacitance (weak QRR,sp dependence on the ramp rate): the SJ device turns off faster ( tRR=0.3−0.8× CB ), is snappier ( tB/tA=0.23−0.56×CB ), and shows larger JPR(1.8−2.8×CB) while recovering less charge ( QRR,sp=0.4−0.8×CB ). The CB device shows the expected increase of QRR,sp with temperature and only modest tRR temperature variation. Overall, the CB device provides softer, predictable RR without a cryogenic anomaly, whereas SJ delivers the shortest trRR above 77 K but exhibits the 77 K anomalous increase and is consistently snappier.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

The 4H−SiC power DMOSFET has emerged as a competitive alternative to Si equivalents due to the wide bandgap of 4H−SiC enabling thinner drift regions and higher doping for the same breakdown voltage, leading to a dramatic reduction in Ron,sp. While a wide bandgap enables the large critical electric field that makes 4H−SiC competitive for unipolar devices, it also leads to a higher on-state voltage for bipolar devices, including the 4H−SiC DMOSFET integral body diode. Additionally, the 4H-SiC DMOSFET body diode exhibits certain undesirable switching characteristics. While demonstrating a much-faster reverse recovery (RR) than Si body diodes, they tend to exhibit increased snappiness which can lead to large voltage overshoots and increased power loss [1]. Thus, the antiparallel body diode inherently present in all DMOSFETs is often shorted by a Schottky diode in switching applications of the 4H−SiC DMOSFET, increasing costs.
Charge balance (CB) and superjunction (SJ) drift layers improve the on-state performance of the 4 H SiC DMOSFET by improving the trade-off between BV and Ron,sp [2,3]. However, the improved onstate performance enabled by the CB and SJ drift-layer can be counteracted by degraded RR performance, as observed in the Si SJ integral diode, where excessive oscillations are caused by rapid changes of the SJ capacitance with voltage [4]. Knowledge of the RR characteristics is therefore required in order to evaluate the trade-offs of different power MOSFETs in circuit applications.
This study evaluates and compares the RR performance of the body diodes of GE (General Electric) 3.3kV4H−SiCCB and SJ DMOSFETS, from liquid nitrogen temperatures up to 423 K . The static performance of the DMOSFETs have previously been characterized in [5]. An anomalous RR is consistently observed for the SJ DMOSFET at 77 K . A mechanism for the observed anomalous RR is hypothesized and simulated.
Methodology

[picture]

Fig. 1. Full-Cell Cross-Section of CB and SJ Vertical DMOSFETs

Fig. 1. Full-Cell Cross-Section of CB and SJ Vertical DMOSFETs

Devices and structures. Inductive RR measurements are performed on GE 3.3kV4H−SiC chargebalance (CB) and superjunction (SJ) DMOSFETs packaged in TO-247. Full-cell cross-sections for the conventional (Conv), CB, and SJ vertical DMOSFETs are shown in Figure 1. The CB architecture is implemented through intermittent shallow Al implants interleaved with the growth of a 12μ mn type epitaxial layer ( 1×1016 cm−3 ) to form buried charge-balance regions that act as electric-field dividers, enabling higher drift-layer doping at a fixed breakdown voltage. Intermittent vertical P-type "bus" pillars ( 12μ m depth) are realized via high-energy Al implantation ( >20MeV ) to tie the buried CB layers to the P+source/anode for hole supply. The SJ device employs alternating vertical P- and N-type pillars ( 5μ m pillar width) formed with the same high-energy implantation approach; pillar dopings are 1×1016 cm−3. Both CB and SJ stacks are scalable to higher voltage ratings. For the 3.3 kV DMOSFETs studied here, the drift region thickness is 24μ m.

[picture]

Fig. 2. Schematic reverse recovery switching waveforms and the associated performance parameters [6]

Fig. 2. Schematic reverse recovery switching waveforms and the associated performance parameters [6]

Temperature control. Cryogenic data are taken in liquid nitrogen ( 77 K ) and in a dry-ice/isopropanol bath ( 195 K ). High-temperature (HT) measurements use a temperature-controlled hot plate at 423 K (150∘C). Devices are soaked at the setpoint prior to testing to ensure thermal equilibrium.

Inductive reverse-recovery setup. RR of the body diode is characterized with a standard inductive double-pulse circuit. An 18 mH inductor is used as the load. The gate and source of the 4H−SiCSJ or CB DMOSFET are shorted and the body diode is used as the freewheeling diode. The RR waveform is measured at the start of the second pulse. Duty cycles of <1% are used to minimize device selfheating. Given the differing device areas, a current density ( JF=50 A/cm2 ) is targeted. The pulse width is set in order to achieve the target JF. The ramping rate ( di/dt ) is varied by varying the external gate resistance between 0Ω,50Ω, and 100Ω of the bottom transistor. Lead lengths are minimized in order to minimize parasitic inductance. Switching parameters are extracted according to Figure 2.

Experiments and Results

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

[picture]

Fig. 3. Sample RR Current Waveforms for 4H−SiCSJ(a) and CB (b) body diodes.

Fig. 3. Sample RR Current Waveforms for 4 H − S i C S J ( a ) and CB (b) body diodes.

Switching Characteristics. Excluding the SJ cryogenic anomaly at 77 K , both CB and SJ body diodes exhibit capacitance-dominated reverse recovery over 77 K−423 K and VR=0.5−1kV at JF=50Acm−2.QRR,sp has only a weak dependence on dJ/dt (Figure 4a), consistent with conventional 4HSiC body diodes where an implantation-damage "tail" near the junction limits the lifetime and causes minority carriers to recombine before they can be extracted, leaving the depletion charge extraction to dominate the RR waveform [1,7]. In this regime the 4H-SiC SJ body diode does not exhibit the excessive oscillations reported for the Si SJ body diode [4]. The fast minority carrier recombination in the damage layer of the implanted pillars suppresses the pre-depletion current build-up that produces the oscillations due to a large di/dt once the pillars pinch off. This is clearly seen in Figure 10 as the SJ begins supporting significant voltage only 10−20 ns after the current-zero crossing, indicating the current almost immediately consists of extracted depletion charge. Consistent with increasing minority carrier lifetime with temperature, Figure 4 b shows that the CB diode demonstrates the expected increasing QRR,sp with temperature, whereas the temperature trend of the SJ diode remains relatively flat, indicating that the switching remains capacitance dominated even at higher temperatures. A minority carrier charge extraction component begins to be detectable for the CB diode at 423 K , as indicated by the slight positive slope of QRR,sp vs dJ/dt at 423 K . Finally, the best snappiness characteristics for both diodes is seen at room temperature (Figure 7).

Comparison. Above 77 K , the SJ device generally exhibits faster turn-off, with the SJ exhibiting a tRR0.3x−0.8x that of the CB (Figure 9). The larger tRR of the CB device is expected due to increased resistance from the P -bus tying the charge sheet layers together introducing a larger RC time constant. As expected, the SJ is consistently snappier than the CB device, with a tB/tA of about 0.23x−0.56x that of the CB device. This is expected as the pillars must fully pinch-off before significant voltage can be supported, leading to a large drop in capacitance. The same mechanism drives the larger JPR(1.8x− 2.8 x ) of the SJ devices. Despite the larger JPR, the SJ exhibits a smaller QRR,sp than the CB, approximately 0.4x−0.8x that of the CB due to the smaller tRR. Interestingly, unlike the SJ , the CB
shows only minimal variation of switching time with temperature. These comparisons hold across the differing dJ/dt values caused by varying the external gate resistance of the bottom MOSFET in the DPT set-up.

[picture]

Fig. 4. QRR,sp dependence on dJ/dt (a) and temperature (b) for 4H−SiCCB and SJ Body Diode

Fig. 4. Q R R , s p dependence on d J / d t (a) and temperature (b) for 4 H − S i C C B and SJ Body Diode

Anomalous Cryogenic RR. At 77 K , the SJ body diode exhibits an anomalous increase in QRR,sp of 3.5 x compared to room temperature (RT) and 5 x relative 195 K . This behavior remains across multiple tested SJ devices. This is the opposite trend than what is expected from the well-documented trend of the minority carrier lifetime increasing with temperature. Thus, QRR,sp for the SJ becomes 1.9x-3.0x then that of the CB under matched conditions. The RR is no longer junction-capacitance dominated as QRR,sp has a clear dependence on the ramp rate in Figure 4. A larger slope of QRR,spvs reverse voltage at 77 K was also observed, indicating additional extracted charge besides the depletion charge. The increased QRR,sp remains clear even when JF is reduced to 20 A/cm2. In contrast, the SJ at 195 K shows an almost pure junction-capacitance dominated waveform, with QRR,sp remaining within 1% across the three different ramp rates. In Figure 8, a shallow voltage dip is consistently seen around ~200−300 V for the SJ at 77 K which is absent in the voltage waveforms taken at other temperatures.

[picture]

Fig. 5. Static I-V Characteristics for the 4H−SiCCB and SJ Body Diodes at various temperatures.

Fig. 5. Static I-V Characteristics for the 4 H − S i C C B and SJ Body Diodes at various temperatures.

CCNR Behavior in SJ. In the process of investigating the origin of the anomalous RR behavior of the SJ diode at 77 K , static I-V characterization was performed and are shown in Figure 5. A short pulse width ( 80μ s, for a duty cycle of 1.9% ) was used to minimize device self-heating. The turn-on knee increases at lower temperatures due to an increase in the junction barrier height as the Fermi level moves towards the band edges. Decreased acceptor ionization also induces a large series resistance in the diode. CCNR behavior is observed solely for the SJ device triggered at JF=50Acm−2. The current decay tail at the end of the second pulse is investigated to determine the operating point of the SJ device during switching and is shown in Figure 6a. No CCNR behavior is observed in the transient I-V of the SJ diode.

[picture]

Fig. 6. (a) The current decay curve through the 4H−SiCSJ body diode at the end of the second pulse (b) Extracted J-V characteristics from the current decay pulse.

Fig. 6. (a) The current decay curve through the 4 H − S i C S J body diode at the end of the second pulse (b) Extracted J-V characteristics from the current decay pulse.

Analysis and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

Switching Characteristics. The CB body diode addresses several shortcomings of the conventional 4H-SiC DMOSFET body diode while preserving the core advantage over Si. Turn-off remains capacitance-dominated and fast across the tested conditions ( tRR=~100−350 ns ), yet the recovery is markedly softer: at room temperature tB/tA can exceed 10 and, aside from 77 K , was greater than 1.4 in 9/9 RT scenarios tested and in 8/9 HT scenarios tested. The softer recovery reduces voltage overshoot and loss without sacrificing speed. Coupled with the CB drift region's improved Ron,spBV trade-off, this yields a device that combines better on-state performance with more benign reverse recovery, diminishing the need to short the CB body diode with a Schottky diode. Outside 77 K , the SJ body diode retains the same advantages of the conventional 4H−SiC body diode over Si diodes (fast turn-off and comparatively low JPR due to the capacitance-dominated switching) while still retaining the principal drawback of increased snappiness ( tB/tA>1.4 in only 9/15 RT scenarios tested and in 0/15HT scenarios tested). This snappiness limitation, however, is intrinsic to the SJ structure as it is due to the requirement of pillar pinch-off prior to significant voltage being supported. However, the 4H−SiC SJ does not suffer from excessive oscillations typical of Si SJ structures because the switching is depletion-capacitance dominated.
Comparison. The results favor the CB body diode for RR performance as it preserves fast, capacitance-dominated switching while remaining substantially less snappy than the SJ due to the lack of the pillar pinch-off constraint. It has a predictable temperature dependence, with QRR,sp increasing with temperature from 77 K−423 K, and almost no variation in switching time with temperature at matching conditions.

[picture]

Fig. 7. Dependence of snappiness on dJ/dt at various temperatures for the 4H−SiCCB and SJ Body Diodes.

Fig. 7. Dependence of snappiness on d J / d t at various temperatures for the 4 H − S i C C B and SJ Body Diodes.

[picture]

(b)

Figure 8. (b)

Fig. 8. Voltage waveforms during RR for 4H−SiC SJ Body Diode.

Anomalous Cryogenic RR. There are two possible sources for the additional QRR,sp observed in the SJ RR at 77 K . The additional extracted charge is either present before the RR is initiated (in the onstate) or is generated during the RR. The expected trend of decreasing lifetime with decreasing temperature predicts a reduction in stored minority carriers in the on-state (before initiation of RR) at 77 K compared to RT. The voltage zero-crossing temperature dependence (Figure 10) rules out a large increase in the stored minority carrier charge in the on-state, as such an increase would also increase t1 compared to RT. The measured decrease in t1 at 77 K compared to RT correlates with an expected lower lifetime at 77 K . Observing Figure 8, a consistent negative differential resistance (NDR) is observed around −VAK=200 V−300 V. NDR during RR has been previously observed in [8] and was attributed to dynamic breakdown. The breakdown voltage of the SJ rapidly decreases with the degree of charge imbalance [9]. While in [8], dynamic breakdown was caused by large transient current densities significantly modifying the background doping, the current densities in this case cause only a <0.01% modification in pillar doping. Rather, [9] reveals a plausible mechanism. For the SJ to support voltage, both the p -pillar and the n -pillar need to deplete. Depletion of the p -pillar is driven by hole emission of the acceptors. Due to the deepness of the Al acceptor level in 4H−SiC, the hole emission time at 77 K can exceed the switching time scale. For optimally designed SJ pillars, the lateral electric field at pillar pinch-off (when significant voltage begins to be supported) is equal to the critical electric field. If the p -pillars remain undepleted due to the large hole emission time at 77 K , the local electric field can exceed the critical field, causing avalanching. Since the avalanching happens at a high-voltage and large current, it is accompanied with significant local self-heating. The local self-heating decreases the hole emission time and locally depletes the p-pillar, compensating the n -pillar and reducing the electric field below the critical field. The large local electric field also decreases hole emission time through the Poole-Frenkel effect. Thus, destructive breakdown is avoided through negative feedback as the large electric fields leading to avalanching also create the condition to deplete the p -pillar and reduce the local electric field by compensating the donors in the n-pillar.

[picture]

Fig. 9. Dependence of the reverse recovery time ( tRR ) on dJ/dt at various temperatures for the 4 H SiC CB and SJ body diode.

Fig. 9. Dependence of the reverse recovery time ( t R R ) on d J / d t at various temperatures for the 4 H SiC CB and SJ body diode.

Simulations. We investigate our hypothesis by performing RR simulations of the 4H−SiC SJ DMOSFET using TCAD Sentaurus. Figure 11a shows the RR simulation of the SJ at 300 K as a baseline. In Figure 11b, a large ( >100x ) increase is seen in IPR when modeling the acceptors as traps located 0.2 eV above the valence band with σn=σp=1E−15 cm−2 and using the default Sentaurus PooleFrenkel model. Figure 11c reproduces the NDR characteristic seen in the SJ RR at 77 K , but the diode is no longer capable of turning off. When self-heating effects are also included (Figure 12), all observed characteristics are reproduced: (1) a large increase in QRR,sp compared to room temperature, and (2) an NDR dip during the RR. The simulations are only a qualitative reproduction, as IRP exceeds 100 A in the simulation. However, doping significantly reduces the thermal conductivity of 4H−SiC [10], especially at low temperature where the undoped thermal conductivity reaches a peak, and this effect was not modeled. A reduced thermal conductivity enhances self-heating and reduces the switching time and IRP of the simulated SJ body diode.

[picture]

Fig. 10. Temperature Dependence of the voltage zero-crossing time ( t1 ) at various reverse voltages.

Fig. 10. Temperature Dependence of the voltage zero-crossing time ( t 1 ) at various reverse voltages.

[picture]

Fig. 11. Simulated RR of 4H−SiC SJ Body Diode. (a) 300 K RR (b) 77 K RR, including temperature and electric-field hole emission time of acceptors (c) Same as (b), but including avalanche generation.

Fig. 11. Simulated RR of 4 H − S i C SJ Body Diode. (a) 300 K RR (b) 77 K RR, including temperature and electric-field hole emission time of acceptors (c) Same as (b), but including avalanche generation.

[picture]

Fig. 12. Simulated RR characteristics of 4H−SiC SJ Body Diode including self-heating effects and electric-field and temperature-dependent hole emission time for acceptors. (a) RR waveform, (b) Maximum temperature inside device during RR.

Fig. 12. Simulated RR characteristics of 4 H − S i C SJ Body Diode including self-heating effects and electric-field and temperature-dependent hole emission time for acceptors. (a) RR waveform, (b) Maximum temperature inside device during RR.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

RR is characterized for 3.3kV4H−SiC SJ charge-balance CB DMOSFET body diodes from 77−423 K using an inductive double-pulse. For T>77 K, both are capacitance-dominated: SJ turns off faster ( tRR=0.3−0.8×CB ), is snappier ( tB/tA=0.23−0.56×CB ), and shows larger JPR ( 1.8−2.8× CB ) while recovering less charge ( QRRsp=0.4−0.8×CB ). CB remains fast ( tRR≈100−350 ns ), has softer recovery ( tB/tA>1.4 in essentially all non-cryogenic cases), and follows a predictable temperature trend ( Qrr,sp increases with T with modest trrr variation). At 77 K the SJ shows an anomalous RR: QRR,sp increases by 1.4×−3.5× vs room temperature and 5× vs 19 K , JPR increases by >2×, and tRR changes by <30 ns; QRR,sp also regains sensitivity to ramp rate and VR and persists at JF=20 A/cm∧2 (vanishing by 7.5 A/cm2 ). Static I-V shows current-controlled negative resistance (CCNR) only for the SJ at 77 K , but transient decay during RR does not; we therefore have no evidence that CCNR directly causes the anomalous QRR,sp. TCAD including deep-acceptor emission and field/temperature-assisted effects qualitatively reproduces the cryogenic trends. Overall, CB is the safer default across temperature (fast, soft, predictable; no cryogenic anomaly), while SJ offers the shortest tRR above 77 K at the cost of higher snappiness and a 77 K charge increase.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

Z. Wang, J. Zhang, X. Wu, K. Sheng, Evaluation of reverse recovery characteristic of silicon carbide MOSFET intrinsic diode, IET Power Electron. 9 (2016) 969-976.

R. Ghandi, et al., Deep Implanted SiC Super-Junction Technology, presented at ICSCRM 2024, Raleigh, NC, USA, Sept. 29-Oct. 4, 2024.

R. Ghandi, et al., 4.5 kV SiC charge-balanced MOSFETs with ultra-low on-resistance, in: Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), 2020, pp. 126-129.

P. Xue, G. Fu, Analysis of the reverse recovery oscillation of superjunction MOSFET body diode, Solid-State Electron. 129 (2017) 81-87.

Z. He, C.W. Hitchcock, R. Ghandi, S. Kennerly, T.P. Chow, Comparative performance evaluation and analysis of high-voltage superjunction, charge-balanced and conventional 4 H SiC DMOSFETs at cryogenic and high temperatures, in: Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), 2025.

B.J. Baliga, Fundamentals of Power Semiconductor Devices, second ed., Springer, Cham, 2019, pp. 249-255.

S. Chowdhury, C.W. Hitchcock, R. Dahal, I. Bhat, T.P. Chow, Current-controlled negative resistance in high-voltage p-i-n rectifiers, IEEE Trans. Electron Devices 64 (2017) 897900.

M. Domeij, Transient breakdown in 4H-SiC p-i-n diodes, Solid-State Electron. 44 (2000).

N. Donato, F. Udrea, Static and dynamic effects of the incomplete ionization in superjunction devices, IEEE Trans. Electron Devices 65 (2018) 4469-4475.

R. Wei, S. Song, K. Yang, et al., Thermal conductivity of 4H-SiC single crystals, J. Appl. Phys. 113 (2013) 053503.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/performance-analysis-of-sic-power-devices/978-3-0364-3130-7

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 119-124

doi: 10.4028/p-wV3ZEX

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-21

Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

Marvin Gloth a*, Drinas Kelmendi b, Hamed Azimi c, Benjamin Weigt d and Tobias Erlbacher e 

Nexperia, Stresemannallee 101, 22529 Hamburg, Germany

a  Marvin.Gloth@nexperia.com, b  Drinas.Kelmendi@nexperia.com, c  Hamed.Azimi@nexperia.com, d Benjamin.Weigt@nexperia.com, e Tobias.Erlbacher@nexperia.com

Keywords: Silicon Carbide, Deep Oxide Traps, Tunneling, Body Diode, Dynamic Conduction, Sub-Threshold Regime, Flat-Band Voltage Shift

Abstract

This paper investigates the dynamic conduction behavior of silicon carbide (SiC) MOSFETs in the sub-threshold regime. We demonstrate that controlled gate bias preconditioning, combined with time-resolved electrical measurements in thermal equilibrium, reveals a notable drift in the source-drain voltage Vsd. The direction of this drift depends on the polarity of gate preconditioning and is directly related to variations in the channel conduction. These effects are shown to be attributed to charge release from deep oxide traps, leading to a gradual shift in the flatband voltage ( Vfb ) over time. Experimental results reveal that these dynamic effects are most prominent in the depletion and weak inversion regimes. Our findings highlight the influence of oxide trap dynamics on the body diode forward voltage ( Vf ) and its significance for the reliability of SiC devices, specifically in its role as the temperature-sensitive parameter.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

Despite their revolutionary characteristics, SiC MOS-FETs exhibit unique challenges, particularly related to sub-threshold conduction, as well as their correlation to Vf. Previous studies have shown that Vf, as a temperature-sensitive electrical parameter (TSEP), exhibits pronounced time dependence [1,2] and is further affected by the applied gate bias [3]. This dynamic Vf may lead to inaccuracies in junction temperature estimation, causing over- or under-stress conditions during reliability tests. To illustrate this effect, Fig. 1 shows an example where the cooling curve of the body diode in a discrete SiC-MOSFET was measured at different Vgs after being subjected to identical heating conditions through the active channel. The results reveal that the temperature response during cooling significantly differs between measurements, demonstrating that the influence of gate bias cannot be neglected. Huerner et al. [4] investigated the influence of gate voltage on the forward conduction properties of the body diode. The study showed that the current path through the channel remained significant even for gate voltages below the threshold voltage, creating an additional conduction path in parallel to the body diode. Their simulations further demonstrated that once the MOSFET enters depletion, the current through the channel becomes negligible and primarily flows through the body diode. However, the sub-threshold conduction and its correlation to the body-diode characteristics remain largely unexplored.

[picture]

Fig. 1. Junction temperature cooling curve at different Vgs for a chiller temperature of Tc=25∘C

Fig. 1. Junction temperature cooling curve at different V g s for a chiller temperature of T c = 25 ∘ C

Experimental Setup and Findings

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To systematically analyze the dynamic conduction behavior, a Keysight B 1505 parameter analyzer with the circuit configuration shown in Fig. 2 was used. A set of tests as shown in Tab. 1 was defined for these investigation. In Phase 1 (Pre-Conditioning), the SiC MOSFETs were subjected to controlled gate bias Vgs,pre, to reach either strong inversion or strong accu-mulation. After Phase 1, the gate bias was switched to different Vgs, meas  values, each initiating a voltage

[picture]

Fig. 2. Measurement circuit for measuring the dynamic conduction behavior

Fig. 2. Measurement circuit for measuring the dynamic conduction behavior

monitoring phase (Phase 2). During this phase, a measurement current of 10 mA is continuously applied from source to drain to measure Vsd. This measurement current was chosen sufficiently small to make self-heating negligible. Multiple products from different manufacturers and different design technologies, including planar MOSFETs, trench MOSFETs with PN junctions, and planar MOSFETs incorporating embedded Schottky junctions (MPS), were used for these investigations. For represen-tation comparison, two device types - a planar MOSFET with a PN junction and a planar MOSFET with an MPS structure- were selected.

Table 1. Test Plan for measuring the dynamic conduction behavior

Phase 1: Pre-Conditioning | Phase 2: Voltage-Monitoring | Measurement Current
mode | Vgs,pre | time | Vgs,meas | time | Im
strong Inversion | +15 V | 60 s | -10 V...+10 V | 1000 s | 10 mA
strong Accumulation | -15 V | 60 s | -10 V...+10 V | 1000 s | 10 mA

Fig. 3a shows the response measured at Vgs, meas =−3 V for the two preconditioning modes outlined in Tab. 1. These graphs reveal several key observations: First, Vsd is clearly time-dependent, with the largest shift in ΔVsd occurring at the transition from Phase 1 to Phase 2. Then the signal gradually converges to a steady-state value, exhibiting time constants of up to τ≈160s.

[picture]

Fig. 3. (a) Dynamic reverse-conduction response after different gate-preconditioning voltages at -3 Vgs, meas  (b) ΔVsd after different gate preconditioning at various gate voltages.

Fig. 3. (a) Dynamic reverse-conduction response after different gate-preconditioning voltages at -3 V g s , meas (b) Δ V s d after different gate preconditioning at various gate voltages.

Interestingly, the preconditioning bias defines the drift direction, which exhibits an inverse settling behavior. However, the conduction levels ultimately converge to a common steady-state value, independent of the initial conditions. Comparing ΔVsd with Cgs within the defined Vgs, meas  range from the Tab. 1 reveal a direct correlation to the channel conduction regimes, as shown in Fig. 3b. The dynamic effects are most pronounced during channel depletion and weak inversion, while they are considerably less significant under strong inversion and accumulation, as indicated by the Cgs curves. Furthermore, the direction of the voltage sweep in the capacitance measurement introduces a hystere-sis effect. Similarly, another hysteresis is evident in the ΔVsd measurements, depending on the applied preconditioning. The amplitude of ΔVsd is lower when the device is preconditioned in inversion com-pared to preconditioning in accumulation.

These findings indicate that the underlying mechanism in the dynamic Vsd cannot be explained solely by the body diode and is somehow linked to the MOS capacitor behavior. Therefore, mechanisms like self-heating and deep-level bulk crystal defects, can be excluded based on our measurements. Thus the behavior is related to an additional current path through the channel [4].

Flat-band voltageVsdShift

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Fig. 4 illustrates a simplified representation model of the parallel conduction paths through the body diode and the channel. In this configuration, the channel conduc-tion is determined by the charges controlled through the MOS-capacitor and its electrostatics. Therefore, the flat-band voltage ( Vfb ) at the SiC/SiO2 interface must now be taken into account. Eq. (1) defines the relation between Vfb and the built-in potential ( Vbi ) as a function of the metal/polysilicon work function ( Φm ), the semiconductor work function ( Φs ), and the trapped charges within the oxide ( −Qox ,t/Cox  ). Any shift in Vfb directly influences the threshold voltage and, consequently, the degree of channel conduction.

[picture]

Fig. 4. Simplified representation model

Fig. 4. Simplified representation model

Vfb=−Vbi=Φm−Φs−Qox,tCox(1)

According to Kang et al.[5] the trap charge related flat-band voltage shift can be expressed as ΔVfb by Eq. (2).

ΔVfb=−Qox,tCox=−1Cox∫0toxxttoxρ(x)dx→ΔVfb(t)∝Q(0)Coxe−tτ(2)

Based on this relation, the shift in ΔVfb settles exponentially. This shift induces a corresponding variation in threshold voltage ( ΔVth  ), which reflects a change in channel resistance ( ΔRch ), and thus influences the source-drain voltage (ΔVsd). To quantify the average variation of Vfb as a function of ΔVsd, Figure 5 compares Vsd at t=0 s and t=6 s for various gate-source voltages ( Vgs ). For simplicity, it is assumed that Vsd has reached steady state after 6 s , such that the vertical difference at a given Vgs corresponds to ΔVsd.

[picture]

Fig. 5. Sub-threshold behavior at the beginning and end of the Vds(Vgs) measurement at Im=10 mA. It shows rendering trap dynamics due to Vth  and PN-conduction properties. Zoom shows the average sub-threshold shift due to hole release and the resulting Vfb shift.

Fig. 5. Sub-threshold behavior at the beginning and end of the V d s ( V g s ) measurement at I m = 10 m A . It shows rendering trap dynamics due to V th and PN-conduction properties. Zoom shows the average sub-threshold shift due to hole release and the resulting V f b shift.

At the same time, at a fixed Vsd, the horizontal gap represents a ΔVgs. This ΔVgs shift is timedependent and reflects the dynamics of the MOS capacitor, which are governed by trap dynamics expressed as ΔVfb. The magnitude of the shift allows for an estimation of the amount of trap charges participating in the dynamic response, providing a visual representation of Eq. (2). Furthermore, the slope of the curves provides insight into sensitivity of the channel to charge changes at the gateoxide. This behavior demonstrates the proportional correlation between gate charge and channel conductance in this regime.

Another observation indicates that for gate voltages exceeding the Vth , the channel enters strong inversion, thereby reducing the sensitivity of conduction to shifts in Vfb. Once Vsd reaches the forward voltage of the PN/MPS junction, variations in the flat-band voltage become less pronounced, as the measurement current flows primarily through the body diode. The impedance of the body diode is dominating the depleted channel. This effect may occur even before accumulation of the channel and is particularly pronounced in MOSFETs with an integrated MPS junction.

Trap Dynamics Mechanics

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As discussed in the previous section, the observed behavior of Vsd is driven by trap dynamics that affect the channel conduction. Kang et al. [5] attributed this trap dynamics to the presence of deep ox-ide traps exhibiting long tunneling time constants. The time constants are governed by the tunneling probability, which is, in turn, strongly dependent on the spatial position of the trap within
the oxide. Traps located deeper in the oxide, i.e., farther from the SiC/SiO2 interface, exhibit significantly longer time constants than those near the interface, rendering them more difficult to detect during transient or fast measurements. Thicker oxides further exacerbate this effect, as the reduced tunneling probability for deeply embedded trap states results in more pronounced charge release over prolonged times. The following Eq. (3) provides a quantitative description of this phenomenon [6]. ΦB,h―,Ec,Et,mox* and ms* represent the discontinuity between semiconductor and oxide, reduced Planck constant, conduc-tion band edge, trap energy level, effective electron masses in the oxide and in the semiconductor, respectively.

τ(x)=mox*22x(1+12η1x)2π2η2h¯2Dite2η1x with η12=2mox*(ΦB+Ec−Et)h¯2,η22=2ms*(Ec−Et)h¯2(3)

The analysis of trap dynamics indicates that the observed signal at Fig. 3a cannot be adequately represented by a single time constant. A deconvolution-based approach, applied across the temperature range, did not result in conclusive and reliable estimations of the activation energies associated with the participating trap states. Nevertheless, the extracted mean time constant of τ≈160 s suggests that the tunneling probability of deep traps appears to dominate the overall time constant of the observed dynamic effect.

After a positive preconditioning, the oxide gradually releases holes, leading to a decreased channel depletion. Conversely, after a negative preconditioning, negative charges are released, increasing the channel depletion. Fig. 3a illustrates the dynamic reverse conduction behavior response and the presence of both deep positive and negative oxide traps at −3 Vgs, meas  for positive (+15 V) and negative (−15 V) preconditioning respectively. The switching trap behavior dependence on the preconditioning voltage shows similar signatures attributed to dipole oxygen vacancies (e.g., Eγ4t centers) [7].

Summary

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This work investigates the dynamic conduction of SiC MOSFETs in the sub-threshold regime under conditions of low reverse current and thermal equilibrium. Gate-bias preconditioning is shown to induce inverted drifts in Vsd(t), which converge toward a common steady state. The effect is most pronounced during channel depletion and weak inversion, consistent with the observed correlation between Vsd(t) and Cgs(VGs). The behavior is attributed to time-dependent flat-band shifts (Vfb(t)) arising from trap dynamics in the oxide. A characteristic time constant of τ≈160 s was extracted, indicating tunneling from traps located deep within the oxide. In regimes of strong inversion or strong depletion, the sensitivity to Vfb shifts diminishes, rendering the drift negligible. Alternative explanations such as self-heating or deep bulk crystal defects were systematically excluded. These findings carry practical implications for reliability assessment and for temperature sensing based on the diode forward voltage ( Vf ) as a TSEP: preconditioning and relaxation times must be carefully controlled or compensated to avoid bias in junction-temperature estimation. Future work will focus on the quantitative extraction of trap energy and depth distributions through extended temperature sweeps and complementary techniques (e.g., charge pumping, DLTS, scanning capacitance), as well as on assessing process and oxide-thickness dependencies to mitigate the observed drift.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

M. Noah, et al. "Dynamic calibration: How to properly estimate junction temperature in SiC MOSFETs subject to body diode voltage shift. "Proceedings of the 14th Int. Conference on Inte-grated Power Electronics Systems (CIPS), Düsseldorf 2024.

J. Breuer, et al. "Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling - a Dynamic Approach. "Proceedings of the 14th Int. Conference on Integrated Power Electronics Systems (CIPS), Düsseldorf 2024.

F. Kato, S. Sato, K. Koui, H. Tanisawa, H. Hozoji and H. Yamaguchi, "Study of Gate Bias Volt-age for Preventing Threshold Shift of SiC-MOSFET Body Diode during Transient Temperature Measurements," 2019 International Conference on Electronics Packaging (ICEP), Niigata, Japan, 2019, pp. 88-91

A. Huerner, et al. "Analytical model for the influence of the gate-voltage on the forward conduction properties of the body-diode in SiC-MOSFETs. "Proceedings of the International Con-ference on Silicon Carbide and Related Materials, ICSCRM 2017 Trans Tech Publications Ltd, 2018. 901-904

C. J. Kang, et al. "Charge trap dynamics in a SiO 2 layer on Si by scanning capacitance microscopy, Appl. Phys. Lett. 74, 1999. 1815-1817

R. E. Paulsen, R. R. Siergiej, M. L. French and M. H. White, "Observation of near-interface oxide traps with the charge-pumping technique," in IEEE Electron Device Letters, vol. 13, no. 12, pp. 627-629, Dec. 1992

C. J. Nicklaw, et al. "The Structure, Properties, and Dynamics of Oxygen Vacancies in Amorphous SiO2", IEEE Transactions on Nuclear Science, vol. 49, no. 6, Dec. 2002.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 125-130

doi: 10.4028/p-m0gjDq

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-02-26

Online:
2026-05-21

Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1057.125.pdf

Ruei-Ci Wu 1,a, Kung-Yen Lee 2,3,b*, Pei-Chi Liao 2,c, Pei-Chun Liao 2,d, Jui-Chi Chu 2,e

1 SiCEV Electronics Co., Ltd, Taiwan

2 Graduate School of Advanced Technology, National Taiwan University, Taiwan

3 Department of Engineering Science and Ocean Engineering, National Taiwan University, Taiwan

a  ricky_wu@sicev.com.tw, b  kylee@ntu.edu.tw, cr13k  43003@ntu.edu.tw, d  d13k44005@ntu.edu.tw, er13k43039@ntu.edu.tw

Abstract

This study demonstrates that the output capacitance ( Coss  ) of a 4H−SiC MOSFET is proportional to the length of JFET ( LJFET  ) at a low Vds , since under this condition, the gate-to-drain capacitance ( Cgd ) may account for nearly half of Coss . Furthermore, when Vds is low, the Coss  of MOSFETs with square and hexagonal cell topologies is approximately 20% and 25% higher than that of MOSFETs with the strip cell topology, respectively, due to larger JFET areas. However, when Vds is higher, the Coss  of MOSFETs with square and hexagonal cell topologies is lower because of the lower drain-to-source capacitance ( Cds ) resulting from smaller Pwell areas. The split-gate MOSFET can reduce Cgd, but the smaller poly-gate area decreases the depletion capability, resulting in a higher Cds. As Ljfet of the MOSFET decreases, Cgd becomes lower, which may shorten the switching time, but due to the increased area of Pwell ( LPW ), the reverse recovery current ( IIr ) increases. This study proposes partially increasing the gate oxide thickness. Although this may slightly increase Cds, the shorter switching time results in a 5% reduction in the turn-on switching loss (Eon ).

Keywords: Cell topology, Split-gate MOSFET, Output capacitance ( Coss  ), Abrupt drop phenomenon, Switching losses

Introduction

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Coss  has a significant impact on the switching time and reverse recovery characteristics of MOSFETs [1], [2], [3]. Coss  consists of Cgd and Cds, and Cds consists of the sidewall and bottom capacitances of the Pwell ( CSw and CB ) [4], [5], as illustrated in Fig. 1. Therefore, the structure and topology of both the JFET and Pwell significantly influence Coss  [6], [7]. However, their correlation and mechanisms have not yet been sufficiently studied. When Vds is low, Coss  is dominated by Cgd and Csw. . At high Vds, the JFET is fully depleted, Cgd and Csw is saturated, and Coss  is then dominated by CBt [5], [8], [9]. Therefore, the area of the JFET and the sidewall of the P-well affect Coss  more significantly at low Vds, whereas the area of the bottom of P -well affects Coss  at high Vds. This study investigated the influences of the variation of LJFET  and LPW , as well as the split-gate structure on Coss . Accordingly, the Coss  of MOSFETs with strip, square, and hexagonal cell topologies was compared. Furthermore, turn-on time ( ton ), reverse recovery current ( Irr ), and turn-on energy loss ( Eon ) of the MOSFETs with different LJFET  and LPW  were obtained by the double pulse test (DPT) in this study.

[picture]

Fig. 1. Schematic and parasitic capacitances of the 4H−SiC MOSFETs in this study.

Fig. 1. Schematic and parasitic capacitances of the 4 H − S i C MOSFETs in this study.

Experimental

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The MOSFETs with strip, square, and hexagonal cell topologies were fabricated in this study, as shown in Fig. 2. The LJFET  and LPW  of the MOSFETs are listed in Table I. The concentrations of epitaxy and Pwell of the MOSFETs are approximately 8×1015 cm−3 and 2×1018 cm−3, respectively. For comparison, the split-gate MOSFET was also fabricated, with the spacing between adjacent poly gates being 1.0μ m. The forward and reverse Ids−Vds curves and capacitances of MOSFETs were measured by Keysight B1505A, whereas the DPT was simulated using TCAD software, Sentaurus.

[picture]

Fig. 2. The capacitances of MOSFETs with different cell structures and topologies. All the MOSFETs were fabricated in this study.

Fig. 2. The capacitances of MOSFETs with different cell structures and topologies. All the MOSFETs were fabricated in this study.

Table I. The structural parameters of MOSFETs fabricated in this study.

Topologies | Strip | Strip | Strip | Strip | Split-gate | Square | Hexagonal
mathematical formula | 2.4 | 2.2 | 2.0 | 2.2 | 2.2 | 2.4 | 2.4
mathematical formula | 6.5 | 6.5 | 6.5 | 5.0 | 5.0 | 6.5 | 6.5

Results and Discussions

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Fig. 3 shows that the on-resistance ( Ron ) of the hexagonal-cell and square-cell MOSFETs is approximately 21% and 10% lower than that of the conventional strip-cell MOSFET, respectively, because of the larger channel areas. Additionally, Fig. 4 shows that their breakdown voltages ( BV ) are nearly the same. According to Fig. 5, when Vds is low (less than 10 V ), Cgd represents approximately half of Coss  in the conventional strip-cell MOSFET, as indicated by the blue dashed and red dotted lines. In addition, since the abrupt drop occurs at a Vds of 10 V , this implies that the JFET is fully depleted at this point. Therefore, when Vds exceeds 10 V , both Cgd and CSw become saturated, and Coss  is dominated by CBt, as illustrated in Fig. 1.

As shown in Fig. 6, when Vds is low, Coss  decreases as LJFET  is shortened from 2.4μ m to 2.0μ m, due to a reduction in Cgd. When LJFET is shortened by 0.2μ m,Coss  decreases by 2%. However, as Vds increases, the difference between Coss  of the various MOSFETs becomes small. This is because Cgd decreases more rapidly than Cds, making its influence on Coss  less significant. After the abrupt drop, the Coss  of different MOSFETs are more consistent, because CBT  of each MOSFETs is similar.

[picture]

Fig. 3. The measured forward Ids−Vds curves of the MOSFETs with different cell topologies.

Fig. 3. The measured forward I d s − V d s curves of the MOSFETs with different cell topologies.

[picture]

Fig. 4. The measured reverse Ids−Vds curves of the MOSFETs with different cell topologies.

Fig. 4. The measured reverse I d s − V d s curves of the MOSFETs with different cell topologies.

[picture]

Fig. 5. The measured Ciss, Coss, and Crss (Cgd) of the conventional strip-cell MOSFET.

Fig. 5. The measured Ciss, Coss, and Crss (Cgd) of the conventional strip-cell MOSFET.

[picture]

Fig. 6. The measured Coss of the conventional strip-cell MOSFETs with different LJFET and LPW.

Fig. 6. The measured Coss of the conventional strip-cell MOSFETs with different L J F E T and L P W .

From Fig. 7, at a low Vds, the Coss of the square and hexagonal-cell MOSFETs are 20% and 25% higher than that of the strip-cell MOSFET, respectively, because of the higher Cgd resulting from the larger JFET area and higher CSw resulting from more sidewalls of Pwells. Nevertheless, after the abrupt drop, the Coss  of the square and hexagonal-cell MOSFETs becomes slightly lower than that of the strip-cell MOSFET, owing to their smaller P-well areas. Even though the difference in Coss  is relatively small, high-voltage switching can still cause considerable variations in space charge and significantly affect Irr . Additionally, it can be inferred that when Coss  is higher at low Vds , it may be lower at high Vds when the chip area of the MOSFET is fixed.

As shown in Fig. 8, Cgd can be reduced not only by shortening LJFET or decreasing the JFET area, but also by reducing the poly-gate area. Therefore, a split-gate MOSFET with the poly-gate length reduced by 1.0μ m exhibits a 28% reduction in Coss  at low Vds . However, a smaller poly gate reduces the depletion capability of the MOSFET, leading to a higher Cds. As a result, after Cgd saturates, the Coss  of the split-gate MOSFET may become higher than that of the conventional MOSFET, and the abrupt drop occurs later since the JFET should be fully depleted at a higher Vds.

According to Fig. 9, when LJFET  decreases, Cgd  is reduced, allowing the MOSFET to turn on more quickly. Therefore, the turn-on time ( ton ) is shortened. However, Irr may increase due to the larger Pwell area, which leads to a higher Cds. Hence, it can be concluded that there is a trade-off between ton and Irr. In addition, it is found that the MOSFET with LJFET and LPW of 2.2μ m and 6.5μ m, respectively, achieves an Eon  of about 8% and 6% lower than those of the other two MOSFETs with LJFET and LPW of 2.0μ m and 6.5μ m, and 2.4μ m and 6.5μ m, respectively, as shown in Fig. 9 .

[picture]

Fig. 7. The measured Coss of the MOSFETs with different cell topologies.

Fig. 7. The measured Coss of the MOSFETs with different cell topologies.

[picture]

Fig. 8. The measured Coss of the conventional and split-gate MOSFETs.

Fig. 8. The measured Coss of the conventional and split-gate MOSFETs.

[picture]

Fig. 9. The simulated turn-on waveforms of the MOSFETs with different structures during DPT.

Fig. 9. The simulated turn-on waveforms of the MOSFETs with different structures during DPT.

In this study, a novel MOSFET with partially thickened gate oxide is proposed, as shown in Fig. 10. This design lowers Cgd by reducing the gate oxide capacitance, yet it does not significantly affect Cds, since the depletion width of the P−N junction is maintained. As a result, the ton of the novel MOSFET is slightly shorter than that of the conventional MOSFET, whereas the Irr of both MOSFETs remains nearly the same, as shown in Fig. 11. Consequently, the Eon  of the novel MOSFET is reduced by 5% compared with that of the conventional MOSFET.

[picture]

Fig. 10. Schematic of the novel MOSFET with a partially thickened gate oxide.

Fig. 10. Schematic of the novel MOSFET with a partially thickened gate oxide.

[picture]

Fig. 11. The simulated turn-on waveforms of the conventional and novel MOSFETs during DPT.

Fig. 11. The simulated turn-on waveforms of the conventional and novel MOSFETs during DPT.

Summary

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Before the abrupt drop, Coss  is dominated by Cgd and Cds, whereas after the abrupt drop, it is dominated only by Cds because JFET is fully depleted. Hence, at low Vds, MOSFETs with a longer LJFET  or a larger JFET area, such as hexagonal-cell and square-cell MOSFETs, exhibit higher Coss . At higher Vds,Coss increases with the Pwell area. In addition, although the split-gate MOSFET can reduce Cgd , its inferior depletion capability not only delays the occurrence of the abrupt drop but may also lead to an increase in Cds.
Cgd and Cds depend on the areas of the JFET and P-well, respectively. Thus, a higher Cgd may correspond to a lower Cds. Furthermore, ton and Irr depend on Cgd and Cds, respectively. Consequently, a shorter ton results in a higher Irr. This indicates a trade-off between ton and Irr.

This study proposes a novel MOSFET with a partially thickened gate oxide, which shortens ton but ensures that Irr does not increase excessively. According to the simulation results, the Eon  of the novel MOSFET is 5% lower than that of the conventional MOSFET.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.125.pdf

H. Jiang, J. Wei, X. Dai, C. Zheng, M. Ke, X. Deng, Y. Sharma, I. Deviny and P. Mawby, "SiC MOSFET with Built-in SBD for Reduction of Reverse Recovery Charge and Switching Loss in 10-kV Applications," 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 2017, pp. 49-52, doi: 10.23919/ISPSD.2017.7988890.

J. Wei, M. Zhang, H. Jiang, X. Zhou, B. Li and K. J. Chen, "Superjunction MOSFET with Dual Built-In Schottky Diodes for Fast Reverse Recovery: A Numerical Simulation Study," in IEEE Electron Device Letters, vol. 40, no. 7, pp. 1155-1158, July 2019, doi: 10.1109/ LED.2019.2917556.

S. Jahdi, O. Alatise, R. Bonyadi, P. Alexakis, C. A. Fisher, J. A. Ortiz Gonzalez, L. Ran and P. Mawby, "An Analysis of the Switching Performance and Robustness of Power MOSFETs Body Diodes: A Technology Evaluation," in IEEE Transactions on Power Electronics, vol. 30, no. 5, pp. 2383-2394, May 2015, doi: 10.1109/TPEL.2014.2338792.

R. C. Wu, K. Y. Lee and P. C. Liao, "Adjustment of Abrupt Drops in the C-V Curves of Various 4H-SiC MOSFETs and JBS Diodes," IEEE Electron Device Letters, vol. 46, no. 2, pp. 135-138, 2025, doi: 10.1109/LED.2024.3522278.

R. C. Wu, K. Y. Lee, Y. Y. Wen and P. C. Liao, "The Correlation of the Drain-source Capacitance Variation and the P-pillar Structures in a Quasi Super Junction MOSFET," Materials Science in Semiconductor Processing, vol. 178, 108413, 2024, doi: 10.1016/j.mssp.2024.108413.

A. Agarwal, K. Han, and B. J. Baliga, "Impact of Cell Topology on Characteristics of 600 V 4HSiC Planar MOSFETs," IEEE Electron Device Letters, vol. 40, no. 5, pp. 773-776, 2019, doi: 10.1109/LED.2019.2908078.

H. Wu, H. Luo, J. Zhang, B. Zheng, R. Wang, and X. Chen, "Comparison and Analysis on Static and Dynamic Performance of SiC Planar MOSFETs with Different Cell Topologies," Materials Science in Semiconductor Processing, vol. 184, 108849, 2024, doi: 10.1016/j.mssp.2024.108849.

Z. Y. Ye, L. Liu, Y. Yao, M. Z. Lin and P. F. Wang, "Fabrication of a 650V Superjunction MOSFET with Built-in MOS-Channel Diode for Fast Reverse Recovery," in IEEE Electron Device Letters, vol. 40, no. 7, pp. 1159-1162, July 2019, doi: 10.1109/LED.2019.2915008.

S. Roy, A. Bhattacharyya, C. Peterson, S. Krishnamoorthy, " Lateral High-Permittivity Dielectric Superjunction Schottky Barrier Diode with Power Figure of Merit," IEEE Electron Device Letters, 43(12), 2037-2040, 2022, doi: 10.1109/LED.2022.3216302.

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Keywords Index

#

4 H -sic Mosfet Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

4h-sic Lateral Cmos Technology Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

A

Analytical Modeling An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

B

Bias Temperature Instability Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Bipolar Phototransistor Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Body Diode Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Border Traps Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

C

Capacitance Measurements Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Capacitance Peak Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Charge Pumping Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Charge-balance Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Coulomb Scattering Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Critical Dimension Metrology Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Cryogenic Temperatures Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

D

Deep Oxide Traps Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Draininduced Barrier Lowering (dibl) Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Dynamic Breakdown Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Dynamic Conduction Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Dynamic Losses 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

E

Ellipsometry Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

F

Far-uvc Detection Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Flat-band Voltage Shift Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Fowler-nordheim Current Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

G

Gate Capacitance Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Gate Leakage Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Gate Oxide Field Crowding Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Gated Hall Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

H

Hall Mobility Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

High-k 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Hysteresis Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

I

Interface Traps Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

M

Merged Pn Schottky Diode Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Mev Implantation Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Mobility Modeling Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

N

Non-repetitive Surge Current Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Not Logic Gate Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

O

Ocd Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

P

P-i-n Diodes An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

Planar Mosfet Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

R

Reflectometry Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Repetitive Surge Current Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Reverse Recovery Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

S

Schottky Barrier Diode Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Semi-superjunction Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Short-circuit Reliability Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Silicon Carbide Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes; Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Silicon Carbide (sic) Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Sin 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Split-gate Mosfet (sg-mosfet) Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Sub-threshold Regime Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Superjunction Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Surface Phonon Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Surface Roughness Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Surge Current Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

T

Threshold Voltage Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Transconductance Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Trench Mosfet Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Triple Sense Method Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Tunneling Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

U

Ultraviolet Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Authors Index

A

Antoniou, M. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Azimi, H. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

B

Baier, L. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Balogh, E. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Benedetto, L. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Borca-Tasciuc, G. An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Borghese, A. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Breglio, G. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

C

Cao, Q. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Cheng, P. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Chow, T. An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Chu, J. Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Cui, Y. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

D

Daliento, S. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Damcevska, J. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Das, S. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

deBoer, S. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Dikó, B. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Dimitrijev, S. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

E

Erlbacher, T. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

F

Feiler, W. Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

G

Gammon, P. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Ghandi, R. Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Gloth, M. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Gott, J. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

H

Haasmann, D. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Han, J. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Harada, S. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Hinojosa, M. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Hitchcock, C. Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Hou, T. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

I

Iosifidis, N. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Irace, A. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

J

Jia, R. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

K

Kelmendi, D. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Kiss, Z. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Knoll, L. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Konstantinov, A. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Körfer, J. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

L

Lee, H. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Lee, K. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Lelis, A. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Li, C. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Liang, L. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Liao, P. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Licciardo, G. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Lichtenwalner, D. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Liguori, R. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Lim, J. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Liu, X. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Liu, Y. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Luo, L. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Lynch, J. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

M

Mancini, S. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Maresca, L. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Matacena, I. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

May, A. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Melnyk, K. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

N

Narita, S. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Naureen, S. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

O

Ortiz-Gonzalez, J. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

P

Peng, B. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

R

Reigosa, P. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Renz, A. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Reshanov, S. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Riccio, M. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Rinaldi, N. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Rommel, M. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Rubino, A. Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Rusch, O. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Ryu, S. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

S

Schneider, N. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Scholten, D. Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Shah, V. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Stark, R. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Stecconi, T. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Stein, S. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Sung, W. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Sütő, A. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

T

Takenaka, K. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Tanner, P. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Tawara, T. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

W

Wang, W. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Weigt, B. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Wen, Y. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Wu, R. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Y

Yildirim, M. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Yuan, L. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Z

Zeng, F. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Zhang, Y. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Zhong, Y. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Ziegler, J. Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs