Processes in Devices Fabrication

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Processes in Devices Fabrication

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

All rights reserved. No part of the contents of this publication may be reproduced, processed or transmitted in any form or by any means without the written permission of the publisher.

Trans Tech Publications Ltd
Seestrasse 24c
CH-8806 Baech
Switzerland
https://www.scientific.net

Volume 1158 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

Full text available online at https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Distributed worldwide by
Trans Tech Publications Ltd
Seestrasse 24c
CH-8806 Baech
Switzerland
Phone: +41 (44) 9221022
e-mail: sales@scientific.net

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-05

Online:
2025-09-08

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1158.-1.pdf

This special edition presents recent advances in processes for fabricating integrated circuits and power electronics devices based on silicon carbide. The contributions explore critical aspects of planar CMOS and MOSFET technologies, including contact formation, dielectric stack engineering, oxidation process analysis, and gate oxide integrity, all of which directly affect device reliability and performance.

Attention is also devoted to contact forming processes and minimisation of conduction loss for optimal efficiency in power semiconductor switches.

Some articles consider innovations related to post-deposition annealing and deep implantation processes.

The edition also highlights processes and techniques such as trench etching, super-junction technology, and the use of metal-oxide-semiconductor capacitors in advanced device structures.

By combining perspective materials processing techniques, device engineering, and circuit integration methods, this special edition provides a comprehensive overview of the state of the art in SiC-based power electronics device fabrication technologies, serving as a valuable resource for researchers, engineers, and practitioners in the field.

Table of Contents

Preface

Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Yi Jie Lin, Chuan Han Chen, Ming Han Wang, Bing Yue Tsui

Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Kai Wen Hsu, Huai Lin Huang, Chia Lung Hung, Yi Kai Hsiao, Bing Yue Tsui

Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

Sandra Krause, Aleksey Mikhaylov, Uwe Schroeder, Thomas Mikolajick, Andre Wachowiak

Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Marilena Vivona, Patrick Fiorenza, Giuseppe Greco, Salvatore Di Franco, Gabriele Bellocchi, Paola Mancuso, Simone Rascunà, Antonio Massimiliano Mio, Giuseppe Nicotra, Filippo Giannazzo, Fabrizio Roccaforte

Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Xavier Pages, Simon van der Linde, Jeppe Oterdoom, Mark Steltenpool, Vladimir Kuznetsov, Jaap Beijersbergen, Mickael Sanchez, Sébastien Kerdilès

The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Young Bin Im, In Kyu Kim, Ji Yeong Yoon, Jin Gu Lee, Gi Hoon Park, Je Sung Lim, June Woo Son, Jung Ho Lee, Y.J. Jang, Chang Beom Jeong

A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Jae Hyung Park, Jeff Joo Hyung Kim, Ashish Kumar, Jacob Zacks, Daniel Flint, Daniel J. Lichtenwalner, Sei Hyung Ryu

Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Abdul Hannan Yeo, Qin Gui Roth Voo, Lakshmi Kanta Bera, Umesh Chand, Navab Singh, Surasit Chung, Xuan Sang Nguyen, Zhan Jiang Quek, Akhil Ranjan, Vudumula Pavan Kumar Reddy, Sze Jian Garrick Ho, See Kiat Lim, Muhammad Ozalis Omar, Jia Wei Xie, Yee Chia Yeo, Xiao Gong

Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Motoki Kobayashi, Hidetsugu Uchida, Naoki Hatta, Seiji Ishikawa, Yuta Higashi, Hiroshi Sezaki, Shinsuke Harada, Kazutoshi Kojima

Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Mustafa Akif Yildirim, Vishal Ajit Shah, Marina Antoniou, Andrew Newton, Sami Bolat, Gerard Colston, Andrew Graham, Richard Jefferies, James A. Gott, Kushani Perera, Michael J. Powell, Peter Michael Gammon, Philip Andrew Mawby, Robert Gunn, Arne Benjamin Renz

Deep Implanted SiC Super-Junction Technology

Reza Ghandi, Collin Hitchcock, Stacey Kennerly

Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Rydhem Grover, Kelly Turner, Gerard Colston, Arne Benjamin Renz, Marina Antoniou, Peter Michael Gammon, Philip Andrew Mawby, Vishal Ajit Shah

Study of SiC Trench Etching Characteristics for Different Crystal Planes

Akhil Ranjan, Lakshmi Kanta Bera, Shiv Kumar, Hua Mao Lin, Umesh Chand, Navab Singh, Surasit Chung, Abdul Hannan Yeo, Qin Gui Roth Voo, Arvind Sundaram, Li Yuan Liu, Jasmine Woo Yuen Kam

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 1-8

doi: 10.4028/p-atG6aA

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-08-31

Revised:
2025-05-08

Accepted:
2025-05-08

Online:
2025-09-08

Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

Yi-Jie Lin , Quan-Han Chen , Ming-Han Wang , and Bing-Yue Tsui

Institute of Electronics, National Yang Ming Chiao Tung University, Ta-Hsueh Road, Hsinchu, Taiwan, R.O.C.

yiyijieqq.ee10@nycu.edu.tw, david890611.ee11@nycu.edu.tw, minghan.wang53@gmail.com, dbytsui@nycu.edu.tw

Keywords: silicon carbide, 4 H -SiC, P-type isolation structure, monolithic integration, CMOS, VDMOSFET, edge termination structure

Abstract

In this study, we developed an ion implantation process to create a P-type junction isolation (P-iso) structure, which effectively isolates CMOS and VDMOSFET devices on a single SiC wafer. To ensure a sufficiently high blocking voltage and to prevent punch-through or reachthrough in all p-n junctions during operation, Sentaurus TCAD was used to optimize the conditions for the P-well, N-well, P-iso region, and multi-floating zone (MFZ) design. A high-energy ion implantation, reaching up to 2.5 MeV , was then conducted to verify the breakdown voltage ( ) of the P-iso and MFZ structures. Experimental verification confirms a breakdown voltage (VBD) exceeding 2000 V .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

As SiC device fabrication technology matures, the development of SiC integrated circuits (ICs) has become both possible and attractive [1-4]. The need for SiC CMOS arises from several concerns associated with using Si substrates for circuits that drive power MOSFETs. Si off-chip circuits require long conduction lines to control the gate of power MOS devices, leading to increased area consumption and parasitic effects such as electrical signal overshoot or oscillation caused by parasitic parameters [5]. Additionally, Si ICs lack thermal stability, whereas SiC power devices can operate at high temperatures and in harsh environments [6-7]. Therefore, a heat sink is essential to dissipate heat in hybrid power systems, potentially undermining the exceptional physical properties of SiC .

To integrate planar CMOS with a vertical power MOSFET on a single chip, the N-well of the PMOSFET must be isolated from the n-type substrate that serves as the drain of the power MOSFET. Without this isolation, a significant potential could be conducted to the body of the PMOSFET when the power MOSFET is in blocking mode, leading to malfunction of the CMOS circuits. A monolithic

Fig. 1 Schematic cross-sectional structure of the monolithic integration of CMOS and 600 V VDMOSFET on 4H-SiC using P-iso structure [4].

Fig. 1. Schematic cross-sectional structure of the monolithic integration of CMOS and 600 V VDMOSFET on 4H-SiC using P-iso structure [4].

Fig. 2 Schematic cross-sectional P-iso structure and the four criteria.

Fig. 2. Schematic cross-sectional P-iso structure and the four criteria.

Fig. 3 Main process steps to fabricated the P-iso test structure.

Fig. 3. Main process steps to fabricated the P-iso test structure.

integration of SiC CMOS circuits and 600-V-class VDMOSFET has been demonstrated by using the P -iso structure formed by P -bottom ion implantation followed by n -type epitaxial layer growth as shown in Fig. 1 [8]. Since Al atoms may out-diffuse during the growth of the n -type epitaxial layer and contaminate the epi-tool, it is problematic for production. In light of this, a single epitaxy method combined with high-energy implantation can effectively separate the N-well from the epi-layer, simplifying the process and reducing contamination issues. In this work we demonstrate a P -iso structure formed by high energy ion implantation achieving an isolation ability beyond 2 kV .

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

We primarily used TCAD simulations to introduce the P-iso structure through high-energy ion implantation and conduct a thorough investigation to determine the optimal conditions. Fig. 2 presents a cross-sectional schematic diagram of a PMOSFET featuring the P-iso structure. To ensure isolation under reverse bias, the P -iso structure design must address several factors: (a) reach-through at the N-well/P-bottom and P-bottom/N-epi junctions. (b) punch-through at the P+/N-well and N-well/Pbottom junctions. (c) lateral reach-through at the N-well/P-well and P-well/N-epi junctions. (d) the P-iso edges can withstand the high voltage from the drain of vertical power MOSFET. The lowvoltage CMOS is designed to operate at a supply voltage of 20 V . To ensure flexibility, a higher voltage ( 24 V ) was applied in the simulation. The target voltage rating for the VDMOSFET is 1.7 kV , with the edge termination design requiring a exceeding 2 kV .

According to the simulation results, test structures were designed to verify the 1.7 kV P -iso structure. The main fabrication steps are illustrated in Fig. 3, while Fig. 4 presents the cross-sectional and top views of the test structure. The starting material is an N-type SiC substrate, overlaid with an N-type SiC epitaxial layer doped with nitrogen, featuring a thickness of and a concentration of . The buffer layer is thick with a doping concentration of . The

Fig. 4 (Left) Cross-sectional and (right) top view of the P-iso text structure.

Fig. 4. (Left) Cross-sectional and (right) top view of the P-iso text structure.

surface of this epitaxial layer is (0001) Si-face, angled off-axis toward the direction. In this structure, the electrode potential of the N-well is applied to 24 V , and the P-well to 0 V . Since the P -iso is connected to the P -well, its potential is also 0 V , while a high voltage is applied to the substrate. The actual is determined by the voltage at which the substrate current reaches .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

TCAD simulation began with an ideal one-dimensional parallel plate junction, free of edge corners, was modeled, including the N-well, P-well, and P-bottom, with fixed well conditions. Fig. 5 shows the breakdown voltage as a function of ion implantation energy for the P -bottom at different doses. When the dose is , reach-through occurs in the P -bottom, resulting in a significantly lower than 1.7 kV . As the dose increases beyond , Vbd exceeds 2.4 kV and the breakdown mechanism changes to avalanche breakdown. The results also indicate that higher ion implantation energy reduces the likelihood of reach-through, as increased energy raises both and , leading to a thicker P-bottom layer that is more resistant to reach-through. Later in this paper, the P-bottom implantation dose is maintained at .

Next, the susceptibility of the N -well to punch-through under reverse bias at both the -well junction and the N-well/P-bottom junction must be addressed. The depth of the N-well, influenced

Fig. 5 (Left) Simulated structure and (right) Breakdown voltage as a function of ion implantation energy of the P-bottom with difference doses. (Criterion a)

Fig. 5. (Left) Simulated structure and (right) Breakdown voltage as a function of ion implantation energy of the P-bottom with difference doses. (Criterion a)

Fig. 6 TCAD simulated electrical potential distribution along the cut line A at substrate bias 2000 V. (Criterion b)

Fig. 6. TCAD simulated electrical potential distribution along the cut line A at substrate bias 2000 V. (Criterion b)

by the ion implantation energy of the P-bottom, is critical; insufficient depth could lead to punchthrough during CMOS operation. Simulations were performed using the potential setup shown in Fig. 6, which models a 20 V -operated CMOS inverter in a low-output state under high substrate bias, with the substrate set to 2000 V . When the P-bottom implantation energy is 1.5 MeV or lower, a narrow plateau at the maximum potential can be seen in Fig. 6, indicating a risk of punch-through. To avoid this, it is recommended that the implantation energy exceed 1.5 MeV to ensure the N-well is deep enough to prevent punch-through.

The P-well serves as the pick-up layer for the P-bottom, stabilizing its electric potential and preventing it from remaining in a floating state. The width of the P -well should be kept as small as possible to minimize the layout area it occupies; however, caution must be taken to avoid lateral reach-through if the P -well is too narrow. Fig. 7 shows the relationship between the and the width of the P -well. Though there appears to be no significant dependence between them, likely because the is limited to around 1050 V due to the concentration of the electric field at the lower edge corner of the P -iso structure because edge termination structure is not included in this simulation. We can observe that higher ion implantation energy results in a higher . As the implantation energy

Fig. 7 TCAD simulated breakdown voltage as a function of the width of P-well. (Criterion c)

Fig. 7. TCAD simulated breakdown voltage as a function of the width of P-well. (Criterion c)

Fig. 8 TCAD simulated breakdown voltage as a function of the displacement of P -bottom to P well. (Criterion d)

Fig. 8. TCAD simulated breakdown voltage as a function of the displacement of P -bottom to P well. (Criterion d)

for the P -bottom increases, it penetrates deeper, reducing the overlap between the P -well and P bottom. This reduced overlap decreases the doping concentration gradient at the lower edge corner of the P -iso structure, leading to a higher .

Continue the previous paragraph, we need an edge termination design to protect the corner of the P-bottom and MFZ-JTE is employed in this work. After optimizing the structural design, the width of the JTE was set to , and an 8-zone MFZ configuration was selected. Each zone has a width of , with the spacing between rings set to , and from the innermost to the outermost zone as shown in Fig. 8. The P-bottom is initially aligned with the P-well. The of this edge termination structure is approximately 2000 V , about of the of the parallel plate junction, meeting the blocking voltage requirements. Finally, the relative position between the P -bottom and P -well should also be simulated, as the corner might protrude due to lateral diffusion from implantation or process alignment inaccuracies. A negative displacement of the P bottom effectively extends beyond it, helping to disperse the electric field and increase the . When the P -bottom is displaced by , the is maximized, improving by approximately .
Fig. 9 demonstrates that the isolated PMOSFET exhibits identical transfer characteristics at a substrate bias of either 0 V or 2 kV , indicating complete isolation between the N -well and N -epi. Using the same P-bottom ion implantation conditions, Fig. 10 shows the Vbd as a function of epilayer thickness with varying doping concentrations. This confirms that the high-energy ion implantation method can effectively form a P-iso structure, even for devices with higher voltage ratings.

Fig. 9 TCAD simulated transfer characteristics of a PMOSFET in the isolated N-well at substrate bias of 0 V and 2000 V .

Fig. 9. TCAD simulated transfer characteristics of a PMOSFET in the isolated N-well at substrate bias of 0 V and 2000 V .

Fig. 10 TCAD simulated breakdown voltage as a function of epi-layer thickness with different doping concentration.

Fig. 10. TCAD simulated breakdown voltage as a function of epi-layer thickness with different doping concentration.

The simulation results are verified by the test structure shown in Fig. 3. Fig. 11 shows the SIMS profile of the P -bottom and simulated results by SRIM and TCAD. Both P-bottom profiles are quite similar, with the SIMS-analyzed profile showing a slight tail at the end. The SRIM simulation does not account for channeling effects in the crystal, so the deep tails present in the implanted profile are not evident in the figure. Fig. 12 shows the measured blocking characteristics of the test structures with different P -well width. Low leakage current and around 2 kV is demonstrated. Based on these results, we can conclude that we successfully fabricated the designed structure and achieved the target blocking voltage.

Fig. 11 The Al concentration profiles for the P-bottom, including SIMS, TCAD simulation, and SRIM simulation.

Fig. 11. The Al concentration profiles for the P-bottom, including SIMS, TCAD simulation, and SRIM simulation.

Fig. 12 Measured blocking characterstics of the 1.7 kV P-iso test structure with P-well width of 10,30 , and .

Fig. 12. Measured blocking characterstics of the 1.7 kV P-iso test structure with P-well width of 10,30 , and .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

A P-iso structure for monolithic integration of planar CMOS and 1.7 kV VDMOSFET on 4H-SiC formed by high energy ion implantation is studied. Design parameters are evaluated by TCAD simulation. The better process condition is then verified by actual test structures. A 2 kV blocking capability is achieved. It is believed that the high energy ion implantation method has the potential to be used in isolation above 1.7 kV .

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

This work was supported by the National Science and Technology Council, Taiwan, R. O. C. under the contract No. NSTC 112-2218-E-A49-017. Test structures fabrication were helped by Diodes Taiwan Inc., Nano Facility Center, National Yang Ming Chiao Tung University, and Taiwan Semiconductor Research Institute, National Applied Research Laboratories.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.1.pdf

J.Y. Jiang et al., Demonstration of CMOS integration with high-voltage double-implanted MOS in 4H-SiC, IEEE Electron Device Letters. 42.1 (2020) 78-81.

M. Okamoto et al., First demonstration of a monolithic SiC power IC integrating a vertical MOSFET with a CMOS gate buffer, Proc. 33rd ISPSD. (2021) 71-74.

S.B. Isukapati et al., Monolithic integration of lateral HV power MOSFET with LV CMOS for SiC power IC technology, Proc. 33rd ISPSD. (2021) 267-270.

B.Y. Tsui et al., First integration of CMOS logic circuit, gate driver, and VDMOSFET on a 4H-SiC single chip, in Proc. 34th ISPSD. (2022) 321-324, 2022.

Z. Zeng et al., Comparative study on multiple degrees of freedom of gate drivers for transient behavior regulation of SiC MOSFET, IEEE Transactions on Power Electronics. 33.10 (2017) 8754-8763.

J. Wang, A Comparison between Si and SiC MOSFETs, IOP Conference Series: Materials Science and Engineering. (2020) 012005.

F. Qi et al., Si and SiC power MOSFET characterization and comparison, IEEE Conference and Expo Transportation Electrification Asia-Pacific (ITEC Asia-Pacific). (2014) 1-6.

B.Y. Tsui et al., Design and characterization of the junction isolation structure for monolithic integration of planar CMOS and vertical power MOSFET on 4 H -SiC up to , IEDM. (2022) 9.3.1-9.3.4.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 9-15

doi: 10.4028/p-V5GxAC

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-04

Revised:
2025-08-04

Accepted:
2025-08-05

Online:
2025-09-08

Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

Kai-Wen Hsu , Huai-Lin Huang , Chia-Lung Hung , Yi-Kai Hsiao and Bing-Yue Tsui

Institute of Electronics, National Yang Ming Chiao Tung University ED641, Ta-Hsueh Road, Hsinchu, Taiwan, R.O.C.

Semiconductor Research Center, Hon Hai Research Institute, Taiwan, R.O.C.

djason.yk.hsiao@foxconn.com, bytsui@nycu.edu.tw

Keywords: Schottky barrier diode, MOS Capacitor, Sacrificial Oxidation, Strain-induced damage, Silicon Nitride

Abstract

The impact of silicon nitride ( ) stress on has been investigated. Currentvoltage (I-V) measurements on Schottky barrier diode show that films thicker than 100 nm degrade both the ideality factor and Schottky barrier height. A sacrificial oxidation effectively reduces defects from a -thick layer, but defects persist with films over 300 nm . Interface state density of metal oxide semiconductor capacitor with a 44 -nm-thick gate oxide confirms the effectiveness of sacrificial oxidation in mitigating defects.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

Silicon nitride , renowned for its high strength, hardness, and excellent corrosion resistance, is commonly used in IC manufacturing, such as hard mask and diffusion barrier [1-2]. Previous studies have indicated that the stress induced by at high temperatures may damage the Si surface [3]. Hence, a pad layer is deposited before the layer to mitigate such effects, a practice also observed in SiC device fabrication [4]. However, there is scarce literature on the impact of induced stress on SiC surfaces to support the necessity of pad on SiC . Therefore, we fabricated Schottky barrier diode (SBD) and metal oxide semiconductor capacitor (MOSCap) to assess whether generates defects on SiC and to explore whether sacrificial oxidation can mitigate such issues.

Device Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

The main process flow of SBD is shown in Fig. 1(a). Sample ID and split conditions are listed in Table 1. All samples began with nitrogen-doped off-axis substrate with a thick epitaxial layer. The doping concentration of the epitaxial layer was . After standard RCA cleaning and a final diluted HF dip, films with various thicknesses were deposited by a LPCVD (Low Pressure Chemical Vapor Deposition) system and subsequently annealed at in ambient to simulate the LOCOSiC (LOCal Oxidation of SiC) process [5]. Some samples underwent a sacrificial oxidation (to a thickness of 45 nm ) at in ambient after removal by hot . After removing the sacrificial oxide layer, a 500 -nm-thick PECVD SiO2 layer was deposited as field oxide (FOX). Active areas were defined using photo lithography and wet etching processes. stack was sputter-deposited, patterned and annealed at for 5 minutes in vacuum to form Schottky contact for SBD [6]. We also fabricated MOSCap on samples without sacrificial oxidation. To grow gate oxide, thermal oxidation was conduct at in ambient for 140 minutes, followed by annealing at in a NO ambient ( diluted with ). The capacitance equivalent thickness (CET) of gate oxide is approximately 44 nm . Aluminum was deposited by thermal evaporation and patterned to form the electrode for the MOS capacitor, and all samples finished with the backside aluminum electrode and sintering in ambient.

Table 1 Sample ID and split conditions

Sample ID | Si₃N₄ Thickness (nm) | Sacrificial Oxide Thickness (nm)
Control | 0 | 0
N36S0 | 36 | 0
N100S0 | 100 | 0
N100S45 | 100 | 45
N315S0 | 315 | 0
N315S45 | 315 | 45

Fig. 1 Main process flow and device structure of the (a)SBD (b)MOSCap. Red letters indicate the process step with split conditions.

Fig. 1. Main process flow and device structure of the (a)SBD (b)MOSCap. Red letters indicate the process step with split conditions.

Experimental Results & Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

Fig. 2 shows the current-voltage (I-V) characteristics of the SBDs with -thick and thick layer, respectively. As the layer was deposited directly on SiC substrate, thermal stress generated during the high-temperature process changed the I-V characteristics of the SBD. As shown in Fig. 2, this induced a noticeable rightward shift in the I-V curves, indicating an increase in the Schottky barrier height . The shift is more pronounced in the N315S0 sample compared to N100S0, suggesting that the extent of damage increases with increase of the thickness of the layer. After applying a -thick sacrificial oxidation process, the I-V curve of the N100S45 sample shifts back and closely aligns with that of the control sample, indicating that has returned to a level near its original value. This effective recovery indicates that the damage introduced by the
layer was shallow enough to be removed by a -thick sacrificial oxidation process [7-8]. However, a noticeable deviation remains between the N315S45 sample and the control sample, implying that the damage caused by the layer was more severe and deeper than the removal capability of the sacrificial oxidation process.

Fig. 2 Current-voltage characteristics of the (a) Control, N100S0, and N100S45 (b) Control, N315S0, and N315S45 SBDs.

Fig. 2. Current-voltage characteristics of the (a) Control, N100S0, and N100S45 (b) Control, N315S0, and N315S45 SBDs.

To further investigate this phenomenon, the statistical distributions of the ideality factor ( n -factor) and are depicted in Fig. 3. As previously discussed, the -thick layer leads to an increase in , while having minimal impact on the ideality factor ( n -factor). A 45 -nm-thick sacrificial oxidation layer can effectively mitigate the increase in . In contrast, the deposition of a 315-nm-thick layer without sacrificial oxidation results in poor n -factor and values, along with a broad distribution. The significant variations in both parameters suggest non-uniform stress, likely caused by the thick layer (over 300 nm ), which may crack within the layer itself, leading to uneven stress distribution [3].

Fig. 3 Statistics of (a) ideality factor and (b) barrier height of different samples. The radius of the SBD is . Eight SBDs were measures on each sample.

Fig. 3. Statistics of (a) ideality factor and (b) barrier height of different samples. The radius of the SBD is . Eight SBDs were measures on each sample.

Table 2 Doping concentration and barrier height extracted from reverse curve.

Sample ID | Nsub (cm⁻³) | Φb (eV)
Control | 1.05×10¹⁶ | 1.22
N36S0 | 1.07×10¹⁶ | 1.22
N100S0 | 1.19×10¹⁶ | 2.35
N315S0 | 1.19×10¹⁶ | 4.58

Fig. 4 Reverse-biased capacitance-voltage characteristics of Control, N36S0, N100S0, and N315S0 SBDs.

The reverse biased capacitance-voltage ( ) characteristics measured on SBDs without sacrificial oxidation are shown Fig. 4. The measurements were performed at a frequency of 100 kHz , with the voltage sweeping from 0 V to -1 V , and the doping concentration ( ) and calculated from the curves are presented in Table 2. The curves show that samples N100S0 and N315S0 exhibits significantly lower capacitance compared to the control sample. This decrease in capacitance, associated with an increased Schottky barrier height, suggests the presence of defects introduced by thermal stress. Moreover, the impact on becomes more pronounced with increasing thickness, consistent with our earlier observations from SBD I-V measurements. It is worth noting that the values obtained from the C-V curves are significantly higher than those derived from I-V measurements, implying that additional factors are involved, such as the presence of charge trapping and de-trapping in the defect layer within the SiC substrate. For all samples, the calculated from the curves are close to the doping concentration of the epitaxial layer used in device fabrication, suggesting that most of the epi-layer remains unaffected. However, the values obtained from the C-V curves are unreasonable, with the value for the N300S0 sample even exceeding the bandgap value of [9]. This indicates that a large number of traps exists in the defect layer within the SiC substrate, which are generated by the stress of the thick layer. The trapping and de-trapping of charge carriers result in a significant reduction in capacitance, leading to considerable errors in the extrapolated . In contrast, the curve for the -thick layer ( N 36 S 0 ) closely overlaps with the control. The calculated and the for this sample
are nearly identical to those of the control, indicating that the 36 -nm-thick layer has minimal impact on the SiC .

The defect characteristics introduced by in SiC were investigated using Deep Level Transient Spectroscopy (DLTS), as shown in Fig. 5. The control group and the N36S0 group did not exhibit any significant defect signals. In contrast, the N100S0 group showed a peak around 600 K , with a defect level at and a trap concentration of approximately , corresponding to the defect previously reported to appear in SiC after implantation and radiation exposure [10-11]. The presence of this defect may lead to the slight increase in observed in the and V characteristics of the N100S0 group.

Fig. 5 DLTS spectra of Control, N36S0, N100S0, and N315S0 SBDs.

Fig. 5. DLTS spectra of Control, N36S0, N100S0, and N315S0 SBDs.

In comparison, the N315S0 group demonstrated a more pronounced peak around 560 K , corresponding to a deeper defect level at , associated with the well-known EP2 level, which has been suggested to be related to carbon interstitials [12]. This defect exhibited a significantly higher trap concentration of approximately , which likely contributes to both the notable increase in and the degradation of the n -factor in the I-V characteristics of the N315S0 group, as well as a considerable decrease in capacitance observed in the measurements.

For MOSCaps, high-frequency ( 100 kHz ) and quasi-static capacitance-voltage (C-V) measurements were conducted to calculate interface state density ( ) using the high-low frequency method [9]. The capacitance equivalent thickness (CET) of MOSCap is 44 nm . The energy distribution of is presented in Fig. 6. Both samples show that at 0.2 eV below the conduction band edge is lower than , and they exhibit similar trends within the range of 0.2 eV to 0.6 eV below the conduction band edge. Furthermore, Time-Zero-Dielectric-Breakdown measurements on MOSCaps were conducted, and the current density-voltage (J-V) curves are depicted in Fig. 7. Both samples exhibit similar current rise trends and breakdown characteristics, showing no distinct differences.

Fig. 6 Energy distribution of , extracting by high-low frequency method on MOSCaps.

Fig. 6. Energy distribution of , extracting by high-low frequency method on MOSCaps.

Fig. 7 Time-Zero-Dielectric-Breakdown characteristics of MOSCaps.

Fig. 7. Time-Zero-Dielectric-Breakdown characteristics of MOSCaps.

The rapid increase in leakage current when the electric field exceeds is attributed to FowlerNordheim (F-N) tunneling, which is related to the effective barrier height of the interface [13]. The effective barrier height was evaluated from the curves in the 6 to range using the classical expression for tunneling, which can be described as

where is the electron effective mass in is the electron effective mass in and is the free electron effective mass. The calculated barrier heights are 2.64 eV for the control sample and 2.62 eV for the N100S0 sample, both of which are slightly lower than the theoretical value of 2.7 eV . This discrepancy can be attributed to the presence of interface traps and oxide traps [13-15]. Although no sacrificial oxidation was performed on the MOSCaps, the gate oxide thickness is similar to that of the sacrificial oxide in the SBD N100S45 sample. The defects associated with the -thick film are nearly absent in both the and TZDB measurements for the MOSCaps. These findings suggest that the oxidation process is effective in mitigating the impact of the layers.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

A film thinner than 36 nm deposited directly on SiC generally does not impact the quality of the SiC substrate. However, a film over 100 nm thick can introduce significant stress, damaging the SiC surface layer. The presence of defects resulting from the stress can increase both the ideality factor and the Schottky barrier height. Additionally, charge trapping in the defect layer can lead to inaccurate capacitance measurements and incorrect calculations. The extent of damage is related to the thickness of the layer-a 45-nm-thick sacrificial dry oxidation was able to mitigate the effect from the layer but failed to eliminate defects generated from the layer over 300 nm . Therefore, similar to Si process, it is recommended to insert a pad layer between film and SiC .

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

This work was supported by the National Science and Technology Council, Taiwan, R. O. C. under the contract No. NSTC 112-2218-E-A49-017.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.9.pdf

G.S. May and C.J. Spanos, Fundamentals of Semiconductor Manufacturing and Process Control, Hoboken, NJ: John Wiley & Sons (2006).

Xiao Hong, Introduction to Semiconductor Manufacturing Technology, Prentice Hall Inc., New Jersey, USA (2001).

M. Tamura and H. Sunami, Jpn. J. Appl. 8, 1097 (1972).

C. -L. Hung, B. -Y. Tsui, C.-P Shih, IEEE Transactions on Electron Devices, vol. 69, no. 10, pp. 5742-5748 (2022).

B. -Y. Tsui, T. -K. Tsai, Y. -T. Lu, J. -H. Lin, C. -L. Hung and Y. -X. Wen, in IEEE Transactions on Electron Devices, vol. 68, no. 12, pp. 6644-6647 (2021).

J. -C. Cheng and B. -Y. Tsui, in IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3739-3745 (2018).

Lanni, L., Malm, B. G., Östling, M., & Zetterling, C. M. (2014). Materials Science Forum, vol. 778-780, Trans Tech Publications, Ltd., Feb. 2014, pp. 1005-1008.

K. Kawahara, M. Krieger, J. Suda, and T. Kimoto, Journal of Applied Physics, vol. 108, no. 2, p. 023706 (2010).

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, John Wiley & Sons Singapore Pte. Ltd (2014).

T. Dalibor, G. Pensl, H. Matsunami, T. Kimoto, W. J. Choyke, A. Schöner, and N. Nordell, Phys. Status Solidi A 162, 199 (1997).

Thomas Dalibor, Gerhard Pensl, Tsunenobu Kimoto, Hiroyuki Matsunami, Shankar Sridhara, Robert P. Devaty, Wolfgang J. Choyke,Diamond and Related Materials,Volume 6, Issue 10 (1997).

Katsunori Danno, Tsunenobu Kimoto, J. Appl. Phys. 15 May 2007; 101 (10): 103704.

K. Agarwal, S. Seshadri and L. B. Rowland, in IEEE Electron Device Letters, vol. 18, no. 12, pp. 592-594 (1997).

O. Aviñó-Salvadó, B. Asllani, C. Buttay, C. Raynaud and H. Morel, in IEEE Transactions on Electron Devices, vol. 67, no. 1, pp. 63-68 (2020).

R. Waters and B. V. Zeghbroeck, Appl. Phys. Lett., vol. 76, no. 8, p. 1039 (2000).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 17-25

doi: 10.4028/p-MxQp6y

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-04

Revised:
2025-02-12

Accepted:
2025-02-20

Online:
2025-09-08

Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

Sandra Krause , Aleksey Mikhaylov , Uwe Schroeder , Thomas Mikolajick , Andre Wachowiak

TU Dresden, 01062 Dresden, Germany

Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria

NaMLab gGmbH, Nöthnitzer Straße 64, 01187 Dresden, Germany

sandra.krause@mailbox.tu-dresden.de, aleksey.mikhaylov@infineon.com, uwe.schroeder@namlab.com, thomas.mikolajick@namlab.com andre.wachowiak@namlab.com

Abstract

This study investigates the role of the electrical failure of the film in the breakdown of and stacks. Our findings indicate that the breakdown is governed by the film, regardless of its thickness. This highlights the importance of carefully considering the interfacial layer when using high-k materials in SiC devices. We demonstrate that thicker layers offer several benefits, including reduced leakage, enhanced thermal stability and electrical strength, and decreased trapping. In contrast, stacks with thinner have a higher effective k value, exploiting the benefits of high-k dielectrics. Our experimental results suggest that a layer underlying 30 nm crystalline or provides optimal performance. Furthermore, we present calculations that reveal the trade-off between thickness, k value, and breakdown voltage for a 50 nm thick dielectric stack. Our results imply that a k value exceeding 20 does not yield significant benefits in 50 nm thick /dielectric stacks.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

The use of (dielectric constant ) as a gate dielectric has become a limiting factor in the development of high-performance silicon carbide ( SiC ) power devices. It is widely recognized that replacing with high-k dielctrics can overcome these limitations and offer new opportunities for device optimization [1]. However, the SiC /oxide interface poses a significant challenge. The lattice mismatch between the crystalline dielectric and the SiC substrate is a common issue for most high-k oxides [1], [2], [3]. Furthermore, the natural growth of carbon-rich on SiC during the deposition or annealing of the high-k oxide is unavoidable [4]. Both effects can lead to interface defects, which can significantly deteriorate the device performance [1], [5].

To address the challenges associated with the oxide interface, numerous studies have demonstrated the benefits of intentionally adding a high-quality interfacial film. This interlayer provides several advantages, including a low density of interface states ( ) [6], high channel mobility [7], smooth interface morphology [8], low trap density in the bulk of the film [1], [9] and low frequency dispersion [6]. Additionally, the interlayer provides a high band offset towards the conduction/valence band ( ) of SiC [3], which positively impacts the leakage current [9], [10] and flatband voltage [10]. However, the film reduces the effective k value of the stack [4], which undermines the benefits of introducing high-k dielectrics. To our knowledge, there is a lack of comprehensive studies that explore a wide range of interlayer thicknesses and consider parameters relevant to power devices. Therefore, a conclusion still needs to be drawn regarding the optimal compromise for the interfacial layer thickness. This study aims to bridge this gap by systematically investigating the implications of different thicknesses on power device performance.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

This study investigates the behavior of MOS capacitors with high-k stacks on n-type substrates. Hafnium oxide ( ) or zirconium oxide ( ) films with a target thickness of 30 nm were deposited by atomic layer deposition (ALD) on top of films with thicknesses ranging from 2 to 45 nm (Fig. 1a). The ALD deposition was done at with as oxidant and a tris(dimethylamino)-cyclopentadienyl-Zirconium- precursor for and a tris(dimethylamino)cyclopentadienyl-hafnium- precursor for . Both and are promising materials for high-k dielectric films [1], [2], [8], [12]. The films were deposited and subsequently nitrided to ensure high quality interfaces meeting cutting-edge industry standards. A titanium nitride / titanium / platinum stack was deposited as the top electrode. Following deposition, the samples were annealed in Argon ambient at for 1 minute, resulting in crystallization of the high-k layer (Fig. 1b, c). The layer thicknesses were determined using X-ray reflectometry (XRR) and verified by transmission electron microscopy (TEM). The crystallographic phase of the high-k films was determined from the peak positions in grazing incidence X-ray diffraction measurements (GIXRD). The k value was calculated from the MOS capacitance in the accumulation regime, representing an "effective" k that accounts for the entire dielectric stack, including and the high-k layer. The k value of the high- k film was calculated using an equivalent circuit model consisting of two capacitors in series, the measured layer thicknesses, and the k value of . The leakage current density and the electric breakdown field were determined using current-voltage (IV) measurements. A positive voltage was applied to the top electrode to induce accumulation in the metal / insulator / SiC structure. The was defined at a of .

Fig. 1. (a) Schematic representation of the investigated samples. TEM image of a sample with (b) and ca. and (c) ca. and ca. , revealing the lattice planes of the crystal grains.

Fig. 1. (a) Schematic representation of the investigated samples. TEM image of a sample with (b) and ca. and (c) ca. and ca. , revealing the lattice planes of the crystal grains.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

Stacked capacitors with thicker layers demonstrate a higher and lower k (Fig. 2a), which is attributed to the higher breakdown strength and lower k of . In contrast, capacitors with pure follow the opposite trend because thinner oxide films generally exhibit a higher . The latter was measured on reference capacitors with film only and aligns well with literature values (Fig. 2a) [13]. For the samples with thin layers, the stacks exhibit a higher than the samples. This can be explained by the more suitable band alignment for on SiC [1]: although and have a similar bandgap of 5.7 eV and 5.6 eV , respectively, the conduction band offset between and SiC is 1.8 eV , which is larger than between and . However, for the samples with thicker , the physical distance between the semiconductor and the high-k oxide reduces this effect. As a result, the breakdown of the plays a more significant role: the higher k value of the tetragonal crystalline , [8] compared to the monoclinic crystalline leads to a higher electric field within the film at the same applied voltage. Consequently, the critical breakdown field within the film is reached at lower voltages for the stacks, resulting in a lower .

The breakdown of the film plays a crucial role in the breakdown behavior of the dielectric stack, as illustrated in Figure 2b: the IV curves reach the breakdown condition when the electric field within the film ( ) reaches the breakdown values presented in Fig. 2a [13]. This observation leads to the conclusion that the breakdown governs the breakdown of the stacked dielectric film. A slight deviation towards higher fields can be attributed to the omission of the contribution of the surface potential [15] and the shift in (cf. Fig. 4). EsiO2 was calculated using eq. (7) in [15]

with as the applied voltage, , and the determined from capacitance-voltage measurements.

Fig. 2. (a) Electric breakdown field of and stacks of and high-k dielectric. (b) of the and stacks versus the electric field within the film.

Fig. 2. (a) Electric breakdown field of and stacks of and high-k dielectric. (b) of the and stacks versus the electric field within the film.

The exact breakdown mechanism has been described in detail by Kumta et al. [16]. Our samples exhibit a similar behavior: after the film breakdown, the entire applied voltage drops across the remaining high-k layer. For stacks with thick films, this leads to an immediate breakdown of the stack (1-step breakdown). In contrast, samples with thin reach the breakdown limit in at lower applied voltages. The high-k oxide remains intact, exhibiting a high leakage current, and breaks down subsequently ( 2 -step breakdown). This phenomenon was validated by measuring a monitor current during the dielectric relaxation of the internal polarization within the high-k dielectric [16], i.e., at 0 V applied. The procedure is illustrated in the inset of Fig. 3a. When the externally applied field is removed, a decaying current in the opposite direction to the leakage current can be measured. This relaxation current ( ) stems from free hopping charges that neutralize the internal bound charges that previously caused the polarization of the dielectric. Notably, is negligible for but can be detected in and until the dielectric undergoes a breakdown [16]. The leakage curve and the corresponding monitor current in Fig.3a clearly demonstrate the 2-step breakdown of the stack with and .

For a more comprehensive understanding of the breakdown phenomena of the stacks, I-V measurements were carried out at elevated temperatures (exemplary data for stacks shown in Fig. 3b). For the stacks with thin film, the primary conduction mechanism is trap-assisted tunneling with a significant temperature dependence [17]. At , the is reduced by compared to the measurements at , and the at is increased by four orders of magnitude. For the sample with , Fowler-Nordheim tunneling is the predominant mechanism, which shows much less temperature dependence [17]. For measurements performed at , at remains within the detection limit, and is reduced by only as
compared to measurements at . The reduction of can be attributed to the temperaturedependent Fermi-Dirac distribution of the electrons, which translates to an increased availability of electrons for tunneling at higher temperatures.

Fig. 3. (a) Leakage and relaxation current in the stack of and . The relaxation current was measured after a 1 s delay time. The inset displays the presence of the relaxation current over time. (b) J-E plot for the sample with and measured at temperatures between and .

Fig. 3. (a) Leakage and relaxation current in the stack of and . The relaxation current was measured after a 1 s delay time. The inset displays the presence of the relaxation current over time. (b) J-E plot for the sample with and measured at temperatures between and .

Fig. 4. (a) Consecutive CV measurements of the sample with with . (b) Several CV measurements with different sweep delays, i.e., the time intervals between voltage application and capacitance measurement ( with ). (c) Hysteresis of the first CV sweep for samples with 2 and , depending on the maximum applied bias.

Fig. 4. (a) Consecutive CV measurements of the sample with with . (b) Several CV measurements with different sweep delays, i.e., the time intervals between voltage application and capacitance measurement ( with ). (c) Hysteresis of the first CV sweep for samples with 2 and , depending on the maximum applied bias.

CV measurements were performed to determine the k -value and trapping behavior of the stacks. Stacks with thin exhibit a significant hysteresis between the up-sweep and down-sweep curves (Fig. 4), indicating that electrons from the SiC accumulation layer are trapped at the high-k interface or within the high-k [5]. With every subsequent measurement, the CV curve shifts towards higher voltages, resulting in a higher and smaller hysteresis (Fig. 4a). This implies that trapped electrons are not released during the down-sweep [18]. The shift saturates after a certain number of measurements, indicating that all accessible traps are filled after a specific time.

The hysteresis is found to increase under two conditions i) when the sweep delay of the measurement is increased (Fig. 4b), and ii) when the maximum applied bias is increased (Fig. 4c). The sweep delay refers to the time interval between applying the bias and measuring the corresponding capacitance. At slower sweep rates, the electrons have more time to fill so-called "slow" traps. At higher maximum bias, the electrons possess more energy and can access traps, which are energetically not accessible at lower fields. Both effects lead to an increase in the number of trapped charges, resulting in a larger hysteresis.

The shift of was evaluated over several measurement runs in Fig. 5a. The figure shows the saturation effect mentioned earlier and the difference in behavior for different thicknesses. Notably, the charge trapping is more pronounced in films with thin . In contrast, a thicker film acts as both a physical and an electrical barrier, inhibiting electrons from tunneling towards the high-k oxide [4]. Fig. 5b shows the decline of the hysteresis for thicker films. The hysteresis was measured during the first measurement run. The maximum applied voltage was adjusted to ensure the same field ( ) for all samples, i.e., 8 V for the sample with and 20 V for the sample with . Fig. 5c shows the decline of the , measured at the first up-sweep, for samples with thicker . The ideal , i.e., in complete absence of any trapped, fixed, or mobile charges within the dielectric, depends only on the work function of the electrode metal and the electron affinity of the semiconductor. In our case, for SiC and TiN, it has a value of 1.0 V [19]. Predominantly, the trapped and fixed charges located in the oxide and at the interfaces shift Vfb. Negative charges trapped in the dielectric shift towards higher positive voltages. With thicker interfacial , the trapped charges within the high-k material are further away from the SiC surface which weakens their influence on the voltage shift [5]. Moreover, the shift of towards negative values is associated with an accumulation of positive charges within the [11]. The more negative VFB with thicker could be explained by positive fixed charges in the . The difference between the and series indicates a corresponding difference in fixed charges within the bulk of the high-k or at the high-k/ interface.

Fig. 5. (a) Flatband voltage of consecutive CV runs. (b) CV hysteresis versus thickness. (c) of the first up-sweep in CV measurements versus the thickness of the sample. For all measurements, the maximum applied bias was , i.e., the maximum voltage was adjusted according to the stack thickness.

Fig. 5. (a) Flatband voltage of consecutive CV runs. (b) CV hysteresis versus thickness. (c) of the first up-sweep in CV measurements versus the thickness of the sample. For all measurements, the maximum applied bias was , i.e., the maximum voltage was adjusted according to the stack thickness.

These results highlight the importance of carefully designing the thickness ratio of the and high-k films for a particular application. Therefore, field calculations are presented in Fig. 6. A stack with a total thickness of 50 nm , consisting of a film and a high-k film, was assumed. The thickness of the layer varied from 0 to 50 nm , resulting in the fraction in the stack ranging from to . The k value of the high- k material was varied from 0 to 40 . The electric fields within the two dielectric films at a specific applied voltage were calculated by using eq. (1). The breakdown condition of the stack is reached when the field within the film surpasses the breakdown limit of as presented in [13] and confirmed in Fig. 2a. In both plots, Fig. 6a and b, the curves resemble the breakdown condition for the film, i.e., the voltage at which the field within the film exceeds the breakdown limit. Several effects determine the shape of the curves in both plots: i) a high k value of the high- k oxide, i.e., a strong polarization, pushes the electric field towards the , ii) for a given k value and applied voltage, the electric field in the is lower for a thicker film than for a thin film, iii) thinner films exhibit a higher breakdown field. The last two effects are contrary and lead to the crossing of the curves in Fig. 6a. In this plot, each line shows the expected breakdown voltage for a particular stack combination. The crossing occurs at a range of
k values between 12 and 20 , revealing that in that range, the variation of thickness between 2 and 10 nm has only a small influence on the breakdown voltage. Hence, the favored thickness is as small as possible to maintain a high effective k value. At higher k values, the polarization of the high-k material is so strong that the electric field reached within the film is exceedingly high. Therefore, the ESiO2 must be reduced by increasing the film thickness.

Fig. 6b provides further guidance for the stack composition: To withstand a specified voltage, the stack must be designed in such a way that the combination of its thickness and k value lies above the curve. The area below the curve represents all stack combinations where the electric field within the exceeds the breakdown limit. The background of the graph area visualizes the overall k value of the specific stack combination calculated from the thicknesses and k values by using

Both plots suggest that using high-k materials with in a stack with is not beneficial. This is because either the breakdown voltage is very low or the thickness has to be increased significantly. This, in turn, reduces the effective k value of the stack ( ), which negates the effort of increasing the k value of the oxide stack.

Fig. 6. Theoretical field calculation for capacitors with high-k oxide stacks with as the film thickness, as the k value of the high-k oxide, and as the voltage applied to the entire stack, and flatband voltage . The total stack thickness is constant at 50 nm . (a) The curves represent the breakdown voltage for a stack consisting of a film with the specified thickness and a high- k dielectric with the specified k value. (b) The background color displays the effective k value of the stack. The curves represent the breakdown condition of the film: in stacks that appear below the curve the at the specified voltage is higher than the breakdown field of resulting in a breakdown of the stack.

Fig. 6. Theoretical field calculation for capacitors with high-k oxide stacks with as the film thickness, as the k value of the high-k oxide, and as the voltage applied to the entire stack, and flatband voltage . The total stack thickness is constant at 50 nm . (a) The curves represent the breakdown voltage for a stack consisting of a film with the specified thickness and a high- k dielectric with the specified k value. (b) The background color displays the effective k value of the stack. The curves represent the breakdown condition of the film: in stacks that appear below the curve the at the specified voltage is higher than the breakdown field of resulting in a breakdown of the stack.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

This study demonstrates that in and stacks, the film breaks down first, independent of its thickness. The electrical failure of the film leads to a significant increase in the leakage current and, ultimately, to the breakdown of the stack. With thicker , the FowlerNordheim mechanism dominates the carrier conduction, enabling low leakage and high breakdown field at . However, thick significantly reduces the effective k value of the stack. For a final decision about the most suitable trade-off, Fig. 7 compares the relevant parameters for all the investigated thicknesses. The samples with 7 nm (green area) provide the best compromise between all parameters, including a comparatively high k value. Therefore, we conclude that 7 nm of interfacial below 30 nm of crystalline or offers the best trade-off. For these stacks, the dielectric constant remains high, at 13 for the stack and 11 for the stack. The hysteresis at an applied bias of is reduced by for the and for the samples compared to the stack with 2 nm . The average breakdown fields of the entire stack are and , respectively, which is reasonably high. The leakage current density at for the stacks is and for the stacks. This is well below the leakage limit of widely accepted in literature [20].

Fig. 7. Comparison of (a) and (b) samples with all 5 investigated thickness values. For clarity, the graph axes are defined such that the least favorable values are centralized. The desired metrics, e.g., high EBD and low Jleak, are furthest away from the center. Consequently, a larger area encompassed by a sample indicates a more suitable performance.

Fig. 7. Comparison of (a) and (b) samples with all 5 investigated thickness values. For clarity, the graph axes are defined such that the least favorable values are centralized. The desired metrics, e.g., high EBD and low Jleak, are furthest away from the center. Consequently, a larger area encompassed by a sample indicates a more suitable performance.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

The results highlight the importance of thoughtfully designing the thickness ratios of the and high-k films in dielectric stacks. Theoretical calculations of the electric fields in a 50 nm stack indicate that the k value of the high- k material should be lower than 20 to avoid early breakdown due to breakdown.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

This work was co-financed by the European Union and from tax revenues on the basis of the budget adopted by the Saxon State Parliament.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.17.pdf

A. Siddiqui, R. Y. Khosa, and M. Usman, "High-k dielectrics for 4H-silicon carbide: present status and future perspectives," J. Mater. Chem. C, vol. 9, no. 15, Art. no. 15, 2021.

M. Nawaz, "On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs," Active and Passive Electronic Components, vol. 2015, pp. 1-12, Dec. 2015.

J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," J. Vac. Sci. Technol. B, vol. 18, no. 3, Art. no. 3, 2000.

J. Robertson, "High dielectric constant oxides," Eur. Phys. J. Appl. Phys., vol. 28, no. 3, pp. 265291, Dec. 2004.

S. M. Sze and K. K. Ng, Physics of semiconductor devices, Third edition. Hoboken, NJ: WileyInterscience, 2007.

C.-M. Hsu and J.-G. Hwu, "Investigation of carbon interstitials with varied SiO 2 thickness in HfO2/SiO2/4H-SiC structure," Applied Physics Letters, vol. 101, no. 25, p. 253517, Dec. 2012.

J. Urresti, F. Arith, S. Olsen, N. Wright, and A. O'Neill, "Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO2 / Gate-Stack," IEEE Trans. Electron Devices, vol. 66, no. 4, pp. 1710-1716, Apr. 2019.

M. Gutowski et al., "Thermodynamic stability of high- dielectric metal oxides ZrO 2 and HfO2 in contact with Si and SiO2," Applied Physics Letters, vol. 80, no. 11, Art. no. 11, Mar. 2002.

K. Y. Cheong, J. H. Moon, D. Eom, H. J. Kim, W. Bahng, and N.-K. Kim, "Electronic Properties of Atomic-Layer-Deposited Thermal-Nitrided Stacking Dielectric on 4 H SiC ," Electrochem. Solid-State Lett., vol. 10, no. 2, p. H69, 2007.

R. Mahapatra, A. K. Chakraborty, A. B. Horsfall, N. G. Wright, G. Beamson, and K. S. Coleman, "Energy-band alignment of HfO2SiO2SiC gate dielectric stack," Applied Physics Letters, vol. 92, no. 4, p. 042904, Jan. 2008.

K. Iwamoto et al., "Experimental evidence for the flatband voltage shift of high-k metal-oxidesemiconductor devices due to the dipole formation at the high-k/SiO2 interface," Applied Physics Letters, vol. 92, no. 13, p. 132907, Mar. 2008, doi: 10.1063/1.2904650.

S. Krause, T. Mikolajick, and U. Schroeder, "Improving Thick Films for SiC Power Devices by Si, Y and La Doping," SSP, vol. 359, pp. 29-34, Aug. 2024.

J. W. McPherson, "Increases in Lorentz Factor with Dielectric Thickness," WJCMP, vol. 06, no. 02, pp. 152-168, 2016.

C. Richter et al., "Si Doped Hafnium Oxide-A 'Fragile' Ferroelectric System," Adv. Electron. Mater., vol. 3, no. 10, Art. no. 10, Oct. 2017.

R. G. Southwick, J. Reed, C. Buu, R. Butler, G. Bersuker, and W. B. Knowlton, "Limitations of Poole-Frenkel Conduction in Bilayer MOS Devices," IEEE Trans. Device Mater. Relib., vol. 10, no. 2, Art. no. 2, Jun. 2010.

A. Kumta, Rusli, and J. H. Xia, "Breakdown phenomena of Al-based high-k dielectric/SiO2 stack on 4H-SiC," Applied Physics Letters, vol. 94, no. 23, p. 233505, Jun. 2009.

A. Paskaleva, D. Spassov, and D. Dankovic, "Consideration of conduction mechanisms in highk dielectric stacks as a tool to study electrically active defects," Facta Univ Electron Energ, vol. 30, no. 4, Art. no. 4, 2017.

A. Vasilev et al., "Oxide and Interface Defect Analysis of lateral 4H-SiC MOSFETs through CV Characterization and TCAD Simulations," MSF, vol. 1090, pp. 119-126, May 2023.

R. G. Southwick and W. B. Knowlton, "Stacked Dual-Oxide MOS Energy Band Diagram Visual Representation Program (IRW Student Paper)," IEEE Trans. Device Mater. Relib., vol. 6, no. 2, pp. 136-145, Jun. 2006.

J. Weckbrodt, N. Ginot, C. Batard, and S. Azzopardi, "Monitoring of Gate Leakage Current on SiC Power MOSFETs: An Estimation Method for Smart Gate Drivers," IEEE Trans. Power Electron., vol. 36, no. 8, Art. no. 8, Aug. 2021.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 27-32

doi: 10.4028/p-S2Zh3j

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-08-18

Accepted:
2025-08-18

Online:
2025-09-08

Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

Marilena Vivona , Patrick Fiorenza , Giuseppe Greco , Salvatore Di Franco , Gabriele Bellocchi , Paola Mancuso , Simone Rascunà , Antonio Massimiliano Mio , Giuseppe Nicotra , Filippo Giannazzo and F. Roccaforte

CNR-IMM, Strada VIII n.5, Zona Industriale, I-95121, Catania, Italy

STMicroelectronics, Stradale Primosole 50, I-95121, Catania, Italy

marilena.vivona@imm.cnr.it, patrick.fiorenza@imm.cnr.it, giuseppe.greco@imm.cnr.it, salvatore.difranco@imm.cnr.it, gabriele.bellocchi@st.com, paola.mancuso@st.com, simone.rascuna@st.com, antonio.mio@imm.cnr.it, giuseppe.nicotra@imm.cnr.it, jfilippo.giannazzo@imm.cnr.it, kfabrizio.roccaforte@imm.cnr.it

* corresponding author

Abstract

In this work, we investigated the electrical properties evolution of Schottky contacts following thermal annealing treatments at temperature up to . The electrical characterization under forward and reverse bias revealed a reduction of the barrier height from 1.45 eV (as-deposited contact) to 1.30 eV ( -annealed contact), with the presence of inhomogeneity in the contact, while the leakage current followed a thermionic-field emission (TFE) model after annealing at and presented a significant increase for the -annealed contact. The electrical characterization was associated with microstructural analyses, which highlighted an enlargement of the grains forming the structure of the Mo-film and the presence of voids near the interface. These observations can be at the base of the variation in the electrical behavior of the contact.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

Nowadays, Schottky-barrier diode (SBD) on is an established technology used in several real-world applications [1]. Although this large use, additional improvement is still possible for a fully exploitation of the potentialities. Essentially, the properties of the metal/ contact are at the base of the SBD performance and the achievement of a superior control on this interface drives an optimization of the use of the SBD. Over the last two decades, various approaches have been considered for gaining control in this system. Particular attention was paid to the choice of the metal and its evolution with thermal annealing in the Schottky contact formation [2,3]. Recently, the exploration of low-work function materials, such as W and Mo-based contacts, has demonstrated promising results for minimizing the power dissipation of Schottky diodes and offering good thermal stability [3,4]. In particular, Mo showed a large variability of the Schottky barrier height ( ) value dependent on the passivation treatment of the surface [5] or the temperature of the metal deposition [6], with the varying between 1.0 and 1.5 eV . From a structural point of view, Mo can readily form carbides and silicides and for that reason Mo-film deposited with Si or C element can be useful in preventing the reaction with SiC surface. For example, Mo-based contacts containing C were recently investigated, either deposited in laminated layers or from Mo-C alloyed targets [7,8], demonstrated stability of the electrical characteristics even at high annealing temperature. However, the origin of this electrical behavior is not clear and additional investigation on the interface is necessary: on the one hand to correlate the electrical properties of the contact with the process, on the other hand to link the electrical behavior also to the microstructural properties, for better understanding the role of the and C in the contact formation.

In this study, we follow the evolution of the electrical properties of contacts with increasing the annealing temperature up to . The electrical characterization is combined with a microstructural analysis to shed light on the interface behavior and possible reactions to finally explain the electrical behavior.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

The starting material for this study consisted in a wafer with a n -type epitaxial layer (doping concentration of ) grown onto a -doped substrate. Schottky diodes were fabricated starting from the deposition of a large-area back-side Ohmic contact by sputtering 100 nm thick Ni layer, followed by a rapid thermal annealing (RTA) treatment in a furnace at in for 60 s [9]. Then, for the front-side Schottky contact, 80 nm -thick Mo film was sputtered with the contact area defined by optical photolithography, lift-off processing steps and RTA treatments for 10 min in at temperatures of 700 and . On these annealed samples, the electrical characterization under forward and reverse bias was carried out for a set of equivalent diodes by I-V measurements in a Karl-Suss MicroTec probe station equipped with a parameter analyzer. For comparison, the as-deposited contact was also investigated. The temperature dependence of both forward and reverse I-V characteristics (I-V-T) was studied for selected samples. A microstructural analysis was associated to the electrical characterization, with lamellae for the annealed samples prepared by a Dual Beal Thermofisher Helios 5 focused ion beam (FIB) and analyzed by probe Cs corrected JEOLARM200F Scanning Transmission Electronic Microscope (S/TEM). A Gatan GIF Quantum ER system was also used for electron energy loss spectroscopy (EELS) measurements.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

Firstly, the investigation on the electrical behavior of the contacts under forward and reverse bias is reported in Fig. 1. Specifically, Fig.1a shows the forward current density-voltage (J-V) characteristics, representative of a set of 10 diodes, for the as-deposited, and annealed contacts, while the significant parameters of the contact (i.e. the Schottky barrier and ideality factor n ) extrapolated from the linear part of the curves in Fig. 1a according to the thermionic emission (TE) model [10], are reported in Fig.1b. A preliminary statistics study demonstrated the possible occurrence of double-barrier curves mostly after annealing at . This aspect requires however further investigation and will be the object of a future focused work. The J-V characteristics under reverse bias are plotted in Fig.1c.

Fig. 1. a) Forward J-V curves of the as-deposited, 700 and -annealed Schottky contacts. b) Ideality factor and Schottky barrier height for the as-deposited and annealed contacts. c) Reverse J-V characteristics of the as-deposited, and -annealed Mo/4H-SiC Schottky contacts.

Fig. 1. a) Forward J-V curves of the as-deposited, 700 and -annealed Schottky contacts. b) Ideality factor and Schottky barrier height for the as-deposited and annealed contacts. c) Reverse J-V characteristics of the as-deposited, and -annealed Mo/4H-SiC Schottky contacts.

We observed that the as-deposited and -annealed contacts have similar electrical characteristics, whereas a slight shift towards lower voltage appeared for the J-V curves of the -annealed contact. As shown in Fig.1b, up to annealing at only a slight variation of the , from 1.45 eV to 1.40 eV occurred while is 1.30 eV for the -annealed contact. The ideality factor n is low, including for the -annealed sample. Regarding the reverse characteristics reported in Fig.1c, the -annealed contact featured an increase of the leakage current from the as-deposited, suggesting the predominance of a thermionic field emission mechanism (TFE) [11] for the current transport. Instead, a different electrical behavior under reverse bias was observed for the -annealed sample, with an increase of the leakage current mainly over 15 V . More quantitative analyses are ongoing to better understand the physical mechanisms ruling the transport under reverse bias. In order to highlight the variation of the forward and reverse characteristics for the set of measured diodes in the two cases ( and -annealed contacts), Fig. 2 reports the forward J value at 0.25 V against the reverse J value at 40 V .

Fig. 2. Forward current density at 0.25 V versus reverse current density at 40 V for a set of diodes annealed at and .

Fig. 2. Forward current density at 0.25 V versus reverse current density at 40 V for a set of diodes annealed at and .

Clearly, the -annealed contact presented a larger statistical distribution than that related to the -annealed contact, supposed related to a certain level of inhomogeneity of the metal/semiconductor interface.
Then, a current-voltage-temperature (I-V-T) study was performed on the as-deposited, and -annealed contacts with measurements temperature varying between and . The J-V curves acquired at varying temperature for the three cases are reported in Fig.3, respectively.

Fig. 3. a) Forward J-V characteristics acquired in a range of temperature varying between and (step of ) for a) as-deposited -SiC contact annealed, b) and c) annealed contacts.

Fig. 3. a) Forward J-V characteristics acquired in a range of temperature varying between and (step of ) for a) as-deposited -SiC contact annealed, b) and c) annealed contacts.

The temperature-dependence of the ideality factor n and Schottky barrier , derived from the analysis of the forward characteristics, is plotted in Fig.4. A similar behavior is observed by the nand temperature-dependence for the three cases.

Fig. 4. a) Forward J-V characteristics acquired in a range of temperature varying between and (step of ) for a) as-deposited -SiC contact annealed, b) and c) annealed contacts.

Fig. 4. a) Forward J-V characteristics acquired in a range of temperature varying between and (step of ) for a) as-deposited -SiC contact annealed, b) and c) annealed contacts.

Finally, we combined the electrical characterization of the and -annealed contacts to a microstructural investigation by bright-field S/TEM analysis. The micrographs of the two annealed contacts are shown in Figs. 5a and 5b.

Fig. 5. Bright-field S/TEM of a) and b) thermal annealed Schottky contacts.

Fig. 5. Bright-field S/TEM of a) and b) thermal annealed Schottky contacts.

This analysis demonstrated a different situation occurred after and annealing: in the first case, an unreacted surface is still present, keeping the Mo layer in the metallic form with grain sizes in the range of few tens of nanometers and providing continuous and homogeneous interface. Instead, at we observed the presence of columnar grain in the Mo-film, therefore with a vertical size of about 75 nm . Noteworthy, even upon treatment at high temperature ( ), it was not observed a reaction between the Mo-film and the semiconductor interface. In addition to the variation of the grain size, the Mo-films in the contact annealed at highest temperature revealed the presence of less dense (brighter) areas near the interface, as consequence of the re-organization of this film, as confirmed by the associated High-Angle annular Dark-Field (HADDF) imaging (not shown here). Chemical analyses performed by EELS in the interfacial region demonstrated that no reaction occurred between the Mo and , while the brighter regions observed at can be
associated to voids formed as a consequence of the grains' enlargement. The different structure of the Mo film and interface morphology can explain the evolution of the electrical characteristics of the contacts annealed at .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

In this paper, we performed an electrical characterization on Schottky diodes. In particular, the electrical properties of the contacts following thermal annealing treatments at temperature up to were studied under forward and reverse bias. Under forward bias, a reduction of the barrier height from 1.45 eV (as-deposited contact) to 1.30 eV ( -annelaed contact) was observed, with the presence of a certain level of inhomogeneity for all the contacts. Under reverse bias, leakage current followed a thermionic-field emission (TFE) model after annealing at , whereas it presented a significant increase after 15 V for the -annealed contact. Microstructural analyses were carried out by S/TEM analyses, highlighted an enlargement of the grains forming the structure of the Mo-film and the presence of voids near the Mo/ interface. These observations occurring at the interface can explain the variation in the electrical behavior of the contact.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

This work is supported by the European Union Next Generation EU program through the MURPNRR project SAMOTHRACE (No. ECS00000022). This paper has been partially supported by AdvanSiC. The AdvanSiC project has received funding from the European Union's Horizon Europe programme under grant agreement No 101075709. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union. Neither the European Union nor the granting authority can be held responsible for them.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.27.pdf

F. Roccaforte, P. Fiorenza, G. Greco, R. Lo Nigro, F. Giannazzo, F. Iucolano, M. Saggio, Emerging trends in wide band gap semiconductors ( SiC and GaN ) technology for power devices, Microelectron. Eng. 187-188 (2018) 66-77.

R. Yakimova, C. Hemmingsson, M.F. MacMillan, T. Yakimov, E. Janzén, Barrier Height Determination for n-Type 4H-SiC Schottky Contacts Made Using Various Metals, J. Electron. Mater. 27 (1998) 871-875.

M. Vivona, G. Bellocchi, R. Lo Nigro, S. Rascunà, F. Roccaforte, Electrical evolution of W and WC Schottky contacts on 4H-SiC at different annealing temperatures, Semicond. Sci. Technol. 37 (2022) 015012 1-8.

R. Rupp, R. Elpelt, R. Gerlach, R. Schomer, M.; Draghici, A new SiC diode with significantly reduced threshold voltage. In Proceedings of the 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 28 May-1 June 2017; pp. 355-358.

A. B. Renz, V. A. Shah, O. J. Vavasour, Y. Bonyadi, F. Li, T. Dai, G. W. C. Baker, S. Hindmarsh, Y. Han, M. Walker, Y. Sharma, Y. Liu, B. Raghothamachar, M. Dudley, P. A. Mawby, P. M. Gammon, The improvement of Schottky diodes via a P 2 O 5 surface passivation treatment, J. Appl. Phys. 127 (2020) 025704 1-9.

T. N. Oder and S. B. Nardella, Effects of deposition temperature on Mo/SiC Schottky contacts, AIP Advances 12 (2022) 025117 1-6.

T. Suzuki, H. Wakabayashi, K. Tsutsui, H. Iwai, K. Kakushima, Laminated Mo/C Electrodes for 4H-SiC Schottky Barrier Diodes with Ideal Interface Characteristics, IEEE Electron. Dev. Lett. 37 (2016) 618-620.

Z.-Y Yang, Y. Wang, X. Li, J. Yang, D. Shi, F. Cao, Thermal stability of Mo-C alloy Schottky contacts on n-type 4H-SiC, Microelectron. Eng. 239 (2021) 111531 1-5.

M Vivona, G Greco, F Giannazzo, R Lo Nigro, S Rascunà, M Saggio and F Roccaforte, Thermal stability of the current transport mechanisms in Ni-based Ohmic contacts on n- and p-implanted 4H-SiC, Semicond. Sci. Technol. 29 (2014) 075018 1-7.

S. M. Sze, and K. N. Kwok, Physics of Semiconductor Devices; John Wiley & Sons: Hoboken, NJ, USA, 2007.

F. A. Padovani and R. Stratton, Field and thermionic-field emission in Schottky barriers. SolidState Electron. 9 (1966) 695-707.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 33-40

doi: 10.4028/p-7Bd8tb

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Revised:
2025-08-19

Accepted:
2025-08-19

Online:
2025-09-08

Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

The original version of this paper is available on https://www.scientific.net/MSF.1158.33.pdf

Xavier Pagès , Simon van der Linde , Jeppe Oterdoom , Mark Steltenpool , Vladimir Kuznetsov , Jaap Beijersbergen , Mickael Sanchez , Sebastien Kerdiles

Levitech b.v; Neonweg 42; 1362AE Almere, The Netherlands

Université Grenoble Alpes, CEA-LETI, Grenoble, France

xavier.pages@levitech.nl, simon.van.der.linde@levitech.nl, jeppe.oterdoom@levitech.nl; mark.steltenpool@levitech.nl; Vladimir.kuznetsov@levitech.nl; jaap.beijersbergen@levitech.nl; mickael.sanchez@cea.fr; sebastien.kerdiles@cea.fr

Keywords: Silicide top contact; rapid thermal anneal (RTA), conductive heating

Abstract

This paper explains the potential of a heat conduction based RTA (Rapid Thermal Anneal) system (Levo) to overcome the main shortcomings of conventional lamp heated tools systems for silicide top contact anneal during SiC MOSFET device fabrication. The advantage of conductive heating is that the radiation-related properties, like transparency of the wafer, does not play a role, and consequently, that the whole rapid thermal anneal becomes independent of wafer type. In this study SiC wafers and Si wafers (both 200 mm ) were annealed consecutively without any system adjustment. The silicon wafers were used to qualify the process (contamination / within-wafer uniformity and wafer-to-wafer repeatability).

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.33.pdf

SiC crystal is today one of the most promising semiconductor material for next-generation of hightemperature and high frequency electronic devices applications [1]. It has a wide band gap ( 3.3 eV ), a high breakdown field of ( ; 10 times higher than Silicon), a high thermal conductivity ( ), a high thermal stability [2] and a very high carrier mobility and electron saturation drift velocity ( ). As a matter of fact, enormous progress has been recorded in power devices like Metal Oxide Semiconductor Field Effect Transistor (MOSFET) over the last decade [4 .

Today the fabrication of vertical silicon carbide (SiC) MOSFET devices (DMOS and UMOS) involves multiple annealing steps along the process flow. It is interesting to note that the techniques used to anneal SiC wafers differ greatly depending on the progress in the manufacturing process.

First, the formation of the doped areas ( p channel / source / etch termination) requires post implantation annealing process at high temperature (typically between and ). This step is typically performed in batch furnaces for several minutes. These long anneals are possible because the diffusion coefficients of dopant in the SiC wafer remains extremely low, even at very high annealing temperatures (above ) [7]. Nevertheless, two challenges are usually associated with the annealing of ion implanted areas. First, the generation of crystal structure damages that, for high-dose implantation, can lead to amorphization of the material. This effect will be reduced if implantation is performed at high temperature (typically around ). Second, the requested high temperature annealing of or higher, causes Si evaporation and surface roughness. This surface degradation process is avoided by depositing a dense carbon film by sputtering prior to activation anneal. Because of the two above mentioned issues, both source and base regions can sometimes be formed epitaxially (UMOSFET) which enable the fabrication process free of ionimplantation and the associated high-temperature annealing, preventing therefore the device from surface degradation.

Second, the formation of the top contact (silicided based) which is typically done with lamp-based RTA (Rapid Thermal Anneal) systems. A common technique to form contacts on SiC is to deposit a suitable metal in a heavily doped n - or p -type region, followed by post-deposition anneal typically at . The most promising material is nickel ( Ni ) for n-type regions and aluminum-titanium (Al-Ti) for p-type region. SiC devices need contacts with a contact resistance ( ) in the range of or lower [13]. The strongly depends on the contact material, the doping level, and annealing conditions. The main challenge lamp RTA systems face when processing transparent SiC wafers is to meet the temperature control requirements, which originate from the fact that SiC wafers are transparent to IR radiation and must be inserted into graphite boxes. This complicates wafer temperature measurement, making "true" RTA impossible (the thermal mass of graphite box considerably slows down wafer heat up and cooldown rates) and enhances the sensitivity to residual oxygen contamination. Other important parameters are the surface preparation before metal deposition [8, 9], surface roughness [10], organic and metal contamination [11], natural oxide formation [11] and graphitized skin [12],

Finally, the formation of the bottom contact is performed using laser annealing system after wafer backside thinning. Wafer grinding was introduced to reduce the resistive contribution of the substrate. It has been calculated that thinning the wafer thickness from 350 down to decreases the resistive contribution down to of the total RON [6]. The tunable laser energy density combined with ultrashort irradiation time allows heat accumulation at the wafer surface only. Therefore, laser annealing in back Ohmic contact formation enables the possibility to complete the device front side first, and then to process the back-side contact without detrimental effects.

In the following sections we will explain the potential of conductive based RTA system (Levo) to overcome the main shortcomings of conventional lamp heated systems for silicide top contact anneal during SiC MOSFET device fabrication. The advantage of conductive heating is that the radiationrelated properties, like transparency of the wafer, does not play a role, and consequently, that the whole RTA process becomes independent of wafer type.

Theoretical Considerations

The original version of this paper is available on https://www.scientific.net/MSF.1158.33.pdf

Current lamp-based systems use pyrometers and measure the substrate emissivity to monitor the heating power to control the substrate temperature during anneal. Unfortunately, this procedure does not work when, like for SiC wafers, the substrate is transparent to IR radiation or when large emissivity variations are present on the device side of the wafer. For that reason, it makes sense to consider conductive heating systems that are not sensitive to substrate type and not sensitive to variations in emissivity (Levo RTA systems).

Since the contribution of convection is very small, the general heat flux can be written like in Equation 1. The first and second terms on the right represent the heat transfer ( ) from the reactor surface to the wafer from the conductive and radiative contributions, respectively. All the parameters shown in equation 1 , with the exception of the emissivity , are bulk properties of materials and material dimensions. The heat transfer mechanism is strongly depending on the gap distance ( g ) between the wafer and the reactor surface. In the case of Levitech RTA systems, the gap distance ( g ) is typically in the range of 0.15-0.3 mm (depending on wafer thickness). Annealing in Levo RTA system is therefore dominated by the conduction which has strong technological advantages for processing of transparent SiC wafers.

Equation 1: Heat flux from the reactor to the wafer:. is the rate at which the temperature of the wafer changes with time. The factor 2 stems from the fact that the wafer is heated from both sides.
specific density of the wafer;
specific heat capacity of the wafer;
wafer thickness;
time (s);
temperature of the reactor ;
wafer temperature;
thermal conductivity of the bearing gas ,
gap distance between wafer and hot reactor wall
emissivity of the wafer
Stephan-Boltzmann constant
In figure 1, Equation 1 is solved as a function of time. In this calculation, a thick) SiC wafer is heated from to a process temperature of .

Fig.1. Heating profile of thick with Levitor RTA system for process temperatures of .

Fig.1. Heating profile of thick with Levitor RTA system for process temperatures of .

The SiC wafers are directly inserted inside the reactor chamber without using graphite boxes. This allows to skip the (too) long purging step prior anneal. The heating and cooling speeds are high (> ) (see figure 1). High heat-up and cool-down rates enable a perfect control of the silicidation process because the uncontrolled silicidation, wich is occuring during heat up (and natural cooling), of the SiC wafer is avoided. The absence of a stabilization step during heat up (in figure 1 the SiC wafer is annealed directly from room temperature to process temperature) combined with a forced cooldown guarantee a high throughput.

Experimental Setup and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.33.pdf

In this study both SiC wafers with a thickness of and Si wafers were annealed consecutively without any system adjustment with a 200 mm Levo conductive RTA system at CEA Leti.

The Levo system heats the wafer by placing it in an axial gas bearing in between two heated reactor gas divider (see figure 2). Gas flowing through a radial gas bearing keeps the wafer centered in the horizontal plane. Wafer centering is achieved by building-up a pressure difference along the wafer
edge whenever the wafer is shifted out of its central position. Such construction ensures that the wafer never touches the reactor gas divider. The thin and uniform gas layer ensures very fast wafer heating through gas conduction. The wafer heat-up rate is determined by the thermal conductivity of the bearing gas. At a gap of , when nitrogen is used, a heat up rate of approximately is realized. (see figure 1), however when helium is used, heat-up rates up to are reached. Reactive gases ( for surface Nitridation, for metal reduction or surface cleaning process) or inert gas like Argon (when nitrogen sensitive ALD layers are present on the wafer before anneal) can also be part of the gas system for Rapid Thermal Process (RTP).
After annealing in the reactor, the wafer is transferred to a cooling station by a quartz wafer carrier enclosed by a quartz guard (edge) ring. This guard ring prevents slip (crystal defects at the edge of the wafer) during transport.
In the cooling station, the same bearing principle is used as in the reactor section. Similar to the reactor section, different gases can be used as bearing gas

Fig. 2. Cross section of the Levitor chamber with a wafer being processed.

Fig. 2. Cross section of the Levitor chamber with a wafer being processed.

Figure 3 shows the 200 mm SiC wafer and the 200 mm Si wafer before process in the atmospheric front end of the Levitor 200 mm system. The silicon wafers were used to qualify the process.

Fig. 3.

Fig. 3.

These wafers were annealed at for 60s under nitrogen in order to get a representative Nickel silicidation process step. The associated wafer temperature transient and pressure measurement during anneal are shown in figure 4.

Fig. 4. left wafer temperature transient of 200 mm SiC and 200 mm Si wafers annealed at for 60s in nitrogen; right Reactor pressure during process.

Fig. 4. left wafer temperature transient of 200 mm SiC and 200 mm Si wafers annealed at for 60s in nitrogen; right Reactor pressure during process.

When soak anneal processes are carried out in the Levo RTA system, the wafer temperature becomes equal to that of the heating reactor gas divider within a few seconds. Because the wafer cannot exceed reactor surface temperature, temperature overshoot is physically impossible. The silicon wafer reaches the process setpoint temperature in seconds whereas the SiC wafer requires seconds to be at process temperature. This difference arises from the different specific heat capacity Cp (see equation 1) of silicon and 4 H SiC crystal at high temperature (see figure 5). The wafer cooling process exhibits 2 different slopes. The first part of the cooling (right after the 60s soak process) depicts the radiative cooling of wafers during their transfer from the reactor to the cooling station. This step takes exactly to transfer the wafer from reactor to cooling station and 1 s to close the cooling station). The slower radiative cooling rate of the SiC wafer is caused by the high heat capacity of SiC . After the cooling station is closed, a forced cooling through conduction enables fast wafer cooling and it takes less than 10s to reach temperature of lower than for wafer unloading.
The right part of figure 4 shows the partial pressure inside the reactor during process for both the 200 mm silicon (first peak) and the 200 mm SiC wafer ( peak). The difference in peak pressure results from difference in wafer thickness, the SiC wafer was only thick whereas the Silicon wafer is thick. The distance between the upper and lower surfaces of the reactor is fixed. Consequently, the gap distance between reactor and wafer (see figure 2) is slightly larger for the SiC wafer which results in a lower pressure build up during anneal.

Fig. 5. Specific heat capacity Cp of silicon and 4 H SiC wafer as a function of temperature

Fig. 5. Specific heat capacity Cp of silicon and 4 H SiC wafer as a function of temperature

High heat-up and cooldown rates enable a perfect control of the silicidation process. The uncontrolled silicidation wich is occuring during slow heat-up (and during radiative cooling) of the SiC wafer is avoided. This is important because SiC MSOSFET silicided top contacts are generally performed
using a two step annealing process (RTA1 at selective etch to remove unreacted nickel / RTA2 at ). In this two-step approach, the PVD Ni layer is deposited on the entire wafer surface and an uncontrolled RTA1 anneal will cause excessive Ni diffusion leading to undefined Ni silicide thickness after RTA1. This effect is a well known issue on advanced planar silicon transistor at advanced technology node.

Figure 6 shows the estimated throughput for SiC wafers annealed with process time representative of silicide contact.

Fig. 6. Estimated throughput for SiC wafer processed in Levitor as a fonction of process time.

Fig. 6. Estimated throughput for SiC wafer processed in Levitor as a fonction of process time.

The absence of both long purging time prior heat-up and stabilization step during heat-up (in figure 1 the SiC wafers are annealed directly from room temperature to process temperature) combined with a forced cooldown guarantees a high throughput.

The silicon wafers were used to qualify the process (contamination, within-wafer uniformity and wafer-to-wafer repeatability). Table 1 reports the metal contamination levels before and after annealing. The residual oxygen level during anneal was less than 1 ppm .

Table 1. Contamination level atoms/ (VPD ICPMS) before and after anneal at for 60 s in

| Before anneal | After anneal
Al; Ca; Co; Cu; Na;Ta; Ti; V;W; Zn | Not detected | Not detected
Cr | Not detected | 1,5E9
Fe | 6,4E8 | 5,8E8
Mn | Not detected | 6,3E7
Ni | Not detected | 5,2E9

The within-wafer uniformity and wafer-to-wafer repeatability was measured on high energy ( 30 keV ) Arsenic implanted silicon wafers. The advantage of such deep implant is that the dopant activation process remains sensitive to temperature variation even after long soak annealing time at . It is therefore considered as a good indicator of the wafer temperature uniformity during silicidation anneal at for 30 s . The anneals were performed without any process tuning (i.e in the same configuration as for the SiC wafer). Figure 7 shows the sheet resistance measurements after annealing.

Fig. 7. Arsenic_1E16 As _ 30 keV implanted wafers after anneal at for 30 s . the left hand scale is the sheet resistance ( 5 mm edge exclusion) the right hand scale shows the wafer uniformity.

Fig. 7. Arsenic_1E16 As _ 30 keV implanted wafers after anneal at for 30 s . the left hand scale is the sheet resistance ( 5 mm edge exclusion) the right hand scale shows the wafer uniformity.

The high accuracy mechatronics of the Levitor system ensure an excellent wafer-to-wafer (WtW) temperature repeatability. The temperature sensitivity was calculated by measuring the Rs deviation after processing 2 extra wafers at +5 deg and -5 deg as compared to setpoint. The calculated temperature sensitivity was of which correspond to a WtW temperature uniformity of .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1158.33.pdf

The advantage of conductive heating is that annealing of SiC wafers becomes independent of emissivity, providing better uniformity and repeatability of wafer temperature. Si wafers can be used for rapid and accurate process montoring. Uncontrolled silicidation occurring during heating and cooling of the SiC wafer could be avoided by high heating and cooling rates. Long purge time is not needed and the risk of residual oxygen is reduced because no graphite boxes are used. The wafer cools down quickly because there is no need of successive cooling steps caused by the thermal mass of the graphite box. This allows achieving high throughput, e.g. for process time of 60 s . The technology used in the Levitor RTA system (conductive heating of a wafer supported by gas bearings) allows low contamination level (all below ). The pressure created in the gas bearing during wafer processing ensures oxygen levels during annealing are less than 1 ppm .

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.33.pdf

Kimoto, T.; Cooper, J.A. Fundamentals of Silicon Carbide Technology, 1st ed.; John Wiley & Sons: Singapore, 2014.

Roccaforte, F.; Fiorenza, P.; Greco, G.; Lo Nigro, R.; Giannazzo, F.; Patti, A.; Saggio, M. Challenges for energy efficient wide band gap semiconductor power devices. Phys. Status Solidi A 2014, 211, 2063-2071.

Z. Wang, S. Tsukimoto, M. Saito and Y. Ikuhara; Introducing Ohmic Contacts into Silicon Carbide Technology; WPI Research Center, Advanced Institute for Materials Research, Tohoku University 2-1-1 Katahira, Aoba-ku, Japan Silicon Carbide - Materials, Processing and Applications in Electronic Devices

Kimoto, T. Material science and device physics in SiC technology for high-voltage power devices. Jpn. J. Appl. Phys. 2015, 54, 040103.

She, X.; Huang, A.Q.; Lucía, Ó.; Ozpineci, B. Review of silicon carbide power devices and their applications. IEEE Trans. Ind. Electron. 2017, 64, 8193-8205.

F. Roccaforte, G. Brezeanu, P.M. Gammon, F. Giannazzo, S. Rascunà, M. Saggio, Schottky contacts to silicon carbide: physics, technology and applications, in "Advancing Silicon Carbide Electronics Technology vol. I", Mater. Res. Found. 37(2018) 127-190

F. Roccaforte, F.Fiorenza, P.Vivona, M.; Greco, G.; Giannazzo, Selective Doping in Silicon Carbide Power Devices. Materials 2021, 14, 3923

L.M. Porter, R.F. Davis: Mater. Sci. Eng. B 34, 83 (1995)

J. Crofton, L.M. Porter, J.R. Williams: phys. stat. sol. (a) 202, 581 (1997)

M.J. Bozack: phys. stat. sol. (a) 202, 549 (1997)

S.W. King, R.J. Nemanich and R.F. Davis: J. Electrochem. Soc. 146, 2648 (1999)

L. Muehlhoff, W.J. Choike, M.J. Bozack, J.T. Yates, Jr.: J. Appl. Phys. 60,2842 (1986))

R.J. Trew: phys. stat. sol. (a) 162, 409 (1997)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 41-46

doi: 10.4028/p-2Df4qK

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Revised:
2025-08-04

Accepted:
2025-08-05

Online:
2025-09-08

The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

The original version of this paper is available on https://www.scientific.net/MSF.1158.41.pdf

Youngbin Im , Inkyu Kim , Jiyeong Yoon , Jingu Lee , Gihoon Park , Jesung Lim , Junewoo Son , Jungho Lee , Y.J. Jang , Changbeom Jeong

Onsemi Pyeongcheon-ro 850beon-gil Bucheon-si Gyeonggi-do, Republic of Korea

KIST Hwarang-ro 14-gil Seongbuk-gu Seoul, Republic of Korea

youngbin.im@onsemi.com, inkyu.kim@onsemi.com, djingu.lee@onsemi.com, egihoon.park@onsemi.com, jesung.lim@onsemi.com, gjunewoo.son@onsemi.com, hjungho.lee@onsemi.com, iyjjang@kist.re.kr, chang.jeong@onsemi.com

Keywords: SiC gate oxide, thermal oxidation, lower pressure oxidation, chlorine oxidation.

Abstract

This study investigates the effects of lower pressure and chlorine gas added oxidation on the Gate Oxide Integrity (GOI) during the SiC MOSFET Gate Oxide (GOX) process. For structural comparison, analyses were conducted using Dynamic SIMS and TOF-SIMS. Notable differences in the uniformity of silicon concentration within the oxide layer were observed under various GOX conditions. To evaluate the impact of these differences on the characteristics of SiC MOSFETs, results were compared. To enhance the reliability of the findings, evaluations of GOX were performed across multiple products. The experimental results indicated that the SiC MOSFET wafers subjected to chlorine oxidation exhibited improved performance compared to other conditions.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.41.pdf

In the semiconductor oxidation process of Si , chlorine plays a crucial role in removing metallic impurities within the GOX [1-3]. However, in SiC processes, various other techniques are being introduced concerning the quality of GOX [4]. SiC devices primarily utilize implant sources like Al, which certainly introduces metallic impurities into the gate oxide during thermal oxidation process. And some of study shown effective results to SiC GOX process. [5-7] This paper aims to investigate the effects of chlorine oxidation on SiC MOSFET devices. Additionally, considering the influence of lower pressure oxidation on oxide quality, as discussed at ICSCRM2023 [8], we aim to examine its impact on SiC MOSFET devices.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.41.pdf

This study evaluated the characteristics representing the Gate Oxide Integrity (GOI) of SiC MOSFETs under various Gate Oxide (GOX) conditions to determine which conditions produce the most effective thermal oxidation process. Furnace thermal oxidation was performed to achieve the same target GOX thickness at a constant temperature. Additionally, SIMS analysis of the oxidized SiC wafers was conducted to compare the effects of lower pressure oxidation and chlorine gas-added oxidation during the GOX process.

TOF SIMS (Lower Pressure Ox)

TOF SIMS (Thermal Ox)

Fig. 1. SIMS comparison.

Fig. 1. SIMS comparison.

To compare the effects of pressure and chlorine in the gate oxidation process, TOF-SIMS and Dynamic SIMS(D SIMS) analysis (Fig. 1) were conducted. D SIMS analysis revealed the behavior of chlorine within the oxide layer, showing uniform Si distribution in the presence of chlorine. Similarly, TOF-SIMS analysis confirmed that in the presence of chlorine, both Si and exhibited uniformity within the layer.

Fig. 2. comparison -SiC MOSFET A, Istress , Tstress .

Fig. 2. comparison -SiC MOSFET A, Istress , Tstress .

Fig. 3. comparison -SiC MOSFET B, Istress , Tstress .

Fig. 3. comparison -SiC MOSFET B, Istress , Tstress .

Fig. 4. comparison - SiC MOSFET C, Istress , Tstress .

Fig. 4. comparison - SiC MOSFET C, Istress , Tstress .

The is a standard destructive test method to verify the gate oxide quality in MOSFET devices. To evaluate the effect of pressure control and added chlorine gas during thermal oxidation, characteristic is evaluated. As shown in (Fig. 2-4) we obtained the results that improved at added chlorine gas ( ) better than thermal oxidation ( ).

The SIMS analysis and evaluation results demonstrate the effect of added chlorine during the GOX thermal oxidation process. [5-7] Experimental results confirmed that the passivation or gettering effect reduces the defects within the GOX layer formed on the SiC wafer, leading to the formation of stable .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.41.pdf

The analysis results of this study demonstrated that, regardless of the pressure conditions in the GOX process, the gate oxide treated without chlorine exhibited a significant decrease in silicon concentration from the interface to the surface. In contrast, the gate oxide formed through chlorine oxidation maintained a consistent silicon concentration throughout the entire GOX layer. This signifies the maintenance of uniformity in across the entire gate oxide area and serves as evidence for improved compared to gate oxides under different conditions showing Si concentration degradation comparatively due to carbon defects. Therefore, thermal oxidation with chlorine can form a stable , and this effect is an improvement in gate oxide quality, as seen in improvement results of SiC MOSFET devices.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.41.pdf

U.S. Patent No. 5393686 (1995)

KR Patent No. 10-1996-0075209 (1996)

P.W. Mertens, M.J. McGeary, M. Schaekers, H. Sprey, B. Vermeire, M.Depas, M. Meuris and M. M. Heyns, "Effect of Cl in Gate Oxidation", Mat. Res. Soc. Symp. Proc. Vol. 477.

Maria Cabello, Victor Soler, Gemma Rius, Josep Montserrat, Jose Rebollo, Philippe Godignon, "Advanced processing for mobility improvement in MOSFETs: A review", Materials Science in Semiconductor Processing 78 (2018) 22-31.

P. T. Lai, J. P. Xu, H. P. Wu, C. L. Chan, "Interfacial properties and reliability of grown on 6 H -SiC in dry plus trichloroethylene", Microelectronics Reliability 44 (2004) 577-580.

J, P, Xu, P. T. Lai, H. P. Wu, C. L. Chan, "Effect of chlorine on interfacial properties and reliability of grown on , Appl. Phys. A 81, 173-176 (2005).

B. L. Yang, L. M. Lin, J. P. Xu, P. T. Lai, "Improved I-V Characteristics of SiC MOSFETs by TCE Thermal Gate Oxidation", 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

Youngbin Im, Inkyu Kim, Seongpil Son, "SiC MOSFET Gate Oxide Quality Improvement Method in Furnace Thermal Oxidation with Lower Pressure Control", Defect and Diffusion Forum (2024).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 47-51

doi: 10.4028/p-I2v7fz

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Revised:
2025-02-12

Accepted:
2025-02-24

Online:
2025-09-08

A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

Jae-Hyung Park , Jeff Joohyung Kim , Ashish Kumar , Jacob Zacks , Daniel Flint , Daniel J. Lichtenwalner , and Sei-Hyung Ryu

Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

jacob.zacks@wolfspeed.com, daniel.flint@wolfspeed.com, daniel.lichtenwalner@wolfspeed.com, sei-hyung.ryu@wolfspeed.com

Keywords: Transmission line model (TLM), circular TLM (CTLM), contact resistivity, ohmic contact

Abstract

To ensure maximum device current is supplied through a vertical device having a backside ohmic contact, the specific contact resistivity, , must be well characterized as it constitutes a portion of the device resistance. While there are multiple approaches to deduce , the transmission line model (TLM) remains a convenient choice because of its simplicity in terms of fabrication, measurement, and analysis. For thick substrates where mesa isolation is impractical, the circular transmission line model (CTLM) is an attractive path. In this study we propose an additional restriction on the CTLM design such that the is readily extracted from a simple linear regression just as is the case in a linear TLM. We demonstrate the simplified method by extracting of an ohmic contact to the c-face of substrate.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

To minimize conduction loss for optimal efficiency in a power semiconductor switch, all resistive components, including ohmic contact resistance for example, need to be characterized and understood. The measure of ohmic contact resistance between a metal and a semiconductor is generally conveyed by specific contact resistivity, , which is scale-invariant with respect to contact area. While there are multiple approaches to deduce it [1-5], the transmission line model (TLM) remains a convenient choice because of its simplicity in terms of fabrication, measurement, and analysis. TLM assumes one-dimensional flow of current that can be challenging to satisfy because devices are realized in three-dimensional space with finite sizes, i.e. currents bend at edges and corners, causing deviations away from the one-dimensional model. The issue can be circumvented in part by using circular transmission line model (CTLM) that reduces two ( x and y ) dimensions into a single radial ( r ) one by introducing radial symmetry to the metal contact pattern. However, there is a price to pay as CTLM requires more complicated analysis to extract the contact resistivity. This work proposes an additional restriction in the CTLM design such that the specific contact resistivity is readily extracted from a simple linear regression just as is the case in a linear TLM. In addition, we report our finding that the statistical errors of the extracted quantities, such as semiconductor sheet resistance ( ) and transfer length ( ), depend on the values of CTLM design parameters. Finally, we demonstrate how we can combine the results of two varying designs - one optimized for extracting and the other optimized for to arrive at deducing the specific contact resistivity.

Theory

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

Given a CTLM structure as shown on Fig. 1, the resistance across two metal pads on a semiconductor separated by an annular gap is given by Eq. 1 where and are outer radius and inner radius respectively, and , and are the modified Bessel functions of first and second kinds. Eq. 1 can be simplified to Eq. 2 assuming [6].

Fig. 1. Circular contact resistance test structure showing the designations of inner and outer radii, and . The inset shows a cross-sectional view.

Fig. 1. Circular contact resistance test structure showing the designations of inner and outer radii, and . The inset shows a cross-sectional view.

Fig. 2. Schematics of representative CTLM structures with varying gap spacings, representing group A (top) and group B (bottom).

Fig. 2. Schematics of representative CTLM structures with varying gap spacings, representing group A (top) and group B (bottom).

After imposing a design restriction as shown in Eq. 3 so that the reciprocal sum of and is a constant value, , Eq. 2 can be further simplified to Eq. 4 . Note that Eq. 4 has the same linear equation form as linear TLM formulation. A simple linear regression of the resistance as a function of varying ratio of and allows the extraction of sheet resistance and transfer length from the slope and y-intercept respectively. The specific contact resistivity is obtained from the expression in a straightforward manner.

The choice of must be such that it allows the assumption ( to use Eq. 2) to hold while managing to yield a reasonable range of gap spacing that satisfies Eq. 3. Given the value of 263 , a wide range of annular gap spacing can be chosen as shown in Table 1 below. Table 1 shows CTLM design parameters for the two groups to demonstrate the simplicity of the proposed methodology.

Table I. CTLM design parameters.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

Two sets of CTLM structures, groups A and B, were fabricated on the c-face of Wolfspeed 4 H SiC substrates with off-axis cut, using one set of process conditions for ohmic contact formation. Resistance of each CTLM was extracted by fitting a line to the IV curve measured on a typical semiconductor probe station as shown in Fig. 3.

Fig. 3. An example plot of I-V curves at for extracting resistance for varying gaps.

Fig. 3. An example plot of I-V curves at for extracting resistance for varying gaps.

Fig. 4. Resistance versus at for the groups A (left) and B (right). Inset is showing the comparison.

Fig. 4. Resistance versus at for the groups A (left) and B (right). Inset is showing the comparison.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

Figure 3 shows an example of four I-V curves with four gap spacings, each with a specific ratio of . The collection of the resistances and their corresponding ratios are plotted on Fig. 4 by groups A and B. Group A (red) was designed with CTLM structures with large ratio values, or large gap spacings. Both groups A and B have values close to unity (see the inset in Fig. 4), indicating the simplified approach to CTLM from Eq. 3 and Eq. 4 are not unreasonable. The slopes and y-intercepts of the fitted lines in Fig. 4 yield the sheet resistance and transfer length respectively using Eq. 4. The fitted lines on Fig. 4 reveal a distinction between groups A and B as the red fitted lines resemble a band of parallel lines while the blue lines cross the y -intercept in a tighter window. In other words, group A, having the larger spacings, owes more of its resistance to the semiconducting film and, therefore, provides more reliable extraction of as indicated by higher values of . Group B, having smaller spacings, is more reliable at extracting as shown by narrower window of y intercepts.

Fig. 5. Extracted sheet resistance (left) and transfer length (right) distributions are compared between groups A and B .

Fig. 5. Extracted sheet resistance (left) and transfer length (right) distributions are compared between groups A and B .

Fig. 6. Standard errors in the extracted values from linear regression are compared between groups A and B (left). Specific contact resistivity distributions (right) are plotted by group. The arrow indicates the best estimate by combining group A and B results.

Fig. 6. Standard errors in the extracted values from linear regression are compared between groups A and B (left). Specific contact resistivity distributions (right) are plotted by group. The arrow indicates the best estimate by combining group A and B results.

Figure 5 shows the values of extracted and . We have more confidence in the extracted value of from group A because of the higher values as shown in the Fig. 4 inset. On the other hand, the extracted values of from group B are more reliable as their statistical distribution is tighter and their percentage errors in y-intercept are lower. Some transfer length values, above , from group A violate the assumption while that is not an issue with group B. Since there was no way to know the transfer length a priori, this issue would have to be resolved through iteration. It is worth noting that the extracted quantities are generally aligned between the two groups despite their respective shortcomings and even potential violation of the assumption used to extract the relevant quantity.

Figure 6 shows the respective standard errors in y-intercept and slope. It highlights that group A has a large variation in y-intercept that leads to the large variation in the extraction of . This is unexpected because it is typically assumed that higher resistance values yield better measurement sensitivity and the consequent higher values would increase the confidence in the line fitting. The data suggests the CTLM design should consider a balance of the voltage drop between semiconducting and contact regions. Put another way, high accuracy and high precision measurement may utilize varying CTLM structures aimed at extracting the sheet resistance and the transfer length separately, knowing their statistical errors in both cannot be simultaneously minimized. Good news is that there is only marginal difference between the statistical averages for groups A and B if their errors and assumptions can be ignored. The specific contact resistivity of group A is while that of group B, with a tight distribution of , is ) at room temperature. Based on our learnings, it would make sense to combine the of group A and the of group B to yield .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

We have demonstrated a simple method for the design and analysis of CTLM structures. It yields a straightforward analysis at the expense of upfront design restriction. We found that the gap spacings of CTLM structures yield a trade-off relationship between the standard errors of sheet resistance (slope) and contact resistance (y-intercept) and can marginally skew the extracted value of . The conclusion of this study is that methods of ohmic contact evaluation need to be made with close attention to the design of the structures being used.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.47.pdf

W. Shockley, Report No. AL-TDR-64-207 (1964).

H. Murrmann and D. Widmann, IEEE Trans. Electron Dev. ED-16 1022-1024 (1969)

G. K. Reeves, Solid State Electron, vol. 23, no. 5 487-490 (1980)

G. S. Marlow and M. B. Das, Solid-State Electron. 25 91-94 (1982)

J. G. J. Chern and W. G. Oldham, IEEE Electron Dev. Lett. 5 178-180 (1984)

D. K. Schroder, Semiconductor Materials and Device Characterization, John Wiley & Sons (2006)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 53-57

doi: 10.4028/p-92rbzH

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-08

Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1158.53.pdf

Abdul Hannan Yeo , Voo Qin Gui Roth , Lakshmi Kanta Bera , Umesh Chand , Navab Singh , Surasit Chung , Nguyen Xuan Sang , Quek Zhan Jiang , Akhil Ranjan , Vudumula Pavan Kumar Reddy , Ho Sze Jian Garrick , Lim See Kiat , Muhammad Ozalis Omar , Xie Jiawei , Yeo Yee Chia , Gong Xiao

Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore 138634

Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117583

hannan_yeo@a-star.edu.sg, Roth_Voo@a-star.edu.sg, Lakshmi_kanta_bera@a-star.edu.sg,

Chand_Umesh@a-star.edu.sg, navab@a-star.edu.sg, Surasit_chung@a-star.edu.sg, Nguyen_Xuan_Sang@a-star.edu.sg, Quek_Zhan_Jiang@a-star.edu.sg, Lim_See_Kiat@a-star.edu.sg, mMuhammad_Ozalis_Bin_Omar@a-star.edu.sg, njiaweix@u.nus.edu, Yeo_Yee_Chia@a-star.edu.sg, Gong_Xiao@a-star.edu.sg

Keywords: ohmic contacts, p-type SiC, boron plasma treatment.

Abstract

Heavily p-type doped ( ) implants are commonly used to achieve low specific contact resistance (SCR) for p-body diodes through a costly ion implantation process. Alternatively, our study proposes a single-step plasma treatment method using plasma. This method incorporated a high concentration of self-activated p-type boron dopants in the SiC lattice with minimal damage.

Experimental I-V data from Schottky Barrier Diodes (SBDs), combined with TCAD simulation, demonstrated that approximately of boron atoms were activated in the SiC lattice (at a depth of without the need for high temperature ion implant activation. Our approach using plasma treatment realizes an SCR value of , which is approximately 1 order of magnitude lower than that of untreated samples.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.53.pdf

Variations caused by a rapid change in drain-source voltage ( ) can influence the electrical potential within the p-body region during transistor switching [1]. Several factors contribute to such influence: (i) Increased output capacitance charge due to higher doping concentrations in the drift layers, leading to a high displacement current during switching; (ii) Low hole mobility of SiC from the high sheet resistance of the p-body region [2]; and (iii) High SCR in the p-body ohmic contact [3-4].
implantation plays a critical role in enhancing carrier injection and hole tunneling at the metalSiC (MS) interface, despite its high cost and unwanted defects [5]. Plasma doping offers a promising method for incorporating dopants into the SiC lattice with minimal crystal damage at lower temperatures [6]. This study investigates the effectiveness of a single-step plasma treatment for self-activated p-type boron dopant incorporation into SiC. This method to form ohmic contacts at the p-body could facilitate higher switching speeds and minimize switching losses in SiC MOSFETs.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.53.pdf

First, a m-thick p-type epitaxial (p-epi) SiC layer with an aluminum doping of on an n -type SiC substrate was used. This substrate was chosen to emulate the p -body region of the SiC MOSFET. The samples were wet cleaned and treated with different plasma conditions for further analysis as per previous work [7].

Fig. 1. (a) SIMS analysis of boron concentration in SiC lattice before and after treatment (b) XPS spectra of SiC surface after plasma treatment.

Fig. 1. (a) SIMS analysis of boron concentration in SiC lattice before and after treatment (b) XPS spectra of SiC surface after plasma treatment.

Boron concentration of more than was observed near the surface with an enhanced concentration up to a depth of over the untreated sample, as shown in the secondary ion mass spectrometry (SIMS) profile in Fig. 1 (a). In Fig. 1 (b), X-ray Photoelectric Spectroscopy (XPS) spectra revealed a notable presence of boron atoms on the surface of the treated samples, with the boron 1s peak detected at . These results indicate the presence of Boron atoms at the surface and in the SiC lattice up to 30 nm after plasma treatment.

Fig. 2. (a) TEM cross-section of samples with unrefined and optimized recipe (b) AFM of samples after treatment after optimization.

Fig. 2. (a) TEM cross-section of samples with unrefined and optimized recipe (b) AFM of samples after treatment after optimization.

Previous studies have established that plasma has the capability to etch SiC [8-9]. Therefore, it was critical that the treatment process had to be optimized to minimize surface etching with a minimal etching depth less than 5 nm , as evidenced in transmission electron microscopy (TEM) images in Fig. 2 (a). With the unrefined recipe, a large etching depth of was observed which is undesirable for good ohmic contacts. After optimizing the plasma conditions in the recipe, a minimal surface etching of 5 nm was obtained. We further conducted atomic force microscopy (AFM) to examine the surface roughness after plasma treatment, showing low roughness values of , as depicted in Fig. 2 (b). It is noteworthy that prior research has addressed how minor surface etching and low values are unlikely to substantially affect the quality of the ohmic contact [8].

Fig. 3. (a) Cross-section of samples with unrefined and optimized recipe
(b) AFM of samples after treatment after optimization.

Fig. 3. (a) Cross-section of samples with unrefined and optimized recipe (b) AFM of samples after treatment after optimization.

The self-activation of boron atoms after plasma treatment was investigated using Schottky barrier diodes (SBDs). The diodes were fabricated on commercial n-epi wafers with a nitrogen doping of ( ) as shown in Fig. 3 (a). A Ti/Al Schottky metal on the frontside and a Ni-based ohmic metal contact on the backside was employed in this study. Electrical measurements (I-V tests) conducted on the SBDs revealed a substantial increase in the knee voltage ( ) by +1.5 V for treated samples, as depicted in Fig. 3 (b). This could have indicated self-activation of the boron atoms during the plasma treatment process.

Fig. 4. TCAD simulation of Schottky barrier diodes (SBDs) with different percentage of boron activation with correlation to experimentally obtained I-V data.

Fig. 4. TCAD simulation of Schottky barrier diodes (SBDs) with different percentage of boron activation with correlation to experimentally obtained I-V data.

Simulations in Sentaurus TCAD estimated that approximately of the boron dopants were activated, consistent with experimental observation of the increased after plasma treatment, as demonstrated in Fig. 4. This partial activation could have been made possible due to the high energy plasma source. However, high temperature annealing would still be required to achieve fully activated dopants in the SiC lattice.

Fig. 5. (a) CTLM process flow with gap spacings of . I-V after PMDA at (b) untreated and (c) treated.

Fig. 5. (a) CTLM process flow with gap spacings of . I-V after PMDA at (b) untreated and (c) treated.

Circular transmission line method (CTLM) structures were fabricated with a Ti-based metal stack on the p-SiC as shown in Fig. 5 (a) for SCR extraction as per previous work [7]. The treatment was carried out across the sample prior to lithography and metal deposition. Ohmic I-V behaviour was observed on CTLM structures from different gap spacings of after post metal deposition annealing (PMDA) at as shown in Fig. 5 (b-c). The SCR of treated samples extracted, exhibited a one order of magnitude reduction from (untreated) to (treated) as shown in Fig. 6 (a-b). The SCR values were obtained from three sets of CTLM structures.

Fig. 6. Ave R vs. Gap of CTLM structures (a) untreated and (b) treated (c) Benchmarking of SCR value with other work on highly doped substrates.

Fig. 6. Ave R vs. Gap of CTLM structures (a) untreated and (b) treated (c) Benchmarking of SCR value with other work on highly doped substrates.

This reported SCR value is relatively low for moderately doped p-SiC ( ) as benchmarked with other studies on highly doped substrates ( ) as illustrated in Fig. 6 (c) [9-12]. A higher should yield a lower SCR value with this plasma treatment which will be studied in future work.

Fig. 7. (a-j) TEM-EDX and elemental colour map of metal silicide at the Metal-SiC junction after PMDA.

Fig. 7. (a-j) TEM-EDX and elemental colour map of metal silicide at the Metal-SiC junction after PMDA.

TEM-EDX colour mappings in Fig. 7 ( ), revealed intermetallic diffusion of both Ni and Al into the SiC and the formation of layers after PMDA. This formation of the stable and favourable Ti-silicide phase was the main mechanism of the ohmic contact formation. Carbon out diffusion was also observed after PMDA, and the formation of Ti-based carbide complexes could also be seen. Boron atoms were observed in the SiC lattice and out diffusion to the surface after PMDA.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1158.53.pdf

In this study, we have experimentally demonstrated a plasma treatment method that incorporated activated boron dopant atoms ( ) in a single step at low temperatures ( ). This high concentration of boron atoms at the MS interface could have facilitated high carrier injection which formed favourable ohmic contacts reducing the SCR by almost 1 order of magnitude to . The SCR value obtained was relatively low for mildly doped when benchmarked with highly doped p-type substrates. This novel single step plasma treatment allows for the reduction of SCR at the source region in p-SiC.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1158.53.pdf

This work was supported by A*STAR (Agency for Science, Technology and Research Singapore), under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.53.pdf

S. Hino et al., "SiC-MOSFET Structure Enabling Fast Turn-On and -Off Switching," Materials science forum, vol. 717-720, pp. 1097-1100, (2012)

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology. Hoboken, NJ, USA: Wiley, (2014).

R. Konishi, Ryuichi Yasukochi, O. Nakatsuka, Y. Koide, M. Moriyama, and M. Murakami, "Development of Ni/Al and Ni/Ti/Al ohmic contact materials for p-type 4H-SiC," Materials Science and Engineering: B, vol. 98, no. 3, pp. 286-293, (2003)

M. Vivona, G. Greco, C. Bongiorno, R. Lo Nigro, S. Scalese, and F. Roccaforte, "Electrical and structural properties of surfaces and interfaces in Ohmic contacts to p-type implanted ," Applied Surface Science, vol. 420, pp. 331-335, (2017)

R. Hou et al., "Ultra-Shallow Doping B, Mg, Ni, Cu, Mn, Cr and Fe into SiC with Very High Surface Concentrations Based on Plasma Stimulated Room-Temperature Diffusion," Journal of Materials Engineering and Performance, vol. 28, no. 1, pp. 162-168, (2018)

L. Ottaviani et al., "Plasma Immersion Ion Implantation Applied To N[sup +]P Junction Realisation In 4H-SiC," AIP conference proceedings, (2011)

A. Hannan et al., "The Effect of Nitrogen Plasma Treatment Process on Ohmic Contact Formation to N-Type 4H-SiC," Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena, vol. 359, pp. 59-63, (2024)

Huseyin Ekinci, V. V. Kuryatkov, D. L. Mauch, J. C. Dickens, and S. A. Nikishin, "Plasma Etching of n-Type 4H-SiC for Photoconductive Semiconductor Switch Applications," Journal of Electronic Materials, vol. 44, no. 5, pp. 1300-1305, (2015)

S. Tsukimoto, K. Nitta, T. Sakai, M. Moriyama, and M. Murakami, "Correlation between the electrical properties and the interfacial microstructures of TiAl-based ohmic contacts to p-type 4H-SiC," Journal of Electronic Materials, vol. 33, no. 5, pp. 460-466, (2004)

F. Roccaforte et al., "Metal/Semiconductor Contacts to Silicon Carbide: Physics and Technology," Materials Science Forum, vol. 924, pp. 339-344, (2018)

H. Tamaso, S. Yamada, H. Kitabayashi, and T. Horii, "Ti/Al/Si Ohmic Contacts for both nType and p-Type 4H-SiC," Materials Science Forum, vol. 778-780, pp. 669-672, (2014)

B. H. Tsao, S. Liu, and J. D. Scofield, "Improved AlNi Ohmic Contacts to p-Type SiC," Materials Science Forum, vol. 457-460, pp. 841-844, (2004)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 59-65

doi: 10.4028/p-Y3u94c

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-08

Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

M. Kobayashi , H. Uchida , N. Hatta , S. Ishikawa , Y. Higashi , H. Sezaki , S. Harada , and K. Kojima

SICOXS Corporation, 5-11-3, Shimbashi, Minato-ku, Tokyo 105-0004, Japan

Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki 305-8568, Japan

PHENITEC SEMICONDUCTOR Corp., 6833, Kinoko-cho, Ibara, Okayama 715-8602, Japan

ª*motoki.kobayashi.x2@smm-g.com, hidetsugu.uchida.x7@smm-g.com, naoki.hatta.x8@smm-g.com, dishikawa-seiji@aist.go.jp, higashi-phenitec@aist.go.jp, hiroshi-sezaki@phenitec.co.jp, s-harada@aist.go.jp, kazu-kojima@aist.go.jp

Keywords: Bonded substrate, Backside metal contact resistance, Circular TLM, Temperature dependence

Abstract

A unique hybrid structure of the bonded substrate offers advantages not achievable with conventional bulk substrates, such as a reduction in on-state resistance and the suppression of forward bias degradation in power devices. This study focuses on the contact resistance between the polycrystalline layer and the backside metal ( ) of bonded substrates, along with its temperature dependence. The results indicate that the bonded substrates exhibit low backside contact resistance, even without annealing, and this resistance remains stable at elevated temperatures. Furthermore, power devices utilizing bonded substrates demonstrated reduced on-state resistance, as evaluated using Schottky barrier diodes (SBDs). Specifically, bonded substrates without contact annealing lowered the forward voltage (VF) by compared to bulk substrates with contact annealing. These findings suggest that bonded substrates simplify the backside contact process compared to bulk substrates, offering significant benefits in reducing on-state resistance in SiC power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

The bonded substrate ( ), produced by SICOXS, consists of an ultra-thin (less than ) monocrystalline 4 H -SiC layer bonded to an n-type low-resistivity polycrystalline 3C-SiC substrate using the surface-activated bonding method. This hybrid structure presents advantages not possible with traditional bulk substrates, such as a reduction in on-state resistance[1] and the suppression of forward bias degradation in PiN diodes[2-3].

This study examines the contact resistance between the polycrystalline layer and the backside metal of bonded substrates. Given that the polycrystalline layer in bonded substrates exhibits extremely low resistivity (below ), the objective is to investigate the differences in backside contact resistance and its temperature dependence between bulk and bonded substrates. Additionally, to assess the suitability of bonded substrates with low-resistivity polycrystalline material and low backside contact resistance for power device applications, we fabricated SBDs on bonded substrates.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

Fig. 1 presents the process flow and a schematic of the circular transmission line model (cTLM) structure used in this study. Three types of sample substrates were tested: (Sample a) bulk substrates with contact annealing (annealed mono-SiC), (Sample b) bonded substrates with contact annealing (annealed bonded-SiC), and (Sample c) bonded substrates without contact annealing (unannealed bonded- SiC ). The resistivity of the bulk substrates and the polycrystalline layer of the bonded substrates were approximately and , respectively. was used as the ohmic metal, and contact annealing was performed using rapid thermal annealing at . The cTLM method was applied to measure backside contact resistance with high accuracy. In the cTLM technique, when the sum of radii ( ) is constant, the total resistance between two electrodes depends linearly on the spacing parameter . By fitting the measured values for different d values, the sheet resistance ( ) and the transfer length ( ) can be determined. The specific contact resistance is then calculated using [4]. The cTLM pattern was designed with constant and varying between 5 and . For I-V measurements, a Keithley B1505A was used, and the measurement temperature was controlled at room temperature (RT) and using a hot plate.

Fig. 2 outlines the process flow and schematic of the Schottky barrier diode (SBD) with a junction barrier Schottky structure, evaluated in this study. The same three types of sample substrates (SBD 1: annealed mono-SiC, SBD 2: annealed bonded-SiC, and SBD 3: unannealed bonded-SiC) were used for the SBD evaluation as for the cTLM assessments. The backside metal for the SBDs was , and the contact annealing conditions were the same as those used in the cTLM process. The forward current (IF)-forward voltage (VF) and reverse current (IR)-reverse voltage (VR) characteristics of the SBDs were measured.

Fig. 1. (a) Process flow and (b) schematic image of the cTLM structure in this study.

Fig. 1. (a) Process flow and (b) schematic image of the cTLM structure in this study.

Fig. 2. (a) Process flow and (b) schematic image of the SBD structure in this study.

Fig. 2. (a) Process flow and (b) schematic image of the SBD structure in this study.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

1. Backside contact resistance and its temperature dependence

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

Fig. 3(a) illustrates the I-V characteristics at for the cTLM measurements. All samples demonstrate ohmic contact behavior. Fig. 3(b) presents the TLM plots at RT. All samples exhibit good linearity in the TLM plots, and the contact resistance can be accurately measured using linear approximation. The slope and intercept for calculating the contact resistance were determined from the approximate equation at .

Fig. 3. (a) I-V characteristics at for the cTLM structure, and (b) TLM plots at room temperature (RT). Sample a represents annealed mono-SiC, sample b represents annealed bondedSiC , and sample c represents unannealed bonded- SiC .

Fig. 3. (a) I-V characteristics at for the cTLM structure, and (b) TLM plots at room temperature (RT). Sample a represents annealed mono-SiC, sample b represents annealed bondedSiC , and sample c represents unannealed bonded- SiC .

Fig. 4 displays the backside contact resistance at RT. The values of backside contact resistance for unannealed bonded-SiC are consistent with results from another research[5]. Unannealed bondedSiC shows lower backside contact resistance compared to annealed mono- SiC , with annealed bondedSiC demonstrating the lowest resistance. Notably, the contact resistance of unannealed bonded- SiC is an order of magnitude lower than the resistance of the polycrystalline material itself ( at thickness of ), indicating that the contact resistance is not a limiting factor. These findings confirm that low resistance backside contacts can be formed on bonded substrates without annealing. Therefore, the elimination of the backside contact annealing process represents a key advantage of bonded substrates.

Fig. 4. Backside contact resistance at room temperature (RT). Sample a represents annealed monoSiC , sample b represents annealed bonded- SiC , and sample c represents unannealed bonded- SiC .

Fig. 4. Backside contact resistance at room temperature (RT). Sample a represents annealed monoSiC , sample b represents annealed bonded- SiC , and sample c represents unannealed bonded- SiC .

Fig. 5 shows the backside contact resistance and the reduction ratio for each sample at both RT and . The contact resistance of annealed mono-SiC decreases at compared to RT, while the contact resistance of both bonded-SiC samples remains unchanged, demonstrating stability within this temperature range. Unannealed bonded-SiC reduces contact resistance by at RT and at compared to annealed mono-SiC. In addition to reducing backside contact resistance, the lack of temperature sensitivity provides another advantage of bonded substrates.

Fig. 5. (a) Backside contact resistance and (b) the reduction ratio of samples and at room temperature (RT) and , compared with sample a. Sample a represents annealed mono-SiC, sample b represents annealed bonded- SiC , and sample c represents unannealed bonded- SiC .

Fig. 5. (a) Backside contact resistance and (b) the reduction ratio of samples and at room temperature (RT) and , compared with sample a. Sample a represents annealed mono-SiC, sample b represents annealed bonded- SiC , and sample c represents unannealed bonded- SiC .

The difference in temperature dependence between the bulk substrate and the bonded substrates is discussed below. Equation 1 shows the relationship between substrate donor concentration and contact resistance[6].

In these equations, , and is the Richardson constant. Here, h is the Planck constant, q denotes the electron charge, k is the Boltzmann constant, T is the absolute temperature, is the effective electron mass, is the dielectric constant, is the barrier height for carrier transport, is the electron carrier concentration (corresponding to the nitrogen concentration in the polycrystalline bonded substrate), and represents the energy difference between the conduction-band edge and the Fermi level of the semiconductor. The characteristic energy is related to the tunneling probability for electrons in ohmic contacts.

It is expected that is mainly determined by and from Eq.1, and is primarily determined by from Eq.2. These relationships indicate that when tunneling current dominates ohmic contact behavior, the current in ohmic contacts depends on Nd. Conversely, if thermionic emission current dominates, the current depends on . Therefore, if tunneling current is the dominant mechanism in ohmic contacts, the temperature dependence diminishes.

Fig. 6 presents the fitting curves of temperature dependence for contact resistance, compared with the measured values of backside contact resistance (shown in Fig. 5). The fitting curve was calculated using Equation 1, with parameters adjusted to align with the measured values. From Fig. 6, the measured values closely follow the fitting curve, confirming that the strong temperature dependence of annealed mono-SiC is due to thermionic emission current in ohmic contacts. In contrast, the
minimal temperature dependence observed in bonded-SiC is predominantly influenced by tunneling current in the ohmic contact. Since the specific contact resistance of bonded-SiC is primarily determined by the donor concentration ( ) and is independent of the barrier height , the difference in between bonded-SiC with and without contact annealing is negligible.

Based on the above discussion, the reduced temperature dependence of backside contact resistance in bonded substrates can be attributed to the tunneling mechanism dominating the ohmic contact, driven by the high carrier concentration of the polycrystal. The polycrystalline layer of 4 H SiC bonded substrates has a higher nitrogen concentration (approximately ) than the 4H-SiC bulk substrates (approximately ).

Fig. 6. Fitting curves of temperature dependence for contact resistance, compared with the measured values of backside contact resistance.

Fig. 6. Fitting curves of temperature dependence for contact resistance, compared with the measured values of backside contact resistance.

2. Effects of on-state resistance reduction evaluated by SBDs

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

Fig. 7 shows the (a) forward current (IF) - forward voltage (VF) characteristics and (b) VF at IF 18 A for the SBDs, along with the corresponding reduction ratios. The VF of both annealed and unannealed bonded-SiC are equivalent and lower than that of annealed mono-SiC. Specifically, unannealed bonded-SiC reduces VF by compared to annealed mono-SiC. Given that the backside contact resistance of bonded-SiC is very low at RT for unannealed bonded-SiC), the difference in VF across the SBDs is primarily attributed to the low resistivity of the polycrystalline layer ( at thickness of ). Fig. 8 presents the reverse current (IR)-reverse voltage (VR) characteristics of the SBDs. No significant difference is observed in the relationship between breakdown voltage and reverse leakage current. These results indicate that the 4H-SiC bonded substrate is highly advantageous for reducing the on-state resistance of SiC power devices.

Fig. 7. (a) IF-VF characteristics and (b) VF at IF for SBDs, along with the reduction ratio. SBD 1 represents annealed mono-SiC, SBD 2 represents annealed bonded-SiC, and SBD 3 represents unannealed bonded- SiC .

Fig. 7. (a) IF-VF characteristics and (b) VF at IF for SBDs, along with the reduction ratio. SBD 1 represents annealed mono-SiC, SBD 2 represents annealed bonded-SiC, and SBD 3 represents unannealed bonded- SiC .

Fig. 8. IR-VR characteristics of SBDs. SBD 1 represents annealed mono-SiC, SBD 2 represents annealed bonded-SiC, and SBD 3 represents unannealed bonded-SiC.

Fig. 8. IR-VR characteristics of SBDs. SBD 1 represents annealed mono-SiC, SBD 2 represents annealed bonded-SiC, and SBD 3 represents unannealed bonded-SiC.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

In this study, we investigated the contact resistance between the polycrystalline layer and backside metal ( ) of bonded substrates, along with its temperature dependence. Backside metal contact resistance was measured with high accuracy using the cTLM method. The results revealed that the bonded substrates exhibit low backside contact resistance, even without annealing, and that the contact resistance remains stable at high temperatures. The reduced temperature dependence of backside contact resistance in bonded substrates can be attributed to tunneling-dominant ohmic contact, driven by the high carrier concentration of the polycrystalline layer, which has a higher nitrogen concentration than that of bulk substrates. In addition, the effects of on-state resistance reduction in power devices using bonded substrates were evaluated through SBDs. Unannealed bonded- SiC reduced VF by compared to annealed mono- SiC . These findings suggest that bonded substrates can simplify the backside contact process compared to SiC bulk substrates and offer significant advantages in reducing the on-state resistance of SiC power devices.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

This research was conducted under the joint research project of Tsukuba Power Electronics Constellations (TPEC). The co-authors, S. Ishikawa and Y. Higashi, are affiliated with PHENITEC SEMICONDUCTOR Corp.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.59.pdf

T. Shimono, H. Uchida, A. Onogi, and H. Fujiwara, presented at the Meeting on Advanced Power Semiconductors, Japan (2020)

N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, K. Yagi, M. Kobayashi, S. Kurihara, S. Harada, and K. Kojima, Key Engineering Materials 948, p. 107 (2023)

H. Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, S. Kurihara, S. Harada, and K. Kojima, Abstract of 20th ICSCRM, p. 209 (2023)

H. Kato, D. Takeuchi, N. Tokuda, H. Umezawa, H. Okushi, and S. Yamasaki, Diamond and Related Materials, 18, no. 5-8, pp. 782-785 (2009)

H. Biard, S. Odoul, W. Schwarzenbach, I. Radu, C. Maleville, A. Potier, M. Ferrato, and E. Guajioty, Solid State Phenomena, 1662-9779, 344, pp. 47-52 (2023)

Y. Liu, S. P. Singh, L. M. Kyaw, M. K. Bera, Y. J. Ngoo, H. R. Tan, S. Tripathy, G. Q. Lo, and E. F. Chora, ECS Journal of Solid State Science and Technology, 4, no. 2, pp. 30-35 (2015)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 67-74

doi: 10.4028/p-q2IYST

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-06

Accepted:
2025-08-06

Online:
2025-09-08

Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

Mustafa Akif Yildirim , Vishal Ajit Shah , Marina Antoniou , Andrew Newton , Sami Bolat , Gerard Colston , Andrew Graham , Richard Jefferies , James A. Gott , Kushani Perera , Michael J. Powell , Peter M. Gammon , Philip A. Mawby , Robert Gunn , Arne Benjamin Renz

School of Engineering, University of Warwick, Coventry, UK

Oxford Instruments Plasma Technology, Bristol, UK

Hitachi Energy Semiconductors Switzerland Ltd, Lenzburg, Switzerland

Warwick Manufacturing Group, University of Warwick, Coventry, UK

mustafa.yildirim@warwick.ac.uk, Vishal.Shah@warwick.ac.uk, Marina.Antoniou@warwick.ac.uk, Andrew.Graham.1@warwick.ac.uk, Richard.Jefferies@warwick.ac.uk, j.gott@warwick.ac.uk, iKushani-Hapuhinna.Perera@warwick.ac.uk, michael.powell@oxinst.com, IP.M.Gammon@warwick.ac.uk, P.A.Mawby@warwick.ac.uk, robert.gunn@oxinst.com, Arne.Renz@warwick.ac.uk

Keywords: high-K dielectrics, atomic layer deposition, post-deposition annealing

Abstract

This study investigates the interface and reliability of metal-oxide-semiconductor capacitors (MOSCAPs) based on and using atomic layer deposition (ALD) and postdeposition annealing (PDA). and were used as dielectric layers, with systematic PDA treatments conducted at , and in or forming gas (FG, a mixture of and ) environments to evaluate the impact of the PDA conditions on the interface characteristics of SiC MOSCAPs. The flat-band voltage for 3C-SiC MOSCAPs averaged at for samples and for samples when MOSCAPs annealed at in FG. PDA in forming gas also significantly reduced hysteresis, dropping from 1.75 V to 0.18 V for and from 2.49 V to 0.04 V for samples. For MOSCAPs, as-deposited devices exhibited high oxide charges and poor interface quality. The average flat-band voltages for were , while MOSCAPs showed . After PDA at , the flat-band voltage improved to for SiC and for . Additionally, hysteresis was reduced from 0.61 V to 0.15 V for and from 0.23 V to 0.05 V for samples. We propose a figure of merit (FOM) which is defined as the ratio of the breakdown field to the product of flatband voltage shift, hysteresis effect, and density of interface states. The results demonstrate that PDA significantly enhances the interface quality and electrical characteristics of the MOS capacitors (MOSCAPs), with nitrogen ( ) PDA yielding higher FOM for stacks and forming FG PDA showing superior interfacial quality for 3C-SiC stacks.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

In 2019, emissions from transportation, including aviation fuels, accounted for of the overall greenhouse gas emissions in the European Union-27 [1]. Transition to electric vehicles, and improving their power electronics efficiency, is one of the best choices to decelerate global warming and reduce the effects of climate change. Due to their superior physical and electrical properties, silicon carbide ( SiC )-based metal oxide semiconductor field-effect transistors (MOSFETs) have become commercially competitive with silicon insulated-gate bipolar transistors (IGBTs) in power
applications requiring blocking voltages between 600 V and 1700 V [2,3]. One major challenge that reduces the yield and long-term reliability, hence the further uptake of the technology, is a high density of interface states at the interface, which is typically two to three orders of magnitude higher than in Si-based counterparts [4, 5].

Although SiC is the only compound semiconductor that can form a native layer by consuming the SiC during thermal oxidation, this process differs from the thermal oxidation of Si . During the oxidation of SiC , Si reacts with to form SiO and products. Then the removal of the resultant carbon from the SiC must be considered. When the initially grown oxide is thin, the carbon in the matrix reacts and diffuses out in products of and . However, as the layer becomes thicker the diffusion of these products through the oxide and outside the oxide/atmosphere surface becomes limited. There has been evidence showing residual carbon near or at the interface, with strong evidence of high interface densities thereby low channel mobilities of SiC MOSFETs [6, 7]. Alternative deposition methods for SiC gate dielectrics are particularly appealing, as they prevent substrate consumption and avoid leaving excess carbon atoms, effectively addressing this issue. Due to its ability to provide highly accurate control over thickness (typically within a few angstroms), uniformity, reproducibility, and conformal deposition, atomic layer deposition (ALD) has emerged as a favoured method for depositing gate dielectrics on [8]. ALD operates by sequentially introducing pairs of gaseous chemical precursors into a reaction chamber.

Gauss's law expresses the electric field in an insulator to an adjacent semiconductor by the following equation:

where is the electric field in the semiconductor and are the dielectric constant of the semiconductor and insulator, respectively [4], [7]. The dielectric constant of is approximately 2.5 times lower than the dielectric constant of SiC . This causes the breakdown of first in -based devices hence, preventing SiC from reaching its full potential. Equation 1 suggests that using insulators with a dielectric constant similar to or greater than that of SiC would be ideal for minimizing electrical stress in SiC-based electronics. As shown in Equation 2, using a high- material allows for the same or even greater capacitance with a physically thicker dielectric layer. Having a thicker dielectric layer helps to reduce leakage current, which in turn improves reliability and helps maintain the desired performance. In this equation, represents the permittivity of free space, A is the area of the capacitor, and denotes the thickness of the dielectric layer [9]. This initiates an investigative effort into the utilization of high- dielectrics as the gate dielectric layer in silicon carbide (SiC) based electronic devices. Some of the properties of an ideal dielectric for SiC should be as follows. The dielectric should have low fixed and mobile oxide charges and low density of fixed and mobile interface states. Moreover, the dielectric should have a high breakdown field, a large energy band gap, a high dielectric constant, and a high band offset with SiC to minimise leakage current. Despite having several reported studies of high- dielectrics-SiC with good electrical properties [5, 10-12]. High leakage current still is a huge hampering factor. To resolve this problem scientists proposed a high- material with a thin layer to have an initial large band offset in high- structures.

Oxide deposition techniques such as atomic layer deposition (ALD) and low-pressure chemical vapour deposition (LPCVD) have already been shown to offer a solution to improve control of the interface and circumvent SiC-specific defects, such as carbon clusters, which are inherent in industrystandard thermal oxidation processes [8]. Post-deposition anneals (PDAs) of ALD-deposited layers in forming gas (FG) mixture of and have had a positive impact on both mobility and reliability [8, 13].

In this investigation, we further explore the effect of PDAs on ALD-formed dielectric stacks on 3C-SiC and 4H-SiC MOS-capacitors (MOSCAPs). The dielectric stacks, comprising and underwent PDAs across a temperature range from to in either pure or a forming gas in . The ALD as-deposited and MOSCAPs exhibit a high oxide charge and poor interface quality, which are significantly enhanced after undergoing a PDA process. In contrast, the ALD as-deposited 3C-SiC MOSCAPs show slightly better initial interface characteristics compared to their counterparts, and they too display notable improvements following the PDA treatment. Interface characteristic metrics such as interface state density, flatband voltage shift, hysteresis, and breakdown voltages in the annealed samples are analyzed to assess the improvements brought by the PDA process. To evaluate the overall quality of the MOSCAPs, a figure of merit (FOM) is proposed, defined as the ratio of the breakdown field to the product of the flatband voltage shift, hysteresis, and interface state density. Our analysis revealed that PDA in ambient produces higher figures of merit (FOM) for the 4 H -SiC MOSCAPs, while FG PDA results in higher FOMs for the 3C-SiC MOSCAPs, indicating better interfacial quality in the latter.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

4H-SiC wafers with low-doped epilayers and 3C-SiC epilayers grown on highly doped Si wafers were cleaved into approximately chip-sized samples. The 3C-SiC epilayers are thick with unintentional doping, while the epilayers are thick with intentional doping of . The detailed growth process can be found here[14]. Cleaved samples then underwent a solvent clean (acetone, isopropyl alcohol and deionised water), and RCA process (Hydrofluoric acid (HF), RCA-1, HF, RCA-2 and HF). Then samples were loaded into a plasma-enhanced ALD chamber to deposit dielectrics. and were deposited using oxygen plasma at , with Bis(DiEthylAmido)Silane (BDEAS) as the silicon precursor and Tetrakis(dimethylamido)Hafnium (TDMAH) as the hafnium precursor. The growth rate for was approximately 0.05 nm per cycle, while the growth rate was around 0.1 nm per cycle. After the deposition of the dielectric or stacked dielectric layers, the samples underwent selective annealing process, to investigate the effects of different ambient conditions. Annealing was performed under 5 standard liter per meter (slm) flow of forming gas ( in ) or in a pure atmosphere for 1 hour at temperatures of , and . This process was critical for studying the impact of the PDA on the material properties, as highlighted in previous work [8]. Table 1 illustrates the fabrication matrix of SiC MOSCAPs. A standard photolithography lift-off and metal deposition processes were applied to pattern Al dots with a thickness of 200 nm . Before backside metal contact the backsides of the wafers were etched to eliminate any native oxide layer.

Table 1. A comprehensive overview of the substrate materials, dielectric stack compositions, and post-deposition annealing conditions employed in the fabrication of SiC MOSCAPs.

Substrate
Dielectric Stack
Post-deposition annealing ambient conditions
Post-deposition annealing temperature conditions

4H-SiC

3C-SiC

SiO₂ (30 nm)

HfO₂/SiO₂ (25nm/5nm)

As-dep

N₂

Forming Gas (5 % H₂ in N₂)

As-dep

600°C

900°C

1100°C

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

Figure 1(a) presents a schematic illustration of the fabricated MOSCAPs. The MOSCAPs with only a single layer had a 30 nm thick layer deposited, while those with included a interfacial layer before the deposition. The thin layer is essential in reducing leakage current, as has a lower bandgap and, therefore, a smaller conduction band offset with SiC compared to , which can increase leakage. The higher conduction band offset of the layer acts as a barrier, effectively minimizing leakage while still allowing the to enhance capacitance [9, 15]. This combination significantly improves the overall performance of the MOSCAP. Figure 1(b) shows a TEM image of the thin intermediate layer and layer. MOSCAP structures.

Fig. 1. (a) Schematic representation of the fabricated MOSCAPs and associated circuitry. (b) Cross-sectional TEM image demonstrating the thickness of the stack in the MOSCAP structures.

Fig. 1. (a) Schematic representation of the fabricated MOSCAPs and associated circuitry. (b) Cross-sectional TEM image demonstrating the thickness of the stack in the MOSCAP structures.

Electrical Characterization

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

To further investigate the interface characteristics of the ALD-deposited dielectrics on 3C-SiC and 4H-SiC MOSCAPs, room temperature capacitance-voltage measurements were carried out. Figure 2 shows normalized responses were taken from 12 devices at 1 kHz to 1 MHz frequencies.

Fig. 2. curves of ) and b) and and d) MOS capacitors with different gate dielectric stacks annealed at various temperatures in FG gas ambient. The device area for each device is .

Fig. 2. curves of ) and b) and and d) MOS capacitors with different gate dielectric stacks annealed at various temperatures in FG gas ambient. The device area for each device is .

4H-SiC MOSCAPs

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

As-deposited 4 H -SiC MOSCAPs with and dielectric layers as the gate oxide typically exhibit significant quantities of net negative charge, both within the oxide and at the interface. This is reflected in their flat band voltages, with MOSCAPs averaging , while MOSCAPs show a lower average of . Additionally, these devices do not display accumulation mode, suggesting a leaky oxide layer as it can be seen in figure 3 . While the breakdown voltage of MOSCAPs improves with both FG and annealing, the breakdown voltage of improves only with annealing. This phenomenon requires further investigation to elucidate the underlying factors influencing this behaviour. However, after annealing the devices at , and , the curves begin to shift to the left, indicating passivation of the negative charges. Notably, after annealing, the capacitance of the device saturates entirely when they are swept into deep accumulation, further confirming improvements in the oxide quality. When annealed at for 1 hour in forming gas (FG) ambient, the average flat-band voltages improved to and , reflecting a reduction in net negative charge for and samples, respectively. In addition to improving the flat band voltage, annealing the samples significantly reduces hysteresis. The hysteresis was notably reduced, improved from 0.61 V to 0.15 V for the - SiC MOSCAPs, and from 0.23 V to 0.05 V for the MOSCAPs. Alongside the reduction in hysteresis, a low level of density of interface states ( ) was obtained, which was extracted using the high-low measurement method, with 300 Hz as low frequency and 1 MHz as high frequency. The density of interface states for 4H-SiC MOSCAPs averaged at for and for at 0.2 eV below conduction band ( ) after annealing at in an ambient.

3C-SiC MOSCAPs

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

On the other hand, with a narrower band gap ( 2.3 eV ), has several advantages over 4 H and : it requires a lower electric field for inversion and has a significantly lower trap density at the interface. Additionally, the high density of near-interface traps in the conduction band does not affect channel current, further improving the performance of 3C-SiC MOS structures compared to . Furthermore, the larger conduction band offset at the interface , which even exceeds that of the interface, suggests that devices may offer greater reliability [15,16]. Consequently, as-deposited 3C-SiC samples exhibit strong accumulation, near-ideal flat band voltage, and narrower C-V curves between high and low frequencies as can be seen in Figures 2 c ) and d). The flat band voltages were found to average at Vand for and samples, respectively. They showed similar behaviours compared to 4H-SiC samples post-annealing. When annealed at for 1 hour in FG ambient, the average flat-band voltages shifted to and . Although annealing the 3C-SiC samples doesn't seem to improve the flat band voltages, it greatly reduces the hysteresis. The hysteresis effect was significantly improved, reducing from 1.75 V to 0.18 V for the sample, and from 2.49 V to 0.04 V for sample. 3C-SiC MOSCAPs, showed slightly better values, achieving for and for at after annealing at in an FG ambient, demonstrating enhanced interface characteristics.

Fig. 3. Current-Voltage Characteristics of MOSCAPs: (a) and (b) with or as dielectric layer annealed at in FG or ambient.

Fig. 3. Current-Voltage Characteristics of MOSCAPs: (a) and (b) with or as dielectric layer annealed at in FG or ambient.

Figure 4 a) and Figure 4 b) present a summary of the extracted parameters, including the breakdown field ( ), flatband voltage shift ( , where is the difference between the metal and semiconductor work functions, and is the measured flatband voltage), hysteresis (H), and the density of interface states.

Fig. 4. a) and b) Summaries of extracted electrical parameters for the MOSCAPs, including breakdown field ( ), flatband voltage shift ( ), hysteresis ( H ), and the density of interface states (DIT). The hysteresis values scaled up 10 times. The density of interface states as measured at c) and d) Final calculated figures of merit (FOMs) used to determine the optimal gate dielectric stack and post-deposition annealing (PDA) conditions for and

Fig. 4. a) and b) Summaries of extracted electrical parameters for the MOSCAPs, including breakdown field ( ), flatband voltage shift ( ), hysteresis ( H ), and the density of interface states (DIT). The hysteresis values scaled up 10 times. The density of interface states as measured at c) and d) Final calculated figures of merit (FOMs) used to determine the optimal gate dielectric stack and post-deposition annealing (PDA) conditions for and

moscaps.

For an ideal dielectric or dielectric stack, certain characteristics are desired: a high breakdown field a minimal shift in flat band voltage from its ideal value, low , and minimal hysteresis. To evaluate the overall quality of gate dielectrics, we propose a figure of merit (FOM) which shows the ratio of the breakdown field to the product of flat band voltage shift, hysteresis effect, and density of interface states:

We propose this as a metric to help gauge the effectiveness of gate dielectrics. The final calculated FOMs to evaluate the optimum gate dielectric stack and PDA condition for and MOSCAPs are shown in Figures 4c) and 4d). In our analysis, we observed that the PDA yields higher figures of merit (FOM) for the 4 H -SiC stacks, whereas FG PDA demonstrates higher FOMs, indicating superior interfacial quality, for the 3C-SiC stacks.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

The investigation into the interface and reliability of and MOS structures through gate dielectric stacking and post-deposition annealing has yielded promising results. The use of ALD for depositing and dielectrics, combined with PDA treatments, has proven to be an effective strategy for improving the quality of the interface. The optimized PDA conditions, which differ for 3C-SiC and 4H-SiC MOSCAPs, have led to a reduction in interface trap density, oxide charge, and hysteresis, while overall device performance. The proposed figure of merit (FOM) has been instrumental in determining the optimal dielectric stack and PDA conditions for each SiC polytype. The findings underscore the importance of material and process optimization in realizing the full potential of SiC technology in the fight against climate change and in the development of sustainable energy solutions.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

The project "Innovations in Power MOSFET Gate technology through the use of ALD oxides" has received funding from Innovate UK / InnoSuisse call UK-Switzerland Bilateral: Collaborative R&D under project no. 10089219. The authors would like to thank Richard Jefferies and Andrew Graham from the cleanroom facility at the School of Engineering, University of Warwick, for their generous support during device fabrication and characterization.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.67.pdf

Eea, "Transport and environment report 2022 - Digitalisation in the mobility system: challenges and opportunities," doi: 10.2800/47438.

X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, "Review of Silicon Carbide Power Devices and Their Applications," IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 8193-8205, Oct. 2017, doi: 10.1109/TIE.2017.2652401.

C. Langpoklakpam et al., "Review of Silicon Carbide Processing for Power MOSFET," Feb. 01, 2022, MDPI. doi: 10.3390/cryst12020245.

A. Siddiqui, R. Y. Khosa, and M. Usman, "High-k dielectrics for 4H-silicon carbide: present status and future perspectives," Apr. 21, 2021, Royal Society of Chemistry. doi: 10.1039/d0tc05008c.

P. Fiorenza, F. Giannazzo, and F. Roccaforte, "Characterization of SiO2/4H-SiC interfaces in 4H-SiC MOSFETs: A review," 2019, MDPI AG. doi: 10.3390/en12122310

S. T. Pantelides et al., " and Interfaces for MOSFETs - Challenges and Advances," Materials Science Forum, vol. 527-529, pp. 935-948, Oct. 2006, doi: 10.4028/www.scientific.net/msf.527-529.935.

K. Zekentes and K. Vasilevskiy, "Advancing Silicon Carbide Electronics Technology II Core Technologies of Silicon Carbide Device Processing," 2020. [Online]. Available:

A. B. Renz et al., "Development of high-quality gate oxide on using atomic layer deposition," in Materials Science Forum, Trans Tech Publications Ltd, 2020, pp. 547-553. doi: 10.4028/www.scientific.net/MSF.1004.547.

G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High- gate dielectrics: Current status and materials properties considerations," J Appl Phys, vol. 89, no. 10, pp. 5243-5275, May 2001, doi: 10.1063/1.1361065.

S. Tanimoto, "Highly reliable gate dielectric on ," Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), vol. 90, no. 5, pp. 1-10, May 2007, doi: 10.1002/ecjb.20329.

T. Hosoi et al., "AlON/SiO2 stacked gate dielectrics for 4H-SiC MIS devices," in Materials Science Forum, Trans Tech Publications Ltd, 2009, pp. 541-544. doi: 10.4028/www.scientific.net/MSF.615-617.541.

H. Watanabe et al., " (Invited) Impact of Stacked AlON/SiO 2 Gate Dielectrics for SiC Power Devices ," ECS Trans, vol. 35, no. 2, pp. 265-274, Apr. 2011, doi: 10.1149/1.3568869.

A. B. Renz et al., "Initial investigations into the MOS interface of freestanding 3C-SiC layers for device applications," Semicond Sci Technol, vol. 36, no. 5, May 2021, doi: 10.1088/13616641/abefa1.

G. Colston et al., "Three-Dimensional Epitaxy of Low-Defect 3C-SiC on a Geometrically Modified Silicon Substrate," Materials, vol. 17, no. 7, Apr. 2024, doi: 10.3390/ma17071587.

F. Li, S. Qiu, M. Jennings, and P. Mawby, "Reliability study of mos capacitors fabricated on 3c-sic/si substrates," in Materials Science Forum, Trans Tech Publications Ltd, 2020, pp. 659664. doi: 10.4028/www.scientific.net/MSF.1004.659.

A. Schöner, M. Krieger, G. Pensl, M. Abe, and H. Nagasawa, "Fabrication and characterization of 3C-SiC-based MOSFETs," Chemical Vapor Deposition, vol. 12, no. 8-9, pp. 523-530, Aug. 2006, doi: 10.1002/cvde. 200606467.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 75-79

doi: 10.4028/p-qAFI4Q

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-28

Accepted:
2025-08-28

Online:
2025-09-08

Deep Implanted SiC Super-Junction Technology

The original version of this paper is available on https://www.scientific.net/MSF.1158.75.pdf

R. Ghandi , C. Hitchcock , S. Kennerly

GE Aerospace Research, Niskayuna, New York 12309, U.S.A.

ghandi@ge.com, collin.hitchcock@ge.com, stacey.kennerly@ge.com

Keywords: SiC Superjunction, MOSFET, Deep Implantation

Abstract

GE Aerospace is developing a novel fabrication method for devices using ultrahigh energy deep implantation and epitaxial overgrowth. We report succesful fabrication of the world's first 3.5 kV SiC SJ deep implanted junction barrier Schottky (JBS) diodes and 5 kV SiC SJ deep implanted MOSFETs, which exhibit record low specific on-resistance (Ron,sp) and superior breakdown voltages. This innovative method offers a scalable path towards more efficient mediumvoltage converters, outperforming traditional SiC unipolar devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.75.pdf

Medium-voltage (MV) power conversion systems ( ) are currently limited to switching frequencies of several hundred hertz or below due to losses in solid-state switches and diodes. The existing conventional wide-bandgap solutions for MV-class switches and diodes are constrained by the lack of availability of uniform high-quality, very lightly doped thick SiC epitaxial layers with low defect densities. Additionally, conventional SiC unipolar switches and diodes rated suffer from high conduction losses at high temperatures. SiC SJ devices promise the best performance at , with lower conduction loss at elevated temperature.Prior to this work, multiepitaxial SiC SJ devices have been demonstrated [1-4]. Fabricating such devices by conventional ion implantation of dopants requires many iterations of epi regrowth due to the shallow depth of conventionally implanted atoms in SiC. GE Aerospace is currently exploring a novel fabrication architecture for devices using ultra-high energy deep implantation and epitaxial overgrowth.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1158.75.pdf

GE's deep-implanted SJ technology is based on processes developed for charge-balanced (CB) devices, an intermediate structure between conventional and superjunction designs [56]. In these devices, the drift layer consists of buried p-type charge-balanced regions that are electrically connected to the top anode or source terminal via high-energy implanted regions, referred to as P-Bus[Ref]. We demonstrated that these devices achieve record-low differential on-resistance, which is lower than the SiC 1D-unipolar limit. However, CB devices exhibited a temperature-dependent turn-on delay that decreased at higher temperatures. We showed that the delay originated from the high resistance of the low-doped P-Bus, which decreases at higher temperatures due to the higher ionization rate of p-type charges. Recently, the team demonstrated the world's first 3.5 kV SiC SJ deep implanted junction barrier

Fig. 1. SEM image of 3.5 kV ( epi and deep-implanted) SiC SJ-JBS diode.

Fig. 1. SEM image of 3.5 kV ( epi and deep-implanted) SiC SJ-JBS diode.

Schottky (JBS) diodes (Fig. 1). These devices are formed through a small number of thick ( each) epitaxial overgrowths. After each overgrowth, deep high-energy implants form P-doped and N-doped pillars extending through the full epilayer. Fig. 2 shows atwo layer SJ-JBS diode with an Ron,sp of at room temperature and at , which is below the SiC unipolar limit. The breakdown voltage is 3.8 kV with low leakage prior to breakdown.

Fig. 2. Forward and reverese characteristics of 3.5 kV SiC deep implanted SJ JBS diodes.

Fig. 2. Forward and reverese characteristics of 3.5 kV SiC deep implanted SJ JBS diodes.

Reverse recovery measurements of SiC SJ diodes were performed using ITC57300/57220 with results shown in Fig. 3. No change in the turn-off current and voltage waveforms were observed when the junction temperature increased from room temperature to and the total device capacitive charge is estimated at . The GE team also demonstrated the world's first 5 kV SiC SJ deep implanted MOSFETs (Fig. 4). These devices were formed with three rounds of ultra-high energy deep implantation and epitaxial overgrowth. The conduction and blocking characteristics of the 5 kV deep implanted SJ MOSFET are plotted in Fig. 5. The Ron,sp at room temperature is , which is

Fig. 3. Reverse recovery characteristics of 3.5 kV SiC deep-implanted SJ JBS diodes at room temperature and .

Fig. 3. Reverse recovery characteristics of 3.5 kV SiC deep-implanted SJ JBS diodes at room temperature and .

Fig. 4. SEM image of 5 kV ( epi and deep-implanted) SiC SJ-MOSFETs.

Fig. 4. SEM image of 5 kV ( epi and deep-implanted) SiC SJ-MOSFETs.

Fig. 5. Forward and reverese characetristics of 5 kV SiC deep implanted SJ.

Fig. 5. Forward and reverese characetristics of 5 kV SiC deep implanted SJ.

Fig. 6. Switching waveform characteristics of deep-implanted SJ MOSFETs under duple pulse testing.

Fig. 6. Switching waveform characteristics of deep-implanted SJ MOSFETs under duple pulse testing.

The ultra high enregy implantation required for fabrication of these devices results in a new processing challenge. To fully recover defects following implantation, SJ devices need to undergo a high temperature activation anneal at ; devices receiving only the conventional activation anneal at exhibit high leakage (Fig.7). This requirement emerged from an extensive Synchrotron X-ray Rocking Curve Topography (SXRCT) and Reciprocal Space Mapping (RSM) analysis, which revealed a high level of strain induced by high-energy implantation of Al and N in . The study showed that conventional annealing at was insufficient to recover the strain and suggests that higher annealing temperatures, as high as , lead to better lattice recovery.
Fig. 8 is a comparison between and deep implanted SJ devices and the SiC unipolar entitlement showing a scalable path toward realization of more efficient MV conveters.

Fig. 7. Comparison of the leakage current of 4.5 kV SiC SJ MOSFETs annealed at and .

Fig. 7. Comparison of the leakage current of 4.5 kV SiC SJ MOSFETs annealed at and .

Fig. 8. Comparison between s reported CB and deep-implanted SJ devices, together with the unipolar and SJ limits.

Fig. 8. Comparison between s reported CB and deep-implanted SJ devices, together with the unipolar and SJ limits.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1158.75.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DEAR0000674 and DEAR0001007 advised by Program Director Isik Kizilyalli. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.75.pdf

T. Tanaka et.al. 2018 IEEE Int. Electron Devices Meet., p. 8.2.1-8.2.4.

M. Baba, . ISPSD, 2021, pp. 83-86.

H. Cheng et al., "36th ISPSD, Jun. 2024, pp. 13-16.

R. Kosugi et al., "ISPSD 2019s, May 2019, pp. 39-42.

R. Ghandi, . ISPSD, 2019, pp. 179-182.

R. Ghandi, . ISPSD, 2020, pp. 126-129.

T. Tanaka et al., " 2018 IEEE Int. Electron Devices Meet., pp. 8.2.1-8.2.4, 2019

Z.Chen , ECS Journal of Solid State Science and Technology, Volume 11, Number 6, 2022.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 81-86

doi: 10.4028/p-PnS5D9

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-08-20

Accepted:
2025-08-21

Online:
2025-09-08

Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

The original version of this paper is available on https://www.scientific.net/MSF.1158.81.pdf

Rydhem Grover , Kelly Turner , Gerard Colston , Arne B. Renz , Marina Antoniou , Peter Gammon , Philip. A. Mawby , Vishal A. Shah

School of Engineering, University of Warwick, Coventry, CV4 7AL, United Kingdom

rydhem.grover@warwick.ac.uk, kelly.turner@warwick.ac.uk, g.colston.1@warwick.ac.uk, p.a.mawby@warwick.ac.uk, vishal.shah@warwick.ac.uk

Keywords: trench filling epitaxy, 4H-SiC, superjunction, chemical vapor deposition

Abstract

Trench filling epitaxy on using trichlorosilane ( ) and hydrogen chloride has shown to improve the tolerance to trench angle misalignment relative to the [11 ] substrate direction in deeper trenches than previously reported. Extraction of growth rates from cross-sectional SEM shows that epilayer growth on the mesa corner facet is the most sensitive to trench misalignment, suggesting that HCl may mediate the facet growth rate within from to maintain symmetric growth.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.81.pdf

Trench filling epitaxy (TFE) is a practicable approach to produce high-voltage, energy efficient superjunction power electronic devices from silicon carbide [1,2]. For superjunction fabrication, TFE involves etching uniformly spaced trenches into an n -doped substrate and homoepitaxially refilling the trenches with p-doped material to produce a lateral stack of p-n junctions with a charge-balanced depletion region. To achieve this balance, trenches must be filled without the formation of voids to ensure an even doping distribution [3]. However, typical TFE by chemical vapor deposition (CVD) from silane and propane under hydrogen dilution, leads to faster SiC deposition at mesa tops than inside the trenches, which causes trenches to seal before filling can be completed [4-6]. The direction of epilayer growth near the mesa top is also shown to be sensitive to slight misalignment of the trench angle to the direction in (Fig. 1), which also can lead to premature trench closure by inclination of the growth angle [7,8].

Fig. 1. Schematic diagram of inclined epilayer growth on mesas due to trench/ substrate misalignment with and without HCl during CVD.

Fig. 1. Schematic diagram of inclined epilayer growth on mesas due to trench/ substrate misalignment with and without HCl during CVD.

Efforts to mediate the growth rate at the mesa top and improve trench filling rate and quality have focused on the use of halogenated agents, typically HCl or chlorinated precursors [9-12]. It is known that chloride compounds can improve the SiC growth rate on planar substrates, which is suggested to be caused by removal of condensed Si in the boundary layer and by the formation of surface-active intermediates, such as and . In trench filling, HCl also has the benefit of acting as a spatially selective etchant, favoring etching near the mesa tops rather than inside the trenches, which can prevent trench-sealing overgrowth. Recently, it is also shown that HCl can improve the processing window for TFE by increasing the tolerance for trench angle misalignment to the substrate [15]. In this report, the relationship between misalignment angle, epilayer growth rate and the role of HCl are considered. Although improved misalignment tolerance improves trench filling, voids remain present in this work due to the influence of other factors affecting trench filling, such as trench aspect ratio, sidewall angle and tuning of the CVD conditions and chemistry. The relationship between void size and misalignment tolerance is not directly extracted and is therefore not discussed.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1158.81.pdf

Commercial doped substrates off-cut by in were coated with a 500 nm layer of by low-pressure chemical vapor deposition (LP-CVD) at via tetraethyl orthosilicate (TEOS). The trench pattern was then applied to the wafer by photolithography using AZ5214E photoresist and subsequent sputtering of a 900 nm thick Ni layer at from an Ar plasma at 140 W RF power with a 30 sccm Ar injection rate. After the photoresist and excess Ni was removed by solvent lift-off in acetone/ isopropanol, trenches were etched to and depth by ICP-RIE in an / Ar plasma at respective RF and LF powers of 60 W and 1000 W . To prepare the trenches for epitaxy, the remaining Ni and oxide layers were removed by a full RCA clean.

Trench epitaxy was performed using an LPE ACiS-M8 reduced-pressure (RP)-CVD at and 100 mBar with the susceptor rotating at 60 rpm . Facets at mesa corners were introduced by ramping the temperature from to the growth temperature under flow prior to growth. Source gases were used at fixed flow rates of and with dilution to grow a epilayer at . Growth was completed both with and without HCl , which was added at a flow rate of 500 sccm . In all cases, doping markers were added for every of growth by 30 s bursts of . The samples are characterized by cross-sectional SEM recorded on the ( ) plane by cleaving through the trench patterns along the direction.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.81.pdf

Trench Refill Misaligned to the Direction. It is previously shown that using a chlorinated growth process in trench filling epitaxy can significantly improve the tolerance for trench misalignment to the direction [14]. This effect has been replicated here for trenches of both and depth ( pitch), shown by a plot of trench misalignment angle ( ) versus epilayer growth angle ( in Fig. 2a. Using doping markers recorded by cross-sectional SEM of refilled trenches, the angle at which adjacent growing surfaces fuse over time, denoted as shows how far the epilayer growth deviates from vertical as the trench direction is varied about (Fig. 2c). Similar to previously reported data, using and in the growth process allows vertical epilayer growth ( ) even when the trench angle is misaligned at , indicated by the green shaded section in Fig. 2a. A so far unreported trend emerges when the misalignment is in magnitude, where growth begins to straighten by from a local maximum at . This is visualized in Fig. 2c by arrows marked on cross-sectional SEM images of deep filled trenches. Notably, misalignment at negative angles seems to cause a further deviated growth angle of approximately relative to positive misalignment angles.

Fig. 2. a) Graph of trench misalignment angle versus epilayer growth angle for and deep trenches refilled under 500 sccm of HCl . b) Graph of difference in facet growth rate on each side of the trench (left axis) and the magnitude of the epilayer growth angle (right axis) versus trench misalignment angle. c) Cross-sectional SEM images recorded on the ( ) plane of deep trenches from to misalignment, showing inclined growth marked by the arrow direction.

Fig. 2. a) Graph of trench misalignment angle versus epilayer growth angle for and deep trenches refilled under 500 sccm of HCl . b) Graph of difference in facet growth rate on each side of the trench (left axis) and the magnitude of the epilayer growth angle (right axis) versus trench misalignment angle. c) Cross-sectional SEM images recorded on the ( ) plane of deep trenches from to misalignment, showing inclined growth marked by the arrow direction.

Initial growth rates can be extracted by measuring the thickness of the epilayer at the first doping marker on each trench surface (top, bottom, sidewall and facet shown in Fig. 2c). For the deep trenches, the growth rate on the mesa top and trench bottom are unaffected by , remaining at and , respectively. However, the sidewall growth rate varies from to and can be asymmetric at each side of the trench, leading to a discrepancy of up to at . Most significantly, the growth rate on the facet (top corner of the mesa) is dependent on , varying from to with a difference between left and right facet growth of up to at . The difference in facet growth rate for each misalignment angle is plotted in Fig 1b (left axis) with the magnitude of (right axis) showing a clear correlation between asymmetric facet growth and deviated overall epilayer growth. Since HCl has been shown to etch the SiC epilayer near the mesa top and on the facet, it is possible that HCl improves trench misalignment tolerance through controlling growth at the facet by crystal plane dependent etching [8, 9]. As misalignment will expose difference facet and sidewall surfaces, their activity for both growth and etching will likely be asymmetric, accounting for non-vertical epilayer growth.

Fig. 3. a) Plot of step angle versus trench misalignment angle for deep, pitch trenches filled under 500 sccm HCl . Step angle refers to the surface step direction in the epilayer overgrowth relative to the trench direction. b) Top-down SEM images of the epilayer overgrowth for trenches filled under 500 sccm HCl , showing surface step angles.

Fig. 3. a) Plot of step angle versus trench misalignment angle for deep, pitch trenches filled under 500 sccm HCl . Step angle refers to the surface step direction in the epilayer overgrowth relative to the trench direction. b) Top-down SEM images of the epilayer overgrowth for trenches filled under 500 sccm HCl , showing surface step angles.

Further evidence for HCl affecting growth on corner facets is observed by top-down SEM of the epilayer surface. Fig. 4 shows the epilayer surface of deep trenches filled without HCl at varied misalignment angles. The direction of surface steps is observed, which shows a single step direction for each misalignment angle, that decreases from from the trench direction at and at . Notably, the step direction for trenches aligned to the direction is , rather than , which are present in the substrate and would be expected to be inherited by the epilayer for step-flow growth on a planar 4 H -SiC substrate. This may indicate that facet or sidewall growth can cause a twisting of the overall growth direction, since both facets and sidewalls will exhibit different surface structures based on the trench misalignment angle.

Comparing the epilayer step directions for trenches filled without HCl (Fig. 4) and with HCl (Fig. 3) shows a clear difference, especially at low ( ) misalignment angles. Surface steps at show two symmetric directions at and from the trench direction, compared with the single step at for trenches filled without HCl .

Fig. 4. Top-down SEM images of epilayer overgrowth on refilled deep, pitch trenches filled without HCl . Images are recorded with the stage tilted away from the viewing angle. Annotations mark the surface step angle relative to the trench direction.

Fig. 4. Top-down SEM images of epilayer overgrowth on refilled deep, pitch trenches filled without HCl . Images are recorded with the stage tilted away from the viewing angle. Annotations mark the surface step angle relative to the trench direction.

According a plot of step angle versus trench misalignment angle shown in Fig. 3a, which was extracted from top-down SEM images partly presented in Fig. 3b, the step angle abruptly increases from to at and decreases to 70 at . This twist is followed by an approximately linear deviation in step angle from misalignment angles of to , with a larger deviation observed at . This trend reflects that of the growth angle extracted from cross-sectional SEM and, therefore, suggests that an appearance of two symmetric step directions indicates vertical growth. While the mechanism of this can only be conjectured from these empirical data, it can be suggested that the step angle may be controlled by the relative epilayer growth rates on the trench sidewall, facet and mesa top, causing a twist in step angle. The difference in step angles between trenches filled with and without HCl may, therefore, by rationalized by HCl acting as a mediator for the facet growth rate for trench directions from , which may expose surface structures more susceptible to etching by HCl compared with those exposed at higher degrees of misalignment.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1158.81.pdf

Using a chlorinated gas mixture in trench filling CVD on can help to minimize epilayer growth inclination caused by misalignment of the trench direction to the substrate direction. Using HCl in refill epitaxy has broadened the processing window for photolithography processing to allow a error in mask alignment, and this effect seems independent of the trench depth. Based on the relationship between mesa corner facet growth rate and trench misalignment angle, asymmetric facet growth accounts for epilayer deviation, indicating that HCl most likely controls growth on the facets and its activity depends on the stability of the exposed facet.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.81.pdf

T. Kimoto, High-Voltage SiC Power Devices for Improved Energy Efficiency, Proc. Jpn. Acad. Ser. B Phys. Biol. Sci., 98 (2022) 161-189

V. Veliadis, SiC Mass Commercialization: Present Status and Barrier to Overcome, Mater. Sci. Forum, 1062 (2022) 125-130

F. Udrea, G. Deboy and T. Fujihira, Superjunction Power Devices, History, Development, and Future Prospects, IEEE Transactions on Electron Devices, 64 (2017) 713-727

R. Kosugi, Y. Sakuma et al, Development of SiC Super-Junction (SJ) Device by Deep TrenchFilling Epitaxial Growth., Mater. Sci. Forum, 740-742 (2013) 785-788.

S. Ji, K. Kojima, R. Kosugi et al, Influence of Growth Pressure on Filling 4H-SiC Trenches by CVD Method, Jpn. J. Appl. Phys., 55 (2015) 01AC04

S. Ji, R. Kosugi et al, A Study of CVD Growth Parameters to Fill Deep 4H-SiC Trenches, Mater. Sci. Forum, 963 (2019) 131-135

Y. Ishida, Proposal of the Mechanism for Inclination Growth on a Mesa Top During 4H-SiC Trench Filling Epitaxy, Jpn. J. Appl. Phys., 56 (2017) 070307

R. Kosugi, J. Shiyang, K. Mochizuki et al, Strong Impact of Slight Trench Direction Misalignment from [11-20] on Deep Trench-Filling Epitaxy for SiC Super-junction Devices, Jpn. J. Appl. Phys., 56 (2017), 04CR05

S. Ji, R. Kosugi et al, An Empirical Growth Window Concerning the Input Ratio of HCl/ SiH4 Gases in Filling 4H-SiC Trench by CVD, Appl. Phys. Express, 10 (2017), 055505

S. Ji, R. Kosugi et al, CVD Filling of Narrow Deep 4H-SiC Trenches in a Quasi-Selective Epitaxial Growth Mode, Mater. Sci. Forum, 924 (2018) 116-119

Z. Zhao, Y. Li et al, 4H-Trench Filling by Chemical Vapor Deposition Using Trichlorosilane as Si-Species Precursor, J. Cryst. Growth, 607 (2023) 127104

K. Turner, G. Colston et al, Effect of Mesa Sidewall Angle on 4H-Silicon Carbide Trench Filling Epitaxy Using Trichlorosilane and Hydrogen Chloride. Adv. Mater. Interfaces, (2024) 2400466

Ö. Danielsson, Understanding the Chemistry in Silicon Carbide Chemical Vapor Deposition, Mater. Sci. Forum, 924 (2018) 100-103

P. Sukkaew, E. Kalered et al, Growth Mechanism of SiC Chemical Vapor Deposition: Adsorption and Surface Reactions of Active Si Species, J. Phys. Chem. C, 122 (2017) 648-661

G. Colston, K. Turner et al, Epitaxial Trench Refill of 4H-SiC by Chlorinated Chemistry, Appl. Phys. Lett., 124 (2024) 192102

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/processes-in-devices-fabrication/978-3-0364-1911-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1158, pp 87-91

doi: 10.4028/p-RDZf7r

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-16

Accepted:
2025-08-17

Online:
2025-09-08

Study of SiC Trench Etching Characteristics for Different Crystal Planes

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

Akhil Ranjan , Lakshmi Kanta Bera , Shiv Kumar , Huamao Lin , Umesh Chand , Navab Singh , Surasit Chung , Abdul Hannan Yeo , Voo Qin Gui Roth , Arvind Sundaram , Liu Liyuan , and Jasmine Woo Yuen Kam

Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), 2 Fusionopolis Way, Innovis #08-02, Singapore 138634, Republic of Singapore

ranjan_akhil@a-star.edu.sg, lakshmi_kanta_bera@a-star.edu.sg, shiv_kumar@a-star.edu.sg, dlin_huamao@a-star.edu.sg, chand_umesh@a-star.edu.sg, navab@a-star.edu.sg, surasit_chung@a-star.edu.sg, hannan_yeo@a-star.edu.sg,

Keywords: Crystal angle, Trench etching, Profile angle, Trench depth, Sidewall roughness

Abstract

We have successfully demonstrated comprehensive trench etching of across various crystal orientations. The results show that both the trench profile and etching depth are unaffected by changes in crystal plane orientation. We achieved our target trench etching depth of , with vertical sidewall profile angles ranging from to for different crystal planes. Additionally, we performed a qualitative analysis of sidewall roughness for various crystal planes using a 3DAFM scan. It was observed that crystal angles from to relative to the ( ) plane exhibited lower surface roughness. We have also explained the mechanisms associated with these surface roughness characteristics.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

Superior properties of SiC, such as a wide band gap, high breakdown electric field, large thermal conductivity, and the ability to withstand high voltage, are highly beneficial for high power and high voltage device applications [1]. Out of three types of SiC-based devices, two types of vertical devices, the surface channel and the trench channel, have been commercialized. SiC trench power MOSFETs offer a high drive capability due to their ultra-low on-resistance, high channel mobility, and high breakdown voltage [1,2]. Extensive research has been conducted on the properties of A-face or M-face trench MOSFETs [3, 4], but there is limited literature available on trench MOSFETs in different crystal planes [5]. To the best of our knowledge, no thorough study has been conducted on the etching characteristics of SiC trenches in relation to different crystal orientation planes. This report presents a comprehensive study, for the first time, on SiC trench etching depth, sidewall profile angle, and sidewall surface morphology in relation to various crystal plane orientations.

Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

To initiate the study, a mask layout was designed with different crystal angles, each corresponding to a specific crystal plane orientation. The fabrication process was started by depositing a hard mask on a 4-degree offcut, 6" 4H-SiC wafer and subsequently patterning it. Next, a dry etching process was employed to etch the oxide hard mask under a photoresist (PR) mask using gas chemistries. Subsequently, PR was stripped using plasma, and SiC trench etching was accomplished using a dry etching method with gas chemistries under the oxide hard mask, which exhibited a SiC /oxide selectivity of . A cyclic recipe in loops with alternating gas chemistries was employed to achieve an anisotropic dry etch profile and a trench shape with vertical sidewalls, without micro-trenching. Each loop in the recipe consisted of 3 steps, having suitable gas chemistry for physical sputtering, SiC etching, and biproducts polymer removal during etching. The etching thickness and profile were verified using surface profiler measurements and a DRSEM scan. It was followed by the post-etch polymer removal using the NE14 wet clean method. Further, the
remaining oxide hard mask was removed using buffer oxide etchant (BOE), resulting in the final SiC trench profile. To analyze the trench etching depth and the sidewall profile, Focused Ion Beam Scanning Electron Microscopy (FIB/SEM) scans were conducted for each crystal angle. A qualitative analysis of the sidewall roughness for each crystal plane was performed using a 3DAFM scan.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

The lattice parameters for all the crystal planes were theoretically calculated for each crystal angle. Subsequently, the corresponding crystal images were obtained by inserting the lattice parameters into the crystal maker software. Table 1 lists the crystal plane orientation, crystal images, and the mask layout corresponding to various crystal angles. In addition, the resulting FIB/SEM and DRSEM images of the SiC trench-etched profile for each crystal plane orientation are provided in this table. One of the undesirable phenomena that mostly occurs during SiC etching is microtrenching, in which the etching at the edge of the trench is faster than at the centre [6]. This particular effect results in electric field crowding in the micro-trench region and causes early device breakdown. The SiC trench profile for each crystal angle was obtained with a vertical sidewall and without microtrenching, as shown in the FIB/SEM images. Please note that, during FIB//SEM inspection, Platinum is coated on the sample for SEM measurement. Arrow like structures in the center of the trench is coming from the Platinum coating on the sample.

Table 1. Crystal images, mask lay-out and trench profile for various crystal planes.

Angle (°) | 0 | -15 | -30 | -45 | -60 | -75 | -90
Crystal plane | 11̄20 | 21̄2̄0 | 202̄0 | 31̄2̄0 | 42̄2̄0 | 86̄2̄0 | 11̄00
Crystal images | Crystal structure at 0° | Crystal structure at -15° | Crystal structure at -30° | Crystal structure at -45° | Crystal structure at -60° | Crystal structure at -75° | Crystal structure at -90°
Mask Lay-out | Mask layout at 0° | Mask layout at -15° | Mask layout at -30° | Mask layout at -45° | Mask layout at -60° | Mask layout at -75° | Mask layout at -90°
FIB/SEM | FIB/SEM image at 0° | FIB/SEM image at -15° | FIB/SEM image at -30° | FIB/SEM image at -45° | FIB/SEM image at -60° | FIB/SEM image at -75° | FIB/SEM image at -90°
DRSEM | DRSEM image at 0° | DRSEM image at -15° | DRSEM image at -30° | DRSEM image at -45° | DRSEM image at -60° | DRSEM image at -75° | DRSEM image at -90°

DRSEM scan was conducted at each stage of etching to verify the completion of the etching layer and to examine the sidewall profile of the etched layer. Fig. 1(a) shows the DRSEM image after the oxide hard mask etching and PR stripping. Following the SiC etching, the wafer underwent a wet clean using NE14, as depicted in Fig. 1(b). A distinct interface was observed between the oxide hard mask and the SiC etched surface, demonstrating the effectiveness of the etching process. Finally, Fig. 1(c) presents the SiC trench profile after the removal of the oxide hard mask.

Fig. 1. DRSEM scan profile after, Oxide hard-mask etching (a), SiC trench etching (b), and postoxide removal (c).

Fig. 1. DRSEM scan profile after, Oxide hard-mask etching (a), SiC trench etching (b), and postoxide removal (c).

The sidewall profile angles were extracted from the FIB/SEM images and plotted against the crystal angles, as illustrated in Fig. 2. The reported profile angle values are the median values of 4 measurement's locations. Achieving a vertical sidewall profile angle ( ) is essential for the optimal performance of Trench MOSFETs during the trench etching process. The plot shows that a vertical sidewall profile angle within the range was obtained across various crystal plane orientations, indicating that variations in crystal plane orientation do not impact the trench profile.

Fig. 2. Profile angle against the crystal angles.

Fig. 2. Profile angle against the crystal angles.

Furthermore, it is essential to investigate the trench etching depth for different crystal planes in order to estimate the etching rate, and understand the interactions between the etching gas chemistry and the corresponding crystal atoms and orientation. The trench depth is plotted against the crystal angles, as shown in Fig. 3. It can be observed from the plot that the targeted trench etching depth of was successfully achieved for various crystal planes. As expected, the trench profile and etching depth are not affected by the variation in crystal plane orientations, since the trench etching takes place in the C axis direction.

Fig. 3. Trench depth against the crystal angles.

Fig. 3. Trench depth against the crystal angles.

After etching the trench, it is crucial to analyze the roughness profile of the sidewalls. A rough sidewall has adverse effects on channel mobility, gate oxide leakage, and device reliability [3, 4]. A qualitative analysis of the sidewall roughness for each crystal plane was conducted using a 3D AFM scan, as shown in Fig. 4 (a). During the scan, tip moves inside the trench, scanning 1st sidewall to bottom surface, to 2nd sidewall, and finishes scan at top of the trench. Measurement is repeated for 8 adjacent points. Measurement corresponding to these points is shown as colored line in Fig. 4 (a) (iii). Average of these 8 points is taken as final roughness value. The root mean square (RMS) roughness characteristics for different crystal plane orientations against the crystal angles are depicted in Fig. 4 (b).

Fig. 4. 3DAFM scan profile (a), and RMS roughness against the crystal angles (b).

Fig. 4. 3DAFM scan profile (a), and RMS roughness against the crystal angles (b).

In the side wall images from the DRSEM scan, we observed the presence of striations on the trench sidewall, which is the main cause of surface roughness. Fig. 4 (b) illustrates that the crystal angles ranging from to exhibit a slightly higher roughness of 0.4 nm compared to the crystal angles of to . It has been previously demonstrated that dense structures are more easily smoothed by the dry etching process than loosely packed structures [7]. As depicted in the crystal images in Table 1, the crystallographic orientations of and are more closely packed, systematic, and homogeneous structures. This may be a possible reason for obtaining a smoother surface using plasma
etching and exhibiting lower surface roughness for these crystal angles. Further study is required to investigate this phenomenon. Additional improvement in the sidewall roughness can potentially be achieved by implementing post-trench annealing.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

This report presents a comprehensive study, for the first time, on SiC trench etching depth, the sidewall profile angle, and sidewall surface morphology in relation to various crystal plane orientations. SiC trench profile for each crystal angle was obtained with a vertical sidewall and without micro-trenching. Vertical sidewall profile angle (within the range of ) was obtained for various crystal plane orientations, indicating that the variation in crystal plane orientation does not affect the trench profile. The targeted trench etching depth of was achieved for various crystal planes. The etching depths are not affected by the variation in crystal plane orientations since the trench etching takes place in the C -axis direction. A qualitative analysis of the sidewall roughness for each crystal plane was conducted using a 3DAFM scan. The crystal angles ranging from to exhibit a slightly higher roughness of 0.4 nm compared to the crystal angles of to . Crystallographic orientations of and are more closely packed, systematic, and homogeneous structures, which may be a possible reason for obtaining a smoother surface using plasma etching and exhibiting lower surface roughness for these crystal angles.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

This work was supported by A*STAR (Agency for Science, Technology and Research Singapore), under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/MSF.1158.87.pdf

M. D. Pirnaci, L. Spitaleri, D. Tenaglia, F. Perricelli, M. E. Fragalà, C. Bongiorno, A. Gulino, Systematic characterization of plasma-etched trenches on 4H-SiC wafers, ACS Omega 6 (2021) 20667-20675.

B. Jones, J. Mitchell, J. Evans, F. Monaghan, M. Jennings, C. Bolton, K. Riddell, H. Ashraf, O. Guy, Introducing foundry-compatible SiC and GaN trench processing technologies for reliable automotive application, Mat. Sci. Forum 1062 (2022) 582-587.

W. Zhao, H. Ge, P. Wu, X. Bai, X. Wu and T. Zhu, Research on trench etching and photolithography process of SiC trench MOSFET, J. Phys.: Conf. Ser. 2083 (2021) 022093-99.

K. Kutsuki, Y. Murakami, Y. Watanabe, T. Onishi, K. Yamamoto, H. Fujiwara, T. Ito, Effect of surface roughness of trench sidewalls on electrical properties in trench MOSFETs, J. Appl. Phys. 57 (2018) 04FR02-06.

Z. Shen, F. Zhang, X. Liu, G. Sun, Y. Zeng, Influence of treatment on the surface morphology of SiC with different wafer orientation and doping, J. Crystal growth 607 (2023) 127105-127112.

D. Ruixue, Y. Yintang, H. Ru, Microtrenching effect of SiC ICP etching in plasma, J Semicond 30(1) (2009) 016001.

S.A.Rasgon, Thesis, Chem. Eng Dept, MIT, (2005)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Keywords Index

4

4 H -sic Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

4h-sic Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

A

Atomic Layer Deposition Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

B

Backside Metal Contact Resistance Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Bonded Substrate Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Boron Plasma Treatment Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

C

Chemical Vapor Deposition Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Chlorine Oxidation The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Circular Tlm Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Circular Tlm (ctlm) A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Cmos Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Conductive Heating Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Contact Resistivity A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Crystal Angle Study of SiC Trench Etching Characteristics for Different Crystal Planes

D

Deep Implantation Deep Implanted SiC Super-Junction Technology

E

Edge Termination Structure Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

H

High-k Dielectrics Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

L

Lower Pressure Oxidation The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

M

Monolithic Integration Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Mos Capacitor Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Mosfet Deep Implanted SiC Super-Junction Technology

O

Ohmic Contact A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Ohmic Contacts Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

P

P-type Isolation Structure Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

P-type SiC Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Post-deposition Annealing Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Profile Angle Study of SiC Trench Etching Characteristics for Different Crystal Planes

S

Sacrificial Oxidation Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Schottky Barrier Diode Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

SiC Gate Oxide The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

SiC Superjunction Deep Implanted SiC Super-Junction Technology

Sidewall Roughness Study of SiC Trench Etching Characteristics for Different Crystal Planes

Silicide Top Contact; Rapid Thermal Anneal (rta) Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Silicon Carbide Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Silicon Nitride Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Strain-induced Damage Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Superjunction Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

T

Temperature Dependence Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Thermal Oxidation The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Transmission Line Model (tlm) A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Trench Depth Study of SiC Trench Etching Characteristics for Different Crystal Planes

Trench Etching Study of SiC Trench Etching Characteristics for Different Crystal Planes

Trench Filling Epitaxy Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

V

Vdmosfet Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Authors Index

A

Antoniou, M. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing; Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

B

Beijersbergen, J. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Bellocchi, G. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Bera, L. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

Bolat, S. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

C

Chand, U. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

Chen, C. Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Chung, S. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

Colston, G. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing; Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

F

Fiorenza, P. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Flint, D. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Franco, S. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

G

Gammon, P. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing; Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Ghandi, R. Deep Implanted SiC Super-Junction Technology

Giannazzo, F. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Gong, X. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Gott, J. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Graham, A. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Greco, G. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Grover, R. Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Gunn, R. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

H

Harada, S. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Hatta, N. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Higashi, Y. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Hitchcock, C. Deep Implanted SiC Super-Junction Technology

Ho, S. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Hsiao, Y. Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Hsu, K. Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Huang, H. Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Hung, C. Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

I

Im, Y. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Ishikawa, S. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

J

Jang, Y. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Jefferies, R. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Jeong, C. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

K

Kam, J. Study of SiC Trench Etching Characteristics for Different Crystal Planes

Kennerly, S. Deep Implanted SiC Super-Junction Technology

Kerdilès, S. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Kim, I. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Kim, J. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Kobayashi, M. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Kojima, K. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Krause, S. Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

Kumar, A. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Kumar, S. Study of SiC Trench Etching Characteristics for Different Crystal Planes

Kuznetsov, V. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

L

Lee, J. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Lichtenwalner, D. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Lim, J. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Lim, S. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Lin, H. Study of SiC Trench Etching Characteristics for Different Crystal Planes

Lin, Y. Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

Linde, S. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Liu, L. Study of SiC Trench Etching Characteristics for Different Crystal Planes

M

Mancuso, P. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Mawby, P. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing; Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Mikhaylov, A. Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

Mikolajick, T. Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

Mio, A. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

N

Newton, A. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Nguyen, X. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Nicotra, G. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

O

Omar, M. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Oterdoom, J. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

P

Pages, X. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Park, G. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Park, J. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

Perera, K. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Powell, M. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Q

Quek, Z. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

R

Ranjan, A. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

Rascunà, S. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Reddy, V. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Renz, A. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing; Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Roccaforte, F. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Ryu, S. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model

S

Sanchez, M. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Schroeder, U. Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

Sezaki, H. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

Shah, V. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing; Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

Singh, N. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

Son, J. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Steltenpool, M. Rapid Thermal Anneal with Conductive Heating for SiC Contact Formation

Sundaram, A. Study of SiC Trench Etching Characteristics for Different Crystal Planes

T

Tsui, B. Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation; Impact of Silicon Nitride Stress on Defects Generation in 4H-SiC and the Effect of Sacrificial Oxidation on Defects Reduction

Turner, K. Improved Angle Tolerance in -SiC Trench Filling Epitaxy Using Chlorinated Chemistry

U

Uchida, H. Advantages of Backside Metal Contact Resistance on -SiC Bonded Substrates for Power Devices

V

Vivona, M. Evolution of the Electrical and Microstructural Properties of Mo/4H-SiC Contact with the Annealing Temperature

Voo, Q. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

W

Wachowiak, A. Impact of Interfacial Layer Thickness on the Electrical Performance of /High-k Stacks on -SiC

Wang, M. Isolation Structure for Monolithic Integration of Planar CMOS and 1.7 kV Vertical Power MOSFET on 4H-SiC by High Energy Ion Implantation

X

Xie, J. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Y

Yeo, A. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC; Study of SiC Trench Etching Characteristics for Different Crystal Planes

Yeo, Y. Plasma Treatment for Enhanced Ohmic Contact Performance to p-Type 4H-SiC

Yildirim, M. Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing

Yoon, J. The Investigation of Effective Thermal Oxidation to SiC MOSFET Gate Oxide Quality Improvement

Z

Zacks, J. A Simplified Method for Extracting Contact Resistivity Using the Circular Transmission Line Model