SiC Application and SiC Devices Reliability and Stability

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

SiC Application and SiC Devices Reliability and Stability

Special topic volume with invited peer-reviewed papers only

Edited by

Prof. Victor Veliadis and Dr. Arash Salemi

Sócientific.Net

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Volume1024 of
Key Engineering Materials
ISSN print 1013-9826
ISSN web 1662-9795

Full text available online at https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-12

Online:
2025-09-12

Preface

The original version of this paper is available on https://www.scientific.net/KEM.1024.-1.pdf

This special edition is devoted to problems of ensuring the functional stability and reliability of silicon carbide devices, as well as the analysis of specific applications of them as part of sensors in conditions of hard radiation and for use in quantum research.

The collection is organised into two chapters.
The first chapter addresses critical aspects of performance degradation, long-term stability, and reliability evaluation in SiC -based power devices, and the second chapter explores the expanding role of SiC in frontier technologies and extreme environments.

The special edition combines issues related to the reliability and stability of silicon carbidebased electronic devices with an analysis of engineering solutions for their applications in frontier technologies and extreme conditions, providing readers with a comprehensive overview of current advances and future directions of applications.

Table of Contents

Preface

Chapter 1: Analysis of Device Reliability and Characteristic Stability

Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Andrea Piccioni, Maximilian Wolfgang Feil, Thomas Aichinger

TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Shuo Ben Hou, Christoffer Lundgren, Wlodek Kaplan, Sergey Reshanov

Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Li Meng Shi, Michael Jin, Jia Shu Qian, Monikuntala Bhattacharya, Shiva Houshmand, Heng Yu Yu, Atsushi Shimbori, Marvin H. White, Anant K. Agarwal

Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Umesh Chand, Yu Chieh Chien, Abdul Hannan Yeo, Qin Gui Roth Voo, Shiv Kumar, Akhil Ranjan, Binni Varghese, Wei Jie Wang, Pavan Vudumula, Tamara Fidler, Patrick Schmid, Mario Saggio, Maurizio Castorina, Marco Camalleri, Jia Xie, Xiao Gong, Surasit Chung, Lakshmi Kanta Bera, Navab Singh, Yee Chia Yeo

Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

Madhu Lakshman Mysore, Darshan Koorana Prasanna Kumar, Chao Hao Wang, Josef Lutz, Thomas Basler

Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Olayiwola Alatise, Saeed Jahdi, Peter Michael Gammon, Jose Ortiz-Gonzalez, Mana Hosseinzadehlish, Konstantinos Floros, Ingo Ludtke

Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC Engineered Substrates

Mohamed Alaluss, Christoph Böhm, Madhu Lakshman Mysore, Patrick Heimler, Thomas Basler, Ahmed Elsayed, Karl Oberdieck, Sudhanshu Goel

Device Performance and Reliability of SiC CMOS up to

Emran K. Ashik, Sundar B. Isukapati, Hua Zhang, Tian Shi Liu, Utsav Gupta, Adam J. Morgan, Veena Misra, Woong Je Sung, Ayman Fayed, Anant K. Agarwal, Bong Mook Lee

Chapter 2: Quantum Applications, Sensors and Use in Space Engineering

SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Daniel B. Habersat, Anand Sampath, Greg Garrett, Michael Derenge, Franklin Nouketcha, Brenda VanMil, Michael Wraback, Jonathan Schuster, Jeremy Smith, Enrico Bellotti, Mike Zhu, Reza Ghandi, Mehrnegar Aghayan

Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

Kasif Teker, Mustafa Akif Yildirim, Tarik U. Teker

Fabrication of -SiC Low Gain Avalanche Detectors (LGADs)

Benjamin J. Sekely, Yashas Satapathy, Tao Yang, Greg Allion, Phillip Barletta, Steve Holland, Stefania Stucci, Carl Haber, Spyridon Pavlidis, John F. Muth

All Electrical Near-Zero Field Magnetoresistance Magnetometry up to Using SiC Devices

Fabrizio Sgrignuoli, Ivan Viti, Zhi Gang Yu, Elijah Allridge, Patrick M. Lenahan, Shubhodeep Goswami, Reza Ghandi, Mehrnegar Aghayan, David M. Shaddock

SiC in Space: Potential High-Power Application Survey

Antxon Arrizabalaga

SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space

Antxon Arrizabalaga

Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

Antxon Arrizabalaga

Keywords Index

Authors Index

Chapter 1

Analysis of Device Reliability and Characteristic Stability

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 3-7

doi: 10.4028/p-M3e3xl

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-03

Revised:
2025-05-30

Accepted:
2025-05-30

Online:
2025-09-12

Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

The original version of this paper is available on https://www.scientific.net/KEM.1024.3.pdf

Andrea Piccioni , Maximilian W. Feil , Thomas Aichinger

Infineon Technologies Austria AG - Siemensstraße 2, 9500 Villach, Austria (AT)

andrea.piccioni@infineon.com, maximilian.feil@infineon.com,

Keywords: Bias Temperature Instability (BTI), Gate Switching Instability (GSI), Gate Switching Stress (GSS), Threshold Voltage, On-State Resistance, Drift, Degradation, Switching Energy, Power Converter Application.

Abstract

In addition to the well-known bias temperature instability (BTI) phenomena, recently, it has been revealed that SiC MOSFETs show another instability during high-frequency repetitive switching between and , referred to as gate-switching instability (GSI). This study shows the increase in switching energy caused by gate-switching instability drift as key performance parameters in electric power conversion systems, especially, when operating in hardswitching mode. A new methodology based on double pulse test was applied at each readout. The results highlighted the significance of the degradation mechanism through its impact on hardswitching applications with high-switching frequency. Therefore ruggedness against GSI plays a pivotal role in the long-term re- liable operation of SiC MOSFET devices to ensure durable and efficient power conversion systems.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.3.pdf

The increasing adoption of SiC MOSFETs is attributed to their superior performance characteristics compared to conventional silicon-based power devices. The advantages of SiC MOSFETs are their ability to operate at elevated temperatures, lower switching losses due to their faster switching speeds, and higher critical electric field strength; resulting in improved efficiency and reduced energy losses. Consequently, SiC MOSFETs are well-suited for high-power applications such as electric vehicles, renewable energy systems, and industrial power supplies. However, since the early days of SiC MOSFET development, the interface has posed a challenge [1]. Significant advancements in reducing the defect density at the interface significantly boosted the commercialization of SiC MOSFETs, however, both research and academia are still striving to reduce it even further. The bias temperature instability (BTI) in MOSFETs has been a well-documented phenomenon for decades, previously observed in silicon p-MOSFETs [2][3]. Recently, a new degradation mechanism affecting the long-term reliability of SiC MOSFET devices, known as gate-switching instability (GSI), has been identified. This phenomenon superimposes BTI effects but is triggered only under repetitive gate-switching stress (GSS) between a negative ( ) and a positive ( ) gate bias. Since its discovery in 2018 by Infineon Technologies AG, GSI has been extensively studied [4][5][6] to understand its physical motivations and dependencies, leading to advanced modeling approaches [7]. In addition to Infineon Technologies AG, other semiconductor manufacturers [8] and research groups [9][10] have also contributed to improving the understanding of this phenomenon. Recently, it was discovered that VDS bias in GSS can cause an additional impact on GSI [11]. As this is the latest discovery, the effect of is not included in this study. Additionally, [12] shows that the devices also used in this paper (from manufacturer M1) don't show Vds influence during GSS. While significant research has focused on electrical characteristics (parametric screening of , V ) over the time/cycle of stress, little attention has been given to the switching losses impact. The novel method proposed in Fig. 1a quantifies the application impact of the drift caused by
the GSI (with stress parameters as close as possible to real usage), by monitoring turn-on - Eon - and turn-off - Eoff - energy at each readout. This approach is used to strengthen the understanding of this phenomenon in the application of power conversion systems.

Fig. 1. (a) Proposed GSS methodology with electrical parameters readout and novel double pulse tests. (b) Violin plots with gate-source threshold voltage from the two manufacturers at their pristine state, calculated relative to their median.

Fig. 1. (a) Proposed GSS methodology with electrical parameters readout and novel double pulse tests. (b) Violin plots with gate-source threshold voltage from the two manufacturers at their pristine state, calculated relative to their median.

Proposed GSS with Dynamic Switching Performance Monitoring

The original version of this paper is available on https://www.scientific.net/KEM.1024.3.pdf

Method Description. To ensure a comparison of technologies and a sufficient statistical population, 23 SiC MOSFET devices in the TO-247-4 package from each of the two vendors are stressed and measured. Figure 1 b shows their distribution. The devices of manufacturer 1 (M1) were generation trench SiC MOSFETs, and the devices of manufacturer 2 (M2) were generation planar SiC MOSFETs. Although the devices from both M1 and M2 were in the range, their gate charge ( ) differed significantly ( and ). Therefore, the gate resistance ( ) was selected accordingly to ensure a fair comparison. Figure 1a illustrates the proposed application-oriented gate-switching stress (GSS) measurement procedure, which incorporates double pulse tests (DPTs) at each readout to simulate real-world operating conditions. In accordance with the JEP195 guideline [13], the key GSS parameters are defined in Table 1 with a focus on application-driven requirements. At each readout, the following stress levels were applied:

24 hours equivalent of cycles

1000 hours equivalent of cycles: Representative of the end point in time of a given application profile (EoAP)

Electrical parameters were monitored, and double pulse tests were performed at each readout. For completeness, the JEP195 guideline [13] encourages comparing at least exemplary switching behavior and switching losses before and after GSS. The boundary conditions for the double pulse test for the two manufacturers are listed in Table 1. The same 1200 V SiC Schottky Diode IDW40G120C5B was used as a high-side device in the double pulse test half-bridge leg.

Results: Electrical Parameters. Figure 2a illustrates the values of the devices under test (DUT) after 24 hours and 1000 hours of gate-switching stress (GSS), referenced to their pristine values. A notable difference in drift is observed between the devices from manufacturer 1 (M1) and manufacturer 2 (M2). Specifically, the median drift after 24 hours was , and after 1000 hours, indicating a relatively stable threshold voltage. In contrast, the median drift after 24 hours was , and after 1000 hours, suggesting a more pronounced degradation of the threshold voltage. The static performance of the devices, characterized by the on-state resistance ( ), deteriorated proportionally to the drift due to the reduction in over-drive voltage, which is the difference between the gate-source voltage ( ) and the threshold voltage . Figure 2b shows that the median drift was after 24 hours and after 1000 hours, indicating a relatively small increase in on-state resistance.

In contrast, the median drift was after 24 hours and after 1000 hours, suggesting a more significant degradation of the on- state resistance. These results suggest that the M1 devices demonstrated a higher ruggedness against electrical parameter drift caused by GSI, which is a critical aspect of device reliability.

Fig. 2. Violin plots with electrical parameter readouts from the two manufacturers over the test hours, relative to the electrical parameter readouts at their pristine state (a) gate-source threshold voltage (b) drain-source on-state resistance.

Fig. 2. Violin plots with electrical parameter readouts from the two manufacturers over the test hours, relative to the electrical parameter readouts at their pristine state (a) gate-source threshold voltage (b) drain-source on-state resistance.

Table 1. Application-relevant GSS and DPT parameters - * max values by datasheets.

| Gate-switching stress | Double-pulse test
Param. | VGS(H)* | VGS(L)* | fsw | Tmeas | Tstress | VDC | ID | Rg | Tvj | VGS
Unit | V | V | kHz | °C | °C | V | A | Ω | °C | V
M1 | 23 | -7 | 500 | 25 | 125 | 800 | 9,20 | 33m 56, 100 | 25 | -2, +18
M2 | 19 | -8 | 500 | 25 | 125 | 800 | 9,20 | 15, 33, 56 | 25 | -4, +15

Fig. 3. Violin plots with double pulse test readouts from the two manufacturers at 1000 hours, relative to the double pulse test readouts at their pristine state (a) at 20 A function of external gate resistance (b) En function of drain current with and .

Fig. 3. Violin plots with double pulse test readouts from the two manufacturers at 1000 hours, relative to the double pulse test readouts at their pristine state (a) at 20 A function of external gate resistance (b) En function of drain current with and .

Results: Dynamic Performance. The drift of electrical parameters, such as and the transfer characteristic, have a direct impact on the device performance during turn-on and turn-off events, which are respectively represented by and . While an increase in is beneficial for Eoff, it has the opposite effect on Eon. However, Eon is typically 2.5-to 4 times higher in magnitude than Eoff, which means that improvements in Eoff have only a marginal impact on the total losses in the hard-switching applications. Therefore, it is essential to focus on the turn-on event, which dominates the total losses. Figure 3a illustrates the values after 1000 hours of GSS, referenced to their pristine values. The results indicate a minor decrease in the performance of the devices from manufacturer 1 (M1), which is consistent with the lower drift. Specifically,
the increment in median with was after 1000 hours, suggesting a relatively small increase in turn-on energy losses. In contrast, the increase in median with was , indicating a more significant degradation of its turn-on performance. Figure 3b shows the values after 1000 hours of GSS, referenced to their pristine values. The impact of current density on devices from M2 is noteworthy, unlike the quasi-constant behavior of devices from M1. This suggests that the devices from M2 are more prone to aggravated degradation of their dynamic performance at higher current densities, which can become critical for their performance and reliability in applications with overload requirements.

Summary and Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1024.3.pdf

In conclusion, the long-term reliability of SiC MOSFET devices is dependent on their ability to withstand GSI, which can significantly impact the performance and efficiency of power conversion systems. The proposed method with its application-driven approach provides a unique perspective on the consequences of GSI, highlighting its profound effects on the dynamic performance of SiC MOSFET devices. The results of this study are remarkable: after 1000 hours of GSI stress, devices from manufacturer 1 (M1) exhibited a median drift of approximately , resulting in a moderate median increase of turn-on energy of only . In contrast, devices from manufacturer 2 (M2) suffered from a median drift of approximately , leading to a substantial median increase of turn-on energy of 7.69%, which can have significant implications for end-of-application profile operation. These findings clearly demonstrate that ruggedness against GSI should be of major priority when selecting SiC MOSFETs for a demanding application. This is important for designers and engineers to ensure the development of efficient and reliable power conversion systems that meet the stringent requirements of modern applications. Further research into the application impact of GSI is essential for the continued advancement of SiC-based power conversion. Having realized this, Infineon has been extensively studying [6][7] and improving this new phenomenon and has provided customers with clear mitigation strategies and application-tailored design guidelines [14] to ensure reliability over the lifetime.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.3.pdf

J.A. Cooper et al. "Status and prospects for SiC power MOSFETs". In: IEEE Transactions on Electron Devices 49.4 (Apr. 2002), pp. 658-664. ISSN: 00189383. DOI: 10.1109/16.992876.

D.K. Schroder. "Bias temperature instability in silicon carbide". In: 2009 International Semiconductor Device Research Symposium. 2009 International Semiconductor Device Research Symposium (ISDRS 2009). College Park, MD: IEEE, Dec. 2009, pp. 1-2. ISBN: 978-1-4244-6030-4. DOI: 10.1109/ISDRS.2009.5378170.

Z. Chbili et al. "Unusual bias temperature instability in SiC DMOSFET". In: 2013 IEEE International Integrated Reliability Workshop Final Report. 2013 IEEE International Integrated Reliability Workshop (IIRW). South Lake Tahoe, CA, USA: IEEE, Oct. 2013, pp. 90-93. ISBN: 978-1-4799-0352-8 978-1-4799-0350-4 978-1-4799-0351-1. DOI: 10.1109 / IIRW . 2013 . 6804166.

Maximilian W. Feil et al. "Towards Understanding the Physics of Gate Switching Instability in Silicon Carbide MOSFETs". In: 2023 IEEE International Reliability Physics Symposium (IRPS). 2023 IEEE International Reliability Physics Symposium (IRPS). ISSN: 1938-1891. Mar. 2023, pp. 1-10. DOI: 10.1109/IRPS48203.2023.10117740.

Maximilian W. Feil et al. "Recent Developments in Understanding the Gate Switching Instability in Silicon Carbide MOSFETs". In: 2023 IEEE International Integrated Reliability Workshop (IIRW). 2023 IEEE International Integrated Reliability Workshop (IIRW). South Lake Tahoe, CA, USA: IEEE, Oct. 8, 2023, pp. 1-9. ISBN: 9798350327274. DOI: 10.1109/IIRW59383.2023.10477632.

Maximilian W. Feil et al. "Gate Switching Instability in Silicon Carbide MOSFETs-Part I: Experimental". In: IEEE Transactions on Electron Devices 71.7 (July 2024), pp. 4210-4217. ISSN: 0018-9383, 1557-9646. DOI: 10.1109/TED.2024.3397636.

Tibor Grasser et al. "Gate Switching Instability in Silicon Carbide MOSFETs-Part II: Modeling". In: IEEE Transactions on Electron Devices 71.7 (July 2024), pp. 4218-4226. ISSN: 0018-9383, 1557-9646. DOI: 10.1109/TED.2024.3397629.

Jaume Roig et al. "A Physics-Oriented Analysis of SiC Trench MOSFETs Under Gate Switching Stress Test Conditions". In: 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). Bremen, Germany: IEEE, June 2, 2024, pp. 100103. ISBN: 9798350394825. DOI: 10.1109/ISPSD59661.2024.10579599.

Huaping Jiang et al. "Dynamic Gate Stress Induced Threshold Voltage Drift of Silicon Carbide MOSFET". In: IEEE Electron Device Letters 41.9 (Sept. 2020), pp. 1284-1287. ISSN: 07413106, 1558-0563. DOI: 10.1109/LED.2020.3007626.

Amartya K. Ghosh et al. "Comparison of AC and DC BTI in SiC Power MOSFETs". In: 2022 IEEE International Reliability Physics Symposium (IRPS). 2022 IEEE International Reliability Physics Symposium (IRPS). Dallas, TX, USA: IEEE, Mar. 2022, 7A.2-1-7A.2-6. ISBN: 978-1-66547-950-9. DOI: 10.1109/IRPS48227.2022.9764494.

Sven Thiele et al. "Gate Switching Instability of SiC MOSFETs under Simultaneously High Drain-Source Voltage and High Frequency Acceleration". In: 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). Bremen, Germany: IEEE, June 2, 2024, pp. 136-139. ISBN: 9798350394825. DOI: 10.1109/ISPSD59661.2024.10579621.

M. Sievers et al. "Monitoring of parameter stability of SiC MOSFETs in real application tests". In: Microelectronics Reliability 114 (Nov. 2020), p. 113731. ISSN: 00262714. DOI: 10.1016/ j.microrel.2020.113731.

JEDEC. "Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-OxideSemiconductor Devices for Power Electronic Conversion". In: JEDEC, Feb. 1, 2023.

"Guidelines for CoolSiC MOSFET gate drive voltage window". In: Nov. 17, 2023.

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The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 9-13

doi: 10.4028/p-9eYPnN

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Accepted:
2025-03-16

Online:
2025-09-12

TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

The original version of this paper is available on https://www.scientific.net/KEM.1024.9.pdf

Shuoben Hou , Christoffer Lundgren , Wlodek Kaplan , Sergey Reshanov

Coherent, Inc., Isafjordsgatan 22B, Kista, Sweden

shuoben.hou@coherent.com, christoffer.lundgren@coherent.com, wlodek.kaplan@coherent.com, sergey.reshanov@coherent.com

Keywords: Time-dependent dielectric breakdown (TDDB), high temperature gate bias stress (HTGB), channel leakage, subthreshold swing, positive bias temperature instability (PBTI), negative bias temperature instability (NBTI).

Abstract

We identify one type of outlier SiC MOSFET device from massive parametric test that shows excessive channel leakage and abnormal subthreshold swing at low and low . Time-dependent dielectric breakdown (TDDB) and high temperature gate bias stress (HTGB) tests have been performed on these outlier devices to check their reliability. TDDB lifetime is shorter for a device with a higher Ss-th, but there is no indication that the Ss-th outliers would lead to an extrinsic failure. The post-PBTI curve of the outlier device is overall shifted rightward and the off-state leakage at is lower. The post-NBTI is reduced at and the off-state leakage is almost unchanged.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.9.pdf

Silicon carbide (SiC) device market is achieving a compound annual growth rate of driven specially by the rapid growth in the sales of electric vehicles [1]. Along with an accelerated expansion in production, SiC MOSFET manufacturing is still facing the issue of a relatively low yield compared to Si counterparts primarily due to defective substrate/epitaxy and a high interface trap density ( ) at the gate oxide-SiC interface. A thorough device screening method after processing is essential for a manufacturer to deliver reliable chips especially for automotive applications [2]. In this paper, we identify one type of outlier MOSFET device that shows excessive channel leakage and abnormal subthreshold swing ( ) at low and low . Such devices are difficult to detect in large-volume parametric tests because low-current tests are normally omitted to maintain a high throughput. A reliability study on these outliers is necessary to determine whether they should be screened out. We perform TDDB and HTGB tests following JEDEC guidelines [ 3,4 ] on these outlier devices and compare the results to nominal ones. Pre- and post- stress DC test of individual device is shown to see the device degradation in threshold voltage ( ) and off-state leakage current.

Method

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The device under test (DUT) in this paper are SiC MOSFET prototypes rated at 1.2 kV and encapsulated in TO-247 package. Room temperature DC characterizations, e.g. transfer Id-VG and off-state , are tested by Keithley high power source measurement units (SMU).

TDDB Test (constant-voltage stress). The DUT is placed in a high temperature socket in a preheated oven. After loading the sample and the selected temperature is stabilized, a DC bias voltage supplied by Keithley SMU is applied on the DUT until the device fails abruptly (IG reaching compliance). The time to failure is regarded as the TDDB lifetime of the device. A typical curve of IG over time is shown in Fig. 1. TDDB test in this paper has two conditions: (1) (electrical field at gate oxide) at and (2) at .

HTGB Test. The test is accomplished by measure-stress-measure method (see Fig. 2) following the JEDEC guidelines to evaluate both positive (PBTI) and negative (NBTI) bias temperature instability. The electric field applied on the DUT is and for PBTI and NBTI respectively. The time interval of the bias stress is logarithmically increased. Threshold voltage (VTH) of the DUT is extracted at from sweep tested in-situ between two intermediate stress biases. For PBTI, VTH is tested by sweeping the voltage from high to low after positive conditioning while for NBTI it is inverted.

Fig. 1. A typical curve of gate leakage current (IG) over time from a TDDB test.

Fig. 1. A typical curve of gate leakage current (IG) over time from a TDDB test.

Fig. 2. Waveform of the HTGB voltage under measure-stress-measure method.

Fig. 2. Waveform of the HTGB voltage under measure-stress-measure method.

Results

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The transfer curve of a device with abnormal is shown in Fig. 3 (red) together with a nominal one (black). The abnormal device has an excessive leakage current at low gate voltage instead of having a constant subthreshold slope. This excessive leakage also affects the device at off-state at , as shown in Fig. 4 (black solid). The outlier device shows two order of magnitude higher leakage current at and . Note that this leakage current is caused by defects in the gate which is distinguishable from a leakage caused by defects in the drift region because it can be eliminated by a reverse gate bias as shown in Fig. 4 (red solid).

Fig. 3. Transfer curves of a nominal device and a outlier.

Fig. 3. Transfer curves of a nominal device and a outlier.

Fig. 4. Off-state curves of a outlier at and a nominal one at .

Fig. 4. Off-state curves of a outlier at and a nominal one at .

The subthreshold swing at range is calculated by Eq. 1.

The nominal value of our fabricated devices is . About of the total number of our processed chips show much higher Ss-TH ( ).

Fig. 5. TDDB ( lifetime as a function of .

Fig. 5. TDDB ( lifetime as a function of .

Fig. 7. profile of the nominal device and the outlier device pre- and post-NBTI.

Fig. 7. profile of the nominal device and the outlier device pre- and post-NBTI.

Fig. 6. TDDB lifetime as a function of Ss-th.

Fig. 6. TDDB lifetime as a function of Ss-th.

Fig. 8. Weibull plot of TDDB lifetime under two test conditions.

Fig. 8. Weibull plot of TDDB lifetime under two test conditions.

Devices with different values of have been tested for TDDB. The TDDB lifetime is shorter for a device with a higher Ss-th, as shown in Fig. 5 and Fig. 6 respectively, under both test conditions as described in Method. It is known that is positively correlated with the of oxide interface as described in Eq. 2 [5], where k is Boltzmann constant, T is temperature, q is electron charge, is depletion capacitance, is oxide capacitance.

The extracted profile of our devices is shown in Fig.7. The outlier device shows a higher at high energy levels. There is no doubt that a higher (in other word, a worse gate quality) leads to a shorter TDDB lifetime. However, the TDDB lifetime varies little for devices with either or higher except only one outsider. The TDDB lifetime and could be fitted by a hyperbola function (dash line in Fig. 5 and Fig. 6). Our interpretation is that higher originates from the larger number of interface traps caused by material defects rather than processing defects. The former would have instant impact on TDDB lifetime. The Weibull plot of the TDDB lifetime of the two test conditions are shown in Fig. 8. All the TDDB failures should be classified as "intrinsic mode".

Fig. 9 and Fig. 10 show the HTGB in-situ Vth drift over time for PBTI and NBTI, respectively. is only around 0.2 V and starts to remain stable from hours for PBTI whilst it is neglectable for NBTI for both types of devices. of both NBTI and PBTI is well within the JEDEC qualification criterion ( ). The little impact on by HTGB is as expected because is extracted at and the is similar for both nominal and outlier devices at low energy levels.

Fig. 9. In-situ drift over time of PBTI.

Fig. 9. In-situ drift over time of PBTI.

Fig. 10. In-situ drift over time of NBTI.

Fig. 10. In-situ drift over time of NBTI.

The pre-/post- curve in the subthreshold region is shown in Fig. 11. The pre-/postHTGB off-state leakage current at and is shown in Fig. 12. The post-PBTI curve is overall shifted rightward and the off-state leakage at is lower. On the other hand, the post-NBTI Ss-th is reduced at and the off-state leakage is almost unchanged. The reverse bias acted as a curing process that slightly improves the quality of MOS interface (see the post-NBTI profile in Fig. 7, blue).

Fig. 11. Pre- and post- curves of the outliers.

Fig. 11. Pre- and post- curves of the outliers.

Fig. 12. Pre- and post- HTGB leakage current at and of the outliers.

Fig. 12. Pre- and post- HTGB leakage current at and of the outliers.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1024.9.pdf

A high value at low is an indication of material defects that increase the interface trap density at high energy levels. The HTGB study shows that the devices with high Ss-th have a low risk in gate failure although a full 1000 -hour stress is yet to be verified. There is no indication that the Ssтн outliers would generate extrinsic TDDB failures though a higher value leads to a shorter TDDB lifetime. In case a high screening standard of TDDB lifetime is required, a critical (<1 ) upper specification limit of should be introduced but this is not included in the JEDEC or AEC-Q101 standard [6] for automotive qualification.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.9.pdf

Yole Intelligence, Power SiC 2023 (2023).

T. Liu, S. Zhu, M. H. White, A. Salemi, D. Sheridan and A. K. Agarwal, IEEE Journal of the Electron Devices Society, 9, p. 633-639 (2021).

JEDEC Publication No. 184 (2021).

JEDEC Publication No. 194 (2023).

S. Yu, M. H. White and A. K. Agarwal, IEEE Access, 9, pp. 149118-149124 (2021).

Automotive Electronics Council, AEC-Q101 (2021).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 15-21

doi: 10.4028/p-2Bd9VO

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-15

Accepted:
2025-08-15

Online:
2025-09-12

Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

The original version of this paper is available on https://www.scientific.net/KEM.1024.15.pdf

Limeng Shi , Michael Jin , Jiashu Qian , Monikuntala Bhattacharya , Shiva Houshmand , Hengyu Yu , Atsushi Shimbori , Marvin H. White , Anant K. Agarwal

Dept. of Electrical & Computer Eng., The Ohio State University, Columbus, OH, USA

Ford Motor Company, Dearborn, MI, USA

shi.1564@osu.edu, jin.845@osu.edu, qian.539@osu.edu, bhattacharya.119@osu.edu, ehoushmand.3@osu.edu, yu.3868@osu.edu, ashimbor@ford.com, white.1829@osu.edu, iagarwal.334@osu.edu

Keywords: Screening, Charge to Breakdown, Gate Leakage Current, Extrinsic Failure, Gate Oxide Lifetime.

Abstract

This study demonstrates a negative correlation between gate leakage current ( ) and time to breakdown ( ) of gate oxide in various commercial SiC discrete MOSFETs and power modules. SiC MOSFETs with higher leakage current at the same gate voltage exhibit lower oxide failure time in the constant-voltage Time-Dependent Dielectric Breakdown (TDDB) test. The novelty lies in the discovery that measured under conditions of either low gate voltage at RT or high at can be utilized to identify discrete devices or power modules with non-infant failures or lower intrinsic lifetime. Aggressive screening based on helps to reduce non-infant extrinsic failure probability and identify devices with more uniformity of intrinsic lifetime.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.15.pdf

A significant challenge in the adoption of SiC MOSFETs for electric vehicle (EV) applications is the issue of gate oxide failure. In practical circuits, certain SiC MOSFETs exhibit early gate oxide breakdown, which is primarily attributed to the high extrinsic defect density inherent in these devices . Therefore, it is essential to implement a screening process to eliminate unreliable devices prior to deployment [3-5]. The conventional screening method involves applying high-voltage pulses to the gate electrode for a specified duration, followed by the removal of failed devices. However, manufacturers tend to employ conservative screening conditions to avoid compromising the performance of SiC MOSFETs [6-8]. The conventional screening process can basically remove infant failures, but some non-infant failures close to the intrinsic failure line still survive [9].

In this study, gate leakage current ( ) and gate oxide lifetime ( ) measurements are performed on a variety of commercial SiC discrete MOSFETs and power modules. The relationship between gate leakage current and oxide lifetime is analyzed using the charge-to-breakdown mechanism. Based on the measurement results, an optimized screening method is developed to eliminate extrinsic failure tails and identify devices with more consistent intrinsic lifetime characteristics. Furthermore, the effectiveness of the enhanced screening technique is validated.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1024.15.pdf

Table 1 summarizes the relevant information for the commercial SiC discrete MOSFETs and power modules studied in this work. SiC devices with different gate structures and current ratings are selected for the investigation. Fig. 1 illustrates the test procedures for measuring gate leakage current and oxide lifetime in SiC planar 17 A discrete MOSFETs. Initially, is measured at room temperature (RT) with a gate voltage of 30 V , followed by the measurement at with a gate voltage of . Subsequently, a constant-voltage Time-Dependent Dielectric

Breakdown (TDDB) test is conducted at to determine the lifetime of the gate oxide. Depending on the parameter information of the SiC MOSFETs from different vendors, the measured voltages of and are adjusted accordingly.

The breakdown characteristics of the gate oxide are analyzed using the Fowler-Nordheim (FN) tunneling and charge-to-breakdown ( ) mechanisms [10-14], as described in Eq. 1-3. In addition, the oxide lifetimes obtained from the TDDB tests are plotted using Weibull distribution [15]. Based on the cumulative distribution function (see Eq. 4), the oxide lifetime with different failure rates can be calculated. The value of for devices that cannot reach is predicted from the fitted line of and .

Table 1. Commercial 1.2 kV SiC devices studied.

Type | Discrete Device | Discrete Device | Power Module | Discrete Device | Discrete Device
Current (A) | 17 | 115 | 450 | 11 | 17
Structure | Planar | Planar | Planar | Planar | Double-Trench
tox (nm) | ~38 | ~38 | ~38 | ~46 | ~55

Fig. 1. Test procedures for SiC planar 17 A discrete MOSFETs.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1024.15.pdf

Constant-voltage TDDB tests at are conducted on SiC discrete MOSFETs and power modules, as illustrated in Fig. 2. The results show that a small percentage of commercial devices still experience early oxide breakdown. Moreover, the oxide lifetime distributions for power modules and trench devices exhibit greater variability compared to planar devices. Therefore, it is necessary to optimize the screening technology to reduce the probability of early oxide breakdown and allow the remaining devices to have a high uniform intrinsic lifetime of gate oxide. Fig. 3 shows the test curves of gate leakage current for SiC planar 17 A discrete MOSFETs devices, from the beginning of the TDDB test until oxide breakdown. The charge-to-breakdown ( ) is calculated using the integration method. Fig. 4 illustrates the Weibull distributions of for both SiC planar and trench discrete MOSFETs. Although the oxide lifetime of trench devices is highly variable, the is uniformly distributed. This indicates that the gate oxide tends to break down when the total charge passing through it exceeds a certain threshold, and the charge-to-breakdown mechanism can be used to explain oxide intrinsic breakdown.

Fig. 2. Weibull distribution of measured oxide lifetimes for commercial SiC discrete MOSFETs and power modules.

Fig. 2. Weibull distribution of measured oxide lifetimes for commercial SiC discrete MOSFETs and power modules.

Fig. 3. Constant-voltage TDDB test curves for SiC planar 17 A discrete MOSFETs.

Fig. 3. Constant-voltage TDDB test curves for SiC planar 17 A discrete MOSFETs.

Fig. 4. Weibull distribution of extracted from constant-voltage TDDB.

Fig. 4. Weibull distribution of extracted from constant-voltage TDDB.

Fig. 5 illustrates the oxide lifetime at with failure rates of , and 10 ppm for SiC planar 17 A discrete MOSFETs, calculated from Weibull statistics. It can be seen that planar 17 A discrete device with less than cannot meet the lifetime requirement of 20 years under operational conditions. To establish the relationship between gate leakage current and oxide lifetime for SiC planar 17 A MOSFETs, is measured at both and . The measured values are correlated with the oxide lifetime at for each device, as depicted in Fig. 6 (a) and (b). Based on the negative correlation between and , SiC planar 17 A MOSFETs
with an greater than at , and at may exhibit a shorter lifetime than . It can also be found that devices with higher at also exhibit higher at high .

Fig. 5. Oxide lifetimes at with the failure rate of and 10 ppm for SiC planar 17 A discrete MOSFETs.

Fig. 5. Oxide lifetimes at with the failure rate of and 10 ppm for SiC planar 17 A discrete MOSFETs.

Fig. 6. Correlation between gate leakage current and oxide lifetime for SiC planar 17 A discrete MOSFETs: (a) at vs. oxide lifetime at . (b) at vs. oxide lifetime at .

Fig. 6. Correlation between gate leakage current and oxide lifetime for SiC planar 17 A discrete MOSFETs: (a) at vs. oxide lifetime at . (b) at vs. oxide lifetime at .

The same negative correlation is observed in other commercial devices, as shown in Fig. 7. Higher gate leakage current in SiC MOSFETs correlates with shorter oxide lifetime. According to recent studies, the charge-to-breakdown mechanism provides a reasonable explanation for intrinsic oxide breakdown. This mechanism suggests that a certain amount of charge must be transported before breakdown occurs. During the TDDB test, the gate leakage current primarily consists of electrons injected into the conduction band from SiC via FN tunneling. The FN tunneling current density can be expressed by Eq. 1, which shows that leakage current density depends on the oxide electric field ( ). Due to variations in fabrication, there are differences in effective oxide thickness ( ) between devices. A smaller results in a larger at the same gate voltage, leading to higher leakage current in devices. Since is a constant value, devices with higher leakage current will exhibit shorter lifetimes. Extrinsic breakdown can be described as defect-related breakdown. This breakdown is caused by irregularities in the , or the surface and interface roughness. The tiny distortions lead to thickness fluctuation. In this case, locally enhanced electric field near the steps accelerates oxide breakdown. Also, the enhanced electric field at the defect site can increase the locally leakage current. Based on the present results, not all devices with extrinsic failures have large
leakage current. The total leakage current may depend on the type of defect, the location of the defect and the defect density. The physical mechanism of extrinsic breakdown requires further study.

Fig. 7. Correlation between the gate leakage current and the oxide lifetime for SiC discrete MOSFETs and power modules.

Fig. 7. Correlation between the gate leakage current and the oxide lifetime for SiC discrete MOSFETs and power modules.

Based on the above test results and analysis. An optimized screening technique based on leakage current is proposed. This approach is to obtain by applying gate voltage and identify SiC MOSFETs with low oxide lifetime according to the value of . Generally, devices with higher at low voltage and RT also exhibit higher at elevated temperatures and voltages. However, high temperature and high voltage conditions are more effective in screening out devices prone to infant failures. Therefore, high temperature and high voltage conditions serve not only as a test for but also as a screening process for the devices. Previous studies have shown that during 100 ms screening at , the maximum acceptable oxide electric fields for SiC planar and trench MOSFETs, without causing negative threshold voltage shifts, are and , respectively [16,17].

To demonstrate the effectiveness of this method, two new batches of SiC MOSFETs with planar and trench gate structures are selected for screening and TDDB testing. Fig. 8 (a) and (b) show the gate leakage current under different stress conditions and the distribution for each SiC planar and trench MOSFET, respectively. As shown in Fig. 8 (a), there are five leaky SiC planar MOSFETs detected at and . Five leaky devices do not exhibit oxide failure after undergoing the test. Subsequently, the oxide lifetime is measured using the TDDB test. The results show that oxide failure time of these five devices is in the range of 1.7 and 10 hours, which is lower than the oxide lifetime of normal devices. Fig. 8 (b) shows the distribution of SiC trench MOSFETs at and . It can be observed that the gate oxide of one device fails under the stress of , which can be considered as an infant failure. The remaining SiC trench MOSFETs have a large variation in despite passing the test without breakdown. For trench devices with large oxide lifetime variation, a portion of the devices with exceeding a certain range can be removed, allowing the remaining devices to exhibit higher lifetime uniformity. It can be concluded that the screening method proposed in this paper considers SiC MOSFETs that exhibit higher at different oxide stress conditions as devices that will experience non-infant failure. By removing these devices, the failure probability is reduced. In addition, the process used to measure can also eliminate devices with infant failures.

Fig. 8. Gate leakage current under different stress conditions for:
(a) SiC planar 11 A discrete MOSFETs. (b) SiC trench discrete MOSFET.

Fig. 8. Gate leakage current under different stress conditions for: (a) SiC planar 11 A discrete MOSFETs. (b) SiC trench discrete MOSFET.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1024.15.pdf

This study proposes a screening method to reduce the probability of gate oxide failure in commercial SiC MOSFETs, based on the observed negative correlation between and . The results indicate that devices with higher tend to have shorter oxide failure times. By removing leaky SiC MOSFETs, the intrinsic oxide lifetime distribution of the remaining devices becomes more uniform. Additionally, measurements under high-temperature and high-voltage conditions help to identify and eliminate some infant failures.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.15.pdf

T. Aichinger, M. Schmidt, Gate-oxide reliability and failure-rate reduction of industrial SiC MOSFETs, in: 2020 IEEE International Reliability Physics Symposium (IRPS), IEEE, Dallas, TX, USA, 2020: pp. 1-6. https://doi.org/10.1109/IRPS45951.2020.9128223.

T. Liu, S. Zhu, M. Jin, L. Shi, M.H. White, A.K. Agarwal, Impacts of Area-Dependent Defects on the Yield and Gate Oxide Reliability of SiC Power MOSFETs, in: 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), IEEE, Redondo Beach, CA, USA, 2021: pp. 5-8. .

H. Miki, M. Sagawa, Y. Mori, T. Murata, K. Kinoshita, K. Asaka, T. Oda, Accurate screening of defective oxide on SiC using consecutive multiple threshold-voltage measurements, in: 2022 IEEE International Reliability Physics Symposium (IRPS), 2022: p. 8B.2-1-8B.2-7. .

J. Berens, T. Aichinger, A straightforward electrical method to determine screening capability of GOX extrinsics in arbitrary, commercially available SiC MOSFETs, in: 2021 IEEE International Reliability Physics Symposium (IRPS), 2021: pp. 1-5. .

Y. Zheng, R. Potera, T. Witt, Characterization of Early Breakdown of SiC MOSFET Gate Oxide by Voltage Ramp Tests, in: 2021 IEEE International Reliability Physics Symposium (IRPS), IEEE, Monterey, CA, USA, 2021: pp. 1-5. .

L. Shi, T. Liu, S. Zhu, J. Qian, M. Jin, H.L.R. Maddi, M.H. White, A.K. Agarwal, Effects of Oxide Electric Field Stress on the Gate Oxide Reliability of Commercial SiC Power MOSFETs, in: 2022 IEEE 9th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), IEEE, Redondo Beach, CA, USA, 2022: pp. 45-48. .

L. Shi, S. Zhu, J. Qian, M. Jin, M. Bhattacharya, M.H. White, A.K. Agarwal, A. Shimbori, T. Liu, Investigation of different screening methods on threshold voltage and gate oxide lifetime of SiC Power MOSFETs, in: 2023 IEEE International Reliability Physics Symposium (IRPS), IEEE, Monterey, CA, USA, 2023: pp. 1-7. .

L. Shi, J. Qian, M. Jin, M. Bhattacharya, H. Yu, M.H. White, A.K. Agarwal, A. Shimbori, Evaluation of Burn-in Technique on Gate Oxide Reliability in Commercial SiC MOSFETs, in: 2024 IEEE International Reliability Physics Symposium (IRPS), IEEE, Grapevine, TX, USA, 2024: pp. 1-6. .

Z. Chbili, A. Matsuda, J. Chbili, J.T. Ryan, J.P. Campbell, M. Lahbabi, D.E. Ioannou, K.P. Cheung, Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs, IEEE Trans. Electron Devices 63 (2016) 3605-3613. .

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P. Moens, J. Franchi, J. Lettens, L.D. Schepper, M. Domeij, F. Allerstam, A Charge-toBreakdown (Q bd ) Approach to SiC Gate Oxide Lifetime Extraction and Modeling, in: 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE, Vienna, Austria, 2020: pp. 78-81. .

J. Qian, L. Shi, M. Jin, M. Bhattacharya, A. Shimbori, H. Yu, S. Houshmand, M.H. White, A.K. Agarwal, Modeling of Charge-to-Breakdown with an Electron Trapping Model for Analysis of Thermal Gate Oxide Failure Mechanism in SiC Power MOSFETs, Materials 17 (2024) 1455. .

J. Qian, L. Shi, M. Jin, M. Bhattacharya, H. Yu, M.H. White, A.K. Agarwal, A. Shimbori, Z. Xu, Investigation of the Constant Current Stress for Charge-to-breakdown Extraction in Commercial SiC Power MOSFETs, in: 2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), IEEE, Charlotte, NC, USA, 2023: pp. 1-4. .

S. Zhu, T. Liu, L. Shi, M. Jin, H.L.R. Maddi, M.H. White, A.K. Agarwal, Comparison of Gate Oxide Lifetime Predictions with Charge-to-Breakdown Approach and Constant-Voltage TDDB on SiC Power MOSFET, in: 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), IEEE, Redondo Beach, CA, USA, 2021: pp. 1-4. .

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L. Shi, J. Qian, M. Jin, M. Bhattacharya, H. Yu, A. Shimbori, M.H. White, A.K. Agarwal, Investigation on gate oxide reliability under gate bias screening for commercial SiC planar and trench MOSFETs, Materials Science in Semiconductor Processing 174 (2024) 108194. .

L. Shi, J. Qian, M. Jin, M. Bhattacharya, H. Yu, M.H. White, A.K. Agarwal, A. Shimbori, Z. Xu, An Effective Screening Technique for Early Oxide Failure in SiC Power MOSFETs, in: 2023 IEEE 10th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), IEEE, Charlotte, NC, USA, 2023: pp. 1-4. .

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 23-28

doi: 10.4028/p-yA5cwi

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-28

Accepted:
2025-08-28

Online:
2025-09-12

Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

Umesh Chand , Chien Yu-Chieh , Abdul Hannan Yeo , Voo Qin Gui Roth , Shiv Kumar , Akhil Ranjan , Binni Varghese , Weijie Wang , Pavan Vudumula , Tamara Fidler , Patrick Schmid , Mario Saggio , Maurizio Castorina , Marco Camalleri , Jia Xie , Gong Xiao , Surasit Chung , Lakshmi Kanta Bera , Navab Singh , Yeo Yee Chia

Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore 138634

Centrotherm International AG, Blaubeuren, Germany

STMicroelectronics, Singapore & Catania, Italy

National University of Singapore, Singapore

chand_umesh@a-star.edu.sg, Chien_Yu_Chieh@a-star.edu.sg,

cHannan_Yeo@a-star.edu.sg, Roth_Voo@a-star.edu.sg,

shiv_kumar@ime.a-star.edu.sg, Ranjan_Akhil@a-star.edu.sg, Binni_Varghese@a-star.edu.sg,

Wang_Weijie@a-star.edu.sg, ivudumulapk@ime.astar.edu.sg, jtamara.fidler@centrotherm.de,

patrick.schmid@centrotherm.de, mario.saggio@st.com, maurizio.castorina@st.com,

marco.camalleri@st.com, ojiaweix@u.nus.edu, elegong@nus.edu.sg,

surasit_chung@ime.a-star.edu.sg, 'lakshmi_kanta_bera@ime.a-star.edu.sg,

navab@ime.a-star.edu.sg, yeo_yee_chia@hq.a-star.edu.sg

Keywords: Deposited Oxide, Interface Trap Density, Flat Band Voltage, and Reliability.

Abstract

In this work, we propose and experimentally validate a novel approach to achieve superior interface properties of the MOS capacitors through a low-temperature oxide deposition technique for gate dielectric followed by a nitridation process. Low interface trap density ( ), robust flat-band voltage stability under positive bias stress, and decent leakage current density ( ) can be unambiguously verified after nitric oxide (NO) gas postdeposition annealing.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

Silicon carbide (SiC) power MOSFETs are a key enabling technology in high-efficiency power electronics applications, particularly in systems requiring high voltage, high temperature, and high switching frequency. Despite their promise, one of the primary challenges SiC MOSFETs faces is their inherently low channel mobility, which limits overall device performance[1,2]. This issue is largely attributed to the high interface trap density (Dit) at the interface, primarily caused by carbon-related defects formed during the high-temperature oxidation process to create the gate dielectric layer [2,3]. These defects introduce unwanted energy states within the bandgap, which act as traps, reducing the mobility of carriers and thereby degrading the on-state performance of the device.

Various strategies have been explored to mitigate these challenges, including modifications to the oxidation process and post-oxidation annealing treatments. Traditional oxidation methods at high temperatures often result in significant carbon contamination at the SiC interface, increasing the density of interface traps. Low-temperature deposition techniques have recently emerged as a promising alternative. These methods offer better control over the interface properties, reducing carbon-related defects and thus improving channel mobility [4,5]. However, despite the advantages,
the precise impact on long-term device reliability and performance remains an open area of research. A deeper understanding of the interface engineering under these conditions is crucial to unlocking the full potential of SiC MOSFETs.

In this work, we explore the effectiveness of a low-temperature deposited oxide as a gate dielectric in mitigating interface-related challenges in SiC MOSFET technology. Our results show that the deposited oxide approach yields a minimal of , excellent device-to-device uniformity, decent leakage current density ( ), and superior flat-band voltage stability ( ) under positive bias stress.

Fig. 1. Fabrication process flow for the MOS capacitors.

Fig. 1. Fabrication process flow for the MOS capacitors.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

MOS capacitors were fabricated on a highly doped n-type off-cut (0001) substrate, with a thick nitrogen-doped homo-epilayer. Key aspects of the process flow are illustrated in Fig. (1). High-resolution transmission electron microscopy (HRTEM) images were obtained for all the samples to investigate the presence of an additional layer at the interface following post-oxidation/deposition annealing (POA/PDA). A sharp interface can be seen between and SiC [Fig. 2(a-b)]. To access device yield and uniformity, we randomly selected 15 devices of the same die and measured [Fig. 3(a)]. The tight statistical distribution of for randomly selected devices is shown in Fig. 3(b). Capacitance-voltage ( ) measurement was conducted to investigate the impact of different methods on the interface [Fig. 3(c-f)]. The oxide-4 devices significantly reduce to [Fig. 4(a)], which may be attributed to the effective mitigation of carbon-related defects in deposited oxide, and the incorporation of nitrogen may further passivate dangling bonds at the interface after NO POA. The tight distribution with small coefficient of variation ( ) is observed for [Fig. 4(b)]. X-ray photoelectron spectroscopy (XPS) study supported the existence of a slightly nitrogen-rich SiC surface after NO POA/PDA [Fig. 4(c)].

Fig. 2. (a-d) Cross-sectional TEM of the interface for all the samples.

Fig. 2. (a-d) Cross-sectional TEM of the interface for all the samples.

Fig. 3. (a) for the MOS capacitors and (b) statistical distribution of for randomly selected devices and (c-f) quasi static and curves of the MOS capacitors.

Fig. 3. (a) for the MOS capacitors and (b) statistical distribution of for randomly selected devices and (c-f) quasi static and curves of the MOS capacitors.

Next, the measurements were repeated from -5 V to various accumulation voltages from 5 V to 25 V [Fig. 5(a-d)] to investigate the effect of high accumulation voltage on flat-band ( ) stability. The improved stability for the oxide-4 devices could be due to the reduction of interface defects and near interface traps at the interface. Furthermore, we examined the stability by conducting a positive bias stress test. The oxide field ( ) is applied according to industry guidelines to ensure accurate and reliable testing procedures [10]. A constant voltage stress corresponding to values of 3,5 , and was applied for a duration of up to [Fig. 5(e-h)]. The bulk trap density ( ) extracted as a function of bias stress time with various values of 3, 5 , and shown in Fig. 6(a-d). The oxide-4 scheme device manifests superior stability against bias stress with the lowest extracted .

Fig. 4. (a) energy distribution of estimated by the high-low method [2], (b) the distribution of extracted at around , and (c) nitrogen concentration plotted for for all samples.

Fig. 4. (a) energy distribution of estimated by the high-low method [2], (b) the distribution of extracted at around , and (c) nitrogen concentration plotted for for all samples.

Fig. 5. (a-d) curves with different accumulation voltages of the MOS capacitors and (e-h) as a function of bias stress time with various of 3,5 , and .

Fig. 5. (a-d) curves with different accumulation voltages of the MOS capacitors and (e-h) as a function of bias stress time with various of 3,5 , and .

This can be attributed to the minimization of carbon-related defects through the deposited oxide approach, in which the trap states are further reduced by NO-PDA. Finally, we benchmark the and of our devices with previously reported deposited oxide SiC devices (Table I). It is reasonable to conclude that the oxide-4 device in this study has achieved the lowest and a satisfactory value ( ).

Fig. 6. (a-d) as a function of bias stress time with various field of 3,5 , and . (e) change in plotted as a function of nitrogen concentration and Table-1 Benchmark of this work with reported work.

Fig. 6. (a-d) as a function of bias stress time with various field of 3,5 , and . (e) change in plotted as a function of nitrogen concentration and Table-1 Benchmark of this work with reported work.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

In summary, our deposited gate oxide on SiC with NO-POA had produced low and led to a significant enhancement in MOS capacitor device performance and reliability such as superior stability under positive bias stress.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

This work was supported by the Science and Engineering Research Council of A*STAR (Agency for Science, Technology, and Research) Singapore, under Grant No. A20H9a0242.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.23.pdf

T. Kimoto and H. Watanabe, Appl. Phys. Express 13, 120101 (2020).

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications (Wiley, New York, 2014).

U. Chand et al., International Conference on Silicon Carbide and Related Materials (ICSCRM), (2023).

P. Fiorenza, et al., Material Science in Semiconductor Processing, 169, 107866 (2023).

T.H. Kil, et al., AIP Advance, 13, 115304 (2023).

M. Yakut, et al., ICSCRM, (2023).

K. Tachiki, et al., Applied Physics Express, 14,031001 (2021).

M. Lim, et al., ICSCRM, 535-540, (2019).

S. Asaba, et al., ICSCRM, 924, 457-460 (2017).

D. A. Gajewski et al., ICSCRM, 179-186 (2023).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 29-37

doi: 10.4028/p-O0YawH

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Accepted:
2025-05-05

Online:
2025-09-12

Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1024.29.pdf

Madhu Lakshman Mysore , Darshan Koorana Prasanna Kumar , Chaohao Wang , Josef Lutz , Thomas Basler

Chemnitz University of Technology, Chair of Power Electronics, Chemnitz, Germany

madhu-lakshman.mysore@etit.tu-chemnitz.de,

darshan-koorana.prasanna-kumar@etit.tu-chemnitz.de, chaohao.wang@etit.tu-chemnitz.de,

josef.lutz@etit.tu-chemnitz.de,

Keywords: Overcurrent turn-off, Robustness, Gate-leakage, Gate oxide, Electric field, TCAD.

Abstract

The aim of this study is to investigate the overcurrent turn-off robustness limit of SiC MOSFETs from three different manufacturers with three different cell technologies up to very high turn-off currents to determine a possible destruction limit and failure type. The influence of the negative gate-source voltage ( ,off) was studied because of the high drain-source overvoltage in connection with the decreased , which is the most critical point for the gate oxide field stress for the different cell technologies. All measurements were performed at a positive gate-source voltage ( ) above the specified datasheet values to reach high currents without channel pinch-off. In addition, the influence of temperature on the overcurrent robustness was studied. Finally, TCAD simulations were performed to determine the reason for the failure mechanism under the overcurrent turn-off conditions. All the manufacturer devices can withstand several times higher gate-source voltages under overcurrent conditions than the values recommended in the datasheet.

Introduction

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Silicon Carbide (SiC) power MOSFETs are widely adopted in various applications due to their superior material properties such as low intrinsic carrier density, high breakdown field, and high thermal conductivity [1]. Owing to their material advantages, SiC -based power devices can achieve higher operating temperatures, faster switching speeds and lower conduction losses than those of Si IGBTs.

SiC MOSFETs are used in various applications such as electric vehicles, motor drives, and renewable energy systems. For example, on-board chargers or wind turbine converters must handle overcurrent events due to grid faults or sudden changes in wind speed. During an overcurrent event, a SiC MOSFET might be subjected to excessive current levels beyond its rated specifications. In response to an overcurrent event, SiC MOSFETs must also able to turn-off high currents to protect the device and circuitry. This leads to significant voltage spikes due to the parasitic inductive components of the switching circuits. As a result, the device may operate in avalanche mode which can lead to a catastrophic failure of the device. Moreover, the SiC MOSFETs have thinner gate oxide and can withstand one order magnitude of higher electric field in the bulk than its Si counterparts. These very high voltage spikes can be critical for the gate oxide. Hence, to ensure the stable operation of such systems, it is important to understand the overcurrent turn-off and its limits for SiC MOSFETs under various conditions. In [2] a first study of repetitive overcurrent turn-off events was performed within the recommended gate bias. Although the robustness of SiC MOSFET continues to increase, there are still concerns about the gate oxide reliability [3, 4]. Consequently, in this study, the overcurrent turn-off capabilities of 1.2 kV SiC MOSFETs were evaluated for different cell technologies from three different manufacturers using a double-pulse test. The devices were driven at very high gate voltages, far beyond the allowed range along with various other conditions that strongly influence the dynamic gate switching for the devices. Furthermore, electro-thermal simulations were carried out to investigate overcurrent turn-off failures.

Device Under Test and Experimental Setup

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The Device Under Test (DUTs) were commercially available 1.2 kV SiC MOSFET from three different manufacturers (M1, M2, and M3) with similar current ratings. These three SiC MOSFETs have different cell technologies, as shown in Fig. 1. The device parameters for the different SiC MOSFETs are listed in Table. 1. The gate oxide thickness was estimated by measuring the gate leakage current until breakdown using a source measurement unit (SMU).

Fig. 1. Schematic cross-section of the cell head of SiC MOSFETs from different manufacturers.

Fig. 1. Schematic cross-section of the cell head of SiC MOSFETs from different manufacturers.

Table 1. Device parameters of the SiC MOSFETs from different manufacturers.

Device parameters | M1 | M2 | M3
Gate technology | Trench | Double trench | Planar
Estimated gate oxide thickness | 65 nm | 55 nm | 45 nm
Measured drain-source breakdown voltage at 1 mA (27°C) | 1440 V | 1615 V | 1515V
Rated current | 31 A | 31 A | 32 A
Rds,on | 80 mΩ | 80 mΩ | 60 mΩ
Recommended VGS,on | 20 V | 18 V | 15 V
Recommended VGS,off | 0 V | 0 V | -4 V
Package type | TO-247-4

Fig. 2. (a) Schematic of the overcurrent turn-off equivalent circuit (b) Measured overcurrent turnoff behaviour of M3 devices at two different initial temperatures for given conditions of .

Fig. 2. (a) Schematic of the overcurrent turn-off equivalent circuit (b) Measured overcurrent turnoff behaviour of M3 devices at two different initial temperatures for given conditions of .

A schematic diagram of the measurement setup to measure the overcurrent turn-off capability of the SiC MOSFETs is shown in Fig. 2(a). The parasitic inductance ( ) of the commutation loop was 30 nH . A 3.3 kV SiC MOSFET with was utilized as a freewheeling diode (FWD). The load inductance ( ) is connected in parallel to the FWD. The magnitude of the turn-off drain current of the DUT can be adapted by adjusting the turn-on time ( ). The gate-source voltage ( ) and drain-source voltage ( ) were measured at the sense-source (SS) terminal without the influence of load-source inductance (LS). A Rogowski coil was used to measure the current.

An exemplary overcurrent turn-off measurement at a DC-link voltage of 1000 V with switched from at two different initial temperatures is shown in Fig. 2(b). At a turn-off current of 120 A, the SiC MOSFETs turn-off with a fast rate of current slope ( ) causing a significant induced overvoltage across the drain and source. The increase in initial junction temperature ( ) shows slightly lower and subsequently lower overvoltage.

Fig. 3. Impact of negative gate bias on measured overcurrent turn-off for M1 device. Conditions: , , .

Fig. 3. Impact of negative gate bias on measured overcurrent turn-off for M1 device. Conditions: , , .

Fig. 4. Impact of positive gate bias on measured overcurrent turn-off for M2 device. Conditions: , , .

Fig. 4. Impact of positive gate bias on measured overcurrent turn-off for M2 device. Conditions: , , .

The influence of different negative gate voltages on the overcurrent turn-off behaviour of the MOSFET at a fixed ,on of 20 V and 800 V is shown in Fig. 3. Due to the higher amplitude in the switched gate bias, an acceleration of the turn-off was recorded. This leads to a higher and correspondingly a higher overvoltage ( ) shortly before avalanche breakdown. In Fig. 4, the positive gate bias was varied at fixed of -4 V and DC-link voltage of 800 V for M 2 device. The turn-off measurements were carried out at four times the datasheet specified value and showed slightly faster for increased values. For both measurements in Fig. 3 and Fig. 4, the was above the rated voltage of the devices to operate at the border of the safe-operating area. At overcurrent turn-off, the voltage and current derivate can be adjusted by varying and .

Results and Analysis

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The overcurrent turn-off capability was determined by gradually ramping the drain current in steps of 5 A for a fixed and . Once the channel pinch-off was observed at a high turn-off current, the measurement was stopped, and was increased in steps of 1 V . The overcurrent turn-off measurement steps were repeated until the destruction of the DUTs occurred or a strong drift in the electrical parameters was observed, such as gate leakage current (IGSS), or loss of blocking capability or increased drain-source leakage current (IDss).

At : Fig. 5 shows the overcurrent turn-off robustness limit with the help of the lastpass for different manufacturers at two different DC-link voltages. The minimum allowed values, was chosen as recommended by the datasheet. For measurements below 800 V , the devices do not exhibit any failures in the investigated current ranges for all manufacturers. M1 devices show the highest robustness limit with last-pass of 53 V for two different . M1 SiC MOSFETs exhibit the highest last-pass for both DC-link voltages as compared to other manufacturers because of thicker gate oxide as mentioned in Table 1. Moreover, the M2 devices at 1000 V and switched from 50 V to -4 V shows lower overcurrent turn-off capability as compared to switched from 50 V to 0 V . M3 devices at 800 V show increased last-pass by 1 V with lower . Furthermore, at 1000 V and of -4 V , the M3 device shows higher overcurrent turn-off capability than of 0 V , which is in contrast to M 2 devices.

Fig. 5. Overcurrent turn-off robustness of the different manufacturers: last-pass for two different . The last-pass current and its of the devices are mentioned on the top of each bar along with last-pass Measurement conditions: , .

Fig. 5. Overcurrent turn-off robustness of the different manufacturers: last-pass for two different . The last-pass current and its of the devices are mentioned on the top of each bar along with last-pass Measurement conditions: , .

Fig. 6. Measured IGss in between overcurrent turn-off measurements at DC-link voltage of 1000 V for different manufacturers at . Note: change in y-axis scale.

Fig. 6. Measured IGss in between overcurrent turn-off measurements at DC-link voltage of 1000 V for different manufacturers at . Note: change in y-axis scale.

Fig. 7. Comparison of the last-pass and destructive pulses at overcurrent turn-off of the SiC MOSFETs for (a) M2 (b) M3 at a given condition of .
Inset: zoomed of the last-pass and destructive pulses.

Fig. 7. Comparison of the last-pass and destructive pulses at overcurrent turn-off of the SiC MOSFETs for (a) M2 (b) M3 at a given condition of . Inset: zoomed of the last-pass and destructive pulses.

All the devices failed due to an increased independent of the manufacturer. The measured in between the current pulses shows an increased leakage current for a higher turn-off current, as shown in Fig. 6. The M1 devices however do not show a significant change in IGSS with increased turn-off current, but a sudden increase in after turn-off current of 178 A with of ,
as shown in Fig. 6(a). Conversely, the M3 devices show a slight increase in IGss with higher turn-off current, as shown in Fig. 6(b). This increase in the IGSS indicates pre-damage to the gate before the destructive overcurrent turn-off pulse. Any further overcurrent turn-off measurements with increased will lead to catastrophic failure or a gate voltage drop, as shown in Fig. 7. A sudden collapse at the beginning of pulse for M2 devices, eventually leading to failure is plotted in Fig. 7(a). Moreover, M3 devices show a drop in the value during steady state phase, indicating gate damage and correspondingly increased above the maximum datasheet values [see inset Fig. 7(b)].

Fig. 8. Overcurrent turn-off robustness of the different manufacturers: last-pass for two different . The last-pass current and its of the devices are mentioned on the top of each bar along with last-pass . Measurement conditions: , .

Fig. 8. Overcurrent turn-off robustness of the different manufacturers: last-pass for two different . The last-pass current and its of the devices are mentioned on the top of each bar along with last-pass . Measurement conditions: , .

At : In general, all the tested devices from different manufacturers show an increased last-pass with increased junction temperature, as shown in Fig. 8. The tendency of the influence is similar to the room temperature. Interestingly, the M1 devices show significantly increased overcurrent turn-off capability without any failure up to of 64 V . The measurements were stopped at 64 V due to the limitation of the gate driver unit (GDU). Moreover, the M2 and M3 devices show an increased last-pass in the range of 1 V to 2 V as compared to the measured results at (Fig. 5). Furthermore, the increase in last-pass was due to the reduced at increased temperatures, see Fig. 2(a). At higher temperatures, the overcurrent turnoff capability of the M2 devices increases. M3 devices show lower overcurrent turn-off capability with increased . The M2 and M3 devices showed increased gate leakage currents at last-pass and failure types were the same as discussed at room temperature. For all the SiC MOSFETs and both temperatures, the increased gate leakage current is probably due to trap-assisted tunnelling from the generated defects in gate oxide [5].

Fig. 9. Post-failure chip surface of the failed devices under overcurrent turn-off condition for (a) M1 (b) M2 (c) M3.

Fig. 9. Post-failure chip surface of the failed devices under overcurrent turn-off condition for (a) M1 (b) M2 (c) M3.

Fig. 9 shows the post-failure chip surface of the different manufacturer devices after decapsulating the TO packages. M1 and M3 devices do not directly show any failure region on the chip surface or even on the gate runner. However, the M2 device shows the failure spot on the gate runner for all the measured conditions.

Electro-Thermal Simulation Results

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In this section, electro-thermal simulations were performed to understand the gate failure mechanism under overcurrent turn-off conditions with different gate biases for three different cell technologies using Synopsys TCAD [6]. For this, self-built 1200 V half-cell trench-gate, double-trench-gate and planar-gate structures were designed corresponding to the real structure and calibrated, see also Fig. 1.

Fig. 10. (a) Simulated overcurrent turn-off for M1 devices for two different ,off values at (b) electric field distribution in the bottom gate oxide at time point of Simulation conditions: . Inset: simulated electric field in the gate oxide.

Fig. 10. (a) Simulated overcurrent turn-off for M1 devices for two different ,off values at (b) electric field distribution in the bottom gate oxide at time point of Simulation conditions: . Inset: simulated electric field in the gate oxide.

The overcurrent turn-off capability of the M1 device was approximately the same irrespective of the applied values for 800 V and 1000 V at both temperatures. To verify this, overcurrent turnoff simulations were performed and compared at values of 0 V and -7 V with of 53 V and , as shown in Fig. 10(a). The simulation shows a faster and correspondingly higher for lower value similar to the measurements. Fig. 10(b) displays the plotted electric field distribution at the bottom gate oxide for two different values at their corresponding . The high electric field at the pn-junction during overcurrent turn-off at and the driven gate oxide field sum up to an effective high electric field, eventually triggering pre-damage to the gate oxide of the devices which fits to increased IGSS at turn-off currents. The influence of the negative shows a small increase in the corner and bottom gate oxide electric field even though the overvoltage at turn-off increases strongly. This is due to the shielding by the deep -doped regions below the gate, see Fig. 1(a).

Fig. 11. (a) Simulated overcurrent turn-off for M1 devices for different gate bias along with change in temperature (b) electric field distribution in the bottom gate oxide at time point of Simulation conditions: . Inset: simulated electric field in the gate oxide.

Fig. 11. (a) Simulated overcurrent turn-off for M1 devices for different gate bias along with change in temperature (b) electric field distribution in the bottom gate oxide at time point of Simulation conditions: . Inset: simulated electric field in the gate oxide.

Fig. 11(a) shows the compared simulation results for at with at to understand the influence of the initial junction temperature on increased last-pass ,on or increased overcurrent turn-off robustness. The electric field in the gate bottom oxide at the corresponding was plotted in Fig. 11(b). As the initial temperature increased, the electric field in the bottom gate oxide decreased due to the reduced at higher temperatures even though increased to 64 V , see Fig. 11(b). Also, the ionization coefficient decreases with higher temperatures hence, the critical electric field required for impact ionization increases with temperature.

Fig. 12. (a) Simulated overcurrent turn-off for M 2 devices for two different ,off values at (b) electric field distribution in the bottom gate oxide at time point of . Simulation conditions: . Inset: simulated electric field in the gate oxide.

Fig. 12. (a) Simulated overcurrent turn-off for M 2 devices for two different ,off values at (b) electric field distribution in the bottom gate oxide at time point of . Simulation conditions: . Inset: simulated electric field in the gate oxide.

For M2 SiC MOSFETs, the simulations were performed to verify the reduced overcurrent turn-off robustness at lower values. At and 1000 V , the measured overcurrent turn-off capability was reduced by 61 A for values of -4 V compared to the 0 V case. Fig. 12(a) shows the simulated overcurrent turn-off results for M2 device with two different values at and of 52 V . The electric field distribution in the gate oxide at the bottom trench for values of 0 V and -4 V is plotted in Fig. 12(b). The increases by 133 V and correspondingly, the electric field in the bottom gate oxide increases strongly and exceeds at . The gate oxide shielding seems not to be sufficient for M2 devices. Although the are still below the dielectric breakdown point the tendency in the simulation is shown, also compared to M1. Similar simulated results were found under unclamped inductive switching in [7].

Fig. 13. (a) Simulated overcurrent turn-off for M 3 devices for two different values at (b) electric field distribution in the planar gate oxide at time point of . Simulation conditions: . Inset: simulated electric field in the gate oxide.

Fig. 13. (a) Simulated overcurrent turn-off for M 3 devices for two different values at (b) electric field distribution in the planar gate oxide at time point of . Simulation conditions: . Inset: simulated electric field in the gate oxide.

The measured M3 results show increased overcurrent turn-off capability with lower values, which is vice-versa to M2 devices. To understand this behaviour, overcurrent turn-off simulations were performed for two different values at with of 43 V , as shown in Fig. 13(a). The electric field distribution in the planar gate oxide at shows a higher magnitude of electric field at of 0 V as compared to -7 V , as shown in Fig. 13(b). Even though, the increases strongly for negative values, the gate oxide field is reduced as shown in the Fig. 14.

Fig. 14. Simulated electric field distribution in the M 3 devices with planar gate oxide at time point of from Fig. 13(a). Simulation conditions: ,

Fig. 14. Simulated electric field distribution in the M 3 devices with planar gate oxide at time point of from Fig. 13(a). Simulation conditions: ,

The simulations for different cell technologies have shown a high electric field in the gate-oxide region during turn-off. The simulated electric fields are in a range between to for the investigated cell technologies. This electric field magnitude along with possible defects in gate oxide and geometrical weak points (like corners etc.,) are a vulnerable point during turn-off. It has been noted that in reality, the electric fields in the gate oxide could be much higher since our simulation structures were just ideal as compared to the real structures. Furthermore, the overcurrent turn-off capability increase with increased is due to reduced

Summary

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The overcurrent turn-off capability of the SiC MOSFETs with distinct cell technologies from different manufacturers was studied in detail by measurements and supplemented with TCAD simulations. All the devices show different last-pass gate-source voltages due to their dissimilar gate oxide thickness, structure and shielding. The measured last-pass gate-source voltages are far beyond the safe operating area at DC-link voltages of 800 V and 1000 V . The measurements below 800 V do not show any failure for the measured conditions, the channel pinch-off is the limiting factor. The influence of the negative gate-source voltage strongly depends on the device design. As the initial temperature was increased, the last-pass increases for all the manufacturers. Especially, the M1 devices show a significantly increased last-pass at high temperatures. All the devices show an increased gate leakage current at last-pass field in the gate oxide at during turn-off in the range of to depending on the cell technologies.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.29.pdf

T. Kimoto and J. A. Cooper, Fundamentals Silicon Carbide Technology: Growth, Characterization, Devices, Applications Singapore: Wiley, Nov. 2014.

B. Findenig, et. al., "Robustness of SiC MOSFETs under Repetitive High Current Pulses" ICSCRM conference, Davos, Switzerland, 2022, in Material Science Forum, Vol. 1092, pp. 119-125.

D. Peters, et. al., "The new CoolSiC Trench MOSFET Technology for Low Gate Oxide Stress and High performance" in PCIM, Nuremberg, Germany, 2017, pp. 168-174.

R. Boldyrjew-Mast, et. al., "Impact of Degradation Mechanisms in Gate Stress Tests on the Hard-Switching Behavior of 1.2 kV SiC Power MOSFETs" in Proc. of ISPSD, Canada, 2022, pp. 229-232.

J. W. McPherson, "Time dependent dielectric breakdown physics - Models revisited" in Microelectronics Reliability 52, 2012, pp. 1753-1760.

TCAD Sentaurus Manual, Synopsys Inc., Mountain View, CA, USA,2022.

K. Yao et. al., "Investigation of UIS Failure Mechanism in 1.2 kV Trench SiC MOSFETs using Electro-Thermal-Mechanical Stress Analysis" in Proc. of ISPSD, Nagoya, Japan, 2021, pp. 115-118.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 39-47

doi: 10.4028/p-LpH9R4

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-03-11

Accepted:
2025-03-11

Online:
2025-09-12

Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

The original version of this paper is available on https://www.scientific.net/KEM.1024.39.pdf

Olayiwola Alatise , Saeed Jahdi , Peter Gammon , Jose Ortiz-Gonzalez , Mana Hosseinzadehlish , Konstantinos Floros and Ingo Lüdtke

University of Warwick, Coventry, CV4 7AL, United Kingdom

University of Bristol, Bristol, BS8 1UB, United Kingdom

Compound Semiconductor Applications Catapult, Newport, NP10 8BE, United Kingdom

O.Alatise@warwick.ac.uk, saeed.jahdi@bristol.ac.uk, P.M.Gammon@warwick.ac.uk,

J.A.Ortiz-Gonzalez@warwick.ac.uk, m.hosseinzadeh@bristol.ac.uk, konstantinos.floros@csa.catapult.org.uk,

Keywords: SiC MOSFET, Silicon IGBT, High Voltage Direct Current, Modular Multilevel Converter

Abstract

Voltage-Sourced Converters (VSC) that are used in High Voltage Direct Current (HVDC) systems are currently implemented in silicon Insulated Gate Bipolar Transistor (IGBT) technology. Advocates of Silicon Carbide ( SiC ) as a high voltage technology suggest that SiC has the potential to enhance the performance of these systems by improving the energy conversion efficiency. The preferred topology for the latest VSC-HVDC systems is modular multilevel converters (MMC), which are comprised of cascaded half-bridge or full-bridge sub-modules with voltages ranging between 1.3 kV and 2.8 kV . However, the ratings of current state of the art SiC power devices is not adequate. Furthermore, the low switching frequencies in Modular Multi-level Converter (MMC) topology of VSC-HVDC systems means that conduction losses dominate, hence, the fast-switching capability of SiC power devices is not necessarily an advantage. State of the art high voltage silicon devices exhibit comparable if not lower losses. This review evaluates the potential performance of SiC power devices in MMC-VSC-HVDC systems and reviews the challenges ahead for SiC devices.

Introduction

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VSC-HVDC systems are now considered to be a critical component of future power system with more renewable energy generation, interconnection of asynchronous Alternate Current (AC) systems, developments of DC super-grids as well as the implementation of reactive power compensation technologies like Static Compensators (STATCOMs). Traditionally, HVDC was implemented as current source Line Commutated Converters (LCC) based on series connected thyristor valves. This choice of converter technology was predicated on the fact that phase-controlled thyristors did not have self-turn-off capability, hence, phase to phase commutation was initiated by voltage reversal of the AC system. This meant that the switching frequency of the converter was limited to the system frequency ( 50 Hz or 60 Hz ), hence, the sizes of the filters for harmonic management could not be optimized. Although bulk power transfer was made possible, current source LCC converters exhibited numerous limitations including commutation failure in weak AC systems, inability to black-start and large filter sizes from low switching frequencies [1]. Hence, self-commutating VSC technology based on IGBTs arose as an alternative to LCC systems in applications such as offshore power transmission from wind farms where the physical size of the converter is limited by the size of off-shore platform.

Unlike the thyristor, which is a 4-layer latching device that conducts current through impact ionization induced avalanche multiplication, the IGBT conducts current through MOS-channels based on drift-diffusion mechanisms thereby making IGBTs more controllable with inherent self-turn-off capability. IGBT based self-commutating VSC technology is capable of 4-quadrant operation, can operate in weak AC systems, does not need reactive power compensation, can blackstart and is not limited by the AC system frequency. However, VSC-HVDC, whether the earlier 2-level topology with series connected devices or the more recent modular multilevel converter
(MMC) topology with cascaded half-bridge ( 2 devices) or full H -bridges ( 4 devices), suffer from higher losses since IGBT modules and their package are not as well optimized as thyristors for high currents [2].

The limited performance of silicon IGBTs in VSC-HVDC systems is one of the motivations behind the development of SiC as a high voltage power device. SiC is a wide-bandgap power semiconductor material with a high critical electric field and low intrinsic carrier concentration, making it suitable for high-voltage blocking at high junction temperatures. Its high thermal conductivity also makes it efficient at dissipating power. Historically, SiC was first released as Schottky diodes, before power Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) became commercially available, first at 1.2 kV and more recently at 1.7 kV . Manufacturers have demonstrated 3.3 kV [3], 6.5 kV [4] and 10 kV SiC MOSFETs together with 15 kV SiC IGBTs [5], however, as experimental prototypes with low current capability. Medium voltage grid converters such as Solid-State Transformers, Dual Active Bridge DC-DC Converters and STATCOMs based on 10 kV and 15 kV SiC devices are demonstrated.

SiC power MOSFETs and diodes are well-known for high-speed switching capability resulting from their unipolar characteristics since bipolar devices that use conductivity modulation suffer from tail currents in the case of IGBTs and reverse recovery in the case of PiN diodes and it exacerbates further with increased minority carrier lifetime. However, in MMC applications where maximum switching frequencies are 150 Hz thereabouts, the switching capabilities are not much of an advantage since conduction losses dominate. Furthermore, the temperature characteristics of silicon bipolar devices are better than those of SiC unipolar devices at high current ratings since minority carrier lifetime in bipolar devices increases with temperature thereby counteracting the resistive losses.

There are still significant challenges despite all the recent successes in SiC based power electronics. These challenges include, but are not limited to, gate oxide reliability, relatively low current handling capability, limited die size, high defect densities during crystal growth, low epitaxial growth rates and conduction losses that still are not as good as contemporary high voltage silicon bipolar technologies like IGBTs, Gate Turn-Off Thyristors (GTOs) and Integrated-Gate Commutated Thyristors (IGCTs). This paper balances the performance of current state of the art SiC power devices with the requirements of modern MMC-VSC-HVDC systems.

Device Technology Performance in VSC-HVDC

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The first VSC-HVDC topology was a 2-level VSC comprising of series connected IGBT modules for voltage sharing in the off-state [6]. The high switching losses, electromagnetic stresses, lack of modularity and the design complexities regarding dynamic voltage balancing motivated academic and industrial research towards multi-level converter topologies including diode clamped, flying capacitor, cascaded H-bridges and MMC [7]. MMC topologies, where the AC sine waves are synthesized by discrete voltage levels from separate DC sources, have been the preferred option due to its modularity and fault tolerance. By using bypass thyristors and mechanical switches, defective voltage units can be shorted thereby making the converter significantly more fault tolerant than the preceding 2-level VSC or the multi-level NPC. MMC topologies can be Half-Bridge (HB), FullBridge (FB) or hybrids like the Alternate Arm Converter (AAC) [8] or the Series Bridge Converter (SBC) [9]. Although the FB and AAC offer fault blocking capability, the additional losses (due to higher device count in the current flow path) and additional control complexities means that the HBMMC is the only variant that has been commercialized to date. A typical MMC-VSC comprises of 6 valves for the 3 phases with each phase comprised of the required number of series connected voltage units required to block the total DC voltage in the off-state. There is a fundamental trade-off between the number of units (which depends on the unit's voltage) and the complexity of the overall control system. A high number of levels implemented with lower voltage units will produce a smoother sinewave and reduce the voltage requirements of all unit components; however, with a more complex control system. A smaller number of levels implemented in higher voltage modules reduces the complexity of the control system however at the expense of producing a less smooth sinewave and needing high voltage rated voltage unit components including capacitors, busbars and ancillary
electronics. The number of levels can be at least 100 voltage units for eliminating the need to install output filters, however, even a converter with only 23 voltage steps can provide a harmonics output of . On the contrary, today's VSC-HVDC converters have a significantly higher number of levels in the region of a few hundred. This is driven by the fact that the typical line-to line voltage of (so valve voltage of 640 kV ) needs to be shared between voltage-sourced levels.

Using the half bridge MMC topology shown in Fig. 1 together with the system level parameters in table 1, the performance of commercially available 1.7 kV SiC MOSFETs (from Wolfspeed) together with high voltage IGBTs ( and 6.5 kV ) and IGCTs from Hitachi (then ABB) is analyzed. The converter is simulated under 6 different conditions as stated in table 2. Table 3 shows the power module technology simulated with the critical datasheet parameters used for the simulation.

Fig. 1. The MMC-VSC-HVDC-HB converter topology used as the architecture to explore impact of SiC technology on HVDC power systems.

Fig. 1. The MMC-VSC-HVDC-HB converter topology used as the architecture to explore impact of SiC technology on HVDC power systems.

Table 1. System parameters for the MMC converter. Table 2. MMC converter operation modes.

Parameter | Value | Unit
AC Voltage | 350 | kV
DC Voltage | ±320 | kV
DC Current | 350 | A
Active Power | 225 | MW
Reactive Power | -200 - 200 | MVar
Frequency | 50 | Hz

Table 3. Device parameters used in MMC simulation.

Device | Make | Voltage (kV) | Current (A) | Switch Thermal Resistance (°C/W) | Diode Thermal Resistance (°C/W) | VCE at 300 V & 125 °C (V)
SiC MOSFET | CREE | 1.7 | 325 | 0.071 | 0.065 | 5.1
Silicon IGBT | ABB | 1.7 | 800 | 0.021 | 0.036 | 1.7
Silicon IGBT | ABB | 4.5 | 1200 | 0.009 | 0.019 | 1.8
Silicon IGBT | ABB | 6.5 | 1000 | 0.009 | 0.017 | 2.5
Silicon IGCT | ABB | 6.5 | 1290 | 0.008 | 0.017 | 1.8

The voltage rating of the individual units will ultimately determine the number of units needed to block a given DC voltage. Fig. 2 shows the number of voltage source units for the different power modules under analysis where the number of units needed increases as the voltage rating of each unit decreases. It should be noted that the module blocking voltages are considered to be de-rated by i.e. it is assumed that the maximum blocking voltage imposed on the device is of its rated breakdown voltage so the 1.7 kV module is operated at 1.2 kV , the 4.5 kV devices are operated at 3.2 kV and finally 6.5 kV devices are operated at 4.5 kV .

The converter losses are calculated solely according to the information extracted from the datasheets. The following steps are used in modelling the conversion losses of the converter [10]:

Fig. 2. The number of voltage units per converter's device technology. The devices with higher voltage ratings will support the line voltage with smaller number of units connected in series impacting the overall conduction and switching losses.

Fig. 2. The number of voltage units per converter's device technology. The devices with higher voltage ratings will support the line voltage with smaller number of units connected in series impacting the overall conduction and switching losses.

i The operating mode of the converter determined by the control algorithm is used to determine the load current through the transistor and anti-parallel diode.
ii The recommended gate drive voltage is used to determine the on-state voltage drop from the output characteristics
iii The temperature and current-dependent conduction loss is calculated from look-up tables.
iv The temperature and current-dependent switching loss is calculated from look-up tables.
v The combined losses are input to the thermal model which is derived from the datasheet thermal impedance characteristics (the case temperature is fixed).
vi The calculated junction temperature determines the new losses together with load current and switching state.

Fig. 3(a) shows a technology comparison of the unit losses, voltage of each units, number of voltage units, total converter losses and the junction temperature while the MMC is in inverter mode. Fig. 3(b) shows the same comparison while the converter is in rectifying mode. It can be seen from Fig. 3(a), that as far as the total converter losses are concerned, the 6.5 kV silicon IGCT is the most efficient technology whereas the 1.7 kV SiC MOSFET is the least efficient. Fig. 4 shows the simulated maximum junction temperature of the devices in the power module during (a) capacitive mode and (b) inductive mode of operation. During inverting operation, the junction temperature refers to the transistor and in rectification mode, the junction temperature refers to the diodes. Looking at the junction temperatures, the SiC MOSFET module exhibits the highest junction temperatures. This is due to the fact that SiC power devices typically have higher junction-to-case thermal resistances compared to comparatively rated silicon IGBTs as can be seen in table 3. This is because SiC chips have considerably smaller active areas compared to comparatively rated silicon IGBT chips. Early generation SiC chips had thicker substrates (for ease of mechanical handling), despite having thinner drift layer thicknesses that result in low conduction losses. The new generations, though, use advanced substrate thinning techniques that improve thermal impedance between junction and case.

Fig. 3. Comparison of the main converter parameters for different power module technologies for the (a) Inverter, and (b) Rectifier modes.

Fig. 3. Comparison of the main converter parameters for different power module technologies for the (a) Inverter, and (b) Rectifier modes.

Fig. 4. Junction temperature of power devices in capacitive and inductive modes of operation.

Fig. 4. Junction temperature of power devices in capacitive and inductive modes of operation.

Fig. 5 shows the total voltage unit and converter losses for the different device technologies in the MMC in inverter and rectifier operation for both inductive and capacitive modes of operation. In this figure, the 1.7 kV silicon IGBT has the lowest losses followed by the 1.7 kV SiC MOSFET module. This is expected since they are the lowest voltage rated devices, hence, will have the lowest conduction losses. The 1.7 kV silicon IGBT module exhibits half the losses of the 1.7 kV SiC MOSFET module. When looking at the total simulated converter losses, the silicon bipolar (IGBTs and IGCT) based converters have lower losses than the 1.7 kV SiC MOSFET based converter. The high losses of the SiC MOSFET converter compared to IGBTs and thyristors is due to the fact that the MOSFET is unipolar while the IGBT and IGCT are bipolar. Bipolar devices use conductivity modulation from minority carrier injection to ensure low conduction losses while MOSFETs rely only on the drift of majority carriers. As far as conduction losses are concerned, high voltage SiC MOSFETs are not as efficient as silicon IGBTs and this difference becomes magnified as the voltage level of devices increase. This is one of the key motivations behind research into SiC IGBTs.

Fig. 5. The simulated voltage units losses, and converter losses, for different devices in the MMC.

Fig. 5. The simulated voltage units losses, and converter losses, for different devices in the MMC.

Challenges for SiC Implementation

The original version of this paper is available on https://www.scientific.net/KEM.1024.39.pdf

Gate Driving Issues in SiC. Fast switching rates in SiC power MOSFETs result in low switching losses. Being unipolar, these losses are determined by the charging and discharging of parasitic capacitances. In high power bipolar devices like IGBTs and thyristors, the switching rate is not only determined by capacitance discharge but also by the extraction and recombination of minority carriers
in voltage blocking drift layers. This results in tail currents for IGBTs and reverse recovery for PiN diodes. The high and enabled by SiC causes problems in the presence of parasitic capacitances and inductances [11]. Due to the much higher voltage and current commutation rates inherent in SiC MOSFET switching, electromagnetic oscillations (ringing) is a well-known problem that results from resonating LC components. Higher switching generates more voltage oscillations. Likewise, higher will generate more current oscillations.

Other problems that result from high voltage/current commutation rates include Miller-capacitance feedback effects (between transistors in the same phase leg) leading to short circuits across the DC link of the converter [12]. This is sometimes referred to 'parasitic gate turn-on' or 'cross-talk'. High across the SiC MOSFET coupled with the Miller capacitance induces a parasitic current and flows through the gate resistance and results in a parasitic gate voltage. If this unintentional gate voltage exceeds the threshold voltage, then the device turns-on thereby causing a temporary short circuit. This problem is solved in IGBTs by turning off with negative gate voltages thereby increasing the offset between the off-state and threshold voltage. This approach works in SiC as well, however, this can have reliability implications since the gate oxide is not as reliable as in silicon. Slowing down the device can mitigate cross-talk; however, this will be at the expense of increased switching losses.

Gate Dielectric Reliability. Gate dielectrics in silicon MOSFETs and IGBTs are formed simply by the thermal oxidation of silicon. Interface and fixed oxide traps result from imperfections in the silicon interface. Over the decades, these traps have been well managed by improved process recipes in silicon, however, academic and industrial publications [13] show that the interface is more challenging. This is due to excess carbon atoms, originating from the SiC, which get trapped at the oxide interface during gate formation via thermal oxidation [14]. There has been significant research into the development of reliable oxide interfaces for SiC MOSFETs [15]. Threshold voltage shift and bias temperature instability (BTI) are well-known reliability problems in SiC that are due to increased interface and fixed oxide traps [13]. BTI results from electron capture from the channel into the gate dielectric when the device is in inversion (device is on and VGS is high) and hole capture from the channel when the device is in accumulation (device is off and is negative). The result is a downward threshold voltage drift for negative BTI (NBTI) and an upward threshold voltage drift for positive BTI (PBTI). PBTI can cause a marginal increase in on-state resistance, however, NBTI can cause destructive failure through current crowding in high current modules where parallel devices are required to share current and gate synchronization is lost due to unequal NBTI shifts between parallel devices [13]. Typically, the IGBT characteristics for the unstressed device and the stressed device overlap, meaning there is virtually no Vth shift. This is not the case with SiC as there is a shift in the transfer characteristics for PBTI and NBTI.

The previous section on gate driving issues in SiC highlighted the need to turn-off SiC power MOSFETs with negative voltages to avoid cross-talk between devices in the same phase leg. The improved gate dielectric properties in silicon devices means high off-state negative gate voltages can be used to suppress the effect completely. However, in SiC there are limitations to how high the offstate negative gate voltage can be and there are long term reliability implications for the continued use of negative voltages due to NBTI. For this reason, negative turn-off voltages for SiC MOSFETs are lower compared with Silicon devices.

Thermo-Mechanical Reliability of SiC Devices. In applications with high failure costs, like HVDC, the reliability of the packaging system is paramount for increasing the speed of adoption of SiC power modules. The traditional Direct-Bond Copper (DBC) based packaging technology was developed for silicon devices hence the different thermomechanical properties of the silicon chip have an impact on the stresses on the packaging elements and its reliability. The stiffness of the SiC chip, a result of its Young's Modulus being three times higher compared with a silicon chip, causes higher thermomechanical stresses in the solder due to Coefficient of Thermal Expansion (CTE) mismatch, hence the fatigue increases and its lifetime reduces [16]. The physical size of SiC chips, which are smaller in area and thicker than Silicon IGBT chips, also contribute to higher stresses on the solder [17]. All these factors initially contribute to a reduced power cycling capability of modules
using SiC chips [16], hence the development of packaging more suitable for SiC chips is necessary. Research studies [18] have shown alternative packaging alternative for SiC chips, with improved interconnects, metallization, solders, ceramic substrates and assemblies are proposed and evaluated. There are studies already presenting an improved power cycling capability of SiC modules: using sintered silver die attach [19] and sintered copper [20]. A packaging alternative which has demonstrated a superior power cycling capability and reliability is pressure packaging (press-pack or pressure contacts), where the solder and wirebonds are removed and the semiconductor chip is sandwiched between two copper poles using two intermediate contacts for CTE matching [21]. This packaging system ensures failure into a stable short-circuit [22], which is a requirement for topologies with series connected devices, as used in alternate arm converter MMC topologies. Some initial studies of SiC using pressure contacts have been presented, for example [23], and a higher power cycling capability has been reported [24], together with stable short-circuit capability. However, as the chip size is smaller compared with silicon, the development of a high current press-pack module will be challenging as it involves the parallel connection [25] of multiple chips [26].

Prospect of SiC in HVDC

The original version of this paper is available on https://www.scientific.net/KEM.1024.39.pdf

The results of the current study indicate that the application of currently available SiC transistor technology is not yet fully practical in HVDC converters [27]. However, the properties of SiC devices are rapidly improving and there could be a room in the future for these devices in HVDC converters. This holds as SiC technology was initially developed for medium voltages and high frequency applications and reduction of on-state resistances and switching speeds were main design targets. In HVDC switching speed is not that important so a targeted designed device for this application could change the current landscape. For this to be realized, SiC MOSFETs with very low on-state resistances and acceptable price are required to outperform IGBTs. The voltage rating of devices should increase to 4.5 kV with larger chips which should increase the current rating of devices to at least 500 A for viable paralleling solutions. Larger chip size would improve the thermal resistance characteristics, so the excessive junction temperatures seen in current SiC device would no longer exist. SiC devices show strong avalanche ruggedness compared with silicon device and this could be useful in heady-duty applications. The breakthrough would of course be significant reduction in price coupled with complete elimination of the gate oxide failure mode in fabrication and increase in rating.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1024.39.pdf

This paper has reviewed the feasibility of SiC power MOSFETs for VSC-HVDC applications at the time of writing. MMC simulations have been used to compare the performances of 1.7 kV SiC MOSFET modules with 1.7 kV Silicon IGBT modules as well as higher voltage rated IGBT and IGCT modules. The results show that overall converter losses are highest with the SiC MOSFET modules because the conduction losses are still higher compared to silicon IGBT and IGCT modules. The number of voltage sourced units required for a given DC voltage is higher because of the reduced breakdown voltage available in SiC MOSFETs compared to silicon IGBT technology where 4.5 kV and 6.5 kV voltage blocking capability is available. SiC IGBTs appear to be the ideal candidate for VSC-HVDC systems since SiC MOSFET technology exhibits unacceptable conduction losses. There are still major technological challenges regarding the fabrication of high voltage and high current SiC modules suitable for HVDC systems. Until then, silicon bipolar technology will continue to dominate.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1024.39.pdf

We acknowledge the funding support of UK EPSRC via grant EP/Y000307/1 and Catapult Network's 'Innovation Launchpad Network+' program with grant EP/W037009/1 through the Researcher-in-Residence in collaboration with Compound Semiconductor Applications Catapult in Newport, UK.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 49-56

doi: 10.4028/p-k87Vmx

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-04

Accepted:
2025-08-04

Online:
2025-09-12

Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC Engineered Substrates

The original version of this paper is available on https://www.scientific.net/KEM.1024.49.pdf

Mohamed Alaluss , Christoph Böhm , Madhu Lakshman Mysore , Patrick Heimler , Thomas Basler , Ahmed Elsayed , Karl Oberdieck , and Sudhanshu Goel

Chemnitz University of Technology, Chair of Power Electronics, Chemnitz, Germany

Robert Bosch GmbH, Reutlingen, Germany

mohamed.alaluss@etit.tu-chemnitz.de, christoph.boehm@etit.tu-chemnitz.de, karl.oberdieck@de.bosch.com, sudhanshu.goel@de.bosch.com

Keywords: SiC MOSFET, SiC Engineered Substrate, SmartSiC, Body Diode, Reverse Recovery, Surge Current, Short Circuit, TCAD

Abstract

The improvement of the electrical properties of power semiconductors using engineered substrates is becoming increasingly significant. This paper investigates the dynamic performance and robustness of SiC MOSFETs based on SmartSiC engineered substrates, focusing on the reverse recovery of the body diode and their ruggedness under overload conditions such as short-circuit and surge current. A comparison with SiC MOSFETs based on conventional monocrystalline substrates was performed to evaluate the results. A significant decrease in reverse recovery charge was observed, particularly at higher temperatures, while the robustness during short-circuit type I and surge current was not affected.

Introduction

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Power semiconductor devices based on silicon carbide ( SiC ) are increasingly being adopted, particularly in the automotive industry. To meet the constantly growing demand, the availability of highquality base material is crucial. Moreover, there is a need to further optimize factors such as cost and wafer yield. SmartCut technology addresses this by combining a thin ( 350 high-quality monocrystalline SiC layer with a thick low-resistivity polycrystalline SiC carrier wafer through wafer bonding and wafer cut by hydrogen implantation [1,2]. This results in an engineered SmartSiC substrate with a low resistivity ( ), significantly lower than that of commercial monocrystalline material ( ). Furthermore, the ability to reuse the monocrystalline donor wafer multiple times after the splitting process improves the utilization efficiency of the SiC starting wafer.

The reliability of power devices using the engineered substrates, particularly in terms of power cycling capability, has been explored in several publications [2,3]. However, assessing dynamic performance, such as the reverse recovery process, and ensuring robustness under overload conditions is also crucial. The electrical and thermal properties of the engineered substrate can impact the power device's performance in these scenarios. Therefore, this paper examines the extent to which the dynamic performance and the overload robustness are influenced.

Methodology and Devices under Test

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To evaluate the performance of a power device based on a SiC engineered substrate, it is crucial to compare it with a device based on a conventional pure monocrystalline substrate as reference. For this purpose, SiC MOSFETs of the 1200 V voltage class with a trench structure were fabricated using both SiC engineered and conventional monocrystalline substrates. By processing these two types of SiC MOSFETs under similar conditions, their performance can be directly compared, enabling an
evaluation of the SiC engineered substrate's impact. The cell design, the - base region and the buffer layer are identical for both devices types. Furthermore, the assembly and interconnection technology (AIT), based on a die top system (DTS), is the same for both types of SiC MOSFETs. However, it is important to note that the MOSFET based on a SiC engineered substrate is thicker than the reference SiC MOSFET. The schematic cross section of both devices is depicted in Fig. 1.

Fig. 1: Schematic cross section of (a) reference and (b) SiC engineered substrate based MOSFET.

Fig. 1. Schematic cross section of (a) reference and (b) SiC engineered substrate based MOSFET.

Fig. 2: Comparison of IV-characteristic for different .

Fig. 2. Comparison of IV-characteristic for different .

The substrate resistance in a MOSFET based on a SiC engineered substrate can be divided into three individual components: the resistance of the thin monocrystalline layer, the resistance at the bonding interface, and the resistance of the polycrystalline layer. The resistivity of the bonding interface is extremely low, typically ranging from 3 to [4]. In total, these resistances are up to lower than that of a conventional substrate [1]. Given that the resistance of the n -channel/JFETregion is the dominant component in a 1200 V SiC MOSFET, the overall reduction in total resistance ( ) for the MOSFET based on a SiC engineered substrate will be less pronounced. Fig. 2 shows a comparison of the IV-characteristic for both SiC MOSFETs. A reduction in the voltage drop and consequently the resistance can be observed in both quadrants at both measured temperatures ( ) for the MOSFET based on the SiC engineered substrate. However, to obtain a qualitative assessment of the resistance reduction, the resistance of 35 devices was measured for each of the two device technologies. A trend toward lower is observed for the MOSFET based on a SiC engineered substrate, with an average reduction of compared to the reference.

Measurement Results and Discussion

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Reverse recovery behavior. Initially, the reverse recovery behavior was measured during the turnoff process of the body diode. A measurement setup and methodology described in [5] was used to perform this investigation. The high-side and low-side MOSFET are the same type of MOSFET. The DC-Link voltage was set to 850 V for all measurements. To ensure an equitable comparison of the reverse recovery at similar switching speeds, identical gate resistances and values were chosen for both device technologies. Fig. 3 compares the reverse recovery behavior of the reference and SiC engineered substrate based device at different temperatures.

At , no significant difference can be observed between voltage ( ) and current density (js) for both technologies. A typical, almost capacitive-only switching behavior is observed. However, at , the device based on the SiC engineered substrate shows a lower reverse recovery current peak density ( ) and time ( ). Consequently, the losses during reverse recovery ( ) are reduced.

Fig. 3: Comparison of the measured reverse recovery behavior for different at , and .

Fig. 3. Comparison of the measured reverse recovery behavior for different at , and .

The reverse recovery charge ( ) is comprised of a capacitive stored charge ( ) and a stored charge from charge carriers ( ) [6]. Fig. 4a illustrates the temperature dependency of , revealing that both substrate technologies show an increase in at higher . This increase is attributed to a higher ionization degree of the p-doped region and a higher carrier lifetime at elevated temperatures, leading to a more pronounced influence of . Additionally, the difference in between the reference and the SiC engineered substrate based device increases with elevated . At , the of the device based on a SiC engineered substrate is reduced by compared to the reference device. Further measurements were conducted at elevated temperatures and various current densities. A higher current density results in a higher , as the increased current density enhances plasma in the drift region (see Fig. 4b). Thus, the contribution to increases. The reduced of the device based on a SiC engineered substrate is also noticeable under different current densities, with the reduction becoming more significant as the current density increases.

Fig. 4: Reverse recovery charge for different temperatures and current densities at , and .

Fig. 4. Reverse recovery charge for different temperatures and current densities at , and .

The device based on a SiC engineered substrate shows a reduced voltage drop in the quadrant and a lower , which initially appears contradictory. Therefore, a more detailed understanding
of plasma behavior during reverse recovery is necessary to explain these findings from the measurements for both technologies. To investigate this, electro-thermal simulations were carried out on a self-designed 1200 V half-cell SiC MOSFET with a trench-cell structure using Synopsys TCAD [7]. Furthermore, the devices' substrate compositions were considered, as shown in Fig. 1. For the device based on a SiC engineered substrate, the doping concentration on the drain-side was adjusted (see Fig. 5a). The poly-SiC material has a higher doping concentration compared to mono-SiC, resulting in higher electrical conductivity [4]. Additionally, a hypothesis was made that the bonded mono-SiC contains a higher density of trap levels due to hydrogen implantation [8]. The IV-characteristic curve in the quadrant for both structures, simulated at an temperature of , is illustrated in Fig. 5 b . The body diode of the device based on a SiC engineered substrate shows a lower voltage drop as compared to the reference device, similar to the measured IV-characteristic (see Fig. 2).

Fig. 5: Doping concentration and simulated IV-characteristic in quadrant for both device technologies.

Fig. 5. Doping concentration and simulated IV-characteristic in quadrant for both device technologies.

A time-dependent electro-thermal reverse recovery behavior was simulated at a DC-link voltage of 850 V , and of for both structures. The simulated reverse recovery behavior for reference and SiC engineered substrate based MOSFET is shown in Fig. 6a. The and are lower for the SiC engineered substrate based device as compared to the reference device. Hence, the simulated results show reduced . To understand the plasma behavior during reverse recovery, four time points were considered (see Fig. 6a). The electric field, electron and hole density were plotted at the corresponding time points in Fig. 6b. At time point , the body diode operates in conduction mode. For the device based on a SiC engineered substrate, a higher density of trap levels introduced by the bonded mono-SiC, results in a reduced electron injection from the drain-side. Consequently, the hole density is lowered at the interface between the -base and the buffer, along with the penetration depth into the buffer region. In total, this leads to a reduced back-side emitter efficiency and charge carrier lifetime. The time point was selected at the zero crossing of the current during the onset of the diode turn-off. For both and , the electric field is negligible as the device is still in the conduction mode. Subsequently, the electron and hole densities near the p-region decrease for both structures as the current density reduces. However, at the -region/buffer interface, the hole density and penetration depth remain lower for the device based on a SiC engineered substrate. At time point , the device based on a SiC engineered substrate reaches the reverse recovery current peak. Additionally, it shows a stronger electric field expansion with higher magnitude. At time point , the plasma is removed for the device based on a SiC engineered substrate and the electric field spans the entire -region due to faster depletion of charge carriers. Further, the hole density is three orders of magnitude lower than in the reference device at the drain-side of the -region. The reduced hole density, as well as the corresponding electron density, results in a lower and for the device based on a SiC engineered substrate, as observed in the measurements.

Fig. 6: Comparison of simulated reverse recovery behavior and electric field and charge carrier density at different time points at and .

Fig. 6. Comparison of simulated reverse recovery behavior and electric field and charge carrier density at different time points at and .

Short-circuit behavior. In this section, the short-circuit type I (SC I) robustness of SiC MOSFETs based on a SiC engineered substrate is assessed and compared with the reference. The maximum short-circuit withstand time (tscwt) for each type was determined by gradually increasing the shortcircuit duration by 50 ns until either failure occurred or a change in one of the static parameters was observed. The initial short-circuit time was set to 500 ns and the DC-link voltage was set to 800 V . Measurements were taken at and . Five DUTs were tested for each condition and device technology. A typical SCI waveform is shown for both device technologies in Fig. 7a.

Fig. 7: Comparison of the short-circuit type I behavior and maximum short-circuit current density peak at different for and .

Fig. 7. Comparison of the short-circuit type I behavior and maximum short-circuit current density peak at different for and .

A significant difference in short-circuit behavior was not observed. However, a slightly higher short-circuit current density was noted for the device based on a SiC engineered substrate. Fig. 7b compares the measured maximum short-circuit current density as a function of for the measured initial. At each measured initial temperature, the maximum short circuit current remains within the same range, irrespective of the substrate used and the corresponding specific on-state resistance. The short-circuit current is primarily determined by the n-channel and, thus, the cell design. Hence,
the substrate resistance does not influence the short-circuit current. The saturation current ( ) of the MOS-channel, and thus the short-circuit current, can be calculated using the following equation:

with channel conductivity

where - channel width, - mobility of electrons in the channel, - gate oxide capacitance, length of channel [9]. Fig.7b further indicates that within a device group, a lower specific resistance results in a higher short-circuit current. This effect is e.g. due to variations in the threshold voltage. In particular, a lower threshold voltage reduces channel resistance, leading to a lower total on-resistance. Additionally, a lower threshold voltage results in a higher short-circuit current, as described by Equation 1. At elevated temperature, the short-circuit current density decreases due to the reduction in the charge carrier mobility within the channel and bulk region.

Fig. 8 shows the obtained maximum short-circuit withstand time and the corresponding energy for both device technologies at different initial. Considering the average value for both, short-circuit withstand time and corresponding energy, no substantial difference between the two technologies is found. The variation in the maximum current peak leads to a variation in the achieved short-circuit duration. The failure of the DUT could be detected either by an increase in the gate leakage current ( GSS) after the short-circuit stress or by the destruction of the device during the turn-off phase of the short-circuit.

Fig. 8: Comparison of the short-circuit type I capability at different for and . (Note: line represents the mean value for each device group)

Fig. 8. Comparison of the short-circuit type I capability at different for and . (Note: line represents the mean value for each device group)

Surge current behavior. The surge current robustness of the SiC MOSFET based on a SiC engineered substrate in quadrant was evaluated with respect to a 10 ms current half-sine wave. The surge current capability was determined by increasing the surge current amplitude stepwise, till the DUT failed or a static electric parameter indicated the imminent destruction of the device. The investigation was carried out with a of -5 V , at two different of and . Five DUTs were tested for each condition and device technology. A comparison of the surge current capability in terms of critical current density amplitude and corresponding energy density is given in Fig. 9. The device based on a SiC engineered substrate shows no significant change in the critical current density amplitude for both . However, the critical energy leading to failure is lower for the device based on SiC engineered substrate. To analyze this behavior, a comparison of the surge current behavior was conducted. Fig. 10 shows a lower voltage drop during the surge current for the device based on a SiC engineered substrate, leading to an reduction in surge current energy. This reduction is

Fig. 9: Comparison of the surge current capability at different for and .

Fig. 9. Comparison of the surge current capability at different for and .

explained by the low resistivity of the polycrystalline SiC . The reduction in critical energy density is expected, in principle, to lead to a higher surge current capability. Although the voltage drop and corresponding energy density decrease during the surge current, no significant change was observed in the critical surge current amplitude. Instead, a reduction in critical energy density was detected by indicating that a critical temperature is reached at lower energy density levels. A failure of the devices was identified by an increase in GSS for both device technologies. The molten aluminium can damage the gate insulation, which may result in a short between gate and source contacts.

Fig. 10: Comparison of the surge current behavior at Surge and .

Fig. 10. Comparison of the surge current behavior at Surge and .

Fig. 11: Comparison of the thermal impedance of the devices and thermal conductivity of the substrates [4].

Fig. 11. Comparison of the thermal impedance of the devices and thermal conductivity of the substrates [4].

The results indicate a difference in thermal behavior between the two device technologies. The thermal behavior was evaluated through thermal impedance measurements, as depicted in Fig. 11. The thermal resistance during surge current could be approximated with the thermal impedance . At this point, the device based on a SiC engineered substrate exhibits a higher thermal resistance. The polycrystalline SiC has a lower thermal conductivity than monocrystalline SiC (see Fig. 11). However, the difference in thermal conductivity decreases at elevated temperature, thus reducing its impact during surge current as the device can reach temperatures above . Further, the chip is thicker, which further increases thermal resistance. Nonetheless, the thicker chip also provides higher thermal capacity, partially counteracting the increased thermal resistance.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1024.49.pdf

This study explores the dynamic behavior and robustness of MOSFETs fabricated using SiC engi neered substrates, compared with those based on purely monocrystalline substrates. The results indicate that MOSFETs based on a SiC engineered substrate exhibit a reduction in on-state resistance, attributed to the lower specific resistance of the polycrystalline SiC . The analysis of the reverse recovery behavior reveals that the MOSFETs based on a SiC engineered substrate achieve a lower reverse current peak and shorter reverse recovery time, especially at elevated temperatures and high current densities, resulting in a reduced reverse recovery charge and losses. TCAD simulations indicate that these improvements can probably be explained by a reduced electron injection and reduced hole density. In terms of robustness, no significant differences were observed in short-circuit type I behavior when comparing MOSFETs with a SiC engineered substrate to their monocrystalline counterparts. The reduction in substrate resistance does not lead to an increase in short-circuit current. However, a decrease in critical energy density during surge current events was noted, despite the critical current density remained unchanged. This decrease is attributed to variations in thermal behavior, which are partially due to the lower thermal conductivity and higher thickness of the MOSFETs based on a SiC engineered substrate.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/KEM.1024.49.pdf

This work has been carried out within TRANSFORM project which has received funding from the Key Digital Technologies Joint Undertaking (KDT JU) under Grant Agreement No101007237. The JU receives support from the European Union's Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.49.pdf

N. Daval et al., "SmartSiC for Manufacturing of SiC Power Devices", in Proc. EDTM, Oita, Japan, 2022, pp. 85-87.

E. Guiot et al., "Improved Power Cycling Reliability through the use of SmartSiC Engineered Substrate for Power Devices", in Proc. PCIM Europe 2023, Nuremberg, Germany, 2023, pp.1-5.

E. Guiot et al., "Proven Power Cycling Reliability of Ohmic Annealing Free SiC Power Device through the Use of SmartSiC Substrate", in Proc. Materials Science Forum 2023.

H. Biard, A. Drouin, W. Schwarzenbach, K. Alassaad, L. Coeurdray, et al., "Poly-SiC Characterization and Properties for SmartSiC ", in Materials Science Forum 1124, pp. 2125.

X. Liu, X. Li, C. Herrmann and T. Basler, "The Impact of the Dead-Time on the Reverse Recovery Behavior of SiC-MOSFET Body Diodes", in Proc. ISPSD, Hong Kong, 2023, pp. 322-325.

P. Sochor, A. Huerner, Q. Sun and R. Elpelt, "Understanding the Switching Behavior of Fast SiC MOSFETs", in Proc. PCIM Europe 2022, Nuremberg, Germany, 2022, pp. 1-8.

TCAD Sentaurus Manual, Synopsys Inc., Mountain View, CA, USA, 2022.

S. Harada, T. Mii, H. Sakane et al., "Suppression of stacking fault expansion in a epitaxial layer by proton irradiation." in Sci Re 12, 13542 (2022).

J. Lutz, H. Schlangenotto, U. Scheuermann, and R. De Doncker, "Semiconductor Power Devices: Physics, Characteristics, Reliability, Second Edition", Berlin, Germany, Springer-Verlag, 2017.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 57-64

doi: 10.4028/p-rS5BUg

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-08-02

Accepted:
2025-08-04

Online:
2025-09-12

Device Performance and Reliability of SiC CMOS up to

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

Keywords: MOSFET, CMOS, Field Effect Mobility, Threshold Voltage, Chemical Vapor Deposition, Transfer Characteristics, Interface Traps, Reliability, BTI

Abstract

This study evaluates the performance and reliability of SiC n- and p-MOSFETs across a temperature range from room temperature up to , focusing on field effect (FE) mobility and threshold voltage variations under high thermal and bias stress conditions. By analyzing the variations in field effect mobility and threshold voltage under different stress conditions, our study illustrates distinct behaviors between devices with thermally grown oxides and those with chemical vapor deposited (CVD) oxide layers, underscoring significant differences in long term performance. Results indicate that while n-MOSFETs maintain threshold voltage shifts below and exhibit robust characteristics up to , p-MOSFETs exhibit permanent threshold voltage shifts of up to and mobility reductions of particularly above DC stress. The 2 nm ultrathin thermal (UT) followed by 40 nm CVD , outperform thermal oxides, sustaining less degradation in mobility and less shift in threshold voltage under bias temperature instability (BTI) conditions at voltages up to and temperatures as high as . This research advances SiC CMOS technology by confirming that SiC n-MOSFETs are ready for high-temperature circuit applications, while highlighting the need for further improvement in p-MOSFETs to enhance their reliability under extreme conditions.

Emran Ashik, Sundar B Isukapati, Hua Zhang, Tianshi Liu, Utsav Gupta, Adam J Morgan, Veena Misra, Woongje Sung, Ayman Fayed, Anant K Agarwal, Bongmook Lee

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

Department of ECE, North Carolina State University, Raleigh, NC, USA
College of Nanoscale Sci. and Eng., SUNY University at Albany, NY, USA
Department of ECE, Ohio State University, Columbus, OH, USA
College of Eng., SUNY Polytechnic Institute, Utica, NY, USA
ekashik@ncsu.edu, Slsukapati@sunypoly.edu, zhang.8230@buckeyemail.osu.edu,
dliu.2876@buckeyemail.osu.edu, égupta.1121@buckeyemail.osu.edu, adam.morgan@nomispower.com, vmisra@ncsu.edu, wsung@albany.edu, ifayed.1@osu.edu, jagarwal.334@osu.edu, kleeb1@sunypoly.edu

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

Silicon carbide (SiC) has accumulated significant attention in the semiconductor industry due to its outstanding physical and electronic properties [1]. As a wide bandgap material, SiC is inherently capable of operating at higher electric fields, power levels, and thermal environments compared to traditional silicon-based devices. This robustness makes SiC an ideal candidate for power electronics, particularly in applications requiring high efficiency and reliability under extreme conditions such as in electric vehicles, aerospace, and industrial power systems [2], [3]. SiC distinguishes itself from other wide-bandgap semiconductors by allowing the straightforward growth of gate oxides in a similar manner to silicon. This key advantage positions SiC as a superior choice for applications requiring wide bandgap materials due to its ease of fabrication and enhanced device performance. Despite its significant advantages, SiC technology, particularly in metal-oxide-semiconductor fieldeffect transistors (MOSFETs), encounters notable challenges that can impact device performance and reliability. One such challenge is the poor interface quality between the SiC substrate and the gate oxide. The interface quality is crucial because it affects the mobility of charge carriers and the stability of the device's electrical characteristics under different operating conditions. Imperfections at this interface, such as traps and defects formed mainly due to carbon cluster formations and oxygen
vacancies, lead to increased electron scattering, reduced carrier mobility, and fluctuations in threshold voltage, which in turn compromise the efficiency and lifespan of the MOSFET [4], [5], [6].

Due to these imperfections, high-temperature operations can accelerate the failure of SiC MOSFETs, worsening issues like increased leakage currents and dielectric breakdown [7]. One of the critical issues in SiC MOSFETs is the reliability of the gate oxide layer when subjected to temperatures exceeding , a standard threshold in power electronics [8], particularly regarding the degradation mechanisms that impact their long-term stability and performance. The reliability concerns arise from the significant presence of traps at the interface. Strategies such as enhanced passivation layers and thermally stable contact materials are critical for maintaining device performance and longevity under these conditions. Among the reliability concerns, bias temperature instability (BTI), particularly negative BTI, poses a significant challenge for SiC MOSFETs, manifesting as large shifts in threshold voltage (Vth) [9], [10], [11]. These shifts are exacerbated at high temperatures, leading to degraded device performance and lifetime [7]. The underlying cause often ties back to the quality of the gate oxide. Thermally grown silicon dioxide ( ) on SiC tends to exhibit a higher density of interface traps ( ), which are accentuated under thermal stress and electric bias, further compounding reliability issues [12], [13].

This paper represents the behavior of n - and p -type SiC MOSFETs across a wide temperature range, from room temperature up to , with a particular focus on mobility and threshold voltage variations. By conducting a comparative study of devices with thermally grown oxides versus those with CVD oxides, it highlights distinct performance differences under various stress conditions. Our results underscore the superior stability and performance of deposited oxide layers compared to traditional thermal oxides, particularly in high-temperature applications. It also provides new findings on how n- and p-MOSFETs respond differently to temperature-related stress, with n-MOSFETs showing less change in performance under these conditions, offering insights for improving SiC CMOS for extreme environment.

Fabrication Process

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

The fabrication of n - and p -channel MOSFETs was conducted at Analog Devices Inc., utilizing 6-inch epitaxially grown SiC wafers. The implanted channels were doped with nitrogen and aluminum at concentrations of and for n - and p -channels, respectively. A visual overview of the design is illustrated in Fig. 1. This study investigates three different gate oxide conditions: a standard thermally grown oxide and two CVD oxides, which were grown to thicknesses of 20 nm and 40 nm using ADI's established CVD method. Additionally, a 2 nm ultrathin thermal oxidation step was applied prior to the CVD process to enhance nucleation. More comprehensive details of the fabrication process are available in [9], [14].

Fig. 1. The cross-section of the n - and p -channel MOSFETs is selectively illustrated that relates to the key findings of this study. For a comprehensive view and detailed analysis of the full cross-section, refer to the documentation presented in [9].

Fig. 1. The cross-section of the n - and p -channel MOSFETs is selectively illustrated that relates to the key findings of this study. For a comprehensive view and detailed analysis of the full cross-section, refer to the documentation presented in [9].

Characterization Method

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

Oxide capacitances were extracted by driving the device into accumulation to determine the effective oxide thickness (EOT). For all transfer characteristics, was applied to drain while source and substrate was at 0 V . All devices have channel length and channel width to keep and avoid any geometry effect. The peak FE mobility was extracted using,

Where, drain current , gate to source voltage , drain to source voltage , oxide capacitance in accumulation per unit area (in ). To perform BTI characteristics, stress-sense-stress technique was used [11]. The threshold voltage was characterized using the intercept of maximum slope via linear extrapolation of vs characteristics [15]. In order to minimize the time between two "stress" stage the "current level" is chosen from the drain current at threshold voltage and voltage shift was observed to achieve that "current level" is considered as shift for BTI measurement. This setup enabled the application of very low voltage stress for a very short time to "sense" the threshold voltage shift after each "stress" step.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

Device Characteristics vs. Temperature. Fig. 2 illustrates the transfer characteristics of n - and p-channel MOSFETs with gate oxide formed using ultrathin thermal and thick CVD grown across a range of temperatures. As temperatures rise from room temperature ( ) to , there is a decrease in the threshold voltage, attributed to the enhanced thermal voltage ( ) which boosts the inversion charge density in the channel of both n - and p -MOSFETs [16]. FE mobility in SiC predominantly increases with temperature due to mobility predominantly limited by Coulombic scattering [9], [17]. Lattice damage during implantation, incomplete recovery after activation annealing, surface roughness and large density of traps at/near interface provide significant amount of scattering centers for charge carriers. Initially, field effect (FE) mobility increases with temperature. As the device characteristics are analyzed beyond this point, the influence of Coulombic scattering diminishes with increasing temperature, while phonon scattering becomes more prevalent, acting as main constraints on mobility at elevated temperatures. As a result, the mobility shows a downward trend for both n- and p-channel MOSFETs as temperatures rise, with the decline starting around for n-MOSFETs and for p-MOSFETs. The complex interplays of different scattering mechanisms shapes the device performances at different temperatures.

Fig. 2. Transfer characteristics of (a) n-channel and (b) p-channel MOSFETs with temperature ranging from to . Both MOSFETs have ultrathin thermal (UT) thick CVD grown .

Fig. 2. Transfer characteristics of (a) n-channel and (b) p-channel MOSFETs with temperature ranging from to . Both MOSFETs have ultrathin thermal (UT) thick CVD grown .

To gain a deeper understanding of how device mobility is influenced by temperature, the field effect (FE) mobility across different gate oxide conditions is extracted in Fig. 3. These conditions include a 50 nm thermal oxide, , and CVD . The measurement temperature was varied from to . The FE mobility was derived using Eq. 1 and subsequently normalized to the corresponding room temperature mobility value to ensure consistency in comparison.

The variance in temperature behavior between n - and p -MOSFETs can be largely attributed to the fundamental scattering mechanisms affecting carrier mobility [16]. As temperature rises, charge carriers gain kinetic energy, enhancing their ability to overcome the potential barriers of ionized impurities. This results in a reduced probability of carrier scattering by these impurities, thereby increasing the Coulombic scattering-limited mobility. However, alongside this increase, temperature also amplifies lattice vibrations within the semiconductor material, enhancing phonon scattering. Phonon scattering involves the interaction of charge carriers with the vibrating atoms of the lattice, which increases with temperature due to greater vibrational energy. As a consequence, phonon scattering becomes a significant limitation on mobility at higher temperatures, ultimately leading to the observed decrease in mobility as temperatures approach and exceed the transition point. From Matthiesen's rule,

where, and are coulombic scattering limited and phonon scattering limited mobility respectively. In SiC MOSFETs with as gate dielectric, the FE mobility is limited by coulombic scattering with being much less than . This is due to traps at interface [4]. With the increase in temperature, increases which gives rise to the effective mobility in Matthiesen's rule (Eq. 2). However, decreases with increase in temperature due to increased vibrational energy from higher temperature which eventually overturns the total mobility dependent solely on .

Fig. 3. Percentage change in FE mobility vs temperature for
(a) n-channel and (b) p-channel MOSFETs.

Fig. 3. Percentage change in FE mobility vs temperature for (a) n-channel and (b) p-channel MOSFETs.

For n-MOSFETs, there is a continuous increase in peak mobility up to a temperature of , at which point the mobility begins to decrease. This peak and subsequent decline mark a transition from mobility being primarily limited by Coulombic scattering to being limited by phonon scattering and the "transition point" indicates the temperature at which phonon interactions become sufficiently prominent to overshadow the effects of Coulombic scattering. For p-MOSFETs, however, this transition occurs at a significantly lower temperature of . This is due to the charge carriers (holes) in the p-MOSFETs have significantly heavier effective masses compared to the charge carriers (electrons) in n-MOSFETs [1]. The carriers with heavier effective mass have more energy at higher temperature to overcome the barrier for coulombic scattering centers which diminishes the effect of coulombic scattering quicker than lighter counterparts. Hence, the p-MOSFETs have lower
"transition" temperature compared to n-MOSFET. Furthermore, the mobility vs. temperature results for p-MOSFETs are very different for different gate oxide conditions compared to n-MOSFETs. The traps near conduction band are very much optimized over the last few decades with different annealing and POA while there is limited research on traps near valence band and the difficulty in extraction of traps near valence band. The difference in mobility change vs. temperature (Fig. 3 (b)) can be attributed to the differences in traps distribution near the valence band.

BTI vs. Temperature. BTI analysis is not only critical to diagnose the reliability and longevity of MOSFETs under combination of electrical and thermal stress but also provides crucial information about gate oxide quality and interface traps. A stress bias is applied at the gate while source, drain and substrate are grounded. The threshold voltage shifts due to injection of charges into the dielectric traps located at or near the oxide/semiconductor interface with different stress time. Positive and negative bias temperature instability measurements were conducted on both n - and p -channel MOSFETs. In order to contrast the results, the thermal oxide condition was characterized alongside the UT+CVD oxide condition. Fig. 4 shows the PBTI and NBTI shift of threshold voltages with stress and the temperature was varied from room temperature to .

Fig. 4. BTI characteristics of n - and p -MOSFETs at various temperature with DC stress. For each measurement, the "current level" was chosen before applying any stress at corresponding temperature.

Fig. 4. BTI characteristics of n - and p -MOSFETs at various temperature with DC stress. For each measurement, the "current level" was chosen before applying any stress at corresponding temperature.

In Fig. 4 (a) and (b), The PBTI shifts for both thermal and deposited oxides, respectively, indicate that both types of oxide are effectively optimized. The traps near the conduction band are passivated sufficiently to prevent substantial shift in the threshold voltage. As the temperature increases, the shift in also increases. Even though same gate bias was applied to stress the dielectrics, the reduction in threshold voltage at higher temperature causes an increase in the effective electric field. As a result, the shifts are slightly larger at higher temperature. The effective electric field can be extracted using the following equation-

where, Eeff is the electric field that acts on the oxide and EOT is the effective oxide thickness. The electric field applied at the gate has two-fold role in MOS structure; one part acting upon necessary band bending to form the channel which essentially is equal to whereas, the rest acts on the gate oxide. Few data points are off from the trend which indicates the charged mobile ion movement in gate oxide which can be ignored from the analysis. Nevertheless, the shift in Vth for both types of oxides is less than even with measurement temperature as high as .

In Fig. 4 (c) and (d), we observe significant threshold voltage shifts in p-MOSFETs under -25V bias stress across different temperatures, more so than in n-MOSFETs. Due to the higher initial threshold voltage in p-MOSFETs, configured by using the same poly-Si gate material and the presence of un-passivated interface traps near the valence band, the effective gate oxide electric field is much smaller compared to n-MOSFETs ( for thermal oxide and for deposited oxide). The pronounced shift in p-MOSFETs is linked to the un-passivated carbon clusters and oxygen vacancies at the interface [12]. Additionally, a secondary slope becomes evident more quickly at higher temperatures, indicating an accelerated activation of defect states, which impacts the NBTI behavior significantly.

The prolonged bias application could activate deep-level traps, resulting in a distinct secondary slope in BTI studies [9]. These BTI characteristics include an increase in interface trap density ( ), a reduction in field effect (FE) mobility, and a rise in threshold voltage, which notably do not revert even after the stress is removed. Higher temperatures increase band bending due to increased thermal voltage ( ) and facilitate the thermal generation of carriers. The band bending pushes more traps closer to the valence band at the gate oxide interface, which in turn activates additional deep-level traps under prolonged stress. Consequently, this process precipitates the emergence of the secondary slope earlier in the BTI timeline, thereby affirming the complex interplay among temperature, bias stress, and trap activation in p-MOSFETs. Since it has already established that thermal oxide has more traps near valence band compared to our novel deposited oxide, the secondary slope of thermal oxide starts at lower temperature than that of deposited oxide.

To complete our analysis, FE mobility was extracted following each BTI stress evaluation, with Fig. 5 demonstrating the percentage change in FE mobility in relation to its initial state. While nMOSFETs showed a negligible change in mobility ( ) at and up to across both oxide types, p-MOSFETs registered more substantial declines: for deposited oxides and for thermal oxides at the same temperature. This marked degradation in thermal oxides correlates with their earlier activation of secondary slopes and a higher presence of interface traps near the valence band. This further establishes the enhanced stability and efficiency of our newly developed deposited oxides over conventional thermal oxides.

Fig. 5. FE mobility degradation after BTI measurement at varied temperature for (a) n-MOSFET and (b) p-MOSFET with thermal and deposited oxides.

Fig. 5. FE mobility degradation after BTI measurement at varied temperature for (a) n-MOSFET and (b) p-MOSFET with thermal and deposited oxides.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

In this study, n- and p-MOSFETs fabricated on 6 -inch wafers demonstrated distinct behaviors across different gate oxide conditions, from room temperature up to . Devices with ultrathin thermal combined with CVD exhibited superior field effect mobility and stability compared to those with traditional thermal oxides, particularly under high-temperature conditions. Bias temperature instability (BTI) tests revealed minimal threshold voltage shifts for n-MOSFETs under extreme thermal stress, highlighting their durability, whereas p-MOSFETs faced significant permanent threshold voltage shifts and mobility reductions above , pointing to un-passivated deep level traps within the bandgap near the valence band. These findings suggest the necessity for enhanced passivation strategies, particularly near the valence band, to improve the performance and reliability of SiC MOSFETs, and demonstrate that deposited oxide stacks offer a more reliable alternative to traditional thermal oxides for high temperature applications.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

The work was funded by Advanced Research Projects Agency-Energy (ARPA-E) U.S. Department of energy, under Award Number DE-AR0001028

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.57.pdf

W. J. Choyke and G. Pensl, "Physical Properties of SiC," MRS Bull., vol. 22, no. 3, pp. 25-29, Mar. 1997, doi: 10.1557/S0883769400032723.

R. R. Siergiej et al., "Advances in SiC materials and devices: an industrial point of view," Mater. Sci. Eng. B, vol. 61-62, pp. 9-17, Jul. 1999, doi: 10.1016/S0921-5107(98)00438-3.

M. Alexandru et al., "SiC Integrated Circuit Control Electronics for High-Temperature Operation," IEEE Trans. Ind. Electron., vol. 62, no. 5, pp. 3182-3191, May 2015, doi: 10.1109/TIE.2014.2379212.

G. Pensl et al., "Traps at the SiC/SiO2-Interface," MRS Online Proc. Libr. OPL, vol. 640, p. H3.2, Jan. 2000, doi: 10.1557/PROC-640-H3.2.

V. V. Afanas'ev, "Electronic properties of SiO 2 SiC interfaces," Microelectron. Eng., vol. 48, no. 1, pp. 241-248, Sep. 1999, doi: 10.1016/S0167-9317(99)00379-2.

E. Pippel, J. Woltersdorf, H. Ö. Ólafsson, and E. Ö. Sveinbjörnsson, "Interfaces between 4HSiC and SiO 2 : Microstructure, nanochemistry, and near-interface traps,"J. Appl. Phys., vol. 97, no. 3, p. 034302, Dec. 2004, doi: 10.1063/1.1836004.

D. J. Lichtenwalner et al., "Accelerated Testing of SiC Power Devices," in 2020 IEEE International Integrated Reliability Workshop (IIRW), Oct. 2020, pp. 1-6. doi: 10.1109/IIRW49815.2020.9312873.

A. Christou, Reliability of High Temperature Electronics. RIAC, 1996.

E. K. Ashik et al., "Bias Temperature Instability on SiC n- and p-MOSFETs for High Temperature CMOS Applications," in 2022 IEEE International Reliability Physics Symposium (IRPS), Mar. 2022, p. 3B.4-1-3B.4-8. doi: 10.1109/IRPS48227.2022.9764565.

A. J. Lelis, R. Green, D. B. Habersat, and M. El, "Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs," IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 316-323, Feb. 2015, doi: 10.1109/TED.2014.2356172.

R. Green, A. Lelis, and D. Habersat, "Threshold-voltage bias-temperature instability in commercially-available SiC MOSFETs," Jpn. J. Appl. Phys., vol. 55, no. 4S, p. 04EA03, Mar. 2016, doi: 10.7567/JJAP.55.04EA03.

R. W. Kee, K. M. Geib, C. W. Wilmsen, and D. K. Ferry, "Interface characteristics of thermal Si02 on SiC," J. Vac. Sci. Technol., vol. 15, no. 4, pp. 1520-1523, Jul. 1978, doi: 10.1116/1.569779.

T. E. Rudenko, I. N. Osiyuk, I. P. Tyagulski, H. Ö. Ólafsson, and E. Ö. Sveinbjörnsson, "Interface trap properties of thermally oxidized n-type and ," Solid-State Electron., vol. 49, no. 4, pp. 545-553, Apr. 2005, doi: 10.1016/j.sse.2004.12.006.

S. B. Isukapati et al., "Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology," in 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2021, pp. 267-270. doi: 10.23919/ISPSD50666.2021.9452235.

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Y. Tsividis, Operation and Modeling of the Mos Transistor (The Oxford Series in Electrical and Computer Engineering). USA: Oxford University Press, Inc., 2004.

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Chapter 2

Quantum Applications, Sensors and Use in Space Engineering

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 67-72

doi: 10.4028/p-qsEbu9

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-01

Accepted:
2025-08-04

Online:
2025-09-12

SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

The original version of this paper is available on https://www.scientific.net/KEM.1024.67.pdf

Daniel Habersat , Anand Sampath , Greg Garrett , Michael Derenge , Franklin Nouketcha , Brenda VanMil , Michael Wraback , Jonathan Schuster , Jeremy Smith , Enrico Bellotti , Mike Zhu , Reza Ghandi , and Mehrnegar Aghayan

DEVCOM Army Research Laboratory, 2800 Powder Mill Road, Adelphi, MD 20783 USA

Boston University, Department of ECE, 8 St. Mary's Street, Boston, MA 02215, USA

GE Aerospace Research, 1 Research Circle, Niskayuna, NY 12309, USA

daniel.b.habersat.civ@army.mil, anand.v.sampath.civ@army.mil, gregory.a.garrett.civ@army.mil, michael.a.derenge.civ@army.mil, michael.wraback.civ@army.mil, hjonathan.schuster2.civ@army.mil, ijeremy.l.smith135.ctr@army.mil, jbellotti@bu.edu, kmjzhu@bu.edu, 'ghandi@ge.com, mMehrnegar.Aghayan@ge.com

Keywords: avalanche, photodiode, spatial uniformity, single photon, UV detector

Abstract

We are investigating avalanche photodiodes for use as solar-blind, single-photon UV detectors, which could enable low cost, size, weight, and power devices that are reliable and robust, suitable for many sensing applications. One concern for these devices is the spatiallynonuniform gain which limits the useful device area and impedes the scaling necessary to compete with leading UV sensor architectures. We examined various potential sources of the nonuniformity, and conclude that the typically observed phenomenon is likely caused by impact ionization anisotropy and the wafer offcut angle needed to maintain a consistent polytype during epitaxial growth. Additionally, we present both linear and Geiger-mode spatial maps on the same devices to explain the observed differences in each.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.67.pdf

SiC is attractive for UV single-photon avalanche detectors (SPADs) as it is inherently blind to visible light, and photon counting (i.e., Geiger mode) as well as high-gain linear-mode devices have been demonstrated [1,2]. However, issues remain regarding bias-dependent spatial uniformity of detection efficiency (DE) and responsivity [3, 4, 5]. Specifically, Guo et al. [3] observed increasing spatial non-uniformity with gain in 4 H SiC APDs in linear-mode operation for gain below 10,000. In contrast, Cai et al. [4] observed that the Geiger-mode spatial nonuniformity of SiC avalanche photodiodes (APDs) was poor at low excess bias but improved with increasing bias, which was attributed to anisotropy in impact ionization and asymmetric bevel angles (the latter caused by process variation and the miscut of the substrate). Li et al. [5] showed that the direction of the spatial nonuniformity flipped when comparing pin and nip diodes, and argued that impact ionization alone was the cause.

In this paper, we examine the spatial uniformity of the response of operating in both linear and Geiger-modes by spatial mapping, unifying the behaviors observed in the two regimes. We also provide a cleaner view of the anisotropy through the use of pill-shaped devices, and rule out wafer-level variations like i-layer thickness and doping. Finally, initial results from full-band Monte Carlo modeling confirm that the substrate offcut angle is responsible asymmetric spikes in the gain for carriers generated at the edges of the device along the projection of [1120] onto the device plane.

Experimental Details

The original version of this paper is available on https://www.scientific.net/KEM.1024.67.pdf

The basic structure used in this study was fabricated on commercially-available wafers with a -offcut angle, in a p-illuminated, pin configuration using the epitaxial layers indicated in Fig. 1. To form the device structure, we used a photoresist-reflow etching process to create a negative bevel of . Thermally-deposited and densified was used as a passivation layer and to isolate the bonding pads. After etching an optical window at the top of each mesa, ohmic contacts were formed along with a 300 nm layer of which served as an anti-reflective coating. Most devices Prwere circular mesas with a diameter at the base and ring contacts at the top and bottom, an example of which is shown in Fig. 2.

Once diced, individual devices were packaged onto TO-5 headers and capped with an open lid to allow UV transmission. These packages were then mounted to a socket on our custom measurement apparatus, shown in Fig. 3. The output of a pulsed UV LED operating at 285 nm was filtered and shaped to form a beam with a waist of . A moving stage with precision stepper motors was used to move the device along the focal plane. The photon flux is controlled by varying the pulse trigger frequency and a selectable neutral-density filter; a beam block can also be selected to allow in situ dark measurements. Optical power is calibrated by using a Si photodetector at high power levels, and a Cs-Te photocathode PMT for low power and single-counting modes. Custom printed circuit boards allow the system to be easily configured to measure either linear-mode current or Geigermode counts (the latter using a passive-quenching circuit). An external bias supply controls the operation of the APD. Photocurrent or counts are measured as a function of photon flux, bias, and position and used to generate spatial maps of responsivity and detection efficiency.

Fig. 1. Vertical structure of the avalanche photodiode.

Fig. 1. Vertical structure of the avalanche photodiode.

Fig. 2. Optical image of an example SiC
APD.

Fig. 3. Diagram of the setup used to locally illuminate a spot on the device and spatially profile photoresponse.

Fig. 4 shows a series of measured spatial maps of the responsivity (operating in linear mode) of a avalanche photodiode from unity-gain up to a dark current of (where average gain is ). A high optical power ( ) was used to ensure plenty of photosignal. The maps have all been oriented so that [1120] is parallel to the horizontal axis and [1100] is parallel to the vertical axis (i.e., if one were looking into the Si -face of the wafer, the primary wafer flat would be at the bottom). With each map, measurements of the dark current and its standard deviation are made using a beam block-the grey-shaded areas on each map are where the measured signal was noise limited. (The blue areas on the right of Figs. 4a-c are some residual current decay caused by movement of the stage as it rasters back after each line scan, and are only slightly larger than the dark current noise.)

The unity-gain responsivity in Fig. 4a equals an external quantum efficiency of and is highly uniform across the optical window at the top of the mesa. The inner white ring is the location of the top ohmic contact, while the outer ring marks the edge of the mesa bevel. While uniform response is observed at unity-gain, even by Fig. 4b where the gain is less than , the responsivity is found to become increasingly non-uniform with increasing gain and characterized by localized hot-spots with values more than 10x greater than the average.

This device began to avalanche at 153.1 V , corresponding to the map at 10 nA in Fig. 4e for linear mode. The series of Geiger-mode maps, shown in Fig. 5, start here as well where dark carriers start generating detectable counts. The position and orientation of the device in these maps is the same as for the linear mode maps. However, the optical power has been reduced to 100 fW and a flux of . A neutral density filter with an optical density of 2.0 is used to lower the probability of coincident photons to less than , ensuring single-photon counting statistics.

As expected, the two "hotspots" that formed in the upper- and lower-right sides of the linear-mode maps correspond to the exact locations where photocounts are first generated in Geiger mode, since both effects would be attributed to regions of high field. Unlike the linear-mode map, however, as the dark count rate (via more excess bias) is increased, uniformity improves since the avalanche probability cannot go above . Our passive quench circuit has a "reset" time of about , and so the dead time in the circuit begins to represent an increasing portion of the sampling time as the total count rate goes above , meaning the peak detection efficiency of is likely too low.

Fig. 4. Linear-mode responsivity maps for 285 nm at dark currents of a) (unity), b) 10 pA , c) , and f) . The maps are oriented so that the horizontal axis is along [1120] and the vertical axis is along [1100].

Fig. 4. Linear-mode responsivity maps for 285 nm at dark currents of a) (unity), b) 10 pA , c) , and f) . The maps are oriented so that the horizontal axis is along [1120] and the vertical axis is along [1100].

Fig. 5. Geiger-mode single-photon detection efficiency maps for 285 nm at dark-count rates of: a) , and f) 100 kHz . The photon flux rate was 155 kHz with a photon emission probability per trigger pulse to minimize generation of coincident photons.

Fig. 5. Geiger-mode single-photon detection efficiency maps for 285 nm at dark-count rates of: a) , and f) 100 kHz . The photon flux rate was 155 kHz with a photon emission probability per trigger pulse to minimize generation of coincident photons.

The spatial maps, responsivity in particular, show that there is a strong variation along [1120] but hint at uniformity in the perpendicular [1100] direction. To that end, we fabricated high aspect-ratio devices whose edges are aligned with the crystal axes, and produced devices in both parallel and perpendicular orientations. The device images and maps of linear responsivity in Fig. 6 are presented in the same orientation as our earlier data with respect to the crystal axis, although these devices are n-illuminated and therefore the direction of the spatial gradient has reversed. As before, both devices were completely uniform at unity-gain. Even when a long mesa edge is perpendicular to [1120], a high degree of uniformity is maintained along [1100] with large gain. Likewise, at least to the scale of this device, the nonuniformity effect along [1120] does not appear to saturate.

Fig. 6. Optical image (a) and responsivity map at moderate gain (b) of a "vertical" device, along with corresponding optical image (c) and responsivity map (d) of a "horizontal" device.

Fig. 6. Optical image (a) and responsivity map at moderate gain (b) of a "vertical" device, along with corresponding optical image (c) and responsivity map (d) of a "horizontal" device.

Numerical modeling was employed to examine the impact of two potential causes for spatial nonuniformity of the response - (1) epitaxial variation in the multiplication (drift) region of the diode, and (2) anisotropy of impact ionization and the miscut of the substrate. The photocurrent in 4H-SiC APDs was calculated for varying multiplication layer thickness using Synopsys TCAD Sentaurus in which the finite element method is

Fig. 7. TCAD simulations of QE-Gain product versus multiplication-layer thickness deviation for various biases near avalanche breakdown.

Fig. 7. TCAD simulations of QE-Gain product versus multiplication-layer thickness deviation for various biases near avalanche breakdown.

the gain by approximately half an order of magnitude, which is qualitatively similar to trends measured in real devices. Here it is important to note that a variation in i-layer thickness over the scale of a device is comparable to the relative variation expected across a 100 mm wafer.

However, such a thickness or doping variation due to the epitaxial growth would likely have a random or radial orientation [6] which can be detected in the nonuniformity of photoresponse. We measured the responsivity maps at moderate gain for devices in different quadrants of the same wafer-shown in Fig. 8. In each case, the nonuniformity remained aligned with the [1120] direction, suggesting that any localized variations of doping or thickness were not responsible for the phenomenon.

Fig. 8. Responsivity maps (a,c) and wafer location schematic
(b) of two devices from different quadrants of a SiC wafer.

Fig. 8. Responsivity maps (a,c) and wafer location schematic (b) of two devices from different quadrants of a SiC wafer.

Finally, full-band 3D Monte Carlo calculations [7, 8] were utilized to study the influence of anisotropic impact ionization, comparing devices fabricated on-axis and with a miscut. Fig. 9 plots the calculated gain in a APD that is oriented with c-axis (blue) and tilted due to a wafer miscut (red). Calculations show that while the gain in the c -axis oriented device is symmetric across the wafer, the tilted device shows strongly enhanced gain on one side and reduced gain on the opposite side. These results are attributed to the anisotropy in impact ionization in [0001] and [1120] directions and consistent with experimental data.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1024.67.pdf

We performed a comprehensive study of the nonuniform gain in SiC APDs, as evidenced by changes in responsivity. Our data provides the first direct comparison of linear and Geiger mode maps, showing that the same features appear in both. By measuring devices with different orientations and at different locations on a wafer, we feel confident in concluding (as others have recently done [5]) that the impact ionization anisotropy present between [0001] and [1120] is the primary cause. Initial full-band Monte Carlo simulations match our experimental data and conclusions. At the same time, we cannot rule out influences by variations in the bevel angle when using shallow-angle bevels for suppression of the edge fields [4], which tend to be very sensitive to small changes in the angle achieved [9].

Fig. 9. Monte Carlo-simulated electric field (top) and gain versus lateral position (bottom) for tilted and untilted devices.

Fig. 9. Monte Carlo-simulated electric field (top) and gain versus lateral position (bottom) for tilted and untilted devices.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.67.pdf

X. Bai, H.D. Liu, D.C. McIntosh, J.C. Campbell, High-Detectivity and High-Single-Photon-Detection-Efficiency 4H-SiC Avalanche Photodiodes, IEEE Journal of Quantum Electronics, 45 (2009) 300-303, https://doi.org/10.1109/JQE.2009.2013093.

X. Zhou, T. Han, Y. Lv, J. Li, W. Lu, Y. Wang, et al., Large-Area 4H-SiC Ultraviolet Avalanche Photodiodes Based on Variable-Temperature Reflow Technique, IEEE Electron Device Letters, 39 (2018) 1724-1727, .

X. Guo, A.L. Beck, X. Li, J.C. Campbell, D. Emerson, J. Sumakeris, Study of reverse dark current in avalanche photodiodes, IEEE Journal of Quantum Electronics, 41 (2005) 562-567, .

X.L. Cai, C.F. Wu, H. Lu, Y.F. Chen, D. Zhou, F. Liu, et al., Single Photon Counting Spatial Uniformity of 4H-SiC APD Characterized by SNOM-Based Mapping System, IEEE Photonic Tech L, 29 (2017) 1603-1606, .

T. Li, Y. Zhou, X. Tao, W. Xu, D. Zhou, F. Ren, et al., Study of Gain Spatial Nonuniformity in n-on-p and p-on-n 4H-SiC Avalanche Photodiodes, IEEE Photonic Tech L, 36 (2024) 465-468, .

M.F. MacMillan, T. Oldham, V. Rengarajan, P. Wu, Improved Uniformity of Silicon Carbide Epitaxy Grown in a High-Volume Multi-Cassette Epitaxy Reactor, Mater. Sci. Forum, 924 (2018) 92-95, .

I. Prigozhin, S. Dominici, E. Bellotti, FBMC3D--A Large-Scale 3-D Monte Carlo Simulation Tool for Modern Electronic Devices, IEEE Transactions on Electron Devices, (2020) 1-9, .

M. Zhu, F. Bertazzi, M. Matsubara, E. Bellotti, Quantum mechanical model of crossing and anti-crossing points in 3D full-band Monte Carlo simulations, J. Appl. Phys., 135 (2024), .

B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer US, Boston, MA, 2008.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 73-77

doi: 10.4028/p-hpc4bI

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-12

Revised:
2025-05-12

Accepted:
2025-05-12

Online:
2025-09-12

Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

The original version of this paper is available on https://www.scientific.net/KEM.1024.73.pdf

Kasif Teker , Mustafa A. Yildirim , and Tarik U. Teker

Faculty of Engineering, Bogazici University, Istanbul, Turkey

School of Engineering, University of Warwick, Coventry, UK

College of Engineering, Virginia Tech, Blacksburg, VA, USA

kasif.teker@bogazici.edu.tr, mustafa.yildirim@warwick.ac.uk,

Keywords: Self-powered photodetectors, Au nanoparticles, Plasmonics, Sustainable devices

Abstract

This study presents a systematic investigation into the influence of gold nanoparticles on the performance of a self-powered metal-semiconductor-metal (MSM) 4H-SiC UV photodetector (SiC-UVPD), with a focus on the nonsymmetric contact phenomenon arising from differences in the contact areas of the gold electrode pair under 254 nm UV light exposure. The self-powered SiC-UVPD device exhibited a very good sensitivity of , great responsivity of , and excellent detectivity of under 254 nm UV light without any external power. In fact, the specific detectivity of the self-powered SiC-UVPD improved by following the application of Au nanoparticles. Self-powered photodetectors are desirable devices for green energy applications due to their unique advantages such as smaller footprints and wireless operation.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.73.pdf

Ultraviolet photodetectors (UVPD) attract great attention in optical communications, pharmaceutical and chemical analysis, environmental sensing, flame detection, biomedical electronics, missile detection, and space communications [1]. Photodetectors capable of operating without any external power source can solve the energy requirement along with simplifying and reducing the cost of overall device fabrication. Conventional photodetectors need external power sources to operate, which is not desirable for smart sensor systems and devices. However, selfpowered photodetectors can harvest energy from the environment enabling small, portable, costeffective, and multifunctional devices for future optoelectronic applications [2-4]. Therefore, improving the performance of these devices has become very crucial for the fabrication of efficient, sustainable, energy and environment friendly devices.

Wide bandgap semiconductors (WBG) such as GaN [5], SiC [6], [7], and AlN [8] are good candidate materials to construct UV photodetectors due to their excellent mechanical, chemical and thermal stability, and radiation resistance. Among these WBGs, is a very good candidate for constructing UV photodetectors capable of operating at high temperature, high frequency, and high radiation conditions [9] owing to the superior physical properties with a large bandgap energy ( 3.26 eV ), high electron drift velocity ( ), and high thermal conductivity ( ).

One effective technique to enhance the photodetection capabilities of photodetectors is by functionalizing the surface of a semiconductor with metal nanoparticles. These nanoparticles can improve the scattering of incident photons and increase optical absorption around each particle in the active region of the semiconductor, thereby enhancing the overall performance of the photodetector. Furthermore, when metal nanoparticles on the surface of a semiconductor interact with UV light, they can generate localized surface plasmons. These plasmons produce a large number of photoexcited electrons, which can be transferred into the semiconductor, resulting in an increased photocurrent under UV light exposure. Among various metal nanoparticles, gold nanoparticles receive particular attention due to their excellent chemical stability, ease of synthesis, and high density of easily polarizable conduction electrons. These properties enable strong interactions with electromagnetic fields and facilitate the generation of nonlinear optical phenomena [10]. This study presents a systematic investigation into the influence of gold nanoparticles on the performance of a self-powered

MSM 4H-SiC UV photodetector, focusing on the nonsymmetric contact phenomenon arising from differences in the contact areas of the gold electrode pair under 254 nm UV light exposure.

Experimental Details

The original version of this paper is available on https://www.scientific.net/KEM.1024.73.pdf

SiC-UVPD was fabricated via a highly practical and cost-effective fabrication scheme. The photodetector was constructed on a small piece ( ) of n-type 4H-SiC wafer with a resistivity of ohm.cm. A physical mask and a sputter coater system were used to deposit nonsymmetrical gold electrodes with a gap spacing of and length of 2 mm . The same gold electrode pair was used for all the measurements. The size of the small Au electrode was about half of the large Au electrode. To investigate the influence of gold nanoparticles on the performance of the photodetector, the surface of the fabricated SiC-UVPD was coated with Au for , and 20 s deposition times. Following each Au thin film deposition step, the SiC-UVPD was heated at for five minutes to transform the deposited Au film into nanoparticles. No anti-reflection coating was used in this study. The surface morphology of the fabricated SiC-UVPD and Au-NPs were investigated via scanning electron microscopy. A sourcemeter (Keithley 2634B), which is attached to a probe station and controlled with a Labview program was used to carry out the electrical measurements at room temperature. A UV lamp (UVP-UVLMS 38) with a power density of and a wavelength of 254 nm was used.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1024.73.pdf

Fig. 1 shows a scanning electron microscopy image of the Au nanoparticles on the SiC-UVPD surface and a schematic diagram of the measurement setup of the self-powered SiC-UVPD. The size of the Au nanoparticles ranges from 30 nm to 40 nm for 15 s and 20 s deposition times, respectively.

Fig. 1. A scanning electron microscopy image of the Au nanoparticles on the SiC-UVPD (scale bar is ); and a schematic diagram of the measurement setup of the self-powered SiC-UVPD.

Fig. 1. A scanning electron microscopy image of the Au nanoparticles on the SiC-UVPD (scale bar is ); and a schematic diagram of the measurement setup of the self-powered SiC-UVPD.

The surface density of gold nanoparticles (Au-NPs in the active area divided by the total active area of the SiC-UVPD) was calculated to be about and for the SiC-UVPD-Au15s and SiC-UVPD-Au20s devices, respectively. The size and distribution of the gold nanoparticles after each deposition/heating step were found to be quite uniform. The number and areas of the Au nanoparticles- assuming each nanoparticle to be circular- were calculated. The areal coverage of the Au nanoparticles was then divided by the total gap area of the device.

To evaluate performance characteristics of the SiC-UVPD, current-time (I-t) measurements were performed through 20 -s multiple cycles under the UV light at 0 V through a sourcemeter. Fig. 2 displays the I-t plots of the SiC-UVPD following the applications of Au nanoparticles with different surface densities (from 5 -s to 20 -s Au deposition) at 0 V , revealing strong enhancements in photocurrent. In fact, the Ion/Ioff ratio gradually increases with the increase of Au deposition time reaching to a maximum on/off current ratio of 934 with 15 -s Au deposition under 254 nm of UV light. However, a slight decrease on the Ion/Ioff ratio (870) is observed with 20-s Au deposition under 254 nm UV light. Moreover, the SiC-UVPD exhibited a very good sensitivity of . Furthermore, responsivity, which can be described as the ratio of photocurrent from a photodetector to an incident optical power, is expressed by, Ion - Ioff , where A is the active area of the photodetector and Plight is the power intensity of incident light. The responsivity of the selfpowered SiC-UVPD is without any Au NPs, while the responsivity increases to with the SiC-UVPD-Au15s under 254 nm UV light.

Fig. 2. I-t plots of the SiC-UVPD following the applications of Au nanoparticles with different surface densities (from 5-s to 20-s Au deposition) under 254 nm UV light exposure at 0 V .

Fig. 2. I-t plots of the SiC-UVPD following the applications of Au nanoparticles with different surface densities (from 5-s to 20-s Au deposition) under 254 nm UV light exposure at 0 V .

Specific detectivity (D*) is described as the ability of a photodetector to detect small optical signals. As the detectivity increases, the capability of the device to sense smaller optical signals increases as well. The specific detectivity is expressed by, , where is the responsivity, is the effective exposed area, is the electronic charge, and Ioff is the dark current. The specific detectivity of the plain SiC-UVPD is under the UV light exposure. Moreover, the detectivity of the self-powered SiC-UVPD improved by following the application of Au nanoparticles reaching to Jones. Table 1 summarizes some of the performance parameters of the self-powered SiC-UVPD under 254 nm UV light. It is worth noting that a slight decrease in the performance of the SiC-UVPD was observed with 20 s Au deposition under 254 nm UV light. This performance decline can be attributed to the increased surface coverage of the SiC with Au nanoparticles at this deposition duration. A similar trend was reported for a ZnO photodetector coated with Pt nanoparticles, where longer Pt deposition times ( 50 s ) led to a decrease in the device performance [11].

Table 1. A summary of some performance parameters of the self-powered SiC-UVPD including on/off current ratios, sensitivity, responsivity, and specific detectivity under the UV light exposure.

Au Deposition time (s) | On/off current ratio | Sensitivity (%) | Responsivity (A/W) | Detectivity (cm.Hz1/2.W⁻¹)
No Au NPs | 551.40 | 5.50 × 10⁴ | 0.18 | 4.12 × 10¹¹
5 | 761.57 | 7.61 × 10⁴ | 0.25 | 5.70 × 10¹¹
10 | 845.29 | 8.44 × 10⁴ | 0.27 | 6.33 × 10¹¹
15 | 934.71 | 9.34 × 10⁴ | 0.30 | 7.00 × 10¹¹
20 | 869.74 | 8.69 × 10⁴ | 0.28 | 6.51 × 10¹¹

Here, it is important to provide an explanation for the self-powering mechanism of the MSM SiCUVPD device. The traditional MSM photodetectors with two symmetric back-to-back Schottky contacts on a planar surface require an external power source to generate photocurrent. In fact, MSM devices fabricated with two different electrode materials (one ohmic and one Schottky contact) can operate without any external power. Nevertheless, these MSM devices suffer from poor performance and complex fabrication steps. These drawbacks can be overcome by using nonsymmetric pair of planar electrodes with different contact areas enabling efficient separation of the photogenerated carriers due to a difference in electric field built in each Schottky junction [12]. As a result, the difference in Schottky barrier heights between the two junctions without any applied bias voltage under the UV light exposure leads to a substantial photocurrent from the device. In brief, combined with the practical and cost-effective fabrication, the self-powered SiC-UVPD can lead the path towards novel, high performance, emerging sustainable energy, and eco-friendly optoelectronic devices particularly for harsh environments.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1024.73.pdf

We have successfully demonstrated substantial performance improvement of the self-powered SiC-UVPD device through the applications of Au nanoparticles with varying surface densities. The fabricated SiC-UVPD exhibited a very good sensitivity of , great responsivity of , and excellent detectivity of under 254 nm UV light without any external power with the Au deposition time of 15 s . However, a slight decrease in the performance of the SiC UVPD was observed with 20 s Au deposition under 254 nm UV light, which can be attributed to the excessive surface coverage of the SiC surface with Au nanoparticles. In consequence, the presented SiC photodetector could offer great alternatives to produce next-generation self-powered, sustainable, environment-friendly optoelectronic devices capable of operating in harsh environment conditions with minimal maintenance.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.73.pdf

H. Chen, K. Liu, L. Hu, A. Al-Ghamdi, X. Fang, New concept ultraviolet photodetectors, Mater. Today. 18 (2015) 493.

M.A. Yildirim, K. Teker, Self-powered silicon carbide ultraviolet photodetector via gold nanoparticle plasmons for sustainable optoelectronic applications, Physica Scripta 97 (2022) 115804.

L. Su, W. Yang, J. Cai, H. Chen, X. Fang, Self-powered ultraviolet photodetectors driven by built-in electric field, Small 13 (2017) 1701687.

T. Kim, Y. Ko, C. Yoo, B. Choi, S. Han, N. Kim, Design optimisation of wide-band piezoelectric energy harvesters for self-powered devices, Energ. Convers. Manage. 225 (2020) 113443.

T.U. Teker, K. Teker, Enhanced Photoresponse of a Self-Powered Gallium Nitride Photodetector via Sequentially-Deposited Gold Nanoparticles for Sustainable Optoelectronics, J. Electron. Mater. 52 (2023) 2372-2379.

H. Mousa, M.A. Yildirim, K. Teker, Performance enhancement of 3C-SiC thin film UV photodetector via gold nanoparticles, Semicond. Sci. Tech. 34 (2019) 095002.

A.S. Pratiyush, S. Krishnamoorthy, R. Muralidharan, S. Rajan, D.N. Nath, Advances in solar-blind UV photodetectors, Elsevier 2018.

Y. Ali, K. Teker, Fabrication of Ultraviolet Photodetector with Aluminum Nitride Nanowire Networks via Direct Transfer Method, Microelectronic Engineering 211 (2019) 26-28.

T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology, Wiley-IEEE Press 2014.

V. Amendola, R. Pilot, M. Frasconi, O. M. Maragò, M. A. Iatì, Surface plasmon resonance in gold nanoparticles: a review, J. Phys-Condens. Mat. 29 (2017) 203002.

C. Tian, D. Jiang, B. Li, J. Lin, Y. Zhao, W. Yuan, J. Zhao, Q. Liang, S. Gao, J. Hou, J. Qin, Performance enhancement of ZnO UV photodetectors by surface plasmons, ACS Appl. Mater. Interfaces 6 (2014) 2162-2166.

H.-Y. Chen, K.-W. Liu, X. Chen, Z.-Z. Zhang, M.-M. Fan, M.-M. Jiang, X.-H. Xie, H.-F. Zhao, D.-Z. Shen, Realization of a self-powered ZnO MSM UV photodetector with high responsivity using an asymmetric pair of Au electrodes, J. Mater. Chem. C. 2 (2014) 9689.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 79-86

doi: 10.4028/p-0t5ifB

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-27

Accepted:
2025-08-27

Online:
2025-09-12

Fabrication of -SiC Low Gain Avalanche Detectors (LGADs)

The original version of this paper is available on https://www.scientific.net/KEM.1024.79.pdf

Ben J. Sekely , Yashas Satapathy , Tao Yang , Greg Allion , Philip Barletta , Steve Holland , Stefania Stucci , Carl Haber , Spyridon Pavlidis , John F. Muth

¹Department of Materials Science and Engineering, North Carolina State University, Engineering Bldg I, 911 Partners Way, Raleigh, 27606, NC, U.S

Department of Electrical and Computer Engineering, North Carolina State University, 2410 Campus Shore Dr, Raleigh, 27606, NC, U.S

Physics Division, Lawrence Berkeley National Laboratory, 1 Cyclotron Rd, Berkeley 94720, CA, U.S

NCSU Nanofabrication Facility, North Carolina State University, 2410 Campus Shore Dr, Raleigh, 27606, NC, U.S

Brookhaven National Laboratory, 98 Rochester St, Upton, 11973, NY, U.S

seholland@lbl.gov, stucci@bnl.gov, chhaber@lbl.gov, spavlidis@ncsu.edu, muth@ncsu.edu

Keywords: LGAD, PiN Diode, Particle Detection, High Energy Physics, Radiation.

Abstract

Low gain avalanche detectors (LGADs) offer high temporal resolution for high energy particle detection, which is critical for next generation experiments in hadron colliders. While silicon LGADs (Si-LGADs) have rapidly matured in the last decade, research into silicon carbide (SiC) LGADs has only recently begun. By accounting for fundamental differences in material properties and fabrication processes, we present a prototype device design and process flow for LGADs with etch-based isolation. Critical steps of the process flow and their results are discussed, including plasma etching, passivation, and the formation of low resistivity contacts. Electrical characterization (I-V, C-V) shows sufficient depletion of the device structure to demonstrate low-gain charge carrier multiplication.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.79.pdf

In high energy hadron colliders, such as the High Luminosity Large Hadron Collider (HL-LHC), and possible future colliders, events contain increasingly large numbers of minimum ionizing particles (MIPs), with significant overlap of many simultaneous collisions in close proximity. Present tracking systems, based upon highly segmented silicon pixels or strips lack the timing resolution required to separate these events. Next generation collider detectors, now in preparation, will contain new fast timing devices, referred to as Silicon Low Gain Avalanche Detectors (Si-LGADs) with timing resolution in the range , but with limited spatial resolution. Si-LGADs offer better time resolution than current pixels and strips. This is due to thinner drift regions allowing charge carriers to quickly travel across the device and signal amplification through the use of an avalanche mechanism [1].

Si-based detectors are however susceptible to bulk radiation damage effects and consequently must be operated at temperatures around requiring complex, bulky, and expensive cooling systems.

The 2019 Department of Energy Basic Research Needs for High Energy Physics Detector R&D identified a number of priority research directions including improved spatial resolution for fast timing, the application of new alternative materials, and reduced cooling and mass requirements [2]. In the present work we are developing LGADs to address these directions by using rather than Si .

There are several reasons to adopt 4 H silicon carbide in place of Si in LGADs. Firstly, the ionization coefficient of holes exceeds that of electrons in SiC , unlike in Si . This, combined with the fact that the saturation velocity of electrons in SiC is over twice that of holes in silicon, means that a SiC LGAD structure should be constructed with n-type drift and gain layers. Consequently, the fast signal comes from the higher mobility avalanche electron drifting back across an n -type epitaxial layer, rather than slower hole drifting across a p-type layer in the case of a Si LGAD. Additionally, the wider band gap and greater atomic displacement energy threshold of are expected to reduced the dark current and lead to a higher theoretical radiation resistance, respectively [3,4]. Moreover, the larger thermal conductivity of SiC can simplify cooling requirements and reduce system complexity. is also of interest due to its high technological maturity and large commercial availability. For all of these reasons, is an attractive polytype choice for LGAD device development.

In the following, we describe the epitaxial design and development of first generation SiC LGADs for particle detectors. Each of the fabrication steps has been characterized. The resulting LGADs and associated test structures have been electrically tested to confirm they adhere to our expectations. We note that -particle irradiation with a source using the same devices is not presented here, butm treated in a separate publication [5].

Epitaxial Design and Characterization

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These stacks were purchased as 6 " wafers from a commercial vendor with a off-axis cut. The epi-stack shown in Fig. 1 is designed to collect holes at the front-side p-type contact layer. Thicknesses and doping concentrations were determined using Synopsys TCAD simulations with the following considerations:

The nitrogen-doped ( N -doped) n-type drift region is as low doped as possible to decrease the depletion voltage and therefore operating voltage, allowing for reduced scattering of mobile charge carriers and a better timing performance. The concentration is the minimum dopant concentration that could be commercially achieved. The drift layer thickness requires a balance: a thin region achieves a better timing resolution as the carriers travel shorter distances but reduces the MIP interaction volume and generates fewer carriers, requiring a higher gain to achieve a higher signal-to-noise ratio and be read by the read-out electronics.

The N-doped gain layer must be highly doped to create a large E-field at the p-n junction to quickly sweep out generated e-h pairs as well as induce avalanching. The gain layer thickness must be thick enough to allow for carrier multiplication but thin enough to keep the device operating at low gain (10-20) [6]. Low gain is needed to amplify signals generated by MIPs since too high a gain can amplify background noise and increase event pileup that occurs when signals from multiple MIPs are too close in timing and are indistinguishable from one another.

The aluminum doped p-type layer must be highly doped to form a good metal-semiconductor contact and minimize the resistance generated carriers experience before being collected as signal. Additionally, the high p-type creates a large E-field at the p-n junction.

These stacks were epitaxially grown by a commerical vendor using metal-organic chemical vapor deposition (MOCVD) with the buffer and drift layers grown in one run, followed by the growth of the gain and p-type contact layer. A PiN diode epi-stack was grown similar to the LGAD but without the gain layer ( Fig. 1). Secondary-Ion Mass Spectroscopy (SIMS) data confirms the doping and thickness of the contact and gain layer. Doping of the drift region is low enough to be outside the detection limit. The LGAD devices were fabricated in tandem with the PiN diodes. The two are compared to demonstrate carrier multiplication in the LGAD. The controllable low-gain mechanism of these devices is shown in a separate publication [5].

Process Flow

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Device fabrication was carried out on a 1 " die from the epi-stacks shown in Fig. 1. Test structures and devices have been fabricated with the outlined process shown in Fig. 2. The device layout includes mesas of varying sizes ( ) and test structures for process testing and
electrical characterization. Additional devices are being fabricated with this process flow in epistacks with varying gain layer doping concentration to investigate the effects on avalanching behavior, but are not discussed in this paper.

Fig. 1. Thickness and doping concentration of the left: LGAD and right: PiN diode.

Fig. 1. Thickness and doping concentration of the left: LGAD and right: PiN diode.

Fig. 2. Condensed process flow for the fabrication of an LGAD in .

Fig. 2. Condensed process flow for the fabrication of an LGAD in .

There exist several fabrication challenges when processing . It is, for example, difficult to obtain smooth etched surfaces using plasma-based etch steps in with high etch rates and achieve vertical sidewalls. Reduced surface roughness can be achieved using a select gas composition and pressure during Reactive Ion Etching (RIE) to obtain an etch of minimal roughness. This allows for a better interface between a passivation layer and the etched and reduce the surface dark current from damage at the semiconductor surface. For LGADs, a good passivation strategy is important to reduce dark current and to minimize E-field enhancement at device edges and therefore avoid breakdown. Two different passivation methods were investigated: 1) plasma-enhanced chemical vapor deposition (PECVD) of silicon dioxide ( ) and 2) thermal oxidation with a subsequent thicker PECVD SiO2 layer. Devices are fabricated using each approach and the dark current is compared. Ohmic contacts are also desired in LGADs to minimize series resistance. The process for ohmic contact formation on p-type is discussed since various thickness and compositional variations of metal stacks are used for p-type SiC contacts in the literature.

Reactive Ion Etching in 4H-SiC

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Mesa etching is a relatively simple technique to control the E-field in the device. While E-field enhancement at the device edges using this approach is expected, which will reduce the expected break-down voltage of the devices, this approach is used to demonstrate initial device operation. Future implementations will target more sophisticated edge termination strategies, such as planar junction termination extensions (JTEs), which use ion implantation [1].

In this work, an etch recipe has been developed for a mesa etch of in depth in order to etch through the contact and gain layers and isolate the devices. RIE is used to etch the mesa structures and requires process refinement to achieve smooth surfaces for the required etch depth. A smooth etch surface is desired to reduce the number of surface defects that can contribute undesired leakage current paths, E-field enhancement and instability [7]. We use a photoresist mask rather
than metal since it is simple to deposit and remove. Compared to a metal mask, photoresists typically demonstrate reduced micromasking during the etch. Micromasking occurs when the etch mask is etched and redeposited on a previously exposed region, masking the region and creating a rougher etch result.

Fig. 3. AFM images of the left: unetched mesa and right: etched region.

Fig. 3. AFM images of the left: unetched mesa and right: etched region.

The gasses used are a mixture of fluoroform ( ), diatomic oxygen ( ) and argon (Ar). Fluoroform is used as a source for fluorine atoms and is primarily responsible for etching . An oxygen gas flow of demonstrates a good balance between etch rate and surface roughness in etched regions of .The RIE process of etching with fluorinated and oxygenated species is described as a combination of physical ion bombardment and a chemically reactive process. The Si -terminated face of is etched by fluorine ions while the C-terminated face is etched by both fluorine and oxygen ions [10]. Argon affects the etch process via physical bombardment, removing residual organics from the redeposited photoresist that might induce micromasking [11] and increase etch roughness.

A smooth etch result is demonstrated using atomic force microscopy (AFM) as shown in Fig. 3. The valley-to-peak heights in both cases is about 27.5 nm which indicates the etch is not roughening the silicon carbide. Using scanning electron microscopy (SEM) shown in Fig. 4, the angle of the etched mesa side walls are measured at , indicating the selectivity of the SiC to the resist mask is low, as expected when using a photoresist mask. Vertical mesas are desirable to achieve a higher breakdown voltage and can be optimized in future studies.

Device Passivation Strategies

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Device passivation is a critical step, in particular following mesa etching, to minimize surface traps capable of increasing dark current [12] or causing premature breakdown. Historically, researchers passivated devices using thermally grown [13], Plasma-Enhanced Chemical Vapor Deposition (PECVD) and SiN [14], or with combinations of thermal oxides and deposited dielectrics [7]. Given the high thermal budget available at this stage in the process, we investigated two approaches: PECVD only, and the combination of dry thermal oxidation followed by PECVD oxide.

The PECVD SiO2 was deposited using an Oxford Plasmalab 80 Plus PECVD with inlet gas con- centration of helium ( He ), nitrous oxide and silane . The oxide was deposited at a pressure and temperature of 1000 mTorr and , respectively. The alternate method consists of a thermal oxidation in a Titan II thermal oxidation chamber prior to the PECVD deposition. The sample is exposed to dry oxygen at for 5 hours. Before cooling down, the sample is annealed at the same temperature in a nitrogen environment.

Fig. 4. Cross-sectional SEM image of a mesa in the PiN diode. The sidewall and oxide thickness are measured at and 491.3 nm , respectively.

Fig. 4. Cross-sectional SEM image of a mesa in the PiN diode. The sidewall and oxide thickness are measured at and 491.3 nm , respectively.

Fig. 5. Dark current of diodes passivated using left: only a PECVD oxide film and right: thermal oxidation and PECVD oxide film.

Fig. 5. Dark current of diodes passivated using left: only a PECVD oxide film and right: thermal oxidation and PECVD oxide film.

The total oxide thickness was measured using the SEM image shown in Fig. 4 in addition to a reflectivity measurement using a Filmetrics tool model LS-DT2. The total oxide thickness is 500 nm . The PECVD oxide is 450 nm resulting in a thermal oxide thickness of 50 nm .

The effectiveness of each passivation approach was evaluated by measuring the dark current of fabricated diodes. The resulting data is shown in Fig. 5. The dark current under a reverse bias of 10 V for a PECVD passivated device is hundreds of nA . However, the dark current for a device passivated with a thermal oxidation and subsequent PECVD oxide layer does not reach 0.1 nA at a reverse bias of 110 V . While the dark current shown here is larger than some avalanching photodiodes (APDs) [15], it is comparable to others [7, 16]. Due to the reduced dark current, passivation via both thermal oxidation and PECVD are selected.

Low Resistivity Contacts

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After selectively exposing the top of the mesa by RIE of the passivation layer, metal contacts are deposited using electron beam (e-beam) evaporation on both the back-side substrate and top- side contact layer. It is important to create ohmic contacts for LGADs in order to aid charge collection, as having a Schottky barrier will act as a current limiter by preventing charge carriers from travelling through the metal-semiconductor interface. While methods to create ohmic contacts differ in the literature, it has been found that Ni - and Al -based metal stacks are commonly used in creating ohmic contacts in n-type and p-type , respectively [17, 18, 19]. In this process, is deposited as the anode and as the cathode. The Ti on the anode promotes adhesion and uniform formation of a layer during annealing [20] while the Ti in the cathode is used to create a layer post-annealing [21], reducing the Schottky barrier height (SBH) at both interfaces. The Al will further reduce the SBH by diffusing towards the surface during annealing and increasing the conductivity at the surface as Al is the p -type dopant of [22]. The n-type and p-type contacts were simultaneously annealed at
for 5 min. in a environment. Afterwards, an layer and stack were deposited using e-beam evaporation as pad contacts for probing on the anode and cathode, respectively.

Fig. 6. Left: characteristics of for anode annealed at for 5 min . in a environment. Right: I-V characteristics of cTLMs for cathode annealed at for 5 min . in a environment.

Fig. 6. Left: characteristics of for anode annealed at for 5 min . in a environment. Right: I-V characteristics of cTLMs for cathode annealed at for 5 min . in a environment.

Fig. 7. Left: I-V characteristics of a diameter LGAD. Center: C-V and Right: Inverse C-V characteristics of a diameter 4H-SiC LGAD. Figures adapted and modified from [5].

Fig. 7. Left: I-V characteristics of a diameter LGAD. Center: C-V and Right: Inverse C-V characteristics of a diameter 4H-SiC LGAD. Figures adapted and modified from [5].

Circular transmission line measurement (cTLM) structures were fabricated on the substrate and contact layer to extract specific contact resistivity. The diameter of the inner circular pad of the cTLM is and the spacing between the adjacent contacts is , and . The I-V characteristics of the cTLMs were measured using a Keithley 4200 semiconductor parameter analyzer. According to Fig. 6, the linear I-V curves indicate ohmic contact formation on the substrate. The contacts on the contact layer show a small Schottky barrier as seen by the slight non-linearity in the I-V curves in Fig. 6. For an LGAD that will be operating at high voltages between the full depletion voltage (voltage at which the entire device is depleted) and the breakdown voltage, this Schottky barrier does not pose any major issue. It should be noted that the I-V curves were approximated to be linear to calculate the specific contact resistivity for the p-type contact. Specific contact resistivities of and were calculated for the p- and n-type contacts, respectively.

Electrical Characterization

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I-V and C-V characteristics of the devices were characterized using a Keithley 2657A high voltage SMU and Keithley 4200 semiconductor parameter analyzer, respectively. A breakdown voltage of 1160 V was measured in the LGAD. To fully deplete the gain and drift layers to ensure all electron- hole pairs generated by incoming MIPs are collected, this device must operate at a bias greater than 2 kV . The high depletion voltage required is due to the thick drift region. The breakdown voltage can be increased by incorporating edge termination features in future studies.

The gain layer depletion voltage ( ) was measured to be 77 V as shown by the characteristic "step" feature in the C-V curve in Fig. 7. The doping levels of the gain and drift layers in the LGAD and PiN diode were calculated from the C-V data to be (gain layer), (LGAD drift layer), and (PiN diode drift layer). Using an abrupt 1D diode model, the thickness of the gain layer was found to be from the extracted and doping levels. The calculated doping levels and thicknesses are close to the target values.

Summary

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Critical steps in a process flow for the fabrication of a LGAD are discussed. The roughness pre- and post-RIE is shown to be similar through a comparison of AFM images. SEM confirms the etch depth, sidewall angle, and oxide thickness. The dark currents from two different passivation strategies are compared, with a thermal oxidation coupled with PECVD oxide demonstrating lower dark current which is beneficial to avoid breakdown during high voltage operation. The Ni and Al metal stacks form low resistivity contacts in n - and p -type . Electrical characterization of the devices shows the ability to sustain high voltage as well as depletion of the gain layer to demonstrate low-gain charge carrier multiplication in the LGAD structure. Radiation response testing using particles corroborates the electrical characterization results on these same devices [5]. To test how detectors withstand high radiation environments, electrical and -particle irradiation response testing will be compared before and after exposure to high fluences of radiation. The use of ion implantation for JTEs and in place of epitaxial growth is being considered for future experiments.

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The original version of this paper is available on https://www.scientific.net/KEM.1024.79.pdf

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 87-95

doi: 10.4028/p-OI6ItK

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-11-14

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-12

All Electrical Near-Zero Field Magnetoresistance Magnetometry up to Using SiC Devices

The original version of this paper is available on https://www.scientific.net/KEM.1024.87.pdf

F. Sgrignuoli , I. Viti , Z.G. Yu , E. Allridge , P. Lenahan , S. Goswami , R. Ghandi , M. Aghayan , and D.M. Shaddock

QuantCAD LLC, 5235 S. Harper Ct., Chicago IL, 60615, USA

The Pennsylvanian State University, University Park, PA, 16802, USA

GE Aerospace Research Center, 1 Research Cir, Niskayuna, NY, 12309, USA

*afabrizio.sgrignuoli@quantcad.com, ivan.viti@quantcad.com, zhigang.yu@quantcad.com,

Elijah.Allridge@coherent.com,

Keywords: Quantum magnetometry, NZFMR, high temperature, SiC diodes

Abstract

Silicon Carbide ( SiC ) is renowned for its exceptional thermal stability, making it a crucial material for high-temperature power devices in extreme environments. While optically detected magnetic resonance (ODMR) in SiC has been widely studied for magnetometry, it requires complex setups involving optical and microwave sources. Similarly, electrically detected magnetic resonance (EDMR) in SiC, which relies on an electrical readout of spin resonance, has also been explored for magnetometry. However, both techniques require microwave excitation, which limits their scalability. In contrast, SiC 's spin-dependent recombination (SDR) currents enable a purely electrical approach to magnetometry through the near-zero field magnetoresistance (NZFMR) effect, where the device resistance changes in response to small magnetic fields. Despite its potential, NZFMR remains underexplored for high-temperature applications. In this work, we demonstrate the use of NZFMR in SiC diodes for high-temperature relative magnetometry and achieve sensitive detection of weak magnetic fields at temperatures up to . Our technology provides a simple and cost-effective alternative to other magnetometry architectures, eliminating the need for a microwave source or complex setup. The NZFMR signal is modulated by an external magnetic field, which alters the singlet-triplet pair ratio controlled by hyperfine interactions between nuclear and electron/hole spins, as well as dipole-dipole/exchange interactions between electron and hole spins, providing a novel mechanism for relative magnetometry sensing at elevated temperatures. A critical advantage of our approach is the sensor head's low power consumption, which is less than 0.5 W at for magnetic fields below 5 Gauss. This approach provides a sensitive, reliable, and scalable solution with promising applications in space exploration, automotive systems, and industrial sectors, where high performance in extreme conditions is essential.

Introduction

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Due to its unique thermal, mechanical, and electronic properties, SiC has emerged as a crucial material in high-power electronics and devices designed for operation in harsh environments. Its wide bandgap (approximately 3.2 eV for ) allows SiC to sustain high electric fields, high voltages, efficient heat dissipation, and operate at temperatures far exceeding those of silicon-based devices [1]. These attributes make this material indispensable in applications requiring durability and efficiency under extreme conditions, such as power electronics, automotive systems, smart grids, and aerospace [2-4], to cite a few. Additionally, SiC hosts defects that exhibit optically and electrically active spin states, making it a versatile material for quantum sensing and spintronics [5-11]. Unlike nitrogen-vacancy (NV) centers in diamonds, SiC defects are compatible with modern semiconductor fabrication techniques, offering a scalable platform for quantum technologies [5,11].

A concrete example of SiC's pivotal role lies in small-size, weight, and power consumption (SWaP) magnetometry for high-temperature environments, crucial for applications ranging from engine monitoring and chip quality control to space exploration [12-14]. Conventional magnetometers, such as fluxgates, face significant limitations in size, power consumption, and susceptibility to thermal noise [14]. Fluxgate magnetometers also require frequent calibration and are prone to performance degradation due to noise interference [14]. ODMR techniques have introduced high sensitivity for magnetic field detection at smaller scales [15]. However, ODMR systems, such as optically pumped magnetometry (OPM), rely on microwave excitation and optical detection, complicating their integration into SWaP devices [14]. Similarly, EDMR, which monitors spindependent phenomena by detecting changes in electrical current, improves signal readout but still requires microwave fields, limiting its practicality in miniaturized devices [16]. These techniques also struggle to function in high-temperature environments, with fluxgates degrading above [17], OPMs suffering from instability in atomic vapor cells [18], and EDMR experiencing reduced spin coherence and increased thermal noise [19].

Near-zero-field magnetoresistance (NZFMR) is emerging as a powerful defect metrology alternative [20-23], overcoming many of the limitations of traditional magnetometry [14]. NZFMR does not require microwave sources or large magnetic fields, significantly reducing system complexity, power consumption, and cost [24]. By avoiding RF fields, NZFMR enables spectroscopy below metallization layers to detect point defects in fully processed semiconductor devices, making it highly valuable for integrated circuit reliability [23]. Moreover, NZFMR allows for self-calibrating magnetometry [14]. Similar to the EDMR, NZFMR involves spin-dependent changes in current, but instead of relying on resonance at higher fields, the change is centered at near-zero magnetic fields. Low-field hyperfine mixing and electron-electron dipolar interactions alter the singlet-to-triplet pairing ratio in an NZFMR response, enabling the detection of changes in the recombination current with external magnetic field variations [24-26]. Additionally, the magnetic isotopes of host and dopant atoms involved in hyperfine interactions act as natural, stable markers, allowing selfcalibration over time and temperature [14]. This stability is rooted in the stable energy levels of SiC's defects, which remain unaffected by temperature fluctuations, ensuring consistent performance across various conditions [6].

By utilizing NZFMR to probe the spin properties of active defects in standard SiC p-n junction devices, we have demonstrated an all-electrical SWaP relative magnetometry capable of operating at temperatures up to without isotopic purification or design enhancements. The proposed technology represents a significant advancement, overcoming the limitations of existing magnetometry techniques and opening new avenues for metrology and space exploration. It provides a reliable, scalable, cost-effective solution for extreme environments without sacrificing sensitivity, setting a new standard for high-performance magnetic field sensing across the most challenging conditions.

Methods

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The core of our method relies on the near-zero-field spin-dependent recombination (SDR) phenomenon, which enables the electrical readout of a current that encodes the magnetic field in which the sensor is immersed. The intrinsic defects of the SiC device dictate the response of the SDR current. When a semiconductor junction device is biased to yield a pronounced recombination current, carriers couple with deep-level (spin-dependent) defect electrons, as schematized in Fig.1. These spin states can be singlet or triplet states. Due to the Pauli exclusion principle, electron-hole recombination is allowed only in a singlet spin configuration, creating a bottleneck when the pair is in a triplet state. At near-zero magnetic fields, this bottleneck is alleviated by low hyperfine interactions [25, 26], which flip the defect electron's spin triplet into singlet states. This process remains active despite the thermal energy being orders of magnitude larger than the single-triplet mixing energy.

Fig. 1. Illustration of the SDR mechanism, the primary responsible for the NZFMR effect. A conduction electron (gold sphere) and a trapped electron (gold sphere bound to a isotope, represented by a grey sphere) couple to form an intermediate spin state. The singlet-triplet pairs form due to a nuclear magnetic field and a small external magnetic field B . The local magnetic field sensed by each electron is then the vector sum of these two fields.

Fig. 1. Illustration of the SDR mechanism, the primary responsible for the NZFMR effect. A conduction electron (gold sphere) and a trapped electron (gold sphere bound to a isotope, represented by a grey sphere) couple to form an intermediate spin state. The singlet-triplet pairs form due to a nuclear magnetic field and a small external magnetic field B . The local magnetic field sensed by each electron is then the vector sum of these two fields.

Figure 2 shows our custom experimental setup for detecting DC magnetic fields via a conventional SiC diode's response using lock-in amplification. As schematized in Figure 2a, this approach relies on standard equipment and traditional SiC devices rather than isotopically purified materials, offering a cost-effective solution. The SiC device utilized in this study was not specifically designed for magnetometry. It is a lateral diode intended for high-temperature operation, featuring an ionimplanted p -well within a low-doped n -epitaxial region on a mid-cut conductive substrate. The structure is encapsulated by vapor-deposited and films. The die was attached to a -compatible alumina substrate using gold-nanoparticle sintered pastes, with Au pads and routing lines directly written onto the substrate [27-29]. This packaged diode is stacked between two sets of coils [30], functioning respectively as modulation and nulling coils. Even though the nulling coils can cancel out unwanted background magnetic fields in real-world applications, they are utilized to generate the quasi-DC magnetic field sensed in this work. A signal generator (e.g., Siglent SDG2042X) is configured to ramp the voltage applied to the nulling coil amplifier from a negative to a positive value over 60 seconds. This controlled voltage sweep alters the background magnetic field experienced by the SiC diode. Repeating this 60-second sweep multiple times, we can acquire multiple datasets under the same conditions and then average them to enhance signal quality and reduce noise. The nulling coil amplifier is assembled entirely from commercially available components - an OPA541-based, high-voltage, high-current audio amplifier board - providing a
budget-friendly alternative to specialized lab instrumentation. Similarly, a TPA3116D2-based XH-M543 dual-channel stereo audio amplifier board drives the modulation coils. Both amplifiers are powered by a programmable DC power source (e.g., Rigol DP932E). The modulation coils generate alternating magnetic fields driven by an AC signal, which interact with the sample to modulate its magnetization. The modulation frequency is carefully chosen to enhance signal sensitivity significantly when suppressing low-frequency noise. Besides their different functionalities, these coils have a 28 AWG cross-sectional area and a field efficiency of 40 Gauss amps [30]. They were connected with ceramic-coated wire, secured with through-hole connectors, and further enhanced with conductive paste to reduce resistance to create the stack shown in Fig. 2b. This assembly is housed within a high-temperature oven (e.g., TableTop furnace company), showing full operation even after 60 minutes at with a current of 2 amps, demonstrating long-operation capabilities.

Fig. 2. (a) Diagram of the high-temperature magnetometry setup. (b) A SiC diode mounted on a printed circuit board chip stack with modulation and nulling coils, specifically designed to sustain high-temperature operations, formed the assembly, which was placed in the oven. The proposed technology is approximately the size of a quarter, demonstrating a significant reduction in form factor.

Fig. 2. (a) Diagram of the high-temperature magnetometry setup. (b) A SiC diode mounted on a printed circuit board chip stack with modulation and nulling coils, specifically designed to sustain high-temperature operations, formed the assembly, which was placed in the oven. The proposed technology is approximately the size of a quarter, demonstrating a significant reduction in form factor.

To handle the weak signals produced by the SiC diode, the setup integrates a preamplifier, a lockin amplifier (e.g., SR850 DSP model from Stanford Instruments), and different control components, as illustrated in Figure 2(a). The preamplifier strengthens the weak SDR signals, while the lock-in amplifier isolates and enhances the signal of interest by locking onto the modulation frequency. This lock-in technique improves the signal-to-noise ratio, making extracting meaningful data from the noisy environment easier. The lock-in amplifier is tuned to the modulation frequency, allowing selective detection of the resonant responses induced by the alternating magnetic field. The system also includes an analog-to-digital converter (ADC) handled by an Arduino-compatible microcontroller (e.g., ELEGOO Uno R3 board), which features a built-in 10-bit ADC, which reads the amplified analog signals and sends the digitized data to a PC interface for further analysis. In summary, the combination of high-temperature materials, advanced modulation techniques, and sensitive detection (mostly made of commercially available components assembled in-house) makes the system suitable for robust DC magnetometry in extreme conditions. Significantly, our setup is not limited to DC detection. By adequately changing the electronics and the features of our lock-in amplifier to detect signal characterized by frequencies of the order of kHz , we can also extend our method to detect AC magnetic fields.

Fig. 3. (a) Relative current as a function of the applied magnetic field at different temperatures. data are multiplied by a factor of 2 to increase visibility. (b) Forward bias voltage as a function of temperature. These data are obtained by fixing the diode current to 200 nA for all the different temperatures.

Fig. 3. (a) Relative current as a function of the applied magnetic field at different temperatures. data are multiplied by a factor of 2 to increase visibility. (b) Forward bias voltage as a function of temperature. These data are obtained by fixing the diode current to 200 nA for all the different temperatures.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/KEM.1024.87.pdf

Figure 3 reports averaged NZFMR signals (panel a) and forward bias (panel b )measurements for different temperatures. As the temperature increases, the NZFMR signals shift, and the relative current exhibits a gradual change across the magnetic field range (see panel (a)). This shift stems from the local change in the magnetic field background sensed by the SiC diode at higher temperatures. Because these background variations remain unquantified (and lie beyond the scope of this study, which focuses on demonstrating the reliability of relative magnetometry at high temperatures), we refer to our results as "relative." The data of panel (a) are averaged over 20 measurements at each temperature. Without this averaging, the temperature-induced drift would mask the NZFMR signal, making it challenging to detect magnetic field-related changes. Although the NZFMR signal weakens at higher temperatures (see Fig. 3a), the correlation between the magnetic field and current remains evident, confirming the system's ability to detect NZFMR under extreme thermal conditions. The SiC device becomes more conductive, increasing the temperatures. Indeed, the bias voltage is reduced to maintain a constant current of 200 nA on a SiC diode, which helps minimize thermal effects. Also, power consumption increases slightly at due to an increase in coil resistivity from at to at . Still, it remains low: lower than 0.5 W for fields less than 5 Gauss. Therefore, the proposed technology operates at low power, reflecting the vision of a robust SWaP all-electrical magnetometer on-chip to hostile environments.

Fig. 4. (a) Demonstration of high-temperature relative magnetometry. Change in the device current with the magnetic field. Data are taken at . Each curve has an average of twenty runs.
(b) Magnetometry sensitivity estimations as a function of the bandwidth for different temperatures.

Fig. 4. (a) Demonstration of high-temperature relative magnetometry. Change in the device current with the magnetic field. Data are taken at . Each curve has an average of twenty runs. (b) Magnetometry sensitivity estimations as a function of the bandwidth for different temperatures.

Figure 4 demonstrates how an applied offset magnetic field affects NZFMR measurements and device sensitivity. Panel (a) shows NZFMR signals for three offset fields: +1.5 Gauss (blue), 0 Gauss (green), and -1.5 Gauss (red). Each trace exhibits a systematic vertical shift in relative current as the offset field varies. The red and blue curves intersect a horizontal reference line - originating from the zero-offset (green) curve - at approximately -1.25 G and +1.5 G , respectively. These values match the applied offset fields within a precision of . This shift indicates a clear correlation between changes in the magnetic environment and the relative current response, demonstrating NZFMR magnetometry at high temperatures. Panel (b) presents the device's sensitivity as a function of bandwidth for various temperatures, estimated using the following relation:

where is the electronic charge, is the DC current responsible for the flicker noise, is the measurement bandwidth, is the current change, and is the signal line width [14]. As the bandwidth increases, the system's sensitivity decreases because more noise is introduced over a broader range of frequencies, which lowers the signal-to-noise ratio and makes it harder to detect small changes in the magnetic field. Simultaneously, panel (b) also shows a temperature dependence, with lower temperatures yielding better sensitivity. This behavior is due to increased thermal noise, raising the temperature. This reduction in sensitivity at elevated temperatures is primarily driven by two factors: the broadening of the NZFMR signal (i.e., ) and a decrease in the current response (i.e., to magnetic fields. Higher temperatures reduce the current response to applied magnetic fields due to increased carrier recombination and thermal excitations that compete with the magnetoresistive effect. Despite these factors, the sensitivity reduction is modest (almost two orders of magnitudes), demonstrating that our SiC-based NZFMR sensor remains robust for high-temperature magnetic field detection, even though not specifically designed for magnetometry applications.

Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1024.87.pdf

In conclusion, we demonstrate the feasibility of an all-electrical NZFMR-based relative magnetometry using SiC diodes for high-temperature applications. By integrating a commercially available SiC diode originally not designed for magnetometry - onto a custom stack with high-temperature-ready modulation and nulling coils, we detect low magnetic fields at temperatures up to . Our system is cost-effective and scalable, thanks to in-house assembly using readily available electronic components, eliminating the need for specialized research instrumentations. Moreover, the compact form factor - approximately the size of a quarter - and low power consumption of under 0.5 W at for magnetic fields below 5 Gauss make this solution especially attractive. Its robust and low-SWaP design positions it as a promising option for all-electrical relative magnetometry in harsh environments.

Several strategies could be used to further improve this system's sensitivity, especially at high temperatures. First, designing SiC diodes specifically for magnetometry by engineering defect states and optimizing doping profiles could enhance the current response , reducing spin-independent recombination losses at elevated temperatures and, thus, a higher sensitivity. Additionally, using isotopically purified SiC material will minimize hyperfine interactions, leading to a narrower line width and an enhanced signal. Furthermore, advanced signal processing techniques, including adaptive filtering and noise reduction algorithms, could extract more accurate signals from noisy environments, improving the overall performance. By implementing these strategies, SiC -based NZFMR magnetometry can achieve superior sensitivity and reliability, positioning it as a leading solution to high-performance magnetic field sensing in extreme environments and a reliable technology for space exploration, automotive systems, and industrial applications.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/KEM.1024.87.pdf

The room-temperature data are based on work supported by the National Aeronautics and Space Administration under Contract No. 80NSSC23CA145 issued through the SBIR/STTR Program. The high-temperature data are based on work supported by the Defense Advanced Research Projects Agency (DARPA) under Agreement No. HR0011-23-9-0114. We acknowledge useful discussions with M. E. Flatté, C. J. Cochrane, and H. Kraus.

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Patent Pending

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/sic-application-and-sic-devices-reliability-and-stability/978-3-0364-1916-9

Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 97-106

doi: 10.4028/p-4i8vgQ

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-03-26

Accepted:
2025-03-26

Online:
2025-09-12

SiC in Space: Potential High-Power Application Survey

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

Antxon Arrizabalaga

European Space Agency (ESA), Netherlands

antxon.arrizabalaga@esa.int

Keywords: SiC, semiconductor, industry, power electronics, business case, high power, space power, space electronics.

Abstract

The next space missions require power levels that current space qualified semiconductor technology cannot provide. The silicon carbide devices are considered to overcome these challenges, and provide the required technical performance. European space industry is asked in individual meetings about their specific needs and requirements, this information is gathered, classified and presented to the silicon carbide manufacturers. This work is the connection between the two industries to better understand the requirements and applications, and build a new business case for the SiC devices in space applications.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

The space exploration missions as well as the future development plans of the main space agencies in the world demand several orders of magnitude more power than what is currently available [1], [2]. The European Space Agency (ESA) is pushing for high-voltage (HV) systems to enable the highpower (HP) in space, but this transition is blocked by the operation of electrical, electronic, and electro-mechanical (EEE) components in space, forcing the engineers to apply deratings to the maximum rated values for reliability reasons [3].

On the one hand, the space qualified Si components show poor performance in HP systems, due to their limited blocking voltage and low current level. On the other hand, and even if the GaN devices show unmatched performance there are no available space qualified HV GaN devices yet. Following the trend in terrestrial HP applications, power distribution [4], [5], electric vehicles and traction [6], [7], [8] and aerospace applications[9], [10] for example, space engineers are looking to the SiC as an answer to the technical challenges presented by the new HP applications.

SiC has already been proposed for and tested in space applications with promising results. Improved efficiency and system level performance are achieved in a high input voltage power processing unit (PPU) [11] in a HP PPU [12], and in HV ( 100 V ) distribution systems [13], [14]. Even if the reported results are positive, there is a wide gap on the space market to be covered by SiC , needing a clear effort from the SiC manufacturers to develop and test space qualified SiC components that could be used to achieve the technical figures required in the new HP space applications.

In this paper, the author tries to bridge the existing gap between the SiC manufacturers and the potential end users of their products, the space power industry. By gathering the needs of the main European companies of the space industry, presented firsthand to the author, the potential applications of SiC semiconductors in space are classified, also identifying the main technical drivers required in each one. By doing so, the author presents a new market and potential business case for the SiC manufacturers, guiding them to a better understanding of the needs the space power industry has, and helping the adoption of the SiC technology by the space industry, to finally overcome the challenges of the next HP systems in space.

Methodology

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

As it is mentioned in the introduction of the paper, this work is carried out in constant communication with the main European space power companies. The work is divided in 5 phases, needing the contribution of the industry in four of them. Fig. 1 summarizes the phases and the number of companies involved in each one of them.

Phase 1, First Contact. During the first phase of the project, the most important space power companies in Europe are identified, together with the key people inside the organizations to stablish the first contact by email. In the communication, the main idea of the project is explained, and the company is invited to an individual meeting with the author. The companies and the key people are selected using the expertise of the most experienced colleagues in ESA, which in some cases even participate in the first communication. The companies are offered to invite any individual colleague or advisor to the meeting, to ensure the information is transferred and received correctly, and most importantly, it reaches the right people inside the institutions. 12 companies are contacted in this first phase.

Phase 2, Individual Meetings. One-hour meetings are set with the companies during the second phase. The first half of the meeting is used by the author to present the project in detail. There, the background of the project, the terrestrial approach and the benefits of the SiC devices are explained. The author also presents the main terrestrial voltage standards and its applications, finishing the presentation with a review of the published radiation testing results and the existing SiC based space systems. A discussion and feedback opportunity opens right after.

In the end of the meeting, the author presents and shares a fill-in form specially designed for the project, which the companies are asked to fill-in and send back to the author. The form is divided in two categories, making a difference between the most urgent needs and future wishes the companies might have. In each category, the companies should name and describe the specific application benefiting from the required new semiconductor devices, explain the technical characteristics of the current solution, describe the main drivers to improve it and make comments on the needed or desired semiconductor characteristics.

The companies are then given time to discuss internally and fill-in the form gathering the needs from different internal departments. Out of the 12 initially contacted companies, 10 answered positively and went through meeting the author in the individual meetings and receiving the fill-in form.

Phase 3, Gathering, Classification and Redaction of the Information. The third phase consists of gathering the information in the filled-in forms, classifying the applications mentioned by all the companies, putting together all the common answers and writing a wide document with all this information. This work is done individually by the author, keeping the confidential status of all the answers.

Fig. 1. Summary of the phases of the project, together with the number of companies participating in each phase.

Fig. 1. Summary of the phases of the project, together with the number of companies participating in each phase.

Out of the 10 meetings, one company declined the offer to participate stating their focus is on the lower power spectrum, and the current technology satisfies their needs. Another company participated actively in the meeting, gave positive feedback and even participated in further information exchange during the following months. However, and even if their feedback is considered and used in the following stages of the project, they failed to deliver an organized answer by filling-in the form. The project continues with 8 formal answers out of the 10 meetings, gathering all the information in a document called technical specification document.

Phase 4, Review of the Technical Specification Document. All the 8 contributing companies receive the technical specification document and are asked to check and review it internally. All the companies agree on the content of the document, giving positive feedback to the author.

Phase 5, Divulgation of the Results. The final phase of the project is making the results public, writing technical papers such as this work, and presenting the project in specialized conferences. The main objective of the project, as mentioned in the introduction, is to connect both the SiC manufacturers and the space power industry, so the final phase of the project is equally important to achieve the main objective.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

Classification by Industry Requirements. The requirements of the industry clearly divide the applications in two types and are summarized in Fig. 2. In the first case, industry wants to increase the power of existing low-power systems, keeping the performance figures. These application type includes HP distribution, needing HP latching current limiters (LCL), HP DC-DC converters and rectification. A common desire is to increase the voltage of the application, but due to the complexity of the solution, and to be able to reach even higher power, increasing the current is also needed. The considered application voltage for these applications is above 100 V , the higher the better, up to 300 V . Systems up to 100 A are desired. The rectification stage, or the rectifying component in each system should also be considered.

The second application type is looking to improve the performance figures of already existing HP systems. In this application type, we can find HP motor drives, to drive pumps or use in vector thruster control in the launchers.

Fig. 2. Application classification by the industry requirements.

Fig. 2. Application classification by the industry requirements.

These are already existing applications, that operate at HP and in very demanding conditions. Reducing the losses and the complexity of these systems, by reducing the needed number of parallel devices for example is also a requirement for industry. HP motor drives operate at HV, over 100 V up to ideally 1 kV , and consume high-current, over 200 A . Even if industry mentioned the 200 A limit in these applications, further requirements are found to supply up to 400 A for electric motor drives. The final applications are the very HV applications. Covering switches, circuit breakers and diodes. These applications work at over 800 V , but limited current. As their development stage is still preliminary in most cases, the interest shown by industry is also reserved.

Classification by ESA Innovation Categories. ESA classifies innovations in three categories, according to the degree of innovation they bring when compared to the state-of-the-art. Each innovation category brings a different degree of risk for the industry, directly related to the time, cost and effort required for its development, and the possibility of its massive adoption by the end users. This section explains the three innovation categories, and classifies the applications presented before in each one of the categories, shown in Fig. 3.

The first category is called enhancing and refers to innovations which bring a substantial improvement to the state-of-the-art system. It is usually based on a technology replacement, keeping the same features, but improving the performance. In the case of the SiC, this kind of innovation would mean replacing the Si devices in an existing application and optimizing the system to get system-level benefits. Enhancing innovations represent low risk for manufacturers, and the development cost, time and effort should be low. The adoption of the innovation by industry should be straightforward and have high probability of success. Most of the applications mentioned by the industry fall in this category.

The second category is called enabling and refers to innovations which will allow a new feature, new application, or even a new mission. The technologies in the enabling innovation category are considered as critical technologies for a certain feature, application or mission. In the case of the SiC, this means that without the adoption of such devices, the new desired feature, application or mission is no longer possible, due to the limitations of the state-of-the-art technology. Enabling innovations represent medium-high risk for manufacturers, as their development cost and effort is higher, since this new feature, application or mission has never been done before. In addition, its adoption by industry is more challenging, and the probability of success is lower, because the new feature, application or mission in which this innovation is required might be delayed, suffer a significant variation, or even get cancelled in the worst-case scenario. Very HV applications fall in this category of innovation.

The last category is called game-changing and refers to innovations which promise to bring entirely new capabilities. With this kind of innovation, completely new missions could be considered in the future. Game-changing innovations represent high-risk high-reward scenarios for manufacturers, as they would be leading totally unexplored markets. However, the adoption by industry is not even considered yet, leading to high uncertainty in the future markets. Industry is asked to focus on the enhancing and enabling innovations during the meetings, because the main goal of the work is to develop a business case for an early, cost-effective and successful adoption of the SiC technology by the European space industry.

Fig. 3. Application classification by ESA innovation categories.

Fig. 3. Application classification by ESA innovation categories.

Main Drivers. Industry is asked to highlight the main technical drivers to optimize in each application. Each application has its own characteristics, so depending on the target application, SiC manufacturers should focus on one or another technical feature to optimize in their product. Fig. 4 shows the main drivers to consider in each application, highlighted in grey, together with the technical requirement to make an impact in each main driver.

Increased current and thermal performance is a main driver for the applications willing to increase the power. With the current level increment, the conduction characteristics gain relevance, being also a main driver for all the enhancing applications. This means industry is looking for devices that are rated at high current and can perform in severe thermal environments, with reduced conduction resistance when compared to the space qualified silicon devices.

For HV and HP DC-DC converters, the switching performance is equally important. The same main driver should also be considered in the rectification and synchronous rectification applications, by optimizing the reverse recovery of the diodes. Due to the limited space qualified drivers, switching frequencies are usually not high in these applications, but pushing to 100 kHz or above is a desire of the industry, if the device technology allows it. With better switching performance than the space qualified Si , this is where SiC becomes key for these switched applications. Even if HP motor drives are also switched applications, the lack of magnetic components such as high frequency transformers or inductors in the topology reduces the interest of increasing the switching frequency to the 100 kHz range. Although a reduction of the switching losses is welcome, the extremely high current of the applications makes the conduction performance more important than the switching in this application.

All the before mentioned improvements should come with a reliable and relatively high blocking voltage capability. Mostly for HP motor drives and very HV applications this is a challenging requirement. Finally, it is worth mentioning that the peripheral technology used in the application should follow the proposed improvements, and the new features should be achieved with space qualified technology. This includes space qualified driving devices for improved conduction and switched performance, and printed circuit boards (PCB) technology for the required high current. The device packaging and connectors are also equally important.

Fig. 4. Main drivers to optimize for each application, with the technical requirements for each main driver.

Fig. 4. Main drivers to optimize for each application, with the technical requirements for each main driver.

Radiation. The HV operation of SiC MOSFETs in space is fully connected to the radiation effects, mostly to single event effects (SEE). Extensive testing has shown SiC devices need to be derated in voltage to prevent single event burnouts (SEB), analyzing the phenomenon in detail and proposing several causes [15], [16], [17]. In addition, these MOSFETs can suffer degradation due to SE even at significantly lower blocking voltages [15], [18][19]. The last reported tests show the SEE free voltage limit depends on the nominal blocking voltage of the devices and is related to the epi layer thickness [17], [20].

Table 1 highlights the SEB voltage limit for the maximum tested linear energy transfer (LET) for different rated voltage SiC MOSFETs, based on the available results in the literature. The results show 1200 V SiC MOSFETs, a widely developed voltage standard for the automotive market, is promising to operate in most of the space application voltage levels. If the nominal blocking voltage is confirmed to be related to the SEB voltage limit, the imminent development of several kV SiC MOSFET also suggests very HV applications could be possible in space in the near future [21], [22]. However, and even if this literature review seems promising, the results should be validated by more extensive testing. It is also important to remember the fact that the data presented in Table 1 shows the SEB voltage limit, so more careful study is mandatory to obtain the real SE degradation limits
that will meet mission specifications. This is why industry considers qualifying SiC MOSFETs for space applications is necessary to gain confidence and acceptance among the end users in the space market, as the HV capability is still not proven.

Table 1. SEB voltage limit for the maximum tested LET for different rated voltage SiC MOSFETs.

LET
[MeV-cm²/mg]
Nominal voltage of the SiC MOSFET [V]

650
900
1200
1700
3300

25

400

45
300

60

550
850

65

400

Packaging. The final technical comment of the industry is regarding the packaging needed to provide the technical requirements. The first concern is regarding the fast switching and the switching performance, which directly relates to the parasitics in the packaging and connections to the PCB. Currently discrete components are used in space, but their interconnection to build most of the power converter topologies such as the buck, boost, isolated bridges and inverters require a half-bridge connection of two discrete devices. Packaging the half-bridge in a single package, optimizing the parasitics and taking the burden or designing a more complicated layout from the designers is considered beneficial by industry.

The second concern is the thermal management of the devices in HP systems. Most of the times, HP means needing to remove several watts from the device, and the thermal coupling of the devices is not always straightforward. Designing HP packages with optimized thermal coupling to the thermal plate of satellites or the cooling system in the module is another requirement from industry. This can separate SiC devices from the extremely miniaturized GaN devices for example and make them the evident choice for HP systems in space. Packaging SiC in space qualified half-bridge modules, with minimum parasitics and optimized thermal coupling is key for their adoption in HV and HP DC-DC converters, as well as for HP motor drives. Some companies also mention HP six-pack modules for three-phase motor drives. Fig. 5 summarizes the different applications mentioned during this work, together with the operation points and the required packages. The vertical arrow represents the switching frequency of each application. For distribution LCLs, for example, no switching is needed, so discrete packaging is preferred. If we advance in the , HP modules show up, some to optimize thermals, in very high current applications, others to optimize the parasitics, in higher . In high , GaN devices should be considered.

Fig. 5. Required packaging type for each application, depending on the operation characteristics. In blue, the most important technical requirement for each application.

Fig. 5. Required packaging type for each application, depending on the operation characteristics. In blue, the most important technical requirement for each application.

Ongoing Work

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

As it has been shown in this work, there is interest on the SiC devices for several HP space applications, but industry still needs to find the answer to some technical questions. The operation conditions of the SiC devices in space applications will be very different from those in terrestrial applications. First of all, the voltage will be derated, using at least 1200 V SiC devices in 100 V or 150 V applications. In addition, there are no space qualified drivers optimized for SiC devices, and all the peripheral technology such as PCB connections and capacitor for example also need to be space qualified. The superior performance of the SiC devices in space conditions need to be tested.

This is a work the author is also doing inside ESA. Building conceptual prototypes, the space operation conditions are tested with commercial SiC. In the first prototype, the same space qualified drivers are used to compare the losses of a space qualified Si MOSFET and the losses on a 1200 V commercial SiC MOSFET is space operation conditions. This tests if the better physical characteristics of the SiC devices are still beneficial when severely derating the voltage, and using non optimized drivers. In addition, it tests if the one to one technological replacement will be beneficial in terms of losses, using already available and well known space qualified peripheral technology. The results are favorable and will be available soon.

The second conceptual test is done by using HP half-bridge SiC modules, again with space qualified peripheral technology and space operation conditions. A prove of concept 400 A inverter is designed and tested for motor drives, using 1200 V HP half-bridge commercial SiC modules, but
driving them with space qualified drivers. In the design, the performance of the SiC modules with space technology and operation conditions is tested, but it also works as a technology demonstrator, providing a reference design to industry on how to design HP systems, up to 400 A with space technology on a PCB. In addition, the challenges of HP are combined with the challenges the high switching speed of the SiC brings, facing high and rates, all tested in space operation conditions.

All this conceptual tests and demonstrator designs are supported by the launch of the EPOSiC project by ESA. In this project, Europe looks to support the development of space qualified SiC technology by funding the design, development, testing and qualification of a HP half-bridge SiC module, tested and qualified to switch 300 V and 50 A , together with an extended operation temperature range. The project intends to provide the technology requested by industry and gathered in this work.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

This paper presents the work done together with the European space power industry, gathering their needs and requirements to tackle the next HP space missions. SiC technology is identified as a potential technology to overcome the HP challenges to come, so the most interesting applications for the SiC are listed, together with the main drivers to optimize in each one. The applications are classified according to the requirements of industry, but also following the ESA innovation categories. This provides SiC manufacturers a clear understanding of the potential applications as well as the development roadmap to follow when targeting a specific application. The author also presents the SiC technology demonstrators developed in ESA to answer the main technology and performance questions industry has.

This work is a connection between the SiC manufacturers and the potential end users of their products, the space power industry. It will help them to better understand the needs the space power industry has, and adapt their products to provide the most desirable technical features. If done, a new business case could open for the SiC devices. It also shows the involvement of the author and ESA in the matter, offering themselves to assist on the adoption of this technology, as well as on the development of roadmaps and product definitions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.97.pdf

Nasa, "NASA's lunar exploration program overview," 2020.

European Space Agency (ESA), "ESA lunar exploration journey." Accessed: May 14, 2024. [Online]. Available:

European Space Agency (ESA-ESTEC) Requirements & Standards Division, "ECSS-Q-ST-30-11C-Rev.2," 2021.

J. W. Kolar and G. I. Ortiz, "Solid state transformer concepts in traction and smart grid applications." [Online]. Available:

X. She, A. Q. Huang, and R. Burgos, "Review of solid-state transformer technologies and their application in power distribution systems," IEEE J Emerg Sel Top Power Electron, vol. 1, no. 3, pp. 186-198, Sep. 2013, doi: 10.1109/JESTPE.2013.2277917.

A. Rujas, V. M. Lopez, I. Villar, T. Nieva, and I. Larzabal, "SiC-hybrid based railway inverter for metro application with 3.3 kV low inductance power modules," in IEEE Energy Conversion Congress & Expo (ECCE), 2019.

J. Zhu, H. Kim, H. Chen, R. Erickson, and D. Maksimovic, "High efficiency SiC traction inverter for electric vehicle applications," in IEEE Applied Power Electronics Conference and Exposition (APEC), IEEE, 2018.

A. Matallana et al., "Power module electronics in HEV/EV applications: New trends in widebandgap semiconductor technologies and design aspects," Renewable and Sustainable Energy Reviews, vol. 113, p. 109264, Oct. 2019, doi: 10.1016/J.RSER.2019.109264.

W. Perdikakis, M. J. Scott, K. J. Yost, C. Kitzmiller, B. Hall, and K. A. Sheets, "Comparison of Si and SiC EMI and efficiency in a two-level aerospace motor drive application," IEEE Transactions on Transportation Electrification, vol. 6, no. 4, pp. 1401-1411, Dec. 2020, doi: 10.1109/TTE.2020.3010499.

U. Nasir et al., "A SiC based 2-Level power converter for shape-and-space-restricted aerospace applications," in IEEE 13th International Conference on Power Electronics and Drive Systems (PEDS)., 2019.

K. E. Bozak, L. R. Piñero, R. J. Scheidegger, M. V Aulisio, M. C. Gonzalez, and A. G. Birchenough, "High input voltage, silicon carbide power processing unit performance demonstration," in AIAA Propulsion & Energy Conference, 2015. [Online]. Available:

R. J. Scheidegger, W. Santiago, K. E. Bozak, L. R. Piñero, and A. G. Birchenough, "High power silicon carbide (SiC) power processing unit development," 2015. [Online]. Available:

A. Lopez, P. F. Miaja, M. Arias, and A. Fernandez, "Circuit Proposal of a Latching Current Limiter for Space Applications Based on a SiC N-MOSFET," IEEE J Emerg Sel Top Power Electron, vol. 10, no. 5, pp. 5474-5485, Oct. 2022, doi: 10.1109/JESTPE.2022.3163585.

D. Marroquí et al., "Towards higher current and voltage LCLs," in 13th European Space Power Conference (ESPC) , 2023.

A. F. Witulski et al., "Single-event burnout mechanisms in SiC power MOSFETs," IEEE Trans Nucl Sci, vol. 65, no. 8, pp. 1951-1955, Aug. 2018, doi: 10.1109/TNS.2018.2849405.

R. A. Johnson et al., "Unifying concepts for ion-induced leakage current degradation in silicon carbide Schottky power diodes," IEEE Trans Nucl Sci, vol. 67, no. 1, pp. 135-139, Jan. 2020, doi: 10.1109/TNS.2019.2947866.

A. Witulski et al., "Single-event effects in silicon carbide high voltage power devices for lunar exploration," 2023.

A. Witulski et al., "Single-Event Effects in Silicon Carbide High Voltage Power Devices for Lunar Exploration," in Annual NASA Electronic Parts and Packaging (NEPP), 2023.

C. Martinella et al., "Heavy-ion induced single event effects and latent damages in SiC power MOSFETs," Microelectronics Reliability, vol. 128, Jan. 2022, doi: 10.1016/j.microrel.2021.114423.

A. Sengupta et al., "Development of SEB-immune high voltage SiC power devices for lunar applications," in Annual NASA Electronic Parts and Packaging (NEPP), 2022.

L. M. Tolbert, "Increasing switching performance of 10 kV SiC MOSFETs for medium voltage applications," in Swiss Chapter of IEEE PELS Webinar, 2022.

V. Pala et al., " 10 kV and 15 kV silicon carbide power MOSFETs for next-generation energy conversion and transmission systems," in IEEE Energy Conversion Congress and Exposition (ECCE) , 2014.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 107-114

doi: 10.4028/p-K3RxtO

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-02-18

Accepted:
2025-03-12

Online:
2025-09-12

SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space

The original version of this paper is available on https://www.scientific.net/KEM.1024.107.pdf

Antxon Arrizabalaga

European Space Agency (ESA), Netherlands

antxon.arrizabalaga@esa.int

Keywords: Space, high-power motor drive, SiC, high-power module, area reduction.

Abstract

This work proposes SiC half-bridge modules to improve the high-power motor drive systems in space. The high current capability of the modules allows to reduce the number of required components, reducing the required PCB area. Using analytical loss calculation models the losses and the efficiency of the Si and SiC configurations is calculated, obtaining better results with the SiC due to the lower conduction losses, even if the voltage rating of the devices is severely derated to avoid single event burnouts in the space application.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.107.pdf

The new missions in space will require high power (HP), as the main space agencies aim to land on the moon and even create a permanent lunar base [1], [2]. Among these HP systems, electric motor drives gain relevance for their application in launchers, electric pump control, lunar landers, cargo ships and the heavy machinery that will be required in the permanent lunar base construction and maintenance.

This work considers a three phase (3P) 56 kW electric motor drive, using the 2 level (2L) 3P voltage source converter (VSC) topology. As most HP motor drives in space, it has a dedicated battery, which operates at 150 V when fully charged, but can go as low as 100 V in the end of discharge. Fig. 1 shows the electrical architecture of the system. At the lowest input voltage and maximum power, the 2L 3P VSC must operate at , creating a challenging environment for current space technology.

Following the approach in terrestrial HP electronics, SiC devices are being considered to improve the technical figures of HP systems in space, mostly due to the limitations of the space qualified Si technology. Even if SiC devices have already been tested in space systems [3],[4],[5], [6], they are susceptible to single event effects (SEE) and need to derate their voltage considerably to avoid SE burnouts (SEB) [7], [8], [9]. The SEE test results analyzed in the bibliography [7], [8], [9], show 1200 V SiC MOSFETs can suffer degradation at blocking voltages as low as 300 V at high Liner Energy Transfers (LET). This rules 650 V SiC devices out of this application, and forces to use 1200 V SiC MOSFETs, but it also opens up the opportunity to use HP half-bridge (HB) modules containing these 1200 V SiC MOSFETs, as specified in Fig. 1.

Fig. 1. The electrical architecture for high-power motor drives with HP HB SiC modules in space.

Fig. 1. The electrical architecture for high-power motor drives with HP HB SiC modules in space.

Fig. 2. The selected devices with dimensions, (a) Si MOSFET and (b) SiC half-bridge module.

Fig. 2. The selected devices with dimensions, (a) Si MOSFET and (b) SiC half-bridge module.

Table 1. Main ratings of the selected devices.

Parameter
Si MOSFET
SiC module
Unit

Part number
IRHNS9A7264
FF2MR12W3M1H_B11
/

Technology
Space qualified Si MOSFET
Industrial SiC half-bridge module
/

Vds(max)
250
1200
V

Id(max) continuous
(Tj = 100°C for Si − 175°C for SiC)
52
400
A

Required number
36
3
# of discretes/modules

The paper compares the converter setup for a 56 kW motor drive with space qualified Si MOSFETs and 1200 V SiC HP HB modules, in terms of printed circuit board (PCB) design, as well as the thermal and electrical performance. The next steps to follow up on the project are also presented.

Converter Setup

The original version of this paper is available on https://www.scientific.net/KEM.1024.107.pdf

Device Selection. 250 V components must be used to switch 150 V in space, applying the derating rules [10]. To reach the required RMS current in the maximum power, 300 Arms, and considering IRHNS9A7264 Si MOSFETs with 52 A continuous maximum current at , 6 parallel devices must be used, 12 per phase to get the high and low sides, and 36 in total to get the three phases of the 2L 3P VSC. Using the FF2MR12W3M1H_B11 1200 V SiC HB module, with 400 A continuous maximum current at only 3 modules are required to form the whole 2 L 3 P VSC. The selected driver for both configurations is the space qualified high and low side, HV and high speed RIC7S113 driver. In the case of the SiC modules, two drivers per module are used, to double the gate current capability. Fig. 2 shows the two selected devices, together with their dimensions. Table 1 shows their main ratings. It should be noted the Si device is surface mounted, while the SiC module is screwed directly to the cooling system, and the PCB press fitted on top.

PCB Layout. The power stage design is shown in Fig. 3, using the space qualified high and low side, HV and high speed RIC7S113 driver, and the required bootstrap components. In the case of the SiC modules, the second driver is connected directly underneath the main driver in the bottom layer. This is possible because the SiC modules are connected to the PCB by press-fitting, and the generated gap is enough to place the second driver. By doing so, no extra PCB area is required and the gate current is doubled. In the Si configuration, this cannot be done because the Si MOSFET is SMD, thus the PCB must be directly connected to the cooling system to ensure thermal dissipation. The converter with the 36 Si MOSFETs and their driving components require in the PCB, Fig. 3(a). However, the configuration with the larger SiC HB modules, only needs , as only three modules and driving components are needed. The required PCB area is reduced with the use of SiC HB modules.

Fig. 3. PCB area required for the motor drive power stage with (a) space graded Si MOSFETs and (b) SiC modules.

Fig. 3. PCB area required for the motor drive power stage with (a) space graded Si MOSFETs and (b) SiC modules.

DC Losses and Thermal Restrictions. The DC resistance of any conductor is proportional to its length. Following this principle, we can deduce the DC resistance thus the DC losses in the PCB required by the Si MOSFETs will be around 2.5 times higher than the ones in the PCB with SiC modules. These losses are proportional to the square of the RMS current, so not neglectable at all in such high-current systems.

The second consideration is the thermal design of the two configurations. In the first design, the Si devices are SMD, dissipating heat directly to the PCB. This heat should be added to the one directly generated in the PCB by the DC losses mentioned before. However, having all the components in one side of the PCB would allow to directly connect the PCB to the cooling system, making the thermal conduction of the PCB easier.

On the contrary, the SiC modules are optimized for thermal performance, having a thermal plate directly conducting the heat to the cooling system. In fact, the modules are screwed to it, connecting the PCB on top by press-fitting it. Again, this makes the thermal management of the SiC modules easier but complicates the dissipation of the DC losses in the PCB.

Finally, if the device thermal resistance is compared, a big difference can be observed. The junction to PCB thermal resistance of the Si MOSFETs is , while it is , 12.5 times less, for each MOSFET in the SiC HB module. Each SiC module is composed of two parallel dies in the high side, and two parallel dies in the low side, composing 4 dies (MOSFETs) per module and 12 in total in the whole converter. In the case the two configurations generate the same losses, which it is seen to be false in the following section, each Si MOSFET would have to dissipate less power than each SiC MOSFET because of their parallel connection. However, if both use the same cooling system, the temperature increase in each Si MOSFETs would be 4 times higher than in each SiC MOSFET, showing the advantages of the thermal optimization of the SiC modules.

Electrical Performance

The original version of this paper is available on https://www.scientific.net/KEM.1024.107.pdf

Analytical Loss Model. The electrical performance of the two configurations is tested using analytical equations to calculate the losses. The conduction losses are calculated using the generic equation (1),

is the forward voltage drop, which is considered 0 V simplifying to (2) in MOSFET technology.

calculation is done for the 2L 3P VSC converter, considering sinusoidal AC current and the conduction times of the high side and low side switches for all the fundamental period [11]. (3) is synthesized being the modulation index and the power factor of the inverter.

Next, the switching losses of the MOSFETs are calculated. The calculations are based on (4), where the on and off transitions are separated, being the turn-on time, and the turn-off time. is the switching frequency of the converter.

The switching times are represented depending on the gate charges, the gate to source charge , the gate to drain charge and driving circuit characteristics such as the gate current . Considering the turn-on circuit and the turn-off circuit are the same, (5) is derived, and replacing (5) and for the 2L 3P VSC in (4), the expression (6) is obtained for the switching losses.

Next, the body diode losses are calculated. In the 2L 3P VSC the body diodes conduct during dead times , which is considered constant, 500 ns , in this work. First, the duty cycle of the diode is calculated with respect to the switching period (7).

Then, the average and RMS currents are calculated for the diode, in order to populate (1). The conduction time of the diode is constant during the fundamental period, and a diode only conducts during one half of the fundamental period, so the conduction losses of the diode are calculated with (8), being the forward voltage drop of the body diode, and the conduction resistance, which is obtained from the conduction characteristic plot in the datasheets.

Last, the switching losses of the diodes are also calculated, which are considered to occur due to the reverse recovery charge, , and shown in (9) [12]. Remember each diode only participates during half of the fundamental period. is considered negligible in the case of the SiC MOSFETs, so the diode switching losses are neglected for the SiC converter.

For the Si , and even if the manufacturer only provides the data for the maximum current, the reverse recovery charge increases with the forward current, , of the diode [12]. For this loss model, the is considered to increase with the square root of in the diode, until the data provided by the manufacturer is reached. So a specific is considered for each operating point, depending on the current conducted by the diode.

Table 2. Main technical characteristics of the selected devices at , obtained from the manufacturer datasheets.

Parameter | Si MOSFET | SiC module | Unit
QGS | 64 | 400 | nC
QGD | 48 | 25 | nC
Qrr(If = 50 A) | 4.864 | / | μC
RDS(on) (Tj = 100 °C for Si − 175 °C for SiC) | 28.9 | 3.09 | mΩ

Calculating a variable only causes marginal differences in the losses, however, using this approach avoids penalizing the Si in low power operation conditions, which would happen if the full losses were considered. In reality, the diode only stores the corresponded to the conducted forward current in each operation condition, thus generating lower switching losses in low power operations.

The main technical characteristics to populate the analytical model are shown in Table 2, obtaining the data from the manufacturers datasheets, and considering the capacity characteristics constant at the operation voltage. In the case of the Si , the manufacturer already provides the gate charges for different operation voltages. For the SiC modules, the charges are obtained from the capacity characteristics plot for , and using the expressions (10) and (11) from [13], that again assume the interelectrode capacitances constant.

Analytical Loss Model Results. The analytical model presented before is used to calculate the losses and the efficiency of both configurations at the lowest input voltage, thus at the highest current, showing the results in Fig. 4. First, all the power range is tested at 20 kHz switching frequency, Fig. 4(a). At low power, the current in the converter is low, so high efficiency is achieved with the SiC configuration. The Si configuration is penalized by the body diode switching losses which are neglected in the SiC configuration. As the power thus the current is increased, the conduction losses become much more relevant. The better conduction resistance, , of the SiC modules makes the difference in efficiency, improving it around when compared to the Si configuration at maximum power.

However, this first results already show the good switching performance of the Si configuration, taking advantage of the parallel devices, but mostly the individual driving of each device, minimizing the switching losses. The Si configuration achieves lower switching losses at high power, even if the quadratic relation to the current highly affects conduction losses, completely dominating the switching losses as the power is increased.

The good switching performance of the Si configuration is shown in Fig. 4(b), in where the losses of the two configurations are calculated for the full power, but at different switching frequencies. It is seen the switching losses at full power are very similar for both configurations, but the conduction losses are the ones making all the difference. In fact, it is desirable to keep the switching frequency as low as possible, to reduce the losses of the system. Selecting a switching frequency about 10 to 15 times higher than the fundamental frequency of the inverter should be enough for such HP motor drives. Once again, this analysis shows the dominance of the conduction losses over the switching losses in HP systems in space.

Fig. 4. Power loss distribution and efficiency of the motor drive with SiC modules and Si MOSFETs, for (a) different operation powers at 20 kHz switching frequency and (b) different switching frequencies at maximum power.

Fig. 4. Power loss distribution and efficiency of the motor drive with SiC modules and Si MOSFETs, for (a) different operation powers at 20 kHz switching frequency and (b) different switching frequencies at maximum power.

Fig. 5. Proof-of-concept prototype for the next steps in the project (a) conceptual diagram, (b) the PCB with the SiC HB modules underneath and (c) a close look to the SiC HB modules screwed to the cooling system with the PCB press-fitted on top.

Fig. 5. Proof-of-concept prototype for the next steps in the project (a) conceptual diagram, (b) the PCB with the SiC HB modules underneath and (c) a close look to the SiC HB modules screwed to the cooling system with the PCB press-fitted on top.

Conclusion and Future Work

The original version of this paper is available on https://www.scientific.net/KEM.1024.107.pdf

This work proposes 1200 V SiC HB modules to improve the HP motor drives in space. Using the high current capability of SiC HB modules the systems can be designed using a single module per phase, reducing the required PCB area . In addition, analytical loss calculations confirm the conduction losses are the most dominant form of losses in this type of application, so reducing these losses becomes key to improve the efficiency. The lower of the SiC modules, when compared to the space qualified Si MOSFETs allow to increase the efficiency of the system significantly.

Their specific design for HP, with the thermal conduction pad to directly screw the modules to the cooling system, as well as the high current capability make the SiC modules the perfect devices to overcome the challenges faced by Si devices in HP systems in space.

A proof-of-concept prototype has been designed and built, Fig. 5, combining the SiC HB modules and space qualified drivers. The next steps will focus on proving these modules can be driven with space qualified drivers, by testing the prototype, enabling the easy technological transition to the SiC for space industry. Overall, following the terrestrial trend to use HP SiC modules in HP systems seems logical also in space, even if the 1200 V voltage rating needs to be derated significantly.

References

The original version of this paper is available on https://www.scientific.net/KEM.1024.107.pdf

Nasa, "NASA's lunar exploration program overview," 2020. [Online]. Available: https://www.nasa.gov/wp-content/uploads/2020/12/artemis_plan-20200921.pdf.

European Space Agency (ESA), "ESA lunar exploration journey." Accessed: May 14, 2024. [Online]. Available:

K. E. Bozak, L. R. Piñero, R. J. Scheidegger, M. V Aulisio, M. C. Gonzalez, and A. G. Birchenough, "High input voltage, silicon carbide power processing unit performance demonstration," in AIAA Propulsion & Energy Conference, 2015. [Online]. Available:

R. J. Scheidegger, W. Santiago, K. E. Bozak, L. R. Piñero, and A. G. Birchenough, "High power silicon carbide (SiC) power processing unit development," 2015. [Online]. Available:

A. Lopez, P. F. Miaja, M. Arias, and A. Fernandez, "Circuit Proposal of a Latching Current Limiter for Space Applications Based on a SiC N-MOSFET," IEEE J Emerg Sel Top Power Electron, vol. 10, no. 5, pp. 5474-5485, Oct. 2022, doi: 10.1109/JESTPE.2022.3163585.

D. Marroquí et al., "Towards higher current and voltage LCLs," in 13th European Space Power Conference (ESPC), 2023.

A. F. Witulski et al., "Single-event burnout mechanisms in SiC power MOSFETs," IEEE Trans Nucl Sci, vol. 65, no. 8, pp. 1951-1955, Aug. 2018, doi: 10.1109/TNS.2018.2849405.

R. A. Johnson et al., "Unifying concepts for ion-induced leakage current degradation in silicon carbide Schottky power diodes," IEEE Trans Nucl Sci, vol. 67, no. 1, pp. 135-139, Jan. 2020, doi: 10.1109/TNS.2019.2947866.

A. Witulski et al., "Single-event effects in silicon carbide high voltage power devices for lunar exploration," 2023. [Online]. Available:

O'Sullivan, D. (1993). Space Power Electronics, Design Drivers (I). EPE Journal, 3(2), 8592. .

B. Ozpineci, L. M. Tolbert, S. K. Islam, and Md. Hasanuzzaman, "Effect of Silicon Carbide (SiC) power devices on HEV PWM inverter losses," in .The 27th Annual Conference of the IEEE Industrial Electronics Society (IECON), IEEE, 2001.

N. Shammas, D. Chamund, and P. Taylor, "Forward and reverse recovery behavior of diodes in power converter applications," in Proc. 24th Int. Conf. Microelectronics (MIEL 2004), Niš, Serbia and Montenegro, 2004, pp. 1-10.

Maniktala, S. (2012). Conduction and Switching Losses. In Switching Power Supplies A - Z (pp. 311-341). Elsevier. .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1024, pp 115-121

doi: 10.4028/p-Ssi1Fh

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-10

Revised:
2025-03-26

Accepted:
2025-03-26

Online:
2025-09-12

Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1024.115.pdf

Antxon Arrizabalaga

European Space Agency (ESA), Netherlands

antxon.arrizabalaga@esa.int

Keywords: SiC, LCL, high power distribution, space electronics, high power packaging.

Abstract

High power and high voltage distributions will be required in space, but the necessary latching current limiters to manage the loads are not feasible with current Si P-MOSFET technology in the required power and voltage range. The generated losses and the number of parallel components make the system performance unacceptable. SiC N-MOSFETs are proposed as an alternative, due to their superior current ratings, reduced conduction resistance and increased thermal limits. Using these characteristics, two preliminary designs are proposed with SiC N-MOSFETs, one to optimize the power losses in the nominal operation and the other to reduce the required number of parallel devices and increase the allowable time under fault of the system. Both configurations overcome the challenges brought by the high power and high voltage distributions in space, reducing the losses and the complexity of the system while increasing the time under fault. This work shows how SiC technology can enable high power and high voltage distribution in space, while highlighting the importance of high power packages and thermal characteristics in certain applications.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1024.115.pdf

The demand for high-power (HP) electronic systems is growing in space, as the main space agencies are designing more ambitious space and lunar missions [1], [2]. All these HP payloads will require HP distribution, which will have to be high voltage (HV), preferably over 100 V . The latching current limiters (LCL) are used for managing the loads in space electrical distribution systems being the Si P-MOSFETs the preferred devices due to their easy control. However, space graded Si P-MOSFETs are limited in terms of conduction resistance and blocking voltage, generating unacceptable losses if used at HP [3].

In this contest, the use of SiC devices in space HP systems is being studied [4],[5],[6], [7]. However, and due to their susceptibility to single event burnouts (SEB) at high blocking voltage, their operation voltage is significantly derated forcing to use 1200 V SiC devices below 300 V in space environments [8], [9], [10]. Although the 1200 V voltage rating is highly popular in terrestrial applications and provides a wide variety of products with different characteristics, SiC P-MOSFETs are marginal, being the vast majority SiC N-MOSFETs.

The driving of N-channel MOSFETs for LCL was solved in [11], [12], and SiC N-MOSFETs have been proposed and demonstrated for a class 10 LCL [3], achieving improved performance when compared to Si P-MOSFETs. This work studies the possibility to further increase the power of the distribution line, up to 10 kW while following the operation defined for a class 10 LCL [13].

Study

The original version of this paper is available on https://www.scientific.net/KEM.1024.115.pdf

Operation of the LCL. A 120 V distribution line is considered to supply the HP payloads. A constant 83 A current is distributed in the line during nominal operation, reaching 10 kWs . When a fault occurs in one of the loads, the load current in the line is increased to the limiting value following the regulation of class of the nominal current [13], defining the operation under fault in 116.2 A . The minimum current limiting time is 1.5 ms , so the LCL must operate limiting the fault current at least for that period.

Fig. 1. Operation of the proposed HP LCL.

Fig. 1. Operation of the proposed HP LCL.

The junction temperature, , of the device must remain below the maximum permitted value for each device, following the derating standards for electrical, electronic and electro-mechanical (EEE) components [14]. After this time, the power line can be powered down, or kept on until 3 ms , if the limit is not reached, when the whole line needs to be powered down if the fault is not cleared. Fig. 1 shows the current profile in the distribution line under study, highlighting every operation point. The overload event with the current overshoot is not considered for this analysis.

To calculate the power losses in the analyzed configurations, as well as the , the analytical equations proposed in are [15] used. The power losses under nominal operation are calculated with (1), being the conduction resistance and the nominal value of the distribution current under nominal operation, 83 A , times -0.5 ms to 0 ms in Fig. 1.

When the fault occurs, times 0 ms to 1.5 ms in Fig. 1, the power device works in linear mode, blocking the full line voltage, and conducting the limiting current, . The power loss in the device is expressed as (2).

For the thermal modeling, a Cauer network is used, considering an ideal heat-sink for every configuration. Datasheet values are used to model the transient temperature evolution populating the Cauer model, using the transient thermal impedance graphs provided by the manufacturers. The junction temperature is calculated using (3), where represents the steady state temperature of the junction during nominal operation, and the temperature increment in the device during the operation under fault.

The junction temperature in the nominal operation is calculated using the power losses in nominal operation , and the junction to case thermal resistance in (4).

Then the temperature rise during time is calculated during the fault operation with ( 5 ), modeling it like a RC network and considering the thermal capacitance obtained from the transient thermal impedance graphs provided by the manufacturers.

Device Selection. A Si P-MOSFET and two SiC N-MOSFETs are selected for the study, Table 1. Due to the low HV availability of the Si P-MOSFETs, the selected device has low current capability, and high . This leads to high losses in nominal operation, as well as a high required component count in parallel. High current SiC devices are selected, with the objective of only using a single device in the HP LCL.

Table 1. Main technical characteristics of the selected devices.

Parameter | IRFP9240 | AIMBG120R010M1 | SCT020H120G3AG
Technology | Si P-MOSFET | SiC N-MOSFET | SiC N-MOSFET
Name | Si | SiC 1 | SiC 2
Vds [V] | 200 | 1200 | 1200
Id (Tj = 100 °C) [A] | 7.5 | 150 | 128
RDS(on) [mΩ] | 500 | 8.7 | 9.3
Tj(max)[°C] | 150 | 175 | 200
RTh(J−C)[°C/W] | 0.83 | 0.13 | 0.2
CTh(J−C)[J/W] | 0.018 | 0.019 | 0.075

Fig. 2. Packages of the selected devices with their dimensions, (a) Si, (b) SiC 1 and (c) SiC 2.

Two different packages are compared, but also considering the maximum limit of each device. [14] states is the maximum junction temperature for EEE components, or , whichever is more restrictive. However, an exception is made in devices with . In such cases the criteria should prevail. Exploring the high capability of SiC MOSFETs, a SiC device with small SMD package and is selected, while the other SiC device is a SiC MOSFET with a HP package and extended temperature range. Having a HP package increases the footprint area, but slows down the thermal dynamic due to the increased . Table 1 shows the main device characteristics, while Fig. 2 shows the packaging of each device as well as their dimensions.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1024.115.pdf

Nominal Operation. 16 parallel Si devices are required to operate the HP distribution line due to the current rating and the current during the fault operation. Dividing the nominal operation current between the 16 devices, and applying (1), the power losses in the nominal operation point are calculated to be 215 W . A single SiC device is required considering their current rating for both devices. Doing the same calculation, the LCL with SiC 1 consumes 60 W while the LCL with SiC 2 consumes 64 W in normal operation.

However, the three configurations consume and must dissipate the same amount of power during a fault, 13944 W, calculated with (2). This power is independent from the device, being the junction temperature the limiting factor during a fault, as shown in Fig. 1.

Thermal Simulation. Equation (3) is used to calculate the evolution during a fault for the three configurations. Even if the limit is extended to and to for SiC 1 and SiC 2 devices respectively using the exception in [14], both SiC devices cannot withstand the thermals stress of a fault during 1.5 ms with a single device. On the contrary, the 16 paralleled Si devices do not require any further change due to the thermal stress.

Fig. 3. Junction temperature evolution of the analyzed devices during a fault event.

Fig. 3. Junction temperature evolution of the analyzed devices during a fault event.

Simulation shows 8 parallel devices are required for SiC 1, while 2 parallel devices are just not enough for SiC 2, requiring 3. Fig. 3 shows the calculated evolution during a fault for the three configurations, together with the thermal limits. These results show a clear dependency on the thermal capacitance during the fault operation, rather than on the thermal resistance.

Using (5) at the end of the minimum current limiting time, , for different and couples, simulating the different characteristics of devices and packages, and normalizing the temperature increase , Fig. 4 can be obtained. The plot shows how the temperature increase barely changes even if the thermal resistance is increased, when the thermal capacitance is high. On the contrary, at low , even a small increase in the causes a big change in the increased temperature. This is what forces SiC 1 to parallel up to 8 devices even with a better than SiC 2. The effect of the can be clearly seen, damping the thermal response when exposed to short but high power dissipation periods. So, it is concluded the use of the HP packages with high thermal capacitance is key for their use in LCLs, or in the applications with high transients in the load current thus in the thermal stress, helping to reduce the temperature increase in the junction during the short high power dissipation periods.

Fig. 4. Normalized junction temperature after limiting the current 1.5 ms for different and .

Fig. 4. Normalized junction temperature after limiting the current 1.5 ms for different and .

Final Configuration. As seen in Fig. 3, the thermal limits of the application force the parallelization of several devices. This affects both the required PCB area for each configuration, as well as the nominal operation losses. The dimensions of each device are shown in Fig. 2, but the required area of the PCB for each configuration is shown in Fig. 5, considering just the power stage. The control stage must be added to this area, but it is not discussed in this work. Table 2 summarizes all the relevant results of the three configurations.

The configuration with the Si devices requires , while the configuration with SiC 1 only requires , even considering the 8 parallel devices. That is an reduction in the required area. The configuration with SiC 1 uses half of the devices required by the Si configuration, and reduces the power losses in the nominal operation point from 215 W to just 7.5 W . The time before hitting the thermal limit under a fault is the same for both configurations, 1.6 ms , see Fig. 3. These results show a substantial improvement in the performance of the HP LCL by selecting SiC technology, mostly in terms of nominal operation performance, enabling the LCL based HP distribution systems with acceptable losses.

However, if the objective is to reduce the number of required parallel devices for the LCL, and maximize the time under fault the system can withstand, a HP package must be selected due to the higher , as seen in Fig. 4. To achieve these objectives, the configuration with SiC 2 is preferred, only requiring 3 parallel devices and being able to withstand a fault for over 2.3 ms , increasing the time under fault 0.7 ms when compared to the previous configurations. This is due to its extended , but even if the thermal limit of SiC 1 was to be respected, the maximum time under fault for SiC 2 would be 1.83 ms , still 0.23 ms more. This again shows the benefits of using HP high packages. The power losses under nominal operation are 21.35 W , still significantly lower than the configuration with Si , but higher than the losses with SiC 1 due to the reduced number of parallel devices. The required area is less than for the Si , but higher than for the configuration with SiC 1.

Fig. 5. Minimum PCB area required for the power stage of the whole LCL with (a) Si P-MOSFET, (b) SiC 1 and (c) SiC 2, with a 6 to 10 scale.

Fig. 5. Minimum PCB area required for the power stage of the whole LCL with (a) Si P-MOSFET, (b) SiC 1 and (c) SiC 2, with a 6 to 10 scale.

Table 2. Final configuration relevant results.

Parameter | Si | SiC 1 | SiC 2
Required parallel devices | 16 | 8 | 3
Required PCB area [cm²] | 81 | 16.5 | 26
Nominal operation power losses [W] | 215 | 7.5 | 21.35
Maximum time under fault [ms] | 1.6 | 1.6 | 2.3

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1024.115.pdf

LCLs are not feasible in HP and HV distributions in space, in the range of tens of KWs, if Si P-MOSFET technology is used, because the losses are too high, the number of required parallel devices takes too much area and complicates the design. However, this paper shows a HP LCL for space is feasible if SiC N-MOSFET technology is used due to the higher current rating, the highly improved and the extended .

If the power losses in the nominal operation are to be reduced, the SiC N-MOSFET with the lowest should be selected, and use parallel devices to distribute the losses until the thermal limit is met. The paralleling strategy will further reduce the power losses in the nominal operation. However, if the number of parallel devices is to be minimized, and the time under fault maximized, this study shows the of the package should be considered. Using HP packages with high slow down the thermal dynamics of the LCL, allowing to reduce the required parallel devices thus simplifying the design and increasing the time under fault. SiC technology will enable LCLs for the HP and HV distributions in space, providing designers with several optimized solutions depending on the objectives of the missions.

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The original version of this paper is available on https://www.scientific.net/KEM.1024.115.pdf

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Keywords Index

A

And Reliability Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Area Reduction SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space

Au Nanoparticles Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

Avalanche SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

B

Bias Temperature Instability (bti) Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Body Diode Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Bti 28b58916-5532-453e-b189-a47ea63cb0e0

Business Case SiC in Space: Potential High-Power Application Survey

C

Channel Leakage TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Charge To Breakdown Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Chemical Vapor Deposition 28b58916-5532-453e-b189-a47ea63cb0e0

Cmos 28b58916-5532-453e-b189-a47ea63cb0e0

D

Degradation Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Deposited Oxide Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Drift Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

E

Electric Field Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

Extrinsic Failure Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

F

Field Effect Mobility 28b58916-5532-453e-b189-a47ea63cb0e0

Flat Band Voltage Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

G

Gate Leakage Current Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Gate Oxide Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

Gate Oxide Lifetime Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Gate Switching Instability (gsi) Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Gate Switching Stress (gss) Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Gate-leakage Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

H

High Energy Physics 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

High Power SiC in Space: Potential High-Power Application Survey

High Power Distribution Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

High Power Packaging Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

High Temperature All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

High Temperature Gate Bias Stress (htgb) TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

High Voltage Direct Current Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

High-power Module SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space

High-power Motor Drive SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space

I

Industry SiC in Space: Potential High-Power Application Survey

Interface Trap Density Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Interface Traps 28b58916-5532-453e-b189-a47ea63cb0e0

L

Lcl Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

Lgad 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

M

Modular Multilevel Converter Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Mosfet 28b58916-5532-453e-b189-a47ea63cb0e0

N

Negative Bias Temperature Instability (nbti) TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Nzfmr All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

O

On-state Resistance Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Overcurrent Turn-off Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

P

Particle Detection 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Photodiode SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Pin Diode 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Plasmonics Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

Positive Bias Temperature Instability (pbti) TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Power Converter Application Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Power Electronics SiC in Space: Potential High-Power Application Survey

Q

Quantum Magnetometry All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

R

Radiation 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Reliability 28b58916-5532-453e-b189-a47ea63cb0e0

Reverse Recovery Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Robustness Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

S

Screening Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Self-powered Photodetectors Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

Semiconductor SiC in Space: Potential High-Power Application Survey

Short Circuit Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

SiC SiC in Space: Potential High-Power Application Survey; SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space; Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

SiC Diodes All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

SiC Engineered Substrate Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

SiC Mosfet Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications; Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Silicon Igbt Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Single Photon SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Smartsic Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Space SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space

Space Electronics SiC in Space: Potential High-Power Application Survey; Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

Space Power SiC in Space: Potential High-Power Application Survey

Spatial Uniformity SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Subthreshold Swing TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Surge Current Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Sustainable Devices Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

Switching Energy Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

T

Tcad Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs; Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Threshold Voltage Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems; 28b58916-5532-453e-b189-a47ea63cb0e0

Time-dependent Dielectric Breakdown (tddb) TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Transfer Characteristics 28b58916-5532-453e-b189-a47ea63cb0e0

U

Uv Detector SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Authors Index

A

Agarwal, A. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules; 28b58916-5532-453e-b189-a47ea63cb0e0

Aghayan, M. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity; All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Aichinger, T. Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Alaluss, M. Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Alatise, O. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Allion, G. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Allridge, E. All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Arrizabalaga, A. SiC in Space: Potential High-Power Application Survey; SiC Half-Bridge Modules to Improve Efficiency and Reduce Area of High-Power Motor Drives in Space; Latching Current Limiter for High-Power Distribution in Space Enabled by SiC N-MOSFET

Ashik, E. 28b58916-5532-453e-b189-a47ea63cb0e0

B

Barletta, P. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Basler, T. Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs; Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Bellotti, E. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Bera, L. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Bhattacharya, M. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Böhm, C. Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

C

Camalleri, M. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Castorina, M. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Chand, U. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Chien, Y. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Chung, S. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

D

Derenge, M. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

E

Elsayed, A. Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

F

Fayed, A. 28b58916-5532-453e-b189-a47ea63cb0e0

Feil, M. Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Fidler, T. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Floros, K. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

G

Gammon, P. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Garrett, G. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Ghandi, R. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity; All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Goel, S. Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Gong, X. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Goswami, S. All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Gupta, U. 28b58916-5532-453e-b189-a47ea63cb0e0

H

Haber, C. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Habersat, D. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Heimler, P. Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Holland, S. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Hosseinzadehlish, M. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Hou, S. TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Houshmand, S. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

I

Isukapati, S. 28b58916-5532-453e-b189-a47ea63cb0e0

J

Jahdi, S. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Jin, M. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

K

Kaplan, W. TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Kumar, D. Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

Kumar, S. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

L

Lee, B. 28b58916-5532-453e-b189-a47ea63cb0e0

Lenahan, P. All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Liu, T. 28b58916-5532-453e-b189-a47ea63cb0e0

Ludtke, I. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

Lundgren, C. TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

Lutz, J. Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

M

Misra, V. 28b58916-5532-453e-b189-a47ea63cb0e0

Morgan, A. 28b58916-5532-453e-b189-a47ea63cb0e0

Muth, J. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Mysore, M. Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs; Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

N

Nouketcha, F. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

O

Oberdieck, K. Dynamic Characterization and Robustness of SiC MOSFETs Based on SmartSiC ™ Engineered Substrates

Ortiz-Gonzalez, J. Prospects and Challenges for SiC Power Devices in MMC-VSC-HVDC Applications

P

Pavlidis, S. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Piccioni, A. Dynamic Switching Energy Monitoring during Gate Switching Stress to Evaluate Performance Degradation in Hard Switching Electric Power Conversion Systems

Q

Qian, J. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

R

Ranjan, A. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Reshanov, S. TDDB and HTGB Study of SiC MOSFET with Excessive Channel Leakage

S

Saggio, M. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Sampath, A. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Satapathy, Y. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Schmid, P. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Schuster, J. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Sekely, B. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Sgrignuoli, F. All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Shaddock, D. All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Shi, L. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Shimbori, A. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Singh, N. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Smith, J. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Stucci, S. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Sung, W. 28b58916-5532-453e-b189-a47ea63cb0e0

T

Teker, K. Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

Teker, T. Influence of Gold Nanoparticle Distribution on the Performance of Self-Powered Silicon Carbide Ultraviolet Photodetector

V

VanMil, B. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

Varghese, B. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Viti, I. All Electrical Near-Zero Field Magnetoresistance Magnetometry up to

Voo, Q. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Vudumula, P. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

W

Wang, C. Investigation of Overcurrent Turn-Off Robustness of V SiC MOSFETs

Wang, W. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

White, M. Optimization of Gate Oxide Screening Technology for Commercial SiC Discrete MOSFETs and Power Modules

Wraback, M. SiC Avalanche Photodiodes - Crystal Orientation and Spatial Uniformity

X

Xie, J. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

Y

Yang, T. 07f4aac4-b93b-48b5-9dc9-93f7cddeda55

Yeo, A. Achieving Low , Competitive Performance and Enhanced Post-Stress Flatband Voltage Stability Using Deposited Oxide

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