Silicon Carbide and Related Materials 2021

Selected peer-reviewed extended papers abstracts of
which were presented at the which were presented at the European Conference on
Silicon Carbide and Related Materials
(ECSCRM 2020-2021)

Edited by
Dr. Jean François Michaud
Dr. Luong Viet Phung
Prof. Daniel Alquier
Prof. Dominique Planson

Silicon Carbide and Related Materials 2021

Selected peer-reviewed extended papers abstracts of which were presented at the European Conference on Silicon Carbide and Related Materials (ECSCRM 2020-2021)
October 24-28, 2021, Tours, France

Edited by

Dr. Jean François Michaud, Dr. Luong Viet Phung, Prof. Daniel Alquier and Prof. Dominique Planson

Scientific.Net

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Volume 1062 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

Full text available online at https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp -11-0

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2022-05-18

Online:
2022-05-31

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

The 13th European Conference on Silicon Carbide and Related Materials 2020-2021 (ECSCRM 2020-2021) was held in Tours, France, from October 24th to 28th, 2021. ECSCRM, in alternance with ICSCRM, is the world's premier technical conference series for wide bandgap semiconductor technology based on silicon carbide ( SiC ) and related materials. In this so particular time, where COVID-19 has deeply changed our lives and our way of living for the last two years, we are extremely proud to have received a total of 660 attendees, 460 in presence in Tours and 200 online in an unprecedent hybrid format of the event, including colleagues from 29 countries that participated in this conference to report and discuss the recent progresses of fundamental research and technological achievements in this SiC field. We thank all the plenary and invited speakers for their outstanding presentations as well as all participants for valuable work.

More than 240 papers were presented during the technical sessions: 3 plenary, 14 invited oral, 4 invited poster, 70 contributed oral, and 152 contributed poster presentations. The papers covered most of the current research efforts on SiC domain and topics going from material growth to power device applications. During the technical exhibition, 59 companies and organizations have presented their great achievements, products, and services at their booths, presently or virtually. This clearly demonstrates that industry has a strong interest in SiC and related materials. We thank all the sponsors and exhibitors. Without them, the event would not have been possible. We also specifically thank NOVASiC for the financial support of this publication. The four major chapters of the proceedings are collections of papers in the areas of material growth and wafer manufacturing, characterization and defect engineering, material and device processing, power devices, packaging, and applications. We delight to thank all the reviewers for their work. Their contribution was crucial to maintain the high scientific standards of this publication, that is, for the first time, in open access.

ECSCRM 2020-2021 was endorsed by Université de Tours, CNRS and INSA de Lyon via the implication of GREMAN and AMPERE labs. We would not have been successful without the backstage labor of the many persons from the lab and the great help and availability of both Steering and Technical Program Committees. The conference was financially supported by local public authorities (Tours Metropole and Region Centre Val de Loire) and 14 companies. We would like to take this opportunity to thank them again for their sponsorship and support, especially during this very difficult period with a one year postpone.

ECSCRM and ICSCRM events have explored, presented and discussed the new achievements in the field of wide-bandgap semiconductors focusing on silicon carbide ( SiC ) and other related wide bandgap semiconductors. ECSCRM and ICSCRM steering committees have decided in Tours to have a fusion of the two events. In the future, ICSCRM will bring every year together world-leading scientists, distinguished experts, experienced engineers, and young students working in this field from all over the world. The last two years have been particularly intense for SiC technologies and have seen extremely strong market growth for SiC applications, with an impressive increasing maturity. This reflects the dynamism of both the scientific research part and the actions carried out by the industry. Many challenges await us in the coming years and the conference will also be the opportunity to discuss the future of SiC technologies.

The next conference of the series, ICSCRM 2022, will be held in Davos, Switzerland, from September to , 2022 (www.icscrm2022.org). The conference will be chaired by Prof. Ulrike Grossner (ETH Zürich).

We wish the organizers of the next ICSCRM much success.

The ECSCRM 2020-2021 Publication Committee
Dr. Jean-François MICHAUD, Dr. Luong Viet PHUNG,
Prof. Daniel ALQUIER, Pr. Dominique PLANSON

Conference Chairs and Committees

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Conference Chairs

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Daniel Alquier (University of Tours - GREMAN, FRANCE)
Jean-François Michaud (University of Tours - GREMAN, FRANCE)
Dominique Planson (INSA Lyon - AMPERE, FRANCE)

ECSCRM Steering Committee

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Daniel Alquier (University of Tours, FRANCE)
Danilo Crippa (LPE, ITALY)
Michael Dudley (Stony Brook University, NY, USA)
Gabriel Ferro (Université Claude Bernard, Lyon, FRANCE)
Adam Gali (Budapest University of Technology and Economics, HUNGARY)
Tsunenobu Kimoto (Kyoto University, JAPAN)
Michael Krieger (Friedrich-Alexander Universitat Erlangen-Nürnberg, GERMANY)
Alexander Lebedev (Ioffe Institute, St Petersburg, RUSSIA)
Phil Mawby (University of Warwick, UNITED KINGDOM)
Dethard Peters (Infineon Technologies, GERMANY)
Dominique Planson (INSA Lyon, FRANCE)
Fabrizio Roccaforte (National Research Council Catania, ITALY)
Adolf Schöner (Ascatron, SWEDEN)
Konstantinos Zekentes (Foundation for Research and Technology, Heraklion, GREECE)

ECSCRM Advisory Panel

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Peter Deak
Phillipe Godignon
Hiroyuki Matsunami
Roberta Nipoti
Roland Rupp
John Stoemenos

Local Organizing Committee

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Daniel Alquier (University of Tours - GREMAN, FRANCE)
Jérôme Billoué (University of Tours - GREMAN, FRANCE)
Jean-François Michaud (University of Tours - GREMAN, FRANCE)
Luong Viêt Phung (INSA Lyon - AMPERE, FRANCE)
Dominique Planson (INSA Lyon - AMPERE, FRANCE)
Quê Lan Tran Ngoc (University of Tours - CERTeM, FRANCE)

Local Assistance Committee

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Imen Abdennabi (University of Tours - GREMAN, FRANCE)
Micka Bah (CNRS - GREMAN, FRANCE)
Naima Benyagoub (University of Tours - GREMAN, FRANCE)

Clément Berger (University of Tours - GREMAN, FRANCE)
Frédéric Cayrel (University of Tours - GREMAN, FRANCE)
David Chouteau (CNRS - GREMAN, FRANCE)
Romain Dailleau (University of Tours - GREMAN, FRANCE)
Thomas Defforge (INSA CVL - GREMAN, FRANCE)
Gael Gautier (INSA CVL - GREMAN, FRANCE)
Brice Le Borgne (University of Tours - GREMAN, FRANCE)
Magali Léger (University of Tours - GREMAN, FRANCE)
Clément Mauduit (University of Tours - GREMAN, FRANCE)
Daniela Neacsa (University of Tours - GREMAN, FRANCE)
Rémi Rouffaud (University of Tours - GREMAN, FRANCE)
Priyadarshini Shanmugam (University of Tours - GREMAN, FRANCE)
Damien Valente (University of Tours - GREMAN, FRANCE)
Stella-Marie Ze (University of Tours - GREMAN, FRANCE)

PCO, Website & Communication

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Operated by Vertcom

Award Committee

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Michael Dudley (Stony Brook University, USA)
Ulrike Grossner (ETH, SWITZERLAND)
Andrea Irace (University of Napoli, ITALY)
Phil Mawby (University of Warwick, UK)
Jean-François Michaud (University of Tours, FRANCE)
Fabrizio Roccaforte (CNR-IMM, National Research Council Catania, ITALY)
Luong Viêt Phung (INSA Lyon, FRANCE)

Technical Program Committee

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Materials

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Al Burk (Wolfspeed, A Cree Company, USA)
Didier Chaussende (SIMAP-CNRS, Grenoble, FRANCE)
Danilo Crippa (LPE, ITALY)
Gabriel Ferro (University Claude Bernard, Lyon, FRANCE)
Francesco la Via (CNR-IMM, National Research Council, Catania, ITALY)
Alexander Lebedev (Ioffe Institute, St Petersburg, RUSSIA)
Marc Portail (CRHEA-CNRS, FRANCE)
Adolf Schoner (Ascatron, SWEDEN)
Hidekazu Tsuchida (CRIEPI, JAPAN)

Characterization and Modeling

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Peder Bergman (Linkoping University, SWEDEN)
Michael Dudley (Stony Brook University, USA)
Adam Gali (Budapest University of Technology and Economics, HUNGARY)
Ulrike Grossner (ETH, SWITZERLAND)

Tsunenobu Kimoto (Kyoto University, JAPAN)
Michael Krieger (Friedrich-Alexander-Universitat Erlangen, Nuremburg, GERMANY)
Jean-François Michaud (University of Tours, FRANCE)

Processing

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Daniel Alquier (University of Tours, FRANCE)
Wolfgang Bergner (Infineon Technologies, AUSTRIA)
Peter Gammon (University of Warwick, UK)
Roberta Nipoti (CNR-IMM Bologna, ITALY)
Fabrizio Roccaforte (CNR-IMM, National Research Council Catania, ITALY)
Hiroshi Yano (Univ. Tsukuba, JAPAN)
Konstantinos Zekentes (Foundation for Research and Technology, Heraklion, GREECE)

Devices and Applications

The original version of this paper is available on https://www.scientific.net/MSF.1062.-11.pdf

Alberto Castellazzi (Kyoto University of Advanced Science, JAPAN)
Emmanuel Collard (STMicroelectronics, Tours, FRANCE)
Phillipe Godignon (CNM, Centro Nacional de Microelectronica, Barcelona, SPAIN)
Andrea Irace (University of Naples Federico II, ITALY)
Phil Mawby (University of Warwick, UK)
Andrei Mihaila (ABB, Zurich, SWITZERLAND)
Dethard Peters (Infineon Technologies, GERMANY)
Luong Viêt Phung (INSA Lyon, FRANCE)
Dominique Planson (INSA Lyon, FRANCE)
Mario Saggio (ST, Catania, ITALY)
Yoshiyuki Yonezawa (AIST, JAPAN)

Publication Support

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NOVASiC

SiC & Related Materials Polishing and Epitaxy

Institutional Partners

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Tours
métropole
Val de Loire
CentreVal de Loire
www.regioncentre-valdeloire.fr

Sponsors

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Diamond Sponsor

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Wolf

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Platinum Sponsors

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RIIKTROM

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Gold Sponsors

life.augmented

IIVI

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Powering the futurn

Soitec

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APPLIED MATERIALS

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make possible

NOVASiC

Sponsors

3D. MICROMAC

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GT ADVANCED
TECHNOLOGIES
PTS

Exhibitors

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3D-Micromac
Aehr Test Systems
Aixtron
Annealsys
Beneq
Cameca
Centrotherm
Ceramic Forum
Clas-SiC Wafer Fab
CMC Materials
CS Clean Solutions AG
DISCO
Entegris / Sinmat
Epiluvac
EtaMax
Fraunhofer IISB
GT Advanced Technologies
IBS
Kiselkarbid i Stockholm AB (KISAB)
KLA
Lasertec Corp
LayTec
LPE
Meister Abrasives AG
Mersen
mi2-factory
Nanotronics
Nippon Kornmeyer Carbon Group
Nissin Ion Equipment
NOVASiC
NuFlare Technology

AG Omega Physics
OS TECH CO
Pfeiffer Vacuum
Plasma-Therm
PR Hoffman Machine Products
PTS
Pureon
PVA Crystal Growing Systems
RENA Technologies
Rigaku
Saint-Gobain
Schupp
Semilab
SGL Carbon
Showa Denko
Silvaco
SK Siltron CSS
Soitec
SOMOS
Sumitomo Electric
Tokyo Electron
Toray Research Center
Toyota Tsusho corporation
TRUMPF Hüttinger
Wolfspeed
X-Fab

Virtual booth

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ITES
Toyo Tanso

Table of Contents

Preface

Chapter 1: Material Growth and Wafer Manufacturing

Models for Impurity Incorporation during Vapor-Phase Epitaxy

Kazuhiro Mochizuki, Fumimasa Horikiri, Hiroshi Ohta, Tomoyoshi Mishima

Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

Yann Jousseaume, François Cauwet, Gabriel Ferro

Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Daniel Baierhofer, Bernd Thomas, F. Staiger, B. Marchetti, C. Förster, Tobias Erlbacher

High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer

Ruggero Anzalone, Giuseppe Greco, Fabrizio Roccaforte, Patrick Fiorenza, Nicolo Piluso, Andrea Severino

3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Gabriel Ferro, Taguhi Yeghoyan, François Cauwet, Stéphane Coindeau, Thierry Encinas, Véronique Soulière

A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Daichi Dojima, Moeko Matsubara, Hideaki Minamiyama, Tadaaki Kaneko

The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Brunella Cafra, Nicolo Piluso, Agata Grasso, Aye Aye Moon, Andrea Severino

Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer

Kristijan Luka Mletschnig, Mathias Rommel, Gregor Pobegen, Werner Schustereder, Peter Pichler

Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Rolf Grieseler, Isabella Gallino, Natallia Duboiskaya, Joachim Döll, Deepshikha Shekhawat, Johannes Reiprich, Jorge A. Guerra, Marcus Hopfeld, Hauke L. Honig, Peter Schaaf, Joerg Pezoldt

Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

E. Kodolitsch, V. Sodan, M. Krieger, Nikolaos Tsavdaris

Advances in 200 mm 4H SiC Wafer Development and Production

Ian Manning, Kevin Moeggenborg, Andrey Soukhojak, Jon Searson, Matthew Gave, Gil Chung, Edward Sanchez

Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Haitham Hrich, Matthieu Moret, Olivier Briot, Matthieu Paillet, Jean Manuel Decams, Périne Landois, Sylvie Contreras

Effect of N and AI Doping on 3C-SiC Stacking Faults

Cristiano Calabretta, Viviana Scuderi, Ruggero Anzalone, Annalisa Cannizzaro, Marco Mauceri, Danilo Crippa, Simona Boninelli, Francesco La Via

Impact of N Doping on 3C-SiC Defects

Cristiano Calabretta, Viviana Scuderi, Annalisa Cannizzaro, Ruggero Anzalone, Marco Mauceri, Danilo Crippa, Simona Boninelli, Francesco La Via

Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding

Manuel Kollmuss, Michael Schöler, Ruggero Anzalone, Marco Mauceri, Francesco La Via, Peter J. Wellmann

In Situ Monitoring of Unintentionally Released Nitrogen Gas in the Initial PVT Silicon Carbide Growth Process Using Mass Spectrometry

Jonas Ihle, Peter J. Wellmann

Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride

Marcin Zielinski, Marc Bussel, Hugues Mank, Sylvain Monnoye, Marc Portail, Adrien Michon, Yvon Cordier

Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide

Matthias Arzig, Ulrike Künecke, Michael Salamon, Norman Uhlmann, Peter J. Wellmann

Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues

Marc Portail, Sébastien Chenot, Mahdis Ghorbanzadeh-Bariran, Rami Khazaka, Luan Nguyen, Daniel Alquier, Jean François Michaud

Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy

Tawhid Rana, Gil Chung, Andrey Soukhojak, Meong Keun Ju, Matthew Gave, Edward Sanchez

Review of Sublimation Growth of SiC Bulk Crystals

Peter J. Wellmann, Matthias Arzig, Jonas Ihle, Manuel Kollmuss, Johannes Steiner, Marco Mauceri, Danilo Crippa, Francesco La Via, Michael Salamon, Norman Uhlmann, Melissa Roder, Andreas N. Danilewsky, Binh Duong Nguyen, Stefan Sandfeld

Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Johannes Steiner, Binh Duong Nguyen, Melissa Roder, Andreas N. Danilewsky, Stefan Sandfeld, Peter J. Wellmann

Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Manuel Kollmuss, Johannes Köhler, Hai Yan Ou, Wei Chen Fan, Didier Chaussende, Rainer Hock, Peter J. Wellmann

SiC Mass Commercialization: Present Status and Barriers to Overcome

Victor Veliadis

Séverin Rouchier, Gweltaz Gaudin, Julie Widiez, Frédéric Allibert, Emmanuel Rolland, Kremena Vladimirova, Guillaume Gelineau, Nicolas Troutot, Christelle Navone, Guillaume Berre, Daphnée Bosch, Yen Lin Leow, Alain Duboust, Alexis Drouin, Jean Marc Bethoux, Romain Boulet, Audrey Chapelle, Enrica Cela, Guillaume Lavaitte, Adeline Bouville-Lallart, Laurent Viravaux, Florence Servant, Shivan Bhargava, Shawn Thomas, Ionut Radu, Christophe Maleville, Walter Schwarzenbach

Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Wei Fan, Jeff Lennartz, Peter Schmidt-Sane, Brian Kozak, Bruno Balland, Alex Galyukov, Daria Zimina, Daniel Feezell

Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

Marcin Zielinski, Marc Bussel, Catherine Moisson, Hugues Mank, Sylvain Monnoye, Marc Portail, Adrien Michon, Yvon Cordier

Opening Through 200 mm Silicon Carbide Epitaxy

Danilo Crippa, Mani Azadmand, Marco Mauceri, Silvio Preti, Marco Puglisi, Carmelo Vecchio

Chapter 2: Processing

Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Diego Calvo Ruiz, Carmine Sileno

Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry

Patrick Fiorenza, Corrado Bongiorno, A. Messina, Mario Saggio, Filippo Giannazzo, Fabrizio Roccaforte

Impact of Dislocation on Warpage of Thinned -SiC Wafers

Brunella Cafra, Ruggero Anzalone, Andrea Severino

Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Sobin Mathew, Sergey P. Lebedev, Alexander A. Lebedev, Bernd Hähnlein, J. Stauffenberg, E. Manske, Joerg Pezoldt

Polish Scratch Simulation vs. Polish Tool Type

Kevin Moeggenborg, Meong Keun Ju

Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Dirk Lewke, Frank Supplieth, Maik von Ringleben, John Ransom

Via Size-Dependent Properties of TiAI Ohmic Contacts on 4H-SiC

Alexander May, Mathias Rommel, Susanne Beuer, Tobias Erlbacher

Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment

A. Benjamin Renz, Oliver James Vavasour, Amador Pérez-Tomás, Qinze Cao, Vishal Ajit Shah, Yeganeh Bonyadi, Vasantha Pathirana, Tanya Trajkovic, G.W.C. Baker, Philip Andrew Mawby, Peter Michael Gammon

The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Christopher Frewin, Mohamad Beygi, Evans Bernardin, Chen Yin Feng, Francesco La Via, William Dominguez-Viqueria, Stephen E. Saddow

Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

Cristiano Calabretta, Alessandro Pecora, Marta Agati, Stefania Privitera, Annamaria Muoio, Simona Boninelli, Francesco La Via

A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Xavier Gay, Norbert Bay, Franck Delahaye, Stefan Hansen, Holger H. Kuehnlein

Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Markus Italia, Ioannis Deretzis, Alfio Nastasi, Silvia Scalese, Antonino La Magna, Massimo Pirnaci, Daniele Pagano, Dario Tenaglia, Patrizia Vasquez

Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

Clément Berger, Daniel Alquier, Jean François Michaud

Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

Vinoth Sundaramoorthy, Stephan Wirths, Lars Knoll

Highest Quality and Repeatability for Single Wafer SiC CMP Designed for High Volume Manufacturing

Sean Yu, Jian Jun Hu, Long Long Xu, Mike Liu, Eulia Liu, John Givens, Jamie Leighton

Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap

Maria Canino, Fulvio Mancarella, Filippo Bonafe, Franco Corticelli, Cristiano Albonetti, Roberta Nipoti

Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Roberta Nipoti, Virginia Boldrini, Maria Canino, Fabrizio Tamarri, Salvatore Vantaggio, Antonella Parisini

Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing

Gil Chung, Ian Manning, Andrey Soukhojak, Matthew Gave, Charles Lee

Chapter 3: Characterization, Modelling and Defect Engineering

Identification of High Resolution Transient Thermal Network Model for Power Module Packages

Shuhei Fukunaga, Tsuyoshi Funaki

Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

Johji Nishio, Chiharu Ota, Ryosuke Iijima

Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

Judith Woerle, Manuel Belanche Guadas, Marco Negri, Christopher Lamontagne, Filippo Bonafe, Roberta Nipoti, Ulrike Grossner

Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method

Yoshitaka Nishihara, Koji Kamei, Daisuke Shiomi, Kenji Momose

Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Kazumi Takano, Yasuyuki Igarashi

Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection

Alessandro Meli, Annamaria Muoio, Riccardo Reitano, Antonio Trotta, Miriam Parisi, Laura Meda, Francesco La Via

Automatic Image Analysis of Stackingfault

Annamaria Muoio, Cristiano Calabretta, Viviana Scuderi, Massimo Zimbone, Francesco La Via

Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

A.M. Vidarsson, J.R. Nicholls, Daniel Haasmann, Sima Dimitrijev, E.Ö. Sveinbjörnsson

Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Alina Muravitskaya, Anna Rumyantseva, Atse Julien Eric Ndohi, Camille Sonneville, Dominique Planson, Pierre Michel Adam, Sylvain Potiron, Mihai Lazar

Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Yu Ogata, Kohei Yamasue, Xufang Zhang, Tsubasa Matsumoto, Norio Tokuda, Yasuo Cho

Measurement of Dislocation Density in SiC Wafers Using Production XRT

Andrey Soukhojak, Tyler Stannard, Ian Manning, Charles Lee, Gil Chung, Matthew Gave, Edward Sanchez

Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Tommaso Fazio, Giuseppe Fisicaro, Ioannis Deretzis, Elisabetta Paladino, Antonino La Magna

Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

Piyush Kumar, Maria Mendes Martins, Marianne Etzelmüller Bathen, Judith Woerle, Thomas Prokscha, Ulrike Grossner

Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Francesco La Via, Luca Belsito, Matteo Ferri, Sergio Sapienza, Alberto Roncaglia, Marcin Zielinski, Viviana Scuderi

The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2

A. Benjamin Renz, Oliver James Vavasour, Peter Michael Gammon, Fan Li, Tian Xiang Dai, G.W.C. Baker, Nicholas Grant, John D. Murphy, Philip Andrew Mawby, Vishal Ajit Shah

KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Nicolas Bercu, Mihai Lazar, Olivier Simonetti, Pierre Michel Adam, Mélanie Brouillard, Louis Giraudet

Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Kohei Yamasue, Yasuo Cho

4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

Dominique Planson, Camille Sonneville, Pascal Bevilacqua, Luong Viet Phung, Besar Asllani, Dominique Tournier, Pierre Brosselard

Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

Manuel Belanche Guadas, Piyush Kumar, Judith Woerle, Roger Stark, Ulrike Grossner

Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Yafei Liu, Hong Yu Peng, Ze Yu Chen, Qian Yu Cheng, Shanshan Hu, Balaji Raghothamachar, Michael Dudley, Ramon Collazo, Zlatko Sitar, James Tweedie, Michal Bockowski, Vincent Meyers, F. Shadi Shahedipour-Sandvik, Bing Jun Li, Jung Han

Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography

Hong Yu Peng, Ze Yu Chen, Yafei Liu, Qian Yu Cheng, Shanshan Hu, Xian Rong Huang, Lahsen Assoufid, Balaji Raghothamachar, Michael Dudley

Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

Ze Yu Chen, Hong Yu Peng, Yafei Liu, Qian Yu Cheng, Shanshan Hu, Balaji Raghothamachar, Michael Dudley, Reza Ghandi, Stacey Kennerly, Peter Thieberger

Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Qian Yu Cheng, Hong Yu Peng, Shanshan Hu, Ze Yu Chen, Yafei Liu, Balaji Raghothamachar, Michael Dudley

Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Marianne Etzelmüller Bathen, Robert Karsthof, Ulrike Grossner, Lasse Vines

Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

Marie Amandine Pinault-Thaury, François Jomard

Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

Lars Knoll, Giovanni Alfieri, Gianpaolo Romano, Andrei Mihaila, Yulieth Arango, Moritz Wehrle, Vinoth Sundaramoorthy, Stephan Wirths

Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence

Judith Woerle, Brett C. Johnson, Roger Stark, Massimo Camarda, Ulrike Grossner

Evaluation of Line-Shape Defect in Epitaxial Wafer

Ling Guo, Daisuke Shiomi

Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon

Filippo Giannazzo, Patrick Fiorenza, Emanuela Schiliro, Salvatore Di Franco, Sylvain Monnoye, Hugues Mank, Marcin Zielinski, Francesco La Via, Fabrizio Roccaforte

A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Hrishikesh Das, Swapna Sunkari, Joshua Justice, Danielle Hamann

Ni/Heavily-Doped 4H-SiC Schottky Contacts

Marilena Vivona, Giuseppe Greco, Salvatore Di Franco, Patrick Fiorenza, Filippo Giannazzo, Antonino La Magna, Fabrizio Roccaforte

Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Paolo Badalà, Emanuele Smecca, Simone Rascunà, Corrado Bongiorno, Egidio Carria, Anna Bassi, Gabriele Bellocchi, Silvia Castorina, Cristina Tringali, Antonino La Magna, Alessandra Alberti

Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Collin Hitchcock, Reza Ghandi, Peter Deeb, Stacey Kennerly, Mohamed Torky, T. Paul Chow

Structural, Electronic and Optical Properties of 6H-SiC and 3C-SiC with the Application in Solar Cell Devices

Ibrahim Taibi, Hamza Abid

Chapter 4: Power Devices and Applications

Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Xiao Li Tian, Cheng Zhan Li, Yu Yang, Wang Feng, Jiang Lu, Chang Wei Zheng, Cheng Yue Yang, Yun Bai, Xin Yu Liu

Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Zimo Yuan, Keijo Jacobs, Mietek Bakowski, Per Ranstad, Adolf Schöner, Sergey Reshanov, Wlodek Kaplan, Hans Peter Nee, Anders Hallén

Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Takaaki Tominaga, Toshiaki Iwamatsu, Yukiyasu Nakao, Hiroyuki Amishiro, Hiroshi Watanabe, Naruhisa Miura, Satoshi Yamakawa, Shuhei Nakata

Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation

Shuhei Nakata, Yuta Sato

Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Sofía Otero Ugobono, J.M. Rafi, Philippe Godignon, G. Pellegrini, Gemma Rius, M.C. Jiménez Ramos, J. García López, A. García Osuna

Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Daniel J. Lichtenwalner, Donald A. Gajewski, Sei Hyung Ryu, Brett Hull, Scott Allen, John W. Palmour

Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

Siva Kotamraju, Pavan Vudumula

Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

Cédric Mathieu de Vienne, Pierre Lefranc, Besar Asllani, Pierre Olivier Jeannin, Bruno Lefebvre

Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

Reza Ghandi, Collin Hitchcock, Stacey Kennerly

AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Marie Lesecq, Eric Frayssinet, Marc Portail, Micka Bah, Nicolas Defrance, Thi Huong Ngo, Mahmoud Abou Daher, Marcin Zielinski, Daniel Alquier, Jean-Claude De Jaeger, Yvon Cordier

Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

Felix Hoffmann, Stefan Schmitt, Nando Kaminski

Investigation of SiC Thyristors with Varying Amplifying Gate Design

Sigo Scharnholz, Ralf Hassdorf, Dirk Bauersfeld, Bertrand Vergne, Luong Viet Phung, Dominique Planson

Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Martin Domeij, Jimmy Franchi, Sotirios Maslougkas, Peter Moens, Jan Lettens, Jake Choi, Fredrik Allerstam

Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design

Lu Yang Zhang, Tian Xiang Dai, Peter Michael Gammon, Neophytos Lophitis, Florin Udrea, Amit Tiwari, Jose Ortiz-Gonzalez, A. Benjamin Renz, Vishal Ajit Shah, Philip Andrew Mawby, Marina Antoniou

Neutron Detection Study Through Simulations with Fluka

Annamaria Muoio, Alessandro Meli, Antonio Trotta, Miriam Parisi, Laura Meda, Francesco La Via

A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

G.W.C. Baker, Fan Li, Tian Xiang Dai, A. Benjamin Renz, Lu Yang Zhang, Yun Yi Qi, Vishal Ajit Shah, Philip Andrew Mawby, Marina Antoniou, Peter Michael Gammon

DC Modeling of -SiC nJFET Gate Length Reduction at

Mohit R. Mehta, Philip G. Neudeck, John W. Lawson

A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

A. Benjamin Renz, Oliver James Vavasour, Mathias Rommel, G.W.C. Baker, Peter Michael Gammon, Tian Xiang Dai, Fan Li, Marina Antoniou, Philip Andrew Mawby, Vishal Ajit Shah

Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Lakshmi Kanta Bera, Navab Singh, Ze Yu Chen, Calvin Chua Hung Ming, King Jien Chui, Ravinder Pal Singh, Yee Ye Sheng, Surasit Chung, K. Michael Han, Ka Ren Chong, Dim Lee Kwong

Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Simon Mendy, Rui Zhu Wu, Jose Ortiz-Gonzalez, Olayiwola Alatise

Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

Munaf T. Rahimo, Iulian Nistor, David Green

Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Rosine Coq Germanicus, Kimmo Niskanen, Alain Michez, Niemat Moultif, Wadia Jouha, Olivier Latry, Jerôme Boch, Ulrike Lüders, Antoine D. Touboul

SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Roman Maloušek, Jan Chochol, Hrishikesh Das, Swapna Sunkari, Joshua Justice, Krister Gumaelius, Jimmy Franchi, Martin Domeij, Fredrik Allerstam, Ryota Wada, Takashi Kuroi

Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Sara Kochoska, Martin Domeij, Swapna Sunkari, Joshua Justice, Hrishikesh Das, Thanh Toan Pham, Jimmy Franchi, Sotirios Maslougkas, Ho Jung Lee, Xue Qing Hu, Thomas Neyer

Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices

Mohamed Torky, T. Paul Chow

Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

Mohamed Torky, T. Paul Chow

Edge Terminations for -SiC Power Devices: A Critical Issue

Philippe Godignon, Josep Montserrat, José Rebollo, Dominique Planson

Impact of Device Design Parameters on 15 kV SiC MOSFETs

Siddarth Sundaresan, Jaehoon Park, Vamsi Mulpuri, Ranbir Singh

Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Ben Jones, Jacob Mitchell, Jon Evans, Finn Monaghan, Mike Jennings, Chris Bolton, Kevin Riddel, Huma Ashraf, Owen James Guy

Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

Vinoth Sundaramoorthy, Andrei Mihaila, Lucas Spejo, Renato Amaral Minamisawa, Lars Knoll

A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Priyadarshini Shanmugam, Luis Iglesias, Marc Portail, Isabelle Dufour, Dominique Certon, Daniel Alquier, Jean François Michaud

Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Neophytos Lophitis, Peter Michael Gammon, A. Benjamin Renz, Tian Xiang Dai, Amit Tiwari, Tanya Trajkovic, Philip Andrew Mawby, Florin Udrea, Marina Antoniou

Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Sofia Aslanidou, Alberto García-García, Gemma Rius, Philippe Godignon

Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Olfa Karker, Konstantinos Zekentes, Aude Bouchard, Isabelle Gélard, Xavier Mescot, Valerie Stambouli, Edwige Bano

Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Ali Ammar, Luong Viet Phung, Dominique Planson, Hervé Morel, Camille Sonneville

Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Valentin Valero, Laurent Ottaviani, Abdallah Lyoussi, Vladimir Radulović, Luka Snoj, Adrien Volte, Michel Carette, Christelle Reynard Carette

Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts

Kaloyan Naydenov, Nazareno Donato, Florin Udrea, Andrei Mihaila, Gianpaolo Romano, Stephan Wirths, Lars Knoll

On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Nazareno Donato, Kaloyan Naydenov, Florin Udrea, Andrei Mihaila, Gianpaolo Romano, Stephan Wirths, Lars Knoll

Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Fatme Abed Ali, Yvan Avenas, Pierre Lefranc, Pierre Olivier Jeannin, Hadi Alawieh, Toni Youssef, Hassan Moussa

Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Eiichi Murakami, Tatsuya Takeshita, Kazuhiro Oda

Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Alexander Tsibizov, Roger Stark, Ulrike Grossner

SiC MOSFET C-V Characteristics with Positive Biased Drain

Ilaria Matacena, Luca Maresca, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento, Alberto Castellazzi

A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

Alessandro Borghese, Michele Riccio, Luca Maresca, Giovanni Breglio, Slavo Kicin, Andrea Irace

SiC MOSFET C-V Curves Analysis with Floating Drain Configuration

Ilaria Matacena, Luca Maresca, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento

Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Ilaria Matacena, Luca Maresca, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento

Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Yusuke Yamashiro, Masakazu Okada, Masakazu Baba, Takanori Tanaka, Shingo Tomohisa, Hiroshi Watanabe, Kazutoshi Kojima, Shinsuke Harada, Hiroshi Yamaguchi

Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Joseph A. McPherson, Andrew A. Woodworth, T. Paul Chow, Wei Ji

Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Michael Waltl, Yoanlys Hernandez, Christian Schleich, Katja Waschneck, Bernhard Stampfer, Hans Reisinger, Tibor Grasser

Keywords Index

Authors Index

Chapter 1

Material Growth and Wafer Manufacturing

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 3-7

doi: 10.4028/p-9bg88x

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-21

Revised:
2022-02-01

Accepted:
2022-02-08

Online:
2022-05-31

Models for Impurity Incorporation during Vapor-Phase Epitaxy

The original version of this paper is available on https://www.scientific.net/MSF.1062.3.pdf

Kazuhiro Mochizuki , Fumimasa Horikiri , Hiroshi Ohta and Tomoyoshi Mishima

Hosei University, Koganei, Tokyo 184-8584, Japan

SCIOCS Co. Ltd., Hitachi, Ibaraki 319-1418, Japan

kazuhiro.mochizuki.66@hosei.ac.jp, horikirif@sc.sumitomo-chem.co.jp, hiroshi.ohta.43@hosei.ac.jp, tomoyoshi.mishima.67@hosei.ac.jp

Keywords: impurity, vapor-phase epitaxy, surface diffusion, step kinetics, segregation.

Abstract

Impurity incorporation during vapor-phase epitaxy on stepped surfaces was modeled by classifying rate-limiting processes into i) surface diffusion, ii) step kinetics, and iii) segregation. Examples were shown for i) desorption-limited Al incorporation during chemical vapor deposition (CVD) of (0001) SiC, ii) preferential desorption of C atoms from kinks during CVD of Al-doped (000-1) SiC, and iii) segregation-limited C incorporation during metalorganic vapor-phase epitaxy of (0001), (000-1), and (10-10) GaN.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.3.pdf

Impurity incorporation during vapor-phase epitaxy has been modeled via, for example, site competition and surface vacancies . The latter, however, cannot explain the variation in impurity doping around facets [5]. Moreover, in the cases of homoepitaxial growths of SiC and GaN , misoriented substrates are often used for polytype [6] and doping-uniformity [7] controls, respectively. Accordingly, we modeled impurity incorporation during step-flow growth by taking Aldoped SiC and C -doped GaN, as examples. We believe the models should be beneficial for determining allowable off-angle variations for desired doping-level uniformities in advanced devices. Although Al was chosen due to the availability of a thermodynamic model [8], N doping for SiC could be similarly treated under the assumption of the N segregation coefficient being unity [9].

Proposed Models

The original version of this paper is available on https://www.scientific.net/MSF.1062.3.pdf

Impurity incorporation during vapor-phase epitaxy on stepped surfaces was modeled by classifying rate-limiting processes into i) surface diffusion [10], ii) step kinetics [11], and iii) segregation [12] (Table I).
i) Desorption limits impurity incorporation at step-edges when surface diffusion length is less than a half of the average inter-step distance, . This should be the case with incorporation of Al , whose was estimated to be less than 2 nm at [10], into stepped . This is due to relatively large (eg., 7.2 nm for ) originating from four-bilayer-high steps [13]. Based on the Burton-Cabrera-Frank (BCF) theory [14], we derived the following equation for in [10]:

where , and are, respectively, the incident flux, equilibrium vapor pressure, and mass of atom, and are, repectively, the equilibrium constant and activity coefficient for AlC, is growth temperature, and is Boltzmann's constant. Eq. (1) explains why was independent of the off-angle (ranging from to ) when the C/Si ratio, , was small (i.e., 1.8 [15]); due to large , the first term in the right-hand side, which corresponds to the Al desorption flux, became
dominant (solid line in Fig. 1). Eq. (1) also explains why increased with when was large (i.e., 4-6 [16]); due to small , the second term in the right-hand side, which corresponds to the Al flux incorporated into the solid, became so large that increased with the step density on the surface (dashed and dotted lines in Fig. 1).

Table I. Rate-limiting processes of impurity incorporation during vapor-phase epitaxy.

Fig. 1. , calculated as first term (solid line) and second term (dashed and dotted lines) in righthand side of Eq. (1), as a function of equilibrium vapor pressure of Si , with assumptions of of , growth rate of , and of 2.0 nm .

Fig. 1. , calculated as first term (solid line) and second term (dashed and dotted lines) in righthand side of Eq. (1), as a function of equilibrium vapor pressure of Si , with assumptions of of , growth rate of , and of 2.0 nm .

ii) Preferential desorption of host atoms from kinks limits impurity incorporation at kinks even when . This should be the case with incorporation of Al into that has one-bilayer-high steps [13]. We assume that a C atom making two bonds with a Si atom stays at kinks, while that a C atom making one bond with a Si atom easily desorbs from kinks [Fig. 2(a)].

Since is typically small (eg., ), some surface-diffusing Al atoms that arrive at kinks keep waiting (for an average time ) until C atoms make one bond with Si atoms at kinks Fig. 2(b)] before they are incorporated into the solid [Fig. 2(c)]. Based on the reported experimental results [16], surface Al concentration (normalized by the mean residence time ) was calculated (Fig. 3). in the vicinity of step-edges (i.e., local minima in Fig. 3) on (000-1) is much larger than that on (0001), indicating longer on (000-1).

Fig. 2. Schematic illustrations of (a) preferential desorption of a C atom having one bond with a Si atom, (b) adsorption of a C atom to a dangling bond of a Si atom and bonding of an Al atom to two C atoms, and (c) bonding of another Al atom to three C atoms at kinks on .

Fig. 2. Schematic illustrations of (a) preferential desorption of a C atom having one bond with a Si atom, (b) adsorption of a C atom to a dangling bond of a Si atom and bonding of an Al atom to two C atoms, and (c) bonding of another Al atom to three C atoms at kinks on .

iii) Segregation limits impurity incorporation even when and desorption of host atoms from kinks is negligible. This should be the case with incorporation of C into GaN that is typically grown with the N/Ga ratio exceeding 1000 [17-19]; namely, soon after a N atom making one bond with a Ga atom desorbs from kinks, another N atom makes one bond with the Ga atom. When the length of time before the C concentration at the step-edge site reaches its equilibrium value, , is much smaller than the meantime until a C atom incorporated at kinks moves through the step-edge site to the surface site, , the C concentration in the solid can be expressed as [20]

where and are, respectively, the equilibrium C concentrations at the surface site and at the step-edge site, is the diffusion coefficient in the solid, is the average step velocity, and is the lattice constant. As shown in Fig. 4, the results for (0001) [17], (000-1) [18], and (10-10) [19] growths are well reproduced with of that agrees with the experimentally determined value [21].

Fig. 3. Distribution of calculated with assumptions of of , growth rate of , of 6, and of 2.0 nm .

Fig. 3. Distribution of calculated with assumptions of of , growth rate of , of 6, and of 2.0 nm .

Fig. 4. Step-velocity dependences of carbon concentrations fitted to the reported results [17-19].

Fig. 4. Step-velocity dependences of carbon concentrations fitted to the reported results [17-19].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.3.pdf

Impurity incorporation during step-flow growth was modeled and exemplified by and GaN: C cases. We believe the proposed models should contribute to determining allowable off-angle variations for desired doping-level uniformities in advanced SiC and GaN devices.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.3.pdf

This work was supported in part by the "Project of GaN technology innovation for enabling decarbonized society and lifestyle" funded by the Ministry of the Environment Government of Japan.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.3.pdf

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 8-12

doi: 10.4028/p-8302i1

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-22

Revised:
2022-02-11

Accepted:
2022-03-14

Online:
2022-05-31

Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

Yann Jousseaume , François Cauwet , Gabriel Ferro

Laboratoire des Multimatériaux et Interfaces, Université de Lyon, 6 rue Victor Grignard, 69622

Villeurbanne, France

yann.jousseaume@univ-lyon1.fr, francois.cauwet@univ-lyon1.fr, gabriel.ferro@univ-lyon1.fr

Keywords: Surface structuring, step-bunched morphology, sandwich, liquid silicon

Abstract

In view of obtaining a step bunched morphology on large surfaces, a sandwich configuration is investigated. A piece of silicon is melted between two off wafers, allowing a better spreading of the liquid than a Si drop approach. This successfully leads to highly step-bunched surfaces, though with irregular steps. The most regular step and terrace stuctures were found to be the result of epitaxial growth via a dissolution-precipitation process occuring from the edges to the center of the wafers. This is probably caused by radio-frequency induced electromagnetic convection within liquid Si . This process is quenched when using smaller liquid thickness.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

Despite the attractive properties and already wide use of silicon carbide in power electronics, the performances of SiC metal-oxide-semiconductor field effect transistors (MOSFETs) remain limited due to low channel mobility. A high density of electrically active defects at the interface is being held accountable for this limitation [1]. While the origin of these interfacial traps is still under debate, recent experimental studies [2] attribute them to the micro/macro step-bunched morphology inherent to commonly used off-axially grown epitaxial surfaces [3]. Such a morphology is expected to critically impact the quality of the interface, for instance by initiating non-ideal oxidations and nonstoichiometric near-interface regions [4].

A recent study has found that MOS capacitors fabricated on macrostepped surfaces show a systematic decrease of the interface traps density of compared to "standard" samples [5]. Although this work gave an interesting direction for further study, it also raised the issue of controlling the formation of such macrostepped surfaces. A simple way would be to put a 4H-SiC wafer in contact with a liquid Si drop [6,7]. The induced atomic rearrangement would generate the reconstruction of the off surface with very large terraces of few width, which is more than 100 times wider than those found in standard epitaxial surfaces grown by chemical vapour deposition (CVD). But while such a Si drop approach was appropriate for preliminary demonstration and for small areas of , its extrapolation to industry-scale areas (full 4-6" wafer) is clearly not straightforward. A substancial increase in the sample size would require the development of a set up where the liquid silicon would be more spread over the SiC surface. This is the goal of the present work.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

In order to force the spreading of the liquid Si , a sandwich configuration is investigated. The sandwich consists in a stacking where a piece of n type Si wafer is placed in between two -face wafers (see Fig. 1 left). To avoid any Si loss upon melting from the wafers sides, the chosen lateral size of the bottom wafer ( SiC bottom) is larger than the top one (SiC top), i.e. and for the bottom and top wafers, respectively. The pressure applied by the top wafer should force the liquid Si to spread on both surfaces until reaching the square edges of the SiC-top wafer (Fig. 1 right). Such natural spreading is expected to lead to homogeneous Si liquid thickness between the SiC wafers, which are thus considered parallel. We
will also assume that the area occupied by the liquid Si is equal to the surface of the SiC -top wafer, with no liquid overflow (this was confirmed experimentally). With these assumptions, we are able to calculate the theoretical liquid thickness from the mass of the initial Si wafer piece.

After ultrasonic cleaning in methanol of each part of the assembly, the stacking is placed upon a graphite susceptor which is then inserted in a RF-heated homemade vertical cold wall CVD reactor working at atmospheric pressure under . Such cold wall configuration under flowing can generate substantial vertical thermal gradient if the sample is thick enough. A typical experiment consists in heating the assembly above Si melting point for and then cooling it. The elaboration conditions of the samples studied here are listed in Table 1. After removing the sample from the reactor, the solidified Si is chemically etched in a mixture of for several hours. The obtained reconstructed surfaces of both SiC top and bottom wafers are examined on the one hand using optical microscopy to study the obtained macrostepped morphology, and on the other using mechanical profilometry to check the homogeneity of the surface structuring process and the possible occurrence of any mass transport phenomenon.

Figure 1. Schematics of the investigated sandwich set up and the expected thermal gradient direction in this configuration before and after Si melting.

Figure 1. Figure 1. Schematics of the investigated sandwich set up and the expected thermal gradient direction in this configuration before and after Si melting.

Table 1. Elaboration conditions of the investigated samples.

Sample | Temperature [°C] | Time [min] | Si liquid thickness [μm]
A | 1550 | 30 | 30
B | 1550 | 120 | 30
C | 1600 | 30 | 30
D | 1550 | 30 | 400

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

First, as shown in Fig. 2, every wafer treated in this work displays a pronounced macrostep bunching which is easily visible by optical microscopy. Interestingly, in the case of the SiC top wafers, of the surface is step-bunched. This confirms the potential of the liquid Si interaction approach for macro-structuring of surfaces on large areas. But the precise step structure of each wafer varies depending on both its position within the stack and the experimental conditions. For instance, the bottom wafers always display wider terraces than the top ones. Comparing samples A and B , it can be noted that an increase from 30 to 120 min of the interaction duration does not a have a significant effect on the resulting SiC surface morphology. Increasing temperature from (sample B) to (sample C) has a more pronounced effect essentially for the bottom SiC, which displays wide but highly irregular steps. Increasing Si liquid thickness from 30 to (sample D) leads to a significant improvement of the straightness of the steps which are now clearly all parallel. This is precisely towards such a surface reconstruction that the present work aims at. The uniformity of this reconstruction has yet to be verified, as well as the possible occurrence of mass transport within the system. For that purpose, 3D profilometry mapping on both top and bottom wafers of samples B and D (Fig. 3) was performed. It can be observed that the "best" reconstructed surface of sample D is also the less homogeneous in terms of
height variation across the wafer. On this sample, both top and bottom wafers display a butterflylike pattern with positive (up to ) height while the edges are delimited with -6 to depressions. In the case of sample B (with only liquid thickness, Fig. 3 right), the 3D maps are visibly much flatter on both top and bottom wafers, even though the bottom SiC wafer displays a central bumping at with edge delimitation at .

Figure 2. Optical microscopy images of the top and bottom SiC wafers from the investigated assemblies (see Table 1) after interaction with molten Si . Images are taken at the center of each wafer.

Figure 2. Figure 2. Optical microscopy images of the top and bottom SiC wafers from the investigated assemblies (see Table 1) after interaction with molten Si . Images are taken at the center of each wafer.

Figure 3. 3D profilometry maps of the top (up) and bottom (down) wafers of sample D and sample B.

Figure 3. Figure 3. 3D profilometry maps of the top (up) and bottom (down) wafers of sample D and sample B.

The 3D mapping results suggest that some matter transport, from the edges to the center of the wetting area, occurs on both SiC wafers of the same assembly. All seems to happen like if the edges were preferentially etched and the dissolved carbon was transported to the center where it precipitated to form epitaxial SiC. The fact that both top and bottom wafers display the same pattern suggests that this dissolution-precipitation process takes place on the same SiC surface and not from one surface to the other. According to the expected vertical thermal gradient within the assembly during the treatments (see Fig. 1), one would have expected the main C transport to be from the
bottom SiC (hotter) to the top SiC (colder). This is definitely not the case here since growth evidently occurs on the bottom surfaces of both B and D samples. Such results obviously raise an interrogation on the very existence of a vertical thermal gradient in this set up. However, the previously mentionned differences in morphology for both wafers of the same stack (see Fig. 2) suggest that these surfaces are not at the same temperature, though the resulting thermal gradient is probably too small to counterbalance the edge-to-centre mass transport. The latter phenomenon could originate from convection rolls generated by the intense magnetic field coming from the RF heating [8,9]. Such rolls would transport C more efficiently than the thermal gradient would do, as evidenced in liquid phase SiC growth experiments [10]. The butterfly pattern would then just reflect the forced convection scheme that happens within the liquid Si. The fact that the mass transport pattern is less pronounced for smaller liquid thickness is another hint towards the presence of these convection rolls, as they require a certain amount of liquid to form.

Considering the main purpose of this work which is to generate a well controlled step bunching for further MOS studies, it is important to keep in mind that the most wanted morphology (with wide and regular terraces) was exclusively spotted at the center of sample D , where some SiC growth occurred. This means that the SiC doping at the surface of these areas may have varied due to this growth, possibly being out of the targeted range for MOS. The doping level of these reconstructed surfaces has thus to be verified before considering a broader development of the presented process. Finally, if less parallel macrosteps are deemed suitable enough for MOS fabrication, a structured top SiC wafer resulting from an interaction with liquid thickness could then be a good compromise since it exhibits an apparently growth-free and homogeneous step-bunched surface.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

A sandwich configuration-based process for macrosteps design on large areas off surfaces has been studied. Despite the homogeneous spreading of the liquid Si and the demonstration of such structuring, uncontrolled mass transport occurs within the liquid, arguably caused by convection rolls. Further study is needed for pursuing the obtention of a regular macrostepped morphology while avoiding SiC growth.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

This work has been financially supported by French ANR in the framework of the 19-CE24-0007 "Risemos" project.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.8.pdf

A. Chatterjee, A. Bhat, K. Matocha, Investigation of electrically active defects of silicon carbide using atomistic scale modeling and simulation, Phys. B Condens. Matter, 401-402, (2007), 81-84

J. Woerle, B. C. Johnson, C. Bongiorno, K. Yamasue, G. Ferro, D. Dutta, T. A. Jung, H. Sigg, Y. Cho, U. Grossner and M. Camarda, Two-dimensional defect mapping of the interface, Phys. Rev. Mater., 3, 8, (2019), 084602

T. Kimoto, Z. Y. Chen, S. Tamura, S. I. Nakamura, N. Onojima and H. Matsunami, Surface morphological structures of 4 H -, 6H- and 15 R -SiC (0001) epitaxial layers grown by chemical vapor deposition, Jpn. J. Appl. Phys., 40, 5R, (2001), 3315-3319

P. Fiorenza, F. Iucolano, G. Nicotra, C. Bongiorno, I. Deretzis, A. La Magna, F. Giannazzo, M. Saggio, C. Spinella, F. Roccaforte, Electron trapping at interface probed by transient capacitance measurements and atomic resolution chemical analysis, Nanotechnology 29 (2018) 395702

M. Camarda, J. Woerle, V. Souliere, G. Ferro, H. Sigg, U. Grossner and J. Gobrecht, Analysis of 4 H -SiC MOS Capacitors on macro-stepped surfaces, Mater. Sci. Forum, 897, (2017), 107110

D. Chaussende, L. Parent-Bert, Y. J. Shin, T. Ouisse and T. Yoshikawa, Effect of aluminum during the high temperature solution growth of Si-face , Mater. Sci. Forum, 858, (2016), 37-40

V. Soulière, D. Carole, M. Camarda, J. Woerle, U. Grossner, O. Dezellus and G. Ferro, 4H surface faceting during interaction with liquid Si, Mater. Sci. Forum, 858, (2016), 163-166

U. Burr and U. Müller, Rayleigh-Bénard convection in liquid metal layers under the influence of a horizontal magnetic field, J. Fluid Mech., 453, (2002), 345-369

Y. Tasaka, T. Yanagisawa, K. Fujita, T. Miyagoshi and A. Sakuraba, 2D oscillation of convection roll in a finite liquid metal layer under a horizontal magnetic field, J. Fluid Mech., 911, (2021), 1-24

F. Mercier, J.-M. Dedulle, D. Chaussende and M. Pons, Coupled heat transfer and fluid dynamics modeling of high-temperature SiC solution growth, J. Crystal Growth 312 (2010) 155-163

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 13-17

doi: 10.4028/p-h7gy42

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-01

Revised:
2022-02-09

Accepted:
2022-03-28

Online:
2022-05-31

Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

The original version of this paper is available on https://www.scientific.net/MSF.1062.13.pdf

D. Baierhofer , B. Thomas , F. Staiger , B. Marchetti , C. Förster , T. Erlbacher

Robert Bosch GmbH, Tübinger Str. 123, 72762 Reutlingen, Germany

Friedrich-Alexander-Universität Erlangen-Nürnberg, Lehrstuhl für Elektronische Bauelemente, Cauerstr. 6, 91058 Erlangen, Germany

Daniel.Baierhofer@de.bosch.com, Bernd.Thomas@de.bosch.com,

Frank.Staiger@de.bosch.com, Benjamin.Marchetti@de.bosch.com,

Christian.Foerster@de.bosch.com, Tobias.Erlbacher@iisb.fraunhofer.de

Keywords: defect detection, epitaxial layer, defect classification, growth parameters, usable area

Abstract

The yield of high power 4H-SiC Trench-MOSFET devices, especially for those with large chip area, is largely dependent on the quality of the underlying epitaxial layers and therefore low densities of critical defects are of utmost importance. Different growth conditions for the deposition of epitaxial layers were investigated to reduce the impact of defects on electrical device performance.

For this investigation, thick n-type epitaxial layers were grown varying growth rates for the buffer and the drift layer in a warm-wall chemical vapor deposition reactor. The defects in the epitaxial layers were characterized utilizing surface microscopy as well as ultra-violet photoluminescence techniques. A quantitative comparison of surface defects and crystallographic defects between the different growth conditions was conducted with these methods. The impact of the growth conditions on the formation of critical defects is discussed in detail. The reduction of critical defects, which resulted in an increase of the predicted die yield, as well as an outlook on future investigations, is discussed.

Introduction

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Silicon carbide (SiC), more precisely the 4 H polytype, is of increasing interest as a material for high power and high voltage devices due to its wide band-gap, electrical properties as well as thermal properties [1-3]. These characteristics allow the fabrication of small and efficient devices, compared to established silicon technology, e.g. high power supply inverter consisting of high breakdown voltage SiC trench metal oxide semiconductors (MOSFETs) [3, 4].

Homo-epitaxial layers of highest quality have to be grown on mono-crystalline substrates for such devices to work reliably. This includes the quality of layer thickness, roughness, doping concentration and respective homogeneities, as well as surface and crystallographic defect densities [4-6]. Existing imperfections in the SiC substrate can act as nucleation centres for additional defects in the epitaxial layer [1, 4, 6]. Carefully chosen epitaxial growth parameters allow for the transformation into other defect types, harmless for device operation [1, 4, 6]. Further classification in device critical defects (CDs) and non-critical defects has to be made, since not all defects present in the epitaxial layer cause device failures or device degradation, as their effect is also dependent on the device type [7].

This paper presents a method to reduce known CDs for trench MOSFETs by varying epitaxial growth parameters which reduces various types of stacking faults. This work focuses on the influence of the growth rate of the epitaxial buffer and drift layer on the resulting defect density while keeping all other growth parameters constant.

Experimental Procedure

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Commercial 150 mm 4H-SiC substrates (all from the same supplier) with low micropipe density and off cut angle of towards the [11 ] direction were used for this investigation. A homoepitaxial n-type layer was grown on the "epi ready" polished and wet chemical cleaned Si-face substrates using a multi-wafer warm-wall chemical vapor deposition epitaxy reactor. Mitigation of generic boule impact was assured by using wafers from four different crystal boules, consequently abbreviated with the first two letters of the vendor code, LG and RF, as well as LT and TQ for the combinations of the varied growth rates ( 5 wafers each boule). Lasertec's SICA88 was used for surface and crystallographic defect analysis utilizing confocal optics for surface inspection and ultraviolet photoluminescence (UV-PL) imaging.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.13.pdf

A growth run using standard conditions (STD) served as base line for comparison. The growth rate was varied to a lower growth rate (LGR) and a higher growth rate (HGR) for buffer and drift layers in various combinations. For example, a variation of the buffer growth rate was combined with a standard drift layer growth rate and vice versa. Compared to the standard process HGR refers to an increase of in growth rate while LGR was carried out with a decreased growth rate. All other process parameters during the epitaxial layer growth were maintained constant for all growth rate variations.

Fig. 1 shows the normalized CD counts for each wafer/crystal and growth rate. CDs include carbon inclusions and micropipe clusters, scratches, basal plane dislocations, downfalls as well as downfall related polytype inclusions and stacking faults detected on the surface (triangles and partial triangles).

Fig. 1. Normalized critical defect counts vs. crystal and growth rate with HGR/LGR referring to high and low growth rate of the respective layer.

Fig. 1. Normalized critical defect counts vs. crystal and growth rate with HGR/LGR referring to high and low growth rate of the respective layer.

Fig. 2. Normalized predicted yield vs. crystal and growth rate with a die size considering critical defects only.

Fig. 2. Normalized predicted yield vs. crystal and growth rate with a die size considering critical defects only.

In Fig. 1 and Fig. 2, the defect counts for the STD layer grown on the LG crystal were set to 1. The highest number of defects was detected with LGR of the buffer layer with 1.48 on crystal LG. Whereas in the LGR drift layer 1.44 and 1.15 critical defects for LG and RF were detected respectively, and a HGR buffer resulted in the lowest critical defect counts, 0.40 for LG and 0.45 for RF. A predicted yield for a die size was calculated for each epilayer and was normalized by setting the LG crystal with standard growth rate to 1 as shown in Fig. 2. Only CDs were considered for the yield prediction. The results are consistent with those shown in Fig. 1, where high yields can be predicted with HGR Buffer, 1.23 and 1.22 for LG and RF, while low yields would result from LGR Buffer of LG, 0.92, and LGR Drift with 0.95 for LG and 0.94 for RF.

In Fig. 3, the critical defect counts are split in several detected defect class groups and plotted vs. epitaxial layer growth rate normalized by setting the standard growth parameters to 1 . These defect

Fig. 3. Separated defect class counts included in critical defects vs. growth rate and combined for the crystals.

Fig. 3. Separated defect class counts included in critical defects vs. growth rate and combined for the crystals.

Fig. 4. Normalized critical defect counts vs crystal and growth rate with L/H referring to a lower/higher growth rate in buffer-drift.

Fig. 4. Normalized critical defect counts vs crystal and growth rate with L/H referring to a lower/higher growth rate in buffer-drift.

class groups are substrate defects, i.e., scratches and polytype inclusions originated in the substrate, basal plane dislocations, various types of stacking faults excluding UV-PL only types, as well as downfalls and downfall related defects. In this graph an almost linear increase of CDs from HGRBuffer, 0.5 defect counts, to LGR-Drift, 1.52 defect counts, can be seen.

Combinations of different growth rates were carried out based on these findings and the resulting CD counts can be seen in Fig. 4, as well as the resulting stacking fault (SF) counts in Fig. 5. In this figure, L/H refers to a lower/higher growth rate, same as previously described, for the buffer and drift layer separately with respect to the STD labeled standard growth rate for both layers which is normalized to 1 for crystal TQ. The lowest CD counts were achieved by low buffer/high drift rate combination (L-H) with 0.52 and 0.72 for the LT and TQ crystal, respectively, while the highest CD counts were detected by the low buffer and drift rate combination (L-L) with 1 for LT and 1.59 for TQ. Where STD growth rates resulted in 0.48 CD counts for the LT crystal.

Fig. 5 shows the detected CD counts of various types of surface protruding SFs. These defects, out of all defect classes considered for the CD counts shown in Fig. 4, were affected the most by the different growth rates. The number of SFs detected on the TQ crystal with STD growth rates is normed to 1 . The lowest SF counts were detected by L-H with 0.79 and 0.65 for the LT and TQ crystal while highest SF counts were again detected by L-L with 1.53 for LT and 1.80 for TQ. For the LT crystal the lowest SF counts very detected by STD growth rates with 0.70 .

Fig. 5. Normalized stacking fault counts vs crystal and growth rate with L/H referring to a lower/higher growth rate in buffer-drift.

Fig. 5. Normalized stacking fault counts vs crystal and growth rate with L/H referring to a lower/higher growth rate in buffer-drift.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.13.pdf

Defect measurements carried out after varying either the buffer or drift layer growth rate separately, as depicted in Fig. 1, show that the LGR buffer layer deposition reduces the counts of CDs on LG by and on RF. Whereas using the HGR drift reduced the CDs by and for LG and RF. The LGR drift increases the CDs by for LG and for RF. The LGR buffer results in more CDs on LG and less CDs on RF. These values show that long deposition times, especially LGR drift, result in a consistent increase in CDs due to additional etching at high temperatures under atmosphere during the epitaxial layer deposition. In this case a significant increase in surface detected scratches on the wafer edge are mainly responsible for the increase of CD counts. The variations of the buffer layer growth rate show improved step-flow growth conditions due to a statistical saturation of the substrate surface with C and Si atoms. The reduction in CDs can consequently be seen in an increase of the predicted yield when using a generic die size grid in Fig. 2. Therefore, no significant additional bunching of CDs occurred. Combining the CD counts by growth rate, Fig. 3, shows a mostly linear increase from to where substrate defects, i.e., scratches, and stacking faults are impacted the most. Varying both buffer and drift layer growth rates simultaneously, Fig. 4, shows that for the L-H combination the lowest CD counts are achieved, whereas results in slightly higher and similar CD counts to the standard parameter. Highest CD counts where achieved by L-L, due to significant additional etching of the surface during the layer deposition which is detected as additional scratches. During this increased growth time no additional downfall related polytype inclusions could be detected. The generation of triangular stacking faults, Fig. 5, was suppressed by the low growth rate of the buffer layer, which allows for well-defined stepflow growth and a high conversion of basal plane dislocations. The additional fast drift layer deposition reduced etching of the surface and the statistical chance of downfall related defects.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.13.pdf

This paper highlights the impact of different growth conditions for buffer and epitaxy layer, i.e., growth rates and combinations thereof, on the reduction of defects with a focus on macroscopic surface protruding stacking faults in epitaxial layers of silicon carbide wafers by one vendor. Defect analysis of the homo-epitaxial layer grown with different buffer and drift layer growth rates showed a significant difference and reduction in defects, especially those grouped as TrenchMOSFET device critical defects. In the first part of the experiment, it was established that a high buffer growth rate resulted in the lowest counts of critical defects, while the highest critical defect counts were achieved by a low drift-layer growth rate. These defect counts resulted consequently in the highest and lowest yield predictions when a generic die size grid was applied, for high buffer and low drift layer growth rate, respectively. The class of substrate defects, e.g., scratches, as well as triangular stacking faults are further identified to be impacted the most by different growth rates. Additionally, it is shown that further growth rate combinations, low buffer/high drift rate combination, resulted in lower critical defects and especially a reduction in device critical triangular stacking faults. We were able to show that the growth rate of both buffer and drift layer, affect the critical defect generation differently and play an important role in achieving highest quality epitaxial layers. Verifying the defect related improved growth conditions by comparing correlated electrical yield data will be the subject of future investigations.

Funding

The original version of this paper is available on https://www.scientific.net/MSF.1062.13.pdf

This work was supported by the IPCEI project (BMWi 16IPCEI625) by the German Federal Ministry for Economic Affairs and Energy by resolution of the German Bundestag.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.13.pdf

D. Baierhofer, Current SiC Power Device Development, Material Defect Measurements and Characterization at Bosch, in: 49th ESSDERC, IEEE, 2019, pp. 31-34.

B.J. Baliga, Synopsys, in: Wide Bandgap Semiconductor Power Devices, Elsevier, 2019, pp. 373-388.

T. Kimoto, SiC material properties, in: Wide Bandgap Semiconductor Power Devices, Elsevier, 2019, pp. 21-42.

T. Kimoto, H. Watanabe, Defect engineering in SiC technology for high-voltage power devices, Appl. Phys. Express 13 (2020) 120101.

S. Ha, P. Mieszkowski, M. Skowronski, L.B. Rowland, Dislocation conversion in 4H silicon carbide epitaxy, Journal of Crystal Growth 244 (2002) 257-266.

B. Kallinger, B. Thomas, S. Polster, P. Berwian, J. Friedrich, Dislocation Conversion and Propagation during Homoepitaxial Growth of 4H-SiC, MSF 645-648 (2010) 299-302.

H. Das, S. Sunkari, J. Justice, H. Pham, K.S. Park, Effect of Defects in Silicon Carbide Epitaxial Layers on Yield and Reliability, MSF 963 (2019) 284-287.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 18-22

doi: 10.4028/p-0b73tf

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-05

Revised:
2022-02-07

Accepted:
2022-02-08

Online:
2022-05-31

High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

Ruggero Anzalone , Giuseppe Greco , Fabrizio Roccaforte , Patrick Fiorenza Nicolo Piluso and Andrea Severino

STMicroelectronics, Stradale Primosole, 50, 95121 Catania, Italy

CNR-IMM, Strada VIII, n. 5 - Zona Industriale, 95121 Catania, Italy

ruggero.anzalone@st.com, giuseppe.greco@imm.cnr.it, , fabrizio.roccaforte@imm.cnr.it, patrick.fiorenza@imm.cnr.it, nicolo.piluso@st.com andrea.severino@st.com

Keywords: KOH etching, dislocations, high temperature, GaN

Abstract

In this work, the effect of high temperature molten KOH wet etching on GaN/AlGaN epilayer has been investigated for different family of dislocations. The high etching temperature (up to ) allows a good definition of the pits, making easy the observation and the counts. Such high temperature will allow a detailed study on the statistical distribution of the dislocations on whole wafer by optical microscope for screw/mixed dislocation. A comparison on dislocation density between AlGaN/GaN structure grown on Si (111) substrate and substrate has been performed.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

One of the keys for the success in the fabrication of reliable gallium nitride (GaN) -based devices depends on the ability to grow epitaxial films on substrates such as sapphire, silicon or silicon carbide, with a low density of defects [1]. In fact, the weak match in lattice parameter and thermal expansion coefficient, results in a high density ( ) of threading dislocations within the nitride film [2]. It is assumed that these defects affect the electrical performance of the devices and the optical properties of the material. For such a reason, investigating the nature of dislocations has become mandatory for GaN-based device development.

High temperature wet chemical etching is a traditionally widely used method to determine the defect density in semiconductor. For example, molten potassium hydroxide etching, performed at temperature higher than , is a well-established method for the dislocation counting and evaluation in silicon carbide [3].

In this study, the high temperature etching effect of KOH on different GaN/AlGaN samples for threading dislocation (TD) evaluation is reported.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

In details, GaN/AlGaN layers epitaxially grown on Silicon floating zone (111)-oriented substrate and on Silicon Carbide ( ) substrate were studied. For GaN grown on Si samples, to understand the effect of the etching temperature on the dislocation, different temperatures and different etching times have been studied. The temperature was investigated from to and the times change from 30 sec to 180 sec . The short time of etching is due to the rapid etching of silicon substrate on high temperature KOH . For GaN layer grown on SiC substrate, the KOH etching was performed at for 5 minutes.

Due to the very small size of the pits, SEM or TEM and AFM analysis are the only techniques capable to observe the surface and the cross section of the samples.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

In figure and b the SEM image of a GaN epitaxial layer grown on Silicon substrate after molten KOH etching performed for 1 minute at is reported (lower temperature investigated). To overcome the problem of very rapid etching of silicon substrate at such a high etching temperature in molten KOH , we deposited on the wafer back a Ni thin layer as sacrificial layer. With this expedient, it is possible to perform high temperature KOH etching on Si .

From literature, it was observed that, according to the Burgers vectors of TDs in a GaN epilayer, pure edge TDs are emerged into the terraces, while screw/mixed TDs are associated with the step terminations. Large etch pits exactly correspond to the step terminations, and the small etch pits always appear within the terrace [4]. Screw/mixed TDs are more readily etched and then expand into large etch pits, while edge TDs are more resistant to chemical etching. From this observation, the large etch pits originate from the screw/mixed and small ones from pure edge TDs. The origin of "very large" dislocation, which goes through the entire thickness of the GaN layer (about 2 microns), is under investigation. A plausible origin can be the deep etching of the several pits (thousand for ) present on the GaN surface after the epitaxial growth process and before the etching process (see figure 1c).

Figure 1. (a) and (b) SEM images of the GaN surface (grown on Si substrate) after molten KOH etching for 120 sec at . Three different family of pits as a function of dimension are visible. The dislocation density of the sample was evaluated about . (c) Example of pit on GaN surface after the growth (without KOH etching).

Figure 1. Figure 1. (a) and (b) SEM images of the GaN surface (grown on Si substrate) after molten KOH etching for 120 sec at . Three different family of pits as a function of dimension are visible. The dislocation density of the sample was evaluated about . (c) Example of pit on GaN surface after the growth (without KOH etching).

The dislocation density of the sample reported in figure 1a was evaluated about , in agreement with other literature findings [5-6] using different chemistry of etching or different analysis technique.

The temperature range explored is from to and no different features were observed, except the enlargement of the "large pits" and an initial coalescence phenomenon for small pits. In this way, by increasing the time of the etching and the temperature, in the early future we will be able to have a statistical density distribution of the dislocations (at least for screw/mixed dislocation family) on whole wafer with an easy distinguishment of the large pits just by an optical microscope observation (entire 6 inch wafer will be observed). Today we are restricted only to the high-resolution techniques (SEM, TEM, AFM) that are impossible to extend to whole wafer.

The surface profile of the sample etched for 1 minute at was observed by AFM and reported in figure 2 with two different scales ( micron and micron). From the line-scan profile, the pits shown different depth and width. This is due to the different nature of dislocation as screw/mixed or pure edge TDs. The pits density evaluated from the AFM image is , not far from the results obtained by SEM analysis.

Figure 2. AFM image of the GaN surface after molten KOH etching for120 sec at , and line scan profile of the surface (left: and right ). The pits density evaluated from the AFM image is .

Figure 2. Figure 2. AFM image of the GaN surface after molten KOH etching for120 sec at , and line scan profile of the surface (left: and right ). The pits density evaluated from the AFM image is .

Figure 3. SEM image of the GaN surface (grown on substrate) after molten KOH etching for 5 min at . Three different family of pits as a function of dimension are visible.

Figure 3. Figure 3. SEM image of the GaN surface (grown on substrate) after molten KOH etching for 5 min at . Three different family of pits as a function of dimension are visible.

In figure 3, the results of KOH etching performed on GaN layers epitaxially grown on 4 H SiC are also presented. In this case, the KOH etching times was prolonged to 5 minutes and the temperature is . Also in this case, three different families of dislocations in terms of pits dimension are visible. The dislocation nature is the same of the one observed on Si substrate. The high temperature adopted makes the pits shape very well defined and easy to be counted. The dislocation density measured in GaN on SiC samples was found in the range , i.e. at least a factor of 3 lower than in Silicon substrate. Specifically, the AFM performed on the same GaN/SiC sample (figure 4) shows a similar profile of the one previously observed in Si, but with a lower dislocation density: around . The number of dislocations is quite similar to that observed with the AFM without the KOH etching of the surface (image not shown), .

Figure 4. AFM image of the GaN surface after molten KOH etching for 5 min at and line scan profile of the surface (left: and right ). The pits density evaluated from the AFM image is .

Figure 4. Figure 4. AFM image of the GaN surface after molten KOH etching for 5 min at and line scan profile of the surface (left: and right ). The pits density evaluated from the AFM image is .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

In this work, the feasibility of high temperature molten KOH etching process on GaN sample has been shown. We compared GaN/AlGaN layers grown on Silicon and SiC substrates, finding difference in terms of pits density. The high temperature coupled with long time etching make possible, in the early future, the implementation of optical microscope technique for whole wafer scan ( 6 and 8 inches) for the screw/mixed dislocation family (the large pits).

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

This work has been partially supported by the Italian Ministry for University and Research (MUR) in the framework of the National Project PON EleGaNTe (Electronics on GaN-based Technologies), ARS01_01007.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.18.pdf

S. Nakamura, T. Mukai, and M. Senoh, Appl. Phys. Lett. 64, 1687 (1994).

X. H. Wu, L. M. Brown, D. Kapolnek, S. Keller, B. Keller, S. P. Den Baars, and J. S. Speck, J. Appl. Phys. 80, 3228 (1996).

R. Anzalone, N. Piluso, A. Severino, S. Lorenti, G. Arena and S. Coffa, Materials Science Forum 1662-9752, Vol. 963, pp 276-279

J Chen, J F Wang, H Wang, J J Zhu, S M Zhang, D G Zhao, D S Jiang, H Yang, U Jahn and K H Ploo. Semicond. Sci. Technol. 21 (2006) 1229-1235

L. Zhang, Y. Shao, Y. Wu, X. Hao, X. Chen, S. Qu, X. Xu. Journal of Alloys and Compounds 504 (2010) 186-191

A. Pandey, B. S. Yadav, D. V. Sridhara Rao, D. Kaur, A. K. Kapoor, Appl. Phys. A (2016) 122:614

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 23-27

doi: 10.4028/p-aaf11g

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-12

Revised:
2022-02-08

Accepted:
2022-02-24

Online:
2022-05-31

3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

The original version of this paper is available on https://www.scientific.net/MSF.1062.23.pdf

FERRO Gabriel , YEGHOYAN Taguhi , CAUWET François , COINDEAU Stéphane , ENCINAS Thierry and SOULIERE Véronique

Laboratoire des Multimatériaux et Interfaces, UMR CNRS 5615, 6 rue Victor Grignard, Lyon 1 University, 69622 Villeurbanne (France)

CMTC - SIMaP, Université Grenoble-Alpes, 1260 rue de la piscine, 38402 Saint Martin d'Hères (France)

gabriel.ferro@univ-lyon1.fr, taguhi.yeghoyan@gmail.com, stephane.coindeau@grenoble-inp.fr, ethierry.encinas@grenoble-inp.fr, veronique.souliere@univ-lyon1.fr

Keywords: 3C-SiC, heteroepitaxy, substrate orientation, high index, morphology

Abstract

This work investigates the heteroepitaxial growth on silicon substrates having a wide variety of orientations, i.e. (100) on axis and off, (111), (110), (211), (311), (331), (510), (553) and (995). All the 3C-SiC layers were grown using the same two-step CVD process with a growth rate of . According to X-ray diffraction characterizations, direct heteroepitaxy (layer having exactly the same orientation as the substrate) was successful on most of the Si substrates except for (110) one which was the only orientation leading to obvious polycrystalline deposit. Each layer led to a specific surface morphology, the smoothest being the ones grown on , and (995) substrates. None of these layers cracked upon cooling though those grown on , (211) and (553) substrates were highly bowed.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.23.pdf

Despite decades of research and hundreds of published articles, the 3C-SiC heteroepitaxially grown on silicon substrate has still not reached sufficient crystalline quality for industrial use in electronics. The growths are usually performed with the (100) or (111) orientation of the Si substrate, both generating their own additional difficulties such as antiphase domains generation for the former case or cracks for the latter case. The use of other substrate orientations, such as (110) and (211), was scarcely investigated despite interesting features in terms of defects density reduction [1,2], surface morphology [3,4] or stress reduction in [111] oriented films [4-6]. From these studies, it seems that the optimal growth conditions could be specific to each orientation which makes the investigations trickier. In addition, the use of higher Miller's index substrate orientations were never reported so far for 3C-SiC heteroepitaxial growth. There is thus still room for purely exploratory work on the effect of Si substrate crystalline orientation on the resulting 3CSiC layers. This is done in the present work.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.23.pdf

The layers were deposited by atmospheric pressure chemical vapour deposition (CVD) using gas mixture. The Si substrates were pieces of with various crystalline orientations, comprising (100), (111), (110), (211), (311), (331), (510), (553) and (995), as stated by the supplier. All orientations were on-axis except for (100) case for which off-axis wafers were used additionally. They were ultrasonically degreased in methanol before loading in the CVD reactor. The growth procedure involved in-situ removal of the Si substrate native oxide under at . Then, a standard two-step process was used including 10 min carbonization at under 12 sccm propane followed by 60 min epitaxy at under ratio of 4 using 1.5 sccm silane and 2 sccm propane. This is our optimal procedure for growing state-of-the-art 3C-SiC on
substrate at a growth rate of . Each growth run was performed on four to five different Si substrates, including at least one piece of (100) oriented wafer for reference purpose.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.23.pdf

The resulting 3C-SiC layers morphologies obtained on each kind of Si substrate are shown in Figure 1. They clearly display different surface features and roughnesses. By naked eyes, samples grown on , (211), (311), (553) and (995) look mirror like while the other ones are milky ((331), (510)) to dull ((110), (111)). The smoother surface (displaying the finest microstructure) seems to be the one grown on (100) off and (995) substrates. Interestingly, none of these layers cracked upon cooling, even the 3 C -SiC(111) layers which are known to undergo high tensile stress. The limited samples size probably explains the absence of crack. However, the bow of some samples, due to accumulated thermal stress, is detectable by optical microscopy at x1000 magnification via the impossibility to focus correctly on the full image area. These highly bowed layers ( 30 to from center to the edge), grown on , (211) and (553) substrates, are all concave shaped and thus tensile strained. More experimental and theoretical work is required for correlating these orientations with the bow.

Atomic force microscopy (AFM) images obtained on each of these samples (see Figure 2) follow the general tendencies found by optical microscopy. The corresponding RMS values (see Table 1) confirms that the smoothest surfaces are obtained on (100) off and (995) orientations which display similar grain-like microstructure of lateral size. Layer grown on (110) substrate is by far the roughest. Elongated and/or parallel features are commonly found on other orientations, with apparent boundaries between domains in some cases ((331), (510)).
X-Ray diffraction (XRD) characterizations (in - mode) were performed on all these samples in order to obtain information on the epitaxial relationships which may exist between each substrate/layer couple and to have. The results are summarized in Table 1. The layers with low Miller index show the same orientation as the one of the substrate which means that the heteroepitaxial growth was successfully achieved. This was not the case for (110) orientation since both 3C-SiC(111) and (110) planes were detected. This layer is obviously polycrystalline.

Table 1. Summary of the XRD and AFM ( scan) results obtained on the -SC layers grown on differently oriented Si substrate.

Si orientation
3C-SiC - XRD
AFM - RMS (nm)

peak
2θ (°)
3C-SiC layers

(100)
(200)
41.5
16

(100) 2°off
(200)
41.5
3.4

(110)
(111)
(220)
35.7
60.02
97.3

(111)
(111)
35.7
53

(211)
(422)
105.14
16

(311)
(311)
72.03
12,7

(331)
(331)
100.76
17,3

(510)
-
-
25,2

(553)
-
-
15,7

(995)
-
-
8,8

Such orientation mixing was already reported for the use of substrate [4, 7] while other authors observed also the sole formation of (111) oriented 3C-SiC layers [2,8]. It seems that this particular (110) substrate orientation requires adapting the growth conditions for optimizing either (111) or (110) full orientation of the 3C-SiC layer. For the layers grown on Si substrate with h Miller index ((510), (553) and (995)), no XRD peak from the 3C-SiC layer or even the substrate could be detected. These high index planes are indeed not known as diffracting ones in XRD standard configuration. If the layers were polycrystalline, we would probably have detected some low index 3C-SiC peaks such as (111) or (200), so that their absence is a hint toward
monocrystallinity. If these layers are monocrystalline, their low-index planes could diffract by applying a proper tilt of the sample. Calculation of the crystallographic angles between these low and high index planes are reported in Table 2. One can see that the misorientation angle between these high and

Table 2. Calculated angles between planes in crystalline structure.

| (510) | (553) | (995)
(111) | 47.21° | 12.27° | 13.81°
(100) | 11.3° | 49.39° | 48.8°

low index planes is high ( ) which explain their absence in the patterns recorded in standard mode. Deeper XRD investigations, like using pole figures, are thus requested for confirming this point. This was performed on sample grown on (995) oriented substrate since this sample displays unusual grain-like surface morphology (which could be interpreted as resulting from columnar growth or twinning) and interesting low surface roughness. In Figure 3 are displayed the (111) pole figures recorded on the Si substrate and the 3CSiC deposit. These figures are very similar, indicating that the (111) planes orientation of Si and 3C-SiC are identical. This means that the 3C-SiC layer is epitaxial with the Si substrate, without any twinning. Moreover, the central spot appears for a angle of about , value which is close to the calculated angle between (111) and (995) planes (see Table 1). The three spots located at and and are expected for a three-fold symmetry axis around the central [111] direction. Note that a weak spot appears also at about for both substrate and layer. This spot is not predicted by the simulation and its presence remains under investigation. The crystal quality of the SiC-3C layer needs to be evaluated, for example by Rocking-Curve measurements, but the width of the spots observed along rotation on the (111) pole figure of 3C-SiC seems promising on this point. Pole figures remain to be done on the two other layers grown on and (553) (which did not display any XRD peak in mode) in order to confirm their heteroepitaxial nature (in which we strongly believe).

Figure 3. XRD pole figures recorded on the (995) oriented sample and showing the (111) planes of both the Si substrate (a) and the 3C-SiC layer (b).

Figure 1. Figure 3. XRD pole figures recorded on the (995) oriented sample and showing the (111) planes of both the Si substrate (a) and the 3C-SiC layer (b).

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.23.pdf

The heteroepitaxial growth of 3C-SiC layers on Si substrate having various orientations was found to be successful for most of the orientations. Only (110) orientation led to obvious polycrystalline growth. High bowing was observed for , (211) and (553) substrates while low roughness was found for off, and (995). Deeper XRD and Raman spectroscopy analyses are currently under investigation for completing this exploratory work.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.23.pdf

T. Nishiguchi, Y. Mukai, M. Nakamura, K. Nishio, T. Isshiki, S. Ohshima, S. Nishino, Mater. Sci. Forum 457-460, (2004) 285-288

T. Nishiguchi, M. Nakamura, K. Nishio, T. Isshiki, S. Nishino, Appl. Phys. Lett. 84(16) (2004) 3082-3084

T. Nishiguchi, Y. Mukai, S. Ohshima, S. Nishino, Phys. Stat. Sol. (c) 0 (7), (2003) 2585-2588

R. Anzalone, A. Severino, G. D'Arrigo, C. Bongiorno, G. Abbondanza, G. Foti, S. Saddow, F. La Via, J. Appl. Phys. 105 (2009) 084910

A. Konno, Y. Narita, T. Ito, K. Yasui, H. Nakazawa, T. Endoh, M. Suemitsu, ECS Transactions, 3 (5) (2006) 449-455

R. Anzalone, C. Bongiorno, A. Severino, G. D'Arrigo, G. Abbondanza, G. Foti, F. La Via, Appl. Phys. Lett. 92 (2008) 224102

S. Sambonsuge, S. Ito, S. Jiao, H. Nagasawa, H. Fukidome, S.N. Filimonov, M. Suemitsu, Phys. Stat. Sol. (A) 213 (5) (2016) 1125-1129

H. Zheng, J. Su, Z. Fu, G. Li, X. Li, Ceramics International 34 (3) (2008) 657-660

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 28-32

doi: 10.4028/p-85ph3t

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-02-02

Accepted:
2022-03-10

Online:
2022-05-31

A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

Daichi Dojima , Moeko Matsubara , Hideaki Minamiyama and Tadaaki Kaneko

Kwansei Gakuin University, 2-1 Gakuen, Sanda, Hyogo, 669-1361, Japan

Toyo Aluminium K.K., 4-8-1 Aioi-Cho, Yao, Osaka, 581-0082, Japan

d.dojima@kwansei.ac.jp, moeko-matsubara@toyal.co.jp, chideaki-

minamiyama@toyal.co.jp, kaneko@kwansei.ac.jp

Keywords: Hetero-epitaxial growth, Crack reduction, Thermal stress relaxation, Flexible SiC substrate

Abstract

The fabrication of novel semiconductor seed crystals using hetero-epitaxial growth on substrates such as Si , sapphire, and SiC , which have been successfully grown to large diameter and high quality, is very attractive as a breakthrough technology. However, a critical issue in heteroepitaxial growth is the formation of cracks due to thermal stress caused by the difference in the thermal expansion coefficient between the substrate and the growth layer during the cooling process after growth. In this study, we propose a method to reduce thermal stress by using a "Flexible substrate," which is a substrate with mechanical flexibility enhanced by removing more than of its volume with periodic through holes. Using this method, we obtained an AlN hetero-epitaxial growth layer with absolutely no cracks observed. This method is applicable not only for AlN on SiC but also for the fabrication of various new semiconductor materials.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

The recent trend toward lower cost and larger diameter SiC wafers have opened the door for their application as seed substrates for hetero-epitaxy of large diameter new-generation semiconductor bulk crystal. Due to its high band-gap and thermal conductivity, AlN has a high potential for DUVLED and high-frequency transistors [1]. However, the cost of AlN is very high because the wafer diameter has not expanded over several years due to its extremely slow radial growth rate. Since the lattice mismatch between those materials is as tiny as , high-quality AlN bulk crystals can be obtained using SiC as a substrate. For heteroepitaxial growth of , the sublimation method at temperatures as high as is used. The most severe problem in AlN/SiC hetero-growth is also the formation of the crack in the AlN growth layer due to thermal stress because of the significant difference in the thermal expansion coefficient of (Fig. 1. (a)). Therefore, using Pendeo growth with mesa-structured SiC substrates has been considered to suppress the cracks. In this method, thermal stress destroys the mesa structure and separates the AlN growth layer from SiC substrate to reduce cracking (Fig. 1. (b)). The mesa structure on the SiC surface is fabricated by selective ion etching or the ununiform thermal decomposition of the SiC surface in the initial stage of AlN growth [2]. However, the critical issue of this method is that the lateral wing-like of AlN is deformed due to lattice mismatch and thermal stress, causing dislocation and grain boundary generation [3, 4] (Fig. 2. (a)). Therefore, a method to prevent crack and grain boundary formation in AIN/SiC heteroepitaxial growth is necessary. To solve this issue, we propose the use of the Flexible SiC substrate to reduce the thermal stress (Fig. 1. (c)). The surface of Flexible SiC substrate is patterned to be a single connected surface, resulting in a zippering growth mode of AlN when closing the through-hole. In zippering growth, the grain boundary and the dislocations generation are significantly suppressed (Fig. 2. (b)) [5]. In this study, we examine the crack suppression effect of the AlN hetero-epitaxial growth layer using the Flexible SiC substrate.

Fig. 1. AlN growth processes on the (a) un-processed, (b) mesastructured, and (c) Flexible SiC substrate.

Fig. 1. AlN growth processes on the (a) un-processed, (b) mesastructured, and (c) Flexible SiC substrate.

Fig. 2. (a)Pendeo epitaxy on the mesa-structured substrate and (b) Zippering growth on the Flexible substrate.

Fig. 2. (a)Pendeo epitaxy on the mesa-structured substrate and (b) Zippering growth on the Flexible substrate.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

Flexible SiC substrates were fabricated from thick off by pulsed laser processing to remove of its volume by periodic through-hole. The patterns were designed to improve the isotropic flexibility, as reported by C. Schumacher et al. [6]. All samples were thermally etched at by Si-vapor etching [7] for about to remove polishing and laser processing damage on the SiC seed substrate surface. For the AlN sublimation growth, the temperature, , and pressure were set at , and 30 kPa . a high-temperature gradient environment of is applied to suppress unintentional SiC surface decomposition at the initial phase of AlN growth [8]. High-purity AlN powder manufactured by Toyo Aluminum K. K. was used as the source material. The SiC substrates and the AlN growth layer were observed using a laser microscope, optical microscope, Raman spectroscopy (excitation wavelength: 532.3 nm ), and SEM ( 1 kV ).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

Fig. 3. shows the laser microscopy mapping images of the Unprocessed SiC substrate and the Flexible SiC substrate. It is observed that most of the volume of the Flexible SiC substrate is removed by the through holes made by laser processing. Flexible SiC substrates are treated with periodic through holes by pulsed laser, and about of the volume of the SiC substrate is removed. Since the intense laser processing introduces significant processing damage to the SiC substrate surface, thermal etching was used to remove it. Fig. 4. shows bird's eye view SEM images of (a) after laser processing and (b) thermally etched Flexible SiC substrate. After laser processing, the surface roughness due to laser ablation can be observed on the SiC surface. It can be seen that the thermal etching of on the lasered flexible SiC substrate removes the damage and restores the surface flatness. Therefore, in order to eliminate the harmful effects of laser processing, all SiC substrates will be thermally etched before AlN growth.

Fig. 3. Laser microscopy images of (a) the unprocessed SiC substrate and (b) the Flexible SiC substrate.

Fig. 3. Laser microscopy images of (a) the unprocessed SiC substrate and (b) the Flexible SiC substrate.

Fig. 4. 1 kV -SEM bird-view image of Flexible SiC substrate (a)as laser processing and (b) after thermal etching.

Fig. 4. 1 kV -SEM bird-view image of Flexible SiC substrate (a)as laser processing and (b) after thermal etching.

Next, a thick AlN growth layer was grown on these SiC substrates using the sublimation method at a growth temperature of . Fig. 5. shows the optical microscope and SEM images of AlN grown on unprocessed SiC substrate and Flexible SiC substrate, respectively. The AlN on the unprocessed SiC substrate was observed to have many cracks in both the optical microscope image and SEM, and even the underlying SiC substrate was cracked. In contrast, no cracks were observed in the AlN growth layer on the Flexible SiC substrate in either macroscopic observation by optical microscopy or microscopic observation by SEM. This result suggests that using a Flexible substrate can reduce the thermal strain induced during the cooling process of hetero-epitaxial growth.

The results of the Raman spectroscopy evaluation of these samples are shown in Fig. 6. Fig. 6 (a) and (b) show the measured Raman peak shift mapping images of AIN on unprocessed SiC substrate and flexible SiC substrate, respectively. The Raman peak shift is known to vary with the strain of the AlN crystal, and is for an unstrained AlN single crystal [9]. The fact that the average Raman shift value shifts to the lower frequency side for unstrained AlN in both samples indicate that tensile strain is introduced. From these results, we can see that both samples have introduced thermal strain. In the AlN growth layer on the Unprocessed SiC substrate, there are linear regions of stress relaxation along the <11-20> direction. Cracks in the AlN growth layer tend to form along with the direction so that its stable surface, , is exposed. Therefore, the linear stress relaxation region along the <11-20> direction is considered to be the relaxation of thermal strain by the cracks. On the other hand, no linear stress relaxation region was observed in the AlN-grown layer on the flexible SiC substrate, which supports the absence of cracks. The fact that the average tensile stress is also slightly higher can be attributed to the fact that stress relaxation has not occurred.

Fig. 5. Optical microscopy images and SEM images of thick AlN grown layer surface on (a), (c) the unprocessed SiC substrate and (b), (d) the Flexible SiC substrate.

Fig. 5. Optical microscopy images and SEM images of thick AlN grown layer surface on (a), (c) the unprocessed SiC substrate and (b), (d) the Flexible SiC substrate.

Fig. 6. (a)Raman peak shift mapping image of AlN on unprocessed SiC . Same area observation images of AIN on Flexible SiC by (b)Raman peak shift mapping, (c)optical microscopy, and (d)Raman peak FWHM mapping.

The optical microscope images and Raman peak FWHM mapping images of the AlN growth layer on the flexible SiC substrate are shown in Fig. 6. (c) and (d), respectively. The flexible SiC substrate is seen through the AlN growth layer in the optical microscope image. It can be seen that the pattern of the SiC substrate and the region with large FWHM observed in the FWHM mapping are in the same location. It is known that a lattice mismatch generates a high density of dislocations of about at the interface between AlN and SiC , and that the dislocation density is significantly smaller when the hetero-grown layer forms a hollow structure [2,10]. This suggests that the flexible substrate can also be expected to reduce the crystal defect density by reducing the interfacial area.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

In conclusion, we proposed a method to suppress thermal stress during the cooling process, which is a critical issue in hetero-epitaxial growth, by using Flexible SiC substrate with periodic through holes fabricated by laser processing. As a result of the heteroepitaxial growth of AlN with a thickness of on a Flexible SiC substrate with of the volume removed, no cracks were observed by SEM and optical microscopy. In addition, no crack-induced stress relaxation was observed in strain analysis using Raman spectroscopy. Therefore, the use of Flexible substrates is expected to lead to breakthroughs in the development of various new materials using heteroepitaxial growth.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

We are grateful to Mr. Kiyoshi Kojima of Toyota Tsusho Corporation for technical support on SiC surface processing and to Toyo Aluminium K. K. for providing high-purity AlN source material.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.28.pdf

Hirokuni Tokuda, Maiko Hatano, Norimasa Yafune, Shin Hashimoto, Katsushi Akita, Yoshiyuki Yamamoto, and Masaaki Kuzuhara, High Al Composition AlGaN-Channel High-Electron-Mobility Transistor on AlN Substrate, Appl. Phys. Express, 3 (2010) 121003.

G. R. Yazdi, R. Vasiliauskas, M. Syväjärvi, and R. Yakimova, Fabrication of free-standing AlN crystals by controlled microrod growth, J. Cryst. Growth, Vol. 310, issue 5 (2008) 935-939.

Tsvetanka S. Zheleva, Scott A. Smith, Darren B. Thomson, Kevin J. Linthicum, Pradeep Rajagopal, and Robert F. Davis, Pendeo-epitaxy: A new approach for lateral growth of gallium nitride films, J. Electron. Mater., 28 (1999) L5-L8.

R. R. Sumathi, R. U. Barz, P. Gille, and T. Straubinger, Influence of interface formation on the structural quality of AIN single crystals grown by sublimation method, Physica Status Solidi C, 8.7-8 (2011) 2107-2109.

Philip G. Neudeck, J. Anthony Powell, Glenn M. Beheim, Emye L. Benavage, and Phillip B. Abel, Enlargement of step-free SiC surfaces by homoepitaxial web growth of thin SiC cantilevers, J. Appl. Phys., 92 (2002) 2391.

Christian Schumacher, Steve Marschner, Markus Gross, and Bernhard Thomaszewski, Mechanical characterization of structured sheet material, ACM Trans. Graph., Vol. 37, No. 4, 148 (2018) 1-15.

Shoji Ushio, Tatsuya Karaki, Kenta Hagiwara, Noboru Ohtani, and Tadaaki Kaneko, Surface Phase Diagram of 4 H -SiC Step-Terrace Structures during Si-Vapor Etching in a TaC Crucible, Mater. Sci. Forum, Vol. 717-720 (2012) 573-576.

Daichi Dojima, Koji Ashida, and Tadaaki Kaneko, In-situ growth mode control of AIN on SiC substrate by sublimation closed space technique, J. Cryst. Growth, Vol. 483, 1 (2018) 206-210.

Martin Kuball, Raman spectroscopy of GaN, AlGaN and AlN for process and growth monitoring/control, Surf. Interface Anal., 31 (2001) 987-999.

Yoshitaka Taniyasu, Makoto Kasu, and Toshiki Makimoto, Threading dislocations in heteroepitaxial AlN layer grown by MOVPEon SiC ( 0001 ) substrate, J. Cryst. Growth, 298 (2007) 310-315.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 33-37

doi: 10.4028/p-3dn536

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-02-01

Accepted:
2022-02-08

Online:
2022-05-31

The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1062.33.pdf

Brunella Cafra , Nicolò Piluso , Agata Grasso , Aye Aye Moon Andrea Severino

ST Microelectronics, stradale primosole, 5095121 Catania, Italy

ST Microelectronics, 629, Lorong 4/6, 319521, Toa Payoh, Singapore

brunella.cafra@st.com, nicolo.piluso@st.com, agata.grasso@st.com, aye-aye.moon@st.com, andrea.severino@st.com

Keywords: defect density, flexural strength, substrate thinning, thermal treatment.

Abstract

In this work the intrinsic and induced defects related to the mechanical strength of wafer have been investigated by considering substrates having different dislocation density and subjected to different treatments such as thinning process and high temperature bulk and laser annealing. Three point bending test has been performed on die extracted from the substrates in order to calculate the stress the die can withstand at breakage (flexural strength). The variation of intrinsic defect density seems does not act to modify the material flexural strength. Conversely, a considerable correlation between the induced defect density and flexural strength has been found.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.33.pdf

The presence of structural extended and point-like defects can impact SiC-based devices performances not only from the electrical but also from the mechanical point of view. Nowadays it is well known that SiC defects are detrimental to die electrical reliability and performance ; the impact they can have on device mechanical yield is not properly investigated. In this respect, an investigation on the correlation between defectivity, whether intrinsic or processing induced, and the mechanical strength of substrate can be of use. The flexural strength, that is the stress the die can withstand under an applied load at breaking, has been used as reference parameter. Three point bending (3pb) tests have been exploited on well identified substrate regions and the collected data have been correlated with the corresponding defect density.

Experimental

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Commercially available substrates have been used in this study. A set of substrates, characterized by different dislocation density (wafer #1 and wafer #2), have been used to study the effect of intrinsic SiC defectivity on mechanical strength. KOH wet etch process at for 5 min has been performed to highlight the SiC crystal defects. Wafer surface optical inspection after KOH etching has been performed by automated optical microscopy (nSPEC by Nanotronics) to monitor the density and distribution of defects. Whole wafers have been inspected by using x10 objective. Another set of substrates have been used to study the effect of process induced defectivity on mechanical strength by performing thinning process and subsequently high temperature bulk thermal treatment and laser treatment at high fluence. Failure strength investigation has been performed on all wafers by 3 point bending test (Instron 5566) on a variety of die properly selected per defect density along wafers. The tool accuracy is of and the support span length is of 3 mm . Load has been applied in correspondence of the center of the span length and has been increased at a constant rate of .

Results and Discussion

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Commercially available substrates with off-angle and different defect density have been used in this experiment. After KOH wet etching [ ] optical images have been collected all along the wafers size and the corresponding defect density map is shown in figure 1 a) and 1 b) respectively for wafer#1 and wafer #2. Dots of different colors refers to different defect dimensions. The overall counting of 26621 defects have been detected for wafer #1 and 6251 defects have been counted for wafer #2. Beside the different defect counts, strong variation is also observed in defect distribution on wafer, marked with black and red circles respectively for high density (HD) and low density (LD) regions. Should be also underlined that different defect density among wafers is linked to the belonging ingot and the relative position within it as well as on growth conditions such as temperature, pressure and vapor equilibrium. To obtain statistically significant data, a total amount of 60 dies of have been taken from each wafer from selected zones. The defect density calculated per each zone is reported in figure 2. In our wafers, based on the area under investigation, whether HD or LD, mainly BPD originated from stress caused by strain from lattice distortion has been found and BPD arrays, half-loop array (HLA), have been found on HD zone.

Figure 1. Wafer scale defect density distribution as obtained by n -spec analysis after KOH . etching for wafer #1 (a)) and wafer #2 (b).

Figure 1. Figure 1. Wafer scale defect density distribution as obtained by n -spec analysis after KOH . etching for wafer #1 (a)) and wafer #2 (b).

Dies selected have been subjected to three-point bending test in order to calculate the stress the die can withstand at breakage (flexural strength)[ ] that, based on the theory of a suspended beam of known geometry supported on both ends , it can be represented by:

Where F is the maximum load, that is the load which causes die breakage and L,W and d respectively the length, width and thickness of the die. In our case the die dimensions are and the die thickness is 350 um . Flexural strength values as calculated in correspondence of the dies selected from HD and LD regions on both wafers and compared with our finding in terms of defect density per each zone are shown in figure 3. On both wafers low flexural strength values have been found in correspondence of a defect density of about 500/die size, the flexural strength increasing by a factor of two if the defect density is higher than 600/die size and keeping almost constant on large range of defect density.

Figure 2. Defect density as a function of wafers zone per wafer#1 (red) and wafers #2 (blue).

Figure 2. Figure 2. Defect density as a function of wafers zone per wafer#1 (red) and wafers #2 (blue).

No significant changes indeed have been observed for die strength in regions where defect density was up to 2000/ die size. It is to note that dies having low flexural strength in correspondence of low defect density represent 7%-10% of total low density dies analyzed.

Figure 3. Variations of flexural strength as a function of defect density for intrinsic defects.

Figure 3. Figure 3. Variations of flexural strength as a function of defect density for intrinsic defects.

Apart from the intrinsic defects present in crystal, during the device fabrication flow the SiC substrate undergoes to processes that can induce defectivity in the form of stacking fault, micro cracks and cracks. Sources of induced defectivity are the wafer thinning process, necessary for increasing device performances, reducing undesired power dissipation and providing greater package miniaturization, as well as the high temperature thermal treatments, whether bulk or local, necessary for example for dopant activation or silicide formation. Flexural strength data as a function of the above-mentioned processes are shown in figure 4 and compared with the corresponding values
obtained for untreated SiC. The thinning process, a mechanically material removing process, causes a worsening of failure strength, which reduces from 1200 MPa to 800 MPa , across the wafers due subsurface damage in the form of microcracks and cracks introduced during the thinning. Failure strength values obtained for wafers subjected to bulk and laser thermal treatment after thinning keep almost unchanged with respect to the values obtained before thinning. With high temperature bulk annealing ( ) the SiC crystal undergoes to morphological changes with off terraces of multiple height steps and appearance of dislocation (here not shown) that contributes to keep low the failure strength. Finally, high fluence laser annealing, with high temperature gradient across the SiC surface introduces local compressive stress (estimated of the order of 100 MPa in our case) in confined region, surrounded by not thermally stressed region, that promotes further substrate damaging such as microcracks and hence possible mechanical break up.

Figure 4. Variations of flexural strength as a function of defect density in case process induced defectivity.

Figure 4. Figure 4. Variations of flexural strength as a function of defect density in case process induced defectivity.

This finding highlight that when we deal with alternative ways to the standard chemical mechanical polishing (CMP) and pure mechanical approach (dry polishing) to relief the stress induced by thinning and restore wafer surface, attention has to be devoted to the impact the process can have on the die mechanical strength.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.33.pdf

The impact the intrinsic and induced defects can have on the mechanical strength of wafer has been investigated by means of three point bending. It has been shown that the die flexural strength keeps almost unchanged on a large range of SiC crystal intrinsic defect density. As a difference, the defect density induced on SiC surface by thinning process reduces the die strength of a factor of 1.4, the value being almost unchanged in case of subsequent high temperature treatment.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.33.pdf

Bergman, J. P., Lendenmann, H., Nilsson, P. A., Lindefelt, U. & Skytt, P. Mater. Sci. Forum 353-356, 299-302 (2001).

Lendenmann, H. et al. Mater. Sci. Forum 353-356, 727-730 (2001).

11. Yao, Y.-Z.; Ishikawa, Y.; Sugawara, Y.; Saitoh, H.; Danno, K.; Suzuki, H.; Kawai, Y.; Shibata, N., Jpn. J. Appl. Phys. 2011, 50 (7R), 075502.

T. Kimoto & J. A. Cooper, Fundamentals of Silicon Carbide Technology, IEEE Wiley, 2014

NE. Dowling, "Mechanical behavior of materials: engineering methods for deformation, fracture, and fatigue, 3rd Edition," (Prentice Hall/Upper Saddle River, NJ, 2007).

Stoney G., Proc. R. Soc. Lond. 82 (1909) 172

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 38-43

doi: 10.4028/p-sg9dq0

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-08

Accepted:
2022-02-24

Online:
2022-05-31

Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer

The original version of this paper is available on https://www.scientific.net/MSF.1062.38.pdf

Kristijan Luka Mletschnig , Mathias Rommel , Gregor Pobegen , Werner Schustereder and Peter Pichler

Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria

Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystraße 10, 91058 Erlangen, Germany

Kompetenzzentrum Automobil- und Industrieelektronik GmbH, Europastraße 8, 9524 Villach, Austria

KristijanLuka.Mletschnig@infineon.com, Mathias.Rommel@iisb.fraunhofer.de, Gregor.Pobegen@k-ai.at, Werner.Schustereder@infineon.com, Peter.Pichler@iisb.fraunhofer.de

Abstract

The excellent material properties of the wide band gap semiconductor SiC are accompanied by challenges in device processing. Of particular importance is the incomplete activation of implanted Al acceptors after high-temperature annealing. In this work, we present a novel approach in applying the differential-capacitance method to lateral MOS capacitors, where systematic errors in its characterization are reduced by introducing a buried current-spreading layer. We find that the implantation of an additional current-spreading layer significantly reduces series resistance effects and enables a reliable capacitance-voltage measurement of low dopant concentrations of p-type wells in n-type epitaxial layers. The measurement of an Al box-like profile implanted at and resulting in a doping concentration of shows full activation after annealing at for 30 minutes.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.38.pdf

The aluminum acceptors in SiC were reported to be incompletely activated whereby the activation degree depends on the implanted dopant concentration, annealing temperature, and annealing time [1]. Dopant activation in is typically derived from Hall measurements [2], though this method requires high sample temperatures due to the rather high ionization energy of Al. Besides, the method still leaves room for ambiguities since the Hall scattering factor is significantly less established for implanted high dopant concentrations than for low-concentration epitaxial layers [3] despite recent thorough investigations [4].

Another standard method to determine activation at room temperature used also in our work is the direct measurement of the net active dopant concentration within a space-charge region (SCR) via capacitance-voltage (C-V) measurements [5, 6] as determined by equation 1, with elementary charge , contact area , dielectric constant and relative permittivity .

For SiC, this approach was e.g. demonstrated for p-type epitaxial layers on p-type substrates using Schottky barrier diodes in vertical configuration [7] or using mercury probes in vertical and lateral configuration [8]. In order to facilitate a direct characterization of p-type implanted and annealed areas in n-type epitaxial layers on n-type substrates we fabricated planar MOS capacitors with laterally contacted p-wells (Fig. 1) [9].

The equivalent circuit of this setup is assumed to consist of a capacitor with capacitance , which is to be determined, with an Ohmic parallel conductance , as well as a series resistor with resistance , as depicted in Fig. 1. The measured quantities, in turn, are the capacitance and conductance in parallel circuit, which depend on the angular probe frequency . The components of both equivalent circuits are related to each other via equations 2 a and 2 b :

Thus, measuring the capacitance assuming a parallel equivalent circuit, the capacitance decreases for high AC frequencies with increasing series resistance . To determine the frequencyindependent true capacitance , the condition must be fulfilled [10]. For low Al acceptor concentrations in SiC (as e.g. in p-type implanted wells in n-type epitaxial layers) the series resistance can become critical, especially for large contact areas. Furthermore, depending on the p- and n-type concentrations, the voltage-dependent SCR of the MOS capacitor can extend up to the intrinsic SCR of a p-well's p-n-junction, leading to a full or partial pinch-off in the conductive channel between the SCRs, causing a voltage dependent .

To reduce and prevent a pinch-off, we implanted and annealed a buried Al layer of moderate concentration below the Al box-like profile, acting as a current-spreading layer during the capacitance measurement (Fig. 1). To further reduce , the annular contact implantation was extended in depth to connect the current-spreading layer.

Fig. 1 Cross-sectional (left) and top view (right) of a lateral MOS capacitor with an annular Ohmic contact ring, current-spreading layer and vertically extended contact implantation, including the schematics of the proposed equivalent circuit. Sketch is not to scale.

Fig. 1. Cross-sectional (left) and top view (right) of a lateral MOS capacitor with an annular Ohmic contact ring, current-spreading layer and vertically extended contact implantation, including the schematics of the proposed equivalent circuit. Sketch is not to scale.

Experimental Details

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Lateral MOS capacitors were processed on n -type 4 H -SiC substrates with a nitrogendoped epitaxial layer. An Al box-like profile with a plateau concentration was implanted through a 50 nm stray oxide at . The profile consists of multiple energy implantations with parameters presented in Table 1. This Al well was implanted through a circular opening with a diameter of about in an mask structured by plasma etching. Additionally, in part of the samples Al was implanted at with an energy of 900 keV to a peak concentration of to form a current-spreading layer.

Table 1: Implantation parameters for the Al box-like profiles with optional current-spreading layer.

Energy [keV]
30
50
75
105
145
200
300
900

Dose [cm⁻²]
3·10¹⁷ cm⁻³
5.4·10¹¹
7.5·10¹¹
9.0·10¹¹
1.2·10¹²
1.6·10¹²
2.3·10¹²
5.4·10¹²
2.4·10¹⁴

Dose [cm⁻²]
1·10²⁰ cm⁻³
1.8·10¹⁴
2.5·10¹⁴
3.0·10¹⁴
4.0·10¹⁴
5.2·10¹⁴
7.6·10¹⁴
1.8·10¹⁵
/

A contact-implantation ring with a width of and a box-like depth profile with a plateau concentration of was implanted at into the outer rim (see Table 1 for the implantation parameters). This high-concentration profile extends towards the current-spreading layer, as schematically depicted in Fig. 1.

Following the removal of the oxide mask, the wafer was protected with graphite. After activation annealing at for 30 minutes, the graphite capping layer was removed and a 100 nm TEOS oxide was deposited and densified, later acting as oxide layer in the MOS structure. A Ni silicide Ohmic contact ring was formed in the contact regions via rapid thermal processing. A thick Al top-metallization was then deposited on the Ti/TiN liners and structured such that the central contact pad has a diameter of about and a distance to the Ohmic contact ring of about silicide backside Ohmic contacts were formed by thermal annealing.

The capacitance-voltage characteristics were measured with an Agilent 4294 A precision impedance analyzer. The p-well is inherently isolated from the n-type epitaxial layer through the intrinsic p-n-junction. To keep the SCR of the p-n-junction unbiased, the annular contact of the lateral MOS capacitor and the backside contact to the n-type substrate were kept at the same potential, as indicated in Fig. 1.

Results and Discussion

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To determine the series resistance , the frequency-dependent capacitance and conductance were measured on two neighboring MOS capacitors on a single wafer, one with and one without current-spreading layer with an AC-amplitude of 100 mV . From fitting equation 2 b to , the actual conductance was found to be below at 0 V DC-bias in both samples (Fig. 2a). The series resistance is then determined by applying a non-linear least square optimizing function for equation 2b to the experimental data, as shown in Fig. 2b. The capacitance at 0 V DC-bias is about for both samples.

Fig. 2 a) Conductance-frequency dependence and b) capacitance-frequency dependence at 0 V DC-bias for samples with (blue empty circles) and without (red dots) current-spreading layer. Dots denote the experimental data, lines correspond to the numerical fit. The legends include the fitted conductance and series resistance values, respectively.

Fig. 2. a) Conductance-frequency dependence and b) capacitance-frequency dependence at 0 V DC-bias for samples with (blue empty circles) and without (red dots) current-spreading layer. Dots denote the experimental data, lines correspond to the numerical fit. The legends include the fitted conductance and series resistance values, respectively.

We find from Fig. 2b that introducing a current-spreading layer significantly reduces the series resistance from about to about . Moreover, the experimental data cannot be adequately described for the sample without current-spreading layer in the whole frequency range within the parallel equivalent circuit model with a series resistor. We attribute the discrepancies to the influence of parasitic components on , such as serial capacitances or inductances. Therefore, the data taken into account for fitting were limited to 10 kHz for the latter sample.

To conclusively relate the capacitance's frequency dependence to the series resistance, we have investigated its temperature dependence for the sample with a current-spreading layer (Fig. 3a). We found that decreases with increasing temperature, characterized by a slope of 128 meV in an Arrhenius plot evaluation (Fig. 3b). This corresponds well to the reported ionization energy of Al for a concentration of about [12] and is consistent with a series resistance that is predominantly determined by the current-spreading layer.

Fig. 3 a) Capacitance-frequency dependence at 0 V DC-bias for the sample with a current-spreading layer measured at different temperatures. b) Arrhenius representation of the series resistance determined from fitting the data.

Fig. 3. a) Capacitance-frequency dependence at 0 V DC-bias for the sample with a current-spreading layer measured at different temperatures. b) Arrhenius representation of the series resistance determined from fitting the data.

With the values found from fitting the experimental data at 0 V DC-bias shown in Fig. 2b, the condition at a typical AC probe frequency of 100 kHz is only fulfilled for the sample with a current-spreading layer ( ). For the sample without a current-spreading layer, the probe frequency had to be reduced to 1 kHz . For both samples, capacitance and series resistance were evaluated from -40 V accumulation bias towards 40 V depletion bias (Fig. 4a).

Fig. 4 a) The data for -40 V accumulation towards 40 V depletion bias at 100 kHz and 1 kHz for the sample with and without a current-spreading layer, respectively. b) The series resistance as a function of applied voltage determined from data.

Fig. 4. a) The data for -40 V accumulation towards 40 V depletion bias at 100 kHz and 1 kHz for the sample with and without a current-spreading layer, respectively. b) The series resistance as a function of applied voltage determined from data.

In both samples, the capacitance decreases with voltage as the SCR is expanding. However, for the sample without a current-spreading layer, the measured capacitance drops below the capacitance value of the sample including a current-spreading layer for voltages exceeding 5 V .

By determining the series resistance from measuring it is revealed that diverges with increasing voltage in the sample without a current-spreading layer, whereas it increases only slightly for the sample including a current-spreading layer (Fig. 4b). We attribute the drastic increase in series resistance in the sample without a current-spreading layer to a pinch-off in the conductive channel between the SCRs of the p -well and p - n -junction. This is supported by the estimated width of the p well's SCR of about 380 nm at 40 V depletion bias, which would extend throughout the whole profile in case that no current-spreading layer is present.

The C-V data were used to determine the net dopant concentration via the differential-capacitance method [5]. For the sample including a current-spreading layer, the detected net dopant concentration is about at lower bias voltages, showing a slight increase of the concentration with depth (Fig. 5). This increase in concentration is supported by SIMS measurements and can be attributed to the tail region of the implanted current-spreading layer. Overall, a stable profile can be obtained owing to the high AC probe frequency of 100 kHz .

In contrast, when measuring the sample without a current-spreading layer, the resulting profile is noisy due to the lower probe frequency of 1 kHz , which could be overcome by increasing the measurement time. However, the dopant concentration is significantly underestimated above 5 V depletion bias as a result of the pinch-off in the conductive channel between the SCRs of the p-well and p-n-junction (Fig. 5).

Fig. 5 SIMS profiles (open symbols) compared to profiles derived from the differential-capacitance method (full symbols) for the samples with and without current-spreading layer.

Fig. 5. SIMS profiles (open symbols) compared to profiles derived from the differential-capacitance method (full symbols) for the samples with and without current-spreading layer.

The dopant concentration derived from SIMS measurements agrees well with the net dopant concentration of the sample with a current-spreading layer, which implies full dopant activation for a dopant concentration of after annealing at for 30 minutes. These results are in good agreement with previously reported activation degrees derived from mercury probe measurements [8]. However, recent Hall-measurements of Al-implanted samples in a comparable concentration range ( ) suggest a compensation ratio of about [13], which is not apparent in our data. Hall measurements of the sample without a current-spreading layer are pending to investigate this dissent.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.38.pdf

In conclusion, we have demonstrated that the activation of low-concentration Al implanted p -wells in n-type 4H-SiC can be determined on lateral MOS capacitors with reduced series resistance by introducing a buried current-spreading layer. The experimental data on the capacitance-frequency dependence agree well with the parallel equivalent circuit model.

The temperature dependence of for the sample with a current-spreading layer follows an Arrhenius law with a slope of about the ionization energy of , which is consistent with a series resistance determined predominantly by the current-spreading layer.

Depending on the series resistance, the AC probe frequency needs to be adjusted following the condition to accurately measure the capacitance voltage characteristics. If the condition is not met due to a high series resistance, the dopant concentration derived from differential capacitance measurements can be severely underestimated. Although introducing a current-spreading layer alters the underlying dopant profile, it could in principle be implanted deeper below the profile to be investigated.

Finally, we report that aluminum with a concentration of implanted at reaches full activation after annealing at for 30 minutes. To investigate the discrepancy to reported compensation ratios of about in this concentration regime, Hall-measurements are to be performed on the samples used in this work.

Since the capacitance-voltage method worked very well in the regime of low Al concentrations, we expect that the presented setup is also a promising method for investigating higher dopant concentrations and different doping species.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.38.pdf

We would like to thank Paweł Michałowski from Łukasiewicz-IMiF for performing the SIMS measurements.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.38.pdf

V. Šimonka, A. Hossinger, J. Weinbub and S. Selberherr, IEEE T. Electron Dev. 65 (2018) 674679.

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D.K. Schroder, Semiconductor Material and Device Characterization, third ed., John Wiley & Sons, New Jersey, 2006.

T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, John Wiley & Sons, Singapore, 2014.

T. Kimoto, O. Takemura, H. Matsunami, T. Nakata and M. Inoue, J. Electron. Mater. 27 (1998) 358-364.

M. Lazar, C. Raynaud, D. Planson, J.-P. Chante, M.-L. Locatelli, L. Ottaviani and P. Godignon, J. Appl. Phys. 94 (2003) 2992-2998.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 44-48

doi: 10.4028/p-7u1v90

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-14

Accepted:
2022-03-10

Online:
2022-05-31

Rolf Grieseler , Isabella Gallino , Natallia Duboiskaya , Joachim Döll , Deepshikha Shekhawat , Johannes Reiprich , Jorge A. Guerra , Marcus Hopfeld , Hauke L. Honig , Peter Schaaf and Jörg Pezoldt

Sección Física, Departamento de Ciencias, Pontificia Universidad Católica del Perú, Av. Universitaria 1801, 15088 Lima, Peru

FG Werkstoffe der Elektrotechnik, Institut für Werkstofftechnik and Institut für Mikro- und Nanotechnologien MacroNano TU Ilmenau, Gustav-Kirchhoff-Straße 5, 98693 Ilmenau, Germany

Lehrstuhl für Metallische Werkstoffe, Universität des Saarlandes, Campus C6.3, 66123; Germany

FG Nanotechnologie, Institute für Mikro- und Nanoelektronik and Institut für Mikro- und Nanotechnologien MacroNano , TU Ilmenau, Gustav-Kirchhoff-Straße 7, 98693 Ilmenau, Germany

Zentrum für Mikro- und Nanotechnologien, TU Ilmenau, Gustav-Kirchhoff-Straße 7, 98693 Ilmenau, Germany

rolf.grieseler@pucp.edu.pe, i.gallino@mx.uni-saarland.de, natallia.duboiskaya@tu-ilmenau.de, djoachim.doell@tu-ilmenau.de, edeepshikha.shekhawat@tu-ilmenau.de, johannes.reiprich@tu-ilmenau.de, guerra.jorgea@pucp.edu.pe, marcus.hopfeld@tu-ilmenau.de, ihauke.honig@tu-ilmenau.de, jpeter.schaaf@tu-ilmenau.de, kjoerg.pezoldt@tu-ilmenau.de*

Keywords: phase transition, reactive materials, reaction enthalpy, X-ray diffraction, differential scanning calorimetry

Abstract

An alternative low thermal budget silicon carbide syntheses route is presented. The method is based on self-propagating high-temperature synthesis of binary silicon-carbon-based reactive multilayers. With this technique, it is possible to obtain cubic polycrystalline silicon carbide at relatively low annealing temperatures by a solid state reaction. The reaction starts above . The transformation process proceeds in a four-step process. The reaction enthalpy was determined to be (-70 ± 4) .

Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

The original version of this paper is available on https://www.scientific.net/MSF.1062.44.pdf

Introduction

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A large variety of growth and formation techniques for cubic silicon carbide films have been proposed and evaluated, for example, sublimation growth [1], liquid phase epitaxy [2], chemical vapor deposition [3], molecular beam epitaxy (MBE) [4], magnetron sputtering [5], ion beam synthesis [6] and self-propagating high-temperature synthesis of powder mixtures [7-9]. For different applications, low cost and low thermal budget techniques are desirable, especially in the field of microelectromechanical systems and coating applications. Beside the thin film technologies an alternative route of forming SiC is the application of self-propagating reactions (SPR) via annealing of silicon and carbon powder mixtures as demonstrated in [7-9]. In these studies it has been shown that different SiC polytypes can be formed in dependence on the C source used for the SPR. For the application of SPR for thin film technologies, the powder mixture has to be transformed into a multilayer system consisting of Si-C bilayers stacked into a layer with a certain total thickness on a substrate of choice.

This goal can be achieved by combining the widely used magnetron sputtering techniques with the rapid thermal processing technology (RTP). In this contribution, the direct synthesis of SiC on Si or on substrates in a binary Si -C multilayer system deposited by magnetron sputtering and subsequently annealed using RTP is reported. The phase formation and structural evolution was studied in dependence on the annealing temperature. A special emphasis was given to the reaction enthalpy in the Si-C multilayer system.

Experimental

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The samples were prepared by magnetron sputtering using high purity silicon and carbon targets. Alternating layers of Si and C, with layer thickness of 50 nm each and a bilayer periodicity of 100 nm , are repeatedly deposited at room temperature onto the substrates until an overall film thickness of is achieved. Two types of substrates were used for the deposition: (1) boron doped p-type Si(100) with a specific resistance of and (2) the same substrate as in (1) but covered with a 90 nm thick layer grown by dry oxidation. The samples were annealed in a RTP furnace in pure Ar atmosphere and in a temperature range between 500 and with annealing times of 1 and 5 min . The heating-up rate was set to . The cooling-down rate was kept at . The morphology of the samples was studied with scanning electron microscopy (SEM). The structural investigations were performed by X-ray diffraction (XRD) and reflection Fourier transform infrared (FTIR) measurements. Differential scanning calorimetric (DSC) and differential thermal analysis (DTA) measurements were performed to investigate the phase formation and determine reaction enthalpy.

Results and Discussion

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Fig. 1 shows cross section and plane view SEM images of the as deposited reactive multilayer film deposited on bare silicon substrate. The dark grey layers in Fig. 1 (a) correspond to C whereas the light grey layers stem from Si in the multilayer stack. The interface between Si and C shows a wave like behaviour. This is reflected in the plane view image as given in Fig. 1 (b), where a grain like structure of the upper silicon film is evident. The measured average thickness of the Si and the C layers are 53 and 48 nm , respectively

Fig. 1. SEM images of the as deposited silicon-carbon reactive multilayer stack: (a) cross section of the near surface region, (b) plane view of the surface.

Fig. 1. SEM images of the as deposited silicon-carbon reactive multilayer stack: (a) cross section of the near surface region, (b) plane view of the surface.

Fig. 2 shows a measured characteristic set of grazing incidence XRD patterns of the RTP annealed samples in comparison to the as-deposited sample. The XRD patterns were measured at an incidence angle of . The patterns can be divided into two groups. The first group combines the spectra of the deposited sample and the samples annealed below . The second group consists of all samples annealed at and above. The characteristic feature of the first group is the appearance of three broad diffraction peaks suited approximately at and . The peak at the lowest angular position can be assigned to . Such peak location and peak form is typical for amorphous or nanocrystalline (nc) Si structures. Furthermore, reflections that could be assigned to crystalline C of any nature are completely absent, indicating that the C is initially amorphous. A similar spectra was obtained from triple layers in [10]. The peak at is located in the region of the and the -SiC(111) peaks stemming from nc-SiC crystallites formed at the interfaces of the Si-C layers. The peak at around can be interpreted as the alloying of Si with C during the deposition
of the Si-C bilayers. The Scherrer analysis revealed crystallite size values between 2.0 and 2.5 nm for Si and SiC, respectively. The second group of XRD spectra is characterized by a distinct crystallization of the Si layers in the multilayer stack evidenced by the reduction of the full width of the half maximum of the and peaks and the increase of their intensity. With increasing annealing temperature the very broad peak located at splits into two broad peaks.

Fig. 2 Compiled grazing incidence XRD patterns from as deposited and annealed Si/C bilayer stacks deposited on without . RTP annealing for 1 min. The spectra are shifted along the vertical direction.

Fig. 2. Compiled grazing incidence XRD patterns from as deposited and annealed Si/C bilayer stacks deposited on without . RTP annealing for 1 min. The spectra are shifted along the vertical direction.

They can be assigned to nc- SiC(100) and the nc- SiC(111). This can be caused either by a mixture of -SiC and -SiC, or -SiC and -SiC containing stacking faults with a hexagonal structure. The broad peak located at approximately with a symmetric peak form for the as deposited state and for the samples annealed at temperatures below transforms into a peak with an asymmetric peak form. The sharp part of the diffraction peak is located at the lower angular position and stems from . The broad shoulder at the higher angular position of this peak can be related to a combination of two overlapping peaks; the peak of the C alloyed Si and the -SiC(220) peak. The XRD pattern of the samples annealed at 5 min are qualitative similar. For both annealing times the temperature dependent structural evolution was independent on the substrate, indicating weak dependence of the reaction and structure formation on the substrate and an imprinting of the transformation process by layer deposition and annealing conditions.

Fig. 3 Cross section SEM images of the silicon-carbon reactive multilayer stack RTP annealed at and for 5 min .

Fig. 3. Cross section SEM images of the silicon-carbon reactive multilayer stack RTP annealed at and for 5 min .

Fig. 3 shows cross section images of the Si-C reactive multilayer stack annealed at (Fig. 3 (a)) and (Fig. 3 (b)) for 5 min. The measured average Si and C layer thicknesses for the sample were 48 and 45 nm , respectively. The reduced layer thicknesses stem from the compaction of the sputter deposited material. The contrast and the morphology of the interfaces in Fig. 3 (a) is very similar to the non-annealed state as shown in Fig. 1 (a) indicative for a missing or very weak SiC formation. Conducted FTIR reflection studies have not shown the evidence of a SiC phonon vibration frequencies. In case of annealing at , the morphology of the layers is changed. The Si layers are enlarging up to 80 to 90 nm at the expense of the dark grey carbon layers. In the centre of the Si layers, the contrast remains which indicates a non-consumed Si. The contrast of the thickened part of the Si layer is slightly different indicating that SiC has been formed. At different locations, a coalescence of the layers with the Si contrast appears. Nevertheless, some dark grey areas are remaining. Therefore, the C layer is not fully transformed. The morphology change points out that the SiC formation occurs mainly in the C layer by Si diffusion into C rather than by C diffusion into Si. Infrared measurements revealed a reflection peak at which can be assigned to the -SiC TO vibration frequency. This phonon mode position is characteristic for compressive strained SiC. A second weaker peak was found at characteristic for a alloy formation [11]. The Si grain size increases up to 10 nm for the highest annealing temperature. For SiC up to 6 nm was obtained.

Fig. 4 Combined heat flow thermogram measured with DSC and DTA of the Si-C multilayer annealed with a heating rate of .

Fig. 4. Combined heat flow thermogram measured with DSC and DTA of the Si-C multilayer annealed with a heating rate of .

Fig. 4 depicts the combined thermal analysis. The broad DSC peak between and shows a shoulder peak at around and a maximum between 520 and . This peak might be attributed to the gradual crystallization process of the deposited Si layers and C layers. The crystallisation process causes densification of the Si and C layers evidenced by the SEM investigations shown in Figs. 1 and 3. The second process contributing to this structure is the Si and C interdiffusion at Si-C interface regions in the multilayer supported by the shift of the Si(311) XRD peak for annealing temperatures below (see Fig. 2). The subsequent decomposition of the alloy leads to nucleation of SiC at the interface. The nucleation of SiC by reaction of Si with elemental C occurs even below [12]. The two exothermic peaks at and are related to intense SiC phase formation and growth. The double peak structure might stem from two different growth mechanisms. At lower temperatures columnar growth occurs, whereas at higher temperature three dimensional growth dominates as observed for MBE growth [4]. A schematic model of the transformation process can be found in [10]. The determined total reaction enthalpy was in agreement with literature values on powder being in the range of -69 to [8, 9].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.44.pdf

The imprinted transformation process in Si-C multilayer stacks is a multistep process and consist of four steps: (1) layer densification, (2) Si and C interdiffusion, (3) SiC nucleation and (4) SiC growth with temperature dependent growth modes. The SiC growth starts between 600 and and results in a compressively stressed polycrystalline - and -SiC. The reaction enthalpy was determined to be .

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.44.pdf

The authors are grateful for the financial support of this study by the German Science Foundation under contracts PE 624/16-1, SCHA 632/29-1, SCHA 632/30-1and GA 1721/3-1.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.44.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 49-53

doi: 10.4028/p-f26rb5

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-22

Accepted:
2022-03-07

Online:
2022-05-31

Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

The original version of this paper is available on https://www.scientific.net/MSF.1062.49.pdf

E. Kodolitsch , V. Sodan , M. Krieger , N. Tsavdaris

Lehrstuhl für Angewandte Physik, Department Physik, Friedrich-Alexander-Universität Erlangen-Nürnberg, Staudtstraße 7, 91058 Erlangen, Germany

Infineon Technologies Austria AG, Siemensstraße 2, 9500 Villach, Austria

Elisabeth.kodolitsch@infineon.com, Vice.Sodan@infineon.com, Michael.krieger@fau.de, Nikolaos.Tsavdaris@infineon.com

Abstract

In this work we report on the impact of various crystalline defects present in epitaxial layers on the electrical blocking characteristics of SiC power devices. Dedicated test structures were fabricated and electrically characterized in reverse bias mode. SiC substrate and epitaxial crystal defects, as well defects due to front-end processing were detected and classified using commercial inspection tools. Devices with a single defect-type were studied which leads to a direct correlation of the leakage current spot position within the device and the obtained blocking characteristics. This gives a better understanding of each crystal defect impact on device's performance which leads to an improvement in the reliability and cost reduction of SiC power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.49.pdf

In the recent years, silicon carbide ( SiC ) technology started showing a continuous raise in market share for high power electronic applications, as the SiC devices display a higher performance, efficiency and reliability. However, despite a rapid development in SiC bulk material, crystal defects are still present in both SiC substrates and epitaxial layers leading to a reduction of the overall yield. In order to ensure a device performance close to the theoretical limits, it is essential to have a better understanding of the impact of such crystal defects on SiC device characteristics. Several studies have already reported the effect of surface and crystalline defects such as carrots, micropipes and triangle epitaxial defects on reverse device characteristics [1-7]. These reports focus either on high volume statistics analysis or specific case studies. However, the presence of multiple type of defects per device, their density and location in both active and passive areas of the devices, as well as the variety of devices and specifications reported, makes it difficult to draw clear conclusions over the kill rate of each crystal defect and their exact role in the failing mechanism.

In this contribution, we focus on analyzing the influence of crystalline defects on the reverse characteristics that can lead to a reduced blocking capability of SiC power devices. Hence, for the study devices that contain only one type of crystal defect per device were considered. Photon emission microscopy (PEM) observations combined with the recorded reverse characteristics, allow a direct correlation between the screened epitaxial defects and the tested devices.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.49.pdf

N -type epitaxial layers were grown on off-axis towards [11-20] direction 4H-SiC substrates. Epitaxial defects were localized and classified algorithmically on a commercially available inspection tool, using an optical microscope along with a photoluminescence (PL) channel that is operating with a 660 nm long pass filter. Dedicated SiC test structures containing an active area ( junction) and an edge termination were fabricated and related voltage blocking characteristics were studied. Devices with a single defect type were selected and clustered into two distinctive groups: devices which show intrinsic behavior and devices which show increased leakage currents (exceeding the
range at total electric field over the epi layer up to ). This classification enables the study of both scenarios for devices containing the same defect type. Backside PEM analysis was performed in order to localize the exact position of leakage current spots within the devices. PEM is used to detect photonic radiation from a defective site within the devices due to excessive heat generation. The emission is thereby detected with highly sensitive cameras and gives information on potential failure positions.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.49.pdf

To analyze and understand the behavior of each defect type on the blocking characteristics, we looked towards devices with a specific one-type defect per device. Fig. 1 shows the optical microscopy and photoluminescence images of the six most common killer defects under investigation: triangular defects with a inclusion, Frank-type defects (includes a stacking fault in the basal plane and also in the prismatic plane), micropipes, nanoscale pits, 5 (a-b) Shockley type stacking faults (SSF), and 6 (a-b) carrots type defects.

Figure 1. Optical microscopy (a) and photoluminescence images (b) of defect-types: triangular defects (1), Frank-type defect (2), micropipes (3), nano-scale pits (4), stacking faults (5) and carrots (6)

Figure 1. Figure 1. Optical microscopy (a) and photoluminescence images (b) of defect-types: triangular defects (1), Frank-type defect (2), micropipes (3), nano-scale pits (4), stacking faults (5) and carrots (6)

While most of the defects mentioned above showing characteristic surface morphology features, only SSFs do not show any surface feature and are only detectable due to their distinctive PL signal. The reverse characteristics of devices containing only one single defect type were recorded and compared to a reference (defect-free) device showing intrinsic behavior. The measured reverse leakage current as a function of the electrical field is shown in Fig. 2.

Figure 2. Reverse leakage current characteristics vs. electrical field of SiC devices with one-type defect per device and without as reference (see black curve).

Figure 2. Figure 2. Reverse leakage current characteristics vs. electrical field of SiC devices with one-type defect per device and without as reference (see black curve).

Devices with triangular defects (see Fig. 1 (1a-b)) results to one order of magnitude higher leakage current compared to the reference device and show an ohmic behavior by already applying very low voltages (case of only one device is shown in Fig.2). PEM emission spots were detected directly on the triangular defect position for all studied devices (Fig.3). Moreover, the leakage emission spots seem to be independent of the defect position within the device, such as, the active p-n junction area and/or the edge termination region. It has been predicted theoretically that the bandgap at a local polytype change is reduced, thus leading to an increase of the leakage current [8].

Similar blocking characteristics as the one described above were identified on devices with micropipe-type defects originated from the substrate. However, from the PEM analysis, it was found that micropipes only lead to increased leakage current if they are located in the active p-n junction area. In of the tested devices the micropipe defect was located at the edge termination region, which did not result to an increased leakage current. Micropipes were described to act as direct leakage current path through the device, also on earlier studies [9].

On the other hand, devices that contain Frank-type stacking faults (FSFs) and carrots defects showed high device- to- device variations. Accordingly, some devices display no reduction in the blocking capabilities, while other devices showed a significant variation of the leakage currents ranging from few nanoampere to several microampere . PEM analysis reveals that emission spots were along the defects' surface feature (Fig. 3 (b-c)). The emission spots on these devices could only be detected when the defect was situated in the active junction area.

Figure 3. Photon emission microscopy (PEM) spots detected on the devices with a defect-type as: triangular defect (a), a Frank-type defect (b) and a carrot (c).

Figure 3. Figure 3. Photon emission microscopy (PEM) spots detected on the devices with a defect-type as: triangular defect (a), a Frank-type defect (b) and a carrot (c).

In order to have a correct overview of the defect contribution (i.e. defect surface or volume impact) to the obtained blocking characteristics, chemical mechanical polishing (CMP) was carried out on the grown layer after epitaxy process.

The surface feature of FSFs and carrot defects can vary both in shape and depth and is known to be the indication of an underlying prismatic stacking fault [10, 11]. The CMP resulted in a smoother surface feature of the defects as displayed in Fig. 4 (Ia and IIa). Subsequently, device processing and testing was implemented and PEM analysis was carried out on one device that shows an increased leakage current and contains a carrot defect (Fig. 4 III). The position of the emission spot is located at the area of the prismatic SF, similar to the devices without the CMP process. Thus, the defect surface feature does not contribute in the reduction of the blocking capability but instead it is the prismatic stacking fault within the epitaxial layer volume (Fig. 4 IV).

Devices containing Shockley type stacking faults (Fig.1 (5a-b)) showed reverse characteristics comparable with the ones obtained on the reference device (see Fig.2). A correlation of the defect position with the emission spots observed by PEM was only found in two out of twelve devices, at electric fields above implicating no negative affect on the blocking characteristics, neither if located in the active junction area of the device nor in the termination region.

While for all above-mentioned defect types per device a correlation, in some cases more pronounced, could be found, no clear correlation was found for single nano-scale pits type defects. These defects are approximately 200 nm in diameter and associated to substrate threading dislocations. It was shown in literature that the topology of these defects type can influence leakage
current and breakdown voltage in SiC p-n and Schottky diodes [12, 13]. Based on the results displayed in Fig. 2, no increase of the reverse characteristics, neither leakage current emission spots on the defect position could be observed.

Figure 4. Optical microscope (a) and the PL channel (b) images of devices with carrot-type defects prior (I) and after chemical mechanical polishing CMP (II). PEM spots were observed on the position of the prismatic SF (III) leading to an increased leakage current in comparison to a reference device (defect free) (IV).

Figure 4. Figure 4. Optical microscope (a) and the PL channel (b) images of devices with carrot-type defects prior (I) and after chemical mechanical polishing CMP (II). PEM spots were observed on the position of the prismatic SF (III) leading to an increased leakage current in comparison to a reference device (defect free) (IV).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.49.pdf

In this work, a direct correlation between various crystal defect types, their location and impact on the reverse leakage current of SiC devices was performed. Devices with a single defect were selected for this study and PEM analysis was carried out, to verify the position of the defect and the leakage current spots. Devices containing a triangular defect with a 3C-SiC inclusion or a micropipe showed leakage current with a clear ohmic behavior at a very low electric field. For devices containing Franktype SF and carrot defects, we observed high device-to-device variations of the blocking capabilities. Leakage current spots on those devices were located at the position of the prismatic SF of the defect. This is independent of the surface feature of the defects as demonstrated for wafers with CMP treated surface. No significant correlation was found for devices that contain a Shockley type stacking fault or a nano-scale pit. The evaluation of the impact of various defects on the leakage current fails is essential towards the improvement of reliability and cost reduction of SiC power devices.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.49.pdf

T. Kimoto et al., Prog. Cryst. Growth Charact. Mater. 62, (2016), 329-351

J. Zhao et al., Nanotechnol. Precis. Eng. 3, (2020), 229

R. Konishi et al., Japanese J. Appl. Phys. 52 (2013)

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T. Katsuno and Y. Watanabe et al., Japanese J. Appl. Phys. 50 (2011)

E. Van Brunt et al., Materials Science Forum 924, (2018), 137-142

H. Das et al., ECS Transactions 80, (2017), 239-243

U. Lindefelt et al., in Silicon Carbide- Recent Major Advances (eds W. J. Choyke, H. Matsunami and G. Pensl), Springer, (2004), pp. 89

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 54-58

doi: 10.4028/p-3iz201

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-03-01

Accepted:
2022-03-01

Online:
2022-05-31

Advances in 200 mm 4H SiC Wafer Development and Production

The original version of this paper is available on https://www.scientific.net/MSF.1062.54.pdf

Ian Manning , Kevin Moeggenborg , Andrey Soukhojak , Jon Searson , Matthew Gave , Gil Chung and Edward Sanchez

SK Siltron css, 530011 Mile Road, Auburn, MI 48611 U.S.A.

kevin.moeggenborg@sksiltron.com,

andrey.soukhojak@sksiltron.com, djonathan.searson@sksiltron.com,

Keywords: 200 mm , physical vapor transport, PVT, bulk crystal growth, 4 H , defects, x-ray topography, resistivity

Abstract

H SiC wafers were produced from bulk crystals grown using a physical vapor transport (PVT) method. The configuration of the growth cell was modified to both allow for the growth of larger crystals with respect to the standard 150 mm process, and to induce a thermal environment necessary to increase the mass deposition rate. A increase in deposition rate was achieved relative to the standard process. The resulting wafers exhibited resistivity uniformity comparable to commercial 150 mm product. Optical and x-ray techniques were used to evaluate wafer quality, and revealed surface and bulk crystal defect densities acceptable for epilayer growth.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.54.pdf

The recent surge in the electric vehicle market, driven in part by ramped exhaust regulations [1], continues to increase demand for power modules capable of high-temperature operation. This in turn has applied pressure on device manufacturers to improve throughput, and to seek ways of reducing production costs. One proven cost reduction method is to expand the surface area of the 4 H SiC wafers typically used as device substrates. [2] Building on prior development of 4 H SiC bulk crystal growth and processing methods to increase wafer diameter, [3] SK siltron css has committed to developing the next tier of power electronics substrates.

As with the effort to expand wafer diameter from 100 mm to 150 mm , the key challenge to further expanding to 200 mm is to increase the size of the bulk crystals while maintaining both throughput and crystal quality. Changes to process pressure and thermal conditions have been predicted to promote polytype switching, [4] and can lead to the generation of dislocations that are detrimental to device performance. [5] This study investigated modifications to the growth cell to both accommodate larger crystals and increase mass deposition rate, with attention to analyzing defect formation.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.54.pdf

A PVT method was used to grow 4H n-type SiC crystals, which were processed into wafers using grinding, slicing and polishing techniques common to the industry. The internal volume of the growth cell was modified to accommodate crystal sizes larger than those used to produce 150 mm wafers, while the mass transport rate was controlled by adjusting the thermal environment. Wafer resistivity was measured using a contact eddy current method. Surface and internal defects were imaged using a photoluminescence imaging technique (SICA 88). Macroscopic defects were assessed using fullwafer images obtained from (11 ) x-ray topograph reflections (Rigaku XRTMicron). Basal plane dislocation densities were qualitatively assessed using high resolution ( ) reflections.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.54.pdf

A comparison between the mean mass deposition rates recorded for the standard 150 mm and 200 mm processes is shown in Fig. 1. To achieve the necessary mass transport, the thermal driving force characteristic of PVT was increased via adjustments to the growth package configuration. A increase in mean mass deposition rate relative to the standard 150 mm process was obtained, enabling further enhancements to bulk crystal size.

Figure 1. Mean mass deposition rate of the 200 mm process, normalized to the value obtained for the standard 150 mm process (included for reference).

Figure 1. Figure 1. Mean mass deposition rate of the 200 mm process, normalized to the value obtained for the standard 150 mm process (included for reference).

Resistivity maps of typical 200 mm and 150 mm wafers selected from similar locations relative to the bulk crystal surface are shown in Fig. 2. Spatial uniformity of resistivity is important for repeatable electrical performance across device dies fabricated over the wafer surface. As shown, a high degree of uniformity has been demonstrated for 200 mm wafers in comparison with standard 150 mm material, indicating that local nitrogen uptake was not significantly affected by the larger surface area of the growth front or elevated deposition rate.

Figure 2. Representative resistivity maps of (a) a 200 mm wafer ( 12 mm edge exclusion); (b) a 150 mm wafer ( 15 mm edge exclusion).

Figure 2. Figure 2. Representative resistivity maps of (a) a 200 mm wafer ( 12 mm edge exclusion); (b) a 150 mm wafer ( 15 mm edge exclusion).

A wafer-level defect map obtained from SICA 88 photoluminescence imaging of a representative 200 mm wafer is shown in Fig. 3. Surface and bulk crystal defects, as well as surface damage such as scratches and pits, can reduce device die yield. It was therefore important to verify that the growth process modification required to expand bulk crystal diameters did not lead to significant defect generation. Fig 3. verifies that killer defects counts remained acceptable for epilayer growth, with the majority classified as "PL black" and "PL white" features. These features are hypothesized to be dislocation lines, decorated with dopant atoms that change the emission wavelength relative to the bulk crystal, and have no expected impact on performance. The micropipe density measured for the wafer shown in Fig. 3 was .

Figure 3. Defect map (left) of a representative 200 mm wafer obtained from SICA88. Defect counts with corresponding classifications are included (right).

Figure 3. Figure 3. Defect map (left) of a representative 200 mm wafer obtained from SICA88. Defect counts with corresponding classifications are included (right).

Full-wafer reflection scans of typical 200 mm and 150 mm wafers are compared in Fig. 4 (a) and (b). As a complement to PL characterization, XRT was performed to detect the presence of grain boundaries, micropipes and stacking faults that may have been introduced by the accelerated bulk crystal growth rate. It was found that the majority of the wafer area remained free of these defects, with grain boundaries observed near the periphery. Low micropipe and stacking fault counts were also noted. High resolution XRT scans were also performed along radial
bands from center to edge in the direction, and the resulting images were compared with scans of 150 mm wafers selected from crystals of similar length. An example is shown in Fig. 4 (c) (200 mm wafer) and (d) (150 mm wafer) (contrast adjusted to highlight defects). The images indicate that the density of basal plane dislocations (resolved as curved line segments) of the 200 mm wafer is similar to that of the 150 mm wafer. The XRT technique is currently being refined such that dislocation densities can be accurately measured.

Figure 4. reflection x-ray topograph images of (a) a representative 200 mm wafer, and (b) a representative 150 mm wafer. high-resolution images taken along the radius are shown for a (c) 200 mm and (d) 150 mm wafer.

Figure 4. Figure 4. reflection x-ray topograph images of (a) a representative 200 mm wafer, and (b) a representative 150 mm wafer. high-resolution images taken along the radius are shown for a (c) 200 mm and (d) 150 mm wafer.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.54.pdf

A PVT bulk crystal growth method capable of producing epi-ready 200 mm wafers was developed. The mass deposition rate of the process was increased by over the standard 150 mm process to ensure that the cycle time remained unaffected by the increase in crystal size. The resulting wafers showed low doping variation, resulting in excellent resistivity uniformity. Photoluminescence imaging and XRT revealed low densities of microscopic and macroscopic defects. Dislocation densities were qualitatively compared using high resolution XRT scans. Additional studies are required to improve edge quality.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.54.pdf

M. Yamamoto, T. Kakisaka, and J. Imaoka, Technical trend of power electronics systems for automotive applications, Jpn. J. Appl. Phys. 59 (2020) SG0805.

A. Bhalla, Recent Developments Accelerating SiC Adoption, Mater. Sci. For. 924 (2015) 793798.

J. Quast, D. Hansen, M. Loboda, I. Manning, K. Moeggenborg, S. Mueller, C. Parfeniuk, E. Sanchez, and C. Whiteley, High Quality 150 mm 4H SiC Wafers for Power Device Production, Mater. Sci. For. 821-823 (2015) 56-59.

T. Shiramomo, B. Gao, F. Mercier, S. Nishizawa, S. Nakano, Y. Kangawa, and K. Kakimoto, Thermodynamical analysis of polytype stability during PVT growth of SiC using 2D nucleation theory, J. Crys. Growth 352 (2012) 177-180.

H. Wang, F. Wu, S. Byrappa, S. Sun, B. Raghothamachar, M. Dudley, E. Sanchez, D. Hansen, R. Drachev, S. Mueller, and M. Loboda, Basal plane dislocation multiplication via the Hopping FrankRead source mechanism in 4H-SiC, Appl. Phys. Lett. 100 (2012) 172105.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 59-63

doi: 10.4028/p-1ak21z

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-09

Accepted:
2022-03-10

Online:
2022-05-31

Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1062.59.pdf

Haitham Hrich , Matthieu Moret , Olivier Briot , Matthieu Paillet , Jean-Manuel Decams , Périne Landois , Sylvie Contreras

Laboratoire Charles Coulomb, UMR 5221, Univ Montpellier, CNRS, Montpellier, France

Annealsys, 139 rue des Walkyries, 34000 Montpellier, France

haitham.hrich@umontpellier.fr, matthieu.moret@umontpellier.fr, olivier.briot@umontpellier.fr, matthieu.paillet@umontpellier.fr, jmdecams@annealsys.com, perine.landois@umontpellier.fr, sylvie.contreras@umontpellier.fr

Abstract

Herein, we report an original adaptation of an XRD set-up in order to measure the miscut angle values in our 4H-SiC on axis substrates with a high precision of . This study also reveals a correlation between the formation of wide steps on and the relative orientation of the SiC crystalline planes versus the gas flow direction. These two results paves the way towards the reproducible growth of graphene over wide SiC steps.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.59.pdf

Step bunching is defined as the movement of atoms at high temperature leading to the formation of steps [1]. When graphene is grown by sublimation on the Silicon (Si) face of Silicon Carbide (SiC), step bunching takes place and continues until the buffer layer (BL) is fully formed [2]. The width and height of the SiC steps thus formed highly affect the properties of the graphene above [3].

During thermal annealing, around in our experimental conditions, will starts to undergo a surface reconstruction [4, 5]. At this stage, new steps with a certain shape, height and width begin to form. At higher temperature, around , the BL appears. The BL is the first carbon layer that is formed during the SiC sublimation on the Si face. It is covalently bonded (for about of its C atoms) to the Si atoms in the SiC underneath. At higher temperatures, the BL detaches from the SiC and is transformed into the first layer of graphene and, at the same time, another BL is formed underneath and so on. The complete formation of the BL hinders the surface atoms motion because of the higher energy needed for this process at this stage which would involve subsequent breaking the BL-Si bonds and re-bonding. This means that the tuning of the step's shape on the Si face of SiC can only be done before the full formation of the BL .

Yazdi et al. have demonstrated that each SiC polytype has its own surface energy which corresponds to the energy needed to remove a particular terrace. These authors argued that, in the case of , there are two different surface energies [2]. As a consequence, steps with different surface energies will have different erosion velocities during sublimation. Steps with the lowest energy will have a higher erosion velocity as compared to the steps with the highest energy. Faster steps will catch up the slower ones and step bunching will take place. This phenomenon will lead to the formation of new steps that are wider (up to ) and higher with a height above one nm [6]. This step bunching continues until the full formation of the BL which results in the stabilization of the surface [7]. This suggests that the step bunching in SiC can be fully controlled only by the choice of the polytype used and by the parameters of the growth process such as the temperature ramp, pressure, duration, temperature... However, this hypothesis alone cannot explain the formation of large steps in . Indeed, several experimental works have shown that the shape of steps resulting from step bunching is highly influenced by the initial miscut angle of the

SiC wafer [8]. Dimitrakopoulos et al., have shown that in the case of , the width of steps is inversely proportional to the miscut angle with respect to the crystallographic plane. And this statement has been even confirmed for small miscut values lower than .

Miscut Angle Measurement by XRD

The original version of this paper is available on https://www.scientific.net/MSF.1062.59.pdf

The miscut is related to the geometry of the as received wafers and cannot be controlled. According to supplier information, our are on axis with a miscut lower than . However, with such an uncertainty it is very difficult: (i) to compare our graphene growth results from one substrate to another when originating from different wafers, and (ii) to unravel the effect of each growth parameter on the SiC steps shape. An evaluation of the miscut angle with a higher precision is needed.

Here, we report an unusual method to determine the miscut angle on substrates which is based on a combined optical alignment and X-Ray Diffraction (XRD) rocking curve measurement. This technic is similar to the one used by Enslin et al. to determine the miscut angle on sapphire substrates [10]. The miscut angle of three SiC wafers have been determined using the method described below and the values obtained are very close. An example is presented in the following.

Fig. 1. (a) Scheme of the experimental setup to align the substrate's normal and the axis of the inplane rotation ( -axis) of the diffractometer, (b) XRD map of the , measured near the reflection, with n an integer number, indicating the miscut angle .

Fig. 1. (a) Scheme of the experimental setup to align the substrate's normal and the axis of the inplane rotation ( -axis) of the diffractometer, (b) XRD map of the , measured near the reflection, with n an integer number, indicating the miscut angle .

First, the optical alignment is made in order to make collinear the substrate's normal and the inplane rotation axis ( -axis) of the diffractometer. As shown in the Fig. 1 (a), this is realized by using a 2 mm diameter laser device pointing on the center of the goniometer. The laser is reflected by the SiC surface onto a screen placed about 11 m away from the sample. This large distance allows to be highly precise on the adjustment of the sample holder tilting and to achieve an error on the angles between and . Aligning the surface's normal with the -axis consists in minimizing the amplitude of the precession figure observed on the screen. Once this alignment done, a series of rocking curves ( -scan) on the ( 000 n ) plane ( n being an integer) is made by varying from to . If the crystalline planes are tilted relative to the substrate surface (due to the miscut angle), the sample rotation around the -axis results in a variation of the XRD peak position in the -direction. In Fig. 1 (b), the peak position is plotted as a function of the corresponding angle. The resulting curve is fitted using a sinus function which amplitude, , equals the miscut angle with respect to the SiC (0001) plane [10]. This miscut angle turned out to be lower than for our three SiC wafers. Thus, the results obtained in the same growth conditions for two samples originating from different wafers from this series can be used to address the synthesis reproducibility. Moreover, such a low miscut angle should be favorable to the growth of wide SiC steps [9].

Effect of the Crystalline Orientation vs Gas Flow Direction

The original version of this paper is available on https://www.scientific.net/MSF.1062.59.pdf

After an optimization of the growth conditions, such as the temperature ramp and the environment of the growth, a homogeneous distribution of well-aligned and wide ( ) steps has been achieved as illustrated by AFM imaging (Fig. 2 (a)). However, for two out of the eight samples prepared with the same growth conditions, wide steps have not been achieved and zigzag shaped steps are observed instead. The single difference between these two samples' sets was the orientation of the substrate on its holder after the growth. For the wide steps samples, an unintentional rotation of counter clock wise (ccw) has been observed while no rotation was observed for the ones without large steps. Besides rotation, samples unintentional translation is sometimes observed but without an effect on the width of the steps. This suggests that the orientation of the sample, i.e. of the crystalline planes, relative to the gas flow direction during the growth has an influence on the resulting steps' shape.

Fig. 2. (a) Topological AFM image on a sample surface that had a rotation of during the growth ( ); (b) and (c) Optical microscopy (OM) images of a sample grown with the plan close to perpendicular and close to parallel to the gas direction, respectively. For each OM image, the corresponding VESTA schematization is given [11].

Fig. 2. (a) Topological AFM image on a sample surface that had a rotation of during the growth ( ); (b) and (c) Optical microscopy (OM) images of a sample grown with the plan close to perpendicular and close to parallel to the gas direction, respectively. For each OM image, the corresponding VESTA schematization is given [11].

The AFM image correlated with the crystalline directions of our revealed that the steps are aligned parallel to the plane ( ) in agreement with the work of ref [12]. The authors of [12] have demonstrated the formation of ordered steps on consisting of two planes: (0001) and high-index . In order to minimize the surface energy during thermal annealing, unstable surfaces, which are tilted with respect to a stable surface, will tend to decompose into these thermodynamically stable surfaces, i.e. (0001) and [13]. It is however very speculative at this stage to compare our results to these studies because they have been obtained on with an off-cut with respect to the direction or , which parameter is still unknown in our case. Moreover, none of the studies cited above took into account the effect of the gas flow direction versus the SiC crystalline plane which could be critical as shown here.

In order to validate that our results are truly related to the direction of the gas flow, control experiments have been achieved in the very same growths experimental conditions. Before growth, samples were intentionally placed in a manner where the gas direction was close (i) to perpendicular and (ii) to parallel to the ( ) plane. The corresponding optical microscopy images obtained after growth are shown in Fig. 2 (b) and 2 (c), respectively. In the first case, step bunching with the formation of wide and well aligned steps parallel to the plane on the surface occurs (Fig. 2 (b)). While, in the second case, zigzag shaped steps are observed (Fig 2. (c)). This result confirms that the appearance of giant steps on the crystalline plane depends on the relative gas flow direction.

Together with the precise characterization of the miscut angle presented in the first part, taking into account the orientation of the sample during growth allowed us to improve the control and reproducibility of our graphene samples on wide steps. As a result, a homogeneous distribution of well-aligned steps using an mix gases system has been achieved for more than 25 growths. OM and AFM characterizations (not shown) revealed that steps of 8 to in average width are
obtained. Furthermore, Raman mapping (not shown) showed that a continuous graphene film (with up to being graphene monolayer) is covering these large steps. The number of graphene layers were estimated using the ratio of the integrated intensity of the G band of graphene on the integrated intensity of the G band of a highly oriented pyrolytic graphite used as reference [14].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.59.pdf

We have shown that an original adaptation of an XRD set-up allows to measure the very low miscut values of our SiC on axis substrates with a high precision of . This parameter is essential to enable the comparison of growths carried out on different substrates. In addition, we have demonstrated the critical influence of the relative orientation of the SiC crystallographic planes versus the gas flow direction for obtaining wide and well-defined SiC steps during the SiC surface preparation stage before graphene growth. These two results pave the way towards the enhanced reproducibility of graphene growth over large SiC steps.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.59.pdf

H. Matsunami, T. Kimoto, Step-controlled epitaxial growth of SiC: High quality homoepitaxy, Materials Science and Engineering: R: Reports 20 (1997) 125-166.

G.R. Yazdi, R. Vasiliauskas, T. Iakimov, A. Zakharov, M. Syväjärvi, R. Yakimova, Growth of large area monolayer graphene on and a comparison with other SiC polytypes, Carbon 57 (2013) 477-484.

Y. Shi, A.A. Zakharov, I.G. Ivanov, G.R. Yazdi, V. Jokubavicius, M. Syväjärvi, R. Yakimova, J. Sun, Elimination of step bunching in the growth of large-area monolayer and multilayer graphene on off-axis 3C SiC (111), Carbon 140 (2018) 533-542.

P. Landois, T. Wang, A. Nachawaty, M. Bayle, J.-M. Decams, W. Desrat, A.-A. Zahab, B. Jouault, M. Paillet, S. Contreras, Growth of low doped monolayer graphene on via sublimation at low argon pressure, Physical chemistry chemical physics PCCP 19 (2017) 1583315841.

T. Wang, J.-R. Huntzinger, M. Bayle, C. Roblin, J.-M. Decams, A.-A. Zahab, S. Contreras, M. Paillet, P. Landois, Buffer layers inhomogeneity and coupling with epitaxial graphene unravelled by Raman scattering and graphene peeling, Carbon 163 (2020) 224-233.

Y. Shi, A.A. Zakharov, I.G. Ivanov, G.R. Yazdi, V. Jokubavicius, M. Syväjärvi, R. Yakimova, J. Sun, Elimination of step bunching in the growth of large-area monolayer and multilayer graphene on off-axis 3C SiC (111), Carbon 140 (2018) 533-542.

M. Kruskopf, K. Pierz, D.M. Pakdehi, S. Wundrack, R. Stosch, A. Bakin, H.W. Schumacher, A morphology study on the epitaxial growth of graphene and its buffer layer, Thin Solid Films 659 (2018) 7-15.

R. Dagher, B. Jouault, M. Paillet, M. Bayle, L. Nguyen, M. Portail, M. Zielinski, T. Chassagne, Y. Cordier, A. Michon, CVD Growth of Graphene on SiC (0001): Influence of Substrate Offcut, MSF 897 (2017) 731-734.

C. Dimitrakopoulos, A. Grill, T.J. McArdle, Z. Liu, R. Wisnieff, D.A. Antoniadis, Effect of SiC wafer miscut angle on the morphology and Hall mobility of epitaxially grown graphene, Appl. Phys. Lett. 98 (2011) 222105.

J. Enslin, A. Knauer, A. Mogilatenko, F. Mehnke, M. Martens, C. Kuhn, T. Wernicke, M. Weyers, M. Kneissl, Determination of Sapphire Off-Cut and Its Influence on the Morphology and Local Defect Distribution in Epitaxially Laterally Overgrown AlN for Optically Pumped UVC Lasers, Phys. Status Solidi A 216 (2019) 1900682.

K. Momma, F. Izumi, VESTA 3 for three-dimensional visualization of crystal, volumetric and morphology data, J Appl Crystallogr 44 (2011) 1272-1276.

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Y. Ishida, S. Yoshida, Investigation of the giant step bunching induced by the etching of 4 H SiC in Ar-H 2 mix gases, Jpn. J. Appl. Phys. 55 (2016) 95501.

N. Camara, J.-R. Huntzinger, G. Rius, A. Tiberj, N. Mestres, F. Pérez-Murano, P. Godignon, J. Camassel, Anisotropic growth of long isolated graphene ribbons on the C face of graphite-capped 6H -SiC, Phys. Rev. B 80 (2009).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 64-68

doi: 10.4028/p-s5v3jb

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-03-16

Accepted:
2022-03-17

Online:
2022-05-31

Effect of N and AI Doping on 3C-SiC Stacking Faults

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

Cristiano Calabretta , Viviana Scuderi , Ruggero Anzalone , Annalisa Cannizzaro , Marco Mauceri , Danilo Crippa , Simona Boninelli and Francesco La Via

CNR-IMM, VIII Strada, 5, 95121 Catania, Italy

STMicroelectronics, Stradale Primosole 50, 95121

Catania, Italy

LPE, Strada XVI, Catania, Italy

LPE, via Falzarego 8 Baranzate (MI), Italy

cristiano.calabretta@imm.cnr.it, viviana.scuderi@imm.cnr.it, ruggero.anzalone@st.com, annalisa.cannizzaro@imm.cnr.it, marco.mauceri@lpe-epi.com, danilo.crippa@lpe-epi.com, simona.boninelli@imm.cnr.it, francesco.lavia@imm.cnr.it

Keywords: 3C-SiC; Stacking Faults; doping; AI; Ni; defect; KOH etching; SEM; μ-Raman.

Abstract

This study offers a comprehensive examination of the behavior of crystals grown on off-axis (100) Si substrates with different off-axis angles along and for N and Al doping, respectively. The investigation takes advantage of molten KOH etching to conduct an indepth investigation of the average density and size of the SFs inside the crystal for both n - and p type doped 3C-SiC epitaxial layers. Moreover, 3C-SiC grown on a off-cut substrate was revealed to have a greater concentration of SFs due to the absence of self-annihilation along the plane (-1-10). Considering two different doping ranges suitable for IGBTs and MOSFETs development, the impact of doping and off-angle on the crystal quality, concentration, and length distribution of SFs was then investigated in order to quantify the influence of N and Al incorporation on the structural and optical characteristics of the semiconductor. It turned out that under heavy nitrogen doping ( ), when the dopant concentration grew, the average length of the stacking faults (SFs) expanded while their density dropped.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

Due to its higher mobility and a lower electronic density of states at the junction compared to reveals itself as a remarkable SiC polytype. These properties, resulting from the higher symmetry due to lower phonon scattering and lower bandgap ( 2.5 eV ), make 3C-SiC ideal for applications in power electronics [1], since they provide numerous benefits in metal oxide semiconductor (MOS) devices and microelectromechanical systems (MEMS) in harsh environments [2]. 3C-SiC can be grown by heteroepitaxial growth on Si wafers. However, this type of CVD growth involves of the lattice parameter mismatch between SiC and Si as well as an difference in thermal expansion coefficient. Such mismatches contribute to the generation of SFs lying on the (111) planes as well as misfit dislocations at the interface with Si substrate [3-5]. Doping is known to influence both the crystalline and mechanical properties of semiconductors. It is therefore of interest to verify its action on 3C-SiC [6]. Both -Raman and SFs assessment through molten KOH etching were conducted on various doped samples, in order to evaluate the impact of N and Al incorporation on the structural and optical characteristics of the semiconductor. The concentrations examined in this study for Al and for are consistent with the doping levels required for many power devices on 3C-SiC.

Specifically, for vertical metal-oxide-semiconductor field-effect transistor (MOSFET) devices, the substrate concentration should be as high as in order to reduce the device state resistance. Instead, the p-collector of insulated gate bipolar transistors (IGBTs) is characterized by a
concentration of approximately [7]. Today, IGBT manufacturing is particularly costly due to the difficulty to grow 4 H -SiC p -doped wafers, whereas this issue could be avoided by relying on heteroepitaxial growths of . Consequently, in this work p and n doping were carried out with the above mentioned concentration required for the design of the IGBT and MOSFET. For the two types of doping, two alternative off-axis substrate orientations were used: and <100>. Using the two intrinsic growths as a benchmark, it was possible to state that, regardless of the type of doping, 3C-SiC growth on oriented Si substrate succeeds in efficiently close the (-1-11) SFs family, whereas the off-axis angle results in higher SFs generation and propagation.

Materials and Methods

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

3C-SiC was grown in a horizontal hot-wall CVD reactor, on (100) oriented Si substrates off-axis along the for N doped samples and off-axis along the for Al doped samples. Precursor gases were Tri-chloro-silane (TCS) and Ethylene ( ) with ( ) employed as carrier gas. A two-step growth process was applied with the carbonization plateau at followed by CVD growth step at . A group of 4-inch wafer was grown with 313, 800 and fluxes during growth, while another one with constant Trimethylaluminum (TMA) fluxes. To increase crystal quality, the growth was first performed at for 30', followed by another 30'growth at and then carrying on at until a 70 layer was reached. Si substrate was then melted at inside the reactor to reach a freestanding wafer. Two different intrinsic samples were also grown on and off-cut substrate directions with the above mentioned steps in order to cross check the contributions of both the off-cut direction and of the concentration of dopant incorporated in 3C-SiC on crystal quality. From Secondary Ion Mass Spectroscopy (SIMS) analysis the three TMA fluxes led respectively to Al concentration as high as and , while fluxes resulted in concentrations of . Micro-Raman spectroscopy was used to assess 3C-SiC crystal quality. SFs evaluation was carried out through molten KOH etching performed at for 3 ' and subsequent SEM analysis.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

Through in-plane -Raman analysis it was attested how the investigated Al concentration exhibits an increase in Transverse Optic (TO) mode FWHM of in the highest doped sample with respect to the intrinsic 3C-SiC relative value. The N incorporation, on the other hand, displays a different behavior, as shown in Fig. 1a.

High N doping induces progressive crystal quality improvement through flow rise in chamber, as demonstrated by the FWHM dropping of Raman TO mode to in doped sample. Selective KOH etching was employed to perform SFs density evaluation. Fig. 1b displays three SEM micrographs related to the intrinsic and doped sample grown on off-cut off-axis substrate and doped sample grown on off-cut off-axis substrate after molten KOH etching process. The presence of SFs is highlighted by the wet etching process due to the difference in etching speed established by the altered binding energy between the defect-free crystalline matrix and the faulted crystal. This facilitates the generation of grooves around the SFs, making them accessible to statistical investigation. As may be observed, the density of SFs is in accordance with the Raman trend depicted in Fig. 1a.

Fig. 2 shows a significant change in the concentration and medium size of SFs between the intrinsic and the highly doped sample. Al doped sample exhibit SFs concentration ranging from for to for the sample with doping, attaining a slight reduction only to for the highest Al doping level (Fig. 2a). In the case of N
doping, instead, SFs density shows a different trend; it is, in fact, evident that if for the intrinsic off axis sample the average SFs density is , by increasing N doping to and , such value is notably reduced by almost an order of magnitude to and and has been proven to be independent from N saturation threshold [8] in 3C-SiC crystalline matrix.

Figure 1. a) 3C-SiC TO mode FWHM for Al and N doped samples; b) SEM micrograph of intrinsic N and Al doped samples after molten KOH etching.

Figure 1. Figure 1. a) 3C-SiC TO mode FWHM for Al and N doped samples; b) SEM micrograph of intrinsic N and Al doped samples after molten KOH etching.

This result is consistent with ab initio Density Functional Theory (DFT) calculation, which establishes that nitrogen doping around a SF increases its formation energy [9] and, thus, suppresses the SF formation. The medium length values in N-type doping are larger than the value of the intrinsic off-axis with off-cut direction. In comparison with the Al doping, the lowered SFs concentration is susceptible to a less effective mechanism of mutual annihilation and contributes to SFs average size increase from to (Fig. 2b).

Figure 2. a) SFs density b) SFs mean length of P and Al doped epitaxial layers. The graphs report the data related to intrinsic samples under different and off-cuts.

Figure 2. Figure 2. a) SFs density b) SFs mean length of P and Al doped epitaxial layers. The graphs report the data related to intrinsic samples under different and off-cuts.

The <110> off-axis direction of Si substrates favors propagation up to the surfaces of the SFs lying along the plane (111), whereas the SF lying on (-1-11) opposite to the growth step are prohibited [10]. Indeed Fig. 2a exhibits how the orientation of the off-axis angle introduces a consistent variation in the concentration of SFs already between intrinsic heteroepitaxies. The
off-axis angle in n-type samples is in the direction, favoring the inhibition of SFs along the plane (-1-11). The off-axis angle for p-type samples is along the direction and does not avoid SFs propagation from (-1-11). As a result, the SFs lying along the (-1-11) are fully removed only in n-type sample off-cut direction. In conclusion the association of current doping systems alongside compliance substrates adoption, such as inverted Silicon pyramids [11] or buffer layer [12] could further implement growth strategies in order to reduce the concentration of SFs and leading to the development of efficient power devices.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

This research was funded by SiC Nano for PicoGeo project, European Union's Horizon 2020 research and innovation programme under grant agreement No. 863220.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

N and Al doped 3C-SiC heteroepitaxial layers, were grown on a substrate in a horizontal hot-wall CVD reactor. Samples were grown on Si (100) off-axis along and for N and Al doped samples with two doping ranges, respectively. In the case of N-type doping, it was discovered that, as the dopant concentration increases, the mean length of the SFs grows from to , but the density drops. Instead, when the doping concentration is increased in p-type doping, the mean length and density of the SFs stay almost unchanged. Both quantities (density and average length) are influenced by the cutting angle's orientation. In reality, the off-axis angle along the promotes the suppression of the SFs along the plane ( ), lowering the density of the SFs detected on surface and expanding their average length. Conversely, not all of the SFs along the plane (-1-11) were suppressed on off-cut. This increases the reciprocal annihilation process, which is able of decreasing the average lengths of the SFs on the surface.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.64.pdf

M. Willander, Silicon carbide and diamond for high temperature device applications. J. Mater. Sci. Mater. Electron. 2006, 17, 1-25.

R.G. Azeved, A SiC MEMS resonant strain sensor for harsh environment applications. IEEE Sens. J., 7, 2007, 568-576.

F. La Via et al. New approaches and understandings in the growth of cubic silicon carbide, Materials, 14(18), 2021, 5348.

M. Zimbone et al., Generation and Termination of Stacking Faults by Inverted Domain Boundaries in 3C-SiC, Crystal Growth and Design, 20(5), 2020, 3104-3111.

M. Zimbone et al. Extended defects in 3C-SiC: Stacking faults, threading partial dislocations, and inverted domain boundaries, Acta Materialia, 213, 2021, 116915.

V. Scuderi et al. Characterization of 4 H -and 6 H -like stacking faults in cross section of 3 C -SiC epitaxial layer by room-temperature -photoluminescence and -raman analysis, Materials, 13(8) 2020, 1837.

Li, R.; Huang, et al. carrier-storage-enhanced superjunction IGBT with n-Si and p-3C-SiC pillars. Electron. Lett., 55, 2019, 1353-1355.

, Y.Sharmaa,Vishal Shaha, et al., App.Surf.Science, 353, 958-963, (2015)

Y. Umeno, K. Yagi, and H. Nagasawa, Phys. Status Solidi B, 1-6, (2012).

C. Calabretta, et al. Effect of Nitrogen and Aluminum Doping on 3C-SiC Heteroepitaxial Layers Grown on Off-Axis Si (100), Materials, 14(16), 2021, 4400.

M. Zimbone et al. 3C-SiC growth on inverted silicon pyramids patterned substrate, Materials, 2019, 3407.

M. Zimbone, M. Zielinski, C. Bongiorno et al 3C-SiC growth on inverted silicon pyramids patterned substrate, Materials, 12(20), 2019, 3407.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 69-73

doi: 10.4028/p-54nqrc

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-03-16

Accepted:
2022-03-17

Online:
2022-05-31

Impact of N Doping on 3C-SiC Defects

The original version of this paper is available on https://www.scientific.net/MSF.1062.69.pdf

Cristiano Calabretta , Viviana Scuderi , Annalisa Cannizzaro , Ruggero Anzalone , Marco Mauceri , Danilo Crippa , Simona Boninelli , and Francesco La Via

CNR-IMM, VIII Strada, 5, 95121 Catania, Italy

STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy

LPE, Strada XVI, Catania, Italy

LPE, via Falzarego 8 Baranzate (MI), Italy

cristiano.calabretta@imm.cnr.it, viviana.scuderi@imm.cnr.it, annalisa.cannizzaro@imm.cnr.it, ruggero.anzalone@st.com, marco.mauceri@lpe-epi.com, danilo.crippa@lpe-epi.com, simona.boninelli@imm.cnr.it, francesco.lavia@imm.cnr.it

Keywords: 3C-SiC; Stacking Faults; Dislocations; Molten KOH; Defect reduction; nitrogen doping; SEM.

Abstract

This work studies the variation of the defects density of in situ doped 3C-SiC layers during heteroepitaxial Chemical Vapour Deposition (CVD). A review on the evolution of defects density as a function of 3C-SiC grown thickness, for different N doping concentrations is offered. The doping range spanned in the experiment suits the realization of power devices.

The outcome of this work provides an explanatory picture of the significant drop in stacking faults density by roughly an order of magnitude through the N doping at concentrations of the order of during the growth. Conversely, N doping shows to favor the development of dislocation-like defects within the crystalline matrix. However, in few , the crystal is able to display an effective dislocation closure mechanism, which rapidly recovers crystal quality.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.69.pdf

3C-SiC is a particularly attractive SiC polytype since it has higher mobility and a lower density of states at the interface than 4 H and . These characteristics, along with 2.5 eV bandgap, make 3C-SiC suitable for power electronic applications, due to several benefits in MOS devices such as a notable reduction for medium voltage applications working under 1200 V [1].

Current technology is largely based on Si heteroepitaxial growth which involves mismatch in the lattice parameter and different thermal expansion coefficient. As a consequence, several types of defects, such as dislocations and stacking faults (SFs) nucleate close to the interface, both during the high temperature deposition and the cooling down, driven by the misfit strain relaxation [2-3]. Such defects hinder 3C-SiC device realization and provide significant leakage sources that are incompatible with large-scale integration (VLSI) technology.

So far, compliant substrates have been involved in preventing stacking faults, usually found at the interface, from reaching the surface [4]. Up to now, studies have been focused on the trend of dopant incorporation as a function of the growth parameters and on the evidences of conductivity [5-6], however investigation on the effect induced by CVD doping on 3C-SiC crystal defects have been rare [7-8].

This work provides an innovative detailed examination of nitrogen ( N ) doping impact over crystal, following defect evolution along grown layers based on molten KOH etching applied on uniformly lapped samples at an angle of from sample backside.

Materials and Methods

The original version of this paper is available on https://www.scientific.net/MSF.1062.69.pdf

3C-SiC growth was performed in a horizontal hot-wall Chemical Vapour Deposition (CVD) reactor using (100) oriented off-axis with off-cut Si substrates. Precursor gases were Tri-chloro-silane (TCS) and Ethylene ( ) with ( ) as carrier gas. A two-step growth process was applied with the carbonization plateau at followed by CVD growth step at . One 4inches wafer was grown intrinsic while other growths were carried out with constant 314,800 and fluxes. To increase crystal quality, the process was first performed at a low growth rate of for 30', followed by another 30' growth at and then fast growth rate of was carried out until a layer was reached. Afterwards, Si substrate was melted at in the reactor to reach a free-standing wafer. Secondary Ion Mass Spectroscopy (SIMS) investigation led to N concentrations of . Molten KOH etching at for was performed on uniformly lapped sample at an angle of from sample backside in order to provide a comprehensive examination of crystal defects from the initial growth layers up to thicknesses of through SEM microscopy in-plane analysis.

Discussion

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Through the molten KOH etching process, SFs are visually highlighted and are revealed as lines that stand out from the non-defective crystal, while dislocations present inside the crystal are enhanced in the form of pits.

Particularly impressive SFs density variation is visually attested in Fig. 1, which exhibits two SEM images of intrinsic and doped sample, in Fig. 1a) and 1b), respectively, acquired at growth depth post molten KOH etching. The appearance of SFs in a single direction is driven by preferential etching following binding energy difference within Si-terminated and C -terminated ones .

In Figure 1a there is a noticeable presence of SFs and two examples are enclosed by red dashed lines. On the other hand, in Fig. 1b a reduced number of SFs are present, but with the appearance of etch pits. Two examples of etch pits which are usually linked to dislocations are indicated by yellow dashed circles.

Figure 1. SEM micrograph acquired at the growth thickness of of a) an intrinsic sample and of b) a sample doped at subjected to molten KOH etching.

Figure 1. Figure 1. SEM micrograph acquired at the growth thickness of of a) an intrinsic sample and of b) a sample doped at subjected to molten KOH etching.

Within Figures 2 a and b the results coming from decaying exponential fits arising from the measurements of the SFs and etch pits densities are represented. Figures 2a and b show, in particular, the confidence curves of the exponential fits extracted from the experimental densities data with respect to the grown 3C-SiC layer thickness, from interface to thickness. Fig 2a shows the intrinsic sample (grey band) following a constant SFs concentration trend, whose density range goes from at to at . This trend is followed by the SFs size evolution, which goes from an average value of at the interface to in length at growth (not shown). Conversely, the introduction of N into the chamber drives a remarkable SFs density decrease, from the first layers. Based on the observations of the lowest and highest doped samples, at the interface the SFs concentration are fairly comparable attesting on for the lower doped sample (red band in the graph) and of ( for higher doping (violet band in the graph). Indeed, in the first the density contribution from both crystals is highly influenced by the low growth rate involving lower SFs generation. The subsequent growth rate rising to responds to a slight increase in the SFs density during the low doped growth, while in the case of higher flow, an exponentialdecay trend involves SFs density to stabilize at already at . The comparison between these two apparently contrasting trends responds to the different dopant concentrations incorporated in the crystal.

From calculations made using Vienna Differential Functional Theory it is evident that N favors the increase of the formation energy of SFs. As a result, assuming that the dopant effect appears when it is inside or close to the SF [9] the significant decrease in SFs density is explained by increased N incorporation in the crystal matrix. Moreover, it is worth noting that when subjected to intermediate doping , the crystal matrix undergoes lower SFs generation in the first due to a longer exposure to low growth rates during CVD growth.

Figure 2. The confidence curves of the decaying exponential fits plotted by the density data of SFs a ) and etch pits b) as a function of the growth thickness.

Figure 2. Figure 2. The confidence curves of the decaying exponential fits plotted by the density data of SFs a ) and etch pits b) as a function of the growth thickness.

Nevertheless, it is evident that from growth higher SF closure mechanism prevails in the highest doping regime. It is worth noting, however, that if the misfit stress between and Si substrate is effectively contained by carbonization steps in intrinsic growth, rapid multiplication of dislocations and progressive increase in dislocations density with growing strain is testified in the doped samples from Figure 2b. In fact, the relaxation of the compressive stress accumulated consequently to the doping incorporation occurs through the generation and gliding of dislocations
whose density increases with the flow in CVD chamber. Etch pits density in the intrinsic sample is just over 100 etch pits , while in the most doped samples etch pits at are observed up to at growth thickness. It is interesting to note that the density falls below the value recorded in the intrinsic growth in the case of the sample with medium doping from depth. The identification and atomic structure of the dislocations revealed by the etch pits were exhaustively investigated in [10], as well as -PL cross-section maps of the band-to-band peak intensity located at 540 nm performed for the intrinsic and heavily doped samples along the entire grown thickness. The map of the doped sample showed how the band-to-band peak grows faster and more homogeneously in the most doped sample than in the intrinsic one, confirming the improved quality of the grown crystal through doping. As a result of the foregoing, it is possible to assert that 3 C -SiC crystal quality strongly benefits from suitable N doping, since the first grown layers and further strategies to shrink the dislocations density in the early stages of growth can include growth rates tuning and N supplied concentration as well as generation of physical opposite dislocations.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.69.pdf

This research was funded by SiC Nano for PicoGeo project, European Union's Horizon 2020 research and innovation programme under grant agreement No. 863220.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.69.pdf

This paper provides a comprehensive description of the N doping effect on epitaxial layers. It demonstrates that the crystal is highly sensitive to N doping concentration in the range of and significantly lowers the density of SFs by an order of magnitude.

The addition of N doping within the growth chamber increases the concentration of dislocation-like defects within the initial growth layers; nevertheless, the density of these defects is rapidly decreased during growth in the first microns. This trend is beneficial for breaking down dislocation concentrations, below the densities measured inside the intrinsic crystal, leading in light of what stated for SFs to highly pure 3C-SiC crystal.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.69.pdf

F. La Via et al. New approaches and understandings in the growth of cubic silicon carbide, Materials, 14(18), 2021, 5348.

M. Zimbone et al., Generation and Termination of Stacking Faults by Inverted Domain Boundaries in 3C-SiC, Crystal Growth and Design, 20(5), 2020, 3104-3111

M. Zimbone et al. Extended defects in 3C-SiC: Stacking faults, threading partial dislocations, and inverted domain boundaries, Acta Materialia, 213, 2021, 116915.

M. Zimbone et al. 3C-SiC growth on inverted silicon pyramids patterned substrate, Materials, 2019, 3407.

M. Zielinski et al. Nitrogen doping of 3C-SiC thin films grown by CVD in a resistively heated horizontal hot-wall reactor, Journal of Crystal Growth, 310,2008, 3174-3182.

H.K.E. Latha et al., Microstructure and electrical properties of nitrogen doped 3C-SiC thin films deposited using methyltrichlorosilane, Materials Science in Semiconductor Processing, 29,2015, 117-123.

V. Scuderi et al. Characterization of 4 H -and 6 H -like stacking faults in cross section of 3C-Sic epitaxial layer by room-temperature -photoluminescence and -raman analysis, Materials

C. Calabretta, et al. Effect of Nitrogen and Aluminum Doping on 3C-SiC Heteroepitaxial Layers Grown on Off-Axis Si (100), Materials, 14(16), 2021, 4400.

Y. Umeno, K. Yagi, and H. Nagasawa, Phys. Status Solidi B, 1-6, (2012).

C. Calabretta et al. Impact of nitrogen doping on the selective closure of Stacking Faults in 3C-SiC, Journal of Materials Science (submitted).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 74-78

doi: 10.4028/p-6ef373

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-15

Accepted:
2022-03-10

Online:
2022-05-31

Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding

The original version of this paper is available on https://www.scientific.net/MSF.1062.74.pdf

M. Kollmuss , M. Schoeler , R. Anzalone , M. Mauceri , F. La Via , P. Wellmann

Crystal Growth Lab, Materials Department 6 (i-meet), FAU Erlangen-Nürnberg, Martensstr. 7, D-91058 Erlangen, Germany

STMicroelectronics, stradale Primosole 50, 95121 CATANIA, Italy

LPE S.P.A., Sedicesima Strada, 95121, Catania, Italy

CNR-IMM, sezione di Catania, Stradale Primosole 50, I-95121 Catania, Italy

manuel.kollmuss@fau.de, michael.schoeler@fau.de, ruggero.anzalone@st.com, Marco.Mauceri@lpe-epi.com,

Keywords: 3C-SiC; Sublimation growth; large-area growth; bow reduction; stress reduction.

Abstract

One setback that hinders the breakthrough of cubic silicon carbide is the lack of suitable seeding material for sublimation growth methods such as PVT. We present the growth of large area cubic silicon carbide material, up to a diameter of 100 mm , with a sublimation growth process called close spaced PVT (CS-PVT). Freestanding 3C-SiC seeding layers were grown by a homoepitaxial CVD process. Subsequently CS-PVT was used to grow crystals up to a thickness of 1 mm . To prevent backside sublimation a carbon containing layer was applied as protection. Due to the presence of a wafer bow as well as a rough backside of the used seeds additional effort was necessary to apply the coating. After growth no visible curvature was present independent of the grown layer thickness and sample size. Raman spectroscopy was performed on the seeds and grown crystals, showing that the overall stress level of the material was reduced by CS-PVT.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.74.pdf

Large area growth of hexagonal polytypes of silicon carbide ( and ) up to diameters of 150 mm using physical vapor transport (PVT) can be considered mature. In fact, the first wafer production with a diameter of 200 mm has been implemented. Meanwhile the same cannot be said for the cubic polytype ( ). The growth of this polytype is mainly hindered by a lack of suitable seeding material as a starting point for sublimation growth processes. Nevertheless, progress was made in recent years regarding this problem. Schuh et al. [1] showed that thin 3C-SiC layers fabricated by heteroepitaxial chemical vapor deposition (CVD) on silicon can be used to prepare a seeding stack suitable for high temperature growth processes. Crystals with reasonable size and thickness could be grown using this method [2,3]. However, cracking of the thin 3C-SiC layers during seed preparation limited the achievable diameter. A promising new seeding material has become available due to ongoing research in the field of CVD growth of 3C-SiC. Anzalone et al. [4] described the production of freestanding 3C-SiC wafers grown by homoepitaxial CVD at elevated temperature. Using such seeding material for sublimation growth processes offers new possibilities for the growth of large area cubic silicon carbide. A suitable sublimation process for is the close space PVT (CS-PVT) which is also referred to as sublimation sandwich. In this work we present the growth of freestanding 3C-SiC crystals up to diameters of 100 mm on homoepitaxial grown 3C-SiC seeds using CS-PVT. Remaining problems as well as the possibilities of this approach are discussed. Additionally, the potential of the presented approach towards the growth of 150 mm 3C-SiC crystals will be presented.

Experimental

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CS-PVT growth was carried out in a state-of-the-art PVT reactor using a sandwich like hot zone to reach the required growth conditions for stable growth of cubic silicon carbide. A Tantalum foil acting as a carbon getter was placed underneath the source to maintain a silicon rich gas phase. The distance between the source and the seed was kept small (gap size 1 mm ) by a graphite spacer to achieve a high vertical temperature gradient. The high supersaturation suitable for the cubic polytype goes along with the temperature gradient and is also achieved by a fast heat up of the system ( ). Poly- or monocrystalline SiC wafers were used as source material while free-standing, (100) oriented 3C-SiC layers provided by LPE Epitaxial Technology Center in Catania were used as seeds. The seeds had a tilt of towards [110], a diameter of 150 mm and a thickness of 200-235 . A laser ablation process was used to remove the defect-rich edges of the seeds and to cut the seeds to a sample size of either 50 mm or 100 mm . To protect the backside of the seeds during sublimation growth a carbon containing coating was applied. As the used seeds contained a wafer bow the application of this backside coating was done manually and will be described later. CS-PVT growth was conducted at temperatures between 1970 and under vacuum conditions with vertical temperature gradients between 4 and resulting in growth rates between 90 and . After the sublimation growth the backside protection layer was removed by oxidation. The growth setup and the hot zone used is also described in [5,6]. For the optical characterization of the grown crystals an Epson perfection v800 flat-bed scanner with a maximum resolution of 6400 dpi was used. Raman measurements were conducted using a Horiba LabRAM HR Evolution confocal Raman microscope with a laser wavelength of 532 nm , a power of 3.19 mW power at an optical resolution of 50x and a grating of .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.74.pdf

Fig. 1: Left: High resolution scan of freestanding 3C-SiC crystal grown by CS-PVT with a diameter of and a thickness of . The flat is the result of layer breakage during seed preparation. The darker area stems from the rough backside of the seed used. Right: Photography of same crystal after optical polishing on front- and backside resulting in a specular appearance.

Fig. 1. Left: High resolution scan of freestanding 3C-SiC crystal grown by CS-PVT with a diameter of and a thickness of . The flat is the result of layer breakage during seed preparation. The darker area stems from the rough backside of the seed used. Right: Photography of same crystal after optical polishing on front- and backside resulting in a specular appearance.

Growth of freestanding large area material. Fig. 1 shows the results for the growth on a seed with a diameter of 100 mm . The resulting crystal had a diameter of 92 mm due to the used graphite spacer and had a thickness of . The crystal exhibits the yellow color typical for the cubic polytype of silicon carbide and has a smooth growth front. The polytype was also confirmed by Raman measurements, as no other peaks were observed besides those characteristic for . During the seed preparation cracking of the bowed seed occurred during the removal of the defect rich edges of the seed, leading to the visible flat. Laser ablation will not cut through the whole seed once the thickness reaches values higher approx. . Thus, a slight mechanical force has to be applied to
separate the seed edges which, together with the present bow and remaining stress in the seed, can result in cracking. The freestanding area of the layer is approximately . To our knowledge this marks the first time a freestanding 3C-SiC crystal with such size and thickness was grown. The bow of the used seed wafer vanished during the sublimation growth and will be discussed in the next section. Due to flattening it was also possible to do optical polishing of the crystal on the front as well as the backside resulting in a specular surface as it can be seen in Fig. 1 (right).

Fig. 2: High resolution scan of cracked, freestanding 100 mm 3C-SiC crystal grown by sublimation growth on a seeding stack. The manufacturing of the seeding stack is described in [2,5]. Multiple cracks can be seen in the crystal showing the limitation of the seed transfer used.

Fig. 2. High resolution scan of cracked, freestanding 100 mm 3C-SiC crystal grown by sublimation growth on a seeding stack. The manufacturing of the seeding stack is described in [2,5]. Multiple cracks can be seen in the crystal showing the limitation of the seed transfer used.

Another approach for the sublimation growth of 3C-SiC is mentioned in [2, 5]. Prior to the growth a seeding stack needs to be produced from a thin 3C-SiC layer grown on silicon by heteroepitaxial CVD. During this transfer process the silicon is etched away. However, the handling of the freestanding layers as well as the etching itself, comes with a high risk of layer cracking. The cracking probability will increase with increasing layer size and limits the scale up potential. An example for the sublimation growth on seeding stacks produced by this transfer can be seen in Fig 2. Compared to the crystal in Fig. 1 multiple cracks are clearly visible showing the limitations for large area growth. In contrast the approach used in this work showed a significant lower probability of seed cracking. Therefore, a reasonable potential for upscaling towards larger diameters can be associated. An improvement in the seed quality should reduce the chance of cracking. Laser ablation could become even redundant, if the defect density at the seed edges is further decreased. This would allow the growth of crystals with larger diameters using sublimation growth.

Reduction of wafer bow during CS-PVT. Fig. 3 shows a comparison between the freestanding seed and the resulting crystal after CS-PVT for a 50 mm growth run. The visible bow in the left-hand figure is typical for the used seeds. These layers still suffer from a bowing up to 4 mm for a 150 mm wafer. In this context, bow refers to the deviation between the seed or crystal center and a reference plane defined by the edges of the sample. The bow of the seed in Fig. 3 has a value of approx. 0.5 mm . During the sublimation growth this bow completely vanished, resulting in a flat crystal. This phenomenon was observed for all experiments carried out, regardless of the sample diameter and the grown layer thickness, which was between 0.5 and 1 mm . To further understand this effect a seed was heated up to the same temperature as during growth runs. Instead of vacuum an argon atmosphere at 800 mbar was applied to suppress sublimation of SiC in the growth cell thus, checking if the bow reduction can be induced by a heat treatment alone. As no reduction of the bow could be observed, the reduction mechanism must be induced by the material grown on top of the seed during CS-PVT.

Raman spectroscopy was used to evaluate the stress level in the samples before and after sublimation growth. The peak position of the transversal optical mode was used. For a stress-free crystal, the value of the peak should be at a Raman shift of [7]. Due to internal stress of the crystal lattice the position will shift to lower values or higher values for tensile or compressive stress, respectively. The measurements showed that the values for all samples were closer to the stress-free value after the sublimation growth. Therefore, not only a reduction of the sample bow but also a reduction of the overall stress inside the sample was achieved by CS-PVT. This is in good agreement
with the results of Schuh et al. [2]. They also observed a stress reduction during sublimation growth. Although, they used a different type of seeding material, it shows the potential of the sublimation growth processes for stress reduction in silicon carbide crystals. This is important as the influence of stress and its handling becomes more pivotal with increased crystal size.

Fig. 3: Left: Seed (upper) and crystal after the CS-PVT growth (lower) for a 50 mm sample. The clearly visible bow of the seeding layer completely vanished during the sublimation growth (bottom). Right: Peak position of the TO-Mode of Raman spectroscopy for seeding layers (blue) and associated crystals grown by CS-PVT. For all samples a reduction of the stress towards the stress-free value of could be observed (red dotted line).

Fig. 3. Left: Seed (upper) and crystal after the CS-PVT growth (lower) for a 50 mm sample. The clearly visible bow of the seeding layer completely vanished during the sublimation growth (bottom). Right: Peak position of the TO-Mode of Raman spectroscopy for seeding layers (blue) and associated crystals grown by CS-PVT. For all samples a reduction of the stress towards the stress-free value of could be observed (red dotted line).

Backside protection. Currently there are two main challenges regarding the backside protection of the seeding layers used: the bow and a rough backside. Besides the risk of seed breakage, bow also complicates the application of backside protection since processing methods like spin coating can't be used. Therefore, a more manual approach was used. First the backside of the seed was covered completely with a carbon containing liquid coating and afterwards the seed was placed vertically to allow the excess material to drain off. Subsequently, a high temperature annealing under vacuum conditions was performed to cure the coating. The rough backside of the seeds has its origin in the fabrication of the layers. The initial CVD growth step is done on silicon. Afterwards the silicon is removed by an in situ melting process inside the CVD reaction chamber [8]. During this step the backside of the grown 3C layer is damaged leading to surface roughening [9]. This roughness can hamper the adhesion of the backside protection layer during the sublimation growth. Therefore, the right choice of processing parameters plays a crucial role. Coatings that are too thick can delaminate during vapor phase growth processes whereas layers that are too thin can lead to insufficient protection. In both cases backside sublimation will occur, limiting the process window for sublimation growth.

Summary/Outlook

The original version of this paper is available on https://www.scientific.net/MSF.1062.74.pdf

We showed that homoepitaxial 3C-SiC layers can be successfully used for large area bulk growth of freestanding 3C-SiC crystals by CS-PVT. Crystals up to nearly 100 mm could be grown with thicknesses up to 1 mm . During the growth the remaining bow in the seeding layers vanish and, additionally, the stress level of the samples can be reduced. To protect the crystal from backside sublimation during the growth runs a carbon containing coating was applied. However, the bow of the seeds as well as the rough backside made additional efforts necessary regarding the coating process. Compared to seeding material used in other works for sublimation growth of cubic silicon carbide, this approach showed a higher overall scale up potential, bringing the goal of 150 mm cubic silicon carbide bulk crystals within reach.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.74.pdf

This work is funded by the European H2020 framework program for research and innovation under grant agreement number 720827 (CHALLENGE).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.74.pdf

P. Schuh, P. Vecera, A. Hirsch, et al. Physical vapor growth of double position boundary free, quasi-bulk on high quality on Si CVD templates. in Materials Science Forum (2016) 89-92.

P. Schuh, F. la Via, M. Mauceri, et al., Growth of Large-Area, Stress-Free, and Bulk-Like 3CSiC (100) Using 3C-SiC-on-Si in Vapor Phase Growth, Materials 12(13) (2019) 2179.

P.J. Wellmann, P. Schuh, M. Kollmuss, et al. Prospects of Bulk Growth of 3C-SiC Using Sublimation Growth. in Materials Science Forum (2020) 113-119.

R. Anzalone, M. Zimbone, C. Calabretta, et al., Temperature Investigation on 3C-SiC HomoEpitaxy on Four-Inch Wafers, Materials 12(20) (2019) 3293.

F. La Via, M. Zimbone, C. Bongiorno, et al., New Approaches and Understandings in the Growth of Cubic Silicon Carbide, Materials 14(18) (2021) 5348.

P. Wellmann, N. Ohtani and R. Rupp, Wide Bandgap Semiconductors for Power Electronics: Materials, Devices, Applications, Weinheim, John Wiley & Sons, 2021.

A. Severino, C. Bongiorno, N. Piluso, et al., High-quality 6 inch (111) 3C-SiC films grown on off-axis (111) Si substrates, TSF 518(6) (2010) 165-169.

R. Anzalone, N. Frazzeto and F. La Via, U.S. Patent US 2021/0062361 A1. (2021)

F. La Via, M. Mauceri, V. Scuderi, et al. 3C-SiC bulk growth: Effect of growth rate and doping on defects and stress. in Materials Science Forum (2020) 120-125.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 79-83

doi: 10.4028/p-gt22u6

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-18

Revised:
2022-02-15

Accepted:
2022-03-10

Online:
2022-05-31

In Situ Monitoring of Unintentionally Released Nitrogen Gas in the Initial PVT Silicon Carbide Growth Process Using Mass Spectrometry

The original version of this paper is available on https://www.scientific.net/MSF.1062.79.pdf

Jonas Ihle and Peter J. Wellmann

¹Crystal Growth Lab, Materials Department 6 (i-meet), FAU Erlangen-Nürnberg, Martensstr. 7, |D91058 Erlangen, Germany

ajonas.ihle@fau.de, bpeter.wellmann@fau.de

*corresponding author

Abstract

Different initial process steps during PVT crystal growth of SiC were monitored with a mass spectrometer. To measure the gas phase composition in the PVT growth machine during these steps the continuously pumped exhaust gas was analyzed by a quadrupole mass spectrometer (PrismaPro QMG 250). In order to reduce unintentionally doping of the crystal by contaminations in the growth setup the focus was on the release of nitrogen during the initial steps of the growth process. During the heat up of the growth setup in vacuum a substantial release of molecular nitrogen was observed at . Further, the influence of pump and purge-steps on the amount of nitrogen in the gas phase was examined. After performing a pump and purge step, the intensity of the measurable nitrogen-related signal ( ) was approximately of the initial value. In-situ monitoring of the gas phase during the initial steps of crystal growth proved to be a versatile tool for the development of a process minimizing unintentionally doping through released nitrogen.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.79.pdf

Controlled doping is an important issue for bulk growth of silicon carbide. Stable doping density over the whole bulk is desirable for n-type material, for high purity semi-insulating a low doping density is necessary [1,2]. Therefore, it is important to know the sources of unintentionally background doping. One source of background doping are impurities incorporated in material which are present in the reaction chamber (e.g. powder source, crucible and other carbon part) [3,4]. These materials could be examined previously and therefore are not the main issue of this study. Another source of background doping are parts in the PVT growth machine with high specific surfaces. A representative of this type is the graphite isolation. Gas species of the ambient air such as nitrogen, could adhere on the surface before installation and could release uncontrolled during crystal growth. Few is known about the release of nitrogen from the growth setup during the initial phases of PVT crystal growth. However, many authors report unintentional background doping with nitrogen [5, 6].

In this work, the evolution of nitrogen release during different initial phases of silicon carbide crystal growth over time is investigated using in-situ mass spectroscopy.

Experimental

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Growth machine and setup. The monitoring was conducted during growth processes of 100 mm n-type crystals in a conventional PVT growth machine with inductive heating. To provide the desired pressure an oil-free, multi-stage roots pump in combination with a control valve is applied to the growth machine. In all the processes the growth setup and the isolation were of the same type and shape. As silicon carbide source nominally undoped material exhibiting a purity of ca. 6 N was applied for all growth runs. Temperature measurements above were done with quotient pyrometers, below it is an extrapolation and is intended as an illustration (e.g. in figures).

Process steps. The initial phases of crystal growth consist of five steps: (i) pump down to vacuum at room temperature, (ii) holding vacuum during heat up to medium temperature ( ), (iii) T-plateau at medium temperature ( ), (iv) heat up to high temperature ( ) and build-up of an inert gas pressure of , (v) gradual reduction of pressure (typically in the range of 5 to 10 mbar ) and introducing of nitrogen gas for doping. During this last step the growth of the crystal will begin. Optionally, at the end of process step (iii) it is possible to conduct one (or more) pump and purge-steps. This optional step is divided into two substeps: (iiia) building up an inertgas-pressure of 200 mbar with an argon flow of 100 sccm for 90 minutes, (iiib) stopping the argon flow and pumping down the PVT setup to vacuum pressure again. Between two pump and purge steps an interval of about 120 minutes is necessary to reach a sufficient vacuum in the PVT growth machine.

Residual gas analysis. During all five steps, exhaust is pumped out of the PVT growth machine. A part of the exhaust gas volume can be diverted between the control valve and the roots pump and passed through a high-vacuum pumping station (HiCube 80 Eco, Pfeiffer Vacuum Technology) in a quadrupole mass spectrometer (PrismaPro QMG 250, Pfeiffer Vacuum Technology) for gas analysis. At process step (i), (ii) and (iii) the control valve is fully opened, at step (iv) and (v) the valve is actively controlled to provide the desired pressure. It must be mentioned that the spectra can only be compared if the control valve is in the same position during the measurements. During monitoring of a growth run, a mass spectrum is recorded every ten minutes in the range of to .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.79.pdf

Release of nitrogen at initial process steps. In the initial steps of the PVT growth process mainly the process step (ii) and (iii) are of interest, as these steps serve to purify the growth setup. During the heat up in vacuum, there are some abnormalities in the PVT pressure curve observable. In the first part of step (ii) the pressure increases linearly with temperature, followed by a phase of decreasing pressure. After this second part, the pressure increases again and reaches the maximum pressure in step (ii), followed by a phase of slightly decreasing pressure. During this process step, the exhaust gas was continuously analyzed with the mass spectrometer to determine a possible correlation between pressure evolution and nitrogen present in the gas phase.

In Fig. 1 the pressure in the PVT growth machine and the temperature at the top of the crucible over run time of process step (ii) is shown. The figures represent the data of crystal growth run A (top) and B (bottom). For better understanding of the phenomena in the evolving of pressure, the duration of process step (ii) was varied. In growth run A , the length of step (ii) was , in growth run it was . By examination of the evolution of the molecular nitrogen-related signal (at in the spectra) with mass spectrometry, it is noticeable, that the curve progression of the nitrogen-related signal shows segments which are in accordance with the pressure curve and others which are not. During two thirds of the run time of process step (ii), the intensity of this signals increases slightly. At the time, which the pressure curve describes the first maxima, the intensity of the nitrogen-related signal still increasing constantly. No connection between the signal and the pressure can be established. The maximum in the curve of the nitrogen-related signal (or in the case of B: the plateau) occur at the same time as the second pressure maximum in the PVT growth machine. Due to the concurrence of these maxima, it seems reasonable to assume that the pressure in the PVT growth machine increases because of the massive release of nitrogen inside the reaction chamber. Maxima of other signals than could not be seen in the full mass spectra at this time, except the signal at (not shown). However, it is more than one order of magnitude weaker than the signal at . In both growth runs, the maxima in the nitrogen-related signal were measured at the end of the second third or at the beginning of the last third of the step run time. At this time, both growth setups will be in the same temperature range. So, it seems to be a temperature-dependent release of nitrogen from the growth setup, which reaches the necessary temperature at this point. The part of the growth setup which releases the nitrogen at this time is actually not known. Further examinations are necessary to understand this process.

Fig. 1: Pressure (dark green / a.) and temperature (red / b.) in the PVT growth machine during initial step (ii). Additionally, the variation of the mass spectroscopy signal at during initial step (ii) over time (yellow / c.) is shown. Data from growth run no. A (top) and B (bottom).

Fig. 1. Pressure (dark green / a.) and temperature (red / b.) in the PVT growth machine during initial step (ii). Additionally, the variation of the mass spectroscopy signal at during initial step (ii) over time (yellow / c.) is shown. Data from growth run no. A (top) and B (bottom).

Pump and purge steps. To reduce unintentional species from the growth setup it is common to carry out one (or more) pump and purge steps before starting crystal growth.

Analogous to Fig. 1, Fig. 2 shows the pressure in the PVT growth machine, the temperature at the top of the crucible and the measured signal of during the pump and purge steps at the end of process step (iii). The figure represents the data of crystal growth run B. At the end of process step (iii) the pressure in the PVT growth machine lays constant at , after the first pump and purge step the pressure reaches a value of . One reason for the significantly lower pressure that can be achieved is the reduction of the present amount of nitrogen. The signal intensity at was significantly reduced from at run time to almost at run time . By pumping and flooding with inert gas again it should be possible to further reduce the amount of nitrogen and the achievable vacuum pressure. Besides the reduction of the amount of molecular nitrogen as a result of the pump and purge steps, a reduction of the signal intensity was also observable at (molecular hydrogen), (carbon), (nitrogen) and others (data not shown). It should be mentioned, that during active argon flow the valve at the exhaust outlet is actively controlled and because of that the signal intensity measured by the mass spectrometer is not comparable to that measured by fully opened valve.

Fig. 2: Pressure (dark green / a.) and temperature (red / b.) in the PVT growth machine during pump and purge steps. Additionally, the variation of the mass spectroscopy signal at over time (yellow / c.) is shown. Data from growth run no. B.

Fig. 2. Pressure (dark green / a.) and temperature (red / b.) in the PVT growth machine during pump and purge steps. Additionally, the variation of the mass spectroscopy signal at over time (yellow / c.) is shown. Data from growth run no. B.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.79.pdf

The evolution of the amount of nitrogen during the initial steps of silicon carbide crystal growth in a PVT growth machine could be monitored by in-situ mass spectrometry. During heat up in vacuum a sharp rise in the intensity of the nitrogen-related signal was measured in the range of about . This event could be related to the pressure increase that occurred at the same time in the PVT growth machine. Additionally, the influence of pump and purge steps as part of the initial crystal growth process on the amount of nitrogen in the gas phase was examined. It was shown that the amount of nitrogen could be reduced efficiently with this method.

Using these results further developments of the growth process are possible to minimize the incorporation of unintentionally released nitrogen. Besides this, other species occurring during the process steps could be monitored and examined for further understanding of reaction- and releasing processes.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.79.pdf

We greatly acknowledge the provision of the experimental setup for gas analysis, consisting of highvacuum pump station (HiCube 80 Eco) and quadrupole mass spectrometer (PrismaPro QMG 250) by Pfeiffer Vacuum Technology and the financial support by the German Science Foundation (DFG) under contract number WE2107/12-2 and WE2107/15-1.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.79.pdf

Peter J. Wellmann, Review of SiC crystal growth technology, Semiconductor Science and Technology 33.10 (2018): 103001.

H-J. Rost et al., Influence of nitrogen doping on the properties of single crystals grown by physical vapor transport, Journal of crystal growth 257.1-2 (2003): 75-83.

Ta Ching Hsiao et al., Major Carrier Element Concentrations in SiC Powder and Bulk Crystal, Materials Science Forum. Vol. 963. Trans Tech Publications Ltd, 2019.

Jeong Min Choi et al., New materials for semi-insulating SiC single crystal growth by PVT method, Materials Science Forum Vol. 963. Trans Tech Publications Ltd, 2019.

Eunjin Jung et al., Synthesis of V-doped SiC powder for growth of semi-insulating SiC crystals, Ceramics International 44.18 (2018): 22632-22637.

J. R. Jenny et al., High-purity semi-insulating 4H-SiC grown by the seeded-sublimation method, Journal of electronic materials 31.5 (2002): 366-369.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 84-88

doi: 10.4028/p-n5l77t

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-18

Revised:
2022-03-10

Accepted:
2022-03-10

Online:
2022-05-31

Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

Marcin Zielinski , Marc Bussel , Hugues Mank , Sylvain Monnoye Marc Portail , Adrien Michon , Yvon Cordier .

NOVASiC; Savoie Technolac; 73375 Le Bourget du Lac cedex; France

CRHEA, CNRS-UPR10, Université Côte d'Azur, rue Bernard Grégory, 06560 Valbonne, France

mzielinski@novasic.com, mbussel@novasic.com,

smonnoye@novasic.com, mpo@crhea.cnrs.fr, am@crhea.cnrs.fr, yc@crhea.cnrs.fr

Keywords: 3 C -SiC, 4 H -SiC, CVD, p-type doping, Al memory effect

Abstract

Experimental results presented in this contribution demonstrate that adding HCl to the SiC CVD process is not only an efficient way to suppress the Aluminum memory effect but may also be considered as a powerful tool for fine tuning of intentional Al incorporation in and thin films. The approach is easy to implement and seems more reliable than changing TMA bubbling/dilution parameters during the growth. An ad-hoc phenomenological model is proposed to explain the correlation between the HCl supply and Al incorporation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

Aluminum is a principal p-type dopant in silicon carbide epitaxy. Precise and reproducible control of epilayer doping is of major concern in fabrication of epitaxial stacks for electronic devices. It requires a detailed understanding of the influence that the growth conditions may have on dopant incorporation (see [1] and references therein).

The precursor used in CVD growth of Al-doped SiC epilayers is liquid Tri-Methyl-Aluminum (TMA). The TMA bubbler has to be kept under stabilized pressure / temperature and connected to an dilution line to allow fine tuning of precursor supply. Consequently, modifications of the TMA supply during the growth process are more complex to achieve than for gas precursors (like Nitrogen as n-type dopant), due to longer stabilization times.

Another issue in deposition is related to the Al memory effect [2] which prevents obtaining sharp doping interface after growing heavily Al-doped layer and maintains high residual incorporation of Aluminum in subsequent runs. Several solutions limiting the influence of this uncontrolled Al contamination were proposed: reactor baking between runs, site-competition growth with high ratio or adding hydrogen chloride ( HCl ) gas to the process. The latter solution, proposed by Ji et al, was particularly efficient to reduce Al residual and achieve abrupt NID interface [3], however the mechanism was not explained.

To better understand the interplay between the presence of HCl during the growth process and the reduction of Al incorporation in the epilayer we performed a series of growth experiments involving simultaneous introduction of TMA and HCl in the reactor chamber. The growth trials included heteroepitaxial and homoepitaxial growth. We used and contactless sheet resistance measurements to evaluate the variations of doping between samples. The results led us to propose a phenomenological model that explains Al doping variations observed experimentally.

Experimental Details

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CVD setup. SiC thin films were deposited in previously described horizontal, low pressure, resistively heated hot wall CVD system with rotating sample holder [4]. Standard chemistry was used with purified hydrogen ( ) as carrier gas, high purity ( 5 N ) silane ( ) and propane ( ) as
principal precursors, Tri-Methyl-Aluminum (TMA) as Al source and hydrogen chloride (HCl) diluted in . The bubbler containing liquid TMA under stabilized pressure / temperature was connected to dilution line, allowing the control of TMA supply in the range . The supply of pure HCl could be controlled in the range .

Table 1: Characteristics of sample series analyzed in present study.

Series
Polytype
TEPI
(°C)
Growth Rate
(μm/h)
TMA
(sccm)
HCl
(sccm)

(A)

4.0×10⁻³ - 1.1×10⁰
0

(B)

2.3×10⁻¹ - 9.1×10⁻¹
0

(C)
3C-SiC
1400
2
9.1×10⁻¹
0-40

(D)
5.6×10⁻²
0-21

(E)
1.7×10⁻¹
0-42

(F)
1.1×10⁰
0-42

(H)
4H-SiC
1750
15
1.1×10⁻¹
0-100

Sample growth. The deposition of films on on-axis substrates was performed using broadly described 3-step process (annealing / carbonization / CVD) with CVD step at relatively high temperature ( ) and low growth rate ( ) in order to attain the best possible structural quality of 3C-SiC epilayer. Typical 3C-SiC film characteristics are given in Ref. [5]. Additionally, homoepitaxial films were deposited on the Si -face of off substrates. Growth was carried out at with deposition rate of under different TMA and HCl flow rates.

Samples. Three series of m thick 3C-SiC(100) epilayers were prepared. Series (A) and (B) were grown without HCl , with different TMA flow rates ( ). For series ( C ), the TMA was fixed and various HCl flow rates were applied. Furthermore, 3C-SiC multilayer stacks (D-F), for SIMS analyses of Al incorporation [Al], were deposited by varying TMA and HCl flow rates. For each SIMS sample deposition started with NID SiC grown without HCl (step 1), then HCl was added (step 2). TMA with constant flow rate was introduced into reactor during step 3 and HCl flow rate was progressively reduced to zero (steps 3-10). The process finished with NID layer (step 11) grown under same HCl flow as in step 2. The experiments were performed for three different TMA flow rates.

For we show in this paper the results for a representative series of samples grown with TMA supply 0.11 sccm , under HCl flow rates covering all the available range . The results will be referred to as series . The principal characteristics of sample series are shown in Table 1.

Characterizations. Secondary ion mass spectrometry (SIMS) measurements of [Al] depth profiles were carried out on a Cameca IMS 6f machine using a primary beam and positive secondary ions ( for Al and as reference signal). Usual detection limit (DL) for Al was . For 3C-SiC/Si samples, the sheet resistance and conductance ( ) of 3C-SiC film was systematically estimated from contactless, eddy current measurements of the wafer before / after the growth. For samples Al incorporation was estimated from measurements with an Hg -probe.

Experimental Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

Figure 1a shows the evolution of 3C-SiC conductance ( ) with for sample series (A) and (B). [Al] is also reported. As expected, stronger conductance was measured for samples with high [Al]. The observed conductance variation (less than 2 decades) is smaller than that of [Al] ( 3 decades) due to concomitant evolution of carrier mobility [6].

Figure 1: (a) Conductance of epilayers as a function of Al supply for sample series (A-B), full & open circles. [Al] values for series (A) are also reported (full diamonds). (b) Conductance of 3C-SiC epilayers (series (C)) as a function of HCl supply.

Figure 1. Figure 1: (a) Conductance of epilayers as a function of Al supply for sample series (A-B), full & open circles. [Al] values for series (A) are also reported (full diamonds). (b) Conductance of 3C-SiC epilayers (series (C)) as a function of HCl supply.

In Figure 1b the evolution of conductance with HCl flow rate for sample series shows clearly decreasing trend. We conjecture that observed tendency reflects the reduction of Al incorporation under HCl flow. This supposition is confirmed by SIMS analyses of multilayer samples (D-F). Figure 2a shows the [Al] profile for the sample (D). It reflects the doping sequence described in previous section. The peak at the interface is related to the presence of residual impurities in the reactor. Introduction of HCl in step 2 leads to the reduction of [Al] down to SIMS detection limit, validating the previous observations of Ji et al [5]. After the introduction of TMA, [Al] increases with decreasing HCl flow rate , following well defined levels for every growth step 3-10. During the last NID step (11), with is reduced to a level as low as in the step 2. The 3 decades' [Al] transition between steps 10 and 11 is extremely abrupt.

The aluminum concentrations obtained in samples (D-F) are presented in Figure 2b as a function of , using log-log scale. The incorporation without HCl is also reported (solid, horizontal lines on the left part of the plot). For each dataset, the points follow a line with constant slope close to -1 , suggesting inversely proportional dependence of versus . Interesting point is that even for low value , almost tenfold reduction of is observed with respect to incorporation without HCl . On the same Figure 2 we reported also the results of series obtained for . As for 3C-SiC samples, a reduction of [Al] is observed with increasing . However, for low HCl flow rates, slower variation is observed. The tenfold reduction of is achieved for .

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

As illustrated in Figure 2b, values seem inversely proportional to . On the other hand, for very low HCl supply, should not increase infinitely but ought to be limited by the total amount of available Al species. This leads us to propose quantitative, phenomenological model for interaction during the growth.

Introduction of HCl in the reactor opens an additional reaction path for Aluminum atoms: they can be either introduced as impurity in SiC layer or react with chlorine to form other species that won't participate in SiC film growth and will be extracted from reactor chamber as a reaction byproduct. The probability for Al atoms to react with chlorine is increasing with HCl supply, from 0 (without HCl ) to 1 at high HCl flow rate. We propose to introduce dimensionless quantity , directly proportional to HCl flow rate, and to quantify in the following way:

The probability for Al atom to incorporate the SiC layer is . Consequently, the Aluminum concentration, proportional to , should follow the relation:

where denotes the aluminum incorporation in absence of is considered as fitting parameter. Power function evolution is generally reported [2], with the exponent between 1 and 2, depending on the experimental conditions and geometry of CVD reactor (see also the result on Fig. 1a).

Figure 2: (a) [Al] depth profile in sample (D) with indicated sub-layers. (b) Evolution of [Al] with for samples (D-F) and (H). Dashed lines correspond to the best fit using proposed model.

Figure 2. Figure 2: (a) [Al] depth profile in sample (D) with indicated sub-layers. (b) Evolution of [Al] with for samples (D-F) and (H). Dashed lines correspond to the best fit using proposed model.

The datasets (D-F) and (H) shown in Figure 2b were fitted using the above described approach. value for each dataset was taken directly from the experiments with values adjusted for datasets (D-F) increase progressively ( ) with increasing applied during the process. For dataset (H), considerably higher value was found. We may associate this effect either to different growth rate and growth temperature settings, or link it with difference of polytype / lattice orientation.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

We observed and clarified the variation of intentional Al incorporation, inversely proportional to the flow rate of HCl added during CVD process of SiC . For samples, tenfold reduction was obtained for HCl flow rates as low as 2 sccm . For higher HCl supply, the reduction exceeded 2 decades without degradation of surface morphology or structural quality of film. For , tenfold reduction was achieved for sccm. Proposed phenomenological model describes well the tendencies observed in and . In parallel, we could verify that in , the nitrogen incorporation was not affected by HCl presence in the process.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

This work has been partially supported by the European projects CHALLENGE (Call: H2020-NMBP-2016-2017, grant. agreement 720827) and PicoGeo (Call: H2020-FETOPEN-2018-2020, Proposal number: 863220).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.84.pdf

M. Zielinski et al, Mat. Science Forum 858, 137 (2016).

A. Schöner et al, Mat. Science Forum 600-603, 175 (2009).

S. Ji et al, Japanese Journal of Applied Physics 53, 04EP07 (2014).

A. Leycuras, Mater. Sci. Forum, 338-342, 241, (2000).

M. Zielinski et al, Mater. Sci. Forum, 924, 306, (2018).

S. Contreras et al, Phys. Status Solidi A 214, 1600679 (2017)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 89-93

doi: 10.4028/p-f58944

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-18

Revised:
2022-02-14

Accepted:
2022-03-10

Online:
2022-05-31

Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide

The original version of this paper is available on https://www.scientific.net/MSF.1062.89.pdf

Matthias Arzig , Ulrike Künecke , Michael Salamon , Norman Uhlmann and Peter J. Wellmann

¹Crystal Growth Lab, Materials Department 6 (i-meet), Friedrich-Alexander-Universität Erlangen-Nürnberg, Martensstr. 7, 91058 Erlangen, Germany

Fraunhofer Institute for Integrated Circuits, Development Center for X-Ray Technology (EZRT), 90768 Fürth, Germany

matthias.arzig@fau.de, ulrike.kuenecke@fau.de, michael.salamon@iis.fraunhofer.de, norman.uhlmann@iis.fraunhofer.de, peter.wellmann@fau.de

Abstract

The growth conditions of 75 mm SiC crystals in the PVT process is varied by different methods while the temperature field is kept constant. The addition of graphite into the source material leads to the formation of an ordered step flow with step heights of , while the addition of graphite into the source together with doping changes the step kinetics on the main facet, leading to very large, bunched steps of . When elemental Si was added into the source material large macro steps are formed on the whole crystal surface. While the doping induced step bunching is related to the incorporation kinetics, the large steps induced in Si-rich conditions are attributed the reduction of surface energy. With the variation of the inert gas pressure the morphology of the surface is altered, similarly. Under low pressure conditions ( 0.2 mbar ) a fine step structure evolves, while at a high pressure ( 40 mbar ) large surface steps are formed on the whole growth interface. Large surface steps are strongly impeded in their lateral motion at defects permeating the growth interface. At these sites the formation of foreign polytypes is facilitated.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.89.pdf

The technology to grow 4H-SiC single crystals has matured and suppliers continuously improve the crystal quality and increase the diameter. With the transfer to renewable energies and to a decarbonization of the individual traffic, the demand for SiC based power devices rapidly increased. The growth of SiC is limited to crystal-lengths of several 10 mm due to the large temperature gradients and the necessary high temperatures make the process energy intensive. This makes the industrial growth of SiC expensive due to the required manual labor for every growth run and the high energy costs. It is therefore very important to find a process window with a high yield of highquality crystalline material of the desired polytype.

While in the literature mainly the influence of the doping gas on the step morphology is discussed [2], we present a simultaneous correlation of nitrogen doping, -ratio and inert gas pressure which influence the surface morphology of the growing crystal. As SiC occurs in the form of several polytypes, a fine structure of growth steps is advantageous to prevent the nucleation of foreign polytypes [1].

Experimental

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Several 75 mm 4H-SiC crystals were grown by the PVT method in the same temperature field while the gas phase composition was varied by different methods (see Table 1). The crystals were grown at a temperature of measured at the top of the crucible which corresponds to a temperature of at the seed surface as estimated by numerical simulation. Growth is performed on the c-polar face of seeds and powder from the same batch is used for all growth runs.

In a set of experiments, additional of graphite (crystal #1) or silicon (crystal #3) were mixed into the SiC source powder, respectively, without intentional doping. To discriminate the influence of the doping gas also an experiment with additional graphite and nitrogen doping was conducted (crystal #2). For these experiments an inert gas pressure of 10 mbar is established with Argon. Furthermore, the gas phase composition is varied without additions to the source material, by carrying out crystal growth processes at different inert gas pressures of 0.2 mbar (crystal #4) and 40 mbar (crystal #5) changing the mass transport of the reactive gas species to the growth interface.

Table 1: Growth parameters of the SiC crystals.

Crystal | #1 | #2 | #3 | #4 | #5
Addition to source | C | C | Si | - | -
Doping | - | N₂ | - | N₂ | N₂
Growth pressure [mbar] | 10 | 10 | 10 | 0,2 | 40

Results and Discussion

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Figure 1: Step structure at the edge of the main facet of a) crystal #1, b) crystal #2 and c) crystal #3. Large surface steps on the surface of crystal #3 pile up at defects. The arrow marks where the formation of the foreign polytype inclusion (p) formed.

Figure 1. Figure 1: Step structure at the edge of the main facet of a) crystal #1, b) crystal #2 and c) crystal #3. Large surface steps on the surface of crystal #3 pile up at defects. The arrow marks where the formation of the foreign polytype inclusion (p) formed.

Influence of doping. The addition of into the gas phase changes the step kinetics on the main facet, leading to step bunching as also reported in literature [2]. But in our case, the bunched steps visible in Figure 1 b) are much larger with an average height of and an average width of measured by laser scanning microscopy (LSM). A more detailed inspection of the giant macrosteps on crystal #2 with field emission scanning electron microscopy (FESEM) and atomic force microscopy (AFM) (Figure 2) reveals that they are build up from closely bundled smaller steps with heights in the range of 10 nm . These bundles of steps are found on the facet of the crystal to be formed dynamically. They can be bunched together very closely giving the impression of a single macrostep but also bundles where the substeps move apart from each other, dissolving the large macrostep are found in Figure 1 b). The undoped crystal in contrast exhibits a very ordered pattern of bunched steps with an average step height of and width of determined by LSM. Effects leading to an ordered step structure are the step repulsion [3] as well as the Ehrlich-Schwoebel effect [4]. When is adsorbed on the crystal surface it is believed to change the incorporation rates of adatoms at the step edges from the upper and lower terrace leading to a density fluctuation of steps [2,5]. This change in the step kinetics leads to different step patterns on the facet as visible on crystal #1 and #2 in Figure 1 a) and b). The charge carrier concentration of the nominally undoped crystal is determined to be while for the doped crystal #2 it is determined to be . Both crystals exhibited an overall high polytype stability, but it must be noted that in the case for crystal #1, without nitrogen doping, a singular polytype switch occurred at the end of the growth process. Therefore, the topmost part including the main facet of crystal #1 are of the 6H polytype.

This is important when the fine steps in between the macrosteps are regarded which are of half unit cell size for crystal #1. On the large terraces of crystal #2 the very ordered pattern of fine steps visible in Figure 2 a) is of single unit cell step height, validated by AFM. In the convex shaped growth interface besides the main facet both crystals exhibit a very smooth surface.

Figure 2: a) FESEM image of the facet of crystal #2. The ordered steps in between the large macro steps are of single unit cell height b) AFM image showing the ordered fine steps on the terrace left and the bundled together macrosteps right.

Figure 2. Figure 2: a) FESEM image of the facet of crystal #2. The ordered steps in between the large macro steps are of single unit cell height b) AFM image showing the ordered fine steps on the terrace left and the bundled together macrosteps right.

Influence of C/Si ratio. Although grown nominally undoped, too, the charge carrier concentration of for crystal #3 is larger than that of crystal #1, which is attributed to the site competition effect [6]. From in situ CT growth surveillance (not shown here), it is obvious that no molten Si exists during growth of crystal #3. Therefore, a change from SiC-C to SiC-Si equilibrium conditions is not expected. The step structure of crystal #3 grown from a SiC powder source with additional Si compared to crystal #1 grown from a source powder with additional graphite differs not only on the main facet but on the whole crystal surface. With an average height of the steps are bigger and their spacing of is larger, too. The morphology of the large bunches differs from that of crystal #2 suggesting a different cause of their formation. In AFM measurements the step treads are found to be planes where rarely any finer steps are found on top. The step structure seems to be more determined by the reduction of surface energy than by step kinetics, as large low energy surfaces are developed between the risers of the macro steps. Low energy surfaces are also found to develop in the solution growth of SiC [7]. The comparison of crystal #1 and #3 shows that the C/Si ratio in the growth cell influences the step morphology on the whole crystal surface. As depicted in Figure 1 c ) the surface morphology at the crystal flank besides the main facet is dominated by large surface steps in the case of growth from a Si rich source material. The step flow is disturbed where defects (micropipes in particular) permeate the surface of the crystal. When the steps pile up at a defect, a wide terrace is formed behind it, exposing the basal plane to the growth ambient. Here the 2D nucleation with a different stacking sequence can occur, enabling the formation of a foreign polytype inclusion. This especially takes place in the transition area from the facet to the convex curved part of the growth interface. The asterisk in Figure 1 c ) marks where this mechanism led to the formation of a polytype inclusion in crystal #3. When carbon is added into the source material, a very smooth surface is formed at the crystal flank as depicted in Figure 1 a) and b). Defects running along the c-direction seem to hamper the step flow only little. The nucleation of foreign polytypes is reduced.

Influence of inert gas pressure. The temperature at the top of the source leads to the formation of a combined equilibrium pressure of the reactive gas species ( ) of 23 mbar [9] for the crystals #4 and #5. In the case of crystal #4 this is more than the inert gas pressure of 0.2 mbar allowing the reactive gas species to be transported by a pressure gradient into the gas room. At the large inert gas pressure of 40 mbar for crystal #5, only the transport by the concentration gradient i.e. diffusion of the reactive species through the Ar in the gas room is possible. From the reactive gas species Si has the highest diffusion coefficient while the carbon carrying molecules
and have lower ones [8], enabling a lower ratio at the growth interface. This means for crystal #4 the C/Si ratio at the growth interface is larger (more C-rich) than for crystal #5 (more Sirich) due to the different transport mechanisms. Nevertheless, the difference in the C/Si ratio should be smaller than for crystals #1 and #3. The doping levels of crystals #4 and #5 are comparable with and , respectively.

Figure 3: a) smooth surface of crystal #4 b) surface of crystal #5 featuring large steps and a polytype inclusion denoted by p

Figure 3. Figure 3: a) smooth surface of crystal #4 b) surface of crystal #5 featuring large steps and a polytype inclusion denoted by p

In Figure 3 differences in the step size on the growth interfaces are visible. For crystal #4 the surface is very smooth with a step height of 0.5 nm on the facet measured by AFM. Crystal #5 is characterized by large steps on the whole crystal surface. The average macro step height on the facet edge is with an average distance of measured by LSM. Like in the Si-rich case (crystal #3), the step flow on crystal #5 is strongly disturbed at defects. The large terraces behind a pile up of steps at defects enable the formation of foreign polytype inclusions (Figure 3 b) leading to the formation of diverse foreign polytype inclusions in crystal #5.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.89.pdf

The gas phase composition in front of the growing crystal in the PVT process can be manipulated in several ways. While the doping gas influences the step kinetics leading to step bunching on the main facet, the C/Si ratio in the gas phase seems to influence the step morphology on the whole crystal surface. A step flow of fine steps seems to be beneficial for the polytype stability and can be induced by additional graphite in the source material as well as by the growth under low pressure conditions without further additions to the source material. Because a foreign polytype inclusion catastrophically deteriorates the crystal quality, growth conditions which promote the formation of fine steps on the growth interface are recommended.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.89.pdf

Kimoto, T., A. Itoh, and H. Matsunami, Step-Controlled Epitaxial Growth of High-Quality SiC Layers. physica status solidi (b), 1997. 202(1): p. 247-262.

Ohtani, N., et al., Step bunching behaviour on the {0001} surface of hexagonal SiC. Journal of Crystal Growth, 2000. 210(4): p. 613-622.

Marchenko, V.I. and A.Y. Parshin, Elastic properties of crystal surfaces Journal of Experimental and Theoretical Physics, 1980. 52(1).

Schwoebel, R.L. and E.J. Shipsey, Step Motion on Crystal Surfaces. Journal of Applied Physics, 1966. 37(10): p. 3682-3686.

Ohtani, N., et al., Observation of Macrostep Formation on the (0001) Facet of Bulk SiC Crystals. Materials Science Forum, 2000. 338-342: p. 379-382.

Larkin, D.J., et al., Site-competition epitaxy for superior silicon carbide electronics. Applied Physics Letters, 1994. 65(13): p. 1659-1661.

Mitani, T., et al., Morphological stability of 4H-SiC crystals in solution growth on {0001} and surfaces. Journal of Crystal Growth, 2017. 468: p. 883-888.

Avrov, D.D., et al., Inclusions of carbon in ingots of silicon carbide grown by the modified Lely method. Semiconductors, 2008. 42(13): p. 1469-1474.

Avrov, D.D., et al., The analysis of mass transfer in system -SiC- -SiC under silicon carbide sublimation growth. Journal of Crystal Growth, 1999. 198-199: p. 1011-1014.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 94-98

doi: 10.4028/p-00832x

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-19

Revised:
2022-02-04

Accepted:
2022-02-08

Online:
2022-05-31

Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues

The original version of this paper is available on https://www.scientific.net/MSF.1062.94.pdf

Marc Portail , Sébastien Chenot , Mahdis Ghorbanzadeh-Bariran , Rami Khazaka , Luan Nguyen , Daniel Alquier and Jean-François Michaud

CRHEA, CNRS-UPR10, Université Côte d'Azur, Rue Bernard Grégory, 06560 VALBONNE, France

Université de Tours, GREMAN, UMR-CNRS 7347, 16 rue Pierre et Marie Curie, BP 7155, 37071 TOURS cedex 2, France

mpo@crhea.cnrs.fr, sc@crhea.cnrs.fr, mgb@crhea.cnrs.fr, @crhea.cnrs.fr, @crhea.cnrs.fr, alquier@univ-tours.fr, michaud@univ-tours.fr

**Present address at ASM Belgium NV, Kapeldreef 75, 3001 Leuven, Belgium

Abstract

We present an epitaxy-based approach for realizing a Capacitive Micromachined Ultrasonic Transducer (CMUT). The design requires to grow a heterostructure on a Si substrate. This requires different growth steps of SiC on Si and Si on SiC . We present some specific growth related issues, namely the control of selectively grown Si on a masked layer and the further regrowth of on a layer. The final release of the SiC membrane, to define a CMUT, is also presented using a simple thermal treatment to reduce the total number of technological steps.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.94.pdf

Capacitive Ultrasonic Micromachined Transducers (CMUTs) are a family of MEMS devices widely used for medical ultrasonic imaging and non-destructive sensing (biology, gas industry, etc..). Their base principle relies on the monitoring of capacitance changes between two parallel electrodes, one of them being suspended above a sealed cavity [1]. If such a device is widely used for consumer applications, the development of SiC-based sensors could address a growing demand for applications in harsh environments (nuclear, space, etc...), according to physical and chemical properties comparing very favorably to commonly used materials (PZT, silicon) in terms of higher chemical inertness and hardness to radiation. Thus, we propose in this work to consider a heterostructure on a substrate as a base platform for designing a SiC -based CMUT structure. We discuss presently some of the different issues encountered in the fabrication of such an heterostructure, using Chemical Vapor Deposition (CVD) for targeting the formation of crystalline epilayers, whose utilization is expected to improve device performances according to better mechanical properties than amorphous forms.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1062.94.pdf

Targeted heterostructure. Fig. 1 summarizes the different steps, developed in our lab, to achieve a layer forming a suspended membrane, separated from an underlying base layer by an insulating film (final step (6)). The whole process requires both epitaxial and technological steps. We presently only focus on the epitaxial steps (4) and (5) according to their special interest in terms of epitaxial growth. The achievement of step (6), based on a thermal approach, will be also discussed.

CVD growth steps. Both SiC and Si epilayers have been grown in a home-made resistively heated hot wall horizontal SiC reactor, using and for C and Si precursors, diluted in . In addition to precursors, hydrogen chloride has been used for step (4).

In step (1), a layer is grown on 2 inch using a "classical" two stages process (carbonization under during 10 min at followed by an epitaxial plateau at , ) with a typical thickness close to . See [2] for a review on SiC growth on Si .

Steps (2) to (4) form a key sequence to obtain a patterned surface with silicon mesas separated by an insulating material, formed in steps (2) and (3) and detailed after. Step (4) is a subsequent growth step, required to selectively grow Si on the masked surface. We have already reported about the growth of Si on non-patterned 3C-SiC(100) surfaces, with a single step process using diluted in at , 900 mbar [3]. Presently, we assume that the selective character of the growth can be triggered by the addition of chlorine in the gas phase. Taking as base process that developed on non-patterned 3C-SiC(100) surfaces, we added HCl to with ratio equal to 0 (no HCl ), 0.4, 0.8, 1 and 2. Different growth temperatures have been explored, ranging from to .

Step (5) requires the grow of SiC on a patterned surface. Few papers in the literature address specifically the control of the final orientation of SiC grown on [4,5] but it is known that the growth of SiC on surface can lead to different SiC orientations. Presently, we focus on the role of the introduction temperature of the propane during the thermal ramp up prior to the epitaxial stage. This step is composed of a 5 -minute annealing under hydrogen at , followed by a short cooling down to ; heating is then turned on again and is introduced during the temperature ramp-up precisely at a given temperature ranging from 850 to and flows up to the epitaxial temperature ( ). Comparative growths have also been realised on substrate for benchmarking on a "defect free" surface.
3. Insulating mask and patterning. has been employed as an insulating mask. 200 nm thick films have been deposited using cathodic sputtering (2)). Following deposition, formation of a micrometer-sized patterning, compatible with a CMUT design, has been realized using photolithography, etching (ICP process using as etchants), and lift-off process for step (3).

Figure 1. Schematic workplan for heterostructure elaboration, base structure of a CMUT device.

Figure 1. Figure 1. Schematic workplan for heterostructure elaboration, base structure of a CMUT device.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.94.pdf

Selective growth of silicon. Fig.2a-c shows Scanning Electron Microscope (SEM) micrographs recorded after Si growth on a masked 3C-SiC(100) surface (step) under different conditions. The square shaped structures, linked by rectangular areas, observed on the SEM images correspond to the initial 3C-SiC(100) windows. Areas between these square shaped zones correspond to the initial mask. In addition to the SEM morphological observations, Energy Dispersive Xray Spectroscopy (EDS) has been used to characterize the chemical nature of the surface coverage. EDS spectra have been systematically acquired for all samples on both "mask" and "window" zones (Fig.2). An evolution of the morphology is observed. On the initial SiC windows, the surface presents a quite rough character independent on the or growth . A higher magnified image of such a surface is presented in Fig.2d where small grains can be seen. Significant changes were noticed on the masked regions according to the growth conditions. At "low" ratio and growth values
(Fig2.a) the masked regions present a rough character which totally disappear for the highest value we used and for higher temperatures (Fig2.c). In the same time, EDS measurements indicates the presence of a Si film on the mask in the former case, whereas only stoichiometric (checked by performing quantitative analysis - not shown) is measured in the last one.

Figure 2. SEM images recorded on SiO 2 masked surface after Si growth under different conditions. EDS spectra recorded both on mask and window regions. (d)-(e) SEM on chlorinated - non-chlorinated growth respectively.

Figure 2. Figure 2. SEM images recorded on SiO 2 masked surface after Si growth under different conditions. EDS spectra recorded both on mask and window regions. (d)-(e) SEM on chlorinated - non-chlorinated growth respectively.

This clearly reveals a selective growth character for the last case. Selectivity has been widely discussed and documented for the growth of Si on Si substrate [6] but, to the best of our knowledge, no publication has reported on this mechanism for Si on 3C-SiC. According to the large dependence of the selective character on the experimental parameters for the Si on Si case (pressure, chemistry employed for the growth, geometry of the patterns...) our results cannot definitely state the most critical parameters for achieving the selectivity. However, the importance of both high Cl/Si ratio and high growth temperature for favouring the selectivity with a mask is presently demonstrated. Another point of interest is related to the effect of HCl addition on the morphology of the grown Si film. As illustrated in Fig.2d-e, a clearly different morphology is obtained according to whether the process is chlorinated or not. For a non-chlorinated growth (Fig.2e), a quite smooth Si film is developing on the surface, characterized by the presence of anti-phase domains as already reported elsewhere [3]. However, the addition of HCl lead to a strongly facetted Si film (Fig.2d). This has been observed even for the non-null lowest values used ( 0.4 ).
2. Growth of SiC on Si(110). Fig. 3 presents X-rays diffraction (XRD) spectra recorded both on reference substrates (I) and on patterned heterostructures (II) after growth of SiC . On substrate, a comparison is made between samples grown with propane introduced at (a) and (b). It can be seen that the SiC film grown with the introduction is clearly (111) oriented, whereas both and diffraction lines are observed for introduction, revealing a polycrystalline nature. The same growth process was applied to patterned heterostructures, with a propane introduction. For that case, diffraction is clearly observed but we notice a weak diffraction (Fig.3-II-a), attesting to a lower degree of organization than on the Si substrate. Fig. 3 also presents the typical surface morphology observed for the different samples. The sample grown with propane introduction at shows a regular 3-fold symmetry which can be related to twinned domains according to the possibility for to grow on a surface with two equivalent in plane positioning [7]. A higher roughness is observed after growth with propane introduction at a higher temperature, as well as in the case of growth on the thin layer formed on the heterostructure. In the last case, this could be attributed to the lower
quality of the Si grown film, favouring the development of misoriented domains, with respect to the very high quality of the Si substrate. We previously assumed that surface roughness could trigger the final SiC crystalline orientation [8]. The present results also show that both temperature of introduction and quality of the initial impact the SiC regrowth.

Figure 3. XRD (I) SiC on Si substrate: (a) intro , (b) intro ; (II) SiC on heterostructure: (a) non-annealed, (b) annealed; SEM on intro surface (III), intro (IV), heterostructure (V).

Figure 3. Figure 3. XRD (I) SiC on Si substrate: (a) intro , (b) intro ; (II) SiC on heterostructure: (a) non-annealed, (b) annealed; SEM on intro surface (III), intro (IV), heterostructure (V).

Thermal annealing. Finally, the last issue presently addressed is the way of achieving a silicon dissolution for creating a SiC suspended membrane on a cavity (step 6)). In order to avoid a chemical approach requiring different processing steps (opening holes in the uppermost part of SiC, dissolving Si and closing the holes), a thermal annealing at under during minutes at 200 mbar has been performed. According to the relative low thickness of SiC, the suppression of the intermediate Si has been obtained by this method, as confirmed by SEM (not shown) and XRD where Si (220) diffraction can be suppressed after such annealing (Fig. 3-II-b). SEM performed in cross section configuration also tends to reveal that this suppression mechanism does not lead to a membrane thickening and let's assumes that Si removal could preferentially be due to the formation of volatile species able to diffuse throughout the defective thin SiC layer and be released in the gas phase. The point is of importance for two reasons: (i) the thermal annealing is efficient to achieve a suspended SiC membrane, but (ii) it shows that such membrane is featured by a porosity due to defects, requiring to further address this potentially problematic point.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.94.pdf

We present some epitaxy-related issues for an ongoing research project aiming to develop crystalline SiC-Si stacked heterostructures for CMUT fabrication. We emphasized some steps which can be helpful for a better understanding of mechanisms encountered during the different steps of the heterostructure elaboration.

This work has been financially supported by ANDRA (PIA4-2016-2022) within the scope of the "H2MEMS" project.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.94.pdf

A. S. Ergun, G. G. Yaralioglu, B. T. Khuri-Yakub, J. Aerosp. Eng., 16, pp 76-84 (2003)

G. Ferro, Crit. Rev. in Sol. State and Rel. Mat., 40, pp 56-76 (2015)

R. Khazaka, M. Portail, P. Vennéguès, D. Alquier, J-F. Michaud, Acta Materialia 98, pp336-342 (2015)

T. Nishiguchi, M. Nakamura, K. Nishio, T. Isshiki, S. Nishino, Appl. Phys. Lett. 84, pp3082-3084 (2004)

S. Sambonsuge, L. N. Nikitina, Y. Y. Hervieu, M. Suemitsu, S. N. Filimonov, Russ. Phys. J. 56, pp1439-1444 (2013)

M. R. Goulding, Mat. Sci. Eng. B 17, pp47-67 (1993)

T. Nishiguchi, et al., Mat. Sci. Forum 483-485, pp193-196 (2005)

R. Khazaka, J-F. Michaud, P. Vennéguès, L. Nguyen, D. Alquier, M. Portail. J. Appl. Phys. 120, 185306 (2016)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 99-103

doi: 10.4028/p-11oe88

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-19

Revised:
2022-02-25

Accepted:
2022-03-10

Online:
2022-05-31

Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy

The original version of this paper is available on https://www.scientific.net/MSF.1062.99.pdf

Tawhid Rana , Gil Chung , Andrey Soukhojak , Meongkeun Ju , Matt Gave and Edward Sanchez

SK Siltron CSS, Auburn, MI, USA

tawhid.rana@sksiltron.com, gil.chung@sksiltron.com, andrey.soukhojak@sksiltron.com, mk.ju@sksiltron.com, matthew.gave@sksiltron.com, edward.sanchez@sksiltron.com,

Keywords: Silicon carbide epitaxy, Basal plane dislocation (BPD), Interfacial Dislocation (ID).

Abstract

Interfacial Dislocation (ID) in SiC epitaxy was investigated. It is known that generation of interfacial dislocation on SiC epitaxy depends mainly on misfit strain between substrate and the epilayer. In this paper we investigate the impact of temperature profile, doping profile of the epilayer and resistivity of the substrates on the formation of interfacial dislocation in epilayers. Our preliminary results show that thermal profile during the epitaxy plays a key role in formation of interfacial dislocation in epilayers. We demonstrated reduction or elimination of interfacial dislocation in epilayers by optimizing the temperature profile of the substrates during the epitaxial growth.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.99.pdf

Silicon carbide is a material of choice for high power electronics due to its superior electronic and thermal properties [1]. However, reduction of defects in SiC epitaxy is challanging for reliable device performance. Defects can adversly impact the device performance by increasing leakage current, forward voltage degradation, higher on resistance etc. Among various defects, basal plane dislocation (BPD) is particularly detrimental due to its unpredictable forward voltage degradation under stress [2]. Hence, reduction in BPD is desired to achieve improved device reliability. While most of the BPDs in epitaxy are due to the propagation of BPDs from the substrate to epilayer, BPD can also be generated in epitaxy during the formation of interfacial dislocation (ID) since interfacial dislocations are accompanied by a pair of BPDs (Fig. 1). The BPDs in interfacial dislocations are shown after KOH etching in Fig. 1a. and in PL images in Fig. 1b. Interfacial dislocations are generated when their critical thickness are exceeded [3]. Hence, in order to reduce in grown BPDs, it is essential to reduce or eliminate interfacial dislocation, especially for thicker epilayers. In this paper we investigate the influence of doping concentration, temperature profile, and we optimize the process to reduce or eliminate ID in epilayers. Our preliminary results suggest temperature profile plays a dominant role for the formation of ID during the epitaxial growth.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.99.pdf

Commercial grade CVD reactor was used to grow epitaxial layers with a thickness of substrates ( 150 mm diameters). Reactor pressure and temperature were kept fixed with a fixed doping concertation of ( N -type) and a ratio of . Epitaxial growths were performed at , with a fixed growth rate and for a film thickness of . A buffer layer of a thickness of and a doping of was used for these epilayers.

Fig. 1: a) Half loop areays of TEDs are shown after KOH etching. Apair of BPDs shown in dotted circles seen after KOH etching b) PL image of the interfacial dislocation is shown for an epilayer. BPDs in PL images are seen as dark horizontal lines at the top and bottom of the interfacial dislcoations.

Fig. 1. a) Half loop areays of TEDs are shown after KOH etching. Apair of BPDs shown in dotted circles seen after KOH etching b) PL image of the interfacial dislocation is shown for an epilayer. BPDs in PL images are seen as dark horizontal lines at the top and bottom of the interfacial dislcoations.

Temperature profile over the wafer region was varied by changing the geometry of the graphite parts. Simulation was performed to determine the temperature profile using a commercially available software. Candela CS920 PL imaging was employed to detect and count defects in the epilayer, and KOH etching was performed to decorate the defects. For these epilayers, we visually count the number of interfacial dislocations from the PL imaging as shown in Fig 1(b)

Fig. 2: a) Temperature profile with higher temperature at the center of the wafer generates higher interfacial dislocation (a) and temperature profile with lower temperature at the center generates lower interfacial dislocation (b).

Fig. 2. a) Temperature profile with higher temperature at the center of the wafer generates higher interfacial dislocation (a) and temperature profile with lower temperature at the center generates lower interfacial dislocation (b).

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.99.pdf

To study the effect of temperature profile, we grew epitaxy with both bowl shape and dome shape temperature profiles. In the dome shape temperature profile, the center temperature is higher than the edge (Fig. 2, condition 1). On the other hand, center is lower than edge for bowl shape temperature profile (Fig. 2, condition 2). When epitaxy was grown with a dome shape temperature condition, we observed high number interfacial dislocations in the center of the epilayers. However, if epilayer was grown using a bowl shape temperature profile, we see a much lower density of interfacial dislocation in the epilayer than that of in a dome shape temperature profile (Fig. 3). This
can be explained by misfit stress created by thermal strain [3-5]. We believe that misfit strain is higher when temperature on the center of the wafer is higher than the edge of the wafer. On the other hand, misfit related strain was lowered by optimizing the temperature profile. We believe, with the optimization, the temperature profile is flattened compared to the non- optimized condition.

Fig. 3: Variability plot to compare interfacaial dislocaiton for two different temperature profiles. Higher number of interfacial dislocaiton is seen when center temperature is higher than the temperature at the edge. Interfacial dislocaiton was reduced significantly with optimizaiton of temperature profile.

Fig. 3. Variability plot to compare interfacaial dislocaiton for two different temperature profiles. Higher number of interfacial dislocaiton is seen when center temperature is higher than the temperature at the edge. Interfacial dislocaiton was reduced significantly with optimizaiton of temperature profile.

Misfit strain can also be created by doping mismatch between substrate and epilayer, as lattice distortion can occur due to doping mismatch [3]. To investigate the impact of doping mismatch, we compared resistivity profile of bare wafers, and doping profile of the epilayers with higher and lower interfacial dislocation (Fig. 4) conditions. We divded wafers into two groups. Group including wafers with 0 interfacial dislocation was named as "good" and group including wafers with interfacial dislocation was named as "bad" (Fig. 4). For our case, doping profile of epilayers with low interfacial dislocation were comparable to the doping profiles of epilayers with higher interfacial dislocation (Fig. 4a). Doping profiles of the buffer layers were also comparable for these epilayers. Typical edge and center doping concentration is shown in Fig. 4b for these epilayers. Similarly, we compared the doping profile of the substrates used for these epilayers. We do not observe any clear correlation for doping profile of the wafers to the generation of interfacial dislocation. Doping profiles of the wafers with low interfacial dislocations were comparable to the doping profile of the wafers with higher interfacial dislocations in the epilayers. These results indicates that the doping concentration related misfit may not have as strong impact as thermal misfit to generate ID during the epitaxy.

Fig. 4: Radial profile was compared for various values for good vs bad wafers for ID. No correlation was seen. a) radial profile of doping concentration of the epilayers b) typical buffer layer profile shown for a wafer.

Fig. 4. Radial profile was compared for various values for good vs bad wafers for ID. No correlation was seen. a) radial profile of doping concentration of the epilayers b) typical buffer layer profile shown for a wafer.

Sammary

The original version of this paper is available on https://www.scientific.net/MSF.1062.99.pdf

We conducted study the impact of temperature, doping concentration and substrate resistivty on the formation of interfacial dislocation in SiC epitaxy. Our results show that temperature profile plays a key role in generating interfacial dislocation, whereas doping profile did not show a good correlation in generating the interfacial dislocation.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.99.pdf

. P. G. Neudeck, R. S. Okojie and Liang-Yu Chen, Proceedings of the IEEE, vol. 90, no. 6, June 2002, pp. 1065-1076

. S. Maximenko and T. Sudarshan, J. Appl. Phys. 97, 074501 (2005)

. Wang, Huan Huan, et al. Materials Science Forum, vol. 778-780, Trans Tech Publications, Ltd., Feb. 2014, pp. 328-331.

. Xuan Zhang, Masahiro Nagano and Hidekazu Tsuchida, Materials Science Forum, Vols 679680 (2011) pp 306-309

. Hirofumi Matsuhata, et al, Materials Science Forum, vol. 600-603, Trans Tech Publications, Ltd., Sept. 2008, pp. 309-312.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 104-112

doi: 10.4028/p-05sz31

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-21

Accepted:
2022-03-07

Online:
2022-05-31

Review of Sublimation Growth of SiC Bulk Crystals

The original version of this paper is available on https://www.scientific.net/MSF.1062.104.pdf

P.J. Wellmann , M. Arzig , J. Ihle , M. Kollmuß , J. Steiner , M. Mauceri , D. Crippa , F. LaVia , Salamon , N. Uhlmann , M. Roder , A. Danilewsky , B.D. Nguyen , S. Sandfeld

Crystal Growth Lab, Materials Department 6 (i-meet), FAU Erlangen-Nürnberg, Germany

LPE S.P.A., 95121 Catania and 20021 Baranzate (MI), Italy

CNR-IMM, Sezione di Catania, Catania 95121, Italy

Development Center for X-Ray Technology (EZRT), Flugplatzstr. 75, D-90768 Fürth, Germany

Crystallography, University of Freiburg, Herrmann-Herder-Str. 5, D-79104 Freiburg, Germany

Institute for Advanced Simulations -- Materials Data Science and Informatics (IAS-9), Forschungszentrum Jülich GmbH, 52425 Jülich, Germany

Chair of Materials Data Science and Materials Informatics, Faculty 5 -- Georesources and Materials Engineering, RWTH Aachen University, 52056 Aachen, Germany

peter.wellmann@fau.de, matthias.arzig@fau.de, jonas.Ihle@fau.de, manuel.kollmuss@fau.de, Francesco.LaVia@imm.cnr.it, 'michael.salamon@iis.fraunhofer.de,

norman.uhlmann@iis.fraunhofer.de, melissa.roder@krist.uni-freiburg.de, a.danilewsky@krist.uni-freiburg.de, bi.nguyen@fz-juelich.de, s.sandfeld@fz-juelich.de

*corresponding author

Abstract

The review on bulk growth of SiC includes a basic overview on the widely used physical vapor transport method for processing of boules as well as the discussion of three current research topics: (a) Sublimation bulk growth of large area, freestanding cubic SiC, (b) in-situ Visualization of the PVT Process using 2D and 3D X-ray based imaging and (c) prediction of dislocation formation and motion in SiC using a continuum model of dislocation dynamics (CDD).

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.104.pdf

In recent years SiC has become the key player among semiconductor materials for power electronic applications. Since the first reports of physical vapor transport (PVT) growth of SiC by Tairov and Tsvetkov [1] in 1978 and Ziegler [2] in 1983, a remarkable progress of SiC based crystal growth, epitaxy and device processing can be observed. For a review on the complete topic of SiC fundamentals, technology and application it is referred to [3]; for a comprehensive review on the bulk growth process of SiC please see [4]. The success of SiC is related to its superior materials properties like extremely high electrical break down field and large heat conductivity compared to the standard silicon counterpart and to a meanwhile very well-developed processing technology exhibiting a comparably high yield. The extraordinary physical properties also include obstacles related to the strong chemical bonds and the complex phase diagram of the material that cause challenges in the growth process. Today's technology matureness is the major reason why SiC outplays other wide bandgap materials like , AIN and Diamond, respectively, for application in power electronics [5]. A key issue for the success of SiC compared to the mentioned wide bandgap counterparts is related to the availability of SiC wafers of large diameter ( standard, demonstrated) and high crystalline quality. Beside the power electronic application, there is a rapidly increasing interest to use SiC in novel photonic applications [6-11]. In all cases, high quality SiC wafers exhibiting a low structural defect density are of particular interest. In addition, low unintentional doping emerges as an important property for novel photonics.

The review paper comprises (i) an introduction to the high temperature crystal growth process of SiC including a brief historical overview [4] as well as (ii-iv) a report on three hot research topics on bulk growth of SiC currently studied in the crystal growth lab at FAU. (ii) In the first focal area, challenges and recent progress of sublimation bulk growth of cubic SiC will be reviewed. (iii) 3D insitu visualization of the growth process by X-ray computed tomography has been applied to investigate the shape of the crystal growth interface as well as the morphology of the consumed SiC powder source. (iv) The third study is attributed to the analysis of the distribution of the dislocation density in as it evolves during the growth process and the cooling down of the SiC boule.

Fig. 1 (a) Phase diagram of SiC. (b) Scheme of the basic PVT process.

Fig. 1. (a) Phase diagram of SiC. (b) Scheme of the basic PVT process.

Bulk Growth Process of SiC

The original version of this paper is available on https://www.scientific.net/MSF.1062.104.pdf

Since the early days of bulk growth of SiC using the physical vapor transport (PVT) [1,2] the basic process has hardly changed, however, the technologic implementation went through numerous progress steps which become necessary because of the increasing requirements to reach a higher crystalline quality and a larger crystal size. The process temperature which usually lies above demands high temperature stable hot zone components. Carbon materials play a key role for the construction of the growth crucible out of isostatic graphite as well as the surrounding high temperature insulation out of porous graphite or fibrous graphite felt. As crucible material, also bulk TaC or graphite coated with TaC are used. Compared to graphite, TaC shows a greater chemical resistance against chemical reactions with the SiC -related gas species Si and . Due to a much lower emissivity of TaC compared to graphite, also an impact on the temperature field distribution inside the growth cell is observed. For the semiconductor application of SiC, purification of graphite crucible parts in a high temperature halide-based cleaning procedure appears inevitable.

Also related to purity, special emphasis must be put on the proper choice of the SiC source material which is often a SiC powder exhibiting a grain size between approximately up to a few millimeters. Purity levels should lie in the 6 N range if n-type conducting materials like doped with nitrogen is desired. In the case of semi-insulating SiC for the application in high frequency devices as well as substrates for GaN base electronic switching devices, ever higher demands in the 7 N or even 8 N range are beneficial. A new demand on high purity SiC comes along with the novel photonic applications of SiC in the field of quantum information. In principle, low background doping levels as low as may be reached using advanced chemical vapor deposition (CVD) of epitaxial layers. Nevertheless, to exclude contamination of the CVD growth cell due to some decomposition of the SiC seeding material, also the SiC wafer applied during homoepitaxial growth needs to fulfil high standards related to low background doping.

The choice of the PVT method as main bulk growth method today is related to the phase diagram of SiC (see Fig.1a) which exhibits a peritectic decomposition of SiC at ca. into carbon and a Si -rich solution. It should be noted that the thermodynamical data of the phase diagram of SiC
presented in literature still vary. While the decomposition temperature around is widely accepted (also unpublished work of the authors confirm this value), the maximum solubility of C in a Si-melt, as well as the precise shape of liquidus line (see curve in Fig. 1a) partially differ. The great technologic advance of the PVT growth method over solution growth of SiC using a Czochralski [12] or Vertical Bridgman [13] configuration could be related to an earlier availability of PVT growth process technology, rather than to large fundamental thermodynamic considerations. It is noteworthy that SiC crystals prepared by solution growth often exhibit a higher crystalline perfection than in the case of PVT growth. The latter is usually attributed to the smaller deviation from thermodynamic equilibrium in the case of solution growth compared to vapor growth. Nevertheless, in terms of crystal size and yield of SiC wafer production, the PVT method outperforms solution growth by far.

Fig. 2 Image of a state-of-the-art grown in the crystal growth lab of FAU using a SICma 600 PVT machine (PVA-CGS, Germany).

Fig. 2. Image of a state-of-the-art grown in the crystal growth lab of FAU using a SICma 600 PVT machine (PVA-CGS, Germany).

In the basic PVT method, a SiC source material and a SiC seed are placed into a crucible which exhibits a pronounced axial temperature gradient to establish a SiC-based mass transport from the source to the seed. In Fig. 1b the axial temperature gradient is set through a cooling channel which interrupts the heat insulation of the crucible on the top. Major efforts have been put into tailoring and design of the proper temperature distribution inside the growth cell. For this, computer simulation of the thermal field and to a certain extend also of the SiC-based mass transport have become standard tools. The demands are twofold. Firstly, the radial temperature gradient should be minimized as much as possible to reduce thermally induced stress of the growing SiC boule while keeping a medium axial temperature maintaining a constant mass transport from the SiC source to the SiC growth interface. The minimization of stress in the growing SiC boule has become the major challenge for the preparation of large crystal diameters of 150 mm and 200 mm , respectively. Note: Beside thermally induces stress, also doping level variations are known to induce strain in the crystal lattice. Secondly, the gas phase composed mainly out of and and the transport paths through the growth cell need to be set properly. Thermodynamically, Si -vapor dominates the gas phase with the highest partial pressure. Chemical reactions with the inner side walls of the growth cell need to be diminished as much as possible. The application of proper graphite materials becomes a key element in the growth cell design. As an option, coating of the graphite surfaces with TaC or even the application of a part or the complete crucible set out of TaC has been reported in literature. Valid
temperature field calculations demand the precise knowledge of the thermal properties of the growth cell components, like the crucible, insulation, SiC source materials and SiC boule.

Initially, the reduction of the defect density during SiC crystal growth was much focused on the reduction of the density of micropipes, which are known to be screw dislocations with a burgers vector exceeding the value of 3c. Usually, micropipes arise at growth process instabilities related to unintentional polytype switches, at secondary phase inclusion (i.e. carbon inclusions or Si droplets) and at cavities in the crystal lattice [14]. Today, micropipe densities well below are standard in n-type wafers. Major research and development efforts target the further reduction of the dislocation density, with basal plane and threading screw dislocations being the most severe line defect for electronic devices. Section "prediction of dislocation formation and motion in SiC" addresses the modeling of the evolution of the dislocation density during PVT bulk growth.

A high yield during production of SiC boules demands a high polytype stability of the growth process. In the case of , a high -ratio in the gas phase (or to say a less Si rich gas phase in the growth regime dominated by a high Si partial pressure) and nitrogen doping stabilize the process. From the perspective of fundamental materials science, growth kinetics aspects, i.e. the height and width of the propagating surface steps (either dominated by continuous step flow or by spiral growth), play the key role, rather than thermodynamic energy differences between various SiC polytypes [15]. However, the cubic polytype, i.e. 3C-SiC, exhibits many obstacles related to the fabrication of high quality SiC crystals for application in mid power electronic switches and novel photonic devices. In the next section "progress of bulk growth of 3C-SiC" the newest achievements and ongoing limitations will be presented.

Fig. 3 Evolution of the diameter of free standing 3C-SiC by sublimation growth on CVD 3C-SiC-onSi seeds.

Fig. 3. Evolution of the diameter of free standing 3C-SiC by sublimation growth on CVD 3C-SiC-onSi seeds.

Progress of Bulk Growth of 3C-SiC

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Contrary to 4H-SiC where homoepitaxial seeding is standard, 3C-SiC bulk growth has been mainly carried out using heteroepitaxial seeding either on ( 0001 ) oriented and or on (111) and (100) oriented thin epitaxial 3C-SiC-on-Si films. Already the first 3C-SiC bulk growth attempts by [16, 17] followed this procedure. Later, several investigations focused on the investigation of proper process parameters that enable stable growth of 3C-SiC by sublimation growth [16-28]. Today, it is generally accepted that a silicon rich gas phase, a high supersaturation at the growth interface and a processing temperature are important to crystallize the cubic polytype. Nucleation of 3C-SiC on hexagonal (0001) oriented SiC is usually accompanied by formation of double positioning grain boundaries (DPBs). Note: DPBs do not occur during nucleation of 3C-SiC on (100) oriented Si . Other structural defects which have been observed after heteroepitaxial nucleation of 3CSiC are stacking faults (SFs) and antiphase boundaries (APBs). It has been recently demonstrated that SFs and APBs can be significantly reduced or even diminished during 3C-SiC nucleation on undulant, off-axis (100) oriented Si substrates [29]. Motivated by this preliminary work, a new effort was started to prepare large area bulk cubic SiC wafers. Thin (thickness to ) CVD grown 3C-SiC-on-

Si layers were removed from the Si -substrates and transferred to high-temperature stable poly- SiC wafer carriers. These new seed stacks were placed into a CS-PVT setup which can easily provide the large axial temperature gradients necessary to reach the anticipated high supersaturation for stable 3C-SiC growth (for process details it is referred to [30-33] and chapter 5 in [3]. Fig. 3 depicts the quick evolution of diameter increase of the free standing 3C-SiC wafer materials with a thickness of up to 1 mm which is related to the availability of larger seeding materials as well as to the up-scaling of CS-PVT growth cell. A further increase of the thickness to values of a few and several millimetres failed so far because of the presence of the so-called protrusion defects. Protrusions start from inverse pyramidal defects at the initial Si-SiC seeding interface and enlarge during growth due to their surrounding SF structure (Fig. 4).

Fig. 4 Cross sectional view of a 3 mm thick free standing 3C-SiC boule. Even in the case of a low density, the expansion of the protrusion defects during growth (bottom = early growth stage, top = final crystal surface) leads to an almost complete spreading of the distorted crystal at the crystal end.

Fig. 4. Cross sectional view of a 3 mm thick free standing 3C-SiC boule. Even in the case of a low density, the expansion of the protrusion defects during growth (bottom = early growth stage, top = final crystal surface) leads to an almost complete spreading of the distorted crystal at the crystal end.

3C-SiC areas not affected by the expansion of protrusions, however, exhibit a perfect crystalline structure and prove the stable growth condition in the newly developed CS-PVT setup. For special cases of (100) 3C-SiC seeding layers with a off-axis declination towards [100] a significant overgrowth of protrusions was observed by Schöler et al. [34]. Nevertheless, as a long-term goal, the presence of protrusions needs to be completely diminished in order develop a real bulk growth process with boule thicknesses beyond 10 mm , respectively. To review the currents status: While 50 mm freestanding 3C-SiC wafers with high crystalline quality are fabricated on a regular base, the preparation of bulk 3C-SiC with a diameter of 100 mm and 150 mm suffers from unintentional cracking of the thin seeding layers. A complete description of the current status of large area growth of free standing 3C-SiC wafers using the CS-PVT method is described in chapter 5 in [3].

2D/3D In-Situ Visualization of the PVT Process

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In-situ visualization methods of the growth process play a key role to develop a bulk growth process as well as to carry out production processing with high reproducibility. Temperature measurements at the top and at the bottom of the growth cell using optical pyrometers may be called standard. Highly advanced 2D and 3D X-ray based in-situ visualization of the PVT process bridges between production and basic process development. While 2D X-ray visualization [35] could be applied to monitor the progress of the SiC boule production, the technical efforts for 3D X-ray CT [36] pay off only for special R&D problems under investigation. Advantages of the 3D X-ray CT insitu visualization are the ability to precisely determine the evolution of the size and position of the (000-1) facet of the crystal growth interface [37](see right image in Fig. 5). In addition, the evolution of the SiC source material may be determined with high precision. In particular, the anisotropy of the step-by-step densified feedstock can be acquired. In conjunction with a newly developed physical model of the heat transfer in anisotropic porous media, the real temperature distribution inside the growth cell has been determined [38]. A correlation of the curvature of the growth interface and predominant step flow mechanism was presented in [39].

Fig. 5 Series of in-situ 3D computed tomography views inside the PVT growth cell at . The imaging allows to track the evolution of the crystal growth interface including the shape, size and position of the facetted growth area. In addition, a high-resolution visualization of the SiC source material enables the precise determination of the temperature field and related growth conditions inside the growth cell.

Fig. 5. Series of in-situ 3D computed tomography views inside the PVT growth cell at . The imaging allows to track the evolution of the crystal growth interface including the shape, size and position of the facetted growth area. In addition, a high-resolution visualization of the SiC source material enables the precise determination of the temperature field and related growth conditions inside the growth cell.

Prediction of dislocation formation and motion in SiC

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Dislocations are known to be one of the major lifetime-limiting defects in semiconductor materials. In SiC, the micropipe, a hollow core screw dislocation of pure or mixed type exhibiting a Burgers b , is known to cause an immediate device failure [40]. Under bipolar device operation basal plane dislocations appeared to act as source for stacking fault generation and propagation in SiC which causes early device failure [41]. Screw dislocations increase the reverse-blocking current in SiC Schottky barrier diodes and alter the performance of SiC MOSFET devices. Even threading edge dislocation are detrimental for device operation if a line up is observed. In general, dislocation formation is observed in the presence of thermally or mechanically induced stress during crystal growth, including the final cooling to room temperature.

From a characterization point of view, dislocation may be visualized using KOH defect etching of SiC wafers (see Fig. 6e)[42, 43] and in a more advanced way by X-ray topography methods [44]. In recent years, using white beam X-ray topography a deep insight in dislocation generation, propagation as well as interaction has been gained (see [45, 46] and chapter 7 in [3]).

To relate the formation of dislocations during crystal growth with the thermal boundary conditions, the thermoelastic strain in the growing SiC crystal as well as the critical shear stress have been considered [47, 48]. For a deeper analysis the so called Alexander-Haasen (AH) model [49] may be applied which uses a continuum model for predicting the evolution of dislocation density in semiconductors through a local dislocation multiplication law. The adaption of the AH model to the complex crystal structure of hexagonal SiC has been carried out by [50]. Recently, Nguyen and Sandfeld ([51] and chapter 8 in [3]) pointed out the limitations of the AH model concerning the lack of motion of dislocations and introduced a more general continuum model of dislocation dynamics (CDD) which explicitly considers dislocation fluxes. Using the AH-GROMA approach for CDDmodeling, the authors show that the consideration of motion of dislocation can have significant impact on the evolution and final distribution of dislocation density. As a result, the calculated evolution of the dislocation density in the growing SiC crystals and the related local plasticity differ significantly between the AH - and the CDD -model. In the AH -model a pile up of dislocation density and plasticity in the area of the maximum shear stress inside the SiC boule is predicted. Due to dislocation motion, however, in the CDD-model dislocations migrate into crystal zones of low shear stress (like into the center of the SiC boule) resulting in a completely different dislocation and plasticity distribution which matches better with experimental data than the AH-model. Fig. 6 shows a comparison of the AH -model and the CDD-model with experimental data. The final dislocation density in the real SiC boule exhibits a maximum in the central area of the SiC boule which is also well predicted in the
more advanced CDD. The AH-model however fails to explain the experimental findings due to the lack of implementation of dislocation motion.

Fig. 6 Comparison of the final dislocation distribution during SiC PVT growth at ca. : (a) and (b) are longitudinal cuts through the SiC boule, while (c) and (d) represent cross sections at . (a) T-field of the model-SiC boule. (b) Related calculated shear stress inside the SiC boule. (c) dislocation distribution after AH-modelling. (d) dislocation distribution after CDD-modeling using a so-called AH-GROMA approach. (e) Image of a SiC wafer that has been sliced from a SiC boule which growth conditions match quite well the modeling assumptions. KOH defect etching was carried out to visualize dislocations. Dark areas represent a high dislocation density.

Fig. 6. Comparison of the final dislocation distribution during SiC PVT growth at ca. : (a) and (b) are longitudinal cuts through the SiC boule, while (c) and (d) represent cross sections at . (a) T-field of the model-SiC boule. (b) Related calculated shear stress inside the SiC boule. (c) dislocation distribution after AH-modelling. (d) dislocation distribution after CDD-modeling using a so-called AH-GROMA approach. (e) Image of a SiC wafer that has been sliced from a SiC boule which growth conditions match quite well the modeling assumptions. KOH defect etching was carried out to visualize dislocations. Dark areas represent a high dislocation density.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.104.pdf

Financial support by the European Commission under the framework of Horizon 2020 (CHALLENGE #720827, SICOMB #899679) and the Germany Science Foundation (DFG)(WE2107/12-2, UH246/4-2, WE2107/15, SA2292/6, DA357/7) is greatly acknowledged.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 113-118

doi: 10.4028/p-y8n42h

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-15

Accepted:
2022-03-10

Online:
2022-05-31

Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1062.113.pdf

J. Steiner , B.D. Nguyen , M. Roder , A. Danilewsky , S. Sandfeld , P. J. Wellmann

¹Crystal Growth Lab, Materials Department 6 (i-meet), FAU Erlangen-Nuremberg, Martensstr. 7, D-91058 Erlangen, Germany

Research Center Jülich Institute for Advanced Simulation, Wilhelm-Johnen-Str., D-52428 Jülich, Germany

Crystallography, Institute of Earth Sciences, Albert-Ludwigs-University Freiburg, Herrmann-Herder-Str. 5, D-79104 Freiburg i. Br., Germany

Chair of Materials Data Science and Materials Informatics, Faculty 5 - Georesources and Materials Engineering, RWTH Aachen University, 52056 Aachen, Germany

a.danilewsky@krist.uni-freiburg.de, s.sandfeld@fz-juelich.de, peter.wellmann@fau.de *corresponding author

Keywords: silicon carbide, physical vapor transport, birefringence, KOH etching

Abstract

Screw-type dislocations like micropipes (MP) and threading screw dislocations (TSD) are prohibiting the function or at least diminishing the efficiency of electronic devices based on silicon carbide (SiC). Therefore, it is essential to characterize wafers in an efficient and fast manner. Molten potassium hydroxide etching or white-beam X-ray topography (SWXRT) are either destructive in the case of KOH etching or not economically viable in the case of SWXRT for an indepth characterization of every wafer of one SiC crystal. Birefringence microscopy is being utilized as a fast and non-destructive characterization method. Instead of microscopic setups, commercially available flat-bed scanners equipped with crossed polarizer foils can be used for fast large-area scans. This work investigates the feasibility of such a setup regarding the detection rate of MPs and TSDs. The results of a full-wafer mapping are compared with birefringence microscopy and KOH etching. In the investigated sample clusters of MPs caused by a polytype switch in the beginning of the growth could be identified by both birefringence microscopy and the flat-bed scanner setup, as well as small angle grain boundaries and threading edge dislocation (TED) arrays. However, the resolution of the scanner was not sufficient to identify TSDs. Nevertheless the setup proves to be an easy-to-setup and cheap characterization method, able to quickly identify defect clusters in wafers.

Introduction

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In recent years, the physical vapor transport (PVT) method to grown bulk silicon carbide (SiC) crystals has been established to grown large-area micropipe-free material for the usage in high performance power electronic devices. While micropipes (MP) have largely been eliminated from commercially available wafers, they still can occasionally emerge due to unintentional polytype switches or post-growth annealing treatment [1]. Although SiC crystals with an apparent polytype switch are generally discarded for processing, a polytype switch in the initial seeding phase from 4 H to for example 15 R and back to 4 H will not be visible from the crystal's surface. Such a switch can happen due to suboptimal growth parameters [2]. The distinction between medium-grade and high-grade SiC wafers most often depends on the presence of MPs. Furthermore other defects like threading edge dislocations (TED) or threading screw dislocations (TSD) are still apparent in the currently available wafers, diminishing the performance of devices [3]. White-beam X-ray topography (SWXRT) allows a non-destructive and highly detailed investigation of dislocations in SiC [4], however it is also expensive considering the beam-time required for full-wafer mappings,
in addition to a limited availability of synchrotron sites [5]. In recent years, more compact systems like the Rigaku XRTmicron tool were developed, bridging the gap between SWXRT and birefringence microscopy in availability and setup dimensions. Molten potassium hydroxide (KOH) etching is another accessible characterization method, enabling the determination of dislocation density and types in a timely and cheap manner [6]. However, after the etching process the sample requires further polishing to remove the etch pits, resulting in a loss of bulk SiC material. From an economical point of view this makes this method undesirable. Birefringence imaging however can be used for quality control of grown crystals regarding micropipes as a cheap and non-destructive method.

It has been shown that birefringence microscopy utilizing the rotating polarizer method allows to quantitatively investigate MPs and also TSDs, as long as the Burgers vector of the dislocation exhibits an edge component [7, 8]. Image processing techniques can be utilized for an automatic evaluation of the defect density regarding MPs and TSDs [9]. However with the rise of larger SiC wafers of up to 200 mm diameter, the required dimensions in a microscopic setup start to limit fullwafer mappings. In addition, due to the sequential nature of mapping with a microscope the required time to map larger wafers rises increasingly, up to a power of two.

In this work we investigate the applicability of a new fast-scanning birefringence setup and its limitations regarding the ability to detect the different defect types such as MPs and TSDs. For this, a crystal was grown via the PVT method, sliced into wafers and polished. The wafers were examined with our new flat-bed scanning setup and compared with the results of the birefringence microscopy. To evaluate the detection rate of MPs and TSDs, the wafers were then etched with molten KOH .

Experimental

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A crystal was grown with the PVT method. The wafers were sliced and polished to allow an optical characterization. The wafers are cut off-axis and exhibit a thickness of .

Flat-bed birefringen

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ce setup. A commercially available flat-bed scanner (Epson perfection v800) with a maximum resolution of 6400 dpi and a scanning area of up to was utilized. The SiC-wafer is placed between two linearly polarizing foils, placed in a 90 degree configuration in respect to each other so that passing light is fully extinguished. One scan of a 100 mm diameter sample takes approximately 7 minutes.

Figure 1: Schematic of the flat-bed scanner setup.

Figure 1. Figure 1: Schematic of the flat-bed scanner setup.

Polarization microscopy. For the birefringence microscopy a Zeiss Imager.Z1m microscope belonging to the Crystallography of the Albert-Ludwigs-University Freiburg was used. The sample was mapped with 5 x magnification and the images stitched with the accompanied Zen software. Further image editing was done to remove the brightness shift of the respective images before stitching. One mapping took approximately 30 minutes. Due to the microscope's setup, it took 5 scans to completely map one 100 mm wafer.
KOH Etching. The KOH etching was carried out using the fully automated FAU KOH-etching setup, which is able to perform etchings of multiple 150 mm to 200 mm SiC wafers.
The samples were placed into a KOH melt of for 6

Figure 2: FAU KOH-etching setup

Figure 2. Figure 2: FAU KOH-etching setup

minutes until the dislocations are etched sufficiently.

Discussion

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Comparison between flat-bed scanner image and stitched microscopic image. Fig. 3a) depicts the result of the birefringence measurement done with the flat-bed scanner setup while Fig. 3b) shows the image taken by birefringence microscopy with the Imager.Z1m. In the latter case, a magnification of 200x was employed. The faint repetitive rectangular pattern is an artefact of the stitching process. Both setups are able to show a MP cluster in the center of the wafer. This cluster was caused by a polytype switch during the start of the crystal growth and is not visible in an optical scan. In addition, small angle grain boundaries (SAGB) can be observed at the edge of the wafer. These SAGBs also extend into the center of the wafer, which are apparent in the scan as well. In Fig. 4a) a repeating pattern is visible in our scanner setup. This pattern was verified in Fig. b) and c) as TED arrays by KOH etching.

Apart from that, the sample depicts a homogeneous intensity distribution in both images 3a) and 3b). The black dots visible are carbon inclusions caused by a process irregularity. In general, there are no apparent features missing in the birefringence image taken by the flat-bed scanner setup compared with the one taken by the Imager.Z1m microscope. The MP cluster in the center of the sample is magnified in Fig. 3c) and 3d), where 3c) belongs to the scanner setup and 3d) to the microscopic setup. For an easier comparison, two MPs are marked as 1 and 2. The MPs are clearly visible in both images, as well as a faint hexagonal pattern in the facet region. However, this pattern was not detected after the KOH -etching was completed. Since it is also apparent in the optical scan without birefringence, it is most likely a variation in nitrogen doping concentration in the facet, which was already reported in literature [10]. Overall, the result of the flat-bed scanner setup proves to be comparable with the one taken by birefringence microscopy.

Limitations of the flat-bed scanner setup. The limitations of this setup also have to be considered. Figure 3e) shows another magnified image of the MP cluster, concentrating on the MPs marked as 1 to 4 . An additional etch pit is marked as 5 . This defect is identified as a TSD via microscopy. The image was taken after the sample has been etched with molten KOH . While these four MPs are visible in the birefringent images, the TSD marked with 5 doesn't show any intensity variation in neither the images taken by the flat-bed scanner setup nor taken by the microscope. The defect count of TSDs and MPs in Fig. 3e) was approximated as 33 in total by means of image analysis using an algorithm developed by the Research Center Jülich Institute for Advanced Simulation. From these 33 threading dislocations, nine were identified as MPs. As a conclusion, the defect cluster can be detected in general while a calculation of the total defect density is not feasible with only birefringence imaging, since from nine MPs only four showed a contrast in the birefringence measurements. The defect cluster depicted in Fig. 3c) and d) exhibits 427 etch pits belonging to

TSDs and MPs. 68 of these defects show a contrast in the images taken with the flat-bed scanner setup, while the remaining 359 defects cannot be observed by the setup.

MP 1 was further investigated in Fig. 3f), where the focus of the microscope was shifted to highlight the path of the MP. As discussed in [7], the MP doesn't progress exclusively along the caxis but also has an edge component. This behavior was observed for all MPs exhibiting an intensity shift in the birefringence measurements. Other MPs didn't show any influence on the detected strain in the crystal. It is calculated by Steeds and further covered by Ouisse et al. that screw dislocations without any edge component in the burgers vector are invisible in birefringence measurements, since they are photoelastically isotropic in the basal plane [8, 11]. Moreover, similar to the TSD marked with 5, we could not detect any TSDs featuring an intensity variation. While possible, it is highly unlikely that there are no mixed-type screw dislocations present in this sample. Therefore, the conclusion has to be that our flat-bed scanner setup doesn't feature the required dynamical range necessary for the detection of TSDs. It has to be noted that the Imager.Z1m microscope was not able to detect TSDs as well despite the fact that birefringence microscopy was able to be utilized for investigating TSDs in previous works.

Figure 3: Birefringence mapping of the sample done with a) the flat-bed scanner setup and b) the Imager.Z1m microscope. c) and d) depict magnifications of the area marked with a rectangle in a) and b), respectively. e) pictures the region of the sample after KOH etching, marking MPs with birefringence signal as 1-4 and a TSD without any signal as 5 . MPs 1 and 2 are the same as in the images c) and d). f) illustrates the path of MP 1 through the crystal. The path is marked with a dashed line.

Figure 3. Figure 3: Birefringence mapping of the sample done with a) the flat-bed scanner setup and b) the Imager.Z1m microscope. c) and d) depict magnifications of the area marked with a rectangle in a) and b), respectively. e) pictures the region of the sample after KOH etching, marking MPs with birefringence signal as 1-4 and a TSD without any signal as 5 . MPs 1 and 2 are the same as in the images c) and d). f) illustrates the path of MP 1 through the crystal. The path is marked with a dashed line.

Figure 4a): Birefringence image of the sample before etching, taken with the flat-bed scanning setup, showing a TED array. b): Magnified image of the etched sample. c): Further magnification showing the single TEDs.

Figure 4. Figure 4a): Birefringence image of the sample before etching, taken with the flat-bed scanning setup, showing a TED array. b): Magnified image of the etched sample. c): Further magnification showing the single TEDs.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.113.pdf

It has been shown that a partial amount of MPs could be identified by the flat-bed scanning setup equipped with two crossed polarizer foils. There was no notable loss in intensity compared with conventional birefringence microscopy. A MP cluster invisible in an optical scan could be detected as well as SAGBs and a TED array. KOH etching was done to investigate the sensitivity of the system to dislocations other than MPs. It has been shown that the setup was not able to detect TSDs or single TEDs. Nevertheless, due to its simple setup and since one full mapping of a 100 mm wafer only takes around 7 minutes, such a system could be an alternative as a non-destructive and fast characterization method to quickly identify SiC wafers with low or high MP density.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.113.pdf

The funding by the DFG under the contract numbers WE2107-15, SA2292-6 and DA357-7 is greatly acknowledged.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.113.pdf

J. Quast, M. Dudley, J.Q. Guo, D. Hansen, I. Manning, S. Mueller, B. Raghothamachar, E. Sanchez, C. Whiteley and Y. Yang, Post-Growth Micropipe Formation in 4H-SiC, Materials Science Forum 858 (2016) 367-370.

J.W. Choi, C.H. Son, J.M. Choi, G.S. Lee, W.J. Lee, I.S. Kim, B.C. Shin and K.R. Ku, Initial Stage Modification for 6 H -SiC Single Crystal Grown by the Physical Vapor Transport (PVT) Method, Materials Science Forum 615-617 (2009) 7-10.

P.G. Neudeck, W. Huang, M. Dudley, Breakdown degradation associated with elementary screw dislocations in 4H-SiC p(+)n junction rectifiers, Solid•State Electron. 42(12) (1998) 2157-2164.

Y. Chen, M. Dudley, Direct determination of dislocation sense of closed-core threading screw dislocations using synchrotron white beam x-ray topography in 4 H silicon carbide, Appl. Phys. Lett. 91(14) (2007).

J. Steiner, M. Roder, B.D. Nguyen, S. Sandfeld, A. Danilewsky and P.J. Wellmann, Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of , Materials (Basel) 12(13) (2019).

S.A. Sakwe, Z.G. Herro, P.J. Wellmann, Development of a KOH Defect Etching Furnace with Absolute In-Situ Temperature Measurement Capability, Mat.Sci.Forum 483-485 (2005) 283.

L.T.M. Hoa, T. Ouisse, D. Chaussende, Critical assessment of birefringence imaging of dislocations in 6H silicon carbide, J. Cryst. Growth 354(1) (2012) 202-207.

T. Ouisse, D. Chaussende, L. Auvray, Micropipe-induced birefringence in 6 H silicon carbide, J. Appl. Crystallogr. 43(1) (2009) 122-133.

A. Kawata, K. Murayama, S. Sumitani and S. Harada, Design of automatic detection algorithm for dislocation contrasts in birefringence images of SiC wafers, Jpn. J. Appl. Phys. 60(Sb) (2021).

K. Yokomoto, M. Yabu, T. Hashiguchi and N. Ohtani, Correlation between the step-terrace structure and the nitrogen doping variation observed on the ( ) facet of crystals, J. Appl. Phys. 128(13) (2020).

J.W. Steeds, Introduction to anisotropic elasticity theory of dislocations (Monographs on the physics and chemistry of materials) by J. W. Steeds, Acta Crystallographica Section A 30(2) (1974) 303.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 119-124

doi: 10.4028/p-nshb40

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-21

Revised:
2022-02-15

Accepted:
2022-03-10

Online:
2022-05-31

Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

The original version of this paper is available on https://www.scientific.net/MSF.1062.119.pdf

M. Kollmuß , J. Köhler , H. Ou , W. Fan , D. Chaussende , R. Hock , P.J. Wellmann

Crystal Growth Lab, Materials Department 6 (i-meet), FAU Erlangen-Nürnberg, Martensstr. 7, D-91058 Erlangen, Germany

Department of Photonics Engineering, DTU, 2800 Kgs. Lyngby, Denmark

Université Grenoble Alpes, CNRS, Grenoble INP, SIMAP, 38000 Grenoble, France

Chair for Crystallography and Structural Physics, FAU, Staudtstr. 3, D-91058, Germany

manuel.kollmuss@fau.de, johannes.jk.koehler@fau.de, haou@fotonik.dtu.dk, weifa@dtu.dk, didier.chaussende@grenoble-inp.fr, frainer.hock@fau.de, peter.wellmann@fau.de

Keywords: CVD, cold wall reactor, void, low temperature, heteroepitaxy, 3C-SiC

Abstract

C -SiC films have been grown on [100] n -doped Si substrates in a horizontal cold wall CVD reactor. Without the use of plasma enhancement, the precursors silane and propane are used to deposit silicon carbide films at . The structure of the grown films has been investigated via FESEM, XRD and Raman spectroscopy. It has been found that the growth rates are between 200 and . Additionally, structural analysis give evidence of polycrystalline phases. Reasons for that could be insufficient cracking of the precursors and homogenous nucleation of Si species in the gas phase.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.119.pdf

In the evolving field of photonic applications SiC plays an important role. The unique optical properties which are related to a wide bandgap, a high third-order optical nonlinearity and a high refractive index, make SiC a promising material for applications such as frequency combs [1]. Additionally, the CMOS compatibility of SiC makes it an even more attractive material regarding the development of optical devices [2]. Based on and , frequency combs were already investigated and show a high potential in the field of photonic applications [1, 3]. Combining SiC with an underlying film forms a suitable refractive index contrast for frequency combs [1]. Since becomes thermally unstable at , epitaxial growth of on Si at is of particular interest, because it would pave the way to heteroepitaxial growth on Si-on-Insulator (SOI) substrates.

In this work thin films are grown in a horizontal cold wall CVD reactor in the temperature regime below . Without the use of a plasma the precursors propane and silane are thermally cracked in the reaction chamber to form SiC thin films on [100] oriented silicon substrates. In this temperature regime 3C-SiC is the thermodynamically most stable polytype [4]. Nevertheless, finding the right growth parameters for a high quality single crystalline SiC film in a cold wall reactor without the use of plasma is challenging. This study includes a series of 3C-SiC thin films deposited at different process parameters (variation of T and ratio) as well as structural, morphological and spectroscopic characterization.

Experimental

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Substrates and epitaxial growth. The CVD experiments were carried out in the horizontal cold wall CVD reactor AIX 200/4 SiC. Silane ( in ) and propane are used as precursors and functions as carrier gas. The temperature of the inductively heated graphite susceptor is set by the power of the radio frequency power supply (Hüttinger TIG 20/300). The sample temperature is
acquired using an optical differential pyrometer. Calibration was verified by observing the melting of Germanium on Si substrate on the susceptor at . N-doped [100] Silicon Wafer pieces with the area of from SIEGERT WAFER GmbH are used as substrates. Before enclosing the substrates into the reaction chamber, they were cleaned in hot bath of acetone, following by a hot bath of ethanol and a Radio Corporation of America (RCA) cleaning step. In between those steps, the substrates were rinsed with deionized water and were dried under a nitrogen stream.

Each epitaxial process consists of several steps. Initially the reaction chamber is flushed several times with hydrogen gas to remove contaminations. Afterwards the susceptor is heated up to an elevated temperature of for a hydrogen etching step of twenty minutes at reduced pressure . For the carbonization step, the temperature is held at for 10 min , while the pressure is increased to 150 mbar . Consequently, a temperature ramp-up to the epitaxial growth temperature is performed. Depending on the process, the temperature and the gas flow rates are kept at the desired level during epitaxial growth for one hour before cooling down under argon flow. For the whole process the rotation of the susceptor is controlled by a gas flux beneath the susceptor. Fig. 1 depicts a typically epitaxy process.

Fig. 1: Typical epitaxial growth process with hydrogen etching, carbonization and epitaxial growth.

Fig. 1. Typical epitaxial growth process with hydrogen etching, carbonization and epitaxial growth.

In Table 1 two experimental growth series are listed. In the first series the temperature is variated, while the ratio is kept constant. In the second series, the ratio is variated for a constant growth temperature. The measured substrate temperature of sample E 10 was slightly lower than for sample E9, E11 and E15, although the applied power of the induction heating was constant for the complete series. Sample E9 is defined as the standard process with a C/Si ratio of 6.8 and a process temperature close to . These standard parameters are based on the work of M. Wilhelm et al. [5]. The is variated by the increase or decrease of the precursor fluxes (see Fig. 3).

Table 1: Overview of the two experimental growth series performed in this work. The mean growth temperature during epitaxial growth and the respective ratios are listed.

Series 1
(T variation)
Series 2
(C/Si variation)

Sample
E2
E3
E4
E9
E10
E11
E15

Temperature (°C)
1126
1153
1164
1183
1166
1183
1188

C/Si ratio
6.8
6.8
6.8
6.8
14.1
14.2
28.1

Characterization. Field effect scanning electron microscopy (SEM) (JEOL, JSM7610F) is used to analyze the surface topography and the cross section of the epitaxial thin films. The growth rate was determined using the layer thicknesses evaluated by SEM cross section image analysis. Structural analysis was carried out using X-ray diffraction (X'Pert, Philips) and Raman spectroscopy (Horiba Scientific LabRAM HR Evolution at a wavelength of 405 nm ), respectively.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.119.pdf

Fig. 2 shows topological SEM images of three samples grown at different temperatures for one hour (series 1, Table 1). The mean temperature during the epitaxial growth is indicated in the corresponding SEM images. Two main effects could be observed with increasing temperature. First the overall optical appearances of the samples changed from dull to mirror-like (no figure shown). And second the topological roughness of the layers decreases. This is attributed to a decrease of grain-like structures that will mainly form at lower temperatures on top of an underlying "closed" 3C-SiC layer. The surface coverage by these structures decreases from for sample E2 to 14.04 % for Sample E4. At higher temperatures (just below ) such particles could be virtually eliminated (see Fig. 3). EDX measurements indicated that the ratio in the grains is shifted towards higher values compared to the closed 3C layers underneath. Therefore, the particles could be associated to homogenous nucleation reactions of silicon species in the gas phase [6].

Fig. 2: SEM topography images of 3C-SiC layers grown on silicon substrates at different temperatures. The mean process temperature as well as the surface covered with grain like structures are indicated in with T and A respectively.

Fig. 2. SEM topography images of 3C-SiC layers grown on silicon substrates at different temperatures. The mean process temperature as well as the surface covered with grain like structures are indicated in with T and A respectively.

In Fig. 3 plan view and cross section SEM images of the four samples belonging to the experimental series 2 are depicted, where the C/Si ratio is variated by controlling the gas flows of silane and propane. For all samples no grain-like structures on top of the underlying layer are visible. Compared to the first growth series the temperatures were higher leading to a reduction of homogenous nucleation in the gas phase and therefore to an elimination of the grain-like structures. From the film thickness of the standard process a growth rate of ca. can be derived. Depending on the C/Si ratio the structure of the grown films slightly changes (Fig 3). By increasing the propane flow (sample E10, Fig. 3b) in comparison to the standard process (sample E9, Fig. 3a), the topology changes to a film consisting of smaller grains. This could be due to the increased availability of carbon precursors, which could favor the formation of multiple but smaller 2D-SiC nuclei on the surface compared to lower propane flow rates. Furthermore, the growth rate increases from to . Meanwhile for a reduced silane flow the grain size of the grown layer is comparable to the standard process. The growth rate changes only slightly with values of for sample E11 and for sample E15, respectively. Chassagne et al. [7] showed, that the growth rate of SiC in a VPE reactor is mainly determined by the silane flux. In our work we found that a change in the propane flux has a higher impact while changes in the silane flow have only a small influence on the growth rate. Whereas a C/Si ratio of ca. 14 by increasing the propane flow (E10) leads to relatively small grains on the surface, a C/Si ratio of ca. 14 by decreasing the silane flow (E11) leads to comparatively bigger, merging grains. This could be explained by the lower
temperatures used in our work. While Chassagne performed epitaxial growth runs at temperatures as high as our experiments were limited to temperatures below . For lower temperatures the cracking of propane will be less efficient limiting the available carbon gas species for the SiC growth. This finding agrees with the work done by Wilhelm et al. [5].

Fig. 3: SEM topography images and cross section images of samples grown in the growth series 2 with different ratio at the same temperature.

Fig. 3. SEM topography images and cross section images of samples grown in the growth series 2 with different ratio at the same temperature.

Raman spectroscopy (Fig. 5a) measurements of the samples of series 2 confirmed that the grown layers are 3C-SiC by the typically TO- and LO-peaks at around and [8], respectively. A tendency of an increase of the LO-mode peak with increasing C/Si ratio is observed. Such behavior was also observed by Wilhelm et al. and could be linked with a slightly increased layer quality [5]. Note: Also, the for sample E 10 is increased the formation of smaller SiC grains due to the higher propane flow rate will lead to a reduced layer quality also evident in the higher signal of the TO-mode. Fig. 5b depicts the XRD measurement of sample E11. Next to the characteristic peaks for (200) and (400) 3C-SiC also a (311)-peak can be identified. This leads to the conclusions, that the films are not purely single crystalline. Additionally, the peak at ca could be attributed to the 6 H polytype. This indicates the formation of stacking faults which can generate, due to their crystallographic orientation, a signal characteristic for the hexagonal polytype.

Fig. 5: (a) Raman spectroscopy results of growth series 2. (b) XRD Analysis of sample E11 with indication of SiC peaks and the (400) silicon peak (substrate). The two broad peaks at around and origin from the sample holder.

Fig. 5. (a) Raman spectroscopy results of growth series 2. (b) XRD Analysis of sample E11 with indication of SiC peaks and the (400) silicon peak (substrate). The two broad peaks at around and origin from the sample holder.

Cross section analyses indicate the presence of voids beneath all grown films. These voids form during the carbonization step by out-diffusion of silicon from the substrate. To avoid this effect, the carbonization step was adjusted. Therefore, the carbonization temperature is increased from to . In addition, a silane flow of 0.3 sccm is implemented during the heat up to growth temperature. Anzalone et al. [9] showed that the addition of Si containing gas species during carbonization can reduce the void formation. Fig. 4a shows the plan view SEM of a layer grown with the adjusted carbonization step. All other growth parameters were kept constant with regard to the standard process of the growth series 2 . The topography of the grown film is covered with grain-like
structures. This result and the findings from series 1 (Fig. 2) raise the assumption, that homogenous nucleation of Si species occurred during the carbonization step, which could be attributed mainly to the low temperatures. Additionally, the cross-sectional SEM image in Fig. 4b proofs, that voids could not be completely eliminated in the underlying silicon using the process described.

Fig. 4: (a) Topologically SEM image of a sample grown with standard parameters during epitaxial growth using elevated temperatures and a small silane flow during carbonization. (b) Cross-section SEM image of the same film, showing a void structure in the underlying silicon substrate.

Fig. 4. (a) Topologically SEM image of a sample grown with standard parameters during epitaxial growth using elevated temperatures and a small silane flow during carbonization. (b) Cross-section SEM image of the same film, showing a void structure in the underlying silicon substrate.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.119.pdf

Thin films of 3C-SiC have been grown in a cold wall CVD reactor at different temperatures and C/Si ratios. A growth series for increasing temperature towards shows grain-like structures on top of an underlying SiC layer, which origin is attributed to homogenous nucleation in the gas phase. ratio variations exhibit differences in the film-structure. The growth rates range between and . While an increase in propane flow leading to a higher growth rate, a decrease of silane flow has a less significant effect on the growth rate. XRD analysis indicate, that films grown at are not yet of single crystalline structure.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.119.pdf

Financial support by the European Union's Horizon 2020 research and innovation program under grant agreement No 899679 (SiComb).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.119.pdf

T. Fan, H. Moradinejad, X. Wu, et al., High-Q integrated photonic microresonators on 3C-SiC-on-insulator (SiCOI) platform, Optics express 26(20) (2018) 25814-25826.

P. Xing, D. Ma, K.J. Ooi, et al., CMOS-compatible PECVD silicon carbide platform for linear and nonlinear optics, ACS Photonics 6(5) (2019) 1162-1167.

M.A. Guidry, K.Y. Yang, D.M. Lukin, et al., Optical parametric oscillation in silicon carbide nanophotonics, Optica 7(9) (2020) 1139-1142.

F. La Via, A. Severino, R. Anzalone, et al., From thin film to bulk 3C-SiC growth: Understanding the mechanism of defects reduction, Materials Science in Semiconductor Processing 78 (2018) 57-68.

M. Wilhelm, M. Rieth, M. Brandl, et al., Optimization of growth parameters for growth of high quality heteroepitaxial 3C-SiC films at 1200 C, TSF 577 (2015) 88-93.

A. Vorob'ev, S.Y. Karpov, M. Bogdanov, et al., Numerical study of SiC CVD in a vertical cold-wall reactor, Computational materials science 24(4) (2002) 520-534.

T. Chassagne, G. Ferro, D. Chaussende, et al., A comprehensive study of SiC growth processes in a VPE reactor, TSF 402(1-2) (2002) 83-89.

Z. Feng, A. Mascarenhas, W. Choyke, et al., Raman scattering studies of chemical-vapordeposited cubic SiC films of (100) Si, Journal of applied physics 64(6) (1988) 3176-3186.

R. Anzalone, G. Litrico, N. Piluso, et al., Carbonization and transition layer effects on 3C-SiC film residual stress, Journal of Crystal Growth 473 (2017) 11-19.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 125-130

doi: 10.4028/p-6zcw3b

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-08

Accepted:
2022-03-07

Online:
2022-05-31

SiC Mass Commercialization: Present Status and Barriers to Overcome

The original version of this paper is available on https://www.scientific.net/MSF.1062.125.pdf

V. Veliadis

PowerAmerica/North Carolina State University, 930 Main Campus Drive, Suite 200, Raleigh NC 27606, USA

jvveliad@ncsu.edu

Keywords: SiC, substrate, epitaxy, fabrication, etch, heated implantation, Ohmic contact, silicide, SiC fab infrastructure, SiC foundry, fabless, basal plane dislocations, bipolar degradation, 200 mm

Abstract

In an increasingly electrified technology driven world, power electronics is central to the entire clean energy manufacturing economy. Silicon (Si) power devices have dominated power electronics due to their low cost volume production, excellent starting material quality, ease of fabrication, and proven reliability. Although Si power devices continue to improve, they are approaching their operational limits primarily due to their relatively low bandgap, critical electric field, and thermal conductivity that result in high conduction and switching losses, and poor high temperature performance. Silicon Carbide's (SiC) compelling efficiency and system benefits have led to significant development efforts over the last two decades and today planar and trench MOSFETs, and JFETs are commercially available from several vendors as discrete components or in high power modules in the 650 V to 1700 V voltage range. High impact application opportunities, where SiC devices are displacing their incumbent Si counterparts, have emerged and include automotive and rail power electronics with reduced losses and reduced cooling requirements; novel data center topologies with reduced cooling loads and higher efficiencies; variable frequency drives for efficient high power electric motors at reduced overall system cost; more efficient, flexible, and reliable grid applications with reduced system footprint; and "more electric aerospace" with weight, volume, and cooling system reductions contributing to energy savings. In particular, SiC insertion in electric vehicles brings major competitive advantages and is a volume application opportunity that can spur manufacturing economies of scale and lower system costs. As SiC continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. It should be noted that in many applications, insertion of SiC reduces overall system cost compared to Si even though SiC devices can cost more than their Si counterparts. This is due to the passive component and cooling system simplifications enabled by the efficient high frequency SiC operation. In this paper, we will review key aspects of SiC technology and discuss overcoming barriers to mass commercialization.

SiC Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1062.125.pdf

Today, the SiC wafer represents of the overall SiC device cost [1], a consequence of its unique complex fabrication specifics. Conventional SiC substrates are primarily grown by the seeded sublimation technique at temperatures of , which creates process control challenges. Crystal expansion is limited requiring the use of large high-material quality seeds, and the sublimation growth rates can be relatively low in the order of . Dislocations propagate through the boule and are present in the device wafers. Furthermore, SiC material's hardness, which is comparable to that of diamond, makes sawing and polishing SiC substrates slow and costly relative to Si .

The epitaxial layers, where SiC devices are fabricated, are grown by chemical vapor deposition (CVD) in horizontal or planetary reactors at . Pressure typically ranges from 30 to 90 Torr and growth rates can be as high as . Epitaxial growth is done on 4 -degree off-cut substrates to maintain the polytype stability of the substrate. Epitaxy goals are to restrict "performance-degrading" defect propagation from the substrate into the epitaxy and ensure that any "performance-degrading" defects propagating from the substrate propagate as benign defects into the
epitaxy. As defects in SiC wafers limit large-area device yields, and numerous devices are paralleled in modules to increase current output, tight epitaxial doping and thickness uniformities are highly desirable, particularly as wafer size increases. Fig. 1 shows a JFET pinch-off voltage map (a parameter that depends on doping) of an overall yield wafer [2]. The screening parameter ranges appear in the top table. The pinch-off voltage screening ranges appear in the bottom table. "Failed" JFETs appear in gray and are primarily located at the wafer edges. The yield includes the contribution of devices located at the wafer edges. The large uniformly situated white squares contain experimental devices and characterization structures. Each color-coded wafer area corresponds to JFETs with pinch-off voltages within the range shown in the bottom right table. The "bull's eye" structure (concentric circular regions of different colors) correlates well with the measured radial doping variation in the epitaxy of this "older generation" 3-inch 4H-SiC wafer. The radial doping variation renders "outer" devices out of specification and lowers yields.

Fig. 1. JFET pinch-off voltage wafer map." The "bull's eye" structure (concentric circular regions of different colors) correlates well with the measured radial doping variation in the epitaxy of this "older generation" 3-inch 4 H SiC wafer. The screening parameter ranges appear in the tables.

Fig. 1. JFET pinch-off voltage wafer map." The "bull's eye" structure (concentric circular regions of different colors) correlates well with the measured radial doping variation in the epitaxy of this "older generation" 3-inch 4 H SiC wafer. The screening parameter ranges appear in the tables.

Overall, SiC wafer fabrication is more complex and slower than that of silicon. The result is more expensive wafers, and ultimately higher device costs. A key part of the vertical integration occurring in today's SiC industry is securing internal substrate and epitaxy wafer capabilities to eliminate purchasing profit margins. In addition, opportunities for disruptive SiC substrate formation, boule slicing, sawing/polishing, etc., have a high return and are being sought by several companies [3].

Presently, the majority of SiC device production is on 150 mm wafers. 200 mm SiC wafers were demonstrated in 2015, and a seven-year or so period historically passes before they become available as products. It is highly desirable that defect density and the cost of material per are the same or lower for 200 mm vs. 150 mm wafers. In addition, wafer planarity should not be worse in the 200 mm wafers. Due to the large fab/foundry overheads, and assuming 200 mm tools are in place, the cost of processing a wafer is to a first approximation unrelated to its size. So processing a 200 mm wafer will produce about 1.8 times more devices than a 150 mm wafer at the same processing cost. Of course, a 200 mm wafer will be more expensive than a 150 mm wafer, and that needs to be factored into the overall cost equation. Many silicon fabs/foundries are starting to process SiC wafers as well, and given the plethora of 200 mm Si fabs/foundries with fully depreciated tools, there are many large 200 mm Si companies waiting on the sidelines to enter SiC production when 200 mm wafers become commercially available. These are companies that have established 200 mm silicon wafer production and do not want to retool to fabricate at the 150 mm SiC wafer size that is currently commercially available. Therefore, when 200 mm wafers become available, many 200 mm fabs/foundries will start producing SiC devices. To illustrate the economic benefits of moving to larger wafer size, let us assume starting material cost parity per between 150 mm and 200 mm wafers. Further assuming a cost for a fully processed 150 mm SiC wafer, and of that coming from the starting wafer material ( fabrication cost), a back of the envelope calculation points to a device cost
reduction when switching to 200 mm . The same fabrication cost scenario, with now of the overall cost representing the starting wafer material, allows for a device cost reduction when switching to 200 mm wafers. These calculations do not include additional processing cost reductions that will come with streamlined mass production in large 200 mm volume fabs/foundries.

SiC Device Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1062.125.pdf

For mass SiC commercialization, high yielding fabrication processes are required. Numerous wellestablished processes from silicon technology have been successfully transferred to SiC . However, SiC material properties necessitate optimization of specific processes including wafer thinning, etching, heated implantation and anneal, and low resistivity Ohmic contact formation [2]. SiC is inert against chemical solvents and only dry etching is practical. Furthermore, the hardness of SiC results in low photoresist selectivity and a "hard" mask, usually composed of metal or dielectrics, is required for SiC photolithographic patterning and etch. deep SiC mesas, trenched using a "silicon" reactive-ion etch (RIE) tool and a Cr/Al mask, are shown in Fig. 2. Cr assists with adhesion of metal layers to the underlying SiC surface. The RIE was fluorine- based for higher mask/SiC selectivity. RIE settings were optimized to eliminate micro-masking and achieve vertical etched sidewall profile formation.

Fig. 2. Reactive-ion etched deep vertical SiC mesas using a mask. Cr assists with adhesion of metal layers to the underlying SiC surface. The RIE was fluorine- based.

Fig. 2. Reactive-ion etched deep vertical SiC mesas using a mask. Cr assists with adhesion of metal layers to the underlying SiC surface. The RIE was fluorine- based.

Fig. 3. Scanning electron microscopy image of a "post ion-implantation" annealed SiC wafer in the presence of a carbon protective cap layer. Excellent surface morphology and high device yield are attained.

Fig. 3. Scanning electron microscopy image of a "post ion-implantation" annealed SiC wafer in the presence of a carbon protective cap layer. Excellent surface morphology and high device yield are attained.

Conventional thermal diffusion is not realistic in doping SiC due to its high melting point and the low diffusion constant of dopants within SiC . Heated ion-implantation is typically performed for doping densities of (the higher doping densities assisting with ohmic contact formation), and room temperature implantation can work well for low implant doses . Nitrogen/phosphorus and aluminum are the preferred impurities for n-type and p-type SiC doping, respectively. The as-implanted depth profiles are retained after the anneal for , and N as expected from their low diffusion constants. The lack of diffusion makes it easy to form shallow junctions and difficult to form deep ones. After ion implantation, a anneal is performed for lattice damage recovery, and high dopant electrical activation. A protective cap layer covering the SiC wafer protects its surface from degradation due to Si desorption and migration of surface atoms, Fig. 3.

The high value of the SiC/metal barrier results in rectifying metal contacts and post metal deposition anneal is required for ohmic contact formation. Typically, a layer is blanket deposited and patterned on the wafer for the simultaneous ohmic contact formation on the n-type and p-type doped regions, Fig. 4. Depending on the specifics of the fabrication process, isolating the
source from the gate areas with dielectrics can facilitate high yields in the subsequent high temperature processing.

Fig. 4. Scanning electron microscopy image of a patterned Ni layer on a SiC wafer surface. Dielectric isolates the metalized implanted gate areas (pitted surface) from the n -doped source stripes.

Fig. 4. Scanning electron microscopy image of a patterned Ni layer on a SiC wafer surface. Dielectric isolates the metalized implanted gate areas (pitted surface) from the n -doped source stripes.

Fig. 5. Scanning electron microscopy image of the Ni patterned SiC wafer of Fig. 8, after a rapid-thermal-annealing event. Ni silicide is formed with no shorting of the p-gate to the nsource regions.

Fig. 5. Scanning electron microscopy image of the Ni patterned SiC wafer of Fig. 8, after a rapid-thermal-annealing event. Ni silicide is formed with no shorting of the p-gate to the nsource regions.

High temperature annealing of the Ni patterned wafer creates Ni -silicide for low resistivity ohmic contact formation. Rapid thermal annealing (RTA) at , using standard silicon fabrication equipment, was used to create Ni-silicide with no metal strings, Fig. 5. The dielectric isolates the source from the gate areas eliminating shorting during the high temperature silicide process.

Unlike Si wafers, SiC wafers are transparent. This complicates the use of "silicon" tools for CDSEM and metrology measurements, as the focal plane is determined with the use of an optical microscope. SiC-specific wavelength metrology/inspection tools are now available from multiple vendors. Another issue is the relative lack of flatness of SiC wafers, compared to those of Si, which can complicate photolithography. In addition, the high-temperature SiC processing can further degrade wafer flatness, occasionally rendering wafers unusable. This is particularly problematic with the thick epitaxy wafers used in +3.3 kV device fabrication. Efforts are underway to produce flatter starting SiC wafers, and to minimize flatness degradation during fabrication. Lastly, the poor interface quality reduces inversion layer mobility. Thus, passivation techniques including annealing in nitrides are utilized to improve the interface quality similar to the case of silicon [4].

Device manufactures have developed IP for several SiC processing steps and compete on both design and processing. Although SiC is not fully CMOS-compatible, the SiC industry has leveraged Si technology processes and infrastructure by making the relatively small financial investments required to adapt existing fabs. Today, SiC manufacturing has matured and its fab infrastructure now mirrors that of Si. Integrated SiC device manufactures coexist with foundries and fabless companies, and design houses provide know-how and IP that can be leveraged to accelerate entry to market, Fig. 6. SiC device fabrication in volume fabs alongside Si has emerged as a "cost reduction" model exploiting "silicon" manufacturing economies of scale. Through re-purposing older fully depreciated 150 mm (and 200 mm in the near future) Si foundries, SiC power devices can be manufactured with the relatively small investments necessary to support the unique SiC processing steps. Minimizing fabrication cost by exploiting the mature Si volume production assumes the fab is loaded close to capacity with standard Si and SiC processes running on the same lines. In addition, aggregating the demand for SiC substrates and epilayers in volume fabs contributes to lower material costs. Lower fabrication costs in a fully depreciated "capacity loaded" fab, coupled with decreased material costs can lead to significant price reductions for SiC devices. This approach offers a new opportunity for outdated Si foundries, which have not kept up with the channel length reductions of the last two decades, to continue manufacturing legacy Si parts while ramping up SiC fabrication that requires relatively modest micron design rules [5].

Fig. 6. The U.S. SiC fab infrastructure mirrors that of Si. It consists of Integrated Device Manufacturers, Foundries, Fabless companies, and Design houses.

Fig. 6. The U.S. SiC fab infrastructure mirrors that of Si. It consists of Integrated Device Manufacturers, Foundries, Fabless companies, and Design houses.

Defects, Reliability, and Ruggedness

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The majority of"killer" defects have been virtually eliminated in modern SiC wafers. Basal-PlaneDislocations (BPDs) are the major remaining defect degrading device performance [6]. BPDs can propagate from the wafer substrate through the thickness of the epitaxial layers where devices are fabricated. BPDs can also be generated during the high-temperature ion-implantation fabrication process. In commercial wafers, more than of substrate BPDs propagate as relatively "benign" threading edge dislocations in epitaxial layers grown off axis by CVD [7].

Fig. 7. Representative drift layer SiC JFET forward gate-drain voltages as a function of time for a fixed dc gate-drain bipolar stress. The compliance is set at . A biased JFET, with its gate-drain diode's bipolar current giving rise to blue/violet electroluminescence, is shown in the inset.

Fig. 7. Representative drift layer SiC JFET forward gate-drain voltages as a function of time for a fixed dc gate-drain bipolar stress. The compliance is set at . A biased JFET, with its gate-drain diode's bipolar current giving rise to blue/violet electroluminescence, is shown in the inset.

Fig. 8. BPD-related JFET ON-state conduction degradation and full recovery by annealing. The black squares, red triangles, and open circles represent the ON-state conduction characteristics prior to bipolar stress, after 5 hours of bipolar stress, and after a anneal, respectively.

Fig. 8. BPD-related JFET ON-state conduction degradation and full recovery by annealing. The black squares, red triangles, and open circles represent the ON-state conduction characteristics prior to bipolar stress, after 5 hours of bipolar stress, and after a anneal, respectively.

When bipolar current flows through a SiC device, electron-hole pair recombination at BPDs in the drift layer provides the energy to activate dislocation glides that give rise to stacking faults and degradation. To investigate the impact of BPDs on the electrical characteristics of ion-implanted SiC transistors 17 JFETs with drift epilayers ( 10 kV rated) were stressed at a fixed gate-drain DC
bipolar current density of for 5 hours. Representative curves are presented in Fig. 7 [8]. At , the gate-drain p-n junction is turned on, as evidenced by the emission of blue/violet electroluminescence at the edges of the JFET (inset photograph of Fig. 7), and bipolar current flows. Of the 17 JFETs stressed, six exhibit no forward gate-drain voltage degradation. This confirms that with optimized process flows and implantation recipes, BPDs are not generated during fabrication. Nine JFETs exhibit intermediate voltage degradation, and two exhibit severe voltage degradation. Bipolar current in the presence of BPDs leads to forward gate-drain p-n junction and ON-state conduction degradations as shown in Fig. 8. Interestingly, transistor BPD-related electrical degradations can be fully reversed by annealing at , while non-degraded characteristics remain unaffected by this annealing.

Threshold voltage instability is the main remaining reliability concern in SiC MOSFETs, which are the dominant transistors in SiC-based power electronics applications. It is primarily due to oxide traps at the gate-oxide interface. A positive shift in the SiC transistor's threshold voltage has the deleterious effect of increasing conduction losses, while a negative shift is undesirable as it can spontaneously turn the device on. Valuable SiC reliability data has been accumulated over years of field operation and is driving device optimization. SiC devices can be made more rugged by leveraging design trade-offs. This, combined with intelligent gate drives, can provide adequate circuit protection [9].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.125.pdf

The compelling efficiency and system benefits of SiC are leading to wide adoption with insertion in electric vehicles being the volume application that enables manufacturing economies of scale and lower system costs. Industry is removing the last barriers to mass SiC commercialization that include higher than Si device cost, the presence of basal plane dislocations, and reliability and ruggedness concerns. The wafer represents a disproportionately high percentage of the overall SiC device cost, compared to that of Si , and technological improvements and transition to volume 200 mm wafer production will help lower those costs. SiC manufacturing has matured, non-CMOS compatible processes are fully developed, and the SiC fab infrastructure mirrors that of Si. Basal plane dislocations are the major remaining yield lowering defect to overcome. Gate-oxide interface quality improvements will enhance performance and alleviate any lingering reliability concerns.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.125.pdf

https://www.exa-watt.com/power-electronics

V. Veliadis, Silicon Carbide Junction Field Effect Transistors (SiC JFETs), in: Wiley Encyclopedia of Electrical and Electronics Engineering, Online (2014) pp. 1-37.

S. Wolf, R..N Tauber, Silicon Processing for the VLSI Era, vol.1, Lattice Press, California, 1986, pp. 222-223.

V. Veliadis, Compound Semiconductor Magazine 25, vol. 36, pp. 36-42, 2019.

E. Van Brunt, A. Burk, D. J. Lichtenwalner, R. Leonard, S. Sabri, D. A. Gajewski, A. Mackenzie, B. Hull, S. Allen, and J. W. Palmour, Mat. Sci. Forum 924 (2018) 137-140.

T. Kimoto, Jpn. J. Appl. Phys. 54 (2015) 040103-1-27.

V. Veliadis, H. Hearne, E. Stewart, M. Snook, W. Chang, J. Caldwell, H. Ha, N. El-Hinnawy, P. Borodulin, R. Howell, D. Urciuoli, and C. Scozzie, IEEE Elec. Dev. Lett. 33, (2012) 952-954.

A. Kumar, S. Parashar, S. Sabri, E. Van Brunt, S. Bhattacharya, and V. Veliadis, IEEE 30th Inter. Sym. on Power Semiconductor Devices and ICs (ISPSD), (2018) 423-426.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 131-135

doi: 10.4028/p-mxxdef

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-21

Revised:
2022-02-14

Accepted:
2022-03-10

Online:
2022-05-31

The original version of this paper is available on https://www.scientific.net/MSF.1062.131.pdf

Séverin Rouchier , G. Gaudin , J. Widiez , F. Allibert , E. Rolland , K. Vladimirova , G. Gélineau , N. Troutot , C. Navone , G. Berre , D. Bosch , Y.L. Leow , A. Duboust , A. Drouin , J-M. Bethoux , R. Boulet , A. Chapelle , E. Cela , G. Lavaitte , A. Bouville-Lallart , L. Viravaux , F. Servant , S. Bhargava , S. Thomas , I. Radu , C. Maleville , W. Schwarzenbach

Soitec SA, Bernin (France), CEA-LETI, Grenoble (France), Applied Materials, Bernin (France)

severin.rouchier@soitec.com, gweltaz.gaudin@soitec.com, cjulie.widiez@cea.fr, frederic.allibert@soitec.com, emmanuel.rolland@cea.fr, kremena.vladimirova@cea.fr, guillaume.gelineau@cea.fr, nicolas.troutot@cea.fr, christelle.navone@cea.fr, Guillaume_Berre@amat.com, Daphnee_Bosch@amat.com, yenlin_LEOW@amat.com, Alain_Duboust@amat.com, alexis.drouin@soitec.com, romain.boulet@soitec.com, audrey.chapelle@soitec.com, guillaume.lavaitte@soitec.com, adeline.bouville-lallart@soitec.com, 'laurent.viravaux@soitec.com, 'florence.servant@cea.fr, 'shivan_Bhargava@amat.com, Shawn_Thomas@amat.com, ionut.radu@soitec.com, christophe.maleville@soitec.com, walter.schwarzenbach@soitec.com

Abstract

Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high power electronics. Despite the continuously improving quality and supply of substrates, the availability of such wafers is still insufficient. An advantageous opportunity is offered by the Smart Cut technology with the integration of a very high quality SiC layer transferred to a low resistivity handle wafer. This bi-layer material enables a significant yield optimization and improvement of the device's electrical performance. Moreover, an additional key feature of the Smart Cut technology is the possibility to re-use multiple times the donor wafer, leading to reduced manufacturing costs and enabling the high volume production of SiC wafers. In this paper, we report the latest advances in the development of such so called SmartSiC™ substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.131.pdf

Among its unique properties, including high electric field breakdown strength and high thermal conductivity, Silicon carbide (SiC) is a material of choice for power devices allowing a higher frequency operation but also to reduce the size and the power losses of the devices. Thus, SiC is a key material for devices developed for high growth applications such as automotive or renewable energy [1]. Semiconductor companies are currently facing an urgent need for capacity expansion to meet the growing market demands. Despite the recent progress in material with a continuous improvement of the quality and the supply, the availability of near defect-free wafers, enabling very high yields, is still insufficient. In this context, we have developed an innovative bi-layer SiC substrate, and installed a dedicated Pilot Line to support the technology development and initial sampling. Thanks to the Smart Cut technology [2], a very high quality 4H-SiC layer is transferred to a specific handle wafer with low resistivity leading to improvement of the device yield and electrical performance.

Smart CutTechnology and Low Resistivity Material

The original version of this paper is available on https://www.scientific.net/MSF.1062.131.pdf

For over 30 years, the Smart Cut™ technology has been used to produce several millions of wafers, through high volume manufacturing processes, mostly silicon wafers. The process has been successfully adapted for SiC material by transferring a high quality crystalline SiC layer to a low resistive wafer support (Fig. 1) [2-5]. Thereby the engineered SmartSiC substrate is epi-ready and the epitaxy growth process to be performed is simpler than for conventional SiC wafers, as the conversion buffer layer is already done.

Figure 1: SmartSiC versus bulk substrates for power devices [2-3]

Figure 1. Figure 1: SmartSiC ™ versus bulk substrates for power devices [2-3]

The Smart Cut technology, described in the following figure (Fig. 2), is based on several key steps like the hydrogen implantation of the donor wafer, allowing to control the thickness of the transferred layer (from to ). A key element of the transfer process is the realization of a highly conductive bonding interface to ensure excellent vertical conductivity through the newly formed substrate. The finishing steps ensure excellent roughness and thermal stability, to prepare an EPI-ready surface. The donor wafer is re-used multiple times, opening the path for high volume wafer production.

Figure 2: Smart Cut process description [2-3]

Figure 2. Figure 2: Smart Cut process description [2-3]

The geometrical and electrical properties of the finished product are closely driven by those of the handle wafer. Fig. 3 illustrates the low resistivity values obtained within the engineered substrate in comparison to commercially available bulk 4H-SiC (Fig. 3a) - the electrical resistivity of the innovated substrate is at least 4 times lower than standard bulk . Moreover, in addition to the improved electrical conductivity, the shape of product, measured through wafer diameters, the thickness, the edge shape, the bow, the warp, the Site Front sQuare focal plane Range (SFQR) and the Total Thickness Variation (TTV) is equivalent to commercial bulk wafers. (Fig. 3b)

Figure 3: 3.a/ Resistivity mapping by Eddy Current measurement on compared to handle wafer low resistivity. 3.b/ BOW & SFQR values distribution on both the reference bulk wafer and the low resistivity handle wafer

Figure 3. Figure 3: 3.a/ Resistivity mapping by Eddy Current measurement on compared to handle wafer low resistivity. 3.b/ BOW & SFQR values distribution on both the reference bulk wafer and the low resistivity handle wafer

SmartSiCPerformance and Validation

The original version of this paper is available on https://www.scientific.net/MSF.1062.131.pdf

An excellent layer integrity and quality is demonstrated. The picture on Fig 4 shows a 150 mm SmartSiC substrate, highlighting the defect-free surface quality, including the small edge crown width ( ).

Figure 4: Picture of a Smart substrate

Figure 4. Figure 4: Picture of a Smart substrate

Intensive physical, chemical and electrical characterizations have been conducted on the SmartSiC to assess the performance of the engineered substrate. Thus, the roughness measurements carried out by AFM in scan confirm the achievement of a smooth surface with (Fig. 5a), similar to a standard substrate. The thickness uniformity of the transferred layer was also measured and a standard deviation lower than was determined (Fig. 5b). The grazing incidence diffraction by X-Ray (GID) on {11-20} plane shows that the layer on the final product is fully stress relaxed (Fig. 5c). Thus, the top 4H-SiC layer on the Smart Cut™ substrate is guaranteed to be EPI-ready.

Figure 5: 5.a/ AFM on SmartSiC & 5.b/ SmartSiC Layer uniformity & 5.c/ GID on {11-20} plane comparison with SmartSiC

Figure 5. Figure 5: 5.a/ AFM on SmartSiC & 5.b/ SmartSiC Layer uniformity & 5.c/ GID on {11-20} plane comparison with SmartSiC

From the well-known manufacturing experience, the Smart Cut process does not impact the geometry of the incoming material. Thus, SmartSiC exhibits the same performance on wafer geometry parameters like flatness, bow, warp and TTV compared to the handle wafer low resistivity (Fig. 6a). The crystal quality of the final substrate is directly linked to that of the donor wafer. We have developed a specific characterization by KOH etching (specially adapted to analyze a thin film), and this one confirms the absence of crystal defect creation during the Smart Cut™ process. SICA inspections on SmartSiC and donors after KOH etching show exactly the same defect density trend (Fig. 6b).

Figure 6: 6.a/ SmartSiC geometry & 6.b/ SICA on donor & SmartSiC after KOH etching (same scan position)

Figure 6. Figure 6: 6.a/ SmartSiC ™ geometry & 6.b/ SICA on donor & SmartSiC ™ after KOH etching (same scan position)

Last but not least, to monitor the electrical performance of the composite wafer, a test structure has been developed to determine the resistivity of the bonding interface (Ohmic behavior with an interface resistivity ). I(V) curves show that SmartSiC has a lower resistivity than conventional (Fig. 7). Thus, this SiC substrate improves the total vertical resistance by a factor of at least 2 (wafer thickness at ) to 3 (wafer thickness at ) versus .

Figure 7: Electrical test structure and I(V) result

Figure 7. Figure 7: Electrical test structure and I(V) result

Conclusions

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The Smart Cut technology provides for the power devices manufacturers an innovative SmartSiC substrate with high crystal quality and low electrical resistivity. The recycling of the initial (donor) SiC wafer enables cost-effective manufacturing of very large volumes with reduced investments. A pilot line is currently ready for 150 mm substrates and 200 mm substrates preparation will be engaged beginning of 2022.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.131.pdf

T. Kimoto et al., "Material science and device physics in SiC technology for high-voltage power devices." Japanese Journal of Applied Physics 54.4 (2015): 040103.

W. Schwarzenbach et al., "Smart Cut™ SiC Substrates for Manufacturing of High Quality Power Devices", Electron Devices Technology and Manufacturing Conference (2021)

L. Di Cioccio et al., "Silicon carbide on insulator formation using the Smart Cut process" Electronics Letters 32.12 (1996): 1144-1145.

F. Letertre et al. "SiC Power Devices on QUASIC and SiCOI Smart-Cut® Substrates: First Demonstrations." Materials Science Forum. Vol. 433. Trans Tech Publications Ltd, 2003.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 136-139

doi: 10.4028/p-ppa587

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-23

Revised:
2022-02-14

Accepted:
2022-03-07

Online:
2022-05-31

Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

The original version of this paper is available on https://www.scientific.net/MSF.1062.136.pdf

Wei Fan , Jeff Lennartz , Peter Schmidt-Sane , Brian Kozak , Bruno Balland , Alex Galyukov , Daria Zimina and Daniel Feezell

¹Momentive Technologies, 22557 Lunn Road, Strongsville, Ohio, USA

STR US, Inc., 10404 Patterson Avenue, Richmond, Virginia, USA

University of New Mexico, 1313 Goddard St. SE, Albuquerque, New Mexico, USA

wei.fan@momentivetech.com, jeffrey.lennartz@momentivetech.com, peter.schmidtsane@momentivetech.com, brian.kozak@momentivetech.com, dfeezell@unm.edu

Keywords: Emissivity, TaC, SiC, GaN, PVT, CVD, MOCVD, epitaxy

Abstract

Tantalum carbide (TaC) coating, produced in an ultrahigh temperature chemical vapor deposition (CVD) process, exhibited high thermal and chemical stabilities, low emissivity, and high purity. Low emissivity of was measured on TaC coating at and compared with the one of SiC coating. As revealed in both simulation and experiment, the low emissivity of TaC coatings not only improves temperature uniformity in the SiC PVT process, but also reduces power consumption in both SiC crystal growth and GaN epitaxial deposition. The results provide important guidance to process tuning when switching from a conventional graphite or SiC-coated component to its TaC-coated counterpart.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.136.pdf

Tantalum carbide ( TaC ) with its high thermal stability, high purity, and high chemical resistance, is often used to coat graphite to suppress contamination and to protect graphite reactor components from corrosive environments [1]. TaC coating is typically applied to crucibles and guide rings in SiC physical vapor transport (PVT) process, and susceptors, carriers, and ceilings in SiC and GaN epitaxial chemical vapor deposition (CVD). Traditionally bare graphite and SiC-coated reactor components are commonly used in those processes. The metallic appearance of TaC coating is quite different from the dark surfaces of graphite and SiC coating. It suggests a different radiation behavior at high temperature. While the operating temperature of GaN and SiC epitaxial deposition ranges from 1100 to [2, 3], SiC crystal growth can reach [4]. Temperature uniformity and gradients are extremely important to those processes and can largely impact the process yield and product quality. Understanding the influence of TaC coating on thermal profiles is of great benefit to process control.

Coating Preparation

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TaC coating in study was generated through a proprietary ultrahigh temperature CVD process by Momentive Technologies Inc. [5]. The coating has an average thickness of , grain size of 20 and roughness (Ra) of . A variety of graphite grades and shapes was used as substrates to receive the coating and good coating adhesion was regularly achieved. Cross section SEM revealed a dense and conformal coating on substrate surfaces, including sharp inner corners. Impurities of B, , and Al measured on the coating by GDMS were 1 to 2 orders of magnitude lower than the ones in purified graphite. XRD and XPS analyses indicated TaC coating is highly crystalline and has a Ta
to C ratio of . SiC coating used in this study for comparison was purchased commercial product and also made by CVD process.

Emissivity

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Emissivity is a material property that gages the energy radiated from a surface. Its value is a function of temperature as well as radiation wavelength. We conducted multi-wavelength pyrometry measurement on a group of SiC and TaC coating samples at . The emissivity spectra (Fig. 1) clearly show that TaC coating presents a much lower emissivity, ranging from to , compared to SiC coating. Typical high temperature graphite emissivity is similar to or higher than that of SiC [6]. A temperature profile change is, therefore, expected in a system that employs TaC coating vs. the traditional SiC coating or bare graphite.

Fig. 1. Emissivity spectra of TaC and SiC coatings measured at

Fig. 1. Emissivity spectra of TaC and SiC coatings measured at

Crystal Growth

The original version of this paper is available on https://www.scientific.net/MSF.1062.136.pdf

A SiC PVT process using both conventional graphite and TaC-coated graphite crucible sets was modeled to understand the impact of emissivity on temperature profile, which can lead to changes in growth rate and ingot shape. Virtual Reactor, the modeling software for crystal growth that employs global heat transfer, heterogeneous chemistry, gas flow, and mass transport, was used in this study. A TaC emissivity of 0.4 was assumed, as was zero reactivity to SiC vapor. The simulation (Fig. 2) revealed that a more uniform temperature would be achieved with the TaC-coated crucible compared to the graphite incumbent. In addition, the superb thermal and chemical stability of TaC coating prevented the carbon reaction with Si vapor. As the result, the distribution along the radial direction was more uniform with TaC coating. A power reduction due to the decreased radiative heat loss was also predicted and later confirmed by experimental work at DongEui University [5].

Fig. 2. Simulated SiC crystal front temperature distribution in the radial direction using TaC-coated crucible (left) and conventional graphite crucible (right) through 70 hours of crystal growth

Fig. 2. Simulated SiC crystal front temperature distribution in the radial direction using TaC-coated crucible (left) and conventional graphite crucible (right) through 70 hours of crystal growth

Epitaxial Deposition

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Another study at the University of New Mexico evaluated TaC and SiC coated wafer carriers with identical dimensions in a commercial metal-organic chemical vapor deposition (MOCVD) tool (Veeco P75). GaN p-n junctions with 7-layer InGaN/GaN quantum well were deposited on sapphire substrates at . Target light emitting wavelength was . It was found that, in order to achieve the same GaN growth rate ( ), 7% more power was required when using the SiC -coated carrier. The same growth rate indicated that the same wafer temperature was reached in both cases. It was further confirmed by the electrical and optical measurements on the produced GaN LEDs (Fig. 3) showing nearly identical characteristics. The low emissivity of the TaC coating on the wafer carrier resulted in less radiative heat loss and, thus, consumed less power.

Fig. 3. Electrical and optical characteristics of LEDs produced using SiC and TaC carriers: (a) and (b) electroluminescence result, (c) electroluminescence light output and (d) V-I curve

Fig. 3. Electrical and optical characteristics of LEDs produced using SiC and TaC carriers: (a) and (b) electroluminescence result, (c) electroluminescence light output and (d) V-I curve

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.136.pdf

TaC coating presented much lower surface emissivity at high temperature compared to SiC coating and graphite. As demonstrated by simulation and experiment, the low emissivity of TaC coatings not only improves temperature uniformity in the PVT process, but also reduces power consumption in both crystal growth and epitaxial deposition. The results provide important guidance to process tuning when switching from a conventional graphite or SiC-coated component to its TaC-coated counterpart.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.136.pdf

D. H. Lee, etc., Materials Science Forum 778-780, 26 (2014)

E. Arslan, etc., J. Phys. D: Appl. Phys. 155317, 41 (2008)

M. Ito, etc., Appl. Phys. Express, 15001, 1(2008)

M. Nakabayashi, etc., Materials Science Forum 600-603, 3 (2009)

W. Fan, etc., Materials Science Forum 22-25, 963 (2019)

Y.S. Touloukian and D.P. DeWitt, Thermophysical Properties of Matter 7: Thermal Radiative Properties (1970)

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 140-145

doi: 10.4028/p-10ru0j

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-11-09

Revised:
2022-03-10

Accepted:
2022-03-10

Online:
2022-05-31

Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

Marcin Zielinski , Marc Bussel , Catherine Moisson , Hugues Mank , Sylvain Monnoye , Marc Portail , Adrien Michon , Yvon Cordier

NOVASiC; Savoie Technolac; 73375 Le Bourget du Lac cedex; France

Université Côte d'Azur, CNRS, CRHEA, rue Bernard Grégory, 06560 Valbonne, France

mzielinski@novasic.com, mbussel@novasic.com, cmoisson@novasic.com, hmank@novasic.com, smonnoye@novasic.com, mpo@crhea.cnrs.fr, yc@crhea.cnrs.fr

Keywords: 3C-SiC, CVD, Vanadium

Abstract

The present experimental study demonstrates the feasibility of Vanadium doping of 3C-SiC hetero-epitaxial material. Vanadium concentration in 3C-SiC is determined from SIMS measurements. Some of Vanadium incorporation trends as well as the influence of Vanadium doping on 3C-SiC resistivity are observed.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

Semi-insulating (SI) Silicon Carbide is used at industrial scale as substrate material for high frequency GaN based devices in order to minimize the parasitic conduction that reduces the device performance. During last 10 years it became also the support of choice for graphene related devices. Highly resistive SiC substrates were obtained through the introduction of Vanadium (V) doping in PVT bulk growth in mid-90's. However, the V concentration close to solubility limit, necessary to compensate important residual doping of the crystal, was at the origin of degradation of structural quality of bulk material. Progressively, V-doped SiC substrates were replaced by high purity semiinsulating material using intrinsic defects (ex C -vacancies) to compensate the residual doping.

A renewed interest in Vanadium doping came in late 2010's with the possibility of introducing V in epitaxially grown . Strongly resistive epilayers of well controlled thickness and resistivity were obtained within (relatively) cheap CVD growth process .

In the case of cubic silicon carbide ( ), one of the issues that prevent the development of electronic devices based on heteroepitaxial 3C-SiC epilayers is the presence of important leakage current related to existence of intrinsic structural defects within the material (stacking faults, -twins, grain boundaries) [3,4], especially in the near interface region of the epilayer. One could expect that the incorporation of Vanadium, especially during the first phase of the growth, should reduce the leakage and improve the electrical properties of the material.

In the present contribution we test the feasibility of Vanadium doping of epilayers grown on silicon, investigate some of incorporation trends and evaluate the influence of Vanadium incorporation on electrical properties of 3C-SiC material.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

CVD setup. Previously described horizontal, low pressure, resistively heated hot wall CVD system with rotating sample holder [5] was employed for deposition of SiC epilayers, with standard chemistry: purified hydrogen ( ) as carrier gas, high purity ( 5 N ) silane ( ) and propane ( ) as principal precursors. We chose Vanadium tetrachloride ( ) as Vanadium precursor. The bubbler under stabilized pressure / temperature was connected to an dilution line. This approach allowed the control of flowrates in the range .

Sample description. Standard characteristics of 3C-SiC epilayers were described in [6]. For the present study, three series of 3C-SiC/Si samples were prepared. First, a batch of thick 3C-
epilayers were grown with various flowrates to establish the maximum Vanadium supply that does not deteriorate the structural / morphological properties of 3C-SiC. In second series, multilayer 3C-SiC(100) and (111) samples with variable Vanadium supply were prepared for SIMS analyses. Finally, a series of thin 3C-SiC epilayers was grown on highly resistive substrates . Contactless sheet resistance measurements were performed on these epiwafers after backside polishing (necessary to remove the parasitic conductive poly- deposited on the backside).

Figure 1. Optical microscopy images of thick 3C-SiC(100) epilayers. Left: standard NID film. Center and right: V doped films. VCl4 flowrate is indicated on the top of the image.

Figure 1. Figure 1. Optical microscopy images of thick 3C-SiC(100) epilayers. Left: standard NID film. Center and right: V doped films. VCl4 flowrate is indicated on the top of the image.

To allow the comparison with literature results that exist for hexagonal polytype, multilayer stacks for SIMS analyzes and single layer samples were prepared. High resistivity SiC films were grown with Vanadium concentration [V] estimated at [V] .

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

Vanadium incorporation in -SiC. Figure 1 shows typical optical microscopy images of thick epilayers. Films with flowrates up to present the same morphology as for standard, undoped (NID) film. For higher Vanadium supply (starting from ), surface defects appear.

Figure 2. Example of SIMS depth profile of Vanadium incorporation in 3C-SiC(100).

Figure 2. Figure 2. Example of SIMS depth profile of Vanadium incorporation in 3C-SiC(100).

Figure 2 shows the depth profile of Vanadium incorporation [V] measured by SIMS in 3C-SiC(100) film grown under supply increasing step by step. SIMS analyses were precisely calibrated using reference sample with controlled Vanadium concentration. To avoid the structural deterioration of the sample we limited the Vanadium supply to . Sublayers are clearly defined and the interface between strongly V doped and the topmost, V-free, sublayer is sharp ([V] drop decades). Minor Vanadium memory effect persists however, as reflected by presence of small [V] peak at 3C-SiC/Si interface.

Figure 3. Vanadium incorporation as a function of supply in and .

Figure 3. Figure 3. Vanadium incorporation as a function of supply in and .

In Figure 3 we show the Vanadium incorporation, deduced from SIMS analysis of multilayer samples as a function of flowrate. Vanadium incorporation in (111) oriented 3C-SiC is slightly higher than for (100) orientation. For both orientations the experimental data can be fitted with power function (exponent for (111) and 1.3 for (100) orientation).

Figure 4. Growth temperature dependence of Vanadium incorporation in 4H-SiC, extrapolated to lower temperature range.

Figure 4. Figure 4. Growth temperature dependence of Vanadium incorporation in 4H-SiC, extrapolated to lower temperature range.

Taking into account literature data on V solubility in (solubility limit ) and low applied flowrates of , Vanadium concentration range indicated on the figures 2 and may appear overestimated. To evacuate the possible doubts on validity of SIMS calibration and ensure the compatibility of our data with existing literature results, we performed some comparative growth experiments on Si -face . We show in

Figure 4 SIMS results taken from a epilayer grown during a slow temperature ramp between . Their extrapolation down to 3 C -SiC deposition regime ( ) allows to estimate Vanadium incorporation above at , i.e. 3 decades higher than in .

Figure 5. Vanadium incorporation as a function of ratio in and Si-face.

Figure 6. DC I-V curves recorded in vertical configuration for n -doped substrate (blue), 4H-SiC:V (green), glass (grey), 3C-SiC:V (red, continuous), 3C-SiC:N+ (red, dots) and 3C-SiC NID (red, dashed line).

Figure 6. Figure 6. DC I-V curves recorded in vertical configuration for n -doped substrate (blue), 4H-SiC:V (green), glass (grey), 3C-SiC:V (red, continuous), 3C-SiC:N+ (red, dots) and 3C-SiC NID (red, dashed line).

We compare in Figure 5 the influence of ratio on in -face and under same supply . In slightly increases with increasing ratio, suggesting preferential incorporation on Si sites, which is expected taking into account atomic radii. In 3C-SiC this increase is marginal (but the study could be performed only for ). Together with almost identical incorporation in (100) and (111) oriented samples (Fig. 3), the results obtained in 3C-SiC do not confirm that Vanadium incorporates on Si-sites.

Electric properties of 3C-SiC:V. The conditions of Vanadium supply during the growth of a series of thin, highly resistive templates are reported in Table I. Eddy current sheet resistance of standard, Vanadium-free reference sample (A) is (mean value of 17 points cartography on 100 mm diameter wafer). The resistance of sample (B), with V-doping in topmost part of epilayer increases to . In Sample (C), where the Vanadium was supplied during
entire CVD step, further increase to was recorded. Introduction of during carbonization step does not seem to further enhance the epilayer sheet resistance (sample D). Finally, for thicker epilayer with increased V supply we recorded . This enhancement of sheet resistance with respect to Vanadium free epilayer is certainly due to Vanadium doping. However, taking into account the reduced 3C-SiC thickness , corresponding 3C-SiC resistivity remains below , very far from the values of bulk SI material (typically ).

Table 1. List of (H.R.) samples and conditions of Vanadium supply. "V" and "2V" stand for flowrate of, respectively, and . Related Vanadium concentration in 3C-SiC epilayer is, respectively, .

Sample:
(A)
(B)
(C)
(D)
(E)

Carbonization:
no V
no V
no V
V
V

Epitaxy:
0.4μm NID
0.1μm NID
0.3μm V
0.4μm V
0.4μm V
0.6μm 2V

RSHEET
2 kΩ/sq
9 kΩ/sq
14 kΩ/sq
11 kΩ/sq
15 kΩ/sq

I-V measurements were performed using Hg probe in vertical configuration (Hg contact, , on the topside of the wafer, mechanical metal contact, , on the backside) for different types of SiC material. The DC I-V curves (in range) are reported in Figure 6. Obviously, this approach does not allow us to statue quantitatively on the resistivity of SiC material. However, a qualitative differences can be clearly seen: for highly conductive substrate ( ), 1 A current range is reached for voltages below . After the deposition of thick 4 H -SiC:V epilayer ([V] ) on such conductive substrate, the I-V vertical characteristics become similar to those of insulating glass (measured current below ).

For the I-V curves are reported for 3 samples with differently doped epilayer: NID, , grown on lowly conductive substrate ( ). All the samples exhibit similar electric behavior indicating that vertical conduction is dominated by the substrate resistivity. The Vanadium related increase of 3C-SiC resistivity is too small to reduce significantly the vertical conductance of the epiwafer. We may conjecture that despite high Vanadium concentration, not all V atoms are acting as traps or that conduction through extended defects paths in 3C-SiC cannot be screened by the presence of V atoms. Even if at this stage we did not observe by optical microscopy any big precipitation defects reported in [1], we can't exclude the formation of submicron, V-rich clusters. The study will be continued to verify this hypothesis.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

Through this study we demonstrated the feasibility of V doping of CVD grown 3C-SiC epilayers and validated the V-related increase of 3C-SiC resistivity. The effect of Vanadium introduction is not as spectacular as in 4H-SiC epilayers, where semi-insulating character of epilayer was achieved. However, observed increase of epilayer resistivity may still be useful ex. in preparation of templates for III-N based RF HEMT devices.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

This work has been partially supported by the European project PicoGeo (Call: H2020-FETOPEN-2018-2020, Proposal number: 863220).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.140.pdf

R. Karhu et al, J. Appl. Phys. 125, 045702 (2019)

K. Murata et al, J. Appl. Phys. 126, 045711 (2019)

X. Song et al, Appl. Phys. Lett. 96, 142104 (2010)

F. Gianazzo et al, Adv. Electron. Mater. 6, 1901171 (2020)

A. Leycuras, Mater. Sci. Forum, 338-342, 241, (2000).

M. Zielinski et al, Mater. Sci. Forum, 924, 306, (2018).

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 146-151

doi: 10.4028/p-369665

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-12-09

Revised:
2022-03-10

Accepted:
2022-03-10

Online:
2022-05-31

Opening Through 200 mm Silicon Carbide Epitaxy

The original version of this paper is available on https://www.scientific.net/MSF.1062.146.pdf

Danilo Crippa , Mani Azadmand , Marco Mauceri , Silvio Preti , Marco Puglisi , Carmelo Vecchio

LPE, via Falzarego 8, 20021 Baranzate (MI), Italy

LPE, XVI Strada, Zona Industriale, 95121 Catania (CT), Italy

danilo.crippa@lpe-epi.com, mani.azadmand@lpe-epi.com, marco.mauceri@lpe-epi.com, silvio.preti@lpe-epi.com, marco.puglisi@lpe-epi.com, carmelo.vecchio@lpe-epi.com

Keywords: 200 mm , epitaxy, 4H-SiC, thickness uniformity, doping uniformity, run-to-run, defects

Abstract

In this paper, the performance of a new CVD reactor (called PE1O8) designed by LPE and developed in the European project REACTION to process uniform homoepitaxy on 200 mm substrate is reported. Its tunable multi-zone injection system and new gas delivery configuration ensure the uniform gas distribution throughout the substrate. Excellent thickness and doping uniformity on 200 mm substrates are achieved with run-to-run variation less than and respectively.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.146.pdf

SiC outperforms Si in many applications, owing superior electronic properties such as high temperature stability, wide energy band gap, high breakdown electric field strength, and high thermal conductivity. Nowadays, electric vehicles traction systems are undergoing significant improvements upon availability of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), due to their higher switching speed, higher operation temperature, and lower thermal resistance [1-4]. In the last years, the market for SiC-based power devices has been grown very rapidly; consequently, the demand for a high quality, defect-free, and uniform SiC materials is increased.
In the last decades, substrate suppliers were able to enlarge wafer diameter from 2 inch to 150 mm (keeping the same crystal quality). Today the mainstream wafer size for SiC devices is 150 mm while, in order to reduce the production cost per unit device, some device manufacturers are in the early stages of setting up 200 mm fabs [5]. To realize this aim, alongside the need for commercially available 200 mm SiC wafers, the ability of performing uniform SiC epitaxy is highly demanded. So, the next challenge after achieving decent quality 200 mm SiC substrates would be to perform high quality epitaxial growth on those substrates.

Engaging in REACTION project [6], LPE has designed and manufactured a horizontal single wafer hot-wall fully automatic CVD reactor (named PE1O8) equipped with a multi-zone injection system able to process up to 200 mm SiC substrates. Here we report its performance on SiC epitaxy and the preliminary results of 200 mm epi-wafers.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.146.pdf

PE1O8 system design and features. PE1O8 is a fully automated cassette-to-cassette system, designed to process up to 200 mm SiC wafers. Format switching between 150 and 200 mm has been made possible minimizing tool downtime. Heat up phase reduction fosters productivity, alongside automation reduces man labor improving quality and repeatability.

To ensure an efficient and cost competitive epi-process, three main factors are reported: 1) fast process, 2) high uniformity in thickness and doping, 3) minimized defect formation during the epiprocess. In PE1O8, the small graphite mass and the automatic load/unload system permit to complete one standard run in less than 75 minutes (standard Schottky diode recipe using a growth rate of ). The automatic system permits to load/unload at high temperature. As a result, rump up
and cool down time are very short, while bake out step has been suppressed. This ideal condition permits to grow real undoped material.

The compactness of the machine and its three-channel injection system lead to a versatile system with high performances in both doping and thickness uniformities. This is inquired through computational fluid dynamics (CFD) simulations in order to guarantee comparable gas flow and temperature uniformity both for 150 and 200 mm substrate format. This new injection system, as shown in Fig. 1, uniformly delivers the gas in the central and in the lateral parts of the deposition chamber. The gas blending system enables the modification of the locally distributed gas chemical composition, further expanding the number of process parameters tunable to optimize epitaxial growth.

Figure 1. Simulated gas velocity magnitude (top), and gas temperature (bottom), in PE1O8 process chamber on a plane placed 10 mm above the substrate.

Figure 1. Figure 1. Simulated gas velocity magnitude (top), and gas temperature (bottom), in PE1O8 process chamber on a plane placed 10 mm above the substrate.

Additional features involve an improved gas rotation system, which uses a feedback control algorithm in order to smooth the performances and have a direct measurement of the rotation speed, and a new generation PID for temperature control.

Epitaxial process parameters. A n-type 4H-SiC epitaxial growth process was developed in a prototype chamber. Trichlorosilane and ethylene are used as silicon and carbon atoms precursors; is used as the carrier gas and Nitrogen for n-type doping. Si-face commercial 150 mm SiC substrates and research grade 200 mm SiC substrates were used to grow thick -doped 4 H -SiC epilayers.
In-situ etching of the substrate surface are applied using flow at elevated temperatures. After that etching step, n-type buffer layer is grown using low growth rate and low C/Si ratio to prepare a smooth layer. On top of this buffer layer, a high growth rate ( ) active layer is deposited, using higher C/Si ratio.
The process developed was then transferred to the PE1O8 reactor installed at ST-Sweden premises. Similar process parameters and gas distribution are used for both 150 mm and 200 mm samples. Due to the limited number of 200 mm substrates available, the fine-tuning of the growth parameters is postponed for future studies.

Epi thickness and doping performance of the samples are evaluated by FTIR and CV mercury probe, respectively. Surface morphology is investigated by Nomarski differential interference contrast (NDIC) microscope, and the defect density of the epilayers is measured by Candela.

Preliminary results. The preliminary results of doping and thickness uniformity of 150 mm and 200 mm epi-grown samples processed in the prototype chamber are shown in Fig. 2. Epilayers are grown uniformly along the 150 mm and 200 mm substrate surface with a thickness variation ( average) as low as and , and doping variation ( average) as low as and , respectively. The intrinsic doping value is approximately .

Figure 2. Thickness and doping distribution of 200 mm and 150 mm epi-wafers

Figure 2. Figure 2. Thickness and doping distribution of 200 mm and 150 mm epi-wafers

The process repeatability is investigated by comparing run-to-run variation, resulting in a variation as low as in thickness and in doping. As shown in Fig. 3, the new 200 mm process results are comparable with the state of art results previously achieved on 150 mm by PE1O6 reactor.

Figure 3. Run to Run thickness and doping uniformity of 200 mm samples processed by prototype chamber (Top), and the state of art 150 mm samples made by PE1O6 (Bottom)

Figure 3. Figure 3. Run to Run thickness and doping uniformity of 200 mm samples processed by prototype chamber (Top), and the state of art 150 mm samples made by PE1O6 (Bottom)

Regarding to the samples surface morphology, NDIC microscopy confirms a smooth surface with roughness below the detectability range of the microscope.

PE1O8 results. The process was then transferred to the PE1O8 reactor. The thickness and doping uniformity of 200 mm epi-wafers is shown in Fig 4. Epilayers are grown uniformly along the substrate surface with a thickness and doping variation ( average) as low as and respectively.

Figure 4. Thickness and doping distribution of 200 mm epi-wafer processed in PE1O8 reactor

Figure 4. Figure 4. Thickness and doping distribution of 200 mm epi-wafer processed in PE1O8 reactor

To investigate the defect density of the epi-grown wafers candela is employed. As presented in Fig. 5 total defect density as low as and are achieved on 150 mm and 200 mm samples, respectively.

Accordingly, the Total Usable Area (TUA) after epitaxy is calculated and for 150 mm and 200 mm samples respectively. It worth to mention again that these results are achieved only after a few runs and further improvement is expect by fine tuning the process parameters.

Figure 5. Candela defect map of thick 200 mm (left) and 150 mm (right) epi-wafers grown by PE1O8

Figure 5. Figure 5. Candela defect map of thick 200 mm (left) and 150 mm (right) epi-wafers grown by PE1O8

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.146.pdf

The new designed PE1O8 hot-wall CVD reactor and its ability to perform uniform 4H-SiC epitaxy on 200 mm substrates is described in this paper. The preliminary results on 200 mm are very promising with a thickness variation as low as over the sample surface and doping performance with a variation as low as over the sample surface. The TUA after epitaxy is calculated to be and for 150 mm and 200 mm samples respectively, while an improvement is predicted in case of 200 mm TUA having higher substrate quality in future.
Considering that the results on 200 mm substrates reported here are based on a handful set of tests, we believe by fine-tuning the growth parameters, it is possible to further improve the results which are already close to the state of arts results achieved on 150 mm samples.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.146.pdf

This activity is a part of the REACTION project (grant number 783158). The authors thank all the REACTION project collaborators and in particular II-V Inc. for supplying 200 mm SiC wafers and STMicroelectronics for Candela measurements.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.146.pdf

Zhang, L., Yuan, X., Wu, X., Shi, C., Zhang, J. and Zhang, Y. Performance evaluation of highpower SiC MOSFET modules in comparison to Si IGBT modules. IEEE Transactions on Power Electronics, 34(2), pp.1181-1196 (2018).

Bhatnagar, M. & Baliga, B. J. Comparison of , and Si for power devices. IEEE Trans. Electron Devices 40, 645-655 (1993).

Shenai, K., Scott, R. S. & Baliga, B. J. Optimum semiconductors for high-power electronics. IEEE Trans. Electron Devices 36, 1811-1823 (1989).

Alves, L.F., Lefranc, P., Jeannin, P.O. and Sarrazin, B. Review on SiC-MOSFET devices and associated gate drivers. IEEE international conference on industrial technology (ICIT), pp. 824829 (2018).

Musolino, M., Xu, X., Wang, H., Rengarajan, V., Zwieback, I., Ruland, G., Crippa, D., Mauceri, M., Calabretta, M. and Messina, A. Paving the way toward the world's first 200 mm SiC pilot line. Materials Science in Semiconductor Processing, 135, p. 106088 (2021).

Information on .

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Chapter 2

Processing

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 155-159

doi: 10.4028/p-4cttw9

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-30

Revised:
2022-02-24

Accepted:
2022-02-24

Online:
2022-05-31

Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

The original version of this paper is available on https://www.scientific.net/MSF.1062.155.pdf

Dr. Diego Calvo Ruiz and Carmine Sileno

¹Meister Abrasives AG, Industriestrasse 10, 8450 Andelfingen, Switzerland

diego.calvoruiz@meister-abrasives.ch, carmine.sileno@meister-abrasives.ch

Keywords: grinding, polishing, thinning, vitrified, bonding

Abstract

The present paper shows a new fixed abrasive bond-grit formulation aimed for best-inclass, low-cost and high-quality finished SiC wafer surfaces. Grinding wheels manufactured with this technology can accomplish ultra-smooth and TTV surfaces due to their unique bonding structure and their tailored grit size. Additionally, SiC wafers ground with these wheels exhibit reduced sub-surface crystal damage, mirror-like polished surface and improved wafer geometry while both the grinding forces and the wheel wear are kept low.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.155.pdf

The obtention of high-quality finished surfaces in Silicon Carbide ( SiC ) wafer thinning is essential in the pursuit of mass production of novel power semiconductor devices [1]. State-of-the-art SiC wafers are pre-processed via several cycles of lapping or mechanical diamond polishing followed by Chemical Mechanical Polishing (CMP) [2], processes which entails many steps and high machining costs due to the associated slow material removal rate [3]. To enable a reduction of consumable costs, grinding with a consolidated diamond abrasive technology has been investigated as an alternative to lapping and diamond polish over the last years [4-5]. Thus, modern ultra-fine grinding wheel technologies have achieved sub-nm surface roughness (Ra) and sub- m Total Thickness Variation (TTV) values despite the well-known hardness, stiffness and strength of monocrystalline SiC [6-7].

Experimental Procedure

The original version of this paper is available on https://www.scientific.net/MSF.1062.155.pdf

In this study, numerous wafers were ground using standard backgrinding equipment. A representative close-up region from one of the grounded 6" SiC wafers is illustrated in Fig. 1. As it can be observed from the 3D analysis (Fig. 1c), the surface profile is extremely homogeneous and grinding lines are nearly prevented. This is confirmed with the subsequent area and surface roughness measurements shown in Table 1 and Table 2, respectively. The corresponding wafer exhibits an Arithmetic Mean Height (Sa) of 0.85 nm in combination with a Total Height (Rt) of 3.78 nm . Interestingly, a sub-nm Root Mean Square Deviation (Rq) value is obtained, which correlated with the expected high surface quality shown in Fig. 2. It should be noted that more wafer regions and extra SiC wafers were considered, and nearly identical results were achieved.

At the heart of Meister Abrasives' novel grinding technology, capable of producing SiC surfaces with the mentioned quality, is the proprietary bond-grit formulation. It features bonding structures, which are abrasive grains bond in a vitrified matrix system. With this approach, the same number of grains are active in the work zone. When material removal takes place on the substrate, new, sharp diamond grains are introduced by the matrix system. Meister Abrasive's bond-grit formulation offers several advantages over competing technologies. As the diamonds employed in the wheels are specifically selected to the grinding process applications, the benefits include enhanced cutting behaviour, excellent self-dressing behavior and improved cooling. By developing new bondmatrixes, specifically tailored for each grit size, Meister offers a single bond for each wheel technology, leading to reach longer lifetime and lower grinding forces.

Fig. 1. Selected region ( ) from our UF6 grounded SiC wafer: a) contour topographic analysis of top view; b) line profile of diagonal represented in a); c) 3D view of identical area; and (d) Atomic Force Microscopy (AFM) scan of a by area (note the Z-scale is 3.16 nm ).

Fig. 1. Selected region ( ) from our UF6 grounded SiC wafer: a) contour topographic analysis of top view; b) line profile of diagonal represented in a); c) 3D view of identical area; and (d) Atomic Force Microscopy (AFM) scan of a by area (note the Z-scale is 3.16 nm ).

Table 1. Area roughness parameter measurements of Fig. 1 obtained with Filmetrics Profilm3D via WLI (White Light Interferometry).

Parameter | ISO 4287 Amplitude (nm)
Peak Height (Sp) | 4.56
Valley Depth (Sv) | 7.36
Maximum Peak to Valley Depth (Sz) | 11.91
Arithmetic Mean Height (Sa) | 0.85
Root Mean Square Height (Sq) | 1.03
Skewness (Ssk) | -0.07
Kurtosis (Sku) | 2.75

Table 2. Line roughness parameter measurements of Fig. 1 obtained with Filmetrics Profilm3D via WLI.

Parameter | ISO 4287 Amplitude (nm)
Maximum Peak Height (Rp) | 1.56
Maximum Valley Depth (Rv) | 1.46
Maximum Height (Rz) | 3.02
Total Height (Rt) | 3.78
Arithmetic Mean Deviation (Ra) | 0.55
Root Mean Square Deviation (Rq) | 0.66
Skewness (Rsk) | 0.13
Kurtosis (Rku) | 2.46

A key feature of Meister unique bonding technology is its highly porous open structure (see Fig. 3, which illustrates that the porosity). This enables low force grinding processes that besides decreasing surface roughness, improve wafer geometry, in terms of total thickness variation (TTV), bow and warpage. Using Meister Abrasives' solutions, grinding process engineers can produce wafers with a TTV below while keeping the grinding forces very low and steady. This smooths processing conditions, helps to avoid production breaks associated with overcurrent warnings.

Fig. 2. Representative picture of UF6-grounded SiC wafer.

Fig. 2. Representative picture of UF6-grounded SiC wafer.

Fig. 3. Representative ultra-fine wheel with a porous structure. This novel material, exhibiting a porosity can be seen by the naked eye, maintains enough bonding to grind SiC.

Fig. 3. Representative ultra-fine wheel with a porous structure. This novel material, exhibiting a porosity can be seen by the naked eye, maintains enough bonding to grind SiC.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.155.pdf

The novel grinding wheel technology presented in this paper can help prime wafer and device manufacturers shorten wafer preparation steps to the minimum. Thanks to the ultra-smooth surface profile achieved with this method, diamond slurry costs can be therefore avoided, CMP slurry costs can be hugely reduced, and throughput can be drastically increased, and process time can be significantly reduced, as illustrated in Fig. 4. Furthermore, the pioneering nature of the bonding technology enables manufacturers to use low force grinding processes that improves wafer geometry (TTV, Bow and Warp) and decrease surface roughness even further.

Fig. 4. Comparison of standard lapping processes vs Meister course and ultra-fine grinding technologies.

Fig. 4. Comparison of standard lapping processes vs Meister course and ultra-fine grinding technologies.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.155.pdf

A. R. Powell, J. J. Sumakeris, Y. Khlebnikov, M. J. Paisley, R.T. Leonard, E. Deyneka, S. Gangwal, J. Ambati, V. Tsevtkov, J. Seaman, A. McClure, C. Horton, O. Kramarenko, V. Sakhalkar, M. O'Loughlin, A. A. Burk, J. Q. Guo, M. Dudley and E. Balkas, Materials Science Forum 858 (2016) 5-10.

Y. Ling, SIMTech Technical Report PT/01/001/PM (2001).

H. Feng-Wei, G. Dong-Ming, K.Ren-Ke and F. Guang, Transactions of Nonferrous Metals Society China 22 (2012) 3027-3033.

J. Pan, X. Zhang, Q, Yan and S. Chen, The International Journal of Advanced Manufacturing Technology 89 (2017) 619-627.

Y. Yiqing, H. Zhongwei, W. Wenshan, Z. Huan, L. Jing and X. Xipeng, The International Journal of Advanced Manufacturing Technology 108 (2020) 997-1006.

H. Kasuga, H. Ohmori, T. Mishima, Y. Watanabe and W. Lin, The Journal of Ceramic Process Research 10(3) (2009) 351-354.

K. Yamaguchi, M. Touge, T. Nakano and J. Watanabe, in Proceedings of the International Symposium on Advances in Abrasive Technology, edited by Advanced Materials Research (Trans Tech Publications), 2009, pp. 282-287.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 160-164

doi: 10.4028/p-u08hm8

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-06

Revised:
2022-03-01

Accepted:
2022-03-02

Online:
2022-05-31

Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

P. Fiorenza , C. Bongiorno , A. Messina , M. Saggio , F. Giannazzo , F. Roccaforte

¹CNR-IMM, Strada VIII 5 95121, Catania, Italy

STMicroelectronics Stradale Primosole 50 95121, Catania, Italy

patrick.fiorenza@imm.cnr.it, corrado.bongiorno@imm.cnr.it, angelo.messina@st.com, mario.saggio@st.com,

*corresponding author

Abstract

Silicon dioxide ( ) layers deposited on and subjected to different post deposition annealing (PDA) in NO and were studied to identify the key factors influencing the channel mobility and threshold voltage stability in lateral implanted MOSFETs. Cyclic gate bias stress measurements allowed to separate the contributions of interface states ( ) and near interface oxide traps (NIOTs) in the two oxides. The reduction of these traps in the NO annealed sample is due to the lower amounts of sub-stoichiometric silicon oxide ( ) and carbon-related defects at the interface, as could be demonstrated by Electron Energy Loss Spectroscopy. The experimental results indicate that limiting the SiC re-oxidation during post-deposition annealing in MOSFET technology is a key factor to improve the mobility and threshold voltage stability.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

The performances of MOSFETs are strongly influenced by the processing of the SiC interface [1,2]. In particular, threshold voltage ( ) instability phenomena [3,4] and poor field effect channel mobility ( ) [5,6] often occur in these devices and can be partially mitigated by post oxidation annealings (POA) or post oxide deposition annealings (PDAs) [5]. Hence, a great attention of the scientific community is devoted to optimize the interface by POAs or PDAs. However, while the introduction of Nitrogen or others atomic species can produce some benefits in the interfacial carrier transport, they can introduce additional trapping states, which are detrimental for the stability [7]. Hence, the introduction of such undesired traps at the interface should be limited.

On the other hand, it is mandatory to develop reliable, fast and accurate determination methods, able to minimize the amount of undetected traps during the investigation [8].

In this paper, interfaces on implanted p-type , formed with deposited subjected to different PDAs in NO or , were investigated by cyclic gate stress measurements to determine the amount of trapped charges. Furthermore, nanoscale structural/chemical analyses allowed to identify the key factors influencing the channel mobility and stability in lateral MOSFETs. In particular, a correlation between the chemical disorder at the deposited interface after the PDAs and the electrical properties of the lateral MOSFETs is presented.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

In this paper, different lateral MOSFETs were fabricated on 4 -off-axis n-type ( 0001 ) 4H-SiC epitaxial layers ( ), with a p -type Al-implanted body region ( ). The gate oxide was a 40 nm thick deposited layer [9]. Different PDAs were performed in a horizontal furnace in a sub-atmospheric pressure regime at in NO or [10], in order to investigate the electrical and chemical impact on the interface.

The MOSFETs were characterized by means of current voltage ( ) transfer characteristics measured in a CASCADE Microtech probe station, using a Keysight B1505A parameter analyzer. The MOSFETs chemistry interface was investigated by Scanning Transmission Electron Microscopy (STEM) analyses (JEOL ARM200CF at a primary beam energy of 200 keV ) and electron energy loss spectroscopy (EELS).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

The standard procedure to determine the threshold voltage in lateral MOSFETs uses the linear fit of . However, this method requires the gate bias sweep and can be not sensitive to an eventual variation of the charge state in the insulator during the measurement. Hence, it is important to minimize the system perturbation induced by the measurement itself. Recently, we have presented a method to measure the variation by means of a single point measurement, avoiding relaxing effects on the majority of trapped charge [8]. The whole semiconductor bandgap trapping states were probed by varying the gate bias stress from inversion to accumulation and backward followed by a single point measurement at .

Fig. 1a describes schematically the cyclic gate bias sequence used to probe the whole bandgap and to probe the variations. Fig. 1 b shows how the measured at varied upon the cyclic gate bias stress is applied. The variation can be correlated to the variation.

The variation occurring from the minimum and maximum stress values can be associated to the total amount of electrons that can be trapped at the interface traps [8]. On the other hand, closing the cyclic gate bias sequence it is possible to notice a residual variation at . This can be associated to the remaining amount of charge at the near interface oxide traps (NIOTs) [8]. Fig. 1b shows the values measured at for each stress point according to Fig. 1a on the sample after a PDA in . Those single point measurements can converted to threshold voltage variation . If this variation is monitored at different temperatures (e.g., from up to ), it is possible to monitor the amount of detectable and NIOTs in the two systems.

Fig. 1. (a) Schematic illustration of the cycling gate bias stress sequence. (b) Experimental single point measured during the cyclic gate bias stress for a fixed time of 2 s used to extrapolate the variation.

Fig. 1. (a) Schematic illustration of the cycling gate bias stress sequence. (b) Experimental single point measured during the cyclic gate bias stress for a fixed time of 2 s used to extrapolate the variation.

By repeating the experimental procedure on the samples under investigation, it is possible to estimate the total amount of traps at the interface and in the oxide NIOTs. In particular, the amount of detected decreases with the increasing temperature (from ), while the detected NIOTs are nearly constant in the investigated temperature range (about ) [8,11]. This behavior can be associated to a tunneling mechanism from the semiconductor into a trap located into the insulator [11-13]. On the other hand, it has been demonstrated that the main variation is due to the and their charge retention capability has an activation energy of , which in turn can be associated to the intrinsic interface state defects of the system [13].

The PDAs performed in NO or resulted into a different MOSFET electrical behavior. For example, the maximum field effect mobility value after annealing in was more than twice larger than the value measured in the sample annealed in . Moreover, the different PDAs performed in NO or produced different variation under the cyclic bias stress. As described previously, from the cyclic bias stress it is possible to extract both the and the NIOTs. Hence, the relative amount of the and NIOTs can be varied by a fine tuning of the PDA. As an example a PDA in NO reduced both trapping mechanisms reducing the instability (and increasing the field effect mobility). In particular, Fig. 2a shows the comparison between the variation during the cyclic stress obtained on the samples after PDAs in NO and respectively. As can be seen in the highlighted region of Fig. 2a, the PDA in NO demonstrates a reduction of both the and NIOTs with respect of the PDA in [14]. Evidently, the two interfaces produced with the two different PDAs are different. Such difference has to be pursued at the intimate chemical nature of the interface.

Fig. 2b shows the comparison of the EELS profile collected on both PDA SiO2/ interfaces, demonstrating that the improved and NIOTs in the NO sample can be associated to a reduced amount of and C -based defects [14].

Fig. 2. (a) variation during the cyclic gate bias stress on and NO samples. variation between and +30 V corresponds to the total and the residual variation at V corresponds to theNIOTs. (b) EELS profiles of and carbon for PDA in and NO.

Fig. 2. (a) variation during the cyclic gate bias stress on and NO samples. variation between and +30 V corresponds to the total and the residual variation at V corresponds to theNIOTs. (b) EELS profiles of and carbon for PDA in and NO.

Fig. 2b shows the carbon and EELS profiles collected on both and NO samples. The PDAs signals are compared to those collected on the as deposited reference sample. The as deposited interface shows carbon and profiles that represent the steepest transition between the SiC substrate and the insulator. As can be noticed, both PDAs produced a broader interface element transition compared to the as deposited sample. This progressive change in the and carbon profiles across the interface are due to the slight re-oxidation induced by the PDA. These results allowed to draw the correlation between the electrical properties and the chemical order at the interface. In particular, it is worth noticing that the smaller amount of interface traps in
the sample annealed in NO can be associated to a thinner and steeper sub-stoichiometric layer with respect to the case. Furthermore, both samples show similar carbon. In particular, the carbon profiles show a decreasing tail within the oxide. The carbon tails extend from the SiC interface into the oxide for about 1.2 nm and 0.9 nm for the sample annealed in in NO , respectively. It has to be emphasized that in Fig. 2b only the carbon profile of the sample annealed in is shown for the sake of clarity. These carbon-related defects within the insulator can be associated to the residual NIOTs detected by the cyclic gate bias stress procedure.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

In this paper, a combined electrical/chemical study of deposited interfaces on implanted p-type , subjected to different PDAs in NO or is presented. The lateral MOSFETs were investigated by cyclic gate stress measurements and nanoscale structural/chemical analyses. This basic study allowed to identify the key factors influencing the channel mobility and stability in lateral MOSFETs. The results demonstrated that the threshold voltage instability of 4H-SiC MOSFETs, associated to different trapping mechanisms, is directly related to the interface chemistry and can be mitigated by an accurate control of the nitridation conditions of deposited oxides. In particular, interface traps can be associated to a sub-stoichiometric layer and near interface oxide traps can be associated to carbon tails extending from the SiC interface into the oxide due to the interface re-oxidation occurred during the PDAs.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

This work was carried out in the framework of the ECSEL JU project REACTION (first and euRopEAn siC eigTh Inches pilOt liNe), grant agreement no. 783158

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.160.pdf

F. Roccaforte, P. Fiorenza, G. Greco, R. Lo Nigro, F. Giannazzo, F. Iucolano, M. Saggio, Microelectronics Engineering 187, 66 (2018)

T. Kimoto and J. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications (JohnWiley & Sons, Singapore, 2014).

H. Yano, N. Kanafuji, A. Osawa, T. Hatayama, T. Fuyuki, IEEE Trans. Electron Dev. 62, 324 (2015)

A.J. Lelis, R. Green, D.B. Habersat, M. El, IEEE Trans. Electron Dev. 62, 316 (2015)

M. Cabello, V. Soler, G. Rius, J. Montserrat, J. Rebollo, P. Godignon Mater. Sci. Semicon. Proc. 78, 22 (2018).

P. Fiorenza, F. Giannazzo, A. Frazzetto, F. Roccaforte, J. Appl. Phys. 112, 084501 (2012).

Keita Tachiki, Mitsuaki Kaneko, Tsunenobu Kimoto; Applied Physics Express 14, 031001 (2021)

P Fiorenza, F. Giannazzo, S. Cascino, M. Saggio, F. Roccaforte. Appl. Phys. Lett. 117, 103502 (2020)

A. Frazzetto F. Giannazzo, P. Fiorenza, V. Raineri, F. Roccaforte, Appl. Phys. Lett. 99, 072117 (2011)

A. Severino, N. Piluso, M.A. Di Stefano, F. Cordiano, M. Camalleri, G. Arena, Mater. Sci. Forum 963 456-459 (2019)

A. J. Lelis, D. Habersat, R. Green, A. Ogunniyi, M. Gurfinkel, J. Suehle, and N. Goldsman, IEEE Trans. Electron Devices 55, 1835 (2008).

V. V. Afanas'ev, A. Stesmans, M. Bassler, G. Pensl, and M. J. Schulz, Appl. Phys. Lett. 76, 336 (2000).

P. Fiorenza, A. La Magna, M. Vivona, F. Roccaforte, Appl. Phys. Lett. 109, 012102 (2016)

P. Fiorenza, C. Bongiorno, F. Giannazzo, M. S. Alessandrino, A. Messina, M. Saggio, F. Roccaforte, Appl. Surf. Sci. 557149752 (2021)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 165-169

doi: 10.4028/p-599hof

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-12

Revised:
2022-03-01

Accepted:
2022-03-01

Online:
2022-05-31

Impact of Dislocation on Warpage of Thinned -SiC Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1062.165.pdf

Brunella Cafra , Ruggero Anzalone , Andrea Severino

ST Microelectronics, stradale primosole, 5095121 Catania, Italy

brunella.cafra@st.com, ruggero.anzalone@st.com, andrea.severino@st.com

Abstract

In this work the relationship between changes in wafer center bow after thinning process and the wafer morphology has been shown. KOH wet etching allowed the observation and counting of dislocations in 4H-SiC substrate. In deep a correspondence between changes in wafer center bow and the dislocations density of the SiC substrate has been observed. By using a counting software, a relationship between the basal plane dislocations and center bow has also been observed.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.165.pdf

Wide band-gap semiconductor SiC material can overcome the limitations of Si for high voltage/high power devices due to its high electron mobility, high electron saturation drift velocity and high thermal conductivity. SiC based devices such as diodes and power MOSFET are nowadays a reality in the semiconductor industry and their electrical performances are quite comparable, if not superior for some aspects, with the Si counterpart. For semiconductor application wafer thinning plays an important role on device performances guaranteeing for example strong reduction on ONResistance (Ron) on power devices. The thinning process, having SiC material low fracture toughness and extreme brittleness, has to be properly performed in order to achieve high quality and crack-free substrate. Moreover, during the grinding process, the part of the SiC substrate directly in contact with the grinding wheel damages, with cracks and amorphous regions clearly visible by morphological analysis. This part of the substrate can be considered as a film, whose thickness depends on the size of grinding wheel [ ], which causes variations on wafer bowing, introducing a compressive stress on the wafer surface .

In this work we will focus on the study of relationship between SiC wafers which undergoes a thinning process and the defect density (dislocation mainly) [4-5]. Variations on wafer center bow (C-bow) for three different SiC substrate properly selected for defect density has been shown as a function of the defect density. A series of analyses have been carried out to investigate the morphological changes and defectivity of the SiC wafer surface.

Experimental Setup

The original version of this paper is available on https://www.scientific.net/MSF.1062.165.pdf

Commercially available substrate with off-angle and thickness have been used in this experiment. Wafers have been thinned down to by performing a mechanical grinding on the C -faces using a conventional in-feed grinding process. Warpage measurements have been performed by E+H MX 102-204-RA-2C tool [6]. Sample surface roughness (Sq) and the peak to valley height line parameter ( Rt ) have been measured by optical profilometry analysis (MicroXaM). Dislocations have been identified by KOH etching. The etching has been performed in molten KOH inside a nickel crucible at a temperature of for a period of . Major dislocations in SiC substrates include threading screw dislocations (TSD), threading edge dislocations (TED), and basal-plane dislocations (BPD). EPD (Etch Pit Density) and BPD etch pits densities have been calculated based on the observation under fully automated ( and Z ) optical microscopy (nSPEC by Nanotronics). With a powerful software for the image analysis coupled with highresolution microscope, a 6 inches wafer map with detailed dislocations count and classification has been obtained [7].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.165.pdf

Figure 1 shows large area ( ) optical profilometer analyses performed on SiC Cface before and after grinding process. As received wafers show a quite flat face with a surface roughness ( Sq ) of about 0.6 nm and a peak to valley height ( Rt ) of about 3 nm (fig. 1a)). As a consequence of the thinning process the shape of the surface remarkably changes showing grinding wheel marks, a surface roughness (Sq) of about 4.6 nm and a maximum height of the profile (Rt) of about 29 nm (fig. 1b)). The corresponding morphology in section, investigated by TEM analysis (images not shown), reveals a damaged region with lateral and median cracks extending for a depth of about 600 nm . This damaged region is an area with high density dislocations and large strain [8,9].

Figure 1. Optical profilometer images of the as received SiC C - face surface a) and grinded surface b)

Figure 1. Figure 1. Optical profilometer images of the as received SiC C - face surface a) and grinded surface b)

Despite the same grinding process has been performed on all SiC wafers under investigation, different Cbow values have been measured as it is possible to see from data collected in fig. 2 where Cbow values normalized (N Cbow) to the lowest one, obtained for wafer 1, have been collected. It is to note an increasing by a factor of about 1.6 and 2.4 in Cbow values respectively for wafer 2 and wafer 3. The differences found cannot be accounted for in terms of grinding process variation since the same grinding process has been performed on all wafers and we wonder if a correlation exists among variations in wafer Cbow and wafer defect density (mainly dislocation).

Figure 2. Normalized Cbow (N Cbow) values for wafers under investigation. The Cbow value increase by a factor of 1.6 and 2.4 on wafer 2 and 3 respectively.

Figure 2. Figure 2. Normalized Cbow (N Cbow) values for wafers under investigation. The Cbow value increase by a factor of 1.6 and 2.4 on wafer 2 and 3 respectively.

Fig. 3 shows the whole defect count maps of wafers 1 and wafer 3 having respectively the lower and higher value of Cbow. With the nspec tool, the high-resolution map (about 14.000 tiles) allows observing with high level of detail the entire wafer, counting the whole Etch Pits Density (EPD) with the possibility to distinguish within all the pits the different type of dislocations (BPD, TSD and TED).

Figure 3. High resolution whole wafer map of the 6 inch. samples with the higher value of dislocation density (left) and lower valuer (right). The EPD density is pits for sample 1 (left) and pits for sample 3 (right). The edge exclusion is 2 mm for both maps.

Figure 3. Figure 3. High resolution whole wafer map of the 6 inch. samples with the higher value of dislocation density (left) and lower valuer (right). The EPD density is pits for sample 1 (left) and pits for sample 3 (right). The edge exclusion is 2 mm for both maps.

The EPD density is pits for sample 1 and pits for sample 3. A deep analysis allowed a better classification of dislocation type and the same trend was observed for the basal plane dislocation (BPD) that are between 1900 and 2000 pits for sample 1 and less than 200 pits for sample 3. This means that in sample 1 over than the pits are made by BPD.

In figure 4 the relationship between the Cbow and the etch pits density (EPD) has been reported. From the figure the correspondence between the high value of Cbow and the lower value of dislocation density is clearly observable. The wafer that exhibits the highest wafer bowing (wafer 3) shows also the lowest EPD count.

For energetic reason the defect (mainly dislocation in SiC substrate was observed) is a preferential way to release the internal stress of the wafer after the growth. For this reason the highly defect sample correspond to the lower bended samples and vice versa.

Figure 4. Center bow (Cbow) as a function of Etch pit density (EPD). All the three wafers have been measured after the same thinning process.

Figure 4. Figure 4. Center bow (Cbow) as a function of Etch pit density (EPD). All the three wafers have been measured after the same thinning process.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.165.pdf

In this work, a different behaviour in terms of wafer Cbow after the thinning process has been reported for the three wafers under investigation. Since the same thinning process has been performed on the three wafers, we investigated whether this finding can be ascribed to different characteristics of the wafers. Indeed we have observed that the three wafers show differences in terms of dislocation density (EPD) with the highest values obtained in correspondence of the lowest wafer bowing measured. In details, a difference was observed also for basal plane dislocation density that is higher in the sample with lower center bow.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.165.pdf

J. A. Randi, J. C. Lambropoulos and S. D. Jacobs, Applied Optics, 44 (12), 2241-2249 (2008)

R.C. Teixeira, K. De Munck, P. De Moor, K. Baert, B. Swinnen, C. Van Hoof and A. Knuettel, J: Int. Circ. And Sys. 2008, V3 (2) 83-89.

M. Ohring, material Science of thin film, 2nd ed. (academic press, 2002).

T. Ailihumaer, H. Peng, B. Raghothamachar, M. Dudley, G. Chung, I. Manning, and E. Sanchez, Materials Science Forum, 1662-9752, Vol. 1004, pp 393-400

T. Ailihumaer, H. Peng, B. Raghothamachar, M. Dudley, G. Chung, I. Manning, And E. Sanchez, Journal Of Electronic Materials, Vol. 49, No. 6, 2020.

MX204-8-21-RA-2C user's guide

R. Anzalone, N. Piluso, A. Severino, S. Lorenti, G. Arena and S. Coffa Materials Science Forum 1662-9752, Vol. 963, pp 276-279

B Zhang, T Histoshi, Y Masanori, . Journal of Materials Science, 1988, 23(9): 3214-3224.

J G Sun, M Shirber, W A Ellingson. Laser-based optical scattering detection of surface and subsurface defects in machined Si3N4 components. John Wiley & Sons, Inc., 1997: 273-280.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 170-174

doi: 10.4028/p-wn4zya

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-24

Accepted:
2022-02-24

Online:
2022-05-31

Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

S. Mathew , S.P. Lebedev , A.A. Lebedev , B. Hähnlein , J. Stauffenberg , E. Manske and J. Pezoldt

FG Nanotechnologie, Institute für Mikro- und Nanoelektronik and Institut für Mikro- und Nanotechnologien MacroNano , PF 100565, 98684 Ilmenau, Germany

Ioffe Physical Technical Institute, Russian Academy of Sciences, St. Petersburg, 194021 Russia

FG Technische Physik I, Institut für Physik and Institut für Mikro- und Nanotechnologien MacroNano , TU Ilmenau, Postfach 100565, 98684 Ilmenau, Germany

FG Fertigungs- und Präzisionsmesstechnik, Institut für Prozessmess- und Sensortechnik and Institut für Mikro- und Nanotechnologien MacroNano , PF 100565, 98684 Ilmenau, Germany

sobin.mathew@tu-ilmenau.de, lebedev.sergey@mail.ioffe.ru, shura.lebe@mail.ioffe.ru, bernd.haehnlein@tu-ilmenau.de, jaqueline.stauffenberg@tu-ilmenau, eberhard.manske@tu-ilmenau.de, joerg.pezoldt@tu-ilmenau.de

Keywords: epitaxial graphene, silicon carbide, nano-gratings.

Abstract

A technical methodology of fabrication of hierarchically scaled multitude graphene nano gratings with varying pitches ranging from the micrometer down to sub 40 nm scale is proposed. These are combined with sub 10 nm step heights on 4 H and 6 H semi-insulating SiC for length scale measurements is proposed. The nano gratings were fabricated using electron-beam lithography combined with dry etching of graphene, incorporating a standard semiconductor processing technology. A scientific evaluation of critical dimension, etching step heights, and surface characterization of graphene nano grating on both polytypes were compared and evaluated.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

SiC has attracted different perspectives of scientific applications owing to its predominant physical properties. In particular, the large bandgap, low intrinsic carrier concentration, high breakdown field strength, and numerous polytypes make SiC, a promising candidate for high performance applications and microelectromechanical systems . However, for many applications, understanding and revealing the impact of substrate surface morphology and surface instabilities in SiC like nanofaceting, step bunching, and step meandering is crucial [3]. Understanding these nanoscale interface interactions requires a profound knowledge of the material at the atomic scale. It further demands the necessity of advanced characterization tools to generate new multidisciplinary knowledge about nanoscale phenomena. Consequently, an extensive improvement of available metrology methods and technologies for subatomic measurement for many ambitious research approaches at the atomic level is necessary.

Currently, laser interferometers are often used in high-resolution measurement applications. Based on the suitable laser scale today, a resolution of 5 pm can be achieved [4]. But these techniques confront many technological complexities due to the ever-increasing nonlinear problems in fringe interpolation [5]. However, the feasibility of using atomic lattices as the length scale standard was first demonstrated by Aketagawa on highly oriented pyrolytic graphite (HOPG) in 2007 [6] and paved a new basis for forthcoming research methods. Our aim is to apply this idea on epitaxial graphene to demonstrate atomic lattices with a perfect crystallographic structure for new subatomic measurement techniques. Using standard planar semiconductor processing technology, a hierarchically scaled multitude grating structure is developed and demonstrated, i.e., a diffraction grating consisting of different pitches with an atomic-scale resolution. Furthermore, these designed grating structures can be analysed with the nanofabrication machine (NFM-100). This machine is equipped with a tip-based
measuring system and has a positioning range of 100 mm in diameter with sub-nanometre precision [7]. However, it is crucial to make an appropriate material choice for this approach. Since this method is dependent on the lattice parameters of the material, a material that can withstand and make weak interaction with the environment in terms of oxidation is needed.

Considering the prerequisite properties of the material and feasibility of surface structuring with possible technologies, here we choose graphene grown on semi-insulating SiC for the study. We propose a design combining diffraction gratings consisting of different ridge widths and pitches ranging from the micro- to the sub- 40 nm scale. Moreover, here we try to explore and investigate the possibility of understanding the surface morphology of graphene formed on 6 H and 4 H SiC polytypes and their inhomogeneity in interface roughness for length scale measurement purposes.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

Epitaxial graphene was grown on the Si -face of on-axis semi-insulating and . The graphitization process was carried out in a high-temperature furnace between and in an argon atmosphere at atmospheric pressure using the two-step methods [8-10]. For structuring and fabrication of graphene gratings, the samples were cleaned and spin-coated at 4000 rpm with a highresolution negative resist, hydrogen-silsesquioxane (HSQ) (XR-1541-4%) and immediately baked on a hot plate at . The final resist thickness was about 30 nm . For high-resolution patterning and fabrication of nano gratings on graphene, we employed electron beam lithography at 20 kV and aperture in a Raith 150 system [11]. Subsequently, the exposed structures were developed with a twostep process in a solution of (DI: TMAH) and (DI: TMAH) for 1 min at room temperature. The samples were etched using an inductively coupled plasma etching technique with oxygen for 30 s. After etching, the resist was removed by buffered oxide etching (BOE) for 1 min and rinsed in DI for another 1 min . Evaluation and characterization of critical dimensions and etching step heights of the structured gratings were carried out using scanning electron microscopy (SEM) and atomic force microscopy (AFM) in non-contact mode. Here we employed AFM tips with a diameter below 20 nm .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

The AFM images in Fig.1(a) and (b) illustrate the surface morphology and profile obtained from the pristine epitaxial graphene grown on the Si -face of semi-insulating 6 H and 4 H SiC polytypes. The

Fig. 1. Surface topography AFM images of bare graphene samples on (a) 6 H and (b) with their respective height profile.

Fig. 1. Surface topography AFM images of bare graphene samples on (a) 6 H and (b) with their respective height profile.

graphene formed on the surface is provided parallelly placed macro steps structures. During the graphitization process, these macro step like terraces are formed on the surface of SiC and distributed along the step edges of the SiC substrate due to the step bunching process [12]. Moreover, terraces formed on 6H-SiC periodically separated with step edges with an average width of 500 nm . The micro-steps formed on the step edges have an average height of 1.5 nm . Interestingly, the macro steps are evenly aligned, and their step edges are moderately straight. Furthermore, these step edges act as nucleation centres for graphene formation. As the Si and C edge atoms are weakly bonded, a variation of the graphene layer thickness in this region often occurs [13]. The average root mean square (RMS) roughness obtained from the graphene surface on the terrace is 0.9 nm . Besides the 6 H -SiC, the
surface morphology of graphene formed on was comparatively different with a combination of larger and smaller terraces. Fig 1 (b). shows the topography of graphene surface and its profile obtained from the scanned direction. The presence of wide and narrow terraces indicates the inhomogeneity in graphene layer thickness. According to the profile the formed terraces are from to wide. The height of the terrace steps varies between 3 and 6 nm . The (RMS)

Fig. 2. AFM image of graphene line gratings and their surface profile obtained from both SiC polytypes (a) 250 nm pitch graphene line gratings on and (b) Graphene line gratings with 250 nm pitch on .

Fig. 2. AFM image of graphene line gratings and their surface profile obtained from both SiC polytypes (a) 250 nm pitch graphene line gratings on and (b) Graphene line gratings with 250 nm pitch on .

roughness obtained from the graphene surface on the terrace is 0.6 nm . Furthermore, since these macro step like structures alter the homogeneity of the graphene surface, it is necessary to obtain samples with minimum surface instabilities for grating fabrication. Consequently, these imperfections must be considered during the fabrication of gratings. Fig 2. (a) and (b) shows AFM surface topology images of graphene line gratings obtained from both polytypes and their surface profiles. It is worth noting that the surface profile obtained from the line gratings on shows a homogenous pattern. The step heights and pitches obtained are comparably equal and uniform. And this behaviour is evident in all other structures with different pitch sizes of the graphene gratings obtained from . Since the sample has homogenous morphology with evenly equal terraces and step-edges, the gratings formed on the are similar. Apart from this, the graphene line gratings obtained from show an inhomogeneity in step heights. This irregularity in the graphene grating structure is predominantly visible in the profile line scan obtained from the terrace region and caused by the underlying terrace edges.

Additionally, it further contributes to the distinct line width and causes instability and irregular construction of gratings and surface profile. The graphene grating line widths were obtained for a constant exposure dose of ( ) with different pitches.

Fig. 3. (a) shows the dependency of the structured graphene line width of graphene gratings obtained after the etching process in semi-insulating and substrates, respectively and (b) dependency of the etching depth of graphene gratings

Fig. 3. (a) shows the dependency of the structured graphene line width of graphene gratings obtained after the etching process in semi-insulating and substrates, respectively and (b) dependency of the etching depth of graphene gratings

We estimated the critical dimension of the line gratings by analysing the grayscale intensity profile of the SEM image according to the methodology developed in [14]. The dependency of measured line widths of graphene gratings after etching is illustrated in Fig 3. (a). The line widths are increasing with pitch size independent of substrate polytype. The persistent charge accumulated in the semiinsulating SiC substrate might explain this unexpected behaviour. Furthermore, the substrate charging and persistent residual charges while examining the gratings on semi-insulating substrates also influence the line widths [11]. Moreover, the presence of large terraces of 4 H SiC surfaces further alters the charging of the semi-insulating substrate. Therefore, backscattered electrons lead to a dose variation in the resist and consequently to a variation of the line width. The narrow linewidths obtained for lower pitches in 4 H SiC further support the interpretation. Interestingly, the average line width for the same pitch on is larger than the line widths on , supporting the interpretation of the line width dependence on the persistent charge accumulated during the electron beam exposure due to the lower bandgap of . However, we could also observe larger line widths for lower pitches in , and this might be originating due to the intra and inter proximity effects during the electron beam exposure [15,16]. Importantly, the polytype structure, the polarity and the misorientation affects the step bunching [17]. Due to the higher repulsive force between steps on 6 H surfaces compared to 4 H the 6 H surface is more stable against step height fluctuations and step bunching [17]. This might explain the observed formation of large terraces and large step heights in the 4 H case. As a result the graphene gratings formed on both polytypes have distinct structural variations affecting the critical dimension.

We further evaluated the dependency of etch depth on the line density (pitch) of graphene line gratings obtained from both polytypes. Fig. 3(b) shows the etch depth obtained from the AFM measurements. The etching depths obtained from different gratings with varying pitches at constant exposure doses are additionally shown. The etching depths obtained from both 6 H and show a similar behaviour. Considering the etch depth profiles obtained from both samples, we could observe a contracting behaviour with decreasing pitch size. This decreasing pattern in the etching depth is due to the micro loading effect [18, 19], which reduces the etch rate along with diminishing opening dimension due to transport limitations. Furthermore, the average root mean square (RMS) roughness obtained from the grating surface of is less ( 0.09 nm ) than the RMS value obtained for . However, in 6H-SiC, the surface waviness and roughness obtained from beneath the graphene gratings are minimized. The roughness along the graphene lines is comparable for both polytypes and has an average value of 0.06 nm .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

A multitude of grating designs consisting of gratings with different pitches ranging from the micrometre down to sub 40 nm scale combined with sub 10 nm step heights on 4 H and 6 H semi-insulating SiC for length scale measurements has been demonstrated. The gratings obtained on are preferable due to the absence of step bunching at the graphene formation conditions studied. So, the graphene formation conditions must be chosen in such a way that step bunching is suppressed.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

The authors acknowledge the support of this research by the program of the Carl-Zeiss-Stiftung program "Durchbrüche" by the project "MemWerk" under contract P2018-01-002, DAAD under grant 57435564 and TU Ilmenau by the project "Vernetzung der Kompetenzen".

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The original version of this paper is available on https://www.scientific.net/MSF.1062.170.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 175-179

doi: 10.4028/p-wkn17q

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-24

Accepted:
2022-02-24

Online:
2022-05-31

Polish Scratch Simulation vs. Polish Tool Type

The original version of this paper is available on https://www.scientific.net/MSF.1062.175.pdf

Kevin Moeggenborg , Meongkeun Ju

SK siltron css

Mile Road, Auburn, MI 48611, USA

kevin.moeggenborg@sksiltron.com

mk.ju@sksiltron.com

Keywords: silicon carbide, polish, scratch, model, defect, wafer

Abstract

Wafer scratching from handling and processing can impact the performance of devices grown on a substrate. Knowledge of process conditions and modeling of scratches on wafers can be used to elucidate the root cause of scratches so that they can be eliminated.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.175.pdf

Semiconductor wafers for epitaxy and device manufacture are required to be flat and defect-free within tight manufacturing tolerances. The negative impacts of surface damage on device manufacture are well known . Wafer processing from a wire sawn wafer may include multiple grinding, lapping, and polishing steps. Ideally each step improves the surface quality of the wafer from the previous processing step.

Of particular concern for a finished wafer is the presence of remnant scratches on the surface. Such scratches can retain residual contamination from processing and can lead to killer defects in initial epitaxy layers. The final CMP (Chemical Mechanical Polishing) step is intended to remove all residual scratching from prior processing steps without creating new scratches [4]. One potential scratch source after CMP is polish removal that was insufficient to eliminate prior scratching. Contaminant particles in the CMP process, potentially introduced by insufficiently cleaned wafers, can also cause random scratches [5]. Finally, the wafer itself can be a source of scratches. Chips of material, usually separated from wafer edges, can cause singular scratches, or become embedded in the polishing pad to cause multiple scratches. In the case of a batch polisher a single such particle can scratch multiple wafers.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.175.pdf

Modeling of scratch patterns from batch and single wafer polish processes was performed using Visual Studio C++ and Microsoft Excel programs. The geometry of the system for a single wafer polisher, is shown in Fig. 1. For the model, the wafer head is considered fixed in space at coordinates and rotates through angle in unit time. Since the head is rotating, its coordinates also rotate as shown. The scratch source p is fixed on the pad at radius R from the center and rotates through angle as a function of time. With each revolution of the pad, the scratch source moves across the wafer surface describing an arc scratch. Modeling for a batch wafer polisher is the same as for the single wafer polisher except that the coordinate of the wafer has eccentricity from center of the head.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.175.pdf

Wafering lines can experience "excursions" in which end-of-line wafers exhibit increased defectivity. Often, increased scratch levels due to polishing failures are the issue. With multiple processing steps in the line, modeling of scratch shapes can be a useful tool to identify the problematic step in the process and to help isolate the source of scratch generation.

The shape of a wafer scratch is dependent on several parameters, including platen speed, polish head speed, particle location on the platen, and wafer location for a single wafer polish process. Head oscillation will contribute a known variability to scratch shape. Scratch shape on a batch polisher is
affected by these same factors plus the additional parameter of wafer distance from the center of the polishing head.

Coordinate system for the polish head.

Figure 1: Geometry and relative motion of the coordinate system for a single wafer polisher.

Shown in Fig. 2 is a comparison of relative motions for single vs. batch polishers. For both systems, the wafers and the platen turn in the same direction. The batch polisher, however, holds multiple wafers on a single polish head. Fig. 3 demonstrates the change in scratch shape for a particle stuck in a polish pad as a function of relative distance from the center of the platen. As shown, the curvature of a resulting scratch increases with increasing distance from the center of the platen and is higher for the smaller diameter platen.

Figure 2: Comparison of polish setup for a batch and single wafer polisher.

Figure 1. Figure 2: Comparison of polish setup for a batch and single wafer polisher.

Figure 3: Curvature of a scratch as a function of particle location from the platen center for the batch and single wafer polishers of Fig. 2. Both datasets were obtained using 35 rpm platen and polish head speeds.

Figure 2. Figure 3: Curvature of a scratch as a function of particle location from the platen center for the batch and single wafer polishers of Fig. 2. Both datasets were obtained using 35 rpm platen and polish head speeds.

For a batch polisher, the number of scratched wafers is further affected by the amount of time the scratch source (particle) is on (or embedded in) a pad. Many scratch events last for less than a single revolution of the platen before the originating particle is flushed off of the pad or into a pad groove (Fig. 4a). When the particle is on the pad for longer times, scratching can be more severe. In the simplest case in which the platen and head rpms are matched, a particle stuck in a pad will produce a single visible scratch regardless of time on the pad. It is difficult to exactly match these speeds, however, and some processes intentionally use different head and platen speeds. In this case, a particle will create a new wafer scratch with each revolution as shown in Fig. 4b. Note that due to the offset in platen speed ( 40 rpm ) and head speed ( 38 rpm ) the long duration event will scratch every wafer in the head. The offset of these scratches is dependent upon the speed and speed differential between the head and platen in the process.

An example of modeling of scratch patterns for a polished wafer is shown in Fig. 5. In this case, light scratching is seen as a series of blue dots on the wafer metrology image in Fig. 5a. Using the tool configuration and polishing parameters, the scratch pattern was modeled in Fig. 5b). Fitting of the model to the data is shown in Fig. 5c. As shown, 5 individual scratches are identified indicating that the scratch source was present on the polish pad for at least 5 revolutions.

Figure 4: For a batch polish process with 40 rpm platen speed and 38 rpm head speed. a) Polish scratch for particle on the pad for revolution, and: b) Polish scratches for the same particle on the pad for many revolutions.

Figure 3. Figure 4: For a batch polish process with 40 rpm platen speed and 38 rpm head speed. a) Polish scratch for particle on the pad for revolution, and: b) Polish scratches for the same particle on the pad for many revolutions.

Figure 5: Modeling of a scratched wafer from a single wafer polisher. a) Defect metrology map of scratched wafer: b) Modeled scratch map: c) Alignment of modeled scratches with metrology data.

Figure 4. Figure 5: Modeling of a scratched wafer from a single wafer polisher. a) Defect metrology map of scratched wafer: b) Modeled scratch map: c) Alignment of modeled scratches with metrology data.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.175.pdf

Scratch defects from polish and lapping processes are dependent upon process configuration and process conditions. Knowing these parameters, the formation of scratches on a wafer can be readily modeled. This modeling and simulation can be used to help determine the location and lifetime of individual scratch sources. For multistep processes, modeling can help identify individual process steps that contribute to scratching events.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.175.pdf

C.L. Neslen, W.C. Mitchel, and R.L. Hengehold, J. Electronic Materials, 30(10), 1271-1275, (2001).

E.K. Sanchez, S. Ha, J. Grim, M. Skowronski, W.M. Vetter, M. Dudley, R. Bertke, and W.C. Mitchel, J. Of the Electrochemical Society, 149(2), G131-G136, (2002)

Chi-Young Choi, Joon-Hyung Lee, and Sang-Hee Cho, Solid-State Electronics, 43, 2011-2020, (1999).

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T-Y Kwon, M. Ramachandran, and J-G Park, Friction, 1(4), 281-305, (2013).

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 180-184

doi: 10.4028/p-e031p2

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-03-12

Accepted:
2022-03-13

Online:
2022-05-31

Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

The original version of this paper is available on https://www.scientific.net/MSF.1062.180.pdf

Dirk Lewke , Frank Supplieth , Maik von Ringleben and John Ransom

3D-Micromac AG, Technologie-Campus 8, 09126 Chemnitz, Germany

X-FAB, 2301 N University Ave, Lubbock, TX 79415, USA

Lewke@3d-micromac.com, Frank.Supplieth@xfab.com, Ringleben@3d-micromac.com,

John.Ransom@xfab.com

Keywords: laser, annealing, ohmic contact formation, metallization, Silicon Carbide, 4H-SiC.

Abstract

Within this paper, we will present the results of a study on the ohmic contact formation process with nanosecond (ns) pulsed UV lasers. For the study we compared two laser processes: The base line process with a pulsed laser with Gaussian beam profile and the 3D-Micromac AG process with a pulsed laser with top hat beam profile. The forward voltage characteristics at wafer level was analyzed and proves a clear benefit of the top hat laser process. Besides, the forward voltage characteristics of a second run was performed to analyze the influence of increasing energy density to the electrical characteristic of heat sensitive front side structures. Also with high energy density no negative influence could be detected.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.180.pdf

4H-SiC power semiconductor devices like diode, MOSFET or JFET are vertical devices with structures at the chip front side and a metallization stack at the chip back side. The current flow at this kind of devices is vertical between the front side and the back side. By thinning of the chips, the resistance can be reduced [1] and this is done more and more. While producing those power devices, the front side will be processed first. After this, the SiC wafer is thinned from the back side by a grinding process. After the grinding step, the metallization stack is produced on the back side of the wafer.

Typically, nickel (Ni) is used as a first metallization layer. However, combinations of titanium (Ti) and silicon (Si) can also be realized[2]. Directly after metal deposition, the electrical characteristics of the metal SiC interface correlate with a Schottky characteristic curve. The Ohmic Contact Formation (OCF) process is performed after the first metallization layer is deposited. This process applies heat to the back side of the wafer to convert the Schottky contact into an ohmic contact. In additional process steps, more metal layers are applied to finish the back side processing. For standard thick SiC wafers without back side grinding (e.g. thickness), flash lamps were used to perform the OCF process. Due to the wafer thickness reduction, this annealing cannot be performed anymore due to the high heat load at the front side of the wafers. This is why, with thinner wafers down to 80 thickness and below, nano-second (ns) laser systems are used to perform the OCF process. Within this paper two possible ns lasers systems were compared regarding resulting electrical characteristics. With one system it was demonstrated that the heat of the back side do not harm the electrical characteristics of the front side.

Ohmic Contact Formation

The original version of this paper is available on https://www.scientific.net/MSF.1062.180.pdf

After applying the first metallization layer at the back side of power semiconductor wafers, an ohmic contact between semiconductor and metallization has to be formed. For SiC power semiconductors, typically Ni or Ti layers with thickness of 40 to 100 nm are used. To form an ohmic contact with oven annealing, a heat treatment of approx. at the wafer back side is necessary [3,4]. While applying the heat, the back side metal together with the Silicon from the SiC forms a metal silicide e.g. a nickel silicide ( ). The residual carbon forms carbon clusters at the
interface of SiC and . [4, 5]. For thin wafers, short pulsed lasers have major benefits due to not influencing the front side of the SiC wafers while the heat treatment is performed at the back side.

Experimental Setup

The original version of this paper is available on https://www.scientific.net/MSF.1062.180.pdf

Two laser systems were used. Both laser systems were equipped with a solid state nanosecond laser with 355 nm wavelength. The first system is the base line process and runs under production. At the laser interaction zone the beam profile of this laser has a Gaussian TEM00 characteristic. The pulse length of the single laser pulses is approx. . The process runs under oxygen reduced atmosphere. Therefore, a nozzle applies nitrogen to the wafer surface irradiated by laser.

Fig. 1: Flat Top profile of laser spot

Fig. 1. Flat Top profile of laser spot

The second system was the 3D-Micromac AG's microPRO XS OCF. This system is equipped with a 25 W nanosecond laser with a pulse length between 50 and 100 ns . The laser beam at the interaction zone has a flat top profile of approx. in diameter (Fig. 1).

The benefit of a flat top profile compared to a Gaussian beam is the homogenous energy distribution over the wafer. With such a system, larger laser spots are possible which leads to an increase of throughput. A galvo scanner system is used to guide the laser over the surface of the sample. To reduce the oxygen level, a process chamber is purged with . The oxygen level during processing was .
The used wafers were fully processed power electronic wafers. The diameter of the wafers is 150 mm and their thickness is between and . For wafer thinning, two different grinding processes (Grinding A and B) were used to check if an influence on forward resistance can be seen. At the back side of the wafers, a 75 nm thick nickel layer was sputtered. After the laser-based ohmic contact formation, the wafers were cleaned, and the back side metallization stack was finished with to thick of Aluminum layer. Subsequently, to finishing the processing, the forward resistance was measured for each device at wafer level.

Two wafer runs were performed. The first run was with six wafers with vertically resistor structures. Two thicknesses ( 80 and ) as well as the two different grinding processes are shown in this paper. For this evaluation, low forward resistance was the main quality criteria. For the base line process, only one parameter set was used. For the 3D-Micromac process, a parameter sweep was performed (Fig. 2). Hereby, the pulse energy density and the pulse overlap was varied (Table 1).

The second run was performed on and thick wafers with SiC JBS diodes, to analyze the influence of the back side heat load, generated by the laser OCF processing, on the front side structures. These JBS structures are chosen because they are one of the products running in xfab production, which are most sensitive to heat at front side structures. If head load at the front side is too high, this will be seen in the electrical characteristic. This test is to prove the usability of the process for production. One parameter was used for the base line process and a parameter sweep for the 3D-Micromac process was performed by variation of energy density and pulse overlap (Fig. 4 and Table 2).

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.180.pdf

In Fig 3. exemplary electrical results of run 1 are shown. As a result, it was demonstrated that all tested parameters with a top hat profile result in comparable or lower forward resistance as with a Gaussian energy profile - so all parameters are comparable or better than for the base line process. Furthermore, it could be shown that by tuning the pulse to pulse overlap and pulse energy, density an optimum forward resistance can be achieved. Higher energy density or higher pulse overlap results in lower forward resistance. Nevertheless, with reduction of the overlap, an increase of throughput
can be achieved. By reading the results it has to be taken into account, that there is also an influence of wafer raw material to the electrical results. This is due to inhomogeneous dopant concentration in wafer material. The effect can be seen in Fig 5.

Since vertical devices are used, the forward resistance will be reduced with reduction of the wafer thickness. The wafer thickness has a much higher influence on the forward resistance than the laser parameters (Compare Fig 3 a) and b)). Nevertheless, with reduction of the wafer thickness, the influence of the laser parameters will be more and more important.

The grinding process also has an influence on the forward resistance values. The influence of the grinding process is comparable with the influence of the laser parameters (Compare Fig 3 a) and c)).

Fig. 2: Overview of parameter field for run 1

Fig. 2. Overview of parameter field for run 1

Table 1. Run 1: Process parameter fields per each wafer

Parameter # | Pulse energy density [%] | Pulse overlap | Beam profile
P0 | Base line | Base line | Gaussian
P1 | 78 | Max | Top hat
P2 | 78 | Middle | Top hat
P3 | 85 | Max | Top hat
P4 | 85 | Middle | Top hat
P5 | 93 | Max | Top hat
P6 | 93 | Middle | Top hat
P7 | 93 | Min | Top hat
P8 | 93 | Min | Top hat
P9 | 100 | Max | Top hat
P10 | 100 | Middle | Top hat

Fig. 3: Weibull distributions of forward resistance measurement on three wafer types. a) Grinding A with thickness, b) Grinding A with thickness, c) Grinding B with thickness. Aim is to reduce vertical resistance. Top Hat process shows lower vertical resistance than base line process

Fig. 3. Weibull distributions of forward resistance measurement on three wafer types. a) Grinding A with thickness, b) Grinding A with thickness, c) Grinding B with thickness. Aim is to reduce vertical resistance. Top Hat process shows lower vertical resistance than base line process

In Fig 5. the results of wafer run 2 are shown. Only at the parameter with the lowest energy irradiation - P5 at wafer 3 and 6 - a change from the base line to the other parameter fields is visible. At these fields, the laser energy irradiation was not high enough to form a proper ohmic contact. Hence, the resistance is higher. By analyzing all other parameter fields, it can be seen, that with increasing energy irradiation, the resistance does not significantly change from base line process to the parameter field. This proves that higher energy irradiation do not affect the electrical characteristic of the wafer's front side for 150 and thick wafers.

Fig. 4: Overview of parameter field for run 2 (wafer 1 and 4)

Fig. 4. Overview of parameter field for run 2 (wafer 1 and 4)

Table 2. Run 2: Process parameter fields for each wafer

Parameter # | Wafer # | Pulse energy density [%] | Pulse overlap | Beam profile
P0 | 1,2,3,4,5,6 | Base line | Base line | Gaussian
P1 | 1, 4 | 100 | Min | Top hat
P2 | 1, 4 | 100 | Max | Top hat
P3 | 2, 5 | 90 | Min | Top hat
P4 | 2, 5 | 90 | Max | Top hat
P5 | 3, 6 | 78 | Min | Top hat
P6 | 3, 6 | 78 | Max | Top hat

Fig. 5: Forward Voltage: Colors green to red correspond to minimum to maximum per wafer. Wafer 1-3 are thick. Wafer 4-6 are thick. For parameter see Table 2. From left to right the energy irradiation is increased from min. to max.. It can be seen that at minimum energy irradiation results in forward voltage increase due to not fully performed ohmic contact formation. An increase to maximum energy irradiation do not change the forward voltage. Higher forward voltage at wafer edge region is a result of inhomogeneous dopant distribution in wafer material.

Fig. 5. Forward Voltage: Colors green to red correspond to minimum to maximum per wafer. Wafer 1-3 are thick. Wafer 4-6 are thick. For parameter see Table 2. From left to right the energy irradiation is increased from min. to max.. It can be seen that at minimum energy irradiation results in forward voltage increase due to not fully performed ohmic contact formation. An increase to maximum energy irradiation do not change the forward voltage. Higher forward voltage at wafer edge region is a result of inhomogeneous dopant distribution in wafer material.

Within this paper, the influence of the process parameters on laser-based ohmic contact formation was evaluated and compared with the influence of the wafer parameters such as wafer thickness and grinding process. With this knowledge, the optimal process regime can be adjusted. In an additional wafer run it could be shown that laser thermal annealing for ohmic contact formation does not affect the surface structures even with higher laser energy and thin wafers.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.180.pdf

Yasuhisa Sano et.al., "Back-Side Thinning of Silicon Carbide Wafer by Plasma Etching Using Atmospheric-Pressure Plasma", Key Engineering Materials Volume 516, 2012, p. 108-112

Milantha De Silva ., "Low resistance Ti-Si-C ohmic contacts for power devices sing laser annealing", Materials Science Forum Volume 897, 2017, pp 399-402

Sang Youn Han ., "Ohmic contact formation mechanism of Ni on -type ", Appl. Phys. Lett. 79, 1816, 2001

Roland Rupp ., "Laser backside contact annealing of SiC power devices: A prerequisite for SiC thin wafer technology", 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2013, pp. 51-54

Benedikt Adelmann ., "Temperature and Stress Simulation of during LaserInduced Silicidation for Ohmic Contact Generation", Metals, Vol. 7, no. 12, 2017, p. 545

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 185-189

doi: 10.4028/p-36s1w4

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-25

Accepted:
2022-02-25

Online:
2022-05-31

Via Size-Dependent Properties of TiAI Ohmic Contacts on 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

A. May , M. Rommel , S. Beuer and T. Erlbacher

Fraunhofer IISB, Schottkystrasse 10, Erlangen 91058, Germany

Chair of Electron Devices, University of Erlangen-Nuremberg, Cauerstrasse 6, Erlangen 91058, Germany

Alexander.May@iisb.fraunhofer.de, Mathias.Rommel@iisb.fraunhofer.de, Susanne.Beuer@iisb.fraunhofer.de, Tobias.Erlbacher@iisb.fraunhofer.de

Abstract

P-type Ti/Al-based contact vias of different sizes but identical processing were electrically characterized using linear transfer length method (TLM) patterns and metal-oxide-semiconductor (MOS) transistors. While the TLM patterns and MOS transistors with large vias follow ohmic contact behavior, Schottky contact properties were observed for smaller contact via dimensions. Focused ion beam (FIB) analysis of the contact vias verified the presence of on large contact vias and its absence on smaller ones, correlating its absence with the electrical Schottky properties.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

Limitations for Silicon, e.g. high power or high frequency application and operation in harsh environment such as high temperature, open up the market for high-bandgap materials like silicon carbide (SiC). The 4 H polytype is the technologically most mature one, featuring among others high electric field breakdown strength and high thermal conductivity [1].

To optimize SiC technology, it is essential to minimize power loss, e.g. by ensuring a low resistive ohmic contact. Due to its band gap, no natural chemical element allowing a p-type ohmic metal semiconductor interface by reducing the Schottky barrier height to nearly zero exists for SiC. Therefore, metal stacks are traditionally employed in combination with a sintering process, also referred to as silicidation process, to partially overcome this issue [1,2].
emerged as one of the most prominent p -type stack choices with the ability to form contacts with low contact resistivity due to the formation of the max phase at around . The presence of Al enhances the formation on the surface, which correlates to a reduction of Schottky barrier height and lower specific contact resistance [1-3].

However, the impact of the contact dimensions has not been researched in detail. Therefore, this work investigates the influence of contact via dimensions of TLM patterns and MOS transistors on -based p-type ohmic contact formation on .

Sample Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

Samples on 100 mm wafers were fabricated with a double-well CMOS process using 13 different lithography masks [4]. Wells and contact implantations (nplus and pplus) have been realized using room temperature ion implantation and subsequent annealing for 30 min in Ar ambient with a carbon capping layer. A total dose of was implanted in the pplus region, resulting in a plateau within the first 100 nm with a nominal Al surface concentration of around . The gate stack consists of 50 nm thermally grown gate oxide that was NO densified at for 30 min and 500 nm polycrystalline silicon (PolySi). Employed contact materials were 50 nm NiAl for n-type and Ti/Al for p-type with 80 nm Ti and 300 nm Al . This nearly is supposed to be sufficient for successful ohmic contact formation [1, 5].

It has been previously observed, that Al has a strong tendency to diffuse into during contact annealing [3, 6], damaging or even destroying circuits. Hence, spacing between oxide and contact area is essential. An additional design rule was implemented, extending all edges of contact areas by
, forming the new spacing area structured via dry etching. The original contact vias were patterned inside the spacing area with separate lithography and lift-off steps afterwards. A 2 min annealing step in Ar atmosphere at activated the silicidation. Finally, was deposited as metallization. The resulting MOS structures are depicted schematically in Fig. 1a).

Fig. 1: a) schematic of NMOS and PMOS cross view and b) electron beam image of a PMOS fabricated by IISB with labeled channel and contact via dimensions.

Fig. 1. a) schematic of NMOS and PMOS cross view and b) electron beam image of a PMOS fabricated by IISB with labeled channel and contact via dimensions.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

In the following, channel length and width of transistors are abbreviated to width in - length in (e.g. 80-500). Contact via dimensions share the same nomenclature with the first number as the width in and the second as the length in via (e.g. 66-25), as labeled in Fig. 1b).

TLM patterns and transistors were characterized at room temperature using an Agilent 4156C Precision Semiconductor Parameter Analyzer and a Cascade PA200 prober with a Keithley SCS4200 measuring unit.

TLM structures were designed and evaluated as described in detail by Schroder [7], consisting of five different evaluation distances, namely 15, 30, 60, 120 and , with two metal pads per contact via. Measurements were performed with four probes to prevent contact and line resistances of the measuring probes influencing electrical measurements. Table 1 presents the results, namely sheet resistance R_sh, contact resistance R_C, transfer length L_T, contact resistivity , all including standard deviation (StdDev), and coefficient of determination .

Table 1: Averaged results of 14 TLM measurements for Ti/Al-based p-type contacts with pplus implantation including wafer level deviation.

R_sh
[Ω/sq]
StdDev
[%]
R_C
[Ω]
StdDev
[%]
L_T
[μm]
StdDev
[%]
ρ_C
[mΩcm²]
StdDev
[%]
R²
[-]

23700
2
1370
9
5.8
10
8.0
18
0.999

Contact resistivities between and have been observed in literature [ ], leaving the results one to two orders of magnitude higher, but still showing ohmic contact behavior for all structures evaluated.

Fig. 2: Output characteristics of a) PMOS 20-6 and b) PMOS 80-500 from a center die. The inset shows a higher resolution of the first 2 V of VD for VGs of 19 V and 20 V from the PMOS 20-6.

Fig. 2. Output characteristics of a) PMOS 20-6 and b) PMOS 80-500 from a center die. The inset shows a higher resolution of the first 2 V of VD for VGs of 19 V and 20 V from the PMOS 20-6.

Similarly to the TLM results, a PMOS 80-500 with a contact via of 66-25 exhibits ohmic output results, depicted in Fig. 2b). However, a PMOS 20-6 with a 16-3 contact via shows Schottky properties, displayed in Fig. 2a), indicated by the nonlinear slope between 0 V and 1.5 V , see inset in Fig. 2. This phenomenon was also observed for PMOS with higher widths having 96-3 and 396-3 contact vias and on devices from other dies and wafers. Due to not having any process variation, it is assumed that the geometries of the contact via contribute to this effect. Therefore, the width can be excluded as a sole cause.

To get behind this effect, contact vias of the electrically characterized transistors were investigated via FIB, presented in Fig. 3, using a Helios G4 PFIB CXe from ThermoFisher Scientific to visualize possible differences in their contact regions. On the 66-25 contact via, a formed layer can be identified, indicated by its terrace like off-axis epitaxial growth, as depicted in Fig. 3c) [2, 3]. However, it is not present on the 16-3 via shown in Fig. 3e), which, due to identical processing, correlates the missing formation to the different dimensions of the contact via. This also matches the observed electrical properties at the beginning of the output characteristics with the presence or absence of the layer.

Fig. 3: Tilted SEM images of FIB prepared cross sections of I) 66-25 (a), c) and d)} and II) 16-3 -based contact vias and e)} after finished processing. Multiple cuts across the complete via length, which start in the oxide free spacing area, with width distance between them and larger magnifications of the SiC contact interface are depicted for both via sizes.

Fig. 3. Tilted SEM images of FIB prepared cross sections of I) 66-25 (a), c) and d)} and II) 16-3 -based contact vias and e)} after finished processing. Multiple cuts across the complete via length, which start in the oxide free spacing area, with width distance between them and larger magnifications of the SiC contact interface are depicted for both via sizes.

Interestingly, the layer is not observed to continuously span across the whole contact area, as seen in Fig. 3d), and is additionally not completely connected with the metallization above, resulting in some sort of cavities on the interface. Both effects lead to a smaller than expected effective contact area, also explaining the discrepancies between the TLM results and literature values of the contact resistivity. As verified by FIB, complete coverage and connectivity, which is assumed for the evaluation, is not given. This negatively affects the accuracy of the TLM results.

These cavities are present over the whole 66-25 contact via, while the smaller one has only a few, displayed in Fig. 3a) and 3b). The connections between and the metallization appear to be grains with some crystalline character. While not forming , other material combinations from the Al-Ti-Si-C quaternary system are present at the 16-3 contact via. Possible materials could be or . The small grains on the SiC surface of the via are assumed to be Al-rich [8]. The reason for the change in morphology indicates differences in the reaction kinetics. This might occur due to varying surface conditions and activation energies or a temperature distribution deviation during the RTP process.

Further investigation using X-ray diffraction and transmission electron microscopy is required to understand the materials at the small contact via. Also, the cavities formed above the layer and the critical contact via dimensions remain undetermined and open possibilities for future research.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

The anomaly of Schottky properties on transistors related to small Ti/Al-based contact via dimensions was observed, in contrast to ohmic contact behavior of larger ones. Here, two transistors were investigated via FIB , revealing a formed layer at the SiC surface for the larger via and a lack of for the smaller via. With identical processing and the design being the only variation, this correlates the missing formation of with the electrically observed Schottky properties. Further investigation is required to determine the reactions taking place at the smaller contact via, explain the absence of and comprehend the formed cavities above the layer.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

iRel40 is a European co-funded innovation project that has been granted by the ECSEL Joint Undertaking (JU) under grant agreement No 876659. The funding of the project comes from the Horizon 2020 research programme and participating countries. National funding is provided by Germany, including the Free States of Saxony and Thuringia, Austria, Belgium, Finland, France, Italy, the Netherlands, Slovakia, Spain, Sweden, and Turkey.

The document reflects only the author's view and the JU is not responsible for any use that may be made of the information it contains.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.185.pdf

T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology, John Wiley & Sons Singapore Pte. Ltd, Singapore, 2014.

S. Tsukimoto, K. Ito, Z. Wang, M. Saito, Y. Ikuhara, M. Murakami, Growth and Microstructure of Epitaxial Contact Layers on SiC, Mater. Trans. 50 (2009) 1071-1075.

M. Kocher, Charakterisierung und Modellierung von Ti/Al-basierten ohmschen Kontaktgebieten auf p-dotiertem 4H-Siliciumcarbid, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, 2021.

A. Abbasi, S. Roy, R. Murphree, A.-U. Rashid, M.M. Hossain, P. Lai, J. Fraley, T. Erlbacher, Z. Chen, A. Mantooth, Characterization of a Silicon Carbide BCD Process for Circuits, in: WiPDA 2019: 7th Annual IEEE Workshop, Wide Bandgap Power Devices & Applications Raleigh, NC, Oct. 29-31, IEEE, Piscataway, NJ, 2019, pp. 231-236.

T. Abi-Tannous, M. Soueidan, G. Ferro, M. Lazar, C. Raynaud, B. Toury, M.-F. Beaufort, J.-F. Barbot, O. Dezellus, D. Planson, A Study on the Temperature of Ohmic Contact to p-Type SiC Based on Ti 3 SiC 2 Phase, IEEE Trans. Electron Devices 63 (2016) 2462-2468.

Prabriputaloong K., Piggott M. R., Reduction of SiO 2 by Molten Al, Journal of the American Ceramic Society 56 (1973) 184-185.

D.K. Schroder, Semiconductor material and device characterization, Third edition, IEEE Press Wiley-Interscience; IEEE Xplore, Hoboken, New Jersey, Piscataway, New Jersey, 2006.

F. Roccaforte, A. Frazzetto, G. Greco, F. Giannazzo, P. Fiorenza, R. Lo Nigro, M. Saggio, M. Leszczyński, P. Pristawko, V. Raineri, Critical issues for interfaces to p-type SiC and GaN in power devices, Applied Surface Science 258 (2012) 8324-8333.

F.A. Mohammad, Y. Cao, K.-C. Chang, L.M. Porter, Comparison of Pt-Based Ohmic Contacts with Ti-Al Ohmic Contacts for p -Type SiC, Jpn. J. Appl. Phys. 44 (2005) 5933-5938.

O. Nakatsuka, T. Takei, Y. Koide, M. Murakami, Low Resistance TiAl Ohmic Contacts with Multi-Layered Structure for p-Type 4H-SiC, Mater. Trans. 43 (2002) 1684-1688.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 190-194

doi: 10.4028/p-97jy4p

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment

The original version of this paper is available on https://www.scientific.net/MSF.1062.190.pdf

A.B. Renz , O.J. Vavasour , A. Péréz-Tomás , Q. Cao , V.A. Shah , Y. Bonyadi , V. Pathirana , T. Trajkovic , G.W.C. Baker , P.A. Mawby , and P.M. Gammon

School of Engineering, University of Warwick, Coventry, UK

Catalan institute of Nanoscience and Nanotechnology (ICN2), CSIC, Barcelona, Spain

Lyra Electronics, Warwick University Campus, Wellesbourne, UK

Cambridge Microelectronics Ltd., Capital Park, Fulbourn, Cambridge, UK

a*A.Renz@warwick.ac.uk, o.vavasour.1@warwick.ac.uk, amador.perez@icn2.cat, q.cao.2@warwick.ac.uk, y.bonyadi@warwick.ac.uk, vasantha.pathirana@camutronics.com, t.trajkovic@camutronics.com, Guy.Baker@warwick.ac.uk, P.A.Mawby@warwick.ac.uk, P.M.Gammon@Warwick.ac.uk

Abstract

A systematic study is presented into the impact of a surface passivation treatment, carried out prior to the deposition of a high refactory metal contact to 3.3 kV JBS diodes. Electrical results from Mo, W and Nb diodes reveal that those diodes that undergo the treatment have a major leakage current reduction, most significantly by 3.5 orders of magnitude to for treated W diodes. When applied to fully optimized diodes, the surface passivation treatment reduces the apparent barrier height, as well as the leakage current. SIMS analysis reveals that during the treatment, phosphorous diffuses into the top 50 nm of the SiC, achieving a peak density of , while XPS results suggest some of this diffuses into the contact metal during the contact anneal, altering the Schottky barrier height. TCAD simulations help give more insight into band diagram changes at the Schottky interface, where the partial activation of the phosphorous ions is shown to alter the Schottky barrier, promoting a thermionic field emission conduction, effectively lowering the barrier height at the interface in diodes.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.190.pdf

SiC Schottky diodes have now been commonly adopted, replacing legacy Si PiN diodes in a number of applications [1]. Yet the voltage range of the commercial devices available is still narrow, , and the widescale release of 3.3 kV devices would be attractive for traction, PV and industrial inverters. Just as at lower voltages, the Schottky barrier height (SBH) can be controlled by the choice of contact metal and the related processing steps. The choice of SBH is a trade-off between low forward voltage drop with a low SBH, and low leakage current with a high SBH. However, in reality, minimising on-state conduction losses is typically prioritised and a low SBH will be chosen by utilising titanium (Ti), or molybdenum nitride (MoN) contacts to create a SBH as low as 0.86 eV . This group recently reported on the development of a surface passivation treatment, in which a phosphorous pentoxide ( ) layer is grown on the surface, and then removed, prior to the deposition of a Mo contact metal [4]. This resulted in a reduced on-state SBH, 0.11 eV lower than the untreated version, and a lower leakage current by two to three orders of magnitude. In this paper, we use secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS) to provide a detailed picture of the changes that occur in the SiC Schottky subsurface region. The treatment is also applied to other refractory metals, tungsten (W) and niobium (Nb), as well as to fully optimised 3.3 kV junction barrier Schottky (JBS) diodes.

Figure 1: 1-5 show the processing steps carried out during the treatment and contact formation, and their effect on the Schottky interface. 6 shows the layout of the final 3.3 kV JBS diode.

Figure 1. Figure 1: 1-5 show the processing steps carried out during the treatment and contact formation, and their effect on the Schottky interface. 6 shows the layout of the final 3.3 kV JBS diode.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.190.pdf

For the fabrication of and Mo mesa isolated Schottky diodes on lightly nitrogen doped epitaxial layers (starting wafer in Fig. 1, step 1), the deposition was carried out at for 2 hours in nitrogen ( ) ambient in a tube furnace, utilising a silicon diphosphate source wafer. This process results in the deposition of on the surface of the SiC samples (Fig. 1, step 2), with phosphorous partly diffusing into the SiC. After having removed the previously deposited oxide on top of SiC (Fig. 1, step 3), the e-beam deposition of 100 nm of or Mo was done on the diodes, respectively. The formation of a Schottky contact was then finished after a rapid thermal anneal at for 2 minutes was carried out. The exact process conditions of the fabrication can be found in [4].

To test the process on fully optimised and terminated device structures operating at high currents and reverse voltages, 3.3 kV SiC JBS diodes (active areas and ) were then produced. The full details of the fabrication process of these JBS devices can be found in [5].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.190.pdf

On-state and off-state rectifying characteristics of the unterminated Mo, W , and Nb diodes were measured using a Keysight B1505A with a Semiprobe semi-automatic probe station. Ideality factors and barrier heights in the on-state were extracted between forward current densities of to

Figure 2: (left) Ideality factors and SBHs for refractory metal/SiC Schottky diodes. (right) Leakage current densities (at -200 V ) of more than 100 devices of each small area refractory metal/SiC Schottky diodes.

Figure 2. Figure 2: (left) Ideality factors and SBHs for refractory metal/SiC Schottky diodes. (right) Leakage current densities (at -200 V ) of more than 100 devices of each small area refractory metal/SiC Schottky diodes.

Figure 3: On state characteristics of a) the JBS diodes and b) the 42.25 mm 2 JBS diodes; c) off state characteristics of the JBS diodes [5].

Figure 3. Figure 3: On state characteristics of a) the JBS diodes and b) the 42.25 mm 2 JBS diodes; c) off state characteristics of the JBS diodes [5].

. An overview of the distribution of these parameters can be seen in Fig. 2. Across the entire dataset, the -treatment consistently reduces leakage current densities ( ), the largest reduction being for the W diodes, which reduces from for those untreated, to for those treated. A similar reduction by three orders of magnitude to takes place in the -treated Mo devices, and to in the Nb devices.

In the on-state, all measured devices showed ideality factors lower than 1.12 which proves the applicability of the thermionic emission model [6]. The trends of the SBH vary according to the metals: the initially low barrier height of Nb Schottky diodes of 0.78 eV is increased after the treatment to 0.93 eV . This trend is repeated in the W diodes, where the average barrier height is raised from 1.13 eV to 1.20 eV post treatment. However, as previously reported [4] the -treatment once again lowered the SBH of the contacts, the average barrier height of treated diodes having reduced from 1.26 eV to 1.21 eV .

The on-state of the optimised device structures shows the reduction of barrier height for the Mo devices on smaller die size (Fig. 3 a)) as well as for the JBS diodes (Fig. 3 b)), a trend that follows the description presented in the previous paragraph.

Figure 4: a) SIMS analysis showing the build-up of P at the P2O5 treated Mo/ SiC interface, b) HR-TEM images of the untreated (top) and P2O5 treated (bottom) Mo/SiC interface [5], and c) band diagrams, pre-and post-treatment, based on TCAD simulations.

Figure 4. Figure 4: a) SIMS analysis showing the build-up of P at the P2O5 treated Mo/ SiC interface, b) HR-TEM images of the untreated (top) and P2O5 treated (bottom) Mo/SiC interface [5], and c) band diagrams, pre-and post-treatment, based on TCAD simulations.

In the off-state of the 3.3 kV JBS diodes (Fig. 3 c)), a higher proportion of the treated devices reached the rated voltage without suffering soft breakdown. This effect is thought to be attributable to the passivation of leakage current paths beneath the Schottky interface, as XPS, SIMS and TEM results show [4]. Little difference was witnessed between treated and untreated devices, in either the resistance of large area devices (Fig. 3b)), or the switching performance of the devices. These results suggest that -treated devices could be utilised to reduce leakage current in a 3.3 kV JBS diode, so maximising the size (the current rating) that these chips could be scaled up to.

A number of characterisation techniques offer up an insight into the effect of each step of the treatment and subsequent metallization, and this is summarized in Fig. 1. First, SIMS analysis (Fig. 4a), shows that the treatment results in the diffusion of P into the subsurface, to a depth of 50 nm , and a peak concentration of atoms . However, with a processing temperature of just , only a small fraction of these are expected to be electrically active. Second, TEM micrographs (Fig. 4b) taken before and after the treatment suggest that surface imperfections form, and are subsequently filled, during the deposition. EDX analysis on these confirmed that the oxide remains in place after HF etching and metallization. Third, XPS analysis (not shown) of thin Mo layers formed on untreated and treated surfaces shows that the work function of the interfacial metal increases by around , likely the result of P diffusion from the subsurface during the contact anneal, forming a Mo phosphate at the interface.

The combined effect of these three observed changes brings about a complex change to the band structure at the Schottky interface, as modelled in TCAD (Fig. 4c). The increase in metal work function is counteracted by a reduction in Fermi level position relative to the conduction band edge . If of the subsurface P is electrically active (peak concentration of ), then is reduced by 80 meV . The increase in interfacial doping also encourages thermionic-field emission through the barrier at lower energy levels. These competing effects heavily influence the on-state, and an overall reduction in the SBH (from forward I-V measurements) is consistently recorded in both the small area diodes (Fig. 2) and the JBS diodes (Fig. 3). However, the SBH of treated Nb and W contacts is consistently higher than that of their untreated counterparts, likely due to a larger metal work function increase.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.190.pdf

Electrical results of refractory metal (W, Nb and Mo) Schottky diodes that had undergone a treatment demonstrated a consistent reduction of leakage current across the entire dataset, when they were compared to their untreated counterparts. For Mo SBDs, this occurred in parallel to a reduction in barrier height. Whilst the application of the same treatment on fully optimised 3.3 kV Mo JBS diodes repeated the observed improvement, surface investigations using SIMS, XPS and EDX showed that this was likely due to the diffusion of phosphorous into the SiC top surface, and later into the contact metal. TCAD simulations suggested that the changes in the on-state were caused by an increase in subsurface doping due to the presence of partially-activated phosphorous ions after the treatment. These causes a reduction of by approximately 80 meV , whilst the increased doping enhances thermionic field emission conduction through the barrier.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.190.pdf

F. Roccaforte, G. Brezeanu, P. Gammon, F. Giannazzo, S. Rascunà, and M. Saggio, "Schottky Contacts to Silicon Carbide: Physics, Technology and Applications," Advancing Silicon Carbide Electronics Technology, I: Metal Contacts to Silicon Carbide: Physics, Technology, Applications, 2018.

R. Rupp, R. Elpelt, R. Gerlach, R. Schömer, and M. Draghici, "A new SiC diode with significantly reduced threshold voltage," in Power Semiconductor Devices and IC's (ISPSD), 2017 29th International Symposium on, 2017: IEEE, pp. 355-358.

L. Stöber, J. Konrath, F. Patocka, M. Schneider, and U. Schmid, "Controlling 4H-SiC Schottky Barriers by Molybdenum and Molybdenum Nitride as Contact Materials," IEEE Transactions on Electron Devices, vol. 63, no. 2, pp. 578-583, 2015.

A. Renz et al., "The improvement of Mo/4H-SiC Schottky diodes via a P2O5 surface passivation treatment," Journal of Applied Physics, vol. 127, no. 2, p. 025704, 2020.

A. B. Renz, Vavasour, O.J., Shah, V.A., Pathirana, V., Trajkovic, T., Bonyadi, Y., Wu, R., Ortiz-Gonzalez, J.A., Rong, X., Baker, G.W.C., Mawby, P., and Gammon, P.M., " 3.3 kV SiC JBS diodes employing a P2O5 surface passivation treatment to improve electrical characteristics," IEEE Energy Conversion Congresse and Exposition (ECCE), 2021.

R. J. Tung, "Electron transport at metal-semiconductor interfaces: General theory," Phys. Rev. B, vol. 45, no. 23, p. 13509, 1992.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 195-203

doi: 10.4028/p-a08hju

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Accepted:
2022-03-07

Online:
2022-05-31

The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

C. Frewin, M. Beygi, E. Bernardin, C. Feng, F. La Via , William Dominguez-Viqueira and S.E. Saddow

NeuroNexus, LLC, Ann Arbor, MI, USA

Dept. of Electrical Engineering Dept., University of South Florida, Tampa, FL, USA

Dept. of Mechanical Engineering, University of South Florida, Tampa, FL, USA

IMM-CNR, Catania, Sicily, IT

Moffitt Cancer Center, Tampa, FL, USA

Dept. of Medical Engineering, University of South Florida, Tampa, FL, USA

cfrewin@neuronexus.com, beygi.mohamad@gmail.com, evans.bernardin@outlook.com, chenyinfeng@usf.edu, saddow@usf.edu

Keywords: Neural Interface, Brain Implants, SiC biomedical, MEMS

Abstract

Silicon Carbide (SiC) has been demonstrated as both a bio- and neuro-compatible wide-band-gap semiconductor with a high thermal conductivity and magnetic susceptibility and may be potentially compatible with human brain tissue. Two single-crystal, solid-state forms of SiC have been used to create monolithic intracortical neural implants (INI) without using physiologically exposed metals or polymers, thus eliminating many known reliability challenges in-vivo through a single, homogenous material. Amorphous was used to insulate 16 -channel functional INI and the electrochemical and MRI compatibility (7T) performance were measured. interfaces were fabricated using homoepitaxy,alternating epitaxial films of n-type and p-type forming an isolating PN junction which prevents substrate leakage current between the 16 adjacent electrodes and traces fabricated which were formed using deep-reactive ion etching (DRIE). 3C-SiC interfaces were fabricated in a similar fashion, but the epitaial conductive layers were grown on on both bulk crystalline (100) silicon and SOI wafers. In both cases a conformal coating of was used as the top-side insulator and windows opened using RIE to allow electrochemical interaction. Electrochemical charaterization achieved through electrochemcial impedance spectroscopy (EIS) and cyclic voltammetry (CV) indicates performance on par, or exceeding, that of Pt reference electrodes with the same form fit. While magnetic resonance imaging (MRI) is an essential, non-contact method used to investigate issues with the nervous system, the high field MRI (e.g., 3 T and higher) necessary for proper diagnosis can be a safety issue for patients with INI due to inductive coupling between the powerful electromagnetic fields and the implanted device. This results in having to use lower electromagnetic field power (less than 1.5T), and therefore lower resolution, which hinders diagnostic prognosis for these patients. In this work the MRI compliance of epitaxial, monolithic SiC INI was studied. The specific absorption rate (SAR), induced heating, and image artifacts caused by the portion of the implant within a brain tissue phantom located in a 7 T small animal MRI machine were estimated and measured via finite element method (FEM) and Fourier-based simulations. Both the simulation and experimental results revealed that free-standing 3C-SiC films had no observable image artifacts compared to silicon and platinum reference materials inside the MRI at 7 T while FEM simulations predicted an SAR reduction for compared to Pt. These initial simulations and experiments indicate a SiC monolithic INI may effectively reduce MRI induced heating and image artifacts in high field MRI.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

Silicon Carbide ( SiC ) is a potentially biocompatible semiconductor [1] material that may revolutionize implantable biomedical devices, such as biosensors and neural implants, and could enable many advanced biomedical applications [2]. SiC devices offer higher power densities and lower energy losses, as well as being chemically inert and physically robust, allowing the development of lighter, more compact, and higher efficiency products ideal for long-term in-vivo applications. Applications can range from passive material components, like heart stent coatings and bone implant scaffolds, to more complicated devices, like neurological implants and biosensors. One of the large issues facing the medical device community has been the lack of physiologically acceptable materials which also offer electronic functionality. Most of the current implementations of electrically active biomedical devices use silicon materials technology, which is unfortunately a material only stable in-vivo for acute periods of time, usually measured in months reliably [3,4,5, 6]. Biomedical devices designed for permanent, chronic applications, like physiological sensors, brain-machine-interfaces (BMI), and smart structural (bone) or organ implants, require a more robust, reliable material that is not only electrically functional, but is not recognized as a foreign object within the biological system [7]. A physiologically compatible, chronically implantable device designed to interact directly with individual cells has great potential to assist millions of people affected by trauma or disease of the brain and spinal cord as well as individuals who have lost limbs or sensory organs. This kind of device potentially has the effect of not only restoring patient health, but also improving their overall quality of life. Unfortunately, as devices become smaller so they can interact with individual cells, they fail chronically in-vivo which has been attributed to both abiotic and biotic factors. Until now, no known, chronically reliable solution to this device challenge has been found, however, silicon carbide may complement or even replace materials, like silicon, as it has demonstrated excellent performance in multiple animal models as well as chemical and physical evaluations [7]. In particular, 3C-SiC the cubic crystalline polytype of silicon carbide, appears to be an ideal material to meet this challenging application: it has demonstrated evidence of bio- and hemocompatibility; the deposition of this polytype allows for tailored doping profiles as well as integration onto silicon platforms allowing seamless integration of electronics with the implants; it is highly durable and chemically inert, even within harsh, corrosive, and oxidative physiological environment; SiC is also an excellent thermal conductor.

This paper focuses on recent advances in the development of monolithic silicon carbide intracortical neural implants, specifically where only SiC is the only material in contact with the physiological environment. These monolithic 'all-SiC' implants were constructed using SiC as the electrical device material and amorphous as an external insulator [8, 9]. Three different devices are reported: 4 H -SiC, 3 C -SiC and carbon-electrodes which are sandwiched between a top and bottom layer of -SiC, inevitably to form an ultra-thin ( ) implant [10]. Device fabrication and electrochemical characterization are reported for all three device types of devices, with MRI compatibility analysis reported for free-standing 3C-SiC implants [11].

Monolithic SiC Neural Interfaces

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

Monolithic intracortical neural interfaces (INI) designed to interact directly with individual neurons have made impressive progress towards human utilization in recent years, but still display questionable long-term reliability. In this paper we report on the development and characterization of highly resilient SiC INI. SiC is a physically robust, biocompatible, and chemically inert semiconductor. Two monolithic 'all-SiC' INI are reported here comprised of monocrystalline SiC and 3C-SiC. Details of each device may be found in the literature as reported by Bernardin et. Al [8] and Beygi et. Al [9], respectfully. A planar MEA design (Fig. 1(a)) was used to characterize neural probe performance using single-ended electrodes of varying tip diameter ( , and 800 ), PN diode test structures and double-ended mesa resistors to evaluate electrode resistivity.

4H-SiC Fabrication and Characterization: The device support was micromachined from p-type 4HSiC, with conductors created from n-type , simultaneously providing electrical isolation through the resulting pn junction. -SiC was utilized as the top side insulation, preventing shorting of the pn diode by the electrochemical environment. Electrodes were designed with a geometric surface area (GSA) varying from 496 to . Electrical characterization showed high-performance pn diode behavior, with typical turn-on voltages of and reverse bias leakage below . Current leakage between adjacent electrodes was maximally over a voltage range of -50 V to 50 V . Since the monolithic SiC devices rely on the integration of only robust and highly compatible SiC material, they offer a promising solution to probe delamination and biological rejection often associated with the use of multiple materials used in many current INI devices.

Figure 1: All- SiC planar device used for electrical and electrochemical testing. (a) planar MEA mask with single-ended electrodes (top half) of varying recording tip diameter and test structures (bottom half). (b) Optical micrograph of fabricated diameter all-SiC single-ended electrodes. (c) One end of an all-SiC interdigitated electrode (IDE) showing metal contact pad (top) and portion of two interdigitated wide mesas of on p base layer with a pitch of . (d) Histogram of 20 IDE devices from -50 V to +50 V . Of 20 devices, only 2 showed measurable current flow at the diode turn-on voltage ( +2.3 V ), while 4 IDEs showed current flow between -16 V to -50 V . The remaining 14 continued to block to at least .

Figure 1. Figure 1: All- SiC planar device used for electrical and electrochemical testing. (a) planar MEA mask with single-ended electrodes (top half) of varying recording tip diameter and test structures (bottom half). (b) Optical micrograph of fabricated diameter all-SiC single-ended electrodes. (c) One end of an all-SiC interdigitated electrode (IDE) showing metal contact pad (top) and portion of two interdigitated wide mesas of on p base layer with a pitch of . (d) Histogram of 20 IDE devices from -50 V to +50 V . Of 20 devices, only 2 showed measurable current flow at the diode turn-on voltage ( +2.3 V ), while 4 IDEs showed current flow between -16 V to -50 V . The remaining 14 continued to block to at least .

Electrodes which display semi-metallic charge transport can be fabricated by degenerately doping the SiC epilayer during the growth process. The use of alternate polarity SiC, heavily doped n-type grown on p-type SiC, creates a pn diode, which provides isolation between adjacent electrodes due to the depletion layer that develops at the junction. Amorphous then serves as a conformal, top-side insulating coating to prevent the electrochemical environment from interacting with the pn diode junction or the SiC electrical traces. A high quality epiwafer was grown and delivered to the USF SiC group by researchers at Linköping University (Linköping, Sweden [8]). Once received all-SiC INI development began with the fabrication of devices on as illustrated in Fig. 1.

Electrochemical performance was evaluated using electrochemical impedance spectroscopy (EIS) and cyclical voltammetry (CV) in 7.4 pH aerated PBS. Experimental results verified that the trace length did not significantly affect the overall electrical impedance of the SiC electrodes, a similar effect seen with conventional neural probes metal traces. The results from the EIS measurements are shown in Figure 2(a). The electrode interaction with the electrolyte displayed a nearly purely capacitive characteristic at frequencies less than 10 kHz , as is displayed by the phase angle of for the electrodes with less than geometrical surface area. Another notable trend was that the impedance decreased with an increase in electrode area. Figure 2(b) plots the impedance and phase obtained from the electrodes when measured at 1 kHz , the frequency associated with the action potential associated with cortical neural processes. The smallest electrode ( ) had an average impedance of , which decreased to for the largest, area electrodes. The trend lines added to the graph show a relative linearity associated with all the electrodes.

Figure 2: electrode performance vs. geometrical surface area. (a) EIS data (error bars represent the standard deviation). Inset shows basic circuit model which produced an impedance profile similar to experimental data. (b) A box and whiskers plot for the impedance and phase at the frequency of 1 kHz vs. area. Mean impedance and phase represented with a dot. All tests performed in PBS) with a pH of 7.4.

Figure 2. Figure 2: electrode performance vs. geometrical surface area. (a) EIS data (error bars represent the standard deviation). Inset shows basic circuit model which produced an impedance profile similar to experimental data. (b) A box and whiskers plot for the impedance and phase at the frequency of 1 kHz vs. area. Mean impedance and phase represented with a dot. All tests performed in PBS) with a pH of 7.4.

Figure 3(a) displays select representative cyclic voltammetery, CV, curves for each of the electrodes reported in this study taken across the potential water limit for Pt ( -0.6 to 0.8 V ). Figure 3(b), on the other hand, shows select curves using the extended water window ( -2.0 to 2.8 V ) from the all-SiC electrodes. Both micrographs demonstrate a decrease in the hysteresis cycle when the area is decreased. Once again, CV data supports a dominant capacitive interaction mechanism with the electrolytic ions. The current remains constant for the CV sweep, until it nears the potential limit on either side of the test. At this point, the charge potential is reversed, leading to a large influx of current which follows the resistor-capacitor (RC) charging process. After the charging, the current once again remains constant until the next potential ramp shift.

Figure 3: (a) CV plot showing a single curve from cyclic voltammetry evaluation of a select electrode. Curves bounded at the potentials typically used for platinum or iridium electrodes of -0.6 V and +0.8 V . Inset shows detail for the three smallest electrodes. (b) Plot of second CV curve from a select electrode. Ramp rate same as (a), but potential limits extended until onset of a large current flux. All tests performed in 7.4 pH PBS .

Figure 3. Figure 3: (a) CV plot showing a single curve from cyclic voltammetry evaluation of a select electrode. Curves bounded at the potentials typically used for platinum or iridium electrodes of -0.6 V and +0.8 V . Inset shows detail for the three smallest electrodes. (b) Plot of second CV curve from a select electrode. Ramp rate same as (a), but potential limits extended until onset of a large current flux. All tests performed in 7.4 pH PBS .

3C-SiC Fabrication and Characterization: The 3C-SiC (cubic silicon carbide) all-SiC INI was developed incorporating many standard silicon semiconductor micromachining processes. This started with the epitaxial growth of a film on a SOI wafer, followed by patterning of the 3 C SiC epitaxial films via thin film contact photolithography techniques. The subsequent etching of the electrode traces and recording sites used a deep-reactive ion etching (DRIE) process, followed by deposition of a conformal -SiC film via PECVD, and the opening of windows in the a-SiC film via RIE (recording and wire-bonding sites). The final probe definition etch through the buried oxide layer was accomplished via additional DRIE processes. The final step was the release of the finished device from the substrate SOI wafer which was achieved through hydrofluoric acid wet etching the buried oxide layer. The fabrication steps are shown in Figure 4.

Figure 4: The fabrication flow of all-SiC neural probes. Planar MEA fabrication concluded at Step 7 for reference. Reprinted with permission from Elsevier [12].

Figure 4. Figure 4: The fabrication flow of all-SiC neural probes. Planar MEA fabrication concluded at Step 7 for reference. Reprinted with permission from Elsevier [12].

The INI were characterized using the same methods as the devices. The results are presented in the summary section where comparison of all SiC neural interfaces is made. Figure 5 shows some details of the devices fabricated on SOI:

Figure 5: SEM and AFM analysis 3C-SiC films and a pre-released all-SiC neural probe. (a) Cross-section SEM micrograph of epitaxial 3C-SiC on SOI wafer. AFM analysis on the epitaxial 3C-SiC film (b) edge region of the wafer (c) center region of the wafer. (d) Optical micrograph of to be released neural probe and (e)(f) SEM micrographs of recording sites and package pads. Reprinted with permission from Elsevier [12].

Figure 5. Figure 5: SEM and AFM analysis 3C-SiC films and a pre-released all-SiC neural probe. (a) Cross-section SEM micrograph of epitaxial 3C-SiC on SOI wafer. AFM analysis on the epitaxial 3C-SiC film (b) edge region of the wafer (c) center region of the wafer. (d) Optical micrograph of to be released neural probe and (e)(f) SEM micrographs of recording sites and package pads. Reprinted with permission from Elsevier [12].

Carbon-electrode SiC INI

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

Carbon containing materials, such as graphene, carbon-nanotubes (CNT), and graphene oxide, have gained prominence as possible electrode materials for implantable neural interfaces due to their excellent conductive properties. While carbon is a promising electrochemical interface, reliable and repeatable fabrication processes are needed for reliable and repeatable device production and this factor impacts large scale device production. Here we demonstrate that carbon (C) electrodes and traces constructed from pyrolyzed-photoresist-film (PPF), when combined with amorphous silicon carbide ( ) insulation, can be fabricated with repeatable processes using tools easily available in most semiconductor facilities. Directly forming C on simplifies the fabrication process while eliminating noble metal evaporation/sputtering and lift-off processes. C electrodes in oxygenated phosphate buffered solution at pH 7.4 demonstrated excellent electrochemical charge storage capacity (CSC) of , an impedance of , and phase angle of at 1 kHz with a recording site area.

C on a-SiC Fabrication and Characterization: The - SiC INI was fabricated via standard semiconductor micromachining processes. As reported in [10], -SiC was deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) using 12 sccm SiH 4 and 360 sccm CH 4 as silicon and carbon precursors along with 700 sccm Ar carrier gas. The chamber was heated to , pressure maintained at 1100 mTorr , and an RF plasma was applied with a power of 200 W . Positive
photoresist (AZ12xt) was spin-coated at 500 rpm for for 50 s , and for 2 s for layer measured via stylus profilometer on the surface of the deposited a-SiC. The resist coated substrate was soft-baked at for 3 min which was then followed by UV exposure at 120 . Next, a one-minute post-exposure bake at was performed and followed by pyrolyzation within a annealing tube furnace held at atmospheric pressure under an Ar and environment of 100 sccm and 5 sccm , respectively. Thermal ramp rate was , followed by a thermal soak at for one hour. After annealing, the wafer was cooled down to room temperature while remaining under the same flow of Ar and . The top, conformal - SiC insulator layer was then deposited on the pyrolyzed C layer as per the base layer process. Contact and electrode windows were opened in the top insulator through reactive ion etching (RIE) for 5 minutes time: 37 sccm CF 4 and , RF power 200 W , and a base pressure of 50 mTorr . Bond pads were formed on the contact mesas via E-beam evaporation starting with 50 nm of Ti as an adhesion layer followed by 300 nm of Au to facilitate device packaging. The die was then bonded to a Si handle wafer device side down using crystal bond (Ted Pella, Inc.) and the silicon substrate was thinned using deep reactive ion etching (DRIE) to achieve a Si supporting layer. The final process step was to harvest the probes from the Si handle wafer via dissolution of the crystal bond adhesion layer in acetone. The C sandwiched with was characterized for both its material and electrical properties as shown in Figure 6 below. Resistivity measurement was performed using the double-ended resistors from the planar MEA of Figure 1. The resistivity was for a C film thickness of 387 nm and a trace width of .

Figure 6: Fabricated C on - SiC probe characterization data: (a) SEM cross section micrograph after PPF annealing at . Photoresist thickness prior to annealing and of 387 nm after annealing ( vertical shrinkage). (b) Composite optical image of single shank neural probe. (c) SEM plan view micrograph showing electrode and recording tip detail. (d) Raman Spectra of C films on -SiC versus annealing temperature shows a red shift with increasing annealing temperature indicating improved PPF film structure. Reprinted with permission from Micromachines [10].

Figure 6. Figure 6: Fabricated C on - SiC probe characterization data: (a) SEM cross section micrograph after PPF annealing at . Photoresist thickness prior to annealing and of 387 nm after annealing ( vertical shrinkage). (b) Composite optical image of single shank neural probe. (c) SEM plan view micrograph showing electrode and recording tip detail. (d) Raman Spectra of C films on -SiC versus annealing temperature shows a red shift with increasing annealing temperature indicating improved PPF film structure. Reprinted with permission from Micromachines [10].

Electrochemical characterization was performed using the identical methods as the 4 H - and 3C-SiC INI. This time comparison with a standard Pt metal electrode was performed in order to baseline the probe performance to a known standard.

Figure 7: Electrochemical performance of and Pt reference electrode. (a) PPF (C) and Pt EIS impedance vs. frequency and (b) CV data comparison of PPF (C) vs. Pt with same recording area ( ). Note significantly larger curve area for PPF vs. Pt indicating superior charge storage capacity. Reprinted with permission from Micromachines [10].

Figure 7. Figure 7: Electrochemical performance of and Pt reference electrode. (a) PPF (C) and Pt EIS impedance vs. frequency and (b) CV data comparison of PPF (C) vs. Pt with same recording area ( ). Note significantly larger curve area for PPF vs. Pt indicating superior charge storage capacity. Reprinted with permission from Micromachines [10].

MRI Performance of 3C-SiC Neural Interfaces

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

This last section looks at the magnetic resonance imaging (MRI) compliance of cubic silicon carbide (3C-SiC) INI through finite element method (FEM) simulations followed by device exposure to 7 Tesla MRI fields while placed within a brain tissue phantom. The simulations were used to predict induced tissue heating as well as static magnetic field ( ) perturbation to understand image artifact generation, and the MRI experiments to validate the simulation results. The MRI safety of 3C-SiC is compared to other materials commonly used for neural implants such as platinum ( Pt ) and silicon . The outcome is a comparative study with respect to MRI-induced perturbation or image artifacts, and MRI-induced heating is presented to compare the MRI safety of 3C-SiC neural implants to the other materials. Results indicate that further development of an all-SiC INI constructed of 3CSiC and is warranted.

3C-SiC Neural Probe Fabrication and Characterization: As described throughout we developed monolithic planar INI fabricated from cubic silicon carbide ( ) which contained no other material, except gold (Au) which was placed on the contact pads to facilitate wire bonding to the package. This fabrication method can potentially reduce induced current in the electrode which leads to tissue heating and image artifacts. The high thermal conductivity of 3C-SiC ( for SiC on par with pure copper ( ), allows for better heat dissipation especially when compared to . SiC possesses a magnetic susceptibility of -12.87 ppm , a factor that is much closer to brain tissue ( ) when compared to . Thus, SiC has an intrinsic MRI compatibility advantage over conventional probe materials. When one considers the ability to form relatively high-resistivity conductive traces, in comparison with metals, neural probes fabricated monolithically from 3C-SiC possesses a resistance to magnetic perturbation caused by magnetic susceptibility differences and decrease the heat generated by MRI induced currents on the neural probe conductive traces.

Details of the data presented here may be found in Beygi et Al. [11]. Figure 8 shows a portion of the experimental data whereby an all-SiC neural probe displayed negligible image artifacts in a brain tissue phantom at 7 Tesla within an animal bore MRI system at the Moffit Cancer Center, Tampa, FL. Not shown are induced heating simulations which indicate that is predicted to have a SAR value lower than Pt and below the limit established by the FDA.

Figure 7: MRI data from a fabricated 3C-SiC all-SiC neural probe under 7 T MRI scanning. The same MRI sequence used for image artifact numerical analysis was used in this experiment. (a) Photograph of experimental setup (PLA holder, plastic tube, tissue phantom and neural probe). (b) A close-up image of the 3C-SiC neural probe glued on the PLA holder. (c) sagittal view of the neural probe under 7 T MRI. The tip of the probe showed a circular image artifact. (d) coronal view of the neural probe. The shank generated less image artifacts than the pads, due to the metallic pads which would be outside of the brain during probe use and is not an issue. Reprinted with permission from Micromachines [11].

Figure 8. Figure 7: MRI data from a fabricated 3C-SiC all-SiC neural probe under 7 T MRI scanning. The same MRI sequence used for image artifact numerical analysis was used in this experiment. (a) Photograph of experimental setup (PLA holder, plastic tube, tissue phantom and neural probe). (b) A close-up image of the 3C-SiC neural probe glued on the PLA holder. (c) sagittal view of the neural probe under 7 T MRI. The tip of the probe showed a circular image artifact. (d) coronal view of the neural probe. The shank generated less image artifacts than the pads, due to the metallic pads which would be outside of the brain during probe use and is not an issue. Reprinted with permission from Micromachines [11].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

The development of SiC -based neural interfaces has been presented with measured electrochemical performance superior to that of standard Pt electrodes. 4 H - and "all-SiC" monolithic neural interfaces, as well as C derived from pyrolyzed photo resist (PPF) sandwiched with , were used to create these interfaces. Consequently, no metals or polymers are in contact with brain tissue which is highly significant since this is known to negatively impact long-term in-vivo reliability and performance. Table 1 provides a comparison between the results summarized here and contemporary neural interfaces showing the exceptional performance of our SiC neural interfaces.

Table 1: Electrochemical properties of SiC and common neural electrode materials.

Material | Recording area (kμm²) | Impedance @1kHz (kΩ) | Charge storage capacity* (mC/cm²)
4H-SiC [4] | 496 | 375 | 11
3C-SiC [12] | 1.9 | 165 | 74
C/a-SiC [10] | 1.9 | 25 | 14,160
Pt [10] | 1.9 | 104 | 12
PEDOT/CNT [13] | 2.83 | 15 | 6
Carbon-nanotube fiber [14] | 1,450 | 141 | 372
Graphene Fiber [15] | 0.749 | 38 | 798
IrOx [16] | 0.177 | 133 | 29
TiN [13] | 2.83 | 55 | 5

Charge Storage Capacity (CSC) value sum of anodic and cathodic phases.

In addition to the electrochemical performance of SiC neural interfaces, a preliminary study (numerical and experimental) of the MRI compatibility of the all- SiC neural interface showed very promising performance in a 7 T animal bore MRI tool indicating that the present limit of 3 T, which greatly reduces image resolution, may be exceeded. In all cases additional research is planned in animal models (rodent) to further demonstrate the utility of SiC neural interfaces for long-term human implant applications.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.195.pdf

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Beygi, M.; Dominguez-Viqueira, W.; Feng, C.; Mumcu, G.; Frewin, C.L.; La Via, F.; Saddow, S.E., "Silicon Carbide and MRI: Towards Developing a MRI Safe Neural Interface," Micromachines 2021, 12, 126.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 204-208

doi: 10.4028/p-98r1yh

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-03-16

Accepted:
2022-03-16

Online:
2022-05-31

Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

Cristiano Calabretta , Alessandro Pecora, , Marta Agati , Stefania Privitera , Annamaria Muoio , Simona Boninelli and Francesco La Via

Keywords: 4H-SiC; Laser Annealing; XeCl; dopant activation; phosphorus; aluminum; defects; TEM; Raman; SEM;

Abstract

This paper discusses a novel annealing technique for 4 H -SiC implants which involves the use of pulsed XeCl laser ( ). In particular, an absorbing graphitic coating is used to protect the sample from surface atoms desorption or phase separation. Both conventional furnace annealing and laser annealing on P and Al implants, commonly employed for source and body in metal-oxidesemiconductor field-effect transistors (MOSFETs), were examined through Transmission Electron Microscopy (TEM), -Raman spectroscopy and Scanning Electron Microscopy (SEM). It is shown that the implant activated through traditional thermal annealing at for 30 min has a large network of dislocation loops, while they do not appear to be present in the laser annealed implant. Through Raman spectroscopy and SEM investigations both the crystalline quality of the laser annealed sample and the integrity of the surface were attested.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

As a result of new developments in SiC crystal growth and process technologies, the manufacturing of power MOSFETs has begun. Source and body regions in MOSFETs are achieved by ion implantation and subsequent mandatory thermal annealing at . However, in this temperature regime generation of C interstitial-vacancies couples is registered along the whole epitaxial layer, affecting carrier mobility and lifetime in channel region. Particularly, carbon vacancies have been found to be the origin of the so called and deep energy levels: the main carrier lifetime killers in 4H-SiC [2]. In addition, a network of dislocation loops is also produced in the implant projected range together with not satisfactory activation rates [3-4]. To work around these issues, pulsed-laser-based methods have been applied for post-implant annealing of P and Al doped 4H-SiC epitaxial layers in order to recover the crystal structure and to electrically activate the doping species. Although this technique has proven effective activation results, it has not yet reached maturity as industrial process, due to the scarce control over the surface damage caused by laser radiation-SiC interaction. Unlike silicon, 4 H -SiC does not favor post-melting epitaxial regrowth [5-6-7]. This work, therefore, shows a pioneering method to acquire a substantial control over irradiated surface quality, allowing to implement implanted 4 H -SiC crystalline and electrical properties.

Materials and Methods

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

The experiments were carried out on a Cree-supplied SiC wafer with a nitrogen concentration of . Then, a epitaxial layer was grown along the (0001) off-axis direction through low pressure hot wall chemical vapor deposition. Source P ion implantation was performed at with energies varying from 30 to 200 keV and fluences ranging from to in order to generate an almost uniform doped layer thick with a concentration of , while body Al implant was characterized by thick implanted layer [8]. Photoresist was spin coated on sample surfaces and pyrolyzed at in order to achieve graphitization on surface. Final 90 and 180 nm thick layers were deposited on double P and Al implanted SiC samples. Once irradiated by means of a XeCl laser source ( ) with 40 Hz pulse and 1000 shots/point, graphite was removed through oxygen plasma attack. For comparison, some samples were left uncoated and another underwent heat treatment at for 30 min . Experimental investigation was carried out by means of TEM and SEM microscopy, and micro-Raman spectroscopy through He-Cd ( ) laser source.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

The technique exploits irradiations over a graphitic absorber layer. Indeed, thanks to its melting temperature and high absorption coefficient, graphite is the best candidate to fully absorb laser radiation, allowing a heat diffusive regime along the underlying implanted . Fig. 1 displays the XTEM acquisition from two samples subjected to furnace annealing and graphite assisted laser annealing at .

Figure 1. XTEM images of two samples processed with conventional thermal annealing at for 30 min and laser annealing at shots/point.

Figure 1. Figure 1. XTEM images of two samples processed with conventional thermal annealing at for 30 min and laser annealing at shots/point.

In Fig. 1a the sample processed at for shows dense dislocation loops network related to the 250 nm thick source region as a consequence of point defects aggregation stimulated by high temperature annealing, under thermal equilibrium conditions. The 550 nm thick body region, below the source implant, is affected by rear aggregates and follows the lower Al implant concentration. Indeed, owing to the lower implanted dose, the amount of interstitials available for the generation of extra-planes is consequently lower in body region. In Fig. 1b laser annealed sample presents limited source region defectiveness and the body region is remarkably free from dislocation loops. It can be deduced that, if on the one hand the shorter diffusion times result in a smaller dislocation loops size distribution, on the other hand it is known that thermal non-equilibrium regime is effective in preventing generation of point defects. Micro-Raman spectroscopy attested SiC characteristic Raman modes restoration, as indication of the effective crystalline recovery following laser treatment. In particular, Fig. 2a exhibits how lattice subjected to laser annealing is sensible to the applied laser energy density. The analyses were performed through a He-Cd laser source ( ) on the samples after graphite remotion by oxygen plasma etching. The UV laser was required to investigate the two implanted layers and minimize the signal from underlying substrate and epitaxial layer. Following a statistic on the average spectrum extracted from -Raman maps under backscattering conditions, the polynomial fits with confidence bands of transverse optic full width at half maximum (FWHM) are displayed. From comparison it emerges that FWHM shows improving trend with graphitic layer thickness. When irradiated under 180 nm graphitic layer, SiC exhibits , slightly lower than in furnace annealed SiC, thus corroborating TEM analysis. Samples subjected to laser annealing with uncoated surface exhibit FWHM decreasing with energy up to threshold. However, such behavior could be attributed to implant etching and SiC oxidation phenomena exposing the underlying SiC epitaxy. Above , the progressive increase in FWHM testifies how SiC is affected by melting processes which determine crystalline deterioration.

The covering effect of the graphite layer on SiC is displayed in SEM micrographs taken on uncoated as well as 180 nm graphite coated samples and underwent laser annealing at the energy density of . Indeed, to support the reported Raman results, Fig. 2b depicts how high temperatures stimulate the mobility of surface atoms, triggering their desorption and promoting consequent surface degradation. Furthermore, the spherical agregates discussed above are shown and were detected with an average size of 131 nm and with of surface coverage. Such spheres detected on the surface have been identified as spheres through Electron Energy Loss Spectroscopy (EELS) analysis and are the consequence of surface active oxidation with the oxygen present in the chamber [9]. Figure 2c, shows the 180 nm graphite covered implant surface once the residual graphite has been removed from the sample by oxygen plasma etching. It turns out how the sample was rather preserved than the previous by the overlap of graphitic coating. These pictures demonstrate the efficacy of the coating media in preserving SiC surface during laser shots.

Figure 2. a) FWHM trend of mode with respect to energy density for different coating thicknesses. SEM micrographs acquired on sample surface underwent laser annealing b) with no coating and c) with 180 nm coating.

Figure 2. Figure 2. a) FWHM trend of mode with respect to energy density for different coating thicknesses. SEM micrographs acquired on sample surface underwent laser annealing b) with no coating and c) with 180 nm coating.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

This work has been supported by the European ECSEL JU project REACTION (grant agreement n. 783158).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

The findings inherent to the development of an innovative laser annealing approach in order to avoid damage of the implant surface were disclosed in this study. The deposition of a graphitic coating layer is used in this approach. MOSFET's source and body implants were exposed to varying XeCl pulsed laser intensities and graphitic coating thicknesses. It was observed that using a graphite thickness of 180 nm protects the implant from surface erosion at while also demonstrating superior crystalline quality in terms of the FWHM of the Raman (TO) mode with respect to conventional furnace annealed implant. TEM analysis demonstrated the absence of extended defects within the implanted area.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.204.pdf

A. Severino, et al. Effects of Thermal Annealing Processes in Phosphorous Implanted 4H-SiC Layers Mat.Sci Forum, 407, 2019, 963.

R. Nipoti, et al. Defects related to electrical doping of 4 H -SiC by ion implantation. Mater. Sci. Semicon. Proc. 78, 2017, 13-21.

C. Calabretta, Thermal annealing of high dose p implantation in 4H-SiC, Mater Sci Forum, 963, 2019, 399-402.

V. Šimonka, et al. Transient model for electrical activation of aluminium and phosphorusimplanted silicon carbide. J. Appl. Phys.123, 2018, 325701.

Boutopoulos et al. Laser annealing of Al implanted silicon carbide: Structural and optical characterization. Appl. Surf. Sci. 2007, 253, 7912-7916.

F. Mazzamuto et al. Silicon Carbide recrystallization mechanism by non-equilibrium melting laser anneal. Mater. Sci. Forum 2016, 858, 540-543.

C. Calabretta et al. 4H-SiC MOSFET source and body laser annealing process, Mater Sci Forum,1004, 2020, 705-711.

P. Fiorenza et al. High-Resolution Two-Dimensional Imaging of the 4 H -SiC MOSFET Channel by Scanning Capacitance Microscopy, Nanomaterials 11, 2021, 1626.

C. Calabretta, et al. Laser Annealing of P and Al implanted 4H-SiC epitaxial layers, Materials, 12(20), 2019, 3362.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 209-213

doi: 10.4028/p-nx5r53

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-25

Accepted:
2022-03-09

Online:
2022-05-31

A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

Xavier Gay , Norbert Bay , Franck Delahaye , Stefan Hansen and Holger H. Kuehnlein

RENA Technologies GmbH, Höhenweg 1, 78148 Gütenbach, Germany

Xavier.Gay@rena.com, Norbert.Bay@rena.com, Franck.Delahaye@rena.com, Stefan.Hansen@rena.com, Holger.Kuehnlein@rena.com

Keywords: electrochemical porosification, wet chemistry, single side processing

Abstract

In this paper we present a novel tool layout for wet chemical processing of porous silicon carbide layers. The novel tool concept includes single side processing without edge exclusion. There is no need to contact the backside of the wafer. We show SEM cross sections of the porous layer made by different currents densities. With increased current density the porosity increases. After optimization of the process conditions, we achieve a layer thickness non-uniformity of .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

Silicon carbide ( SiC ) is the material of choice for next generation power devices in fast growing applications like electromobility and renewable energies. Due to its inertness, SiC cannot be easily structured by wet chemical processes at room temperature. A porous SiC layer can be obtained by wet electrochemical treatment of SiC [1]. The porous SiC layer can be used e.g. for structuring purposes [2] or e.g. as seed layer for the growth of a SiC epitaxial layer with improved properties .

Tool Description

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

In this paper, we present a novel tool for SiC wet etching named ACE (Advanced electro-Chemical Etching). It uses a wet electrochemical process to generate a porous SiC layer and allows for the single side processing of SiC substrates. The double-tank electrochemical cell is already well known as state-of-art concept for semiconductor porosification [5]. In this double-tank principle, each side of the wafer is contacted with a separated electrolyte tank system. In one electrolyte tank system the wafer is contacted by the electrolyte and in the other electrolyte tank system the electrochemical porosification process takes place. This conventional set up requires sealing of the wafers which complicates the implantation of the system into

Figure 1: Schematic of the tool principle the numbers refer to the reaction as described in the text

Figure 1. Figure 1: Schematic of the tool principle the numbers refer to the reaction as described in the text

a full automatic tool. Moreover, the sealing does not allow to etch the wafer all the way to the edge as required for some applications. In this paper, we demonstrate a new tool concept where only one side of the wafer is contacted with two separated electrolyte tank systems as depicted in figure 1. One main advantage of the novel tool concept is that only one side of the wafer is contacted with chemistry which ensures single side processing. A general view of the tool showing the handling system is shown in figure 2. The wafer is in contact with the electrolyte bath on the bottom side only. It is hold by a simple handling system parallel to the medium surface and positioned over the etching bath. The
motion and rotation of the wafer allows for a homogeneous full area porosification of the SiC wafer surface without edge exclusion, an important feature not available in most electrochemical setups. The system does not require the wafer to be metallized for contacting and works without the need of complex mechanical handling and sealing.

Figure 2: Table top version of advanced electro-chemical etching (ACE) tool.

Figure 2. Figure 2: Table top version of advanced electro-chemical etching (ACE) tool.

SiC Porosification

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

The electrochemical porosification of SiC is a two-step process. In the first step SiC is electrochemically oxidized which is described in Equation 3a and 3b. In the second step, the formed is chemically dissolved which is described in equation 3c. The holes which are needed for the oxidation process are laterally transported through the wafer and generated at the wafer surface in the opposite tank (see equation 2). At the electrodes in each tank, the holes are generated and absorbed to close the electrical circuit (equations 1 and 4).

Experimental Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

The described test setup is used to process wafers. The wafer material is 4 H SiC with c-axis tilt. The n-type doped (N) SiC has a resistivity in the range of 12 to . The wafer thickness is . A diluted HF based medium is used as etching solution. The current density is determined as the total current over the contact surface between the porosification bath and the wafer and is varied in the range of a few tens of . The circulation flow and the distance between wafer and processing bath are optimized for a good wetting of the wafer surface. The porosity of the obtained layer is estimated by using the measured thickness and the weight difference before and after processing.

A first trial with a low current density is performed. The SiC wafer is processed on its full surface for approximately 30 min . A well-defined porous SiC layer is obtained on the wafer surface as can be seen in figure 3. The pore structure is homogenous over the complete porous layer thickness.

A scanning electron microscope picture of the obtained pore structure can be seen in figure 3a and b .

Figure 3: Scanning electron microscope images of the porous SiC layer with a low current density overview a) detailed view from the top of the layer b)

Figure 3. Figure 3: Scanning electron microscope images of the porous SiC layer with a low current density overview a) detailed view from the top of the layer b)

In a further step, we investigate the effect of the current density on the porosity and on the pore structure. Samples with a mid and high current density are prepared and characterized. The pore size gets bigger with increasing current density as it can be seen on figure 4 . The porosity is also found to increase with increasing current density. This shows that the porosity of the obtained porous layer can be controlled by adjusting the current density in our test setup.

Figure 4: Scanning electron microscope pictures of the obtained porous SiC layer for a) low b) mid and c) high current densities

Figure 4. Figure 4: Scanning electron microscope pictures of the obtained porous SiC layer for a) low b) mid and c) high current densities

To investigate the non-uniformity of the etching, the thickness of the porous layer was determined by SEM measurements along the diameter of the wafer. The results are shown in figure 5. The results confirm the capability of the system to etch the wafer all the way to the edge, independently from the process settings. However, an optimization of the parameters was necessary to achieve satisfactory process uniformity. The non-uniformity is calculated as the ratio (max .

Figure 5: Porous layer thickness of 3 SiC wafers with different process conditions.

Figure 5. Figure 5: Porous layer thickness of 3 SiC wafers with different process conditions.

In table 1 we have summarized our results. Process condition C results in a significant better layer non-uniformity. We have achieved a very good layer non-uniformity of .

Table 1: Summary of process results

process
average porous layer
[μm]
weight loss
[mg]
porosification time
[min]
porosity
[%]
layer non-uniformity
[%]

Process condition A
4,08
13,1
30
5,8
27

Process condition B
7,69
38,8
30
9,2
29

Process condition C
9,76
82,8
30
15,4
10

Conclusion and Outlook

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

In this work, we show a new tool layout for a single-sided electrochemical etching process for SiC substrates. The system does not require the wafer to be metallized for contacting and works without the need of complex mechanical handling and sealing. Initial trials show that this setup allows for porosification of the SiC wafer over its full area without edge exclusion. Typical layer thickness of several can be achieved. The porosity of the obtained layer can be varied by varying the applied current density and other process conditions. A low non-uniformity is achieved with optimized process conditions. Further work is ongoing to improve the porosification non-uniformity and removal rate.

This shows the feasibility of such a system for applications where a porous SiC layer is of interest.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.209.pdf

J.S. Shor et al, Appl. Phys. Lett. 62 (1993), 2836

M. Leitgelb et al, ECS Journal of Solid State Science and Technology, 5 (10) P556-564 (2016)

N. S. Savkina et al, Semiconductors, Vol. 35, No2, 2001, pp. 153-157

S.E. Saddow et al, Appl. Surface Science 184, 72-78 (2001)

Gautier et al, Nanoscale Research Letters, 2012 7, 367

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 214-218

doi: 10.4028/p-n9v122

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-19

Revised:
2022-02-25

Accepted:
2022-02-28

Online:
2022-05-31

Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

M. Italia , I. Deretzis , A. Nastasi , S. Scalese , Antonino La Magna M. Pirnaci , D. Pagano , D. Tenaglia , P. Vasquez ,

¹Consiglio Nazionale delle Ricerche, Istituto per la Microelettronica e Microsistemi (CNR-IMM), Z.I. VIII Strada 5, I-95121 Catania, Italy

STMicroelectronics Stradale Primosole 50, I I-95121 Catania, Italy

E-mail: markus.italia@imm.cnr.it, ioannis.deretzis@imm.cnr.it, alfio.nastasi@imm.cnr.it, silvia.scalese@imm.cnr.it, antonino.lamagna@imm.cnr.it, massimo.pirnaci@st.com, daniele.pagano@st.com, dario.tenaglia@st.com, patrizia.vasquez@st.com

Keywords: SiC, plasma etching processes, multi-scale simulation, Kinetic Monte Carlo methods.

Abstract

Manufacturing of Silicon Carbide ( SiC ) based devices will soon require the accuracy and control typical of the advanced Si based nanoelectronics. As a consequence, the processes development will surely benefit of technology computer aided design (TCAD) tools dedicated to the current and future SiC process technologies. Plasma etching is one of the most critical and difficult process for optimization procedures in the micro/nano fabrication area, since the resultant 2D (e.g. in trenches) or 3D (e.g in holes) profiling is the consequence of the complex interactions between plasma and materials in the device structures. In this contribution we present a simulation tool dedicated to the etching simulation of SiC structures based on the sequential combination of a plasma scale global model and feature scale Kinetic Monte Carlo simulations. As an example of the approach validation procedure the simulations are compared with the characterization analysis of particular real process results.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

Process Technology Computer Aided Design (TCAD) codes are fundamental tools for speedup the assessment of the process parameters against the requirements of the next-coming generation of electronics device and they are routinely applied by the R&D teams operating in the field of Si based micro- and nano-electronics. The extraordinary recent development of SiC devices technology has led the specifications for processes' accuracy and control for their manufacturing close to the ones of the advanced Si based nanoelectronics. This progress of SiC based technology will be soon increasingly supported by dedicated TCAD tools with proper model and calibration for this compound wide band gap material. Topography manipulation in 2D (e.g. in trenches profiles) or 3D (e.g in holes profiles) geometries, obtained with the exposition of a pre-existing structure to etchant plasmas, is the results of the complex kinetics due to the interactions between plasmas and materials, and the development of predictive simulations' methods for this directional etching process is particularly challenging.

A multiscale methodology is necessary for an effective TCAD approach since this chemicalphysical simulation should predict the morphology of the etched profile at the device feature scale (i.e. in the range of dimensions) starting from an input which is a combination of the initial (again at the feature scale) geometry and the process parameters, which generate the plasma conditions at the reactor scale ( range). Therefore, the full predictivity of the plasma processes relies on the suitable combination of two simulating approaches dealing with these to scales: 1) the status of the plasma generated in the reaction chamber and 2) the effect of the exposition of the processed sample to the plasma itself. In this contribution we present a simulation tool dedicated to the plasma simulation in SiC based device technology. Simulation results are compared with real processes microscopic analysis for equivalent macroscopic process parameters in order to demonstrate the reliability of the approach.

Model Description

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

The simulation method relies on the sequential combination of the following two approaches [Model 1) and Model 2)]. Model 1) operates at the macroscopic scale of the reactor and its scope is predicting as volume averages: the ion and neutral particle distributions, the electron density field, and the electron temperature field as a function of the process parameters (i.e. the chamber pressure, the fluxes in Standard Cubic Centimeters per Minute (SCCM) of the gases at the inlet, the power released by the electrodes in order to activate the chemical and ionization reactions in the plasma see [1]). The output quantities of this plasma model are fundamental for the correct determination of the local fluxes of the active species used as input parameters at the structure feature scale. The Model 2) (feature scale model) simulates (with an in-cell Kinetic Monte Carlo (KMC) simulation technique see Refs. [2]) the evolution of the microstructures (e.g. the evolution of the etching profile) starting from the "as prepared" sample morphology and materials implementing a stochastic approach for the surface reactions between the plasma component and the atoms in the substrates
The developed version overcomes some limitations of a previous tool [2], and specialized to Si substrate in order to allow: a) the application to the phenomenology in a compound semiconductors (i.e. SiC [3,4]) or more in general a two atoms substrate (see fig. 1) instead of a Si substrate and b) a generic input gas composition instead of a fixed "hardcoded" one.
For this general application and the Models 1) and 2) coupling, a python-based algorithm is designed for the automatic creation and solution of any global plasma models whereas the specific reactions' set is not embedded in the python code but it can be provided by an user defined flexible database. Different chains of surface reactions are activated at the feature scale by the plasma component interacting with the Si and C atom of the substrates (see Fig. 1), they include: neutrals' absorption, ion activated events (etching and sputtering), by-products deposition.

Fig. 1 Upgrade of the plasma etching simulation code scheme from the single atom substrate to a two atoms substrates: left side single element substrate (e.g. Si), right side compound substrate (e.g. SiC). In order to effectively consider separated Si and C reactions' path, the simulation box is divided in a chessboard-like distribution of cubic "cells" with a length where is the atom density [atoms ] of the SiC material. In the scheme orange cells are occupied by carbon atoms and blue cells by silicon atoms and, as a consequence, due to the associated length, each cell contains the average value of one atom (atomistic resolution). Some possible events for the different reactions chain activated by the events which initiated by the C or Si atoms are indicated.

In the application of the simulation discussed the next section (i.e. a plasma obtained with a in mixture) the model complexity (i.e. the different Monte Carlo particle considered in the Model 2)) comprises:

22 cell types (surface coverage types): , ;

20 neutrals: , ;

10 ions: ;

22 by-products: , .

Fig. 2 a) FIB analysis in cross section view of the post-processed sample in the large opened area position; b) SEM analysis in cross section view of the post-processed sample in the trench position.

Fig. 2. a) FIB analysis in cross section view of the post-processed sample in the large opened area position; b) SEM analysis in cross section view of the post-processed sample in the trench position.

Impinging of neutrals activate the coverage species formation which detach, as by products, an increased yield with respect to the substrate species (ion-neutral synergism) due to ion-surface interaction events. Subsequence of events is randomly determined by means of the relative particle density estimated by the Model 1) [2].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

The simulation code has been validated comparing code prediction with experimental characterizations of etching processes where plasma is generated loading the chamber with a mixture. The pre-processing system is composed by a substrate and a film acting as an Hard-Mask (HM) material. Different geometries have been opened in the HM film in the same wafer in order to study visibility effects on the local etching yield. In fig. 2 we show two images obtained in cross section view with a Focused Ion Beam (FIB, panel a)) and Scanning Electron Microscopy (SEM, panel b) for a large area and a trench geometry after the same etching process. Microscopy analysis evidences that the average etch rate (ER) is smaller in the trench with respect to the one measured in the open area location evidencing a limited but measurable shadowing effect due to the reduced average visibility solid angle: ER(trench)/ER(open air) . Moreover, a double step profile is evidenced at the edge of the mask for both geometries.

Fig. 3 EDX analysis in plan (top panel) and cross section (bottom panel) view of the post-processed samples in the trench position. Elements' contrast is indicated by the colours: green O , yellow Si , red C.

Fig. 3. EDX analysis in plan (top panel) and cross section (bottom panel) view of the post-processed samples in the trench position. Elements' contrast is indicated by the colours: green O , yellow Si , red C.

The hypothesis that the double step feature is due to the presence of an additional film (e.g. a resist residual) in the post-processed sample has been excluded by the Energy Dispersive X-Ray (EDX) analysis (fig. 3) which demonstrates that the mask after the process is made purely by .
A "virtual" process completely equivalent to the one discussed above has been simulated with our tool. The pre-etching structures can be inserted in our code as geometry input using a simplified CAD (see fig. 4) or directly uploading SEMs images with proper pixel contrast. In the present analysis we have used blanked structure to simulate large area case and a simplified rectangular shaped mask (Fig. 4) in order to verify if a pre-existing residual resist layer can explain the SEM and EXD results. The final simulated shape evidences also in the simulation a double step features while the Resist layer is completely removed in agreement with the experimental data. Moreover, also shadowing effect is reproduced by the KMC simulation.

Fig. 4. Simulation results of a plasma etching process of a trench with a plasma. The initial system is assumed to be an ideal rectangular hard mask with a residual Resist material on top. Simulation is overlapped with SEM analysis of the same process. Experimental SEM cross section is overlapped in transparency. A limited tapered profile and a reduced vertical etching yield with respect to a planar substrate (shadowing commonly cited as RIE-lag for a reduction) is evidenced by the simulation which consider explicitly the visibility effects.

Fig. 4. Simulation results of a plasma etching process of a trench with a plasma. The initial system is assumed to be an ideal rectangular hard mask with a residual Resist material on top. Simulation is overlapped with SEM analysis of the same process. Experimental SEM cross section is overlapped in transparency. A limited tapered profile and a reduced vertical etching yield with respect to a planar substrate (shadowing commonly cited as RIE-lag for a reduction) is evidenced by the simulation which consider explicitly the visibility effects.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

We have presented a multiscale methodology for the simulation of plasma etching in SiC structure. Comparisons with experimental analyses of the real process, by varying the initial microstructures geometries and the process parameters have been performed in order to validate the numerical tool. The code can be effectively applied in the process optimization where the vertical etching yield and profile shape (e.g. the angle with respect to the hard mask) are critical features for the devices performance (see Fig. 2). Moreover, the coupling approach can be also extended to the atomistic process simulations [5] for more accurate predictions.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

The authors thank the project MADEin4 (Metrology Advances for Digitized Electronic Components and Systems Industry 4.0) that has received funding from the ECSEL-JU under grant agreement No 826589.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.214.pdf

A. Pateau, A Rhallab, M-C.Fernande, M. Boufnichel and F. Roqueta, Modeling of inductively coupled plasma Ar plasma discharge: Effect of on the plasma kinetic properties, Jour, Vac. Sci. & Tech. A 32, 021303 (2014).

Y. Haidar A. Rhallab A. Pateau, A. Mokran, Fadia Taher, , M. Boufnichel and F. Roqueta; Simulation of cryogenic silicon etching under SF6/O2/Ar plasma discharge, J. Vac. Sci. Technol. A 34, 061306 (2016)

L. Jianga, R. Cheung R. Brown and A. Mount; Inductively coupled plasma etching of SiC in SF6/O2 and etch-induced surface chemical bonding modifications, J. Appl. Phys. 93, 1376 (2003)

K. Racka-Szmidt, B. Stonio, J. Zelazko, M. Filipiak and M. Sochacki; Review: Inductively Coupled Plasma Reactive Ion Etching of Silicon Carbide, Materials 15, 123, (2022).

G. Fisicaro, C. Bongiorno, I. Deretzis, F. Giannazzo, F. L. Via, F. Roccaforte, M. Zielinski, M. Zimbone, and A. La Magna, Genesis and evolution of extended defects: The role of evolving interface instabilities in cubic SiC, Appl. Phys. Rev. 7, 021402 (2020).

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 219-223

doi: 10.4028/p-6z36aj

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-24

Accepted:
2022-02-24

Online:
2022-05-31

Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1062.219.pdf

Clément Berger , Daniel Alquier , Jean-François Michaud

Université de Tours, GREMAN UMR-CNRS 7347, INSA Centre Val de Loire, 16 rue Pierre et Marie Curie, 37071 TOURS Cedex 2, France

clement.berger@univ-tours.fr, daniel.alquier@univ-tours.fr and 'jean-francois.michaud@univ-tours.fr

Keywords: Titanium, Ohmic contact, Laser annealing, Interfaces, 4H-SiC

Abstract

This work is focused on the fabrication of Titanium-based ohmic contacts by Laser Thermal Annealing (LTA) on n-type silicon carbide ( ). Their morphologies and electrical properties were studied by using two sets of parameters impacting the laser pulse overlap. With both sets, the ohmic contact transition was reached. The high overlap conditions produced a massive degradation of the contact morphology by leaving uncovered SiC. An optimisation of the annealing parameters was successfully performed by reducing the overlap. With the low overlap configuration, a specific contact resistance of was measured for a fluence of with a satisfying contact surface morphology.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.219.pdf

Silicon carbide ( SiC ) is well known as being an excellent material for working at high frequency, high temperature or at high power due to its wide bandgap and high electrical field [1]. After years of investigations, the quality of became high enough to commercialize devices able to work in such expected applications.

In order to improve the energy efficiency of devices elaborated on larger and, hence, thicker SiC substrates, impacting their electrical performances due to the substrate resistance, the use of a thinned substrate is necessary. This involves achieving the ohmic contact at the end of the process as manipulating a thin wafer remains challenging. Nevertheless, the ohmic contact formation on wide band gap semiconductors is still a topic that can be improved to reduce its resistivity, which plays on the on-state resistance of devices [2, 3]. Commonly on SiC, a high temperature annealing is required to fabricate ohmic contacts on the substrate's backside. Then, a contact annealing that does not affect the wafer frontside is then mandatory. The laser irradiation is certainly one of the best alternative to succeed in this task [4, 5]. By employing optimized laser parameters, simulations of laser thermal annealing (LTA) demonstrated that the irradiated contact surface was heated up to while keeping the opposite face at low temperature ( ) [6].

Recently, several investigations were focused on ohmic contact formation by LTA. As it gives the best ohmic contact by Rapid Thermal Annealing (RTA), Nickel (Ni) is the most widely investigated to form ohmic contact by LTA. Nevertheless, the morphology seems to be strongly inhomogeneous by creating a segregation of the Ni phases leaving uncovered SiC , as demonstrated by Rascunà et al. [7]. We experimented to anneal Ni contacts but, in our case, the morphology was also strongly inhomogeneous (not shown here). Titanium (Ti) is also a candidate to form ohmic contact as it can form phases with both Si and C , that could improve the contact morphology compared to Nickel. A Specific Contact Resistance (SCR) of , determined by Transfer Length Method (TLM), has been already demonstrated using Ti [8].

In this study, the electrical and morphological characterisations will be performed on Ti-based ohmic contact on n-type 4H-SiC, formed by LTA. Based on our experience, a lot of annealing parameter combinations are capable to reach the ohmicity. Nevertheless, here we investigated the contact behaviour as a function of the laser fluence with two sets of pulse overlap by adapting the laser scanning speed and the distance between irradiated lines.

Experimental

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Onto the Si -face of a production-grade wafer from TankeBlue, a vertical isolation was achieved by the epitaxial growth of a thick non-intentionally doped layer. Then a highly nitrogen-doped layer was grown on the top of the isolation. The wafer was cut into samples. Firstly, a RCA cleaning was performed. Between each bath, samples were dipped into diluted fluoridric acid (HF) and rinsed with deionized water. A 100 nm thick Ti layer was deposited onto by DC magnetron sputtering and then it was irradiated thanks to a microPRO OFC tool from 3D-Micromac equipped with a frequency-tripled YAG pulsed laser ( 355 . The beam produced has a near square footprint with a top-hat energy density profile. The irradiations were performed at 30 kHz with a scanning speed of 185 or under atmosphere. To evaluate the electrical performance of the contacts, circular TLM structures were fabricated as presented on Fig. 1. To do so, the TLM structures were fabricated by the etching of the spacings thanks to Ion Beam Etching (IBE) and, as a refill layer, 300 nm Aluminium (Al) were deposited onto the TLM patterns by a lift-off process.

Fig. 1: Schematic representation of the fabrication process used to define the TLM structures.

Fig. 1. Schematic representation of the fabrication process used to define the TLM structures.

Results and Discussion

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Contacts annealed at (high overlap)
Prior to the electrical characterisations, an investigation of the contact morphologies was performed by Scanning Electron Microscope (SEM). The aim is to select conditions compatible with industrial throughput that generate homogeneous contact with regular morphology to limit the failure due to the contact. After the irradiation, samples were dipped into HF to remove the unreacted Ti , without etching the titanium silicides and carbides, which allows to highlight the reaction between Ti and SiC . First, on Fig. 2, a set of annealing was performed at with a distance between the irradiation lines of . We observed a satisfying surface morphology only for the lowest annealing at . With the fluence increasing, a segregation between the contact and SiC appears, creating holes into the contact. An Energy Dispersive Spectroscopy (EDS) analysis of the holes (not shown here) did not reveal the presence of titanium. It is assumed that the titanium turned into liquid phase under the irradiation and was rejected from the centre of the irradiation and crystalised quickly around it. From , the morphology is critically impacted by the high pulse overlap, the titanium forms thick lines following the laser scanning.

Fig. 2: SEM images of Ti annealed between 3.0 and at .

Fig. 2. SEM images of Ti annealed between 3.0 and at .

Electrical measurements were performed on test structures to find conditions that lead to ohmicity. Only the I-V characteristics of contacts annealed at 3.0 and are presented on Fig. 3, because the etching of contacts produced at higher energy densities was not satisfying for the electrical measurements. In the case of the contact annealed at , the I-V curve is linear, that indicates the successful ohmic contact formation. Nevertheless, based on SEM observations, an optimisation of the annealing parameters must be done to improve the contact morphology by reducing the overlaps.

Fig. 3: I-V characteristics for a tests structures made of Ti/4H-SiC contact annealed at .

Fig. 3. I-V characteristics for a tests structures made of Ti/4H-SiC contact annealed at .

Contacts annealed at(low overlap)

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A second annealing setup was performed by increasing the scanning speed to and the distance between lines to . The SEM observations are presented on the Fig. 4 after the HF treatment to reveal Ti-Si-C phases. The contact annealed at shows large uncovered SiC between irradiation lines that indicates a lack of energy to form silicides and/or carbide due an inadequate distance between lines. At , the contact morphology appears highly smooth and then degrades with the increasing of the fluence, mostly on the overlapping areas. AFM measurements on (not shown here) determined a roughness between for the , annealing that is comparable with a classical RTA treatment. At , thick Ti-Si-C phases are formed on the overlapping area and a lot of dark spots, corresponding to a lack of Ti, with an average size of 450 nm are observed.

Fig. 4: SEM images of Ti annealed between 3.0 and at .

Fig. 4. SEM images of Ti annealed between 3.0 and at .

The I-V characteristics for the spacing equals to of contacts annealed from 3.0 to are presented on Fig. 5(a). The current evolves with the increasing of the fluence, which reveals a modification of the contact composition. From , the I-V characteristics are linear, indicating the ohmicity is reached. The Fig. 5(b) presents the evolution of the SCR with the fluence. The optimal SCR of was obtained at , which represents an improvement compared to the literature [8]. From , the contact electrical performances degrade which can be explained by a degradation of the morphology. For such high energy densities, with our setup, no optimisations led to satisfying morphology even with overlap close to 0 , dark spots are always presents. Probably that a thickness modification could help to improve the contact homogeneity.

Fig. 5: (a) I-V characteristics between adjacent TLM pads for a contact annealed at several fluences. (b) Evolution of the SCR as a function of the annealing fluence for contacts.

Fig. 5. (a) I-V characteristics between adjacent TLM pads for a contact annealed at several fluences. (b) Evolution of the SCR as a function of the annealing fluence for contacts.

Summary

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Laser irradiations on contact have been investigated on n-type substrate. The overlap conditions play an important role on the contact morphology. With a high overlap, ohmic contact were produced but the morphology quality was poor. A consequent decrease of the overlap allowed to massively improve the contact surface while keeping the ohmic properties. A specific contact resistance of was reached at . This value is 3 times lower than the literature on laser annealing of Ti contact but, the fluence almost is twice higher. The origin of this improvement could be linked with a structural contact modification which will be investigated in the future.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.219.pdf

This work was carried out in the framework of the ECSEL JU project WInSiC4AP (Wide Band Gap Innovative SiC for Advanced Power), grant agreement n. 737483.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.219.pdf

T. Kimoto, J. A. Cooper, Fundamentals of silicon carbide technology: growth, characterizaton, devices and applications, Wiley, Singapore, 2014.

G. Greco, F. Iucolano, F. Roccaforte, Ohmic contacts to Gallium Nitride materials, Applied Surface Science 383 (2016), 324-345.

C. M. Zhen, X. Q. Wang, X. C. Wu, C. X. Liu, D. L. Hou, Au/p-diamond ohmic contacts deposited by RF sputtering, Applied Surface Science 255 (2008), 2916-2919.

R. Rupp, R. Kern, R. Gerlach, «Laser backside contact annealing of SiC power devices: A prerequisite for SiC thin wafer technology », 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD), Kanazawa, 2013, 51-54.

F. Mazzamuto, S. Halty, H. Tanimura, Y. Mori, Materials Science Forum 858 (2016), 565-568.

C. Berger, J. F. Michaud, D. Chouteau, D. Alquier, Laser annealing simulations of metallisations deposited on 4H-SiC, Material Science Forum 963 (2019), 502-505.

S. Rascunà, P. Badalà, C. Tringali, C. Bongiorno, E. Smecca, A. Alberti, S. Di Franco, F. Giannazzo, G. Greco, F. Roccaforte, M. Saggio, Morphological and electrical properties of Nickel based Ohmic contacts formed by laser annealing process on n-type 4H-SiC, Materials Science in Semiconductor Processing 97 (2019), 62-66.

M. De Silva, T. Kawasaki, T. Miyazaki, T. Koganezawa, S. Yasuno, S.-I. Kuroki, Formation of epitaxial Ti-Si-C Ohmic contact on 4H-SiC C face using pulsed-laser annealing, Applied Physics Letters 110 (2017), 252108.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 224-228

doi: 10.4028/p-c277as

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-23

Revised:
2022-03-15

Accepted:
2022-03-15

Online:
2022-05-31

Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

The original version of this paper is available on https://www.scientific.net/MSF.1062.224.pdf

Vinoth Sundaramoorthy , Stephan Wirths and Lars Knoll

Hitachi Energy, Fabrikstrasse 3, 5600 Lenzburg, Switzerland

vinoth.sundaramoorthy@hitachienergy.com, stephan.wirths@hitachienergy.com, lars.knoll@hitachienergy.com

Keywords: Ohmic contacts, Schottky barrier, shallow implantation, barrier modulation, annealing.

Abstract

In this manuscript Ohmic contact formation at low annealing temperatures is demonstrated using shallow implantation technique. Remarkably, Ni Ohmic contacts with a specific contact resistivity of have been achieved at as-deposited condition. Smooth interfaces along with reduced Schottky barrier at the metal/SiC interface contributed to improved Ohmic performance at as-deposited and anneal conditions.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.224.pdf

Conventional Ohmic contact formation on n-type 4H SiC requires high temperature annealing. Typically, nickel-based metal layers are deposited on SiC layers and annealed at temperatures above in inert atmosphere [1-5]. Ni silicide alloy is already formed in SiC at annealing temperature, but the metal semiconductor contact becomes Ohmic only at high temperatures . This has been attributed to many factors that include an increase of net donor concentration at the silicide/SiC interface; recrystallization of phase on SiC surface during high annealing temperature; formation of nanocrystalline graphitic layer on SiC surface [1-5]. All these factors require higher annealing temperature for the respective mechanism to occur at the metal/SiC interface during silicidation.

This high temperature annealing may not be compatible with the fabrication of SiC devices based on dielectric layers that cannot withstand temperatures above . Annealing at high temperature to form Ohmic contact causes the metal layer to interact with SiC layer. This forms metal silicide or carbides and have a rough surface. The rough morphology of contacts annealed at high temperature could be detrimental to the device performance in the long term. Hence, it is essential to develop a Ohmic contact formation process at low annealing temperatures for device process integration. Ohmic contacts with a low thermal budget have been investigated earlier using high dose implantations [6]. It was followed by a high temperature activation that may not be compatible with device processing.

In order to achieve Ohmic contacts at low anneal temperature, it is key to increase the doping concentration and, thus, reduce the Schottky barrier height at the metal/semiconductor interface. We have developed a process that is based on implanting a high dose of n-type dopants only on the SiC surface to increase the background doping without activation.

Experimental Details

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A thin n -SiC epilayer with a doping concentration of on a 4 H -SiC substrate with a doping concentration of was used as the starting material and implanted with phosphorous. Here, we have used a phosphorous dose of at an energy of 15 keV . Ni contacts have been deposited on these samples and annealed at different temperature starting from to . All the samples have been treated in rapid thermal anneal chamber at for 5 minutes in vacuum before the metal deposition.

Results

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Electrical characterization

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The results of the I-V measurements on the contacts annealed from to is shown in fig 1. The specific contact resistivity was measured using Transfer Length Measurement (TLM) technique at different anneal conditions and shown in table 1 . We observed that the contacts were Ohmic at all anneal conditions, although the best performance was achieved at as-deposited and anneal condition. The contacts start to become more resistive beyond annealing and recover the performance after annealing at .

Fig. 1. I-V curves measured on TLM pads at (a) , (b) . Legend: Pad 1, 2, 3, 4, 5, 6 refers to 5 spacing respectively between the inner and outer circular contacts in TLM pad.

Fig. 1. I-V curves measured on TLM pads at (a) , (b) . Legend: Pad 1, 2, 3, 4, 5, 6 refers to 5 spacing respectively between the inner and outer circular contacts in TLM pad.

Table I. Comparison of specific contact resistivity for Ni Ohmic contact at different annealed condition.

Anneal Temperature
[°C]
Specific contact
resistivity [Ωcm²]

Non anneal
1.9x10⁻⁵

450
2.3x10⁻⁵

550
1.9x10⁻⁴

1000
6x10⁻⁵

Structural characterization

The original version of this paper is available on https://www.scientific.net/MSF.1062.224.pdf

To support the electrical measurements, the secondary ion mass spectrometry (SIMS) was performed for nickel contacts annealed at different conditions. It can be seen from the SIMS analysis at as-deposited condition and anneal condition as shown in figs 2 and 3, that the metal interface is very similar. The nickel silicide is not yet formed at and there is a smooth abrupt interface between the nickel and SiC layer. It can also be seen that the peak of the implanted phosphorous appears at the SiC/Ni interface, thereby reducing the Schottky barrier height to enable Ohmic contact formation already at as-deposited condition. It was observed that the nickel silicide is completely formed at due to strong reaction between nickel and SiC surface (not shown). Phosphorous dopants move away from the metal/SiC interface and embeds with nickel silicide. Annealing at causes more stronger reaction, causing uniform distribution of phosphorous throughout the silicide (fig 4).

Fig. 2. SIMS results at Ni/SiC interface annealed at non-annealed condition.

Fig. 2. SIMS results at Ni/SiC interface annealed at non-annealed condition.

Fig. 3. SIMS results at interface annealed at .

Fig. 3. SIMS results at interface annealed at .

Fig. 4. SIMS results at interface annealed at .

Fig. 4. SIMS results at interface annealed at .

The TEM analysis of contacts annealed at and is shown in figs 5 and 6 . From fig 5, it could be seen that Ni layer did not react with the underlying highly doped SiC material at . It has smooth interface with the SiC layer. Smooth metal/SiC interface coupled with reduced Schottky barrier at the interface contributes to superior Ohmic performance at non-annealed & anneal condition (fig 5). Annealing at causes strong reaction between nickel and SiC layer, thereby forming nickel silicide contacts with rough morphology (fig 6). A relatively high proportion of nickel silicide is formed at an interface layer, disturbing the SiC material below.

Fig. 5. TEM results at interface annealed at .

Fig. 5. TEM results at interface annealed at .

Fig. 6. TEM results at interface annealed at .

Fig. 6. TEM results at interface annealed at .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.224.pdf

A method to form Ohmic contacts at low annealing temperatures has been developed by implanting a phosphorous dose of at an energy of 15 keV in SiC epilayers. This caused an increase in carrier concentration at the metal/SiC interface and modulated the Schottky barrier height at the interface. Due to this, Ohmic contacts with a specific contact resistivity of was achieved already at as-deposited condition. Annealing at produced similar results, as the nickel had not yet reacted with SiC layer and interface was similar to as-deposited condition. However, annealing at degraded the performance, as nickel silicide have been formed at this temperature giving rise to a traditional Ohmic behavior. The electrical behavior was analyzed further by SIMS and TEM. From these analyses, it could be seen that there was a decrease in Schottky barrier and nickel had a smooth morphology at the metal/SiC interface at as-deposited and anneal condition. Smooth interface in combination with modified carrier concentration contributed to improved Ohmic performance at these conditions.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.224.pdf

S. Y. Han, K. H. Kim, J. K. Kim, H. W. Jang, K. H. Lee, N. -K. Kim, E. D. Kim and J. -L. Lee, Appl. Phys. Lett. 79, 1816 (2001).

I. P. Nikitina, K. V. Vassilevski, N. G. Wright, A. B. Horsfall, A. G. O’Neill and C. M. Johnson, J. Appl. Phys. 97, 083709 (2005).

A.V. Kuchuk, V. P. Kladko, K. Golaszewska, M. Guziewicz, M. Wzorek, E. Kaminska and A. Piotrowska, Mat. Sci. Forum. 717-720, 833 (2012).

F. Roccaforte, F. La Via, V.Raineri, Int. J. High Speed Electronics and systems. 15, 781 (2005).

S. Tanimoto, H. Okushi, K. Arai, Silicon Carbide - Recent major advances (Springer, 2004), p. 651.

V. Sundaramoorthy, R. Minamisawa, L. Kranz, L. Knoll, G. Alfieri, Materials Science Forum 924: 413, June 2018.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 229-234

doi: 10.4028/p-a66637

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-25

Revised:
2022-03-15

Accepted:
2022-03-15

Online:
2022-05-31

Highest Quality and Repeatability for Single Wafer SiC CMP Designed for High Volume Manufacturing

The original version of this paper is available on https://www.scientific.net/MSF.1062.229.pdf

Sean Yu , Jianjun Hu Longlong Xu , Mike Liu , Eulia Liu , John Givens , Jamie Leighton

Applied materials Inc. 28 Xinxi road, Xi'an, Shaanxi province, China;

Applied Materials, 3050 Bowers Ave, Santa Clara, California 95054, USA

Sean_yu@amat.com, Jianjun_hu@amat.com, Longlong_xu@amat.com

Mike_liu@amat.com, John_givens@amat.com, Jamie_leighton@amat.com,

Keywords: Silicon carbide, Chemical mechanical polishing, surface roughness (Ra), material removal rate (MRR), flatness,

Abstract

Silicon Carbide (SiC) provides superior thermal conductivity, high carrier mobility and extreme chemical stability in comparison with those of Silicon ( Si ). SiC is already showing significant device performance benefits in power devices, communication, and LED lighting. However, SiC presents many challenges for wafer surface treatment due to its high hardness and remarkable chemical inertness.

Today, mechanical polishing techniques on industrial batch CMP tools are the predominant methods for SiC wafer surface treatment, but material removal rate (MRR), surface defects and wafer flatness control are reaching fundamental limits with increasing wafer diameter. Batch processing typically results in a higher amount of surface scratches and defects, higher wafer to wafer variability, and higher wafer breakage rates. A unique single wafer chemical mechanical polishing (CMP) technique on 150 mm n -doped, offaxis, single crystal, wafers was developed to create a virtually defect-free surface. A polishing head has been designed to manipulate polishing pressures at various zones of the wafer. The removal thickness at each region of wafer surface is modulated and resulting in a highly uniform wafer profile. Additionally, a CMP slurry has been formulated to maximize MRR from to over . Scratch-free wafer surfaces are observed with atomic force microscopy (AFM) and bright field (BF) and dark field (DF) inspection techniques. Roughness on the Si face is reduced to below 0.08 nm . Total length of surface scratches was reduced to 10 mm or less. Industrial metrics of wafer flatness, including total thickness variation (TTV) and local thickness variation (LTV) are modulated and improved. A test run completed on 25 -wafers shows an overall improvement of TTV post CMP process.

1. Introduction

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Silicon carbide (SiC) devices are superior in higher operating voltages, greater current carrying capacity, high operating frequency, capability of working in higher temperature, greater heat dissipation capability and higher reliability, as compared with those of silicon has a great potential in the applications of electronic transistors, GaN-based LED, high-temperature energy conversion devices, and sensors that can operate in extremely high temperature and chemically corrosive environments.

SiC devices require a high-quality epitaxial layer which is dependent upon a defect-free substrate surface known as epi-ready surface. Currently, mechanical polishing techniques including lapping and grinding are the predominant methods for the SiC wafer surface treatment. However, a diamond abrasive is often used in these processes which produces surface containing defects and lattice dislocations. In addition, low material removal rate (MRR) and limited wafer flatness control
extends the process time and affects the yield in mass production. In response to these limitations, we developed a novel chemical mechanical polishing (CMP) technique on 150 mm n -doped, off-axis, single crystal, wafers. The CMP process removes subsurface damage and produce a surface of highest quality and repeatability for the growth of epitaxial SiC .

The material removal rate (MRR) and the quality of finished wafer surface which includes roughness, defectivity and scratches are the two major factors for a SiC CMP process. The slurry has an important impact to both factors. Previous research has been performed to study the abrasive and oxidizer within the slurry and the resultant impact for the SiC substrate surface. Su et al. studied the influencing factors for the material removal rate of 2 inch SiC crystal (0001) Si and (0001) C surfaces. These factors include size and concentration of abrasive alumina , pH value, dispersants and oxidants, and process parameters. Yin et al. evaluated the MRR of 4 -inch SiC wafers by adding as strong oxidant in slurry. Increasing the concentration improved the MRR to a maximum of . Wang et al. developed a two-step CMP process for substrate, with the maximum MRR of on Si-face. In conclusion, based upon these studies, the oxidant and alumina abrasive-based slurry can improve the MRR. However, the reported MRR rates are not efficient enough for scaling SiC CMP product commercialization for larger diameter wafers.

The advantage of single wafer CMP process over batch wafer process lies in the wafer-to-wafer consistency and wafer surface quality. However, the MRR for single wafer CMP must reach greater than for substrate production. This requirement is driven by the 1.5 um Si -face removal target for effective elimination of both surfaces and subsurface damage from incoming grind or lapping.

In addition to MRR demands, wafer flatness control capability is equally essential for a CMP process. A uniform polish from the wafer center to edge is essential to reduce the edge exclusion and improve the total usable area. For SiC CMP, edge exclusion refers to the area around the wafer edge where thickness variation exceeds the specification and cannot be used for device fabrication. The total substrate usable area is increased more than if edge exclusion is minimized from 5 mm to 3 mm for a 150 mm substrate.

2. Experimental

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2.1 Study of MRR

In this study, a SiC CMP process is developed for the purpose of ultra-rapid polishing to ensure the process efficiency and improved surface quality. The slurries are acidic solutions containing alumina abrasive particles and as the oxidant. A thermoplastic polyurethane rigid pad with designed concentric and radial grooving at pad surface was utilized. wafers were purchased from a commercial substrate supplier. These wafers were polished by Applied Materials Mirra Durum CMP configured with a membrane polishing head. The polished SiC wafers were post-CMP cleaned in a brush scrubber equipped with an inline spin rinse dryer (SRD). The weight of SiC wafer is measured by an electronic analytical balance. The MRR is calculated by the equation below:
Here, is the overall weight removed by CMP process, t is the polishing time in seconds. C is a constant which equals the mass density of SiC multiplied by the surface area of SiC wafer. CMP MRR typically follows Preston's law , which is a linear function of the platen speed and the applied pressure (Fig.1). Three (3) types of slurries exhibit the Prestonian effect. As seen in Figure 1, the Si-face MRR is directly proportional to the platen speed and the applied pressure. The Durum single wafer polisher can produce . A MRR demonstrates very low Wafer-To-Wafer Non-Uniformity (WTWNU) throughout a 20-wafer run as shown in Figure 2. This is ideal for high volume manufacturing. The MRR and Ra for both faces is listed in Table 1.

Fig. 1. MRR of Si face CMP as a function of (pressure x velocity) for 3 commercial slurries

Fig. 1. MRR of Si face CMP as a function of (pressure x velocity) for 3 commercial slurries

Fig. 2. Excellent MRR repeatability on 20 SiC wafers run. This is ideal for mass production.

Table 1. MRR and Ra for polishing process. High removal rate with great surface finish is demonstrated.

Wafer Number | MRR (μm/hr) Face-1 | MRR (μm/hr) Face-2 | Ra (nm) Face-1 | Ra (nm) Face-2
1 | 156 | 154 | 0.18 | 0.19
2 | 158 | 156 | 0.17 | 0.18
3 | 157 | 155 | 0.18 | 0.19
4 | 159 | 157 | 0.19 | 0.20
5 | 156 | 154 | 0.18 | 0.19

2.2 Study of wafer flatness

Tropel non-contact metrology from Corning Inc. is an industry standard characterization tool for wafer flatness measurement. In this study, wafers are measured on a Tropel before and after the CMP process. The measured parameter changes indicate the impact of CMP process on wafer overall shape. In the SEMI standards, total thickness variation (TTV) is a general indication of overall thickness variation. Local thickness variation (LTV) indicates the thickness variation within a defined local window. In this study, a area is defined as the LTV measuring window. Thus, a 6inch wafer thickness map consists of 137 windows with a 3 mm edge exclusion (EE). As illustrated in Figure 3 (a) and (b), TTV and LTV with units in microns.

Experiments were conducted to characterize wafer flatness, which bases upon total amount of thickness removed from both faces. SiC wafers are first polished on C-face with a removed thickness of 2.0 um . The wafer is then automatically flipped in the Mirra Durum®. The Si-face CMP follows with a target removal of 1.5 um . The wafer thickness profile, TTV, LTV, and linescan plot of wafer thickness across wafer diameter were characterized.

The thickness map profile and LTV distribution before and after CMP are shown in Figure 3. Wafer thickness profile and LTV before CMP process is shown in Figure 3 (c) and (d). This wafer was then polished utilizing a head with single membrane zone, the result exhibits an MRR edge-fast process. After removing 2.0 um and 1.5 um from the C -face and Si -face respectively, the wafer exhibits a 'Dome" shape thickness profile as indicated in Figure 3 (e). Consequently, due to the dramatic thickness change on wafer edge, the LTVs on edge were increased to above 2.0 um , as Figure 3 (f). This edge fast removal is also confirmed by the removal thickness map shown in Figure 3(g).

A polishing head has been designed to manipulate polishing pressures at various zones across the wafer. The removal thickness can be modulated at each region on the wafer surface resulting in a highly uniform wafer profile. The new designed polishing head enables adjustment of pressure exerted to the edge of the wafer. Figure 3(h) illustrates the effect of pressure difference on edge zone for the wafer thickness removal profile. Total removed thickness was 2.5 um for each wafer (both faces were polished). Compared with the linescan plot of removed thickness of a single zone head CMP process, the uniformity of MRR across wafer diameter has been greatly improved (Figure 3(i)).

In Figure and , the wafer thickness profile from the pre-CMP Tropel measurement indicates that the wafer edge area is thicker than the center area. The multi-zone polishing head was adjusted to the thickness distribution map and the wafer was planarized to achieve the flatness uniformity specification. This is shown in Figure 3 (l) and (m).

A set of 25 SiC 150 mm wafers were then processed utilizing the new multi-zone polishing head to demonstrate repeatability of the improved post CMP wafer shape. As shown in Figure 3(n), TTV improvement of in average has been achieved.

Fig. 3(a)(b). Definition of TTV and LTV, (c)-(f). Wafer thickness profile and LTV distribution comparison for a single zone membrane polishing head. (g). Removed thickness distribution map. Red area indicates larger amount of removal. (h). Illustration of removed thickness linescan for a multizone polishing head. (i) Linescan comparison between single zone and multiple zone polishing head. he multizone head provides uniform removal (j)(m) Wafer thickness profile and LTV distribution comparison pre and post CMP for a multi-zone polishing head. (n) Post CMP shows improvement in TTV with multizone polishing head for 2.5 um of total thickness removal.

Fig. 3. (a)(b). Definition of TTV and LTV, (c)-(f). Wafer thickness profile and LTV distribution comparison for a single zone membrane polishing head. (g). Removed thickness distribution map. Red area indicates larger amount of removal. (h). Illustration of removed thickness linescan for a multizone polishing head. (i) Linescan comparison between single zone and multiple zone polishing head. he multizone head provides uniform removal (j)(m) Wafer thickness profile and LTV distribution comparison pre and post CMP for a multi-zone polishing head. (n) Post CMP shows improvement in TTV with multizone polishing head for 2.5 um of total thickness removal.

2.3 Study of wafer surface roughness and defectivity

The developed CMP process has remarkable tolerance for incoming surface quality. Wafers with different initial surface conditions can be processed and the resulting surface roughness is not relevant. Wafer ( ) was processed by a rough stock polishing process prior to CMP. Wafer (30_03) was polished by a so-called fine polishing process, as shown in Figure 4 (a)(b). Scratch-free wafer surfaces are observed on both wafers after CMP process. The roughness has been reduced to less than 0.1 nm and 0.2 nm for Si and C face, respectively, as shown in Figure 4(c). Post-CMP surface roughness remains consistent regardless of starting roughness. Micro-defects on the substrate surface influence SiC epilayer growth quality. Scratch type defects are generated in mechanical treatment
processes prior to CMP, Mirra Durum single wafer CMP can achieve consistently the lowest levels of scratches and even eliminate scratches.

In this study, a SiC wafer processed by commercially available wafer lapping vendor (mechanical treatment) is compared to wafers polished by Mirra Durum single wafer CMP. The wafers are characterized in a defect inspection tool by Lasertec. The measured defects are classified and presented in visual format for quantity and type. Bright field and dark field defectivity measurements of the lapping wafer are shown in Figure 4(d). The total scratch length was over 100 mm . Scratches are verified by AFM measurement at specific defect aggregative locations on wafer surface as shown in Figure 4 (e). Another SiC wafer was polished by Mirra Durum® single wafer CMP. Bright field and dark field defectivity measurements and AFM image are shown in Figure 4(f). A set of 10 wafers were measured for post-CMP scratches. As shown in Table 2, the maximum number of scratches is wafer with the maximum total length of 6 mm .5 out of 10 wafers exhibited no scratches.

Fig. 4(a)-(b). AFM images of SiC wafers before and after CMP. The incoming surface finish does not affect the post-CMP surface quality. Fig. 4(c). Surface Ra data 0.08 nm Si-face and 0.18 nm C-face can be achieved. Fig. 4(d)-(e). Post-Lapping defectivity. Significant particle results for bright field and obvious scratching defect of dark field are typical. Fig. 4(f)-(g). Post-CMP defectivity. Very low defect results for bright field and dark field analysis are typical for Mirra Durum single wafer CMP.

Fig. 4. (a)-(b). AFM images of SiC wafers before and after CMP. The incoming surface finish does not affect the post-CMP surface quality. Fig. 4(c). Surface Ra data 0.08 nm Si-face and 0.18 nm C-face can be achieved. Fig. 4(d)-(e). Post-Lapping defectivity. Significant particle results for bright field and obvious scratching defect of dark field are typical. Fig. 4(f)-(g). Post-CMP defectivity. Very low defect results for bright field and dark field analysis are typical for Mirra Durum single wafer CMP.

Table 2. Summary of scratches illustrates the excellent surface quality for high volume manufacturing.

Scratch | #1 | #2 | #3 | #4 | #5 | #6 | #7 | #8 | #9 | #10
Length (mm) | 1.61 | 0 | 0 | 5.82 | 0 | 0 | 3.31 | 1.31 | 0.64 | 0
Number (#) | 1 | 0 | 0 | 5 | 0 | 0 | 2 | 1 | 1 | 0

3. Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.229.pdf

A novel single wafer chemical mechanical polishing (CMP) technique on n-doped, off-axis, single crystal, substrates wafers was developed. The effects of material removal rate (MRR) and wafer flatness by CMP parameter and polishing head design were investigated. The MRR is times more efficient than that of conventional lapping or grinding process and overall wafer shape can be maintained or improved. The surface morphology and defect were studied by atomic force microscopy (AFM). A truly defect-free surface with atomic level surface roughness is achieve. Single wafer SiC CMP by Applied Materials Mirra Durum® demonstrated consistent performance and repeatability. This is ideal for 150 m high volume manufacturing and future substrate scaling.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.229.pdf

Lee, H., Jeong, S., Seo, H., Park, B., Oh, J., Jeong, H. and Kim, H., 2007, October. "Experimental analysis on CMP mechanism of single crystal SiC." International Conference on Planarization/CMP Technology (pp. 1-5). VDE.

Moeggenborg, Kevin, et al. "Effect of surface damage on SiC wafer shape." Materials Science Forum. Vol. 821. Trans Tech Publications Ltd, 2015.

Su, Jianxiu, et al. "Material removal rate of 6 H -SiC crystal substrate CMP using an alumina (Al2O3) abrasive." Journal of Semiconductors 33.10 (2012): 106003.

Yin, T., Doi, T., Kurokawa, S., Ohnishi, O., Yamazaki, T., Wang, Z., & Tan, Z. (2012). "The effects of strong oxidizing slurry and processing atmosphere on double-sided CMP of SiC wafer." In Manufacturing Engineering and Automation II (pp. 1131-1134). (Advanced Materials Research; Vol. 591-593).

Wang, Weilei, Weili Liu, and Zhitang Song. "Two-Step Chemical Mechanical Polishing of 4HSiC (0001) Wafer." ECS Journal of Solid State Science and Technology 10.7 (2021): 74004.

F. W. Preston: J. Soc. Glass Technol. 11 (1927) 214.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 235-240

doi: 10.4028/p-621n11

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-26

Accepted:
2022-02-25

Online:
2022-05-31

Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

Mariaconcetta Canino , Fulvio Mancarella , Filippo Bonafè , Franco Corticelli , Cristiano Albonetti , and Roberta Nipoti

CNR-IMM of Bologna, via Gobetti 101, 40129 Bologna, Italy

CNR-ISMN of Bologna, via Gobetti 101, 40129 Bologna, Italy

canino@bo.imm.cnr.it, mancarella@bo.imm.cnr.it, bonafe@bo.imm.cnr.it,

corticelli@bo.imm.cnr.it, cristiano.albonetti@cnr.it, nipoti@bo.imm.cnr.it

Abstract

Encapsulating SiC with a carbon layer (C-cap) is a widely used technique to avoid step bunching during post implantation annealing. In this work we propose a mechanism that explains the roughening that the surface unavoidably undergoes during annealing under the C-cap. We investigated the reactions occurring at the interface between and the C -cap by scanning electron microscopy, energy-dispersive X-ray spectroscopy, and atomic force microscopy carried out at different stages of the sample processing: just after annealing, after C-cap removal in dry Oxygen, and after cleaning in buffered oxide etch solution. Our observations show that, even though the C cap roughens for increasing annealing temperature and time, it is not visibly damaged even after annealing. After the C-cap removal the 4H-SiC surface was covered by a network of clusters that are eventually removed by buffered oxide etch solution. This occurrence suggests that, during the post-implantation annealing, the surface decomposes and the escaped Si and C atoms are trapped inside the C -cap or at the interface between and the C -cap. While C clusters are etched off in the dry atmosphere, the Si clusters oxidize and form nanoparticles which are finally etched by buffered oxide etch.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

The electrical activation of Al in is often carried out at annealing temperatures exceeding . At such elevated temperatures, two detrimental occurrences are observed: step bunching of the SiC surface and increasing of the concentration of carbon vacancies [2], a lifetime killer defect for bipolar devices, in the drift layer. Encapsulating the SiC surface with a carbon layer ( cap) during post implantation annealing can be beneficial both as a source of carbon atoms, provided that the cooling rate is low enough to maintain carbon vacancy thermal equilibrium [3], and to reduce surface roughening. However, surface changes are not completely prevented. It was observed by several authors that the surface of Al ion implanted , annealed at temperatures higher than , is featured by holes and the root means square of the surface roughness (rms) is higher than . It was observed that, for equal annealing treatments, rms increases for increasing Al concentration, and that prolonged annealing, even at temperatures as low as , also results in increased rms [6]. Some authors attribute surface roughening under the C-cap to a deterioration of the C-cap itself [4]. However, the occurrence of material evaporation even under a stable C-cap is not completely ruled out. Indeed, SIMS analyses revealed surface erosion of subsequent to annealing at and , with durations between 15 min and 1 h , while the surface remained smooth [7]. According to this study, material loss is linked to the lattice damage rather than directly to the Al concentration. In this work, we investigate the changes occurring in the C -cap and at the interface between the C -cap and Al ion implanted upon annealing at different temperatures and times, at different stages of the sample processing. We find that the C-cap is compact and that, after C-cap removal, the surface is covered by a network of grains, which can be removed by a Buffered Oxide Etch (BOE) solution. A mechanism involving Si and C evaporation from the surface, and trapping inside or below the C-cap is proposed.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

Two commercial off-axis (0001) n-type 4H-SiC homo-epitaxial wafers were used. The wafer major flat was parallel to the ( ) plane with the flat face parallel to the direction. Al depth profiles with uniform concentration of and extending 200 nm in depth from the wafer surface were created by Al ion implantation at . The implanted SiC wafers were diced in piece before post implantation annealing. The C-cap was a layer of OiR908-35 photoresist from Fujifilm spun at 4000 rpm pyrolysed at . The annealing was carried out in a RF heated graphite crucible at temperatures between and flowing Ar at 1 atm . The annealing temperature was attained with heating and cooling rates. The C -cap was removed by dry oxidation at for 15 min and the surface was cleaned in buffered oxide etch (BOE) for 20 min .

Characterizations were carried out at different stages of sample production. Cleaved cross sections of the samples were observed by a ZEISS Crossbeam 340 BIB/EBL in SEM mode. Energy-dispersive X-ray (EDX) spectroscopy microanalyses on flat surfaces were carried out in a ZEISS EVO|LS10 SEM with a X-Flash at 5 kV and 911 kpcts . The surface morphology was analysed by a Thermomicroscope Autoprobe CP Research Atomic Force Microscope (AFM) with the fast scan direction parallel to <11-20>.

Table 1 reports processing conditions, rms of the C -cap after annealing and of the surface after BOE, and the Figures displaying images of each sample. Considered the slow rate of surface evolution occurring at [6], the samples annealed for 15 min and 30 min are considered equal.

Table 1. Processing conditions (Al concentration, annealing temperature and time), rms of the annealed C -cap, rms of the surface after BOE, and Figure numbers showing images of each sample.

Al [cm⁻³]
T [°C]
Time
[min]
rms C-cap
[nm]
rms SiC [nm]
Figure

1×10²⁰
1750
15
1.3 ± 0.3

4(a)

1×10²⁰
1750
30

1.6 ± 0.4
4(d)

1×10²⁰
1850
120
9.4 ± 0.8
8.8 ± 0.2
4(b,e)

1×10¹⁹
1950
30
20 ± 2
8.3 ± 0.5
1(a-b), 2(a-c), 3(b-d) 4(c,f)

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

Figs. 1(a,b) show the C-cap after annealing at for 30 min . The SEM cross section view in Fig. 1(a) shows that the C-cap is thick, uniformly distributed over the surface, with grains in size and no pass-through hole. The observation of the cleaved profile reveals that the shape of cleaved C -cap does not reproduce the SiC border, thus leaving the SiC surface partly uncovered. Fig. 1(b) shows the AFM micrograph of the C-cap surface in the center of the sample. The granular structure of the C-cap surface is confirmed by the AFM analyses.

Figure 1. Cross section SEM micrograph of a C-cap on a 4 H -SiC sample annealed at for 30 min (a) and AFM morphology of the C-cap surface (b).

Figure 1. Figure 1. Cross section SEM micrograph of a C-cap on a 4 H -SiC sample annealed at for 30 min (a) and AFM morphology of the C-cap surface (b).

Figs. 2(a-c) show the annealed 4H-SiC surface after dry oxidation. Two situations are identified in the SEM tilted cross section shown in Fig. 2(a): in the top region of the picture, i.e. the center of the sample, the surface is covered by clusters; in the lower region, i.e. close to the cleaved border, clusters are not detected. The low magnification image shown in Fig. 2(b) shows a location where the C-cap had been broken during cleavage before the oxidation, and confirms the coexistence of two different morphologies. The AFM micrograph in Fig. 2(c) is taken in the center of the sample. The surface is featured by the superposition of ripples in size, and grains having 100-200 nm diameter.

Figure 2. surface after dry oxidation. High (a) and low (b) magnification SEM cross section views; AFM micrograph acquired in NCM (c).

Figure 2. Figure 2. surface after dry oxidation. High (a) and low (b) magnification SEM cross section views; AFM micrograph acquired in NCM (c).

In order to identify the composition of the clusters shown in Fig. 2(c), we analysed the evolution of the surface close to defects present on the as-implanted wafer, shown in Fig. 3(a). Though the rare occurrence of these defects is not detrimental for the process yield, their presence causes holes in the C-cap, which turned out to be useful for our analysis. Figs. 3(b) and 3(c) show SEM micrographs of the C-cap after annealing, and of the SiC surface after the C-cap removal, respectively. The sequence of Figs. 3(a-c) shows that the SiC surface not protected by the C-cap is eroded upon annealing, and that the incidence of clusters is reduced towards the center of the holes. Comparing the composition obtained from EDX microanalysis on regions with different cluster density allows to infer on the composition of the clusters. Fig. 3(d) shows an example EDX microanalysis. This picture is highly contrasted because the current for EDX measurements must be high in order to get a high number of counts. Indeed, the feature that we are analysing is located on the surface, while the composition is determined within a generation volume of about 600 nm diameter. For this reason, a high number of counts per analysed zone and a wide statistics are necessary to get reliable results. However, we noticed a repeatable difference in composition between regions with different cluster density.

Figure 3. Optical micrograph of the defects on the as-implanted sample (a). Cross section SEM image of the C-cap in correspondence on one defect (b). Cross section SEM image of the SiC surface after C-cap removal (c); the location corresponding to a hole in the C-cap is etched off during the post-implantation annealing while a network of bright clusters covers the surface outside the etched hole. Plan view of an etched hole (d); the white rectangles show the regions where EDX was collected inside a hole (HOLE) and outside (CLUSTER).

Figure 3. Figure 3. Optical micrograph of the defects on the as-implanted sample (a). Cross section SEM image of the C-cap in correspondence on one defect (b). Cross section SEM image of the SiC surface after C-cap removal (c); the location corresponding to a hole in the C-cap is etched off during the post-implantation annealing while a network of bright clusters covers the surface outside the etched hole. Plan view of an etched hole (d); the white rectangles show the regions where EDX was collected inside a hole (HOLE) and outside (CLUSTER).

Table 2 reports the C , Si and O atom concentration obtained by fitting of the EDX spectra in three locations on the surface rich in clusters and four locations inside a hole, as shown in Fig. 3(d). EDX spectra were collected after C-cap removal. It is shown that the regions covered by the C-cap show slightly higher Si and O concentration with respect to the holes, where the C -cap was not present. Despite the limits of the technique, we can infer that the clusters observed on the surface can be made up of .

Table 2. Location on the sample surface and compositional data obtained by EDX analyses: C, Si, and O atomic concentrations and Si to C ratio.

CLUSTER/HOLE | C atom % | Si atom % | O atom % | Si/(Si+C) atom %
CLUSTER | 49.8 | 49 | 1.2 | 49.6
CLUSTER | 49.9 | 48.9 | 1.2 | 49.5
CLUSTER | 49.9 | 48.9 | 1.2 | 50.5
HOLE | 51.5 | 47.7 | 0.7 | 48.1
HOLE | 51.2 | 48.1 | 0.7 | 48.4
HOLE | 51.3 | 48 | 0.7 | 48.3
HOLE | 50.7 | 48 | 1.3 | 48.6

Figs. 4(a-f) show AFM micrographs of the annealed C-cap in Figs. 4(a-c) and of the surfaces of samples annealed in the very similar conditions after C -cap removal and BOE in Figs. 4(d-f). The arrow points the direction parallel to the major flat, i.e. .

Figure 4. AFM micrographs of the annealed C -cap (a-c) and of the surfaces of samples after C-cap removal and BOE (d-f). implantation and annealing at for 15 min (a) and implantation and annealing at for implantation and annealing at for 30 min (c,f). The inset in (f) shows a cross section SEM micrograph of the border not covered by the C-cap during the removal, before BOE (g). The picture is rotated, the cleaved border is on the left.

Figure 4. Figure 4. AFM micrographs of the annealed C -cap (a-c) and of the surfaces of samples after C-cap removal and BOE (d-f). implantation and annealing at for 15 min (a) and implantation and annealing at for implantation and annealing at for 30 min (c,f). The inset in (f) shows a cross section SEM micrograph of the border not covered by the C-cap during the removal, before BOE (g). The picture is rotated, the cleaved border is on the left.

Figs. 4(a,d) show the morphology of a C-cap on a implanted sample annealed at for 15 min (Fig. 4(a)) and of the SiC surface of a sample annealed at for 30 min (Fig. 4(d)). Since the surface evolution at this temperature is slow [6], the image shown in Fig. 4(b) can be considered as representative of a surface annealed for 15 min . Figs. show the morphologies of the C-cap (Fig. 4(b)), and of the corresponding implanted 4 H SiC (Fig. 4(e)), after annealing at for 2 h . Figs. show the morphology of the C-cap (Fig. 4(c)) and of the corresponding implanted 4H-SiC surface (Fig. 4(f)) after annealing at for 30 min . These images show that surface roughening occurs both on the C -cap and on
the surface but a one to one comparison shows no correspondence between the morphologies of the two surfaces with respect to ripple size and height. Fig. 4(g), represented as an inset of Fig. 4(f), shows a high magnification cross section SEM micrograph of the lower border of Fig. 2(a), i.e. the border of the sample that was not covered by the C -cap during the annealing in , acquired before BOE. This picture, that represents a step backward with respect to the AFM micrograph in Fig. 4(f), is inserted to ease the comparison between the surface after BOE and the border before BOE. The remarkable similarity between the border shown in Figs. 2(a) and 4(g) and Fig. 4(f) suggests that a reaction occurring between the C-cap and the 4H-SiC during oxidation is unlikely.

Figure 5. Schematic evolution of the C -cap and the SiC surface along the processing steps: before (a) and after (b)post-implantation annealing; after C-cap removal (c); after wet etching in BOE (d). The arrows between the panels represent the processing steps; the text boxes between the panels summarize the material evolution at each annealing step.

Figure 5. Figure 5. Schematic evolution of the C -cap and the SiC surface along the processing steps: before (a) and after (b)post-implantation annealing; after C-cap removal (c); after wet etching in BOE (d). The arrows between the panels represent the processing steps; the text boxes between the panels summarize the material evolution at each annealing step.

From our investigations it appears that the C-cap is not damaged during the annealing. Indeed, in order to perform this study, we focused on holes created in the C-cap by rare defects present on the wafer surface. Close to these defects, the surface evolves differently with respect to the rest of the wafer, where extensive analysis of the C-cap, and good process yield testified by electrical measurements [8], confirm that the greatest part of the C-cap is undamaged. Consequently, surface roughening due to C-cap deterioration is ruled out in our case. After the C-cap removal in dry the surface is covered by a network of clusters, probably made up . The occurrence of such clusters only in regions which were covered by the C-cap during the oxidation allows to infer that the C-cap can trap Si or C atoms escaping from the SiC surface, and that the excess Si inside or under the C -cap is oxidized during the C-cap removal. Cross section transmission electron microscopy analyses are necessary to check the cluster composition, as well as to prove the occurrence and determine the location of Si trapping. However, independently on the effectiveness of the C-cap at trapping the atoms escaped from the surface, the surface roughness observed on Al -implanted surfaces during high-temperature annealing is likely due to material evaporation.

Before the annealing, the pyrolysed C-cap is deposited on the SiC surface, Fig. 5(a). During the high temperature annealing the surface decomposes but the C -cap prevents the out-diffusion of Si and C atoms; at least a fraction of the escaped atoms remains trapped between the surface and the C-cap surface. The occurrence depicted in Fig. 5(b) has not been detected. It could be verified for example by cross section TEM analyses. Though material evaporation is not proved here, this hypothesis is coherent with the conclusions drawn in reference [7], where material evaporation after high temperature annealing was detected by SIMS analyses. The dry oxidation, Fig. 5(c), removes the C -cap as well as the evaporated C atoms, while the evaporated Si or clusters oxidise; Si or clusters must be small enough to be completely oxidize in 15 min at . It is not likely for
the SiC surface to oxidise because SiC oxidation takes place at much higher temperatures. The BOE wet etching removes the clusters completely, as it is represented in Fig. 5(d).

Despite the different methodology, the mechanism proposed in this paper is in agreement with the observations in reference [7]. However, with respect to reference [7], where the surface morphology after annealing is not characterized, we correlate the material erosion with surface roughening. We did not investigate any possible competition between material evaporation and the C atom supply by the C-cap during high temperature annealing [3]. In principle, the number of atoms involved in the surface rearrangement is far higher, and the two phenomena concern different regions of the samples, i.e. the surface and the epilayer, respectively. Figs. 5(a-d) summarize the mechanism proposed as an interpretation of our observations.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

This paper aims to shed light on the origin of the surface roughening observed in Al ion implanted 4H-SiC after high temperature annealing under a C-cap. Our analyses indicate that any C-cap deterioration during annealing and reactions taking place at the interface between the C-cap and the SiC during oxidation can be excluded. More likely, at temperatures as high as and C can evaporate from the surface, and get trapped inside or under the C-cap. While the excess C is removed in dry , the excess Si oxidizes and is eventually removed in BOE solution.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

The technical staff of IMM Bologna is acknowledged for sample processing: Michele Bellettato, Fabrizio Tamarri and Michele Sanmartin.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.235.pdf

R. Nipoti, A. Carnera, G. Alfieri, L. Kranz. About the Electrical Activation of Ion Implanted Al in at Annealing Temperatures in the Range . Mat. Sci. Forum, 934 (2018) 333-338.

H. M. Ayedh, V. Bobal, R. Nipoti, A. Hallén, B. G. Svensson. Formation of carbon vacancy in 4H silicon carbide during high-temperature processing. J. of Appl. Phys. 115 (2014) 012005.

H. M. Ayedh, R. Nipoti, A. Hallén, B. G. Svensson. Elimination of carbon vacancies in 4H-SiC employing thermodynamic equilibrium conditions at moderate temperatures. Appl. Phys. Lett. 107 (2015) 252102.

K. V. Vassilevski, N. G. Wright, I. P. Nikitina, A. B. Horsfall, A. G. O’Neill, M. J. Uren, K. P. Hilton, A. G. Masterton, A. J. Hydes, C. M. Johnson. Protection of selectively implanted and patterned silicon carbide surfaces with graphite capping layer during post-implantation annealing. Semicond. Sci. Technol. 20 (2005) 271-278.

M. Spera, D. Corso, S. Di Franco, G. Greco, A. Severino, P. Fiorenza, F. Giannazzo, F. Roccaforte. Effect of high temperature annealing ( ) on the morphological and electrical properties of p-type implanted layers. Materials Science in Semiconductor Processing 93 (2019) 274-279.

M. Canino, P. Fedeli, C. Albonetti, R. Nipoti. 4H-SiC surface morphology after Al ion implantation and annealing with C-cap. J. of Microscopy 280 (2020) 229-240.

M.K. Linnarsson, H.M. Ayedh, A. Hallén, L. Vines, B.G. Svensson. Surface erosion of ionimplanted 4H-SiC during annealing with carbon cap. Mat. Sci. Forum 924 (2018) 373-376.

R. Nipoti, A. Parisini, V. Boldrini, S. Vantaggio, M. Canino, M. Sanmartin, G. Alfieri. ion implanted 4H-SiC: annealing time effect. Mat. Sci. Forum 1004 (2019) 683-688.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 241-245

doi: 10.4028/p-n0f23q

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-26

Accepted:
2022-02-25

Online:
2022-05-31

Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

The original version of this paper is available on https://www.scientific.net/MSF.1062.241.pdf

Roberta Nipoti , Virginia Boldrini , Mariaconcetta Canino , Fabrizio Tamarri , Salvatore Vantaggio and Antonella Parisini

CNR-IMM of Bologna, via Gobetti 101, 40129 Bologna, Italy

Department of Mathematical, Physical and Computer Sciences, University of Parma, Viale G.P. Usberti, 7/A, 43124 Parma, Italy

salvatore.vantaggio@fis.unipr.it, antonella.parisini@fis.unipr.it

*corresponding author

Keywords: ion implantation, electrical activation efficiency, dopant ionization energy, charge neutrality equation.

Abstract

Activation and compensation ratios feature the electrical doping efficiency of a semiconductor material by ion implantation. The estimation of these ratios requires a quantitative evaluation of the density of the implanted dopant in substitutional position and of the density of the compensator centers after the mandatory post implantation annealing treatment. In the case of ion implanted , it is a common habit to determine acceptor density, compensator density and acceptor thermal ionization energy by fitting the curve of the drift holes temperature dependence with the charge neutrality equation. However, this strategy could lead to ambiguous results. In fact, this study shows several cases of ion implanted of interest for electronic device fabrication, where at least two sets of such fitting outputs can reproduce the same experimental curve within the uncertainty of the data. Provided that a model for the carrier transport could be set-up, the contemporaneous fits of the temperature dependence of drift hole density and of drift hole mobility is proposed to alleviate the uncertainty of the estimated acceptor density, compensator density and acceptor thermal ionization energy

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.241.pdf

The electrical doping efficiency of a semiconductor material by ion implantation is qualified through the activation and compensation ratios, for which a quantitative evaluation of the implanted dopant density in substitutional position and of the compensator centers density are required, as well as the volume density of the as-implanted dopant. It is worthwhile to remember that the formers are measurable only after the mandatory post implantation annealing treatment.

In the case of ion implanted , it has become a common habit to estimate acceptor density, compensator density and acceptor thermal ionization energy by fitting the temperature dependence of the measured drift carrier density in the ion-implanted layer by the charge neutrality equation. Nevertheless, the number of free parameters, that is three, may be large to accomplish the fitting procedure univocally. In the absence of peculiar features in the temperature trend of the carrier density, such as a clear change in the slope of this curve indicating the compensating impurity density [1], the existence of other constraints would help in increasing the reliability of the optimization of the fitting parameters, also called fitting outputs. Often the net acceptor density obtained from capacitance-voltage ( ) measurements is the other constraint for consolidating the outputs of the carrier curves fitting, as examples see [2,3] for Al implanted layers and [4-5] for Al doped epi-layers. In this study we propose to use, as other constraint, the fitting of the temperature dependent mobility curve that is measured on the same van der Pauw (vdP) devices used for Hall effect measurements, i.e. for obtaining the temperature dependent carrier density curve. Moreover, the fact of using experimental curves that have been obtained on the same sample should hollow us to overcome the
issues/doubts arising when different samples as Schottky diodes or mercury probes for measurements and vdP devices for Hall-effect measurements are used [5].

In case a model for the carrier transport could be set-up, the verification that the same set of free parameters (acceptor density, compensator density and acceptor thermal ionization energy) permits a good fit of the temperature dependence of the mobility data other than that of carrier density, may be an effective way to reduce the uncertainty on the output parameters. Examples of self-consistent fittings of the two set of data, applied to the case of low-doped p-type epitaxial and ion implanted 4 H -SiC are in [6-7].

This study will show several ion implanted samples for which the fitting of the temperature dependence of the drift holes by using only the charge neutrality equation can be satisfied by several set of values for the free parameters with comparable agreement, so that the acceptor and compensator densities, and the acceptor ionization energy are not univocally determined. This drives us to think that for a reliable prevision of the electrical doping of by Al ion implantation in devices fabrication, this method of analysis is not sufficient. Other constraints have to be taken into account together with the charge neutrality equation. We propose to use a model for fitting the temperature dependence of the drift holes mobility, if the sample doping is in a range for which a reliable model for carriers transport can be set-up.

Method, Results, and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.241.pdf

All the samples of this study are from n-type homo-epitaxial off-axis <0001> 4H-SiC wafers with miss-cut angle of . The doping level of the epi-layers is in the range . Moreover, all the samples have been processed and measured in house. Per each sample, Table 1 shows the more relevant processing parameters for the p-type doping by ion implantation. These parameters are Al implanted concentration, post implantation annealing temperature and annealing time. The studied ranges of ion implanted Al concentration is , and those of post implantation annealing temperature and annealing time are and , respectively. These ranges are of interest for optimizing the doping efficiency in the Al implanted p-type well, and well contact region, in n-channel 4H-SiC double implanted vertical MOSFETs.

The measurements of the sheet resistance and the Hall resistance coefficient of Al implanted layers were performed on square and four leaves vdP devices, in the temperature range 150-680 K. These data Hall curves were converted in drift ones by using the Hall factor of [4,6]. Hereafter we will use the terms holes curves and mobility curves to indicate their temperature dependence.

The charge neutrality equation was employed for the simulation of the holes curve and a mobility model for a non-degenerate electron gas for simulating the mobility curves. Such mobility model takes into account the usual scattering mechanisms (holes interaction with ionized and neutral impurities and with phonons) in the relaxation time approximation, with derivation of the energydependent total momentum relaxation time through the Mathiessen rule, as thoroughly explained in [6]. In this frame, the dominant electron-phonon interactions resulted to be the acoustic and nonoptical ones via the correspondent deformation potential and , respectively.

Two fitting methodology approaches have been performed. One estimates the values of activation ratio, compensation ratio, and thermal ionization energy of the acceptors only by fitting the temperature dependence of the holes curves with the charge neutrality equation; we called this approach "p" fit. The other one estimated the same output parameters by fitting both holes and mobility curves; this was called " " fit. The uncertainties of fitting outputs are for acceptor density, for compensating center density, and for acceptor ionization energy. Table 1 shows the " p " and " " fitting outputs values. The difference between " p " and " " values are larger than the output errors. This means that within the uncertainty of the experimental data, significantly different sets of acceptor density, compensator density and acceptor thermal ionization energy values, correspondent to different activation and compensation ratios, account for the same holes curve, with comparable accuracy. This open the issue on the choice of the values to use for a unique evaluation of the doping efficiency for the Al ion implantation process in .

Table 1. Sample summary, ordered for decreasing Al as-implanted concentration. Per each sample, acceptors density, compensators density and value of acceptor ionization energy ( ) as obtained by fitting methodologies " p " and " " (see text). Computed activation and compensation ratios.

sample label
Al implanted density
[cm⁻³]
ann.
temp.
[°C]
ann.
time
[min]
fitting
method
acceptor
density
[cm⁻³]
activation
ratio
[%]
compensator
density
[cm⁻³]
compen-
sation ratio
[%]
EA
[meV]

220c-I7-vP1
6.0×10¹⁹
1600
30
p
5.1×10¹⁹
86
1.8×10¹⁹
35
129

p-μ
3.7×10¹⁹
61
7.8×10¹⁷
2
199

220c-I9-vP1
6.0×10¹⁹
1600
30
p
4.8×10¹⁹
79
1.5×10¹⁹
31
136

p-μ
3.6×10¹⁹
59
1.0×10¹⁸
3
200

350-C1-5A-vP3
1.0×10¹⁹
1600
300
p
4.9×10¹⁸
49
1.7×10¹⁸
34
169

p-μ
3.2×10¹⁸
32
5.4×10¹⁷
17
185

350-A3-1E-vP3
1.0×10¹⁹
1600
30
p
6.0×10¹⁸
60
2.9×10¹⁸
48
169

p-μ
3.1×10¹⁸
31
8.7×10¹⁷
28
185

354-Lb
9.6×10¹⁸
1750
30
p
7.0×10¹⁸
73
2.0×10¹⁸
29
169

p-μ
3.9×10¹⁸
41
9.0×10¹⁷
23
178

354-Mb
9.6×10¹⁸
1800
30
p
9.2×10¹⁸
96
2.2×10¹⁸
24
166

p-μ
4.5×10¹⁸
47
8.8×10¹⁷
20
175

350-C1-5A-vP2
3.0×10¹⁸
1600
300
p
3.0×10¹⁸
100
8.9×10¹⁷
30
181

p-μ
2.3×10¹⁸
76
3.6×10¹⁷
16
196

350-A3-1E-vP2
3.0×10¹⁸
1600
30
p
2.9×10¹⁸
96
9.3×10¹⁷
32
189

p-μ
2.3×10¹⁸
77
6.2×10¹⁷
27
194

220c-I9-vP2
6.0×10¹⁷
1600
30
p
6.0×10¹⁷
100
2.9×10¹⁷
49
205

p-μ
6.0×10¹⁷
100
3.2×10¹⁷
53
201

Some insights can be gained by looking at Figs. 1(a-b). These figures compare the results of the "p" (Fig. 1(a)) and "p-μ" (Fig. 1(b)) fits for sample 350-C1-5A-vP2 of Table 1. Similar graphs could be drawn for the other samples of Table 1. Fig. 1(a) shows an optimized fit of the Hall holes curve by "p" fit and, at the same time, the impossibility to fit the lower temperature side of the mobility curve using the same parameters. In this temperature range the Coulomb scattering is dominant and the fitting curve is directly influenced by the acceptor and compensator centers estimated by the "p" fit. None difficulty to find deformation potential Eac and Enop for fitting the high temperature side of the mobility curve where the phonon scattering is dominant. Differently, Fig. 1(b) shows that the set of output parameters obtained by methodology "p- " gives acceptable fits of both carrier and mobility curves within the uncertainty of the experimental curves over the whole range of temperature of measurement. This brings us to think that the doping efficiency estimated by the " " methodology may be more reliable.

By coming back to the values of Table 1, we can see that, except in the case of the lowest doped sample, the " " methodology brings to an estimation of lower activation ratios, lower compensation ratios and higher acceptor ionization energies.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.241.pdf

This study shows that, within the uncertainty of the experimental data, two significantly different sets of acceptor density, compensator density and acceptor thermal ionization energy values account for the temperature dependent same holes data. This bring to the conclusion that the only fitting of the holes curve by the neutrality equation is not sufficient for a unique identification of the electrical doping efficiency in ion implanted . This, at least in the case of all the samples of this study that cover a quite large range of processing parameters of interest for the fabrication of 4H-SiC double implanted vertical MOSFETs.

Fig. 1. Application of the "p" and "p-μ" fitting methodologies to the same set of experimental curves: fitting output parameters are in the insets. (a) methodology "p" gives optimal fit of the carrier density curve but none fit of the mobility curve in the low temperature region, (b) methodology "p- " gives acceptable fits for both carrier density and mobility curves.

Fig. 1. Application of the "p" and "p-μ" fitting methodologies to the same set of experimental curves: fitting output parameters are in the insets. (a) methodology "p" gives optimal fit of the carrier density curve but none fit of the mobility curve in the low temperature region, (b) methodology "p- " gives acceptable fits for both carrier density and mobility curves.

The issue of how to obtain a reliable and unique estimation of the electrical doping efficiency of the ion implantation process in , drive us to take into account other constraints in addition to the neutrality equation and the holes curves. An option, that we propose but others are possible, is the use of the holes mobility curves with an appropriate analytical model for carrier transport in .

New insights on the thermodynamics of the electrical activation of ion implanted Al in can be recognized only by using what we may shortly call a two constraints methodology for the quantitative analysis of the temperature dependence of both carriers and mobility data. Which makes the subject of our study timely.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.241.pdf

Acknowledgments are due to Mr. Filippo Bonafè, Mr. Giulio Pizzocchero, and Mr. Michele Sanmartin for their support during clean room processing, as well as to Mr. Michele Bellettato for the execution of the ion implantation processes.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.241.pdf

D. K. Schroder, Semiconductor Materials and Devices Characterization, third ed., John Wiley & Sons, New Jersey, 2006, p. 96.

R. Hattori, T. Watanabe, T. Mitani, H. Sumitani, T. Oomori, Crystalline recovery after activation annealing of Al implanted 4H-SiC, Mat. Sc. Forum 600-603 (2009) 585-590.

T. Watanabe, R. Hattori, M. Imaizumi, T. Oomori, Shuttle Activation Annealing of Implanted Al in 4H-SiC, Jpn. J. Appl. Phys. 474 (2008) 2841-2844.

F. Schmid, M. Krieger, M. Laube, G. Pensl, G. Wagner, Hall Scattering Factor for Electrons and Holes in SiC, in: Silicon Carbide. Recent Major Advances, edited by W. J. Choyke, H. Matsunami, G. Pensl, Springer, 2004, p. 517.

S. Contreras, L. Konczewicz, R. Arvinte, H. Peyre, T. Chassagne, M. Zielinski, S. Juillaguet, Electrical transport properties of p-type 4H-SiC, Phys. Status Solidi A 214 (2017) 1600679.

A. Parisini and R. Nipoti, Analysis of the hole transport through valence band states in heavy Al doped 4H-SiC by ion implantation, J. Appl. Phys. 114 (2013) 243703.

R. Nipoti, A. Parisini, V. Boldrini, S. Vantaggio, M. Canino, M. Sanmartin, G. Alfieri, Ion Implanted 4H-SiC: Annealing Time Effect, Mater. Sc. Forum 1004 (2020) 683-688.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 246-250

doi: 10.4028/p-43627c

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-08

Accepted:
2022-03-10

Online:
2022-05-31

Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing

The original version of this paper is available on https://www.scientific.net/MSF.1062.246.pdf

Gil Chung , Ian Manning , Andrey Soukhojak , Matt Gave and Charles Lee

SK siltron css, 5300 Eleven Mile Rd, Auburn, MI, USA

gil.chung@sksiltron.com, ian.manning@sksiltron.com, andrey.soukhojak@sksiltron.com, matthew.gave@sksiltron.com, charles.lee@sksiltron.com

Abstract

Post-growth thermal processing at higher temperature generates more BPDs (basal plane dislocations). It is observed that dislocation visibility in surface inspection tool images varies significantly even at comparable dislocation densities. Combination of dislocation decoration and light absorbance from SiC matrix by point defects or dopants has been proposed as a working hypothesis to explain dislocation visibility variations.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.246.pdf

SiC is a leading material for power electronics to control, convert, and distribute electric power efficiently. The widespread adoption of SiC semiconductor technologies continues to grow, and markets for several applications such as e-mobility, renewable energies and high-end power supplies are rapidly expanding [1,2]. SiC wafers grown by physical vapor transport (PVT) have improved in crystal quality, with significant reductions in crystal dislocations. Concurrently, in-line surface inspection tools with photoluminescence (PL) capabilities have been introduced in the SiC wafer industry to detect and count dislocations accurately [3,4]. In this paper, dislocation density changes by post-growth thermal processing will be discussed. Also, dislocation visibility changes in surface inspection tool images will be reviewed and a working hypothesis will be proposed to explain the dislocation visibility changes.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.246.pdf

4H n-type crystals were grown by the PVT process and post-growth thermal processing at different temperatures were performed. Charge concentrations of the tested wafers range from 2 to . Industry standard wafering, grinding, slicing and polishing techniques were also employed for wafer generation. Dislocations were measured by 1 ) counting etch pits formed at the intersection of dislocations with wafer surfaces following immersion in molten KOH , and 2 ) by XRT images from Rigaku XRT micron. KLA Candela 8520, Lasertec SICA 88 and Etamax MiPLATO tools were used to inspect wafer level defectivities. Table 1 shows specifications for different surface inspection tools.

Table 1. Specifications for three surface inspection tools.

Company | Lasertec | KLA | EtaMax
Model | SICA-88 | Candela CS8520 | MiPLATO-SiC
Scan method | X-Y with TDI camera | R-Theta with PMT | R-Theta with PMT
Detection method | PL 2 ch & Surface (confocal+DIC) | PL, reflection & scattering | PL 3 ch/Surface/Spectrum
Light source | Hg-Xe lamp | 355 nm normal laser | Laser
Surface : 546nm | 405 nm oblique laser | Surface : 355nm laser DIC
PL : 313nm/365nm |  | PL : 355nm

Results and Disussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.246.pdf

It is found that higher post-growth thermal processing temperatures generated more BPDs in wafers as shown in Fig. 1, but the correlation is not strong due to different sampling sizes at different processing temperatures. The driving force for BPD multiplication is the shear stresses in 1) the primary slip direction, that is, the and 2 ) in prismatic slip caused by thermal gradients during the boule growth [5, 6]. The Frank-Read source could be also responsible for multiplication. Higher post-growth thermal processing temperature causes more dislocation gliding and multiplication to result in higher BPD values.

Figure 1. Normalized mean BPD values measured for different post growth thermal processing. Thermal temperatures are increasing from A to E. Processing duration time and cooling rate were fixed. The quantile box plot shows median, 25th and 75th pecentiles. Wafers in this plots include multiple crystals grown from different seeds. BPD values are counted by XRT imaging and counting method.

Figure 1. Figure 1. Normalized mean BPD values measured for different post growth thermal processing. Thermal temperatures are increasing from A to E. Processing duration time and cooling rate were fixed. The quantile box plot shows median, 25th and 75th pecentiles. Wafers in this plots include multiple crystals grown from different seeds. BPD values are counted by XRT imaging and counting method.

Features in the CS8520 ScN image (scattering channel images from the normal laser) match well with BPD lines in XRT images from ( ) as shown in Fig. 2. Wafers processed at different thermal processing temperatures, however, show different CS8520 feature densities as shown in Fig. 3 even at very comparable disloction densities. It was also learned later that those features in CS8520 images could be eliminated or made invisible by further thermal processing. Dislocation decoration by point defects or dopants has been proposed to explain dislocation visiblity in CS8520 images. Interaction between strain fields associated with dislocation lines and point defects/dopants could be a thermal process and depend on energy and entropy of the process. This decoration process seems sensitive to post-thermal processing temperatures and is more aggressive in middle temperature ranges like process C and D as compared to the lowest and highest temperatures (process A and E ) in fig. 1.

Figure 2. XRT (left) and CS8520 ScN (right) images from the same area. Marks in blue and yellow are only for visual guidance.

Figure 2. Figure 2. XRT (left) and CS8520 ScN (right) images from the same area. Marks in blue and yellow are only for visual guidance.

Figure 3. CS8520 ScN images from wafers processed at different post-growth thermal processing temperatures. 36-08 (left) and 71-10 (right) were processed at process D and A, respectively. Bright lines in the images might be decorated dislocation lines. These two wafers show very comparable wafer resistivities and BPD densities.

Figure 3. Figure 3. CS8520 ScN images from wafers processed at different post-growth thermal processing temperatures. 36-08 (left) and 71-10 (right) were processed at process D and A, respectively. Bright lines in the images might be decorated dislocation lines. These two wafers show very comparable wafer resistivities and BPD densities.

To understand roles of point defects/dopants for dislocation visibilty (dislocation decoration) changes, room temperature PL spectra was obtained as shown in Fig. 4. The highly decorated wafer shows a stonger band-edge emission ( 390 nm ) than the un-decorated wafer. The peak around 500 nm could be the nitrogen donor-boron acceptor recombination-related emission [7]. The un-decorated wafer shows two peaks around 527 and 675 nm in the yellow region while the decorated wafer shows a single and dominant peak at 537 nm (PLATO data). The peak at 537 nm could be sum of the two separate peaks at 520 and 675 nm . Previously centers were characterized by the near infrared PL peak around 1300 nm in SiC [8] but origins of peaks from 500 to 700 nm in SiC are not clear at the moment. Wafers at different dislocation visibilities show differnt PL spectra in yellow region. Further work is needed to understand this observation.

Figure 4. PL Spectra from two spectrometer tools. Laser Power/Diameter: (PLATO), (MiPLATO), Spectrometer: Andor SR303i/idus Du-420A-BU2, 150G gratings/ 500 um entrance slit, exposure time: 500 msec (PLATO) and 50 msec (MiPLATO), MiPLATO use a mirror for laser beam reflection and PL transmission. Data collection and analysis by courtesy of EtaMax. 36-08 and 71-10 were processed at process D and A, respectively.

Figure 4. Figure 4. PL Spectra from two spectrometer tools. Laser Power/Diameter: (PLATO), (MiPLATO), Spectrometer: Andor SR303i/idus Du-420A-BU2, 150G gratings/ 500 um entrance slit, exposure time: 500 msec (PLATO) and 50 msec (MiPLATO), MiPLATO use a mirror for laser beam reflection and PL transmission. Data collection and analysis by courtesy of EtaMax. 36-08 and 71-10 were processed at process D and A, respectively.

Some of processed wafers in this study show dark lines and dots in PL images from SICA 88 (NIRW filter) tool as shown in Fig. 5. Those lines and dots correspond to BPDs and TDs, respectively and non-radiative recombination centers along the dislocations formed by decoration of point defects/dopants were proposed [7]. It is also observed that dislocation visibility changes in SICA PL image are significant (a few orders of magnitude in area density) even at very comparable dislocation densities.

Figure 5. SICA 88 NIRW PL images. Decorated wafer (left) and un-decorated wafer (right). Dots in the left image are classfied as PL black dots from the tool vendor defect count recipe. These two wafers are very comparable in both dislocation density and crystal quality. Markers and IDs in the image (left) are generated by the defect recipe.

Figure 5. Figure 5. SICA 88 NIRW PL images. Decorated wafer (left) and un-decorated wafer (right). Dots in the left image are classfied as PL black dots from the tool vendor defect count recipe. These two wafers are very comparable in both dislocation density and crystal quality. Markers and IDs in the image (left) are generated by the defect recipe.

To explain dislocation visibility changes, a simple sketch as shown in Fig. 6 has been proposed as a working hypothsesis. Two major factors play a role to determine dislocation visilibity. First is matrix absorbance, which is light absorbance by SiC wafer itself. Nitrogen dopants or various point defects including complexes could be major variables to control light absorbance. Second could be dislocation decoration itself. Local refractive index, recombination rate or charge states along the dislocations lines could be changed signifcantly to alternate light scattering or PL generation.

Figure 6. Schematic sketch to visualize dislocation decoration and SiC matrix light absorbance for dislocation visibility changes.

Figure 6. Figure 6. Schematic sketch to visualize dislocation decoration and SiC matrix light absorbance for dislocation visibility changes.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.246.pdf

Post-growth thermal processing temperature affects BPD densities significantly. Higher temperature generates more BPDs through multiple slip mechanisms. Large variations in dislocation visibility from different surface inspection tool images are observed. Combination of matrix light absorbance and dislocation decoration has been proposed as a working hypothesis. Further work is needed to understand dislocation decoration by point defects or dopants. Better understanding of dislocation visibility changes in various surface inspection tool images is critical to assess wafer quality accurately.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.246.pdf

Semiconductor Today, Microelectronics, 11/16/2020

Ian Manning et al., Materials Science Forum Vol. 1004 (2020) 37-43

B. Gao and K. Kakimoto, Cryst. Growth Des., 14 (2014) 1272-1278

J. Guo et al., J. of Electronic Materials, 46 (2017) 2040-2044

C. Kawahara et al., Jpn. J. Appl. Phys. 53 (2014) 020304

T. Narahara et al., Materials Science Forum, Vol. 1004 (2020) 349-354

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Chapter 3

Characterization, Modelling and Defect Engineering

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 253-257

doi: 10.4028/p-90gl36

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-24

Revised:
2022-02-14

Accepted:
2022-03-07

Online:
2022-05-31

Identification of High Resolution Transient Thermal Network Model for Power Module Packages

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

Shuhei Fukunaga and Tsuyoshi Funaki

Division of Electrical, Electronic and Infocommunications Engineering, Graduate School of Engineering, Osaka University, Suita, Osaka 565-0871, Japan

Keywords: Power module, transient thermal resistance, deconvolution

Abstract

A transient thermal network model is utilized to design and evaluate the transient thermal characteristics of power modules. Static test method identifies the transient thermal network model from the time response of the junction temperature, which is obtained by using the temperature dependency in I-V characteristics of power devices. This paper experimentally evaluates the transient thermal network model obtained by an AD converter with high-speed sampling and high resolution. The high sampling frequency and resolution for measuring time response of the junction temperature enable to clearly identify the boundary on the transient thermal network model of a power module with the direct bonding copper substrate.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

High-frequency switching operation using SiC power semiconductor devices enables miniaturizing power electronics systems [1][2]. Miniaturization makes thermal management difficult due to increased heat dissipation per unit area/volume. Therefore, thermal design is a key factor for the miniaturization of power electronics systems to maximize the capability of SiC power semiconductor devices.

Thermal design of power module packages aims at spreading and transferring heat dissipated in power semiconductor devices. Heat spreading and transferring capability depend on the structure and material property of power module constitutions. Transient thermal characterization plays an important role in the thermal design of power module packages. A transient thermal network model, which consists of the thermal resistance and capacitance, is utilized to design and evaluate the transient thermal characteristics of power module packages. Static test method [3] is the standard method for identifying the transient thermal network model of power module packages from the junction of the power device to the heatsink. The model is obtained by deconvolution calculation from the time response of the junction temperature with the temperature dependency in I-V characteristics of power semiconductor devices.

We developed a signal processing algorithm to improve the identified transient thermal network models [4]. The developed algorithm enabled clearly to distinguish the boundaries on the structure function related to power module packages. The numerical calculation also revealed that high-speed sampling and high resolution in measuring the time response of the junction temperature improve the accuracy in identifying the transient thermal network model. This paper establishes a measurement system adopting an analog-to-digital (AD) converter with high-speed sampling and resolution. Its performance in identifying the transient thermal network model is experimentally evaluated for a SiC power module with the direct bonding copper (DBC) substrate.

Experimental Setup

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

An experimental setup to obtain the time response of the junction temperature ( Tj ) for a device on a studied power module based on the static test method [3] is illustrated in Fig. 1. SiC SBD S6305 (50 A, ) is attached on a DBC substrate, as illustrated in Fig. 2. A high-speed and high-resolution AD board M2p.5933-x4 (Spectrum) is installed in the controller PC. This AD board can sample the voltage up to 40 MHz with 16-bit resolution. It measures the time response of the
junction voltage in SBD for a fixed small measuring current in cooling transient after the thermal equilibrium condition by the self-heating for the large current. Thermal transient tester T3Ster (MentorGraphics) is used as a current source for heating and measurement current. T3Ster also measures the time response of the junction voltage with -bit resolution, simultaneously as a reference. The floor noise of the installed AD board in the measurement system is evaluated in Fig. 3. "DUT w/o bias" denotes that the studied module is connected to the system, and all the equipment is in a power-on state. The peak-to-peak voltages of the noise are , and 83.2 mV , respectively, for open, short, and the module is connected. The noise of the current source in T3Ster is significantly high, affecting the measured time response of the junction voltage. It is noted that the output data acquired in T3Ster is filtered for analysis, thus it is not shown here.

Figure 1 The experimental setup to obtain the time response of the junction voltage.

Figure 1. Figure 1 The experimental setup to obtain the time response of the junction voltage.

Figure 2 Cross-section image of studied power module substrate.

Figure 2. Figure 2 Cross-section image of studied power module substrate.

Table 1 Physical parameter of materials.

Figure 3 White noise into the AD converter.

Figure 3. Figure 3 White noise into the AD converter.

Figure 4 TSP of the DUT.

Figure 4. Figure 4 TSP of the DUT.

Heating and measuring current are 25 A and 10 mA , respectively. The heating and cooling time is the same 10 sec . The studied module is placed on the water-cooled heatsink, which is set as . The desired time response of the junction temperature is converted from that of the junction voltage using the temperature sensitive parameter (TSP). TSP is obtained in advance under the thermal equilibrium condition using thermostat SH-661 (ESPEC) from to at every for a constant small current 10 mA to SBD. The value of TSP for SBD is , as shown in Fig. 4.

The procedure to obtain a transient thermal network model is summarized as follow, which is addressed in [4]. First, the time response of the junction temperature for unit input power is transformed to by introducing the logarithmic time domain , and numerically differentiated as . The is filtered using the weighted Fourier transformation in the logarithmic frequency domain. The deconvolution calculation is performed for it. After this, the thermal time constant spectrum (TCS) is obtained from the filtered and a known weighted function. The Foster thermal network model obtained from TCS by deconvolution is transformed to Cauer thermal network model by Foster-Cauer transformation.

Figure 5 Power spectrum of . The effective bit length is the parameter.

Figure 5. Figure 5 Power spectrum of . The effective bit length is the parameter.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

The power spectra of experimentally obtained are shown in Fig. 5. The horizontal axis is the order to the fundamental frequency, and the amplitude is normalized for . The sampling frequency is 40 MHz . Here, the effective bit length of the measured data for the installed AD board is given as the parameter. Though the longer effective bit length provides a higher resolution by suppressing the quantization error as discussed in [4], no significant difference exists in Fig. 5. The noise amplitude of the current source in the black line of Fig. 5 is not negligible to each power spectrum. A digital filter or an electrical design of a measurement system is required to suppress the measurement noise for utilizing the high resolution.

Figure 6 Power spectrum of . The sampling frequency is the parameter.

Figure 6. Figure 6 Power spectrum of . The sampling frequency is the parameter.

The power spectra of are shown in Fig. 6. Here, the sampling frequency of the measurement is given as the parameter, and the effective bit length is 14 bits. An oversampling and decimation to suppress the quantization error and eliminate the noise is adopted [5]. The higher sampling frequency of the measurement gives a higher resolution, which coincides with our previous discussion in [4]. For example, the oversampling ratio for 40 MHz sampling frequency to 1 MHz is 40. Then, the signal-to-noise ratio (SNR) improves by 16 dB [5]. This value coincides with the result in Fig. 6.

Figure 7 The obtained transient thermal network model.

Figure 7. Figure 7 The obtained transient thermal network model.

The obtained transient thermal network model, or structure function, is shown in Fig. 7. The structure function represents the cumulative thermal capacitance as a function of the cumulative thermal resistance from the junction to the ambient based on the Cauer thermal network model. "Dif" denotes the differential structure function, which is obtained by numerically differentiating the structure function with . The differential structure function is utilized to detect the inflection points corresponding to the interface of components in power module packages. The red line is calculated from the time response of the by the installed AD board at 40 MHz sampling frequency and 14 bit effective bit length. The blue line is obtained from T3Ster as the reference. The differential structure function calculated from the time response of the with the installed AD board has clear inflection points compared to that by the T3Ster. It is noted that the transient thermal network model gives the isothermal line in the power module package, thus the inflection point does not clearly give the boundary for the constitution of the actual power module package exactly. The high resolution and
high-speed acquisition of the time response of achieve the higher resolution of the obtained transient thermal network. This helps to evaluate and design the transient thermal characteristics of power module packages.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

This paper experimentally evaluated the high-speed and high-resolution acquisition effect for identifying the transient thermal network model. A measurement system adopting an AD converter with a high sampling frequency and resolution was established in this paper. The higher resolution and the higher sampling frequency of the AD converter give the lower noise level. The established system was applied to identify the transient thermal network model of a SiC power module with a DBC structure. High sampling frequency and resolution achieved the higher resolution of the obtained transient thermal network model. This advantage helps to evaluate and design the transient thermal characteristics of power module packages.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

This work was partially supported by JSPS KAKENHI Grant Number 20J10227, Japan, and by JST Open Innovation with Enterprises, Research Institute and Academia (OPERA) Program Grant Number JPMJOP1841, JAPAN, and by NEDO Feasibility Study Program, Japan.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.253.pdf

J. L. Hudgins, G. S. Simin, et al.: IEEE Trans. Power Electron., 18 (3), pp. 907-914 (2003).

H. A. Mantooth, M. D. Glover, et al., IEEE Journal of Emerging and Selected Topics in Power Electronics, 2 (3), pp. 374-385 (2014).

JESD51-14, JEDEC (2010).

S. Fukunaga, and T. Funaki, IEICE NOLTA, 11 (2), pp. 157-169 (2020).

SLAA323A, Texas Instruments (2018).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 258-262

doi: 10.4028/p-6410dm

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-07

Revised:
2022-02-09

Accepted:
2022-03-07

Online:
2022-05-31

Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

The original version of this paper is available on https://www.scientific.net/MSF.1062.258.pdf

Johji Nishio , Chiharu Ota and Ryosuke lijima

Corporate Research & Development Center, Toshiba Corporation, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan

ajohji.nishio@toshiba.co.jp, chiharu.ota@toshiba.co.jp, ryosuke.iijima@toshiba.co.jp

Keywords: single Shockley stacking fault, transmission electron microscopy, UV illumination.

Abstract

Double-rhombic shaped single Shockley stacking faults (1SSFs) were considered to have a converted threading edge dislocation (TED) on the shallower side of the initial basal plane dislocation segments. However, the structural analysis using transmission electron microscopy (TEM) revealed other possible configuration of the double-rhombic 1SSFs expanded from basal plane dislocations (BPDs) of which both ends were connected with two TEDs.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.258.pdf

Forward voltage degradation, which is observed mainly in bipolar devices and also in MOSFETs fabricated on with a p-n junction, is widely known to be attributable to the expansion of 1SSFs in the epitaxial layer that originate from BPDs. Although many studies have proposed concepts for preventing the expansion of BPDs, such as reducing the minority carrier lifetime in the recombination-enhancing layers [1], BPDs are still present in commercially available epitaxial layers and cause variation in the threshold current density for 1SSF expansion.

Structural analysis is considered the key to better understanding how easily 1SSFs expand. We therefore previously investigated differences in the structure of partial dislocations (PDs) surrounding 1SSFs that had considerably different threshold current density for expansion [2]. We also examined PD combinations to determine whether they can expand even after the PD lines have been bent by the step-flow of the epitaxial growth [3,4]. In addition to the commonly observable triangular 1SSFs, different type of triangular 1SSFs that have right-angle on the deeper side of the epilayer and generated from short BPD segments were studied and the BPD was found to have TEDs on both ends [5]. Previous studies explored that the half-loop arrays of the dislocations [6,7] consist of short BPD segments accompanied by two TEDs to the epilayer surface on both ends.

In this study, we investigated the structure of double-rhombic 1SSFs to identify Burgers vectors and core species of the composing partial dislocations (PDs) and found that these is another type of BPD segment that has TEDs on both ends but one of which connected to the TED from the deeper side of the epilayer.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.258.pdf

Two types of double-rhombic 1SSFs (which we label 1SSF-A and 1SSF-B) were selected by photoluminescence (PL) imaging and expanded by UV illumination for 30 min ( ). Structural analysis was carried out by plan-view and cross-sectional transmission electron microscopy (TEM). To examine the fine structure of BPDs and 1SSFs, TEM sample preparation must first be performed by a focused ion beam (FIB) technique. For this, the depth of the 1SSF in the epilayer need to be determined precisely. Estimation from PL imaging can be misleading in terms of depth, because the shallowest ends of the BPDs are not always located at the very surface of the epilayer. Therefore, in this work, preliminary cross-sectional TEM specimens were sampled in locations that contained identical 1SSFs but away from the areas where structural analysis was desired. Based on the 1SSFs depth results, plan-view TEM samples were prepared by FIB. The analysis was performed and Burgers vectors, , were obtained by the extinction rule. From the plan-view TEM images, different
sampling points were determined for the following analyses of cross-sectional TEM and crosssectional scanning TEM (STEM) for high-resolution high-angle annular dark-field STEM (HAADFSTEM). Bright-field (BF) cross-sectional TEM images give information about how the BPD segments are connected with threading dislocations at each end. The HAADF-STEM images help determine the core species of PDs. The experimental procedure employed in this work is summarized in Fig. 1.

Fig. 1 Experimental procedure

Fig. 1. Experimental procedure

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.258.pdf

Measurement of 1SSF depths by cross-sectional TEM. Figures 2 and 3 show PL images and composite SEM images indicating the cross-sectional TEM sampling positions (dashed light-blue rectangles) and areas of 1SSF-A and 1SSF-B observed by plan-view TEM (dashed yellow rectangles), respectively. BF-TEM images acquired with a slight inclination of the sample toward the [0001] direction from the [-1100] zone axis for maximized contrast of 1SSFs. Corresponding 1SSF depths were found to be 3.21 and for 1SSF-A and 1SSF-B, respectively. Using these values, planview TEM samples were cut and thinned from the dashed yellow rectangle areas shown in Figs. 2(c) and 3(c).

Fig. 2 PL and composite SEM images of 1SSF-A: (a) 420 nm BPF, (b) 750 nm HPF, and (c) composite of (b) and an SEM image.

Fig. 2. PL and composite SEM images of 1SSF-A: (a) 420 nm BPF, (b) 750 nm HPF, and (c) composite of (b) and an SEM image.

Fig. 3 PL and composite SEM images of 1SSF-B: (a) 420 nm BPF, (b) 750 nm HPF, and (c) composite of (b) and an SEM image.

Fig. 3. PL and composite SEM images of 1SSF-B: (a) 420 nm BPF, (b) 750 nm HPF, and (c) composite of (b) and an SEM image.

Burgers vector determination by contrast analysis. The Burgers vectors for PDs surrounding 1SSF-A and 1SSF-B were determined based on the plan-view TEM images by the extinction rule under two-beam conditions using different vectors on the specimens sampled at the yellow-dashed lines in Fig. 2(c) and Fig. 3(c), respectively. Figure 4 shows the results of contrast analysis for

1SSF-A. Although 1SSF-A must have contracted and changed its shape [4], the contrast of each dislocation line disappeared when and 1-210 on the left (Fig. 4(b)) and right (Fig. 4(c)) dislocation loops, respectively. Because TEDs are observed as beard-like lines [2] in general planview BF-TEM as in Figs. 4 and 5, we considered the regions marked by the dark arrows correspond to TEDs and they are considered to be the edge positions of the initial unexpanded BPD segment. The structural information on 1SSF-A was summarized in Fig. 4(d). Here, in simplicity, the green dashed line in Fig. 4(d) represents the estimated initial BPD as a simple straight line. Figure 5 shows the results of contrast analysis for 1SSF-B. Also, 1SSF-B must have contracted and changed the shape, it seemed to have also two TEDs. The TED on the [11-20] side, the upper and lower line

Fig. 4 Plan-view BF-TEM results for 1SSF-A (part where TEDs were included): (a) , (b) , (c) , and (d) of PDs and unexpanded BPD.

Fig. 4. Plan-view BF-TEM results for 1SSF-A (part where TEDs were included): (a) , (b) , (c) , and (d) of PDs and unexpanded BPD.

Fig. 5 Plan-view BF-TEM results for 1SSF-B (parts where TEDs were included): (a)-(d) around the [11-20] side of TED, (e)-(h) around the [-1-120] side of TED, (a) and (e) , (b) and (f) , (c) and (g) , and (d) and (h) of PDs and unexpanded BPD.

Fig. 5. Plan-view BF-TEM results for 1SSF-B (parts where TEDs were included): (a)-(d) around the [11-20] side of TED, (e)-(h) around the [-1-120] side of TED, (a) and (e) , (b) and (f) , (c) and (g) , and (d) and (h) of PDs and unexpanded BPD.

contrast disappeared when -20 and -2110, respectively as seen in Fig.5(a) and (b). On the other hand, the TED on the [-1-120] side, the same tendency found in Fig.5(a) and 5(b) also appeared as shown in Fig. 5(e) and 5(f). Therefore, the structural information on 1SSF-B was summarized in Fig. 5(d) and (h). The initial BPD for 1SSF-B have been found to have its of [-12-10].
cross-sectional TEM results. Figures 6 and 7 show cross-sectional TEM images of 1SSF-A and 1SSF-B in FIB samples that were cut to include the TEDs at both ends of the unexpanded BPD segments. In Fig. 6, both ends of the 1SSF-A were found to be connected to TEDs where the unexpanded BPD segment had been previously. This result agrees well with previous etch-pit and PL studies on the half-loop arrays [6,7]. In the case of 1SSF-B, the distance between the two TEDs was so far that we could not acquire an image of them in a single shot. Both ends of 1SSF-B are shown in Fig. 7, where we can see that the deeper end of 1SSF-B is connected to a TED that might have come from the deep part of the epilayer, while the shallower end is connected to a TED that might have penetrated to the surface of the epilayer. We could explain that the TED-BPD-TED conversion was
the result of unstable step flow that once bent TED to BPD and converted back to TED. This speculation was derived from the fact that the region in Fig. 7 was close to the edge of the wafer and the angle between (0001) and TEDs are so different between Figs. 6 and 7, but further statistical study is necessary.

Fig. cross-sectional BF-TEM image of 1SSF-A.

Figure 6. Fig. cross-sectional BF-TEM image of 1SSF-A.

Fig. cross-sectional BF-TEM image of 1SSF-B.

Figure 7. Fig. cross-sectional BF-TEM image of 1SSF-B.

Cross-sectional STEM and HAADF-STEM. At the corresponding boundaries of the 1SSFs, different specimens for cross-sectional observation were cut perpendicular to the PD lines by FIB and HAADF-STEM analysis was performed with finish-to-start using the right-hand definition in the perfect crystal convention. The uniquely determined and core species for each PD are shown in three-dimensional schematics shown in Figs. 8 and 9, which speculatively show the unexpanded BPDs (Fig. 8(a) and Fig. 9(a)) and present a summary of the analysis results (Fig. 8(b) and Fig. 9(b)).

Fig. 8 Schematics of 1SSF-A structure: (a) unexpanded BPD, and (b) analysis results explaining PL imaging.

Fig. 8. Schematics of 1SSF-A structure: (a) unexpanded BPD, and (b) analysis results explaining PL imaging.

Fig. 9 Schematics of 1SSF-B structure: (a) unexpanded BPD, and (b) analysis results explainingr PL imaging.

Fig. 9. Schematics of 1SSF-B structure: (a) unexpanded BPD, and (b) analysis results explainingr PL imaging.

The inclination angle of DRSF was found to be determined by . Only the HLA-type BPD can form the DRSF as shown in Figs. 2 and 8 or upside-down. Although structural identification of the classified structures [8,9] suggests the possible assignment of the BPD segments, preventing the formation of these kinds of BPD segments remains a major issue to be solved.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.258.pdf

We investigated the structure of double-rhombic 1SSFs to identify Burgers vectors and core species of the composing PDs. From the results, we found that these are other types of BPD segments from the previously found ones in triangular 1SSF expanded toward substrate side [5] that had TEDs on both ends; one is HLA-type and another is different TED-BPD-TED origin.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.258.pdf

T. Tawara, et al., J. Appl. Phys. 120 (2016) 115101.

J. Nishio, A. Okada, C. Ota, and R. Iijima, J. Appl. Phys. 128 (2020) 085705.

J. Nishio, A. Okada, C. Ota, and R. Iijima, Jpn. J. Appl. Phys. 60 (2021) SBBD01.

J. Nishio, C. Ota, and R. Iijima, J. Appl. Phys. 130 (2021) 075107.

C. Ota, J. Nishio, A. Okada, and R. Iijima, J. Electron. Mater. 50 (2021) 6504.

S. Ha, H. J. Chung, N. T. Nuhfer, and M. Skowronski, J. Crystal Growth 262 (2004) 130.

N. Zhang, et al., Appl. Phys. Lett. 94, 122108 (2009).

A. Iijima, I. Kamata, H. Tsuchida, J. Suda, and T. Kimoto, Philos. Mag. 97, 2736 (2017).

H. Matsuhata and T. Sekiguchi, Philos. Mag. 98, 878 (2018).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 263-267

doi: 10.4028/p-oneqg9

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-12

Revised:
2022-02-10

Accepted:
2022-04-20

Online:
2022-05-31

Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

J. Woerle , M. Belanche , M. Negri , C. Lamontagne , F. Bonafè , R. Nipoti , U. Grossner

¹Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

Axcelis Technologies Srl, Agrate Brianza, Italy

Axcelis Technologies Inc., Beverly, MA, USA

CNR-IMM Bologna, via Gobetti 101, I-40129 Bologna, Italy

*awoerle@aps.ee.ethz.ch, belanche@aps.ee.ethz.ch, marco.negri@axcelis.com, christopher.lamontagne@axcelis.com, bonafe@bo.imm.cnr.it, nipoti@bo.imm.cnr.it, ulrike.grossner@ethz.ch

Keywords: Ion implantation, resistivity, thermal oxidation, oxidation rate.

Abstract

In this work, we study the impact of the dose rate on the electrical properties of aluminum ( p -body, -body-contact) and phosphorous ( n -source/drain) implanted 4 H -SiC. We find no significant differences for dose rates ranging from to . AFM scans across implanted and non-implanted regions after thermal oxidation and subsequent oxide etching reveal a clear dependence of the oxidation rate on the conduction type and doping concentration. In addition, we observe an increasing (decreasing) oxidation rate for increasing doping concentrations of the n-type (p-type) ion implanted areas.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

For many silicon carbide (SiC) based devices, selective doping by ion implantation is one of the most critical steps during the fabrication process. Undesired variations of the physical or electrical doping profile, increased lattice damage as well as modifications of the surface morphology after the activation annealing can have a significant impact on the final device performance [1-3]. Fortunately, many of the mentioned issues have already been studied in detail or are the focus of ongoing research; however, results are not always conclusive and can strongly depend on the sample preparation or technical details of the implantation and activation annealing process. Furthermore, ion implanters for research purposes may result in notable differences compared to industry-oriented implantation facilities where processes are often performed at much higher dose rates.

To address the open question of process reproducibility, we compare ion implantation and activation-annealing processes performed at two different implantation facilities and show that despite significant differences of the dose rate almost identical electrical properties may be achieved.

In the second part of this work, we focus on the oxidation properties of phosphorous and aluminum implanted SiC by performing an atomic-force microscopy (AFM) study of the surface morphology across the borders of ion-implanted areas and the non-implanted n-type epi-layer after thermal oxidation and subsequent oxide removal. In previous studies on heavily implanted or amorphous SiC [4,5], it was shown, that the lattice damage introduced during high-dose implantations resulted in enhanced oxidation rates, independent of the conduction type. In moderately doped SiC epitaxial layers, on the other hand, Kobayashi et al. [6] found a clear rate dependence both on the doping concentration and the conduction type with an increased oxide thickness for heavily doped n-type SiC and a reduced oxidation rate for p-type SiC . The authors explained their results by the presence of Si vacancies promoting surface reactions in the case of n -type SiC , as well as high densities of Al atoms in the oxide of heavily p-doped SiC, causing a deceleration of the oxide growth. Our AFM
analysis on implanted SiC confirms this trend; however, compared to epitaxial p-type SiC, in the case of Al-implanted SiC, the observed height variations after sacrificial oxidation are significantly higher.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

Within this study, we investigate phosphorous ( P ) and aluminum ( Al ) implantations on off <0001> axis, low-doped n-type 4H-SiC. The implantation parameters were chosen to reflect typical doping densities used for the fabrication of lateral SiC MOSFETs. The multi-energy implantations were performed either at a HV Tandetron 1.7 MeV accelerator (Samples A and B) or an Axcelis Purion tool (Sample C) [7], resulting in an implantation profile as described in Table I. Details on the implantation and annealing parameters are given in Table I. After removal of the capping layer and a cleaning step including a 44 nm thick sacrificial oxide, a gate oxidation in at followed by annealing in NO was performed on Sample C. The final gate oxide thickness was 45 nm . The oxide thickness on the non-implanted areas has been estimated by ellipsometry measurements. For the electrical analysis, Van-der-Pauw structures were fabricated for which either Ni or were used for ohmic contacts on the P and Al ion implanted areas, respectively.

Table I. Sample parameters for the ion implantation and subsequent activation annealing [8,9], where is the depth of the ion implanted region, and are ion implantation and post implantation annealing temperature, respectively, and post-implantation annealing time.

Fig. 1. Resistivity measurements extracted from Van-der-Pauw structures in the temperature range from 300 K to 650 K . (a) P implantation for source/drain, (b) Al implantation for the p-body, (c) Al implantation for the -body-contact.

Fig. 1. Resistivity measurements extracted from Van-der-Pauw structures in the temperature range from 300 K to 650 K . (a) P implantation for source/drain, (b) Al implantation for the p-body, (c) Al implantation for the -body-contact.

Electrical Characterization

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

In Fig. 1, the resistivity of source/drain (Fig. 1(a)), p-body (Fig. 1(b)), and p-body-contact (Fig. 1(c)) ion implanted layers for different dose rates during the implantation are compared. All curves show a negative temperature coefficient at low temperatures, which is more pronounced for the Al implantations. In agreement with previous reports [10], the resistivity decreases with increasing annealing time or annealing temperature. Despite the large differences in dose rate - 20 to 70 times larger in Sample C than in Samples A and B - very similar resistivity values between the samples are observed for both the dopants. This result highlights the possibility of reproducing studies performed on research facilities often using low dose rates in the context of industrial processing.

AFM Characterization

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

In a next step, modifications of the surface morphology due to thermal oxidation were studied. In addition to changes of the surface morphology introduced during activation annealing [11], also subsequent processing steps such as thermal oxidation may significantly alter the surface roughness. When growing an layer by thermal oxidation, a SiC layer of around of the oxide thickness is consumed. As the oxidation rate of epitaxial SiC shows a clear dependence on the doping sign and on the doping density [6], variations of the final oxide thickness and hence SiC consumption may be expected between ion-implanted and non-implanted regions undergoing the same oxidation process. Due to this variation in oxidation rate, the surface morphology across differently implanted areas may offer an estimation of the local oxide thickness on the differently ion implanted regions. Fig. 2 summarizes the results of this oxidation-induced step formation for sample C : compared to nonimplanted regions, the n -type implantation ( P density: ) exhibits an increased SiC consumption of around 7.5 nm , while both p-type implanted regions show less consumption of the SiC with height differences of 1.2 nm and 6.0 nm . For these Al -implanted areas, the reduction of the oxide growth rate is more pronounced for larger doping concentrations. Based on our results, a schematic drawing of the surface of a double-implanted MOSFET after thermal oxidation is depicted in Fig. 2(e).

The increased oxidation rate on ion-implanted SiC with respect to epitaxial SiC may be due to the sum of two effects, both enhancing the oxidation rate: enhanced surface reactions caused by Si vacancies [6], as well as the presence of lattice disorder even after the high temperature post implantation annealing [5]. However, when comparing our findings to the Deal-Grove model on epitaxially grown SiC [6] we find excellent agreement, suggesting no or only a minor contribution of lattice damage to the increased oxidation rate in ion implanted n-type regions.

Fig. 2. (a,b,c) AFM height maps of the SiC surface after oxide removal. (d) Corresponding height profiles extracted from the areas indicated in (a,b,c). Note the differences in scale. (e) Summary of all measured height differences with respect to the n-type epi region.

Fig. 2. (a,b,c) AFM height maps of the SiC surface after oxide removal. (d) Corresponding height profiles extracted from the areas indicated in (a,b,c). Note the differences in scale. (e) Summary of all measured height differences with respect to the n-type epi region.

In the case of Al implanted SiC , we observe a stronger reduction of the oxide growth rate compared to epitaxial p-type SiC: there, considering a similar doping concentration and oxide thickness, height differences around 0.5 nm compared to low-doped n-type or p-type SiC would be expected [6]. This discrepancy is unlikely to be the result of lattice damage in the annealed ion-implanted layer as this would lead to an enhanced growth rate. Instead, we tentatively attribute the reduced oxide growth for the Al-implanted regions to Al atoms from the consumed SiC : being trapped in the oxide the Al may hamper the diffusion from the surface towards the oxide/SiC interface where new oxide is formed.

Another interesting feature of Fig. 2(d) is the peak between the p-body and the epi-layer showing an intermediate region with a reduced SiC consumption compared to the p-body region. In the light of our previous discussion, such a peak may be justified by a local increase in the Al lateral depth profile. In fact, the simulation of the two-dimensional ion depth distribution at a mask border suggests a higher density of the implanted species along the lateral depth profile immediately below the mask border [12]. A similar increased concentration of the implanted dopant under mask border takes place in the case of the and implantations. The fact neither a peak nor a depletion are visible across the borders of the or the regions may be attributed to a less pronounced variation of the oxidation rate at elevated doping densities [6].

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

In this study, we compared ion implantation processes, which were performed at dose rates between and and find no significant difference in the resistivity values of the implanted areas. A subsequent AFM analysis of the SiC consumption during thermal oxidation across the implanted regions reveals height differences of up to 13.5 nm , suggesting a more pronounced doping dependence than what has been reported previously for epitaxial p-type and n-type SiC. Future work will focus on understanding the exact mechanism of the strong reduction of the oxidation rate for Al-implanted SiC as well as to improve the understanding of mask-related height variations observed at the edges of the implanted areas.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.263.pdf

We thank Mr. Fabrizio Tamarri and Mr. Michele Sanmartin for their help with sample processing at the CNR-IMM clean room facilities. The ETH Zurich Foundation is gratefully acknowledged for their financial support.

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T. Dalibor et al., Phys. stat. sol. (a) 162, 199 (1997).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 268-272

doi: 10.4028/p-224t76

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-03-15

Accepted:
2022-03-15

Online:
2022-05-31

Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method

The original version of this paper is available on https://www.scientific.net/MSF.1062.268.pdf

Yoshitaka Nishihara , Koji Kamei , Daisuke Shiomi and Kenji Momose

SHOWA DENKO K.K., 1505 Shimokagemori, Chichibu, Saitama 369-1893, Japan

nishihara.yoshitaka.xixlw@showadenko.com, kamei.koji.xheuz@showadenko.com, shiomi.daisuke.xhixv@showadenko.com, momose.kenji.xhipm@showadenko.com

Abstract

Photoluminescence (PL) imaging provide defect and dislocation characteristics not only in a 4 H silicon carbide ( SiC ) epilayer but also in a substrate. In this work, to detect a large-pit or a barshaped stacking fault (BSF) before epilayer growth, we employed PL under various detection conditions. A large-pit was detected as a dark spot on a substrate due to dislocations orthogonal to a micropipe. The BSF was clearly observed as a bright rectangle by tuning the observation conditions. The finding indicates that device killing defects or dislocations should be detected as soon as possible and thus improve the yield.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.268.pdf

Silicon carbide ( SiC ) is a promising material that can provide high performance power devices owing to its high breakdown field and thermal conductivity. However, various crystal imperfections prevent SiC devices from fulfilling their potential. The impact of such crystal defect has been studied to allow us to understand which defects damage the device yield and reliability. As a result, crystal growth and detecting defects techniques have been developed to reduce the number of defects in an epitaxial wafer. Initially microscopy was used to observe the wafer surface and confirm for defects, however, it is too difficult to detect and classify various defects precisely with this method. Moreover, defects in an epilayer, such as basal plane dislocations (BPDs) and stacking faults, cannot be observed with microscopy.

Photoluminescence (PL) imaging is a powerful tool for detecting extended or in-grown defects in an epilayer [1]. The defects are detected through the energy band of near-infrared (NIR) or nearultraviolet PL excited by ultraviolet light using a laser or lamp. In recent years, the PL technique has been employed at almost as a mass-production process. Although the defects on a SiC substrate should also be evaluated with PL observation, the method is rarely used because it is easily affected by the impurities included in a SiC crystal [2,3]. In this study, we observed large-pits (others (pits)) or bar-shaped stacking faults (BSFs, propagated stacking faults) [4] before growing an epilayer on the substrate due to using the improved PL measurement method.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.268.pdf

The samples used in this evaluation were commercially available n-type substrates with a off-cut angle toward in the [11-20] direction. These bare wafers were observed with a SICA88 (Lasertec Corp.), which provided confocal microscope images with differential interference contrast (CDIC) and PL. The PL imaging measurement was performed using various filters; the excitation source was extracted from a lamp through a 313 nm band pass filter (BPF), and the emission from the SiC wafers was cut off with the BPF or a long pass filter (LPF) to allow us to observe the NIR region clearly. After this evaluation, thick epilayers doped with nitrogen at were grown on these substrates by chemical vapor deposition. Subsequently, crosssectional scanning transmission electron microscopy (STEM) was performed on the epitaxial wafer to reveal the structural features of defects.

One sample was fabricated as a pin diode (PND) to evaluate the expansion of the basal plane dislocation caused by bipolar degradation. To design the PND with an acceptor box profile of , a -layer was formed by implanting Al ions to a depth of below the epilayer surface at room temperature with performing the activation annealing at for 10 min in Ar . For a package mounted on the PND chip diced at , a forward DC was applied for over 1 hour to introduce bipolar degradation.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.268.pdf

Large-pit Detection. Figures 1(a) and (b) show the CDIC and PL with LPF images of a large-pit detected in an epilayer. Both the pit structure and a bright spot at the same position were observed at the surface of the epilayer. This means that the pit was caused by a micropipe or a threading dislocation along with other dislocations formed in a direction parallel to the basal plane, which was introduced when the SiC substrate passed through the epilayer. Figure 1(c) shows a PL image observed at the same coordinates when using a 420 nm BPF with a PLIS-100 (PHOTON Design Corp.) after applying a direct current of for 1 hour to a PND fabricated on an epitaxial wafer. This image implies that extended SFs grown from the large-pit in the epilayer also contribute to bipolar degradation and need to be detected in an epitaxial wafer [5].

Fig. 1 (a)CDIC and (b)PL with LPF images on an epitaxial wafer. (c)PL in a 420 nm BPF image for the same region after applying DC stress to a PND fabricated using the wafer.

Fig. 1. (a)CDIC and (b)PL with LPF images on an epitaxial wafer. (c)PL in a 420 nm BPF image for the same region after applying DC stress to a PND fabricated using the wafer.

STEM image of a large-pit defect in an epitaxial wafer is shown in Fig. 2. A pit-shaped defect at the surface of the epitaxial wafer and a submicron size micropipe extending from the substrate to the epilayer are observed; moreover, dislocations formed from the micropipe caused by spreading in the basal plane are also found. This means that the large-pit causes bipolar degradation due to the expanded SFs from the dislocations. Furthermore, BPDs in the epitaxial wafer extended to triangular SFs, however, dislocations with large-pits can form bar-shaped SFs, which cover larger area of the chip than in the former case. Thus, it is preferable that the large-pit is detected before the epilayer is grown.

Fig. 2 Cross sectional STEM image of large-pit in a wafer.

Fig. 2. Cross sectional STEM image of large-pit in a wafer.

Figure 3 shows CDIC and PL with LPF images of a large-pit detected in a SiC substrate. The pit was found on the surface, which is the same as when it was measured in the epilayer, however, a dark spot was observed due to the different recombination paths in epilayers and substrates [2]. Thus, the large-pit on the substrate could be accurately examined by detecting pits on the surface with dark areas as nonradiative recombination centers in PL images.

Fig. 3 (a)CDIC and (b)PL images observed on a SiC substrate.

Fig. 3. (a)CDIC and (b)PL images observed on a SiC substrate.

BSF Detection. With other epitaxial wafers, PL imaging was used to detect BSFs, when no structures were found on the surface using CDIC mapping. Figure 4 shows several dark rectangles indicating BSFs that extended into the epilayer from the SiC substrate that were observed by using PL imaging with an LPF. Owing to all the BSFs extending to the epilayer from the SiC substrate, they should be detected before the epilayer is grown in order to reduce the number of fabricated epitaxial wafers that include many BSFs.

Fig. 4 PL image observed on an epilayer.

Fig. 4. PL image observed on an epilayer.

Figures 5(a) and (c) show PL images observed with the conventional PL measurement method. BSFs can be found in both images, however, there is a concern that some BSFs may be missed, because one exhibited a very weak contrast with the background and another exhibited a different degree of contrast. These BSFs found as bright contrast (Fig. 5(a)) and dark contrast (Fig. 5(c)) make difficult to detect automatically using various inspection tools. To make it possible to observe BSFs clearly, an improved PL measurement method with choosing suitable detection wavelength using the BPF was employed for the same region, and the results are shown in Figs. 5(b) and (d). The bright area of BSFs observed clearly in both PL images helped us calculate the BSF area or yield and determine whether an epilayer was grown on the substrate.

Fig. 5 PL images observed same location (a)/(b) and (c)/(d) on a SiC substrate using (a), (c)the conventional measurement method, and (b), (d) the improved method.

Fig. 5. PL images observed same location (a)/(b) and (c)/(d) on a SiC substrate using (a), (c)the conventional measurement method, and (b), (d) the improved method.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.268.pdf

The SiC wafer yield must be increased to reduce the total cost of the SiC device or module so that their use will become more widespread. Therefore, we have to know which wafers were grown the epilayer with priority while considering how many wafers include killer defects such as large-pits or BSFs. This study provides us selection methods for use SiC wafers before epitaxial growth that employ an improved PL evaluation technique.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.268.pdf

G. Feng, J. Suda, and T. Kimoto, Appl. Phys. Lett. 92, 221906 (2008).

C. Kawahara, J. Suda, and T. Kimoto, Jpn. J. Appl. Phys. 53, 020304 (2014).

Y. Nishihara, K. Kamei, K. Momose, and H. Osawa, Mater. Sci. Forum 963, 272-275 (2019).

JEITA EDR-4712/100.

T. Ishigaki, T. Murata, K. Kinoshita, T. Morikawa, T. Oda, R. Fujita, K. Konishi, Y. Mori, A. Shima, Proc. 2019 IEEE 31st ISPSD, 259-262, 2019.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 273-277

doi: 10.4028/p-ek87hw

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-13

Accepted:
2022-03-07

Online:
2022-05-31

Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

The original version of this paper is available on https://www.scientific.net/MSF.1062.273.pdf

Kazumi Takano and Yasuyuki Igarashi

ITES, 800 Ichimiyake, Yasu, Shiga 520-2362, Japan

email: kazumi_takano@ites.co.jp, email: yiga@ites.co.jp

Keywords: shockley-type stacking fault, basal plane dislocation, ultraviolet irradiation, ultraviolet photoluminescence, Recombination-enhanced dislocation glide

Abstract

We propose the new practical and effective method, called Selective E-V-C (Expansion-Visualization- Contraction) technique, to screen out the basal plane dislocations (BPDs) which might cause the forward voltage degradation of SiC devices. Since the method can be adopted at the epi wafer receiving inspection process in early stage of production line, it may replace the very time-consuming so-called "burn-in" operation currently utilized in some device manufacturers.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.273.pdf

Almost two decades have passed since the reliability issue of the forward voltage degradation of 4H-SiC devices was first reported [1,2], and since then extensive studies on the issue have been carried out by many researchers, to prove that the degradation is caused by the nucleation and expansion of a single SSF (Shockley-type stacking fault) [3]. The origin of the SSF is a BPD (basal plane dislocation) which exists in the epilayer or near the epilayer and the substrate (epi/sub) interface. The SSFs are expanded by the electron-hole recombination energy when excessive minority carriers are injected into the regions in the vicinity of the BPDs, which is called REDG (recombination-enhanced dislocation glide) mechanism.

The density of BPDs has been drastically reduced mainly by raising the conversion ratio from BPDs in the substrate to benign TEDs (threading edge dislocations) during the epitaxial growth process. However, it was found in recent years that the converted BPDs also expand to SSFs from a BPD-to-TED conversion point [4]. Therefore, in order to prevent the SSF expansion from the conversion point, an introduction of a highly nitrogen-doped buffer layer has been proposed between the low doped drift layer and the substrate, which significantly shortens minority carrier lifetime to reduce the density of injected minority carriers around the epi/sub interface [5]. An adoption of the buffer layer has a great effect on suppressing SSF formation, but it is still never completely eliminated. This means that, among TED-converted BPDs in buffer layer, some tend to expand to SSFs, while others do not. Therefore, on mass production line, there is a strong need for screening out the "malignant" BPDs in buffer layer that will potentially expand to SSFs under forward bias operation. In some device manufacturers so-called "burn-in" screening is currently performed, in which the forward voltage degradation is checked, chip by chip, by applying forward current stress for a certain period. This is a very time-consuming process which raises a total cost of production.

This paper focuses on how to capture TED-converted BPDs in buffer layer and also how to screen only BPDs that tend to expand, and using these methods, we propose the new practical and effective method, called Selective E-V-C (Expansion-Visualization-Contraction) technique [6].

In Selective E-V-C method, at the epi wafer receiving inspection stage, first, both threading BPDs and TED-converted BPDs are captured. Threading BPD means the BPD reaching drift layer surface and TED-converted BPD means the BPD which is converted to TED in drift layer or in buffer layer (including at drift/buffer layer interface). We capture the BPD in drift layer as straight bright line and the BPD in buffer layer as straight dark line by UVPL (ultraviolet photoluminescence) observation [Selection]. Second, UV irradiation is utilized to expand the BPDs
to SSFs [Expansion], which is the same REDG phenomenon as in the case of forward voltage degradation by forward current stress. Third, the expanded SSFs are made visible by UVPL imaging [Visualization] and their distribution map is recorded, and finally the SSFs are contracted by heating under weak UV irradiation in order to return the SSFs to their original or near-original state of the BPDs [Contraction]. By referring to the recorded SSF distribution map, it is possible to accurately identify where on the wafer the defects that cause forward voltage degradation reside, without loading any excessive current that exceeds the maximum rating such as "burn-in" screening (acceleration test).

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.273.pdf

For this work, the sample investigated was a commercially available n-type -SiC substrate with a off-cut angle, on which highly nitrogen-doped buffer layer ( ) and low doped drift layer ( ) were epitaxially grown. The total observation area was .

First, the UVPL images on the BPDs present in the buffer layer as well as in the drift layer, were taken using 380 nm BPF (bandpass filter). Those BPDs can be captured as straight dark line by using NUV (near-ultraviolet) BPF , as reported in some previous papers [7,8]. Fig. 1 depicts observable types of BPDs by using 380 nm (NUV) BPF, and an example is shown in Fig.2A.

Fig. 1 Threading and TED-converted BPDs

Fig. 1. Threading and TED-converted BPDs

Drift layer thickness Buffer layer thickness

Substrate thickness BPD density

Fig. 2. UVPL image by excitation light (Mercury-Arc lamp )
(a) A BPD converted to TED within drift layer.
(b) A BPD converted to TED near interface between drift layer and buffer layer.
(c) A BPD converted to TED within buffer layer.

Fig. 2. UVPL image by excitation light (Mercury-Arc lamp ) (a) A BPD converted to TED within drift layer. (b) A BPD converted to TED near interface between drift layer and buffer layer. (c) A BPD converted to TED within buffer layer.

Second, the UVPL image on the same area with over 700 nm LPF (long-pass filter) was taken, which is capable of only capturing BPD segments in drift layer (Fig.2B). By superimposing the first image and the second image, the BPD in buffer layer and that in drift layer was able to be separated. Third, for BPDs to expand, UV light from Hg-Xe lamps was irradiated over the sample through a quartz fiber with diameter of 8 mm . The irradiation conditions were approximately using a Hg -Xe fiber light source for 4 hours on a cool plate. After UV exposure, the expanded SSFs were examined by UVPL with 420 nm BPF(Fig.3A). Finally, in order to observe closely inside buffer layer, drift layer was completely removed by planarly polishing of 11 from the surface ( buffer layer remained), followed by UVPL observation with 380 nm BPF (Fig.3B).

Fig.3. UVPL image by excitation light (Mercury-Arc lamp )
(a) A BPD that converted to TED within drift layer expanded to SSF.
(b) A BPD that converted to TED near interface expanded to SSF.
(c) A BPD that converted to TED within buffer layer did not expand to SSF after 4 hours of UV irradiation.

Fig.3. UVPL image by excitation light (Mercury-Arc lamp ) (a) A BPD that converted to TED within drift layer expanded to SSF. (b) A BPD that converted to TED near interface expanded to SSF. (c) A BPD that converted to TED within buffer layer did not expand to SSF after 4 hours of UV irradiation.

Table I. Expansion Result

UV Dosage | Number of Tested BPDs | Number of Expanded BPDs
50 mJ/cm² | 36 | 0
100 mJ/cm² | 36 | 8
200 mJ/cm² | 29 | 15
400 mJ/cm² | 29 | 29

Total observed area was , and Table I summarizes the observed BPDs and SSFs, and the following notable facts have been found.

All the BPDs in drift layer (both threading and TED-converted) expanded, and the expanded area was extended into buffer layer in all cases. Because of different SSF expansion velocity between in drift layer and in buffer layer, double-shaped triangles were observed (Fig.4).

On the other hand, some BPDs in buffer layer expanded and some did not. Even unexpanded one appeared as a bright line at 420 nm BPF, so it seemed that the BPD was dissociated into two partial dislocations, in a state of beginning of SSF expansion.

From the length of dark line in buffer layer, the location of TED-converted point (namely, the depth from buffer/drift (b/d) interface) can be estimated. The BPD with deep converted point was expected to be hard to expand as compared with the BPD with the converted point near b/d interface because of short minority carrier lifetime within buffer layer. However, that was not always the case. This means that the ease of expansion cannot be determined by the depth of the converted point alone. Currently, it seems that the most practical way to determine if the buffer layer BPD expands or not is to simulate forward bias degradation with UV irradiation to identify SSF expansion.

Fig. 4. Selective E-V-C technique

Fig. 4. Selective E-V-C technique

Based on these results, we propose a new practical and effective screening procedure to identify malignant BPDs within buffer layer, which expand to SSFs (Fig.4).

Step-1) BPD identification by UVPL with 380 nm BPF (UV irradiation area selected)
Step-2) UV irradiation over the selected area (expansion)
Step-3) SSF observation by UVPL with 420 nm BPF (visualization)
Step-4) Heating process (contraction of SSF and dissociated BPD)
Final heating process has an effect of contracting both SSFs and dissociated BPDs returning to their original or near-original state of the BPDs. In our experiment, almost all the expanded SSFs were contracted by heating for 1 hour.
"In our experiment, we needed 4 hours for each SSF expansion by using Hg-Xe UV lamps. To shorten irradiation time, we recently changed the excitation source from UV lamps to UV laser, and roughly 100 to 1000 times faster expansion speed is obtained, so far."

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.273.pdf

The practical and effective way to screen out the BPDs which might cause the forward voltage degradation is presented, using UV irradiation and UVPL observation. We call it Selective E-V-C technique, and it has a potential to replace the time-consuming "burn-in" screening process.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.273.pdf

H. Lendenmann, F. Dahlquist, N. Johansson, R. Soä derholm, P.A. Nilsson, J. P. Bergman and P. Skytt: Mater. Sci. Forum, 353-356, 727 (2001).

J. P. Bergman, H. Lendenmann, P. A. Nilsson, U. Lindefelt, and P. Skytt, Mater. Sci. Forum 353-356, 299 (2001)

M. Skowronski and S. Ha, J. Appl. Phys. 99, 011101 (2006).M. Skowronski and S. Ha, J. Appl. Phys. 99, 011101 (2006).

A. Tanaka, H. Matsuhata, N. Kawabata, D. Mori, K. Inoue, M. Ryo, T.Fujimoto, T. Tawara, M. Miyazato, M. Miyajima, K. Fukuda, A. Ohtsuki, T. Kato, H. Tsuchida, Y. Yonezawa, and T. Kimoto, J. Appl. Phys. 119, 095711 (2016).

T. Tawara, T. Miyazawa, M. Ryo, M. Miyazato, T. Fujimoto, K. Takenaka, S. Matsunaga, M.Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto, and H. Tsuchida, J. Appl.Phys. 120, 115101 (2016)

PCT/JP2021/ 7020

H. Das, S. Sunkari, H. Naas, M. Domeij, A. Konstantinov, F. Allerstam, T. Neyer, Mater. Sci. Forum, 897, pp222-225 (2017)

H. Itoh, T. Enokizono, T. Miyase, T. Hori, K. Wada, H. Doi, M. Furumai, Mater. Sci. Forum, 1004, pp 71-77 (2020)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 278-282

doi: 10.4028/p-85482w

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-08

Accepted:
2022-03-31

Online:
2022-05-31

Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection

The original version of this paper is available on https://www.scientific.net/MSF.1062.278.pdf

Meli Alessandro , Muoio Annamaria , Reitano Riccardo , Trotta Antonio , Parisi Miriam , Meda Laura and La Via Francesco

¹Dipartimento di Fisica e Astronomia-Università di Catania, Via Santa Sofia 64, 95123 Catania, italy

CNR-IMM Headquarter, Strada VIII 5,95121 Catania, Italy

ENI-MAFE, Via A. Pacinotti 4, 30175 Venezia, Italy

ENI-Renewable Energy and Environmental TECH R&D Center, Via G. Fauser 4, 28100 Novara, Italy

alessandro.meli@imm.cnr.it, annamaria.muoio@imm.cnr.it, riccardo.reitano@ct.infn.it,

Antonio.Trotta@eni.com, miriam.parisi@eni.com, laura.meda@eni.com, 9francesco.lavia@imm.cnr.it

Keywords: 4 H -SiC; neutron detector; epitaxial growth; micro-Raman; i-LOPC, oxidation process, carrier lifetime.

Abstract

In the present work a deep characterization of epi-layer was done. A thick layer was epitaxially grown through chemical vapor deposition (CVD) process in a horizontal hot-wall reactor to obtain a 250 microns thick epi-layer. This sample will be used as particles detector in hostile environments such as neutron detection in a nuclear fusion reactor. Raman and Photoluminescence (PL) spectroscopy have been used to evaluate the quality of epitaxial layer observing the presence of long-range defects. With the support of the Time Resolved Photoluminescence, also important properties such as carrier lifetime and diffusion length were evaluated. Carrier lifetime evaluation before and after a thermal oxidation process at for 48 h was estimated, by considering a lifetime increment after oxidation process, due to the decrease of carbon vacancies. Finally, the influence of stacking fault (SF) defects on carrier lifetime was evaluated observing a decrease of the lifetime for the defects at for both oxidated and non-oxidated samples.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.278.pdf

Silicon carbide ( SiC ) is a wide bandgap semiconductor material with a rigid stoichiometry of . It has various crystalline structures, among which the most interesting for electronic applications are called 3C, 6H and 4H. These crystalline phases show a band gap with values ranging from 2.9 to 3.2 eV from 3 C to 4 H polytypes. Furthermore, the thermal conductivity of SiC , much higher than that of Silicon ( 4.9 versus ), as well as its dielectric strength ( 4.106 versus ) and the electron saturation rate ( 2.107 against ), make this material particularly suitable for high temperature, high voltage or power applications, with non-negligible effects on the efficiency of the electronic systems [1] [2] [3]. A new field of application of material is as detector in harsh environments, [4] where the temperature and the radiation exposure are critical for other semiconductor devices such as silicon. Therefore, the radiation hardness allows the use of SiC material as neutron detector in thermonuclear fusion reactor. Improvements in SiC wafer growth processes and the good quality of the material, with a low defect density, makes this material competitive with Single-Crystal Diamonds (SCD) detectors, currently used in this field.

In a previous paper [5] a comparison between SCD and SiC detectors was reported, observing an increase in resolution for SCD detectors with increasing thickness. Then to increase the resolution of the SiC detectors is necessary to increase considerably the thickness of the epitaxial layer.

The purpose of this work is to study the epitaxial layer properties for the fabrication of a device for neutron detection as an alternative material to diamond detectors used in this field. We have studied a high growth rate process to grow a thick epitaxial layer of and, to estimate the quality of the epitaxial layer, an optical characterization was done through Photoluminescence (PL) spectroscopy for stacking fault defect evaluation. Micro Raman spectroscopy was used for simultaneous determination of both carrier lifetime and induced carriers in equilibrium [7], through the shift of the LO peak. The study of the carrier lifetime and diffusion length is necessary because these parameters are fundamental to collect all charges generated by neutrons, and therefore, to obtain a good signal from these thick detectors. We have compared these results with other two samples with an epitaxial layer of 100 micron (Fig. 1a) obtained with two different growth rates, 60 and , respectively. From Raman measurements it has been observed that both the growth rate and the grown epitaxial layer thickness influence the measured carrier lifetime [8].

Time resolved photoluminescence (TRPL) characterization was done to estimate the carrier lifetime in a low injection regime and, using different wavelengths of the source, the lifetime trend across the entire thickness was analysed (Fig. 1b). In order to increase the carrier lifetime, a thermal oxidation process was carried out, to reduce the carbon vacancies in the entire epitaxial layer [9]. From these results it has been observed that the oxidation process at high temperature ( ) for long time ( 48 h ) has a large effect both on the maximum carrier lifetime and on the uniformity of this parameter along the entire thickness of the epitaxial layer. Finally, a comparison between different kinds of stacking faults (SF) was done, so evaluating the influence of these defects on the carrier lifetime as a function of the injection level and it was observed that at a low injection level the effect on the carrier lifetime is low.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.278.pdf

The spectroscopical characterization through Raman and PL maps was done, for carrier lifetime and stacking faults (SFs) defects evaluation respectively. The sample is a wafer of 4 inches with an epi-layer grown by chemical vapor deposition (CVD) process in a horizontal hot-wall reactor. The volume of the epitaxial layer is fundamental for the neutron detection because the signal analyzed is due to the interaction between neutron with silicon and carbon nuclei generating various reactions, as described in literature [10], and the study of fluence obtained by FLUKA tool [11] highlights the importance of the volume. Therefore, we investigated a thick epi-layer which could be used for detection applications.

An important parameter that describes the quality of the epilayer is the carrier lifetime and it was defined through Raman analysis using Longitudinal Optical Phonon-plasmon Coupling (LOPC) mode and Time resolved Photoluminescence (TRPL) to evaluate the lifetime in a high and low injection regime respectively. In Fig. 1 the carrier lifetime as a function of carrier density (Fig. 1a) and laser power (Fig. 1b) are shown. In particular, Fig. 1a shows the comparison between samples with different thickness and growth rates. These samples were previously grown epitaxially with the same CVD process in the same horizontal hot-wall reactor with a similar process. The lifetime was evaluated by LOPC mode for high carrier densities induced in the epi-layer and TRPL for lower carrier density. An increase of carrier lifetime when the carrier density decrease is observed. Furthermore, for the epitaxial growth an epilayer with a lower density of defects with respect to the is obtained. Then, in the case of the thick epi-layer, we have decided to use the same growth rate. This behaviour is connected with the concentration of point defects at higher growth rate as previously defined in literature [12] [13].

Figure 1. (a) The figure shows the trends of the carrier lifetimes as a function of carrier density for all analyzed samples; (b) Carrier lifetime(blue and red dots) and carrier induced (green and black lines) as a function of laser power used for 250 um thick sample before and after oxidation process.

Figure 1. Figure 1. (a) The figure shows the trends of the carrier lifetimes as a function of carrier density for all analyzed samples; (b) Carrier lifetime(blue and red dots) and carrier induced (green and black lines) as a function of laser power used for 250 um thick sample before and after oxidation process.

A common defect that influences the carrier lifetime is the center, defined as a carbon vacancy in the crystalline structure. There are some processes that allows a decrement of these defects such as oxidation and passivation processes. An oxidation process at for 48 h was done and the carrier lifetime values as a function of laser power used are shown in Fig.1b, compared with values obtained for non-oxidated sample. An increase in lifetime is observed (blue dots) at low power after the oxidation process even if the carrier induced values are higher than the non-oxidated sample. This Raman analysis took place in long-range defect-free areas. However, by photoluminescence maps, some stacking faults (SFs) are found and a study of the influence of these SFs on the carrier lifetime after the oxidation process was evaluated. Fig. 2a shows a PL map of an isolated stacking fault at .

b)

Figure 2. b)

Figure 2. (a) PL map of a stacking fault defect at 430 nm ( 2.88 eV ). (b) LO peak shift at 15 and and OUT (in proximity) of the defect.

By Raman analysis a comparison between the LO shift ON-SF and in its proximity (OUT-SF) was done, observing a decrease of difference in the peak shape and position when the laser power decreases (Fig. 2b). This effect is probably due to the fact that if the carrier lifetime and the diffusion length increases and then this measure is averaged over a larger region around the SFs, the effect on the carrier lifetime and the induced carrier is lower. Therefore, on a 430 nm defect, which is the most common defect present on the wafer, a lower lifetime than in the SF-free area is observed also after the oxidation process. Furthermore, not all types of stacking faults react in the same way. In facts, the defect at 490 nm , seems to be affected by the oxidation process, leading to a longer lifetime, in any case with a lower value than the value obtained in the defect-free area.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.278.pdf

A thorough characterization of epitaxial layer, previously grown, was done to evaluate, an important parameter for neutron detectors such as carrier lifetime. The thick layer is important for the application of this device, that will be used in a thermonuclear fusion reactor. From this study we have observed that very high carrier lifetime (more than ) can be obtained using not extremely high growth rate ( ) and with a high temperature oxidation process. It has been observed also that the different SFs present in the epitaxial layer have a limited effect on the carrier lifetime.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.278.pdf

P. G. Neudeck, R. S. Okojie and L. Y. Chen, "High-temperature electronics-A role for wide bandgap semiconductors?," Proc. IEEE, vol. 90, no. 6, pp. 1065-1076, 2002.

R. Maboudian and e. al., "Advances in silicon carbide science and technology at the micro-and nanoscales," J. Vac. Sci. Technol. A, vol. 31, no. 5, p. 050805, 2013.

B. J. Baliga, Fundamentals of Power Semiconductor Devices, New York: Springer, 2008, p. 215.

S. Tudisco, F. La Via and etal, "Silicon Carbide Detectors for Intense Luminosity Investigations and Applications," Sensors, vol. 18, no. 2289, 2018.

M. Rebai, D. Rigamonti, S. Cancelli, G. Croci, G. Gorini, E. Cippo, O. Putignano, M. Tardocchi, C. Altana, M. Angelone and e. al., "New thick silicon carbide detectors: Response to 14 MeV neutrons and comparison with single-crystal diamonds," Nuclear Inst. And Methods in Physics Research, vol. A 946, p. 162637, 2019.

F. La Via, M. Camarda and A. La Magna, "Mechanisms of growth and defect properties of epitaxial SiC," Applied physics reviews 1, no. 031301, 2014.

N. Piluso, M. Camarda and F. La Via, "A novel micro-Raman technique to detect and characterize 4H-SiC stacking faults," Journal of applied physics, vol. 116, p. 163506, 2014.

A. Meli, A. Muoio, A. Trotta, L. Meda, M. Parisi and F. La Via, "Epitaxial Growth and Characterization of 4H-SiC for Neutron Detection Applications," Materials, vol. 14, no. 976, 2021.

S. Ichikawa, K. Kawahara, J. Suda and T. Kimoto, "Carrier Recombination in n-Type 4H-SiC Epilayers with Long Carrier Lifetimes," Applied Physics Express 5, no. 101301, 2012.

F. Ruddy, A. Dulloo, J. Seidel, M. Das, S.-H. Ryu and A. Agarwal, "The fast neutron response of 4 H silicon carbide semiconductor radiation detectors," IEEE Trans. Nucl. Sci., vol. 53, p. 1666-1670, 2006.

« [Online].

M. Camarda, A. La Magna, P. Fiorenza, G. Izzo e F. La Via, «Theoretical Monte Carlo study of the formation and evolution of defects in the homoepitaxial growth of SiC,» Mater. Sci. Forum, vol. 135, pp. 600-603, 2009.

F. La Via, G. Galvagno, A. Firrincieli, F. Roccaforte, S. Di Franco, A. Ruggiero, M. Barbera, R. Reitano, P. Musumeci, L. Calcagno and e. al, "Epitaxial layer grown with HCl addition: A comparison with the standard process," Mater. Sci. Forum, vol. 163, pp. 527-529, 2006.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 283-287

doi: 10.4028/p-ad93l3

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-15

Accepted:
2022-03-07

Online:
2022-05-31

Automatic Image Analysis of Stackingfault

The original version of this paper is available on https://www.scientific.net/MSF.1062.283.pdf

A. Muoio , C. Calabretta , V. Scuderi , M. Zimbone , F. LaVia

CNR-IMM, VIII Strada 5, 95121 Catania, Italy

CNR-IMM, via S.Sofia 64, 95123 Catania, Italy

INFN - LNS, Catania via S.Sofia , Italy

*e-mail: viviana.scuderi@imm.cnr.it, massimo.zimbone@imm.cnr.it,

Keywords: SiC, stacking fault, image segmentation

Abstract

C silicon carbide is a semiconductor with remarkable properties, making it ideal for the development of long lasting devices, working in harsh environments and under high particle flows. The most significant obstacle to its wider diffusion is the presence of extended, bidimensional and linear defects in its crystal lattice. The purpose of this research is to automatically recognize defects from a TEM image by algorithm that calculates distances and angles.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.283.pdf

Such defects can be classified as Dislocations (D) and Stacking Faults (SF) delimited by their Partial Dislocation (PD). Eliminating the defects in crystal is one of the biggest challenges that could allow the material to be used in microelectronic industries [1-5]. The transmission electron microscope (TEM) image allows to an expert researcher, to obtain visual information about the structure of the defect [6]. Nevertheless the process takes a long time for each single image, often without providing any quantitative information.

In order to analyze this kind of high resolution images, there are different approaches in literature. The segmentation techniques aims to simplify and change the representation of the image in such a way it becomes more meaningful and easier to analyze [7,8] and it is generally used to identify objects and borders (lines, curves). More precisely, image segmentation is the process of assigning a label to each pixel of an image, so that the pixels with the same label share certain characteristics [9]. Thus, the result of image segmentation is a set of segments (or points) that collectively cover the entire image, or a set of outlines extracted from the image.

The identification of the defect zone can be difficult by naked eye and only an expert researcher can highlight the presence of the defect. Thus, an algorithm, based on a segmentation technique, has been created in order to discriminate defective regions according to the properties of the individual points.

Method

The original version of this paper is available on https://www.scientific.net/MSF.1062.283.pdf

The first problem consists to identify the position of the silicon atoms of the crystal lattice, by digital images dm4, a format used by Digital Micrograph, a program used in transmission electron microscopy. This procedure required the use of a new algorithm, because there is no-dedicated function in MATLAB. The dm4 image is transformed into a matrix of elements. Subsequently, the matrix is converted into a light density matrix by the 8 -neighbour technique that attributed to the pixels of the image a new numeric value for each element of the new matrix[10]. Then, the procedure is applied several times by suppressing the neighbouring pixels with lower density. Afterward, the algorithm generates a binary matrix with null elements except those where presumably the atoms of the crystal lattice are present.

The second problem to be solved is to identify if there are areas of the matrix where the density of atoms is not uniform as in the case of a perfect crystal (PC). Submatrices are created that are
compared with each other: those that differ from each other are highlighted and indicate regions where defects are present.

Consequentially, the atoms are divided into two or more sets: those of PC and those, if present, of defect zones or SFs.

In addition, for each atom the program allows to calculate the distance with the neighboring atoms and the angle of the direction formed by the joining the two neighboring atoms and the horizontal line.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.283.pdf

Figure 1a shows the theoretical distances in a PC, while Figure 1b shows the experimentally measured distances from TEM image, automatically calculated by the algorithm. Distances to neighboring atoms were calculated for each point-atom. The algorithm is a robust method for detecting the neighboring atoms of any atom within an image, for evaluating the distances and angles formed with it. Theoretical distances and angular distributions for a PC and for first level stacking faults (SF1) were identified.

Figure 1 a) Theoretical distance( ) from every atom with his neighbors. b) Experimental distance ( ) from every atom with his neighbors

Figure 1. Figure 1 a) Theoretical distance( Å ) from every atom with his neighbors. b) Experimental distance ( Å ) from every atom with his neighbors

A typical result of the distributions of interatomic distances and angular directions of the first congruent neighbors is shown in Fig. 2a and Fig. 2b. In Fig. 2a the distances distributions for PC and SF1 are overlapped in the same image and it's possible to see the difference from Gaussians which does not fit with PC and SF1; in the same way in Fig.2b for angular distributions. These values could be used for the identification of local stress by comparing the experimental values with the theoretical.

Figure 2 a) Overlapping distance distributions for different parts of the same image between the first neighbors b) Overlapping angular distributions for different parts of the same image between the first neighbors

Figure 2. Figure 2 a) Overlapping distance distributions for different parts of the same image between the first neighbors b) Overlapping angular distributions for different parts of the same image between the first neighbors

Table 1 compares the theoretical values with the experimental values obtained automatically by the algorithm for PC. In particular, in the distances, we have only one experimental value which corresponds to the first two theoretical values. This effect is due to the insufficient measurement sensitivity of the image which corresponds to 0.2 angstroms. This value prevents the two values from being resolved from the atom distances distribution. Instead, the experimental angular distribution is congruent with all theoretical values.

Table 1

Perfect Crystal Distances
[A°]

Theoretical
Experimental

2.7
2.9±0.2

3.1

4.4
4.6±0.2

5.1
5.3±0.2

Perfect Crystal Angles[°]

Theoretical
Experimental

0
0±5.0

55
55±6.6

125
125±5.2

180
180±5.5

235
235±6.2

305
305±4.0

Table 2

Stacking faults Distances [A°]
Theoretical | Experimental
2.7 | 2.8±0.3
3.1
4.4 | 4.6±0.4
5.1 | 5.3±0.2
Stacking faults Angles[°]
Theoretical | Experimental
0 | 0±4.5
15 |
55 | 55±5.4
70 |
125 | 125±2.3
196 | 196±5.2
| 225±4.0
252 | 252±3.2
305 | 305±2.2

Table 2 compares the theoretical values with the experimental values obtained automatically by the algorithm for a SF1. Also, in this case, there is only one value for the atomic distances, with a larger error since the Gaussian distribution of the distances has a greater width at half height than in the previous case.

As regards the angular distributions, the difference in the angles measured may depend on the stress suffered by the lattice which changes the spatial position of the atoms in the defect zone. In this regard, more statistics will have to be acquired.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.283.pdf

Crystals are rarely perfect in the regularity of their lattices. Defects of structure also arise from larger scale stacking faults, where the rows of atoms get out of alignment. Image processing and classification algorithms may be categorized according to the space in which they operate. The purpose of our unsupervised algorithm is to be able to detect defects from the crystal with the segmentation technique; the process allows to divide an image into a certain number of homogeneous regions (sets of pixels). Each region is homogenous in terms of some attributes (gray level, texture, color), while adjacent regions must be different in terms of others[10]. The method of nearest neighbors, called k-nearest neighbors algorithm (k-NN), classification is carried out in a set of pre-classified examples in order to find, for each pixel, the nearest neighbors (usually the Euclidean distance is used). The algorithm is able to discriminate the points atoms, then to identify the first 8-neighbours in the PC and SF1. The analysis of the first neighbors appears to be in good agreement with the theoretical values.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.283.pdf

C. Calabretta, et al. Effect of Nitrogen and Aluminum Doping on 3C-SiC Heteroepitaxial Layers Grown on Off-Axis Si (100), Materials, 14(16), 2021, 4400.

V. Scuderi et al. Characterization of 4 H -and 6 H -like stacking faults in cross section of 3 C -SiC epitaxial layer by room-temperature -photoluminescence and -raman analysis, Materials, 13(8) 2020, 1837

F. La Via et al. New approaches and understandings in the growth of cubic silicon carbide, Materials, 14(18), 2021, 5348.

H. Nagasawa et al., 3C-SiC hetero-epitaxial growth on undulant substrate J. Cryst. Growth, 237-239 (2002) 1244-1249

R Anzalone et al. Temperature investigation on 3C-SiC homo-epitaxy on four-inch wafers, Materials 12 (20),2019, 3293

M Zimbone, et al. Extended defects in 3C-SiC: Stacking faults, threading partial dislocations, and inverted domain boundaries, Acta Materialia 213, 2021,116915

S. Ha & W. M. Vetter,A Simple Mapping Method for Elementary Screw Dislocations in Homoepitaxial SiC Layers, Material Science Forum, . 389-393 (2002) 443-446.

G. Linda. Shapiro and C. George Stockman Computer Vision, Prentice-Hall, New Jersey, ISBN 0-13-030796-3, 279-325

L. Barghout and L. W. Lee "Perceptual information processing system." Paravue Inc. U.S. Patent Application 10/618,543, filed July 11, 2003.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 288-292

doi: 10.4028/p-8m5zs1

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-09

Accepted:
2022-03-07

Online:
2022-05-31

Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

A.M. Vidarsson , J.R. Nicholls , D. Haasmann , S. Dimitrijev and E.Ö. Sveinbjörnsson

¹Science Institute, University of Iceland, 107 Reykjavik, Iceland

Queensland Micro- and Nanotechnology Centre, Griffith University, QLD 4111 Brisbane, Australia

School of Engineering and Built Environment, Griffith University, QLD 4111 Brisbane, Australia

Department of Physics, Chemistry and Biology (IFM), Linköping University, SE-58183 Linköping, Sweden

E-mail: amv10@hi.is, s.dimitrijev@griffith.edu.au, einars@hi.is

Abstract

The inversion channel electron mobility in MOSFETs with NO annealed gate oxides is still well below its theoretical limit. The physical reason behind the reduced mobility is not yet fully established but has for example been attributed to a high density of very fast interface traps close to the conduction band edge. These traps are not detected by high-low CV analysis at room temperature but are observed by conductance spectroscopy at low temperatures. In this study we demonstrate how conventional high-low CV analysis of MOS capacitors at cryogenic temperatures can be applied to detect and quantify these very fast traps.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

High power SiC MOSFETs are now commercially available. However, moderate inversion channel mobility has inhibited the development of low power devices where the channel resistance is adversely affecting the power efficiency. The limited mobility is commonly attributed to large density of carbon-related interface defects [1-3].

Compared to the interface, the interface contains a rather high density of interface traps as well as near-interface traps that are located inside the gate oxide. Currently the most successful method to neutralize these traps is to use post annealing in or pure NO at high temperatures [4-7]. This process is able to suppress the density of interface traps by an order of magnitude with energy levels located below the SiC conduction band edge as revealed by CV analysis [6]. However, the inversion channel mobility is still only about 25 which suggests that there are still some interface defects hampering the electron mobility that cannot be detected at room temperature [7].

Recent studies using conductance spectroscopy at cryogenic temperatures have observed very fast interface traps labelled NI, that are detected both in dry thermal oxides and nitrided oxides [8-10]. Subsequent studies have showed that the NI signal is due to direct tunnelling in and out of nearinterface traps located very close to the SiC conduction band edge [8]. Here we demonstrate that the NI traps are observed at cryogenic temperatures using conventional high-low CV analysis.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

In this study we use dry thermal oxide and dry oxide annealed in pure NO grown on off-axis nepitaxial with a net doping of . MOS capacitors were made with aluminium as the gate metal. The dry oxide ( 32 nm ) was grown at for 40 min . The NO annealed oxide ( 41 nm ) was made by dry oxidation at for 60 min followed by annealing in pure NO for 60 min at .

Measurements were performed in a closed loop helium cryostat that is controlled using Lakeshore 331 temperature controller. Capacitance measurements were carried out using Agilent E4980A LRC meter and Keithley 6517B electrometer at fixed temperatures between 50 K and 300 K . High frequency measurements ( ) were conducted by sweeping the samples from -10 V to 10 V DC, using 10 mV AC test signal. Quasi static measurements were performed by sweeping the samples from -10 V to 10 V with ramp measuring the charge and the capacitance is calculated.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

Figure 1 shows capacitance sweeps of both samples using quasi-static and high frequency signals at room temperature, 125 K and 75 K . Fig.1.a of the dry oxide sample at room temperature shows significant frequency dispersion, whereas the dispersion in the NO sample is much smaller (Fig.1.d). This well-known difference in the NO sample has been attributed to lower density of slow interface traps (labelled OX) with energy levels within the SiC bandgap [9]. At 125 K , a large portion of the slow traps in the dry oxide sample do not follow the high frequency signal, resulting in a stretch-out in accumulation due to electron trapping as seen in Fig.1.b [11]. As expected, this stretch-out is not observed in the NO sample due to the lack of OX traps, but frequency dispersion appears (Fig.1.e). At 75 K , a significant stretch-out in accumulation is observed in the dry oxide sample and the dispersion is enhanced (Fig.1.c) while a clear frequency dispersion is observed in the NO sample but no stretch-out in accumulation (Fig.1.f). Due to the stretch-out in the dry oxide sample the higher frequency curves asymptotically reach the accumulation capacitance at higher voltages (not shown). The dispersion starts in weak depletion at a similar surface potential as the NI signal is observed by

Fig. 1. Quasi-static and high frequency capacitance spectra of both samples at room temperature, 125 K and 75 K .

Fig. 1. Quasi-static and high frequency capacitance spectra of both samples at room temperature, 125 K and 75 K .

conductance spectroscopy [10]. At the onset of dispersion, the capacitance is at first influenced by traps that are responding near the test frequency and contribute to the capacitance. Then when the gate bias is increased further, the electron capture rate exceeds the test frequency and the traps remain filled and do not influence the CV curve. The dispersion behaviour versus voltage at 75 K is similar
in both samples. Overall, the data suggests that the dispersion at 75 K is due to the NI traps [10]. It is evident that some of the NI traps have electron emission rate that is temperature dependent. The kink that is visible in weak depletion in figures 1 (c), (e) and (f) is assigned to the onset of electron trapping in NI traps.

For comparison, CV and conductance analysis was performed on sodium-enhanced oxides (SEO) samples. MOSFETs using such oxides exhibit about three times higher inversion channel mobility than NO annealed devices [12]. Neither the OX nor NI traps were observed in both types of measurements within the detection limit (not shown). This further indicates that the CV dispersion at low temperatures is due to NI traps.

Fig. 2. Density of interface traps of both samples extracted from room temperature data (dashed lines) and at cryogenic temperatures (solid lines).

Fig. 2. Density of interface traps of both samples extracted from room temperature data (dashed lines) and at cryogenic temperatures (solid lines).

Figure 2 shows density of interface traps ( ) from high-low CV analysis of both samples. The dashed lines show the if only room temperature data is used and extended over a large energy range. The energy range extraction is based on thermal emission and using an electron capture cross section of . At low temperatures when the near-interface NI trap is the main contribution to the such approach is not physically correct . However, such simplification is justified when comparing relative differences in between different gate oxides containing the NI trap. Solid lines show the extracted using CV data at different temperatures, using a limited energy range for each temperature. The figure shows that using room temperature data results in an underestimation of close to the conduction band edge, especially for the NO sample. At cryogenic temperatures, the NO sample shows similar or higher than the dry oxide due the presence of a high density of NI traps that are too fast to be detected at room temperature. Measuring only at room temperature severely underestimates the density of traps closer to the conduction band edge. In addition, one should keep in mind that substantial surface potential fluctuations (the order of 100 mV ) are present
at the interface [13,14] which makes definitive energy level localization of the interface traps questionable. Nevertheless we can compare the extracted from the cryogenic capacitance measurements for differently prepared gate oxides. Similar trend can be seen from the conductance spectroscopy analysis where the of the NI peak increases as we probe closer to the conduction band edge [9]. The CV analysis provides the total number of Dit (the sum of NI and OX traps) while the conductance spectroscopy can separate between the NI and OX traps. The high density of NI traps in NO annealed samples suggests that they are the main cause of limited inversion channel electron mobility in SiC MOSFETs.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

Very fast near-interface traps (NI) are observed in MOS capacitors using high-low CV analysis at cryogenic temperatures in both dry oxides and NO annealed oxides. Comparison between differently prepared gate oxides suggests that electron trapping and scattering due to these traps is responsible for the rather low inversion channel electron mobility in NO annealed SiC MOSFETs.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

J. R. Nicholls, D. Haasmann, and S. Dimitrijev were supported in part by SICC material Co., Ltd., China, as the industry partner in the Australian Research Council Linkage Project under Grant ARC LP 50100525. A. M. Vidarsson and E. Ö. Sveinbjörnsson were supported by the Icelandic Centre for Research (Rannis) and the University of Iceland Research Fund. Parts of this work were performed at the Queensland node of the Australian National Fabrication Facility (ANFF), a company established under the National Collaboration Research Infrastructure Strategy to provide nanofabrication and microfabrication facilities to Australia's researchers.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.288.pdf

V. Afanasev, M. Bassler, G. Pensl and M. Schulz, Physica Status Solidi (a) 162, 321-337 (1997).

J.M. Knaup, P. Deák, Th. Frauenheim, A. Gali, Z. Hajnal and W.J. Choyke Phys. Rev. B 72, 115323 (2005)

S. Wang, M. Di Ventra, S.G. Kim and S.T. Pantelides Phys. Rev. Lett. 86, 5946 (2001)

M. Cabello, V. Soler, G. Rius, J. Montserrat, J. Rebollo, and P. Godignon, Materials Science in Semiconductor Processing 78, 22-31 (2018).

D. P. Ettisserry, N. Goldsman, A. Akturk, and A. J. Lelis, J. Appl. Phys 116, 174502 (2014).

G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, M. Di Ventra, S.T. Pantelides, L.C. Feldman and R.A. Weller, Appl. Phys. Letters 76, 1712 (2000).

G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, M. Di Ventra, S.T. Pantelides, L.C. Feldman and R.A. Weller, Appl. Phys. Letters 76, 1713 (2000).

H.Yoshioka, T. Nakamura and T. Kimoto, J. Appl. Phys. 112, 024520 (2012).

H.Yoshioka, T. Nakamura and T. Kimoto, J. Appl. Phys. 115, 014502 (2014).

J.R. Nicholls, A.M. Vidarsson, D. Haasmann, E.Ö. Sveinbjörnsson and S. Dimitrijev, IEEE Trans. on Electr. Dev. Vol. 67, (9) 3722-3728 (2020).

E.H. Nicollian and J.R. Brews, MOS Physics and Technology, 1st ed. (John Wiley & Sons Inc., 1982) p. 321-322.

F. Allerstam, H.Ö. Ólafsson, G. Gudjónsson, D. Dochev and E.Ö. Sveinbjörnsson, J. Appl. Phys. 101, 124502 (2007).

E. Bano and T. Ouisse, Appl. Phys. Letters Vol. 65, (21) 2723-2724 (1994)

T. Ouisse, Phys. Stat. Sol. (a) Vol. 162, 339-368 (1997)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 293-297

doi: 10.4028/p-5p0qg2

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

Alina Muravitskaya , Anna Rumyantseva , Atse Julien Eric Ndohi , Camille Sonneville , Dominique Planson , Pierre-Michel Adam , Sylvain Potiron and Mihai Lazar

¹Laboratory Light, Nanomaterials & Nanotechnologies, CNRS ERL 7004, University of Technology of Troyes, 12 rue Marie Curie, 10004 Troyes, France

Laboratoire de Recherche en Nanosciences, Université de Reims Champagne Ardenne, Moulin de la Housse, 51687 Reims, France

AMPERE, UMR 5005 CNRS, INSA Lyon, Villeurbanne, F-69621, France

alina.muravitskaya@gmail.com, anna.rumyantseva@utt.fr, atse-julien-eric.ndohi@insa-lyon.fr,

camille.sonneville@insa-lyon.fr, dominique.planson@insa-lyon.fr, pierre_michel.adam@utt.fr, sylvain.potiron@univ-reims.fr, *mihai.lazar@utt.fr (corresponding author)

Keywords: SERS, GaN, SiC, plasmonic nanoparticles, power device, Raman scattering, nanostructures, thin layers

Abstract

In order to selectively analyze active thin layers close to surface in power devices structures, Raman scattering is necessary with UV excitation. However, the Raman spectra of GaN are usually affected by the direct bandgap photoluminescence of the material, which interferes with the Raman measurements and decreases the quality and resolution of the Raman spectra. In this work, we demonstrate experimentally that nanostructured aluminum films deposed on GaN epitaxial layers decrease the influence of the photoluminescence on the resonant Raman spectra and increase its overall spatial resolution under UV illumination.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

The resonant Raman scattering is a well-established non destructive method for analyzing the surface properties of the GaN determining the crystalline quality, stress, doping, free carrier concentration for process and growth monitoring [1,2]. In GaN power devices one needs to selectively analyze thin layers in the surface (active layers as emitters, channels, junction termination extensions created by ion implantation, metal-contact interfaces) with thickness that does not exceed micrometer at most and can go to and even less [3]. To gain the correct values, the influence of underlayers present in the vertical device (hetero)structure (substrate, buffer, drift layers, etc.) should be eliminated. Thus, for GaN thin layer analyses, UV excitation is preferred to the classical visible or IR excitation wavelengths, since it allows to examine a surface layer of about 40 nm thick (under 325 nm excitation) [4]. However, as GaN has a direct bandgap, strong photoluminescence (PL) contribution can interfere with the measurements and decrease the quality and resolution of the obtained Raman spectra under UV excitation.

One of the approaches to decrease the PL background and increase the Raman signal is to place plasmonic nanoparticles on the top of a layer of interest, which results in a quenching of the PL due to the high non-radiative transfer of the excitation energy to metal, and in the same time, Raman scattering benefits from the local field enhancement and increase in radiative decay rates near resonant plasmonic nanoparticles. In this work, we propose to use structured Al films to diminish the influence of the PL on the resonant Raman spectra of GaN and to increase its overall resolution.

Methods

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

GaN thin epilayers (between 500 nm and thick MOCVD) on sapphire substrates from CNRSCRHEA with a silicon doping concentration in the range of to were covered with Al nanoparticles and Al thin films, which were deposited by means of the vacuum evaporation technique (e-beam PlassysMU400). The samples are presented in Figure 1. The Al nanoparticles film was obtained for a thickness of the deposition of 6 nm . The Al thin film was obtained after 20 nm deposition. In both cases samples were heated up to during the deposition. The Al nanoparticles film was formed during a dedicated e-beam evaporation step only on one of the GaN epilayers presented in Figure 1.

Fig. 1. Optical photos of the GaN epilayers partially covered with Al nanoparticles and films (a and b) and a scanning-electron microscopy image of the area covered with Al nanoparticles (c)

Fig. 1. Optical photos of the GaN epilayers partially covered with Al nanoparticles and films (a and b) and a scanning-electron microscopy image of the area covered with Al nanoparticles (c)

From the area covered with the Al nanoparticle a FEG-SEM (Field emission Scanning Electron Microscope) image is also presented in the right side of Figure 1. On these parts of the samples, photoluminescence (PL) and Raman measurements were done under UV ( ) illumination and in back-scattering geometry with LabRAM spectrometer of Horiba Scientific (scheme in Fig. 2). Three Raman modes are allowed in GaN layers in the backscattering configuration [5]: and

In order to compare and analyze PL and Raman signals similar commercial samples (substrate with n-type epilayers of thickness and doping) have been prepared with the same experimental Al deposition setup.

Fig. 2. PL and Raman signals obtained from different GaN epilayers surfaces covered or not with Al nanoparticles and films, schematically highlighting the SERS effect. The length of the arrows corresponds to the relative intensity.

Fig. 2. PL and Raman signals obtained from different GaN epilayers surfaces covered or not with Al nanoparticles and films, schematically highlighting the SERS effect. The length of the arrows corresponds to the relative intensity.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

As shown in figure 3a, the deposition of the Al on top of the GaN resulted in a drastic fall of the photoluminescence intensity. In the case of the Al nanoparticles film the PL has decreased 10 times, while for the Al thin film it has decreased 100 times.

Then we observed in figure 3b the revealing of the three Raman modes in the spectra: and . A schematic presentation of this SERS (surfaceenhanced Raman spectroscopy) effect is highlighted in Figure 2 and measurements are presented in Figure 3.

Important to note that we do not observe the contribution of the sapphire (GaN epilayer substrate in our samples) modes, which often change the shape of the spectrum of GaN. Indeed the light penetration depth in GaN is less than the epilayer thickness.

Fig. 3. Photoluminescence (a) and Raman scattering spectra (b) ( ) of the GaN epilayers covered with layer of Al nanoparticles and covered with thin Al film layer.

Fig. 3. Photoluminescence (a) and Raman scattering spectra (b) ( ) of the GaN epilayers covered with layer of Al nanoparticles and covered with thin Al film layer.

Compared to visible non resonant Raman spectra (e.g at 532 nm ) in which the peak is the more intense [1], in our UV Raman spectra enhanced by Al , the peak dominates the resonant Raman spectra. This effect is more visible with the Al film than with Al nanoparticles. More over peak is more intense compared to the PL background in the case of the Al thin film, than for the Al nanoparticles film. However, for the layers with Al nanoparticles film, the lines width is sharper and the peak is more pronounced. Al nanoparticles film seems more appropriate to be used in the fine UV Raman analysis of GaN epilayer characteristics as mechanical stress and defects, by considering the resolution obtained for the peak. For doping, peak could be considered using Al films.

Fig. 4. Photoluminescence (a) and Raman scattering spectra (b) ( ) of the SiC epilayers covered with thin Al film.

Fig. 4. Photoluminescence (a) and Raman scattering spectra (b) ( ) of the SiC epilayers covered with thin Al film.

For both films the absorption of the GaN emission by Al layers and consequent fall of the PL play an important role in the Raman lines appearing. Also, the plasmonic enhancement of the Raman scattering may occur, especially as Al sustains localized surface plasmon resonances in the UV region [5, 7].
epilayers and substrates have been also tested without and with Al layer deposited during the same run with the GaN samples. Even though the PL signal was reduced 10 times (Figure 4a) the enhancement of the Raman scattering was not observed (Figure 4b). We note that SiC compared to GaN has an indirect bandgap, and then the PL signal is not so high. Therefore, doping check or other stress and defects identification could be done by direct UV Raman measurements without Al nanoparticles or nanolayers on the surface.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

As for SiC layers Raman can be utilized on GaN layers as a versatile and nondestructive tool to investigate critical layers as those close to two-dimensional electron gas in heterostructures. We show that Al thin layers deposited on top of the GaN epitaxial layers may improve the quality and intensity of the resonant Raman scattering of the GaN functional layers and therefore provide a way to probe doping, defects and various kinds of stress in thin layers (less than of actual structures of power devices. In this case, a thin Al layer is needed to increase Raman scattering signal and decrease the photoluminescence. This metallic layer can be kept or removed after test.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

The authors acknowledge our colleagues from CRHEA-CNRS for the GaN/sapphire samples. This work has been made within the framework of the Graduate School NANO-PHOT (École Universitaire de Recherche, contract ANR-18-EURE-0013). The authors acknowledge the project RETOR.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.293.pdf

Hiroshi Harima 2002 J. Phys.: Condens. Matter 14 R967

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Richard Denny, Abirami. M, Kanimozhi G, Ronit Hara Yandra, Journal of Critical Reviews, Vol 7, Issue 12, 2020, 456-467

J.F. Muth, J.H. Lee, I.K. Shmagin, R.M. Kolbas, H. C. Casey Jr., B. P. Keller, U. K. Mishra, S.P. DenBaars, Appl. Phys. Lett. 71, 18 (1997) 2572.

Z. C. Feng, W. Wang, S. J. Chua, P. X. Zhang, K. P.J. Williams, G. D. Pitt, JRS. 32, 10 (2001) 840-846.

M. W. Knight, N. S. King, L. Liu, H. O. Everitt, P. Nordlander, N. J. Halas, ACS Nano. 8 (2013) 834-840.

A. Muravitskaya, A. Gokarna, A. Movsesyan, S. Kostcheev, A. Rumyantseva, C. Couteau, G. Lerondel, A.-L. Baudrion, S. Gaponenko, and P.-M. Adam. Nanoscale. 12, 11 (2020) 63946402.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 298-303

doi: 10.4028/p-n0z51t

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-03-16

Accepted:
2022-03-17

Online:
2022-05-31

Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

Yu Ogata , Kohei Yamasue , Xufang Zhang , Tsubasa Matsumoto , Norio Tokuda and Yasuo Cho

Tohoku University, 2-1-1 Katahira, Aoba, Sendai, Miyagi 980-8577, Japan

Kanazawa University, Kakumamachi, Kanazawa, Ishikawa 920-1192, Japan

ogty1998@riec.tohoku.ac.jp, yamasue@riec.tohoku.ac.jp, zhang-xufang@se.kanazawa-u.ac.jp, t-matsumoto@se.kanazawa-u.ac.jp, yasuocho@riec.tohoku.ac.jp

Keywords: diamond semiconductor, scanning nonlinear dielectric microscopy

Abstract

Improvement of channel mobility is required to improve the performance of the inversion channel MOSFETs using diamond. The previous studies have suggested that high interface defect density ( ) at the diamond (111) interface has a significant impact on the carrier transport property on a channel region. To investigate the physical origins of the high , especially from microscopic point of view, here we investigate p-type diamond (111) interfaces using scanning nonlinear dielectric microscopy (SNDM). We find the high spatial fluctuations of hydroxyl -terminated diamond (111) interface properties and their difference by the flatness of the diamond surface.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

Because diamond possesses a high breakdown electric field, high thermal conductivity, and high carrier mobility, it has a potential to realize the power devices with high breakdown voltage, high power, and high-speed operation [1-3]. Recently, inversion type p-channel MOSFETs with normally off characteristics have been fabricated using a P -doped and OH -terminated diamond body on a diamond (111) substrate with an atomic layer deposited ( ALD ) dielectric [4]. In addition to the ALD dielectric, OH-termination of the diamond surface is a key for fabricating normally-off and inversion type MOSFETs suitable for power device applications and has been applicable to a (111) surface rather than (100) surface often used for diamond devices [5, 6]. However, the device performance of these MOSFETs is still unsatisfactory. In particular, the improvement of the channel mobility is one of the major issues towards the practical application of the diamond based power devices [4, 5]. In this regard, the previous studies have suggested that high interface defect density ( ) at the diamond (111) interface significantly reduced the channel mobility in the MOSFETs [7]. In order to give microscopic insights on the physical origin of the high , here we investigate the -type diamond (111) interfaces using scanning nonlinear dielectric microscopy (SNDM) [8]. In this paper, we investigate the -type diamond (111) interfaces by differential capacitance ( ) imaging by the conventional SNDM, local capacitance-voltage (CV) profiling, and local deep level transient spectroscopy (DLTS) based on a

Fig. 1 Schematic diagram of SNDM

Fig. 1. Schematic diagram of SNDM

recently developed time-resolved SNDM setup [9].

Methods

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

d imaging by conventional SNDM. Figure 1 shows a schematic diagram of the conventional SNDM [8]. By applying a small sinusoidal voltage to the sample and using a lock-in amplifier, we can obtain the voltage derivative of the capacitance, or . The images reflect the spatial fluctuations of the semiconductor properties such as the polarity of majority carriers, their density distribution, , and density of the fixed charge in the insulating layer, due to their impacts on the local CV profile. Therefore, these semiconductor properties can be evaluated at the nanoscale by imaging. In the time-resolved SNDM, the output signal of the SNDM probe is digitized directly and then the shift of the oscillation frequency is numerically demodulated by offline signal processing [9]. Compared to the conventional SNDM, much wider measurement bandwidth becomes possible and offline digital processing techniques permits the demodulation of capacitance variation without significant signal distortion.
Local CV profiling and DLTS. Local CV profiles can be obtained corresponding to the linear voltage changes of the triangular pulse when we apply a large amplitude triangular voltage pulse to the sample [10]. From the data, we can also extract images by mapping the slopes of the profiles at a particular voltage. Local CV profiling can give insights on microscopic real-space fluctuations of interfacial properties. Note that our method basically reflects local CV profiles at deeply depleted high-frequency rather than low-frequency counterparts. This is because our local CV profiling uses a voltage sweep rate typically as high as several tens of kilohertz, which is much higher than standard macroscopic quasi-static CV profiling and does not allow the generation of an inversion layer.
Macroscopic DLTS is a method of analyzing defects in semiconductors proposed by Lang in 1974 and can evaluate as well [11]. Time-resolved SNDM can be used to perform a microscopic DLTS called local DLTS. In the local DLTS, a rectangular voltage pulse is applied to the sample as in the macroscopic DLTS. We demodulate local transient capacitance response on each measurement point and, by analyzing it, we obtain the microscopic distribution of It has been reported that the spatial resolution of local DLTS is about the tip diameter under typical measurement conditions [12].

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

Samples. The samples for the SNDM measurements were prepared using process and techniques described in Refs. [5, 6, 13, 15-17]. The individual samples had a insulating layer ( 50 nm ) formed by atomic layer deposition (ALD) [5], a high-pressure high-temperature (HTHP) synthesized p-type diamond (111) substrate ( ) with a boron concentration of , a high B concentration p+ diamond CVD layer ( 200 nm ) for ohmic contact formation, and a vacuum deposited gold electrode layer with a thickness of 200 nm [13]. In this study, we measured three different samples, with different termination process by H , O , and OH -groups [6]. They are here denoted by H -, O -, OH -diamond (111), respectively. The diamond (111) surface with atomically flat regions was formed by anisotropic diamond etching process based on a carbon solid solution reaction into Ni [15]. Conventional plasma processes for diamond etching were not used here because of low selectivity and plasma-induced damage [15]. In addition, hydrogen plasma etching was performed to form an atomic step-terrace regions on the p-type diamond surface [16] prior to the ALD process [5]. As reported in Ref. [13], the samples without had atomically-well defined diamond (111) surface with step-terrace and bunching-step regions. SNDM measurements were performed in air at room temperature. We used a Pt-Ir coated conductive cantilever with a tip radius of (Nanotools, C2520094). The reason for choosing such a large radius tip was to increase the signal-to-noise ratio in SNDM measurements. The voltage was applied to the sample relative to the grounded tip. SNDM was combined with a commercial scanning probe microscopy setup (Bruker, Icon) operated in contact-mode atomic force microscopy.
Results of local CV profiling. We begin with the results of local CV profiling based on time-resolved SNDM. The measurement was performed by applying a triangular voltage pulse including backward and forward sweep directions. Each sweep direction had s length. The amplitude of the pulse was
for -diamond (111) and for - and OH-diamond (111). These amplitudes were chosen so that the features of the local CV profiles were obtained for each sample, taking care to avoid dielectric breakdown. The triangular voltage pulse was applied for 1000 times and resultant 1000 capacitance responses were averaged at each measurement position of lattice points within a scanned area. Figure 2 shows typical local CV profiles each selected from 2500 H -[Fig. 2(a)], O-[Fig. 2(b)], and OH-diamond (111) [Fig. 2(c)] data. The blue and red profiles in Fig. 2 show the characteristics obtained from the increasing and decreasing parts of the triangular voltage pulse, respectively. In all samples, we confirmed that local CV profiles had positive slopes resulting from p-type majority carriers. In addition, the H-diamond (111) sample showed accumulation even around 0 V , while the interfaces of the O - and OH -diamond (111) samples were depleted around 0 V . This is due to negative electron affinity of the H -diamond surface causing the high hole concentration [14].

These profiles showed different slopes in the transition from depletion to accumulation. From Fig. 2, the maximum slopes of the local CV profiles for H-, O-, and OH-diamond (111) samples were estimated to be at at 11 V , and at 21 V , respectively, by numerical differentiation. Since the transition occurs more rapidly and capacitance change becomes higher as decreases, is the lowest at the -diamond (111), followed by -, and O -diamond (111) interfaces. Figure 3 shows two-dimensional maps of at the above mentioned voltages for H-[Fig. 3(a)],O-[Fig. 3(b)], and OH-diamond (111) [Fig. 3(c)]. For all samples, the d images have non-uniform distributions.

Fig. 2 Local CV profiles of the /diamond (111) samples with different interface termination processes

Fig. 2. Local CV profiles of the /diamond (111) samples with different interface termination processes

Fig. images reconstructed from local CV profiles

Figure 3. Fig. images reconstructed from local CV profiles

Fig. 4 Topographic and images of the -diamond(111) sample with different flatness. The images on the right have the same color-scale.

Fig. 4. Topographic and images of the -diamond(111) sample with different flatness. The images on the right have the same color-scale.

According to our recent work [17], on the H-diamond (111) sample, because the number of the dangling bonds generating on the diamond (111) surface is equivalent to the valence of hydrogen atoms, it is considered that the dangling bonds can be drastically reduced by hydrogen termination. On the other hand, on the O-terminated sample, is high because double bonds can also be formed between oxygen and carbon atoms, generating new dangling bonds. For the OH -diamond sample, we can expect that is lower than that in the O-diamond sample because of matching between the valence of the OH group and a surface carbon atom. However, it is pointed out that there is a possibility that the effectiveness of the OH -termination process largely depends on the topography of a diamond surface and could leave and generate high at the diamond interface [13]. Since the -diamond (111) interface is important to bring out the performance of inversion type diamond MOSFETs [5, 7, 13], we here focus on the OH-diamond (111) sample. We performed imaging by the conventional SNDM and imaging by local DLTS on the different areas of the OHdiamond (111) sample with different flatness.
imaging. Figure 4 shows topography and images of the -diamond (111) sample. For imaging, we applied a sinusoidal voltage with a frequency of 30 kHz and an amplitude of 3.0 Vp , together with a DC voltage of 5 V . The frequency chosen here was typically used for SNDM imaging. The amplitude and DC voltage were adjusted to obtain sufficiently high signal strength of the signal. We obtained images and topography at the same time with a resolution of pixels. Figures 4(a) and 4(b) show topography and images on an area with atomic flatness and adjacent rough area, respectively. Only the topographic images were here flatten as normally done in AFM imaging. It has been confirmed that, before depositing , the former area had large (111) terraces with atomic steps on the diamond surface, while the adjacent latter area exhibited higher roughness because of insufficient planarization on the same sample, as reported in Ref. [13]. From the topographic images in Fig. 4, the roughness values after deposition were about 1 nm for the flat area and 10 nm for the rough area in root-mean-square. In Fig. 4, both images had spatial fluctuations where dark spots possibly were non-uniformly distributed. In more detail, on the atomically flat area in Fig. 4(a), the dark spots are densely and evenly seen in the image over the measurement area. In contrast, on the area with higher roughness in Fig. 4(b), the dark spots in the image are concentrated on a portion of the scanned

Fig. 5 Local DLTS images of -diamond(111) sample with different flatness

Fig. 5. Local DLTS images of -diamond(111) sample with different flatness

area. These dark spots possibly indicate high regions with lower , and the difference in their spatial distributions suggests that images visualize the difference of the spatial distribution in different surface flatness.
imaging by local DLTS. In order to directly image spatial distribution especially on the -diamond (111) sample, local DLTS based on time-resolved SNDM was further performed. As an accumulation pulse, -long rectangular voltage pulse stepping down to a target level of +5 V from a reference level of -5 V was applied 1000 times and the resulting 1000 repetitive capacitance transients was averaged at each measurement position of lattice points. The scanned area was reduced to for obtaining higher spatial resolution. The target and reference levels were here determined based on the local CV profiles in Fig. 2(c) to make the interface transit from depletion to accumulation. The measurement time was about 15 min . for each image. Figure 5 shows images of the area with atomic flatness [Fig. 5(a)] and higher roughness [Fig.5(b)]. The average of were both as high as order. Non-uniform distribution of was observed in both images. In particular, the line-shaped features of distribution could be observed in the atomically flat area. They might be related to the variation of at the atomic steps in the buried interface. In fact, studies using conductive atomic force microscopy and Kelvin probe force microscopy have shown that may differ depending on the interface step structure [13]. On the other hand, in the rough area, similar line-shaped structures could not be found in the measurement area but clustering high regions were observed. From these results, the flattening process of the diamond surface may affect the distribution of .

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

In this paper, SNDM based imaging, local CV profiling, and local DLTS were carried out for the diamond (111) samples with different interface termination process. From the obtained local CV profiling, we estimated that was the lowest in -diamond (111), followed by -, and -diamond (111) samples. For the -diamond (111) sample, the results of imaging and local DLTS suggested that the flattening process of the diamond surface strongly affects the distribution and size of the interface defects.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

This work was supported in part of by Grants-in-Aid for Scientific Research (S) (Grant No. 16H06360) from the Japan Society for the Promotion of Science, NEDO Uncharted Territory Challenge 2050 Grant Number 19101600-0, and Kanazawa University SAKIGAKE Project 2020.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.298.pdf

S. Shikata and H. Umezawa, Development of Diamond-Based Power Devices, Synthesiology English Edition 6 (2013) 147-157.

C.J.H. Wort and R.S. Balmer, Diamond as an Electronic Material, Mater. Today 11 (2008) 22-28.

J. Isberg, J. Hammersberg, E. Johansson, T. Wikström, D.J. Twitchen, A.J. Whitehead, S.E. Coe, and G.A. Scarsbrook, High Carrier Mobility in Single-Crystal Plasma-Deposited Diamond, Science 297 (2002) 1670-1672.

T. Matsumoto, H. Kato, K. Oyama, T. Makino, M. Ogura, D. Takeuchi, T. Inokuma, N. Tokuda, and S. Yamasaki, Inversion Channel Diamond Metal-Oxide-Semiconductor Field-Effect Transistor with Normally off Characteristics, Sci. Rep. 6 (2016) 31585.

X. Zhang, T. Matsumoto, S. Yamasaki, C.E. Nebel, T. Inokuma, and N. Tokuda, Inversion-Type p-Channel Diamond MOSFET Issues, J. Mater. Res. 36 (2021) 4688-4702.

R. Yoshida, D. Miyata, T. Makino, S. Yamasaki, T. Matsumoto, T. Inokuma, and N. Tokuda, Formation of Atomically Flat Hydroxyl-Terminated Diamond (111) Surfaces via Water Vapor Annealing, Appl. Surf. Sci. 458 (2018) 222-225.

T. Matsumoto, H. Kato, T. Makino, M. Ogura, D. Takeuchi, S. Yamasaki, T. Inokuma, and N. Tokuda, Inversion Channel Mobility and Interface State Density of Diamond MOSFET Using NType Body with Various Phosphorus Concentrations, Appl. Phys. Lett. 114 (2019) 242101.

Y. Cho, Scanning Nonlinear Dielectric Microscopy: Investigation of Ferroelectric, Dielectric, and Semi-conductor Materials and Devices, Elsevier, ISBN9780128172469, 2020.

Y. Yamagishi and Y. Cho, Nanosecond microscopy of capacitance at interfaces by time-resolved scanning nonlinear dielectric microscopy, Appl. Phys. Lett. 111 (2017) 163103.

K. Suzuki, K. Yamasue, and Y. Cho, A Study on Evaluation of Interface Defect Density on High- and Gate Stacks using Scanning Nonlinear Dielectric Microscopy, in 2019 IEEE International Integrated Reliability Workshop (IIRW), 2019.

D.V. Lang, Deep-level Transient Spectroscopy: A New Method to Characterize Traps in Semiconductors, J. Appl. Phys. 45 (1974) 3023-3032.

Y. Yamagishi and Y. Cho, High Resolution Observation of Defects at Interfaces Using Time-Resolved Scanning Nonlinear Dielectric Microscopy, Microelectron. Reliab. 88-90 (2018) 242-245.

M. Nagai, R. Yoshida, T. Yamada, T. Tabakoya, C.E. Nebel, S. Yamasaki, T. Makino, T. Matsumoto, T. Inokuma, and N. Tokuda, Conductive-Probe Atomic Force Microscopy and KelvinProbe Force Microscopy Characterization of OH-Terminated Diamond (111) Surfaces with StepTerrace Structures, Jpn. J. Appl. Phys. 58 (2019) SIIB08.

D. Takeuchi, S. Koizumi, T. Makino, H. Kato, M. Ogura, H. Ohashi, H. Okushi, and S. Yamasaki, Negative Electron Affinity of Diamond and Its Application to High Voltage Vacuum Power Switches, Phys. Status Solidi (a) 210 (2013) 1961-1975.

M. Nagai, K. Nakanishi, H. Takahashi, H. Kato, T. Makino, S. Yamasaki, T. Matsumoto, T. Inokuma, and N. Tokuda, Anisotropic Diamond Etching through Thermochemical Reaction between Ni and Diamond in High-Temperature Water Vapour, Sci. Rep. 8 (2018) 6687.

H. Kuroshima, T. Makino, S. Yamasaki, T. Matsumoto, T. Inokuma, and N. Tokuda, Mechanism of Anisotropic Etching on Diamond (111) Surfaces by a Hydrogen Plasma Treatment, Appl. Surf. Sci. 422 (2017) 452-455.

T. Matsumoto, X. Zhang, and N. Tokuda, Recent Progress and Issues of Diamond Metal-oxidesemiconductor (MOS) Interface for High-Frequency and Power Device Application, Vac. Surf. Sci. 64 (2021) 80-85 (In Japanese).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 304-308

doi: 10.4028/p-37781z

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-22

Accepted:
2022-03-07

Online:
2022-05-31

Measurement of Dislocation Density in SiC Wafers Using Production XRT

The original version of this paper is available on https://www.scientific.net/MSF.1062.304.pdf

Andrey Soukhojak , Tyler Stannard , lan Manning , Charles Lee , Gil Chung , Matthew Gave and Edward Sanchez

SK Siltron css, 530011 Mile Road, Auburn, MI 48611 U.S.A.

andrey.soukhojak@sksiltron.com, tyler.stannard@sksiltron.com, ian.manning@sksiltron.com, charles.lee@sksiltron.com, gil.chung@sksiltron.com, matthew.gave@sksiltron.com, edward.sanchez@sksiltron.com

Keywords: physical vapor transport, PVT, bulk crystal growth, 4H, defects, non-destructive dislocation density measurement, x-ray topography, XRT, image analysis

Abstract

X-ray topography (XRT) presents itself as an attractive non-destructive method to replace industry-standard destructive KOH etching used to measure dislocation density. However, a production-line-compatible XRT has to employ a low scan speed in order to work well with automated image analysis, which makes it impractical for a high-volume manufacturing to scan an entire wafer. We introduce the "radial band" approach to sampling the entire wafer's area with a single-pass 16 mm tall scan band. Such a band spans the entire range of radii and thus captures the typically strong radial dependence of dislocation density over the entire range, while mostly ignoring the typically weak angular dependence of dislocation density and averaging the inevitable noise over the 16 mm band height. The XRT scan time savings for this approach are roughly 15-fold and 20fold for 150 mm and 200 mm wafers respectively.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.304.pdf

Single crystal wafers of 4 H SiC are the top choice for power electronic device substrates due to their excellent thermal and electrical properties. One of the most consequential defects limiting device performance and longevity are dislocations. In particular, threading edge dislocations (TEDs) and threading screw dislocations (TSDs) can both reduce minority carrier diffusion lengths over a range of dopant concentrations [1]. TSDs have been found to reduce breakdown voltage in diodes [2]. TEDs can also convert to basal plane dislocations (BPDs) [3] or enhance their formation [4], which can lead to bipolar degradation via the formation of stacking faults [5].

The KOH etch pit counting method [6] has been traditionally used in the industry as a destructive and hazardous technique to measure TED, TSD, and BPD densities. X-ray topography (XRT) has been long known as an imaging method that can reveal dislocations nondestructively due to its exceptionally high sensitivity to strain in a crystal. Recently, a production-line-compatible XRT instrument has become commercially available [7]. The purpose of this study is to explore the promise of a production-line-compatible XRT as a non-destructive, low-hazard (with proper X-ray containment) alternative to KOH etch pit method of measuring dislocation densities in production.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.304.pdf

Single crystal 4 H n-type SiC boules were grown by a seeded physical vapor transport method. The crystals were then fabricated into 150 mm and 200 mm wafers via grinding, slicing, and polishing. The wafers were scanned in a Rigaku XRTmicron instrument without a monochromator using radiation in reflection mode, using and diffraction vectors. The former reflection reveals both threading and basal plane dislocations. The molybdenum target available in
this tool, which enables transmission mode XRT, was not used, since high-BPD-density regions would produce highly overlapping images of BPDs located throughout the thickness of the wafer and thus degrade the accuracy of image analysis.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.304.pdf

Due to a relatively low flux of X-rays available in a production-line-compatible instrument, in order to achieve needed image quality (e.g. Fig. 1 (a)) to resolve dislocations in XRT images compared to a synchrotron source which has orders of magnitude stronger intensity, the scan speed must be on the order of a few . With 1.6 cm being the height of a single-pass scanned image (band), which is determined by the XRT detector size, imaging an entire wafer requires scanning and then stitching multiple horizontal band images. This takes many hours, which is too long for highvolume manufacturing.

Figure 1. (a) XRT image and overlaid automated image analysis results: (b) found TED/TSD spots labeled with ○ markers, (c) found BPD curvilinear features.

Figure 1. Figure 1. (a) XRT image and overlaid automated image analysis results: (b) found TED/TSD spots labeled with ○ markers, (c) found BPD curvilinear features.

Fortunately, our extensive KOH analysis results (Fig. 2) and data from several whole-wafer XRT scans show that in polar coordinates the radial dependence of dislocation density is much stronger than the angular one, i.e. the distribution of dislocation density over a wafer is wellapproximated by a surface that is a body of revolution. This high degree of rotational symmetry means that XRT scanning a single radial band is an effective and efficient sampling strategy, as is illustrated in Fig. 3. In order to cover the whole range of radii we only need to scan of a 150 mm wafer's area. For 200 mm wafers, the 1.6 cm tall radial band, e.g. Fig. 4, is even more time-efficient, since it occupies a further reduced fraction of the wafer's area: , which is only of .

Figure 2a. Contour maps in logarithmic scale of KOH etch pit density [ ] data for 70 randomly selected wafers (one per boule) illustrating strong radial dependence and weak angular dependence of spatial distribution of dislocation densities in polar coordinates for all three dislocation types of interest (from left: BPD, TED, and TSD).

Figure 2. Figure 2a. Contour maps in logarithmic scale of KOH etch pit density [ ] data for 70 randomly selected wafers (one per boule) illustrating strong radial dependence and weak angular dependence of spatial distribution of dislocation densities in polar coordinates for all three dislocation types of interest (from left: BPD, TED, and TSD).

Figure 2b. Contour maps of KOH etch pit density [ ] obtained by averaging maps for 70 wafers shown in Fig. 2a. From left: BPD, TED, and TSD. Distance units: mm .

Figure 3. Figure 2b. Contour maps of KOH etch pit density [ ] obtained by averaging maps for 70 wafers shown in Fig. 2a. From left: BPD, TED, and TSD. Distance units: mm .

Since threading dislocations appear as spots (TSD typically have higher intensity due to a larger associated lattice strain than TEDs), whereas BPDs appear as curvilinear features (often overlapping or forming junctions), we developed separate algorithms for automated measurement of (1) TSD & TED areal spot density [ ] and (2) total BPD length per unit image area [ ]. The latter value is divided by the effective imaging depth to arrive at BPD density [ ] shown in Fig. 3. The effective imaging depth depends on the X-ray energy, diffraction vector, and the sensitivity of the BPD detection algorithm. It can be empirically found by correlation with the results of other dislocation density measurement techniques and should roughly match the X-ray penetration depth.

Fig. 3(b) can be used to estimate percentage, i.e. probability, of passing devices as a function of radius, i.e. the distance from the wafer center. For example, if a specification limit is represented by one of the horizontal gridlines, say , the probability of a passing device starts off at nearly zero at low radius values (where all red markers are above the limit), then increases dramatically toward the middle of the radial band (where most of the red markers are below the limit), and then drops off to nearly zero at the periphery.

Figure 3. XRT automated image analysis results for BPD density in a randomly selected wafer: (a) whole-wafer heat map ( tiles) with overlaid 16 mm tall single radial band scan area ; (b) radial profiles for the whole-wafer scan (blue) and for the radial band scan area only (red). Note how well the red curve approximates the blue one, while it costs at least an order of magnitude less in terms of the scan time. , and R (distance from wafer center) axes have units of cm .

Figure 4. Figure 3. XRT automated image analysis results for BPD density in a randomly selected wafer: (a) whole-wafer heat map ( tiles) with overlaid 16 mm tall single radial band scan area ; (b) radial profiles for the whole-wafer scan (blue) and for the radial band scan area only (red). Note how well the red curve approximates the blue one, while it costs at least an order of magnitude less in terms of the scan time. , and R (distance from wafer center) axes have units of cm .

The endeavour of replacement of a relatively simple counting and classifying method for pits on a KOH wafer's surface with an image analysis of a grayscale XRT image, which has a vanishing contrast of features located below the top surface of a wafer as the depth of the features increases, is not without its challenges. First, the total detected BPD length in XRT image poorly correlates with KOH etch pit results. This is most likely due to an orientation-dependent proportionality coefficient between BPD length within the imaged depth and areal density of intersections of BPDs with any plane parallel to wafer's surface, i.e. BPD etch pit density. We are currently exploring an orientationsensitive approach to conversion of XRT-measured BPD length to predicted BPD etch pit density. Second, separation of TSD and TED is a challenge for a reflection XRT image due to significant overlap of the distributions of intensities and geometric atributes of TSD and TED spots there. Theoretically, in a reflection image (e.g. bottom XRT image in Fig. 4) only TSDs should produce a contrast, but surface relaxation around TED terminations may still produce dark spots there and thus complicate the analysis. Adding a scan may be needed to isolate TSDs and thus calculate TED density as the difference between spot densities of and reflection images. This is one of the directions of our ongoing work.

Figure 4. -tall XRT radial band scans of the same area of a 200 mm wafer using two shown reflections. The wafer's center is at the center of the left edge of each image. The top image includes the wafer's edge. Orientation of the [ ] direction: .

Figure 5. Figure 4. -tall XRT radial band scans of the same area of a 200 mm wafer using two shown reflections. The wafer's center is at the center of the left edge of each image. The top image includes the wafer's edge. Orientation of the [ ] direction: .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.304.pdf

XRT radial band scans are an effective and efficient sampling strategy compatible with high-volume manufacturing, allowing inaccuracy at and shorter scan time for 150 mm and 200 mm wafers respectively. BPD (curvilinear features) and TD (spots) detection calls for different image analysis algorithms. We are working on a better prediction of BPD etch pit density using an orientation-sensitive data analysis approach and exploring the potential benefits of adding scan to isolate TSDs and thus measure densities of all three dislocation types of interest.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.304.pdf

S. Maximenko et al., J. Appl. Phys. 108 (2010) 013708.

P.G. Neudeck et al., Solid-State Electron. 12 (1998) 2157-2164.

N. Ohtani, et al., J. Cryst. Growth 286 (2006) 55-60.

H. Wang, et al., Appl. Phys. Lett. 100 (2012) 172105.

H. Lendenmann, et al., Mater. Sci. Forum 389-393 (2002) 1259-1264.

M. Katsuno, et al., Jpn. J. Appl. Phys., 38.8R (1999): 4661.

High-Throughput, High-Resolution X-Ray Topography Imaging System: XRTmicron, Rigaku Journal (ISSN 2187-9974) - Winter 2014, Volume 30, No. 1, 30-32.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 309-314

doi: 10.4028/p-ka28ji

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-16

Revised:
2022-02-08

Accepted:
2022-03-07

Online:
2022-05-31

Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

The original version of this paper is available on https://www.scientific.net/MSF.1062.309.pdf

Tommaso Fazio , Giuseppe Fisicaro , Ioannis Deretzis , Elisabetta Paladino and Antonino La Magna

¹Consiglio Nazionale delle Ricerche, Istituto per la Microelettronica e Microsistemi (CNR-IMM), Z.I. VIII Strada 5, I-95121 Catania, Italy

Dipartimento di Fisica e Astronomia "Ettore Majorana", Università di Catania, Via S. Sofia 64, I95129 Catania, Italy

tommaso.fazio@dfa.unict.it, giuseppe.fisicaro@imm.cnr.it, ioannis.deretzis@imm.cnr.it, elisabetta.paladino@dfa.unict.it, antonino.lamagna@imm.cnr.it,

Keywords: Electron-nuclear spin bath, Cluster Correlation Expansion theory, Ab-initio methods, Density Functional Theory, Decoherence, Electron Spin Echo Envelope Modulation.

Abstract

We theoretically study point defects in 3C-SiC for applications in Quantum Technologies, focusing on the neutral silicon vacancy, with an electron spin of 1 , magnetically interacting with the SiC nuclear spin bath containing and C -13 nuclei. Initially, the system's energetics are explored with ab-initio methods based on the Density Functional Theory. Thereon, we apply a Hahn-echo sequence on the electron spin and study the effects of the bath dynamics on the electron spin's coherence. The Electron Spin Echo Envelope Modulation (ESEEM) phenomenon, due to single nuclear spin flipping processes, and the overall decay, or decoherence, due to the electron spin's entanglement with the bath, are examined. We exploit the Cluster Correlation Expansion (CCE) theory to calculate an approximate version of the coherence function and study its behavior.

1. Introduction

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Silicon carbide (SiC) is a well-known material of interest for different technological applications, ranging from shields in accelerators [1] to power devices in electronics [2] and quantum sensors of magnetic field and temperature gradients [3]. For Quantum Technology (QT) applications, the color centers generated by point-like defective configurations constitute the active states. Out of the many SiC polytypes, the most studied ones in the literature are the hexagonal 4 H - and [4], due to the availability of high-quality samples. Recently though, the fabrication techniques and the defectivity control of cubic during the growth process have been greatly enhanced (see e.g. Ref. [5]). Consequently, QT driven investigations dedicated to based systems could raise an increasing interest in the near future.

Due to the relative lack of dedicated studies, our research deals with point defects in 3C-SiC. In particular, we considered the neutral silicon vacancy ( ) magnetically interacting with a bath of naturally occurring Si-29 and C-13 paramagnetic nuclei, i.e., a composite system of interest for QTs because of its optical and coherent control properties [3]. The center, in its neutral charge configuration, can be modeled as a spin-1 defect that evolves in the magnetic environment constituted by the spin-1/2 nuclear spin bath around it. Various control techniques can be applied to the electron spin, such as the use of microwave control pulses that are highly transition-selective [4], effectively reducing the three electron spin's eigenstates to two in the resulting dynamics, so that it can be considered as a qubit. Here we study the effect of the Hahn-echo sequence, an established control technique allowing to refocus the spin coherence resulting from the effect of static magnetic field inhomogeneity and applied in ref. [6] to investigate the residual decoherence of divacancy defects in . To theoretically model such sequence of control pulses, we have employed the Cluster Correlation Expansion (CCE) theory [7]. Such theory consists in breaking up the bath in uncorrelated clusters containing different numbers of interacting nuclear spins, and thereby expressing the qubit coherence as a product of all the contributions coming from the different clusters.

The rest of the paper is organized as follows: section 2 deals with the -initio methods used to calculate the energetics of a neutral silicon vacancy in 3C-SiC. In section 3, based on the system's parameters derived via the ab-initio methods, we numerically calculate the spin coherence evolution under the Hahn-echo sequence, at the first and second order of the CCE expansion, and derive estimates of the decoherence time. Finally, in section 4 our conclusions and ideas for further work are discussed.

Table 1: Formation energies of a neutral silicon vacancy in 3C-SiC and total magnetization for different fcc supercells and k-point sets. Different calculation schemes for the defect's spin are examined, such as the non-polarized (np), non-collinear (nc) and spin-orbit coupling (soc) schemes.

fcc supercell | number of atoms | k points | Form.Ener.(eV) | Tot.Mag.(Bohr mag/cell)
3×3×3 np | 53 | 4 4 4 | 7.30 | not defined
3×3×3 nc | 53 | 4 4 4 | 7.30 | (0.00 0.00 0.09)
3×3×3 soc | 53 | 4 4 4 | 7.30 | (0.00 −0.00 0.09)
4×4×4 np | 127 | 4 4 4 | 7.72 | not defined
4×4×4 nc | 127 | 4 4 4 | 7.61 | (0.00 0.00 2.00)
4×4×4 soc | 127 | 4 4 4 | 7.61 | (0.00 −0.00 2.00)
5×5×5 np | 249 | 4 4 4 | 7.89 | not defined
5×5×5 nc | 249 | 4 4 4 | 7.65 | (0.00 −0.00 2.00)
5×5×5 soc | 249 | 4 4 4 | 7.64 | (0.00 0.00 2.00)
5×5×5 np | 249 | L | 7.89 | not defined
5×5×5 nc | 249 | L | 7.65 | (0.00 −0.00 2.00)
5×5×5 soc | 249 | L | 7.65 | (0.00 0.00 2.00)
6×6×6 np | 431 | 4 4 4 | 7.93 | not defined
6×6×6 np | 431 | L | 7.93 | not defined
6×6×6 nc | 431 | L | 7.66 | (0.00 0.00 2.00)
6×6×6 soc | 431 | L | 7.65 | (0.00 −0.00 2.00)
7×7×7 np | 685 | 3 3 3 | 7.94 | not defined
7×7×7 np | 685 | L | 7.94 | not defined
7×7×7 nc | 685 | L | 7.66 | (−0.00 0.00 2.00)
7×7×7 soc | 685 | L | 7.65 | (0.00 −0.00 2.00)

2. Ab-Initio Defect Formation Energy

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Ab-initio methods based on Density Functional Theory (DFT) are important to calculate, among others, energetic and electronic structure properties of molecules and solids [8]. They can also be used to calibrate magnetic Hamiltonians associated to electron spins interacting with nuclear spin baths, allowing to calculate, for instance, the hyperfine tensor components. The Hamiltonian can be written as

The first term in Eq. (1) is the electron spin Hamiltonian, which is composed by the Zero-Field Splitting (ZFS) terms (first and second term of Eq. (2)), describing the electron spin's self-interaction, and the Zeeman interaction with an external applied magnetic field (last term of Eq. (2)). The last three terms of Eq. (1) are the magnetic hyperfine interactions between the electron and the nuclear spins, the Zeeman terms for each nuclear spin and the dipolar interactions between nuclear spins, respectively. In this context, ab-initio methods are used to capture physical effects due to the 3D
distribution of the spin density in the vicinity of the qubit, which extends significantly until the third neighbor shell in 3C-SiC crystal structure. These effects are not included by the semiclassical approximation, where the electron and nuclear spins are viewed as interacting point magnetic dipoles.

For our computational study we have used the free and open-source Quantum Espresso (QE) code [9] for the energetics. Thus, we have started from the energetics of the defect, by calculating the formation energy of a neutral silicon vacancy within a 3C-SiC supercell with variable size (see Table 1 above). We have used a -point grid for the smaller supercells and an L point sampling for the larger ones, to obtain a good balance between the accuracy of the calculation and its computational cost. Note that from a supercell onward the system's magnetization reaches a stable value, which is the one we expect for an electron spin-1. Furthermore, an interesting thing to note is the importance of correctly modeling the system's spin properties, as this can greatly enhance the convergence of the calculation (see Fig. 1 below). Then we studied other charge states for the and calculated the corresponding formation energies as functions of the electrochemical potential within the bandgap of a 3C-SiC supercell (see Fig. 2 below). We have observed that both the neutral and charged states can be stable in a given range of the electrochemical potential, which can be varied with doping. For instance, the neutral we are interested in is the most stable defect for a p -doped 3C-SiC sample. These calculations have been performed with ultrasoft pseudopotentials.

Fig. 1: Finite scaling analysis of the formation energy for different calculation schemes. Note the faster approach to convergence with a non-collinear (nc) scheme, and adding the spin-orbit coupling (soc), as opposed to the non-polarized (np) scheme.

Fig. 1. Finite scaling analysis of the formation energy for different calculation schemes. Note the faster approach to convergence with a non-collinear (nc) scheme, and adding the spin-orbit coupling (soc), as opposed to the non-polarized (np) scheme.

3. Application of CCE Theory

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In order to tackle the electron-nuclear spin bath problem, we applied the CCE theory [7]. Such theory allows to calculate the off-diagonal component of a solid-state spin quantum system's density matrix, or coherence. In particular, a Python 3 code developed and benchmarked by us, implementing the CCE theory found in literature [10], has been used to calculate the coherence under a Hahn-echo sequence. The CCE equations are the following:

Eq. (3) is the Hahn-echo unitary operator describing the dynamics of the density operator associated to the electron spin interacting with a generic cluster C in Eq. (4), while the Hamiltonian in the exponentials is given by Eqs. (1) and (2), where the only nuclear spins within cluster C are present. Eq. (4) is then substituted in Eq. (5), which is the definition of the contribution to the coherence coming from cluster C. Finally, the coherence in Eq. (6) is calculated as the product of all the contributions coming from the different uncorrelated clusters. Therefore, since the expansion of Eq. (6) can be cut from a given cluster dimension onward, the order of approximation of the theory is defined as the number of nuclear spins inside the biggest clusters we include in Eq. (6). The benchmark was done against Seo et al. [6], whose study is focused on a divacancy in .

Our results, obtained with the customized code, confirm the ones found in the literature [6], and extend them to a neutral in 3C-SiC. In particular, the decay of the coherence is obtained already at the second order of approximation of the CCE theory, or CCE2 level, as shown in Fig. 3 below, left panel. The figure shows the coherence of the qubit under the Hahn-echo sequence, for an external applied magnetic field of 65 G . The blue curve is the coherence calculated at the first order of approximation of the theory, or CCE1 level, where the only contributions considered are from noninteracting nuclear spins. The rapid oscillations of the curve are known as the ESEEM phenomenon in the literature, and are expected to be reproduced at the CCE1 level. At the CCE2 level (orange curve), where also contributions from clusters containing pairs of nuclei are considered, the decay appears. Therefore, pairwise interactions within the bath are responsible for a coherence decay that is not cancelled by the echo [6]. We observe from the right panel of Fig. 3 that, under the approximations performed, the predicted coherence decay is in the milliseconds range. The figure shows the CCE2 coherence and a stretched exponential function fitting its decaying envelope, as well as the optimal values, obtained via a curve-fitting algorithm, for the Hahn-echo coherence time and the stretching factor n of the exponential. These values are 1.124 and 2.448 ms , respectively, for the 150 G curve.

Fig. 2: Graph showing the formation energies of a with and -2 charge states as a function of the electrochemical potential within the bandgap for a 686-atom non-polarized (left) and noncollinear (right) 3C-SiC supercell, respectively.

Fig. 2. Graph showing the formation energies of a with and -2 charge states as a function of the electrochemical potential within the bandgap for a 686-atom non-polarized (left) and noncollinear (right) 3C-SiC supercell, respectively.

Fig. 3: Coherence of a neutral in as a function of free evolution time, within a Hahn-echo sequence, for an external magnetic field of 65 and 150 G , respectively. The result is averaged over 50 different baths. Left: the blue curve is the analytical/CCE1 result and the orange one is the CCE2. Notice the coherence decay in the milliseconds range. Right: CCE2 coherence with a fitting exponential function and the optimal values for the parameters and n , in ms, in the inset.

Fig. 3. Coherence of a neutral in as a function of free evolution time, within a Hahn-echo sequence, for an external magnetic field of 65 and 150 G , respectively. The result is averaged over 50 different baths. Left: the blue curve is the analytical/CCE1 result and the orange one is the CCE2. Notice the coherence decay in the milliseconds range. Right: CCE2 coherence with a fitting exponential function and the optimal values for the parameters and n , in ms, in the inset.

4. Conclusions

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In conclusion, we have used the density functional theory to study the formation energy of the silicon vacancy in , analyzing its charge states and establishing their range of stability as a function of the Fermi level. Moreover, by applying the CCE theory by means of our in-house code, we have evaluated within reliable approximations the ESEEM phenomenon and the decoherence of the spin associated to the defect when Hanh spin-echo protocols with different magnetic field values are applied to the system. The estimated coherence time in is in the milliseconds range.

We hope that our work can inspire new studies on the cubic polytype of SiC , which is gaining new attention within the scientific literature. As for our future perspectives, we are going to complete a magnetic calibration of the Hamiltonian and use the ab-initio calculated values of the hyperfine tensor in our code, to analyze the differences with the semiclassical ones. The preliminary results obtained with a module of QE called Quantum Espresso Gauge-Including Projector Augmented-Wave (QEGIPAW) code [11, 12], show significant deviation with respect to the semiclassical estimates of the model parameters. Finally, we are going to extend such analysis to other defects in SiC and other technologically relevant materials like gallium nitride (GaN).

This work was partially funded by the Italian Ministry for Education, University and Research (MIUR) in the framework of the National Project PON EleGaNTe (Electronics on GaN-based Technologies), Grant No. ARS01_01007.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.309.pdf

Okamura, Katsuya, and Ken Takayama. "High frequency power supply with 3.3 kV SiCMOSFETs for accelerator application." Materials Science Forum. Vol. 897. Trans Tech Publications Ltd, 2017.

Alves, Luciano FS, et al. "SIC power devices in power electronics: An overview." 2017 Brazilian Power Electronics Conference (COBEP). IEEE, 2017.

Castelletto, Stefania, and Alberto Boretti. "Silicon carbide color centers for quantum applications." Journal of Physics: Photonics 2.2 (2020): 022001.

Ivady, Viktor, et al. "Theoretical model of dynamic spin polarization of nuclei coupled to paramagnetic point defects in diamond and silicon carbide." Physical Review B 92.11 (2015): 115206.

Fisicaro, Giuseppe, et al. "Genesis and evolution of extended defects: the role of evolving interface instabilities in cubic SiC." Applied Physics Reviews 7.2 (2020): 021402.

Seo, Hosung, et al. "Quantum decoherence dynamics of divacancy spins in silicon carbide." Nature Communications 7.1 (2016): 1-9.

Yang, Wen, and Ren-Bao Liu. "Quantum many-body theory of qubit decoherence in a finite-size spin bath." Physical Review B 78.8 (2008): 085315.

Chalasinski, Grzegorz, and Malgorzata M. Szczesniak. "Origins of structure and energetics of van der Waals clusters from ab initio calculations." Chemical Reviews 94.7 (1994): 1723-1765.

Giannozzi, Paolo, et al. "QUANTUM ESPRESSO: a modular and open-source software project for quantum simulations of materials." Journal of physics: Condensed matter 21.39 (2009): 395502.

Onizhuk, Mykyta, et al. "Probing the coherence of solid-state qubits at avoided crossings." PRX Quantum 2.1 (2021): 010311.

Pickard, Chris J., and Francesco Mauri. "All-electron magnetic response with pseudopotentials: NMR chemical shifts." Physical Review B 63.24 (2001): 245101.

Varini, Nicola, et al. "Enhancement of DFT-calculations at petascale: nuclear magnetic resonance, hybrid density functional theory and Car-Parrinello calculations." Computer Physics Communications 184.8 (2013): 1827-1833.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 315-319

doi: 10.4028/p-w73601

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-18

Revised:
2022-02-23

Accepted:
2022-03-07

Online:
2022-05-31

Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

The original version of this paper is available on https://www.scientific.net/MSF.1062.315.pdf

Piyush Kumar , Maria Inês M. Martins , Marianne E. Bathen , Judith Woerle , Thomas Prokscha , Ulrike Grossner

¹Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

Laboratory for Muon Spin Spectroscopy, Paul Scherrer Institute, Forschungsstrasse 111, 5232 Villigen PSI, Switzerland

kumar@aps.ee.ethz.ch, maria.martins@psi.ch, bathen@aps.ee.ethz.ch,

woerle@aps.ee.ethz.ch, thomas.prokscha@psi.ch, ulrike.grossner@ethz.ch

Keywords: Muon spin rotation spectroscopy, thermal oxidation, post-oxidation annealing, interface defects.

Abstract

In this work, the interface between and thermally grown is studied using low energy muon spin rotation (LE- SR) spectroscopy. Samples oxidized at were annealed in NO or Ar ambience and the effect of the ambience and the annealing temperature on the near interface region is studied in a depth resolved manner. NO-annealing is expected to passivate the defects, resulting in reduction of interface traps, which is confirmed by electrical characterization. Introduction of N during annealing to the SiC matrix results in a thin, carrier- rich region close to the interface leading to an increase in the diamagnetic asymmetry. Annealing in an inert environment (Ar) seems to have much less impact on the electrical signal, however, the signal shows a reduced paramagnetic asymmetry, indicating a narrow region of low mobility at the interface.

Introduction

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The interface between SiC and thermally grown has large number of interface defects, resulting in low channel mobility and limited device performance. Although NO-annealing has shown to reduce the density of interface states , the resulting changes at the interface and the interplay between N and the SiC crystal are not completely understood . Low energy muon spin rotation (LE- ) spectroscopy is a powerful tool to study thin films and multi-layered structures. The implanted positive muons ( ) act as local probes in the material and enable the extraction of electrical information about the sample in a depth-resolved manner. Herein, we study the effect of thermal oxidation and post-oxidation annealing on the interface of the grown oxide and using LE- SR.

Working Principle of

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The measurements were performed at the low-energy muon (LEM) facility at the Paul Scherrer Institute (PSI), Switzerland [3]. During the experiment, the implanted has the possibility to bind with an electron ( ) in the semiconductor and form a neutral hydrogen-like paramagnetic state known as Muonium ( ). In regions with large carrier concentration, can capture an electron to form or capture a hole to form . Both and are referred to as the diamagnetic states. The paramagnetic and diamagnetic states can be distinguished by their different muon spin precession frequencies in an externally applied magnetic field. The recorded decay asymmetries (diamagnetic: , paramagnetic: ) and the calculated diamagnetic fraction ( ) provide information about the local environment of the implanted .

At LEM, with tunable energy between are implanted at mean depths between and . During slowing down, the produces an ionization track of . Below a few keV , the does not generate by ionization but loses energy by charge-exchange processes [4]. If the leaves the charge-exchange regime as neutral , it is known as 'prompt Muonium'. If the does not form and the final charge state of the muon is positive, it can capture an electron from its ionization track and form what is known as 'delayed Muonium' [5]. Therefore, in order for the delayed to be formed, the electron at the end of the ionization track has to travel to the under the influence of its electric field. The time taken by the electron to reach the depends on the distance traveled and its mobility in that nanoscale of the semiconductor. Therefore, for a low-doped semiconductor and at low temperature where the only available electrons for delayed formation are from the muons' ionization track, a measure of asymmetry is directly proportional to the mobility of electrons around the implantation depth of in the semiconductor [6]. Further details on the measurement procedure are described elsewhere [7].

Experimental Details

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We study n-type, 4 H -SiC samples having a thick epitaxial layer, and a doping density (Nitrogen) of . Thermal oxidation was performed at in atmosphere and the samples underwent a post-oxidation anneal (POA) in NO and Ar atmosphere at for 70 minutes. A thin layer of was deposited on top of the thermal oxide using PECVD to reach a total thickness of 100 nm , such that the distance between the surface and the - SiC interface is equivalent for the three samples. An overview of the sample processing parameters is presented in Table 1.

Results and Discussion

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Fig. 1(a) shows the diamagnetic asymmetry measured. At 10 K , the is expected to stay in the neutral charge state, due to lack of free carriers to form . Therefore, the recorded is similar across the three samples and independent of the POA. The paramagnetic signal as seen in Fig. 1(b) indicates the ease for the last ionization track electron to reach the implanted to form delayed . The paramagnetic asymmetry recorded for the NO-annealed sample is very close to the non-annealed sample indicating that for the two samples, the mobility of electrons perpendicular to the interface is similar. However, the Ar-annealed sample has a smaller indicating a hindrance to the carriers flow in the first 20 nm , beyond which the signal for the three samples is similar. This suggests that the annealing at in Ar ambience affects the first 20 nm of the semiconductor. The recorded for the Ar and NO -annealed samples also show that formation is suppressed in the thermal layer. rises sharply as the SiC region of the sample is reached, showing clearly that the signal is very sensitive to the interface.

Table 1. Description of sample processing steps and resulting oxide layer thicknesses.

Name | Thermal SiO₂ thickness [nm] | Post-oxidation anneal (POA) | PECVD SiO₂ thickness [nm]
1300x | 48 | Not annealed | 52
1300NO1300 | 56 | NO at 1300 °C for 70 minutes. | 44
1300Ar1300 | 48 | Ar at 1300 °C for 70 minutes. | 52

Figure 1: data recorded at and . (a) At low temperatures, due to freeze out of carriers, the formation is suppressed and is similar for the three samples. (b) The signal indicates a higher mobility in the NO-annealed sample when compared to the Ar-annealed sample in the first of SiC .

Figure 1. Figure 1: data recorded at and . (a) At low temperatures, due to freeze out of carriers, the formation is suppressed and is similar for the three samples. (b) The signal indicates a higher mobility in the NO-annealed sample when compared to the Ar-annealed sample in the first of SiC .

The experiments performed at 260 K and 0.5 mT (Fig. 2) show again a drop in the signals for the non-annealed and the Ar-annealed sample, reaching quickly the bulk level [8]. However, the Arannealed sample exhibits a slightly smaller signal, into SiC from the interface compared to the non-annealed sample. The drop in diamagnetic signal is likely due to the reduction in carrier concentration. This argument is also supported by an increase in the signal for the Ar-annealed sample compared to the non-annealed sample beyond 20 nm into the SiC . In contrast, the NOannealed sample has a much higher signal compared to the non-annealed and Ar-annealed samples. The signal for the NO-annealed sample is almost zero whereas it is significantly higher for the other two. Low , together with the increased suggests a region of large carrier concentration, which supports the formation of .

The three samples were characterized electrically and the results of the capacitance-voltage (CV) measurements are shown in Fig. 3 a). Annealing in an Ar environment has very little effect on , whereas with NO-annealing, the is reduced significantly as shown in Fig 3 b). It has been suggested that the silicon vacancies ( ) are formed during thermal oxidation by the emission of silicon, contributing to the large at the interface [9]. Recently, was shown to be sensitive to the presence of in , with enhancing the formation of , resulting in the reduction of the [8]. In our experiment, nitrogen, released during NO-annealing, could passivate the and more specifically , explaining the increase of . The N on the substitutional Si site could act as a donor and result in a region of large carrier concentration. The for the 1300 NO 1300 sample gradually reduces as we move farther away from the interface due to a decreasing Nconcentration in the SiC . This trend suggests that the for the NO -annealed sample would merge with that of the non-annealed sample beyond into the SiC .

Figure 2: data recorded at 260 K and 0.5 mT . (a). The for the NO-annealed sample is significantly higher than Ar and non-annealed samples. (b) for the NO-annealed sample is suppressed, whereas it is significantly higher for the other two samples.

Figure 2. Figure 2: data recorded at 260 K and 0.5 mT . (a). The for the NO-annealed sample is significantly higher than Ar and non-annealed samples. (b) for the NO-annealed sample is suppressed, whereas it is significantly higher for the other two samples.

Figure 3: a) Quasi-static (QS) and high frequency (HF) measurement for the three samples. b) calculated using quasi-static and high-frequency capacitance measurements. The for the NOannealed sample is significantly smaller than for the Ar and non-annealed samples.

Figure 3. Figure 3: a) Quasi-static (QS) and high frequency (HF) measurement for the three samples. b) calculated using quasi-static and high-frequency capacitance measurements. The for the NOannealed sample is significantly smaller than for the Ar and non-annealed samples.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.315.pdf

The effect of oxidation and annealing on has been studied with . NO-annealing results in a region of high carrier concentration near the interface extending up to 70 nm into the SiC region but no appreciable effect on the carrier transport is observed, when compared to the nonannealed sample. Ar annealing has a very slight effect on the (confirmed by CV measurements) and on the signals. However, a reduction in is observed which could suggest a narrow interface region ( ) of reduced mobility.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.315.pdf

Dhar, S., et al., MRS bulletin 30, 288-292 (2005).

Biggerstaff, T. L., et al., Applied Physics Letters 95, 032108 (2009).

Prokscha, T., et al., Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 595, 317-331 (2008).

Prokscha, T., et al., Phys. Rev. Lett. 98, 227401 (2007).

Eshchenko, D. G., et al., Phys. Rev. B 66, 035105 (2002).

Storchak, V., et al., Phys. Rev. Lett. 75, 2384 (1995).

Woerle, J., et al., Phys. Rev. B 100, 115202 (2019).

Woerle, J., et al., Phys. Rev. Applied 14, 054053 (2020).

Hijikata, Y, et al., AIP Advances 5, 067128 (2015).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 320-324

doi: 10.4028/p-04623q

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-19

Revised:
2022-03-22

Accepted:
2022-03-30

Online:
2022-05-31

Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

F. La Via , L. Belsito , M. Ferri , S. Sapienza , A. Roncaglia , M. Zielinski , V. Scuderi

CNR-IMM Catania Stradale Primosole Catania, Italy

CNR-IMM Bologna Via Gobetti 101, 40129 Bologna, Italy

NOVASiC, Savoie Technolac, Arche Bat 4, BP267, 73375 Le Bourget du Lac, France

francesco.lavia@imm.cnr.it, belsito@bo.imm.cnr.it, ferri@bo.imm.cnr.it,

sapienza@bo.imm.cnr.it, roncaglia@bo.imm.cnr.it, mzielinski@novasic.com, viviana.scuderi@imm.cnr.it

*Corresponding author email: francesco.lavia@imm.cnr.it

Keywords: 3C-SiC, stress, Raman.

Abstract

In this work, we investigate, by -Raman spectroscopy the distribution of stress field on a micro-machined structures. They were realized on a 3C-SiC substrate, grown on a Silicon On Insulator (SOI) wafer, after lithography and etching processes. Various structures, such as strain gauge, single and double clamped beams, were analyzed, showing different stress distributions. All the structures show an intense variation of stress close to the undercut region.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

3C-SiC resonators have been investigated for sensing applications [1,2], thanks to the high Quality (Q)-factor that they can achieve at resonance [3], to the higher frequency with respect to other materials for the same geometrical dimensions [4] and to the high Young Modulus [5,6]. In a previous paper [7] has been observed that for crystalline layers the Young modulus increases increasing the thickness thanks to the reduction of the crystal defects (essentially SFs) and that at least a thickness of is needed to obtain the theoretical Young modulus value. In a more recent paper [8], improving the material quality, it has been observed that high values of the Young modulus can be achieved even at lower thickness around for both (100) and (111) 3C-SiC layers. This is a large improvement of the material because it has been observed that the Q -factor depends strongly on the thickness of the layers and high Q-factors can be observed in very thin 3C-SiC layers ( 250 nm )[9]. Q-factor in flexural 3C-SiC resonators critically depends on the presence of stress within the layer, particularly the one appearing on the anchors of the resonator [3] and on the defects present at the interface with the silicon substrate. This effect can be studied with a high resolution spatial technique ( -Raman) that show the stress effect close to the anchors of the resonator [10]. In the previous paper the study has been performed on thick films while in the present paper -Raman measurements on micromachined structures of less than thickness are utilized to derive the residual stress distribution on resonators.

MEMS Realization

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

The films prepared for this study followed typical characteristics of as-grown material presented in previous papers (see details in [11]). 3C-SiC thickness dispersion was below . The RMS roughness ( ) was in the range for (100) epilayers and the range for (111) orientation. The layers were grown on the SOI wafer using classic two-step growth process with silane/propane chemistry. No structural or morphological degradation of was observed with respect to films grown on bare Si substrate. The process illustrated in Fig. 1 was adopted to realize surface micro-machined structures on SOI substrates with SOL and

BOX . After 3C-SiC growth, a double layer of and polycrystalline silicon was deposited on the SiC and patterned by Reactive Ion Etching (RIE) to create the geometry of the structures. Afterwards, the SiC layer was etched by RIE as well, up to the device layer of the SOI underneath and the structures released by etching the device layer by an isotropic plasma. The residual mask after release was removed by HF vapor etching. Empirical calculations [5] on the entire matrix containing several micro-machined structures show a residual stress of about 160 MPa tensile. The stress measure with these structures is essentially connected to the thermal stress due to the presence of the two different materials ( and Si ) that have two different thermal expansion coefficients.

Fig. 1. Fabrication process flow (left panel) and picture of micromachined 3C-SiC test structures (right panel).

Fig. 1. Fabrication process flow (left panel) and picture of micromachined 3C-SiC test structures (right panel).

Raman Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

In order to study the distribution of stress field we performed micro-Raman maps (using a continues He -Ne laser ( 632.8 nm )) on a micro-machined structures. They generally consist of freestanding structures having one or two anchor points with the unreleased region (called undercut region). -Raman spectroscopy is a non-destructive technique particularly useful for the local stress study in micro structures due to the diameter of the laser spot . Transverse optical (TO) Raman mode analysis reveals the stress relaxation on the free standing structure ( ) with respect to the stressed unreleased region. Different structures, such as strain gauge, single and double clamped beams, cantilever, bridge were analysed.

Due to the length of the structure, to reduce the noise present in the experimental acquisition Fig. 2 show the smoothing of the stress profile extracted from the Raman map acquired on a strain gauge. It is essentially a cantilever with an anchor on a suspended structure. Applying the equation proposed by Olego et al. [12, 13], which links the shift of Raman phonon modes to stress relaxation within a 3C-SiC epitaxial layer, we obtained a particular trend of the stress. Close to the anchor point the stress is compressive, along the cantilever the stress decreases and at the end is tensile. This behavior was observed on several strain gauges analysed. However, the cause of this behavior is not yet clear.

Fig. 2: Optical image of the strain gauge (top panel); stress profile extracted from the map (down panel).

Fig. 2. Optical image of the strain gauge (top panel); stress profile extracted from the map (down panel).

Fig. 3 show the TO Raman shift map (Fig. 3(a) and 3(c)) and the stress profile (Fig. 3(b) and 3(d)) extracted from the maps, for a cantilever and a bridge. Both microstructures are wide and 30 and long, respectively. For the cantilever, Fig. 3(b), the stress is quite constant along the structure, with an average value of 160 MPa compressive. Instead, a stress-free value close to the anchorage point of the structures (spectrum between the two dashed lines) was detected. In this case the stress measured by Raman is essentially the intrinsic stress of the film due to the defects present in the layer. Similarly, for the bridge (Fig. 3(d)) the stress is quite constant along the structure, with an average value of 150 MPa tensile, and it reaches a value of 500 MPa tensile close the two anchor points (spectrum between the dashed lines). It is not possible to acquire Raman spectra of SiC correctly, moving in the "bulk" region of the system (beyond the dashed lines in Fig. 3 (a-d), nonreleased areas). In fact, due to the thickness of the SiC (less than ), in the non-released areas, the Raman signal comes mainly from the SOI substrate.

Fig. 3: (a) TO Raman shift map of a cantilever; (b) stress profile extracted from the map; (c) TO Raman shift map of a bridge; (d) stress profile extracted from the map. In the panel a) and c), scale bar is . The dashed lines delimit the undercut region. The unreleased region shows a stress of 130 MPa .

Fig. 3. (a) TO Raman shift map of a cantilever; (b) stress profile extracted from the map; (c) TO Raman shift map of a bridge; (d) stress profile extracted from the map. In the panel a) and c), scale bar is . The dashed lines delimit the undercut region. The unreleased region shows a stress of 130 MPa .

For all microstructures the TO Raman shift in the undercut region evidences a different stress within the film. This difference is due to the processes carried out to realize the microstructure. The plasma etching is an anisotropic process. During the silicon etching, the process also affects the 3C interface, removing a thin layer of . This leads to a small variation in thickness between the center and the edges of the structures which induces a reorganization of the stress fields. The intense variation of the stress near the undercut region can be attributed to a deep modification of the stress tensor where the role of the shear component cannot be neglected [10].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

In this work, we investigate, by -Raman spectroscopy the distribution of stress field on a micromachined structures. In particular, strain gauge, cantilever and bridge were analyzed. For all microstructures the TO Raman shift in the undercut region evidences a different stress within the film. This is associated to the removal of the silicon substrate due to the processing required to fabricate the microstructure.

So, with this technique it is possible to understand the behaviour of the stress inside the microstructures and to optimize the design of the structure and of the anchor points from the point of view of the stress. Future works will be dedicated to analysing systems properly fabricated in order to minimize the generated stress field and defect density within the epitaxial layer.

Acknowledge

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

This research was funded by the European Union within the frame of the project SiC nano for PicoGeo, Grant agreement n. 863220.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.320.pdf

L. Belsito, M. Bosi, F. Mancarella, et al. J. Microelectromech. Syst. 29, 117-128 (2020).

A. R. Kermany, G. Brawley, N. Mishra, et al. Appl. Phys. Lett. 104, 81901 (2014).

E. Romero, V. M. Valenzuela, A. R. Kermany, et al. Phys. Rev. Appl. 13, e44007D (2020).

Y. T. Yang, K. L. Ekinci, X. M. H. Huang, L. M. Schiavone, M. L. Roukes, C. A. Zorman and M. Mehregany, Appl. Phys. Lett., 78(2), 162 (2001)

Lijun Tong, Mehran Mehregany, and Lawrence G. Matus, Appl. Phys. Lett. 60 (24), 2992(1992)

V Cimalla, J Pezoldt and O Ambacher , J. Phys. D: Appl. Phys. 40, 6386 (2007)

R. Anzalone, M. Camarda, A. Canino, N. Piluso, F. La Via, and G. D'Arrigo, Electrochemical and Solid-State Letters, 14 (4) H161-H162 (2011)

S. Sapienza, M. Ferri, L. Belsito, D. Marini, M. Zielinski, F. La Via and A. Roncaglia, Micromachines 12, 1072 (2021).

Atieh R. Kermany, George Brawley, Neeraj Mishra, Eoin Sheridan, Warwick P. Bowen, and Francesca Iacopi, Appl. Phys. Lett. 104, 081901 (2014)

N. Piluso, R. Anzalone, M. Camarda, A. Severino, A. La Magna, G. D'Arrigo and F. La Via, J. Raman Spectrosc. 44, 299 (2013)

M. Zielinski, S. Monnoye, H. Mank, C. Moisson, T. Chassagne, A. Michon, M. Portail, Mater. Sci. Forum, 924, 306 (2018)

D. Olego, M. Cardona, Phys Rev B 25: 1151 (1982).

D. Olego, M. Cardona, P. Vogl Phys Rev B 25: 3878, (1982).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 325-329

doi: 10.4028/p-b76y6c

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-21

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

A.B. Renz , O.J. Vavasour , P.M. Gammon , F. , T. Dai , G.W.C. Baker , N.E. Grant , J.D. Murphy , P.A. Mawby and V.A. Shah

School of Engineering, University of Warwick, Coventry, UK

A.Renz@warwick.ac.uk, o.vavasour.1@warwick.ac.uk, P.M.Gammon@Warwick.ac.uk, ºjohn.d.murphy@warwick.ac.uk, hP.A.Mawby@warwick.ac.uk,

Abstract

A systematic capacitance-voltage (C-V) and time-dependent dielectric breakdown (TDDB) study on silicon carbide ( SiC ) metal-oxide-semiconductor capacitors (MOSCAPs) that use silicon dioxide ( ) is shown in this paper. Oxides were formed using atomic layer deposition (ALD), lowpressure chemical vapour deposition (LPCVD) or direct thermal growth in nitrous oxide ( ) ambient, where both deposited oxides were post-deposition annealed in ambient, too. The electrical characterisation results reveal that the ALD-deposited and -annealed oxides show the best capacitance-voltage ( ) characteristics, with flatband and hysteresis voltages ( ) averaging 1.44 V and 0.41 V , respectively. When measuring the leakage current levels at , the ALDdeposited MOSCAPs' breakdown electric fields are averaging similar to their counterparts at . MOSCAPs which utilized ALD-deposited also showed and increased average injected charge-to failure ( ) at and , respectively, when comparing these devices to their direct thermally grown SiO 2 counterparts.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

Reliability aspects in 4 H -silicon carbide ( ) gate dielectrics, such as an insulator lifetime, threshold voltage stability and high leakage currents, remain an issue of paramount importance, which hamper the further development of power MOSFETs [1]. Most of the interface problems, such as carbon clusters, hydrogen ( H ) and oxygen ( O ) vacancies, are directly related to the thermal oxidation process [2] and can be bypassed by using deposition processes. Among deposition techniques, atomic layer deposition (ALD) offers specific advantages, such as very low deposition temperature, excellent process control[3] and suitability for conformal deposition of gate oxides in trench structures [4]. Deposition of oxide layers is then usually followed by a post-deposition anneal (PDA) in a nitrogen-containing ambient[5], such as nitrous oxide ( ) or nitric oxide (NO)[2], to overcome the as-deposited layer's poor electrical quality.

In this investigation, we present the excellent reliability performance of ALD-deposited layers on SiC , specifically time-dependent dielectric breakdown (TDDB) characterisation of metal-oxide-semiconductor capacitors (MOSCAPs). The results will be shown for post-deposition annealed samples. Here, the distribution of interface parameters, as well as the results from TDDB, will be investigated as metrics of improvement following the PDA process. For benchmarking, processes will be compared to LPCVD-deposited devices, which have undergone the same PDA, and direct thermally grown oxides[5], to demonstrate the superior process quality.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

The active thick epitaxial layer of -type doping was grown in house on 100 mm diameter, off-axis wafers. Growth was performed using a growth rate and nitrogen ( ) as a dopant, in an LPE ACiS M8 chemical vapour deposition (CVD) reactor. After an initial clean, a thick field oxide was deposited and a window was opened via photolithography and reactive ion etching (RIE). Then, quarter wafers underwent one of the three oxidation routines: plasma deposition at using bis(diethylamino)silane (BDEAS) and plasma precursors in an Ultratech Fiji G2 Plasma-Enhanced ALD system. deposition at using tetraethyl orthosilicate (TEOS) as a precursor in a Thermco LPCVD system. 3. Direct thermal growth of in a HiTech furnace at for 5 hrs in ambient. Samples from the first two routines then underwent a PDA in the HiTech furnace, in at for 2 hrs . All oxidation measurements resulted in oxide thicknesses between 50 and 60 nm , which were verified using cross-sectional transmission electron microscopy (TEM) measurements. Finally, 500 nm aluminium (Al) backside contacts were deposited, before a Al layer was deposited on the topside of the samples by means of a liftoff process. A cross-sectional diagram of the fabricated final device structure is shown in Fig. 1 (a).

Figure 1: (a) Cross-section of the fabricated device structures. (b) Leakage current distribution of the measured devices at , with a device area of .

Figure 1. Figure 1: (a) Cross-section of the fabricated device structures. (b) Leakage current distribution of the measured devices at , with a device area of .

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

Table 1 shows the key electrical parameters, extracted using room temperature capacitance-voltage (C-V) measurements, combined with current-voltage (I-V) and constant field TDDB measurements at measurements reveal the already poor quality of ALD as-deposited layers, with flatband voltages averaging 13.94 V and high frequency dispersion in accumulation. All MOSCAPs utilising oxides which were formed in a ambient showed significant improvements. is greatly improved for all -processed samples, with the ALD oxide with PDA offering the lowest flatband voltage, at 1.44 V . Frequency dispersion was greatly reduced for all -processed samples, down to a negligible level of per decade. Although the ALD as-deposited sample shows the lowest hysteresis, the other two deposited layers still showed hysteresis values of 0.41 V , lower than the 0.60 V of the thermally-grown oxide. These results indicate a good general quality of the thermal oxide and of the deposited oxides after PDA.

Figure 1 (b) shows the leakage current distribution of the MOSCAPs at , analysed as a precursor to TDDB, and table 1 shows the extracted breakdown electric field ( ) values. The ALD as-deposited samples showed high leakage current at low voltage and premature breakdown at and were therefore excluded from the TDDB study. The remaining samples, all formed in a ambient, showed significant improvement, with averaging in a similar range, between (ALD SiO with PDA) and (direct thermal growth). TDDB measurements were then performed for constant field values of and , and both the time to failure ( ) and injected charge to failure ( ) were extracted.

Table 1: Key electric parameters of the different MOSCAPs. For flatband voltage, hysteresis and frequency dispersion values, at least 20 devices were measured for each annealing condition at room temperature and all values are given with standard deviations. For I-V analysis and TDDB analysis, at least 50 devices were measured for each split, at .

Sample
EBD
(MV/cm)
VFB
(V)
Hysteresis
(V)
Freq. disp.
(% per decade)
9 MV/cm
9.6 MV/cm

Tfail,63%
(s)
QBD,63%
(C/cm²)
Tfail,63%
(s)
QBD,63%
(C/cm²)

ALD
As-dep.
SiO₂
8.58
± 0.87
13.94
± 0.71
0.31
± 0.08
12.27
± 14.10
-
-
-
-

ALD SiO₂
plus N₂O
PDA
9.71
± 1.38
1.44
± 0.20
0.41
± 0.03
0.18
± 0.06
4786
7.79
120
0.76

LPCVD SiO₂
plus N₂O
PDA
9.83
± 1.09
1.77
± 0.23
0.41
± 0.15
0.13
± 0.06
3715
5.40
65
0.13

Direct
thermal
growth
10.04
± 1.38
2.20
± 0.12
0.60
± 0.26
0.16
± 0.03
3020
5.86
75
0.22

Weibull plots and I-t graphs are shown in Fig. 2, panel (a) and (b) respectively. The ALD oxide with PDA showed the best reliability for all 4 metrics, whereas the LPCVD and thermal oxides gave similar, lower values. For the lower field value of , the ALD oxide improves by , compared to the LPCVD oxide, and by , compared to the thermal oxide. For the higher field value of , the ALD oxide offers a larger improvement, increasing by and by , compared to the thermal oxide. Fig. 2 (b) shows that the breakdown mechanism has changed for the ALD oxide with PDA, showing buildup of positive charge in the MOSCAPs before negative charge triggers breakdown.

Figure 2: (a) Weibull probability distribution and shape factors of more than 50 MOSCAPs for each fabrication process, when stressed at a constant field of at . (b) Current over time for the same devices which were stressed at . ALD samples showed distinct positive charge build up prior to negative charge build up and breakdown, which could be seen for the whole dataset.

Figure 2. Figure 2: (a) Weibull probability distribution and shape factors of more than 50 MOSCAPs for each fabrication process, when stressed at a constant field of at . (b) Current over time for the same devices which were stressed at . ALD samples showed distinct positive charge build up prior to negative charge build up and breakdown, which could be seen for the whole dataset.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

High-quality, high-reliability layers, formed by ALD and post-deposition anneal (PDA), have been demonstrated. Flatband voltage and hysteresis are reduced, compared to thermally grown oxide, and frequency dispersion in accumulation is negligible. At , the oxide critical electric field is in line with thermally grown oxide and LPCVD oxide with PDA. The ALD oxide with PDA has demonstrated higher reliability than LPCVD and thermal oxide in TDDB, offering to improvement. The ALD oxide shows different degradation mechanisms to the LPCVD and thermal oxides, with positive charge building up before breakdown.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

The work presented in this paper has been carried out as part of EPSRC projects EP/P017363/1 and EP/R00448X/1.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.325.pdf

P. Moens, J. Franchi, J. Lettens, L. De Schepper, M. Domeij, and F. Allerstam, "A charge-tobreakdown (q bd) approach to sic gate oxide lifetime extraction and modeling," in International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 78-81, 2020.

P. Fiorenza et al., "Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4 H -SiC MOSFETs subjected to different nitridations," Applied Surface Science, vol. 557, p. 149752, 2021.

S. M. George, "Atomic layer deposition: an overview," Chemical reviews, vol. 110, no. 1, pp. 111-131, 2010.

A. Renz et al., "The improvement of atomic layer deposited interfaces via a high temperature forming gas anneal," Materials Science in Semiconductor Processing, vol. 122, p. 105527, 2021.

K. Tachiki, M. Kaneko, T. Kobayashi, and T. Kimoto, "Formation of high-quality SiC structures by excluding oxidation process with etching before deposition and high-temperature annealing," Applied Physics Express, vol. 13, no. 12, p. 121002, 2020.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 330-334

doi: 10.4028/p-c35702

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-25

Accepted:
2022-03-17

Online:
2022-05-31

KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

The original version of this paper is available on https://www.scientific.net/MSF.1062.330.pdf

Nicolas BERCU , Mihai LAZAR , Olivier SIMONETTI , Pierre-Michel ADAM , Mélanie BROUILLARD and Louis GIRAUDET

Laboratoire de Recherche en Nanosciences EA4682 (LRN), Université de Reims Champagne-Ardenne, France

Lumière, nanomatériaux, nanotechnologies CNRS ERL 7004 (L2n), Université Technologique de Troyes, France

nicolas.bercu@univ-reims.fr, mihai.lazar@utt.fr, olivier.simonetti@univ-reims.fr, pierre_michel.adam@utt.fr, melanie.brouillard@univ-reims.fr, louis.giraudet@univ-reims.fr

Keywords: SiC device characterization, Raman spectroscopy, AFM, KPFM.

Abstract

A non-destructive technique for the characterization of the doped regions inside wide bandgap (WBG) semiconductor structures of power devices is presented. It consists in local measurements of the surface potential by Kelvin Probe Force Microscopy (KPFM) coupled to microRaman spectroscopy. The combined experiments allow to visualize the space charge extent of the doped region using the near-field mapping and to estimate its dopant concentration using the Raman spectroscopy. The technique has been successfully applied for the characterization of a WBG SiC (silicon carbide) device.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.330.pdf

Electronic devices based on wide bandgap semiconductors such as are now widely used in power electronics. The reliability of these power devices is determined by how the strong electric fields present in the semiconductor are handled by device design. Precisely localized doped areas are necessary in order to minimize local electrical field spikes. We present here a non-destructive technique for the characterization of the doped regions in these power devices coupling local measurements of the surface potential by Kelvin Probe Force Microscopy (KPFM) and micro-Raman spectroscopy. The KPFM measurements allow to: i) localize and visualize the extension of the doped regions, ii) identify the location of electric field spikes and iii) characterize the depletion regions at the junction edges or due to doping variations in the semiconductor [1]. Micro-Raman spectroscopy measurements provide additional information on the type of dopants and estimate their concentrations [2].

Experimental Details

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The near-field KPFM technique is an electrical mode of the atomic force microscope. The operating principle is illustrated in Fig. 1 and it uses an original method [3], [4] which allows the simultaneous measurement of the surface electric potential and the second derivative of the tip/air/surface capacitance. This experimental near-field technique uses a two-step scan (dual-pass mode) for each line in order to allow quantitative surface potential measurements on biased devices [4]. While the first line scan (round trip) is used for the surface topography measurement, a second round-trip scan is performed on the same line to measure the surface potential profile. During this second round-trip line scan the probe tip is lifted-up from the surface and follows the previous recorded surface topography at a constant user-defined height of typically a few tenths of nanometers while measuring the local surface potential. An external electronic device (Keysight E5270B) applies the bias voltages to both the sample under test and the AFM tip during the lift scan, the
synchronization with the AFM raster scan being performed using the AFM end-of-line TTL signals [3].

An external digital phase control loop [4] is implemented, enabling to quantitatively measure the surface potential in phase modulation-KPFM mode. The phase shift control loop is based on the measurement of the phase difference between the cantilever excitation drive signal and the actual cantilever oscillation signal. Within a limited tip-to-surface voltage difference ( ), the phase shift describes a parabola following [5]:

where is the sample under test surface potential at the tip location and the bias applied to the tip. The term is the phase parabola opening with the quality factor, the spring constant of the cantilever and the tip/air/surface capacitance.

Fig. 1. Schematics of the KPFM setup and illustration of the lift mode and measured phase shift versus tip bias at various lift heights (B).

Fig. 1. Schematics of the KPFM setup and illustration of the lift mode and measured phase shift versus tip bias at various lift heights (B).

In this study, the area of interest is the lateral emitter junction periphery of a high voltage ( 5 kV ) PiN diode. This area, called the Junction Termination Extension (JTE), is designed to avoid the abrupt increase of the electric field at the emitter edge. The fabrication process and static electrical characteristics of these PiN diodes are detailed in [6, 7]. The diodes crosssection is shown in Fig. 2A and optical images are presented in Fig 2B. The identification of this area of interest is obtained using KPFM thanks to the variation of the second derivative of the capacitance which gives information on the location of the charges [4].

Fig. 2. Structure of the sample with the area of interest of the vertical bipolar PiN diode highlighted (A); Identification of the different device parts on the optical microscope image (B).

Fig. 2. Structure of the sample with the area of interest of the vertical bipolar PiN diode highlighted (A); Identification of the different device parts on the optical microscope image (B).

Raman spectroscopy was already used to measure dopant concentration in specific areas [6]. Compared to conventional techniques such as C-V, SIMS (Secondary Ion Mass Spectrometry) or Hall effect, Raman spectroscopy is a non-contact, non-destructive and easy to implement alternative to investigate doped areas.

Due to its high photon energy, a 325 nm near-UV was selected in order to limit the investigated volume, since the JTE depth is less than . The JTE Al doping profile is presented in Fig 3. A doping concentration plateau between 2 and is obtained from Monte-Carlo simulations and confirmed by SIMS measurements [7].

Fig. 3. Doping profile as a function of the JTE depth.

Fig. 3. Doping profile as a function of the JTE depth.

Results and Discussion

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Using the local capacitance second derivative mapping of the KPFM measurements, the edge of the extension of the JTE implanted junction in reverse bias [7], [8] was identified as illustrated in Fig. 4. The interface between the JTE ( Al p -type doped at ) and the N-doped epitaxial layer (with a concentration of ) is visible away from the emitter, which corresponds to the expected JTE length (as the AFM scanner maximal lateral scan size is smaller than , several consecutive AFM images were performed starting from the metallization edge in order to reach the edge of the JTE region). As shown in Fig 4B, the JTE edge detection is performed using a significant variation of approximately of the measured capacitance second derivative in the KPFM scan lines.

Fig. 4. Mapping of the second derivative of the local capacitance highlighting the edge of the JTE in reverse bias at and capacitive second derivative cross-section showing the step marking the edge of the JTE (B).

Fig. 4. Mapping of the second derivative of the local capacitance highlighting the edge of the JTE in reverse bias at and capacitive second derivative cross-section showing the step marking the edge of the JTE (B).

Once the location and extent of the JTE are identified, the intensity and the position in Raman shift of the characteristic line of the longitudinal optical plasmons-phonons coupling (LOPC) are used to determine the type and the concentration of dopants in the device structure [7]. A systematic shift and a decrease of the LOPC peak intensity are found by focusing alternatively at the JTE and at the N-type epilayer surface (Fig 5), confirming the junction interface detected by KPFM. The low depth of the JTE doping level profile in this particular case (Fig. 3) did not allow a precise estimation of the doping level as the beam interaction depth is higher and therefore interacts also with the N epilayer beneath, even if limited by the use of the 325 nm near-UV laser.

Fig. 5. Raman spectroscopic measurements of the LOPC line ( ) showing a variation of its position in Raman shift and of its intensity as a function of the doping.

Fig. 5. Raman spectroscopic measurements of the LOPC line ( ) showing a variation of its position in Raman shift and of its intensity as a function of the doping.

Therefore, by coupling the near-field KPFM measurements with Raman spectroscopy we obtained a non-destructive technique able to identify the extent of the JTE region of a SiC diode and give information about the dopant type and doping level. Compared to other near-field techniques (such as SCM) the KPFM technique has the advantage of allowing in-situ quantitative surface potential measurements during device operation which can be used for extensive device characterization. This coupled technique can be very useful in reverse engineering of and other WBG power devices.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.330.pdf

A non-destructive technique coupling local measurements of the surface potential by KPFM and micro-Raman spectroscopy was presented. The method was successfully applied to the characterization of the dopants in wide bandgap semiconductor structures. The space charge extent of the JTE region of a wide bandgap SiC diodes could be visualized using the near-field potential mapping, while its dopant concentration could be estimated using Raman spectroscopy.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.330.pdf

This work was financially supported by the Région Grand-Est and the European Community through the FEDER project ATRAKTOR, by the ESR network "site champardennais" through the programs NELO and NOTOR and by the Graduate School NanoPhot. The experiments were carried out within the Nanomat platform (www.nanomat.eu).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.330.pdf

U. Gysin et al., Microelectron. Eng., vol. 160, p. 18-21, juill. 2016, doi: 10.1016/j.mee.2016. 02.056.

Z. Xu et al., Micromachines, vol. 9, n 7, p. 361, juill. 2018, doi: 10.3390/mi9070361.

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C. Raynaud, M. Lazar, D. Planson, J.-P. Chante, Z. Sassi, Mater. Sci. Forum, vol. 457-460, p. 1033-1036, juin 2004, doi: 10.4028/www.scientific.net/MSF.457-460.1033.

M. Lazar, Phd thesis manuscript, INSA Lyon 2002 available on-line these/2002/lazar/page-de-titre.pdf.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 335-340

doi: 10.4028/p-2t7zak

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-03-04

Accepted:
2022-03-07

Online:
2022-05-31

Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

Kohei Yamasue and Yasuo Cho

Tohoku University, 2-1-1 Katahira, Aoba, Sendai, Miyagi 980-8577, Japan

yamasue@riec.tohoku.ac.jp, yasuocho@riec.tohoku.ac.jp

Keywords: SiC-MOSFET, Interface defects, Scanning nonlinear dielectric microscopy, Surface potential fluctuations, Local capacitance-voltage profiling

Abstract

We investigate surface potential fluctuations on interfaces by local capacitancevoltage profiling based on time-resolved scanning nonlinear dielectric microscopy. As experimental indicators of surface potential fluctuations, we measured the spatial fluctuations of local capacitancevoltage and its first derivative profiles through the detection of the voltages at the infection points of the profiles. We show that, even for a sample with a nitrided interface with low interface defect density, the fluctuations of the measured voltages are much higher than the thermal energy at room temperature. This indicates the existence of high potential fluctuations, which can give a significant impact on the carrier transport at the interface of SiC metal-oxide-semiconductor field effect transistors.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

interfaces have been extensively studied because of their significant impact on the performance of the SiC metal-oxide-semiconductor field effect transistors (MOSFETs) such as channel mobility and threshold voltage . Si-face 4 H -SiC MOSFETs with an as-oxidized MOS interface typically show a peak field effect mobility ( ) of or less. As a standard treatment, post oxidation annealing (POA) in nitrogen rich environments has been established for the reduction of interface defect density ( ) [3-7]. Although the POA treatment improves the peak of (e.g. POA in NO achieves about ), the achievable mobility is still much lower than the bulk mobility in SiC. In order to understand the cause of the observed low mobility, possible mechanisms have been suggested so far [8, 9]. In addition, recently, the formation of the interface by hydrogen etching pretreatment of a SiC surface followed by deposition instead of thermal oxidation has been proposed and paid considerable attention as a key to further drastic reduction of interface defects including those at shallow levels [10]. It has been demonstrated that this new technique allows the fabrication of normally-off transistors with of at the peak [11]. However, the record value is still one order magnitude lower than bulk carrier mobility of SiC ( 1000 ).

For deeper understanding of the interface properties, we focus on surface potential fluctuations on interfaces. An early study using the conductance method by Bano et al. has shown that, unlike interfaces have surface potential fluctuations largely exceeding the thermal energy at room temperature ( ) [12]. It has been pointed out that the high surface potential fluctuations can give a significant impact on the carrier transport at the interfaces [12, 13]. Thus, here we investigate the surface potential fluctuations at the interfaces by scanning nonlinear dielectric microscopy (SNDM) [14]. SNDM is a scanning probe microscopy method that has exceptionally high sensitivity to the variation in the microscopic capacitance. So far, the imaging the first voltage derivative of capacitance ( ) by the conventional SNDM was performed on various samples. It has been shown that the images for the samples with different macroscopic levels have commensurate levels of spatial fluctuations [15]. The fluctuations of reflect those of local CV profiles in part. If the local CV profiling is enabled, we are able to give real-space microscopic insights on the surface potential fluctuations of the interfaces.

In this paper, we perform local CV profiling on based on recently developed time-resolved SNDM (tr-SNDM). We discuss the spatial fluctuation of local CV profiles in real-space by extracting the voltages giving particular features of the profiles. We show that the fluctuations of the extracted voltages are much higher than the thermal energy at room temperature.

Local CV and-Profiling

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

Local CV profiling was here performed using tr-SNDM [16]. A tr-SNDM setup was implemented to a commercial atomic force microscopy (AFM) system (Bruker, Dimension Icon) operated in air at room temperature. We mounted a lab-made SNDM probe on the AFM head; the SNDM probe is made of an LC self-oscillator and detects the variation in the microscopic capacitance below the conductive tip of an AFM cantilever attached to the oscillator. The center frequency of the oscillator is modulated by the capacitance variation caused by a voltage pulse applied between the tip and sample. Unlike the conventional SNDM using classical analog signal processing, tr-SNDM demodulates the capacitance response to the voltage pulse by the high-speed direct digitization and offline software signal processing. This permits wide measurement bandwidth and flexible signal treatments. The more details of the technique and setup can be found in Ref. [16].

We can perform point-by-point local CV and profiling by sweeping the voltage at each measurement point on the sample [17, 18]. When a triangular voltage pulse is used for the voltage sweep, the resulting capacitance response can be converted to backward and forward local CV profiles over the sweep range [17]. In addition, the first derivative of the local CV profile, or a profile, can be simultaneously taken by adding a small high frequency voltage to the triangular pulse [18]. The profile can be obtained from a high frequency component arising in the capacitance response, because it has a higher amplitude as the slope of the local CV profile increases. The local CV profiling performed here differs from the standard macroscopic CV profiling based quasi-static voltage sweep. The sweep rate in the local CV profiling is typically equivalent to the frequency in the order of 10 kHz and thus the profiles reflect deep depletion in the depletion region, since an inversion layer is not formed during the fast voltage sweep.

In order to discuss the spatial fluctuations of the local CV profiles, here we focus on the fluctuations of the voltages at the infection points of the individual local CV and profiles. As shown in Fig. 1, these voltages are here denoted and and respectively denote the voltage at the infection point of a local CV profile and that of the corresponding profile. We extract and to estimate the voltage shifts of the local CV profiles. and are numerically detected by finding the voltage at the negative peak of a local profile and that at the positive peak of a local profile, respectively. Local profiles are numerically derived from the profiles. The fluctuations of and are experimental indicators for surface potential fluctuations, because the fluctuations of a built-in potetial at the interface causes the shift of the local CV profiles. The fluctuations can be caused by the spatially non-uniform distribution of and fixed oxide charge density at the interface. and can have different spatial distributions, because they reflect the different spatial distributions of charge states at the different energy levels in general. Since is located closer to the deep depletion region, the spatial fluctuations of are dominated by those of the static charge states with no significant dependence on the applied voltage such as fixed oxide charges and deep level defects. The fluctuations of located near the accumulation region are further affected by those of voltage-dependent charge states such as defects at shallower levels. This implies that is expected to be higher than , as the fluctuations of are cumulatively affected from the shallower levels as well as the static interface charge states.

It is noted that similar local CV analysis, called scanning capacitance spectroscopy [19], has also been performed for samples by scanning capacitance microscopy [20]. In Ref. [20], local CV profiles were obtained by integrating profiles to discuss the spatial fluctuations of , while the sweep rate was much smaller that that in this study.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

Here we measured local CV and profiles on two different n-type samples with a 10 nm -thick thermal oxide layer and dopant concentration. One of the samples was as-oxidized but the other was further treated by POA in NO gas for 60 min . at 1250 deg . C. The oxide layers of the measured samples were thinner than those of typical SiC wafers for power device applications in order to obtain higher spatial resolution in local CV profiling. We think that even the samples with such a thin oxide layer are worth investigating. This is because, as reported in Refs. [21, 22], electric defects such as interface defects, oxide charges, and near interface traps have been detected even for SiC with thin oxide layer thickness, while their density depends on the thickness. In addition, it has been considered that nitrogen atoms are localized at the interface treated by POA in NO gas [23, 24].

We used a Pt -Ir coated microcantilever with a 100 nm radius tip (NanoWorld, EFM-100). For local CV profiling, we applied a 1.5 cycle triangular voltage pulse with an amplitude of and a slew rate of . In addition, a 1 MHz and high frequency sinusoidal voltage was added to the triangular pulse for the simultaneous profiling. The voltage was applied to the sample relative to the grounded tip. For the reduction of noise, a local CV profile was obtained by averaging the capacitance responses to repetitive 160 voltage pulses at each measurement point. The scan size was for both samples.

Figure 2 shows typical local CV [Fig. 2(a)] and [Fig. 2(b)] profiles for the as-oxidized sample. It is confirmed that the local CV profiles showed typical n-type characteristics with a negative slope. As shown in Fig. 3, the nitrided sample had local CV and profiles less stretched out than the as-oxidized one, which was expected from the significant reduction of by the POA treatment. Figures 4 and 5 show and images for the as-oxidized and nitrided samples, respectively. The images were reconstructed by extracting and values from the backward and forward local CV and profiles. We found that and had spatially non-uniform clustered distributions as similar to reported in the previous study [15]. The standard deviations (SDs) of and were summarized in Table I for the comparison of fluctuations. For obtaining values, outliers were excluded, because was not detected within the measurement range on some measurement points especially for the as-oxidized sample. The SDs of were as high as 1 V for the as-oxidized sample but decreased by for the nitrided sample, which indicates the POA treatment significantly reduces contributing surface potential fluctuations. less fluctuated than for both samples, as expected from the location of closer to the deep depletion region with lower interface charge density. The SDs of also decreased by through the POA treatment and became lowest but still several times higher than the thermal energy at room temperature. This suggest that the elimination of the static interface charges and their fluctuations is at least necessary to suppress surface potential fluctuations within the thermal energy level.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

We performed local CV profiling on the as-oxdized and nitrided samples for investigating the surface potential fluctuations, which may give a significant impact on the carrier transport properties of SiC MOSFETs. The SDs of and largely exceeded the thermal energy at room temperature even for the nitrided sample. Our results indicate that surface potential fluctuations remain high even after the significant reduction of by the POA treatment. It seems that the surface potential fluctuations are already higher than the thermal enegy due to the contribution of the static interface charge states such as fixed charges and deep level defects and they further increase with the charge trapping to shallower levels.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

We thank Dr. Hajime Okumura and his group of National Institute of Advanced Industrial Science and Technology for providing samples and macroscopic evaluation results. We also thank

Mr. Toshihiko Iwai, Tohoku University, Japan, for the development of SNDM probes. We are grateful for the experimental assistance given by Ms. Tamiko Ambo, Tohoku University, Japan. This work was supported in part by Grant-in-Aid for Scientific Research (S) (Grant No. 16H06360) from the Japan Society for the Promotion of Science.

Fig. 1. Schematic illustration of local CV [(a)], , and profile [(c)] for an type local metal-insulator-semiconductor capacitor. and respectively denote the voltage at the infection point in (a) and that in (b).

Fig. 1. Schematic illustration of local CV [(a)], , and profile [(c)] for an type local metal-insulator-semiconductor capacitor. and respectively denote the voltage at the infection point in (a) and that in (b).

Fig. 2. Typical local (a) CV and (b) profiles of the as-oxidized sample

Fig. 2. Typical local (a) CV and (b) profiles of the as-oxidized sample

Fig. 3. Typical local (a) CV and (b) profiles of the nitrided sample

Fig. 4. and images of the as-oxidized sample.

Fig. 4. and images of the as-oxidized sample.

Fig. 5. and images of the nitrided sample.

Fig. 5. and images of the nitrided sample.

Table I. Standard deviations of fluctuations in and

Sample | V₁ (backward) / V | V₁ (forward) / V | V₂ (backward) / V | V₂ (forward) / V
As-oxidized | 1.01 | 1.12 | 0.25 | 0.24
Nitrided | 0.22 | 0.22 | 0.14 | 0.13

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.335.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 341-345

doi: 10.4028/p-2ch22f

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-25

Revised:
2022-02-25

Accepted:
2022-03-17

Online:
2022-05-31

4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

The original version of this paper is available on https://www.scientific.net/MSF.1062.341.pdf

D. Planson , C. Sonneville , P. Bevilacqua , L.V. Phung , B. Asllani , D. Tournier , P. Brosselard

¹Univ Lyon, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, CNRS, AMPERE, F-69621, Lyon, France

Caly Technologies, 62 Boulevard Niels Bohr, CS52132, F-69603 Villeurbanne Cedex, France

dominique.planson@insa-lyon.fr, camille.sonneville@insa-lyon.fr, pascal.bevilacqua@insa-lyon.fr, luong-viet.phung@insa-lyon.fr, besar.asllani@insa-lyon.fr, d.tournier@caly-technologies.com, p.brosselard@caly-technologies.com

*corresponding author

Keywords: 4 H -SiC bipolar diode, high voltage device, electro-physical characterisation, periphery protection, OBIC.

Abstract

This paper presents micro-OBIC measurements performed at different voltages on two devices protected by narrow field rings. At the surface of the device #1, a polyimide layer was deposited during the fabrication process. In contrast, the passivation layer was removed on device #2. Thanks to the micro-OBIC micrometer spatial resolution and the spot size that was carefully focused, small gaps in the range of can be visible on OBIC profiles. Thus, the variation of the microOBIC signal accurately reflects the topology of each ring.

Introduction

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Silicon Carbide (SiC) is an attractive semiconductor material for high power and high temperature applications. To reach the expected breakdown voltage, an effective junction termination is required to spread the electrical field profile towards edges mitigating the crowding effect. Among different techniques used for periphery protection [1], Junction Termination Extension (JTE) is a well-known technique often chosen due to their relative design simplicity. However, the structure of the present paper relies exclusively on guard rings, a more challenging approach where small technological deviations on the rings position can completely negate the benefits of the periphery protection. To get the most from those rings, key parameters such as the distance between each ring and the number of rings must be carefully chosen. The efficiency of this periphery protection is optimal when the electric field at the edge of each ring is nearly equal for all rings. Optical Beam Induced Current (OBIC) technique is a non-destructive characterization technique used here to analyze the electric field distribution at the edge of the device periphery. OBIC is an alternative technique compared to other complicated methods like Kelvin Probe Force Microscopy (KPFM) and Electronic Beam Induced Current (EBIC) microscopy, for high resolution analysis of electronic devices. This technique has been used to investigate silicon diodes protected by field rings [2], with spacing greater than , as well as PiN diodes protected by JTE [3], [4]. In this paper, micro-OBIC technique is applied to SiC high voltage bipolar diodes where the design of the guard rings is more tightly constrained to analyze the experimental behavior of the periphery protection with respect to the applied reverse voltage.

Experimental Setup

The original version of this paper is available on https://www.scientific.net/MSF.1062.341.pdf

In the micro-OBIC experimental setup, a 349 nm UV pulsed laser is used to generate electron-hole pairs (EHPs) in the sample due to the laser beam with energy greater than the band gap energy. A set of properly adjusted optics (mirrors, microscope objective ...) is inserted on the beam path to finally get a focused laser spot with a diameter of about as shown on Fig. 1. The sample is placed on
a motorized stage and the position is controlled with LabView (i.e. on automatically and inclination manually). The laser beam energy at the top surface of the device is high enough to generate electron-hole pairs (EHPs), so that an OBIC current could be measured. The micro-OBIC principle has already been described in [4].

The testbench allows us to realize a spatial mapping of OBIC signal, either on a ( ) plane or only on X (or Y) lines. For X or Y lines, the step between two displacements of the laser beam is 200 nm . The DUT can be reverse biased by applying voltage up to 500 V thanks to the SMU (Source Measure Unit) Keithley 237.

Fig. 1. Schematic representation of the micro-OBIC testbench.

Fig. 1. Schematic representation of the micro-OBIC testbench.

The cross section of the DUT and its periphery is sketched on the Figure 2. For the sake of clarity, only one periphery protection is sketched in Fig. 2-a). The epilayer is thick, n-type doped ( ). The main junction is realized by ion implantation, at the same time as the field rings, which were carefully designed by Caly Technologies. The diode is then protected by a passivation layer on the front side.

The measurements were realized on two different square-shaped bipolar diodes protected by field rings, namely device 1 and device 2, with and without passivation layer respectively.

Fig. 2. a) Schematic cross section view of half vertical PiN diodes protected by 22 field rings (principle is sketched here only with 13 rings), b) photograph of the diode with the (diameter) gold ball bonding.

Fig. 2. a) Schematic cross section view of half vertical PiN diodes protected by 22 field rings (principle is sketched here only with 13 rings), b) photograph of the diode with the (diameter) gold ball bonding.

The metallized anode contact is square-shaped, with a side length of , and a corner curvature radius of as shown in Fig. 2-b.

This non-destructive technique allows to measure OBIC currents by scanning the outer edge of the biased diode, in order to assess the periphery protection efficiency. OBIC current increases as the electric field intensity increases in the structure. There is no OBIC current on the metallization, neither far from the periphery of the diode. These OBIC current profiles would come in handy to the designer to optimize the breakdown voltage. The diode is protected by 22 field rings as shown in Fig. 2, with
increasing spacing between them ( from one ring to the next). The distance between the main junction and the first ring is . All the rings have the same width .

Inside a vacuum probing chamber, on-wafer measurements of the devices demonstrated a stable blocking voltage up to 2 kV as shown in Fig. 3.

Fig. 3. Reverse characteristics of both devices (diode #1 with polyimide passivation, diode #2 without any passivation).

Fig. 3. Reverse characteristics of both devices (diode #1 with polyimide passivation, diode #2 without any passivation).

Results and Analysis

The original version of this paper is available on https://www.scientific.net/MSF.1062.341.pdf

By applying different reverse voltages (up to 500 V ) to the same diode and re-scanning the very same location, several OBIC currents can be compared to each other, as shown in Fig. 4. As the reverse voltage increases, the OBIC current increases for the same location, due to the increase of the electric field. One can also observe the extension of the space charge region as the reverse voltage increases and the role of outer field rings, witness of the peripheral protection good design.
As the reverse voltage increases, the number of OBIC peaks increases. From up to , each maximum is related to the presence of a ring as described in [1] and, more precisely, is located on the outer edge of each ring junction. As the reverse voltage increases, the presence of the rings is more clearly revealed by -OBIC. Indeed, the number visible rings by OBIC increase with the reverse voltage. These measurements up to 500 V , show the presence of very close rings (between for the first two rings and for the last two rings). One can count all the 22 field rings for a reverse voltage of 500 V plus one more peak for the border of the main junction. That means that at 500 V all the rings are revealed by the OBIC method.
The amplitude of the maximum doesn't increase much from one voltage to another. The distance between the peaks is in total accordance with the layout of the rings as shown in the figure and in Table 1. Table 1 gives the position of the first 11 rings based on its left lateral edge that is oriented towards the main junction when viewed from the cross-section depicted in fig.2a. The OBIC signal amplitude is given for each left lateral edge. Comparing the data from Table 1 and the OBIC profile shown in Fig. 4, each dip in the profile perfectly matches with the left lateral edge of each ring. All the data in the table 1, were extracted from diode #2 biased under 500 V .

Table 1. Distance from the main junction for ring mask layout and respective OBIC signal values.

Ring number | #1 | #2 | #3 | #4 | #5 | #6 | #7 | #8 | #9 | #10 | #11
Distance from main junction (μm) | 1.2 | 3.97 | 6.81 | 9.72 | 12.7 | 15.75 | 18.87 | 22.06 | 25.32 | 28.65 | 32.05
OBIC signal | 1.19 | 3.99 | 6.99 | 9.79 | 12.79 | 16 | 18.8 | 22.21 | 25.38 | 28.79 | 32.2

After measuring diode #1, some scratches appeared at the surface of the device under test, due to the sweeping of the laser. In fact, this device was passivated with a polyimide layer, allowing a uniform and homogeneous spreading of the electric field as shown in Fig. 4, and the opportunity to test the DUT without package, i.e. avoiding any electrical arcing in the air. With respect to the beam penetration, this additional layer acts as a UV light filter and then can be physically altered, consequently the OBIC signal is reduced by a factor of 100 approximately. Nonetheless, Figure 4 shows the benefits of polyimide layer at the top in terms of electric field distribution: at 500 V the OBIC current is almost constant whereas Figure 5 shows a decrease in OBIC current value. For diode #1 one can observe all the rings from 300 V .

Fig. 4. OBIC currents at the periphery of the diode device #1 (with polyimide) for different reverse voltages (ranging from 0 V up to 500 V ). The mask layout with the spacing between the rings is in grey color.

Fig. 4. OBIC currents at the periphery of the diode device #1 (with polyimide) for different reverse voltages (ranging from 0 V up to 500 V ). The mask layout with the spacing between the rings is in grey color.

In order to study the periphery protection without any passivation layer, the polyimide was removed with a very high-density plasma on a new die. Then, the same experiment has been performed on diode #2 without polyimide layer at the top. The applied reverse voltage was also limited to 500 V . The results are shown in Fig. 5. For diode #2 One can observe all the rings from 400 V .

Compared to the previous measurements on both devices, performing measurements without the polyimide layer gives OBIC profile that reflects the peripheral protection more regular. In both cases, the peaks are related to the distance between the rings, and that is true even for very small distance as low as . More investigation is needed to properly discriminate the electrical effect of the passivation layer and its optical effect as a light filter.

Fig. 5. OBIC currents at the periphery of the diode device #2 (without polyimide) for different reverse voltages (ranging from 0 V up to 500 V by 50 V step). The mask layout with the spacing between the rings is in grey color.

Fig. 5. OBIC currents at the periphery of the diode device #2 (without polyimide) for different reverse voltages (ranging from 0 V up to 500 V by 50 V step). The mask layout with the spacing between the rings is in grey color.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.341.pdf

This paper presents OBIC measurements performed on field rings protected bipolar diodes at different voltages. This test-bench has a well improved spatial resolution compared to the previous OBIC test-bench. We estimated theoretically and experimentally the spatial resolution of the microOBIC to be around . A better resolution is interesting to characterize peripheral protections, such as JTE rings, whose lateral extension is of the order of magnitude of the micron.

JTE rings are directly observable in these experiments, even with narrow distances between each 22 rings. In the near future, this study will be completed by measurements at higher reverse bias under vacuum and to be closed to the breakdown voltage of the device . Indeed, we could transfer the -OBIC test bench into a vacuum 10 kV chamber. It would be also interesting to study these same diodes by other complementary characterization methods such as micro-Raman spectroscopy, SEM/EDX and TOF-SIMS.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.341.pdf

P. Godignon et al., this conference (Tu-1A-Inv).

R. Stengl, High-voltage planar junctions investigated by the OBIC method (1987), IEEE Transactions on electron devices, vol. ED-34, no. 4, pages 911-919.

C. Sonneville et al., Materials Science Forum Vol. 1004, (2020) pp. 290-298.

D. Planson et al., Materials Science in Semiconductor Processing Vol. 94 (2019) pp 116-127

H. Hamad, C. Raynaud, P. Bevilacqua, S. Scharnholz, D. Planson, Materials Science Forum Vols. 821-823 (2015), p. 223-228.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 346-350

doi: 10.4028/p-fnktjf

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-21

Accepted:
2022-03-07

Online:
2022-05-31

Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

Manuel Belanche , Piyush Kumar , Judith Woerle , Roger Stark and Ulrike Grossner

Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

stark@aps.ee.ethz.ch, ulrike.grossner@ethz.ch

Keywords: interface characterization, quasi-static capacitance, capacitance-voltage measurements, MOS capacitors.

Abstract

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4 H -SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density ( ). We show that the extracted strongly depends on the calculation of the surface potential due to variations of the integration constant . In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the extraction.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

Owing to its beneficial electrical and thermal properties, silicon carbide (SiC) is a well-established material for power electronic devices. However, the widespread use of SiC MOSFETs in power applications results in increasingly demanding requirements regarding their performance and reliability. Despite the commercial success of SiC MOSFETs, there are still unsolved reliability issues related to the number of defects and near-interface traps situated at the interface between silicon carbide and silicon dioxide ( ) that are generated during thermal oxidation [1]. Therefore, a careful analysis of the density of interface traps ( ) and their effect on the device performance is crucial for process development and monitoring.

Different methods have been used to study the at the interface [2], among which capacitance-voltage (CV) measurements are the most established technique due to their apparent simplicity in both execution and interpretation of results. The can be extracted as a function of the energy position in the bandgap by comparing a low-frequency or quasi-static capacitance curve with a high-frequency measurement [3] or a theoretical CV curve [4].

However, in quasi-static capacitance measurements, the values obtained for low capacitances are very sensitive to the setup parameters used in the analysis of . This can lead to inaccuracies that are difficult to detect but strongly influence the final result. Here we present a study of the systematic errors encountered when performing quasi-static capacitance-voltage measurements and the subsequent extraction of for the analysis of the interface.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

The devices tested are 4 H -SiC n-type MOS capacitors. For the results in Fig. 1, the analyzed MOS capacitors have a doping concentration of and 48 nm of thermal oxide grown at . The high-frequency capacitance was measured using the Keithley 4200A-SCS.

The quasi-static measurements shown in Fig. 2 and Fig. 3, were performed on MOS capacitors with a 23 nm thick thermal oxide using three systems: Keithley 595 QS CV Meter, Keysight B1500A and Keithley 4200A-SCS. The gate electrode used for all MOS capacitors was a 100 nm layer of nickel deposited with e-beam evaporation.

Extraction of Surface Potential

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

For the study of the , we use the method [4]. In this method, the relationship between the applied gate bias ( ) and the surface potential ( ) is calculated with the quasi-static ( ) and oxide capacitance ( ) by solving the Berglund integral [5]:

where:

Following the method [4], the constant is determined from the extrapolation of a linear fit of vs , where the depletion capacitance ( ) is obtained from a high-frequency CV measurement, i.e. assuming there is no influence from traps. Here we observe that the range used to perform the linear fitting influences the value of . Even though the shift in seems small, it can have a strong impact on the along the energy axis [6], causing a wrong evaluation of the defect density at the interface. In order to extract , it is crucial to limit the linear fit to the range where the MOS capacitor is in depletion, i.e. were decays linearly with , and to not include the voltage range of deep depletion, where the relation vs. is not linear anymore. The depletion region boundaries can be identified by considering that the slope of is inversely proportional to the doping concentration of the epitaxial layer [3].

Figure 1. Impact of the linear fitting range on the analysis of the interface. a) Linear fitting of (blue) for four different voltage ranges and their extrapolation (fit ) to obtain the integration constant . b) Impact of the small variations in on the extraction. Different fitting regions are shown: from depletion to weak accumulation (dark green), only the depletion region (light green), different ranges in the deep depletion regime (red and orange).

Figure 1. Figure 1. Impact of the linear fitting range on the analysis of the interface. a) Linear fitting of (blue) for four different voltage ranges and their extrapolation (fit ) to obtain the integration constant . b) Impact of the small variations in on the extraction. Different fitting regions are shown: from depletion to weak accumulation (dark green), only the depletion region (light green), different ranges in the deep depletion regime (red and orange).

In Fig. 1a, the results of the CV analysis are shown, where the blue curve was obtained at a measurement frequency of 2 MHz . The red and orange curves are obtained by fitting in a range that leads the MOS capacitor into deep depletion and depletion. The dark green curve is evaluated using where the MOSCAP is in accumulation; whereas the light green is obtained by applying the fitting only in depletion. The distance between the intersection point, , for each of the fit ranges is small; from 0.1 V for the smallest to 0.9 V for the largest. The impact of such voltage shifts on the profile is shown in Fig. 1b. These apparently small voltage shifts of can translate to a wide shift of the curve, resulting in a wrong estimation of the interface quality.

Therefore, for obtaining the constant , the fitting of vs must be performed in the depletion region only, which requires a precise selection of the fit range for each device under test.

Analysis of Quasi-Static Capacitance-Voltage Setup Parameters

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

In order to calculate and proceed with the method, a quasi-static capacitance-voltage measurement is required. We have studied the sensitivity of the measurement with respect to the selected ramp-rate (V/s), which is one of the main setup parameters in a quasi-static measurement system. Moreover, we have investigated the impact of using three different setups for the measurements on the extraction.

The ramp-rate ( ) in a quasi-static measurement represents a trade-off between the resolution of the voltage sweep and the noise in the capacitance value [7]. This is illustrated in Fig. 2a showing the quasi-static capacitance ( ) measurements with three different ramp-rates: and , respectively. Applying the method for each of the ramp-rates, we observe that closer to the conduction band, there is a deviation of the extracted for the when compared to the other two values. This originates from the increasing noise in the measured discharge capacitance that becomes more prominent at low ramp-rates.

Figure 2. Influence of ramp-rate on capacitance analysis of the interface, measured with the Keysight B1500A. a) Quasi-static capacitance measured with different ramp-rates: (dark green), (ochre) and . b) extraction from the measurements with different ramp-rates in a).

Figure 2. Figure 2. Influence of ramp-rate on capacitance analysis of the interface, measured with the Keysight B1500A. a) Quasi-static capacitance measured with different ramp-rates: (dark green), (ochre) and . b) extraction from the measurements with different ramp-rates in a).

We acquired the QS measurement of the capacitance with three different systems: Keithley 595 QS CV Meter, Keysight B1500A and Keithley 4200A-SCS. Fig. 3a illustrates the different quasi-static curves measured by the different setups. The results obtained with the different setups show small variations over the entire voltage sweep from deep depletion to accumulation attributable to the slight differences in the quasi-static principles used by each system. Also shown are 1 MHz and 1 Hz
capacitance curves measured with the MFIA Zurich Instruments system that were analyzed using the high-low capacitance method [8].

Taking into consideration the sensitivity of the surface potential calculation as well as the ramprate effect previously discussed, we applied the method and compared the distribution from the measurements performed with the three quasi-static systems, Fig. 3b. We observe that for energies higher than , the results of the three quasi-static setups are matching. However, due to the small differences in lower capacitance, and lower voltage values, the distribution shows a different behaviour in the energy below for the the Keysight B1500A compared to the results from the Keithley 595 QS CV Meter and the Keithley 4200A-SCS. Moreover, Fig. 3b includes the results obtained with the high-low technique [8], which, as expected [4], underestimates the density of interface traps.

Figure 3. a) Quasi-static capacitance measured with the different setups. b) extraction from the different quasi-static setups with the method (dark green, ochre, red) and simultaneous highlow method (blue).

Figure 3. Figure 3. a) Quasi-static capacitance measured with the different setups. b) extraction from the different quasi-static setups with the method (dark green, ochre, red) and simultaneous highlow method (blue).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

In this work, we have studied how the choice of the quasi-static CV setup and selected parameters for applying the method influence the evaluation of . Capacitance-voltage measurements of 4H-SiC n-type MOS capacitors show that the calculation of the surface potential can be a strong source of error if the depletion region is not well identified during the extraction of the integral constant . We assessed the influence of ramp-rate in the quasi-static measurements and observed that its impact is more prominent for lower values of energy due to the increasing relative noise. Finally, we compared three commonly used quasi-static systems, finding differences in their distribution, more noticeable for lower energies. Further studies are needed to ascertain the optimal system and setup for the application of quasi-static methods.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.346.pdf

V. V. Afanasev, M. Bassler, G. Pensl, M. Schulz, Intrinsic SiC/SiO2 Interface States, Phys. Stat. Sol. (a), 162(1), 321-337 (1997).

J. A. Cooper, Advances in SiC MOS Technology, Phys. Stat. Sol. (a) 162, 305-319 (1997).

E. H. Nicollian, J. R. Brews, MOS Physics and Technology, Wiley, New York (1982).

H. Yoshioka, T. Nakamura, T. Kimoto, Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance, J. Appl. Phys. 111, 014502 (2012).

C.N. Berglund, Surface States at Steam-Grown Silicon-Silicon Dioxide Interfaces, IEEE Trans. Electron Dev. ED-13, 701-705 (1966).

D. K. Schroeder, Oxide and interface trapped charges, oxide thickness, in Semiconductor material and device characterization, John Wiley & Sons (2006).

A. Wadsworth, Keysight technologies: The parametric measurement handbook (2014).

R. Castagne, A. Vapaille, Description of the SiO2-Si interface properties by means of very low frequency MOS capacitance measurements, Surf. Sci. 28, 157-193 (1971).

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 351-355

doi: 10.4028/p-dd26nr

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-23

Revised:
2022-02-21

Accepted:
2022-03-07

Online:
2022-05-31

Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

Yafei Liu , Hongyu Peng , Zeyu Chen , Qianyu Cheng , Shanshan Hu , Balaji Raghothamachar , Michael Dudley , Ramon Collazo , Zlatko Sitar , James Tweedie , Michal Bockowski , Vincent Meyers , F. Shadi Shahedipour-Sandvik , Bingjun Li and Jung Han

Department of Materials Science and Chemical Engineering, Stony Brook University, Stony Brook, NY 11794, USA

Department of Materials Science & Engineering, North Carolina State University, Raleigh, NC 27695, USA

Adroit Materials, Inc., 2054 Kildaire Farm Road, Suite 205, Cary, NC 27518

Institute of High Pressure Physics Polish Academy of Sciences, Sokolowska 29/37, 01-142 Warsaw, Poland

SUNY Polytechnic Institute, Albany, NY 12203, USA

Department of Electrical Engineering, Yale University, New Haven, CT 06511, USA

yafei.liu@stonybrook.edu, hongyu.peng@stonybrook.edu, zeyu.chen@stonybrook.edu, qianyu.cheng@stonybrook.edu, shanshan.hu@stonybrook.edu, balaji.raghothamachar@stonybrook.edu, michael.dudley@stonybrook.edu, collazo@ncsu.edu, sitar@ncsu.edu, james@adroitmaterials.com, bocian@unipress.waw.pl, sshahedipour-sandvik@sunypoly.edu, nbingjun.li@yale.edu, ojung.han@yale.edu

Keywords: Gallium nitride; X-ray topography; Power electronics; Substrates; Selective area doping; Ion implantation; Etching and regrowth.

Abstract

Synchrotron X-ray topography techniques are used to characterize the microstructures in gallium nitride materials being developed for selective area doping for power electronic applications. Bulk substrates grown by different methods, epitaxial layers that are subject to ion implantation, annealing, etching and regrowth are characterized by X-ray topography in grazing incidence geometry and X-ray rocking curve topography. Strain and tilt maps of ion implanted epitaxial layers and etched and regrown wafers are generated. From the X-ray topographs, it is concluded that ammonothermal grown substrates show the highest quality among other types and most suitable for high-end electronic applications. It is also revealed that epitaxial growth, ion implantation and the annealing process do not change the dislocation distribution, but ion implantation introduces damage, strain and lattice bending effect, which are removed after annealing. Inductively coupled plasma (ICP) etching gives rise to strain variations in the wafer, while using tertiary butyl chloride (TBCl) to etch the wafer does not affect the strain distribution and can remove some damage from a preceding ICP etching process.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

Gallium nitride ( GaN ) is one of the most promising wide band gap semiconductor materials that can replace silicon in the applications of power electronic devices as the latter has nearly reached its performance limits. However, the performance of the GaN based power devices is limited by the availability of high-quality GaN substrates and reliable selective area doping techniques.

Several bulk growth techniques for GaN have been developed including ammonothermal growth [1] and hydride vapor phase epitaxy (HVPE) [2]. A patterned HVPE method [3] has also been developed to lower the dislocation density. Selective area doping techniques are critical to the fabrication of vertical GaN-based power electronic devices. Ion implantation is a very common
doping technique that can be used for selective area doping. To remove the damage induced by ion implantation and activate the implanted atoms, several annealing methods have been developed for GaN materials, including AlN capped annealing [4], high pressure annealing [5] and a combination of both under non-equilibrium annealing conditions [6]. Selective area etching and regrowth is another method to realize the device structures on GaN materials. Different etching methods have been deployed including inductively coupled plasma (ICP) etching [7] and tertiary butyl chloride (TBCl) etching [8].

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

Table 1 lists the samples that are characterized by synchrotron X-ray topography. Synchrotron monochromatic beam X-ray topography (SMBXT) [9] ( ) and synchrotron X-ray rocking curve topography (SXRCT) [10] ( ) are both conducted at beamline 1-BM of Advanced Photon Source (APS) in Argonne National Laboratory (ANL).

Table 1. Sample list and descriptions

Sample type
#
Description

GaN
substrates
1
Ammonothermal grown substrate

2
Patterned HVPE grown substrate

3
Regular HVPE grown substrate

Epitaxial
growth,
implantation
and annealing
4
Sequentially studied at substrate (grown by ammonothermal method), MOCVD grown epitaxial layer (1 μm), Mg ion implanted, and high pressure annealed (1 GPa, 1440°C, 10 min)

5
Mg/N co-implanted epitaxial layer on ammonothermal grown substrate

6
AlN capped, annealed 1225°C, 2 min, same implantation process as sample 5

7
Continuously grown without etching process on HVPE wafer

Etching and
regrowth
8
ICP etched and regrown on HVPE wafer

9
TBCl etched and regrown on HVPE wafer

10
ICP and TBCl etched and regrown on HVPE wafer

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

GaN Substrates. SMBXT characterization of different types of GaN substrates has been conducted [11-13]. Figure 1 includes the magnified topographs of the GaN substrates grown by ammonothermal method, patterned HVPE method and regular HVPE method. The contrast of white dots in the topographs is identified as threading dislocations, while the curved line contrast represents basal plane dislocations (BPDs). For the ammonothermal grown substrate shown in Figure 1 (a), the overall dislocation density is calculated as , which indicated a very high quality of the GaN substrate. No BPDs are observed in the ammonothermal GaN substrate. In the patterned HVPE GaN substrate shown in Figure 1 (b), large areas with low dislocation densities below are observed between a grid of strain centers with relatively higher threading dislocation densities larger than . BPDs are also observed around strain centers, with a density larger than . In Figure 1 (c), it is noted that not many individual dislocations can be resolved, which means that the dislocation density is in the range of . The threading dislocations, especially screw types, are found responsible in degradation of reverse bias current leakage [14, 15], which can be challenging for highend power electronic device fabrication.

Figure 1. SMBXT images ( ) of bulk GaN substrate grown by (a) ammonothermal method, (b) patterned HVPE method, and (c) regular HVPE method.

Figure 1. Figure 1. SMBXT images ( ) of bulk GaN substrate grown by (a) ammonothermal method, (b) patterned HVPE method, and (c) regular HVPE method.

Epitaxial Growth, Ion Implantation, and Annealing. SMBXT and SXRCT analysis of changes in microstructures during epitaxial growth, ion implantation and different annealing techniques has been conducted [16, 17]. Figure 2 shows the overall SMBXT images of

Figure 2. SMBXT images ( ) of sample 4 in the stage of (a) bare substrate, (b) epitaxial wafer, (c) asimplanted wafer, and (d) annealed wafer.

Figure 2. Figure 2. SMBXT images ( ) of sample 4 in the stage of (a) bare substrate, (b) epitaxial wafer, (c) asimplanted wafer, and (d) annealed wafer.

sample 4 at different processing stages. Both the overall topography images of the bare substrate and epitaxial wafer have only one contour, which indicates very low lattice bending levels. The estimated radius of curvature is larger than 97 m . However, in Figure 2 (c), consisting of pieces of the as-implanted wafer, multiple contours obtained by rocking the sample are needed to cover the wafer area, and the radius of curvature of the wafer is calculated as only 9.7 m . This is due to the insertion of the implanted atoms during the ion implantation process, which causes higher lattice distortions. After high pressure annealing for the piece of the GaN wafer in the middle, it is revealed that the lattice bending level is restored to the original level due to appearance of single contour in the image. This result indicates that the high-pressure annealing process can successfully remove the lattice bending effect by incorporation of the dopant atoms from interstitial sites to substitutional sites in the crystal. Enlarged SMBXT images in Figure 4 show that the threading dislocation distribution remains the same during epitaxial growth, ion implantation, and the subsequent high pressure annealing process ((a), (b), and (c) are from the same region on the wafer, but (d) shows another area of the wafer). The enlargement of dislocation contrast after epitaxial growth is due to the interaction between threading dislocations and the vacancies, by which helical dislocations are formed [18].

Figure 3. (a) Strain map of sample 5; (b) Tilt map sample 5; (c) Strain map of sample 6; (d) Tilt map of sample 6. Note: The pattern of round shapes is for the testing purpose and not microstructure related.

Figure 3. Figure 3. (a) Strain map of sample 5; (b) Tilt map sample 5; (c) Strain map of sample 6; (d) Tilt map of sample 6. Note: The pattern of round shapes is for the testing purpose and not microstructure related.

Figure 4 shows the strain and tilt maps of sample 5 and sample 6 extracted from 0004 rocking curve topographs recorded in 0 and 180 positions. The strain values on the asimplanted wafer ranges from to 0 , and the tilt ranges from to . For the annealed sample, the strain ranges from to , which is similar to the as-

Figure 4. Magnified SMBXT images of sample 4.

Figure 4. Figure 4. Magnified SMBXT images of sample 4.

implanted wafer. However, the tilt range of the annealed wafer is only from -1 arcsecond to 0.5 arcsecond, which is significantly decreased compared to that of the as-implanted wafer. This means that the capped annealing process modifies the lattice strain uniformly across the wafer. The lattice bending effect is also lowered by the annealing process.

Figure 5. (a)-(d) Strain maps of sample 7 to sample 10.

Figure 5. Figure 5. (a)-(d) Strain maps of sample 7 to sample 10.

Figure 6. (a)-(d) Tilt maps of sample 7 to sample 10.

Figure 6. Figure 6. (a)-(d) Tilt maps of sample 7 to sample 10.

Table 2. Strain and tilt ranges of sample 7 to sample 10 from the strain and tilt maps.

# | Description | Strain range | Tilt range
7 | Continuously grown | 4×10⁻⁵ | 230"
8 | ICP etched | 1.6×10⁻⁴ | 300"
9 | TBCl etched | 2.5×10⁻⁵ | 160"
10 | ICP and TBCl etched | 6×10⁻⁵ | 115"

Etching and regrowth. Strain and tilt maps of the etched and regrown samples are plotted out of the SXRCT data. Table 2 summarizes the strain and tilt ranges in the maps in Figure 5 and Figure 6. It can be noted that the ICP etched and regrown sample has a strain range of , while that of the other samples are in the order of . This indicates that the ICP etching process can cause some non-uniform lattice damage to the wafer due to the ion bombardment. The TBCl etched sample, on the other hand, has the smallest strain range. This is because the TBCl etching process does not involve reactive ion bombardment on to the sample. By comparing the strain ranges of ICP etched wafer and the ICP + TBCl etched wafer, it can also be noted that the TBCl etching can recover some of the damage from the ICP process by removing some of the severely damaged layers from the surface. For the tilt ranges of the samples, it should be noted that the imaged regions for sample 9 and sample 10 are smaller. Therefore, the tilt ranges of all the samples are similar, which means that the tilt level is not affected by the different etching processes adopted.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

Synchrotron X-ray topography techniques including SMBXT and SXRCT are adopted to characterize the microstructure of GaN materials for power electronic applications. Ammonothermal grown substrate is found to have the best quality and most promising in high-end power electronic applications. Epitaxial growth, ion implantation and subsequent annealing do not change the dislocation distribution in the wafer, but lattice damage and strain is induced by ion implantation and removed by both high-pressure annealing and capped annealing as revealed by both SMBXT and SXRCT. Furthermore, different etching techniques including ICP, TBCI, and a combination of ICP and TBCl are compared by SXRCT. It is concluded that ICP etching gives rise to enhanced strain by ion bombardment, while using TBCl does not cause damage to the material and can actually recover some damage from a preceding ICP etching process.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

This work is supported by ARPA-E through PNDIODES program (DE-AR0001115, directed by I. Kizilyalli). Topography data was recorded using the resources of the Advanced Photon Source (Beamline 1-BM), a U.S. DOE Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under contract no. DE-AC02-06CH11357. Joint Photon Sciences Institute at Stony Brook University provided partial support for travel and subsistence at the Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.351.pdf

R. Dwiliński, et al., Journal of Crystal Growth 311 (2009) 3015-3018.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 356-360

doi: 10.4028/p-u7m9jr

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-25

Revised:
2022-02-08

Accepted:
2022-03-07

Online:
2022-05-31

Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

Hongyu Peng , Zeyu Chen , Yafei Liu , Qianyu Cheng , Shanshan Hu , Xianrong Huang , Lahsen Assoufid , Balaji Raghothamachar and Michael Dudley

¹Materials Science and Chemical Engineering, Stony Brook University, Stony Brook, New York, 11794, USA

Advanced Photon Source, Argonne National Laboratory, Lemont, Illinois, 60439, USA

hongyu.peng@stonybrook.edu, zeyu.chen@stonybrook.edu, yafei.liu@stonybrook.edu, qianyu.cheng@stonybrook.edu, shanshan.hu@stonybrook.edu, xiahuang@anl.gov, assoufid@anl.gov, balaji.raghothamachar@stonybrook.edu and michael.dudley@stonybrook.edu

Keywords: X-ray Topography, Weak Beam Topography, Dislocation Contrast

Abstract

Synchrotron monochromatic beam X-ray topography has been widely applied to characterize structural defects in SiC crystals. Using ray tracing simulations, the dislocation contrast in X-ray topography under strong diffraction conditions (diffraction takes place at or near Bragg angle) has been intensively investigated. However, the contrast and the configurations of the dislocation images recorded under weak diffraction conditions have not been fully investigated. Recently, we demonstrated that the contrast of dislocations in synchrotron grazing incidence topography under weak diffraction conditions can also be analyzed and interpreted by applying ray tracing principles. In this study, we have extended the application of the ray tracing method to analyze the dislocation contrast in weak beam synchrotron back reflection and rocking curve topography. The ray tracing method is shown to successfully simulate and correlate the contrast of threading screw dislocations at various positions on the rocking curve and thus allow to determine the signs of Burgers vectors.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

Synchrotron X-ray topography (SXRT) is a non-destructive technique that images structural defects (dislocations, stacking faults, grain boundaries, etc.) in bulk crystals, epitaxial films and wafers fabricated for electronic devices [1-5]. Compared to synchrotron white beam XRT, synchrotron monochromatic beam XRT (SMBXT) shows better defect contrast due to its superior strain sensitivity and signal to noise ratio [6]. In SMBXT (for example grazing incidence topography, back reflection topography and rocking curve topography [7-9]), Bragg contours will typically be formed due to the presence of lattice bending, and the intensity profile across such contours tracks the rocking curve of the crystal. Intensive investigations have been carried out on the dislocation contrast in SMBXT when the diffraction takes place at or near the Bragg angle [6,8,9]. However, the contrast of the dislocations under weak diffraction conditions (i.e. off Bragg contour) reveals additional information since it is more sensitive to the local lattice distortion [7]. Therefore, the understanding of the dislocation contrast in weak beam synchrotron X-ray topography is of great interest.

We have previously reported the dislocation contrast in grazing incidence topography (GIT), and it has been demonstrated that the contrast features under weak diffraction conditions can be described by the orientation contrast mechanism and simulated using the ray tracing method [7]. In this work, the contrast of the dislocations in weak beam synchrotron X-ray back reflection topography and rocking curve topography (RCT) will be presented. Threading screw/mixed dislocations
(TSDs/TMDs) with opposite sign of Burgers vector show different contrast features when they are observed off-contour in back reflection topographs, while previous work has shown that TSDs/TMDs always show circular white contrast in back reflection topographs when they are on-contour, irrespective of sign [6]. Moreover, in synchrotron X-ray RCT, where a beam conditioner is used, the contrast of TSDs/TMDs is more sensitive to the diffraction conditions as the rocking curve width is much narrower. As a result, the contrast of TSDs/TMDs with opposite sign of Burgers vector is dramatically different.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

The samples studied in back reflection and RCT are (0001) with and offcut towards respectively. The images in back reflection geometry were recorded using the 000,12 reflection at an energy of 7.5 keV at 33-BM at the Advanced Photon Source (APS) in Argonne National Laboratory, while the 0008 reflection was used in RCT at 1-BM at the APS at an energy of 8 keV .

In back reflection geometry, the monochromator is a double-bounce and the full width at half maximum (FWHM) of reflection is calculated to be according to the DuMond diagram [10]. But the FWHM of reflection in RCT is only around since a Si 331 beam conditioner is used in between the sample and the double-bounce Si (111), whose Darwin width is only around calculated from dynamical theory of X-ray diffraction.

To investigate the contrast of the dislocations and determine their Burgers vectors, ray tracing simulations are used in the present work [11], a technique which is originally developed based on the orientation contrast mechanism. In the simulation, the direction of the diffracted X-rays is calculated based on the normal of local diffraction planes, which can be distorted due to the presence of the dislocation. Projecting the diffracted X-rays onto the recording plate as dots, the image of the dislocation is simulated. Moreover, the incident angle is modified based on the location of the dislocation on the contour and the intensity of each dot is described by a simplified rocking curve of the crystal [7], both of which play a key role in the formation of the contrast in weak beam topography.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

As mentioned in previous section, the intensity profile across the contour in SMBXT tracks the rocking curve of the crystal [7]. Different locations (i.e. different intensities) on the contour represent different incident angles. When the angle is slightly off the Bragg angle, the diffracted intensity will decrease and the contrast on the topograph will be reduced/whiter. A schematic of SiC 000, 12 rocking curve is shown in Fig. 1 (a) and nine different diffraction conditions are marked from 'a' to ' ', where position ' ' is the perfect Bragg condition. On the left side of ' ', the incident angle is smaller than Bragg angle (in the experiment, this is caused by the presence of lattice bending), and on the right, the angle is bigger than Bragg angle.

The simulated images of threading screw dislocations (TSDs) under those diffraction conditions are shown in Fig. 1 (b). The Burgers vectors of the dislocation in the first row is right-hand screw while left-hand screw is shown in the second row. It is clear that under strong diffraction condition, 'e', contrast of TSDs with opposite signs of Burgers vectors are indistinguishable. However, the difference between threading right-hand screw dislocation (TRSD) and threading left-hand screw dislocation (TLSD) can be discerned if the incident angle deviates from perfect Bragg angle. Taking diffraction condition 'a' for example, the TRSD shows darker contrast bordering the top right of the white contrast circle while the darker contrast appears to the bottom right for a TLSD (Fig. 1 (b)). Based upon this difference, the sign of Burgers vector can thus be determined in weak beam synchrotron X-ray back reflection topography.

As shown in Fig. 1 (c), the dislocations show circular white contrast in regular on-contour topograph (as marked by the white box). But the contrast of the dislocation gradually changes if moving towards the left side of the contour (as the lattice curvature is concave, the left side of the contour corresponds to the right side of the rocking curve). The two dislocations in the bottom marked by dark boxes have opposite sign of Burgers vectors as the dark contrast of TRSD appears in the bottom left while the dark contrast of TLSD shows on the top left in the boxes, and they are labeled by ' ' and ' ' respectively. But on the right side of the contour (corresponds to the left side of the rocking curve), the dark contrast of TRSD is on the top right while TLSD shows dark contrast in the bottom right in the dark boxes in Fig. 1 (c). Therefore, the sign of Burgers vector that can not be determined in previous on-contour back reflection topography can now be characterized in weak beam synchrotron back reflection topography.

Figure 1. (a) Simplified rocking curve of in 000,12 back reflection geometry. Nine different diffraction conditions from 'a' to 'i' are marked, where 'e' indicates perfect Bragg condition. (b) Ray tracing simulated image of threading right-hand screw dislocations (TRSD) and threading left-hand screw dislocations (TLSD) are shown in the first and second row, correspondingly to 'a' to 'i' diffraction conditions. Different diffraction conditions are considered. (c) 000, 12 Back reflection topograph of in weak diffraction conditions. Circular white features are threading screw dislocations (TSDs) and simulated images are placed on the right of the topographic images in the boxes. TRSDs are marked by ' ' while TLSDs are marked by 'L'. TSD marked by the white box is under strong diffraction condition.

Figure 1. Figure 1. (a) Simplified rocking curve of in 000,12 back reflection geometry. Nine different diffraction conditions from 'a' to 'i' are marked, where 'e' indicates perfect Bragg condition. (b) Ray tracing simulated image of threading right-hand screw dislocations (TRSD) and threading left-hand screw dislocations (TLSD) are shown in the first and second row, correspondingly to 'a' to 'i' diffraction conditions. Different diffraction conditions are considered. (c) 000, 12 Back reflection topograph of in weak diffraction conditions. Circular white features are threading screw dislocations (TSDs) and simulated images are placed on the right of the topographic images in the boxes. TRSDs are marked by ' ' while TLSDs are marked by 'L'. TSD marked by the white box is under strong diffraction condition.

Figure 2. rocking curve topographs of the same region. Five different diffraction conditions are noted by the (the angle between the incident X-ray and local diffraction plane) and Bragg angle . The variation of the dislocation contrast is shown in (a), (b), (c), (d) and (e) as the diffraction condition changes from rad to rad. Ray tracing simulated image is placed alongside the topographic image in the box.

Figure 2. Figure 2. rocking curve topographs of the same region. Five different diffraction conditions are noted by the (the angle between the incident X-ray and local diffraction plane) and Bragg angle . The variation of the dislocation contrast is shown in (a), (b), (c), (d) and (e) as the diffraction condition changes from rad to rad. Ray tracing simulated image is placed alongside the topographic image in the box.

In addition to the contrast variations in back reflection topographs, we also observed changes of the contrast in synchrotron X-ray RCT. As the FWHM of 4H-SiC 0008 reflection in RCT is only around 2.4", the contrast of the dislocations is much more sensitive to the diffraction conditions. Consequently, the sign of Burgers vector can be determined even using regular on-contour topographs. As shown in Fig. 2 (b) & (c), the diffraction condition is close to the perfect Bragg condition and the TSDs marked by the boxes have opposite sign of Burgers vector. More importantly, the contrast of the dislocation dramatically changes as the angle between the incident X-ray and local diffraction plane changes. As shown in Fig. 2 (a), rad, the white contrast 'fan' appears on the left if the dislocation is TLSD, while the white contrast is on the right for TRSD. Rocking the sample by , the white contrast becomes smaller for both TRSD and TLSD. As the sample continues to be rocked until (Fig. 2 (e)), the white contrast 'fan' becomes bigger on the right side of TLSD and to the left side of TRSD. Ray tracing simulated images placed alongside the topographic images correlate well, indicating that the contrast can be well described by orientation contrast mechanism.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

4H-SiC dislocation contrast in weak beam synchrotron back reflection topography and RCT has been investigated in this study. The sign of Burgers vector can be determined in weak beam back reflection topograph and RCT using ray tracing simulations. The contrast of TSDs is observed to gradually change as the angle between the local diffraction plane and the incident beam changes. All these topographic images in weak beam topography can be simulated using ray-tracing method, indicating that under weak diffraction conditions, orientation contrast mechanism significantly contributes to the formation of the dislocation contrast.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE-AR0001028. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. This research used resources of the Advanced Photon Source (Beamline 1-BM). The Joint Photon Sciences Institute at Stony Brook University provided partial support for travel and subsistence at the Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.356.pdf

B. K. Tanner, D. K. Bowen, Synchrotron X-radiation topography, Mater. Sci. Rep. 8 (1992) 369-407

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X. R. Huang, M. Dudley, W. M. Vetter, W. Huang, W. Si, C. H. Carter Jr, J. Appl. Cryst. (1999). 32, 516-524

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 361-365

doi: 10.4028/p-m7sftq

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

Zeyu Chen , Hongyu Peng , Yafei Liu , Qianyu Cheng , Shanshan Hu , Balaji Raghothamachar , Michael Dudley , Reza Ghandi , Stacey Kennerly and Peter Thieberger

Department of Materials Science and Engineering, Stony Brook University, Stony Brook, 11794, NY, USA

GE Research, Niskayuna, NY, 12309, USA

Brookhaven National Laboratory, Upton, NY, 11973, USA

a*Zeyu.chen@stonybrook.edu, Hongyu.peng@stonybrook.edu, Yafei.liu@stonybrook.edu, Qianyu.cheng@stonybrook.edu, Shanshan.hu@stonybrook.edu,

Balaji.Raghothamachar@stonybrook.edu, Michael.dudley@stonybrook.edu, ghandi@ge.com,

Keywords: 4H-SiC, Ion Implantation, Lattice Strain, Synchrotron X-ray Rocking Curve Topography

Abstract

H -SiC wafers with epilayer were implanted at the Tandem Van de Graaff facility at Brookhaven National Laboratory with tunable energy from 13 MeV up to 66 MeV . Lattice strains introduced by the implantation process were characterized in detail by synchrotron rocking curve Xray topography (SXRCT) and reciprocal space maps (RSMs). It is observed that the strain levels correlate with the atomic mass and energy of acceleration of the dopant atoms.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

Silicon Carbide (SiC) is a promising semiconductor for future power devices due to its wide bandgap, high breakdown voltage and good thermal stability [1]. High voltage 4H-SiC devices are demanded for realization of hybrid aircraft and intelligent power systems. Tao Liu and coworkers have provided a theoretical model describing that deeper junction could enhance the breakdown voltage of the device [2]. Such superjunction 4 H -SiC devices with thick epilayers up to and deep junctions are therefore, being developed for high voltage ( 1.7 to 6.5 kV ) applications. Due to the limitation of diffusion in [3], multi-step ion implantation is an optimized solution for selective doping. Depth of the junction is limited to around by conventional ion implantation since energy range to few hundred keVs is utilized [4,5]. Therefore, higher energy needs to be employed to form deep junctions. A novel multi-step high energy implantation system, allowing adjustable energy to 66 MeV , has been developed at Brookhaven National Laboratory's Tandem Van de Graaff accelerator facility [6]. Ghandi and coworkers have successfully fabricated medium voltage device with deep junction via this implantation system [7]. Ion implantation usually induces lattice strains in the SiC wafers by displacing the Si and C atoms. To comprehensively study the effect of implantation, lattice strain should be characterized in detail. C Jiang and coworkers have indicated observation of tensile strain from Xe implanted 4H-SiC by high resolution X-ray diffraction (HRXRD) [8]. Amigou and coworkers show that tensile strain also exist in N implanted 4H-SiC [9]. In this paper, extent of lattice strain of high energy Al or N implanted are characterized by reciprocal space map (RSM) and synchrotron X-ray rocking curve topography (SXRCT). SXRCT has previously been successfully applied to highly sensitive strain measurement of wafers [10,11,12].

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

For the present experiments, two wafers with epilayer were separately implanted with Al and N atoms on two different wafers at Brookhaven National Laboratory's newly developed
multi-step high energy implantation system without annealing process. Energy ranging up to 42.99 MeV were used for N implantation, while ions with energy range of 13.8 to 65.7 MeV were employed for Al implantation. Total fluence of both implantation is . Sample 1 was implanted in square patterns using masks with regions between the squares unimplanted, while sample 2 was implanted with a mask covering one of the corners. The implanted samples were characterized by SXRCT at Beamline 1-BM at the Advanced Photon Source (APS), Argonne National Laboratory. A double crystal setup was used, where beam conditioner, following the double crystal monochromator, acts as the first crystal and in ( 0008 ) reflection is the second one. The samples were rocked about the [ ] direction in steps of 4 microradian ( ) to image the whole sample. Strain and tilt in the samples could be extracted individually by recording two series of images in and positions about the ( 0008 ) plane normal. Topographs were assembled by stacking the highest intensities of individual images captured by a high resolution CCD camera system with a field of view of and a pixel size of . As described in previous works [10,13], strain and tilt information can be deconvoluted. 0008 RSMs were generated on a Bede D1 diffractometer with . A channel-cut analyzer was placed in front of the detector.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

Fig 1. shows 0008 reflection topographs of N implanted sample 1 and Al implanted sample 2. White contrast areas are from lead pieces used for reference purposes. The square outlines of implanted regions of sample 1 are distorted to rectangles in topograph since the diffracted beam is not exactly perpendicular to the CCD detector. Topograph from Sample 2 includes a section at the bottom right that was not implanted and therefore shows a broader contour pattern than the implanted region due to lower lattice distortion. Contours in topograph of sample 1 are broader than sample 2, indicating the extent of lattice distortion in sample 1 is lower. Within the contours, threading dislocations (TDs) are visible as white contrast dots some of which are highlighted by yellow boxes.

Figure 1. Topographs of (a) N implanted sample 1 (b) Al implanted sample 2 (nonuniformity of contours in white box is from the scratches)

Figure 1. Figure 1. Topographs of (a) N implanted sample 1 (b) Al implanted sample 2 (nonuniformity of contours in white box is from the scratches)

To quantify the lattice strain, strain maps were derived from SXRCT via MATLAB using unimplanted region as reference point. Fig. 2 reveals the strain maps, RSMs of sample 1 and 2, and SRIM simulations. The strain map of sample 1 illustrates a strain level of . Moreover, strain in the implanted regions is slightly tensile compared to the adjacent unimplanted regions. On the other hand, strain level of implanted region of sample 2 is 1.5 to , which is almost 20 times larger
than that of sample 1. In addition, RSM of sample 1 reveals a single peak while RSM of sample 2 shows one main peak with a satellite peak lying on the bottom right. Therefore, a significant tensile strain exists in the implanted region of sample 2. The results from the strain map thus strongly correlate with the results from RSMs and reflect higher damage in sample 2 compared to sample 1.

During ion implantation, heavier dopant atoms require higher stopping energy, which is associated with displacement of Si and C atoms that results in lattice strain. Since aluminum is a heavier element than nitrogen, the damage or strain introduced by aluminum implantation is therefore larger. Damage simulations of whole energy spectrum of nitrogen and aluminum implantation via SRIM 2008 [14] has been performed. Fig. 2 (e) shows displacement per atom (dpa) versus depth profile for each implantation process. The damage is nearly uniform from surface to the planned depth of . Overall, Al ions introduce dpa of order of to the sample, which is almost 3 times higher than damage created by N ions. This difference could be attributed to difference in thickness of the Al foil that is used to increase the energy spread of the beam, energy of acceleration and atomic mass. The maximum energy of acceleration and atomic mass of Al ions are much larger than those of N ions. Besides, since the Al foil used in Al implantation is much thinner, the kinetic energy of Al ions could be larger after ions penetrated the Al foil. As a consequence, dpa created by Al implantation is more significant, which leads to a higher extent of strain in the Al implanted sample, as measured from the strain maps and RSMs.

Figure 2. (a) Strain map of sample 1 (b) Strain map of sample 2 (c) RSM of implanted region of sample 1 (d) RSM of implanted region of sample 2 (e) SRIM damage simulation of sample 1 and 2 (Note: SRIM simulations account for transmission of beam through foil (Al implantation) and foil (N implantation) [6])

Figure 2. Figure 2. (a) Strain map of sample 1 (b) Strain map of sample 2 (c) RSM of implanted region of sample 1 (d) RSM of implanted region of sample 2 (e) SRIM damage simulation of sample 1 and 2 (Note: SRIM simulations account for transmission of beam through foil (Al implantation) and foil (N implantation) [6])

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

4H-SiC wafers with epilayer, subject to high energy ion implantation by N or Al atoms at the Brookhaven National Laboratory's Tandem Van de Graaff accelerator facility, have been characterized by SXRCT and RSMs to comprehensively study the nature of lattice damage caused by implantation. Strain maps derived from SXRCT and RSMs indicate higher levels of strain in aluminum implanted wafers compared to nitrogen implanted ones. The higher atomic mass of Al and the higher maximum energy for implantation that caused higher dpa as shown by the SRIM simulations results in higher levels of strain.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

Samples provided by GE Research. The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DE-AR0001028. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

BNL Work supported by the U.S. Department of Energy, Office of Science, under Contract No. DE[1]SC0012704

This research used resources of the Advanced Photon Source, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.361.pdf

J.A.Cooper and A. Agarwal, SiC power-switching devices-the second electronics revolution?, Proceedings of IEEE, 90(6), p. 956 (2002).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 366-370

doi: 10.4028/p-2kzz01

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-15

Accepted:
2022-03-07

Online:
2022-05-31

Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

Qianyu Cheng , Hongyu Peng , Shanshan Hu , Zeyu Chen , Yafei Liu , Balaji Raghothamachar and Michael Dudley

¹Department of Materials Science and Chemical Engineering, Stony Brook University, Stony Brook, NY, USA

qianyu.cheng@stonybrook.edu, hongyu.peng@stonybrook.edu, shanshan.hu@stonybrook.edu, zeyu.chen@stonybrook.edu, yafei.liu@stonybrook.edu, balaji.raghothamachar@stonybrook.edu, michael.dudley@stonybrook.edu

Keywords: 4 H -SiC, X-ray topography, ray-tracing simulation, penetration depth

Abstract

Understanding the depth from which contrast from dislocations is still discernible (the effective penetration depth of the X-rays) in grazing-incidence synchrotron monochromatic beam Xray topography is of great interest as it enables three-dimensional dislocation configuration analysis and accurate density calculations. To this end, systematic analysis has been performed of topographic and ray-tracing simulated contrast of basal plane dislocations with different Burgers vector and line direction combinations, and a universal method to determine the effective penetration depth based on ray tracing has been developed. This study reveals that the observable dislocation contrast depends on the effective misorientation associated with the dislocation modulated by the photoelectric absorption effect. The dislocations with larger effective misorientation tend to have longer projected length and correspondingly deeper effective penetration depths.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

Synchrotron X-ray topography (XRT) in the grazing incidence geometry is commonly employed for detailed analysis of dislocation configurations and density calculations in off-axis (0001) 4HSiC wafers [1]. In this geometry, information on defects from within the effective penetration depth is exclusively revealed. Therefore, it is essential to establish a procedure to define this effective penetration depth. Dudley, et al. used the projected lengths of dislocation images on reflection topographs recorded from in a Si crystal to determine the effective penetration depth [2]. It was concluded that photoelectric absorption rather than extinction limited the observed penetration depths. This was found to be consistent with the direct image contrast formation mechanism i.e. wherein diffracted X-rays emanating from the distorted regions surrounding the dislocation (which contribute to the image) diffract kinematically and, as such, do not undergo extinction but rather just photoelectric absorption [3]. Huang, et al. showed that pure orientation contrast [4], using the ray tracing technique enabled much more accurate simulations of defect images [5]. Ishiji, et al. estimated the penetration depth based on the photoelectric absorption experienced by the diffracted X-rays, thereby assuming that those rays did not undergo extinction but rather just absorption [6]. However, only basal plane dislocations (BPDs) with screw segments parallel to the off-cut [11 ]-direction were evaluated in that study and other BPDs types were not considered. Therefore, a universal method to determine the effective penetration depth for all dislocation types would be of more practical importance.

In this study, BPDs with different Burgers vector and line direction combinations in physical vapor transport (PVT) grown off-axis crystals have been investigated by synchrotron X-ray grazing-incidence topography in reflection and accompanying ray-tracing simulations [5] incorporating the effects of surface relaxation [7] and absorption [8, 9]. This ray tracing simulation technique is developed based on the mechanism of orientation contrast [4], where the direction of local diffracted X-ray beams is calculated. By projecting the diffracted X-rays onto the recording
plate, the image of the dislocation is simulated. The misorientation associated with the presence of a dislocation is therefore revealed as contrast differences on the image due to the superimposition or separation of diffracted X-rays.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

PVT-grown, off-axis substrate wafers are characterized by synchrotron monochromatic X-ray in grazing-incidence geometry. The images were recorded from the Si-face using the reflection at an energy of 8.99 keV at Beamline I-BM of the Advanced Photon Source (APS) at Argonne National Laboratory (ANL). The contrast of BPDs with different combinations of Burgers vectors and line directions was also investigated through ray-tracing simulations. The gray value intensities for both topographic and simulated dislocation contrasts were measured using ImageJ [10]. The length of the dislocation is measured from the end of the contrast feature observed at the surface intersection down to the position where the gray value intensity of the dislocation contrast decreases to 1/10 of the maximum (slightly different procedure from Ishiji [6]).

In this paper, we assume that the rays contributing to the dislocation image in the ray tracing simulations do not experience extinction but only absorption. We then carry out ray tracing simulations at different depths below the surface subjecting each such set of diffracted beams to photoelectric absorption. This is repeated until the dislocation contrast is no longer discernible. Subsequently, all these images from different depths below the surface are stacked upon each other to generate the full simulated dislocation image [8, 9], which is then compared to the observed images to determine the Burgers vectors and effective penetration depth.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

As shown in Fig. 1, the effective penetration depth can be calculated based on the observable dislocation contrast in the topograph by , where the projected length L of each dislocation is measured along the off-cut direction of its observable length

Fig. 1: Schematic diagram of off-axis . The orange line is a dislocation on the basal plane lying at an arbitrary angle. The dashed orange line represents the observable length of the dislocation on the topograph, and its projected length along off-cut direction is .

Fig. 1. Schematic diagram of off-axis . The orange line is a dislocation on the basal plane lying at an arbitrary angle. The dashed orange line represents the observable length of the dislocation on the topograph, and its projected length along off-cut direction is .

Figure 2 shows four sets of topographic and simulated images of BPDs with different Burgers vector and line direction combinations. The projected lengths measured from each topographic BPD are (from longest to shortest) (Fig. 2(a)); (Fig. 2(b)); (Fig. 2(c)); (Fig. 2(d)), corresponding to effective penetration depths of , and
, respectively. The Burgers vectors of these dislocations determined by comparing with raytracing simulations, are , and , respectively. The line directions are measured with respect to their Burgers vectors, which makes them , , and (screw-type) BPD, respectively. Results clearly indicate that the effective penetration depth varies with the Burgers vector and line direction combination of a dislocation. This effective penetration depth analysis has been conducted for BPDs with all six types of Burgers vector as well as Frank type dislocations created through deflection of threading screw/mixed dislocations onto the basal plane. Those results will be discussed in detail elsewhere [11].

Fig. 2: Grazing-incidence X-ray topographs and corresponding ray-tracing simulation results of BPDs with characters of , screw-type BPD (d).

Fig. 2. Grazing-incidence X-ray topographs and corresponding ray-tracing simulation results of BPDs with characters of , screw-type BPD (d).

The effective penetration depths obtained through this ray-tracing simulation approach differ from the penetration depth calculated simply from photoelectric absorption according to Eq. 1:

where is the linear absorption coefficient, is the incident angle and is the exit angle with the surface. The calculated is for grazing-incidence topograph at an energy of 8.99 keV . The values calculated using ray tracing differ from this since the strength of the contrast from a dislocation depends on the magnitude of the misorientation and this varies with both line direction
and Burgers vector. The stronger the contrast the deeper the effective penetration depth since the starting intensity at the surface intersection is larger and therefore, a fixed value is insufficient.

While the most accurate and reliable results are found by using ray tracing procedure above, a more simplified model can assist the non-expert in assessing the penetration depth. Since the maximum contrast from a given dislocation is proportional to the local effective misorientation, a measure of this strength can be obtained from an approximate expression for the effective misorientation as contributed by both the screw and edge components of a dislocation as in Eqs. 2-4:

where is the diffraction vector, is the Burgers vector, is the line direction, and and represent the screw and edge components of the Burgers vector, respectively. , and are factors calculated based on the lattice displacement of screw and edge dislocation given by Nabarro [12], and are and respectively ( : Poisson ratio). Detailed descriptions are provided in our upcoming publication [11]. The effective misorientation, , of the dislocations considered here are calculated to be , and 0.98 . The effective penetration depth can be estimated through Eq. 5,

where is a constant with an average value around 0.87 . For the BPDs shown in Fig. 2, equation 5 yields values of of , and , respectively. These values are close to those yielded by the full ray tracing simulation approach , and ).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

The effective penetration depth of dislocations in grazing-incidence monochromatic beam X-ray topographs in off-cut wafers is investigated in this study. BPDs with different Burgers vector and line direction combinations are quantitively analyzed in conjunction with ray-tracing simulation incorporating the effects of both surface relaxation and absorption. Analysis of the results indicates that the observable dislocation contrast depends on the effective misorientation associated with the dislocation modulated by the photoelectric absorption effect. As an alternative to the full ray tracing simulation approach, a more simplified factor based on an approximate expression for the effective misorientation (Eqs. 1, 2 and 5) can yield satisfactory results.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DEAR0001028. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof. Research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided additional support for travel and subsistence at the Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.366.pdf

B. Raghothamachar, M. Dudley, and G. Dhanaraj, X-ray topography techniques for defect characterization of crystals, in: G. Dhanaraj, K. Byrappa, V. Prasad, and M. Dudley (Eds.), Springer Handbook of Crystal Growth, Springer, Berlin, Heidelberg, 2010, pp. 1425-1451.

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K. Ishiji, S. Kawado, Y. Hirai, and S. Nagamachi, Jpn. J. Appl. Phys. 56 (2017) 106601.

H. Peng, T. Ailihumaer, F. Fujie, Z. Chen, B. Raghothamachar, and M. Dudley, J. Appl. Cryst. 54 (2021) 439-443.

F. Fujie, H. Peng, T. Ailihumaer, B. Raghothamachar, M. Dudley, S. Harada, M. Tagawa, and T. Ujihara, Acta Mater. 208 (2021) 116746.

T. Ailihumaer, H. Peng, F. Fujie, B. Raghothamachar, M. Dudley, S. Harada, and T. Ujihara, Mater. Sci. Eng.: B 271 (2021) 115281.

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Q. Cheng, H. Peng, S. Hu, Z. Chen, Y. Liu, B. Raghothamachar, and M. Dudley, to be submitted. [12]F. Nabarro, Theory of Crystal Dislocation, Dover ed., New York, 1987.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 371-375

doi: 10.4028/p-ryui6b

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-25

Revised:
2022-02-16

Accepted:
2022-03-17

Online:
2022-05-31

Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

The original version of this paper is available on https://www.scientific.net/MSF.1062.371.pdf

Marianne Etzelmüller Bathen , Robert Karsthof , Ulrike Grossner and Lasse Vines

¹Advanced Power Semiconductor Laboratory, ETH Zürich, 8092 Zürich, Switzerland

Department of Physics, University of Oslo, N-0316 Oslo, Norway

bathen@aps.ee.ethz.ch, r.m.karsthof@fys.uio.no, ulrike.grossner@ethz.ch,

*Corresponding author

Keywords: Point defects, deep level transient spectroscopy, silicon carbide, carbon interstitial, carbon antisite-vacancy pair

Abstract

Silicon carbide (SiC) is a wide band-gap semiconductor of great technological importance, showing promise for application areas ranging from quantum computing and communication to power devices. Vital in both the contexts of power devices and quantum technology is the understanding of intrinsic defects that are introduced during various device processing steps, both immediately after their formation and over the course of defect evolution with temperature. Here we monitor the formation and evolution of intrinsic point defects in n-type after proton irradiation at room temperature and subsequent annealing in the temperature range , and discuss the nature and origin of the and deep level defects observed by deep level transient spectroscopy around . In particular, the controversy on the nature of the trap in particular is addressed, where we propose the presence of two overlapping defect peaks: one metastable level that appears after low energy electron irradiation below the silicon displacement limit, and one more stable level that gradually decreases in concentration until an annealing temperature of . We argue that the former is likely related to carbon interstitials, while the latter was recently tentatively attributed to the carbon antisite-vacancy pair.

Introduction

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The carbon and silicon vacancies in ( and , respectively) have been studied intensively [1] on account of (i) their detrimental impact on minority carrier lifetime and hence device performance, particularly in the case of [2], and (ii) room temperature (RT) single-photon emission and spin manipulation for [3]. The latter characteristics, that are paramount for many quantum technology applications, have also been demonstrated for complexes of the fundamental vacancies including the divacancy , the carbon antisite-vacancy pair and the nitrogenvacancy complex [4].

The carbon antisite-vacancy (CAV) pair was predicted to be electrically active by density functional theory (DFT) calculations and having two sets of charge state transitions in the upper half of the band gap: ( ) at around and ( ) at around , with denoting the conduction band edge. Recently, the ( ) charge transition level (CTL) of the CAV pair was suggested to be responsible for the and levels often observed in deep level transient spectroscopy (DLTS) measurements of [6]. The splitting between the and peaks of about 0.1 eV was also predicted theoretically [5] and can be explained by a difference in CTL energy for the four different CAV configurations ( and ) caused by the inequivalent hexagonal and pseudo-cubic lattice sites in . Another recent work [7] employed photo-induced current transient spectroscopy (PICTS) and detected a level that was also assigned to the ( ) transition of the CAV complex, but due to the use of high purity semi insulating (HPSI) samples with Fermi levels near mid gap, different annealing behavior would be expected as compared to the n -type samples used in Ref. [6]. Nonetheless, an important controversy remains. In Ref. [6], the and trap

Fig. 1: DLTS spectra after 1.8 MeV proton irradiation to a fluence of and a post-anneal (black curves), followed by anneals at (red) and (blue). In (a) a standard lock-in weighting function and a 640 ms rate window were employed while (b) shows the corresponding high-resolution GS4 spectrum.

Fig. 1. DLTS spectra after 1.8 MeV proton irradiation to a fluence of and a post-anneal (black curves), followed by anneals at (red) and (blue). In (a) a standard lock-in weighting function and a 640 ms rate window were employed while (b) shows the corresponding high-resolution GS4 spectrum.

concentrations were reported to decrease steadily upon annealing at temperatures up to . Previous works [8] have reported the presence of in samples irradiated with electrons at low energies below the silicon displacement limit, and a lower annealing temperature than expected for a complex defect like the CAV pair, drawing the assignment of to the CAV pair into question.

In this contribution, we monitor the development of the resulting defect distribution after formation by proton irradiation and annealing up to . We pay particular attention to the and DLTS peaks that are often observed after irradiation of and discuss the possibility of more than one defect species being involved in their appearance. The metastability of the peak will also be discussed in this context.

Experimental Methods

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We introduce intrinsic defects in thick n-type ( N doped) 4H-SiC epitaxial layers ( ) using 1.8 MeV proton irradiation to a fluence of . The substrates were doped to approximately . All implantations were performed at room temperature and at an angle off with respect to the surface normal to avoid channeling effects. The implantation peak was situated at around leaving the defect distributions approximately uniform in the nearsurface region. The evolution of the resulting defect distributions is monitored after several annealing steps at . The heat treatments were performed in conventional tube furnace for 30 min in flow. Schottky barrier diodes (SBDs) were formed by depositing 150 nm thick circular contacts ( 1 mm diameter) of Ni by evaporation through a shadow mask.

The defect signatures were detected using deep level transient spectroscopy (DLTS). DLTS measurements were carried out for temperatures in the range using a measurement frequency of pulse length and 10 V pulse height at a reverse bias of -10 V . Six rate windows between 20 and 640 ms were chosen for evaluation of the transients, using both standard lock-in and GS4 correlation functions. The concentrations of the defect levels observed in the spectra were extracted using numerical simulation of the DLTS spectra based on assumed variable values for trap energy, density and capture cross-section. The correction was taken into account.

Results and Discussion

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The prevalent defects, measured by DLTS immediately after irradiation and a post-anneal to alleviate some of the implantation damage, are as shown in Fig. 1(a). In the figure the S1 and S2 (S-center), and levels can be clearly observed (along with the shoulder of ). The S -center and (and ) levels have previously been assigned to the [9] and [10] defects,

Fig. 2: DLTS spectra after 1.8 MeV proton irradiation to a fluence of and post-anneals at (a) , (b) and (c) . A high-resolution GS4 weighting function was employed (black solid curves) while the blue dotted curves show the cumulative sum of numerical simulations that are fitted to the spectra. Red dotted curves represent the individual fitted peaks.

Fig. 2. DLTS spectra after 1.8 MeV proton irradiation to a fluence of and post-anneals at (a) , (b) and (c) . A high-resolution GS4 weighting function was employed (black solid curves) while the blue dotted curves show the cumulative sum of numerical simulations that are fitted to the spectra. Red dotted curves represent the individual fitted peaks.

respectively, while the and levels were tentatively assigned to the ( ) charge state transition levels of the in four different configurations [6]. Further heat treatments at 400 and see the reduction in and S 2 , likely caused by recombination with remaining Si and C self-interstitials that survived the initial post-anneal [6].

Whereas the other peaks appear to diminish gradually as the temperature is increased, exhibits discordant behavior. The level is enhanced upon annealing at before diminishing again for the anneal. Taking a closer look, we find that the peak position appears to shift. Similar behavior is observed for while the peak remains immobile (see Fig. 1a), discounting a measurement artefact as being responsible for the shift.

Fig. 1(b) shows a high-resolution DLTS spectrum (using the GS4 weighting function) centered on the and peaks. Here, we can see the contours of two different peaks contributing to the defect level. It seems that annealing at promotes the growth of a portion of the peak that quickly vanishes again after annealing, while another part remains. We attribute this behavior to the presence of two different defect species giving rise to two peak components: the original level, and a metastable one appearing at a higher temperature than in the DLTS spectra and disappearing after higher temperature annealing.

Next, we perform numerical simulation of the DLTS spectra to fit the curves and extract parameters for the different features based on assumed variable values for trap energy, density and capture cross-section. The starting point for the simulations was the parameters for and presented in Ref. [11]. Importantly, both and appear to contain more features than previously expected. Fig. 2 shows experimental data (black curves), cumulative fits of the numerical simulations (blue dotted curves) and individual peak fits (red dotted curves) for high-resolution DLTS spectra (GS4 weighting function) of a proton irradiated sample

Fig. 3: Trap concentrations for and extracted from numerical simulations of the DLTS spectra in Fig. 2.

Fig. 3. Trap concentrations for and extracted from numerical simulations of the DLTS spectra in Fig. 2.

As previously found [6], contains at least three contributions and c . However, we also observe the likely appearance of a fourth contribution ( ) after the anneal, which rapidly disappears again above 600 C. More contributions are possible, but further investigations are needed to deduce the complex fine structure of the peak and its thermal evolution. Importantly, at least two contributions are also needed to fit the peak: (stable) and (metastable). The variables used for simulating the DLTS spectra are below and for , and and for denoting the electron capture cross section.

Table 1: Fitting parameters for the six observed trap levels, including the trap energy level below the conduction band edge ( ), electron capture cross-section ( ) and trap concentration ( ).

Trap name | ET (eV) | σn (cm²) | NT (cm⁻³), 300 °C | NT (cm⁻³), 400 °C | NT (cm⁻³), 600 °C
EH₄a | 0.93 | 1.0×10⁻¹³ | 1.7×10¹³ | 1.3×10¹³ | 1.0×10¹³
EH₄b | 0.985 | 1.0×10⁻¹³ | 2.1×10¹³ | 1.7×10¹³ | 1.2×10¹³
EH₄c | 1.04 | 1.0×10⁻¹³ | 2.1×10¹³ | 1.9×10¹³ | 1.0×10¹³
EH₄' | 1.10 | 1.0×10⁻¹³ | 1.2×10¹³ | 1.5×10¹³ | 0
EH₅ | 1.10 | 8.0×10⁻¹⁵ | 1.0×10¹³ | 1.0×10¹³ | 7.0×10¹²
EH₅' | 1.13 | 4.5×10⁻¹⁵ | 1.5×10¹³ | 2.1×10¹³ | 1.0×10¹³

An important feature of the spectra in Fig. 2 is the thermal evolution of the different components of the EH5 peak. After the heat treatments, the two contributions to the peak are present in approximately similar amounts. Annealing at leaves the more stable component of constant or promotes a slight reduction while the metastable s peak grows by . At and above, the ' is reduced to about of its value whereas the main component exhibits a small decrease. While ' disappears rapidly above the more stable is steadily reduced in concentration towards (not shown, see Ref. [6]). The dependencies of trap concentration on annealing temperature are visualized in Fig. 3.

The apparent presence of two distinct defect levels in the vicinity of sheds light on an important discussion. The peak has previously been observed in samples that were electron irradiated to low energies , i.e., below the Si displacement limit [8]. Thus, its relation to the CAV pair has been questioned. Instead, we find that has two components of different thermal stabilities, and . Such a possibility was suggested, but not demonstrated, in Ref. [10]. One component of , termed herein, is assumed to be responsible for the metastability observed in Ref. [8], coming up when we anneal the irradiated sample at but quickly dies afterwards. The other part is the actual EH5, which is more stable and decreases slightly with annealing temperature up to [6]. Previous works [8,11] have reported on this metastability but not separated the two different contributions from one another.

Finally, we speculate that the metastable peak near , is likely related to C interstitials as it appears after 200 keV electron irradiation when, e.g., the S-center is not present. The actual peak, however, is correlated to the occurrence of and and persists at substantially higher temperatures. Thus, we reinforce the previous assignment of to the ( ) charge-state transition of the CAV pair while the metastable behavior is tentatively attributed to carbon interstitial related defects.

Concluding Remarks

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We study proton irradiated n-type 4H-SiC epitaxial layers after annealing at different temperatures and monitor the evolution of the defect population. The traps commonly named and are studied, and their properties extracted by fitting to numerical simulation of DLTS spectra. We reinforce that the level contains at least three contributions, previously assigned to the (+/0) CTL of the CAV complex, with the potential addition of neighboring levels that respond differently to annealing than the other components. In the case of , two defect levels are needed to explain the DLTS signal. The main contribution to appears after irradiation and decreases slowly in concentration up to . The second component, labeled herein, grows substantially upon annealing and disappears rapidly afterwards. In short, we propose that the trap in fact embodies two different defect levels: one that is metastable and related to carbon interstitial defects, whereas the other is more stable persisting until and is tentatively assigned to the (+/0) CTL of the carbon antisite-vacancy pair.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 376-382

doi: 10.4028/p-684nsi

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-11-10

Revised:
2022-02-23

Accepted:
2022-03-07

Online:
2022-05-31

Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

The original version of this paper is available on https://www.scientific.net/MSF.1062.376.pdf

Marie-Amandine PINAULT-THAURY and François JOMARD

¹Université Paris-Saclay, UVSQ, CNRS, GEMaC, 78000 Versailles, FRANCE

marie-amandine.pinault-thaury@uvsq.fr, francois.jomard@uvsq.fr

*corresponding author

Keywords: SIMS, nitrogen, detection limit, diamond, silicon carbide

Abstract

Diamond and Silicon Carbide (SiC) are promising wide band-gap semiconductors for power electronics, SiC being more mature especially in term of large wafer size . Nitrogen impurities are often used in both materials for different purpose: increase the diamond growth rate or induce n-type conductivity in SiC. The determination of the nitrogen content by secondary ion mass spectrometry (SIMS) is a difficult task mainly because nitrogen is an atmospheric element for which direct monitoring of ions give no or a weak signal. With our standard diamond SIMS conditions, we investigate secondary ions under cesium primary ions by applying high mass resolution settings. Nitrogen depth-profiling of diamond and SiC (multi-) layers is then possible over several micrometer thick over reasonable time analysis duration. In a simple way and without notably modifying our usual analysis process, we found a nitrogen detection limit of in diamond and in SiC .

Introduction

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As other wide bandgap semiconductors, diamond and silicon carbide (SiC) exhibits remarkable physical properties that make them suitable for power components . Compared to silicon, power electronic components based on diamond or SiC allow a considerable improvement of the device properties. For SiC power devices, nitrogen doping is a critical point. Indeed, the n-type doping with nitrogen has to be controlled at low values (in the range of to ) in order to fix and increase if necessary the breakdown voltage of the device. Although this doping technology appears mature, the understanding of some synthesis steps remains unsolved. A better knowledge of the structural properties of nitrogen-doped SiC is therefore essential [3-5]. For diamond, the use of nitrogen during its synthesis allows to increase the growth rate [6-8]. However, to avoid deleterious effects on diamond properties, the nitrogen content has to be as low as possible. Indeed, the determination of low doping levels of nitrogen is then essential for both materials.

Light elements, hydrogen, carbon, nitrogen and oxygen, are known as making up the atmosphere. They are present in a lot of materials and in all vacuum chambers. At low content (<1 at%), their presence in materials is difficult to detect. Among the microanalysis techniques, only Secondary Ion Mass Spectrometry (SIMS) can detect them. For SIMS analysis the material is placed under ultrahigh vacuum (up to a few ) and sputtered with a beam of primary ions. The secondary ions resulting from the sputtering are collected and sorted by a mass spectrometer. SIMS analysis performed on a doped semiconductor measures the overall atomic content of a selected impurity, in contrast to electrical measurements from which only impurities participating to conduction are considered. If the extrapolated value of carrier concentration is equal to the atomic content of the corresponding dopant, this means that all dopant atoms participate to the electrical conduction, which informs on the doping quality.

In the semiconductor field, SIMS analysis is usually performed to determine the depth distribution and concentration of dopants but also to study the incorporation of elements resulting from the synthesis process. In order to achieve optimum sensitivity, elements with a low potential for first ionization are detected as positive secondary ions whereas elements with an electro-negative feature are detected as negative secondary ions.

For 20 years, we perform intensive research on diamond in terms of homoepitaxial growth and chemical analysis by SIMS. In this work, we propose to apply and adjust our method of analyzing nitrogen in diamond to silicon carbide. We will emphasis on the nitrogen detection limit, that is to say the smallest measurable nitrogen concent, in these two materials.

Experimental Details

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Dynamic SIMS technique

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The SIMS technique consists in sputtering a solid sample, placed under vacuum, by a focused primary ion beam which is rastered over a square area. This destructive analytical technique can be applied to any type of solid material that can be kept under vacuum. The sputtering by primary ions of a few keV energy induces the ejection of particles from the sample. Part of the ejected particles are ionized (positively or negatively). The sputtered secondary ions are analyzed with a mass spectrometer. The SIMS technique provides a unique combination of extremely high sensitivity for all chemical elements of the periodic table with a very low background. This allows high dynamic range (up to more than 5 decades) and low detection limits (down to ppb level, depending on the SIMS settings, the analyzed element and the studied material).

With dynamic SIMS, the bulk composition and the in-depth distribution of trace elements are investigated with a good depth resolution (typically lower than 10 nm ). This technique gives information about the elemental and isotopic composition through the material thickness (up to a few tens of ). The secondary ion yields will vary greatly according to the chemical environment and the sputtering conditions (ion, energy, angle). Even if this adds complexity to the quantitative aspect of the technique, SIMS is recognized as the most sensitive elemental and isotopic microanalysis technique [9].

Standard SIMS diamond conditions

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The SIMS analysis were performed with dynamic magnetic sector SIMS (IMS7f-CAMECA). For diamond homoepitaxy, SIMS is usually performed in order to measure the depth distribution of dopants (boron or phosphorus) and contaminants (as hydrogen) in the films. In routine analysis, the raster size is . The analyzed zone is restricted to a diameter of to limit the crater edge effects. The depth of the resulting SIMS crater is measured with a Dektak8 step-meter

The analysis are usually performed at low mass resolution, , to have a maximum sensitivity. As the SIMS technique is mostly used in diamond to detect impurities, measurements are performed with parameters allowing high sensitivities. Namely the configuration is classically employed: positive primary ions with a source and detection of negative secondary ions of mass M . The energy of the primary beam is set to 10 keV . Secondary ions are detected in the negative mode by biasing the sample to -5000 V , leading to an interaction energy of the primary ions of 15 keV and an incidence angle of with respect to the normal of the sample. By using a primary intensity in the range of 40 to 60 nA , leading to a sputtering rate of around 0.25 to in diamond matrix, such diamond SIMS conditions do not require time-consuming adjustment.

The detected masses are usually the one coming from the matrix elements of the homoepilayer (as ) and the one coming from the expected impurities that are also contained in the homoepilayer (as the dopants or ).

Detection of nitrogen (low mass resolution)

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Diamond for electronics requires plasma assisted chemical vapor deposition synthesis that allows low impurity contamination. Moreover, diamond homoepilayers are often grown on diamond substrates that contain a high nitrogen level (in the range of ). If thick layers ( ) can be estimated by weight or comparator techniques, the thickness of thin diamond homoepilayers is only accessible by SIMS thanks to the difference in nitrogen content between the layer and the substrate. Unfortunatly, with zero electron affinity, nitrogen give no negative ion . The most efficient way to detect nitrogen is then to collect a molecular ion consisting of a nitrogen atom and a
constituent atom of the matrix (ex: detection of ions in silicon [12]). To compare SiC and diamond, it is necessary to detect the same nitrogen related molecular ions. As diamond matrix does not contain silicone, the usual ions cannot be used in this study. Knowing that carbon is the only matrix element in diamond, the molecular ion is use to detect nitrogen with a good sensitivity (see Fig.1). As a result, we use this molecular ion to analyze nitrogen in diamond and SiC. The corresponding detected mass, M , is close to 26 amu.

Figure 1: and profiles in a diamond delta-doped structure grown on a diamond substrate. The intensity of (matrix element) is intense and constant because there is no change in material between the structure and the substrate (all in diamond). The intensity of (only present in the delta layers) is not changing at the interface because there is no boron in the substrate and up to the first delta layer. The interface between the structure (that contains lower nitrogen amont than the substrate) and the substrate (that contains higher nitrogen amont than the structure) is only visualised thanks to the step marked by the signal.

Figure 1. Figure 1: and profiles in a diamond delta-doped structure grown on a diamond substrate. The intensity of (matrix element) is intense and constant because there is no change in material between the structure and the substrate (all in diamond). The intensity of (only present in the delta layers) is not changing at the interface because there is no boron in the substrate and up to the first delta layer. The interface between the structure (that contains lower nitrogen amont than the substrate) and the substrate (that contains higher nitrogen amont than the structure) is only visualised thanks to the step marked by the signal.

Determination of the nitrogen content: high mass resolution (HMR) for fine tuning
With low mass resolution SIMS analysis, the 26 u.m.a signal contains (26.003074 amu) with all mass interferences as ( 26.00671 amu ). The mass is then not clearly distinguisible from neighboring masses (see Fig.2(a)). Fortunatly, our apparatus allows to work at high mass resolution (HMR), that is to say to separate ions from its neighboring ions. The adjustement consists of slightly closing the entrance and exit slits of the spectrometer, just enough to get close to 7500 (see Fig.2(b)). It is worth to note that the use of HMR settings reduces the signal intensities of the SIMS analysis by few decades.

Figure 2: Mass spectra around 26 amu at (a) low mass resolution where ions are not separated from neighboring ions and (b) high mass resolution where ions are clearly separate from neighboring ions (as ).

Figure 2. Figure 2: Mass spectra around 26 amu at (a) low mass resolution where ions are not separated from neighboring ions and (b) high mass resolution where ions are clearly separate from neighboring ions (as ).

In this work, we have applied our standard SIMS diamond conditions together with HMR settings on two different samples: a low nitrogen doped diamond homoepilayer ( ) and a lightly doped SiC layer ( ). We have detected the - ion as matrix element that has an indepth constant level, and , the element of interest.

Results and Discussion

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Light elements: a specific case

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The analysis of the so-called atmospheric elements presents an additional difficulty. These elements constitute the residual vacuum of the analysis chamber. Under these conditions, the
measured signal can then come from the material but also from background. To limit background contribution, a specific care is taken to reach a vacuum limit of in the analysis chamber. The following paragraph describes the protocol used to determine the limit of detection in both materials.

Raster size method

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We have focused our attention on the determination of the detection limit, DL, reached in such SIMS conditions. For that purpose, we have chosen the raster size method (another method consists in sputtering with high rates to reduce the background contribution). It consists in a step by step reduction of the raster size. A reduction of the raster size induces an increase in the sputtering rate, and therefore more secondary ions are detected by time unit, resulting in an increase of the signal coming from the sample. Each time the raster size is decreased, there is a simultaneous increase of the primary ion density, Jp (ratio between the primary intensity, and the raster size), and the intensity of the detected secondary ions. Fig. 3(a) shows the results obtained on the SiC sample by varying the raster size from down to . The same procedure has been performed on the diamond sample from down to (not shown here).

In Fig.3(b), the mean intensity of the signal over each raster size, , is reported for each primary density, Jp, of each raster size for diamond and SiC samples. In such a plot, the slope of the line corresponds to the fraction of signal actually coming from the material and which is proportional to Jp. The y-intercept corresponds to the constant signal fraction coming from the background. It is this latter value which sets the detection limit under given analysis conditions. Therfore, DL is given here by the y-intercept of the linear fit of the data . In our case, the intercepts are for diamond and for SiC.

Figure 3: (a) Raster size method applied to a lightly nitrogen doped SiC layer (the primary intensity is fixed at 40 nA ). The step by step decrease of the raster size from down to induces an increase of the intensity. (b) Mean intensity of the signal, , in function of the primary ion density, Jp, extracted from the raster size method (upper graph for diamond and lower graph for SiC). The dashed lines are the linear fit of the experimental data. The intercept of the linear fit gives the detection limit, DL.

Figure 3. Figure 3: (a) Raster size method applied to a lightly nitrogen doped SiC layer (the primary intensity is fixed at 40 nA ). The step by step decrease of the raster size from down to induces an increase of the intensity. (b) Mean intensity of the signal, , in function of the primary ion density, Jp, extracted from the raster size method (upper graph for diamond and lower graph for SiC). The dashed lines are the linear fit of the experimental data. The intercept of the linear fit gives the detection limit, DL.

Quantification of DL

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Quantitative SIMS analysis requires standard materials to determine a relative sensitivity factor (RSF) values. In the case of diamond, we use an implanted standard with a known dose of nitrogen while for SiC, we use a bulk SiC with a known nitrogen content. The formula allowing the quantification of DL is given by [DL] = DL*RSF/I [9] where is the mean intensity of the matrix element detected during the analysis (expressed in cps), DL (in cps) is the intensity of the element of interest that is extracted from the raster size method and RSF ( ) is given by the SIMS analysis of the standard materials. The uncertainty of the DL quantification is evaluated to [9]. Table 1 resumes the values obtained from our SIMS analysis by using the - ions as matrix element.

The [DL] value in diamond ( ) is quite high compare to . As the best DL in SIMS should correspond to the detection of 0 or 1 cps , it is necessary to use a sample presenting low enough content of the element of interest but still high enough to be detectable. That is why the raster size method is usually performed on lightly doped samples (namely in the range of ). With higher content, the determination of the DL is no longer precise due to high secondary intensities. Therefore, the extracted DL value may suffer of a high uncertainty.

Diamond | DL ~ 267 cps
Silicon Carbide | DL ~ 8 cps

Table 1: Values of RSF, , DL and [DL] for both wide band-gap semiconductors obtained using diamond SIMS analysis with HMR.

In our case, the diamond sample used contains 30 time more nitrogen than the SiC sample. As a result, the mean intensities of measured with the raster size method are much more important in the diamond sample ( ) than in the SiC sample ( ). Then the error induced in the DL determination is more important for the diamond sample. This could partially explain the factor 40 between the [DL] values of diamond and SiC. The use of a diamond sample with lightly nitrogen doped level should lead to a more accurate value of DL. However, such samples are hard to obtain because the precise control of nitrogen incorporation during diamond growth is a challenge at such low doping level.

In the literature, there are just a few reported studies on nitrogen DL in SiC [13-18] by detecting different nitrogen-matrix ions (as SiN [13]). Most of this studies are performed with higher primary ion intensities (from 80 nA up to 400 nA ) than in our work. The common point is that the lower DL achievable are time consuming and cannot be guaranteed at all the times. Wang et al. [15, 16] use SIMS settings that are limited to bulk and thick layers of SiC ( ) with constant nitrogen content. Indeed, small raster size ( and lower) often leads to un-flat bottom crater that is unwanted for analyzing samples with impurity concentration variation [17]. Moreover, lower raster size induces faster sputter rate and less data points, unsuitable for (ultra-) thin multilayer SiC samples [14]. For Ya Der et al. [18], low DL requires great hardware overheads and retains the transmission of the analytical channel. As a result, it is necessary to evaluate the relevance of our SIMS conditions on multi-layer SiC sample.

Figure 4: HMR nitrogen depth profiles of the diamond and SiC samples. The raster size and the primary ion intensity were adjusted to reach a sputtering rate around and 60 nA for diamond; and 40 nA for SiC ). The dashed areas correspond to the nitrogen DL with an accuracy of .

Figure 4. Figure 4: HMR nitrogen depth profiles of the diamond and SiC samples. The raster size and the primary ion intensity were adjusted to reach a sputtering rate around and 60 nA for diamond; and 40 nA for SiC ). The dashed areas correspond to the nitrogen DL with an accuracy of .

For this reason, we have applied our standard SIMS diamond conditions with HMR settings to another diamond sample and the previous SiC sample through several micro-meters. By adjusting the raster size and the primary ion intensity to have reasonable sputtering rates, we obtain the depth profiles of nitrogen presented in Fig.4. The profiles of in diamond and in SiC can be done in only and , respectively, keeping a low DL, especially in SiC. We observe that the diamond homoepilayer presents a nitrogen signal in the range of the diamond [DL] value. For SiC sample, the buried layer underneath the thick lightly doped layer is also at the SiC [DL] value. Such depthprofiling validates our SIMS settings for the analysis of SiC multi-layers with low nitrogen DL.

Summary

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In this work, we have investigated nitrogen detection by SIMS. We have determined the detection limit, DL, of nitrogen in diamond and SiC. We used our standard diamond SIMS conditions with high mass resolution (HMR) settings that require few adjustments, are reliable and not time-consuming. We found a nitrogen DL value of for SiC, nearly 40 time lower than in diamond. Such value allows the determination of nitrogen in lightly nitrogen doped SiC layers ( ). In the future, we will continue to investigate nitrogen DL in both wide-band gap materials by adjusting HMR SIMS settings to try to reach lower values.

References

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F. Schmid, S. A. Reshanov, H. B. Weber, G. Pensl, M. Bockstedte, A. Mattausch, O. Pankratov, T. Ohshima and H. Itoh, Deactivation of nitrogen donors in silicon carbide, Phys. Rev. B 74 (2006) 245212

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A. Chayahara, Y. Mokuno, Y. Horino, Y. Takasu, H. Kato, H. Yoshikawa, and N. Fujimori, The effect of nitrogen addition during high-rate homoepitaxial growth of diamond by microwave plasma CVD, Diam. Rel. Mater. 13 (2004) 1954-1958

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M.A. Lobaev, A.M. Gorbachev, S.A. Bogdanov, A.L. Vikharev, D.B. Radishev, V.A. Isaev, V.V. Chernov, and M.N. Drozdov, Influence of CVD diamond growth conditions on nitrogen incorporation, Diam. Rel. Mater. 72 (2017) 1-6

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M.-A. Pinault-Thaury, I. Stenger, R. Gillet, S. Temgoua, E. Chikoidze, Y. Dumont, F. Jomard, T. Kociniewski, and J. Barjon, Attractive electron mobility in (113) n-type phosphorus-doped homoepitaxial diamond, Carbon 175 (2021) 254-258

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 383-388

doi: 10.4028/p-kc5309

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-12-23

Revised:
2022-03-04

Accepted:
2022-03-10

Online:
2022-05-31

Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

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Lars Knoll , Giovanni Alfieri , Gianpaolo Romano , Andrei Mihaila , Yulieth Arango , Moritz Wehrle , Vinoth Sundaramoorthy , Stephan Wirths

Keywords: SiC power MOSFET, high-k gate dielectrics, SiC MOSFET reliability, high temperature gate bias test, threshold voltage stability.

Abstract

Recently high-k gate dielectrics for SiC power MOSFETs attracted increasing research interest thanks to promising results related to improved specific channel resistances and threshold voltage stability. We investigated high-k gate stacks for 1.2 kV and 3.3 kV SiC power MOSFETs regarding on-state performance and stability during high temperature gate bias tests. Furthermore, we studied the high-k/SiC interface quality and the effect of burn-in pulses using SiC MOSCAPs. Highk SiC power MOSFETs show significant improvement in on-state performance and threshold voltage stability. We found that the burn-in pulses can be shorter for high-k gate dielectrics compared to based devices.

Introduction

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Nowadays, power electronics is undergoing an exciting and profound technology shift driven by the steadily growing demand for energy of our digital society and the urgent requirement for low carbon emission transport infrastructures. Si based power electronics reaches its performance limits regarding high energy-efficient power converters for e-mobility and renewable energy applications. SiC MOSFETs have entered the power devices arena and are the frontrunners to replace traditional Si IGBT technology due to their higher breakdown voltage and thermal conductivity. Despite their successful market entry, several challenges that are strongly connected to the state-of-the-art gate stack technology are still to be solved though in order to fully exploit the enormous potential of SiC power MOSFETs. Conventional gate oxides for example suffer from highly defective oxide/ SiC interfaces with interface state densities ( ) of in the order of . These defect levels are significantly higher than what it is typically found in systems [4]. Thus, the field-effect mobility of SiC MOSFET, which is strongly related to the , is limited by the carrier trapping effect of the interface states, even after nitridation [5]. The origin of such high is not yet fully understood, but there is a general consensus that it might originate from the presence of C in the or at the interface [6]. Additionally, the threshold voltage stability and drift are unsolved problems in SiC MOS technology. We have developed a novel MOS gate stack technology based on high-k dielectrics for power electronic devices between 1.2 kV and 3.3 kV . The concept of integrating high-k dielectrics in SiC power devices has been investigated since the late 1990s, however, it is only recently that the rather low temperature processes needed for high-k have been successfully combined with the high thermal budgets required for SiC. It is becoming increasingly evident that the predicted device performance gain has not only been experimentally confirmed, but is also featured by other concomitant phenomena, which, for instance, impact on burnin behavior and other effects caused by defects. In this paper, we review the performance gain and threshold voltage stability in low and medium voltage SiC power MOSFETs, while focusing on the key features of an improved dielectric interface.

Figure 1: Extracted hysteresis for various sweep amplitudes from to for high-k and dielectrics with and without post oxidation nitridation

Figure 1. Figure 1: Extracted hysteresis for various sweep amplitudes from to for high-k and dielectrics with and without post oxidation nitridation

Figure 2: extraction from CC-DLTS for various V for high-k (left) and (right) for various pulse voltage from 3 V to 30 V (inset).

Figure 2. Figure 2: extraction from CC-DLTS for various V for high-k (left) and (right) for various pulse voltage from 3 V to 30 V (inset).

Experimental Details

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Thermally oxidized and high-k MOS capacitors were fabricated by thermal oxidation in ambient and state-of-the-art dielectric deposition technique without oxidizing the underlaying SiC interface, respectively. Electrically characterization by C-V and deep level transient spectroscopy was performed. C-V measurements were performed at RT ( 1 MHz ), whereas deep level transient spectroscopy, in constant capacitance mode (CC-DLTS), was performed in the 77-750 K temperature range. CC-DLTS measurements were carried out at a fixed frequency of 1 MHz , by using a reverse bias of -15 V and by keeping a constant pulse height value, with a filling pulse of 1 ms . Another set of measurements was done by replacing the electrical pulse with an UV optical pulse of , e.g. minority carrier transient spectroscopy (MCTS).

The CC-DLTS/MCTS signal was then converted into an energy distribution of the density of interface traps . This was done assuming that the is weakly dependent of the energy and that the capture cross section does not depend on the temperature and energy [5].

A gate stress bias (burn-in) of 20 V was applied to either thermal oxide and high-k MOS capacitors, at 150,175 and , for different time durations. The flat band voltage ( ) was extracted from the measurements, by using the second derivative of the relation between the capacitance C and the gate voltage [7].

Finally, we fabricated planar high-k SiC power MOSFETs for repetitive switching experiments to investigate the threshold voltage stability under harsh dynamic conditions. These devices were soldered on copper substrates, wire bonded and measured in a double pulse tester with a stray inductance of 60 nH .

Results and Discussion

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Figure 1 shows the static gate voltage hysteresis comparing both dielectric layers, also indicating the effect of annealing on the interface. Apparently, the process does not improve the hysteresis effect of the device. The high-k, however, shows no hysteresis up to 20 V that underlines the improved threshold stability still representing one of the greatest challenges for SiC devices and applications. Figure 2 indicates the comparison of the extracted density of interface states ( ) using CC-DLTS of high-k (left) and (right) gate stacks. Here, voltage pulses at different start voltages for the CV characteristics of the MOS capacitor samples were studied. Higher trap densities

Figure 3: Burn-in over time for different temperatures comparing high-k and gate dielectrics.

Figure 3. Figure 3: Burn-in over time for different temperatures comparing high-k and gate dielectrics.

are associated to larger voltage sweeps in both cases. However, the trap density for the high-k gate stacks is more than one order of lower compared to the -based stack. Notably, the pulse voltage dependence drops significantly towards mid gap. We also investigated whether the improved high interface quality does also affect the burn-in behavior.
Figure 3 shows the flat band voltage shift ( ) as function of the burn-in time at various temperatures. The voltage shift saturates at approx. +2.5 V for all temperatures for the stack. This saturation level is reached faster, i.e. at shorter burn-in times, with increasing temperature. Similar behavior was observed for the high-k dielectric, although the saturation voltage is lower.
Figure 4 and 5 display the interface density extracted using CC-DLTS and MCTS for a wide range of the bandgap. We examined as deposited devices and samples after burn-in pulses at , for thermal oxide and high-k dielectrics. As it can be seen, the close to the conduction band is considerably higher for the thermal oxide compared to the high-k dielectric. This might be due to the fact that in the thermal oxide MOS capacitor, the presence of defects in the that give rise to a D distribution close to the conduction band [8] has to be taken into consideration. Close to midgap the two dielectrics show a broad distribution. Despite the superior high-k/SiC interface quality, this peak was not influenced by the choice of dielectric and its corresponding process. Thus, we assume that the defect traps are in the SiC epi layer rather than at the interface. After the burn-in stress, it can be noted that the close to the conduction band was not affected (Figure 4 and 5). On

Figure 4: a) extraction using CC-DLTS and MCTS over the full bandgap for as deposited and burned-in thermal oxide, for a . b) Depth profile of the CC-MCTS signal taken at 750 K , corresponding to the distribution at .

Figure 4. Figure 4: a) extraction using CC-DLTS and MCTS over the full bandgap for as deposited and burned-in thermal oxide, for a . b) Depth profile of the CC-MCTS signal taken at 750 K , corresponding to the distribution at .

Figure 5: a) extraction using CC-DLTS and MCTS over the full bandgap for as deposited and burned-in high-k dielectrics, for a . b) Depth profile of the CC-DLTS peak at .

Figure 5. Figure 5: a) extraction using CC-DLTS and MCTS over the full bandgap for as deposited and burned-in high-k dielectrics, for a . b) Depth profile of the CC-DLTS peak at .

the other hand, we observe a slight decrease in for the thermal oxide samples. The burn-in pulses do not show any effect on the for the high-k samples.
In the following we will provide a short discussion about the microscopic origin of such mid-gap defect distribution. First, it should be noted, that no final conclusions can be drawn based on the presented results and that further investigations are needed. Nonetheless, some hypotheses can be put forward to explain such broad distributions. In their study, Kobayashi et al.[9] have analyzed different defects, e.g., carbon dimers in the , at the interface and in SiC , in a system, by means of density functional theory. Among the investigated defects, the most promising might be the dicarbon antisite , located in the SiC crystal giving rise to several electrical active levels in the band gap. As a matter of fact, is responsible for two very close electrically active levels at midgap, at and [9]. Since DLTS is generally not suitable for separating two (or more) similar emission rates, it can be suggested that such broad might originate from these two closely spaced levels. Possibly, a Laplace DLTS investigation might be useful to separate both contributions.
In the insets of Figure 4 and 5, we report the extracted depth profiles of the CC-DLTS signals at (thermal oxide) and (high-k). The depth distribution of both signals is located at least within the first hundreds of nanometers of the epitaxial layer, meaning that the defects responsible

Figure 6: Static on-state comparison of 1.2 kV and 3.3 kV SiC MOSFETs with high-k and dielectric.

Figure 6. Figure 6: Static on-state comparison of 1.2 kV and 3.3 kV SiC MOSFETs with high-k and dielectric.

Figure 7: Static blocking comparison of 1.2 kV and 3.3 kV SiC MOSFETs with high-k and . dielectric.

Figure 7. Figure 7: Static blocking comparison of 1.2 kV and 3.3 kV SiC MOSFETs with high-k and . dielectric.

for this are rather close to the surface. The concentration, however, is in the range of the drift doping. Thus, it must be assumed that a change due to burn in, as we have seen, has a significant effect on the threshold and flatband voltage of the device.
Figure 6 shows the static on-state characteristics of 3.3 kV and 1.2 kV SiC power MOSFETs with high-k and standard silicon dioxide gate stacks and pitches of 14 um . The channel length amounts to 250 nm . While the high-k gate stack was deposited by a state-of-the-art deposition technique commonly used for example in CMOS technology, the silicon dioxide was formed by high temperature thermal oxidation of a deposited CVD layer and a high temperature post oxidation nitridation (PON) in ambient. As can be seen in the graph, both voltage classes gain significantly in performance. Although the performance of higher voltage devices depends substantially on the epi

Figure 8: Extracted dV/dt from repetitive dynamic turn-on waves of high-k MOSFET switching and and to +15 V at .

Figure 8. Figure 8: Extracted dV/dt from repetitive dynamic turn-on waves of high-k MOSFET switching and and to +15 V at .

resistance, the implementation of high-k leads to a reduction of the on-state by more than . Figure 7 shows the blocking characteristics of the same representative devices from Figure 6. In both voltage classes the high-k dielectric efficiently reduces the reverse leakage by approx. one order of magnitude. Apparently, the channel suffers from drain induced barrier lowering effects which can be suppressed by the larger permittivity and thus electric field in the SiC . Moreover, the stability extracted from dynamic characterization is depicted in in Fig. 8. The extracted dV/dt of the turn-on

Figure 9: Transfer curves of 1.2 kV SiC power MOSFETs with (left) -based and (right) high-k gate stacks after each 20 hours HTGB stress cycle. The insets show the extracted threshold voltage drift as function of stress time.

Figure 9. Figure 9: Transfer curves of 1.2 kV SiC power MOSFETs with (left) -based and (right) high-k gate stacks after each 20 hours HTGB stress cycle. The insets show the extracted threshold voltage drift as function of stress time.

wave forms up to 200 k stress cycles at using a wide gate voltage swing of does not show any signs of degradation. Finally, we performed high temperature gate bias (HTGB) tests on 1.2 kV SiC power MOSFETs with high- k and -based gate stacks. The devices were tested for hours at using a gate voltage of . After each 20 hours gate voltage stress phase we measured the transfer curves, as can be seen in Figure 9, and extracted the threshold voltage drift (c.f. insets of Figure 9). The threshold voltage drift of the high-k devices is considerably lower, i.e. below 100 mV , compared to the -based devices. For the latter we observed a maximum threshold voltage drift of 500 mV after an accumulated HTGB stress of 100 hours.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.383.pdf

In this paper we presented the latest advances of our high-k gate stack technology for vertical SiC power MOSFETs including a thorough study of the SiC/dielectric interface quality using CV, DLTS and MCTS measurements. Additionally, we studied the effect of burn-in voltage pulse on the flatband voltage stability of high-k SiC MOSCAPs. We found that the flatband voltage saturates at lower burnin times for increasing temperature. This saturation is reached even earlier for the high-k gate stacks. 1.2 kV and 3.3 kV SiC power MOSFETs show a significantly improved on-state performance compared to -based control devices and indicate a lower threshold voltage drift. Furthermore, it was demonstrated that the influence of the stress voltage results in a change of the defect concentration.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.383.pdf

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology (Wiley, Singapore, 2014).

H. Yoshioka, J. Senzaki, A. Shimozato, Y. Tanaka, and H. Okumura, AIP Adv. 5, 017109 (2015).

T. P. Chow, H. Naik, and Z. Li, Phys. Status Solidi A 206, 2478 (2009).

E. H. Nicollian and J. R. Brews, MOS Physics and Technology (John Wiley & Sons, Inc, New York, 1982).

T. Hatakeyama, Y. Kiuchi, M. Sometani, S. Harada, D. Okamoto, H. Yano, Y. Yonezawa, H. Okumura, Appl. Phys. Express 10, 046601 (2017)

D Dutta, DS De, D Fan, S Roy, G Alfieri, M Camarda, M Amsler, J Lehmann, H Bartolf, S Goedecker, TA Jung, Appl. Phys. Lett. 115, 101601 (2019)

H.M. Przewlocki, T. Gutt, K. Piskorski, J. Appl. Phys. 115, 204510 (2014)

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T. Kobayashi, Y. Matsushita, J. Appl. Phys. 126, 145302 (2019).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 389-394

doi: 10.4028/p-78l92c

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-26

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

Judith Woerle , Brett C. Johnson , Roger Stark , Massimo Camarda and Ulrike Grossner

¹Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

School of Physics, University of Melbourne, Victoria 3010, Australia

Paul Scherrer Institute, Forschungsstrasse 111, 5232 Villigen, Switzerland

woerle@aps.ee.ethz.ch, brett.johnson2@rmit.edu.au, stark@aps.ee.ethz.ch, massimo.camarda@psi.ch, ulrike.grossner@ethz.ch

Keywords: interface defect density, photoluminescence, capacitance-voltage

Abstract

Electrically active defects at the interface can have detrimental effects on the device performance of SiC MOSFETs. Capacitance- or conductance-based analysis techniques are commonly used to extract the density of interface defects, despite having the disadvantage of requiring dedicated test structures for the analysis. Here, we discuss confocal sub-bandgap photoluminescence (PL) microscopy as a fast and reliable alternative to conventional electrical characterization techniques. For this purpose, the quality of the interface after postoxidation annealing in is studied both by confocal imaging as well as by the high-low and capacitance technique. We find excellent agreement between the optical and electrical analysis and observe a significant increase of the interface defect density for annealing temperatures below .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

For the fabrication of commercially viable SiC metal-oxide-semiconductor field-effect transistors (MOSFETS), the growth of a high-quality gate oxide layer in combination with an abrupt silicon dioxide interface and a low density of defects is vital. Although conventional dry or wet oxidation techniques - similar to what is used for Si - can be used to grow insulation layers on SiC , the termination of the SiC surface has proven insufficient using these processes alone as they lead to a high density of both interface defects ( ) and near-interface oxide traps. This has been linked to very low channel mobilities and thus high channel resistances in SiC MOSFETs [1].

For the characterization of interface and bulk properties of a dielectric layer on a semiconductor, capacitance-voltage (CV) and conductance-voltage (GV) measurements on MOS capacitors are routinely used. One major advantage of these well-established techniques is their selective sensitivity to electrically active defects, facilitating a correlation of measurement results with the device performance of the final MOSFET. However, the inherently wide bandgap of SiC causes a broad variation of interface trap response times, setting strict limits to the energy window that can be investigated at room temperature [2]. In addition, much higher frequencies are required for a correct evaluation of the close to the conduction band compared to, e.g., silicon devices [3]. Another disadvantage of CV and GV techniques is that they require dedicated test structures, which can be cumbersome during process development or for process monitoring purposes. Recently, confocal photoluminescence (PL) microscopy was shown to present an attractive alternative for a nondestructive characterization of the interface [4], allowing for a quick estimation of the interface defect density between individual fabrication steps.

In order to improve the low channel mobility in SiC MOSFETs, a variety of oxidation and postoxidation annealing (POA) treatments have been suggested [5,6], among which nitridation was shown to be particularly promising [7-10]. Both direct growth as well as post-oxidation annealing (POA) in NO or ambients have been intensively studied and are now commonly used for the fabrication
of commercial power MOSFETs [6]. During nitridation, nitrogen accumulates at the interface and although the detailed mechanisms are still not fully understood, there seem to be similarities with Si , where a passivation of the interface defect states via bonds is responsible for the observed improvement [11].

In particular, NO was shown to be very effective in improving the channel mobility for all crystal faces , although its high toxicity sets clear constraints to a widespread implementation. is less of a safety concern but in order to prove beneficial, careful optimization of the nitridation temperature is required as high temperatures are necessary for to dissociate into and which then lead to a simultaneous nitration and oxidation [9,13,14].

The upper temperature limit for nitridation in is set around where NO dissociates into and [15]. The low-temperature limit, on the other hand, is less clearly defined and experimental reports on the beneficial effect of treatments to efficiently passivate interface defects range from to [9,16,17]. A clear understanding of the low-temperature nitridation regime, however, may be essential for applications where very thin oxides are required or where the thermal budget of the samples is limited. Furthermore, a large number of academic and industrial research facilities are restricted both in oxidation temperatures as well as in the choice of processing gases, emphasizing the need for a dedicated low-temperature study.

Hence, the aim of this work is to explore the effects of POA processes in on the quality of the interface in the temperature range between and . The interface defect density is extracted both by conventional capacitance-voltage techniques (i.e. the high-low and C- method) as well as sub-bandgap confocal photoluminescence (PL) spectroscopy and results are discussed in light of temperature-dependent dissociation processes.

Method

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

Samples cut from Wolfspeed wafers with a off-axis orientation and an epi-layer doping concentration of were used in this study. All samples were wet-chemically cleaned and an oxidation was performed for 11 h at in an atmosphere, resulting in an oxide thickness ( ) of 18.5 nm . Post-oxidation annealing in was carried out in the same oxidation furnace for 3 h at temperatures ranging from to . After the nitridation, aluminum was deposited on the front side to define contacts with a radius of . Finally, the oxide on the backside was removed and 100 nm Ni was deposited for the Ohmic back contact.

High-frequency (HF) and quasi-static (QS) CV measurements were performed on a wafer probe station with a Keithley 4200A-SCS parameter analyzer. For the high-frequency measurements, an AC frequency of 1 MHz and an AC amplitude of 25 mV were used. Quasi-static CV curves were obtained by measuring the displacement current in response to a slowly varying DC gate voltage. The ramp rate was fixed to . For each nitridation process, several MOS capacitors were analyzed and a negligible variability between different devices was found. All CV measurements presented here were performed at room temperature. In addition to the capacitance measurements, the oxide thickness of three of the samples were also measured by X-ray reflectometry (XRR) using a Bruker D8 micro-source X-ray diffractometer.

The confocal PL setup used in this study consisted of a 532 nm continuous wave Nd:YAG laser, a dichroic mirror, a high numerical aperture ( 0.95 ) 100x air objective, a 560 nm long pass filter and a fiber-coupled single photon counting module. The theoretical diffraction-limited spatial resolution was 280 nm for emission wavelengths of 600 nm . The samples were mounted onto a piezoelectric XYZ scanning stage allowing for scan sizes of up to . All confocal images presented here were collected at room temperature. More details on the setup and the PL analysis are given in Ref. [4].

Results & Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

For the electrical extraction of the , quasi-static and HF capacitance-voltage measurements were performed and results are presented in Fig. 1. The high-frequency CV curves in Fig. 1a show an increasing stretch-out of the capacitance for decreasing annealing temperatures as expected for increasingly large interface defect densities. For the two lowest annealing temperatures, a small bump is observed in depletion, which is even more pronounced for the quasi-static measurements in Fig. 1b (indicated by the arrow). From the oxide capacitance, the oxide thickness was then extracted and results are presented in the inset of Fig. 1b. With increasing temperature, more and more from the dissociation is available, giving rise to additional oxide growth and hence to an increase of the overall oxide thickness to 20 nm . The sample annealed at , on the other hand, showed a slightly reduced thickness which might be connected to the very large defect density and hence a larger error of the electrically determined oxide thickness.

Figure 1. Normalized capacitance-voltage curves for different annealing temperatures. (a) Highfrequency measurements at 1 MHz . The quasi-static curve for the non-annealed sample is also shown (dash-dotted line). (b) Quasi-static CV curves. The inset shows the oxide thickness as function of the annealing temperature as extracted from CV (filled symbols) and XRR (open symbols) measurements. Additional oxide growth is only observed for temperatures .

Figure 1. Figure 1. Normalized capacitance-voltage curves for different annealing temperatures. (a) Highfrequency measurements at 1 MHz . The quasi-static curve for the non-annealed sample is also shown (dash-dotted line). (b) Quasi-static CV curves. The inset shows the oxide thickness as function of the annealing temperature as extracted from CV (filled symbols) and XRR (open symbols) measurements. Additional oxide growth is only observed for temperatures .

Also indicated in the inset of Fig. 1b are the results of thickness measurements using X-ray reflectometry (XRR) performed on three of the five samples, which show a similar trend as the electrical analysis. Similar to earlier reports [18], the systematic overestimation of from the CV data may be explained by a smaller relative permittivity for thermal oxides grown on SiC compared to Si , i.e. instead of . A variation of the oxide density for different annealing temperatures was not observed during the XRR measurements.

Using both the C- [3] and high-low [19] CV method, the interface trap density was extracted. A comparison of the two methods is presented in Fig. 2. As previously reported, the high-low method is not sensitive to very fast states, which still respond to the probing frequency of 1 MHz , hence leading to an underestimation of the interface defect density close to the conduction band [3]. Apart from the absolute offset between the two methods, a very similar trend is observed for the annealed samples shown in Fig. 2: a strong increase in is detected for the samples annealed at , indicating a deterioration of the interface caused by the POA in as also observed previously [11,20]. With increasing temperature, the decreases again and only for the samples annealed at , a small but consistent improvement to the non-annealed samples is observed.

Figure 2. Density of interface defects as a function of the trap energy position. (a) Trap distribution extracted from the CV measurements in Fig. 1 using the high-low method. (b) Trap distribution according to the method. (c) Comparison of the high-low and method for the non-annealed sample.

Figure 2. Figure 2. Density of interface defects as a function of the trap energy position. (a) Trap distribution extracted from the CV measurements in Fig. 1 using the high-low method. (b) Trap distribution according to the method. (c) Comparison of the high-low and method for the non-annealed sample.

In addition to the electrical characterization of the defect states generated during the low-temperature nitridation, confocal PL microscopy was deployed for optical analysis. While this technique is already extensively used for the analysis of bulk defects using above band-gap light excitation [21,22], it is gaining increasing attention as defect mapping tool for the interface [4,23,24].

Figure 3. (a) Confocal PL maps of thermally oxidized . (b) Comparison of the emission center intensity median (left) and the as extracted by the method (right) as a function of the annealing temperature. Presented values refer to a bandgap energy of .

Figure 3. Figure 3. (a) Confocal PL maps of thermally oxidized . (b) Comparison of the emission center intensity median (left) and the as extracted by the method (right) as a function of the annealing temperature. Presented values refer to a bandgap energy of .

Figure 3a shows confocal PL maps of the nitrided samples after excitation with a sub-bandgap 532 nm laser. Diffraction-limited spots can be observed which are associated with single defects residing at or near the interface. In accordance with the electrical analysis, the integrated intensity of these single defects is observed to decrease as the annealing temperature increases while the density of defects remains around (equivalent to ) in each map. These values are much lower than the defect densities discussed above since only a small energy window is probed with the sub-bandgap energy laser. The decrease in intensity is assumed to be due to modification of the radiative recombination rate due to the presence of nitrogen at the interface [4]. An increased number of defect centers is also observed in vicinity to crystal defects or surface damage (e.g., scratches) of the epitaxial layer. After removal of the layer from the samples, the PL intensity and hence defect density is significantly decreased. The corresponding room-temperature ensemble PL spectra for the studied samples exhibit a large spectral variability, leading to a broad PL peak centered at 750 nm (not shown here).

A direct comparison of the two analysis methods is shown in Fig. 3b where both the integrated PL intensity of the presented confocal PL maps and the electrically extracted as a function of the annealing temperature are presented. Very good agreement between the two analysis methods is found. With both methods, a small improvement of the interface quality compared to the nonannealed sample could be observed for the highest annealing temperature. A further decrease of the is expected as the annealing temperature is further increased [13,17].

In order to explain the observed degradation of the interface at low annealing temperatures, it is valuable to consider the nitridation process in more detail: for efficient nitridation of the interface, the dissociation of into and is essential, which only occurs at temperatures well above . This is also apparent in our measurements where a reduction of is only detected at an annealing temperature of . The significant increase of interface defects at lower temperatures is less intuitive, especially when considering that the diffusion of in should be very slow due to their large molecular size [13]. However, several studies confirm this observation: slow-trap profiling of -annealed SiC revealed increased densities of slow interface traps, (whereas NO annealing led to a significant decrease of the slow traps) and in experiments with diluted an improvement was only achieved when the carbon removal rate from the interface exceeded the carbon accumulation rate [7-9, 25]. The strong increase in observed in the CV and PL measurements may be an indication for a hampered out-diffusion of carbon away from the interface and emphasizes the need for careful optimization of the annealing process.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

In this work, a comparison between capacitance-voltage methods and sub-bandgap confocal photoluminescence microscopy for the characterization of oxidation-induced defects at the interface was presented. The samples, annealed in at different temperatures, exhibited an increasing density of interface defects for decreasing annealing temperatures. At an annealing temperature around , the nitridation had beneficial effects on the . Although confocal PL does not allow for a quantitative analysis, already small variations of the defect density at the interface are detectable and a similar trend for increasing annealing temperatures is clearly observed. This study emphasizes the great potential of confocal PL as a quick and reliable characterization method for a variety of oxide/semiconductor systems without the need of fabricating a full device. Although this work has been performed on smaller sample sizes, an extension of confocal PL to full-wafer mapping is feasible. As the measurement does not require surface contacts, very thin oxides (a few monolayers) can also be accurately measured. Furthermore, measurements can be performed directly on the oxidized wafer and at room temperature, making it an attractive tool for a quick and reliable interface analysis during device fabrication.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

Laura Maurel is gratefully acknowledged for performing the XRR measurements. This work was supported by the Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology (No. CE110001027).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.389.pdf

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology. Wiley (2014).

J. A. Cooper, Phys. Status Solidi A 162, 305 (1997).

H. Yoshioka, T. Nakamura, and T. Kimoto, J. Appl. Phys. 111, 014502 (2012).

B. C. Johnson et al., Phys. Rev. Applied 12, 044024 (2019).

G. Liu, B. R. Tuttle, and S. Dhar, Appl. Phys. Rev. 2, 021307 (2015).

M. Cabello et al., Mater. Sci. Semicond. Process. 78, 22 (2018).

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G. Y. Chung et al., Appl. Phys. Lett. 76, 1713 (2000).

S. Dimitrijev et al., Properties of Nitrided Oxides on SiC, Springer Berlin Heidelberg (2004).

Y. Nanen et al., IEEE Trans. Electron Devices 60, 1260 (2013).

T. Kimoto et al., Jpn. J. Appl. Phys. 44, 1213 (2005).

V. V. Afanas'ev et al., Appl. Phys. Lett. 82, 568 (2003).

T. Suzuki et al., Mater. Sci. Forum 615-617, 557 (2009).

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K. Y. Cheong et al., J. Appl. Phys. 93, 5682 (2003).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 395-399

doi: 10.4028/p-99gtk8

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-12

Revised:
2022-03-03

Accepted:
2022-03-10

Online:
2022-05-31

Evaluation of Line-Shape Defect in Epitaxial Wafer

The original version of this paper is available on https://www.scientific.net/MSF.1062.395.pdf

Ling Guo and Daisuke Shiomi

SHOWA DENKO K.K. Device Solutions Division, 1505 Shimokagemori, Chichibu-shi, Saitama

369-1893, Japan

guo.ling.xhjxe@showadenko.com, shiomi.daisuke.xhixv@showadenko.com

*Corresponding author

Keywords: Line-shape defect, stacking fault defect, threading screw dislocation, threading mixed dislocation, threading edge dislocation

Abstract

In this study, we investigated the origin of line-shape defect in epitaxial wafers. The inspection results revealed that such defects resulted from the substrate entirely and accompanied with dislocation lines during the epitaxial process. Although the defect surface condition with nanometer level of roughness seemed to do little harm to the initial electrical characteristics of power devices, dislocation lines possibly resulted in high leakage current when reverse voltage was applied. To reduce line-shape defects, it is essential to reduce defects and threading dislocations in substrates and to develop a nondestructive method for wafer screening.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.395.pdf

Nowadays SiC Schottky barrier diodes (SBDs) and MOSFETs for various applications are already commercially available with the rapid development of semiconductor technology. To meet the needs of high device yield, thick SiC epitaxial wafers ( ) with low particle defect density have been developed.

As is commonly known, triangular defects (bunched-step segment) [1] resulting from particles during epitaxial growth, large-pit defects [2] resulting from carbon-inclusion defects in substrate, and pit defects [3] resulting from fabrication process are regarded as killer defects for SBDs and planar-MOSFETs. In addition, the line-shape defect (LSD; stacking fault complex), which is classified as Diagonal by confocal microscopy with differential interference contrast (CDIC) (SICA88, LaserTec Corp.), has also attracted the attention of device manufacturers because of its potentially bad influence on reverse electrical characteristics of power devices recently.

By comparing wafers in different states, we found that LSDs resulted from substrate entirely and appear as straight or curved lines on the surface of epitaxial wafers. Because it was not clear whether these defects would affect the initial electrical characteristics of power devices, the origins, structures and possible effects on devices of LSDs were investigated and discussed in this study.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.395.pdf

Taking advantage of high-quality epitaxial growth technology, approximate -thick n -type epitaxial layers with low particle defect density ( ) on substrates were prepared. To investigate the origin of LSDs, CDIC and photoluminescence (PL, ) observation of wafers were performed before and after epitaxial growth. The surface condition of a defect was inspected by hybrid laser microscopy (OPTELICS, Lasertec Corp.). Emission spectrum measurement (PLIS-100, PHOTON Design Corp.) was conducted to identify the type of stacking fault defects if any. Besides, cross-sectional scanning transmission electron microscopy (STEM) to reveal the structural features of the defects was performed, checking if polytype, dislocation line or foreign matter existed.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.395.pdf

Fig. 1 shows CDIC and PL images of the same location on the wafer inspected at two different stages: as-substrate and as-epitaxial. It was found that LSDs mainly resulted from scratches, bar-shape stacking faults (BSF), black patterns in PL images (PL-black), and even no obvious surface abnormalities in substrates. Past research also found that carbon-inclusion defects might result in LSDs with the extremely low conversion rate ( ). In this study, we investigated LSDs resulting from the above four different origins, in samples , and D . Although the origins of LSDs were different, stacking faults (SFs) observed in PL images of A, B, and D looked very similar. Therefore, the destructive analysis method is necessary for further distinction.

Fig. 1. CDIC and PL images of line-shape defects.

Fig. 1. CDIC and PL images of line-shape defects.

Firstly, the surface condition in Fig. 2 shows that LSDs consist of start point and line shape. The start point turned out to be a pit in sample A and D, a bump in sample B, but no obvious abnormity in sample C . The line shape of LSDs had a valley-peak-valley structure in common, with the height between peak and valley ranging from 10 to 40 nm (Table 1). Therefore, it was assumed that roughness at the nanometer level could do little harm to the leakage current of the initial electrical characteristics of devices.

Fig. 2. Surface condition of line-shape defect.

Fig. 2. Surface condition of line-shape defect.

Table 1. Summary of surface condition.

Sample | Origin | Start point | Width [μm] | Height [nm]
A | Scratch | Pit | 2.5 | 10
B | BSF | Bump | 1.0 | 30
C | PL-black | - | 0.7 | 30
D | Unknown | Pit | 1.2 | 40

STEM of the four samples revealed that LSDs were accompanied by SFs and dislocation lines at the substrate-epitaxial interface (Fig. 3). SF types were confirmed by stacking sequence observation, and the result was consistent with the emission spectrum measurement. SF types of samples A, C, and D proved to be Frank-type, and the formation mechanism was almost the same as that of a Carrot defect [4].

Fig. 3. Cross-sectional STEM image of substrate-epitaxial layer interface in defect.

Fig. 3. Cross-sectional STEM image of substrate-epitaxial layer interface in defect.

Table 2. Summary of line-shape defect analysis.

Sample | Origin | SF Type | Peak Wavelength | 3C-SiC | Carbon-inclusion | Dislocation Type
|  |  |  |  |  | Substrate | Epitaxial
A | Scratch | Frank | 486 nm | None | None | None | TMD
B | BSF | Bar-shape | 422 nm | None | None | None | TED
C | PL-black | Frank | 486 nm | None | None | TMD | TSD,TMD
D | Unknown | Frank | 486 nm | None | None | TSD,TMD | TSD,TMD

Dark-field observation to distinguish the dislocation types revealed threading screw dislocation (TSDs) and threading mixed dislocation (TMDs) in the substrate and epitaxial layer in samples C and D, indicating a possible leak path during reverse voltage measurement [5], but there was only threading edge dislocation (TEDs) in sample B. Therefore, it is reasonable to assume that chips with LSDs like those in samples C and D are at higher risk of high leakage current. Besides, energy dispersive X-ray spectroscopy analysis showed that no excess carbon was detected, proving no carbon-inclusion contained in samples. The detailed evaluation results were summarized in Table 2.

In conclusion, we assumed that LSDs resulting from scratch, PL-black and unknown (sample and D ) are more likely to be killer defects for reverse voltage application. To reduce LSDs, the quality improvement of substrate seemed to be fundamental, and currently shallow surface defects, such as scratch, carbon-inclusion, BSF and PL-black, could be detected successfully. However, LSDs like sample D could only be evaluated after epitaxial, because the nondestructive inspection method of dislocation with high accuracy and high throughput is still under development.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.395.pdf

Our research on the investigation of various LSDs revealed that these defects totally resulted from the substrates and accompanied with stacking fault defects and threading dislocation lines during epitaxial growth. Although particle defects have been reduced remarkably by advancing epitaxial growth technology, epitaxial defects resulting from the substrate are still inevitable, and some LSDs may turn out to be killer defects. Therefore, it is important to reduce defects and threading dislocations in substrates and to develop a nondestructive method for wafer screening.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.395.pdf

JEITA EDR-4712/100

L. Guo, K. Kamei, et al., Mater. Sci. Forum. 897 (2017) 39-42.

L. Guo, K. Kamei, et al., Mater. Sci. Forum. 963 (2019) 244-248.

H. Tsuchida, M. Ito, et al. physica status solidi (b) 246.7 (2009) 1553-1568.

P. G. Neudeck, W. Huang, M. Dudley, IEEE Trans. Electron Devices, vol. 46 (1999) 478-484.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 400-405

doi: 10.4028/p-cl40be

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-03-01

Accepted:
2022-03-02

Online:
2022-05-31

Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

F. Giannazzo , P. Fiorenza , E. Schilirò , S. Di Franco , S. Monnoye , H. Mank , M. Zielinski , F. La Via and F. Roccaforte

Keywords: scanning capacitance microscopy; conductive atomic force microscopy; 3C-SiC; Schottky; MOS

Abstract

This paper presents a macro- and nanoscale electrical investigation of Schottky and metaloxide junctions with hetero-epitaxial 3C-SiC layers grown on Si. Statistical current-density-voltage (J-V) characterization of Pt/3C-SiC Schottky diodes showed an increase of the reverse leakage current with increasing the devices diameters. Furthermore, and analyses of capacitors revealed non-idealities of the thermal oxide, such as a high trapped positive charge ( ) and a reduced breakdown field ( ) compared to ideal . Nanoscale electrical characterizations by conductive atomic force microscopy (CAFM) and scanning capacitance microscopy (SCM) allowed to shed light on the origin of non-ideal behavior of Schottky and thermal oxide junctions, by correlating the morphological features associated to 3C-SiC crystalline defects with local current transport and carrier density.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

The cubic polytype of silicon carbide ( ) has been studied since a long time, as it could give some advantages with respect to in MOSFET devices, i.e. a high inversion channel mobility [1,2]. Hence, it is considered a good candidate for power electronics applications in the voltage range [3]. However, the large density of defects in hetero-epitaxial 3C-SiC on Si currently limits the performances of both Schottky and MOS devices based on this material. In particular, the impact of stacking faults (SF) and anti-phase-boundaries (APBs) on the reverse leakage current and on the forward turn-on voltage of Schottky diodes is debated [4,5]. Furthermore, the origin of the extrinsic mechanisms responsible for the observed degradation and premature breakdown of 3C-SiC MOS capacitors [6] is still unclear. Considering the detrimental effect of crystalline defect (such as the threading dislocation) in 4H-SiC MOSFETs reliability under high temperature reverse bias stress[7], it is mandatory to fully investigate the role of crystalline defects in 3C-SiC MOS-based structures to address the real intrinsic reliability for future power electronics application.

In this paper, Schottky contacts and thermal oxide ( ) insulators on hetero-epitaxial 3C-SiC/ Si layers have been investigated by means of nanoscale electrical characterizations [8,9], i.e. conductive atomic force microscopy (CAFM) and scanning capacitance microscopy (SCM), with the aim to correlate the morphological features associated to 3C-SiC crystalline defects with local current transport and carrier density.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

Unintentionally doped thick 3C-SiC layers were grown on on-axis substrates by chemical vapor deposition (CVD) using silane ( ) and propane ( ) as silicon and carbon precursors [10]. After the growth, a chemical mechanical polishing of the surface was carried out to reduce the roughness.

On a first sample, Pt Schottky diodes were fabricated by formation of a Ohmic front contact (by Ni lift-off and thermal annealing at ), followed by lift-off of circular Pt contacts with different radius (from 5 to ) [8]. On a second 3C-SiC sample, a thermal oxide ( ) was grown at , 1 hour, in dry . Lateral metal-oxide semiconductor (MOS) capacitors were obtained by lift-off of metal electrodes, consisting of a circular inner gate (radius ), surrounded by a large-area electrode. Electrical characterization (I-V and/or C-V) of the Schottky diodes and MOS capacitors were carried out in a CASCADE Microtech probe station, using a Keysight B1505A parameter analyzer. Nanoscale electrical characterizations, namely Conductive Atomic Force Microscopy (CAFM) and Scanning Capacitance Microscopy (SCM), have been performed using a DI3100 system by Bruker with a Nanoscope V controller, using conductive (Pt or diamond coated) tips. Current maps were acquired on the bare surface and after the growth of a thin ( ) thermal oxide, properly chosen to apply an electric field up to with the tip using the maximum bias ( 10 V ) allowed by our CAFM setup. Furthermore, the same CAFM tip was used to contact the Pt diodes with different areas and perform current-voltage measurements.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

Fig. 1(a) and (b) show two sets of J-V curves collected on arrays of Pt/3C-SiC Schottky diodes with 5 and radius. Noteworthy, the curves collected on the larger diodes showed a significantly higher leakage current density at negative bias, with a larger spread between different devices. Fig.1(c) shows the "yield" of working devices, defined as the percentage of analyzed diodes with a leakage below a threshold current density of . The red line is the fit of the data with the function reported in the insert of Fig.1(c), commonly employed to describe the yield of electronic devices, where A is the contact area and D is the areal density of defects responsible for devices failure [4]. The evaluated density ( ) from the fit can be associated with the extended defects responsible for a leakage current exceeding the fixed threshold. This areal density corresponds to a typical average distance between the defects.

Fig. curves collected on arrays of diodes with (a) and (b) radius. (c) Percentage of diodes (yield) with a reverse leakage lower than , as a function of diode area. The red line is the fit with the function reported in the insert, where D is the density of defects responsible for the leakage.

Figure 1. Fig. curves collected on arrays of diodes with (a) and (b) radius. (c) Percentage of diodes (yield) with a reverse leakage lower than , as a function of diode area. The red line is the fit with the function reported in the insert, where D is the density of defects responsible for the leakage.

The electrical quality of the thermal oxide on was evaluated by means of and measurements on MOS capacitors. Fig. 2(a) shows the measured curve compared with the calculated one. The nominal oxide thickness ( ) was confirmed by the measured accumulation capacitance, whereas the net doping concentration ( ) in the 3C-SiC layer was estimated from the depletion capacitance. As compared to the ideal curve, the experimental curve exhibits a negative shift, with a flat band voltage , corresponding to a density of trapped positive charges in the thermal oxide. Furthermore, using the conductance method, an interface states density was estimated at 0.1 eV below the 3 C -SiC conduction band edge. Fig. 2(b) shows the J-V curve collected on the lateral MOS capacitor, showing a significantly lower breakdown field ( ) with respect to the theoretical value for .

Fig. 2 (a) C-V curve measured at 1 kHz on a 3C-SiC MOS capacitor compared with the calculated curve; (b) Current density vs voltage (J-V) curve of a 3C-SiC MOS capacitor. The value of the ideal breakdown electric field is indicated by the dashed line.

Fig. 2. (a) C-V curve measured at 1 kHz on a 3C-SiC MOS capacitor compared with the calculated curve; (b) Current density vs voltage (J-V) curve of a 3C-SiC MOS capacitor. The value of the ideal breakdown electric field is indicated by the dashed line.

In the following, the nanoscale electrical characterization of the bare surface and after the growth of a thin thermal oxide are reported. The CAFM metal tip (working as local Schottky contact) was preliminarily employed to probe the conduction on the bare surface, as illustrated in Fig. 3(a). Fig. 3(b) and (c) show the surface morphology and the current map, collected simultaneously with a tip bias . Under this forward polarization, preferential conductive paths are visible on the 3C-SiC bare material, such as the anti-phase boundaries (APBs), indicated as dotted curved lines, and stacking faults (SFs), indicated as straight dashed lines [8]. Furthermore, current maps collected at negative tip bias (not shown) revealed that APBs are the main conductive defects under reverse polarization. Interestingly, their distance is similar to the average value obtained from statistical analysis of macroscopic diodes.

Fig. 3(d) shows a schematic illustration of the CAFM setup on the -SiC system [9]. The morphology of the as-grown oxide (Fig. 3(e)) resembles the one of the bare 3C-SiC material, i.e., characterized by terraces separated by darker lines associated with the APBs. The surface roughness (RMS) was in the order of 5 nm , a value comparable to those measured directly on 3C-SiC layer before oxidation, demonstrating the conformal growth of the oxide onto the substrate, confirmed also by cross-section TEM analyses [9].

Fig. 3(f) reports the simultaneously collected current map by the positively biased conductive tip with . It can be considered as a breakdown map of an array of nano-MOS capacitors simultaneously stressed at . The BD events are not randomly distributed but there are some regions with a larger density, located in correspondence with some APBs. Noteworthy, the SFs were not visible in the case of 3C-SiC covered by thermal . The SCM experimental setup is illustrated in Fig. 3(g), whereas Fig. 3(h) and (i) show two representative images of the SCM signal amplitude and of the phase signal. In particular, both straight line features resembling SFs (dashed lines) and curved line features resembling APBs can be distinguished in the SCM amplitude image in Fig. 3(h), whereas only APBs features can be observed in the phase map in Fig. 3(i). The spatial variations in the SCM amplitude are related to local changes in the carrier density in the 3C-SiC layer.

Interestingly, Fig. 3(i) shows a strong change of the SCM phase signal from on APBs to on the surrounding regions indicating a local increase of the minority carriers (holes) concentration in the 3C-SiC material. Thus, the APBs may act also as a preferential sites for positive charges trapping. On the other hand, the presence of positively charged APBs can cause an enhanced electron injection from the semiconductor into the insulator and the preferential dielectric breakdown close to these extended defects. This can explain the reduced observed in large area MOS capacitors.

Fig. 3 (a) C-AFM setup for current mapping of , (b) surface morphology and (c) current map. (d) CAFM setup for current mapping of , (e) surface morphology and (f) current map. (g) SCM setup for surface carrier profiling of , maps of SCM amplitude (h) and phase (i) signal.

Fig. 3. (a) C-AFM setup for current mapping of , (b) surface morphology and (c) current map. (d) CAFM setup for current mapping of , (e) surface morphology and (f) current map. (g) SCM setup for surface carrier profiling of , maps of SCM amplitude (h) and phase (i) signal.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

Electrical characterization of Schottky and thermal-oxide junctions with showed non-idealities in the device behavior, e.g. high reverse leakage current in Schottky diodes and premature dielectric breakdown of MOS capacitors. Nanoscale electrical characterizations by CAFM and SCM allowed to shed light on the microscopic origin of these phenomena, by correlating the morphological features associated to crystalline defects with local current transport and carrier density.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

M. Zimbone and C. Bongiorno (CNR-IMM, Catania) are acknowledged for their contributions with TEM analyses. This work has been supported by the European project CHALLENGE (Call: H2020-NMBP-2016-2017, grant. agreement 720827).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.400.pdf

H. Nagasawa, M. Abe, K. Yagi, T. Kawahara, N. Hatta, phys. stat. sol. (b) 245, 1272 (2008)

M. Kobayashi, et al., Mater. Sci. Forum 679-680, 645 (2011)

F. Li, F. Roccaforte, G. Greco, P. Fiorenza et al., Materials 14, 5831 (2021).

J. Eriksson, M-H. Weng, F. Roccaforte, F. Giannazzo, et al., Appl. Phys. Lett. 95, 081907 (2009).

G. Fisicaro, C. Bongiorno, I. Deretzis, F. Giannazzo, et al., Appl. Phys. Rev. 7, 021402 (2020).

F. Li, Q. et al. IEEE Trans. Electr. Dev., 67, 237 (2020).

P. Fiorenza, et al. Nanotechnology 31, 125203 (2020)

F. Giannazzo, et al. Adv. Electron. Mater., 6, 1901171 (2020)

P. Fiorenza, et al. Appl. Surf. Sci. 526, 146656 (2020).

M. Zielinski, et al., Mater. Sci. Forum 924, 306 (2018).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 406-410

doi: 10.4028/p-sctxav

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-09

Accepted:
2022-03-10

Online:
2022-05-31

A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

The original version of this paper is available on https://www.scientific.net/MSF.1062.406.pdf

Hrishikesh Das , Swapna Sunkari , Joshua Justice and Danielle Hamann

ON Semiconductor, South Portland, Maine, USA

hrishikesh.das@onsemi.com, swapna.sunkari@onsemi.com, joshua.justice@onsemi.com, danielle.hamann@onsemi.com

Keywords: epitaxy, extended defects, crystal defects, classification, yield, reliability, electrical test, statistics

Abstract

The detection and classification of SiC Epitaxial extended defects was refined to separate out defective areas that influence device characteristics. Die level defect localization along with defect area calculations were performed on millions of die across product groups. A clear impact of non-killer defects was observed, especially with increasing density and defective area in the die. Specifically, all types of stacking faults caused higher leakage, lower blocking voltage, and increases in ON resistance and threshold leakage. Furthermore, MOSFET devices were affected to a much larger extent than diode devices. Testing die with higher numbers of defects provides insight on device reliability. Analyzing devices with specific counts of BPDs let us quantify the amount of bipolar degradation caused drift by product/voltage classes.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.406.pdf

Silicon Carbide is gaining rapid traction in the power electronics space. The highest volume drivers require high power density and efficiency, while maintaining ever increasing requirements on reliability, robustness, and stability over the system life. Concurrently, SiC substrates used to build these devices have over crystal defects even in good production-quality wafers. These substrate crystal defects further nucleate extended defects and crystal defects in the epitaxial layers. Squaring the requirements of reliability with the reality of the material quality, requires a very deep understanding of the SiC material and the fabrication process, as well as the influence these aspects have on the electrical performance including lifetime, stability, or drift. It is no longer sufficient to analyze defects and metrics on a wafer level . Attributes need to be analyzed on the die level, with sufficiently large volumes, to remove process variations. This work presents a framework to determine relevant attributes of die and assess the impact of various defects on electrical performance. This is done on a massive level of tens of millions of die to remove variations coming from the various processes steps.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.406.pdf

N-type epitaxial layers with a doping range between and were grown on off-cut substrates in a warm-wall multi-wafer CVD reactor. The epitaxial layers were characterized by a confocal microscope, the Lasertec SICA88, using a 313 nm excitation lamp. Defects were detected and classified using machine learning algorithms with surface topographic channels along with photoluminescence (PL) channels in the near infrared ( ). With the ability to now detect and classify the numerous non-killer crystal defects (NKDs) in SiC epitaxial layers with greater than purity, each defect can be traced to the corresponding fabricated die. Purity here is defined by the accuracy of the automatic defect classification and is determined by review. Each defect category was further split into defect areas that caused an effect on the devices and areas that do not cause any influence, iteratively. Additionally, the affected defective area caused by each defect was calculated for each die. These enhanced attributes were localized and aligned to the
affected die and such statistics were collected on 3 million die for each product (Diodes and MOSFETs). The effect of these attributes on electrical properties and reliability were analyzed.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.406.pdf

In our previous work [3], we explored statistically the consequence of defect presence in a die; the results on killer defects were very clear. The defect classified as killer defects had kill-rates of or more, as expected. In contrast, NKDs, including V-type defects/Partials and Stacking faults, had a minimal increase in the base kill-rate. Furthermore, an improved localization was developed, where the "dangerous" areas of each defect were identified. As a result, both the count of such defects and the corresponding defective area in each die were determined as shown in Fig. 1. ONSEMI's advanced manufacturing infra-structure seamlessly integrates datasets collected at crystal growth, epitaxy, and device fabrication as well as electrical test results from front-end and back-end stages. In addition, all information related to individual defects like classification, size, contrast, and exact coordinate are collected and stored. This eventually enables the analysis of devices with exact knowledge about type, location, and quantity of specific NKDs. In addition, due to run rates of MOSFETs and Diodes in mass production, large statistical quantities of million devices were analyzed, which provides excellent signal to noise ratio.

Figure 1. Shows the defect identification and then localization within a device die. Fig. 1a shows the identification of the relevant areas of a defect and Fig. 1b shows the localization/alignment of the defect on product die. Fig. 1c-1e shows how actual defective area is calculated when there are multiple and overlapping defects.

Figure 1. Figure 1. Shows the defect identification and then localization within a device die. Fig. 1a shows the identification of the relevant areas of a defect and Fig. 1b shows the localization/alignment of the defect on product die. Fig. 1c-1e shows how actual defective area is calculated when there are multiple and overlapping defects.

Fig. 2 shows the relationship between the kill-rate of the die (i.e. percentage of the die failing with the trend shown as a dashed line) and the number of the defects localized in that die. The secondary axis shows the absolute quantity of die that have those number of defects. The number of affected die decrease by orders of magnitude as the defect densities increase. Diodes and MOSFETs show vastly different sensitivity to NKDs, with MOSFETs being more susceptible to higher densities of Stacking faults. The kill-rate climbs slightly for the diodes to , while for the MOSFETs this rises to . This is attributed to additional yield failure modes like channel leakage. The combination of the distribution density and the effect on the die explains the relatively benign influence these defects have at low quantities but become harmful or "killer" at higher densities. The concept of a die failing depends on a variety of other factors, like process variations of the epi and fabrication and how close to the test specifications the die falls. The true gauge of the effect of the defects is the shift in the parametric test values.

Fig. 3 demonstrates the effect of the density of one NKD type, pure Stacking Faults, has on the electrical leakage and blocking characteristics of both diodes and MOSFETs. These stacking faults are classified as having no surface signatures or features. While the diodes are affected, the impact on the MOSFETs is more severe. There are also more modes of failure in MOSFETs [4]. While killer defects typically lead to hard shorts or excess forward or reverse leakage currents, devices which are affected by multiple NKD demonstrate wider parametric distributions of critical device parameters like breakdown voltages (BVDss), forward voltage ( ) or threshold voltage ( ).

Figure 2. Shows the effect of different densities of non-killer defects on 3 million each of 1200 V Diode and MOSFET die. The MOSFETs are much more sensitive and the kill-rate approaches at higher densities.

Figure 2. Figure 2. Shows the effect of different densities of non-killer defects on 3 million each of 1200 V Diode and MOSFET die. The MOSFETs are much more sensitive and the kill-rate approaches at higher densities.

Figure 3. Shows the degradation of performance as the number of SF per die increase. This eventually causes the die to fail the test limits. The x -axis denotes the bin grouping by defect count.

Figure 3. Figure 3. Shows the degradation of performance as the number of SF per die increase. This eventually causes the die to fail the test limits. The x -axis denotes the bin grouping by defect count.

Figure 4. Shows the sensitivity of RDS(ON) on the presence of BSF density in MOSFETs. The actual BSF defective area per die is also calculated and this shows a stronger trend on RDS(ON). This effect is not seen in Diodes.

Figure 4. Figure 4. Shows the sensitivity of RDS(ON) on the presence of BSF density in MOSFETs. The actual BSF defective area per die is also calculated and this shows a stronger trend on RDS(ON). This effect is not seen in Diodes.

Most extended defects nucleated in the epi are of similar size given the same thickness of the layer. As a result, the defect count can be a good proxy for the defective area. However, for some propagated defects like Bar Stacking Faults (BSF), the actual defect area in the die reflects the reality more accurately. Fig. 4 shows how the on-state resistance of a MOSFET (RDS(ON)) is affected by the presence of BSFs. It is important to also note that the scatter and variations around the secular trends are due to local variations in epi doping/thickness and lot/wafer fabrication variations. Accounting for those on the die level further tightens up the data.

The ability to selectively identify and pick die is very useful for testing the influence of defects on reliability. BPDs have triggered bipolar degradation in SiC MOSFETs, which is well documented in the literature [6,7]. Applying our targeted defect localization approach on epi wafers grown with high BPDs, chips were separated by the number of BPD's per chip among 1200 V and 1700 V rated devices with comparable die size. Body diode stress was applied in DC-mode with over multiple days. While threshold voltage remained stable throughout the stress, RDS(ON) increases, depending on the number of BPD's and the drift layer thickness. This effect is more prominent for 1700 V devices. The graphical result is shown in Fig. 5. Further details and results are to be published in [5].

Figure 5. RDS(ON) shift in percentage after body diode stress for MOSFETs in dependence of voltage class and BPDs per die. Bias and stress conditions are provided. Stress time varies depending on the time needed for RDSon drift to saturate. Similar tend is seen in Pulsed stress tests.

Figure 5. Figure 5. RDS(ON) shift in percentage after body diode stress for MOSFETs in dependence of voltage class and BPDs per die. Bias and stress conditions are provided. Stress time varies depending on the time needed for RDSon drift to saturate. Similar tend is seen in Pulsed stress tests.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.406.pdf

In summary, this work demonstrates the accurate identification of defective areas of extended defects in SiC epitaxial layers and their alignment and localization to product die. This enables very powerful techniques to gauge the effect of defective area density on device performance and reliability. This allows a deeper assessment of the impact the crystal and extended defects have on the devices as well as quantifies the impact of higher NKD density per die. This also provides for targeting of specific die for reliability to quantify potential failure thresholds and amount of parametric drifts.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.406.pdf

H. Das, S. Sunkari, J. Justice, H. Pham and K.S. Park, Mater. Sci. Forum, 963, pp 284-287, (2019)

E. Van Brunt, A. Burk, D. J. Lichtenwalner, R. Leonard, S. Sabri, A. Gajewski, A. Mackenzie, B. A. Hull, S. Allen, and J. W. Palmour. Mater. Sci. Forum, 924, pp 137-142, (2018)

H. Das, S. Sunkari, J. Justice, H. Pham, G. Park, and Y. Seo, Materials Science Forum, 1004, pp. 458-463, (2020)

T. Neyer, M. Domeij, H. Das, and S. Sunkari, 2021 IEEE International Reliability Physics Symposium (IRPS), pp. 1-6, (2021)

S. Kochoska, M. Domeij, S. Sunkari, J. Justice, H. Das, T. T. Pham, J. Franchi, S. Maslougkas, H. Lee, X. Q. Hu, and T. Neyer, To be presented the ECSCRM 2021 Conference, Tours, France.

M. Skowronski, and S. Ha, J. Appl. Phys., vol. 99, no. 1, pp. 011101-1-011101-24, Jan. 2006.

T. Ishigaki, T. Murata, K. Kinoshita, T. Morikawa, T. Oda, R. Fujita, K. Konishi, Y. Mori, and A. Shima. Proc. 2019 31st International Symposium on Power Semiconductor Devices & ICs pp. 259-262.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 411-416

doi: 10.4028/p-ia5ez8

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-24

Accepted:
2022-02-28

Online:
2022-05-31

Ni/Heavily-Doped 4H-SiC Schottky Contacts

The original version of this paper is available on https://www.scientific.net/MSF.1062.411.pdf

Marilena Vivona , Giuseppe Greco , Salvatore Di Franco , Patrick Fiorenza , Filippo Giannazzo , Antonino La Magna and Fabrizio Roccaforte

CNR-IMM, Strada VIII n. 5 Zona Industriale, I-95121, Catania, Italy

marilena.vivona@imm.cnr.it, giuseppe.greco@imm.cnr.it, salvatore.difranco@imm.cnr.it, patrick.fiorenza@imm.cnr.it, fabrizio.roccaforte@imm.cnr.it

Keywords: heavily-doped 4H-SiC, ion-implantation, thermionic field emission, Schottky diode

Abstract

In this work, we focus on the electrical characterization of Ni Schottky contact on n-type heavily doped 4H-SiC layer, achieved by P-ion implantation. In particular, the forward current-voltage characterization of Schottky diodes showed a reduced turn-on voltage for the Ni /heavily-doped if compared to a reference Schottky contact fabricated under similar conditions but without implant. Moreover, it was observed the predominance of a thermionic-field-emission (TFE) mechanism for the current transport through the interface. From a current-voltage-temperature (I-V-T) study, the temperature-dependence of the Schottky barrier and doping concentration were evaluated, obtaining a reduction of the barrier (from 1.77 to 1.66 eV ), while the doping concentration maintains constant around . This study provides useful insights for a deeper comprehension of the electrical behavior of Ni contacts and can have possible applications in 4H-SiC Schottky diode technology.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.411.pdf

Nowadays, 4H-SiC-based devices such as Schottky barrier diodes (SBDs) and metal-oxidesemiconductor field effect transistors (MOSFETs), have reached a high technological maturity and performances (low on-state voltage drop, high switching speed, high breakdown voltage, high temperature operation, etc.), and they can be largely employed in several applications [1]. In spite of the huge progresses, there are still margins of performance improvement associated to the optimization of the metal/semiconductor contact characteristics. Generally, the Schottky barrier properties are driven by an appropriate choice of metal (e.g., low work-function metals, tunable compositions, etc.), suitable semiconductor surface treatments or intentionally changing of the electric field distribution below the interface [2-4]. In this context, many efforts have been dedicated to the basic understanding of the current transport in metal/semiconductor contacts in both lightly and heavily doped epitaxial layers, to achieve a good control of the properties of this system. While several literature works are devoted to the characterization of Schottky contacts on lightly doped , basic studies on metal/heavily-doped SiC interfaces have been rather limited so far, in spite of the importance of these systems for the development of SiC devices (e.g. in Ohmic contact regions). In a recent work, Hara et al. [5] characterized Schottky diodes fabricated on 4H-SiC epitaxial layers with a doping concentration varying from up to , observing a reduction of the barrier height and an increasing dominance of a thermionic field emission (TFE) mechanism for the current transport with increasing the epilayer doping.

Specifically, heavily doped layers can be obtained by ion-implantation, which is an essential process for both n -type and p -type selective doping [6]. For instance, metal/semiconductor contacts with Ohmic properties can be obtained on heavily-doped implanted regions by Ni based films annealed at high temperature, owing to the formation of nickel silicide ( ), as occurring in junction barrier Schottky (JBS) rectifiers technology, where ion-implantation is typically used for selective doping of -type regions [7].

In this work, we focused on the electrical characterization of Ni Schottky contacts onto heavily doped n-type phosphorus-implanted 4 H -SiC layer, under forward bias. Specifically, the Schottky properties and the dominant current transport mechanism were highlighted by a detailed electrical characterization of the contact.

Experimental Details

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N-type epitaxial layer with nitrogen doping of , grown onto a heavily doped substrate, was the starting material of our work. The upper part of the epitaxial layer was heavily doped by phosphorus (P)-ion-implantation at , at energies ranging from 30 to 200 keV and with ion doses between and . The resulting implantation profile extended over 200 nm and with a concentration peak of , as confirmed by previous secondary ion mass spectrometry (SIMS) measurements [8]. A postimplantation thermal annealing treatment, performed at in Ar-ambient and with a carbon capping layer for protecting the sample surface, was able to activate at least of implanted P-ion, as highlighted in Fig.1, which reports the comparison between the SIMS profile

Fig.1: Comparison between the chemical P-profile obtained by SIMS (right scale) and electrically active P profile derived by SCM (left scale).

Fig.1. Comparison between the chemical P-profile obtained by SIMS (right scale) and electrically active P profile derived by SCM (left scale).

Results and Discussion

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As starting point, in Fig. 2 we compared the room-temperature forward current density-voltage characteristics of Ni Schottky contacts formed on n-type heavily-doped 4H-SiC epilayer and on a reference epilayer without doping implantation. Evidently, the Ni /heavily doped contact exhibited a lower turn-on voltage with respect to the reference contact without implant [12].

Fig.2: J-VF curves of Ni Schottky contacts on n-type 4H-SiC epilayer with or without n-type implant. In the inset, the same curves in semilog scale.

Fig.2. J-VF curves of Ni Schottky contacts on n-type 4H-SiC epilayer with or without n-type implant. In the inset, the same curves in semilog scale.

Typically, the forward characteristics for Schottky contact to can be described by the thermionic emission (TE) model [13], with relationship expressed as

where is the effective Richardson's constant of is the elementary charge, is the Schottky barrier, is the Boltzmann's constant, is the absolute temperature, is the voltage applied across the metal/semiconductor interface, is the specific on-resistance and is the ideality factor. In particular, by analyzing the forward characteristic using the TE model, we derived a barrier height of 0.94 eV and an ideality factor of 1.8 , thus showing a high discrepancy from the ideal case for Schottky contact with .

Fig.3: Schematic energy band diagram for the TFE mechanism in a metal/heavily-doped contact under forward bias.

Fig.3. Schematic energy band diagram for the TFE mechanism in a metal/heavily-doped contact under forward bias.

Hence, the current transport through the contact cannot be described by a TE regime. As matter of fact, considering the high doping concentration of the implanted region, a tunneling contribution to the current must be taken into account, as described by the thermionic field emission (TFE) model [15] (Fig.3). The TFE J-V relationship is given by

where the saturation current can be expressed as

with the difference between the bottom of the conduction band and the semiconductor Fermi level, and , where the effective mass ( is the electron mass) and the dielectric constant of the semiconductor ( is the vacuum permittivity).

Fig.4: Experimental room-temperature J-VF curve (open symbols) for Ni/heavily doped Schottky diode and fitting curve according to the TFE model (continuous line).

Fig.4. Experimental room-temperature J-VF curve (open symbols) for Ni/heavily doped Schottky diode and fitting curve according to the TFE model (continuous line).

Fig. 4 reports in a semilog scale the experimental room-tempertaure curve related to a representative diode on heavily doped layer, fitted to a simulated TFE curve. The barrier and the doping concentration were determined as best-fit parameters of the TFE curve, obtaining and . Notably, the ratio gives an indication about the relevance of the TE process with respect to the tunneling one. Using derived from the fit, we obtained a ratio of 0.61 , which confirmed the appropriateness of the TFE model [16]. By knowing the doping concentration, the depletion width at the interface can

Fig.5: Experimental forward curves for -type implanted Schottky diode at T varying from 25 to .

Fig.5. Experimental forward curves for -type implanted Schottky diode at T varying from 25 to .

was found over the measurement temperature range. This latter agrees with SCM profiling measurement related to the electrically active P -ion concentration underneath the interface and with Hall measurements that in the same range of temperature gave an almost constant value for the average carrier concentration over the entire implanted thickness.

Fig.6: T-dependence of and doping concentration, derived by the TFE fits of the forward curves.

Fig.6. T-dependence of and doping concentration, derived by the TFE fits of the forward curves.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.411.pdf

In conclusion, we have electrically characterized Ni Schottky contact on n-type-implanted layer, with doping concentration . This ion-implantation doping produced a reduced forward turn-on voltage in the heavily-doped diode with respect to a reference one. The thermionic-field-emission was the dominant mechanism for the current transport through the interface under forward bias. The temperature analysis of the forward current-voltage curves highlighted a reduction of the Schottky barrier (from 1.77 to 1.66 eV ), while the doping concentration maintained constant around , in the investigate temperature range . This study provides useful insights for a deeper comprehension of the electrical behavior of Ni contacts and can have possible applications in 4H-SiC Schottky diode technology.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.411.pdf

The authors would like to acknowledge STMicroelectronics for providing 4H-SiC implanted samples. The European ECSEL JU project REACTION (Grant Agreement No. 783158) is also acknowledged.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.411.pdf

X. She, A. Q. Huang, O. Lucìa and B. Ozpineci, IEEE Trans. Ind. Electron. 64 (2017) 8193.

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A. B. Renz, V. A. Shah, O. J. Vavasour, Y. Bonyadi et al., J. Appl. Phys. 127 (2020) 025704.

F. Roccaforte, C. Bongiorno, F. La Via and V. Raineri Appl. Phys. Lett. 85 (2004) 6152.

M. Hara, S. Asada, T. Maeda and T. Kimoto, Appl. Phys. Express 13 (2020) 041001.

F. Roccaforte, P. Fiorenza, M. Vivona, G. Greco, F. Giannazzo, Materials 14 (2021) 3923.

R. Pérez, N. Mestres, M. Vellvehi, P. Godignon et al., Semicond. Sci. Technol. 21 (2006) 670.

A. Severino, D. Mello, S. Boninelli, F. Roccaforte et al., Mater. Sci. Forum 963 (2019) 407.

M. Spera, G. Greco, A. Severino, M. Vivona et al., Appl. Phys. Lett. 117 (2020) 013502.

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M. Vivona, G. Greco, F. Giannazzo et al., Semicond. Sci. Technol. 29 (2014) 075018.

M. Vivona, G. Greco, M. Spera, P. Fiorenza et al., J. Phys. D: Apl. Phys. 54 (2021) 445107.

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M.S. Sze, K. Ng. Kwok, Physics of Semiconductor Devices; John Wiley & Sons, USA, 2007.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 417-421

doi: 10.4028/p-x34i2i

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-19

Revised:
2022-02-25

Accepted:
2022-02-28

Online:
2022-05-31

Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

The original version of this paper is available on https://www.scientific.net/MSF.1062.417.pdf

Paolo Badalà , Emanuele Smecca , Simone Rascunà , Corrado Bongiorno , Egidio Carria , Anna Bassi , Gabriele Bellocchi , Silvia Castorina , Cristina Tringali , Antonino La Magna and Alessandra Alberti

STMicroelectronics, Zona Industriale Stradale Primosole, 50-95121 Catania, Italy

CNR-IMM, Zona Industriale Strada VIII, 5-95121 Catania, Italy

paolo.badala@st.com, emanuele.smecca@imm.cnr.it, simone.rascuna@st.com,

corrado.bongiorno@imm.cnr.it, egidio.carria@st.com, gabriele.bellocchi@st.com, silvia.castorina@st.com, cristina.tringali@st.com,

Abstract

Laser annealing process for ohmic contact formation on has attracted increasing attention in the last years, because it enables the fabrication of SiC power devices on very thin substrates. We have investigated the formation of Nickel-based ohmic contact on by using a Yb :YAG laser in scanning mode, with a wavelength of 515 nm and a pulse duration of 1200 ns . A 100 nm thick Ni layer has been deposited on SiC and irradiated at different process conditions. The reaction process has been studied, as a function of fluence and scan number of laser annealing, by means of X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM) analyses. The electrical properties of the annealed layers have been evaluated on Schottky Barrier Diodes (SBDs) devices, confirming the ohmic behavior of the reacted contact and showing improved performances respect to RTA approach. The compatibility of thermal budget of the process in the front side has been verified by means of process simulation. A strong relationship between structural properties of reacted layers and electrical behavior of SBDs devices has been revealed. Solid-state laser annealing process, with wavelength in green light region, can indeed represent a suitable solution for ohmic contact formation of power devices, fabricated on thin substrates.

Introduction

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Silicon Carbide has attracted increasing attention in the last years as suitable material for power devices [1] and sensors [2]. For power electronics, wafer thinning is assuming a crucial role in ONResistance ( ) reduction, but it is demanding at the same time for a new manufacturing approach able to skip the Rapid Thermal Annealing (RTA) process [3]. Among the alternative processes to RTA already demonstrated for Si [4-7], laser annealing seems to be the most promising for ohmic contact formation on SiC [8]. In particular, the use of UV excimer laser annealing for Nickel-based ohmic contact formation on SiC has been widely studied and reported in literature [9-11]. However, alternatives in terms of pulse duration and wavelength could offer additional process option and a wider process window. The formation of Ni-based ohmic contact on has been investigated by using a Yb:YAG laser in scanning mode. Morphological and structural properties of reacted layers have been studied by means of XRD and TEM analyses. Laser process simulations have been performed to predict the temperature field at the wafer scale. Schottky Barrier Diodes (SBDs) have been studied to evaluate the electrical behavior of the annealed layer.

Experimental Setup

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SBD devices have been fabricated on substrates, mechanically grinded at of thickness. A 100 nm thick Ni layer has been deposited on grinded SiC surface by DC sputtering in Ar ambient at a base pressure of . Ni layer has been annealed by Yb : YAG laser in scanning mode, with wavelength of 515 nm , pulse duration of 1200 ns , scan speed of and frequency of 10 kHz , with fluence in the range between and . The laser beam had a top hat profile on the long dimension ( 3 mm ) and a gaussian profile on the short dimension ( ). Overlap between two consecutive annealing lines on the long dimension has been tailored to obtain single, double or triple scan. Morphological and structural properties of reacted layers have been studied by XRD analysis, using a Bruker AXS D8 DISCOVER diffractometer working with a Cu source, and by TEM analysis, using a JEOL-JEM microscope working at 200 keV . SBD devices have been evaluated by using a semiconductor device parameter analyzer (Agilent B1500A) and a high-power curve tracer (Sony Tektronix 371A). As a reference for electrical evaluation, SB diodes have been fabricated on thinned substrate, by using standard RTA process ambient) for Ni silicide-based ohmic contact formation.

Results and Discussion

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XRD analyses have been performed in symmetric and grazing incidence configurations to get information on structural properties of the reacted layers. Fig. 1a shows XRD patterns collected in symmetric configuration on three different samples annealed at of fluence, changing the scanning condition to obtain single, double or triple irradiation on the same area. All the three samples show the presence of phase and the absence of un-reacted Ni . For triple scan annealing, a shift of the peak at to the left with respect to the peak is observed, due to the co-existence of and NiSi phases, stating for a shift of the reaction towards Si -rich phases with the increasing of scan number. Fig. 1b shows XRD patterns collected in grazing incidence configuration, with an incidence angle of , on Ni samples annealed at of fluence, with single and triple scan. In this configuration, the penetration depth is limited to a range of , depending on layer composition. peaks are observed for single scan annealed samples, while peaks are observed for both samples as residuals of reaction, stating for a compositional gradient along reacted layer depth profile.

Fig. 1. (a) XRD patterns in symmetric configuration of the Ni samples annealed at of fluence for single, double and triple scan process. With increasing of scan number, a shift towards Si rich phases is observed. (b) XRD patterns in grazing incidence configuration of the Ni samples annealed at of fluence for single and triple scan process. peaks are observed in both samples.

Fig. 1. (a) XRD patterns in symmetric configuration of the Ni samples annealed at of fluence for single, double and triple scan process. With increasing of scan number, a shift towards Si rich phases is observed. (b) XRD patterns in grazing incidence configuration of the Ni samples annealed at of fluence for single and triple scan process. peaks are observed in both samples.

Fig. 2 shows XRD patterns collected in symmetric configurations on samples annealed with double scan at different fluences in the range between 5 and , compared with a standard pattern from RTA-treated samples. peaks are observed for all three laser annealed samples. For lower fluence ( 5 and ), the peak at is slightly shifted with respect to the peak, likely due to film stress.

Cross sectional Scanning Transmission Electron micrographs of the Ni sample annealed with double scan approach at of fluence, reported in Fig. 3, show a continuous 150 nm thick Ni silicide, without any embedded carbon clusters. All the carbon atoms were segregated in a continuous layer placed close to the interface with the SiC substrate. Any residual un-reacted Ni was observed at the surface. It is worth to be noticed that such concentration of segregated carbon could be detrimental for mechanical robustness of power devices because their shear strength is reduced.

Fig. 2. XRD patterns in symmetric configuration of Ni samples annealed at different fluences with double scan process, compared with standard RTA pattern. peaks are observed for all three laser annealed samples.

Fig. 2. XRD patterns in symmetric configuration of Ni samples annealed at different fluences with double scan process, compared with standard RTA pattern. peaks are observed for all three laser annealed samples.

Fig. 3. Cross sectional High Angle Annular Dark Field (HAADF) STEM images of the Ni sample annealed with double scan at , showing a continuous carbon layer close to the interface between SiC substrate and reacted layer (a) and the absence of segregated carbon outside of this region (b).

Fig. 3. Cross sectional High Angle Annular Dark Field (HAADF) STEM images of the Ni sample annealed with double scan at , showing a continuous carbon layer close to the interface between SiC substrate and reacted layer (a) and the absence of segregated carbon outside of this region (b).

Fig. 4. Forward voltage ( ) of diode at nominal current as a function of fluence and scan number of laser annealing process, compared with standard RTA results. Increasing of fluence and multiple scan play a crucial role in reduction.

Fig. 4. Forward voltage ( ) of diode at nominal current as a function of fluence and scan number of laser annealing process, compared with standard RTA results. Increasing of fluence and multiple scan play a crucial role in reduction.

The electrical properties of the reacted layers have been evaluated on power devices. The forward voltage ( ) of Schottky Barrier diodes at nominal current is reported in Fig. 4 as a function of fluence and scan number of laser annealing process. As a reference, the of a SB diode annealed with standard RTA approach ( ) is shown. Single scan annealing at of fluence results in higher than RTA reference ( ), while double scan process at the same fluence gives values comparable with RTA. If we consider the difference of substrate thickness, i.e. for laser annealing and for RTA, we can conclude that in both cases the quality of ohmic contact formed by laser is worse than the reference, as expected by considering structural properties shown in Fig. 1. SB diodes annealed with double scan approach at of fluence show values lower with respect to the reference diodes annealed by RTA ( ). This improvement is in line with thickness difference between the two approaches. Process simulation [9] demonstrates that the thermal budget in the device region (front) for the laser process is below the one induced by the conventional RTA process for all the cases here considered.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.417.pdf

Ni-based ohmic contact formation on by Yb : YAG laser annealing has been investigated. A strong relationship between structural properties of reacted layers and electrical behavior of SBDs devices has been discussed, showing that they can be properly tuned through the calibration of scan number and fluence of laser annealing process. Based on these results, solid-state laser annealing could represent a valuable solution for ohmic contact formation on thin wafers.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.417.pdf

The authors thank the project MADEin4 (Metrology Advances for Digitized Electronic Components and Systems Industry 4.0) that has received funding from the ECSEL-JU under grant agreement No 826589.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.417.pdf

F. Roccaforte, P. Fiorenza, G. Greco, R. Lo Nigro, F. Giannazzo, F. Iucolano, M. Saggio, Emerging trends in wide band gap semiconductors (SiC and GaN) technology for power devices, Microelectron. Eng. 187 (2018) 66-77.

M. Mazzillo, A. Sciuto, G. Mannino, L. Renna, N. Costa, P. Badalà, Towards a high performing UV-A sensor based on Silicon Carbide and hydrogenated Silicon Nitride absorbing layers, Journal of Instrumentation, 11 (2016) P10010.

S. Rascunà, P. Badalà, C. Tringali, C. Bongiorno, E. Smecca, A. Alberti, S. Di Franco, F. Giannazzo, G. Greco, F. Roccaforte, M. Saggio, Morphological and electrical properties of Nickel based Ohmic contacts formed by laser annealing process on n-type 4H-SiC, Materials Science in Semiconductor Processing, 97 (2019) 62-66.

A. Alberti, P. Badalà, G. Pellegrino, A. Santangelo, Structural and electrical characterization of silicided Au contacts formed at low temperature ( ) on p-type [001] silicon, J. Appl. Phys., 110 (2011) 123510.

P. Badalà, A. Santangelo, G. Pellegrino, A. Alberti, Silicided Au/Ni bilayer on p-type [001] silicon for low contact resistance metallization schemes, Microelectronic Engineering, 107 (2013) 196-199.

P. Badalà, G. Faro, C. Marcellino, G. Pellegrino, A. Santangelo, A. Alberti, Structural characterization of in-situ silicided contacts textured on p-type [001] silicon, Phys. Status Solidi C, 11 (2014) 160-163.

A. Alberti, P. Badalà and A. Santangelo, U.S. Patent 9,728,412 (2017).

Z. Zhou, W. He, Z. Zhang, J. Sun, A. Schöner, Z. Zheng, Characteristics of Ni-based ohmic contacts on n-type 4 H -SiC using different annealing methods, Nanotechnol. Precis. Eng., 4 (2021) 013006.

P. Badalà, S. Rascunà, B. Cafra, A. Bassi, E. Smecca, M. Zimbone, C. Bongiorno, C. Calabretta, F. La Via, F. Roccaforte, M. Saggio, G. Franco, A. Messina, A. La Magna, A. Alberti, Ni/4H-SiC interaction and silicide formation under excimer laser annealing for ohmic contact, Materialia, 9 (2020) 100528.

S. Sanzaro, C. Bongiorno, P. Badalà, A. Bassi, G. Franco, P. Vasquez, A. Alberti, A. La Magna, Inter-diffusion, melting and reaction interplay in under excimer laser annealing, Applied Surface Science, 539 (2021) 148218.

S. Sanzaro, C. Bongiorno, P. Badalà, A. Bassi, I. Deretzis, M. Enachescu, G. Franco, G. Fisicaro, P. Vasquez, A. Alberti, A. La Magna, Simulations of the ultra-fast kinetics in Ni-Si-C ternary systems under laser irradiation, Materials 14 (2021) 4769.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 422-426

doi: 10.4028/p-tqug9l

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-25

Accepted:
2022-03-17

Online:
2022-05-31

Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

The original version of this paper is available on https://www.scientific.net/MSF.1062.422.pdf

Collin Hitchcock , Reza Ghandi , Peter Deeb , Stacey Kennerly , Mohamed Torky , T. Paul Chow

GE Research, 1 Research Circle, Niskayuna, NY 12309, USA

Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180, USA

Collin.Hitchcock@ge.com, Ghandi@ge.com, Peter.Deeb@ge.com, Stacey.Kennerly@ge.com, torkym@rpi.edu, chowt@rpi.edu

Keywords: Superjunction Diode, Temperature Dependent Hall Effect, Capacitance-Voltage, Incomplete Ionization, Aluminum Activation, Aluminum Acceptor Ionization Energy

Abstract

MeV level aluminum implants into were performed as part of superjunction diode fabrication. Measurement of resistance test structures produced resistivities well above expected values with large decreases at elevated temperatures. Capacitance-voltage measurements indicate a high activation rate of the implanted aluminum. Temperature dependent Hall measurements produce reasonable hole mobilities with acceptor ionization energies of approximately 330 meV , well above the 200 meV expected for low concentration aluminum doping in .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.422.pdf

Aluminum is a deep acceptor in 4H silicon carbide with a generally accepted ionization energy of approximately 200 meV for low doping concentrations. The ionization energy is known to decrease with increasing dopant concentration to below 100 meV at concentrations near the solubility limit . There are indications that, at low acceptor concentrations, the ionization energy exceeds the 200 meV generally accepted value [3-7]. Here, we study MeV-level, ultra-high energy (UHE) aluminum implants utilized for p -pillar formation in superjunction (SJ) devices.

Experimental Samples

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Starting with n -type, thick epitaxial layers grown on -SiC substrates, SJ p-pillars and n-pillars were fabricated using masked UHE implants of aluminum and nitrogen respectively. Multiple implants with varying energies were performed targeting a net uniform doping concentration throughout the entire deep epitaxial region [8]. After additional lower energy p-type implantations to form diode anodes and edge termination structures, dopants were activated at anneal conditions ranging from 1700 to . Subsequent processing resulted in vertical p-n SJ diodes. Details of the diode fabrication and performance can be found elsewhere in these proceedings [9].

In addition to the diodes, a number of test structures were co-fabricated on-wafer in order to validate the fabrication processes and to delineate the specifics of device performance. Transmissionline structures (TLMs) and Van der Pauw structures (VDPs) allowed for contact and sheet resistance measurements of implanted layers. Along with purpose-fabricated Hall bars, the VDPs were also used for Hall effect measurements to determine the free carrier concentration and mobility. Finally, a number of diode structures with large area, single-type pillar doping through the entire drift region were available in both n -type and p -type versions for electrical testing of the bulk implanted layers.

Experimental Results

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Resistivities extracted using the p-pillar TLMs and VDPs are shown in Table 1 as a function of activation anneal temperature and measurement temperature. Room temperature results are much higher than expected, with calculated free hole concentrations of between and (assuming hole mobility for this resistivity measurement only) and a corresponding active ionized acceptor ratio of only about of the implanted dose. Also, as illustrated in Table 1, resistivity decreased by an order of magnitude as temperature increased from room temperature to , with free hole concentrations rising to between and (assuming hole mobility for this resistivity measurement only). There was no significant dependence of the measured resistivity on the activation anneal temperature. Since a 200 meV Al acceptor ionization energy results in roughly ionization at room temperature, an ionized acceptor increase of an order of magnitude with temperature should not possible.

Table 1: Sheet resistances of p-pillar implanted regions

Activation Anneal | VDP 25°C (Ω) | TLM 25°C (Ω) | VDP 200°C (Ω) | TLM 200°C (Ω)
1700°C, 30 min | 4.2×10⁵ | 4.27×10⁵ | 3.8×10⁴ | 3.89×10⁴
1800°C, 120 min | 4.5×10⁵ | 4.56×10⁵ | 3.7×10⁴ | 3.84×10⁴
1900°C, 60 min | 4.7×10⁵ | 4.65×10⁵ | 3.7×10⁴ | 4.10×10⁴
2000°C, 40 min | 5.0×10⁵ | 4.57×10⁵ | 3.7×10⁴ | 3.85×10⁴

Fig. 1 illustrates the results of capacitance-voltage (CV) measurements taken on large area ppillar implanted regions. Since the applied DC bias will field-ionize dopants that are incompletely ionized under equilibrium conditions, this technique will measure total activated implant doses. Fig. 1a shows the CV test structure schematically; as DC bias increases, the bottom portion of p-pillar region adjacent to the n-type substrate is probed. Raw CV curves are shown in Fig. 1b, and the differential doping extraction shown in Fig. 1c indicates a near constant active dopant concentration very close to the implanted dose throughout the probed region directly above the substrate surface. Fig. 1d indicates that the probed region extends approximately into the p-pillar region from the substrate interface. Table 2 shows median differential extracted dopings for all 4 activation anneal temperatures taken both at room-temperature and at ; detailed curves for the measurement temperature are qualitatively similar to those in Fig. 1. All extracted acceptor concentrations are close to the implanted value. An example CV of a full SJ diode, implementing both n-pillar and p-pillars, is shown in Fig. 2. No appreciable unexpected differences between CV curves taken at AC frequencies between 1 kHz and 1 MHz were observed. The near full-implant level hole concentrations measured by CV independent of temperature and frequency further point to lower-than-expected ionization of the aluminum dopant.

Hall effect measurements were performed using two different systems. Low noise measurements were obtained measuring p-pillar VDPs between and using a Lake Shore Hall effect system equipped with a cryogenic cold head and electromagnets capable of . Additionally, p-pillar Hall bars were measured on a second system at a fixed, reversable field of 4.8 kG and employing a localized package heating system from room temperature up to . Measured carrier concentrations for all four activation anneal conditions are shown in Fig. 3 on an Arrhenius style plot along with theoretical curves fitted to experiment by adjusting unknown parameters; Hall mobilities are inset at the lower left. Hall scattering factor was assumed to be unity for all analyses. As with the resistance and CV measurements, there were no significant differences between experimental Hall measurement results for any of the experimental activation anneal temperatures. Theoretical Hall curves were generated in a spreadsheet by iterative numerical solution of the Fermi-Dirac occupancy of the valence band and acceptor states. Parameters for the theoretical

Fig. 1: Capacitance-Voltage Measurements ( AC signal) of p-pillar test structures (results for approximately 25 structures at each anneal temperature) (a) Schematic CV test structure, (b) Raw capacitance measurement, (c) Extracted doping as a function of bias voltage, (d) Extracted measurement location (depth into the p-type implanted region from the implant/substrate interface).

Fig. 1. Capacitance-Voltage Measurements ( AC signal) of p-pillar test structures (results for approximately 25 structures at each anneal temperature) (a) Schematic CV test structure, (b) Raw capacitance measurement, (c) Extracted doping as a function of bias voltage, (d) Extracted measurement location (depth into the p-type implanted region from the implant/substrate interface).

Table 2: CV Extracted Median Acceptor Concentrations for P-Pillar UHE Implanted Test Structures.

Anneal, Measured Temp
25°C
(cm⁻³)
200°C
(cm⁻³)

1700°C
1.09×10¹⁶
1.06×10¹⁶

1800°C
1.12×10¹⁶
1.05×10¹⁶

1900°C
1.02×10¹⁶
1.02×10¹⁶

2000°C
1.04×10¹⁶
1.03×10¹⁶

Fig. 2: 25 mV CV measurements of diodes as a function of AC frequency.

Fig. 2. 25 mV CV measurements of diodes as a function of AC frequency.

curves are the total active acceptor concentration, the ionization energy of the acceptor level, and the ratio of compensation by n-type dopants and defects (which are assumed to be at a sufficient energy above the acceptor level to be ionized). Additionally, structures (shown for reference) are well fit by a 70 meV ionization energy curve, consistent with theory.

In the low temperature freeze-out region, where carrier concentration is independent of active acceptor concentration, the best fit to experiment is obtained with an acceptor energy of 330 meV and a compensation ratio of . Comparing experiment to theoretical curves with a compensation ratio of the minimum reasonable value of (based on initial epitaxial doping) produces a reasonable fit assuming an acceptor energy of 350 meV , and examining increased compensation ratios allows a fit at up to compensation and 290 meV before the slope of the experimental curve diverges significantly from the theory and the horizontal asymptote of the experimental curve in the high temperature region begins to converge above the implanted acceptor dose.

Fig. 3. Hall mobile hole concentration and 330 meV ionization energy theoretical curves with varying active dopant doses and compensation ratios for UHE implanted p-pillar regions. Hall mobilities ( ) as a function of anneal and measurement temperatures are inset at lower left.

Fig. 3. Hall mobile hole concentration and 330 meV ionization energy theoretical curves with varying active dopant doses and compensation ratios for UHE implanted p-pillar regions. Hall mobilities ( ) as a function of anneal and measurement temperatures are inset at lower left.

Conclusion

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Based on CV-measured acceptor concentrations very close to the implanted dose (independent of frequency and temperature), we conclude that UHE implants of aluminum at the level are close to activated at all experimental activation anneal conditions. Based on the temperature dependent resistance structure measurements combined with the behavior of temperature-dependent Hall measurements, we conclude that these implants result in acceptor ionization energies significantly higher than accepted low-doping values, with values between 290 meV and 350 meV . Since similar recent results in the literature report good high temperature Hall fits of moderate Al implanted layers with activation by assuming partial activation into an additional, high ionization energy acceptor level [7], we postulate that low dose implanted Al is activated at least partially on an alternate SiC lattice site resulting in a higher effective acceptor ionization energy.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.422.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DEAR0001007. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.422.pdf

T. Kimoto and J. Cooper, Fundamentals of Silicon Carbide Technology, 1st ed, (Wiley & Sons Singapore, 2014), p. 21

C. Darmody and N. Goldsman, J. Appl. Phys. 126, 145701 (2019).

J. Weisse, M. Hauck, T. Sledziewski, M, Tschiesche, M. Krieger, A. Bauer, H. Mitlehner, L. Frey, and T. Erlbacher, Mat. Sci. Forum 924, 184 (2018).

T. Troffer, M. Schadt, T. Frank, H. Itoh, G. Pensl, J. Heindl, H. P. Strunk, and M. Maier, Phys. Stat. Sol. (a) 162, 277 (1997)

N. Saks, A. Agarwal, S-H. Ryu, and J. Palmour, J. App. Phys. 90, 2796 (2001)

H. Matsuura, Mat. Sci. Forum, 389-393, 679 (2002)

J. Weisse, M. Hauck, M. Krieger, A. Bauer, and T. Erlbacher, AIP Advances 9, 055308 (2019)

P. Thieberger, C. Carlson, D. Steski, R. Ghandi, A. Bolotnikov, D. Lilienfeld, and P. Losee, Nuclear Instruments and Methods in Physics Research Section B, 442, 36 (2019)

R. Ghandi, C. Hitchcock, and S. Kennerly, ECSCRM (2021)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 427-432

doi: 10.4028/p-ji5g71

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-21

Revised:
2022-03-15

Accepted:
2022-03-15

Online:
2022-05-31

Structural, Electronic and Optical Properties of 6H-SiC and 3C-SiC with the Application in Solar Cell Devices

The original version of this paper is available on https://www.scientific.net/MSF.1062.427.pdf

TAIBI Ibrahim , ABID Hamza

Applied Materials laboratory (AML), University Djiilali liabes of Sidi Belabbes, 22000 Sidi Belabbes, Algeria

Salhi Ahmed university centre Naama, Algeria

Abstract

H}-\mathrm{SiC}) and structural, electronic and optical properties have been calculated by applying the principles of density functional theory based on the plane wave pseudo-potential. This method is implanted in Wien2k Software. Structural parameters are calculated at the level of Perdew Burke and Ernzerhof (PBE) parameterized generalized gradient approximation (GGA). The obtained results given in Table I were compared to the experimental data in relation with the lattice constant hexagonal ration c/a and the band gap value parameters of and , there was a very accurate concordance.

The superior gap value and the good absorption coefficient drives us to realize a solar cell device using SILVACO Software. The 3C-SiC material resulted in a considerable performance for photovoltaic applications.

Introduction

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The SiC semiconductor as a excellent promising material for solar cells and electronic application, mainly for their high band gap, good chemical resistance and thermal conductivity . Record conversion efficiency up to has been reported in single-junction solar cells with thickness, and for tandem structure [3]. This present work proposes PIN structure based on Solar cells to calculate the current-voltage (J-V) characteristics and the internal quantum efficiency (IQE ( )).

Many authors investigated the SiC solar cells devices, Noor Alhuda et al., [4] have studied the Influence of Environmental Factors on the Performance of 3C-SiC PIN structure Solar Cells. They obtained Record conversion efficiency under 1000 W.m- Light intensity. The studies led by [5] single-junction solar cells based on material evaluated using a two-dimensional finite element method. The efficiencies of is obtained for of and thicknesses. Hamid Heidarzadeh et al. [6] they found an optimal efficiency for 3C-SiC achieved in under a 1000 suns concentration and AM1.5 spectrum irradiation. This work investigates and structural, electronic and optical properties with solar cell devices application. we can organize as follows; the first section focuses on structural, electronic, and optical properties results within the density functional theory. The second section 3C-SiC PIN solar cells structure proposed, to calculate photovoltaic parameters.

The First Section

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Computational methods. The functional density theory within the plane wave pseudo-potential approach as implemented in the WIEN2 code to calculate structural, electronic and optical properties, the Kohnsham equation were solved using (PBE-GGA) for the exchange correlation energy. Throughout our calculation is taken, where represents the smallest muffin tin radius of atoms ( and ), is the maximum value to the reciprocal
lattice vector used in the plane wave expansion. The potential and the charge density were Fourier expanded up to .
Structural, Band structure and optical properties. The crystal structure of and is hexagonal with space group P63mc (186). The Si atoms are located in 2b Wyckoff site with fractional coordinates ( ), and the C atoms are situated in 2 b Wyckoff site with fractional coordinates . The total energy has been calculated and minimized of 6 H -SiC and 3 C SiC to different cell volumes, Fig. 1 and Fig. 2 respectivly. The obtained results given in Table I were compared with results data reported in Reference [7,8] in relation with band gap , the lattice constant and hexagonal ratio c/a.

Fig 1. Total energies as a function of volume of .

Fig 1. Total energies as a function of volume of .

Fig 2. Total energies as a function of volume of 3C-SiC.

Fig 2. Total energies as a function of volume of 3C-SiC.

Table I. The Lattice constant, hexagonal ration c/a and band gap of 6H-SiC and 3C-SiC.

The and band structure is presented in Fig. 3 and Fig. 4. It is clear that the has a indirect band gap with the valence band maximum at G-point and the conduction band minimum locates at the M-point. Also has an indirect band gap with the valence band maximum at X -point and the conduction band minimum locates at the G -point, the calculated band gap for and are 2.015 eV and 1.37 eV respectively.

Fig 3. Band structure of .

Fig 3. Band structure of .

Fig 4. Band structure of .

Fig 4. Band structure of .

Fig 5. The dielectric function of .

Fig 5. The dielectric function of .

Fig 6. The absorption coefficient of 3C-SiC.

Fig 6. The absorption coefficient of 3C-SiC.

Fig. 5 shows dielectric function of 3C-SiC in theoretical calculation, in which the imaginary part of dielectric function contains high-energy zone from 5 to 12 eV , the imaginary part of dielectric function increases rapidly from 6.25 eV with dielectric peaks at 27.5 then decreases with the increase of energy as result the decreases of optical absorption of inter-band electron transition in Fig .6, the same behavior has been reported in Ref. [6]. We can show that the 3C-SiC is a good choice in solar cells application.

The Second Section

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The obtained results in the first section prompted us to study PIN solar cells based on 3C-SiC, the simulation have been carried out using ATLAS SILVACO software for the solution of two dimension, Poisson equation and the continuity equations for free charge carriers.

Where V is the electrical potential, is the permittivity, q is the elementary charge, p,n are the hole, electron concentrations respectively, the density of ionized acceptors and donors respectively. and are the electron and hole mobility. and are the electron and hole diffusion coefficient. R is the (SRH) recombination rate of free electrons and holes. The parameters used in the simulation are listed in Table 2. The solar cell is assumed to be operating under standard conditions, AM1.5 illumination spectrum and temperature . Fig. 7 and Fig. 8 shows the simulated current-voltage (J-V) characteristic and external quantum efficiency (EQE).

Table 2. Parameters used in the simulation at .

Parameter | Symbol | Value | Unit
band gap | Eg | 3.02 | eV
electron affinity | χ | 3.6 | eV
effective density of states | Nc,Nv | 2.10¹⁸ | cm⁻³
electron mobility | μn | 100 | cm²/V.s
hole mobility | μp | 320 | cm²/V.s
dielectric constant | ε | 4.9 |
Electron life time | τ⟨n⟩ | 30 | μ⟨s⟩
Hole life time | τ⟨p⟩ | 10 | μ⟨s⟩

Fig 7. Current density-voltage characteristic (J-V) of 3C-SiC solar cells.

Fig 7. Current density-voltage characteristic (J-V) of 3C-SiC solar cells.

Fig 8. Internal quantum efficiency (IQE) of 3C-SiC solar cells.

Fig 8. Internal quantum efficiency (IQE) of 3C-SiC solar cells.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.427.pdf

This paper investigated the solid state properties such as structural, electronic and optical properties of and , using the first-principles calculation. Our simulations show that is a good choice for photovoltaic applications.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.427.pdf

Z. Cheng, W. Lu, J. Shi, D. Tanaka, N.H. Protik, S. Wang, M. Iwaya, T. Takeuchi, S. Kamiyama, I. Akasaki, H. Amano, S. Graham, Quasi-ballistic thermal conduction in 6H-SiC, J Materials Today Physics 20 (2021) 100462.

N. Daghbouja, B.S. Lib, M. Callistic, H.S. Sena, J. Lind, X. Oud, M. Karlike,f, T. Polcara, The structural evolution of light-ion implanted single crystal: Comparison of the effect of helium and hydrogen, J. Acta Materialia 188 (2020) 609-622.

H. Heidarzadeh, H. Baghban , H. Rasooli , M. Dolatyari , A. Rostami. A new proposal for Si tandem solar cell: Significant efficiency enhancement in 3C-SiC/Si,J Optik 125 (2014) 12921296.

Noor Alhuda S. Al-Jammas. Simulation of the Influence of Environmental Factors on the Performance of 3C-SiC Solar Cells,J College of Basic Education Researchers, 17 (2021) 7452-1992.

Hamid Heidarzadeh. Performance analysis of cubic silicon carbide solar cell as an appropriate candidate for high temperature application, J Optical and Quantum Electronics 52 (2020) 192204.

Hamid Heidarzadeh, Ali Rostami, Mahboubeh Dolatyari, Efficiency analysis and electronic structures of and with 3 d elements impurities as intermediate band photovoltaics, J PHOTONICS FOR ENERGY4 (2014) 042098-042102.

F. C. Zhang, H. W. Cui, X. X. Ruan , W. H. Zhang, Density-functional theory study on electronic structure and optical property of 6 H -SiC, J Materials Research Innovations, S6 (2015) 46-49.

P.L.Zhou, S.K.Zheng, LeiMa, JingfangHe, YanTian, RuqianShi, Electronic and optical properties of Co-doped 3C-SiC from density functional calculations, Journal Solid State Communications, 196 (2014) 28-31.

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Chapter 4

Power Devices and Applications

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 435-441

doi: 10.4028/p-9p5o07

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-24

Revised:
2022-02-15

Accepted:
2022-03-17

Online:
2022-05-31

Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

The original version of this paper is available on https://www.scientific.net/MSF.1062.435.pdf

Xiaoli Tian , Chengzhan , Yu Yang , Wang Feng , Jiang , Changwei Zheng , Chengyue Yang , Yun Bai and Xinyu Liu

Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China

College of Microelectronics, University of Chinese Academy of Sciences, Beijing, China

CRRC Times Electric Co. Ltd, Zhuzhou, China

tianxiaoli@ime.ac.cn, lichengzhan@ime.ac.cn, yangyu@ime.ac.cn, fengwang@ime.ac.cn,

elujiang@ime.ac.cn, zhengcw@csrzic.com, yangchengyue@ime.ac.cn, baiyun@ime.ac.cn, iliuxinyu@ime.ac.cn

Keywords: 4 H -SiC, IGBT, High Voltage, Forward Voltage Drop

Abstract

The 10 kV silicon carbide p-channel insulated gate bipolar transistors (IGBTs) with low forward voltage drop ( ) have been fabricated and characterized successfully. The novel edge termination structure of Four-Region Multistep Field Limiting Rings (FRM-FLRs) and the optimum JFET region design proposed in our previous work is adopted to improve the blocking performance and the on-state characteristics. The fabricated device with a chip size of and an active area of exhibits a high blocking voltage of -10 kV with a small leakage current below - 200 nA . Meanwhile, a low forward voltage drop of -8 V at the collector current of -10 A with a gate bias of -20 V is obtained at room temperature, corresponding to a current density of . Besides, a lower gate leakage current is measured less than 2 nA at the gate voltage of -30 V . Experimental results demonstrate that a better trade-off between the blocking voltage and the on-state characteristics is achieved for the fabricated device, which is desirable for the high power applications.

Introduction

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The increasing pursuit of the efficient power conversion for the high voltage applications like smart grid and traction has generated significant interest in the silicon carbide ( SiC ) devices due to its superior material properties, such as the wide bandgap, high critical electric field, and high thermal conductivity. Compared with SiC MOSFET, IGBTs are considered to be favorable due to the low on-state loss because of their conductivity modulation [1]. Both p-channel and n-channel 4H-SiC IGBTs have been demonstrated with high voltage ability [2-4]. Meanwhile, the p-channel IGBTs have received much attention from some research groups due to the easier fabrication and low resistivity n-type SiC substrates [5]. In recent years, much research has been focused on achieving high blocking performance and low on-state characteristics simultaneously [6-9]. The first 5.8 kV 4H-SiC planar p-IGBT was demonstrated in 2006 [10]. A 12 kV p-IGBT with the of 5.3 V at was presented by Zhang et al. in 2008 [4]. Ryu et al. has reported the 20 kV n-channel SiC IGBT with the on-state voltage of 6.4 V in 2014 [7]. Recently, the blocking voltage of 27 kV and the of 11.7 V at 20 A has been achieved by Brunt et al. [9]. However, some issues should still be solved to improve the performance of SiC IGBTs, such as the low carrier lifetime, the low channel mobility, relatively high leakage current and forward voltage drop ( ). To achieve the best device performances, many technical solutions have been made to pursue a better trade-off between the high blocking ability and low [11,12].

In this paper, a domestic 10 kV 4H-SiC p-channel IGBTs with low is designed by using Silvaco TCAD simulation and fabricated with experimental verification. Experimental results indicate that a better trade-off between the blocking voltage and the on-state characteristics is achieved.

Design and Fabrication

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Fig. 1 shows a schematic structure of the p-channel IGBT. The epitaxial layers were grown on a 4-inch n-type 4H-SiC substrate with off axis. The thick p-type drift layer with a doping concentration of and a thick p -type buffer layer at a doping concentration of were utilized for the device fabrication [13]. The n -type substrate served as the electron injector layer for the p-IGBTs. The n-base with a retrograde profile was formed by implantation of nitrogen ( ) to meet the needs of the threshold voltage and blocking voltage. The contact and emitter were implanted with nitrogen ( ) and aluminum ( ), respectively [13]. All the implants were activated at with a carbon capping on the surface to avoid the step-bunching effect [14]. The channel length was about formed by a non-self-aligned implantation technique. A four-region multistep field limiting rings (FRM-FLRs) termination structure demonstrated in our previous work was used around the device periphery to relieve the electric field crowding and decrease the leakage current at high blocking voltage [15]. The gate oxide with a thickness of 50 nm was grown by dry thermal oxidation and then annealed in nitric oxide at to reduce the density of interface states and improve the channel carrier mobility. Polysilicon was deposited as a gate. contacts were deposited as the p-type ohmic metal, and Ni was deposited as the n-type collector contact metal. The fabricated IGBT has a chip size of and an active area of . Fig. 2 shows the photograph of the fabricated p-IGBT wafer and the top view of a p-IGBT.

Fig. 1. Schematic structure of the p-IGBT

Fig. 1. Schematic structure of the p-IGBT

Fig. 2. Photograph of the fabricated SiC p-IGBT wafer (a) and top view of the SiC p-IGBT (b)

Fig. 2. Photograph of the fabricated SiC p-IGBT wafer (a) and top view of the SiC p-IGBT (b)

In order to obtain a better trade-off between breakdown voltage (BV) and , the device structure is optimized by TCAD simulation based on our previous work [13]. The bandgap narrowing model, Auger recombination (AUGER) and Shockley-Read-Hall (SRH) recombination model, incomplete ionization model, doping and temperature dependent mobility models are used in the ATLAS device simulator. The material parameters of 4H-SiC used in the device simulations are presented in Table 1.

Table 1. 4 H -SiC parameters used in p-IGBT simulations

Parameters | Value | Meaning
Eg300 (eV) | 3.26 | Band gap at 300K
Permittivity | 9.8 | Permittivity
Affinity | 3.7 | Affinity
AUGN (cm⁶/s) | 5 × 10⁻³¹ | Auger recombination parameter for electrons
AUGP (cm⁶/s) | 2 × 10⁻³¹ | Auger recombination parameter for holes
TAUN0 (s) | 1.2 × 10⁻⁶ | Lifetime model parameter for electrons
TAUP0 (s) | 1 × 10⁻⁷ | Lifetime model parameter for holes
Nsrhn (cm⁻³) | 3 × 10¹⁷ | SRH concentration-dependent lifetime model for electron
Nsrhp (cm⁻³) | 3 × 10¹⁷ | SRH concentration-dependent lifetime model for holes

The width of the JFET region ( ) dependence of the BV and the are investigated particularly. Fig. 3 shows the BV and the maximum gate oxide electric field ( ) above the JFET region with the variations of . As increases, the BV decreases gradually, while the is increasing.

Fig. 3. Simulation results of BV and maximum with different

Fig. 3. Simulation results of BV and maximum with different

Fig. 4. Effect of on the at of current density

Fig. 4. Effect of on the at of current density

Fig. 4 shows the effect of on the at of current density. It can be seen that the decreases gradually with the increase of due to the decrease of JFET resistance. According to the simulation results, the of was adopted as the optimum structure to fabricate the p-IGBT. Simulation results reveal that the BV of -14.38 kV and of -7.7 V at the collector current density of is achieved, while the is at the -10 kV blocking voltage, which is a widely accepted criterion for long-term gate oxide reliability [16].

Results and Discussions

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Fig. 5 shows the blocking characteristics of the fabricated at room temperature. The IGBTs were tested with the gate grounded to the emitter and the high voltage applied to the collector by using Agilent B1505A at a wafer-level chip. During the blocking characteristic measuring, the devices were immersed in Fluorinert liquid to prevent arcing in air. It can be seen that the leakage current is lower than -200 nA at -10 kV without a distinct breakdown behavior. It should be noted that a higher bias voltage ( ) is limited owing to the maximum equipment ability. That means a higher blocking ability can be achieved by using the FRM-FLRs termination structure, which is illustrated in detail in our previous work [15]. As seen in Fig. 6, the FRM-FLRs edge termination is divided into four regions. Each region includes multistep field limiting rings. Therefore, the surface electric field of the FRM-FLRs is more uniform to reduce the electric field crowding around the device periphery effectively and achieve a higher blocking voltage of -16 kV shown in Fig. 7.

Fig. 5. Blocking characteristics of the p-IGBT at

Fig. 5. Blocking characteristics of the p-IGBT at

Fig. 6. Schematic cross-section of FRM-FLRs applied in IGBT

Fig. 6. Schematic cross-section of FRM-FLRs applied in IGBT

Fig. 7. Comparison of electric field distribution and blocking characteristics for FRM-FLRs and Con-FLRs

Fig. 7. Comparison of electric field distribution and blocking characteristics for FRM-FLRs and Con-FLRs

Fig. 8 shows the experimental and simulated forward I-V characteristics of the p-IGBT with a negative gate bias at room temperature. It can be seen that the I-V characteristic of simulation indicates a good fitting effect with the result from the experiment. The measured is -8 V at a collector current ( ) of - 10 A with a gate bias of - 20 V , corresponding to a current density of 62.5 . The on-state current density ( ) characteristics are also shown in Fig. 8. Experimental results prove that the fabricated p-IGBT has the of -7.1 V at of with a gate bias of -20 V .

Fig. 8. On-state I-V characteristics of the fabricated p-IGBTs

Fig. 8. On-state I-V characteristics of the fabricated p-IGBTs

Fig. 9. Experiment result of under pressure

Fig. 9. Experiment result of under pressure

Fig. 9 shows the gate leakage current characteristics of the fabricated device at the gate-emitter voltage testing, which is important to evaluate the gate oxide reliability. It can be seen that the gate leakage current of a p-IGBT is lower than -2 nA at the gate bias voltage from 0 to -30 V , which meets the reliability requirement for the actual application.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.435.pdf

A 4H-SiC p-channel IGBT with 10 kV blocking voltage and low has been designed, fabricated and characterized in this paper. The device with a chip size of and an active area of 0.16 shows that the blocking voltage is -10 kV with a small collector leakage current, which is attributed to the FRM-FLRs termination structure design given by our previous work. Moreover, the of -8 V is achieved at and , indicating a current density of . The measured gate leakage current of lower than -2 nA at is reliable for the actual application. Most importantly, the better trade-off characteristics of the fabricated p-IGBTs are acquired, which is desirable for use in high power electric systems.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.435.pdf

This work is supported by the High Technology Industrialization Special Fund of Cooperation between JiLin Province and Academy under Grant No. 2021SYHZ0030 and the Key Research and Development Program of Guangdong Province under Grant No. 2019B090917010.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.435.pdf

X. Wang, and J. A. Cooper, High-Voltage n-Channel IGBTs on Free-Standing 4H-SiC Epilayers, IEEE Trans. Electron Devices. 57.2 (2010) 511-515.

S. Katakami, H. Fujisawa, K. Takenaka, et al., Fabrication of a P-channel SiC-IGBT with high channel mobility, Mater. Sci. Forum. 740-742 (2013) 958-961.

S. Ryu, C. Capell, C. Jonas, et al., 15 kV IGBTs in 4H-SiC, Mater. Sci. Forum. 740-742 (2013) 954-957.

Q. Zhang, M. Das, J. Sumakeris, et al., p-Channel IGBTs with Low On-Resistance in 4H-SiC, IEEE Electron Device Lett., 29.9 (2008) 1027-1029.

Q. Zhang, J. Wang, C. Jonas, et al., Design and Characterization of High-Voltage 4H-SiC p-IGBTs, IEEE Trans. Electron Devices. 55.8 (2008) 1912-1919.

E. Brunt, L. Cheng, M. O'Loughlin, et al., -SiC n-IGBTs with Improved Conductivity Modulation, 2014 Proc. 26th Int. Symp. Power Semicond. Devices IC's, Hawaii, America, June 2014, 358-361.

S. Ryu, C. Capell, C. Jonas, et al., 20 kV 4H-SiC N-IGBTs, Mater. Sci. Forum. 778-780 (2014) 1030-1033.

K. Fukuda, D. Okamoto, M. Okamoto, et al., Development of Ultrahigh-Voltage SiC Devices, IEEE Trans. Electron Devices. 62.2 (2015) 396-404.

E. V. Brunt, L. Cheng, M. O'Loughlin, et al., 27 kV , 20 Ampere-rated n-IGBTs, Mater. Sci. Forum. 821-823 (2015) 847-850.

Q. Zhang, C. Jonas, S. Ryu, et al., Design and fabrications of high voltage IGBTs on 4H-SiC, in Proc. ISPSD, Naples, Italy, June 2006, 285-288.

D. Okamoto, M. Sometani, S. Harada, et al., Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation, IEEE Electron Device Lett., 35.12 (2014) 1176-1178.

T. Kimoto, K. Kawahara, B. Zippelius, et al., Control of carbon vacancy in SiC toward ultrahigh-voltage power devices, Superlattices and Microstructures. 99 (2016) 151-157.

X. Tian, B. Tan, Y. Bai, et al., Simulation Study for the Structural Cell Design Optimization of 15 kV SiC p-Channel IGBTs, Mater. Sci. Forum, 963 (2019) 666-669.

H. Shen, Y. Tang, Z. Peng, et al., Fabrication and Characterization of Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors, Chin. Phys. Lett., 32. 12 (2015) 127101-1-4.

B. Tan, X. Tian, J. Lu, et al., Design and Optimization of Four-Region Multistep Field Limiting Rings for 10 kV 4H-SiC IGBTs, 2018 Proc. 14th IEEE Int. Conf. Solid-state and Integrated Circuit Technology, Qingdao, China, Nov 2018, 1-3.

H. Jiang, J. Wei, X. Dai, et al., SiC Trench MOSFET with Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss, IEEE Electron Device Lett., 37.10 (2016) 1324-1327.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 442-446

doi: 10.4028/p-5po40a

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-27

Revised:
2022-02-14

Accepted:
2022-03-17

Online:
2022-05-31

Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

Zimo Yuan , Keijo Jacobs , Mietek Bakowski , Per Ranstad , Adolf Schöner , Sergey Reshanov , Wlodek Kaplan , Hans-Peter Nee and Anders Hallén

¹KTH Royal Institute of Technology, EECS, Isafjordsgatan 22, SE-164 40 Kista, Sweden

KTH Royal Institute of Technology, EECS, Teknikringen 33, SE-100 44 Stockholm, Sweden

RISE Acreo Swedish ICT AB, Box 1070, SE-164 25 Kista, Sweden

LNU Linnaeus University, FTK, SE-35 191 Växjö, Sweden

II-VI Kista AB, SE-164 40 Kista, Sweden

zimo@kth.se, k.jacobs@tutanota.com, mietek.bakowski@ri.se, per.ranstad@Inu.se, hansi@kth.se, ahallen@kth.se

Keywords: Proton Implantation, Shockley-Read-Hall (SRH) Lifetime, Reverse Recovery, Switching Losses.

Abstract

In this paper, proton implantation with different combinations of MeV energies and doses from to is used to create defects in the drift region of 10 kV 4 H -SiC PiN diodes to obtain a localized drop in the SRH lifetime. On-state and reverse recovery behaviors are measured to observe how MeV proton implantation influences these devices and values of reverse recovery charge are extracted. These measurements are carried out under different temperatures, showing that the reverse recovery behavior is sensitive to temperature due to the activation of incompletely ionized ptype acceptors. The results also show that increasing proton implantation energies and fluencies can have a strong effect on diodes and cause lower and switching losses, but also higher on-state voltage drop and forward conduction losses. The trade-off between static and dynamic performance is evaluated using and forward voltage drop. Higher fluencies, or energies, help to improve the turn-off performance, but at a cost of the static performance.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

Due to the larger band gap, higher breakdown voltage and better thermal performances, 4H-SiC PiN diodes are of interest for high voltage applications, for instance, rectification in resonant softswitching industrial power supplies, X-ray imaging and snubber circuits [1]. The switching losses of PiN diodes is a significant parameter for system design, especially when high switching frequency is necessary.

The Shockley-Read-Hall (SRH) lifetime in the low-doped drift region, plays an important role in controlling switching losses since it affects how fast the stored charge can be removed when the diode is switched off. If the SRH lifetime can be decreased, switching losses can be lower and better dynamic performance can be achieved. Defect states located deep in the band gap can change SRH lifetime since they provide recombination sites for carriers of opposite charge. As a consequence, it is possible to tailor the lifetime by introducing defects inside the device. Low-dose proton implantation can generate defects locally in the diode without causing many defects elsewhere and this offers an interesting alternative for SRH lifetime modification. As an example given by [2], the drift region of as-processed PiN diode can have two dominating deep levels at relatively low concentration, yielding a lifetime of several , while, after proton implantation, new types of stable defects will be dominant. These introduced defects have much higher concentration than native defects and can substantially contribute to a localized drop of the SRH lifetime.

In this paper, we carried out reverse recovery measurements at different temperatures of PiN diodes implanted by different energies and fluencies of protons. High temperature induces larger reverse recovery charge, , due to the further ionization of incompletely ionized acceptor dopants, but may also affect the charge carrier lifetime by temperature dependence of the carrier capture cross sections and bandgap position of deep levels. Increasing the proton implantation energy, or dose, has a positive effect on reducing SRH lifetime and switching losses, but will also cause a rise of the forward voltage. The trade-off between conduction and switching losses is discussed, and it is shown that MeV proton implantation offers a possibility to tailor the lifetime and reach an optimal trade-off between on-state and turn-off losses, using an offline process for metalized devices, before encapsulation.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

The tested diodes have a thick low-doped n -type ( ) drift region, with an active anode area of [3]. The proton implantations are performed at the Ion Technology Centre in Uppsala, Sweden and the implantation parameters are listed in Table 1. The diodes are classified into groups with one, or two proton implantation treatments. Figure 1 shows the distribution of silicon and carbon vacancy defects created by the proton implantation calculated by SRIM [4]. For the 1.9 MeV implant, a foil is used to moderate the energy. After the proton implantation, the samples are heat treated by furnace annealing, at for half an hour and normal atmosphere, to ensure stable defects at elevated temperatures.

A full bridge rectifier with four diodes connected to an input LCC converter using a transformer shown in Ref. [1] is used as the topology for the measurement. The four equivalent diodes are assembled on a PCB for a balanced behavior. Since the temperature behavior is also of interest, the PCB is placed in hot transformer oil to maintain a stable temperature ambient. The rectifier is operated by a 35 ms pulse, therefore self-heating of tested diodes is neglected. The diode voltage is measured by a high voltage probe and diode current is monitored by the voltage across a shunt resistor, which is connected in series with the tested diode. All the reverse recovery measurements are carried out with a steady state blocking voltage of 4 kV and a turn-off current derivative .

Table 1. Selected doses ( ) of protons for the different groups of diodes, using 3 different energies.

Group | Proton Energy [MeV]
| 1.9 | 3.4 | 3.7
1 | 5×10¹⁰ | — | —
2 | 5×10¹⁰ | 5×10⁹ | —
3 | 5×10¹⁰ | — | 5×10⁹
4 | — | 2×10¹⁰ | —
5 | — | 5×10¹⁰ | —
6 | — | 1×10¹¹ | —

Fig. 1. Vacancy depth distribution calculated by SRIM for different proton energies and doses. On the top is a cross section of the diodes, showing the thick drift region.

Fig. 1. Vacancy depth distribution calculated by SRIM for different proton energies and doses. On the top is a cross section of the diodes, showing the thick drift region.

Results and Analysis

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

The turn-off cycle of one of the tested diodes is shown in Fig. 2, including diode reverse current and voltage across the diode. The integrated diode current, starting from when the diode current crosses zero until the diode voltage reaches its maximum blocking voltage, is defined as reverse recovery charge . For higher reverse current, there will be a higher and more switching losses. Two groups of diodes with the same implantation energy, 1.9 MeV , but different fluencies are selected to illustrate how the implantation fluence affects the dynamic performance (Fig. 2 inset). Increasing implantation dose from to will cause an almost decrease in at and has a similar effect at .

Figure 2 (inset) also shows that increasing temperature from 30 to causes an approximately increase in , which is clearly visualized by the reverse recovery current peak in Fig. 3. Higher temperature contributes to larger and higher turn-off losses. This is due to the fact that the incompletely ionized p-type acceptors are ionized at a higher temperature [5], which improves the hole injection from the emitter. Different injection levels of holes at different temperatures simulated in Sentaurus TCAD are shown in Fig. 3 (inset). A increase in from 30 to is found from the integrated hole concentration in the drift region due to the increased ionization of acceptors at a higher temperature and this effect dominates the overall temperature dependence of the reverse recovery.

Fig. 2. Current Voltage (IV) characteristics of the turn-off cycle of a representative diode. The inset shows the reverse recovery for two different proton doses and that a higher temperature causes larger .

Fig. 2. Current Voltage (IV) characteristics of the turn-off cycle of a representative diode. The inset shows the reverse recovery for two different proton doses and that a higher temperature causes larger .

Fig. 3. Higher implantation dose contributes to smaller and less switching losses. The inset shows higher injection level at (Sentaurus TCAD) as a result of activation of more incompletely ionized acceptors in the emitter.

Values of the reverse recovery charge of three other groups are shown in Fig. 4 to compare the effect of implantation energy. All the groups have the same first implantation treatment, while two of the groups have obtained an extra implantation. The group without the second implantation is used as a reference group. Figure 4 shows that a higher implantation energy also helps to achieve a smaller and lower switching losses, and this effect is especially pronounced when the implantation energy is high enough for the protons to nearly reach the cathode side and thereby affecting most of the drift region.

The and the forward voltage, measured at a constant current of 2 A , is plotted as a function of implantation fluence at room temperature in Fig. 5. Proton implantation also increases the on-state losses of the diodes, since a low concentration of defects is formed during the entire proton track (see Fig. 1). These defects will increase the resistivity and forward voltage of the diode. A shorter SRH lifetime improves the dynamic performances by lowering the switching losses, while simultaneously the conduction losses at steady state become larger. This turn-off/on-state trade-off can be effectively tailored for specific applications using proton implantation.

Fig. 4. Higher implantation energy contributes to smaller and less switching losses.

Fig. 4. Higher implantation energy contributes to smaller and less switching losses.

Fig. 5. Proton implantation with higher dose is an effective way to improve the dynamic performance, while the static on-state performance must be sacrificed.

Fig. 5. Proton implantation with higher dose is an effective way to improve the dynamic performance, while the static on-state performance must be sacrificed.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

The reverse recovery behavior of PiN diodes with different proton implantation treatment is compared at different temperatures. It is seen that reverse recovery charge is increased with 30 when going from 30 to due to the ionization of Al acceptors in the emitter. The proton implantation can effectively reduce the SRH lifetime in the drift region, reduce the and contribute to lower switching losses. However, the on-state voltage drop is increased by the proton implantation. The measurement results show that localized carrier lifetime control through proton implantation can be used to find a suitable trade-off between static and dynamic performance of SiC PiN diodes.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

The Ion Technology Centre, ITC, in Uppsala, Sweden is acknowledged for proton implantations (contract 2017-00646-9).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.442.pdf

K. Jacobs, 'Silicon-Carbide-Based High-Voltage Submodules for HVDC Voltage-Source Converters', PhD dissertation, KTH Royal Institute of Technology, Stockholm, 2020. (Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-284797)

P. Hazdra, S. Popelka, A. Schöner, Local Lifetime Control in 4H-SiC by Proton Irradiation, Materials Science Forum, vol. 924, Trans Tech Publications, Ltd., June 2018, pp. 436-439. Crossref, doi:10.4028/www.scientific.net/msf.924.436.

M. Bakowski et al., "Design and Characterization of Newly Developed 10 kV 2 A SiC p-i-n Diode for Soft-Switching Industrial Power Supply," in IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 366-373, Feb. 2015, doi: 10.1109/TED.2014.2361165.

Stopping and range of ions in matter SRIM-2013, downloadable from

C. Darmody and N. Goldsman, 'Incomplete ionization in aluminium-doped 4H-silicon carbide', J. Appl. Phys. 126, 145701 (2019)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 447-451

doi: 10.4028/p-0uk0j4

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-30

Revised:
2022-02-09

Accepted:
2022-03-17

Online:
2022-05-31

Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

Keywords: MOSFET, SBD, Switching, Recovery, Loss

Abstract

The influence of the recovery characteristics on the switching behavior of SiC metal-oxidesemiconductor field-effect transistors (MOSFETs) with rated voltage and current of 1200 V and 50 A, respectively, at different switching speeds was investigated. A comparative analysis of the devices with different recovery characteristics revealed an increase in the turn-on loss ( ) owing to the higher output capacitance charge ( ) and reverse recovery charge ( ) in the recovery arm. On the other hand, a higher in the recovery arm resulted in a lower turn-off loss ( ). In addition, an increase in and further influenced and at a higher switching speed. Furthermore, a higher observed at a higher switching speed indicated a more significant impact of on at a high switching speed than that of . The findings clarified in this study highlight the necessity of focusing the recovery characteristics to ensure a desirable switching loss of SiC MOSFETs.

Takaaki Tominaga, Toshiaki Iwamatsu, Yukiyasu Nakao, Hiroyuki Amishiro, Hiroshi Watanabe, Naruhisa Miura, Satoshi Yamakawa, and Shuhei Nakata

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-Honmachi, Amagasaki, Hyogo 661-8661, Japan
Kanazawa Institute of Technology, 7-1 Ohgigaoka, Nonoichi, Ishikawa 921-8501, Japan
Tominaga.Takaaki@dy.MitsubishiElectric.co.jp, Iwamatsu.Toshiaki@da.MitsubishiElectric.co.jp, Nakao.Yukiyasu@dy.MitsubishiElectric.co.jp, Amishiro.Hiroyuki@cb.MitsubishiElectric.co.jp, Watanabe.Hiroshi@dh.MitsubishiElectric.co.jp, Miura.Naruhisa@db.MitsubishiElectric.co.jp, Yamakawa.Satoshi@ak.MitsubishiElectric.co.jp, nakata.shuhei@neptune.kanazawa-it.ac.jp

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

Owing to their excellent material properties, SiC MOSFETs are regarded as promising candidates for future power electronics compared with commonly used Si insulated gate bipolar transistors (IGBTs). One of the main advantages of SiC MOSFETs over Si IGBTs is the significantly lower switching loss owing to the absence of the minority carrier storage. The resulting higher switching frequency operation of SiC MOSFETs in comparison with that of Si IGBTs enables the realization of a higher power density and lower energy consumption in the power electronics systems.

However, the switching loss of SiC MOSFETs could have a substantial impact on the total loss in high switching frequency operation [1-3]. Therefore, reducing the switching loss of SiC MOSFETs by increasing the switching speed for higher switching frequency operation is of significance.

Because of a higher of SiC devices than that of Si devices, which is attributed to the two orders of magnitude higher doping concentrations of the drift layers, the displacement current of the freewheeling diodes in the recovery arm during the switching process varies the drain current ( ) of the transistors in the switching arm, and thereby influences and [4]. Moreover, the influence of on is in a similar degree as that of , which is derived from the parasitic body diodes of SiC MOSFETs in the recovery arm [4], although dominates and is negligible in Si devices [5].

In this study, the influence of and on the switching loss of SiC MOSFETs with different switching speeds was investigated in order to clarify the impact of the recovery characteristics under a higher switching speed.

Fig. 1. Equivalent circuit for switching measurement, and three types of configurations investigated in this study.

Fig. 1. Equivalent circuit for switching measurement, and three types of configurations investigated in this study.

Fig. 2. (a) Simulated and (b) measured diode characteristics of the recovery arm of each configuration at room temperature (solid lines) and (a dashed line).

Fig. 2. (a) Simulated and (b) measured diode characteristics of the recovery arm of each configuration at room temperature (solid lines) and (a dashed line).

Fig. 3. Recovery waveforms of the configuration (A) at (a) room temperature and (b) with several values.

Fig. 3. Recovery waveforms of the configuration (A) at (a) room temperature and (b) with several values.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

Switching measurements were performed with a double pulse test using the equivalent circuit shown in Fig. 1. To clarify the influence of the recovery characteristics, three type of configurations, which are also depicted in Fig. 1, were investigated. The switching voltage was 600 V , which determines the value in the switching measurements because it is derived from the charging or discharging current of the output capacitance in the recovery arm. The devices used in the recovery arm are (A) a MOSFET, (B) a MOSFET with an SBD, and (C) a MOSFET with two SBDs. The difference in in the recovery arm of each configuration is displayed in Fig. 2(a), which is calculated using TCAD simulation. The higher of (B) and (C) than that of (A) represents the
larger number of SBDs in the recovery arm. Fig. 2(b) shows the measured diode characteristics of the recovery arm for each configuration at room temperature (solid lines) and for the configuration (A) at (a dashed line). The source-drain voltage of (B) and (C) is smaller than the built-in potential of the parasitic body diode of (A) up to the measured current range, indicating that the parasitic body diodes of (B) and (C) are not activated. The higher diode current of (A) at than that at room temperature indicates the existence of minority carrier injection at a higher temperature. To clarify the difference in the minority carrier injection at different temperatures, the recovery waveforms of (A) at room temperature and were evaluated by changing the switching current ( ), as shown in Fig. 3. The reverse recovery current at room temperature shown in Fig. 3(a) is independent of , indicating a negligible influence of minority carrier storage. Therefore, the observed reverse recovery current is derived only from the displacement current due to . On the other hand, as shown in Fig. 3(b), a higher results in a higher reverse recovery current at , which indicates that the reverse recovery current consists of both and .

Fig. 4. Turn-on waveforms of each configuration at of (a) and (b) at room temperature.

Fig. 4. Turn-on waveforms of each configuration at of (a) and (b) at room temperature.

Fig. 5. Comparison of for each configuration at of (a) and (b) at room temperature.

Fig. 5. Comparison of for each configuration at of (a) and (b) at room temperature.

Fig. 6. Turn-off waveforms of each configuration at of (a) and (b) at room temperature.

Fig. 6. Turn-off waveforms of each configuration at of (a) and (b) at room temperature.

Fig. 7. Comparison of for each configuration at of (a) and (b) at room temperature.

Fig. 7. Comparison of for each configuration at of (a) and (b) at room temperature.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

To clarify the influence of in the recovery arm on the turn-on characteristics, Fig. 4 exhibits the turn-on waveforms of each configuration at of (a) and (b) at room temperature. It should be noted that the value in the configuration (A) is negligible at room temperature as discussed in Fig. 3. The value during the variation in the drain-source voltage ( ) is sum of the load current and charging current of the output capacitance in the recovery arm. Therefore, as shown in Fig. 4(a), a higher peak of (B) and (C) than that of (A) is observed owing to the higher of (B) and (C). The larger number of SBDs corresponds to the higher peak of (C) than that of (B). Moreover, as shown in Fig. 4(b), the deviation in peak between each configuration is higher at a higher switching speed, which can be derived from the faster charging time of the output capacitance in the recovery arm.

Fig. 5 shows the relative comparison of of each configuration at of (a) and (b) at room temperature. A higher results in a higher , and the influence of is more emphasized for a lower value. A larger impact of the difference in between each configuration on at a higher switching speed could correspond to the higher deviation in peak, as shown in Fig. 4(b).

The turn-off waveforms of each configuration at of (a) and (b) at room temperature are displayed in Fig. 6. As shown in Fig. 6(a), the lower of (B) and (C) than that of (A) during the variation in is observed owing to the higher , or higher discharging current of the output capacitance, of (B) and (C) in the recovery arm. In addition, the deviation in between each configuration is higher at a higher switching speed, as shown in Fig. 6(b).

Fig. 7 shows the relative comparison of of each configuration at of (a) and (b) at room temperature. A higher results in a lower , and the influence of is more emphasized for a lower value due to the higher deviation in (See Fig. 6(b)). However, unlike the case in the turn-on period, the values of (B) and (C) are nearly equivalent despite the deviation in derived from the difference in . As can be seen in Figs. 6(a) and 6(b), the rate of change in of each configuration also shows some deviation, and a higher corresponds to a lower . A decrease in could have an impact on reducing , while a decrease in could result in a higher . Therefore, the influence of the increased on is determined by the balance of the decreased and .

Fig. 8. Turn-on waveforms of the configuration (A) at of (a) and (b) at room temperature (black lines) and (gray lines).

Fig. 8. Turn-on waveforms of the configuration (A) at of (a) and (b) at room temperature (black lines) and (gray lines).

Fig. 9. Comparison of for the configuration (A) at of (a) and (b) at room temperature (black bars) and (gray bars).

In order to clarify the influence of on , the turn-on characteristics of the configuration (A) at room temperature and were investigated. Fig. 8 shows the turn-on waveforms of (A) at each temperature at of (a) and (b) . As shown in Fig. 8(a), a higher peak at than that at room temperature is observed. This phenomenon is owing to the higher at because is negligible at room temperature, as discussed in Fig. 3, and is independent of the measurement temperature. The deviation in peak is higher in a higher switching speed, as shown in Fig. 8(b), which could be attributed to the faster reverse recovery time. Therefore, as shown in the comparative analysis of at each temperature in Figs. 9(a) and 9(b), the value at is higher than that at room temperature at of , while it is lower at of .

Fig. 10. Dependence of on for the configuration (A) at .

Fig. 10. Dependence of on for the configuration (A) at .

Fig. 10 exhibits the total recovery charge ( ) as a function of extracted from the measured waveforms at . The total recovery charge at is higher at a higher switching speed. Because is independent of the switching speed, the observed dependence on could be attributed to the variation in . This result indicates a more significant impact of on increasing at a higher switching speed than that of .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

In this study, we have experimentally revealed a larger impact of and on the switching loss of SiC MOSFETs at a higher switching speed. The results indicate the importance of paying attention to the recovery characteristics to ensure a desirable switching loss of SiC MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.447.pdf

T. Zhao, J. Wang, A. Q. Huang, and A. Agarwal, in 2007 Ind. Appl. Annu. Meet. (2007), pp. 331-335.

H. Akagi, T. Yamagishi, N. M. L. Tan, S. Kinouchi, Y. Miyazaki, and M. Koyama, IEEE Trans. Ind. Appl. 51, 420 (2015).

T. Tominaga, S. Hino, Y. Mitsui, J. Nakashima, K. Kawahara, S. Tomohisa, and N. Miura, Mater. Sci. Forum 1004, 801 (2020).

T. Tominaga, S. Hino, Y. Mitsui, J. Nakashima, K. Kawahara, S. Tomohisa, and N. Miura, in 2019 31st Int. Symp. Power Semicond. Devices ICs (ISPSD) (2019), pp. 27-30.

D. T. Morisette, J. A. Cooper, M. R. Melloch, G. M. Dolny, P. M. Shenoy, M. Zafrani, and J. Gladish, IEEE Trans. Electron Devices 48, 349 (2001).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 452-457

doi: 10.4028/p-h5u155

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-30

Revised:
2022-02-17

Accepted:
2022-03-17

Online:
2022-05-31

Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation

The original version of this paper is available on https://www.scientific.net/MSF.1062.452.pdf

Shuhei Nakata and Yuta Sato

Kanazawa Institute of Technology, 7-1 Ohgigaoka, Nonoichi, Ishikawa 921-8501, Japan

nakata.shuhei@neptune.kanazawa-it.ac.jp, bb1644575@planet.kanazawa-it.ac.jp

Keywords: SiC, MOSFET, switching, self-turn-on

Abstract

The effect of the contact resistance between the p-well and the source electrode of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) on the self-turn-on phenomenon was investigated experimentally. It was found that the contact resistance significantly affects the self-turnon in addition to the conventional self-turn-on owing to the parasitic capacitances. To simulate this phenomenon, a circuit model including the contact resistance, p -well sheet resistance, and p -well region diode was created, and the simulation results were compared with the measurement results. Consequently, by considering the contact resistance and the forward recovery effect in the diode characteristics, the gate-induced voltage was calculated, with the results close to those of the experiment. Thus, the influence of contact resistance and p -well diode effects are clearly very important when operating SiC MOSFETs at high switching speeds.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.452.pdf

Higher-switching-frequency operation of SiC metal-oxide-semiconductor field-effect-transistors (MOSFETs) would reduce the volume of such passive components as capacitors and inductances in power electronics systems to achieve higher power densities of the systems [1]. When such an operation is performed, the switching loss increases and the efficiency decreases. Increasing the switching speed and shortening the switching time at ON and OFF are effective for reducing the switching loss of SiC MOSFETs。.

However, the resulting sudden change in the drain-source voltage ( ) of the MOSFET causes a large induced voltage at the gate electrode ( ) because of the gate-drain capacitance ( ). Consequently, a self-turn-on phenomenon may occur [2]. Furthermore in the case of SiC MOSFETs, self-turn-on phenomena that cannot be explained by have been reported [3].

Therefore, experiments on the temperature dependence of the self-turn-on phenomenon and the effect of the contact resistance between the p -well and the source electrode were conducted. A mechanism for the self-turn-on phenomenon is proposed as a result of investigating the device physics of SiC MOSFETs.

Experimental Setup

The original version of this paper is available on https://www.scientific.net/MSF.1062.452.pdf

Figure 1 depicts the experimental configuration used to study the self-turn-on of SiC MOSFETs. The SiC MOSFET was placed in the lower arm and was kept off by applying a negative gate bias voltage ( ), which was lower than the threshold voltage of the MOSFET. A high voltage ( ) was applied to the drain source electrode of the lower arm MOSFET by turning on the MOSFET of the upper arm.

Fig. 1 Experimental configuration.

Fig. 1. Experimental configuration.

To control the applied of the lower arm MOSFET, the switching speed of the upper arm MOSFET was changed by the gate resistance ( ) of the upper arm.

To simplify the analysis of the voltage induced in the gate electrode and the self-turn-on phenomenon resulting from , the displacement current was prevented from flowing into the gate bias circuit. Therefore, the gate resistance ( ) was set to a value sufficiently larger than the impedance due to the input capacitance of the MOSFET.

Fig. 2 Typical waveforms of (a) and (b) and .

Fig. 2. Typical waveforms of (a) and (b) and .

Figure 2 shows a typical waveform of a lower-arm SiC MOSFET. Figure 2(a) shows the gate source voltage minus the offset, and Figure 2(b) shows the and drain source currents ( ). As shown in Figs. 2(a) and (b), when increases, a gate voltage is induced and the displacement current flows.

The gate induced voltage ( .) by is defined as the deviation between the peak value and the initial value of , as shown in Fig. 2(a).

Self-turn-on was detected as follows. First, the gate bias voltage was set so that self-turn-on did not occur, and then the current flowing through the lower arm was measured while gradually increasing the bias voltage. When this current increased, it was determined that self-turn-on had occurred. The bias voltage at that time was defined as the self-turn-on prevention voltage ( .).

In this experiment, planar MOSFETs with a rated voltage of 1200 V and chip size of 0.03 cm 2 were adopted.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.452.pdf

In this section, the experimental results and the models that explain the results are described.

Fig. 3 Dependence of . on measurement temperature at of approximately .

Fig. 3. Dependence of . on measurement temperature at of approximately .

Figure 3 shows the relationship between the . and measurement temperature. This experiment was performed under the condition of of approximately . As shown in Fig.3, the positive temperature dependence of . was observed.

The traditional self-turn-on phenomenon is thought occur via . However, the temperature dependence of Cgd and Cgs is not strong enough to explain the temperature dependence of Vprv in Figure 3. The self-turn-on phenomenon in this experiment is clearly another phenomenon.

Fig. 4 Dependence of of samples (A) and (B) on at 25 degrees Celsius.

Fig. 4. Dependence of of samples (A) and (B) on at 25 degrees Celsius.

Figure 4 shows the dependency of . using two samples. The experiments were conducted at 25 degrees Celsius. Sample A had a normal contact resistance ( ) between the p-well and the source electrode, and sample B intentionally had a large .

As shown in Fig. 4, the . of sample B was lower than that of sample A . Moreover, the dependence of . on was larger in sample B than in sample A . These experimental results show that the higher the contact resistance ( ), the more likely the occurrence of the self-turn-on phenomenon.

It is well known that contact resistance increases as temperature decreases. Summarizing the results in Fig. 4, the phenomenon that . has positive temperature dependence, as shown in Fig. 3, and it is considered to be caused by the temperature dependence of the contact resistance.

To understand the mechanism of the dependence . on the temperature and contact resistance described in Figs. 3 and 4, the equivalent circuit model shown in Fig. 5 was developed. The model
included each capacitive component ( , and ) of the MOSFET, the contact resistance and sheet resistance ( ) of the p -well, including their temperature dependence [4], and the diode of the p -well and region ( p -well/ diode). In addition, the forward recovery characteristics was incorporated in the diode so that the transient characteristics could be simulated. The forward recovery characteristics were modeled by a series-connected variable resistor whose resistance changed according to the charge through the diode [5].

Fig. 5 Schematic of an equivalent circuit model.

Fig. 5. Schematic of an equivalent circuit model.

In the simulation, the measured waveform was used as the drain voltage.
In the simulation, the experimental results of were compared with the simulation results. The simulation was performed using the three models: (I) a model that considered only and , (II) a model that included all the components described in Fig. 5 except for the forward recovery characteristics of the p -well diode, and (III) a model that included the forward recovery effect in the p -well diode. The features of the model are summarized in Table I.

Table 1 Three types of models.

model
I
II
III

Cgs & Cgd
✓
✓
✓

other
capacitance
-
✓
✓

ρc & Rsh
-
✓
✓

p-well/n+
diode
-
✓
✓

forward
recovery
-
-
✓

Table 2 Parameters for the simulation.

Parameters | Value
Contact Resistance | 1mΩcm2
Sheet Resistance | 20000Ω sq.
Cgs | 48.8nF/cm2
Cds | C/o = 24.4 (nF/cm2), Vj = 3.5 V, M = 0.56
Cgd | C/o = 9.2 (nF/cm2), Vj = 1.0 V, M = 0.8

The parameters used in the simulation are listed in table 2. For Cds and Cgd, the drain voltage dependence was given by the following equation using the parameters in the table.

Figure 6 shows the dependence of the measured and calculated values of of sample A on (a) at 25 degrees Celsius and (b) temperature at of approximately .

Figure 6(a) shows the relationship between and . The red, blue, and white diamonds are the results of models I, II, and III, respectively. The white circle represents the measurement results.

Fig. 6 Dependence of measured and calculated of sample A on (a) at 25 degrees Celsius and (b) temperature at of around .

Fig. 6. Dependence of measured and calculated of sample A on (a) at 25 degrees Celsius and (b) temperature at of around .

As shown in Fig. 6(a), the calculated of model I shows a large deviation from the measured value and smaller dependence on . However, the results of model II show that is larger than that of model I and the difference from the measured value becomes small. This indicates that the potential fluctuation of the p -well caused by the displacement current flowing through the contact resistance and the sheet resistance affects . However, if is large, the difference from the measured becomes large. This is because the induced voltage of the p-well is limited by the builtin potential of diode in model II.

In model III, a transient high resistance was applied to the p -well diode to consider the forward recovery characteristics. Figure 6 shows that the values calculated using this model agreed well with the measured values, even at large values.

This indicates that the transient characteristics of the p -well diode are also important in the circuit analysis when the MOSFET is switched ON and OFF under the condition of a large .

Figure 6(b) shows the measured and calculated temperature dependences of . The at this time is approximately . As shown in the figure, the measured (white circles) and calculated (white diamonds) values agree well, confirming the validity of this model.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.452.pdf

The SiC MOSFET self-turn-on phenomenon dependency on , temperature, and contact resistance was measured when was applied.

It was found that the self-turn-on prevention voltage ( .) had a positive temperature dependence and was strongly influenced by contact resistance.

To simulate this phenomenon, a circuit model including contact resistance, p-well sheet resistance, and p -well/n + region diodes was created and compared with the measured results. It was found that a closer calculation result to the experimental result could be obtained by considering the contact resistance and the forward recovery effect in the p -well region diode.

It was shown that the contact resistance and p -well diode characteristics are very important for the switching characteristics when SiC MOSFETs operate at a high switching speed.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.452.pdf

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology (Wiley, 2014).

T. Funaki, Comparative study of self turn-on phenomenon in high-voltage Si and SiC power MOSFETs, IEICE Electronics Express 10, (2013) 20130744.

S. Nakata, S. Tanaka, Temperature Dependence of dV/dt Impact on the SiC-MOSFET, Mater. Sci. Forum 963, (2019) 596-599.

M. Vivona, G. Greco, R. Lo Nigro, C. Bongiorno, F. Roccaforte, Ti/Al/W Ohmic contacts to ptype implanted 4H-SiC, Appl. Phys. Lett. 118, (2015) 035705-1 - 035705-7.

K. J. Tseng, Modelling of diode forward recovery characteristics using a modified charge control equation, Int. J. Electronics 84, (1998) 437-444.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 458-462

doi: 10.4028/p-hd601i

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-01

Revised:
2022-03-14

Accepted:
2022-03-17

Online:
2022-05-31

Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

Sofía Otero Ugobono , J.M. Rafí , P. Godignon , G. Pellegrini , G. Rius , M.C. Jiménez-Ramos , J. García López and A. García-Osuna

IMB-CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain

Centro Nacional de Aceleradores (U. Seville, CSIC, J. de Andalucía), Seville, Spain

sofia.otero.ugobono@cern.ch, jm.rafi@csic.es, philippe.godignon@imb-cnm.csic.es, giulio.pellegrini@csic.es, gemma.rius@csic.es, mcyjr@us.es, fjgl@us.es, agosuna@us.es

*Corresponding author

Keywords: Epitaxial graphene, detectors, radiation hardness, resistivity, CTLM.

Abstract

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with grapheneenhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

There is currently a particular interest in the of radiation detectors in different wide bandgap materials, as they present various advantages over silicon devices [1]: low reverse bias voltage operation, even at room temperature after irradiation [2] [3]; potentially greater radiation hardness thanks to its high atomic displacement threshold [4] [5]; higher drift velocity [6]; and higher thermal conductivity [7]. In the past, SiC detectors were discarded due to the lack of high-quality large-area wafers [8]. However, nowadays the widespread use of SiC in power devices has pushed the quality of this material to levels similar to those of silicon. wafers with a layer of up to of epitaxially-grown SiC are now available [9]. The GRACE project aims to take the production of SiC sensors one step further by enhancing their electrical contacts with an epitaxially-grown graphene layer. This could improve the SiC -metal electrical contact as well as the overall thermal management of the devices. In addition, such a development would permit the production of sensors for heavy-ion detection, where the full active area is covered with graphene and no metal. The production and integration of epitaxial graphene on SiC wafers is one of the central challenges of this project. The epitaxial growth of graphene relies on the decomposition and controlled restructuring of the SiC crystal surface, which acts as the template for the subsequent nucleation and growth of graphene layers. The process involves a high temperature thermal process and results in a significant increase of SiC surface roughness [2]. In our case, the graphene is grown from the Al -doped p -type implant in the SiC . Thus, the Al -implanted layer also plays a relevant role, including its relation with the surface micro/nanostructure and metal thin film fabrication. To produce these sensors it was first necessary to identify and validate the best materials to build the devices. We had to address the design of the electrical contacts on p-type SiC, which must be optimised for operation under high levels of radiation and high temperatures. This development included testing the actual impact of enhancing the contacts with graphene, as well as verifying which multilayer alloyed contacts provide the best performance. Irradiation campaigns were carried out to evaluate the radiation hardness of each combination. The results obtained so far from the characterisation of test structures with different
electrical contact designs are reported in this paper. Also, the initial results from the characterisation of the first production runs of SiC and graphene-enhanced SiC (EG-SiC) devices are presented.

Contact Optimisation

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

Fig. 1 Design of the CTLM test structures.

Fig. 1. Design of the CTLM test structures.

The first step towards the production of EG-SiC devices was the development of the fabrication process of test structures for the evaluation of metal contacts on both p-implanted SiC and on p-implanted SiC with a layer of epitaxially grown graphene (EG-SiC). To study the performance of each alloy stack proposed, a test methodology based on the circular transmission line model (CTLM) was used. This method implies the use of test structures comprised by several circular electrodes (inner radius ) encompassed by a non-metallised region (a gap of width ) and surrounded by a conducting (metallised) outer region. The layout of the test structures used can be seen in Fig. 1. The total resistance ( ) of each circular contact is determined by measuring, through the 4 -point method, the voltage drop as a function of the current applied. If these two parameters are linearly dependent, the slope corresponds to the of the contact. Using CTLM, it is possible to extract the values of the sheet resistance and the contact resistivity .

In order to optimise the design of the electrical contacts, two different alloy stacks were proposed: , deposited through evaporation) and , sputter deposition). Low-resistivity SiC ohmic contacts based on are well recorded [6] hence the choice, and the cap layer of W is required to avoid oxidation. Graphene-metal ohmic contacts have not been documented to the same extent as their SiC counterparts. Having said that, the Ti alloy was reported to create an effective ohmic contact with graphene in [12]. To ensure an ohmic behaviour of the contacts, they must be annealed at high temperatures for some minutes. This method is well studied for SiC, and it is known that the contacts must be annealed at temperatures above [6], thus the chips were annealed at for 2 min . A more conservative approach was taken for the EG-SiC test structures, which were annealed at for 15 min . Later studies (not included here) showed that the same annealing process should be applied to both SiC and EG-SiC structures.

The CTLM test structures were produced in chips of about . Optimising their fabrication on EG-SiC was not trivial. As a result, only one EG-SiC chip metallised with (EG-SiC Chip 8), with just three test structures, could be tested. The fabrication of SiC chips was simpler and two chips with tens of CTLM test structures were produced: SiC Chip 1, metallised with Ti/Al/Ti/W; and SiC Chip 2, metallised with Ti/Pt/Au. All chips were manufactured with the same p-implanted SiC wafer, ensuring equal substrate and implant properties for all. To validate the radiation tolerance of the contacts, two irradiation campaigns with protons were carried out at the Centro Nacional de Aceleradores (Seville, Spain). Table 1 summarises all their details.

The results obtained in terms of and as a function of fluence are compiled in Fig. 2. As expected, all devices show a similar degradation upon irradiation of the (related to the doping concentration). At fluences above increases significantly. This is a clear sign of irradiation-induced effective acceptor removal in the p-type implant, an effect thoroughly studied in Si [13]. Regarding , the degradation is most significant beyond . However, this degradation was found to be lower in SiC Chip 2. In fact, this chip presented the lowest of all, both before and after irradiation. In order to obtain conclusive results as to the behaviour of graphene-enhanced contacts, we are planning the fabrication of more EG-SiC chips for a new irradiation campaign.

Table 1 Details of the irradiation campaigns performed on chips with CTLM test structures.

Device
Metallisation
Annealing
Fluence [cm⁻²] (no of samples)

SiC Chip1
Ti/Al/Ti/W
(15/90/30/100 nm - evaporation)
2 min 950°C
0 (2), 10¹³ (5), 10¹⁴ (10),
10¹⁵ (10), 10¹⁶ (10)

SiC Chip 2
Ti/Pt/Au
(20/100/100 nm - sputtering)
2 min 950°C
0 (4), 10¹³ (2), 10¹⁴ (5), 10¹⁵ (5),
3×10¹⁵ (5), 6×10¹⁵ (5), 10¹⁶ (5)

EG-SiC Chip8
Ti/Pt/Au (20/100/100 nm - sputtering)
15 min 450°C
0 (1), 10¹⁵ (1), 10¹⁶ (1)

Fig. 2 Mean sheet resistance (a) and mean contact resistivity (b) as a function of fluence for three types of substrate-metal contacts: Ti/Al/Ti/W on p-implanted SiC (SiC Chip 1), Ti/Pt/Au on p-implanted SiC (SiC Chip 2), and Ti/Pt/Au on epitaxial graphene grown on p-implanted-SiC (EG-SiC Chip 8).

Fig. 2. Mean sheet resistance (a) and mean contact resistivity (b) as a function of fluence for three types of substrate-metal contacts: Ti/Al/Ti/W on p-implanted SiC (SiC Chip 1), Ti/Pt/Au on p-implanted SiC (SiC Chip 2), and Ti/Pt/Au on epitaxial graphene grown on p-implanted-SiC (EG-SiC Chip 8).

Fabrication and characterisation of sensor prototypes

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

A mask consisting of simple diodes, 4 -quadrant diodes, circular diodes, MOS devices, and microstrip sensors was designed. Its design allows for the fabrication of devices with and without graphene enhanced contacts, see Fig. 3. Firstly, a wafer full of SiC devices without graphene was produced (run 13575). The front and back metallisation applied was of and , respectively. These alloy stacks were chosen for their compatibility with the foreseeing encapsulation for high-temperature-operation testing. The devices were electrically characterised and 8 sensors were irradiated. A new run including EG-SiC devices was produced, but

Fig. 3 Cross-section schematic and fabrication steps of SiC (left) and EG-SiC devices.

Fig. 3. Cross-section schematic and fabrication steps of SiC (left) and EG-SiC devices.

it was discovered that the fabrication process had to be modified in order to properly integrate the graphene in the detector structure. Thus, a new run (run 14416) with a metallisation of was produced, using a new and optimised fabrication method. The devices produced were electrically characterised. As a rule, all devices were classified as having high or low leakage current: if the leakage current is lower than 10 nA at 350 V , then they qualify as low current devices. Forward-bias current vs voltage measurements were also performed to verify that all devices worked properly.

SiC prototype sensors: simple diodes. The capacitance (CV) and leakage current (IV) curves with respect to voltage were measured. These measurements were performed using a probe station, where electrical contact is achieved via physical contact between the sensor and both a chuck (back contact) and a tungsten probe needle (front contact). IV measurements require solely the use of a high-voltage source measure unit, together with the aforementioned probe station. On the other hand, CV measurements require a more complex set-up. In addition to the LCR-meter needed for measuring the impedance, two voltage sources must be used simultaneously. One source is used to bias the sensor. The other provides an alternate current, which is necessary to measure the impedance of the device. Furthermore, a custom-made decoupling circuit is connected to both sources in order to disentangle both voltages.

Fig. 4 CV curves at 10 kHz (a) and IV curves (b) for the diodes from run 13575 used in the irradiation campaign. SiC devices metallised with Ti/Al/Ti/Ni, no graphene enhancement.

Fig. 4. CV curves at 10 kHz (a) and IV curves (b) for the diodes from run 13575 used in the irradiation campaign. SiC devices metallised with Ti/Al/Ti/Ni, no graphene enhancement.

The full depletion voltage, extracted from the CV curves (at 10 kHz ), is of of the sensors have a low leakage current. No correlation was found between the location of the devices within the wafer and their leakage current levels. A set of eight diodes were irradiated in pairs with thermal neutrons up to four fluences: . The irradiations were performed at the ATI Triga Mark II nuclear reactor [14]. Fig. 4 shows the CV and IV curves of the devices. At a fluence of and beyond, the measured currents are higher than before irradiation, but significantly lower than those of lower fluences. Analysing the forward-bias region of the curves, no surge in current is observed. This indicates a loss of the pn-junction due to the materials becoming intrinsic after irradiation [15]. This is confirmed by the flat CV curves: a behaviour consistent with a parallel plate capacitor rather than a diode.

EG-SiC sensor prototypes. For this run only a quarter of a wafer was used. A few of the sensors had serious metallisation defects and could not be measured. These defects appeared mainly on the EG-SiC devices. In fact, it has been found that the presence of graphene tends to make the metallisation more fragile. CV/IV measurements were carried out on all the simple diodes and microstrip sensors that had no metallisation issues, see Fig. 5. To measure the microstrip sensors only one middle strip was contacted, the rest were left floating. The depletion voltage of the devices was of of all simple diodes and of all microstrip sensors had low leakage current. The overall results from this run are promising. The next step would be to produce a full wafer with SiC and EG-SiC devices and to perform an exhaustive irradiation campaign.

Fig. 5 CV curves at 10 kHz for the simple diodes (a) and IV curves for the simple diodes and microstrips (b) from run 14416. SiC and EG-SiC devices, all metallised with Ti/Pt/Au.

Fig. 5. CV curves at 10 kHz for the simple diodes (a) and IV curves for the simple diodes and microstrips (b) from run 14416. SiC and EG-SiC devices, all metallised with Ti/Pt/Au.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

We observe low contact degradation with proton irradiation up to . The best resistivity results were obtained with the alloy stack, although further studies are required for . SiC and EG-SiC prototype sensors were successfully fabricated. Neutron-irradiated SiC diodes (fluence ) show signs of pn-junction loss due to the materials becoming intrinsic. An irradiation campaign of EG-SiC devices must be carried out to validate the technology.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

This work was supported by the Spanish State Research Agency (AEI) and the European Regional Development Fund (ERDF), ref. RTC-2017-6369-3. We want to thank Dr Thomas Bergauer for facilitating the irradiations at the Atominstiut.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.458.pdf

G. Casse and M. Moll, "RD50 Prolongation Request 2018," CERN, Geneva, 2018.

S. Aslanidou et al., APL Materials, vol. 8, no. 10, p. 100702, 2020.

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M. Shur et al., SiC Materials and Devices, New Jersey: World Scientific, 2006.

S. Shindé and J. Goela, High thermal conductivity materials, New York: Springer, 2006.

M. Bruzzi et al., Nucl. Instrum. Meth. A, vol. 579, p. 754, 2007.

E.T.C. Epitaxial Technology Center S.r.l., [Online]. Available: .

D. K. Schroder, Semiconductor material & device characterization, NY: Wiley, 2006.

T. Liu et al., Curr. Appl. Phys., vol. 18, p. 853, 2018.

J.S. Moon et al., Appl. Phys. Lett., vol. 100, p. 203512, 2012.

R. Wunstorf et al., Nucl. Instrum. Meth. A, vol. 377, p. 228, 1996.

"Atominstitut TRIGA Mark-II Reactor," [Online]. Available: .

J.M. Rafí et al., IEEE TNS, vol. 67, no. 12, p. 2481, 2020.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 463-467

doi: 10.4028/p-4b1mb3

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-30

Revised:
2022-02-08

Accepted:
2022-02-09

Online:
2022-05-31

Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

The original version of this paper is available on https://www.scientific.net/MSF.1062.463.pdf

Daniel J. Lichtenwalner , Donald A. Gajewski , Sei-Hyung Ryu , Brett Hull , Scott Allen and John W. Palmour

Wolfspeed, a Cree Company 3028 East Cornwallis Road, RTP, NC, USA

daniel.lichtenwalner@wolfspeed.com, donald.gajewski@wolfspeed.com, sei-hyung.ryu@wolfspeed.com, brett.hull@wolfspeed.com, scott.allen@wolfspeed.com and john.palmour@wolfspeed.com

Keywords: Silicon Carbide, MOSFET, oxide reliability, TDDB

Abstract

Power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) while in the high-voltage blocking state and above a threshold for that device. Typically, the SEB failure rate is measured at a high blocking voltage, with the source and gate at ground potential. Here the effect of a negative gate bias, commonly applied during MOSFET switching to the blocking state, on the SEB failure rate is examined. It is observed that the SEB failure rate is only weakly dependent on the negative gate bias, because it does not significantly affect the peak field in the drift region where avalanche breakdown is initiated. A negative gate bias of in the device blocking state at only results in a increase in the MOSFET SEB failure rate.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.463.pdf

All power devices are susceptible to failure by terrestrial neutron single-event burnout (SEB) in the high drain bias ( ) blocking state, above a threshold for that device. This had been discovered initially for Si-based power devices [1,2], and more recently shown for SiC diodes and MOSFETs [3-7]. Typically, the SEB failure rate is measured at a high blocking voltage with the source and gate at ground potential. In this study the effects of a negative gate bias, while at high VDS, on the SEB failure rate are examined, to better match conditions of MOSFETs switched to the off-state using a negative gate bias.

Experimental and Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.463.pdf

Neutron SEB testing of MOSFETs has been performed at Los Alamos National Laboratory (LANL) using their spallation neutron source, as described in [6]. Groups of 12 devices are tested at given and bias conditions (all at ), run until some or all the devices fail, and the failure time is correlated with the neutron fluence to determine a neutron fluence per fail. Fresh sets of 12 parts are mounted for each test at given and values. At very low , only a few devices may fail because the test time needed is very long if the FIT rate is low; while at closer to the rated voltage the test is typically run until all devices in the group fail. The failure rate is converted to the sea level neutron flux level, and the overall FIT rate is obtained for each group using the failure data for all the failed parts in the group, as described in JEP151 [8], and modeled with a trend line as presented in [9]. TCAD simulations of the MOSFET gate field under the various device bias conditions have also been performed to demonstrate electric field effects of the applied bias conditions. The TCAD model has Fowler-Nordheim tunneling enabled, and both hole and electron carriers. The TCAD modeling is not meant to describe the SEB event, but only to show the oxide and SiC fields under the SEB test conditions.

Presented here are results from Wolfspeed 1200 V 16 mohm SiC MOSFETs (C3M0016120K, Gen3), measured under neutron irradiation at LANL. Figure 1 shows the mean failure in time (FIT, fails per billion device hours) scaled to the NY city sea level average flux value, from groups of 12 devices tested to failure at each condition, at and room temperature. The points on the graph are the FIT rate obtained from all the failures in each group [8]. The SEB failure for
these devices follows trends with typically observed for vertical power devices [5, 7, 9], indicating that below a given value failure rates are exceedingly small.

Fig. 1. Mean FIT versus for Wolfspeed G3 1200 V 16 mohm SiC MOSFETs, with . FIT rate is strongly dependent on the value.

Fig. 1. Mean FIT versus for Wolfspeed G3 1200 V 16 mohm SiC MOSFETs, with . FIT rate is strongly dependent on the value.

Fig. 2. Mean FIT versus for Wolfspeed G3 1200 V 16 m SiC MOSFETs, with . FIT rate is weakly dependent on the value.

Fig. 2. Mean FIT versus for Wolfspeed G3 1200 V 16 m SiC MOSFETs, with . FIT rate is weakly dependent on the value.

The effects of negative gate bias on the mean failure rate are shown in Fig. 2 for the Gen3 1200 V 16 mohm devces. The recommended gate turn-off voltage for this device is -4 V , while the minimum rated gate bias is -8 V . The result of decreasing the from 0 V to -8 V on the mean FIT rate at reveals there is overall a small increase in the failure rate as the negative gate bias increases, but the effect is small. The SEB failure rate on average appears to increase about per volt of applied.

To understand better the effect of the negative gate bias on the device, TCAD MOSFET simulations of these planar devices (half-cells shown) have been used to compare the SiC and gate oxide fields under 1200 V V conditions, and at of either 0 V or -8 V . As shown in Figs. 3 and 4, the effects of applying the negative gate bias on the electric fields in the MOSFET are confined

Fig. 3. TCAD MOSFET simulation at and showing E-field distributions.

Fig. 3. TCAD MOSFET simulation at and showing E-field distributions.

Fig. 5. TCAD electric field cutline along the JFET center (left edge of Figs. 3 & 4). Note the higher oxide and JFET fields for .

Fig. 5. TCAD electric field cutline along the JFET center (left edge of Figs. 3 & 4). Note the higher oxide and JFET fields for .

Fig. 4. TCAD MOSFET simulation at and . Note the increased gate oxide field.

Fig. 4. TCAD MOSFET simulation at and . Note the increased gate oxide field.

Fig. 6. TCAD derived oxide field and peak SiC field at the top center of the JFET region of the MOSFET, as and bias levels change.

Fig. 6. TCAD derived oxide field and peak SiC field at the top center of the JFET region of the MOSFET, as and bias levels change.

to the gate oxide region and the SiC JFET region. Note in Fig. 4 that the gate oxide in the left edge of the image near the arrow (the center of the JFET region in the full device cell) has reached a higher field, but the field in the drift itself is relatively unchanged. To demonstrate this more clearly, Fig. 5 shows the E-field versus depth through a cutline along the JFET center (left edges of Figs. 3 and 4), from the gate down through the SiC drift. The fields in both the oxide and SiC at the JFET center increase as increases in the negative bias direction. The peak oxide field and SiC peak JFET field just under the oxide increase when is decreased from 0 V to -8 V . The fact that this closely matches the observed SEB failure rate increase with V GS indicates a correlation between the gate bias and the SEB failure rate. Fig. 5 shows that the field in most of the SiC drift layer, below the JFET region, is unaffected by the applied gate bias, and is higher than the JFET field, due to the P-well shielding of the JFET region. Note that the gate oxide field under blocking and obtained in these TCAD simulations is lower than the typical MOSFET onstate gate oxide field, which is about for a bias.

To better understand the effects of the and bias, the simulated JFET peak SiC field (just under the oxide at the JFET center) and peak oxide fields in the center of the JFET gap are shown in Fig. 6 as a function of the value, for values of either 0 V or -8 V . The negative gate bias increases the oxide field and the SiC field at the JFET center, for all values. The results in Fig. 6 show that the electric fields in the JFET region with of 1100 V and of -8 V are equal to the electric fields obtained with of 1360 V with . If the SEB failure were controlled by the JFET fields alone, then at , applying would result in a similar SEB rate to that at with . From Fig. 1 that would indicate that the SEB rate should increase when is applied; but from the results in Fig. 2 this is clearly not the case. Only a increase in SEB is observed when increasing the from 0 to -8 V at .

Considering the rate of SEB failure observed from and changes in Figs. 1 and 2, and the electric field simulations, the SEB failure rate is clearly more strongly dependent on than , in the valid ranges of device operation. The drain field effects of the applied dominate the SEB failure rate overall because the locations of the device going into avalanche breakdown are controlled primarily by the drain bias. The effect on avalanche voltage of field changes at the top of the JFET region due to VGS effects are very small. Note that the peak SiC fields where avalanche breakdown would be initiated are below the P -shielding region (in Figs. 3 and 4), which is not significantly affected by the applied . The electric field in the JFET region due to applied gate bias would only affect the SEB rate if it changes the electric field where the field peaks occur (making avalanche breakdown more likely), which it does not.

These results, which indicate that the JFET region is not a significant contributor to SEB failure, is in general agreement with other results [5,6] which show that the failure rates of SiC diodes and SiC MOSFETs are similar when the data are properly scaled to device active area and drift field, using avalanche breakdown field as a normalization factor. Device turn-off with negative VGS poses no significant SEB risk, because the SEB failure rate is dominated by the applied drain bias.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.463.pdf

The measured SEB failure data shows that applying at only results in a increase in the SEB failure rate. This generally agrees with the TCAD simulations showing that the oxide field and peak SiC field in the JFET center only slightly increase with negative VGS applied. The effects of the applied on SEB failure rate are much larger than the effect of applying a small negative VGS. The peak SiC fields, which determine the avalanche voltage, are in the drift region below the JFET region (in the P -shielding region), and these are not significantly affected by the applied . Thus, the SEB failure is dominated by the effects of the drain bias, and gate bias effects are minimal.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.463.pdf

E. Normand, D. L. Oberg, J. L. Wert, J. D. Ness, P. P. Majewski, S. Wender, and A. Gavron, IEEE Trans. Nucl. Sci. 41(6), 2203 (1994).

H. R. Zeller, Sol. State Electron. 38(12), 2041 (1995).

H. Asai, K. Sugimoto, I. Nashiyama, Y. Iide, K. Shiba, M. Matsuda, and Y. Miyazaki, IEEE Trans. Nucl. Sci. 59(4), 880 (2012).

T. Shoji, S. Nishida, K. Hamada, and H. Tadano, Jpn. J. Appl. Phys. 53, 04EP03 (2014).

D.J. Lichtenwalner, B. Hull, E. Van Brunt, S. Sabri, D.A. Gajewski, D. Grider, S. Allen, and J.W. Palmour, A. Akturk and J. McGarrity, IEEE IRPS, pp. 2B.2.1-2B.2.6 (2018).

D.J. Lichtenwalner, A. Akturk, J. McGarrity, J. Richmond, T. Barbieri, B. Hull, D. Grider, S. Allen, and J.W. Palmour, Mat. Sci. Forum Vol. 924, 559-562 (2018).

D.J. Lichtenwalner, S. Sabri, E. van Brunt, B. Hull, S.-H. Ryu, P. Steinmann, A. Romero, S. Ganguly, D.A. Gajewski, S. Allen, and J.W. Palmour, 2020 IEEE International Integrated Reliability Workshop (IIRW), 2020, pp. 1-6, doi: 10.1109/IIRW49815.2020.9312873.

JEDEC publication JEP151, Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices (Dec. 2015).

N. Kaminski, A. Kopta, Failure rates of HiPak modules due to cosmic rays, Application Note 5SYA 2042-04 (2013).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 468-471

doi: 10.4028/p-c6r9il

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-02

Revised:
2022-03-09

Accepted:
2022-03-17

Online:
2022-05-31

Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

The original version of this paper is available on https://www.scientific.net/MSF.1062.468.pdf

Siva Kotamraju , Pavan Vudumula

Indian Institute of Information Technology, Sri City, India.

siva.k@iiits.in, pavan.vudumula@iiits.in

Keywords: 6 H -SiC, MOS capacitor, gas sensing, interface states.

Abstract

Comparison of C-V characteristics and interface trap distribution for MOS capacitor with AlN and as high-k dielectric are presented. It is observed that the transition from accumulation to inversion requires a small change in gate voltage for compared to AlN . Furthermore, larger shift in flat band voltage with respect to frequency is observed in case of AlN. A larger change in capacitance with respect to voltage and flat band voltage shift with respect to frequency for AlN indicated a poor choice for MOS capacitor compared to .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.468.pdf

Apart from silicon carbide (SiC) MOSFET's and Schottky diodes, SiC based metal oxide semiconductor (MOS) capacitors has been implemented for gas sensing applications [1]. The presence of these devices as gas sensors in harsh environment exhaust streams help in minimizing pollution. However, these devices are limited by oxide reliability at high temperature. Due to the presence of high level of interface traps with silicon dioxide ( ), other high-k dielectric layers have been extensively explored [2], [3]. In this study, a comparison in terms of characteristics and trap distribution between the two commonly used high-k dielectrics ( AlN and ) for SiC is reported. The aim is to identify the suitable high-k dielectric for SiC MOS structure used in sensor applications considering same interface trap distribution.

Methodology

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The SiC MOS structure shown in Fig. 1 is constructed and simulated using the synopsys sentaurus device simulator at a fixed oxide thickness ( 50 nm ) and lattice temperature ( 700 K ). A fixed oxide charge of 1E12 is defined in the oxide along with uniform distribution of oxide-interface traps ( ) from mid bandgap to conduction band. In the presence of hydrogen environment, a decrease in metal work function was reported by the presence of atoms at the surface [4]. The value of Pd (Palladium) work function has been changed to 4.12 eV (from 5.12 eV ), to take the influence of into account. Palladium is chosen as gate material due to solubility of . The electrical simulation of the device requires accurate mesh resolution at interfaces and field oxide corners which resulted in 25,000 mesh nodes. The physical models include recombination-generation process (R-G) or Shockley-read-hall (SRH) process with doping and temperature dependency, auger recombination model [5]. Mobility along the interface modelled by Philips unified mobility model (Phumob) and Lombardi model to account for the mobility degradation at and interface due to acoustic phonon scattering, electron-hole scattering and surface roughness. Doping dependence, field dependence, and incomplete ionization, anisotropic effects were considered into effect to predict the performance accurately. The influence of interface traps on characteristics of the MOS capacitor are analyzed at high frequency ( 1 MHz ) by varying the interface trap density from 2E12 to 1E13 . The fixed and uniform trap distribution is analyzed for both and structures at 700 K with respect to band energy levels. For better analysis frequency is varied ( ) to observe the flat band voltage ( ) shift for both structures at 700 K .

Fig. 1. Schematic cross-sectional view of MOS capacitor with high-k as dielectric.

Fig. 1. Schematic cross-sectional view of MOS capacitor with high-k as dielectric.

Results and Discussion

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The sensitivity to hydrocarbons can be related to changes in capacitance at a constant gate voltage. In other words, there should be constant capacitance in accumulation and inversion regions and steep slope in the depletion region. Fig. 2a and Fig. 2b show the maximum capacitance normalized curves between hafnium oxide ( ) and aluminum nitride ( AlN ) dielectrics at different interface trap densities. Interestingly, there is a decrement in the capacitance value in the accumulation region for interface which is absent for the interface. This result means that AlN has inferior interface properties compared to .

Fig. 2. Normalized C-V characteristics of (a) and (b) capacitor at different trap concentrations.

Fig. 2. Normalized C-V characteristics of (a) and (b) capacitor at different trap concentrations.

Fig. 3a and Fig. 3b show the trap density as a function of band gap energy for and SiC interface respectively. Uniform distribution of traps from mid band gap to the conduction band and an exponential distribution closer to the conduction band edge has been defined at the interface.

Fig. 3. Trap distribution versus band gap energies of (a) and (b) interface.

Fig. 3. Trap distribution versus band gap energies of (a) and (b) interface.

The uniform energetic distribution of traps for a given concentration is given by , whereas for exponential it is . Here (Energy-mid) and (Energysigma) are the trap parameters in eV ( 0.8 and 1.6 for uniform distribution, 0 and 0.04 for exponential distribution respectively). With the increase in trap concentration, we can see that the uniform distribution reduces rapidly and move away from the conduction band edge for interface.

Fig. 4. at different frequencies for (a) and (b) interface by sweeping gate voltage from -12 V to 12 V .

Fig. 4. at different frequencies for (a) and (b) interface by sweeping gate voltage from -12 V to 12 V .

Fig. 4 a and Fig. 4 b shows the frequency dependent curves simulated with frequencies ranging from 1 kHz to 10 MHz for and interface respectively. The shift in curves from depletion to accumulation with respect to voltage is more in case of interface compared to - SiC interface for the frequency range considered. In other words, the frequency has less influence on the flat band voltage shift for - SiC interface.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.468.pdf

Two-dimensional physics-based simulation of a MOS capacitor for and interface has been presented. Results have shown that the change in the characteristics of is very steep without degradation in accumulation when compared with interface. The voltage shift for frequency range ( ) is comparatively less in interface than interface. Therefore, a MOS capacitor with interface is recommended over for detection of hydrogen at higher temperatures, over 700 K .

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.468.pdf

A. Tirinchy, S. Kandasamy, and W. Wlodarski, High temperature field effect & hydrocarbon gas sensors based on SiC MOS devices, Sensors and Actuators B, 133 (2008), 705-716.

M.T. Soo, K. Y. Cheong and A. Noor, Advances of SiC based MOS capacitor hydrogen sensors for harsh environment applications, Sensors and Actuators B, 151 (2010), 39-55.

Md H. Rahman , Dual mode operation of a Pd/AlN/SiC device for hydrogen sensing, Sensors and Actuators B, 129 (2008), 35-39.

B. Ofrim, F. Undrea, G. Brezeanu and A. Hsieh, Influence of oxide layer thickness and SiC polytype on SiC MOS capacitor hydrogen sensor performance, Advances in Sensors, Signals, Visualization, Imaging and Simulation, 12 (2012). 67-72.

Sentaurus Device User Guide, Synopsys Inc., 690 E. Middlefield Road, Mountain View, CA 94043, Version M2016.12 (December 2016)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 472-476

doi: 10.4028/p-cg93gc

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-07

Revised:
2022-02-10

Accepted:
2022-03-17

Online:
2022-05-31

Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

The original version of this paper is available on https://www.scientific.net/MSF.1062.472.pdf

Univ. Grenoble Alpes, CNRS, Grenoble INP*, G2Elab, F-38000 Grenoble, France

*Institute of Engineering Univ. Grenoble Alpes

G2Elab, 21 rue des martyrs, CS 90624, 38031 Grenoble CEDEX 1, FRANCE

SuperGrid Institute, 23 rue Cyprian, BP1321, 69611 Villeurbanne CEDEX, FRANCE

cedric.mathieudevienne@supergrid-institute.com, pierre.Lefranc@g2elab.grenoble-inp.fr, besar.asllani@supergrid-institute.com, pierre-olivier.jeannin@g2elab.grenoble-inp.fr, bruno.lefebvre@supergrid-institute.com

Keywords: Series-connection, SiC-MOSFET.

Abstract

In this paper, a prototype of 6 series-connected SiC-MOSFETs for double pulses test purpose is presented. This prototype represents many challenges amongst which the measurements of voltage sharing and the EMI issues due to high . High voltage tests are performed up to 8 kV at 65 A and voltage balancing, losses and switching speeds are evaluated. Switching speed up to are recorded.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.472.pdf

In the context of the development of converters in the range of mega-Watt for grid applications with voltage ratings up to tens of -MOSFETs are considered as a promising option. Seriesconnection of MOSFETs has similar conduction resistance at on-state compared to single HighVoltage MOSFET for the same breakdown voltage and the same active chip area [1]. Switching performances are expected to be high. Unfortunately, some solutions applied to reach accurate voltage balancing decrease the switching speeds. Switching performances remain highly better than highvoltage Si -IGBT allowing switching frequency up to hundreds of kHz .

To reach a breakdown voltage of -MOSFETs ( from Wolfspeed) are connected in series. These MOSFETs have a breakdown voltage above 2.2 kV allowing to safely work at 8 kV with 6 MOSFETs. In order to evaluate performances of series-connected SiC-MOSFET with the simplest and reliable drain-source voltage balancing, a prototype is developed with passive snubbers. The focus is made on voltage balancing, gate-drivers supplies and measurement issues. This prototype is designed for 10 kV and tests are performed up to 8 kV . Fast switching speeds are obtained as expected with SiC-MOSFET devices leading to significant common mode current through insulation barriers and measurement equipment.

Voltage Balancing

The original version of this paper is available on https://www.scientific.net/MSF.1062.472.pdf

Snubber circuits. Snubber circuits (Fig. 1) are commonly used to optimize switching trajectory and damp the voltage and current ringing but also to balance voltage across devices connected in series. Snubbers are simple, robust, cheap and simple to implement. In some cases, it is relevant to use a resistor-capacitor-diode (RCD) snubber to charge the capacitor through the diode reducing losses in the resistor at turn-off and then discharging the capacitor at turn-on into the resistor. RCD snubber allows dynamic voltage balancing of series-connected switches since it creates a capacitor voltage divider bridge. Static voltage balancing is then obtained thanks to parallel connected resistors that compose a voltage divider.

Fig. 1: RC snubber and RCD snubber

Fig. 1. RC snubber and RCD snubber

Selection of capacitance is different depending on the snubber objective. If the objective is to damp overvoltage then values is selected to be large enough to store the energy of the stray inductance [2]. Otherwise, if the goal is to balance voltages, the capacitor value is usually selected to be 5-10 times larger than output capacitance value at high voltage of the switching devices [3].

Prototype. The series-connection of MOSFETs is built on a PCB that allows fast and cheap manufacturing. MOSFETs and snubber diodes are soldered as surface mounted components by bending pins in this way there is no holes breaking epoxy isolation. Regarding gate-driver circuits, push-pulls with gate resistors are placed as close as possible to MOSFETs on the same PCB. Gate driver power supplies need high voltage insulation. Bespoke 15 kV insulated flyback (with 9pF of isolation capacitance) are used to supply multiple gate drivers as described on Fig. 2. Each gate driver has small commercial isolated DC-DC converter. Gate signals are insulated thanks to Plastic Optical Fiber (POF). Gate-driver signals can be manually synchronized with nanosecond precision on the optical fiber emitter board that has been specifically designed.

Fig. 2 : Series connected MOSFETs with gate-driver supplies in a double pulse test bench.

Fig. 2. Series connected MOSFETs with gate-driver supplies in a double pulse test bench.

Double pulse test. The test bench is designed to perform short circuit and double pulse tests up to 10 kV . The modularity of this platform means that the stray inductance is not optimized. Total loop inductance is estimated at 400 nH . The half-bridge is built with one or two SiC 10 kV PiN diodes from SuperGrid Institute [4] (used for freewheeling) on high side and the series connected MOSFETs on low-side. The load is a bespoke air-inductor with a value of 1 mH .

Measurement. Current measurement is performed with a shunt resistor. Middle point voltage measurement is measured thanks to high-voltage passive probes P6015A (Tektronix) that have a 75 MHz bandwidth. However, these passive probes cannot be used to measure drain-source voltages sharing since they impact voltage balancing. Parasitic elements have a significant impact on switching behaviors [5] with high switching speed. Connected probes add small capacitance and common mode current path that impact deeply voltage balancing for this high switching speed applications.

One promising solution that is highlighted here is to use insulated differential probes. Such probes have no impedance between probe head and the oscilloscope because of the optical fiber isolation. Some parasites can remain by proximity of the probe head with the circuit. Measurement with high common mode voltage and can be done in a non-intrusive way. The used probe is the Isovu differential probe by Tektronix with the reference TIVP02 bandwidth, differential voltage and common mode voltage).

Switching Performances

The original version of this paper is available on https://www.scientific.net/MSF.1062.472.pdf

Fig. 3 : Switching waveforms measurement at 8 kV and .

Fig. 3. Switching waveforms measurement at 8 kV and .

Balancing. Thanks to these measurements, the voltage balancing can be quantified. Voltage balancing percentage is defined as follows:

Where is the balancing at off state of the MOSFET. The most unbalanced MOSFET has the highest unbalancing percentage. Measurements of Fig. 3 show a maximum unbalancing percentage under . The main voltage unbalance cause is parasitic capacitances though gate drivers supply insulation, other causes are minimized since components are selected, components are not heating and gate driver signals are synchronized.

Losses. An estimation of losses is made by post-processing of the voltage and current . To get accurate results, delays between and are compensated. At turn-off, the measured energy is . This energy is mainly due to snubber capacitors charging. With 2.2 nF for each MOSFET, capacitance energy is:

The remaining 1.8 mJ is lost in the snubber resistor and the MOSFET itself. It could be optimized by reducing the value of energy is dissipated at on-state.

Measured turn-on energy is . Turn-on loss is then: . value is mainly explained by the important recovery current of the diode.

Switching speed. With at turn-off switching, voltage rising slope reach which is well limited by snubber circuit. Contrary to turn-on switching, falling speed is not limited by snubber: voltage speed reaches . At this speed, a significant common mode current passes through the insulation barrier and can potentially damage driver circuits. It could also have functional impact on gate driver circuit and they must be designed with a strong EMI immunity.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.472.pdf

A prototype of 6 series connected SiC-MOSFETs is designed, built and tested in double test up to a bus voltage of 8 kV . It represents a challenge on multiples aspects: voltage balancing, dielectric consideration, EMC immunity and measurements. Thanks to isolated differential voltage probes, it is possible to measure of each MOSFETs in a non-intrusive manner. Balancing percentage is maintained under , meaning that MOSFETs work in safe voltage condition with high switching speed up to at turn-off and at turn-on. Nevertheless, high switching speed represents an EMC risk. Electronic circuits must be designed with low parasitic capacitances (for insulation barriers) and strong EMI immunity and if not enough, switching speed must be slowed down, which unfortunately results in an increase of switching losses. Then snubber values can be optimized to get the best compromise between voltage balancing and switching losses. For this purpose, an optimization tool is under development to optimize the values of components of the snubber circuits based on accurate model of SiC-MOSFET and stray capacitances of the system.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.472.pdf

X. Song, A. Q. Huang, S. Sen, L. Zhang, P. Liu, and X. Ni, "15-kV/40-A FREEDM Supercascode: A Cost-Effective SiC High-Voltage and High-Frequency Power Switch," IEEE Trans. Ind. Appl., vol. 53, no. 6, pp. 5715-5727, Nov. 2017, doi: 10.1109/TIA.2017.2737627.

J. Wang, R. T. H. Li, and H. S. H. Chung, "An investigation into the effects of the gate drive resistance on the losses of the MOSFET-snubber-diode configuration," IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2657-2672, 2012, doi: 10.1109/TPEL.2011.2171723.

K. Vechalapu, S. Bhattacharya, and E. Aleoiza, "Performance evaluation of series connected 1700V SiC MOSFET devices," 2015, doi: 10.1109/WiPDA.2015.7369327.

B. Asllani, H. Morel, L. V. Phung, and D. Planson, " 10 kV silicon carbide PiN diodes-from design to packaged component characterization," Energies, vol. 12, no. 23, pp. 1-12, 2019, doi: 10.3390/en12234566.

Z. Zeng, X. Zhang, F. Blaabjerg, and L. Miao, "Impedance-Oriented Transient Instability Modeling of SiC mosfet Intruded by Measurement Probes," IEEE Trans. Power Electron., vol. 35, no. 2, pp. 1866-1881, 2020, doi: 10.1109/TPEL.2019.2922246.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 477-481

doi: 10.4028/p-b1gfac

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-08

Revised:
2022-02-11

Accepted:
2022-03-17

Online:
2022-05-31

Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

The original version of this paper is available on https://www.scientific.net/MSF.1062.477.pdf

Reza Ghandi , Collin Hitchcock , Stacey Kennerly

GE Research Center, Niskayuna, NY 12309, USA

ghandi@ge.com, collin.hitchcock@ge.com, stacey.kennerly@ge.com

Keywords: Silicon Carbide, Superjunction, Diode, Activation Anneal.

Abstract

We report successful demonstration of 2 kV , SiC super-junction (SJ) PiN diodes formed by deep implantation of Al and N . In our devices, alternating deep n-type and p-type SJ pillars fabricated on a pitch and result in a SJ diode with a measured blocking voltage 500 V higher than comparable non-SJ diodes. Four activation anneals ranging from to were compared for effectiveness in eliminating post-implant lattice damage, and the optimum anneal condition was identified.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.477.pdf

Wide bandgap Silicon Carbide (SiC) power switches and diodes offer the promise of lower conduction and switching losses leading to efficient power conversion. However, for Medium Voltage (MV) class ( ) applications, the advantage of SiC technology is diminished compared to the incumbent Si IGBT technology. MV SiC unipolar devices suffer from high conduction losses at elevated temperatures [1]-[3], and SiC bipolar devices such as IGBTs require a prohibitive 3V junction drop during conduction [4], [5]. SiC super-junctions (SJ) can break the unipolar limit and offer an improved trade-off between specific on-resistance and blocking voltage for MV-class applications. To date, multi-epitaxial growth [6] and trench-refill [7] approaches have been demonstrated for 1.2 kV and 6.5 kV SiC SJ devices. For typical dopant implant energies of several hundred keV , the multi-epitaxial solution for SiC SJs is limited to switches rated to block . Above this rating, the number of epitaxial regrowth steps becomes too large. The trench-refill approach is also challenging, since the refill process tends to produce crystallographic damage, and it is difficult to refill the trenches with the required dopant uniformity. Recently, SiC charge-balanced (CB) diodes and MOSFETs were reported as an alternative solution to SJ devices with a simpler fabrication process [8], [9]. However, the stacked nature of CB devices and the charge carrier redistribution required during switching, results in a device with switching delays that increase with each additional layer, becoming prohibitive when scaling SiC CB devices beyond 4.5 kV .

For scaling beyond 4.5 kV , a new class of SJ devices is being developed that relies on Megavoltlevel implantation to form deep p-type and n-type pillars. This multi-epitaxial SJ approach can be implemented in high voltage SiC devices with a smaller number of regrowth steps. However, highenergy implantation of dopants in SiC may introduce lattice damage that will significantly limit the performance of such devices. Therefore, to evaluate the feasibility of high-energy implantation, single layer 2 kV SiC SJ PiN diodes were fabricated and characterized as a first building block of deepimplanted SJ technology. We employed several activation anneal splits and studied the leakage of PiN diodes to evaluate the presence of lattice damage following high-energy implantation and anneal. We also extracted the Al activation rate of the implanted p-pillars for each anneal split.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.477.pdf

SiC SJ-PiN diodes were fabricated on wafers. A thick n-type epitaxial layer doped to was grown on the starting substrates, and n -type and p -type pillars were formed in the epitaxial layer by multi-energy implantations of Al and N through a patterned, thick, high-density hard mask. The mask was designed to provide enough stopping power to mask implantation energies up to 50 MeV . Implantation was accomplished using a 15 MV Van de Graaff accelerator based tool [10]. To validate the effectiveness of our process in both masking the high
energy implants and aligning the n-type and p-type pillars, a preliminary SiC test wafer was processed and characterized by SEM imaging. In order to improve SEM contrast, implant doses for the test wafer were targeted to achieve dopings of in both the Al and N pillars (four times the device design target of ). Fig. 1 shows a SEM cross section of the fabricated structure. Clearly the masking and alignment process was successful and a pitch SJ structure with deep Al and N doped pillars formed by high-energy implantation is feasible. For subsequent devices wafers, following high energy implantation of the doped SJ pillars, P+ anode and edge termination regions of the diodes were formed using additional low energy Al implantations. Then, the front sides of the wafers were protected with graphitized photoresist in preparation for the dopant activation anneal. To evaluate the effect of temperature in annealing out high-energy implantation lattice damage, four splits were chosen for the anneal (Table1). SJ diode wafers were annealed at temperatures ranging from to in an Ar ambient.

Fig. 1: SEM characteristics of implanted pillars formed on a SiC test wafer.

Fig. 1. SEM characteristics of implanted pillars formed on a SiC test wafer.

Table 1: Activation anneal splits for SiC SJ PiN diodes

Split | Activation Anneal Temperature (°C) | Duration (hours)
1 | 1700 °C | 30 min
2 | 1800 °C | 120 min
3 | 1900 °C | 60 min
4 | 2000 °C | 40 min

The graphite layer was removed following the high temperature activation anneal and the SiC surface roughness was measured using an optical profilometer in special test areas distributed across the wafers. Fig. 2(right) shows the average surface roughness for each of the implanted regions. Surface roughness seems to be relatively independent of implantation type, but varies with activation temperature, with a maximum roughness for the highest activation anneal at . The graphite layer appears to be capable of protecting the front surface during high temperature anneal. However, the wafer back surface was not protected and was significantly altered following activation. As shown in Fig. 2(left), the topography of the SiC back surface shows a marked difference between split 1 and the higher temperature splits. This suggests fundamentally different surface kinetics at temperatures above .
Forward IV characteristics of PiN diodes and extracted differential specific resistances at are plotted in Fig. 3(right). From this plot, higher activation anneal temperatures increase specific on-resistance from for activation anneal split 1 to and for activation anneal splits 3 and 4 respectively. We believe altered surface topography for anneal
temperatures above has adversely affected the cathode contact resistance, and protecting the wafer backside with graphite during activation can avoid this cathode contact damage.

Fig. 2 Left: SiC front-side surface roughness over different implanted regions versus activation anneal splits. Right: SEM images of wafer backsides following high temperature activation anneal.

Fig. 2. Left: SiC front-side surface roughness over different implanted regions versus activation anneal splits. Right: SEM images of wafer backsides following high temperature activation anneal.

Fig. 3 Left: Forward IV characteristics of SiC SJ PiN diodes and extracted differential Ron (inset) for different activation anneal splits. Right: Reverse IV characteristics of SiC SJ-PiN diodes for different activation anneal splits.

Fig. 3. Left: Forward IV characteristics of SiC SJ PiN diodes and extracted differential Ron (inset) for different activation anneal splits. Right: Reverse IV characteristics of SiC SJ-PiN diodes for different activation anneal splits.

Reverse IV characteristics of SJ PiN diodes and simulated blocking plots for ideal SJ diodes and nonSJ diodes with similar initial drift layer doping profiles ( thick and doped to ) are plotted in Fig. 3(left). From this plot, diodes with activation anneal splits 3 and and ) result in breakdown voltages of . This blocking level is 500 V higher than the simulated breakdown voltage of SiC non-SJ diodes and is similar to the simulated plot for an ideal SiC SJ PiN diode. Therefore, we conclude that our implanted n-type and p-type SJ pillars achieve active doping levels close to charge-balance, providing higher blocking voltage for SiC PiN diodes that cannot be achieved with non-SJ structures. However, activation anneal splits 1 and and ) suffer from high leakage current prior to the breakdown and suggests that to fully anneal lattice damage generated during high-energy implantation an activation anneal at is required.

The activation rate of the implanted Al p -pillars was extracted from capacitance-voltage (CV) structures fabricated in test areas of the device wafers. In Fig. 4, a capacitance-voltage plot and extracted profile of electrically active Al over a depth of the p -pillar implanted region is plotted for the activation anneal splits. No significant difference is observed in capacitance values and
extracted active Al concentrations between different anneal temperatures. Extracted Al concentration for p-pillar implants for all activation splits was close to the implant target of . This suggests that unlike high dose Al implantation in SiC , activation anneal at can fully activate low dose Al implantations in SiC . This is in agreement with Al activation models previously reported [11].

Fig. characteristics (left) and extracted active Al doping (right) in p-pillar implanted PiN diodes for different activation anneal splits.

Figure 4. Fig. characteristics (left) and extracted active Al doping (right) in p-pillar implanted PiN diodes for different activation anneal splits.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.477.pdf

2 kV SiC SJ PiN diodes were fabricated using high-energy implantation of Al and N. SJ diodes showed measured blocking voltage 500 V higher than comparable non-SJ diodes. Four different activation anneal splits were employed to remove lattice damage following high-energy implantation. The data shows that SiC SJ PiN diodes annealed at and below, suffer from high blocking leakage and anneals at are required for maximum damage recovery. However, activation anneal temperatures as low as can fully activate low dose implanted Al in SiC .

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.477.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DEAR0001007 advised by Program Director Isik Kizilyalli. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

Centrotherm international AG is also acknowledged for running activation anneal splits in their most current activator tool.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.477.pdf

A. Bolotnikov et al., 2015 IEEE Appl. Power Electron. Conf. Expo., pp. 2445-2452, 2015.

P. A. Losee et al., Mater. Sci. Forum, vol. 858, pp. 876-879, May 2016.

L. Knoll et al., 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2018, pp. 451-454.

L. Han, L. Liang, Y. Kang, and Y. Qiu, IEEE Trans. Power Electron., vol. 36, no. 2, pp. 20802093, Feb. 2021.

Q. Zhang and A. K. Agarwal, phys. stat. sol., vol. 206, no. 10, pp. 2431-2456, 2009.

T. Tanaka et al., 2018 IEEE Int. Electron Devices Meet., pp. 8.2.1-8.2.4, 2019.

R. Kosugi et al., 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2019, pp. 39-42.

R. Ghandi, A. Bolotnikov, D. Lilienfeld, S. Kennerly, and R. Ravisekhar, 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2019, pp. 179-182.

R. Ghandi, A. Bolotnikov, S. Kennerly, C. Hitchcock, P. Tang, and T. P. Chow, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Sep. 2020, pp. 126129.

P. Thieberger et al., Nucl. Instruments Methods Phys. Res. Sect. B Beam Interact. with Mater. Atoms, vol. 442, pp. 36-40, Mar. 2019.

V. Simonka, A. Hossinger, J. Weinbub, and S. Selberherr, IEEE Trans. Electron Devices, vol. 65, no. 2, pp. 674-679, Feb. 2018.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 482-486

doi: 10.4028/p-2wi7o8

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-11

Revised:
2022-02-14

Accepted:
2022-03-17

Online:
2022-05-31

AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

Marie Lesecq , Eric Frayssinet , Marc Portail , Micka Bah , Nicolas Defrance , Thi Huong Ngo , Mahmoud Abou Daher , Marcin Zielinski , Daniel Alquier , Jean-Claude De Jaeger and Yvon Cordier

Keywords: Epitaxy, GaN HEMT, high frequency.

Abstract

In this work, an AlGaN/GaN HEMT structure is grown on a thick 3C-SiC layer on high resistivity Silicon substrate. The RF propagation losses are investigated and compared with the ones of epi-layers grown directly on Silicon and on substrates. Short gate length transistors are fabricated using e-beam lithography. In spite of ohmic contact resistance of , a saturated current density of at a gate bias of +1 V and a transconductance peak higher to for 75 nm T-shaped gate transistors are reached on structure with thick 3C-SiC template. Moreover, for the first time, transition frequencies of are reported on such 3C-SiC template.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

Gallium nitride based devices show clearly their outstanding performances for microwave power applications. These performances are strongly linked with the properties of the substrate used for the epimaterial growth. Best performances are obtained on GaN-on-SiC (Silicon Carbide) devices [1] but SiC substrates suffer from lower availability compared to Silicon ones permitting also to get GaN devices with interesting high frequency performances [2]. However, these last devices still suffer from the difficulty to grow high crystal quality crack-free RF compatible GaN based epilayers. Typically, AlGaN/GaN epilayer High Electron Mobility Transistor (HEMT) structure starts with the growth of an AlN nucleation layer. The growth parameters of this layer strongly influence the propagation losses due to the risk of diffusion of Al and/or Ga into the Si substrate [3-4]. It has been reported that the use of cubic ( ) intermediate layer as a template for the growth of AlGaN/GaN HEMT heterostructures on Si substrate limits the risks of cracks generation, enhances the crystal quality of the GaN film [5-6] and limits the degradation of Silicon substrate resistivity permitting to preserve low RF propagation losses [7]. RF performances were reported on AlGaN/GaN HEMTs on 3C-SiC/Si substrates using an ultrathin 3C-SiC intermediate layer deposited by CVD (Chemical Vapor Deposition) followed by AlGaN/GaN growth by MOCVD (Metal Organic Chemical Vapor Deposition). A current gain cut off frequency ( ) of 176 GHz and a maximum oscillation frequency of 70 GHz were obtained on an 80 nm -rectangular gate length device [8]. Furthermore, and
of 110 GHz were obtained on 100 nm tri-gate devices associated with an ratio of [9]. Beyond these achievements, the thickening of the 3C-SiC intermediate layer seems to be promising to improve the thermal dissipation, to reduce the propagation losses and to increase the RF performance. Relatively low losses can be obtained on HEMT buffer layers grown on Si with a thick 3C-SiC intermediate layer despite the limited initial resistivity of the substrate [7,10] but the demonstration of high frequency performance transistors fabricated on such thick template is still lacking.

Material Growth and Device Technology.

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

Intrinsic Silicon substrate with an initial resistivity higher than is used as a starting substrate. Then, a thick 3 C -SiC transition layer is grown at around by CVD on this substrate. After a chemical mechanical polishing of the 3C-SiC template, the AlGaN/GaN HEMT structure is grown by MOCVD using conditions previously described in [7]. The epitaxial structure consists of a -thick GaN buffer layer on a thick AlGaN/AlN stress accommodation sequence (Fig.1) and followed by an barrier capped with 3 nm -thick SiN layer. A 1 nm thick AlN exclusion layer is used to reduce alloy scattering and improve carrier confinement within the two-dimensional electron gas ( 2 DEG ). For comparison purposes, a similar AlGaN/GaN heterostructure is grown on a high-resistivity bulk 6H-SiC substrate.

Figure 1. (left) Cross section picture of the HEMT structure grown on ; (right) Top: scanning spreading resistance microscopy (SSRM) showing the resistivity drop at AlN/Si interface. Bottom: absence of resistivity drop at AlN/3C-SiC and 3C-SiC/Si interfaces

Figure 1. Figure 1. (left) Cross section picture of the HEMT structure grown on ; (right) Top: scanning spreading resistance microscopy (SSRM) showing the resistivity drop at AlN/Si interface. Bottom: absence of resistivity drop at AlN/3C-SiC and 3C-SiC/Si interfaces

Before the device process, the electrical properties of epilayers are first evaluated with contactless sheet resistance measurements using an Eddy current setup and with mercury-probe CapacitanceVoltage (Hg-CV). The electrical behaviour of the AlN and 3C-SiC epi-layers is studied via scanning spreading resistance microscopy (SSRM) on a bevelled sample as described in [4]. Propagation losses are measured in the frequency range on coplanar waveguides fabricated on the epilayer after ion implantation for isolation. E-beam based technological process is performed to fabricate short gate length devices. metal stack annealed at for 30 s is used to form the source and drain ohmic contacts. T-shaped Schottky gates are then defined. A layer is deposited by PECVD as final passivation. To assess the 2DEG low field transport properties, Hall effect measurements are performed on-wafer on Van der Pauw patterns defined nearby transistors.

Results and Discussion.

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

Table 1 compares the RF propagation losses measured at 40 GHz in the present HEMT with ones of structures grown with a single stress mitigating layer ( 350 nm thick ) on or directly on . Losses are also reported for a HEMT structure grown with a thick GaN buffer layer on . In the present cases, propagation losses are mainly due to parasitic conduction in the epilayers and/or in the substrate. Our previous study of layers grown directly on Silicon has shown that Gallium was mainly responsible for the detrimental reduction of electrical resistivity at the AlN/Si interface [4]. As shown in table 1, losses obtained on 3C-SiC are noticeably lower than those on the structure grown directly on Silicon. It can be also noted that, the insertion of a thicker stack with three AlGaN steps in the present HEMT buffer layer did not change the losses which are around at 40 GHz . Furthermore, the losses obtained on the structure on semiinsulating 6H-SiC clearly illustrate the better stability of such substrate against parasitic doping with III-metal elements during the nucleation and growth of the III-Nitride epilayers.

Table 1. Propagation losses at 40 GHz in the epi-layers grown on templates and substrate.

Grown structure | Substrate resistivity [ohm.cm] | Losses at 40 GHz [dB/mm]
GaN on Si(111) | > 5000 | 1.2
GaN on 3C-SiC/Si(111) | > 5000 | 0.38
HEMT on 3C-SiC/Si(111) | > 5000 | 0.41
HEMT on 6H-SiC | semi-insulating | 0.25

The SSRM analysis of the lower parts of structures grown on Silicon and on are compared in Fig.1. Contrary to the layers grown directly on Silicon, no drop of electrical resistivity is noticed at the -SiC interface, nor at the interface between 3C-SiC and Silicon. This analysis confirms the macroscopic resistivity measurements revealing sheet resistances below typically for direct growth on Silicon while they overpass on the present templates. Hg-CV performed on the present HEMT grown on 3C-SiC indicates a 2DEG charge density close to confirmed by Hall effect measurements revealing a high electron mobility near .s and a sheet resistance of . The HEMT heterostructure grown on 6 H -SiC exhibits a 2DEG density of and a sheet resistance around .

Figure 2. DC output characteristics of a gate transistor fabricated on the HEMT heterostructure grown on (a) , (b) and (c) to steps . (d) comparison of gains measured on the transistors.

Figure 2. Figure 2. DC output characteristics of a gate transistor fabricated on the HEMT heterostructure grown on (a) , (b) and (c) to steps . (d) comparison of gains measured on the transistors.

Devices under test (DUT) in this work feature a two-finger configuration with a gate width ( W ) of , a gate length of 75 nm and a source-to-drain spacing ( ) of . Fig.2. shows the DC output characteristics of the devices. On 3C-SiC/Si, a knee voltage under 3 V and a clear saturation of the drain current are obtained. A saturated current density of is reached at a gate bias . The peak transconductance is at and . A threshold voltage of -3.2 V is deduced from the transfer characteristic (not shown). The gate leakage current is as low as . On , a saturated current density of is obtained at . The peak transconductance is at and . The ohmic contact resistance around is the same on both HEMT structures. The current gain transition frequency ( ) and the maximum oscillation frequency ( ) are directly extracted from the first order frequency extrapolation ( -20 dB /decade) of current gain modulus ( ) and Mason's unilateral gain (U) respectively for a bias point corresponding to the maximum of transconductance. On 3C-SiC/Si, at and , extrinsic current gain cutoff frequency and maximum power gain cutoff frequency are obtained. On 6H-SiC, slightly higher transition frequencies and are obtained at and . These performances are limited by the ohmic contact resistance and the sheet carrier density correlated with the low ( ) Al content regarding the thickness of the AlGaN barrier ( 10 nm ) as well as by some trapping effects. On Si, and . The increase of the Al content up to [11] combined with a well-suited passivation step may result in improved microwave performance.

Conclusion.

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

In this work, AlGaN/GaN HEMT structures are grown by MOCVD on different substrates. Compared with direct growth on Silicon substrate, a clear benefit appears in terms of electrical resistivity for buffer layers grown on thick templates resulting in reduced RF propagation losses.

Transistors fabricated on such template show performances close to those obtained on semi-insulating bulk SiC substrates, with in particular a maximum oscillation frequency of 100 GHz confirming the interest of these devices for high-frequency applications at reduced cost.

Acknowledgments.

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

This work was supported by the technology facility network RENATECH and the French National Research Agency (ANR) through the projects ASTRID GoSiMP (ANR-16-ASTR-0006) and the "Investissement d'Avenir" program GaNeX (ANR-11-LABX-0014). This research work has been partially undertaken with the support of IEMN fabrication (CMNF) and characterization (PCMP).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.482.pdf

K. Harrouche et al, Journal of the Electron Devices Society 7 (2019) 1145.

P. Cui et al, Applied Physics Express 12 (2019) 104001.

S. Chang et al, Semiconductor Science and Technology 35 (2020) 035029.

M. Bah et al, Scientific Reports 10 (2020) 14166.

Y. Cordier et al, Journal of Crystal Growth 310 (2008) 4417.

S. Leone et al, Journal of Applied Physics 125 (2019) 235701.

E. Frayssinet et al, Phys. Status Solidi A 217 (2020) 190060.

W. Jatal et al, IEEE Electron Device Letters 36 (2015) 123.

W. Jatal, et al, Phys. Status Solidi A 214 (2017) 415.

A. Bose et al, IEEE Electron Device Letters, 41 (2020) 301948.

E. Frayssinet et al, Phys. Status Solidi A 214 (2017) 1600419.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 487-492

doi: 10.4028/p-7j50kd

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-12

Revised:
2022-02-08

Accepted:
2022-03-17

Online:
2022-05-31

Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

The original version of this paper is available on https://www.scientific.net/MSF.1062.487.pdf

Felix Hoffmann , Stefan Schmitt , Nando Kaminski

University of Bremen, Institute for Electrical Drives, Power Electronics and Devices (IALB), Otto-Hahn-Allee 1, 28359 Bremen, Germany

Semikron Elektronik GmbH&Co. KG, Sigmundstraße 200, 90431 Nuremberg, Germany felix.hoffmann@uni-bremen.de, stefan.schmitt@semikron.com, nando.kaminski@uni-bremen.de

Keywords: SiC, MOSFET, Si, IGBT, Reliability, High Humidity High Temperature Reverse Bias, H3TRB, Comparison, Failure Analysis

Abstract

In this work, the performance of power modules with SiC MOSFET chips is investigated and compared to their silicon counterparts with similar electrical ratings. For this purpose, SiC MOSFETs and silicon IGBT chips are packaged in the same housing and with the same packaging technology and an TRB test is performed on both types of test devices. The results show that while both types exhibit an excellent TRB performance, the SiC MOSFETs had a significantly longer time to failure but also a wider failure distribution. Hence, the investigations presented in this paper confirm that properly designed SiC devices feature an equal or even better ruggedness against electrochemical stress than standard silicon devics and are equally suitable for applications, which require operation in harsh environments.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.487.pdf

The robustness of power devices against electro-chemical stress is an important qualification criterion, particularly for applications such as wind power or traction, in which the power devices are exposed to harsh environmental conditions . The standard test to evaluate the reliability under harsh environmental stress is the High Humidity High Temperature Reverse Bias (H3 TRB) test. During this test, the device is stored in a climate chamber at elevated temperature and humidity with a reverse voltage applied. The test is a common qualification test and test conditions are similarly defined by several standards (e.g. IEC 60749-5 [4]) with a relative humidity of and an ambient temperature of . While the reverse bias is not specifically defined, a high reverse voltage was shown to be more stressful and hence, is commonly chosen in the range of to of the devices' nominal voltage [5]. So far, there are several reports on the performance of SiC devices, which show excellent results. The good performance however, leads to very long run times and therefore, most of those tests are not performed until end of life (EoL) but are terminated after a certain time, or the test is strongly accelerated by applying an even enhanced stress level [6,7,8]. On the other hand, in order to estimate the service life of SiC devices under thermo-mechanical stress and draw a comparison to their silicon counterparts, it is necessary to perform the tests until a sufficient amount of devices failed and a convincing failure statistics can be derived. In this work, the difference in robustness against electro-chemical stress of silicon and SiC power devices is investigated by means of TRB testing of comparable Si IGBTs and SiC MOSFETs in identical packages.

Device Under Test

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As devices under test (DUTs), Si IGBTs and SiC MOSFETs with the same voltage rating of 1200 V and current rating of 25 A were used. Both chips were packaged in identical packages, a baseplateless module with soldered chips, DCB substrate and silicone gel as filler material. A total of 5 modules with silicon IGBTs and 16 modules with SiC MOSFET chips were considered. Some of the SiC MOSFETs modules were exposed to some degree of thermo-mechanical stress prior to TRB testing. However,

Fig. 1: Comparison of the chip size of the tested silicon IGBT and SiC MOSFET chips

Fig. 1. Comparison of the chip size of the tested silicon IGBT and SiC MOSFET chips

Fig. 2: Comparison of the blocking characteristics of one typical silicon IGBT and SiC MOSFET chip, respectively

Fig. 2. Comparison of the blocking characteristics of one typical silicon IGBT and SiC MOSFET chip, respectively

the failure statistics did not indicate any impact on the lifetime, which is consistent with previously reported results for Si devices [9]. Hence, all SiC devices are treated as a single test batch. The devices with the silicon IGBTs are commercially available (SKiiP 13AC12T4V1), and the SiC MOSFET modules are engineering samples, but were manufactured with the same packaging technology. An image of both chips is shown in fig. 1. It is visible that the SiC MOSFET chip is significantly smaller, and even though both devices have comparable electrical ratings, the area of the SiC MOSFETs is only approximately of the silicon IGBT, which shows the general advantages of SiC as a semiconductor material in comparison to silicon. The blocking characteristics of both device types are shown in comparison in fig. 2. The SiC MOSFETs exhibit a significantly lower leakage current and slightly higher avalanche voltage compared to the Si IGBTs. While the former is a result of the low intrinsic carrier concentration and hence, a material related property, the higher avalanche voltage is likely a result of a more conservative junction termination design, owed to the less mature manufacturing processes for SiC semiconductors.

Test Conditions

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To assess the DUTs ruggedness against electro-chemical stress an TRB test was performed on both types. The tests conditions were identical for both device types with a relative humidity of , an ambient temperature of and a test voltage of 960 V , which corresponds to of the devices' nominal blocking voltage. During the test, the leakage current of the devices was monitored and as a failure criterion an increase in leakage current of one order of magnitude was considered. Intermediate measurements (IM) of the blocking characteristics were performed at room temperature every 500 h . Prior to those measurements, the DUTs had been dried at relative humidity and ambient temperature for 24 h . After the measurements, the environmental test conditions temperature and humidity were applied and settled for 24 h before the test was resumed by reapplying the test voltage.

Test Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.487.pdf

This work focus on a detailed discussion of the test performed on the SiC MOSFETs and the results of the Si IGBTs are used as a reference. A detailed report on the TRB test on the Si IGBTs is given in [9].

The leakage current of the SiC MOSFETs at room temperature at 1200 V over the course of the IMs is shown in fig. 3. The characteristics indicate a general trend of the devices to a slight increase in leakage current with more accumulated time under TRB stress. While the leakage current logging is quite consistent for almost all DUTs, one DUT (solid yellow line in fig. 3) showed a peculiar characteristics with a generally higher leakage current and more variability.

Fig. 3: Characteristics of the leakage current of the SiC MOSFETs at 1200 V initially, and for all intermediate measurements, taken every 500 h over the course of the TRB test

Fig. 3. Characteristics of the leakage current of the SiC MOSFETs at 1200 V initially, and for all intermediate measurements, taken every 500 h over the course of the TRB test

During 10000 h of testing, only 11 out of 16 SiC MOSFETs failed. The measurement of the blocking characteristics at room temperature revealed differences among the failed DUTs. The blocking characteristics of three of the failed SiC MOSFETs initially and after EoL, shown in fig. 4, represent the different changes in blocking characteristics occurred during the test. All failed devices exhibit an increase in leakage current towards their EoL. Some of the failed devices exhibit virtually no remaining blocking capability (blue curve in fig. 4), while for other devices the blocking capability was significantly reduced (orange curve in fig. 4). In contrast, some devices still maintained their full blocking capability at room temperature even after device failure (yellow line) but exhibited a significant increase in leakage current.

The propagating degradation of the DUTs also impacted their leakage current characteristics during re-initialization of the test after the intermediate measurements. The initialization characteristics of one DUT is shown in fig. 5. Before the test initialization the climate conditions were settled for 24 h . During the initialization the voltage is increased from 0 V to the test voltage of 960 V with . The characteristics at the beginning of the test (blue line in fig. 5) show a stable leakage current level as soon as the test voltage was reached. After 5200 h of cumulative TRB stress, The DUT exhibited a small overshoot (orange line) and the leakage current stabilized after some time to a slightly elevated leakage current level. After 7800 h of cumulative TRB stress the overshoot is even more pronounced and a further increase in steady-state leakage current level can be observed (yellow line). This behavior can be an indicator of a local degradation, which increases leakage current initially but is self-limiting due to heat generation.

Failure Analysis

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In order to investigate the failure mechanisms, some of the failed devices were decapsulated and visually inspected with an optical microscope. The images, shown in fig. 6 revealed different degradation patterns. Fig. 6a shows dendrite growth with two dendrites reaching from the unprotected part of the

Fig. 4: Blocking characteristics before and after TRB for three of the failed SiC MOSFETs

Fig. 4. Blocking characteristics before and after TRB for three of the failed SiC MOSFETs

Fig. 6: Microscope images of part of the junction termination of two selected chips after the test

Fig. 6. Microscope images of part of the junction termination of two selected chips after the test

top side metallization to outer edge of the chip. Further EDX analysis revealed that the dendrites are composed of silver and grew on top of the polyimide passivation layer. Silver dendrites are a wellknown degradation mechanism and are a classical cause of failure for silicon power semiconductors as well [10]. In fig. 6b a damage of the polyimide coating at the corner of the chip is visible. While the chip with the dendrite showed effectively no remaining blocking capability after EoL, the chip with the damaged polyimide maintained its blocking capability but exhibited an increase in leakage current. This can indicate there might be a correlation between failure mode and failure pattern. However, the data set it not sufficient and further investigations are necessary before a final conclusion can be drawn.

Statistical Analysis

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In order to compare the failure times of the tested SiC MOSFETs with the silicon IGBTs, the Weibull statistics of both tests are considered. The Weibull distribution of the time to failure during TRB

Fig. 7: Weibull plot of the TRB results of both test splits. The dashed lines indicate the confidence interval of .

Fig. 7. Weibull plot of the TRB results of both test splits. The dashed lines indicate the confidence interval of .

for the Si IGBTs and the SiC MOSFETs is shown in fig. 7. The Weibull shape factor is significantly higher for the silicon IGBTs is due to a narrower failure distribution. This can be a result of the more mature processing technology of silicon devices, which results in smaller manufacturing tolerances and hence, more homogeneous device characteristics. In contrast, the Weibull scale factor, indicating the time, at which of the test population has failed, is by a factor of around 4 higher for the SiC MOSFETs, indicating a higher robustness of the SiC devices against electro-chemical stress. While none of the silicon IGBTs survived more than 2500 h during the reference test, all tested SiC devices survived more than 3000 h of cumulative stress.

Summary and Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.487.pdf

In this work, the difference in robustness against electro-chemical stress of silicon and SiC power semiconductors is investigated by performing TRB tests on comparable silicon IGBT and SiC MOSFET chips in identical packages. The results of this work show, that while both device types exhibit an excellent TRB performance far beyond the typical qualification criterion of 1000 h under the applied test conditions, the SiC MOSFET clearly surpassed the Si IGBTs with respect to the time to failure during the test. The significantly better performance of the SiC MOSFETs is consistent with other investigations [2], but counter intuitive due to the smaller junction termination (JT) of the SiC MOSFETs and the much higher electric fields. However, the module with silicon IGBTs is a commercially available product, which had been on the market for some time and hence, does not utilize the most recent silicon IGBT generation. In contrast the tested SiC MOSFETs featuring a state-of-the-art design. Recent results on next generation Si devices [11, 12] indicate that standard JT of Si IGBTs are prone to electro-chemical degradation and that the next generation of the JT offer an order of magnitude better performance - which would then also fit intuition. Hence, the difference in TRB cannot necessarily be attributed to the semiconductor properties but is likely a result of the advanced JT design of state-of-the-art power electronic devices. In any case, the results of this work clearly show that SiC power devices can be designed to exhibit excellent ruggedness against electro-chemical stress and are well-suited for applications, which require operation in harsh environments.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.487.pdf

K. Fischer, M. Steffes, K. Pelka, B. Tegtmeier, and M. Dörenkämper, "Humidity in Power Converters of Wind Turbines-Field Conditions and Their Relation with Failures," Energies, vol. 14, no. 7, 2021. [Online]. Available: https://www.mdpi.com/1996-1073/14/7/1919

C. Zorn, N. Kaminski, and M. Piton, "Impact of Humidity on Railway Converters," in PCIM Europe 2017; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, May 2017.

A. Brunko, W. Holzke, H. Groke, B. Orlik, and N. Kaminski, "Model-based condition monitoring of power semiconductor devices in wind turbines," in 2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe), Sep. 2019.

International Electrotechnical Commission, "IEC 60749-5:2016 - Semiconductor Devices Mechanical and climatic test methods - Part 5: Steady-state temperature humidity bias life test," International Electrotechnical Commission, Geneva, CH, Standard ISO/IEC TR 29110-1:2016, 2016. [Online]. Available:

C. Papadopoulos, C. Corvasce, A. Kopta, D. Schneider, G. Pâques, and M. Rahimo, "The influence of humidity on the high voltage blocking reliability of power IGBT modules and means of protection," Microelectronics Reliability, vol. 88-90, pp. 470-475, 2018, 29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis ( ESREF 2018 ). [Online]. Available:

C. Zorn, F. Hoffmann, M. Hanf, N. Kaminski, F. Allerstam, A. Konstantinov, and T. Neyer, "H3TRB Test on 650 V SiC JBS Diodes," in Silicon Carbide and Related Materials 2017, ser. Materials Science Forum, vol. 924. Trans Tech Publications Ltd, 7 2018, pp. 581-584.

T. Barbieri, A. Barkley, E. Ayerbe, Z. Major, M. Tauer, J. Young, and D. Gajewski, "Reliability Testing of SiC JBS Diodes for Harsh Environment Operation," in PCIM Europe 2018; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2018.

F. Hoffmann, P. Friedrichs, and N. Kaminski, "H3TRB-Test on 1200 V SiC Schottky Diodes After Previous Operation," in PCIM Europe digital days 2020; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, July 2020.

F. Hoffmann, S. Schmitt, and N. Kaminski, "Impact of Combined Thermo-Mechanical and Electro-Chemical Stress on the Lifetime of Power Electronic Devices," in 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), 2020.

C. Zorn and N. Kaminski, "Temperature humidity bias testing on insulated-gate bipolartransistor modules - failure modes and acceleration due to high voltage," IET Power Electronics, vol. 8, no. 12, pp. 2329-2335, 2015.

J.-H. Peters and N. Kaminski, "Improved HV-H3TRB robustness of a 1700 V IGBT chip set in standard power modules," Microelectronics Reliability, vol. 88-90, 09 in press.

S. Kremp and O. Schilling, "Humidity robustness for high voltage power modules: Limiting mechanisms and improvement of lifetime," Microelectronics Reliability, vol. 88-90, 092018.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 493-497

doi: 10.4028/p-ztr5d7

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-02-22

Accepted:
2022-03-17

Online:
2022-05-31

Investigation of SiC Thyristors with Varying Amplifying Gate Design

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

Sigo Scharnholz , Ralf Hassdorf , Dirk Bauersfeld , Bertrand Vergne , Luong Viêt Phung and Dominique Planson

French-German Research Institute of Saint-Louis (ISL), 5 rue du Général Cassagnou, 68300 Saint-Louis, France

Univ Lyon, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, CNRS, AMPERE, F-69621, Lyon, France

sigo.scharnholz@isl.eu, ralf.hassdorf@isl.eu, dirk.bauersfeld@isl.eu, bertrand.vergne@isl.eu,

*corresponding author

Keywords: Thyristor, Amplifying gate, Device fabrication, Etched JTE, Turn-on characteristic, Onstate characteristic.

Abstract

This paper presents experimental thyristors with different amplifying gate design. In contrast to comparative devices (with simple gate) the amplifying gate thyristors show a characteristic snap-back and a higher gate current to trigger. Their gate-anode I-V characteristics comply with the underlying design constraint, regarding the resistances of pilot and main thyristor: . Moreover, the turn-on waveforms of well-designed amplifying gate thyristors reveal peakshaped inversions in the gate current and voltage transients, providing clear evidence of the successive triggering of pilot and main thyristor.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

Due to their superior performance in terms of current density and blocking voltage, silicon carbide (SiC) thyristors are of particular interest for pulsed power applications [1-3]. Furthermore, in view of the tremendous progress made in SiC crystal quality and wafer size, large-area SiC thyristors appear to be in reach today. In this context, both electrically and optically triggered SiC thyristors require adequate amplifying gate structures. With the aim to investigate this aspect, a mask set featuring numerous SiC thyristor devices with varying amplifying gate structures has been conceived [4]. And based thereon, a 100 mm epitaxial SiC wafer was processed recently. Resulting from this process run, the present paper reports on the electrical characteristics measured on-wafer as well as on singularized and encapsulated SiC thyristor devices with and without amplifying gate.

Device Fabrication and Structure

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

The fabricated devices are asymmetrically blocking, vertical SiC thyristors, of which the thick p-base (drift) layer ( ) is separated by a p-type buffer ( ) from the wafer substrate ( ). The n -base (gate) and the anode layers have a nominal thickness (and doping concentration) of and , respectively. The gate and the single-step junction termination extension (JTE) are formed simultaneously by reactive ion etching (RIE). A second RIE step was used to define the JTE length and thus the device mesa. Following the etching, the primary metallization of gate/cathode ( ) and anode ( ) was realized separately by e-beam evaporation, lift-off, and subsequent annealing. The surface was passivated with thick, deposited . The over-metallization consists of and on the top-side (anode/gate) and the backside (cathode) contacts, respectively.

Fig. 1 shows a scheme of a circular SiC amplifying gate thyristor with characteristic dimensions (radii). All fabricated amplifying gate thyristors have a central, circular gate ( G ) with a radius of and a main anode (A), expanding from an inner radius of to a distance of . Therefore, all devices have the same size of the anode and thus the same resistance of
the main thyristor (cf. cross-section in Fig.1). At the distance of , either ring-shaped or dotted anode shorts are situated for devices with a circular or a square-shaped anode, respectively. With a JTE length of and a security margin to the cutting edge, the die size measures . Fig. 2 depicts one of the experimental amplifying gate thyristors with square-shaped anode and dotted anode shorts.

Fig. 1. Scheme of an SiC amplifying gate thyristor, consisting of a pilot thyristor (index P) in the centre and a main thyristor (index M) with the characteristic resistances and .

Fig. 1. Scheme of an SiC amplifying gate thyristor, consisting of a pilot thyristor (index P) in the centre and a main thyristor (index M) with the characteristic resistances and .

Fig. 2. Micrograph of an experimental, SiC amplifying gate thyristor with square-shaped anode and dotted shorts ( ). Gate (centre) and anode wedge-bonded with wires, cathode (backside) solder attached.

Fig. 2. Micrograph of an experimental, SiC amplifying gate thyristor with square-shaped anode and dotted shorts ( ). Gate (centre) and anode wedge-bonded with wires, cathode (backside) solder attached.

In-between gate and main anode, the amplifying gate is located, consisting of the anode A' of the pilot thyristor and the auxiliary gate . The etch-step separating and forms a circle with varying radius of . This way, the resulting thyristors meet the amplifying gate design criterion ( to different degrees:

safe ( ): the pilot thyristor always triggers the main thyristor

adequate ( ): still ok, but susceptible to technological uncertainties

non-adequate ( ): the pilot is less sensitive than the main thyristor, which may reverse the triggering order, negating the benefits of the pilot.

Electrical Characterization

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

On-wafer (in a vacuum probing chamber), the best devices demonstrated stable blocking up to 2 kV . After dicing, bonding, and encapsulation they were repeatedly tested up to 1.2 kV , the nominal voltage they were conceived for. Fig. 3 exemplarily shows the blocking characteristics (on-wafer and encapsulated) of a square-shaped SiC thyristor with safely designed ( ) amplifying gate and dotted anode shorts (device A). For comparison, the characteristic of a thyristor without amplifying gate is shown (device B), representing one of the best devices in terms of blocking capability. The higher leakage current of encapsulated devices is due to the lower current resolution of the curve tracer. The real leakage current (measured using an SMU on an equivalent device) is in the order of some nanoamperes (not shown), and thus only slightly higher that that one measured onwafer under vacuum.

Fig. 4 shows on-state characteristics (at varying gate currents) of the same amplifying gate thyristor (bottom graph) as in Fig. 3 (device A), compared to a device without amplifying gate (top graph). As expected, the amplifying gate thyristor shows a characteristic snap-back. Note that the difference in the differential on-resistance is due to a spread between samples and not a characteristic difference between the two device types.

By contrast, the fact that the amplifying gate thyristor requires a higher gate current to trigger, means a characteristic difference. For comprehension, note that the amplifying gate thyristors under investigation are experimental devices with a small periphery (main thyristor). They have been conceived only for the purpose of examining the design constraint. Their amplifying gate has about the same size as the gate of the comparative thyristor (without amplifying gate), but due to the parallel current path formed by and , they require a larger gate current to trigger. In terms of a reduced gate current, the amplifying gate only takes advantage when it supplies the gate current via an interdigitated structure to a large area (main) thyristor.

Fig. 3. Forward blocking characteristics of two SiC thyristors measured on-wafer with an SMU (up to breakdown) and after bonding and encapsulation with a curve tracer (limited to 1.2 kV ).

Fig. 3. Forward blocking characteristics of two SiC thyristors measured on-wafer with an SMU (up to breakdown) and after bonding and encapsulation with a curve tracer (limited to 1.2 kV ).

Fig. 4. On-state characteristics of encapsulated SiC thyristors with and without amplifying gate (AG).

Fig. 4. On-state characteristics of encapsulated SiC thyristors with and without amplifying gate (AG).

Fig. 5 shows the gate-anode I-V characteristics of three SiC thyristors with differently dimensioned amplifying gate (non-adequate, adequate and safe, . above), allowing to determine the characteristic resistances and of pilot and main thyristor, respectively. is directly derived from the slope of the I-V characteristic measured between the gate contact G (in the centre) and the ring shaped anode of the pilot thyristor (cf. Fig 1). In the same way, (and thus ) is determined from the slope of the I-V characteristic measured between G and the main anode A. Tab. 1 summarizes the extracted values which confirm the compliance to the above mentioned design rule ( ).

Finally, Fig. 6 shows turn-on characteristics of circular and square SiC thyristors disposing of ringshaped and dotted anode-shorts, respectively. For each of these two types, the curves of three devices with differently dimensioned amplifying gate are shown. Note, that though giving the impression of a logical sequence, there is no coherence of the turn-on delay time with the individual device dimensions. It appears rather that devices with adequately and safely designed amplifying gate reveal a peak-shaped inversion in the gate current and voltage transients, while non-adequately designed devices do not. These peaks originate from the current passing through the anode A' of the pilot thyristor, delivering the gate current for the main thyristor. This way they prove evidence that the pilot thyristor is triggered in advance of the main thyristor, which obviously does not emerge for thyristors with non-adequately designed amplifying gate.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

The results presented in this paper demonstrate that the experimental SiC amplifying gate thyristors under investigation can be triggered adequately fully compliant to the underlying design constraints. Furthermore, the measurements reveal relatively large resistances and of pilot and main thyristor, respectively, being causal for meeting these constraints. Anyway, the main part of the resistance, here quantitatively about , is determined by the sheet resistance of the n -base layer (gate) underneath the two sub-thyristors. The rest, however, as calculations based on TLM
measurements indicate, must be attributed to the contact resistance to the n -base layer. Nevertheless, this relatively high amount does not negatively affect the adherence to the design rule. In so far, the conceived amplifying gate structures can be used as design building blocks for larger area, electrically or optically triggered SiC thyristors.

Fig. 5. Gate-anode characteristics (measured on-wafer) of SiC thyristors with differently dimensioned amplifying gate (cf. Tab.1).

Fig. 5. Gate-anode characteristics (measured on-wafer) of SiC thyristors with differently dimensioned amplifying gate (cf. Tab.1).

Tab. 1. Resistance and extracted from Fig. 5.

Device | rEM (μm) | rSM (μm) | RP (mΩ) | RM (mΩ) | VGG (V)
A | 500 | 1200 | 27.6 | 20.5 | -2.9
B | 620 | 1200 | 17.6 | 20.5 | -2.2
C | 740 | 1200 | 11.6 | 20.5 | -1.9
D | 860 | 1200 | 8.1 | 20.5 | -1.6
E | 980 | 1200 | 5.8 | 20.5 | -1.4

Fig. 6. Turn-on characteristics ( ) of encapsulated SiC thyristors with circular (solid lines) and square-shaped (dotted lines) anode, each with differently dimensioned amplifying gate (cf. legend).

Fig. 6. Turn-on characteristics ( ) of encapsulated SiC thyristors with circular (solid lines) and square-shaped (dotted lines) anode, each with differently dimensioned amplifying gate (cf. legend).

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

Financial support provided by the French DGA under the research program ASTRID, contract no. ANR-11-ASTR-0011, is gratefully acknowledged.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.493.pdf

S. Ryu, D.J. Lichtenwalner, M. O'Loughlin, C. Capell, J. Richmond, E. van Brunt, C. Jonas, Y. et al., 15 kV n-GTOs in 4H-SiC, Materials Science Forum Vol. 963 (2019), p. 651.

M. Agamy, F. Tao, and A. Elasser, A high speed SiC thyristor gate driver for pulse power applications, in Proceedings of the IEEE Energy Conversion Congress and Exposition (Baltimore, MD, USA, 2019) p. 5694.

H. O'Brien, A. Ogunniyi, et al., High-Voltage Silicon Carbide Thyristors on N-Doped Epi for Pulsed Power, in Proceedings of the IEEE Int. Pulsed Power Conf. (Denver, CO, USA, 2021).

S. Scharnholz, L.V. Phung, D. Tournier, B. Vergne, R. Hassdorf, P. Brosselard, and D. Planson, Conception de thyristors SiC permettant l'étude de l'amplification interne de l'allumage, in Proceedings of the Symposium de Génie Electrique (Cachan, France, 2014).

B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, New York, 2008, p. 675.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The radius is the only varying parameter. The other radii, , and are constant for all devices (cf. text).

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 498-503

doi: 10.4028/p-95van7

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-02-17

Accepted:
2022-03-17

Online:
2022-05-31

Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

The original version of this paper is available on https://www.scientific.net/MSF.1062.498.pdf

P. Moens , J. Lettens , J. Choi , F. Allerstam

ON Semiconductor, Isafjordsgatan 32C, 16440 Kista, Sweden

ON Semiconductor, Westerring 15, 9700 Oudenaarde, Belgium

ON Semiconductor, 333 Western Avenue, 04106-1705 Maine, USA

E-mail: martin.domeij@onsemi.com, Jimmy.Franchi@onsemi.com,

sotirios.maslougkas@onsemi.com, peter.moens@onsemi.com, jan.lettens@onsemi.com,

jake.choi@onsemi.com,

Keywords: MOSFET, oxide reliability, charge to failure, gate bias stress, oxide traps

Abstract

Similar charge to failure distributions with mean values of about were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with at . No substantial difference in drift rate with at was found after about 10 s recovery period for stressed devices compared with unstressed devices. Additionally, stressed and unstressed devices did not differ in final shift at after stress (during 3 hrs or 31 hrs ). More gate oxide reliability characterization is important to determine if pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in and was examined after long-term AC gate bias stress by a gate driver switching between -8 V and 20 V for four different commercially available SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.498.pdf

Electrical characterization of SiC gate oxides at high electric fields is important for oxide lifetime modeling, for quality sampling and for screening of potentially unreliable SiC MOSFET chips. Forced gate current ( ) stress [1-2] with measurement of charge to failure ( ) is a way to monitor gate oxide quality with reduced influence of oxide thickness variations. In this work, results are shown for planar SiC MOSFETs in comparison with n-type MOS capacitors (MOScaps) and Si MOSFETs. IG stress of SiC MOSFETs at high oxide fields has been reported to cause significant negative shifts of threshold voltage ( ), and this effect has been attributed to oxide trapping of impact ionization generated holes [3]. To study this effect, transient measurements of gate voltage during stress were carried out for n -type SiC MOScaps and planar MOSFETs to monitor shifts in flatband voltage and respectively. Additionally, was measured during positive stress for previously stressed SiC MOSFETs to examine recovery, and to compare drift during positive stress with unstressed devices.

Another important type of gate bias induced parametric drift of SiC MOSFETs is and onresistance ( ) increase after AC gate bias stress [4-5]. This type of drift has been studied for commercially available SiC MOSFETs subjected to stress using a operating gate driver.

Experimental Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.498.pdf

Gate oxide charge to failure ( ). Constant stress until failure was performed for SiC MOSFETs, SiC MOScaps and Si MOSFETs. The SiC MOSFETs are vertical planar channel 1200 V devices with and of about . The large area ( ) MOScaps were fabricated on an n-type epilayer with the same doping concentration as the drift layer of the SiC MOSFETs. The MOScaps have about thicker gate oxide than the MOSFETs and the gate oxide process is otherwise similar. The Si MOSFETs are a discrete product, and all three types of devices
have been fabricated in the same wafer fab at onsemi. The tested MOScaps were pre-screened with and the SiC MOSFETs have passed a production type wafer sort program.

Fig. 1. measured for SiC MOSCAPs ( 28 pcs ), MOSFETs ( 35 pcs ) and a Si MOSFET product when forcing .

Fig. 1. measured for SiC MOSCAPs ( 28 pcs ), MOSFETs ( 35 pcs ) and a Si MOSFET product when forcing .

Fig. 2. vs. time for n-type MOScaps during 1 second pulses of forced gate current stress at

Fig. 2. vs. time for n-type MOScaps during 1 second pulses of forced gate current stress at

Fig. 3. vs. time for SiC MOSFETs during 1 second pulses of forced gate current stress at

Fig. 3. vs. time for SiC MOSFETs during 1 second pulses of forced gate current stress at

Fig. 4. Room temperature CV sweep of MOScap before and after 1 second pulses of forced gate current stress at

Fig. 4. Room temperature CV sweep of MOScap before and after 1 second pulses of forced gate current stress at

Fig. 1 shows measurements of after forced stress with (gate area) at for all three device types. The SiC MOSFET Q value of is state-of-the-art, slightly exceeding [1]. The tail-free distribution indicates that the device chips are free from locally weak spots and are well matching the planar MOScaps. Fig. 1 illustrates that the SiC MOS technology exceeds the Si MOSFET product in terms of by 50 x .
Analysis of pulsed Ig stress. Positive gate bias stress with moderate oxide fields typically cause positive shifts due to trapping of electrons in near interface traps [6]. The gate oxides studied in this work have electric fields around during stress in the regime, and for such high oxide fields we can expect negative shifts of as reported in [3]. Figs. 2-3 show measurements
of transient during 1s long pulsed stress with at for the same type of SiC MOScaps and SiC MOSFETs as in Fig. 1. In both cases we see transient decrease of during the pulse, presumably due to gradually reduced and values caused by trapping of positive hole charge or emission of negative trapped charge. It is interesting to note that the levels saturate after a few 100 ms for both MOScap and MOSFET. No voltage peak occurred during a pulse (see Figs. 2-3) and the voltage levels at the end of the and pulses are very similar. A possible explanation for this observed voltage saturation during the 1 s pulsed stress is filling of pre-existing traps by holes generated by impact ionization [3] or by anode hole injection [7].

Fig. 4 shows room temperature CV sweeps for a MOScap before and after a 1 s pulse with at . The resulting negative shift of 1.95 V is qualitatively well in line with the observed voltage drop of about 1.4 V from peak to plateau during stress (at ) in Fig. 2. For the SiC MOSFET, was measured at before and was measured after the pulse. From these results it can be concluded that the observed voltage drops during stress in Figs. 2 and 3 are linked to reduced and respectively. The 0.09 V negative shift of the MOSFET is much smaller than the voltage drop of about 0.9 V observed during the pulse in Fig. 3. A possible explanation for this fast recovery of the MOSFET is capture of electrons supplied to the channel from the highly doped source during the measurement.
Recovery and drift of after forced stress. Positive gate bias stress with was carried out at for SiC MOSFET devices previously stressed with during 1 second and unstressed devices ( 2 of each type). Fig. 5 displays vs. time where the stressed devices recover and reaches the value the unstressed ones after 10-20 s. Despite the faster initial shift of the stressed devices, the drift curves later proceed in parallel, showing no significant difference in drift rate. The summary in Table 1 shows that there are only small differences at after stress with at during 1.11e4 , and the finally measured shift at is identical for stressed and unstressed devices. These results indicate that the drop resulting from the pulsed stress with (see Fig. 3) does not cause any permanent changes to and stability as it is measured in regular slow measurements. Additional characterization such as ultra-fast BTI measurements and time dependent dielectric breakdown (TDDB) is important to detect possible effects on device behaviour by the pulse. Degradation of TDDB characteristics is, however, not expected due to the low charge of about for the pulse compared with the measured mean of (see Fig. 1).

Fig. 5. vs. time during stress with at for two devices previously stressed with for 1 second and two unstressed devices

Fig. 5. vs. time during stress with at for two devices previously stressed with for 1 second and two unstressed devices

Table 1. measured before and after the performed tests including at for 1 s , and the following stress with at

Test sequence/Device ID
IG_stressed1
Reference1
IG_stressed2
Reference2

T=25 °C before IG stress
3.00
3.00
3.00
2.96

T=150 °C before IG stress
2.34
2.34
2.35
2.32

T=150 °C after IG stress
2.25
NA
2.25
NA

T=150 °C after VGS=28 V
at T=150 °C for 1.11e4 s
2.71
2.67
2.70
2.62

T=25 °C after VGS=28 V
at T=150 °C
3.22
after 1.11e5 s
3.22
after 1.11e5 s
3.05
after 1.11e4 s
3.01
after 1.11e4 s

AC gate bias stress. A different type of parametric drift under AC gate bias stress (between negative and positive ) with moderate oxide fields is described in ref. [4-5], where a positive drift of and was reported. The number of switching cycles, the level of negative , and voltage over- and undershoots are pointed out as key factors for this type of drift [4-5]. A transient and overshoot free stress was performed at with using a gate driver switching between -8 V and 20 V with duty cycle. The stress measurements were interrupted after different time intervals to run a test program consisting of and . Delta shifts of and normalised shifts are shown in Fig. 6 for onsemi's commercially available 1200 V 80 mohm SiC MOSFET together with 1200 V SiC MOSFET products from three other manufacturers. The results are qualitatively well in line with ref. [5], and it should be noted that is outside the datasheet rating for two of the tested SiC MOSFETs.

Fig. 6. Delta shift and vs. cycles of transient between ( duty cycle) at (the initial condition is plotted as 1 cycle due to the log scale). and values were recorded by moving the device to an ATE socket and running a program consisting of

Fig. 6. Delta shift and vs. cycles of transient between ( duty cycle) at (the initial condition is plotted as 1 cycle due to the log scale). and values were recorded by moving the device to an ATE socket and running a program consisting of

and .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.498.pdf

distributions were measured for SiC MOScaps and MOSFETs with state-of-the-art mean values of about . Fast and quickly saturating negative flatband and threshold voltage drops were found for MOScaps and MOSFETs in time resolved pulsed gate current stress with at during 1 second. No substantial difference in drift rate with at was found after a 10-20 s recovery period for the stressed compared with unstressed devices. Additionally, stressed and unstressed devices did not differ in final shift at
after stress at (during 3 hrs or 31 hrs ). Additional characterization is needed to determine if any permanent change to the device behaviour is caused by the 1 s pulsed stress using with its observed negative drop. Finally, parametric shifts in and was examined after long-term AC gate bias stress by a gate driver (switching between -8 V and 20 V ) for 4 different commercially available SiC MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.498.pdf

K. Matocha, I-H. Ji, X. Zhang and S. Chowdury, Proceedings of the 2019 IEEE International Reliability Physics Symposium (IRPS), p. 276, 2019

P. Moens, J. Franchi, J. Lettens, L. De Schepper, M. Domeij and F. Allerstam, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp78-81, 2020.

S. Maaß, H. Reisinger, T. Aichinger and G. Rescher, 2020 IEEE International Reliability Physics Symposium (IRPS), 2020.

Infineon Application Note AN2018-09

X. Zhong et. al., IEEE Transactions on Power Electronics, "Bias Temperature Instability of Silicon Carbide Power MOSFET under AC Gate Stresses", DOI 10.1109/TPEL.2021.3105272, IEEE

A. Lelis et. al., "Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs", IEEE Transactions on Electron Devices, 62, nr. 2, p. 316323, 2015.

B. Mazza, S. Patané, F. Cordiano, M. Giliberto, G. Barletta and G. Franco, "Electrical overstress effect characterization on Power MOS Trenchfet and correlation with time dependent dielectric breakdown", Microelectronics Reliability 125, 114351, 2021

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 504-508

doi: 10.4028/p-13z22g

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-02-21

Accepted:
2022-03-17

Online:
2022-05-31

Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design

The original version of this paper is available on https://www.scientific.net/MSF.1062.504.pdf

L. Zhang , T. Dai , P.M. Gammon , N. Lophitis , F. Udrea , A. Tiwari , J.A.O. Gonzalez , A.B. Renz , V.A. Shah , P.A. Mawby and M. Antoniou

School of Engineering, University of Warwick, Coventry, CV4 7AL, UK,

Faculty of Engineering, University of Nottingham, Nottingham, NG7 2RD, UK

Department of Engineering, University of Cambridge, Cambridge, CB2 1PZ, UK

Luyang.Zhang.1@warwick.ac.uk, Tianxiang.Dai@warwick.ac.uk, p.m.gammon@warwick.ac.uk, neo.lophitis@nottingham.ac.uk, @eng.cam.ac.uk, jP.A.Mawby@warwick.ac.uk, kma308@cam.ac.uk

Keywords: silicon carbide; IGBT; 10 kV ; power device; short circuit robustness; reliability; carrier lifetime.

Abstract

The commercial success of silicon carbide ( SiC ) diodes and MOSFETs for the automotive industry has led many in the field to begin developing ultra-high voltage (UHV) SiC insulated gate bipolar transistors (IGBTs), rated from 6 kV to 30 kV , for future grid conversion applications. Despite this early interest, there has been little work conducted on the optimal layout for the SiC IGBT, most early work seeking to overcome difficulties in fabricating the devices without a substrate. In this paper, numerical TCAD simulations are used to examine the link between the carrier lifetime of SiC IGBTs and their short circuit capability. For the planar devices, simulations show that increasing carrier lifetime from 1 to , has not only a profound effect reducing on-state losses, but also increases short circuit withstand time (SCWT) by . Two retrograde p -well designs are also investigated, the optimal device for SCWT having a 100 nm channel region of , with this increasing to a peak value of , in a 700 nm region beneath the channel.

Introduction

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The electrical and thermal properties of silicon carbide ( SiC )have made it an excellent candidate for high power applications. Ultra-high voltages (UHV) devices rated at 10 kV and above are an attractive choice for HVDC converters, as to reduce the number of devices required in, for example, voltage-source converters [1,2]. Despite the optimization to gain better on-state performance and lower switching losses, the short circuit robustness of SiC IGBTs needs improving. The impact of a number of the state-of-the-art IGBT developments to date are explored in a series of benchmarking simulations.

Fig. 1 Planar SiC n-IGBT structure.

Fig. 1. Planar SiC n-IGBT structure.

Fig. 2 The p-well doping concentration of the retrograde planar devices, the RG-HD design coming from process simulation.

Fig. 2. The p-well doping concentration of the retrograde planar devices, the RG-HD design coming from process simulation.

To begin, baseline 10 kV planar IGBT geometry has been implemented in the Sentaurus TCAD platform, its layout depicted in Fig.1. The baseline models are then adapted, with the p -well design and the impact of the lifetime . For the baseline models, the anode side of the structure is a fieldstop design with a collector and a -buffer. The cathode side employs a planar gate structure with an n -doped enhancement region. Due to the inherent poor SiC channel mobility, appropriate interface models are necessary and a realistic trap profile with increasing trap concentrations at the edges is employed [3]. This strongly affects the channel mobility due to scattering mechanisms at the interface (i.e., acoustic, surface roughness, coulomb scattering [4]). Retrograde p -well is historically proposed for the high-density Si-based CMOS technology with later studies reporting an improvement in the latching performance compared conventional p -well design [6]. Two retrograde (RG) p -well designs are compared, their doping profiles shown in Fig. 5. They both have a deep, channel region. Beneath this, the "RG-box" variant features a uniform box-profile doping. The second "RGHD" variant features a higher doping, peaking at , which has been designed in the process simulator and verified experimentally. Both implementations are simulated with set to and .
Following analysis of the static characteristics, the short circuit robustness of the variants is investigated via a short-circuit switching simulation. In order to obtain informative results, the p -base current is isolated from the emitter current at the cathode side of the device by adding an additional separate base contact to monitor the current flow at the top of the device. Fig. 3 shows the short circuit test circuit, in which a 5000 V DC pulse is applied to the IGBTs' collector for increasing duration until the device breaks down (via parasitic -base turn-on and eventual thermal runaway). The parasitic inductance (L1) for the test setup is 180 nH .

Fig. 3 Short circuit test circuit for the 10 kV IGBT.

Fig. 3. Short circuit test circuit for the 10 kV IGBT.

Fig. 4 Simulated ON-state characteristics of the planar IGBTs at room temperature, with different lifetimes and p-well designs.

Fig. 4. Simulated ON-state characteristics of the planar IGBTs at room temperature, with different lifetimes and p-well designs.

Static Results

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The forward conducting characteristics of the planar IGBT designs, are shown in Fig. 4; Fig. 5 shows their excess carrier density in the drift region at . As demonstrated experimentally [5, 6, 7], the on-state losses are heavily affected by the underlying carrier lifetime and the distribution of the charge. At the carrier density of the drift layer with a RG-box p-well approaches relative saturation. An Ron,SP.DIFF of is recorded, the is 5.6 V at , and the JON is at . The on-state characteristics are largely unaffected by the different retrograde p-well designs.

Fig. 5 Plasma distributions along the drift region at .

Fig. 5. Plasma distributions along the drift region at .

Fig. 6 Simulated OFF-state characteristics of the planar IGBTs at room temperature, with different lifetimes and p -well designs.

Short circuit Robustness

The original version of this paper is available on https://www.scientific.net/MSF.1062.504.pdf

1) Planar IGBT: Effect of p-well design

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Short circuit switching simulations demonstrated the advantage of the RG-HD p-well design in withstanding a short circuit fault condition. Fig. 7 shows the transient characteristic under shortcircuit conditions with the gate pulse left on until latch up and destruction. This occurred after for the RG-box p-well device whereas the optimised device lasted for over . The reason for this improvement in the RG-HD p-well design is due to its higher doping (Fig. 2) beneath the channel, which provides a low resistance path for hole current to the emitter. Fig. 8 shows the electron current density of the RG-box structure during this period. As minority carriers, in the p-well, the electron density is seen to exceed at , suggesting that the -base junction is forward biased and thus triggering the junction failure, with the device eventually failing due to thermal runaway.

Fig. 7 Simulated Short circuit curves for both retrograde planar devices with .

Fig. 7. Simulated Short circuit curves for both retrograde planar devices with .

2) Planar IGBT: Effect of carrier lifetime

The original version of this paper is available on https://www.scientific.net/MSF.1062.504.pdf

For the SiC IGBTs, like SiC MOSFETs [8,9], SRH generation is responsible for an increase in leakage current. Reducing carrier lifetime enhances the SRH generation in the depletion region of the p -base/n-drift junction, and the holes generated flow through the p-base/n-drift junction, leading to an increase in base leakage current. For the RG-HD p-well structure the lifetime effect is significant. From Fig. 9, an increase in from to brought about an increase in the SCWT of from to . This underlines that a lifetime enhancement procedure (e.g. via surface oxidation [10]) would benefit both ON-state performance and short-circuit capability. Similar to the concept of current saturation, the SRH generation rate reaches a minimum by , and no further improvement in the SCWT occurs above this value.

Fig. 9 Short circuit (last pass) curves for the RG-HD p-well IGBT device, with (a) and (b) .

Fig. 9. Short circuit (last pass) curves for the RG-HD p-well IGBT device, with (a) and (b) .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.504.pdf

The static performance and short circuit robustness of 10 kV SiC IGBTs was investigated. The planar structure is with much improved short circuit robustness, in a similar fashion to silicon devices. However, in contrast to silicon bipolar devices, SiC IGBTs static and dynamic performance does benefit from lifetime enhancement. A highly doped retrograde p-well doping profile is necessary in order to improve on-state and short circuit robustness.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.504.pdf

C. Shen, S. Jahdi, O. Alatise, J. Ortiz-Gonzalez, A. Aithal, and P. Mellor, "Prospects and Challenges of Thyristors in Protection of HB-MMC-VSC-HVDC Converters," IEEE Open Journal of Power Electronics, vol. 2, pp. 145-154, 2021.

K. Jacobs, S. Heinig, D. Johannesson, S. Norrga, and H. P. Nee, "Comparative Evaluation of Voltage Source Converters With Silicon Carbide Semiconductor Devices for High-Voltage Direct Current Transmission," IEEE Transactions on Power Electronics, vol. 36, no. 8, pp. 8887-8906, 2021.

A. Koyama et al., "20 kV-Class Ultra-High Voltage 4H-SiC n-IE-IGBTs," in Materials Science Forum, 2020, vol. 1004: Trans Tech Publ, pp. 899-904.

E. V. Brunt et al., " -SiC n-IGBTs with improved conductivity modulation," in 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 15-19 June 2014 2014, pp. 358-361.

Y. Xiaolei et al., "Low Ron,sp.diff and Ultra-high Voltage n-channel IGBTs with carrier lifetime enhancement process," in 2020 17th China International Forum on Solid State Lighting & 2020 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS), 23-25 Nov. 2020 2020, pp. 42-44.

A. K. Tiwari, M. Antoniou, N. Lophitis, S. Perkin, T. Trajkovic, and F. Udrea, "Retrograde pwell for class SiC IGBTs," IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 30663072, 2019.

V. Afanasev, M. Bassler, G. Pensl, and M. Schulz, "Intrinsic SiC/SiO2 interface states," physica status solidi (a), vol. 162, no. 1, pp. 321-337, 1997.

A. Pérez-Tomás, P. Godignon, N. Mestres, and J. Millán, "A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface," Microelectronic engineering, vol. 83, no. 3, pp. 440-445, 2006.

B. Kakarla, A. Tsibizov, R. Stark, I. K. Badstübner, and U. Grossner, "Short Circuit Robustness and Carrier Lifetime in Silicon Carbide MOSFETs," in 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 13-18 Sept. 2020 2020, pp. 234-237 .

K. Kawahara, J. Suda, and T. Kimoto, "Analytical model for reduction of deep levels in SiC by thermal oxidation," Journal of Applied Physics, vol. 111, no. 5, p. 053710, 2012.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 509-513

doi: 10.4028/p-7027g3

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-20

Accepted:
2022-03-17

Online:
2022-05-31

Neutron Detection Study Through Simulations with Fluka

The original version of this paper is available on https://www.scientific.net/MSF.1062.509.pdf

A.Muoio , A. Meli , A. Trotta , M. Parisi , L. Meda and F. La Via

CNR-IMM, VIII Strada 5, 95121 Catania, Italy

INFN - LNS, Via S. Sofia 62, 95123 Catania, Italy

Università di Catania Dipartimento di Fisica via S.Sofia 64,95123 Catania , Italy

ENI-MAFE, Via A. Pacinotti 4, 30175, Venezia, Italy

ENI - Renewable Energy, Magnetic Fusion and Material Science Research Center, Via G. Fauser 4, 28100 Novara, Italy

*Corresponding author email: annamaria.muoio@imm.cnr.it, alessandro.meli@imm.cnr.it, antonio.trotta@eni.com, miriam.parisi@eni.com, francesco.lavia@imm.cnr.it

Keywords: fluka, neutron detection, silicon carbide

Abstract

In this work the purpose of the simulations is to optimize a new large volume Silicon Carbide (SiC) detector for 14.1 MeV neutrons. The device has an active thickness obtained by epitaxial growth and an active area of . In the first step of the simulations we compare SiC detector performance to Diamond and Silicon detectors, with the same geometric features. In the second step of the simulations we have found the best solution to improve the response of the detector for a fixed epitaxial layer thickness using an overlayer of aniline .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.509.pdf

In theoretical and experimental studies of nuclear physics, an important role has always been played by the interaction of neutron beams with matter; in fact, by being electrically neutral, they are able to overcome the Coulomb barrier and interact directly with the target's nuclei. They are fundamental for investigating the structure of matter and nuclear reactions. Silicon Carbide (SiC) is a compound semiconductor, which is considered as a possible alternative to silicon for particles and photon detection. Its characteristics make it very promising for the next generation of nuclear and particle physics experiments where the temperature and the radiation environment preclude the use of conventional silicon detectors [1-2]. Some studies, based on the effects of neutron, proton and heavy ions irradiation on SiC diodes, evidenced the high radiation hardness of these devices [3], that maintain their performance after high dose irradiation [4]. In this study the efficiency in the detection of neutrons for different materials and thickness is studied by Fluka Montecarlo simulations for a neutron Energy of 14.1 MeV and a fluence of . In previous studies it has been observed that several materials can improve the efficiency of the neutron detectors [5] but these materials cannot be implemented during the detector realization process. Then we have decided to use an aniline overlayer that can be easily deposited during the detector realization process and that can further improve the detector efficiency, for a fixed epitaxial layer thickness.

Results and Discussions

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Reactions with fast neutrons are widely used in nuclear sciences. Investigation of the mechanism of their reactions could improve knowledge on atomic nuclei structure. The following Table 1 shows the possible reactions for fast neutrons with Energy on a SiC detector [6].

Table 1 Fast Neutron-Induced Reactions in Silicon Carbide

REACTION
Q Value
(MeV)
Energy Threshold
(MeV)

¹²C(n,n')¹²C ground state
0
0

¹²C(n,n')¹²C 2+
-4.4389
4.8088

¹²C(n,α)⁹Be
-5.7012
6.4196

¹²C(n,n')3α
-7.3666
8.4286

¹²C(n,p)¹²B
-12.5865
13.7401

²⁸Si(n,n')²⁸Si ground state
0
0

²⁸Si(n,n')²⁸Si 2+
-1.7790
1.8425

²⁸Si(n,α)²⁵Mg
-2.6537
2.7653

²⁸Si(n,p)²⁸Al
-3.8599
4.0042

The investigations through simulations were carried out with the Monte Carlo software Fluka [7]. A parallelepipedal telescopic detector with a base surface of was simulated. In the first study of simulations the SiC interactions with neutrons has been studied and compared with Silicon and Diamond detectors, with the same geometric features. From these simulations reported in Fig. 1a it is possible to observe that the interacting neutrons are much higher in Diamonds with respect to SiC and Silicon because the scattering cross section of carbon is higher than that one of silicon. After that the active area of the SiC detector was increased and with this doble area the interacting neutrons are comparable between the diamond and the SiC detectors. This result is extremely interesting because the better material quality of the SiC material with respect to diamond can give the opportunity to obtain larger devices and then a comparable or better efficiency. Of course, the area of the detector cannot be increased over a certain value because the increase of the area also produces a considerable decrease of the detector production yield, with a subsequent increase of the detector costs.

The second step of the simulations is to study another approach to improve the sensitivity of silicon carbide detectors; from previous studies [8-9], it has been observed that aniline is a good activator of nuclear reactions with fast neutrons. The simulations are done with two detector layers, with the first stage consisting of aniline and a second one of silicon carbide . Different thickness combinations of the first stage were analyzed while SiC layer has a fixed thickness of 250 . The characteristics of the incident neutron beam were the same of the previous simulations set: Neutrons energy 14.1 MeV and Neutrons fluence equal to neutrons . Among the possible reactions induced by the neutron-carbon interaction, there are multiple interactions of elastic and inelastic scattering and reactions of the type and ; a particular analysis was undertaken for the study of proton elastic interactions, for different layers of aniline relating to the bulk of SiC (thickness ) Fig 1b.

Fig.1a Flux versus thickness for different materials (Diamond, Silicon and Silicon Carbide) at different thickness and Fig.1b Differential protons Flux versus thickness of aniline (7,14, 21, 70, 350 e ), for the two layers detector Aniline + SiC.

Fig.1. a Flux versus thickness for different materials (Diamond, Silicon and Silicon Carbide) at different thickness and Fig.1b Differential protons Flux versus thickness of aniline (7,14, 21, 70, 350 e ), for the two layers detector Aniline + SiC.

From these simulations it is possible to observe that the maximum thickness of the aniline stage should be , so as to increase the flux of protons in the SiC detectors. Higher thickness produces a saturation because the protons generated at the surface cannot go out from the aniline layer and reach the silicon carbide.

In all the materials, as reported in Fig. 1a, the interacting neutrons increase by increasing the thickness of the detectors, but very thick detectors are difficult to be realized due to the increase of defects density in very thick epitaxial layers [10-11]. Furthermore, a higher bias is needed to deplete the thick epitaxial layer as shown in Fig.2a. To decrease this high voltage it is possible to decrease the doping concentration in the epitaxial layer, but, in the case of silicon carbide is extremely difficult to reach doping concentration lower than .

Another aspect that should be taken under consideration is that when we use very thick epitaxial layers for the detectors, we need to have a diffusion length larger than the depleted layer to have a good charge collection. From Fig.2b it is possible to observe the diffusion length data, calculated using time resolved photoluminescence (TRPL) for the lifetime calculation. The diffusion length values are higher than the epi-layer thickness for our samples [12] with an optimized epitaxial process, while in the case of other epitaxial growth processes, the diffusion length is close to thickness of the epitaxial layer or even lower. Then with a good epitaxial process the diffusion length does not seems to be the limiting factor in the increase of the epitaxial layer thickness and of the neutron sensitivity. Instead, the high voltage necessary to deplete a thick epitaxial layer, and the low yield of the very thick detectors with large area are the main limitation of this technology. For this reason, the implementation of the overlayer of aniline can be a possible route for the increase of the detector efficiency.

Fig.2a Voltage necessary to obtain a depletion over the entire epitaxial layer as a function of the thickness of the layer with different carrier concentration.Fig.2b Diffusion length as a function of the thickness for our data compared with data in literature [13-14].

Fig.2. a Voltage necessary to obtain a depletion over the entire epitaxial layer as a function of the thickness of the layer with different carrier concentration.Fig.2b Diffusion length as a function of the thickness for our data compared with data in literature [13-14].

Conclusions

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Silicon carbide ( SiC ) is used extensively for the production of high-power semiconductor devices. Today the use of this material in radiation environments such as fusion reactors creates excitement in the nuclear physicist.. In this study we have used FLUKA simulation code to investigate radiation induced effects in for neutrons of 14 MeV . With this work we have observed that we need very thick epitaxial layers to have good sensitivity of the SiC detector at this high energy. For the same thickness of the detector the silicon carbide one is less sensitive with respect to the state of the art diamond detectors, but increasing the area, thanks to the superior quality of this material, it is possible to obtain similar sensitivity. The main difficulties for the realization of very thick detectors is related to the high voltage needed to depleted the thick layers and to the yield decrease due to the large area and the high epitaxial layer. The use of an overlayer of aniline can produce, according to our simulations, a considerable increase of the detector sensitivity.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.509.pdf

A. Owens and A. Peacock, Nucl. Instrum. Methods A, 531, 18 (2004).

E. V. Kalinina et al., Phys lett., 34, 210 (2008).

A. Muoio et al., EPJ Web of Conferences, 117, 10006 (2016).

S. Tudisco et al., EuNPC 2018 Conference, 42 C, 74 (2019).

F.H.Ruddy et al., Proceedings of the 13th International Symposium, doi: 10.1142/9789814271110_0014, (2009)

F.H. Ruddy et al., IEEE Transactions on Nuclear Science 53(3):1666-1670 (2006).

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T. L. Johnson et al.,Proceedings of the America nuclear Society on Theory and Pratices in Radiation Protection and Shieding, ISBN 0-89448-132-0, (1987).

.C.H.Lee et al., Nuclear Engineering and Technology Volume 49, Issue 3, 592-597, , (2017)

F. La Via, M. Camarda, A. La Magna, Applied Physics Reviews 1, 031301 (2014)

F. La Via, G. Izzo, M. Camarda, G. Abbondanza, and D. Crippa, Materials Science Forum Vols. 615-617, 55 (2009).

A. Meli, A. Muoio, A. Trotta, L. Meda, M. Parisi and F. La Via. Materials, 14, 976 (2021).

S. Ichikawa et al. Applied Physics Express 5, 101301 (2012).

T. Miyazawa et al. Applied Physics Letters 97, 202106 (2010).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 514-518

doi: 10.4028/p-cxd7z3

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-03-17

Accepted:
2022-03-17

Online:
2022-05-31

A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

The original version of this paper is available on https://www.scientific.net/MSF.1062.514.pdf

G.W.C. Baker , Fan Li , Tianxiang Dai , Arne Renz , Luyang Zhang , Yunyi Qi , Vishal Shah , Phillip Mawby , Marina Antoniou , Peter Gammon

University of Warwick, Coventry, United Kingdom

guy.baker@warwick.ac.uk, A.Renz@warwick.ac.uk, luyang.zhang.1@warwick.ac.uk, y.qi.1@warwick.ac.uk, vishal.shah@warwick.ac.uk, p.a.mawby@warwick.ac.uk, ma308@cam.ac.uk, 9P.M.Gammon@Warwick.ac.uk

Keywords: superjunction, semi-superjunction, Schottky barrier diode, simulation

Abstract

This paper discusses the design and simulation of semi-SJ structures producing results t

Introduction

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Silicon Carbide (SiC) Schottky diodes and power MOSFETs now offer circuit designers a fastswitching alternative to Silicon ( Si ) PiN diodes and IGBTs within the class. However, despite the low specific on-resistance ( ) of SiC power devices when compared to Si devices, the relationship between and the blocking voltage ( ) ( ) limits the use of SiC unipolar devices at higher voltage ratings. As established in Si , superjunction (SJ) devices allows the relationship between and to be almost linearized, reducing the to below the material's unipolar limit. SJ structures thereby reduce on-state losses at higher voltages, whilst maintaining fast switching compared to bipolar devices.

Superjunction devices are achieved by developing highly-doped and perfectly charge balanced n and p-columns throughout the drift region, as opposed to a single lowly-doped drift region. The requirement for both charge-balanced columns and a high trench aspect ratio ( ; the ratio of trench width to trench depth) results in complex process flows. Many of the traditional SJ fabrication techniques developed for Si SJ processing are yet currently not possible in SiC [2]. However, there have been promising developments in SiC SJ fabrication with Kosugi et al. [3] demonstrating a .demonstrating a 3.3 kV SJ with an epitaxial regrowth and implantation process [4].

Previously, we proposed a 2 kV full-SJ device that could be realised via a trench-etch and tilted implantation [5]. The introduction of a trench sidewall angle of , in reference to the -axis, established a graded charge profile throughout the drift region, resulting in an implantation window that was wider when compared to the vertical SJ - making device fabrication more likely.

In this paper, both the trench sidewall angle and tilted implantation are introduced into a semi-SJ topology. The impact of the sidewall angle will be analysed via TCAD simulation (Sentaurus) and discussed with the aim of maintaining a whilst improving the implantation window.

Device Structure and Simulation Setup

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Fig. 1. Half-cell SiC semi-SJ with key dimensions and parameters.

Fig. 1. Half-cell SiC semi-SJ with key dimensions and parameters.

Fig. 1. Half-cell SiC semi-SJ with key dimensions and parameters.

Fig. 1. Half-cell SiC semi-SJ with key dimensions and parameters.

Angles in reference to the -axis

The proposed semi-SJ as can be seen in Fig. 1 and could be developed via a trench-etch and tilted sidewall implantation. The key dimensions and parameters of the proposed structure can be seen in Table 1. The substrate of the structure is with a doping concentration ( ) of and a thickness (tsub) of , as if it had been thinned post-processing. The drift-region is the combination of the n -drift and the n -BAL ( ), both of which have a doping concentration of . The structure has a uniform doping concentration throughout to simplify device fabrication. The thickness of both the n-drift and n-BAL ( ) total and the thicknesses are split between the -ratio . A controllable bevelled-trench profile has been demonstrated in [6]. The p -pillar has a thickness ( ) of 200 nm , a doping concentration ( ), and is assumed to have a box-shape profile. The implantation profile is formed via two Al ions implantations. The first of which is a tilted implantation into both sides of the trench sidewalls, for a given a tilted implantation at allows for the Al ions to reach the bottom of the trench. The second implantation is a vertical implant into the trench bottom. The simulated doping concentrations consider the impact of both incomplete ionisation and activation [7], however, the effects of compensation have not been considered. The half-cell mesa width ( ) is measured at the trench mid-point and has a width of , with in reference to the -axis. Pivoting the trench angle about the mid-point allows for charge balance to be maintained with varying degrees of trench sidewall angle for a given -ratio. A The trench would be passivated with a high-quality layer before being refilled with polyamide (PI). Metal contacts can be formed on the top- and bottom-side of the device. The work-function of the top-side contact is 5.2 eV , similar to that of Ni. The half-cell pitch ( ) is fixed at for all devices to ensure comparable current densities. The models utilised within this study have been discussed in our previous work [5].

Simulation Results and Discussion

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This paper reports on the TCAD optimisation of semi-SJs with a uniform doping concentration and an angled trench sidewall, as seen in Fig. 1. Firstly, the ratio for vertical structures must be identified. As outlined in Fig. 2 (left-left), the was swept for SJ structures with a -ratio varying between . It should be noted that a of means the structure is a full-SJ. Fig. 2

Fig. 2. The impact of - ratio on the (left-left) and on the (left-right), and the impact of on the charge balance of both full- and semi-SJs (right).

Fig. 2. The impact of - ratio on the (left-left) and on the (left-right), and the impact of on the charge balance of both full- and semi-SJs (right).

(left) demonstrates that the full-SJ achieves a of 2090 V and a of - both the highest and in the study. This is because the structure is fully depleted by the alternating SJ pillars and thus achieves the maximum V BD. However, it is worth noting a -ratio of also achieves a high of 2080 V and a comparable Ron,SP to the full-SJ, whilst also being easier to fabricate. This shows the true nature of the 2-D field shaping in SJ structures. The thin and highly doped BAL being fully depleted by the p-doping that surrounds the trench bottom. can be maintained up to a -ratio of , beyond which a significant reduction in occurs. This is the combined effect of having a shallower SJ region and also a thicker highly doped n-BAL region as increases. As the value of the is further increased, the electric field cannot spread into the thicker region, and thus greater proportions of are lost with increasing .

The Ron,SP of the structures continues to decrease with increasing -ratio, as can be seen in Fig. 2 (left-right). This is the result of two effects; firstly, the impact of the pinching between the alternating n - and p -pillars is reduced as the is reduced, and secondly, the additional unbalanced charge within the BAL adds a significant number of carriers to the forward operating state. It must be noted that as the decreases, so does the . As demonstrated in Fig. 2 (left-left), the implantation window (defined as the full-width at of the peak ) is widened from for -ratios between compared to the vertical full-SJ. The wider implantation window within semi-SJ structures is the result of how the electric field spreads throughout the n-BAL. If the p -pillars are under-doped, a high condition occurs in the SJ region. This leads to a reduction in as a result of the reduction of the peak electric field at the n -drift/n-BAL interface, which further leads to a reduction in the electric field supported within the n -BAL. Conversely, if the p -pillars are over-doped, a high condition occurs within the SJ region. This results in a high electric field at the n-drift/n-BAL interface, which in turn allows for a greater electric field to be supported in the n-BAL. This means that semi-SJs offer a greater tolerance to charge imbalance as a result of the peak occurring at high conditions.

Hereafter, a of was used throughout the rest of this study, equating to a -ratio of . This structure achieved a , a reduced relative to the full-SJ, and an implantation window that was wider than that of the vertical full-SJ. Having established the -ratio, a trench sidewall angle ( ) was introduced into the structure. The impact of was then investigated by sweeping , with the results presented in Fig. 2 (right). It can be seen that the introduction of increases the implantation window for both the full- and semi-SJs, the mechanisms being described in our previous work [5]. The semi-SJ with a sidewall increases the implantation window by relative to the vertical semi-SJ and relative to the vertical full-SJ. Interestingly, the reduction brought about from is reduced in the semi-SJ when compared to the full-SJ. This is because of the combination of both the graded charge profile and the n -BAL, which aids the modulation of the electric field, even under the presence of charge imbalance. Thus, the semi-SJ with
a graded charge profile offers a significantly wider implantation window and a reduced Ass, thus increasing its manufacturability.

Fig. 3. The proposed structures plotted against the unipolar limit (left-left), the forward state characteristics (left-right), and the switching characteristics (right).

Fig. 3. The proposed structures plotted against the unipolar limit (left-left), the forward state characteristics (left-right), and the switching characteristics (right).

The similar on-state results can be seen in Fig. 3 (left-right) with all devices turning-on around 1.6 V - consistent with the work function of Ni. Fig. 3 (left-right) reveals that the vertical semi-SJ has a comparable to the full-SJ. The impact of degrading the device and is reduced when implemented within a semi-SJ topology. The semi-SJ with a sidewall reduces the by and increases the by , relative the vertical full-SJ. These characteristics could be recovered by either optimising the n-BAL region and/or by rebalancing the top of the structure.

Finally, it was found that the introduction of the allowed for the gradual depletion of the drift region, thus reducing the rapid decrease in as the structure is fully depleted. In turn, this allows for smoother switching characteristics as can be seen in Fig. 3 (right) comparing the semi-SJ with a sidewall to the full-SJ. Not only are the effects of ringing suppressed by the gradual depletion of the device, but the peak reverse recovery current is also reduced.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.514.pdf

Simulations have shown that the proposed semi-SJ with a sidewall is a practically realisable solution to SJ design. The structure achieves a wider implantation window and softer switching characteristics whilst only partially degrading the and relative to the full-SJ. The combination of both the graded charge profile with the n-BAL allow for greater tolerance to charge imbalance whilst also allowing the structure to deplete more slowly and thus reducing the response, hence producing a softer reverse recovery.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.514.pdf

The work presented in this paper has been carried out as part of EPSRC project EP/R00448X/1. We gratefully acknowledge this support.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.514.pdf

B. J. Baliga, Fundamentals of power semiconductor devices. Springer Science & Business Media, 2010.

Y. Yonezawa, "Recent Progress in High to Ultra-High-Voltage SiC Power Devices: Development and Application," in 2018 International Power Electronics Conference (IPECNiigata 2018-ECCE Asia), 2018: IEEE, pp. 3603-3606.

R. Kosugi et al., "Breaking the Theoretical Limit of 6.5 kV -Class 4H-SiC Super-Junction (SJ) MOSFETs by Trench Filling Epitaxial Growth," in ISPSD, Shanghai, China, May 19-23 2019.

M. Baba et al., "Ultra-Low Specific on-Resistance Achieved in 3.3 kV -Class SiC Superjunction MOSFET," in 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2021: IEEE, pp. 83-86.

G. Baker et al., "Optimization of 4H-SiC Superjunction Schottky Rectifiers With Implanted P-Pillars for Practical Realization," IEEE Transactions on Electron Devices, vol. 68, no. 7, pp. 3497-3504, 2021.

H.-K. Sung et al., "Vertical and bevel-structured SiC etching techniques incorporating different gas mixture plasmas for various microelectronic applications," Scientific reports, vol. 7, no. 1, pp. 1-9, 2017.

J. Pernot et al., "Electrical transport properties of aluminum-implanted 4H-SiC," Journal of applied physics, vol. 98, no. 2, p. 023706, 2005.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 519-522

doi: 10.4028/p-2pm0e2

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-23

Accepted:
2022-03-17

Online:
2022-05-31

DC Modeling of -SiC nJFET Gate Length Reduction at

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

Mohit R. Mehta , Philip G. Neudeck , and John W. Lawson

KBRWyle Services, LLC., Intelligent Systems Division, NASA ARC, Moffett Field, CA 94035, USA

NASA Glenn Research Center, Cleveland, OH 44135, USA

Intelligent Systems Division, NASA Ames Research Center, Moffett Field, CA 94035, USA

mohit.r.mehta@nasa.gov, neudeck@nasa.gov, john.w.lawson@nasa.gov

Keywords: Turn-Off Characteristics, COMSOL, Shallow Nitrogen Implant, Phosphorous Implant

Abstract

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of (recently fabricated Gen. 11 ICs) limits mission-relevant circuit capabilities. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies (shallow and extended ) to reduce the SiC JFET channel length while maintaining the turn-off behavior needed to realize circuit operation. COMSOL Multiphysics was used to simulate the transfer characteristics and maximum potential below the gate of a 4 H -SiC nJFET at , and a gate length nJFET with turn-off performance comparable to the state-of-the-art is suggested.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

NASA is exploring silicon carbide, a wide band-gap semiconductor material capable of operating at high temperatures, to create robust, high-performance electronics that can work in harsh environments (high radiation levels and high Venusian surface temperatures) [1]. A step towards this goal is to substantially reduce the channel length of nJFETs recently fabricated in the Gen. 11 ICs [2] from to . There are various strategies to reduce the gate length and feature size of a JFET [3]. This paper presents a study on reducing the gate length of a lateral nJFET by comparing and contrasting two fabrication strategies. The first fabrication strategy uses a shallow self-align nitrogen implant (SN, Fig. 1a) along the device's top surface but not below the gate combined with a highdose phosphorous implant directly below the source and drain contacts, while the second strategy (Fig. 1b) uses high-dose phosphorous implants that extend from below the contacts up to the gate

Fig. 1: Schematic for the nJFET device with two doping strategies: a) self-align nitrogen (SN) and b) extended phosphorous (EP). The different layers are substrate (blue), sub-channel layer (light blue), epitaxial layer (green), source and drain epilayer (dark green), nitrogen self-align implant (light green), and gate epilayer (dark blue).

Fig. 1. Schematic for the nJFET device with two doping strategies: a) self-align nitrogen (SN) and b) extended phosphorous (EP). The different layers are substrate (blue), sub-channel layer (light blue), epitaxial layer (green), source and drain epilayer (dark green), nitrogen self-align implant (light green), and gate epilayer (dark blue).

edges. These two doping strategies are explored in order to shorten gate length while maintaining or improving nJFET's turn-off performance. For this study, twelve variations of lateral epitaxial nJFETs with different fabrication strategies, gate lengths, and geometric properties were simulated in COMSOL. However, only a few key results are shown for brevity.

Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

Experiment. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1a) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. The SN device structure is consistent with experiments by NASA GRC in prototype IC generations 10 and 11 [2]. The experiments were performed at and the epilayer thickness of the device was .
Simulations. The 4H-SiC nJFET was simulated using COMSOL Multiphysics v5.6 with the semiconductor module. The material parameters and the physical models used to simulate the electrical potential and carrier concentration profiles were taken from Ref. [4]. The models used to simulate the physics for nJFET were: Auger recombination, Shockley-Read-Hall (SRH) recombination, incomplete ionization, and low-field mobility. The details of the model, its implementation, and the simulation protocol for simulating a 4H-SiC nJFET in COMSOL are available on reasonable request.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

Before the gate length reduction studies, the turn-off and transfer characteristics of the COMSOL simulations were validated with the measured data of a nJFET with the SN strategy at , and the results are presented in Fig. 2. The threshold voltage ( ) were computed using the saturation extrapolation technique. Using this method, the simulated (experimental) values of are computed to be , when , and , when . While the values of are and , respectively.

The simulations show that the is similar for both the doping strategies, while the saturated drain current ( ) is about higher for the EP strategy. The higher value of results from the deeper and higher concentration of dopants used in the EP strategy. The fit with the experiments validates the nJFET model implementation and the simulation protocol. Note that the high

Fig. 2: The transfer characteristics for a gate length 4H-SiC nJFET with self-align N (simulation results from the EP strategy is shown for comparison) is validated with measured experiments for two substrate biases, -25 V (black) and -15 V (brown), at . Left axis shows the total wide device) while the right axis shows normalized . Note that measured current floor was limited by package leakage extrinsic to the device and was not simulated.

Fig. 2. The transfer characteristics for a gate length 4H-SiC nJFET with self-align N (simulation results from the EP strategy is shown for comparison) is validated with measured experiments for two substrate biases, -25 V (black) and -15 V (brown), at . Left axis shows the total wide device) while the right axis shows normalized . Note that measured current floor was limited by package leakage extrinsic to the device and was not simulated.

Table 1: Transfer characteristics for various nJFET designs simulated at . SN and EP were the two implant strategies used to reduce gate-to-source resistance. The parenthetical values are for the SN strategy. For the * case, the epilayer thickness was reduced from to .

# | Type | WM [μm] | WS [μm] | WR [μm] | WG [μm] | −Vth [V] | Idss [A/m]
1 | SN | 3.0 | 6.0 | 3.0 | 6.0 | 8.2 | 11.8
2 (3) | EP (SN) | 3.0 | 6.0 | 4.5 | 3.0 | 8.8 (8.8) | 28.6 (22.9)
4 (5) | EP (SN) | 3.0 | 3.0 | 5.5 | 1.0 | 14.1 (15.8) | 105.9 (66.3)
6* (7*) | EP (SN) | 3.0 | 3.0 | 5.5 | 1.0 | 8.8 (9.4) | 63.2 (36.6)

value of the turn-off current floor in the experiments was a result of the package leaking current [5]. Thus, the simulation model parameters were not modified to quantitatively match the experimental off-state current floor.

Table 1 compares the DC electrical performance of nJFETs with decreasing gate length for each of the doping strategies. These results are consistent with short-channel device physics reported in the literature for other types of field-effect transistor structures. In other words, the ability of the negative gate bias to impose a higher potential barrier to inhibit electron transport from source to drain diminishes as channel length shrinks. This barrier reduction is evident in Figs. 4a-c. However, thinning the epilayer channel does increase the potential barrier, as seen in devices as seen in devices #6* (Fig. 4d) and #7* (not shown). Note that this approach significantly tightens the processing margins and risk associated with still-maturing SiC epilayer thickness tolerance/control as well as the gate finger etch depth. While increasing the -layer doping might also improve device turn-off performance, this would also increase the magnitude of substrate body bias effect that would present additional circuit design challenges. Another experimental risk of the EP strategy is the higher electric field and leakage currents it might impose where the EP implant borders the edge of the gate. While this has not been a problem in experimentally realized SN devices operated at , the increased doping of the EP devices could raise the peak electric field in this region. Therefore, a further study of the EP approach is planned to elucidate its leakage and breakdown properties.

Fig. 3: The simulated turn-off characteristics for selected designs, each I-V curve is annotated with its device number from Table 1. Simulation results from the nitrogen self-align strategy are shown using dashed lines, while the extended phosphorous strategy results are shown using solid lines. Other simulation parameters were: , and .

Fig. 3. The simulated turn-off characteristics for selected designs, each I-V curve is annotated with its device number from Table 1. Simulation results from the nitrogen self-align strategy are shown using dashed lines, while the extended phosphorous strategy results are shown using solid lines. Other simulation parameters were: , and .

Fig. 4: The value of the maximum potential below the gate for the selected devices ( , and 6 ) listed in Table 1. Other simulation parameters were: , and .

Fig. 4. The value of the maximum potential below the gate for the selected devices ( , and 6 ) listed in Table 1. Other simulation parameters were: , and .

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

This paper explored design strategies to optimize the lateral-gate-length of a operating at using COMSOL multiphysics. We compared the turn-off characteristics of two fabrication strategies, SN and EP , with gate length decreasing from to . The results show that the deeper and high concentration of phosphorous dopants combined with a thinner epitaxial channel led to a better turn-off response when decreasing gate length. Simulations resulted in a nJFET design with a gate length without compromising the turn-off performance.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

Computational work was performed at NASA Ames Research Center with financial support from the Center Innovation Fund (CIF), NASA Ames Research Center, while the experimental work was performed at NASA Glenn Research Center with funding from the NASA Science Mission Directorate under Long-Lived In-Situ Solar System Explorer (LLISSE).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.519.pdf

Philip G. Neudeck, Roger D. Meredith, Liangyu Chen, David J. Spry, Leah M. Nakley, and Gary W. Hunter. Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions. AIP Advances, 6(12):125119, dec 2016.

P. Neudeck, D. Spry, M. Krasowski, L. Chen, N. Prokop, L. Greer, and C. Chang. Progressing to Durable SiC JFET ICs From MSI to LSI. In 2020 IEEE International Electron Devices Meeting (IEDM), pages 27.2.1-27.2.4, dec 2020.

R.K. Malhan, Y. Takeuchi, M. Kataoka, A.-P. Mihaila, S.J. Rashid, F. Udrea, and G.A.J. Amaratunga. Normally-off trench JFET technology in 4H silicon carbide. Microelectronic Engineering, 83(1):107-111, jan 2006.

A. Arvanitopoulos, N. Lophitis, S. Perkins, K. N. Gyftakis, M. Belanche Guadas, and M. Antoniou. Physical parameterisation of 3C-Silicon Carbide (SiC) with scope to evaluate the suitability of the material for power diodes as an alternative to . In 2017 IEEE 11th International Symposium on Diagnostics for Electrical Machines, Power Electronics and Drives (SDEMPED), pages 565-571. IEEE, aug 2017.

Philip G. Neudeck, David J. Spry, Liangyu Chen, Norman F. Prokop, and Michael J. Krasowski. Demonstration of digital integrated circuits above . IEEE Electron Device Letters, 38(8):1082-1085, aug 2017.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 523-527

doi: 10.4028/p-92w3k6

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-25

Accepted:
2022-03-17

Online:
2022-05-31

A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

The original version of this paper is available on https://www.scientific.net/MSF.1062.523.pdf

A.B. Renz , O.J. Vavasour , M. Rommel , G.W.C. Baker , P.M. Gammon , T. Dai , F. , M. Antoniou , P.A. Mawby and V.A. Shah

School of Engineering, University of Warwick, Coventry, UK

Fraunhofer Institute for Integrated Systems and Device Technology IISB, Erlangen, Germany

A.Renz@warwick.ac.uk, o.vavasour.1@warwick.ac.uk, mathias.rommel@iisb.fraunhofer.de,

Guy.Baker@warwick.ac.uk, P.M.Gammon@Warwick.ac.uk, T.Dai@warwick.ac.uk, jP.A.Mawby@warwick.ac.uk, vishal.shah@warwick.ac.uk

Keywords: 4 H -SiC, Germanium, Vanadium, implantation, semi-insulating, high-resistivity, epitaxy

Abstract

A systematic germanium (Ge) and vanadium (V) study on epitaxial layers is presented. Electrical results of TLM structures which were fabricated on these layers revealed that highly-doped Ge and V-implanted layers showed extremely low specific contact resistivity, down to . Current flow in the conducting state of Schottky barrier diodes has been successfully suppressed in some implanted layers, with highly V doped samples showing current density values of approximately at 10 V . DLTS spectra reveal the presence of germanium and vanadium centers in the respective samples as well as novel peaks which are likely related to the formation of a novel GeN center.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.523.pdf

The wide bandgap semiconductor 4 H -silicon carbide has widely penetrated the power electronics device market over the past decade, utilising unipolar device structures such as Schottky barrier diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) with blocking voltage ratings from . More recently, interest in high-resistivity, semi-insulating substrates for harsh environment applications has risen. This led to increased research activities in the development of localized semi-insulating layers via epitaxy or implantation in order to produce a SiC -on-insulator ( SiCOI ) materials system.

The use of a semi-insulating substrate reduces parasitic capacitance and leakage, and these are typically fabricated by adding dopants that act as electron-trapping recombination centers deep in the bandgap, at a concentration higher than the nominal dopants.

Applications for SiCOI include radiation hard electronics [1], GaN HEMT platforms [2], high power ( ) and high frequency ( 1 GHz ) RF applications [3]. For 4H-SiC, the most common semi-insulating impurity is vanadium (V), which is often incorporated during substrate or epitaxial growth [4]. Recently, the introduction of germanium (Ge) has shown interest and yielded some potential benefits via epitaxy [5] or implantation [6] into SiC, with lower levels [7], higher mobility [8] and higher conductivity[9]. However, less is known about the combination of Ge with additional n-type compensation doping. This would allow flexibility in device fabrication: allowing selective electrical enhancement or semi-insulation.

In this investigation, a matrix of , and N co-implanted SiC epitaxial layers is characterized, both using electrical and physical methods, to demonstrate the change in insulating properties depending on implantation condition. Device structures that were fabricated on the layers include transfer length method (TLM) bars and Schottky barrier diodes (SBDs). The presence of deep levels in the material was investigated using deep-level transient spectroscopy (DLTS).

Experimental

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thick, n-type doped ( ) epitaxial layers were grown on 100 mm diameter, offaxis, (0001) SiC wafers using an LPE ACiS M8 chemical vapour deposition (CVD) reactor. Growth was performed using tricholosilane and ethylene at a C:Si ratio of 1.1 and of at a reduced pressure of 100 mbar . This gave a growth rate of using an effective flow of 0.12 sccm nitrogen ( ) as a dopant. After an initial clean and dry etch to form mesas for the respective device structures, a plasma deposition was performed at using bis(diethylamino)silane (BDEAS) and plasma precursors in an Ultratech Fiji G2 PlasmaEnhanced ALD system. Afterwards, quarter wafers underwent a blanket implantation schedule (box profile) that is

Figure 1: General schematic for implantation and device layout, a) specifically for a SBD, b) ohmic contact formation for TLM measurement.

Figure 1. Figure 1: General schematic for implantation and device layout, a) specifically for a SBD, b) ohmic contact formation for TLM measurement.

outlined in Table 1. An additional high-dose contact implant in patterned areas was performed where ohmic contacts were required (TLMs). Cross sections of the layer structure of SBD and TLM structures are shown in Fig.1. 200 nm deep, box profile Ge and V implantations, were performed with high and low nominal concentrations of and , both values exceeding the as-grown doping concentration by at least one order of magnitude. Samples were then laser cut into chips before being cleaned and given post-implantation anneal at backside contacts (and topside for TLM samples) were then deposited, before annealing the samples at for 2 minutes to form ohmic contacts. Finally, 100 nm thick molybdenum (Mo) was e-beam deposited, before being annealed at for 2 minutes in argon (Ar) ambient to form Schottky contacts.

Table 1: Overview of the implantation schedule and specific contact resistivity and sheet resistance values for all samples, with post-implantation anneal at .

#ID
Sample description
Implanted concentration (cm⁻³)
Implanted thickness (nm)
Sheet resistance (Ω.sq⁻¹)
Specific contact resistivity (Ω.cm²)

S1
Lowly doped Ge
Ge: 5 × 10¹⁶
Ge: 200
2.06
3.90 × 10⁻²

S2
Lowly doped Ge with co-doped N
N: 1 × 10¹⁸
Ge: 5 × 10¹⁶
N: 100
Ge: 200
15.66
1.51 × 10⁻²

S3
Highly doped Ge
Ge: 5 × 10¹⁸
Ge: 200
10905
1.03 × 10⁻³

S4
Highly doped Ge with co-doped N
N: 1 × 10¹⁸
Ge: 5 × 10¹⁸
N: 100
Ge: 200
8165
2.19 × 10⁻⁷

S5
Control (blanket n+)
N: 5 × 10¹⁸
N: 200
13.95
8.38 × 10⁻³

S6
Lowly doped V
V: 5 × 10¹⁶
V: 200
1016
5.85 × 10⁻⁴

S7
Lowly doped V with co-doped N
N: 1 × 10¹⁸
V: 5 × 10¹⁶
N:100
V: 200
79.74
3.49 × 10⁻³

S8
Highly doped V
V: 5 × 10¹⁸
V: 200
12233
3.48 × 10⁻³

S9
Highly doped V with co-doped N
N: 1 × 10¹⁸
V: 5 × 10¹⁸
N: 100
V: 200
9231
1.52 × 10⁻⁵

DLTS measurements were carried out using a PhysTech FT-1230 DLTS system. For sample preparation, an additional 100 nm layer of nickel was added to the Schottky contacts, the samples
were glued to a chip carrier using conductive EPO-TEK®P1011 and wire bonded. The displayed data is for a time window of 64.5 ms , a reverse bias of -1 V , a pulse voltage of 0 V and a filling pulse duration of 10 ms . In addition to the implanted samples, a control sample with no implantations was also analysed.

Results

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Room temperature current-voltage (I-V) sweep measurements were taken on TLM structures from -1 to steps) to investigate the impact of Ge and V on the specific contact resistivity and sheet resistance. An overview of the results of these TLM measurements is also shown in Table 1. This emphases the drastic increase in sheet resistance from in the nitrogen-blanket implanted sample (sample 5) to sheet resistance values up to around for the samples with high semi-insulating doping, both with and without N co-doping ( and S 9 ). Hence, the high-dose implantation of Ge and V leads to a decrease in specific contact resistivity up to for a highly co-doped Ge sample (S4), which is a promising result allowing a low contact resistance in conjunction with semi-insulating properties.

In a next step, the rectifying characteristics of Schottky diodes were auto-probed at room temperature using a Keysight B1505A with a Semiprobe semi-automatic probe station. On-state current densities were extracted for at least 25 devices. Fig. 2 (a) depicts the forward bias response of devices from the different samples. Here, the V-implanted samples without co-doping (S6&8, blue and green straight line) show a decrease in leakage current density, with current values not exceeding and at a forward bias of 10 V , respectively. A distinction can be seen when comparing this to Ge-implanted samples without co-doping (S1&3, wine and purple solid traces), which exceeded much higher current density values of at the same voltage. Although the specific contact resistivity is reduced by highly doping SiC epilayers with Ge and V, only the highly-doped vanadium samples appear to significantly reduce the specific on-resistance in the forward conducting state.

DLTS temperature scans from a selection of samples is shown in Fig. 2 (b) and an outline of the observed defect levels is given in Table 2. In addition to the intrinsic level and the adventitious Ti level, the implantation of semi-insulating dopants has introduced several levels. Peak #5, observed at in sample 6 [10], is typical of V in , and the similar level at in samples 8 & 9 is probably also due to V, possibly with a shift in caused by the high implantation dose. Similarly, peak #3 observed at in samples is likely a level induced by Ge in . Peaks #2 and #6 are not characteristic of Ge in 4H-SiC and are only observed for a high Ge dose, codoped with N, suggesting that a new defect is formed for Ge and N co-implantation. This is consistent with the extremely high DLTS signal from peak #6.

Table 2: Overview of the detected DLTS peaks and their probable identity.

#Id | Approx. peak temperature (K) | Observed for | Probable identity | Reference
1 | 90 | All | Ti | [10]
2 | 190 | High Ge doping | Unknown, possible GeN centre | -
3 | 240 | All Ge | Ge | [11]
4 | 310 | All except V doped | Z1/2 | [10]
5 | 430/480 | All V | V | [10]
6 | 510 | High Ge w. co-doping | Unknown, possible GeN centre | -

Figure 2: (a) Typical on-state I-V of the Schottky diodes, measured at . (b) DLTS spectrum of Ge and V implanted SBDs, measured from 50 K to 650 K , with . The numbered items refer to the peak identifiers in Table 2.

Figure 2. Figure 2: (a) Typical on-state I-V of the Schottky diodes, measured at . (b) DLTS spectrum of Ge and V implanted SBDs, measured from 50 K to 650 K , with . The numbered items refer to the peak identifiers in Table 2.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.523.pdf

Highly implanted Ge and V layers significantly decrease specific contact resistivity values of TLM structures, down to for a high dose Ge sample (sample 4), which is a promising result regarding the semi-insulating properties. In the conducting state of Schottky barriers, only the highly-doped V layers showed a significant reduction of current density levels to 1 x at 10 V bias. DLTS spectra reveal, beside the presence of common and Ti peak, Ge and V peaks in the respective samples. In addition, novel peaks are observed which are thought to be related to the presence of GeN .

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.523.pdf

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R. Karhu, E. Ö. Sveinbjörnsson, B. Magnusson, I. G. Ivanov, Ö. Danielsson, and J. Ul Hassan, "CVD growth and properties of on-axis vanadium doped semi-insulating 4H-SiC epilayers," Journal of Applied Physics, vol. 125, no. 4, p. 045702, 2019.

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G. Katulka et al., "A technique to reduce the contact resistance to 4 H -silicon carbide using germanium implantation," Journal of electronic materials, vol. 31, no. 5, pp. 346-350, 2002.

T. Dalibor et al., "Deep defect centers in silicon carbide monitored with deep level transient spectroscopy," physica status solidi (a), vol. 162, no. 1, pp. 199-225, 1997.

T. Sledziewski, G. Ellrott, W. Rösch, H. B. Weber, and M. Krieger, "Reduction of implantation-induced point defects by germanium ions in n-type 4H-SiC," Materials Science Forum, vol. 821, pp. 347-350, 2015.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 528-532

doi: 10.4028/p-oajc69

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-25

Accepted:
2022-03-17

Online:
2022-05-31

Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.528.pdf

Lakshmi Kanta Bera , Navab Singh , Zhixian Chen , Calvin Chua Hung Ming , King Jien Chui , Ravinder Pal Singh , Yee Ye Sheng , Surasit Chung , K. Michael Han , Karen Chong and Dim-Lee Kwong

Institute of Microelectronics, 2 Fusionopolis Way, #08-02 Innovis Tower, Singapore 138634

beralk@ime.a-star.edu.sg, navab@ime.a-star.edu.sg, chenzx@ime.a-star.edu.sg,

chuahm@ime.a-star.edu.sg, chuikj@ime.a-star.edu.sg, ravinderps@ime.a-star.edu.sg, Yee_Ye_Sheng@ime.a-star.edu.sg, surasit_chung@ime.a-star.edu.sg,

Michael_Han@ime.a-star.edu.sg, Karen_Chong@ime.a-star.edu.sg, kwongdl@ime.a-star.edu.sg

Keywords: Silicon Carbide, High-k, multi stacks, interface traps.

Abstract

Metal-oxide-semiconductor capacitors with single and multi-layer high-K gate dielectrics on Si (0001) face of n-type 4H-SiC substrates have been investigated. Multi-layered nanolaminated gate-stack comprises alternating ultrathin and . A 5 nm thick interfacial silicon oxynitride is deposited prior to laminated films to investigate interface trap properties and tuning of flat band voltage. Total thickness of gate-stack films including interfacial layer is 55 nm . The thermal stability of multi-layered nanolaminated film is investigated using XTEM. Localized crystallization of is visible after RTA at while remains fully amorphous. Some of grains have extended into layer but was not able to crossover. The measured accumulation capacitance of 55 nm thick gate dielectric gives an effective dielectric constant value of 9.6 and an equivalent oxide thickness of 22 nm from high-frequency capacitance-voltage measurements. A positive flat band voltage of 12.2 V and 10.6 V are observed from both single layer and dielectrics, respectively due to presence of negatively charged oxygen interstitial defects generated during atomic layer deposition process. However, shifted towards negative voltage -7.6 V for multi-layered stacks probably associated with positive Al and Hf interstitials at interface of . Ultrathin interfacial oxynitride films is effective to reduce to and tuning of . The breakdown field of stacked gate dielectric on is .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.528.pdf

Silicon carbide is one of the most promising semiconductor materials used commercially for fabrication of high-power, high frequency, and high-temperature MOSFETs because of its wide band gap, high breakdown field, high thermal conductivity and ability to grow thermal for gate insulator. However, high temperature thermal oxidation processes cause residual carbon related defects at and near the interface leading to high interface state density ( ) and mobility degradation [1]. In addition, 2.5 times higher dielectric constant of SiC than predominantly increases electric field at gate insulator by the same order. These issues can be resolved through integration of high-K gate stacks with dielectric constant higher than that of SiC so that the electric field at the gate stack will be lower than the adjacent SiC and thus reduces dielectric stress. Lori et. al. studied several high-K gate stacks on SiC using MOCVD and PVD techniques but all the gate stack materials resulted in high gate leakage current [2]. Recent studies on (AlON) shows N-related defects leading to significant hole conduction. Hf was then incorporated into AlON to form HfAlON to reduce N-related defects and to improve insulating properties of the dielectric [3-4]. In this work, we developed multi-layer high-K gate dielectrics for 4H-SiC MOSFETs applications.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1062.528.pdf

Metal-oxide-semiconductor (MOS) capacitors were fabricated on Si-face (0001) n-type substrates with thick epitaxial layer. The samples were cleaned using piranha solution ( ) at for 10 minutes followed by rinsing with DI water and drying using gun. Native oxide was removed using dilute for 60 sec prior to dielectric deposition. Multiple stacks of with an interfacial oxynitride ( ) layer were deposited in different combinations using atomic layer deposition (ALD). Fig. 1 shows a physical cross-section view of stack of the gate laminate ( type) along with its corresponding band-diagram.

Fig. 1. Schematics of multi-layer high-k stacks with band alignment on .

Fig. 1. Schematics of multi-layer high-k stacks with band alignment on .

The atomic layer deposition (ALD) process involved cycling of precursor and reactant to achieve deposition of controlled and highly conformal layers at the atomic level. Cyclic nature of the deposition with alternate switching between and is thought to minimize pinhole defects in the film. MOS capacitors were then fabricated on a (0001) Si-face of 4 H -SiC with thick N doped homo-epilayer deposited on highly doped n-type substrate. A stack of Ni/Ti/Ni metal was evaporated on front side using a shadow mask to create MOS capacitor top electrodes, with blanket metal deposition on the substrate backside for the back contact. Samples were annealed at different temperatures to study the temperature stability of the gate stack and effect on . Temperature stability is absolutely needed as silicide formation on SiC MOSFET is a high-temperature step ( 900 to ) and that occurs after gate stack formation.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1062.528.pdf

The microstructural analysis to examine the interfaces of laminated multi-layered stacks after fabricaion of MOSCAP devices annealed at using transmission electron microscopy (TEM). The interfaces of alternating stacks of materials are distinctly maintained as illustrated in crosssectional TEM images in Fig. 2 (a). The localized lattice fringes due to the crystallization of after RTA is observed in higher magnification TEM image (Fig 2(b)) while remained fully amorphous. Some of the grains extended towards layer but were not able to crossover the layer. The bottom layer remains smooth and amorphous.

Fig. 2. TEM cross-section images of multilayer stacks (a) and its high magnification image (b).

Fig. 2. TEM cross-section images of multilayer stacks (a) and its high magnification image (b).

Fig. 3 shows the high frequency capacitance-voltage ( ) charateristics of several dielectric films. The slow rise of capacitance from inversion to accumulation is contributed by sevaral bulk charges and interface traps, and further development work is required to mitigate this issue. The measured
accumulation capacitance of 55 nm thick gate dielectric gives an effective dielectric constant value of 9.6 and an equivalent oxide thickness of 22 nm using high frequency data as shown in Fig. 3.

Fig. 3. Normalized C-V char. of different highK gate stacks on measured at 100 kHz .

Fig. 3. Normalized C-V char. of different highK gate stacks on measured at 100 kHz .

Fig. 4. Plot of vs VG to extract .

Fig. 4. Plot of vs VG to extract .

V is extracted from experimental CV curve using the relationship in equation (1)

where is the dielectric capacitance at accumulation and the measured capacitance of the gate-stacks [5]. The plots of vs for different gate stacks are shown in Fig. 4. The intersection with axis of the linear extrapolation of the graph corresponds to giving . The single and dielectrics show positive which indicates presence of negative charges in the films. Oxygen interstitial defects in dielectric oxide films generated during the ALD process are known to be negatively charged and could possibly be the reason for high fixed negative charges in the film [6]. A high negative is then observed for type stacks. The nano laminate stacks with mild intermixing/doping at the interface of generate more positive Al and Hf interstitial causing shifts in the negative direction. It was presumed that the shift is largely controlled by interfacial trap charges. To solve the large shift issue an interfacial layer was introduced on the SiC surface before deposition of multilayer stacks. As a result, a significant recovery in was observed, as shown in Fig 4. The tuning process demonstrated here is an important step towards implementation of high-k gate stacks on SiC substrate.

The interface state density is extracted using Hill-Coleman conductance method [7,8]

where is the peak conductance value, the corresponding capacitance at the peak gate bias, and is dielectric capacitance at accumulation. Fig. 5 shows the charateristics of different dilectric stacks used to extract interface traps.

Fig.5. Gate conductance versus voltage characteristics of MOS capacitor measured at 100 KHz

Fig.5. Gate conductance versus voltage characteristics of MOS capacitor measured at 100 KHz

Fig. 6. Comparison of interface state density ( ) with published data. This work reports the lowest value among high-k stacks.

Fig. 6. Comparison of interface state density ( ) with published data. This work reports the lowest value among high-k stacks.

The interface state density extracted using equation (2) from the measured values of capacitance and conductance for different high-K stacks are compared with other reported results and illustrated in Fig. 6. The interfacial layer with laminate is effective to reduce to , which is an order of magnitude lower than values previously reported on high-K [7-11] and other gate stacks in this work.

Fig.7. Jg-Vg characteristics of high-K gate stacks on at 300 K

Fig.7. Jg-Vg characteristics of high-K gate stacks on at 300 K

Fig. 8. Jg-Vg characteristics of gate stacks at 300 K after post deposition anneal in at 600 to .

Fig. 8. Jg-Vg characteristics of gate stacks at 300 K after post deposition anneal in at 600 to .

Fig. 7 shows the Jg-Vg characteristics of different gate stacks measured under accumulation. Low gate leakage current density of at demonstrates high gate dielectric integrity. The breakdown field of stacked gate dielectrics on is . The thermal stability of gate stack was investigated by post deposition rapid thermal anneal in . It was found that the gate stack is fully stable up to with slight degradation of flat band voltage ( ) at probably due to the localized crystalization of as seen in TEM. No gate leakage current degradation was observed after post deposition high temperature annealing (Fig. 8), demonstrating robust thermal stability against high-temperature RTA.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.528.pdf

The effect of ultrathin interfacial layer with multi stack nanolaminated films and standalone and gate stacks were systematically investigated. Excellent thermal stability was observed for the multilayer nano laminated film. The interfacial oxynitride film is effective to reduce to and tuning of . In summary, we developed multi-layered high-K gate stack technology with tuneable and low for high-performance SiC power MOSFETs .

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.528.pdf

N. S. Saks, S. S. Mani, and A. K. Agarwal, Appl. Phys. Lett. 76, 2250(2000).

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Hironori Yoshioka, Masashi Yamazaki and Shinsuke Harada, Aip Advances 6, 105206 (2016).

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K. Matsunaga, T. Tanaka, T. Yamamoto, Y. Ikuhara, Physical Rev B, vol. 68, 085110, (2003).

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Y. Wu, S. Wang, Y. Xuan, T. Shen, Peide D. Ye, J. A. Cooper Jr., ISDRS 2007, December 1214, 2007, College Park, MD, USA.

K. Y. Cheong, J. H. Moon, T. J. Park, J. H. Kim, C. S. Hwang, H. J. Kim, W. Bahng, and N. K. Kim, IEEE Trans Electron Dev. Vol. 54, No. 12, 3409 (2007).

T. Hosoi, S. Azumo,Y. Kashiwagi, S. Hosaka,R. Nakamura,S. Mitani,Y. Nakano,H. Asahara,T. Nakamura, T. Kimoto, T. Shimura and H. Watanabe, 2012 International Electron Devices Meeting, p. 15

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This work was supported by the Science and Engineering Research Council of ASTAR (Agency for Science, Technology and Research) Singapore, under Grant No. A20H9a0242.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 533-538

doi: 10.4028/p-z4mz75

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-18

Revised:
2022-03-30

Accepted:
2022-03-30

Online:
2022-05-31

Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

The original version of this paper is available on https://www.scientific.net/MSF.1062.533.pdf

Simon Mendy , Ruizhu Wu , Jose Ortiz Gonzalez , Olayiwola Alatise

School of Engineering, University of Warwick, Coventry, United Kingdom

s.mendy@warwick.ac.uk, robert.wu.1@warwick.ac.uk, j.a.ortiz-gonzalez@warwick.ac.uk,

do.alatise@warwick.ac.uk

Keywords: SiC MOSFETs, FET, threshold voltage mismatch, gate synchronisation, current sharing, parallel-connected MOSFETs, inductive load switching, device under test - DUT

Abstract

In high current applications that use several parallel-connected SiC MOSFETs (e.g., automotive traction inverters), optimal current sharing is integral to overall system reliability. Threshold voltage ( ) variation in SiC MOSFETs is a prevalent reliability issue that can cause a current mismatch in parallel-connected devices. Using experimental measurements and compact modelling, a technique has been developed to characterise variation's impact in up to 8 parallelconnected SiC MOSFETs (self-imposed limit). This model can predict the allowable variation for optimal current sharing. It can also be used to evaluate the impact of other parameters, including gate driver synchronisation, on current sharing in parallel devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.533.pdf

This paper investigates the impact of variation on several parallel (up to 8 - self-imposed limit - the range can be extended to 10s of devices) SiC MOSFETs. The role of parameter variation in the short circuit performance of parallel devices has been investigated in [ ] and unclamped inductive switching [4,5]. Due to the inherent variability of in SiC MOSFETs, it is essential to select devices with minimal variation to avoid unbalanced current sharing and unsynchronised switching between devices [6]. Hence, diagnostic modelling tools that can predict the impact of parameter mismatch on current sharing are required. [7] presents a parallel model, but it does not specify how many parallel devices the model can simulate and does not explore the role of VTH mismatch between devices. They propose adjustment of the gate resistance to solve the inconsistent switching characteristics of parallel devices. [8] investigates the effect of mismatches between device characteristics and circuit components of paralleled SiC MOSFETs. The plots shown bear a close resemblance to the Vth mismatch of up to 8 devices illustrated further in this paper. The DUT with the lower turns ON faster and turns OFF slower. The model, however, is not electrothermal and does not explore the temperature effects of mismatch on current sharing specifically for multiple paralleled DUTs and a long duration of repetitive switching. [9] suggests an active gate driving method to mitigate the current sharing performance caused by mismatched . This is a viable solution but adds more complexity to driving paralleled devices.

While design engineers have traditionally used SPICE based models as diagnostic tools, their application depends on model availability and ease of parameter tuning. This study presents a statespace model derived from parallel-connected MOSFET equivalent circuits that include all parasitic capacitances and inductances [10]. Device datasheets are used to parameterise the model extensively. Unavailable parameters are extracted by curve fittings of the output characteristics from the device datasheet to produce the equation for channel current. The model is temperaturedependent since it incorporates the temperature dependency of and device transconductance. The transient thermal impedance extracted from the datasheet is used to create the thermal network that couples with the electrical parameters.

Model Development and Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.533.pdf

The circuit used to derive the equations for the model is shown in Fig. 1. In the experiments, the PCB tracks are designed to be the same length to mitigate mismatch in parasitics ( , and and resulting transients. The channel current, of the SiC MOSFETs, is modelled from datasheet output characteristics graphs using fitted equations related to the gate overdrive voltage ( ) and temperature T (see Eq. 1) [11]. The physical constants K and are extracted using the curve fitting tool in MATLAB and are made overdrive voltage- and temperature-dependent. The material constant, K , contains , which is overdrive voltage and temperature-dependent [12]. In addition, is overdrive voltage-dependent and temperature-dependent since it is a function of .

From Fig. 1, the following equations (Eq. Eq. 5) are derived, then converted into state-space form according to Eq. 10 and modelled in MATLAB Simulink using the State-Space block.

Fig. 1. The circuit diagram of MOSFET 1, MOSFET 2, to MOSFET n , connected in parallel, which is used to produce the model.

Fig. 1. The circuit diagram of MOSFET 1, MOSFET 2, to MOSFET n , connected in parallel, which is used to produce the model.

Fig. 2. Output characteristics of the model compared to the datasheet at Tj .

Fig. 2. Output characteristics of the model compared to the datasheet at Tj .

Key: is the leg number, from left to right according to Fig. 1, and is the total number of devices connected in parallel. The inputs of the model are , and .

The model is verified by reproducing the output characteristics of the datasheet, as shown in Fig. 3. Fig. 3 shows the model switching test results compared to experimental results of the same parameters for a total load current of 8 A . The experimental measurement was obtained using a double-pulse test setup [13], with two devices in parallel ( and ). The DC link voltage was 200 V , and the total load current was 8 A . The currents were measured using Rogowski coils current probes.

A difference of 1 V , as shown by the plots in Fig. 4 from the model, does not produce much difference in current sharing between DUTs for four and eight parallel-connected devices when the gate signals are synchronous. In Fig. 4, one can observe that configurations with more parallel devices show longer turn-ON and turn-OFF switching times and more differences in the switching delay during turn-ON and turn-OFF between the DUTs, as expected.

The switching time difference created by a difference of any magnitude can be computed using Eq. 9 [11]. For the C3M0280090D SiC MOSFET, the input capacitance, , is 150 pF , the gate resistance used (internal + external) is , and the gate voltage, , is 17 V .

Note: Eq. 9 is an aid for simplifying explanations for the reader. The can be obtained directly from this presented model, which also accounts for the influence of parasitic inductances in the gate loop.

Applying Eq. 9 for and gives a switching time difference of 1.87 ns . From observation and consideration, for ideally in-sync gate drivers, as modelled, the time difference calculated above should hold independent of the number of devices are paralleled.

Fig. 3. (a) Turn-OFF and (b) TurnON plots from the experiment and model. , and the synchronisation mismatch between the gate signals of the DUTs is included in the model.

Fig. 3. (a) Turn-OFF and (b) TurnON plots from the experiment and model. , and the synchronisation mismatch between the gate signals of the DUTs is included in the model.

Fig. 4. (a) and (b) - Turn-OFF for 4 and 8 paralleled DUTs, respectively. (c) and (d) - Turn-ON for 4 and 8 paralleled DUTs, respectively. 1 V mismatch in for four devices in parallel conducting 16 A total load current, and eight devices in parallel conducting 32 A total load current. The signals for these simulation results are synchronised.

Fig. 4. (a) and (b) - Turn-OFF for 4 and 8 paralleled DUTs, respectively. (c) and (d) - Turn-ON for 4 and 8 paralleled DUTs, respectively. 1 V mismatch in for four devices in parallel conducting 16 A total load current, and eight devices in parallel conducting 32 A total load current. The signals for these simulation results are synchronised.

Fig. 5. Turn-OFF ((a) and (c)) and Turn-ON ((b) and (d)) simulation plots showing the current commutation between devices for higher current ( per DUT) - device rating is 11.5 A (C3M0280090D). One of the DUTs is set at 1 V lower .

Fig. 5. Turn-OFF ((a) and (c)) and Turn-ON ((b) and (d)) simulation plots showing the current commutation between devices for higher current ( per DUT) - device rating is 11.5 A (C3M0280090D). One of the DUTs is set at 1 V lower .

Note: some of the colours are not visible in the plots because of overlapping lines. To limit the size of the legend, one colour has been used to specify all the lines that overlap due to identical behaviour.

A delay due to mismatch of 0 to 2 V will correspond to a minimal period- approximately 13 ns (calculated as 1.87 ns for the DUTs tested and modelled above). For a short period of 1-3 ns, the current rise or fall of unsynchronised DUTs will be minimal and would therefore not cause much disparity of current sharing.

A serious reliability issue can arise when mismatch is combined with gate driver unsynchronisation. Both these combined could produce a switching difference of more than 10 ns . For switching time difference , a device turning on too early or turning off slightly later will temporarily conduct a significant proportion of the total current through the branch of the parallel devices being measured, as demonstrated in Fig. 6. More devices in parallel mean a total load current which is likely to be much higher than the current rating of one FET. Hence, more current would be conducted by the one device that switches, either too early during turn-ON or too late during turn-OFF, if the shift of the unsynchronised gate signal is negative or positive, respectively. For repetitive switching this could lead to the failure of the mismatched DUT. One device of a paralleled branch failing would then trigger a cascading failure effect of the whole branch because more power gets dissipated by the remaining FETs of the branch, leading to higher junction temperatures for each remaining FET. Therefore, gate synchronisation becomes the main concern to ensure the reliability of branches of parallel-connected SiC MOSFETs under inductive load (unless if the devices switch slowly due to high gate resistance or high input capacitance), especially when the branch is configured of many paralleled devices (10s of SiC MOSFETs).

Fig. 6. The turn-OFF (a-d) and turn-ON (e-h) simulation plots of 4 parallel-connected DUTs, where 1 DUT is shifted by either 20 ns or 50 ns to produce unsynchronised gate switching of the branch.

Fig. 6. The turn-OFF (a-d) and turn-ON (e-h) simulation plots of 4 parallel-connected DUTs, where 1 DUT is shifted by either 20 ns or 50 ns to produce unsynchronised gate switching of the branch.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.533.pdf

This paper presents an accurate model for predicting the current sharing of parallel-connected MOSFETs under inductive load. The model can account for and gate drive signal mismatch between parallel devices. A comparison of experimental and simulation results with difference and unsynchronised gate signals is used to verify the model. Further simulations show that mismatch with perfect gate synchronisation does not cause much difference in current sharing between groups of four and eight parallel-connected of the MOSFETs tested for this paper. It is not a reliability concern due to the insignificant switching time difference caused by the mismatch. However, mismatch combined with gate un-synchronisation could produce a greater than 10 ns mismatch. As the total current far exceeds the rating of a single MOSFET (more parallel DUTs), 10 ns or more gate driver pulse mismatch can cause one DUT to conduct current beyond its limit, leading to a subsequent device and branch failure.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.533.pdf

R. Wu, S. Mendy, J. O. Gonzalez, S. Jahdi and O. Alatise, "Current Sharing of Parallel SiC MOSFETs under Short Circuit Conditions," 2021 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe), 2021, pp. 1-9.

R. Wu, S. Mendy, N. Agbo, J. Ortiz Gonzalez, S. Jahdi, and O. Alatise. 2021. "Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions" Energies 14, no. 20: 6834

R. Wu, S. N. Agbo, S. Mendy, E. Bashar, S. Jahdi, O. Gonzalez, et al., "Measurement and simulation of short circuit current sharing under parallel connection: SiC MOSFETs and SiC Cascode JFETs," Microelectronics Reliability, vol. 126,p. 114271, 2021

J. Hu et al., "Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS," in IEEE Transactions on Industrial Electronics, vol. 63, no. 4, pp. 2092-2102, April 2016, doi: 10.1109/TIE.2015.2500187.

J. Hu, O. Alatise, J. A. O. González, R. Bonyadi, L. Ran and P. A. Mawby, "The Effect of Electrothermal Nonuniformities on Parallel Connected SiC Power Devices Under Unclamped and Clamped Inductive Switching," in IEEE Transactions on Power Electronics, vol. 31, no. 6, pp. 4526-4535, June 2016, doi: 10.1109/TPEL.2015.2477831.

2016. Power MOSFET Basics: Understanding Gate Charge and Using it to Assess Switching Performance. [ebook] Vishay, pp.1-2. Available at: [Accessed 18 October 2021]

Li, W., Mao, S., Yang, S., Ding, Y. and Zeng, K., 2021. "Modeling and Analysis of the Switching Characteristics Difference for Paralleling SiC MOSFETs in Multichip Power Modules". 2021 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia). [online] Wuhan: IEEE, pp.217,222.

Li, H., Munk-Nielsen, S., Wang, X., Maheshwari, R., Beczkowski, S., Uhrenfeldt, C. and Franke, W., 2015. "Influence of Device and Circuit Mismatch on Paralleling Silicon Carbide MOSFETs". IEEE Transactions on Power Electronics ( Volume: 31, Issue: 1, Jan. 2016). [online] IEEE, pp.621-633

Wei, Y., Woldegiorgis, D., Du, X., Machireddy, V. and Mantooth, A., 2021. "Comprehensive Investigations on Paralleling Operation of SiC MOSFETs based on Subbcircuit Model in MATLAB/SIMULINK". 2021 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia). [online] Wuhan: IEEE, p. 176.

M'Sirdi, Nacer et al. (2019). State Space Models for Power SiC MOSFET: ICEERE 2018.

M. Jin et al. "A Temperature-Dependent SiC MOSFET Modeling Method Based on MATLAB/Simulink," in IEEE Access, vol. 6, pp. 4497-4505, 2018

H. Linewih and S. Dimitrijev, "Channel-carrier mobility parameters for 4H SiC MOSFETs," 2002, pp. 425-430 vol. 2

J. O. Gonzalez, R. Wu, S. Jahdi and O. Alatise, "Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs," in IEEE Transactions on Industrial Electronics, vol. 67, no. 9, pp. 7375-7385, Sept. 2020, doi: 10.1109/TIE.2019.2945299.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 539-543

doi: 10.4028/p-u88313

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-22

Accepted:
2022-03-17

Online:
2022-05-31

Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

The original version of this paper is available on https://www.scientific.net/MSF.1062.539.pdf

M.T. Rahimo , I. Nistor , D. Green

mqSemi AG, Zug, CH-6300, Switzerland

Silvaco Europe Ltd., St Ives, PE27 5JL, United Kingdom

a* munaf.rahimo@mqsemi.com,

Keywords: SiC MOSFET, static behavior, switching behavior

Abstract

This paper presents a Singular Point Source MOS (S-MOS) cell concept suitable for SiC MOSFETs targeting low conduction losses, low switching losses and high robustness. The S-MOS concept differs from standard Planar or Trench MOS cells in the manner by which the total channel width per device area is determined. For the proof of concept and device electrical performance evaluation, the paper will provide 2D and 3D TCAD simulations results for 1200 V SiC MOSFETs including the S-MOS and reference planar and trench structures.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.539.pdf

MOS cell process and design platforms were developed over the years for enabling advanced power devices such as the power MOSFET and IGBT. These devices employ either planar or trench gate MOS cell concepts arranged in cellular or linear layout designs. The advances made on Silicon based MOS devices have provided a strong base for developing SiC power MOSFETs [1] where higher cell packing densities through cell miniaturisation is essential. Therefore, in recent years advanced 3D design concepts similar to the low voltage lateral FINFET [2] have been proposed for improving the device static and dynamic characteristics [3][4]. 3D solutions rely on multidimensional channel arrangements to increase the cell packing densities for lower values.

Following the above trend, a new 3D MOS concept referred to as the "Singular point source" (SMOS) was presented recently and demonstrated using 3D-TCAD simulations for a 1200 V Silicon IGBT structure [5]. In this paper, the S-MOS concept was adapted and implemented on a 1200 V SiC MOSFET structure by means of 3D-TCAD simulations using Silvaco Victory Process and Device Software. A full set of static and dynamic results are presented for comparing the S-MOS with reference SiC MOSFET 2D structures employing Planar and Trench MOS cell designs.

Device Concept and Structure

The original version of this paper is available on https://www.scientific.net/MSF.1062.539.pdf

For planar or trench MOS cells as shown in Fig. 1a and Fig 1b respectively, the channel width is defined as the total peripheral distance around the source which also depend on the geometrical shape of the MOS cells arrangement (i.e., linear or cellular layout design) [6]. On the other hand, the channel width for the S-MOS concept shown in Fig. 1c is defined by a smallscale dimension of the N++ source and junction length. By positioning this small geometrical feature on a trench side-wall, a predetermined unit channel length is provided. Fig. 1 highlights the critical cell dimensions for all designs along with a 2D top view descriptive cross section. For the S-MOS, a cross section at the trench side-wall along the cutline is also depicted. The S-MOS trenches are positioned orthogonally to the source contact stripe while vertical trench channels are prevented from forming on the inner trench side-walls by extending a highly doped P++ region under the N++ source. Therefore, the S-MOS provides only a singular point source reference for defining as in the top view (i.e., not a line as for reference planar or trench MOS cells). From this singular point, the junction depth is defined after implantation and annealing of the source and regions. Despite the lack of diffusion mechanism in SiC compared to Silicon, we can still obtain a in the range of . By approximating
the shape of the N++/P junction to a "quarter of a circle", a around could be reached for a single trench side-wall. is practically slightly longer if calculated at the peak doping position which is deeper than . The total for a given chip is the sum of all on all trench side-walls. This is adequate when implementing small mesa dimensions and different design variants. Based on this approach, the singular point source will allow more cell packing with miniaturised cell dimensions in future designs to increase the channel density in the third dimension and thus reduce the on-state conduction losses of the device.

Fig. 1 Source MOS cell concepts including planar MOS (a), Trench MOS (b) and S-MOS (c). Blue arrows at N++ source represent the channel path (S-MOS cell does not require a JFET region).

Fig. 1. Source MOS cell concepts including planar MOS (a), Trench MOS (b) and S-MOS (c). Blue arrows at N++ source represent the channel path (S-MOS cell does not require a JFET region).

1200 V SiC MOSFET Simulation Models

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The 1200 V S-MOS SiC MOSFET functionality was demonstrated using 3D-TCAD simulations and compared to reference 2D planar and trench models using linear cell layout designs. For this investigation, 3x S-MOS variants, 2x trench MOS variants and 1x planar MOS variant with a JFET region were modelled with different pitch widths as outlined in Table (1) along with other key dimensions. The new design can be realized using standard manufacturing processes since the can be defined with modern processing capabilities while contain no central feature (i.e., contact) to limit the design window. No P-regions were employed at trench bottom corners for these simulations. All devices had a total thickness - drift doping drain depth and maximum doping . All trenches had a width and depth and the gate oxide thickness . The doping profile was adjusted to obtain the required saturation current and blocking capability. The doping concentration for the source and base and respectively.

Different field mobility models were available leading to different static performance with respect to the and threshold voltage . The selected model "fldmob" for all devices led to values close to the expected performance albeit with high levels. Nevertheless, a qualitative assessment of the S-MOS compared to reference devices was achieved. It is important to note that a planar design can be designed with smaller dimensions using cellular layout designs to achieve even lower conduction losses than what was achieved with the presented simulation results.

Table 1 Critical MOS cell dimension for the different simulation models.

Table (1) | μm | S-MOS(A) | S-MOS(B) | S-MOS(C) | Trench(A) | Trench(B) | Planar
Pitch | μm | 1.6 | 2.4 | 4 | 1.6 | 2 | 6
Wcell | μm | 1 | 1.6 | 1.6 |  |  | 1.8
Wmesa | μm |  |  |  | 0.8 | 1.2 |
WmesaX | μm | 0.2 | 0.2 | 0.2 |  |  |
WmesaY | μm | 0.8 | 1 | 1 |  |  |
LT | μm | 0.4 | 0.7 | 1.5 |  |  |

Results and Discussion

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Static and mixed mode inductive load dynamic simulations were carried for all device structures which were scaled for a total active area of . All reference and S-MOS structures had avalanche blocking around 1400 V and threshold voltage levels were at . The values were obviously too high compared to real devices. The output IV characteristics are shown in Fig. 2 up to 600 V and a zoom-in up to 1 V at and . All S-MOS versions provide low levels similar to trench cells around at. In addition, the S-MOS provides a flat saturation current compared to reference models. The increasing saturation current is normally linked to short channel effects for the reference planar and trench structures. Therefore, the S-MOS behaviour requires more study to understand the effect of the new cell concept. Fig. 3 show the SMOS (A) net doping and electron concentration at highlighting the device conduction mode as described above. The figure also shows that the base region placed under the source ensures no vertical inversion channel forms on the inner trench walls as explained earlier.

Fig. 21200 V SiC MOSFET output curves, .

Fig. 21200. V SiC MOSFET output curves, .

Fig. 3 S-MOS (A) 3D model showing device sections, corresponding net doping and electron concentration.

Fig. 3. S-MOS (A) 3D model showing device sections, corresponding net doping and electron concentration.

The inductive switching behaviour is shown in Fig. 4 for nominal conditions , , stray inductance ). The turn-on di/dt was set at similar levels with different gate resistors. The faster dv/dt levels for the S-MOS led to lower losses at lower di/dt than for reference devices as shown in Fig. 5 . All devices show turn-off losses around . The S-MOS provides lower overall losses compared to reference devices as shown in Table (2).

Finally, the short circuit current was simulated for all devices at . Fig. 6 shows the SMOS(C) short circuit current and voltage waveforms and the corresponding net doping and total current density at maximum short circuit current. The figure illustrates the positioning of the
channel on the trench side-wall and the fact that the only available for the S-MOS concept is located in that space. This approach could be the basis for providing new designs having less short channel effects and improved trade-off between conduction losses and short circuit performance and try to mitigate some of the short circuit related limitations associated with SiC MOSFETs.

Table 2 Static and dynamic losses for all devices at under comparable switching conditions.

Table (2) | mΩ-cm² | S-MOS(A) | S-MOS(B) | S-MOS(C) | Trench(A) | Trench(B) | Planar
Rdson | mΩ-cm² | 2.8 | 2.9 | 3 | 2.7 | 3 | 5
Esw | mJ | 12.07 | 15.20 | 17.22 | 20.11 | 18.28 | 15.93

Fig. 41200 V SiC MOSFET nominal switching curves ( ).

Fig. 41200. V SiC MOSFET nominal switching curves ( ).

Fig. 5 Eon vs. and .

Fig. 5. Eon vs. and .

Fig. 61200 V S-MOS(C) SiC MOSFET Short Circuit at and corresponding net doping for reference and total current density at maximum short circuit current at the indicated point on the current waveform.

Fig. 61200. V S-MOS(C) SiC MOSFET Short Circuit at and corresponding net doping for reference and total current density at maximum short circuit current at the indicated point on the current waveform.

Summary

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A new SiC MOSFET based on the S-MOS cell concept was presented showing an alternative method to define and control the device channel width. 3D-TCAD simulation results confirm the functionality of the S-MOS concept compared to reference planar and trench SiC MOSFETs rated at 1200 V . Design optimization is now required since the performance shows promising behaviour.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.539.pdf

M.T. Rahimo "Performance evaluation and expected challenges of Silicon Carbide power MOSFETs for high voltage applications" Mat. Science Forum, Vol. 897, pp. 649-654, May 2017.

D. Hisamoto, E. Takeda "A fully depleted lean-channel transistor (DELTA). A novel vertical ultra-thin SOI MOSFET", IEDM 1989, NewYork, pp 833-836.

N.Tega, H. Yoshimoto, D. Hisamoto, N. Watanabe, H. Shimizu, S. Sato, Y. Mori, T. Ishigaki, M. Matsumura, K. Konishi, K. Kobayashi, T. Mine, S. Akiyama, R. Fujita, A. Shima, and Y. Shimamoto "Novel trench-etched double-diffused SiC MOS (TED MOS) for overcoming tradeoff between RonA and Qgd", Proc. ISPSD 2015, Hong Kong, China, pp. 81-84.

R. P. Ramamurthy, N. Islam, M. Sampath, D.T. Morisette, J. Cooper "The Tri-Gate MOSFET: A New Vertical Power Transistor in 4H-SiC" Electron Device Letters, Vol. 42, No. 1, Jan. 2021.

M.T. Rahimo I. Nistor, D. Green, "Singular Point Source MOS Cell Concept (S-MOS) Implemented on a Narrow Mesa Trench IGBT", Proc. ISPSD 2021, Nagoya, Japan, pp 27-30.

B. J. Baliga, "Fundamentals of Power Semiconductor Devices", New York: Springer, 2008, ISBN 978-0-387-47313-0.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 544-548

doi: 10.4028/p-973n9u

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-02-24

Accepted:
2022-03-17

Online:
2022-05-31

Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

The original version of this paper is available on https://www.scientific.net/MSF.1062.544.pdf

Rosine Coq Germanicus*1a , Kimmo Niskanen , Alain Michez , Niemat Moultif , Wadia Jouha , Olivier Latry , Jerôme Boch , Ulrike Lüders , Antoine D. Touboul

Normandie Univ, Ensicaen, Unicaen, CNRS, CRISMAT, UMR6508, Caen, France

Institut d'Electronique et des Systèmes, UMR5214, University of Montpellier, France

Groupe de Physique des Materiaux, CNRS, UMR6634, Rouen, France

rosine.germanicus@unicaen.fr, kimmo.h.niskanen@jyu.fi, alain.michez@umontpellier.fr, niemat.moultif0@univ-rouen.fr, jouhaieea@gmail.com, olivier.latry@univ-rouen.fr, antoine.touboul@ies.univ-montp2.fr

Keywords: power MOSFET, silicon carbide (SiC), neutrons, single event burnout (SEB), failure analysis

Abstract

Dealing with electronic devices for high reliability applications in terrestrial environments, neutron-induced Single Event Effects must be investigated. In this paper, the experimental observation of an atmospheric-like neutron-induced Single Event Burnout (SEB) on a packaged commercial SiC power MOSFET is presented after irradiation at ISIS-ChipIr. The effects of the SEB in the electrical properties of the MOSFET are established, and the SiC damaged zone is observed by scanning electron microscopy. Based on this failure analysis at the die level, the distinct stages during the SEB mechanism can be defined. The sensitive volume where the secondary particle deposited enough energy to trigger the SEB mechanism is identified and located inside the SiC n-drift epitaxial layer near the epitaxial layer/substrate junction.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.544.pdf

Dealing with high reliability applications in terrestrial and space environments, such as automotive, train transportation, aeronautics or space applications, the consideration of any failure source is a critical necessity. All environmental constraints must be considered, and in particular atmospheric radiations representing an intense continuous flux, which have been shown to affect the overall reliability of electronic systems. In atmospheric environment, neutron-induced single event effects are known indeed to be a crucial concern for high power device reliability [1]. Under the effect of a primary neutron, nuclear interactions occur within the device with any of the constitutive atoms, producing recoil ions and eventually even the generation of localized currents. These unsuited currents possibly induce a thermal breakdown of power devices and a loss of functionality of the entire system, due to the high internal drain to source electric field. This Single Event Burnout (SEB) destructive mechanism has been investigated for SiC power diodes [2] and SiC power MOSFETs [3,4]. For MOSFETs, investigations focused on the effect of applied drain voltage on SEB sensitivity [5]and device technology [6-8]. Impacts of electrical stress [9] and reverse gate voltage [10] were also evaluated. Some studies estimated the location of the sensitive volume for initiating SEB in SiCMOSFET through numerical simulations [11,12]. Moreover, in this reference [12], the authors study the difference between heavy ion and neutron-induced SEB, showing that in the special case of neutron irradiation the sensitive volume is near the epitaxial-substrate junction. By comparing SiCMOSFET and SiC-PIN diodes, no significant failure rates difference was found against neutron single event effect [4], therefore this study concludes that the SEB mechanisms in SiC-MOSFET is due to the current-induced avalanche in the drift region.

In this work, packaged commercial SiC MOSFETs have been tested under an accelerated atmospheric neutron spectrum to determine their reliability for critical applications. At the die level, failure analysis has been performed in order to provide new insights regarding the physical mechanisms at stake during neutron-induced SEB.

Devices and Test Set-Up

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Device Under Test (DUT)

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The devices under test (DUT's) are commercial vertical planar-gate SiC power MOSFETs in a TO-247 molded packages. For this device, nominal maximum ratings are , from 4 V to and on-resistance is . Electrical characterizations, including and measurements, have been performed before and after irradiation for each device.

To evaluate the irradiation effect, a dedicated test board following the MIL-STD-750E test standard has been designed and fabricated. The test board containing DUTs is placed under the radiation beam while drain and gate voltages are controlled. Source measurement units (SMUs) are used to supply voltages and to measure currents in the control room. The SMUs were controlled and data were collected via Ethernet and USB interfaces. The schematic diagram of the developed irradiation test setup is presented in Fig.1.a). The SiC devices were connected in parallel configuration. For each DUT, a series resistor at the drain was placed in order to limit the total current of the power supply to ensure bias voltage stability across the rest of the non-failed devices. On top of that, a capacitance was placed at the drain of each DUT providing sufficient energy for SEB. Fig.1.b) shows the test board in the irradiation room. During neutron irradiation, ( of the ) and were applied.

Figure 1: a) Schematic of the dedicated test board for irradiation (for 3 devices) and b) picture of the board with SiC MOSFETs.

Figure 1. Figure 1: a) Schematic of the dedicated test board for irradiation (for 3 devices) and b) picture of the board with SiC MOSFETs.

Neutron irradiations facility

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Neutron irradiations were carried out at ChipIr (Chip Irradiation) beamline [13] of the ISIS spallation source at the Rutherford Appleton Laboratory, UK. This beamline is dedicated to accelerated testing of microelectronics under atmospheric-like ultra-fast neutron spectrum. For neutron energies above 10 MeV , the average flux is . The acceleration factor compared to the ground level neutron flux is . For this experiment, devices were irradiated up to a neutron fluence of about .

Results and Discussion

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Experimental results are reported in Fig.2. Fifteen devices, with the same lot number, were irradiated by neutrons. A SEB event was detected by the increase of of the device. The cumulative SEB events is plotted versus the neutron fluence (Fig.2.a). Since the neutron-matter interaction is considered as a stochastic process, as expected, a constant rate increase with time is observed. Moreover, Weibull shape parameter of the neutron induced failure distribution is 0.93 , close to 1 ,
which indicates random failures i.e. constant failure rate over time. After the total fluence of of the irradiated devices were destroyed, thus eight devices of the initial lot. For a device having suffered a SEB, subthreshold and before and after irradiation are represented in Fig.2.b). Electrical characterizations after neutron irradiation show the occurrence of the short circuit between the drain and the source due to the SEB. After neutron irradiation, the exhibits an increase and reaches the compliance limit, implying the loss of voltage blocking capability of the SiC MOSFET structure. On top of that, from response, a low resistance current path from gate to source is measured.

Figure 2: a) Fluences of SEB occurrence during neutrons irradiations, b) and before and after neutron irradiation for a device having suffered a SEB.

Figure 2. Figure 2: a) Fluences of SEB occurrence during neutrons irradiations, b) and before and after neutron irradiation for a device having suffered a SEB.

In order to analyze the SiC MOSFET at the die level and provide electrical local analysis, a crosssectional sample preparation was developed. Since the device is a packaged commercial component (not a device from a bare die without packaging), and to conserve the back-end structure, the sample preparation has been based on a backside opening, followed by the mechanical grinding of the copper heat spread. The SiC die has been thinned (less than thickness) in order to become fully optically transparent. The sample cutting axis was located at the center of the damage observed, through the thin SiC material. Our localization method for this SEB damage is different from the analysis presented in reference [12], where the crack was located from the degradation of top polyimide passivation. In our case no degradation was observable on the front side of the device.

Cross sectional Scanning Electron Microscopy (SEM) views indicate the residual trace induced by the SEB inside the SiC die from the top of the gate (in the metal contact source) to the SiC substrate (Fig.3.a)). Indeed, looking at the failure analysis results, residual deformations, cracks, appearance and shape of the materials allow to propose the following scenario for describing the different steps of the failure mechanism. If the root cause is known to be a nuclear neutron-atom interaction, the SEB can only be initiated by ionizing particles such as recoil ions or secondary atoms created through the primary neutron interaction. A bifurcation shape of the damage inside the SiC material suggests that the secondary particle has deposited enough energy in this sensitive volume (area located in Fig.3.a). Due to the high local electrical field, the impact ionization current is created, and generated electrons and holes respectively flow towards the drain (from the SiC epilayer to the substrate) and the source contacts, surrounding the gate contact. This bifurcation trace is clearly located at the point of maximum impact ionization inside the SiC, which corresponds to the hot spot during the SEB (the point of the highest temperature). Therefore, the starting point of the SEB is thus located in the ndrift epitaxial region below the channel. This experimental observation agrees with the location of the SEB sensitive volume determined by simulations in reference [12]. A zoom of the damage in the gate region is compared with a gate without impact (Fig.3.b)). In the SEM view, after the SEB the gate and interlayer dielectric (ILD) are completely blown up. Due to the SEB, the ILD is cut in two parts and one part is displaced, thrown up into the source metal. This is an evidence of a self-sustained
strongly localized overheating through the impact ionization process and/or the Kirk effect. Once the SEB has resulted in the high drain current state due to the short-circuit between drain and source and an electrical connection of the metal source contact to the drain is created. Like a fire blast, a collateral effect likely related to the thermal expansion of SiC material has been observed, leading to the total contact melting and metal inclusion. As a more global thermal consequence, we also observe the delamination of the epoxy resin of the metal layer.

Figure 3: SEM views of the SiC MOSFET structure after SEB, a) large view where the location of the impact is determined and b ) comparison of two gates regions without and after SEB.

Figure 3. Figure 3: SEM views of the SiC MOSFET structure after SEB, a) large view where the location of the impact is determined and b ) comparison of two gates regions without and after SEB.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.544.pdf

In this paper, the total thermal runaway of a SEB mechanism in a packaged commercial SiC power MOSFET was analyzed by SEM. Damage zone is located by a special backside opening to conserve back-end layer structure. Based on failure analysis, the different steps of the SEB scenario have been elucidated and experimentally proves that the neutron-induced SEB sensitive volume is inside the drift region, near the epitaxial-substrate junction. The analysis of the SEM view clearly reveals the starting point of the SEB located in the epitaxial SiC layer and just under the channel region.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.544.pdf

H. Asai, K. Sugimoto, I. Nashiyama, Y. Iide, K. Shiba, M. Matsuda, Y. Miyazaki, IEEE Transactions on Nuclear Science 59 (2012) 880-885.

T. Shoji, S. Nishida, K. Hamada, H. Tadano, Jpn. J. Appl. Phys. 53 (2014) 04EP03.

D.J. Lichtenwalner, A. Akturk, J. McGarrity, J. Richmond, T. Barbieri, B. Hull, D. Grider, S. Allen, J.W. Palmour, Materials Science Forum (2018).

H. Kono, T. Ohashi, T. Noda, K. Sano, Materials Science Forum (2019).

A. Akturk, R. Wilkins, J. McGarrity, B. Gersey, IEEE Transactions on Nuclear Science 64 (2017) 529-535.

H. Asai, I. Nashiyama, K. Sugimoto, K. Shiba, Y. Sakaide, Y. Ishimaru, Y. Okazaki, K. Noguchi, T. Morimura, IEEE Transactions on Nuclear Science 61 (2014) 3109-3114.

F. Principato, S. Altieri, L. Abbene, F. Pintacuda, Sensors 20 (2020) 3021.

C. Martinella, R.G. Alia, R. Stark, A. Coronetti, C. Cazzaniga, M. Kastriotou, Y. Kadi, R. Gaillard, U. Grossner, A. Javanainen, IEEE Transactions on Nuclear Science 68 (2021) 634641.

K. Niskanen, A.D. Touboul, R.C. Germanicus, A. Michez, A. Javanainen, F. Wrobel, J. Boch, V. Pouget, F. Saigné, IEEE Transactions on Nuclear Science (2020) 1-1.

K. Niskanen, R. Coq Germanicus, A. Michez, F. Wrobel, J. Boch, F. Saigné, A.D. Touboul, IEEE Transactions on Nuclear Science 68 (2021) 1623-1632.

Y. Wang, M. Lin, X.-J. Li, X. Wu, J.-Q. Yang, M.-T. Bao, C.-H. Yu, F. Cao, IEEE Transactions on Electron Devices 66 (2019) 4264-4272.

D.R. Ball, B.D. Sierawski, K.F. Galloway, R.A. Johnson, M.L. Alles, A.L. Sternberg, A.F. Witulski, R.A. Reed, R.D. Schrimpf, A. Javanainen, J.-M. Lauenstein, IEEE Transactions on Nuclear Science 66 (2019) 337-343.

C. Cazzaniga, C.D. Frost, J. Phys.: Conf. Ser. 1021 (2018) 012037.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 549-553

doi: 10.4028/p-ix1o7m

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-03-18

Accepted:
2022-03-19

Online:
2022-05-31

SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

The original version of this paper is available on https://www.scientific.net/MSF.1062.549.pdf

Roman Maloušek , Jan Chochol , Hrishikesh Das , Swapna Sunkari , Joshua Justice , Krister Gumaelius , Jimmy Franchi , Martin Domeij , Fredrik Allerstam , Ryota Wada , and Takashi Kuroi

¹ON Semiconductor, Roznov, Czech Republic;

ON Semiconductor, South Portland, ME, USA;

ON Semiconductor, Kista, Sweden; Nissin Ion Equipment Inc., Kyoto, Japan

roman.malousek@onsemi.com, jan.chochol@onsemi.com, hrishikesh.das@onsemi.com, swapna.sunkari@onsemi.com, joshua.justice@onsemi.com, krister.gumaelius@onsemi.com,

jimmy.franchi@onsemi.com, martin.domeij@onsemi.com, wada_ryota@nissin.co.jp, kkuroi_takashi@nissin.co.jp

Keywords: Silicon Carbide, Superjunction, Charge Balance, Channeled implant, Epitaxy, UIS

Abstract

This work details two approaches with multi-epitaxial growth to create a vertical superjunction structure made of alternating pillars. One approach is a chain of very high energy implants, the other uses a preferred implantation direction to achieve a channeled profile. The manufactured devices show a breakdown voltage of 1000 V for channeled, two-step epi with a total thickness of for regular high energy implants using three epi steps of a total thickness of . The measured was for dies with size . UIS and temperature measurement show reliable performance. The channeled implant looks favorable to reduce the number of process steps needed to create an efficient superjunction structure.

Introduction

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The challenge in power semiconductor manufacturing is always to balance the tradeoffs of cost, blocking voltage and forward resistance. In unipolar vertical devices, switching to Silicon Carbide from Silicon already reduces the needed epitaxial thickness of the device, greatly reducing the on-state resistance. The superjunction concept [1] can push this even further by decreasing the thickness and resistance for the same voltage rating. The superjunction is a charge balance structure, made of narrow, highly doped alternating p-n regions in the epitaxial layer, as shown in Fig. 1 a. The superjunction region becomes completely depleted at a high blocking voltage and provides a trapezoidal electric field distribution, leading to higher breakdown voltage (see Fig. 1). The high ndoping enabled by the superjunction concept reduces the on-state resistance. There are multiple ways to create a superjunction structure, with various levels of complexity and equipment needed [2]. In this study, a process is demonstrated relying on vertical pillars made by multi-step epitaxial growth and two implantation methods - very high energy implant chain (VHE) and channeled implant. Devices made by both methods are electrically characterized and compared.

Fabrication Process

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The superjunction diodes are made on heavily Nitrogen ( N ) doped SiC wafers. In the first step, a buffer layer ( , 1e17 , nitrogen) is grown on the substrate, along with a first layer for the pillars. In the case of VHE implant, the layer is lightly n-doped and implanted by a chain of energy and doses with N ions to create a desired concentration. Then the layer is masked with of photoresist, and a similar chain of aluminum (Al) is implanted, with double the total dose of the nitrogen implant to create the p-pillar. The epi and implantation steps are repeated until the desired pillar thickness of is achieved. In the channeled implant scenario, the epi layer was grown with the targeted nitrogen concentration of and Al was implanted along the [0001] crystal
direction to create a deep and flat doping profile [3]. The default pillar pitch is . A process flow of the process is shown in Figure 2 and simulated profiles are shown in Figure 3. For the VHE experiment, the epi and implant process are repeated three times for a total thickness of of charge balance area. The channeled experiment requires only two epi-implant steps with a total thickness of .

Figure 1. Schematic illustration of the Superjunction concept. Left: Classic design of junction barrier Schottky diode. Right: Superjunction with vertical pillars. The charge balance allows the electric field in reverse to spread in trapezoidal fashion, increasing the breakdown voltage.

Figure 1. Figure 1. Schematic illustration of the Superjunction concept. Left: Classic design of junction barrier Schottky diode. Right: Superjunction with vertical pillars. The charge balance allows the electric field in reverse to spread in trapezoidal fashion, increasing the breakdown voltage.

Figure 2. Schematic flow of the multi-epitaxial process. Left: Process with high energy implants. Right: Process with channelled Al implant.

Epitaxial growth techniques were developed to fabricate both highly doped and lightly doped layers. The pre-growth and initial growth conditions were optimized to have minimal pre-etch and an abrupt transition layer. In the case of doped epitaxial layers, a continuous doping profile was verified by SIMS.

Figure 3. Simulation of the implanted profiles after all epi steps, model is based on internal SIMS data. Values are normalized to the maximum in channelled experiment.

Figure 2. Figure 3. Simulation of the implanted profiles after all epi steps, model is based on internal SIMS data. Values are normalized to the maximum in channelled experiment.

Figure 4. Left: Schematic of the device layout. Green stripes show the p-type implanted regions defined by the pillar mask. Right: Photoluminescence photo of the device in breakdown condition. The current is concentrated in the active area, showing robust design of the junction termination.

Figure 3. Figure 4. Left: Schematic of the device layout. Green stripes show the p-type implanted regions defined by the pillar mask. Right: Photoluminescence photo of the device in breakdown condition. The current is concentrated in the active area, showing robust design of the junction termination.

The p-pillar was finalized with a high dose Al implant. A Ti/TiN barrier and aluminum layer was deposited over the active structure and annealed at . The high doped region on the p-pillar forms a Schottky contact while the n-pillar forms a Schottky one. The implants were activated by annealing at high temperature prior to formation of the metal contacts. The wafer was thinned to 200 um and the backside Ni contact was laser annealed.

Device Design. The superjunction diode was designed with stripes along the [ ] direction to avoid the shadowing of the implant with photoresist during the angled implantation needed for channeling. The charge balance was controlled by varying the p-pillar mask width. The JTE termination was designed to distribute the avalanche current homogenously in the active region to achieve a robust device in unclamped inductive switching. The design was verified by photoluminescence measurements and shows uniform emission in the active area at the breakdown voltage. The schematic and the measurement are shown in Figure 4. Both small ( ) and big ( ) dies were manufactured.

Electrical Results. The devices were subject to several tests, both on wafer as well as in package.
Breakdown voltage and Rsp. Wafer level tests were performed on devices near the wafer top, center and bottom, as the epi thickness and concentration vary across the wafer and both parameters affect the resistance and breakdown voltage. The measurements are shown in Figure 5 (a-c). Both approaches worked as intended, with similar values of BV per micrometer of charge balance structure. The VHE approach showed a higher tolerance to the thickness and concentration variation of the epitaxial layers, at the expense of needing more layers to get the desired BV. The variation of the p-pillar width and the implanted dose illustrate the charge balance and its sensitivity. It is apparent by the BV that the channeled experiment was shown to have slightly higher Al concentration in the dose and pillar ratio 1, while the VHE had Al underdosed. The rise of Rsp values for wider ppillars and higher Al doses was caused by the pinching of the n -pillar, which is also the width of the Schottky contact. The specific on-resistance Rsp (extracted in the linear regime) was measured for smaller dies and is thus affected by current spreading. The actual values of Rsp for the device is shown in the temperature dependent analysis.

Figure 5. (a) Results of Breakdown voltage with dependence on type of p -pillar, respective dose and pillar-to-pillar ratio. Inset shows the location of measured devices across the wafer. (b) Rsp values on small devices. (c) BV normalized to the pillar depth. This shows that both approaches have similar characteristics and the BV in mainly determined by the pillar depth. (d) Results of Eas (avalanche energy in unclamped inductive switching, single pulse) on packaged devices.

Figure 4. Figure 5. (a) Results of Breakdown voltage with dependence on type of p -pillar, respective dose and pillar-to-pillar ratio. Inset shows the location of measured devices across the wafer. (b) Rsp values on small devices. (c) BV normalized to the pillar depth. This shows that both approaches have similar characteristics and the BV in mainly determined by the pillar depth. (d) Results of Eas (avalanche energy in unclamped inductive switching, single pulse) on packaged devices.

Unclamped Inductive Switching (UIS). Samples from both concepts underwent UIS to verify device ruggedness. At least 3 samples were measured for each design with an inductance of 1 mH . The maximum sustained energy Eas for the devices with VHE implant was 121 mJ whereas the
channeled implant only sustained 41 mJ (mean values), shown in Figure 5 (d). Based on photoluminescence measurement, the device with VHE implant has avalanche concentrated at the top of the edge of the active region, shown in Figure 6. The good UIS result can be explained by the fact that the avalanche distributes in whole active region at a higher current level. On the other hand, the device with channeled implant has avalanche distributed in the active region but significantly lower UIS capability was achieved. Spots with localized avalanche were observed for all samples and these may be related to local barrier reduction due to material defects. As suggested in [4], the VHE data for the die are close to expectation.
On-state resistance and Breakdown voltage over temperature. Eight devices with the same pillar width and implant conditions were packaged. The data in Figure 7, show that the Rsp values rise with a quadratic dependence on temperature. At lower temperatures, the concentration of ionized dopants decreases, hence Rsp rises. The increase in breakdown voltage with elevated temperature is attributed to increased phonon scattering and therefore a higher electric field is needed to induce impact ionization. [4].

Figure 6. Photoluminescence measurement in UIS. Left: VHE, Right: Channeled

Figure 5. Figure 6. Photoluminescence measurement in UIS. Left: VHE, Right: Channeled

Figure 7. Results of BV and Rsp on large devices at various temperatures

Figure 6. Figure 7. Results of BV and Rsp on large devices at various temperatures

Process Complexity. The multi-epitaxial growth with channeled implant mitigates the risk of introducing additional crystal defects during epi growth. The implantation energies require no special masking process, as the energies are low ( ), yet the channeling provides deep concentration profiles and this reduces the number of epi steps needed.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.549.pdf

A SiC Superjunction diode concept is presented using alternating pillars made by multiepitaxial growth of layers and ion implantation. The implantation is either a chain of high energy implants or medium energy channeled implants. The electrical wafer level measurements show BV of about 210 V per of pillar depth and Rsp of . UIS measurement shows good avalanche robustness of the VHE approach, while the channeled approach has room for improvement. The device follows a predictable temperature behavior, with increase of both Rsp and BV at elevated temperature. Overall, the use of channeled implant offers a reduction of the number of process steps needed to fabricate the structure and makes for a viable alternative to a traditional device architecture.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.549.pdf

Udrea, F., et al. (2017). Superjunction Power Devices, History, Development, and Future Prospects., IEEE T. Electron Dev., 64(3), 720-734.

Kosugi, R., et al. (2014). First experimental demonstration of SiC super-junction (SJ) structure by multi-epitaxial growth method, 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), pp. 346-349

Das, H. et. al. (2020), P-Type and N-Type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication, ECS Transactions, 98 (6) 119-124 (2020)

Konstantinov, A., et al. (2018). Investigation of avalanche ruggedness of 650 V Schottkybarrier rectifiers. Solid State Electron. 147 (2018) 51-57

Nida, S., Grossner, U., (2019) High-Temperature Impact-Ionization Model for 4H-SiC, IEEE T. electron Dev., vol. 66, no. 4

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 554-559

doi: 10.4028/p-nc73ur

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-24

Accepted:
2022-03-17

Online:
2022-05-31

Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

The original version of this paper is available on https://www.scientific.net/MSF.1062.554.pdf

Sara Kochoska , Martin Domeij2,b, Swapna Sunkari , Joshua Justice , Hrishikesh Das , Thanh-Toan Pham , Jimmy Franchi , Sotirios Maslougkas Hojung Lee , Xue Qing Hu , Thomas Neyer

onsemi, Einsteinring 28, 85609 Aschheim, Germany

onsemi, Isafjordsgatan 32C, 16440 Kista, Sweden

onsemi, 333 Western Avenue, 04106-1705 Maine, USA

onsemi, Ltd. 55, Pyeongcheon-ro 850, Bucheon-si, Gyeonggi-do, Korea

sara.kochoska@onsemi.com, martin.domeij@onsemi.com, swapna.sunkari@onsemi.com, joshua.justice@onsemi.com, hrishikesh.das@onsemi.com, thanh-toan.pham@onsemi.com, gjimmy.franchi@onsemi.com, sotirios.maslougkas@onsemi.com, hojung.lee@onsemi.com, xueqing.hu@onsemi.com, thomas.neyer@onsemi.com

Keywords: bipolar degradation, Basal Plane Dislocations, stacking fault, SiC, body diode stress

Abstract

In this work, body diode stress has been carried out for planar SiC MOSFETs. The epitaxial wafers were mapped with Infra-Red photoluminescence (IR-PL) to determine and localize the exact number of basal plane dislocations present in the drift layers of each die. The SiC MOSFETs were then packaged in groups with individual BPD counts in different bins ranging from 0 up to more than 30 per device. Pulsed body diode measurements with high currents of (about ) were then performed with electrical characterization before and after to check for drift in key electrical parameters. Significantly increased was found after high current stress from about 300 A for devices with BPDs. A physical analysis of the degraded devices by backside electroluminescence show the presence of several trapezoid-shaped patterns indicating the occurrence of bipolar degradation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.554.pdf

Bipolar degradation by body diode stress [1] has mainly been studied in SiC MOSFETs for high voltages such as 3.3 kV where it has been found to cause significant increase for some devices [23]. For lower voltage classes like 1200 V , bipolar degradation is expected to have less influence because smaller chip areas will be affected by each stacking fault expansion event. Fig 1. shows drift on . average BPD per die for and 1700 V SiC MOSFETs after body diode stress with a DC current of 15 A corresponding to a quite low current density of [4]. Here, devices without BPDs show no drift and the shift clearly increases with BPD count. Inspired by these results, a further analysis has been done in this work by stressing the body diode in pulsed mode with very

Fig. 1. drift in percentage after body diode stress for MOSFETs in dependance of voltage class and BPDs per die. [4]

Fig. 1. drift in percentage after body diode stress for MOSFETs in dependance of voltage class and BPDs per die. [4]

The BPDs in the epitaxial layers were detected using the IR-PL channel of a SICA88. To obtain a higher density of BPDs in production dies and gauge their effect layers wafers were also grown skipping the BPD converting layer. The exact dimensions and occurrence of each BPD was aligned to the final production die. From this various passing production die were inked into various bins/groups depending on the count of BPDs in each die.

Testing Procedure and Setup Description

The original version of this paper is available on https://www.scientific.net/MSF.1062.554.pdf

Fig. 2 shows the approach of testing the SiC MOSFETs. The samples were electrically characterized before and after stressing by using the Keysight's B1505A Power Device Analyzer. The measured parameters are , . The pulsed body diode stress was performed using a special surge current tester, which can provide currents well above 1 kA and is limited only by the system voltage and the DUT voltage drop. The measurements were all performed at ambient temperature. Fig. 3 shows transient measured forward voltage drop and current during a typical almost square-shaped Id pulse using a measurement frequency of 100 Hz . The tester uses an arbitrary voltage signal,

Fig. 2. Test procedure for bipolar degradation

Fig. 2. Test procedure for bipolar degradation

which enables to create the desired current pulse shape. There is a moderate overshoot due to parasitic inductance, and thereafter shows a small gradual decrease that may be the result of an increasing carrier plasma level due to a temperature increase by self-heating. After the post-characterization of the samples, some of them were sent for a package lead-frame removal to enable back-sided electroluminescence analysis.

Fig. 3. Transient measured body diode forward voltage drop and current during pulsed current measurements with 250,300 and 350 A and .

Fig. 3. Transient measured body diode forward voltage drop and current during pulsed current measurements with 250,300 and 350 A and .

Electrical Analysis after Body Diode Stress for Devices with Different Number of BPDs

Fig. 4. Drift in and vs. BPD count after body diode stress of SiC MOSFETs with 1 million long pulses vs. stress current.

Fig. 4. Drift in and vs. BPD count after body diode stress of SiC MOSFETs with 1 million long pulses vs. stress current.

In the following analysis, results are presented for SiC MOSFETs. There are six groups with different numbers of BPDs per device. Fig. 4 shows the drift in and vs. BPD count after 1 million pulses of body diode stress for different stress currents. The drift in and follow a similar trend with typical drift after body diode stress increasing with the BPD count, but also a significant sample to sample variation for each BPD count group. The large sample to sample variation and the significant shift that can occur for a sample with 1 BPD suggests that the observed shifts are not connected only to the individual BPD count in the epi-layer but may also be influenced by BPDs in the border region between substrate and epi (BPDs in this region cannot be detected in the UVPL analysis). The shifts in are most significant with the largest increase being close to .
The shift vs. stress current for the devices with 1 BPD or more BPDs, illustrates the strong current acceleration of the shift, an effect which is expected since the carrier plasma level will depend on the current density. No significant shifts were found for other parameters such as threshold voltage and breakdown voltage. Fig. 5 shows the drift vs. amount of pulses for a device with 0 BPD, 1 BPD and more than 30 BPDs, where drift does not show any saturation for the devices with BPDs. The results illustrate the usefulness of BPD mapping for predicting the risk for drift after body diode stress and show the stability of zero BPD die at the high stress current of 350 A ( ).

Fig. drift vs. amount of pulses for a device with and more than 30 BPDs .

Figure 5. Fig. drift vs. amount of pulses for a device with and more than 30 BPDs .

Fig. 6. Electroluminescence analysis on 1700 V SiC MOSFETs after body diode stress at very high current density with drift of: a and c) above .

Fig. 6. Electroluminescence analysis on 1700 V SiC MOSFETs after body diode stress at very high current density with drift of: a and c) above .

Fig. 6 shows Electroluminescence (EL) images captured from the backside for previously body diode stressed SiC MOSFETs during body diode forward bias with and . EL patterns can be seen in parts of the chip area where lead frame and solder was removed by mechanical polishing. Triangularly shaped and trapezoidal shaped stacking faults can be observed and there is a clear trend between observed increase in of and after body diode stress and total size of dark areas in EL. The same trend was observed also for the other body diode stressed samples in agreement with bipolar degradation causing creation and expansion of SSF (triangles and SSF bars). No specific features were seen in EL for samples with zero drift.

Simulation Analysis and Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.554.pdf

Forward conduction of the 1700 V SiC MOSFET body diode was simulated in Sentaurus using doping dependent carrier lifetime with in the n-epi and in the p-implanted and the substrate regions to match the measured and simulated forward voltage drop. The cross-section plot in Fig. 7 shows that the hole density in the n-epi region with looks sufficiently large to cause propagation of a triangularly shaped Shockley-type stacking fault from a BPD in the n -epi, a result in line with the correlation between small increase and epi BPD count in Fig. 1. In case of the high current density of the hole density has increased more than 10x in the n-epi and has reached a level in the range in the border region between epi and substrate. The finding of large trapezoidal features in EL after body diode stress at this high current density is likely caused by bar-shaped Shockley-type stacking faults caused by carrier recombination in the epi-substrate border region where most BPDs are converted to threading edge dislocations [5].

Fig. 7. Simulated hole density in vertical cross-section with and using .

Fig. 7. Simulated hole density in vertical cross-section with and using .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.554.pdf

In this paper, individual mapping of BPDs in SiC MOSFET dies was performed to enable correlation of drift after body diode stress with the number of BPDs in the devices.

From this analysis, there is a clear trend that the and drift after high current density body diode stress increases with the number of BPDs in a device. Also, by limiting the stress current densities as a function of the number of BPDs, increase of can be prevented or reduced to a very low level.

On the other hand, if the SiC MOSFETs with are being stressed at extremely high current densities , a significant degradation of can still occur. Therefore, the maximum currents should be accordingly limited to prevent degradation. For devices with 0 BPDs 350 A ( ) was observed as a threshold current to trigger bipolar significant drift and this threshold current density was found to decrease with the number of BPDs per die.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.554.pdf

T. Kimoto et. al., "Understanding and Reduction of Degradation Phenomena in SiC Power Devices", 2017 IEEE International Reliability Physics Symposium, Monterey CA, USA

R. Fujita et. al., "Failure of Switching Operation of SiC-MOSFETs and Effects of Stacking Faults on Safe Operation Area", IEEE Transactions on Electron Devices, 65, nr. 10, p. 4448, 2018.

T. Ishigaki et. al., "Analysis of Degradation Phenomena in Bipolar Degradation Screening Process for SiC-MOSFETs" p. 259, Proc. of the ISPSD, May 19-23, 2019 Shanghai, China

T. Neyer et. al., "Is there a perfect SiC MOSFETs Device on an imperfect crystal?", 2021 IEE International Reliability Physics Symposium (IRPS)

A. Ijima et. al., "Estimation of the critical condition for expansion/contraction of single Shockley stacking faults in 4H-SiC PiN diodes", Applied Physics Letters, Vol. 116, 092105 (2020)

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 560-564

doi: 10.4028/p-18fenn

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-03-15

Accepted:
2022-03-17

Online:
2022-05-31

Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices

The original version of this paper is available on https://www.scientific.net/MSF.1062.560.pdf

Mohamed Torky and T. Paul Chow

¹Rensselaer Polytechnic Institute, Troy, NY 12180, U.S.A.

torkym@rpi.edu, chowt@rpi.edu

Keywords: Superjunction (SJ), effective critical breakdown field, Impact lonization, 2D simulation

Abstract

We determine the effective critical breakdown field for superjunction (SJ) devices and compare it to their conventional counterparts. Also, we investigate its dependence on SJ device structural parameters, such as drift layer thickness ( t ) and pillar width ( W ). In 4H-SiC SJ devices, the effective critical breakdown field was found to be around lower than that of conventional devices owing to their longer ionization paths. In particular, the effective critical electric field varies as and for 4H-SiC SJ and conventional devices respectively but independent of pillar width and doping concentration for high aspect ratio devices ( ).

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.560.pdf

High voltage, vertical superjunction (SJ) power devices, which exhibit a quasi-rectangular field profile, instead of a triangular field profile, at breakdown, offer a better trade-off between breakdown voltage (BV) and specific on-resistance ( ) (ideally, , instead of ) than conventional power devices [1]-[2]. In addition, wide bandgap semiconductors, like , exhibit better pertinent material properties, such as higher critical field and higher thermal conductivity, than silicon. Recently, we have determined the performance limit of devices [3]. However, the dependence of effective critical field on the doping and the drift layer thickness in any semiconductor SJ devices is still unknown. In this paper, the effective critical field for 4H-SiC SJ devices will be determined using a device simulator (Sentaurus), so as to facilitate their BV design.

Device Design

The original version of this paper is available on https://www.scientific.net/MSF.1062.560.pdf

A half unit cell of the DMOS SJ vertical power MOSFET structure is schematically shown in Fig. 1. We simplify the drift region with the idealized PIN diode structure in Fig. 2 and simulate its effective critical field with the drift layer thickness ( t ) ranging from to and pillar widths of , and at the optimized pillar dosage ( ). The impact ionization coefficients in Table 1, used in the simulations, were developed by [4] and the model, the Chynoweth's model, which governs their dependence on the electric field, is shown in Eqs. (1,2).

Table 1. Impact ionization coefficients used in the Sentaurus TCAD [3].

-
An
(cm⁻¹)
Ap
(cm⁻¹)
Bn
(V/cm)
Bp
(V/cm)

Values
8.19×10⁹
4.48×10⁶
3.94×10⁷
1.01×10⁶

Fig. 1. Schematic crosssection of the half unit cell of a vertical SJ DMOS FET.

Fig. 1. Schematic crosssection of the half unit cell of a vertical SJ DMOS FET.

Fig. 2. Ideal PIN SJ Structures with different pillar widths.

For each power device, the electric field is simulated and extracted using Sentaurus TCAD with fine meshing along the PN junctions to account for the depletion regions. In Fig. 3, the effective critical field of the SJ devices (having a quasi-rectangular field profile) is designated as the flat region in the electric field profile, while it is the maximum value in the conventional devices (with a triangular field profile). Both the vertical and the lateral field components for the devices are plotted along the middle of the n-pillar in Fig. 4. The breakdown condition is reached when the total generated current density, from two-carrier simulations of the continuity equation, increases to . The impact ionization rate is given by

In Fig. 5, the impact ionization rate is shown for both the conventional and SJ devices. It decreases rapidly for conventional devices because of the strong dependence between the impact ionization coefficients and the electric field. For the superjunction devices, the impact ionization rate is almost constant along the whole drift layer thickness because of the uniform vertical electric field along the SJ pillars. Moreover, there is a dip in the SJ impact ionization rate near the upper junction, the physical origin of this dip is the sweeping out of carriers laterally due to a finite lateral field as shown in Fig. 4. Also, since the impact ionization rate is a strong function of the electric field, in conventional devices, whose electric field profile is triangular, with the electric field decreasing linearly with the drift layer thickness, the ionization rate drops significantly (exponentially), making the ionization path to be of the total drift region as shown in Fig 5. For SJ devices, the electric field is uniform along the drift layer, hence the impact ionization rate is also uniform causing a longer ionization path.

Fig. 5. Impact ionization rate along the middle of the n-pillar in both conventional and SJ devices.

Fig. 5. Impact ionization rate along the middle of the n-pillar in both conventional and SJ devices.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.560.pdf

The effective critical electric field has been simulated and plotted versus the drift layer thickness for conventional devices, superjunction devices, and intrinsic PIN devices as shown in Fig. 6. An ideal 1D PIN diode, whose drift region is totally intrinsic, is used here to determine the achievable electric field limit (maximum value), which the PiN SJ devices may ultimately achieve ( 3.9 and for conventional and superjunction devices respectively). In Fig. 6, the effective critical field has a dependence on the drift layer thickness as and for 4 H -SiC conventional and superjunction devices respectively.

Fig. 6. A comparison between conventional and superjunction devices vs drift layer thickness for with intrinsic PiN results. ( ).

Fig. 6. A comparison between conventional and superjunction devices vs drift layer thickness for with intrinsic PiN results. ( ).

Fig. 7. Effective critical field maximum limit for for different drift layer thicknesses. PiN simulation results are shown for pillar width of .

Fig. 7. Effective critical field maximum limit for for different drift layer thicknesses. PiN simulation results are shown for pillar width of .

The effective critical field dependence on the pillar width with the same dosage of is shown in Fig. 7. For SJ devices with higher aspect ratios (where as shown in Fig. 2), the effective critical field is almost constant. These results show that the effective critical field has no dependence on the pillar width or pillar doping because, at avalanche breakdown, the pillars behave as an intrinsic semiconductor and the SJ diode approaches a PIN structure. The alternate P and N pillars in the superjunction (SJ) devices dictate the device to have a lateral electric field component because of which the electric field from the ionized acceptors and donors are initially terminated laterally. After the pillars are all depleted and the ions are all laterally terminated, the vertical field will be uniformly distributed along the drift layer as shown in Fig. 4.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.560.pdf

We have determined that the effective critical electric field value of devices is lower than that of conventional, triangular-field devices. Furthermore, the effective critical field dependence on the drift layer thickness is governed by and for superjunction and conventional devices respectively, but there is no dependence on the doping or the pillar width for high aspect ratio ( ) devices.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.560.pdf

F. Udrea, G. Deboy, T. Fujihira, Superjunction Power Devices, History, Development, and Future Prospects, IEEE Trans. Electron Devices. 64 (2017) 713-727.

B. J. Baliga, Fundamentals of Power Semiconductor Devices (Springer, New York, 2008), 358.

X. Zhou, Z. B. Guo, T. P. Chow, Performance Limits of Vertical 4H-SiC and 2H-GaN Superjunction Devices, Mat. Sci. Forum. 963 (2019) 693-696.

H. Niwa, J. Suda, T. Kimoto, Temperature Dependence of Impact Ionization Coefficients in 4HSiC, Mat. Sci. Forum. 778-780 (2014) 461-466.

Z. Stum, Y. Tang, H. Naik, T.P. Chow, "Improved Analytical Expressions for Avalanche Breakdown in 4H-SiC," Mat. Sci. Forum. 778-780 (2014) 467-470.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 565-569

doi: 10.4028/p-37r645

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-03-15

Accepted:
2022-03-17

Online:
2022-05-31

Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.565.pdf

Mohamed Torky and T. Paul Chow

¹Rensselaer Polytechnic Institute, Troy, NY 12180, U.S.A.

torkym@rpi.edu, chowt@rpi.edu

Keywords: Superjunction (SJ), DMOSFET, UMOSFET, Performance Evaluation, 2D simulation

Abstract

We evaluate and compare the static and dynamic performances of four different power MOSFETs (Conventional DMOS and UMOS, Superjunction (SJ) DMOS and UMOS FETs) from 0.6 to 10 kV with the same approach of [1]. The static on-state performance is determined by analytically calculating the specific on-resistance ( ), while the dynamic switching performance is determined by extracting the specific gate charge ( ) and switching energy loss per cycle ( ) using 2D device simulations. It has been found that the SJ UMOS FET exhibits at least a (up to at 0.6 kV ) reduction in the Figure-of-Merit (FoM) compared to the SJ DMOS FET within the breakdown voltage rating range studied.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.565.pdf

4H-SiC has a higher critical electric field than Si, making it possible to achieve high voltage power devices with a much smaller (1000x) specific on-resistance ( ) than Si-based devices at the same breakdown voltage (BV). Besides, superjunction (SJ) devices have better conduction performance over conventional devices due to a lower specific on-resistance in the drift layer, resulting in a better trade-off between , and BV and hence lower conduction power loss [2]. In this paper, the conventional vertical planar DMOS and trench UMOS FETs, and their SJ counterparts, in , in the blocking voltage range between 0.6 to 10 kV , are examined and compared in terms of their static and dynamic performances, determining quantitatively which transistor to have the best performance.

Device Design

The original version of this paper is available on https://www.scientific.net/MSF.1062.565.pdf

The schematic cross-sections of the four power MOSFETs considered are shown in Figs. 1 to 4, with the unit cell pitch of 6 and for DMOS and UMOS structures, respectively. The conventional 4H-SiC devices are designed using t , and dependence on BV [3], while the SJ devices are designed according to [4] for the desired BV ratings. In Table 1, the drift layer thickness and the doping of the conventional UMOS and DMOS FETs, while the structural parameters for SJ FETs is at constant aspect ratio . The electron inversion and accumulation mobilities are assumed to be 15 and .s respectively for DMOS. However, the inversion mobility for UMOS FETs is .s because of the different crystal orientations.

Table 1. Design parameters of conventional and SJ 4H-SiC MOSFETs at different BV ratings.

BV Rating [V] | Conventional 4H-SiC U/DMOSFETs | Superjunction 4H-SiC U/DMOSFETs
| Drift Layer Thickness (t)[μm] | Drift Layer Doping (ND)[cm⁻³] | Pillar Thickness (t)[μm] | Pillar Doping (NP) (t/W=10)[cm⁻³]
0.6k | 5.5 | 2.4×10¹⁶ | 3.0 | 3.3×10¹⁷
1.2k | 11 | 1.2×10¹⁶ | 6.0 | 1.7×10¹⁷
3.3k | 35 | 3.4×10¹⁵ | 24 | 4.2×10¹⁶
4.5k | 50 | 2.2×10¹⁵ | 32 | 3.1×10¹⁶
10k | 130 | 7.3×10¹⁴ | 64 | 1.6×10¹⁶

Fig. 1. Schematic cross-section of the conventional DMOS half-cell.

Fig. 1. Schematic cross-section of the conventional DMOS half-cell.

Fig. 3. Schematic cross-section of the SJ DMOS at different pillar widths.

Fig. 3. Schematic cross-section of the SJ DMOS at different pillar widths.

Fig. 2. Schematic cross-section of the conventional UMOS full-cell.

Fig. 2. Schematic cross-section of the conventional UMOS full-cell.

Fig. 4. Schematic cross-section of the SJ UMOS at different pillar widths.

Fig. 4. Schematic cross-section of the SJ UMOS at different pillar widths.

The specific on-resistance components are depicted in Fig 5 and 6. All of them are calculated using the structural dimensions, doping, and mobility of the corresponding regions. The three main components are the channel region ( ), the JFET region(s) ( ), and the drift region ( ) for the conventional devices. However, for SJ devices, the drift region has a lower resistance because of a higher pillar doping compared to conventional devices. At lower BVs, the resistance of the channel region dominates, while the drift region dominates at relatively BVs. Consequently, at lower BVs, we expect that the conventional and SJ devices will have almost the same specific onresistance (Ron,sp) due to the channel region, however, at higher BVs, SJ devices will deviate from the conventional devices and exhibit a significantly lower specific on-resistance (Ron,sp).

For the dynamic characteristics, the specific gate capacitance is extracted from a 2D device TCAD simulator (Sentaurus) for each device at each BV rating. From the switching simulations, the gate current is integrated over the time to obtain . Furthermore, switching energy loss per cycle ( ) are extracted. The switching circuit is shown in Fig. 7, where the device is scaled with the appropriate resistive load to achieve the same drain current ( ) and ( ) through and across each device.

Fig. 5. Schematic DMOS cross-section showing various specific on-resistance components.

Fig. 5. Schematic DMOS cross-section showing various specific on-resistance components.

Fig. 7. The switching circuit schematic with a resistive load.

Fig. 7. The switching circuit schematic with a resistive load.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.565.pdf

In Fig. 8, the Ron,sp and BV trade-off for SJ FETs is better. For SJ FETs, the trade-off is RoN,sp and for constant asepct ratio and constant pillar width respectively, while it is for conventional FETs. In Fig. 9, is reduced by 89 and for SJ UMOS and DMOS FETs respectively, compared to their conventional counterparts at 3300 V , due to a lower , achieving reduction at 10 kV , while reduction is 8 and at all BV ratings. The lower of UMOS devices is due to a higher channel density, hence lower . In Fig. 10, SJ UMOS exhibits longer turn-off time, hence, higher switching energy losses per cycle due to higher . As illustrated in Fig. 11, the SJ UMOS FET with the narrowest pillar width [5] exhibits the best performance as it has a Figure-of-Merit (FoM) ( ) reduction of , and compared to conventional UMOS at 0.6 to 10 kV ratings respectively, while it is , and in SJ DMOS at the same BV ratings respectively. The FoM reduction is decreasing at higher BV because the pillar resistance dominates at higher BVs. Unlike Si, has a significant specific drain charge because of its heavier doping and shorter thickness at the same breakdown voltage. On the other hand, SJ devices exhibit sharp CV characteristics, enabling them to have very small , and lower switching losses compared to conventional devices. SJ UMOS has higher switching losses due to an average of higher compared to SJ DMOS, however, it has a significant on average reduction of in , achieving the lowest FoM.

Fig. 8. Ron,sp and BV trade-off for conv. DMOS and SJ DMOS with constant aspect ratio and constant pillar width .

Fig. 8. Ron,sp and BV trade-off for conv. DMOS and SJ DMOS with constant aspect ratio and constant pillar width .

Fig. 9. Ron,sp and for SJ DMOS and UMOS FETs at 600,1200 , and 3300 V .
Conventional device results are plotted for a pillar width of .

Fig. 9. Ron,sp and for SJ DMOS and UMOS FETs at 600,1200 , and 3300 V . Conventional device results are plotted for a pillar width of .

Fig. 10. Switching energy loss per cycle ( for SJ DMOS and UMOS FETs at 600, 1200 , and 3300 V . Conventional device results are plotted for a pillar width of .

Fig. 10. Switching energy loss per cycle ( for SJ DMOS and UMOS FETs at 600, 1200 , and 3300 V . Conventional device results are plotted for a pillar width of .

Fig. 11. Figure-of-Merit ( ) for SJ DMOS and UMOS FETs at 600, 1200, and 3300 V . Conventional device results are plotted for a pillar width of .

Fig. 11. Figure-of-Merit ( ) for SJ DMOS and UMOS FETs at 600, 1200, and 3300 V . Conventional device results are plotted for a pillar width of .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.565.pdf

In summary, the SJ UMOS FET has the best performance in terms of the lowest FoM with at least reduction compared to SJ DMOS at all BV ratings, which infers to have the lowest total energy loss (conduction and switching losses).

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.565.pdf

Z. Guo, C. Hitchcock, T. P. Chow, Comparative Performance Evaulation of Lateral and Vertical GaN High-Voltage Power Field-Effect Transistors, Jpn. J. Appl. Phys. 58 (2019) SCCD09

F. Udrea, G. Deboy, T. Fujihira, Superjunction Power Devices, History, Development, and Future Prospects, IEEE Trans. Electron Devices. 64 (2017) 713-727.

Z. Stum, Y. Tang, H. Naik, T.P. Chow, "Improved Analytical Expressions for Avalanche Breakdown in 4H-SiC," Mat. Sci. Forum. 778-780 (2014) 467-470.

M. Torky, T.P. Chow, Determination of Effective Critical Breakdown Field in Superjunction Devices, submitted to ECSCRM (2021).

X. Zhou, Z. B. Guo, T. P. Chow, Performance Limits of Vertical 4H-SiC and 2H-GaN Superjunction Devices, Mat. Sci. Forum. 963 (2019) 693-696.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 570-575

doi: 10.4028/p-lom714

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Accepted:
2022-03-07

Online:
2022-05-31

Edge Terminations for -SiC Power Devices: A Critical Issue

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

P. Godignon , J. Montserrat , J. Rebollo , D. Planson

IMB-CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain

Univ Lyon, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, CNRS, AMPERE, F-69621, Lyon, France

Centro de Investigación Biomédica en Red en Bioingeniería, Biomateriales y Nanomedicina (CIBER-BBN), Madrid 28029, Spain

philippe.godignon@cnm.es, josep.montserrat@cnm.es, jose.rebollo@cnm.es, dominique.planson@insa-lyon.fr

Keywords: edge termination, JTE, breakdown voltage, OBIC

Abstract

Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

Most of planar and trench power devices are based of one or several n-type/p-type junctions. When the active part of the junction ends on the lateral side of the device, a very high electric field appear under reverse voltage biasing, due to junction curvature or trench corners. Then, a periphery protection, called edge termination is necessary. Reliable and robust high voltage devices need effective edge termination structures to protect the device periphery, so that blocking values close to the ideal 1D avalanche voltage value can be achieved. Many types of terminations have been developed in Silicon technology, the main ones being MESA termination for rectifiers and thyristors, field plates for low voltage range, field guard rings (FGR) and junction termination extension (JTE) for planar rectifiers and transistors. Silicon Carbide is not as friendly as Silicon in terms of processing technology for power device fabrication. Several physical limitations make SiC edge terminations more complex to design in a same way to Silicon. The main limitation is the low diffusion coefficients of dopant atoms inside the semiconductor. Deep junction ( ) are difficult to implement and lateral dopants diffusion is very limited. On the other hand, one of the theoretical advantages of SiC versus Si , its high critical electric field, is also a drawback when looking for compatible dielectric layers capable of operating under such high fields in a reliable way. It clearly limits the use of field plates for instance. Finally, the higher interface traps level observed in the interface compared to Si is also affecting the efficiency of the standard Si terminations architectures in the SiC power devices. Charges accumulate at the interface, generating breakdown voltage instabilities, especially with temperature. Finally, the termination design is also relevant to reach high avalanche ruggedness in order to comply with applications prone to unclamped inductive switching. In this case, the edge termination must reach breakdown at higher voltage than the main active junction [1].

Edge Termination Structures

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

Termination optimization is relevant in power device design since it may affect the reliability of the component, but also because it may consume a large area of the die, especially in the case of very high voltage devices (Fig. 1). This is particularly relevant for SiC semiconductor, considering the cost of the starting material and the defects density, which usually limit the die area of the components. In addition, in some cases, edge termination integration increases the fabrication process complexity (increasing the number of photolithography mask levels), like in trench JFETs, pure Schottky diodes, BJTs or thyristors. These aspects have a direct impact on cost and reliability.

Fig. 1: 6.5 kV commercial device picture and evaluation of its respective active and termination area

Fig. 1. 6.5 kV commercial device picture and evaluation of its respective active and termination area

Usual terminations architectures. The more common periphery protection used in SiC commercial devices is the field guard ring (FGR) termination (Fig. 2a). It is formed with -type implantation wells, having a width of few microns. The key design parameters are the rings distances, which usually increase with the ring position, and the first ring distance with the device main junction. This termination usually consumes a large area and require very precise photolithography and mask etching resolution. The optimal first ring distance depends on the epilayer doping and must be lower than for devices voltage ranges below 1.7 kV . Rings termination also depends on the surface charges at the dielectric interface. In this sense, buried rings configuration have been proposed in order to shift the high electric field peaks from the surface to the SiC bulk [2], limiting interface parasitic effects. This is efficient but more complex to implement, since epilayer regrowth or very high energy implantation are required.

The second common type of edge protection is the Junction Termination Extension (JTE), which enable smaller area, but which typically requires an extra Al ion implantation step, with an accurate control of the implanted dose. JTE is also sensible to surface charges [3]. Then, single implantation JTE is not used anymore, as multiple JTE combination, having decreasing implantation dose, have shown to be more efficient in terms of process control. SiC etching process can be also use to mitigate the JTE dose (see Fig. 2b) and create a double or triple JTE structure without the need for 3 Al implantation steps [4]. Even if the number of photolithographic masks is not reduced, the global technological process results simpler and cheaper. However, a combination of JTE + FGR, or JTE + FGR + JTE outer rings (see Fig. 3) is the most stable, reproducible and efficient combination for most of the SiC devices structures, especially for blocking voltages higher than 1.7 kV . For instance, this architecture has been used in [5] for 27 kV diodes demonstration. Other combination of JTE and rings have been proposed in order to reduce termination length [6].

Fig. 2: Schematic of typical termination types including (a) guard rings termination using VDMOS pwell (b) triple JTE created by SiC dry etching

Fig. 2. Schematic of typical termination types including (a) guard rings termination using VDMOS pwell (b) triple JTE created by SiC dry etching

Fig. 3: Schematic of JBS diode termination including (a) JTE with JTE outer rings and P-well FGR (b) comparison of simulated breakdown voltage of a 6.5 kV wafer for different JTE + rings designs

Fig. 3. Schematic of JBS diode termination including (a) JTE with JTE outer rings and P-well FGR (b) comparison of simulated breakdown voltage of a 6.5 kV wafer for different JTE + rings designs

In a previous paper [7], we analyzed different field guard rings, JTE and JTE + rings combinations for 1.7 kV and 4.5 kV planar MOSFETs fabrication. Main results are summarized in Table 1. We intended to use the MOSFET P-well doping to form deep FGR termination (Fig. 1). The efficiency (calculated using simulated ideal 1D breakdown) of these FGR terminations (designs D3 to D8) is lower than the JTE + Rings one (designs D9 to D11). We believe this difference is due to the surface charges type present in our devices. We also tried to use the P-well doping profile as the JTE in a double JTEs configuration (design D2), without clear success. The lateral extension of the P-well in the periphery has basically no impact on the termination efficiency.

Table 1: Measured breakdown voltage and termination efficiency of MOSFET [7]

Design
Schematic cross section
Wafer#1
Average
VBR
(V)
Efficiency
(%)
Wafer#2
Average
VBR
(V)
Efficiency
(%)

D1 (130 μm)
D1 schematic
1930
85
4500
77

D2 (100 + 30μm)
D2 schematic
1870
82
4000
68

D3 (12 rings)
D3 schematic
2000
88
4870
83

D4
D4 schematic
1360
60
4550
78

D5
D5 schematic
960
42
2880
49

D6 (20 rings)
D6 schematic
2080
91
4550
78

D7
D7 schematic
1300
57
4230
72

D8
D8 schematic
890
39
2700
46

D9
D9 schematic
2260
99
5050
86

D10
D10 schematic
2260
99
5130
88

D11
D11 schematic
2270
99
5230
89

Other 2D and 3D parameters must be defined when designing a JTE (+ rings) termination. JTE length or corner radius must be optimized to minimize the consumed area. In table 2 are reported breakdown voltages of 1.7 kV JBS diodes with the termination architecture shown in Fig. 3a. When comparing design D5 to the reference, we can see that a reduction of the corner radius decreases the breakdown capability. The corner radius will also have a strong impact on the device avalanche ruggedness.

Table 2: Impact of the JTE length and corner radius in 1.7 kV JBS diode avalanche voltage

| Reference design | D2 | D3 | D4 | D5
JTE length | 150μm | 100μm | 50μm | 35μm | 150μm
Corner radius | 150μm | 150μm | 150μm | 150μm | 100μm
Avalanche voltage | > 2000V | > 2000V | 1450V | 1320V | 1910V

On the other hand, the recent availability of SiC trench devices also required adaptation of edge termination. In this sense, 3D edge termination like trench guard rings terminations have been recently proposed for SiC devices [8]. This termination configuration has shown to be efficient in Silicon technologies. It allows to reduce the consumed area, and is compatible with the trench fabrication process. Additionally, the bottom of the trench can be implanted with self-aligned buried ring (see Fig 4a), allowing a reduction of the electric field at the SiC surface. In Fig. 4b, we can see another alternative using a wide trench filled with Benzocyclobutene ( BCB ) in an as JTE configuration [9-10]. The critical part of this termination is the trench side wall charges displacement and the possible parasitic channel that can be created with the electric field peaks. The field plate geometry on top of the termination structure is also a key parameter. For high voltage components, especially for bipolar SiC device, positive and negative beveled MESA terminations can also be used. These terminations, formerly used in thyristor and early power diodes components presents the advantage of lower dimensions than planar terminations [11]. The main issue, especially for the negative bevel, is the SiC etching process necessary to reach low aspect ratio angles. However, solution playing with the etching mask topology (photoresist) or using multiple etching steps are possible, even if not fully compatible with mass production requirements.

Fig. 4: Schematic of a) a trench rings termination [8] (b) a trench termination filled with Benzocyclobutene BCB [10]

Fig. 4. Schematic of a) a trench rings termination [8] (b) a trench termination filled with Benzocyclobutene BCB [10]

Other termination elements. One element of the termination never mentioned in the literature is the channel stopper (see Fig. 5a). Nevertheless, it is part of the termination design, as the distance between the end of the JTE or the rings and this channel stopper may affect the breakdown capability, the dynamic behavior and directly contribute to the total area required for the periphery protection of the power devices. To determine the optimal position of the channel stopper by modelling is tricky as it depends on a wide range of parameters such as the interface traps and fixed charge of the different passivation layers, the type of packaging technique used, the position of the top metal electrode, etc. We studied the optimal position of the channel stopper in 1.7 kV JBS diodes passivated with of polyamide. Diodes with a distance of between the end of the JTE and the channel stopper were able to withstand more than 2 kV while the diodes with a JTE-CS distance of exhibit a premature breakdown around 1.6 kV after arcing between the anode and channel stopper metals. A picture of a failing diode at 1.6 kV is shown in Fig. 5b, where the damaged area is clearly seen.

Fig. 5: (a) schematic of the termination with channel stopper (b) A picture of a failed 1.7 kV diode after premature breakdown at 1.6 kV due to short distance between anode and channel stopper

Fig. 5. (a) schematic of the termination with channel stopper (b) A picture of a failed 1.7 kV diode after premature breakdown at 1.6 kV due to short distance between anode and channel stopper

Fig. 5: (a) schematic of the termination with channel stopper (b) A picture of a failed 1.7 kV diode after premature breakdown at 1.6 kV due to short distance between anode and channel stopper

Fig. 5. (a) schematic of the termination with channel stopper (b) A picture of a failed 1.7 kV diode after premature breakdown at 1.6 kV due to short distance between anode and channel stopper

Last but not least, the passivation of the surface in the termination area is a critical aspect for the wide band gap semiconductor high voltage devices. When no passivation is used, premature breakdown due to arcing in air can occur. However, the addition of a passivation layer (for instance polyamide) may change the surface charges state, and impact the breakdown voltage. This is particularly visible in JTE terminations, as the surface charges directly impact the optimal value of JTE implantation dose. Again, a combination of JTE and rings is the most suitable solution to mitigate these charges issues. For high voltage devices ( ), additional effects due to ambient factors like humidity are enhanced and may seriously affect the reliability of power modules if not properly passivated [12]. In this case, solutions pass through a proper packaging technology, for instance using organic passivant like GlobTop. Stability and reliability evaluation of the termination can be done using High Temperature Reverse Bias test (HTRB) [12], including Humidity (H3TRB) [13-14], if a proper evaluation of the passivation is to be done. It is also relevant to test the termination under Unclamped Inductive Switching (UIS) to check the avalanche capability of the device [1].

Termination optimization through advanced characterization:

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

A good understanding of termination behavior also requires advanced characterization tools such as lock-in thermography, photoluminescence, Electron Beam Induced Current (EBIC). Optical Beam Induced Current technique (OBIC) applied to WBG semiconductor devices have shown to be useful to study the efficiency of different edge protection techniques [15]. In order to illustrate some OBIC experiments on different terminations, PiN diodes with several JTE protections ( 1.7 kV -class) has been measured with increasing reverse voltage up to 400 V . Since OBIC setup is under air, as described in [16], it limits the maximum voltage bias for unpassivated devices. Scans were performed from the center of the diode towards the outer periphery. For each results of Fig 6, one can find the drawing of the edge termination at the bottom. Diodes (#1-#3) exhibit increasing length of JTE. Diode #4 has a JTE length of rings. As it can be seen, the OBIC signal appears at least on the JTE length even with 0 V . As the reverse voltage increases, the OBIC signal increases and extends laterally towards the outside. For diode #4, none of the JTE rings are depleted at 0 V . However, these rings are quickly depleted with a reverse voltage as low as 50 V .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

Current edge termination in SiC can reach 100% efficiency, which is relevant for the avalanche ruggedness capability. Termination design is still improving to adapt to the new Trench and SuperJunction technologies or to reduce the consumed area, especially in high and very high voltage devices. However, physical limits as the minimum distance between main top electrode and channel stopper will fix the maximum size reduction achievable. Passivation and packaging are also two of the main concerns for the next generation of high voltage devices.

Fig. 6: OBIC measured current versus distance in experiments on 1.7 kV Class PiN diodes with several JTE protections geometries. Basic drawing of each termination is shown as inset

Fig. 6. OBIC measured current versus distance in experiments on 1.7 kV Class PiN diodes with several JTE protections geometries. Basic drawing of each termination is shown as inset

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

Autors want to acknowledge Dr. V. Soler for his contribution to this work. This work was partially supported by the DiamMOS project funded by the Spanish Government (TEC2017-86347-C2-2-R), cofounded by the EU-ERDF (FEDER), and by the Agència de Gestió d'Ajuts Universitaris i Recerca Funds under Grant 2017-SGR-1384.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.570.pdf

A. Gendron, D. Sdrulla, B. Odekirk, A. Kashyap, L. Starr, Mat. Sci. Forum, Vol 924, pp. 585-588 [2] A. Mihaila et al, Int. Symp. on Power Semiconductor Devices and ICs (ISPSD06), Naples (Italy), June 5-9, 2006, pp.161-164

H. Matsushima, R. Yamada, A. Shima, Int. Symp. on Power Semiconductor Devices and ICs (ISPSD17), Sapporo (Japan), May 28-June 1, 2017, pp. 347-350

T. Dai, L. Zhang, O. Vavasour, et als, Int. Symp. on Power Semiconductor Devices and ICs (ISPSD21), Nagoya (Japan), May 30-June 3, 2021, pp.251-254

N. Kaji, H. Niwa, J.Suda, T. Kimoto, Mat. Sci. Forum, Vols. 778-780 (2014), pp.832-835

A. Mihaila et al., Int. Symp. on Power Semiconductor Devices and ICs (ISPSD16), Prague, June 12-16 (2016), pp. 223

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J. Jeong, J. Cha, G. Kim, S. Cho, H. Lee, Applied Sciences 2020, 10, pp. 753

T. Nguyen et al, Mat. Sci. Forum, Vol. 858, (2016), pp. 982-985.

Y. Liu et al., Int. Symp. on Power Semiconductor Devices and ICs (ISPSD19), pp. 143-146.

W. Sung, B. Baliga, A. Huang, IEEE Trans. on Electron Devices, Vol 63, nº4 (2016), pp. 1630

F. Hoffmann et al, Int. Symp. on Power Semiconductor Devices and ICs (ISPSD18), Chicago, May 13-17 (2018), pp. 435-438.

J. Jormanainen et al, PCIM Europe 2018, 5-7 June 2018, Nuremberg, pp 563-569

D. Cimmino, S. Ferrero, Electronics 2020, 9, pp. 1884

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D. Planson et al., this conference (We-2B-05)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 576-581

doi: 10.4028/p-1k1eb6

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-20

Accepted:
2022-03-17

Online:
2022-05-31

Impact of Device Design Parameters on 15 kV SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.576.pdf

Siddarth Sundaresan , Jaehoon Park , Vamsi Mulpuri , Ranbir Singh

GeneSiC Semiconductor, Dulles VA, USA

*Email: sid.sundaresan@ieee.org (Corresponding Author)

jaehoon.park@genesicsemi.com, vamsi.mulpuri@genesicsemi.com, ranbir@ieee.org

Keywords: Silicon Carbide MOSFET, ultra-high voltage, on-resistance, device design

Abstract

Experimental results from 15 kV -rated SiC DMOSFETs developed by GeneSiC Semiconductor are presented. A breakdown voltage of 16.7 kV is recorded, with < 200 nA leakage current at 15 kV . in the range of or were measured on MOSFETs with chip sizes of and , respectively, with a lowest specific of 238 - . The impact of MOSFET channel length and JFET width on the device performance is elucidated. Single-pulse avalanche energy and is achieved. gate stress applied at showed good stability with only a small increase during the initial stages of the stress time.

Introduction and Experimental Details

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Ultra-high voltage ( ) SiC transistors will be a key enabling technology for smart-grid solidstate transformers [1], traction device and renewable energy systems, power supplies for electron guns, and DoD applications [2]. In this paper, we present experimental results obtained on SiC planar MOSFETs developed by GeneSiC Semiconductor on thick N - drift layers. Different die sizes with total chip areas of and were fabricated. A planar DMOSFET device structure was employed, with different JFET and MOSFET channel lengths. A 50 nm thick gate oxide was used. The device fabrication was conducted using GeneSiC's established process used for fabricating lower voltage rated SiC DMOSFETs. Selected die were packaged in custom packages for high-temperature and UHV characterization.

Static Electrical Characteristics

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Breakdown Voltage: A breakdown voltage of 16.7 kV was measured on MOSFETs fabricated on 5E14 drift layer (Fig. 1a). The simulated unit cell breakdown voltage is shown in Fig 1b. A worst case breakdown voltage, assuming higher drift doping and higher drift thickness is also shown in Fig. 1b.

Figure 1 (a): Breakdown voltage measured on SiC MOSFET fabricated on a drift layer (b): TCAD Simulated breakdown voltage for the SiC MOSFET unit cell with nominal and worst-case (highest doping/lowest thickness) N-epilayer specs.

Figure 1. Figure 1 (a): Breakdown voltage measured on SiC MOSFET fabricated on a drift layer (b): TCAD Simulated breakdown voltage for the SiC MOSFET unit cell with nominal and worst-case (highest doping/lowest thickness) N-epilayer specs.

The measured breakdown voltage is close to the 1-D avalanche breakdown voltage for the N-epilayer, which is an indication of a robust device design. A sub-200 nA drain leakage current is observed at the rated 15 kV blocking voltage.

Output Characteristics: A comparison of output characteristics measured in the and quadrants on SiC MOSFETs (active area ) with different JFET widths is shown in Fig 2a. The MOSFET with JFET width of shows the presence of a "knee voltage" due to a potential barrier in the JFET region, which is clearly absent for the MOSFET with JFET width of values of and are extracted at and , in the quadrant for the different JFET width die, which corresponds to of and , respectively - the 1-D calculated N-drift layer resistance is - , for comparison. The for the two devices in the quadrant (Fig. 2b) are - and - , respectively. The quadrant is closer to the calculated resistance for the N - drift layer, with almost no difference between the two devices with different JFET widths. Since the body-drift p-n junction is forward biased in the quadrant, these observations indicate that a significant portion of the total quadrant can be attributed to the resistance in the JFET region, for these devices. The output characteristics measured at is shown in Fig. 2b. The at increases by a factor of three, when compared to the room-temperature value.

Figure 2: (a) quadrant and quadrant output characteristics at room-temperature and (b) measurements of output characteristics.

Figure 2. Figure 2: (a) quadrant and quadrant output characteristics at room-temperature and (b) measurements of output characteristics.

Impact of JFET Width on : A plot of versus JFET width is shown in Fig. 3. A clear reduction of with increasing JFET width is observed - the minima in the lies beyond the range of JFET widths explored in this study. A lowest of - is extracted for the widest JFET width explored in this study - this is close to the theoretical limit. There was minimal impact of MOSFET channel length on the output characteristics (not shown). The peak gate oxide field was kept below for all device designs explored in this study.

Figure 3: RDS,ON versus JFET Width for 15 kV SiC MOSFETs fabricated in this study.

Figure 3. Figure 3: RDS,ON versus JFET Width for 15 kV SiC MOSFETs fabricated in this study.

Third Quadrant Characteristics: The output characteristics in the quadrant are compared at room-temperature for MOSFETs (active area ) at different gate biases in Fig. 4a, and with different channel lengths, in Fig. 4b. A cross-over current is clearly visible in Fig. 4a, above which zero gate bias results in higher than the case when . When the MOSFET channel is kept off (zero gate bias), the IsD is primarily conducted through the p-n junction in bipolar mode, with conductivity modulation of the N-drift layer. When the MOSFET channel is fully turned on (VGS ), a significant portion of the is conducted by the majority carrier electrons through the MOSFET channel, and less current is conducted by the body diode in bipolar mode, which results in a higher differential on-resistance (or lower ) at a given drain bias. The MOSFET with the longer channel (Fig. 4b) shows a more pronounced bipolar action when compared to its shorter channel counterpart, since the higher channel resistance pushes more current through the p-n junction. There is no impact of the MOSFET channel length in the quadrant output characteristics (not shown) which are largely dominated by the high resistance of the thick drift layer. At (Fig. 4c), the Aluminum acceptors in the P-Well are almost fully ionized [3], and this results in a more stark contrast between the zero gate bias and 20 V gate bias output curves for either device. Fig. 4c shows that operating the 15 kV MOSFET at 20 V gate bias can result in a positive temperature coefficient of Isd, whereas operating the same device at zero gate bias can result in a negative temperature co-efficient of due to the aforementioned competing mechanisms.

Figure 4: Third quadrant characteristics measured (a): at room-temperature with different gate bias, and (b): on MOSFETs with different channel lengths (c) The third quadrant characteristics are compared at different temperatures and gate bias conditions.

Figure 4. Figure 4: Third quadrant characteristics measured (a): at room-temperature with different gate bias, and (b): on MOSFETs with different channel lengths (c) The third quadrant characteristics are compared at different temperatures and gate bias conditions.

Figure 5: Transfer I-V characteristics measured on 25 mm 215 kV SiC MOSFET die at room-temperature and .

Figure 5. Figure 5: Transfer I-V characteristics measured on 25 mm 215 kV SiC MOSFET die at room-temperature and .

Transfer Characteristics: The transfer I-V characteristics of a MOSFET at and are shown in Fig. 5. A gate threshold voltage ( ) of 3.2 V is measured at at roomtemperature, which drops to 1.8 V at . In the range, an average sub-threshold slope (SS) of decade is extracted at , which drops to decade at - a lower SS at higher temperatures (and at lower drain bias) results from an exponentially decreasing acceptor trap density when moving away from the conduction band edge of SiC, towards the mid-gap. The density of interface traps is extracted from the room-temperature SS as in weak inversion, using the equation provided in [4].

Saturation Current Characteristics: The saturation current ( ) characteristics measured on two 15 kV MOSFETs with different channel lengths (Fig. 6). A lower was measured at , with near-identical under operating conditions. A lower is beneficial for increasing short-circuit withstand time, since it reduces the power dissipation during the short-circuit event. The short-circuit robustness of these devices will be reported elsewhere.

Figure 6: Saturation Current characteristics.

Figure 6. Figure 6: Saturation Current characteristics.

High-Temperature Gate Bias Stress: Several 15 kV SiC MOSFETs fabricated in this work were stressed for 60 hours at in a oven. The evolution of the over time is shown in Fig. 7. After an initial increase, the saturates for the remainder of the stress time, similar to the 1200 V SiC MOSFETs reported in [5].

Figure 7: High-Temperature Gate Bias Stress Test.

Figure 7. Figure 7: High-Temperature Gate Bias Stress Test.

Unclamped inductive switching (UIS): Unclamped inductive switching (UIS) was performed on a packaged 15 kV MOSFET at a peak drain current of with a 115 mH inductor at room-temperature, with and . We could not measure the drain voltage during the UIS waveform, due to equipment limitations for measuring such a high voltage. A singlepulse avalanche energy was achieved before the device failed catastrophically. A peak drain voltage of 18.9 kV can be inferred from the inductor discharging waveform (Fig.8), which is in line with the static breakdown voltage reported in Fig. 1.

Figure 8: Unclamped inductive switching waveforms.

Figure 8. Figure 8: Unclamped inductive switching waveforms.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.576.pdf

This work was performed under an US Army Research Laboratory (ARL) Co-operative agreement (CA) contract: CA-W911NF-18-2-0286. The support of ARL program manager Dr. Aivars Lelis is gratefully acknowledged.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.576.pdf

A. Q. Huang et al, in CPSS Transactions on Power Electronics and Applications, vol. 2, no. 2, pp. 118-130, 2017

A. N. Lemmon et al in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 5, no. 1, pp. 309-322, March 2017

M.A. Capano et al. J. Appl. Phys. 87, 8773 (2000)

K. Tachiki et al. Appl. Phys. Express 14031001 (2021)

S. Sundaresan et al. 2020 IEEE IRPS Proceedings pp1-4 (2021), doi: 10.1109/IRPS45951.2020.9128225

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 582-587

doi: 10.4028/p-xd84zm

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-22

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

Ben Jones , Jacob Mitchell , Jon Evans , Finn Monaghan , Mike Jennings , Chris Bolton , Kevin Riddell , Huma Ashraf , Owen Guy

Faculty of Science and Engineering Swansea University, Singleton Park, Sketty, Swansea SA2 8PP, UK

SPTS Technologies, Ringland Way, Newport NP18 2TA, UK

828129@swansea.ac.uk, j.j.mitchell@swansea.ac.uk, J.Evans@swansea.ac.uk, f.monaghan@swansea.ac.uk, m.r.jennings@swansea.ac.uk, chris.bolton@spts.com, kevin.riddel@spts.com, Huma.Ashraf@SPTS.com, o.j.guy@swansea.ac.uk

Keywords: Automotive, Power Device, Reliability, Electric Vehicle, Trench Processing, FoundryCompatible, Trench Corner Rounding, Trench device simulation, ICP etch.

Abstract

In this paper we report the progress of our SiC trench etch development using enhanced ICP-based etch technology. Computer modelling of the electric field strength in the gate oxide as a function of corner geometry was used to illustrate trench corner rounding as an effective method to avoid to high gate oxide field strengths. This is an effort to examine a major ongoing issue in device reliability, and to govern future device design.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

High efficiency electric vehicles of the future will utilise wide bandgap (WBG) semiconductors such as silicon carbide ( SiC ) and gallium nitride ( GaN ) transistors (replacing silicon) in power electronic converters (PEC). With respect to SiC MOSFETs, device manufacturers are developing trench MOSFET (metal oxide field effect transistor) technology to increase the die per wafer and improve performance and reliability. The reliability of SiC and GaN based power devices is inherently related to the trench etch processes. Overcoming challenges relating to device fabrication and design of high voltage SiC and GaN trench devices is a prerequisite for widespread uptake in the automotive sector. Current SiC device structures are primarily MOSFET designs, while GaN device structures are typically based on high electron mobility transistors (HEMT) [1-2]. Trench based architectures offer competitive cellular pitches and greater current carrying capabilities, SiC trench MOSFETs being a prime example of state-of-the-art WBG technology.

This paper reports the development of an in-line SiC trench etch process technology suitable for high-volume GaN and SiC power device manufacture in a semiconductor foundry. Specifically, the trench etching capability demonstrated in this paper is applicable to classic SiC trench MOSFET architectures and GaN device structures based on vertical GaN-on-SiC MOSFETs (as opposed to HEMT) device structures. Fig. 1.1 illustrates Gauss' Law of the electric field enhancement within the gate oxide of a SiC trench power MOSFET. Naturally the failure of the oxide due to increased electric field strength will be exacerbated when considering GaN, since the critical electric field strength in GaN is higher in magnitude compared to .

From the device design perspective, one of the leading technologies specifically aimed at suppressing this enhanced gate oxide electric field is based on a double trench device design approach [3]. This design utilizes secondary trench structures in the sources area as a means of reducing the electric field concentration at the base of the gate trench, providing reduced ON-resistances and reduced input capacitance, compared with contemporary DMOS structure SiC-MOSFETs [4]. The challenges for realising foundry-ready trench etching processes for WBG materials are; (1) Micro-trenches or sharp corners, that induce the crowding of electric field in the corner of the trench, thereby reducing the breakdown field; and (2) Sidewall striations - having the effect of increasing the
leakage current through the gate oxide. Additionally, rounded corners on both the top and bottom of the trench must be processed for electric field suppression.

This paper reports developments in two distinct areas; SiC trench device simulation and SiC trench process etching.

Fig. 1.1: Illustration of Gauss' law showing e-field enhancement in the gate oxide of a SiC trench MOSFET modelled using Silvaco TCAD. 2D trench MOSFET power device model including cutline (left) and the resultant plot of the Electric field magnitude against horizontal position (right).

Fig. 1. 1: Illustration of Gauss' law showing e-field enhancement in the gate oxide of a SiC trench MOSFET modelled using Silvaco TCAD. 2D trench MOSFET power device model including cutline (left) and the resultant plot of the Electric field magnitude against horizontal position (right).

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

Etched SiC samples were fabricated as follows; a layer was deposited onto a 100 mm SiC substrate using an SPTS PECVD tool. The substrate was prepared for photolithography by solvent cleaning and dehydration at . Ti Prime adhesion promoter was deposited on the SiC wafer as a thin film, via spin coating. The wafer substrate was subsequently patterned using AZ® ECI 3012 positive photoresist. The method of patterning involved photoresist deposition by spin coating, exposure using a SUSS MA8 Gen5 Mask Aligner and development with AZ® 726 MIF developer. An oxide etch was performed using an SPTS APS tool. Following this, wide SiC trenches were etched to a depth of , also using the same etch system. Key SiC etch process parameters were 126s processing time, 900 W ICP power, 500 W electrode power, 10 mT pressure, and gas flows of , and He 25 sccm .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

SiC ICP Etch

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

The SEM cross-sections presented in Fig. 2.1 shows (a) the PR used to define the underlying oxide hard mask and (b) the remaining oxide hard mask after the SiC etch. An initial SiC etch rate of was achieved; which could be increased with further optimisation. The trench itself has a width of and a depth of . The sidewall angle is and there are no instances of microtrenching observed. selectivity however is quite low, at around 2:1.
Typical preliminary SiC etch rates reported elsewhere have been known to be as low as [5], so by comparison is a good starting point for further optimisation. Improving the SiC etch rate is key to processing trench MOSFET device architecture. Increasing the ICP power is known to increase the etch rate of materials such as Si , however for SiC increasing the bias power has been found to be more effective.

Currently selectivity is roughly , with the hardmask noticeably etching and degrading Fig. 2.1 (a) - Fig. 2.1 (b). For the 1 um deep trench this is not a major issue, as Fig. 2.1 (b) shows that the SiC etch profile is near vertical, with no instances of micro-trenching and sidewall angle close to . Nevertheless, it is clear from the etched profile, that further mask deformation will result in a compromised SiC etch. Therefore, improving the etch selectivity is crucial for further process development. Increasing process pressure should improve the etch selectivity, as SiC etch rate is known to improve as pressure increases to , while exhibits an inhibited etch rate at this higher-pressure range [5].

Fig. 2.1: SEM imaging of etched (a) and etched SiC using the SPTS APS tool (b). 2um trench width, 1 um depth. Remnants of the hard mask are still visible, while the PR has been stripped post-etch.

Fig. 2. 1: SEM imaging of etched (a) and etched SiC using the SPTS APS tool (b). 2um trench width, 1 um depth. Remnants of the hard mask are still visible, while the PR has been stripped post-etch.

Trench Device Simulation

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When compared to silicon, one of the key benefits is the ability of SiC devices to operate at far larger electric fields. However, due to Gauss's law this material benefit turns into a major design challenge when the gate oxide of a MOSFET is concerned; the field in the oxide can reach up to 2.6 times the field in the SiC - which could result in a field as high as in the gate oxide [6]. Additionally, in a trench MOSFET electric field crowds at the corners of the trench, causing the field values in the oxide to reach unacceptably high levels and thus fail at relatively low (compared to the theoretical maximum) under reverse bias conditions.
Simulations of SiC trench MOSFET structures, investigating the effect of the curvature of the trench etch on the electric field profile, were completed using Sentaurus TCAD. An example trench MOSFET structure, Fig. 2.2 (a), was designed with a drift region doping of in Fig. 2.2(b). The radius of curvature of the trench bottom was varied, whilst keeping the depth & position of the trench constant (Fig. 2.3). This device was then simulated under reverse bias conditions of , and the maximum electric field in the SiC region recorded at each voltage. For comparison, an identical reverse bias simulation was completed at each of the three bias points for a similar design with a sharp right-angle corner. There is a significant change in the field profile within the gate oxide as the trench radius of curvature increases; we observe a change in the electrostatic potential distribution, shown in Fig 2.4, alongside less electric field crowding at the corners of the gate oxide, as shown in Fig 2.5. The maximum field observed in the surrounding SiC layer is also reduces with increased trench curvature.

Device simulations show a decrease of maximum electric field strength per 30 nm of increased radius of curvature, as shown in Fig. 2.6. This rate of decrease in field strength is consistent across all three bias points. By increasing the radius of curvature of trench etch by 100 nm , a decrease of and in field strength is observed at , 750 V and 1000 V , respectively. This equates to a decrease in field strength at all bias points simulated. When comparing the trench with the largest radius of curvature simulated ( 185 nm ) with a trench possessing a right-angle corner, a field decrease of was observed at all three values.

These results carry even more significance when the magnitude of the electric field is considered. At , a drop of field strength in the SiC would result in a drop of in the gate oxide.

Fig. 2.2: a) Model trench cross section. b) Close up image of doping profile around the gate trench of the MOSFET.

Fig. 2. 2: a) Model trench cross section. b) Close up image of doping profile around the gate trench of the MOSFET.

Fig. 2.3: Further model cross sections illustrating the variation of radius of curvature at the of the trench bottom. a) Extensive corner rounding - radius of curvature b) Minimal corner rounding - radius of curvature .

Fig. 2. 3: Further model cross sections illustrating the variation of radius of curvature at the of the trench bottom. a) Extensive corner rounding - radius of curvature b) Minimal corner rounding - radius of curvature .

Fig. 2.4: Potential Distribution plot with contours at a) Extensive corner rounding radius of curvature ) Minimal corner rounding - radius of curvature .

Fig. 2. 4: Potential Distribution plot with contours at a) Extensive corner rounding radius of curvature ) Minimal corner rounding - radius of curvature .

Fig. 2.5: Electric field profile of the gate trench at b) Radius of curvature b) Radius of curvature .

Fig. 2. 5: Electric field profile of the gate trench at b) Radius of curvature b) Radius of curvature .

Fig. 2.6: Plot of trench bottom corner radius of curvature versus electric field strength at three different voltage ratings. Increasing radius of curvature reduces the maximum field observed at the SiC corner. The trend is observed irrespective of applied voltage.

Fig. 2. 6: Plot of trench bottom corner radius of curvature versus electric field strength at three different voltage ratings. Increasing radius of curvature reduces the maximum field observed at the SiC corner. The trend is observed irrespective of applied voltage.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

In summary we have demonstrated development work on our SiC etch capability using an enhanced ICP-based etch tool from SPTS. The influence of several etch process parameters have been considered with a goal of optimising the SiC etch process. Future work on the SiC etch will aim to improve the etch selectivity as trench depth increases. Ultimately, high aspect ratio trenches with rounded corners should be achieved to facilitate fabricating a double trench device design. Additionally, the implied impacts of trench corner rounding on the gate oxide have been investigated using Sentaurus TCAD modelling. A decrease of maximum electric field strength per 30 nm of increased radius of curvature was simulated. This is promising, and work is ongoing to attain electrical characterisation results to confirm the model.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.582.pdf

B.J. Baliga, Fundamentals of Power Semiconductor Devices ed. (Springer, Raleigh, 2008) p.283.

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology (Wiley, Singapore, 2014) p.312.

J. Zheng and M. N. Darwish, US Patent No. 8076719 ( December 2011)

Information on

H. Oda. et al, Optimizing the SiC plasma etching process for manufacturing power devices (CS MANTECH Conference, Scottsdale, 2015)

B.J. Baliga, Silicon Carbide Power Devices (B & JO Enterprise, Singapore, 2005) P. 328

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 588-592

doi: 10.4028/p-u12e6u

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-23

Revised:
2022-03-15

Accepted:
2022-03-17

Online:
2022-05-31

Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

Vinoth Sundaramoorthy , Andrei Mihaila , Lucas Spejo , Renato Minamisawa and Lars Knoll

Hitachi Energy, Fabrikstrasse 3, 5600 Lenzburg, Switzerland

Fachhochschule Nordwestschweiz, Bahnhofstrasse 6, 5210 Windisch, Switzerland

vinoth.sundaramoorthy@hitachienergy.com, andrei.mihaila@hitachienergy.com,

lucas.spejo@fhnw.ch, renato.minamisawa@fhnw.ch,

Keywords: PiN diode, Junction Barrier Schottky (JBS) diode, IGBT.

Abstract

V SiC PiN diode with JTE and p+ rings termination was fabricated and characterized. The static and dynamic performance of SiC PiN diode were compared with that of SiC JBS diode and silicon diode, while switched in combination with a silicon IGBT. SiC PiN provides clear advantage while operating at higher current densities (above ) and had lower leakage current. When switched together with a silicon IGBT, they contribute to losses similar to that of a SiC JBS diode.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

SiC components with 6.5 kV voltage rating and above are of primary interest for power electronics applications such as distribution transformers and medium-voltage drives [1-3]. SiC diodes in particular are an essential component to SiC switches in such applications, especially when reverseblocking components (IGBTs) are involved. In addition, MOSFETs also benefit from the implementation of antiparallel diodes. Especially in medium voltage range, bipolar diode devices (p-i-n) offer better performance compared to unipolar devices (JBS) due to conductivity modulation when high current operation is encountered [4,5].
In this work, we have fabricated 6.5 kV PiN diode that consist of anode contact and an edge termination consisting of Junction Termination Extension (JTE) and p+ rings. We compare the static and dynamic performance of the 6.5 kV SiC PiN diode with that of SiC JBS and a silicon diode in terms of an application with a 6.5 kV Si IGBT.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

6.5 kV SiC PiN diodes were fabricated using 4H-SiC wafers consisting of epilayer with a doping concentration of and a thick anode with a doping concentration of . Ti/Al metal layers were used as Ohmic contact to the anode. The periphery of the diodes was protected using a Junction Termination Extension (JTE) and 5 embedded guard rings. The anode MESA angle was optimized such that the walls are also implanted with (Fig 1b). No lifetime enhancing methods were used here. The average carrier lifetime values measured through were between 0.1 and . The fabrication of PiN diode started with the etching of anode MESA using reactive ion etching (RIE) followed by implantation of rings and JTE. This was followed by activation and formation of the backside Ohmic contact. Then passivation layers were deposited and patterned. Next, metal contact layers were formed on the anode and finally polyimide was deposited and patterned to complete the fabrication process.

Fig. 1. (a) Pictorial cross section of SiC PiN diode, (b) SEM picture showing the sloped anode MESA.

Fig. 1. (a) Pictorial cross section of SiC PiN diode, (b) SEM picture showing the sloped anode MESA.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

Static characterization

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

The normalized forward characteristics at of a 6.5 kV PiN diode is shown in fig. 1 along with the forward characteristics of 6.5 kV SiC JBS and silicon diode. It could be seen that at a current density of the SiC PiN diode has a forward voltage of , whereas SiC JBS and silicon diode reach a current density of at a forward voltage of and , respectively. Hence, SiC PiN diode offers a clear advantage when operating at higher current densities (above ). For current densities less than , SiC JBS and silicon diode depict a lower forward voltage drop, due to the higher knee voltage of SiC PiN diode. The reverse blocking characteristics of these diodes at room temperature are shown in fig. 2. It can be seen in the graph that SiC PiN diode has the lowest leakage current up to 6 kV . The silicon diode reveals a lower reverse leakage than SiC JBS diode throughout the whole range studied.

Fig. 2. Comparison of forward characteristics of 6.5 kV SiC PiN & JBS diodes with Si diode.

Fig. 2. Comparison of forward characteristics of 6.5 kV SiC PiN & JBS diodes with Si diode.

Fig. 3. Comparison of reverse characteristics of 6.5 kV SiC PiN & JBS diodes with Si diode.

Fig. 3. Comparison of reverse characteristics of 6.5 kV SiC PiN & JBS diodes with Si diode.

Dynamic characterization

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

The dynamic performance of these diodes has been analysed by switching them with 6.5 kV silicon IGBT at room temperature. Fig. 3 shows the IGBT turn-on wave form using the SiC JBS, SiC PiN and the Si diode. The IGBT has been switched at a dc link voltage of 4.4 kV and a current of 20 A . As expected, the IGBT turn on current overshoot differs when switched with different diodes. IGBT current overshoot is when switched together with silicon diode. Current overshoot is
and A when switched with SiC JBS and PiN diode, respectively. The switching losses for the diode turn-off and for the IGBT turn-on could thus be significantly reduced using SiC diodes.

Fig. 3. 6.5 kV Si IGBT turn-on characteristics when switched with SiC PiN, SiC JBS or silicon diode.

Fig. 3. 6.5 kV Si IGBT turn-on characteristics when switched with SiC PiN, SiC JBS or silicon diode.

Fig. 4. Turn-off characteristics of 6.5 kV SiC PiN, JBS and silicon diode when switched together with 6.5 kV Si IGBT.

Fig. 4. Turn-off characteristics of 6.5 kV SiC PiN, JBS and silicon diode when switched together with 6.5 kV Si IGBT.

The turn-off characteristics of silicon diode, SiC PiN and SiC JBS diodes when switched together with 6.5 kV silicon IGBT at a dc link voltage of 4.4 kV and current of 20 A is shown in Fig. 4. It could be seen that current overshoot during diode turn off was very high ( ) for silicon diode due to reverse recovery. The current overshoot for both SiC JBS ( ) and PiN diode ( ) was low compared to the silicon diode. The overshoot was very low for SiC JBS due to the absence of minority carriers. There was not significant difference in the turn off characteristics of IGBT when switched with a silicon diode, SiC PiN or JBS diodes (not shown).

The power losses of silicon IGBT during turn on, when switched with different diodes is shown in Fig. 5. It could be seen that the power losses of the IGBT are very high when switched with silicon
diode and it was more than twice than the losses of IGBT switched with SiC diodes. Again, the power losses of the IGBT switched with SiC JBS diode was the lowest. The calculated power losses of IGBT during turn on and turn off with different diodes is shown in table 1. It could be seen that the IGBT turn on losses when switched with silicon diode ( ) was more than twice when switched with SiC diodes ( ). There was not much difference in the turn-off losses of IGBT when switched with different diodes. The loss from SiC diodes ( ) was very low compared to silicon diode .

Fig. 5. Comparison of power losses of 6.5 kV Si IGBT during turn-on, when switched with SiC PiN, SiC JBS or silicon diode.

Fig. 5. Comparison of power losses of 6.5 kV Si IGBT during turn-on, when switched with SiC PiN, SiC JBS or silicon diode.

Table 1. Comparison of switching losses of IGBT when switched with different diode and losses from each diode.

Switched with | IGBT turn on losses (mJ) | IGBT turn off losses (mJ) | Diode losses (mJ)
Si Diode | ~85 | ~89 | ~10
SiC PiN | ~41 | ~85 | <2
SiC JBS | ~39 | ~85 | <2

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

6.5 kV SiC PiN diode with JTE and rings termination was fabricated and characterized. The performance of SiC PiN diode was compared with that of SiC JBS diode and silicon diode, while switched in combination with a silicon IGBT. SiC PiN provides clear advantage while operating at higher current densities (above ) and had lower leakage current. The power loss of silicon IGBT when switched together with SiC PiN or JBS diode was similar. Considering the higher operating current density, low leakage and better dynamic characteristics, SiC PiN offers the superior solution among the diodes studied.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.588.pdf

F. Filsecker et al., "The investigation of a SiC diode module for medium voltage converters", IEEE Trans. Power Electron., vol. 29, no.5, pp. 2272-2280, 2014.

M. Rahimo, "Performance evaluation and expected challenges of silicon carbide power MOSFETs for high voltage applications", Material Science Forum, vol. 897, pp. 649-654, 2017.

F. Filsecker et al., "Comparison of 6.5 kV silicon and SiC Diodes", IEEE Energy Convers. Cong. Ехро., pp. 2261-2267, 2012.

A. Salemi et al., "Conductivity modulated on-axis PiN diodes", Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), vol. 2015, pp. 269-272, 2015.

A. Salemi et al., "Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN diodes", Mat. Sci. Forum, vol. 924, pp. 568-572, 2018.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 593-597

doi: 10.4028/p-m048qs

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-23

Revised:
2022-02-14

Accepted:
2022-03-17

Online:
2022-05-31

A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

P. Shanmugam , L. Iglesias , M. Portail , I. Dufour , D. Certon , D. Alquier , J.F. Michaud

University of Tours, GREMAN Laboratory UMR-CNRS 7347, 16 rue Pierre et Marie Curie, BP 7155, 37071 Tours Cedex 2, France

University of Bordeaux, IMS Laboratory UMR-CNRS 5218, 351 cours de la libération, 33405 Talence Cedex, France

CRHEA CNRS-UPR 10, rue Bernard Grégory, 06560 Valbonne, France

E-mail: priyadarshini.shanmugam@univ-tours.fr, luis.iglesias-hernandez@u-bordeaux.fr, marc.portail@crhea.cnrs.fr, disabelle.dufour@ims-bordeaux.fr, dominique.certon@univ-tours.fr, daniel.alquier@univ-tours.fr, jean-francois.michaud@univ-tours.fr

Keywords: Silicon carbide, 3C-SiC microcantilevers, physical gas detector, hydrogen sensor, MEMS, electromagnetic actuation and inductive detection.

Abstract

This paper demonstrates the ability of 3C-SiC microcantilevers ( ) to monitor binary gas mixture without sensitive coating. Here, 3C-SiC is chosen in particular, as the newly designed sensor will be placed in a radioactive environment. The change in gas concentration is identified using relative shifts in the cantilever's mechanical resonance frequency ( ). The presented microcantilevers work on electromagnetic actuation and inductive detection. In this paper, the fabrication process, optical characterization results using laser Doppler vibrometry and test results under a gas mixture environment are demonstrated. The presented limit of detection shows the ability of 3C-SiC- Cs to detect less than 1% of hydrogen in nitrogen, which makes them suitable for the targeted application.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

Currently, nuclear energy is the major source of electricity in many countries. In France, nuclear power plants produce three-fourth of the electricity [1]. Despite the objective of lowering nuclear energy production in France at in 2035, it is necessary to safeguard the presently generated medium active with long life (MA-LL) and highly radioactive (HA) wastes with great care. Hence, the French National Radioactive Waste Management Agency (ANDRA) has been constructing a special disposal facility, 500 m below the surface of the earth, to handle and store them properly [2]. Among these nuclear wastes, the presence of large quantities of metallic materials will lead to the formation of hydrogen gas. This is due to corrosion in an anoxic medium (corrosion by water in absence of oxygen). To mention, at concentrations between and in volume of air, is highly flammable. Therefore, monitoring the presence of concentration within this facility becomes mandatory to avoid any potential explosion.

Generally, the conventional gas sensors are coated with sensitive materials to absorb the analyte of interest. In case of sensing, it is often coated with metal like palladium or platinum [3]. The main disadvantages of these sensors are fast aging, long response time and low reliability. Therefore, the first set of microcantilevers ( ) without sensitive coating for the targeted application were fabricated with familiar silicon (Si) material. The mentioned study was used to analyze and differentiate the influence of geometries and dimensions of cantilevers in the gas environment [4]. However, the Si-based MEMS devices are not applicable to survive in hostile environments (here radioactive, high temperature and corrosive) because of their premature degradation [5-6]. Hence, we have chosen silicon carbide (SiC) to replace Si. Knowing that SiC has remarkable physical and mechanical properties over conventional materials [7-8]. After the work of Tayeb et al., we upgraded the choice of material, i.e. SiC, with proposed rectangular geometry. In our study, we choose the
cubic polytype of SiC that allows us to grow 3C-SiC(001) thin films epitaxially on cheap substrates.

The paper is divided into multiple sections, in which the first section explains the fabrication process of . Second section demonstrates the optical measurement using laser Doppler vibrometry (LDV). Finally, as a proof of concept, the gas detections were performed for low and very low concentrations of in nitrogen ( ) using inductive detection.

Fabrication of 3C-SiC Microcantilevers

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The process flow to elaborate is shown in Fig. 1. The epi-wafers used to fabricate the microcantilevers contain a m-thick 3C-SiC(001) film heteroepitaxially grown by classical two-step growth process (carbonization followed by epitaxial growth) on 2-inch substrate, with classical thickness of . In the first step (a), only alignment crosses were defined by etching 300 nm of 3C-SiC epilayer. The second step (b) involves patterning and etching of 3C-SiC epilayer, to define the cantilevers geometry. Here, the entire height of the 3C-SiC epilayer was etched, as the microcantilever will be completely made of 3C-SiC (refer Fig. 1.b). Then, a thin film of undoped silica glass (USG) was deposited and patterned. This 200 nm oxide layer insulates the substrate, i.e. , and contact metals used for detection and actuation. In step 4, gold (Au) of 300 nm was deposited for both detection and actuation metals. Moreover, a thin layer of titanium (Ti) was deposited between USG and Au to improve adhesion. Step four (d) is the final process in front-face micromachining. The last step (e) was releasing 3C-SiC- by anisotropic etching of Si(001) along (111) crystallographic direction from the rear side, using of potassium hydroxide (KOH). Further, the fabricated cantilevers were packaged on specially designed printed circuit boards (PCBs) and were taken for further characterizations in air and gas mixture environments.

Fig. 1: Systematic process flow of 3C-SiC- Cs fabrication. (a) Patterning alignment crosses, (b) defining cantilevers geometry, (c) introduction of insulation layer to separate the substrate and the metal contacts, (d) deposition of metals for inductive detection and electromagnetic actuation and (e) releasing of cantilevers from rear side by wet etching the using KOH. (f) Optical microscopic image of single 3C-SiC- showing the metal tracks of detection and actuation circuits.

Fig. 1. Systematic process flow of 3C-SiC- Cs fabrication. (a) Patterning alignment crosses, (b) defining cantilevers geometry, (c) introduction of insulation layer to separate the substrate and the metal contacts, (d) deposition of metals for inductive detection and electromagnetic actuation and (e) releasing of cantilevers from rear side by wet etching the using KOH. (f) Optical microscopic image of single 3C-SiC- showing the metal tracks of detection and actuation circuits.

Optical Characterization of 3C-SiC Microcantilevers Using LDV

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

The laser Doppler vibrometry is a non-contact assessment. The main goal of this optical characterization is to extract the mechanical resonance frequency ( ) and the quality factor ( ) of the fabricated microcantilevers. In order to perform this experiment, the cantilever beam of interest was placed under the laser source and excited using the built-in wave generator of the Polytec MSA500 vibrometer. Here, a prototype was chosen arbitrarily to carry out the first set of characterization. The selected cantilever was of square shape and has a dimension of .

By actuating the cantilever, the velocities for a range of frequencies have been measured. This was caused by Doppler shift from the reflected laser beam due to the motion at the examining area. The
cantilever working principle is based on Laplace law, where the current in the circuit, due to applied voltage ( ), induces a mechanical force ( ) in presence of a contact magnetic field ( ) imposed by the magnet, as shown in Fig. 2. This measurement confirms the electromagnetic actuation mechanism of the microcantilevers by showing a clear resonance peak at its resonance frequency ( ), for applied voltage. To mention, the detection metal track contains two different resistors, namely and . The was the reference resistor situated in the stationary part of the cantilever and was the detection resistor placed on the cantilever beam to detect change in motion by applying various gas concentrations for applied .

Fig. 2: Schematic of 3C-SiC- based hydrogen sensor without sensitive coating: a conductive gold wire is placed over the edge of the cantilever for electromagnetic actuation; the center point in detection metal track is connected to network analyser for measuring the relative change in resonance frequency for respective change in gas concentration caused by induction in the detection resistor.

Fig. 2. Schematic of 3C-SiC- based hydrogen sensor without sensitive coating: a conductive gold wire is placed over the edge of the cantilever for electromagnetic actuation; the center point in detection metal track is connected to network analyser for measuring the relative change in resonance frequency for respective change in gas concentration caused by induction in the detection resistor.

With the measured velocities, the cantilever displacement for a range of frequencies were deduced. An example illustrating this is shown in Fig. 3, for various applied voltages. The measured and calculated for the presented cantilever are 28.55 kHz and 357, respectively.

Fig. 3: Measured (a) displacement amplitude and (b) phase at various applied voltages for the selected microcantilever geometry.

Fig. 3. Measured (a) displacement amplitude and (b) phase at various applied voltages for the selected microcantilever geometry.

Testing of 3C-SiC Microcantilevers under Gas Mixture Environment

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

To perform binary gas mixture analysis, a microcantilever chip prototyped on PCB was placed in the hermetic cell, which allowed the gas to flow during measurement. After making necessary electrical connections, as shown in Fig. 4, the microcantilever was actuated at 500 mV . Then, lower concentrations of hydrogen with nitrogen were introduced in the hermetic cell. Here, was used as a reference gas. The gas flow was controlled using the LabVIEW program developed by IMS laboratory, Bordeaux. Similarly, the resulting shift in resonance frequency for changes in gas concentrations were recorded in another PC.

Fig. 4: Schematic of experimental protocol to measure the shift in resonance frequency for various gas concentrations under binary gas mixture environment, developed by IMS laboratory.

Fig. 4. Schematic of experimental protocol to measure the shift in resonance frequency for various gas concentrations under binary gas mixture environment, developed by IMS laboratory.

Firstly, the gas analysis was carried out for low concentrations of hydrogen, i.e. between and , to validate the system functionality. The results are displayed in Fig. 5.a. Here, the gas concentration was varied for every 5 min with of nitrogen to reset the measurement. After the successful measurement of in , the gas detection for very low concentrations (less than of in ) have been performed. This limit of detection result shows that the tested sensor could detect of in with non-optimized geometry and emission parameters.

Fig. 5: Obtained relative shift in resonance frequency for (a) low concentration ( to ) and (b) very low concentrations (less than ) of in with the presented geometry at of 500 mV .

Fig. 5. Obtained relative shift in resonance frequency for (a) low concentration ( to ) and (b) very low concentrations (less than ) of in with the presented geometry at of 500 mV .

Moreover, both graphs indicate that the resonance frequency increases as hydrogen concentration increases. This is because hydrogen is lighter than nitrogen. For instance, the resonance frequency will shift in the opposite direction, i.e. in negative values, for carbon dioxide in nitrogen, as is denser than . To mention, the densities of and are and respectively at standard temperature and pressure ( and 1 atm ) [9].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

The aim of the presented study was to fabricate a microsystem that can detect the presence of hydrogen in a radioactive environment. This goal has been achieved using the proposed 3C-SiC- . After fabrication, these devices were characterized in air. Primarily, optical characterization was performed with a laser Doppler vibrometer. Through this measurement, the mechanical resonance frequency and the quality factor of each cantilever was determined. Further, the concept of using 3C-SiC- as a hydrogen gas sensor without sensitive coating was validated by conducting tests under a hydrogen environment. The obtained results were very promising with a limit of detection of for in . In future, one could possibly attain a better LOD with optimized geometry and excitation parameters. Further, signal processing techniques should be incorporated to enhance the quality of the resulting signal. This set of preliminary results are promising to use 3C-SiC- as a potential gas detector in harsh environments, due to their physical properties.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

This work has been carried out within the framework of the project H2MEMS, financially supported by the French government's program "Investissements d'Avenir", operated by ANDRA, the French national agency for radioactive waste management. I also acknowledge that the presented sensors were fabricated in CERTeM technological platform.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.593.pdf

Information on https://www.world-nuclear.org/information-library/facts-and-figures/world-nuclear-power-reactors-and-uranium-requireme.aspx.

Information on .

T. Hübert et al., Hydrogen sensors - A review, Sensors and Actuators B: Chemical, 157 (2011), p. 329-352.

M. T. Boudjiet et al., Geometry optimization of uncoated silicon microcantilever-based gas density sensors, Sensors and Actuators B: Chemical, 208 (2015), p. 600-607.

R. K. Sharma et al., Investigation of stability and reliability of tin oxide thin-film for integrated micro-machined gas sensor devices, Sensors and Actuators B: Chemical, 81 (2001), p. 9-16.

D. R. Baselt et al., Design and performance of a microcantilever-based hydrogen sensor, Sensors and Actuators B: Chemical, 88 (2003), p. 120-131.

J.-F. Michaud et al., Micromachining of thin 3C-SiC films for mechanical properties investigation, MRS Proc., 1246 (2010), p. 1246.

J.-F. Michaud et al., 3C-SiC - From Electronic to MEMS Devices, in Advanced Silicon Carbide Devices and Processing, S. E. Saddow and F. La Via, ed. (InTech, 2015), p.33.

Information on .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 598-602

doi: 10.4028/p-64ey6u

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-26

Revised:
2022-03-17

Accepted:
2022-03-17

Online:
2022-05-31

Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

The original version of this paper is available on https://www.scientific.net/MSF.1062.598.pdf

Neophytos Lophitis , Peter M. Gammon , A. Benjamin Renz , Tianxiang Dai , Amit Tiwari , Tatjana Trajkovic , Philip A. Mawby , Florin Udrea , Marina Antoniou

Faculty of Engineering, University of Nottingham, Nottingham, UK

School of Engineering, Warwick University, Coventry, UK

Department of Engineering, University of Cambridge, Cambridge, UK

neo.lophitis@nottingham.ac.uk, p.m.gammon@warwick.ac.uk, a.renz@warwick.ac.uk, t.dai@warwick.ac.uk, akt40@cam.ac.uk, tt208@cam.ac.uk, p.a.mawby@warwick.ac.uk, fu@eng.cam.ac.uk, marina.antoniou@warwick.ac.uk

*corresponding author: Neophytos Lophitis

Keywords: Silicon Carbide, Edge Termination, Trench, Floating Field Rings, IGBT.

Abstract

This work presents the design methodology and performance of a compact edge termination structure aiming rated Silicon Carbide ( SiC ) devices. Standard Floating Field Rings (FFRs) for such high voltage rating SiC devices are not favored because they are inefficient in terms of the achievable breakdown voltage as a percentage of the 1D maximum, consume large chip area, require high implantation energies and small gaps between rings which can violate fabrication limits. We show that the implantation of Aluminium at the bottom of carefully positioned trenches can be analogous to deep Aluminium implantation in terms of performance, thus annulling the need for small gaps between rings and MeV ion implantation. We optimize the distribution of trenches by placing them in multiple zones of different expansion coefficient. The proposed multi expansion ratio Trench FFR termination was utilized to terminate the active area of a 10 kV rated Punch Through nIGBT having p-body and drift region. We found the to be the most optimum trench depth, achieving over 10 kV within less than of termination length.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.598.pdf

Edge termination for devices is an area of intense research. Floating Field Ring (FFR) termination is simple to process, repeatable and the effectiveness does not depend on dose variations. However, the chip area consumed at any voltage rating above 3.3 kV becomes very large, and the efficiency (achievable breakdown voltage as a percentage of the 1D maximum) reduces significantly. For example, FFRs designed for 5 kV achieved efficiency and the termination length was the drift region width [1]; FFRs for 27 kV IGBTs were only efficient and the termination length was the drift length [2]. This drop in efficiency and increase in termination length is attributable to the very shallow FFRs in SiC . The lack of impurity diffusion makes the formation of deep junctions impossible without resorting to MeV implants. Alternatively, Junction Termination Extensions (JTEs) are compact; however, compared to FFRs, JTEs have higher sensitivity to dose variations and to the presence of fixed charge. Adding multiple zones JTE rings and/or p+ rings requires extra calibration and implantation profiles but can increase the efficiency and stability [3]-[6].

We present a compact, scalable, and efficient Trench FFR termination design for rated SiC devices. The Trench FFR design proposed in this work (shown in Fig.1) is implemented for SiC n IGBTs featuring wide drift region of doping concentration [7]-[11]. The FFRs are implanted through the trench openings. An optimized electrostatic potential distribution which avoids weak points was achieved by splitting the termination in 4 zones, each having different expansion coefficient. The optimisation carried out includes the profile of the rings and the peak
concentration, the number of rings, the expansion ratio in each zone, the width and the depth of the trenches. Accurate and appropriate physics models and parameters have been used [12] to optimize the design with TCAD simulations. The results are discussed in the following section.

Fig. 1: Trench Rings edge termination design.

Fig. 1. Trench Rings edge termination design.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.598.pdf

The doping profile of the implanted p rings resulted from calibrated process simulations using Synopsys Advanced TCAD Sentaurus Process (SProcess). Fig. 2 depicts the final. The peak doping is at the bottom of the trench; it is near constant for and then reduces with depth to achieve an effective body/drift junction of depth . The selected profile helps avoid punch through and keeps the space charge at least from the . Any micro-trenches or small variations in the sidewall etching angle will be hidden/buried by the highly doped portion of the p ring, hence having very small or no impact. Device simulations were then conducted with Synopsys Advanced TCAD Sentaurus Device (SDevice) to optimise the distribution of rings and to assess the impact of trench depth and width in the achievable blocking voltage (BV). This multi-parameter, single objective optimisation procedure revealed that 65 rings implanted through trenches deep and wide can achieve efficiency; 1D PNP breakdown voltage ) when distributed in 4 expansion zones (Fig. 1), with a wide initial gap of . A smaller initial gap, and the addition of rings and Al implantations can increase the blocking ability. The dependency of BV on the trench depth for trench widths of and can be seen in Fig. 3.

Fig. 2: Aluminium distribution of implanted Trench FFRs with calibrated SProcess simulations.

Fig. 2. Aluminium distribution of implanted Trench FFRs with calibrated SProcess simulations.

The impact of trench depth on the electric field profile is shown in Fig. 4. Shallow trenches and thus shallow FFR junctions result in a spike in the electric field close to the active area as the electric field pressure cannot be alleviated by the superficial p-ring junction for the same p-rings spacing; this can be solved only by reducing the initial distance and adding more rings. Deeper trenches result in an electric field spike at the edge of the termination because lower potential drop takes place in-between the p-rings; again, this can be addressed by adding more rings hence increasing the termination area.

While adding more rings is not a challenge, reducing the initial gap is limited by the processing capabilities of the foundry. Fig. 5 depicts the electric field distribution and electrostatic potential of an optimised arrangement (trench depth and width ) at 10 kV , whereby the electrostatic potential is fully dissipated within ( the drift region width). The peak electric field remains less than throughout, and less than at the surface (the interface).

Fig. 3: Dependency of blocking voltage on the trench depth and width compared with the 1D PNP limit.

Fig. 3. Dependency of blocking voltage on the trench depth and width compared with the 1D PNP limit.

Fig. 4: Electric field (peak) distribution along the termination at 6 kV for trench depths and trench width .

Fig. 4. Electric field (peak) distribution along the termination at 6 kV for trench depths and trench width .

Although the measurements from the optimized multi expansion zone Trench FFR termination are not available yet, initial experimental results compared to simulations of non-optimised Trench FFR designs featuring identical trench widths and implantation profile but having a fixed expansion ratio are shown in Fig. 6. They validate our simulation results for the specific design and our conclusion that Trench FFRs give the highest performance. They also validate their manufacturability.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.598.pdf

FFRs are widely used in power devices due to their reliability and effectiveness. However, for rated SiC devices, they require deep junctions, or can consume large area and pose a challenge towards the fabrication of small ring spacing. By implanting aluminium at the bottom of trenches we show that the effective junction of FFRs in the edge termination region increases without the need to consult in MeV ion implantation. Trench FFRs placed in multiple zones of different expansion ratio, can be optimised to achieve over efficiency and as little as termination length to drift width ratio; while the required implantation energy is be kept low ( ), the gaps between rings and trench dimensions are kept large ( and respectively) to enhance manufacturability. To achieve the same result with conventional FFRs, the implantation energy required is over 1 MeV which results in excessive damage and the requires thick masks.

Fig. 5: Top image - Plot of electric field and electrostatic potential along a Y-cut passing through the peak E-field value (C1) and a Y-cut at the surface of the semiconductor (C2). Bottom image Electrostatic potential contours depicting the smooth 2D distribution of the electrostatic potential in the termination area. Trench depth is , width is . All dimensions are in .

Fig. 5. Top image - Plot of electric field and electrostatic potential along a Y-cut passing through the peak E-field value (C1) and a Y-cut at the surface of the semiconductor (C2). Bottom image Electrostatic potential contours depicting the smooth 2D distribution of the electrostatic potential in the termination area. Trench depth is , width is . All dimensions are in .

Fig. 6: Initial experimental results (left) compared to simulations (right) on Trench FFRs devices with (non-optimal) fixed expansion ratio.

Fig. 6. Initial experimental results (left) compared to simulations (right) on Trench FFRs devices with (non-optimal) fixed expansion ratio.

Therefore, the proposed trench rings compare well with equivalently rated JTE structures [3, 4]. Furthermore, as with standard FFRs, the rings are expected to be of highly reliable due to the low electric field in the trenches oxide and to be largely independent of dose variations.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.598.pdf

W. Sung and B. J. Baliga, "A Comparative Study 4500-V Edge Termination Techniques for SiC Devices," IEEE Trans. Electron Devices, vol. 64, no. 4, Apr. 2017, doi: 10.1109/TED.2017.2664051.

E. Van Brunt, L. Cheng, M. J. O'Loughlin, J. Richmond, V. Pala, J. Palmour, C. W. Tipton, C. Scozzie, E. Van Brunt, L. Cheng, M. J. O'Loughlin, J. Richmond, V. Pala, J. Palmour, C. W. Tipton, C. Scozzie, E. Van Brunt, L. Cheng, M. J. O’Loughlin, et al., " 27 kV, 20 A 4H-SiC nIGBTs," in Materials Science Forum, 2015, vol. 821, pp. 847-850. doi: 10.4028/www.scientific.net/MSF.821-823.847.

W. Sung, E. Van Brunt, B. J. Baliga, and A. Q. Huang, "A New Edge Termination Technique for High-Voltage Devices in 4H-SiC-Multiple-Floating-Zone Junction Termination Extension," IEEE Electron Device Lett., vol. 32, no. 7, Jul. 2011, doi: 10.1109/LED.2011.2144561.

G. Feng, J. Suda, and T. Kimoto, "Space-Modulated Junction Termination Extension for Ultrahigh-Voltage p-i-n Diodes in 4H-SiC," IEEE Trans. Electron Devices, vol. 59, no. 2, Feb. 2012, doi: 10.1109/TED.2011.2175486.

S. Perkins, M. Antoniou, A. K. A. K. Tiwari, A. Arvanitopoulos, K. N. N. Gyftakis, T. Trajkovic, F. Udrea, and N. Lophitis, "Optimal edge termination for high oxide reliability aiming 10kV SiC n-IGBTs," in 2019 IEEE 12th International Symposium on Diagnostics for Electrical Machines, Power Electronics and Drives (SDEMPED), Aug. 2019, pp. 358-363. doi: 10.1109/DEMPED.2019.8864919.

X. Deng, L. Li, J. Wu, C. Li, W. Chen, J. Li, Z. Li, and B. Zhang, "A Multiple-Ring-Modulated JTE Technique for 4H-SiC Power Device with Improved JTE-Dose Window," IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 5042-5047, 2017, doi: 10.1109/TED.2017.2761995.

A. K. Tiwari, F. Udrea, N. Lophitis, and M. Antoniou, "Operation of ultra-high voltage (&gt; 10 kV ) SiC IGBTs at elevated temperatures: benefits &amp; constraints," in 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2019, pp. 175-178. doi: 10.1109/ISPSD.2019.8757586.

A. K. Tiwari, M. Antoniou, N. Lophitis, S. Perkin, T. Trajkovic, and F. Udrea, "Retrograde pWell for Class SiC IGBTs," IEEE Trans. Electron Devices, vol. 66, no. 7, pp. 30663072, Jul. 2019, doi: 10.1109/TED.2019.2918008.

A. K. Tiwari, M. Antoniou, N. Lophitis, S. Perkins, T. Trajkovic, and F. Udrea, "Performance Improvement of &amp;gt; 10 kV SiC IGBTs with Retrograde p-Well," Mater. Sci. Forum, vol. 963, pp. 639-642, Jul. 2019, doi: 10.4028/www.scientific.net/MSF.963.639.

A. K. Tiwari, S. Perkin, N. Lophitis, M. Antoniou, T. Trajkovic, and F. Udrea, "On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well," in 2019 IEEE 12th International Symposium on Diagnostics for Electrical Machines, Power Electronics and Drives (SDEMPED), Aug. 2019, pp. 351-357. doi: 10.1109/DEMPED.2019.8864804.

S. Perkins, M. Antoniou, A. K. Tiwari, A. Arvanitopoulos, T. Trajkovic, F. Udrea, and N. Lophitis, " 4H-SiC n-IGBTs for Elevated Temperature Environments," 14th Int. Semin. Power Semicond. (ISPS 2018), 2018.

N. Lophitis, A. Arvanitopoulos, S. Perkins, and M. Antoniou, "TCAD Device Modelling and Simulation of Wide Bandgap Power Semiconductors," in Disruptive Wide Bandgap Semiconductors, Related Technologies, and Their Applications, Y. K. Sharma, Ed. Rijeka: InTech, 2018. doi: 10.5772/intechopen. 76062.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 603-607

doi: 10.4028/p-4vc4yb

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-06

Revised:
2022-03-21

Accepted:
2022-03-22

Online:
2022-05-31

Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

The original version of this paper is available on https://www.scientific.net/MSF.1062.603.pdf

Sofia Aslanidou , Alberto García-García , Gemma Rius and Philippe Godignon

1Institute of Microelectronics of Barcelona, IMB-CNM, CSIC, 08193 Bellaterra, Spain

Universitat Autònoma de Barcelona, UAB, 08193

Bellaterra, Spain

sofia.aslanidou@imb-cnm.csic.es, alberto.garcia@imb-cnm.csic.es,

gemma.rius@imb-cnm.csic.es, philippe.godignon@imb-cnm.csic.es

Keywords: epitaxial graphene, silicon carbide, bottom gate, field-effect transistor (FET), electronic devices

Abstract

Current electronics technology increasingly demands higher integration, flexibility, higher efficiency, and performance aspects such as compatibility with higher temperature operation of the semiconductor devices, which may find limitations when silicon is used. The superior intrinsic properties of SiC, eventually combined with the ability of growing monolithically epitaxial, high quality graphene on a SiC wafer (1), makes it a reliable alternative for some electronic applications, such as field effect transistors (FET), radio frequency (RF) power amplifiers, integrated circuits (IC), or sensors. In this work, we describe the fabrication and preliminary electrical characterizations of epitaxial graphene (EG) on a SiC substrate FET devices based on an alternative back gate architecture. We propose a new approach in which the FET device is built on a off-axis cut, doped substrate (the back gate) with, on top of, it a semi-insulating homoepitaxial layer of SiC compensated with vanadium (the dielectric layer). EG will be used as FET conduction channel. Using this V-compensated dielectric layer is aimed to minimize effects on the FET characteristics such as from defects in the SiC crystal, especially below the FET active areas, which would have occurred when using ion implantation to create a buried gate. The EG film was grown by the high temperature Si sublimation method under an Ar ambient. Raman spectroscopy, Atomic Force Microscopy (AFM) and Scanning Electron Microscopy (SEM) were applied in the structural characterization of epigraphene. The lack of D-peak in Raman spectra, together with SEM and AFM images, indicate that high quality monolayer to few layer epitaxial graphene fully covering the SiC surface is deposited. The electrical characteristics of the EG channel-devices and the functionality of the bottom gate were examined with 2-probe and 4-probe method. The electrical properties of the FET devices were also investigated with 3 terminal configuration.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.603.pdf

For more than 5 decades, Moore's law has dictated the advancements in silicon technology. (2) However, the progressive demand for electronic devices with different performance capabilities, integration issues or higher efficiency, generated the need of new semiconductor materials to substitute or complement silicon-based electronics. Silicon carbide, SiC, is a foremost alternative as it combines unique physical and chemical properties, furthermore with the possibility of an monolithic, epitaxial growth of, high quality graphene on the SiC surface. Field effect transistors (FET), radio frequency (RF) power amplifiers and sensors are some of the promising electronic applications of epigraphene (EG) on SiC substrates. (1)
In this work, we describe the fabrication and preliminary electrical characterizations of EG FET devices on SiC substrate based on an alternative back gate architecture. The novelty of our approach is the use of a new material, the SiC doped substrate with the semi-insulating homoepitaxial layer, for the realization of back gated EG FET devices, towards high performance and low losses due to
leakage. Actually, in a previous work (3), the EG FET gate bias was based on using high-energy nitrogen implantation to form a buried N+layer below the FET graphene channel. However, those devices exhibited high leakage current due to the damage generated in the SiC crystal by the implantation process, thus, here we want to eliminate this element by an alternative structure which exploits an advanced film recently enabled in the SiC electronic materials manufacturers (4).

Materials and Methods

The original version of this paper is available on https://www.scientific.net/MSF.1062.603.pdf

The fabrication of this novel monolithic bottom gate architecture is based on a off-axis cut doped substrate, which acts as the back gate. On top of the substrate is a semi-insulating homoepitaxial layer of SiC compensated with vanadium, an innovative material that serves as the dielectric layer. This homoepitaxial layer was grown by chemical vapor deposition by II-VI Incorporated. (4) Photolithography patterning and Reactive Ion Etching (RIE) were implemented for the patterning of the areas to be selectively implanted with N. Ion implantation in SiC depends on many parameters that may affect significantly the crystal and its properties. (5) (6) For this reason, simulations for the depth distribution of the nitrogen dopants as a function of the implantation dose, were performed and showed that the optimal thickness of the selectively implanted area was 300 nm for a doping level of . As a result, the areas that we wanted to operate as vertical conductive channels, should be firstly etched so we could reach the doped substrate (back gate). The dopant activation was a termal annealing at with a protective capping layer in order to prevent Si desorption from the SiC surface. EG was grown by high temperature Si sublimation method, in particular at under an Ar ambient flow. The structural characterization of epigraphene was performed by AFM, SEM and Raman Spectroscopy. For the fabrication of FET devices, e-beam Lithography (EBL) plus RIE was used to pattern the graphene channels. EBL was also used for the patterning of electrical contacts, in combination with thin film metal evaporation ( ) followed by resist lift off. In order to understand accurately the gate functionality, a reference sample without EG was also fabricated. In this case, Ni was sputtered as a metal contact on top of the selectively implanted areas as well as the backside of the sample. The complete architecture of our samples is shown as a cross-section scheme in Fig. 1 along with an SEM cross section image of the layers stack at the implanted area in the reference sample. The latter displays a Ni metal contact, instead of the used in EG samples. For device evaluation, the electrical characteristics of the bottom gate and the graphene FET devices were tested.

Figure 1: Cross-sectional scheme of our new approach of an EG FET device. Darker grey thin film on top of the homoepitaxial SiC layer is the patterned EG to be used as FET conduction channel. With a closer look on the implanted area of the reference sample we can see in the cross section SEM the distinctive layers of the homoepitaxy, selective implantation and gate metal contact.

Figure 1. Figure 1: Cross-sectional scheme of our new approach of an EG FET device. Darker grey thin film on top of the homoepitaxial SiC layer is the patterned EG to be used as FET conduction channel. With a closer look on the implanted area of the reference sample we can see in the cross section SEM the distinctive layers of the homoepitaxy, selective implantation and gate metal contact.

Results

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Firstly, we provide the structural characterization of the sample. AFM and cross-sectional SEM shown in Fig. 2 and Fig. 3, respectively, confirm that RIE step between the implanted and nonimplanted area is . Differences in the surface smoothness (step bunching due to EG growth) can be seen (Fig. 2). Epitaxial graphene was also characterized by SEM and AFM which showed an homogeneous and complete cover of the step-structured SiC . By AFM phase signal displaying, we can also identify the distinctive graphene wrinkles across the step edges of the SiC terraces (Fig.4). The EG quality and the number of graphene layers were analyzed by Raman Spectroscopy. The Raman spectra show a very low D peak, thus, indicating the pristine graphene quality, as its intensity would increase with the presence and amount of both structural and chemical defects. Moreover, by Raman mapping several large areas (typically ), we showed that the films consist in single layer EG stripes, as for example the bright yellow stripe of Fig.5, surrounded by few layer graphene.

Figure 2: AFM topography image and section of the etching step transversal to the SiC steps/terraces. (Scan size: , z-scale: ). RIE step depth confirms that intended conductive channel thickness of could be implemented. Smaller and narrower terraces also formed on both implanted and non implanted areas with no significant differences.

Figure 2. Figure 2: AFM topography image and section of the etching step transversal to the SiC steps/terraces. (Scan size: , z-scale: ). RIE step depth confirms that intended conductive channel thickness of could be implemented. Smaller and narrower terraces also formed on both implanted and non implanted areas with no significant differences.

Figure 3: Cross section SEM image showing the etching step between the implanted and non implanted area.

Figure 3. Figure 3: Cross section SEM image showing the etching step between the implanted and non implanted area.

Figure 4: SEM Image of the EG homogeneously and fully covering the terrace/step-structured SiC surface. Detail of the EG material can be seen by Phase signal AFM Imaging (Scan size: , z-scale: ), particularly the characteristic EG wrinkles across the SiC steps and terraces.

Figure 4. Figure 4: SEM Image of the EG homogeneously and fully covering the terrace/step-structured SiC surface. Detail of the EG material can be seen by Phase signal AFM Imaging (Scan size: , z-scale: ), particularly the characteristic EG wrinkles across the SiC steps and terraces.

Figure 5: Exemplary Raman Spectrum (Left) with the characteristic graphene peaks ( ) and Raman Mapping (Right) showing a single layer graphene stripe, presented in bright yellow, surrounded by few layer graphene, the darker red areas.

Figure 5. Figure 5: Exemplary Raman Spectrum (Left) with the characteristic graphene peaks ( ) and Raman Mapping (Right) showing a single layer graphene stripe, presented in bright yellow, surrounded by few layer graphene, the darker red areas.

The functionality of the back gate and the vertical conductive channels were examined by electrical testing with 2- and 4-probe methods at room temperature. The electrical testing in the reference sample shows Ohmic behaviors. Applying the transfer length method (TLM) measurements, we applied current in the back gate contacts from the sample top side increasing the spacing between them, we could plot the total resistance versus contact spacing d . From these results the contact resistance (Rc) was obtained by extrapolation and is estimated at as shown in Fig.6.

Figure 6: TLM measurements contacting the back gate metal contacts for the study of the buried gate actuation. Plotting RT as a function of d allows the estimation of Rc by extrapolation at .

Figure 6. Figure 6: TLM measurements contacting the back gate metal contacts for the study of the buried gate actuation. Plotting RT as a function of d allows the estimation of Rc by extrapolation at .

Finally, the fabricated FETs were as well electrically tested. Although no lateral leakage current was detected, the vertical leakage current across the insulating epilayer becomes important, in the order of , after an applied gate voltage of . The semi-insulating homoepitaxial layer shows a rectifying behavior, where dominates the leakage current and there is no gate bias-induced charge carrier modulation of the EG channel.

Summary

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An alternative monolithic bottom gate architecture for the fabrication of EG-FETs is proposed with the use of a novel material, a homoepitaxial layer of SiC compensated with Vanadium (insulating) on top of a doped SiC substrate (conductive). This approach eliminates the implantation-induced defects in the SiC crystal, potentially better-preserving the high quality of epigraphene. The electrical characteristics of the back gate proved the functionality of the gate and the selectively implanted conductive vertical channels. However, from the electrical testing of the gate, leakage current from the homoepitaxial layer of SiC compensated with Vanadium was detected, affecting the operation of the FETs. The loss of insulating properties of the homoepitaxial layer is attributed to the two applied
high temperature two annealing steps implied in the fabrication processes, specifically, the activation of the dopants and the epitaxial graphene growth. As a result adjustments are needed, for example the use of a single thermal annealing step for both processes could preserve the epilayer's properties. Furthermore, the functionality of the gate and the performance EG FET devices in low temperatures are being studied and the results will be reported in the near future. Based on this architecture more sophisticated devices such as doubly-gated EG-FET devices can be realized.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.603.pdf

This work was supported by DOC-FAM project, which has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No 754397. G.R. acknowledges Ayudas Ramon y Cajal Grant Ref. RYC-2016-21412.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.603.pdf

Gemma Rius, Philippe Godignon. Epitaxial Graphene on Silicon Carbide: Modeling, Characterization, and Applications. s.1. : Jenny Stanford Publishing, 2018.

Moore, Gordon E. Cramming More Components onto Integrated Circuits. Electronics. 1965, Vol. 38, 8, pp. 114-117.

B. Jouault, et al. Quantum Hall effect in bottom-gated epitaxial graphene grown on the C-face of SiC. Applied Physics Letters . 2012, Vol. 100.

Ilya Zwieback, et al. Vanadium Doped SiC Single Crystals and Method Thereof. US20140234194A1 [ed.] II-VI INCORPORATED. 2013.

Philippe Godignon, Frank Torregrosa and Konstantinos Zekentes. Silicon Carbide Doping by Ion Implantation. Materials Research Foundations. 2020, Vol. 69, pp. 107-174.

Fabrizio Roccaforte, Filippo Giannazzo and Giuseppe Greco. Ion Implantation Doping in Silicon Carbide and Gallium Nitride Electronic Devices. Micro. 2022, Vol. 2, pp. 23-53.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 608-612

doi: 10.4028/p-23d7ab

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-12-04

Revised:
2022-02-24

Accepted:
2022-03-17

Online:
2022-05-31

Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

The original version of this paper is available on https://www.scientific.net/MSF.1062.608.pdf

O. Karker , K. Zekentes , A. Bouchard , I. Gélard , X. Mescot , V. Stambouli , E. Bano

IMEP-LaHC, Univ. Grenoble Alpes, CNRS, Grenoble INP, F-38000 Grenoble, France

LMGP, Univ. Grenoble Alpes, CNRS, Grenoble INP, F-38000 Grenoble, France

MRG-IESL/FORTH, Vassilika Vouton, PO Box 1385 Heraklion, Greece

olfa.karker@grenoble-inp.fr, konstantinos.zekentes@grenoble-inp.fr, aude.bouchard@grenoble-inp.fr, xavier.mescot@imep.grenoble-inp.fr, falerie.stambouli-sene@grenoble-inp.fr,

Keywords: Silicon carbide, biosensor, TCAD simulation, DNA, NWFET

Abstract

A SiCNWFET device serving as a biosensor was designed and simulated using Silvaco ATLAS device simulation software. The performance of the designed device in charges sensing was investigated. The device shows the ability to recognize different interface charge values ranging from -1.10 E 11 to applied on the surface of the silicon carbide nanowire channel to simulate target charge biomolecules that are bound to the biosensor. A significant change in the output current is observed due to the presence of different values of fixed interface charge densities. An optimum, according to the TCAD simulation, the epitaxial structure has been grown. The designed device was fully fabricated on this structure and it exhibited acceptable electrical characteristics.

Introduction

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Field-effect transistors based on Silicon nanowires (SiNWFET) have been intensely developed over the last decades and have proved major promise in label-free, real-time, selective and highly sensitive electrical measurements for biosensing applications [1]. However, problems in terms of result reproducibility still exist. Notably, SiNWs suffer from a lack of long-term chemical stability in physiological environments resulting in drastic signal drift and changes in the signal-noise ratio [2]-[4]. In this regard, SiC semiconductor is the complete alternative material of choice. SiC is particularly attractive for highly sensitive devices owing to its chemical inertness in harsh environments and its biocompatibility. To show the utility of these devices as a biosensor, this paper focuses first on the wafer design and the TCAD Silvaco simulation results in terms of electrical characteristics as a SiCNWFET and then as a biosensor detecting charged molecules. The second part comprises the device process fabrication and the electrical characterisation results. In the conclusion, the characteristics of the device are discussed and the results are summarized.

Biosensor Layout

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The layout of the biosensor is shown in Figure 1. For reasons of statistical investigations of the biosensor performances, many identical FET devices are needed to be incorporated. The device is divided into four separated microwires groups. Each group contains eighteen microwires of different width sizes ( and ) (Figure 1). We choose to fabricate microwires instead of nanowires as it is based on conventional lithography which is non-time consuming, nonexpensive and the most accessible technique. Later on, different SiC micro and nanowires will be
fabricated to experimentally reveal the effect of the nanowire size, number and shape parameters on the sensitivity of our developed SiC-based biosensor. Biosensors with this design have been fabricated with Si core/a-SiC shell [5] as FET material. In the present paper, 4H-SiC is considered as material for the FET fabrication. Source and drain contacts are localized on each SiC microwire extremity and the corresponding metal lines are extended to the device edges as metal pads.

Figure 1: Top view schematic of a device with identical SiC-NR/NW biosensing FETs

Figure 1. Figure 1: Top view schematic of a device with identical SiC-NR/NW biosensing FETs

Wafer Design and the TCAD Silvaco Simulation

The original version of this paper is available on https://www.scientific.net/MSF.1062.608.pdf

Epitaxial Structure

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The polytype has been chosen for the development of the devices. The is one of the most readily grown and can be easily purchased on the market. Furthermore, the bare SiC surface and not the one has been adopted as a sensing surface mainly due to the poor quality of the interface. Figure 2 shows the schematic of the designed SiC epitaxial wafer, the doping concentration ( )
and the thickness of each epitaxial layer. The structure design has been based on SiC MESFET bibliography, on basic

Figure 2: Schematic of the designed full SiC epitaxial wafer

Figure 2. Figure 2: Schematic of the designed full SiC epitaxial wafer

analytical calculations by taking into account charge density to be detected and on the verification of analytical calculation results by |TCAD simulations. A p-type buffer layer is introduced on the top of the n-type conductive substrate to shield the substrate and thus measure the current in the active region of the device (channel). The channel is fabricated from an n-type 4H-SiC epitaxial layer. The topmost layer of the structure is heavy-doped n for ohmic contact formation purposes.

TCAD simulation

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Before proceeding to the device fabrication, the TCAD-Silvaco-ATLAS tool was used to design the 4H-SiC-nanoribbon/nanowire NR/NW biosensing FET. The size of the simulated SiC microwire is as follow: in length, in width and thickness of . The device was simulated to observe and validate the electrical characteristics before and after its configuration as a biosensor for negatively charged species detection. Figure 3 shows a schematic of the simulated device structure. According to the simulations, the applied negative (to the back-gate or substrate) results in a

Figure 3: 3D structure of the simulated device showing the negative fixed charges equivalent to the bounded DNA molecules on the top of the SiC microwire. the latter forms a "pseudo-gate".

Figure 3. Figure 3: 3D structure of the simulated device showing the negative fixed charges equivalent to the bounded DNA molecules on the top of the SiC microwire. the latter forms a "pseudo-gate".

depletion layer formation at the interface between the n - SiCNW channel and the epi-layer, resulting in a controlled magnitude of the output current. Then, several negative interface charge densities were introduced on the surface of the n-type SiC-NW/NR to mimic the targeted deoxyribonucleic acid (DNA) captured by the biosensor (Figure 4). Figure 4 shows the simulated IDS versus characteristic before and after the introduction of the . The back gate voltage was fixed at -1 V , the minimum value to lightly deplete the n - channel in a way to let a sufficient amount of the majority electron carriers interact with the pseudo front gate (the target charged molecules).
Based on the results shown in Figure 4, the negatively repulsed the electron carriers below the n type SiC-NR/NW to form a depletion layer inside the channel, causing a decrease in drain current . The increase of the applied negative charge density had allowed for less drain current to flow across the channel between source and drain region. Thus, the sensitivity as defined Inorm [6] (where I and are respectively the drain current value with and without target charged molecules on the channel surface) is validated (Figure 4, right).

Figure 4: (left) Electrical characteristics in terms of versus for SiC-NW/NR-FET biosensor at fixed back-gate voltage -1 V and when applied different surface charge density ( ) values of and , (right) sensitivity curve of the simulated biosensor in terms of normalized current ( ) versus negative interface charge densities

Figure 4. Figure 4: (left) Electrical characteristics in terms of versus for SiC-NW/NR-FET biosensor at fixed back-gate voltage -1 V and when applied different surface charge density ( ) values of and , (right) sensitivity curve of the simulated biosensor in terms of normalized current ( ) versus negative interface charge densities

Biosensor Processing

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Only two mask steps (source and drain regions and contacts, SiC microwires) are used to fabricate the SiC-NR/NW biosensing FET device. The source and drain regions were etched from the top layer using RIE and mask. The mask was kept for forming ohmic contacts on the source and drain. The SiC microwires were etched from the n- SiC layer under an Al mask using RIE. At the end of the process, the Al mask is etched selectively with respect to the contacts using a solution. The contacts were annealed at for 2 min inside a rapid thermal annealing chamber RTA.

Electrical Characterisation

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The initial electrical characterisation of the as-fabricated devices was performed under ambient conditions using a manual probe station. First, in Figure 5 (left) the transfer characteristic (logarithmic scale) in terms of IDS- of a device was measured at a fixed . The device shows typical FET device electrical characteristics, good control of the channel conductivity through the back gate and low leakage current (Ig). Figure 5 (right) shows characteristics at different negative V GS. The off-current of the device is in the order of pA which yields a good Ion/Ioff ratio of approximately 4 orders of magnitude.

Figure 5: (left) Transfer characteristic ID (axis 1) and IG (axis 2) versus back-gate voltage VBG for , (right) Output characteristic drain current IDS versus drain voltage for different negative values of , (SiC wire dimensions/SiC channel: )

Figure 5. Figure 5: (left) Transfer characteristic ID (axis 1) and IG (axis 2) versus back-gate voltage VBG for , (right) Output characteristic drain current IDS versus drain voltage for different negative values of , (SiC wire dimensions/SiC channel: )

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.608.pdf

We have demonstrated the design, fabrication and operation of a -microwire FET based biosensing device. The device was simulated as a biosensor showing its ability to perform biomolecules detection where charged molecules (DNA) bound on the SiC surface can control the device channel conduction. A simplified fabrication process of the device was implemented. The fabricated device shows proper electrical characteristics.

In conclusion, the designed and fabricated FET device is introduced as a biosensor. We take advantage of the excellent SiC properties, such as biocompatibility, its semiconducting characteristics and its compatibility with the CMOS technology fabrication processes to realize this innovative application. This, together with the fact that the wafers are commercially available, shows that the SiC is an excellent candidate for the development of highly reliable nanosensing devices for environmental and emerging biochemical sensing applications.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.608.pdf

The authors would like to thank all the PTA technical team for their support during the training on the cleanroom equipment and also their advice for the success of the process fabrication. Special thanks to the research team at FORTH-Crete for their continuing support and expertise. Many thanks to Marcin Zielinski and NOVASiC for providing the SiC wafers.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.608.pdf

K. I. Chen, B. R. Li, and Y. T. Chen, "Silicon nanowire field-effect transistor-based biosensors for biomedical diagnosis and cellular recording investigation," Nano Today, vol. 6, no. 2, pp. 131-154, 2011.

A. Peled, A. Pevzner, H. P. Soroka, and F. Patolsky, "Morphological and chemical stability of silicon nanostructures and their molecular overlayers under physiological conditions: towards long-term implantable nanoelectronic biosensors," Journal of Nanobiotechnology, pp. 1-11, 2014.

W. Zhou, X. Dai, T. Fu, C. Xie, J. Liu, and C. M. Lieber, "Long Term Stability of Nanowire Nanoelectronics in Physiological Environments," Nano Lett., vol 14, pp. 1614-1619, 2014.

R. Bange, E. Bano, L. Rapenne, S. Labau, and B. Pelissier, "Chemical Stability of Si-SiC Nanostructures under Physiological Conditions," vol. 897, pp. 638-641, 2017.

Romain BANGE, "Réalisation et optimisation de biocapteurs à base de nanostructures SiC pour la détection électrique d'ADN", PhD thesis, 2019.

B. M. Lowe, K. Sun, I. Zeimpekis, C. K. Skylaris, and N. G. Green, "Field-effect sensorsfrom pH sensing to biosensing: Sensitivity enhancement using streptavidin-biotin as a model system," Analyst, vol. 142, no. 22. Royal Society of Chemistry, pp. 4173-4200, Nov. 21, 2017.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 613-618

doi: 10.4028/p-vms03o

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-25

Revised:
2022-02-28

Accepted:
2022-02-28

Online:
2022-05-31

Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

The original version of this paper is available on https://www.scientific.net/MSF.1062.613.pdf

Ali Ammar , Luong Viet Phung , Dominique Planson , Herve Morel and Camille Sonneville

Univ Lyon, INSA Lyon, Université Claude Bernard Lyon 1, Ecole Centrale de Lyon, CNRS, AMPERE, F-69621, Lyon, France

ali.ammar@insa-lyon.fr, luong-viet.phung@insa-lyon.fr, dominique.planson@insa-lyon.fr, herve.morel@insa-lyon.fr, camille.sonneville@insa-lyon.fr

Keywords: Bipolar Power Devices, Silicon Carbide, Junction Termination Extension, High Electric Field, TCAD Modeling

Abstract

An optimized termination extension tutorial is reported for a small area ( ) 4 H -SiC NPN BJT. The extension system is based on a parametric JTE with isolation rings. Additional aspects such as (1) MESA angle, (2) relieving electric field on the base-drift junction, and (3) blocking the electric field from reaching border structure are investigated. A breakdown voltage greater than 10 kV is recorded, when drift region is n -doped to .

Introduction

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4H-SiC power bipolar devices are considered one of the most reasonable candidates for low-loss and high power semiconductor devices when compared to Silicon (Si) due to (1) a high bandgap allowing it to reach a low intrinsic carrier density even when operating over high temperatures (greater than ) [1], (2) a high saturation drift velocity enabling the operation over high frequencies, and (3) a huge breakdown electric field resulting in the reduction of ON resistance ( ) plus avoiding a second breakdown avalanche effect [2]. Similarly, 4 H -SiC power BJTs, are free from gate oxide problems giving it the ability to sustain high currents with low-voltage drop when compared to SiC MOSFETs [3]. Since BJTs are current controlled devices, making it a disadvantage over MOSFETs, an input drive current is needed on the base terminal in the on-state operation mode leading to an increase in the total power dissipation of the device, thus it is always useful to maximize the current gain in BJTs. The recent reported high voltage 4 H -SiC BJTs include a 10 kV open-base breakdown voltage (BV ) and specific on-resistance of at (RT) with a -doped drift layer [4]; a at a leakage current of with drift layer n -doped to [5], and a 9.2 kV BV with a -doped drift layer and [6]. For high electric field bipolar applications, it is mandatory to implant a highly sophisticated base-drift junction termination extension (JTE) system, which serves in minimizing the electric field plate crowd generated at the MESA edge of the power device. Several approaches were applied to optimize the extension performance; (1) by applying variations over the length and etching depth of the JTE [7], (2) by implanting different doses over the total length of the JTE [8], and (3) by the addition of extra implanted rings [9]. This paper presents different design methodologies for high-voltage SiC BJT termination for obtaining both high-open-emitter (BV ) and high open-base (BV CEO) breakdown voltage greater than 10 kV based on simulation measurements done using Synopses TCAD [10]. The realized results are relative to several technical models associated to the SiC simulation parameters given by TCAD, which were used as follows: Arora model for Doping Dependence., Caughey-Thomas model for High Field Dependence, Scharfetter and VanOverstraetendeMan used for Recombination and Impact Ionization models, and finally Bandgap Narrowing for the band gap model.

SiC BJT Termination Model and Technology

The original version of this paper is available on https://www.scientific.net/MSF.1062.613.pdf

Figure 1: Schematic cross-sectional view of a BJT structure with optimized termination

Figure 1. Figure 1: Schematic cross-sectional view of a BJT structure with optimized termination

Figure 1 represents an illustration of a NPN optimized BJT structure. The structure is built with a -doped collector layer. The lowly n-doped drift layer has a thickness of 120 and a doping concentration . The base layer is p -doped to , with 400 nm highly implants under the base contacts to ensure a low resistive ohmic contact. The emitter layer is n -doped to meeting another highly n -doped emitter contact layer. Theoretically, the highest breakdown voltage of a PN junction with such drift parameters can reach to 14 kV according to Equation 1, where BV represents the blocking voltage in volts, is maximum electrical field that SiC can sustain in V/cm, is the dielectric permittivity of the semiconductor material, and is the doping concentration of the drift region in .

The thickness of the epitaxial layer also influences the breakdown voltage, since the electrical field can be expressed as follows:

where is the drift thickness in meters, giving another form of the blocking voltage:

From Equations 1 and 3, we realize that increasing , and decreasing , both serve in increasing the blocking voltage. This feature can be observed in [8], where the highest breakdown voltage for a BJT to-date is recorded 21 kV . This lab in Kyoto University/Japan, in addition to an optimized termination extension and a proper fabrication process, was able to reach this value with a very low and a greater than . Putting these values in Equation 1, a maximum theoretical breakdown voltage up to 50 kV can be obtained, which is considered far from the recorded results. Normally, it is impossible to reach the theoretical breakdown due to electric field crowding close to junction edges, but research is always working to get near this value by optimizing the termination extension. Figure 1 describes several approaches when designing an optimized extension. From geometrical point of view, fabrication of MESA structures with negative inclination aid in
avoiding problems such as edge breakdown due to a significant reduction of electric field when compared to the bulk one [12].

Figure 2, shows the electric field behavior of same BJT structure but with different MESA angles. An increase in the angle reduces the electric field crowding generated on the junction. Relieving this electrical field crowding effect is also done by implanting isolation rings. These rings can be capped along the JTE as in Figure 1 and integrated at the edge of structure with an ohmic contact performing a PN isolation diode as described in [13].

Figure 2: Electrical field (EF) distribution at MESA with various angle : (a) , (b)

Figure 2. Figure 2: Electrical field (EF) distribution at MESA with various angle : (a) , (b)

Figure 3: Electrical field (EF) behavior at device border: (a) without stopping channel, (b) with SC.

Figure 3. Figure 3: Electrical field (EF) behavior at device border: (a) without stopping channel, (b) with SC.

The efficiency of the JTE is influenced by parameters such as the length ( ), and the implanted dose ( ). The idea is to provide a smooth flow for the electric field by choosing the suitable dose given for the implanted JTE along its length. The chosen dose should be relative to the base doping concentration, for permitting a continuous flow all over the structure. The thickness of the JTE is limited and fixed to , as we vary the dose.

Moreover, is it possible to complete the extension by adjoining rings with the same dose and thickness associated to the JTE (Figure 1). The performance of the rings is relative to their number ( ) and the space given between them ( ), which may vary between each ring. The rings length ( ) which is not considered a critical parameter is fixed to . The number of rings with their associated spaces plus the determines the overall length of the termination system. This length is important when dealing with small sized structures.

In normal cases, no electric field crowd should be present at the edge of the structure, and hence an isolation length should be given after the given extension system. For small structures, where no to little space is available, a highly -doped stop channel can be added after the termination extension (Figure 1) in order to prevent the lateral electric field from reaching the chip edge which is a phenomenon where capability of breakdown voltage decreases as shown in Figure 3.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.613.pdf

Table 1 describes three different general small BJT structures with different designs. Structure 1 as mentioned before refers to an unoptimized device and will be used as a reference. The BV recorded is nowhere from reaching the 10 kV , with a of enhancement due to the absence of JTE and Rings. Structure 2 is built just with a JTE. Several lengths between and were tested with different doses in order to detect the optimum length and dose that match the base doping we have. No rings are integrated in this structure and the recorded BV is increased by since the breakdown voltage obtained is almost triple the one we got from structure 1, translating the ability of peripheral protection to get closer to the theoretical 1D target. After dealing with the JTE parameters, an isolation ring system is added to structure 3 with constant spacing between them. This structure burdened more the electrical field and hence increased significantly the efficiency of the system to reach up to . Finally, referring to the electrical field profile shown in Figure 4 we can clearly notice the importance and potential of adding a JTE and ring system on the electric field. The continuous curve in Figure 4 refers to the electric field associated to structure 1. We realize the peak of the curve is located immediately at the base-drift junction, and then the field sharply vanishes, which explains the low breakdown voltage with such a structure. Paradoxically, the dashed curve represents an optimized structure. We notice how the electric field is distributed all over the structure. The first two peaks of this field determine the starting and ending point of the JTE, while the following ones represent the electric field on each ring border to reach the last one. It is highly recommended to conserve or keep the same electric field along the border of the JTE and rings, in other words; keeping the same level for each peak. This phenomenon also affects the ability of increasing the breakdown voltage and it is controlled by the number and space given between each ring.

Table 1: Variation of breakdown voltage as function of structure design

Structure
JTE
LJTE [μm]
DJTE [x10¹³ cm⁻²]
NRings
BVCBO
[kV]

1
Absence ✖
Absence ✖
Absence ✖
Absence ✖
Absence ✖
3

2
Presence ✓
LJTE ∈ [250, 500]
DJTE ∈ [0.8, 1.5]
Absence ✖
Absence ✖
9

3
Presence ✓
LJTE ∈ [250, 500]
DJTE ∈ [0.8, 1.5]
NRings ∈ [1, 8]
12.6

Figure 4: Variation of electrical field as a function of JTE and Rings presence

Figure 4. Figure 4: Variation of electrical field as a function of JTE and Rings presence

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.613.pdf

A high power, with small area 4 H -SiC NPN bipolar transistor structure with optimized termination extension was investigated in this paper. The termination is highly effective and efficient. A targeted breakdown voltage was reached with a proper electric profile all over the structure. A final structure was ended up with specific parameters where the breakdown voltage recorded is 12.6 kV which forms from the theoretical value ( 14 kV ) with drift thickness n -doped to . Additional points were discussed concerning high doped implanted rings to decrease the electric field peak at the base-drift junction, and highly doped stopping channel for the aim of blocking high electric field on the edge of the structure.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1062.613.pdf

This work was supported by a grant overseen by the French National Research Agency (ANR), the project HV-PhotoSW, ANR-18-CE05-0020-01.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.613.pdf

M. Locatelli, «Silicon carbide against silicon: a comparison in terms of physical properties, technology and electrical performance of power devices,» Journal de Physique III, EDP Sciences, vol. 1, pp. 1101-1110, 1993.

J. A. Cooper et A. Agarwal, «SiC Power-Switching Devices-The Second Electronics Revolution» PROCEEDINGS OF THE IEEE, vol. 90, pp. 956-968, 2002.

S. Krishnaswami, A. Agarwal, S. H. Ryu, C. Capell, J. Richmond, J. Palmour, S. Balachandran, P. T. Chow, S. Bayne, B. Geil, K. Jones et C. Scozzie, «1000-V, 30-A 4H-SiC BJTs With High Current Gain,» IEEE ELECTRON DEVICE LETTERS, vol. 26, pp. 2474-2481, 2005.

Q. J. Zhang et R. Callanan, « 10 kV , 10 A Bipolar Junction Transistors and Darlington Transistors on 4H-SiC,» Materials Science Forum, vol. 1 , pp. 1025-1028, 2010.

A. Salemi et K. Jacobss, «15 kV-Class Implantation-Free 4H-SiC BJTs 15 kV -Class Implantation-Free 4H-SiC BJTs,» IEEE ELECTRON DEVICE LETTERS, vol. 39, pp. 63-66, 2018.

J. Zhang, J. H. Zhao, P. Alexandrov et T. Burke, «Demonstration of first 9.2 kV 4H-SiC bipolar junction transistor,» ELECTRONICS LETTERS, vol. 40, 2004.

A. Salemi, «Area- and Efficiency-Optimized Junction Termination for a 5.6 kV SiC BJT Process with Low ON-Resistance,» International Symposium on Power Semiconductor Devices, 2015.

H. Miyake, «21-kV SiC BJTs With Space-Modulated Junction Termination Extension,» IEEE ELECTRON DEVICE LETTERS, vol. 33, 2012.

D. PLANSON et L. V. PHUNG, «Edge termination design improvements for 10 kV 4H-SiC bipolar diodes,», vol. l, pp. 609-612, 2013.

Sentaurus, TCAD Simulation Tool by Synopses Inc., ver. Q (2019).

B. Buono, «Simulation and Characterization of Silicon Carbide Power Bipolar Junction Transistors,» KTH Royal Institute, Stockholm, 2012.

N. M. Lebedeva, N. D. Il'inskaya et P. A. Ivanov, «Edge-Termination Technique for HighVoltage Mesa-Structure 4H-SiC Devices: Negative Beveling,» PHYSICS OF SEMICONDUCTORDEVICES, vol. 54, pp. 258-262, 2020.

S. Liang, J. Wang et F. Fang, «Optimization Design of Isolation Rings in Monolithically Integrated 1200 V SiC Transistor and Anti-Parallel Diode for Improved Blocking Voltage,» IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 7, pp. 1513-1518, 2019.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 619-626

doi: 10.4028/p-7aduas

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-26

Revised:
2022-02-08

Accepted:
2022-03-07

Online:
2022-05-31

Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

The original version of this paper is available on https://www.scientific.net/MSF.1062.619.pdf

Valentin Valero , Laurent Ottaviani , Abdallah Lyoussi ,

Vladimir Radulović , Luka Snoj , Adrien Volte , Michel Carette and Christelle Reynard-Carette

Aix Marseille Univ, Université de Toulon, CNRS, IM2NP, Marseille, France

CEA/DES/IRESNE/DER, Section of Experimental Physics, Safety Tests and Instrumentation, Cadarache, F-13108, Saint Paul-lez-Durance, France

Reactor Physics Division, Jožef Stefan Institute, Ljubljana, Slovenia

valentin.valero@im2np.fr, laurent.ottaviani@im2np.fr, abdallah.lyoussi@cea.fr,

vladimir.radulovic@ijs.si, eluka.snoj@ijs.si, adrien.volte@univ-amu.fr, michel.carette@univamu.fr, christelle.carette@univ-amu.fr

Keywords: Silicon Carbide, semiconductors, neutrons, detector, 3D thermal simulations.

Abstract

Today, to respond to the increase of development of accurate, precise and relevant experiments in nuclear research reactors and tokamaks with their severe and intense operating conditions, there is a major need of innovative sensors that can accurately measure key parameters such as neutron and photon fluxes or nuclear heating rates. Thus, innovation in the field of nuclear instrumentation and measurements is a privileged research topic. It is crucial to develop optimized devices for accurate on-line in-core measurements, and scientific/technological requirements for various applications such as ageing of materials, safety applications, beam monitoring or nuclear physics. Nowadays, more and more semiconductors are used as sensor materials in nuclear instrumentation to measure various kinds of nuclear radiations. Silicon Carbide ( SiC ) is among them. In fact, SiC detectors could be used for the on-line measurement of key quantities such as neutron (thermal and fast) and photon fluxes. One main challenge is to enlarge the measurement range of this detector type. The work presented in this paper deals with this aim. Firstly, an introduction dedicated to the use of SiC versus other wide bandgap semiconductors and the characteristics of the studied sensor is shown. Secondly, this paper presents 3D numerical results obtained with a parametrical thermal study of the SiC detector using COMSOL Multiphysics code for a nuclear heating range corresponding to TRIGA nuclear research reactor conditions (integral neutron flux leading to a nuclear heating rate of in Tungsten). The main objective is to adapt and optimize the design and the housing of the detector by determining its temperature field for different configurations. The influence of various parameters is presented such as that of the housing material nature, the gas nature around the diode, the gas-gap height and the housing thickness.

Introduction

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Wide bandgap semiconductor materials such as Diamond, Silicon Carbide (SiC), III-V Nitrides or Gallium Arsenide (GaAs) are well-known for their high-power, high-frequency, high-temperature and harsh environment applications. All of this is possible thanks to their lower intrinsic-carrier concentrations than those of Silicon (Si) that induce a very low leakage current. Therefore, these semiconductors are capable of operating at much higher temperature than Si (several hundred degrees). Furthermore, SiC has many advantages in comparison with other wide bandgap semiconductors for measurements in extreme environments. Indeed, it is characterised by a high breakdown-electric field strength, rather high electron mobility, a high thermal conductivity, a high
electron saturation velocity and a high-radiation stability. Moreover, for many years, several improvements were performed about material quality through the development of SiC single crystals with a high-purity and epitaxial layers [1].

In the field of nuclear instrumentation, is used to build (thermal and/or fast) neutron detectors. They can be based on a junction diode [2] (cf. Fig. 1). To detect thermal neutrons, a Neutron Converter Layer (NCL) is implanted in a thick Aluminum contact. This NCL is composed of a material that has a high thermal neutron absorption cross section such as with 3840 barns. The absorption of thermal neutrons by leads to the release of charged particles, i.e. nuclei ( particle) and Li nuclei. These particles deposit/lose their energy in the successive very thin layers of the semiconductor (from 100 nm to ) which create electron/hole pairs that are collected by electrodes positioned on both sides of the detector. The sensitive part of the diode is called the Space Charge Region (SCR). Its width depends on the bias voltage applied across the detector and it is located between the -type epitaxial layer and the n -type epitaxial layer. For this kind of SiC detector, previous original research works have been carried out within the framework of the I_SMART project (Innovative Sensor for Material Ageing and Radiation Testing) involving the CEA and Aix-Marseille University [3]. For instance, for this kind of SiC detector, experimental research work has been carried out on the measurement of thermal neutron fluxes in MINERVE, a Zero-Power Reactor at CEA Cadarache, France with an integral neutron flux (thermal and fast) of .

Figure 1. Schematic of the 4 H -SiC-based diode (see details of thickness in [5])

Figure 1. Figure 1. Schematic of the 4 H -SiC-based diode (see details of thickness in [5])

A new objective is currently being targeted in the framework of the SiC-CALO project (coupling of Silicon Carbide and calorimetric sensors in order to measure key nuclear quantities simultaneously: neutron fluxes and nuclear heating rate). As for the I_SMART project, this new project is also achieved within the framework of a joint laboratory called LIMMEX (Laboratory of Instrumentation and Measurement Methods in EXtreme media) between Aix-Marseille University and the CEA. The project aim is to develop a new type of radiation detection system in order to perform on-line measurements under intense neutron fluxes of for an energy and high nuclear heating rates up to expected in the core of the Jules Horowitz Reactor under construction at the CEA Cadarache research center.

This system will couple a SiC detector with a compact differential calorimeter [5]. To achieve this aim, intermediate steps are necessary. First of all, a new design of each sensor has to be defined thanks to numerical simulations (3D thermal simulations and Monte-Carlo calculations). The optimized design will be manufactured. Then experiments will be carried out in the TRIGA Mark II reactor of the Jožef Stefan Institute (JSI) with a maximum integral neutron flux of about and a maximum nuclear heating rate in Tungsten around in the central irradiation channel [6]. The irradiation campaign will be performed inside an in-core triangular channel (dry air channel) during the first months of 2021. Figure 2 represents the JSI TRIGA Mark II reactor core and shows the various locations of irradiation channels (in yellow) such as the triangular dry air channel also called Triangular Irradiation Channel (TIC). All of these channels can host experiments depending
on the conditions desired (neutron and photon fluxes, nuclear heating rates, temperature, ...). The paper focuses on the 3D thermal numerical simulations realized to propose a new sensor design.

Figure 2. Schematic of the core of the Jožef Stefan Institute TRIGA Mark II reactor with the Triangular Irradiation Channel (TIC)

Figure 2. Figure 2. Schematic of the core of the Jožef Stefan Institute TRIGA Mark II reactor with the Triangular Irradiation Channel (TIC)

3D Thermal Simulation Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.619.pdf

In this part, a parametrical thermal study of various parameters using COMSOL Multiphysics code (finite element code with a heat transfer module) is shown for the SiC detector for a wide range of nuclear heating rate. The nuclear heating rate ( ) represents the energy rate ( ), which is released in one gram of matter exposed to nuclear radiation fluxes and corresponds to an increase of the thermal agitation inside the material, which leads to an increase in temperature.

3D Model. The presented thermal studies were realized for a system restricted to the SiC detector (the experimental irradiation channel and the coolant fluid flow were not modeled yet). The heat equation is solved with only conductive heat transfers (convective and radiative exchange are neglected inside the detector) and for the stationary state. Moreover, for each component of the system, a heat source ( ) calculated from the nuclear heating rate expected inside the TRIGA reactor ( ) and depending on the material density ( ) is applied (cf. Table 1).

Table 1. Energy deposition in the detector housing for a nuclear heating rate equal to and for different materials

Materials | ρi [kg·m⁻³] | Energy deposited Q [W·m⁻³] | Power deposited in the housing P [W]
Aluminum 5754 | 2700 | 270000 | 5.53
Duralumin | 2800 | 280000 | 5.73
Alumina | 3900 | 390000 | 7.98
Titanium TA6V | 4500 | 450000 | 9.21
Stainless Steel 316L | 7850 | 785000 | 16.07

Then, the external boundary conditions corresponding to the coolant fluid flow conditions (fluid temperature and induced heat exchange coefficient) are considered. The maximum temperature of the coolant fluid (dry air) is fixed at and the heat transfer coefficient related to natural convection is taken from to (only 5 and are presented in this paper). The SiC detector is built in 3D (cf. Fig. 3) for a simplified composition: the housing, the SiC diode, the diode support in Alumina and the gas present in the housing. The two-connection wires and the plugs are not considered.

Figure 3. Schematic of the detector geometry built with COMSOL Multiphysics

Figure 3. Figure 3. Schematic of the detector geometry built with COMSOL Multiphysics

The initial general dimensions of this sensor are presented in Table 2. The mesh sizes used in order to obtain the best compromise between the spatial resolution and the duration of each calculation was an extra-thin mesh. It corresponds to a minimal size equal to and a maximal size equal to 1680 . This range is sufficient compared to the total height of the SiC diode (a single layer of modeled).

Table 2. Initial geometrical characteristics of the SiC detector

Sensor components | Dimensions
Sensor components | Length [mm] | Width [mm] | Height [mm]
SiC diode | 10 | 10 | 0.371
Alumina support | 20 | 20 | 2
Housing (external dimensions) | 48 | 28 | 19
Gas-gap | 26.4 | 24 | 8

Results and Interpretations. The first parameter studied was the effect of the housing material nature on the temperatures reached inside the detector. Five different materials were tested: Aluminum 5754, Duralumin, Alumina, Titanium TA6V and Stainless Steel 316L. Figure 4 gives the induced maximal temperature of the detector versus the nuclear heating rate for these five materials for a heat transfer coefficient equal to .

Figure 4. Maximum temperature of the SiC detector versus the nuclear heating rate for five housing materials and for a heat transfer coefficient equal to and a fluid temperature equal to

Figure 4. Figure 4. Maximum temperature of the SiC detector versus the nuclear heating rate for five housing materials and for a heat transfer coefficient equal to and a fluid temperature equal to

As expected, the maximum temperature is obtained for the maximum nuclear absorbed dose rate value and the greatest material density.

This can be explained through the fact that for a constant volume, the weight of the housing is increasing with the density, so the energy deposited in the system is greater (cf. Table 1), leading to higher temperatures. Figure 5 confirms this behavior. Indeed, this Figure shows the maximum temperature versus the value of the total energy deposition, which depends on the nature of the housing material for a nuclear heating rate equal to . More than of the energy is deposited in the housing. Consequently, a housing made of Duralumin is chosen to achieve lower temperature and thanks to other properties such as its high thermal conductivity, its hardness, its important tensile strength and its ease of machining. An additional advantage is lower residual activation following neutron irradiation.

Figure 5. Maximum temperature of the SiC detector versus the specific energy deposited in the housing for five housing materials, a heat transfer coefficient equal to , a fluid temperature equal to and for a nuclear heating rate of

Figure 5. Figure 5. Maximum temperature of the SiC detector versus the specific energy deposited in the housing for five housing materials, a heat transfer coefficient equal to , a fluid temperature equal to and for a nuclear heating rate of

The second parameter studied is the gas nature in the gap for a housing made of Duralumin. Five different gases were tested: Air, Nitrogen, Helium, Argon and Xenon. It is observed that the temperatures reached inside the detector are the same for the different gases. A maximum deviation equal to is observed between the Air and Xenon configurations for a nuclear absorbed dose rate of , a heat transfer coefficient equal to and a fluid temperature equal to . These low differences can be explained by the fact that, as shown in Figure 6, the major part of the main heat conductive exchange is localized through the Alumina support and the Duralumin housing (the gas acting as a thermal insulator).

Figure 6. Temperature fields ( ) obtained inside the middle of SiC detector with an Air gap (on the left-hand section) and with a Helium gap (on the right-hand section) for a fluid temperature equal to , a heat exchange coefficient equal to and a nuclear heating rate equal to

Figure 6. Figure 6. Temperature fields ( ) obtained inside the middle of SiC detector with an Air gap (on the left-hand section) and with a Helium gap (on the right-hand section) for a fluid temperature equal to , a heat exchange coefficient equal to and a nuclear heating rate equal to

It can be concluded that, with this assembly configuration, the gas influence is not significant due to the conductive heat transfer through the Duralumin housing and the Alumina support, which are in contact with no thermal contact resistance considered in the 3D model.

The third parameter studied was the gas-gap thickness (for a housing made of Duralumin and an Air gap). In fact, the height of the gas-gap was reduced but the housing thickness is kept constant. Figure 7 presents the maximum temperature of the SiC detector versus the gas-gap height for two different values of heat transfer coefficient.

Figure 7. SiC detector maximum temperature versus the gas-gap height for two values of heat transfer coefficient, a nuclear heating rate equal to and a fluid temperature equal to

Figure 7. Figure 7. SiC detector maximum temperature versus the gas-gap height for two values of heat transfer coefficient, a nuclear heating rate equal to and a fluid temperature equal to

Whatever the applied value of the heat transfer coefficient, the maximum temperature increases with the height of the Air gap. This is due to the increasing of the housing volume and consequently of the total energy deposition. Actually, between the two extreme values of gas height, there is an increase of 0.8 W of power deposited on matter ( ). In addition, when the heat transfer coefficient increases, the temperature of the detector decreases significantly. Whatever the gas-gap height, the variation of the temperature is around for a heat transfer coefficient of instead of .

Figure 8. Temperature fields ( ) obtained for the 2 mm Duralumin housing (on the left-hand section) and the 0.5 mm Stainless Steel housing (on the right-hand section) with a fluid temperature equal to , a heat exchange coefficient equal to and a nuclear heating rate equal to

Figure 8. Figure 8. Temperature fields ( ) obtained for the 2 mm Duralumin housing (on the left-hand section) and the 0.5 mm Stainless Steel housing (on the right-hand section) with a fluid temperature equal to , a heat exchange coefficient equal to and a nuclear heating rate equal to

The last parameter investigated in this thermal study was the thickness of the housing for two different materials: 2 mm in Duralumin and 0.5 mm in Stainless Steel 316L respectively. For these two configurations, the thickness of the encapsulation is the same in all directions and the gas-gap retains its original dimensions (cf. Table 2). Figure 8 represents the temperature fields obtained with a fluid temperature equal to , a heat exchange coefficient equal to and a nuclear heating equal to for the Duralumin (on the left-hand section) and for the Stainless Steel (on the right-hand section) configurations. These two configurations lead to a significant decrease in the temperature (lower than ) in comparison with the previous dimensions of the detector due to the decrease of the thickness of the housing that induces a lower energy deposition in matter. The similar thermal behavior associated to the two configurations is due to the applied reduction of the housing thickness, which depends on the material nature.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.619.pdf

Thanks to a parametric thermal study, various conclusions were obtained to optimize the SiC detector design. For the first parameter, corresponding to the housing material nature, it was confirmed that the temperature increases in the detector when the nuclear heating rate and the density of the material increase. This is due to the higher energy deposition in the matter. Consequently, a housing made of Duralumin was chosen. Regarding the second parameter (the gas nature in the gap around the SiC diode and its support), the influence is not significant due to its thermal insulation coupled to the predominant conductive heat transfer through the Alumina support and the part of the Duralumin housing in contact with it. In the case of the third parameter (the gas-gap height), when it decreases, the maximum temperature is lower due to the diminution of the housing volume and consequently of the total energy deposition. This thermal behavior is reinforced for a higher heat transfer coefficient applied. For the last parameter studied, the thickness of the housing for a 2 mm Duralumin housing and a 0.5 mm Stainless Steel housing, an important temperature decrease was obtained as consequence of a lower energy deposition in matter. For these two cases, the maximum temperature reached agrees with the use of Tin alloy welds with a melting temperature above ensuring the wire connection.

In the future, a more detailed 3D model with the SiC detector in the triangular dry air channel of the Jožef Stefan Institute TRIGA Mark II reactor will be carried out. This model will contain also other components such as connectors, screws and the instrumentation cables. Moreover, it will consider thermal radiative transfer and specific heat transfer coefficient values using suited natural convection correlation formula depending on the heat sources. Another relevant Monte-Carlo particle transport simulation and modeling dedicated to the interactions between nuclear radiations and matter will be realized. These numerical studies and the results obtained will be used to define the most optimized device for the JSI irradiation campaign scheduled next year. Later, in order to estimate the discrepancy between experimental and numerical results for a specific point inside the detector, a nuclear-radiation hardened thermocouple will be integrated close to the SiC diode inside the gas-gap.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.619.pdf

V. V. Buniatyan and V. M. Aroutiounian, Wide gap semiconductor microwave devices, J. Phys. D: Appl. Phys. 40 (2007) 6355-6385.

F. Issa, V. Vervisch, L. Ottaviani, D. Szalkai, L. Vermeeren, A. Lyoussi, A. Kuznetsov, M. Lazar, A. Klix, O. Palais, R. Ferone, A. Hallén, Study of the stability of detectors by thermal neutron irradiation, Materials Science Forum 821-823 (2015) 875-878.

A. Lyoussi, et al., I _SMART a collaborative project on Innovative Sensor for Material Ageing and Radiation Testing: European Innovative Project for SiC applications in harsh media. KIC_Innoenergy, "CCAV," I_SMART Proposal/Exhibit 1 (2012).

O. Obraztsova, L. Ottaviani, B. Geslot, G. de Izarra, O. Palais, A. Lyoussi, W. Vervisch, Comparison between Silicon-Carbide and Diamond for Thermal neutron detection at Room Temperature, IEEE Transactions on Nuclear Science 67, No. 5, (2020) 863-871.

V. Valero, A. Volte, L. Ottaviani, A. Lyoussi, M. Carette, J. Brun, C. Reynard-Carette, Parametrical study for the coupling of a silicon carbide (SiC) detector and a calorimeter to measure simultaneously neutron flux and radiation absorbed dose rate in research reactors, RRFM 2020 conference proceedings (2020).

K. Ambrožič, G. Žerovnik, L. Snoj, Computational analysis of the dose rates at JSI TRIGA reactor irradiation facilities, Applied Radiation and Isotopes 130, (2017) 140-152.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 627-631

doi: 10.4028/p-s1v84y

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-03-14

Accepted:
2022-03-15

Online:
2022-05-31

Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts

The original version of this paper is available on https://www.scientific.net/MSF.1062.627.pdf

Kaloyan Naydenov , Nazareno Donato , Florin Udrea , Andrei Mihaila , Gianpaolo Romano , Stephan Wirths , and Lars Knoll

Department of Engineering, University of Cambridge, Cambridge, UK.

Hitachi ABB Power Grids, Semiconductors, Lenzburg, Switzerland.

andrei.mihaila@hitachi-powergrids.com, gianpaolo.romano@hitachi-powergrids.com, stephan.wirths@hitachi-powergrids.com, lars.knoll@hitachi-powergrids.com

Keywords: SiC MOSFET; TCAD modelling; cell geometry; inductive switching; UIS

Abstract

This work presents for the first time a comparative numerical study on the performance of planar 3.3 kV SiC MOSFETs during clamped and unclamped inductive switching for various cell layouts and pitches. It is demonstrated that despite its larger on-state losses, the atomic lattice layout (ALL) incurs smaller switching losses than the stripe and the circular designs for all examined cell pitches. Conversely, while the ALL does turn off earlier than the other layouts during UIS, the decrease in the peak lattice temperature that it brings is predicted to be marginal if just a single unit cell is considered.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.627.pdf

The advantageous material properties of SiC have recently made MOSFETs attractive for various power applications. In particular, the superior performance trade-off (between the specific resistance , the breakdown voltage , and the total switching time ) that SiC MOSFETs offer compared to Si devices have allowed for improvements in the efficiency and the reliability of the power system, enabling operation at a higher junction temperature [1]. Nevertheless, despite these advantages of the semiconductor, the increased power density in SiC MOSFETs can aggravate the heat extraction process and hence compromise the reliability of the packaging and the metallisation.

In this context recent studies have looked into the possibility to alleviate these issues by using advanced cellular layouts [2,3]. However, while the static behaviour of these 3D designs is now well understood [2-4], the variation of their dynamic response during both nominal and fault switching conditions, such as unclamped inductive switching (UIS), with the cell pitch requires further study. The latter case becomes particularly important at high ratings of 3.3 kV and above. That is why this work proposes a comprehensive numerical study on the electro-thermal performance of 3.3 kV planar 4 H -SiC MOSFETs during both UIS and clamped inductive switching for three different cell layouts (stripe, circular, and the atomic lattice layout [4]) at a range of cell pitches.

Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1062.627.pdf

The layouts of the examined 3.3 kV designs can be observed in Fig. 1. Here the circular and the ALL are simulated in 2D by solving the drift-diffusion equations for the unit cell in cylindrical coordinates around their respective axis of symmetry. The drift region has a thickness of and is doped n -type at , while the p -well is implemented using a retrograde profile matched to a process simulation [5]. A channel length of 300 nm is assumed, with the acceptor doping at the surface being . The interface is described using the distribution for the Si-face from [6] (assuming only acceptor states above the midgap level), along with a positive fixed charge density of . In turn, the p-short contact half-width is set to . The cases with a different cell pitch are obtained by adjusting the width of the JFET region, while the termination area is neglected.

The above structures are implemented in Sentaurus TCAD [7] and are then inserted into the circuit in Fig. 2 (without the freewheeling diode for UIS mode). Here the unit cells are scaled so as to get an

Fig. 1: Cross-section of a half unit cell of the examined 3.3 kV MOSFET (a) and top views of the stripe (b), circular (c), and ALL (d) topologies (drawn to scale for a cell pitch). The darker tones in (b-d) signify the area over which the gate oxide is placed.

Fig. 1. Cross-section of a half unit cell of the examined 3.3 kV MOSFET (a) and top views of the stripe (b), circular (c), and ALL (d) topologies (drawn to scale for a cell pitch). The darker tones in (b-d) signify the area over which the gate oxide is placed.

active area of . A default diode from the TCAD's in-built SPICE library in [7] is used for the clamped inductive switching case. Conversely, a fixed thermal resistance of is placed at the drain for UIS mode. Unless otherwise stated, all subsequent results are for .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.627.pdf

The performance of the above designs is first examined at nominal inductive switching conditions for an on-state drain current of . In agreement with [4], the circular design is found to have the lowest resistance of all layouts for typical values of (Fig. 3 (a)). Conversely, the ALL attains a comparable only at larger due to its saddle junction, which increases the channel, JFET, and spreading resistances for small (although it also increases the breakdown voltage compared to the other layouts (Fig. 3 (b)). Still, this drawback of the ALL should be less important at a higher rating (and JFET doping), where the drift region forms the dominant contribution to .

On the other hand, from Fig. 4 (a-b) it can be seen that the ALL (circular) attains the fastest (slowest) response of all layouts during both turn-on and turn-off (for a cell pitch). In particular, the ALL exhibits a shorter Miller plateau during both switching instances. These results are confirmed by the C/V waveforms in Fig. 5, where the ALL's is an order of magnitude smaller than in the other designs. This drop of the Miller capacitance arises from the wider lateral extension of the depletion region brought about by the ALL's saddle junction (as seen by the sharper slope of at ) and also from the smaller gate contact area (and hence weaker gate-drain coupling) of the ALL compared to the other designs. The ALL can hence be expected to display a smaller and lower switching losses also at other values. Nonetheless, the smaller of the ALL also leads to notably larger oscillations in the drain current at turn-off if the same gate resistance is used for all layouts (Fig. 4 (b)). Thus, it may become necessary to employ a larger so as to reduce and hence obtain a cleaner turn-off waveform (albeit at the cost of increased switching losses).

Fig. 2: Circuit used for the switching simulations. The diode is removed for UIS mode.

Fig. 2. Circuit used for the switching simulations. The diode is removed for UIS mode.

Fig. 3: Variation of with (a) and off-state I/V curves (b) of the examined designs. The ALL has the highest , yet its becomes competitive only at large .

Fig. 4: Turn-on (a) and turn-off (b) characteristics of the examined layouts (for a cell pitch of ) during clamped inductive switching. The ALL (circular) displays the fastest (slowest) response with the smallest losses, yet it also exhibits increased oscillations.

Fig. 4. Turn-on (a) and turn-off (b) characteristics of the examined layouts (for a cell pitch of ) during clamped inductive switching. The ALL (circular) displays the fastest (slowest) response with the smallest losses, yet it also exhibits increased oscillations.

The variation of the switching responses with can be seen in Fig. 6. Here the losses are computed using the electron current through the channel (hence power dissipation due to capacitive charging is neglected). It can be observed that both and the switching time (defined as the sum of the rise time of during turn-on and the time until the first zero-crossing of at turn-off) increase monotonically with for each layout due to the larger (and hence wider Miller plateau) of the structures with a bigger pitch. The ALL not only has the fastest response for all cases, but the reductions in and that it produces grow at larger cell pitches. At the same time, the amplitude of the observed oscillations falls as is increased (thanks to the larger ). Conversely, at small the ALL's advantage in weakens and gets overruled by its larger .

The responses of the structures during UIS (with removed) are now presented in Fig. 7 (a-c). Although the differences between the layouts are rather small as only a single scaled unit cell is considered, the ALL (circular) still clearly dissipates the inductor current faster (slower) than the others. This can be explained with the larger (smaller) breakdown voltage of the ALL (circular) (Fig. 3 (b)) due to its saddle (cylindrical) junction [4]. Indeed, since the voltage across the load is should fall faster in a layout with a larger drain voltage . The more rapid turn-off of the ALL is found to compensate for the extra heating due to the larger , allowing it to attain the lowest peak temperature (and ). Nonetheless, this reduction is only .

The same trend can also be seen at other cell pitches (Fig. 7 (d)). Here both the turn-off time off and the peak increase with for all layouts due to the corresponding drop of with .

The lowest (highest) degree of self-heating is again attained by the ALL (circular). Still, although the performance differences become somewhat clearer at larger (due to the greater variation of with the layout), the ALL's advantage during UIS (in case of a single unit cell) remains negligible.

Fig. 5: waveforms of the examined layouts for a of . The ALL (circular) displays the smallest (largest) and ratio.

Fig. 5. waveforms of the examined layouts for a of . The ALL (circular) displays the smallest (largest) and ratio.

Fig. 7: (a) and (b) responses of the layouts during UIS, lattice temperature profile (for ) at time (c), and evolution of the UIS response with .

Fig. 7. (a) and (b) responses of the layouts during UIS, lattice temperature profile (for ) at time (c), and evolution of the UIS response with .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.627.pdf

In this paper the impact of the cell layout and the cell pitch on the switching speed and losses of 3.3 kV planar SiC MOSFETs has been investigated numerically. It has been shown that while the circular design attains the lowest , it incurs larger switching losses than the other layouts. At the same time, the ALL attains the smallest thanks to its reduced and hence becomes competitive for designs with a sufficiently large pitch. Conversely, the improvement during UIS due to the isolated effect of the ALL's unit cell is predicted to be marginal. In order to assess if this advantage of the ALL can become truly significant in a real device, the entire die needs to be considered in the analysis.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.627.pdf

A. Q. Huang, Power Semiconductor Devices for Smart Grid and Renewable Energy Systems, Proceedings of the IEEE 105 (2017) 2019-2047.

X. Q. Liu et al., Impact of cell geometry on zero-energy turn-off of SiC power MOSFETs, Material Science Forum 924 (2018) 756-760.

A. Agarwal, K. Han, and B. J. Baliga, Impact of cell topology on characteristics of planar MOSFETs, IEEE Electron Device Letters 40 (2019) 773-776.

B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, 2010.

L. Knoll et al., Planar 1.2 kV SiC MOSFETs with retrograde channel profile for enhanced ruggedness, International Symposium on Power Semiconductor Devices and ICs (2019) 211-214.

H. Yoshioka, T. Nakamura, and T. Kimoto, Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance, Journal of Applied Physics 111 (2012) 014502.

Sentaurus Device User Guide, Synopsys, Mountain View, CA, USA, 2019.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 632-636

doi: 10.4028/p-fnekfr

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-13

Revised:
2022-02-21

Accepted:
2022-03-07

Online:
2022-05-31

On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

The original version of this paper is available on https://www.scientific.net/MSF.1062.632.pdf

Nazareno Donato , Kaloyan Naydenov , Florin Udrea , Andrei Mihaila , Gianpaolo Romano , Stephan Wirths and Lars Knoll

¹Department of Engineering, University of Cambridge, Cambridge, UK.

Hitachi ABB Power Grids, Semiconductors, Lenzburg, Switzerland.

nd391@cam.ac.uk, kn334@cam.ac.uk, u1000@cam.ac.uk, gianpaolo.romano@ch.abb.com, stephan.wirths@ch.abb.com, glars.knoll@hitachi-powergrids.com

Keywords: SiC MOSFET; TCAD modelling; 3D cell geometry; short circuit robustness.

Abstract

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the atomic lattice layout (ALL) ) at small cell pitches (CP) , which can lead to the formation of a filament with a high current density and heat generation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.632.pdf

Initially manufactured for the 600 V range by Rohm in 2010 and immediately followed by the first commercial 1.2 kV 4H-SiC MOSFET from Cree, SiC MOSFETs are now commercially available in either discrete or module configurations mainly for automotive and traction applications. Regarding 1.2 kV 4H-SiC MOSFETs, manufacturers have opted for different cell designs (symmetric/asymmetric trench, planar etc.), in order to tackle issues related to the low mobility at the Si-face, dielectric reliability, gate charge hysteresis, NBTI and PBTI, and bipolar degradation[1-2]. Compared to Si-counterparts, SiC MOSFETs allow for an increased power density and maximum junction temperature (Tjmax), while improving the efficiency and reducing the size of the power electronic system. While the maximum junction temperature itself does provide a useful indication of the device's resistance towards abnormal electrical events such as unclamped inductive switching (UIS) and short circuit (SC), fast thermal transients due to the high-power density are often what limits the reliability of the device, the metallization, and the packaging material[3]. In this context, advanced unit cell topology could be beneficial in suppressing the contribution related to the channel resistance and reducing the fast . In Si , the unit cell layout is known to affect several static (specific on-state resistance ( ) and breakdown voltage BV ) and dynamic ( ratio) electrical characteristics of the power MOSFET [4]. Nevertheless, to date, the impact of the cell layout on the short circuit (SC) performance has not been reported yet in the literature. Thus, this study presents a complete investigation on the thermal runaway failure mechanism for several SiC MOSFET layouts. This type of failure mechanism is obtained when the thermally generated carrier concentration exceeds the background doping concentration and the device reaches an intrinsic state with the formation of a low Ohmic current-path.

Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1062.632.pdf

The different cells analysed are displayed in Fig. 1(a-e). Circular and ALL have been solved by means of cylindrical coordinates. Conversely, the array and Hex layouts have been simulated by using 3D unit cells that account for and of the total cell. Ideal Neumann conditions have been applied to the geometrical boundaries. A layer of positive fixed charges has been added at the interface. The drift (buffer) region's doping and thickness have been set to ( 1 and . The implanted profiles have been matched from a process-based simulation, both the regions are long and the channel length is fixed at 300 nm for all the geometries. The threshold voltage is identical for all topologies analysed in this study.

Fig.1. Top views of (a) stripe (b) array, (c) hex, (d) circular, (e) ALL, (f) cross-section of the stripe.

Fig.1. Top views of (a) stripe (b) array, (c) hex, (d) circular, (e) ALL, (f) cross-section of the stripe.

The SC capability of each structure is examined through single pulse short circuit (type I) mixedmode simulations, using the circuit in Fig. 2(a). A single thermal interface has been added at the drain contact with a specific thermal resistance of . This situation reproduces well the typical heat transfer configuration in which the top area of the device is less thermally conductive compared to the substrate. Reflective heat boundary conditions have been assumed at the geometrical boundaries of the device. For the purpose of this work, thermo-mechanical effects, convection and radiation heat exchange, gate oxide failure or cell-to-cell unbalances have not been accounted for [5].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.632.pdf

Fig. 2 Schematic circuit used for the SC (type I) simulations(a), top view conduction area (orange) for circular and which shows that the area and output IV at .

Fig. 2. Schematic circuit used for the SC (type I) simulations(a), top view conduction area (orange) for circular and which shows that the area and output IV at .

In Fig.2(c), the simulated RonS for SiC devices reproduces well the experimental and theoretical trends observed in [1] for Si-devices, with the circular MOSFET outperforming the other layouts in terms of RonS. Similar ON-state performance (as well as SC performance in Fig.3(a) and breakdown voltage, not shown) can be observed for the array, hex, and circular layouts.
Note that the formation of the channel along the Si-face ( plane) allows for the variation of the channel mobility along the different crystal faces (which could affect the outcome of the comparison for trench-based MOSFETs) to be neglected. The structure's electrothermal response is described, using the classical thermodynamic model (Eq. 1-3) [6-7].

This expression is based on the continuity equation, which relates the rate of change of the internal energy of the system (composed of the lattice and the carriers) to the energy flux due to conduction via Fourier's law, Joule and Thomson heating (second term), optical generation, and an additional term, which accounts for the energy's dynamic variation with the carrier density. The Peltier coefficient here is computed assuming Thomson's second relation and Mott's formula for the Seebeck coefficient. The SC drain current density ( ) and the maximum and average lattice temperatures for a SC pulse are shown in Fig. . It can be observed that follows the same trend (with the cell's topology) as . This also agrees with the (expected) variation of with the cell layout (shown in Fig. 2 (c)).

Conversely, varies in the exactly opposite way. The increased local heat generation in the ALL cell can be explained with the stronger (local) Joule heating effect (where as shown in Eq.3). Indeed, the ALL's smaller JFET area density (calculated in Fig. 2(b)) limits the spreading of the current and hence increases the (local) current density, effectively creating a current filament.

Fig. 3 SC waveforms of (a) the drain current density and (b) and for a fixed .

Fig. 3. SC waveforms of (a) the drain current density and (b) and for a fixed .

Fig.4. (a)RonS ( ) and JFET area/total cell area for different CP; (b)Average junction temperature(Tavg) at and maximum SC drain current density(JD_max); (c) Maximum junction temperature (Tmax) at and normalized short circuit withstand time (SCWT) extracted at the value at which JD reaches again JD_max due to current density increase related to the thermal runaway; (d) normalized short circuit critical energy density vs CP for different layouts.

Fig.4. (a)RonS ( ) and JFET area/total cell area for different CP; (b)Average junction temperature(Tavg) at and maximum SC drain current density(JD_max); (c) Maximum junction temperature (Tmax) at and normalized short circuit withstand time (SCWT) extracted at the value at which JD reaches again JD_max due to current density increase related to the thermal runaway; (d) normalized short circuit critical energy density vs CP for different layouts.

The cells' behaviour for different CPs is presented in Fig. 4 (a-d). Here correlates well with the peak short circuit current ( ) and the critical SC energy ( ). Indeed, the higher of the circular reduces the SCWT due to premature thermal runaway. More interesting is the evolution of with CP, where a non-monotonic trend can be observed for the circular and stripe designs, but not for the ALL (Fig. 4 (c)). This differs from the variation of the JFET area density in Fig. 4 (a) and can be explained through examination of the temperature distribution in the top of the cell (Fig. 5). In the case of the ALL, the peak temperature point lies deep inside the JFET region (and farther from the channel than in the other designs) for all examined CP (Fig. 5). This is a consequence of the smaller conduction area in the JFET region. At larger CP, however, the JFET component of reduces monotonically, which allows for improved current spreading (in the JFET region) and hence slowly shifts the point of the peak current density (and of Joule heating) to the interface. Conversely, while a similar trend can be seen in the stripe cell, the depth (relative to the surface) of the location of is smaller (due to the larger JFET area). In fact, for the circular, the point of remains next to the interface for all examined CP. Nevertheless, unlike in the ALL, the degree of current spreading in the circular and stripe designs saturates above , due to the newly added lateral resistance along the length of the accumulation layer. Thus, RonS eventually starts to rise with CP (due to the inefficient area consumption). More importantly, this also leads to a saturation of the local Joule heating profile and thus of (unlike in the ALL, where it falls continuously with CP).

Fig. 5. Lattice temperature profile at the top of the unit cell for the stripe, circular and ALL layouts at . The cross mark depicts the location of the peak lattice (junction) temperature point.

Fig. 5. Lattice temperature profile at the top of the unit cell for the stripe, circular and ALL layouts at . The cross mark depicts the location of the peak lattice (junction) temperature point.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.632.pdf

In conclusion, this work has clearly demonstrated that there exists a strong correlation between the evolution of the maximum junction temperature (hotspot) and the cell layout, which is not only a function of the JFET area density but also of the current density profile and current spreading in the JFET/accumulation region. Moreover, the average local junction temperature, as well as the location of the hotspot, are both responsible for the device's thermal runaway failure mechanism.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.632.pdf

Adan, Alberto O., et al. "The Current Status and Trends of 1,200-V Commercial Silicon-Carbide MOSFETs: Deep Physical Analysis of Power Transistors From a Designer's Perspective." IEEE Power Electronics Magazine 6.2 (2019): 36-47.

Agarwal et al.. "Impact of Cell Topology on Characteristics of 600 V 4H-SiC Planar MOSFETs". IEEE Electron Device Letters, 40(5), 773-776.

Romano, Gianpaolo, et al. "A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs." IEEE Journal of Emerging and Selected Topics in Power Electronics 4.3 (2016): 978-987.

Baliga, B. Jayant. Fundamentals of power semiconductor devices. Springer Science & Business Media, 2010.

Tsibizov, Alexander, et al. IEEE Transactions on Power Electronics 35.2 (2019): 1855-1865.

Wachutka, G. K., "Rigorous Thermodynamic Treatment of Heat Generation and Conduction in Semiconductor Device Modeling." IEEE Trans. Comput-Aided Des. Integr. Circuits Syst., 9(11), 1141-1149, 1990. DOI: 10.1109/43.62751

M. Cutler and N. F. Mott, "Observation of Anderson Localization in an Electron Gas.", Physical Review, 181(3), 1336-1340, 1969.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 637-641

doi: 10.4028/p-gvcp58

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-14

Revised:
2022-02-21

Accepted:
2022-03-07

Online:
2022-05-31

Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

The original version of this paper is available on https://www.scientific.net/MSF.1062.637.pdf

Fatme Abed Ali , Yvan Avenas , Pierre Lefranc , Pierre-Olivier Jeannin , Hadi Alawieh , Toni Youssef , Hassan Moussa

Institut VEDECOM, 23 bis Allée des Marronniers, 78000, Versailles, France

Univ. Grenoble Alpes, CNRS, Grenoble INP, G2Elab, Grenoble, France

Safran Tech, Electrical & Electronic Systems Research Group, Rue des Jeunes Bois, Châteaufort, 78114 Magny-Les-Hameaux, France

atme.abed-ali@vedecom.fr, yvan.avenas@g2elab.grenoble-inp.fr, pierre.lefranc@g2elab.grenoble-inp.fr, pierre-olivier.jeannin@g2elab.grenoble-inp.fr,

Keywords: High power density, Multichip power module, Package design, Parasitic element, Silicon Carbide (SiC)

Abstract

Compactness, efficiency, and light weight are the key topics in the design of power conversion systems for transportation applications. This demand is achievable by using wide band gap devices such as SiC devices, characterized by the high switching speed and low on-resistance. However, this trend imposes new challenges and the effect of parasitic elements of power package during switching transient becomes significant. Hence, new packaging solutions should be investigated for addressing this concern. This paper presents a new multichip power module architecture, where its design considering capacitive and inductive stray elements is carried out. Using Ansys Q3D Extractor, electromagnetic simulations are achieved to extract the inductive and capacitive parasitic element of one leg of a three-phase inverter.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.637.pdf

The Silicon (Si) material is a semiconductor used in many power electronics applications. The latest technological developments have led to minimal dimension requirements that would be a hard physical limit for this material. Thus, the standard solution proposed to overcome these limits is to replace Si with Silicon Carbide ( SiC ) material [1]. In fact, SiC MOSFETs have shown several advantages over the similarly rated Si IGBTs, such as a higher switching speed and thus lower switching losses. Hence, SiC devices enable the fabrication of converter systems with high performance, high efficiency, and high power density, meeting better new market requirements [2]. However, using these SiC -based switches makes the system very sensitive to parasitic circuit elements. Also, they can lead to higher electromagnetic interferences (EMI), voltage, and current ringing during switching. For example, high di/dt in a switching cell might result in a severe turn-off overvoltage due to the presence of the parasitic stray inductance that must be minimized. Therefore, to take full advantage of the good performances of SiC devices and ensure a good operation of power converters, the optimization of their packaging technology is necessary [3].

In this paper, we propose a new design of a multichip power module, with low parasitic inductance specifications and symmetrical parasitic capacitances. The presented design is based on optimizing the placement of embedded transistors in a PCB layout which allows a self-compensation of the magnetic field that reduces the parasitic inductances of the circuit [4].

Design Principle

The original version of this paper is available on https://www.scientific.net/MSF.1062.637.pdf

It is well known that a low-inductive switching loop is necessary to obtain fast switching. As well, to avoid large EMI during the switching of the transistors, a special attention to the electromagnetic compatibility (EMC) design rules are mandatory. Hence, this section presents the characteristic of
the design that considers capacitive and inductive stray elements to obtain high switching speed capabilities.

Inductance of the overall current commutation loop (Lccl). To reduce , several techniques are considered. As shown in the cross section view of Fig. 1, the power switches are integrated between two PCBs (PCB1 and PCB2) with the flip-chip technology. This technology demonstrates considerable improvements in switching performance, since it allows decreasing and improving the symmetry of common mode capacitances when compared to conventional packages [5]. Also, the flip-chip technology applied to the transistors, reduces the surface of the switching cell, and minimizes LCCL.

Fig. 1: Cross section of the proposed power module.

Fig. 1. Cross section of the proposed power module.

In addition to these features, special attention is paid to the position of the transistors. In our design, both high side (HS) and low side (LS) switches are composed of two SiC MOSFET dies in parallel (Fig. 2a). As shown in the bottom view of PCB1 represented in Fig. 2b, the HS1 MOSFET is placed diametrically opposed to the HS2 (same for LS1 and LS2). This arrangement allows a selfcompensation of the magnetic fields created by the opposite switching loops, loop (1) and loop (2) in Fig. 2c, which ensures minimization of the global parasitic inductance of the switching cell.

Fig. 2: Proposed technology. (a) Electrical scheme. (b) Positioning of transistors. (c) Selfcompensation of the magnetic fields.

Fig. 2. Proposed technology. (a) Electrical scheme. (b) Positioning of transistors. (c) Selfcompensation of the magnetic fields.

EMC. With short switching times, when SiC components are used, the capacitive coupling elements create a considerable impact on the conducted EMC. As shown in Fig. 3, the common mode (CM) capacitor at the output node (OUT), is due to the layout of the module, the interconnections, and the load. The high dv/dt at this node generates common mode currents through Cout. Also, the CM current is conducted by the capacitor of gate driver insulation ( ) that must be reduced. Although, and a recycling path to the CM current inside the module. They can be considered as a part of the CM filter. To keep the advantage of and , bus voltage must be stable enough, and it is necessary to have a symmetrical layout at DC+ and DC-. Also, the
symmetrization of Cout_dc+ and Cout_dc-, which are parallel to the output capacitances of HS and LS transistors respectively, is necessary to have a simultaneous switching of these transistors.

Fig. 3: Representation of the parasitic capacitors.

Fig. 3. Representation of the parasitic capacitors.

Q3D Simulations Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.637.pdf

To verify the advantage of this innovative power packaging technology that combines (i) the flipchip of the MOSFETs and (ii) the diametrically opposed position (designated as configuration 1), a performance study was carried out to compare this first configuration (Fig. 4a) with two others (configuration 2 and 3). Configuration 2 presents a non-crossed position of the transistors but keeps the flip-chip technology (Fig. 4b) that should confirm the interest of the self-compensation of the magnetic field in configuration 1. Also, configuration 3 presents a classical disposition of the transistors without a flip-chip (Fig. 4c), with an architecture closer to the one of conventional packages that should demonstrate the importance of the symmetrical layout in configuration 1.

Fig. 4: Positioning of transistors. (a) Configuration 1. (b) Configuration 2. (c) Configuration 3.

Fig. 4. Positioning of transistors. (a) Configuration 1. (b) Configuration 2. (c) Configuration 3.

Stray inductances. L1 and L2 shown in Fig. 5, represent the stray inductances, due to the packaging, of branch 1 and 2 respectively, and represents the mutual inductance between these branches.

Fig. 5: Self and mutual inductance of paralleled branch.

Fig. 5. Self and mutual inductance of paralleled branch.

The total parasitic inductance is represented by the Eq. 1:

The equivalent parasitic inductance of the CCL can also be represented by the Eq. 2:

The extractions of self and mutual inductances are realized with Ansys Q3D software. To illustrate the influence of the self-compensation of the magnetic flux, the inductance matrix of the first configuration is shown in Eq. 3 and compared with Eq. 4 that represents the inductance of the second configuration.

As can be seen, the mutual inductances between paralleled branches of the first configuration are negative. The equivalent parasitic inductances are 0.86 nH and 1.12 nH for the first and the second configuration, respectively. This proves the hypothesis of self-compensation of magnetic field, where the mutual inductances cancel of the total parasitic inductance and reduces its effect. Common mode capacitors. The extractions of the common mode capacitors are also realized by Ansys Q3D extractor. The results obtained for the first configuration are now compared with the second and third configurations.

Table 1: Q3D results of common mode capacitor.

| Configuration 1 | Configuration 2 | Configuration 3
COUT_LAYOUT [pF] | 0.08 | 0.08 | 38
CDC+_GND [pF] | 39 | 45 | 38.7
CDC-_GND [pF] | 42 | 45 | 0.4
COUT_DC+ [pF] | 74.4 | 93.5 | 105
COUT_DC- [pF] | 73.2 | 98.7 | 49

Table 1 shows that the output capacitance due to the layout design (Cout_layout) is negligeable for the first and second configurations. Also, the capacitance comparison between and reveal that the layout at DC+ and DC- are more symmetric for configurations 1 and 2 due to the flip chip technology. Also, the optimization of the layout is clearly demonstrated by the similar values obtained for the capacitances between DC+, DC- and the output node (Cout_dc+ and Cout_dc-).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.637.pdf

In this paper, the estimation of the stray inductance of a phase leg commutation loop is studied, also the common mode capacitors are considered. The above Q3D-extracted results confirm our hypothesis concerning the minimization of the parasitic inductance of the switching loops by the selfcompensation concept. To complete our study, the analysis of the proposed module should be verified by experimental studies. A double pulse test will confirm the effectiveness of mutual inductance cancellation, and an EMC test will confirm the advantages of the layout symmetrization.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.637.pdf

X. She, A. Q. Huang, Ó. Lucía, et B. Ozpineci,"Review of Silicon Carbide Power Devices and Their Applications," in IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 8193-8205, October 2017.

F. Hou et al.,"Review of Packaging Schemes for Power Module," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 1, pp. 223-238, March 2020.

J. Knoll, C. DiMarino, I. Salkovic, M. Morianz, G. Weis, et H. Stahr,"Design and Analysis of a PCB-Embedded 1.2 kV SiC Half-Bridge Module," CPES VIRGINA Tech 2021, April 2021.

M. AMEZIANI et H. ALAWIEH, "Power electronic module (WO 2020/094959 Al)". Vedecom Institute. 2020. Information on:

E. Hoene, G. Deboy, C. R. Sullivan, et G. Hurley, "Outlook on Developments in Power Devices and Integration: Recent Investigations and Future Requirements," IEEE Power Electronics Magazine, vol. 5, no 1, p. 28-36.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 642-646

doi: 10.4028/p-xz45c3

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-09-24

Revised:
2022-03-09

Accepted:
2022-03-09

Online:
2022-05-31

Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

Eiichi Murakami , Tatsuya Takeshita and Kazuhiro Oda

Kyushu-Sangyo University, 2-3-1, Matsukadai, Higashi-ku, Fukuoka, 813-8503, Japan

eiichi@ip.kyusan-u.ac.jp, t.take@ip.kyusan-u.ac.jp

and oda@ip.kyusan-u.ac.jp

Keywords: SiC-MOSFETs, reliability, time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI), gate current, NO-annealing

Abstract

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

Silicon carbide metal-oxide-semiconductor field-effect transistors ( SiC -MOSFETs) have been successfully applied to railway vehicles. They are also being applied to electric vehicles (EVs). As EVs lack a railway vehicle-like redundancy system, EVs require SiC-MOSFETs to reduce the extrinsic defects. Their reliability needs to be understood. The commercial SiC-MOSFET reliability was compared in bias-temperature instability (BTI) [1], and time-dependent dielectric breakdown (TDDB) [2,3]. Further, gate oxide integrity (GOI) [4,5] was compared for automotive applications.

Several vendors produce SiC-MOSFETs. Here, we compared the reliability of two SiC-MOSFET samples ( A and B ) in BTI and TDDB.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

Both the MOSFETs exhibited a conventional planar vertical structure with a -thick gate oxide when observed under a transmission electron microscope. Positive and negative BTI values (PBTI and NBTI) were measured at using spot monitoring during the stress conditions as a JED0 pattern [6]. TDDBs were measured at room temperature (RT, ), , and , under a constant voltage stress (CVS, or 47 V ). The gate current was monitored during the stress. We employed B2902A PC-controlled source measuring units (Keysight Technologies Inc., Santa Rosa, CA), STH-120 temperature-controlled furnaces (ESPEC CORP., Osaka, Japan), and LTF-70 cold plates (Graphtec Corporation, Yokohama, Japan).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

Fig. 1 depicts the PBTI (a) and NBTI (b) threshold voltage shifts ( ). Sample A exhibited a lower PBTI and a higher NBTI than Sample B, as reported earlier [1]. Moreover, both the samples exhibited hysteresis [7] around 0.4 V by sweeping the gate voltage ( ) at . NO (nitric oxide)-annealing studies suggested higher nitrogen concentration in Sample A [8].

Fig. 2(a) depicts the TDDB time-to-breakdown ( ) at different temperatures. Sample A exhibited larger variation, while Sample B exhibited smaller variations. As three samples were measured

Fig. 1. Threshold voltage shifts by PBTI (a) and NBTI (b). Insets depict the logarithmic plots. The data suggest higher nitrogen concentration in Sample A than in Sample B.

Fig. 1. Threshold voltage shifts by PBTI (a) and NBTI (b). Insets depict the logarithmic plots. The data suggest higher nitrogen concentration in Sample A than in Sample B.

Fig. 2. Temperature dependence of (a) and (b) at V. Sample A exhibited larger variations. Sample B exhibited anomalous temperature dependence in and . The and values were lower at than at RT.

Fig. 2. Temperature dependence of (a) and (b) at V. Sample A exhibited larger variations. Sample B exhibited anomalous temperature dependence in and . The and values were lower at than at RT.

for each condition here, we present Weibull plots for at RT in Fig. 3(a), which were obtained from another experimental set. Sample A exhibited smaller Weibull slope than Sample B.

Fig. 4 depicts the time-dependent gate currents, , that were measured during the CVS at 47 V , RT. Sample A exhibited initial higher that subsequently decreased, while Sample B exhibited a continuous increase. Similar -dependent observations were reported at and [9]. Okada et al. [10] proposed charging-induced dynamic stress in system. This elucidated TDDB anomaly upon using behavioral pattern.

Fig. 3. Weibull plots depicting SiC-MOSFET TDDB data at , RT, for samples A and B (a) and at , RT and for Sample B (b). The vertical axes are defined as : median rank), wherein and denote the cumulative failure and total sample number, respectively. The cumulative defect density is defined as ( : gate area). Thermostream was used in the experiment.

Fig. 3. Weibull plots depicting SiC-MOSFET TDDB data at , RT, for samples A and B (a) and at , RT and for Sample B (b). The vertical axes are defined as : median rank), wherein and denote the cumulative failure and total sample number, respectively. The cumulative defect density is defined as ( : gate area). Thermostream was used in the experiment.

Fig. 4. Time dependence of gate current during gate stress ( , RT). (a) Sample A and (b) Sample B. The change in color indicates the stress interruption for measurements. Insets depict linear increase during the interruptions, suggesting electron detrapping. The data also suggest higher nitrogen concentration in Sample A than in Sample B.

Fig. 4. Time dependence of gate current during gate stress ( , RT). (a) Sample A and (b) Sample B. The change in color indicates the stress interruption for measurements. Insets depict linear increase during the interruptions, suggesting electron detrapping. The data also suggest higher nitrogen concentration in Sample A than in Sample B.

When is in the decreasing phase, a sample with a larger shows a much larger by CVS than expected. On the contrary, in the increasing phase, a sample with larger suffers stronger stress than expected; thus, reducing its . Consequently, while the former resulted in larger variations (as in Sample A), the latter resulted in smaller variations (as in Sample B).

Moreover, we elucidated the TDDB's NO-annealing dependence using test element group (TEG) chips [11]. The samples A and B corresponded to heavy and light NO-annealing situations, respectively. This argument was consistent with the BTI characteristics (Fig. 1). We hypothesized that holes and electrons were trapped near the interface [11]. The trapped location remains to be investigated [ ].

Fig. 2 (b) depicts the calculated . Larger values and normal temperature dependence were observed in Sample A, as reported for system [12]. Although higher temperatures resulted in lower hot-carrier generation, the defect formed upon thermal activation. Therefore, the TDDB temperature coefficient remained positive [13]. However, an anomalous temperature dependence for and was observed in Sample B, which resulted in the largest RT values. Weibull plots from a different experimental set are presented (Fig. 3(b)) to support this anomaly. The extrinsic mode was observed to a greater extent at . This phenomenon should be investigated further.

Understanding the basis of this anomaly requires further investigation. The presence of residual carbon at the interface in an oxidized SiC sample was demonstrated in a carbon-ejection study [14]. The residual carbon might alter thermal activation during the defect formation process. The NO-annealing dependence is being investigated using the TEG chips [11].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

The two SiC MOSFETs exhibited different PBTI, NBTI, TDDB statistics, and temperature dependence in commercial planar structures. These differences are probably due to NO-annealing variations.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

The authors show gratitude to students and faculty members of Department of Electrical Engineering in Kyushu Sangyo University for supporting this study.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.642.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 647-652

doi: 10.4028/p-586z1h

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-02-02

Revised:
2022-03-14

Accepted:
2022-03-14

Online:
2022-05-31

Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

Alexander Tsibizov , Roger Stark and Ulrike Grossner

¹Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

tsibizov@aps.ee.ethz.ch, stark@aps.ee.ethz.ch, ulrike.grossner@ethz.ch

Keywords: SiC MOSFET, inter-terminal capacitance, inter-electrode capacitance, package inductance.

Abstract

Inter-terminal capacitances (ITCs) have major influence on the dynamic performance of power SiC MOSFETs. Knowledge of the exact values for the ITCs is required in order to perform accurate and predictive compact model simulations of their dynamic performance. Since commercial SiC MOSFETs are capable of operating in a wide range of temperatures, it is important to know the values of ITCs in the whole temperature range of operation. Direct measurements of the ITCs with standard equipment is possible only at low current levels (i.e. in the off-state for ), however their values in the on-state also influence the MOSFETs switching performance. In this work, ITCs of a planar SiC MOSFET in the on-state are studied by the means of a calibrated TCAD model, revealing substantial temperature dependence in the range of . In the first approximation, this temperature dependence of the ITCs can be explained by a weaker temperature dependence of the MOSFET channel resistance in comparison to its JFET and epitaxial layer resistances. In addition, it is shown that at high frequencies stray inductances of the TO-247-3 package result in a change of the extracted values of the on-state ITCs. This effect is already notable at 1 MHz .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

Inter-terminal capacitances (ITCs) play important role in dynamic performance of the power SiC MOSFET [1,2]. Knowledge of values for the ITCs is required to perform accurate and predictive compact model simulations of their dynamic performance. An example of such a simple compact model (CM) is shown in Fig. 1. Since commercial SiC MOSFETs are capable of operating in a wide range of temperatures, e.g. from to [3], it is important to know the parameters of the CM over the whole temperature range of device operation. However, at present often only the temperature dependence of the quasi-static MOSFET's current source and body diode are set in the CMs while ITCs do not depend on temperature, see e.g. [4]. Moreover, supported by the off-state measurements it has been suggested that the temperature dependence of power MOSFET's ITCs is weak [5]. As shown in [6], direct measurements of the ITCs with standard equipment are possible only at low current levels (i.e. in the off-state for ), since the power of commercial impedance measurement systems are limited much below the full dynamic range of power MOSFETs. However, the values in the on-state ( ) also influence the switching performance of the MOSFET [1]. Although a number of methods has been suggested recently for the on-state measurements of ITCs of SiC MOSFET [7,8,9], the on-state ITCs and in particular their temperature behavior remain poorly investigated. In this work, the on-state ITCs of a planar gate SiC MOSFET are studied by the means of a calibrated TCAD model [10], revealing a substantial temperature dependence in the range of .

Fig. 1. Electrical equivalent circuit of a power MOSFET including the inter-terminal capacitance , , and internal gate resistance and the parasitic inductances of the terminals of the package. The channel current source and the internal body diode of the MOSFET are represented by symbols M and .

Fig. 1. Electrical equivalent circuit of a power MOSFET including the inter-terminal capacitance , , and internal gate resistance and the parasitic inductances of the terminals of the package. The channel current source and the internal body diode of the MOSFET are represented by symbols M and .

A frequency is often used for the AC measurements of the ITCs in the off-state [3]. The same frequency has been used in [7] for the on-state measurements of ITCs. Our TCAD simulations have shown that at high frequencies stray inductances of TO-247-3 package result in a change of extracted values of the on-state ITCs and this effect is quite pronounced already at 1 MHz .

Method

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

and of a planar SiC MOSFET were extracted from small-signal AC mixed-mode simulations of a calibrated 2D TCAD model [10], aiming to reproduce electrical characteristics of a commercial device [3]. The stray inductances of the TO-247-3 package were included in a simplified manner following [11], see Fig. 1, with the values , and the mutual coupling coefficients extracted in ANSYS Q3D Extractor at 1 MHz . A shunt resistor with the same value was added in parallel to each terminal inductance in order to improve convergence. An internal gate resistance (obtained from our measurements of the C2M0080120D MOSFET at 1 MHz ) has been used in the simulation. The AC signal was applied to the package electrodes and correspondent apparent ITCs were extracted from the AC susceptance at different frequencies. The capacitances are extracted during the quasi-stationary ramp for different constant at two constant device temperatures 300 K and 450 K , revealing their temperature and frequency dependence.

Results & Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

The resulting TCAD simulation shows only a small temperature dependence of the ITCs in the off-state as can be expected from previous works [5], see Fig. 2. However, this is not valid for the onstate ITCs, see Fig. 3, where the temperature dependence is much more pronounced. Such a difference between the temperature dependence of ITCs in the off-state and on-state can be explained with the help of simplified small signal equivalent circuits as presented in Fig. 4. In the off-state, the gate oxide capacitances and are separated by a depleted region and charged correspondingly only from the source or the drain, thus correspondingly contributing only to or . In the on-state, they are connected by the conducting channel, thus making the situation similar to the one considered in [12]. and can be charged through both source and drain contacts, therefore contributing to both and . The share of this capacitance attributed to or depends on the ratio
. Hence, the temperature dependence of and is caused by the large differences between temperature dependence of the channel and drain resistances [13], whose ratio determines the attribution of charge in the channel and JFET region to the source or to the drain. Thereby, it determines the decomposition of into and . The explanation above is quite obvious for the on-state case of , when is approximately equal to the gate oxide capacitance , and . However, for larger the values of the capacitance of the double-diffused metal-oxide semiconductor (DMOS) device may exceed the gateoxide capacitance [14]. This results from the variation on the voltage drop over the gate oxide which is larger than the change in the imposed gate bias when reaching the quasi-saturation region [14].

Fig. 2. Simulated , and in the off-state . Left plot , right one .

Fig. 2. Simulated , and in the off-state . Left plot , right one .

Fig. 3. Simulated and in the on-state . Left plot , right one .

Fig. 3. Simulated and in the on-state . Left plot , right one .

Fig. 4. Simplified electrical equivalent circuit of a vertical double-diffused power MOSFET half-cell structure for a) a closed channel ( ), and c ) open channel ( ). The corresponding small-signal equivalent circuits b) and d) indicate the voltage dependencies of the capacitances and resistances.

Fig. 4. Simplified electrical equivalent circuit of a vertical double-diffused power MOSFET half-cell structure for a) a closed channel ( ), and c ) open channel ( ). The corresponding small-signal equivalent circuits b) and d) indicate the voltage dependencies of the capacitances and resistances.

is used for the demonstration of the on-state ITCs because it is in the region of the Miller plateau voltage. However, it represents the overall behavior of the on-state ITCs well.

The frequency is often used for the measurements of the ITCs in the off-state [3]. TCAD simulations with the stray inductance of the TO-247-3 package show little frequency dependence of the off-state ITCs up to 1 MHz , see Fig. 5. A frequency was used in [7] for the extraction of the apparent on-state ITCs of packaged devices. Fig. 5 shows that in the on-state is large enough to cause a noticeable difference of extracted apparent ITCs in comparison to the internal (related to the die design) ITCs due to the stray inductances of the TO-247-3 package. The internal ITCs correspond to the ones extracted at low frequency ( ). Hence, for the real on-state measurements there is a contradiction in requirements: on the one hand, self-heating affects the extracted ITCs due to a change of device temperature, requiring smaller measurement duration to avoid it. On the other hand, if the measurement duration is too small, the influence of the package stray inductance will distort the results of the measurements, because smaller measurement durations require larger frequencies for AC measurements [7]. A similar problem exists also for the real onstate ITCs measurements based on the voltage sweep method [9]. Usage of a low stray inductance package could mitigate the problem.

Fig. 5. Simulated frequency dependence of apparent at . Left plot: in the off-state . Right plot: in the on-state . Curves for and coincide.

Fig. 5. Simulated frequency dependence of apparent at . Left plot: in the off-state . Right plot: in the on-state . Curves for and coincide.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

Unlike in the off-state, TCAD simulations of SiC MOSFETs show a noticeable temperature dependence of the on-state ITCs ( and ) in the temperature range . Therefore, such temperature dependence should be considered for accurate CM simulations of such devices.

In addition, the values of the ITCs' extracted from the on-state measurements of TO-247-3 packaged devices are strongly affected by the package stray inductances already at . Using lower frequencies for the AC measurements of the on-state ITCs may lead to a strong self-heating (due to a longer measurement time). Thus, the usage of another package with smaller stray inductances for direct measurements of the internal ITCs related to the die design is suggested.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

Dr. Ivana Kovačević-Badstübner is gratefully acknowledged for providing the stray inductance parameters of TO-247-3 package.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.647.pdf

C. Salcines, I. Kallfass, H. Kakitani, A. Mikata, Dynamic characterization of the input and reverse transfer capacitances in power MOSFETs under high current conduction, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, (2016) 2969-2972

R. Stark, I. Kovacevic-Badstübner, A. Tsibizov, B. Kakarla, Y. Ju, B. Jaeger, T. Ziemann, U. Grossner, Analysis of parameters determining nominal dynamic performance of 1.2 kV SiC power MOSFETs, Proc. of IEEE Int. Symp. on Power Semiconductor Devices and ICs (ISPSD), (2018) 407-410

Wolfspeed, C2M0080120D Silicon Carbide Power MOSFET, Rev. D, 09-2019. [Online]. Available:

H. Li, Xingran Zhao, Kai Sun, Z. Zhao, G. Cao, T. Zheng. A Non-Segmented PSpice Model of SiC mosfet With Temperature-Dependent Parameters, IEEE Trans. Power Electron. 34, (2019) 46034612

S.Y. Liu, Y.F. Jiang, W.J. Sung, X.Q. Song, B.J. Baliga, W.F. Sun, A.Q. Huang, Understanding High Temperature Static and Dynamic Characteristics of 1.2 kV SiC Power MOSFETs, Materials Science Forum 897, (2017) 501-504

T. Funaki, N. Phankong, T. Kimoto, T. Hikihara, Measuring Terminal Capacitance and Its Voltage Dependency for High-Voltage Power Devices, IEEE Trans. Power Electron. 24, (2009) 1486-1493

C. Salcines, B. Holzinger, I. Kallfass, Characterization of Intrinsic Capacitances of Power Transistors Under High Current Conduction Based on Pulsed S-Parameter Measurements, 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Atlanta, GA, (2018) 180-184

H. Sakairi, T. Yanagi, H. Otake, N. Kuroda and H. Tanigawa, "Measurement Methodology for Accurate Modeling of SiC MOSFET Switching Behavior Over Wide Voltage and Current Ranges", IEEE Trans. Power Electron. 33, (2018) 7314-7325

C. Deml, K. Hoffmann, Gate-drain capacitance behaviour of the DMOS power transistor under high current flow, PESC 98 Record. 29th Annual IEEE Power Electronics Specialists Conference (Cat. No.98CH36196), Fukuoka, vol.2, (1998) 1716-1719

A. Tsibizov, I. Kovačević-Badstübner, B. Kakarla, U. Grossner, Accurate Temperature Estimation of SiC Power mosfets Under Extreme Operating Conditions, IEEE Trans. Power Electron. 35, (2020) 1855-1865

I. Kovačević-Badstübner, U. Grossner, D. Romano, G. Antonini, J. Ekman, A more accurate electromagnetic modeling of WBG power modules, 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, (2018) 260-263

D. E. Ward, R. W. Dutton, A Charge-Oriented Model for MOS Transistor Capacitances, IEEE J. Solid-State Circuits 13, (1978) 703-708

J. Müting, U. Grossner, Simulation-Based Sensitivity Analysis of Conduction and Switching Losses for Silicon Carbide Power MOSFETs, Materials Science Forum 924, (2018) 693-696

C. M. Liu, J. B. Kuo, Quasi-Saturation Capacitance Behavior of a DMOS Device, IEEE Trans. Electron Devices 44, (1997) 1117-1123

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 653-657

doi: 10.4028/p-2tyqfr

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Revised:
2022-02-25

Accepted:
2022-03-07

Online:
2022-05-31

SiC MOSFET C-V Characteristics with Positive Biased Drain

The original version of this paper is available on https://www.scientific.net/MSF.1062.653.pdf

Ilaria Matacena , Luca Maresca , Michele Riccio , Andrea Irace , Giovanni Breglio , Santolo Daliento and Alberto Castellazzi

¹Dept. of Electrical Engineering and Information Technologies, University Federico II, via Claudio, 21, 80125, Naples, Italy

Kyoto University of Advanced Science, 18 Gotanda-cho, Yamanouchi, Ukyo-ku, 615-8577 Kyoto, Japan

ailaria.matacena@unina.it, luca.maresca@unina.it, michele.riccio@unina.it, dirace@unina.it, breglio@unina.it, daliento@unina.it, alberto.castellazzi@kuas.ac.jp.

Keywords: C-V curves, MOSFET Gate capacitance, interface characterization, TCAD model, SiC MOSFET.

Abstract

Even if SiC MOSFETs technology has undergone huge progress in last years, there are some issues still open, such as high traps density at the interface. This work focuses on the measurement of the Gate capacitance when a DC bias is applied between Drain and Source to characterize the interface. The experimental curves, performed on a commercial SiC power MOSFET, exhibit a peak when the Gate voltage approaches the threshold voltage. Such peak is analyzed through TCAD simulations and its origin is addressed. Numerical analysis shows that this peak is associated to the displacement current, with a strong dependence on the traps concentration at the interface.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.653.pdf

The high performance of the Silicon Carbide ( SiC ) [1] led to a large improvement of this technology in the last decades. SiC power semiconductor devices such as diodes and MOSFETs are now available on the market with stable performances. Although all the progress made, there are still open issues affecting this technology, such as the high traps density at interface [2] and the hysteresis phenomena arising in the current-voltage (I-V) curves. However, the high traps density is detrimental for device performance [3]-[4], affecting channel mobility [5], threshold voltage stability [6] and leakage current amplitude. In this work, through experimental characterizations and numerical simulations, for the first time the behavior of the Gate capacitance is monitored when a DC bias is applied between Drain and Source terminals. More in detail, experimental setup and results are presented in Section 1. In order to understand these results a numerical study has been performed and presented in Section 2. Conclusions are then drawn.

Section 1

The original version of this paper is available on https://www.scientific.net/MSF.1062.653.pdf

Experimental Setup and Results. The experimental setup is presented in Fig. 1a. The aim of this work is the characterization of the Gate capacitance when a DC bias is applied between Drain and Source terminals. Therefore, a ramp ranging from -20 V to 12 V is applied on the Gate with a superimposed AC small signal, Fig 1b. In addition to that, a DC bias is applied between Drain and Source. The capacitance-voltage ( ) curves refer to the commercial planar SiC MOSFET (MSC080SMA120B4), and they have been performed by means of an Agilent 4294A Impedance Analyzer. The small signal amplitude is set to 100 mV while the frequency chosen is 100 kHz . A DC voltage has been applied between Drain and Source during the capacitance measurements, has been set to 1 V , in the first case, and to 2 V in the other case, Fig 1c.

Fig. 1. a) Experimental setup used, b) , and c) .

Fig. 1. a) Experimental setup used, b) , and c) .

The resulting experimental capacitance versus voltage curves are shown in Fig.2. In the accumulation and depletion region (blue and green highlighted in of Fig.2), the obtained capacitance behavior is close to capacitance behavior when no bias is applied between Drain and Source ( ). Initially the capacitance is mostly due to oxide capacitance, and then it decreases due to the increase of the depletion region with applied Gate voltage. The substantial difference occurs in the inversion region: a sharp peak occurs in Fig. 2 when a bias is applied to Drain, while, in the case the Drain is not biased,

Fig. 2. Experimental C-V curves of a commercial SiC MOSFET, when a DC bias of 1 V (black) and 2 V (red) is applied between Drain and Source.

Fig. 2. Experimental C-V curves of a commercial SiC MOSFET, when a DC bias of 1 V (black) and 2 V (red) is applied between Drain and Source.

, capacitance curve doesn't exhibit such peak. The prominent peak occurs in both cases, and , at a voltage which is close to the threshold voltage. This seems to suggest that the occurrence of such peak is related to traps concentration at interface, which mainly affects the threshold voltage in the I-V curve, as will be discussed in the next Section.

Section 2

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Numerical framework and results. A numerical model has been built in Sentaurus TCAD [7] to gain a better understanding on the experimental results. The structure used in this work is a reference model to approximate the commercial device [8]-[11]. The C-V curve has been carried out in
simulation taking into account the effects of long-time-constants traps. To highlight the effect of such traps, a sawtooth signal is applied to the Gate of the TCAD model and for each time step an AC simulation is carried out. In Fig. 3 the simulated curve is reported when a DC bias of 1 V is applied between Drain and Source, together with the relevant simulation parameters. In the same figure, the displacement current in the structure is shown, more precisely in the region near the channel, for three voltage values highlighted in the numerical curve. The displacement current distribution gives a strong insight, since it can be argued that the peak occurs where such current is higher and there is a current flow through the oxide. Therefore, the arising peak has its origin in the channel region. This statement is enforced by considering the derivative of the numerical Drain current with respect to the voltage and the numerical capacitance-voltage curve.

Fig. 3. Numerical curve, with . Insets represent displacement current in the channel region at highlighted voltage values. A fixed charge concentration, , has been set at the interface. The temperature set is , and the frequency is .

Fig. 3. Numerical curve, with . Insets represent displacement current in the channel region at highlighted voltage values. A fixed charge concentration, , has been set at the interface. The temperature set is , and the frequency is .

Fig. 4. a) Numerical curve, with , left y -axis, and derivative of the Drain current , right y -axis. The two curves have a peak occurring at the same voltage. b) Numerical curves, with , and different traps concentration at the interface. The peak width is wider as the traps concentration increases.

Fig. 4. a) Numerical curve, with , left y -axis, and derivative of the Drain current , right y -axis. The two curves have a peak occurring at the same voltage. b) Numerical curves, with , and different traps concentration at the interface. The peak width is wider as the traps concentration increases.

In Fig. 4a, it is clear as the peak of the current derivative is occurring at a voltage which is exactly the voltage at which the capacitance peak is occurring. Thus, characterizing this peak can give reliable information on traps properties. To this end, numerical results show that the higher is the trap concentration, the wider is the region where the capacitance peak occurs. In Fig.4b, the numerical CV curves obtained with different traps concentration at the interface are shown. Increasing traps concentration in the channel region affects the threshold voltage. This also involves a shift of the capacitance peak. From Fig.4b, it can be seen that for the higher concentration considered there is a twofold effect: not only the capacitance peak significantly shifts toward higher voltage but also the region affected is considerably wider.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.653.pdf

The behavior of SiC MOSFET Gate capacitance with a positive bias applied between Drain and Source has been considered in this work. Experimental C-V curves obtained with commercial SiC MOSFETs exhibited a prominent peak in the region of the threshold voltage. The occurrence of such peak has been studied by means of TCAD framework. The numerical analysis showed that the peak occurring in the Gate capacitance is related to traps concentration at the interface. More in detail, the capacitance peak occurs at a voltage where the displacement current is higher. This has been confirmed by comparing the curve with the derivative of the Drain current. Both curves presented a peak occurring at the same voltage. Moreover, by considering different traps concentration at the interface, the numerical analysis allowed to assess that the peak width is wider as the traps concentration increases. This means that this measurement technique supported by numerical analysis can be used as a quick tool for the device characterization and traps concentration extraction.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.653.pdf

B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

C. Raynaud, et al., Comparison of trapping-detrapping properties of mobile charge in alkali contaminated meta,l-oxide-silicon carbide structures, Applied physics letters 66, no. 18: 23402342, (1995).

S. Daliento, et al. "Experimental study on power consumption in lifetime engineered power diodes." IEEE transactions on electron devices 56.11 (2009): 2819-2824.

F. Di Napoli, et al. "On-line junction temperature monitoring of switching devices with dynamic compact thermal models extracted with model order reduction." Energies 10.2 (2017): 189.

V. V. Afanasev, et al., Intrinsic interface states, physica status solidi (a) 162, no. 1: 321-337, (1997).

D.Peters et al., Investigation of threshold voltage stability of SiC MOSFETs, ISPSD, (2018).

Dev, Synopsys. Simulation, TCAD Sentaurus Manual.

L. Maresca, et al., Influence of the MOSFET interface traps distribution on CV measurements evaluated by TCAD simulations. IEEE Journal of Emerging and Selected Topics in Power Electronics, (2019).

G. Romano, et al., A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs, IEEE Journal of Emerging and Selected Topics in Power Electronics 4, no. 3 (2016): 978-987.

Maresca, L., et al., TCAD model calibration for the interface trap in the same of a planar SiC MOSFET. In 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia) (pp. 1-5). IEEE. (2020, September).

Matacena, I., et al., Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations. In Materials Science Forum (Vol. 1004, pp. 608-613). Trans Tech Publications Ltd. (2020).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 658-662

doi: 10.4028/p-278mb0

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-21

Revised:
2022-02-08

Accepted:
2022-03-07

Online:
2022-05-31

A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.658.pdf

Alessandro Borghese , Michele Riccio , Luca Maresca , Giovanni Breglio , Slavo Kicin and Andrea Irace

Department of Electrical Engineering and Information Technologies (DIETI), University of Naples Federico II, Naples, Italy

Power Grids Research, ABB Power Grids Switzerland Ltd, Baden-Dättwil, Switzerland

alessandro.borghese@unina.it, michele.riccio@unina.it, giovanni.breglio@unina.it, slavo.kicin@hitachienergy.com, andrea.irace@unina.it

Keywords: compact modeling, silicon carbide (SiC) MOSFET, SPICE, power module.

Abstract

This paper presents a compact model implemented in SPICE environment for silicon carbide (SiC) MOSFET. The model is easily adjustable to devices belonging to different voltage and current ratings. A previous release of the model was tuned to match the performance of 1.2 kV and 3.3 kV SiC MOSFETs, while, in this contribution, an improved version of the compact model is calibrated for 1.7 kV devices. The agreement between the experimental and simulated data, achieved for both static and dynamic conditions, associated to the model simulation speed, emphasize its suitability as a tool for the simulation of converter containing wide arrangements of devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.658.pdf

SiC MOSFETs have become a commercial reality and both discrete devices and power modules are being progressively adopted in several market applications [1]. Given their increasing usage, there is a higher demand for fast and reliable electrothermal compact models of SiC MOSFETs that can help circuit designers in predicting the performance of the final converter. Switching converters are complex electrical machines and a detailed simulation of their efficiency rests upon a precise description of the losses (static and dynamic) of the underlying transistors. Nonetheless, depending on the complexity of the MOSFET model, the simulation of complex converter topologies in SPICElike tools can be a computationally heavy task and a compromise between simulation speed and accuracy usually exists [2], [3]. Furthermore, commercial SiC MOSFETs are available in different classes of breakdown voltage (namely ranging from 650 V to 3.3 kV ) and on-state resistance (namely ranging from to ), which increases the need for a common and adjustable modeling platform.
In previous literature contributions, we presented a SPICE-based model for SiC MOSFETs [4] and validated its applicability to 1.2 kV [4] and 3.3 kV [5] commercial devices. To further demonstrate its ease of scalability to family of devices of different voltage ratings, here we calibrate an improved version of the model to fit the electrical behavior of 1.7 kV SiC MOSFETs.

Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1062.658.pdf

Experimental Characterization. The devices under tests (DUTs) are A-rated SiC MOSFETs. Since the device are provided as bare dies, they were mounted onto a suitable test substrate to enable their electrical characterization (Fig. 1). The isothermal static current-voltage characteristics ( and ) of 17 DUTs were measured by an in-house developed pulsed curve tracer both at and at . Some parameters determining the on-state current and their spread were evaluated, and the resulting values are reported in Table 1. The MOSFETs exhibit some spread in their current-conduction behavior. Nevertheless, the spread of the transfer characteristics is confined within (Fig. 2). Therefore, the DUT selected as reference for calibrating the model is the one exhibiting the median transfer characteristic. However, the impact of the technological fluctuations on the uneven current sharing can be easily included as reported in [6].

Fig. 1. Example of 1.7 kV SiC MOSFET under test mounted on the test substrate.

Fig. 1. Example of 1.7 kV SiC MOSFET under test mounted on the test substrate.

Fig. 2. Isothermal transfer characteristics of the 17 SiC MOSFETs under test.

Fig. 2. Isothermal transfer characteristics of the 17 SiC MOSFETs under test.

Table 1. Main parameters determining the current conduction and their spread measured at .

Parameter
Threshold voltage:
VTH[V]
Transconductance:
KP [A/V²]
Channel length modulation
parameter: λ [V⁻¹]

Mean value ±
spread
5.77 ± 0.17
0.84 ± 0.06
0.03 ± 0.004

Description of SiC MOSFET Model. The compact electrothermal model described in this work is a variant of the one presented in [4]. A schematic representation of its equivalent circuit is reported in Fig. 3, which highlights the main components used to model the static current flow. These are implemented by conventional SPICE primitives, thus aiding convergence and widening the model compatibility. The modulation of charge in the channel region is modeled by a SPICE LEVEL 3 MOSFET (referred to as ). Following the approach suggested in [7], a standard JFET ( ) in series with was used to describe the modulation of the current path due to the expansion of the space charge region in the JFET area. Such a phenomenon was previously represented in [4] through a voltage dependent resistor. The model is fully electrothermal and includes the temperature dependence of the most relevant physical parameters. Three capacitances determine the dynamic characteristics of the model. These are (i) the gate-to-source capacitance ( ) which is constant and equal to the capacitance of the LEVEL 3 MOSFET , (ii) the voltage dependent junction capacitance of the body diode ( ), and (iii) the non-linear gate-to-drain capacitance ( ). The latter is modeled by an arctangent function through the relation reported in Eq. 1. This modeling choice ensures excellent simulation speed while keeping convergence issues at minimum, and, although it is reported not to be as accurate as other techniques [3], it will be shown that the simulations produce adequate prediction of the switching power losses.

The model parameters controlling the static electrical performances are calibrated through an automatic routine implemented through MATLAB and SIMetrix and outlined by the flowchart in Fig. 4. A subset of physical parameters, such as the threshold voltage ( ), the current factor ( ), and the parameter accounting for the channel-modulation effect ( ), are directly extracted from the experiments ant their values are used as a starting guess of an iterative optimization procedure. The procedure exploits a minimization function provided in the MATLAB optimization toolbox which progressively reduces the gap between the experimental and the simulated data.

Fig. 3. Schematic representation of compact electrothermal model for SiC
MOSFET. The capacitances are omitted for the sake of clarity.

Fig. 3. Schematic representation of compact electrothermal model for SiC MOSFET. The capacitances are omitted for the sake of clarity.

Fig. 4. Flowchart of the automatic routine for the optimization the parameters and the calibration of the static curves.

Fig. 4. Flowchart of the automatic routine for the optimization the parameters and the calibration of the static curves.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1062.658.pdf

From the comparison reported in Fig. 5 (a) and (b), it can be seen that excellent agreement was achieved between the experimental data and the fitted model at . As shown by the data at of Fig. 5 (a) and (c), the static behavior at high temperature is also correctly reproduced. To characterize the dynamic performance of the DUT, a double pulse test (DPT) on an inductive load of 1 mH was conducted by placing in series two MOSFETs in a half-bridge configuration. The highside switch acts as a freewheeling diode since the channel conduction was inhibited by connecting the gate and source terminals together. A schematic of the DPT setup is provided in Fig. 6. The test was performed at , with for both and , and careful evaluation of circuit parasitic components was carried out as it is known that they strongly affect the shape of the waveforms during switching transients [8]. As witnessed by the waveforms of Figs. 7 and 8, the model is able to precisely capture the very fast turn-on ( ) and turn-off ( ) switching transients, including the oscillations caused by the stray components. The accuracy of the of model is also substantiated by the comparison of Fig. 9, where the experimental and simulated waveforms of the power dissipated by the DUT are superimposed. It is worth noticing that the model not only provides a correct estimation of the switching energy, i.e., of the integral of the power dissipated during the commutations, but also of the instantaneous value of the power itself. This is of paramount relevance when it is important to take into account the time evolution of the thermal phenomena since a well-modeled power dissipation translates into an accurate time-dependent heat source [8].

Fig. 5. Comparison between the experimental and simulated isothermal static curves for the (a) transfer characteristics, (b) output characteristics at and (c) .

Fig. 5. Comparison between the experimental and simulated isothermal static curves for the (a) transfer characteristics, (b) output characteristics at and (c) .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.658.pdf

In this paper, a SPICE-based compact model for SiC MOSFET has been presented and calibrated to the experimental data of 1.7 kV devices. The model brings several improvements to a previously published contribution and the results have shown that it can satisfactorily represent the subtleties of the static and dynamic electrical waveforms of 1.7 kV SiC MOSFETs. This type of devices constitutes an additional class of MOSFETs on which the model has been benchmarked, thus proving the ease of scalability of the model itself.

Fig. 6. Schematic of the double pulse test setup adopted for the characterization of the switching transients.

Fig. 6. Schematic of the double pulse test setup adopted for the characterization of the switching transients.

Fig. 8. Comparison between the experimental and simulated current and voltage waveforms obtained during a turn-off event on inductive load at 800 V and 28 A.

Fig. 8. Comparison between the experimental and simulated current and voltage waveforms obtained during a turn-off event on inductive load at 800 V and 28 A.

Fig. 7. Comparison between the experimental and simulated current and voltage waveforms obtained during a turn-on event on inductive load at 800 V and 28 A .

Fig. 7. Comparison between the experimental and simulated current and voltage waveforms obtained during a turn-on event on inductive load at 800 V and 28 A .

Fig. 9. Comparison between the experimental and simulated switching power dissipation obtained during a double pulse test at 800 V and 28 A .

Fig. 9. Comparison between the experimental and simulated switching power dissipation obtained during a double pulse test at 800 V and 28 A .

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.658.pdf

L. Spaziani and L. Lu, Silicon, "GaN and SiC: There's room for all: An application space overview of device considerations," in Proc. IEEE ISPSD, 2018, doi: 10.1109/ISPSD.2018.8393590.

B. W. Nelson et al., "Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Static Behavior," in IEEE OJ-PEL, vol. 1, pp. 499-512, 2020, doi: 10.1109/OJPEL.2020.3036034.

B. W. Nelson et al., "Computational Efficiency Analysis of SiC MOSFET Models in SPICE: Dynamic Behavior," in IEEE OJ-PEL, vol. 2, pp. 106-123, 2021, doi: 10.1109/OJPEL.2021.3056075.

M. Riccio, et al., "A Temperature-Dependent SPICE Model of SiC Power MOSFETs for Within and Out-of-SOA Simulations," in in Proc. IEEE ISPSD, vol. 33, no. 9, pp. 8020-8029, Sept. 2018, doi: 10.1109/TPEL.2017.2774764.

A. Borghese et al., "An Experimentally Verified 3.3 kV SiC MOSFET Model Suitable for High-Current Modules Design," 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2019, pp. 215-218, doi: 10.1109/ISPSD.2019.8757576

A. Borghese et al., "Effect of Parameters Variability on the Performance of SiC MOSFET Modules," in Proc. IEEE ESARS-ITEC, 2018, doi: 10.1109/ESARS-ITEC.2018.8607593.

ON Semiconductor, "Physically Based, Scalable SPICE Modeling Methodologies for Modern Power Electronic Devices," TND6260/DRev. 2021, 2. Available online: (accessed on 07 October 2021).

C. Scognamillo, et al., "Compact Modeling of a 3.3 kV SiC MOSFET Power Module for Detailed CircuitLevel Electrothermal Simulations Including Parasitics," Energies, vol. 14, no. 15, p. 4683, Aug. 2021. Available:

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 663-668

doi: 10.4028/p-96q66n

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-26

Revised:
2022-02-22

Accepted:
2022-03-07

Online:
2022-05-31

SiC MOSFET C-V Curves Analysis with Floating Drain Configuration

The original version of this paper is available on https://www.scientific.net/MSF.1062.663.pdf

llaria Matacena , Luca Maresca , Michele Riccio , Andrea Irace , Giovanni Breglio and Santolo Daliento

1Department of Electrical Engineering and Information Technology, University of Naples "Federico II", Naples, Italy

ilaria.matacena@unina.it, luca.maresca@unina.it, michele.riccio@unina.it, dandrea.irace@unina.it, breglio@unina.it, daliento@unina.it

Keywords: SiC MOSFET, temperature, capacitance, traps.

Abstract

SiC MOSFETs have already replaced silicon-based device in power applications, even if some technological issues are still not solved. Among others, the complex traps distribution at interface is of foremost importance. Interface traps affect the overall device behavior, modifying channel mobility and introducing hysteresis. In this work, the capacitance behavior, when the Drain terminal is floating, is studied through numerical analysis. The effects of traps distribution and its properties on such curves has been studied along with temperature effects. Experimental curves are carried out at various temperatures and compared to the same trends of numerical results.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.663.pdf

Silicon carbide (SiC) MOSFETs have replaced silicon devices due to the higher performance of SiC with respect to silicon material [1]. SiC has a higher bandgap and it claims a high thermal conductivity. These properties established the SiC as the most promising material for power MOSFETs. On the other hand, there are some issues not yet solved in technology, as the interface traps density at interface which affects the overall device behavior. It worth to be noted that traps density at such interface is order of magnitude higher than traps density existing at interface [2]. Traps density influences the channel mobility [3] and threshold voltage stability also introducing threshold voltage hysteresis [4-5]. For all these reasons, having a deep insight in traps density at such interface and counting on a reliable TCAD model is of paramount importance. At this purpose, experimental characterization of SiC MOSFETs together with the numerical results must be performed [6]. Experimental characterization can be obtained considering capacitance versus voltage (C-V) curves. These latter allow to gain knowledge in MOSFET behavior through all its operating regions, as the accumulation, the depletion and the inversion. Nevertheless, capacitance is affected by traps existence and obviously by geometrical and process parameters. Since traps effect varies with temperature and, more in detail, it reduces as temperature increases, experimental characterization should be carried out at different temperatures.

In this work, experimental C-V curves are carried out with a floating Drain configuration, at different temperatures. The Gate capacitance considered is measured leaving the Drain terminal floating. Using these data, we perform a qualitative analysis to gain knowledge on traps distribution existing at interface and improve device reliability. In the first part, TCAD framework and simulation are included. The numerical C-V curves are presented with different traps distribution properties. In the second part, experimental curves are presented including C-V curves. More in detail, these curves are aligned to the numerical one. Numerical analysis is employed to gain better understand in experimental curves.

Numerical Analysis

The original version of this paper is available on https://www.scientific.net/MSF.1062.663.pdf

Numerical analysis has been carried out using Sentaurus environment [7]. The TCAD model of the SiC MOSFET structure considered in this work is presented in Fig. 1 and TCAD models used are reported in [6, 8-11]. The effects of the interface traps on the capacitance behavior are studied by implementing the experimental setup in numerical simulations. The equivalent TCAD C-

V setup is shown in Fig.2. In this work, we analyze the SiC MOSFET capacitance behavior when its Drain terminal is floating. In this schematic, the driving voltage applied to the Gate terminal of the device under test is , Fig.3, while Source terminal is grounded. Interface traps dynamics takes into account the time variation in the capacitance behavior. Traps dynamics modifies the carriers distribution as the driving voltage varies. The traps dynamics is considered by changing the and values of Fig.3. A small signal AC analysis is performed in Sentaurus for each time step. This framework allows to investigate the driving voltage effect on the curves. The interface traps properties considered in simulation are explicated in Fig.4. Traps distribution implemented is a square band distribution with a width, , and a distance from valence and conduction band equal to and , respectively. The considered model let the effects of the interface traps concentration, , the capture cross sections, and , to be considered in the simulation.

Figure 1. SiC MOSFET TCAD model adopted in this work (the structure is not to scale).

Figure 1. Figure 1. SiC MOSFET TCAD model adopted in this work (the structure is not to scale).

Figure 2. Schematic of the mixed-mode circuit used for the simulation of the experimental setup. On the Gate terminal the driving signal is applied, Source terminal is grounded and Drain terminal is floating.

Figure 2. Figure 2. Schematic of the mixed-mode circuit used for the simulation of the experimental setup. On the Gate terminal the driving signal is applied, Source terminal is grounded and Drain terminal is floating.

Figure 3. Driving voltage, VGEN, applied to the MOSFET gate.

Figure 3. Figure 3. Driving voltage, VGEN, applied to the MOSFET gate.

Figure 4. Band diagram of the TCAD structure with trap distribution.

Figure 4. Figure 4. Band diagram of the TCAD structure with trap distribution.

The numerical C-V curves are presented for acceptor type traps with varying distance from the conduction band edge, Fig.5. This numerical analysis has been performed also for donor type traps. The main outcome is that a hysteresis arises from traps existence. This hysteresis effect is not located in a particular part of the curve, but different parts of such curve are affected depending on traps properties: considering different centre values of traps distribution the region "B" (threshold voltage hysteresis), highlighted in Fig. 5, is modified. More in detail, the curve with traps shifts toward left in voltage, with respect to the reference curve without traps, as the traps distribution moves nearer to the conduction band edge. A hysteresis effect occurs also in region "A", highlighted in Fig. 5, even if this part of the curve is not modified with varying . Also the influence of traps concentration has been considered. In Fig.6, it can be seen that increasing the concentration of acceptor like traps the region " B " of the curve shifts towards right. However, varying traps concentration near conduction band doesn't not vary the region "A". From Fig.7, it can be asserted that increasing the temperature the hysteresis effect is less visible in C-V curves obtained with Drain floating.

Figure 5. Numerical curves without traps (markers) and with an acceptors trap band with varying. and .

Figure 5. Figure 5. Numerical curves without traps (markers) and with an acceptors trap band with varying. and .

Figure 6. Numerical C-V curves with an acceptor traps distribution with varying. , and

Figure 6. Figure 6. Numerical C-V curves with an acceptor traps distribution with varying. , and

Figure 7. Numerical C-V curves with an acceptor traps distribution with temperature varying. and .

Figure 7. Figure 7. Numerical C-V curves with an acceptor traps distribution with temperature varying. and .

Experimental Data

The original version of this paper is available on https://www.scientific.net/MSF.1062.663.pdf

The capacitance curves have been obtained using an Impedance Analyzer. The frequency has been imposed to 100 kHz , while the driving voltage has been swept from 20 V to -10 V and vice versa . The capacitance behavior is different depending on the sweep direction of [6]. For this reason, two sweeps have been considered, the first one from positive to negative voltage (sweep down) and the second one from negative to positive voltage (sweep up). The C-V curves obtained for obtained for a commercial 1200 V SiC MOSFET device are shown in Fig.8. Considering these curves, it is clear as the hysteresis effect consists not only in the shift of the curves obtained during the sweep up and the sweep down but in a considerable distortion of the two curves considered. Two hysteresis effects are visible in these measurements: a first one occurring in the region A of

Fig.8, and the second one taking place around the threshold voltage, region B of Fig.8. Considering the C-V curve obtained numerically for a structure without traps [6], [10], it is evident that the experimental curves show an unexpected behavior. This obtained behavior is caused to a complex traps distribution existing in the device at the interface. This traps distribution cannot be easily measured accessing only to device package and in a non-destructive analysis. Hence the need to perform numerical analysis, on the considered device, in a more complex way. This analysis includes TCAD simulations of the device under test considering interface traps distribution and it allows to have a clearer insight in the device physics along with the experimental capacitance curve behavior. A better understand in traps distribution can be gained by considering the temperature behavior of the C-V curves. In Fig.8, the C-V curves at different temperatures obtained following the same setup values described above have also been reported. The devices under test have been heated at the following temperatures: and 450 K . The hysteresis effect is less evident as temperature increases, when Drain terminal is floating. From these measurements, it can be inferred that the capacitance behavior suffers of visible hysteresis effects.

Figure 8. Experimental C-V curves of a commercial SiC power MOSFETs, Cree CMF20120, obtained with floating Drain.

Figure 8. Figure 8. Experimental C-V curves of a commercial SiC power MOSFETs, Cree CMF20120, obtained with floating Drain.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.663.pdf

In this work, SiC MOSFET experimental capacitance has been presented when the Drain terminal is floating. These data confirmed behavior of numerical results. TCAD analysis led to a better understanding on the complex traps distribution at the interface. An accurate characterization of the device under test has been performed on the so-measured capacitance taking into account temperature. More in detail, capacitance behavior in temperature highlighted that hysteresis effect is exacerbated at lower temperature.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.663.pdf

Baliga, B. J. "Fundamentals of power semiconductor devices". Springer Science & Business Media (2010).

C. Raynaud, J. L. Autran, J. B. Briot, B. Balland, N. Becourt, T. Billon, and C. Jaussaud. "Comparison of trapping-detrapping properties of mobile charge in alkali contaminated metal-oxidesilicon carbide structures." Applied physics letters 66, no. 18: 2340-2342 (1995).

V. V. Afanasev, M. Bassler, G. Pensl, and M. Schulz. "Intrinsic SiC/SiO2 interface states." physica status solidi (a) 162, no. 1: 321-337 (1997).

Peters D. et al. "Investigation of threshold voltage stability of SiC MOSFETs." ISPSD (2018).

Okamoto M. et al. "Coexistence of small threshold voltage instability and high channel mobility in 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors." Applied Physics Express, vol. 5, nr. 4, p. 041302 (2012).

Maresca, L. et al. "Influence of the MOSFET Interface Traps Distribution on C V Measurements Evaluated by TCAD Simulations", IEEE Journal of Emerging and Selected Topics in Power Electronics, DOI 10.1109/JESTPE,2940143 (2019).

Sentaurus, T. C. A. D. "Manuals." Synopsys Inc., Mountain View, CA 94043 (2009).

Romano, G., et al. "Short-circuit failure mechanism of SiC power MOSFETs." 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE (2015).

Romano G. et al. "A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs." IEEE Journal of Emerging and Selected Topics in Power Electronics 4.3, p.978-987 (2016).

Matacena, Ilaria, et al. "Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Maresca, Luca, et al. "TCAD model calibration for the interface trap distribution of a planar SiC MOSFET." 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia). IEEE, 2020.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 669-675

doi: 10.4028/p-bzki64

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2022-01-27

Revised:
2022-02-23

Accepted:
2022-02-25

Online:
2022-05-31

Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.669.pdf

Ilaria Matacena , Luca Maresca , Michele Riccio , Andrea Irace , Giovanni Breglio and Santolo Daliento

1Department of Electrical Engineering and Information Technology, University of Naples "Federico II", Naples, Italy

ailaria.matacena@unina.it, bluca.maresca@unina.it, michele.riccio@unina.it, dandrea.irace@unina.it, breglio@unina.it, daliento@unina.it

Keywords: SiC MOSFET, hysteresis, capacitance, trench, planar.

Abstract

SiC MOSFETs have already replace silicon-based device in power applications, even if some technological issues are still not solved. The most important of them is related to the complex traps distribution at interface. Interface traps affect the overall device behavior, modifying channel mobility and introducing hysteresis. In this work experimental C-V and I-V curves are carried out on various commercial SiC MOSFET at different temperatures. The focus is the comparison of hysteresis arising in trench and planar SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1062.669.pdf

Silicon carbide (SiC) MOSFETs have replaced silicon devices due to the higher performance of SiC with respect to silicon material [1]. SiC has a higher bandgap and it claims a high thermal conductivity. These properties established the SiC as the most promising material for power MOSFETs. On the other hand, there are some issues not yet solved in technology, as the interface traps density at interface which affects the overall device behavior. It worth to be noted that traps density at the mentioned interface is order of magnitude higher than traps density existing at interface [2]. Traps density influences the channel mobility [3] and threshold voltage stability introducing also threshold voltage hysteresis [4-5]. For all these reasons, having a deep insight in traps density at such interface and counting on a reliable TCAD model is of paramount importance. At this purpose, experimental characterization of SiC MOSFETs together with the numerical results must be performed [6], [7]. Experimental characterization can be obtained considering current versus voltage (I-V) curves and capacitance versus voltage (C-V) curves. These latter allow to gain knowledge in MOSFET behavior through all its operating regions, as the accumulation, the depletion and the inversion. Nevertheless, capacitance is affected by traps existence and obviously by geometrical and process parameters. This is the case also for transfer I-V characteristics which are influenced by traps distribution. Since traps effect varies with temperature and, more in detail, it reduces as temperature increases, experimental characterization should be carried out at different temperatures.

In this work, after a theoretical introduction to the traps effect on the and curves, experimental C-V curves and I-V curves are presented at different temperatures. This analysis is performed on two different types of SiC MOSFETs: planar and trench devices. These data highlight that in planar devices the hysteresis occurs in both and curves, while this is not the case for trench MOSFETs where the hysteresis stands only in curves.

Traps Effects in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1062.669.pdf

Traps at the interface may introduce hysteresis in the and curve of a SiC MOSFET. Moreover, a strong threshold voltage temperature coefficient may occur if the trap concentration is very high, as for SiC MOSFET devices. In order to better understand traps effects on C-V and I-V curves, numerical analysis has been carried out using Sentaurus environment [8]. The results are presented in this work for a planar SiC MOSFET structure, Fig. 1 [6-11] as an example
to carry out general results. The effects of the interface traps on the capacitance behavior are investigated by implementing the experimental setup in numerical simulations. The equivalent TCAD C-V setup is shown in Fig.2. In this schematic, the driving voltage applied to the gate terminal of the device under test is , Fig.3. Interface traps dynamics takes into account the time variation in the capacitance behavior. Traps dynamics modifies the carriers distribution as the driving voltage varies. The traps dynamics is considered by changing the and values of Fig.3. A small signal AC analysis is performed in Sentaurus for each time step. This framework allows to investigate the driving voltage effect on the curves. The interface traps properties considered in simulation are explicated in Fig.4. Traps are considered through a square band distribution with a width, , and a distance from valence and conduction band equal to and , respectively. The adopted approach allows to take into account the effects of interface traps concentration, , the capture cross sections, and , in the numerical model.

Figure 1. SiC MOSFET TCAD model adopted in this work (the structure is not to scale).

Figure 1. Figure 1. SiC MOSFET TCAD model adopted in this work (the structure is not to scale).

Figure 2. Schematic of the mixed-mode circuit used for the simulation of the experimental setup.

Figure 2. Figure 2. Schematic of the mixed-mode circuit used for the simulation of the experimental setup.

Figure 3. Driving voltage, , applied to the MOSFET gate.

Figure 3. Figure 3. Driving voltage, , applied to the MOSFET gate.

The numerical C-V curves are presented for acceptor type traps with varying distance from both the conduction and the valence band edge, Fig.5. This numerical analysis has been performed also for donors type traps. The main outcome is that a hysteresis arises from traps existence. This hysteresis effect is not located in a particular part of the curve but different part of such curve are affected depending on traps properties: a) Acceptor type traps near to the valence band affect the region "A", highlighted in Fig. 5; b) Acceptor traps near to the conduction band affect the region "B" (threshold voltage hysteresis), highlighted in Fig. 5; c) Acceptor or donor type traps can be identified by comparing C-V curves obtained from the structure with an interface trap distribution with the CV curve of the structure without traps taken as reference. Same conclusions drawn in a) and b) apply to the analysis made considering donors type traps in the simulated structure.

Figure 4. Band diagram of the TCAD structure with trap distribution.

Figure 4. Figure 4. Band diagram of the TCAD structure with trap distribution.

The effects of traps distribution on transfer characteristics ( ) have also been studied, Fig.6. A hysteresis effect arises for VGS sweeping from both positive and negative voltage. The numerical framework implemented for the transfer characteristic simulations is shown in the inset of Fig.6. The voltage imposed between Drain and Source terminals is equal to , the voltage applied on the Gate, , has been scanned from 10 V to 0 V and vice versa. A hysteresis effect occurs for in the range .

Figure 5. Numerical C-V curves without traps (markers) and with an acceptors trap band with and varying. and .

Figure 5. Figure 5. Numerical C-V curves without traps (markers) and with an acceptors trap band with and varying. and .

Figure 6. Numerical transfer characteristic obtained considering an acceptor traps distribution with . In the inset the simulation framework adopted.

Figure 6. Figure 6. Numerical transfer characteristic obtained considering an acceptor traps distribution with . In the inset the simulation framework adopted.

Experimental Data

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Experimental characterization has been carried out through and curves on both planar and trench SiC MOSFETs. The two considered devices are commercial MOSFETs: device #1 [12] as planar structure and device #2 [13] as trench structure. The capacitance curves have been obtained using an Impedance Analyzer. The frequency has been imposed to 100 kHz , while the driving voltage has been swept from 20 V to -10 V and vice versa . The capacitance behaviour is different depending on the sweep direction of [6]. For this reason, two sweeps have been considered, the first one from positive to negative voltage (sweep down) and the second one from negative to positive voltage (sweep up). The C-V curves obtained for the two considered devices are shown in Fig.1. Considering these curves, it is clear as the hysteresis effect consists not only in the shift of the curves obtained during the sweep up and the sweep down but also in a considerable distortion of the two curves considered. It worth to be noticed that the hysteresis effect in device #1 stands only for higher than -15 V , since the two curves overlap in the remaining range. Two hysteresis effects are visible in these measurements: a first one occurring in the region A of Fig.7, and the second one taking place around the threshold voltage, region B of Fig.7. Considering the CV curve obtained numerically for a structure without traps [6], it is evident that the experimental curves show an unexpected behaviour. The obtained behaviour is caused to a complex traps distribution existing in the device at the interface. This traps distribution cannot be easily measured accessing only to device package and in a non-destructive analysis. Hence the need to perform numerical analysis, on the considered device, in a more complex way. This analysis includes TCAD simulations of the device under test considering interface traps distribution and it allows to have a clearer insight in the device physics along with the experimental capacitance curve behaviour. A better understand in traps distribution can be gained by considering the temperature behaviour of the curves. In Fig.8, the curves are obtained following the same setup values described above. The devices under test have been heated at the following temperatures: and 450 K . The hysteresis effect is less evident as temperature increases in both structures. From these measurements, it can be inferred that the capacitance behaviour of both the planar and the trench SiC MOSFETs considered suffers of visible hysteresis effects.

Figure 7. Experimental curves of the two SiC power MOSFET s considered, Cree CMF20120 and Infineon 12M1H140.

Figure 7. Figure 7. Experimental curves of the two SiC power MOSFET s considered, Cree CMF20120 and Infineon 12M1H140.

Figure 8. Experimental C-V curves of the two considered devices with temperature varying.

Figure 8. Figure 8. Experimental C-V curves of the two considered devices with temperature varying.

The characterization of the devices under test has been performed also in terms of transfer characteristics. In Fig. 9 the characteristics are shown. These curves have been obtained for a temperature of and 400 K . The curves have been carried out using a pulse I-V tracer. The pulse width has been set to . The voltage imposed between Drain and Source terminals is equal to , the voltage applied on the Gate, , has been scanned from 0 V to 20 V and vice versa. It can be stated from Fig.9, that hysteresis effect is visible only in the planar structure considered, and more in detail this effect is more visible for lower temperature. The I-V curves relative to the trench structure don't show any hysteresis effects.

Figure 9. Experimental characteristics obtained for different temperature values for the two considered devices.

Figure 9. Figure 9. Experimental characteristics obtained for different temperature values for the two considered devices.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.669.pdf

In this work, two types of SiC MOSFETs have been characterized: a planar device and a trench structure. Two commercial power SiC MOSFETs have been considered. The characterization has been performed through and curves. From these curves hysteresis effects emerged. More in detail, for planar device hysteresis effects occur in both and curves. For what it concerns the considered trench device, the hysteresis is only visible in curves. All the considered curves have been obtained also with increasing temperature. In particular, considering the curves for both devices it can be stated that hysteresis effects are less visible with increasing temperature.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.669.pdf

Baliga, B. J. "Fundamentals of power semiconductor devices". Springer Science & Business Media (2010).

C. Raynaud, J. L. Autran, J. B. Briot, B. Balland, N. Becourt, T. Billon, and C. Jaussaud. "Comparison of trapping-detrapping properties of mobile charge in alkali contaminated metal-oxide-silicon carbide structures." Applied physics letters 66, no. 18: 2340-2342 (1995).

V. V. Afanasev, M. Bassler, G. Pensl, and M. Schulz. "Intrinsic SiC/SiO2 interface states." physica status solidi (a) 162, no. 1: 321-337 (1997).

Peters D. et al. "Investigation of threshold voltage stability of SiC MOSFETs." ISPSD (2018).

Okamoto M. et al. "Coexistence of small threshold voltage instability and high channel mobility in (0001) metal-oxide-semiconductor field-effect transistors." Applied Physics Express, vol. 5, nr. 4, p. 041302 (2012).

Maresca, L. et al. "Influence of the MOSFET Interface Traps Distribution on C V Measurements Evaluated by TCAD Simulations", IEEE Journal of Emerging and Selected Topics in Power Electronics, DOI 10.1109/JESTPE,2940143 (2019).

Matacena, Ilaria, et al. "Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Sentaurus, T. C. A. D. "Manuals." Synopsys Inc., Mountain View, CA 94043 (2009).

Romano, G., et al. "Short-circuit failure mechanism of SiC power MOSFETs." 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE (2015).

Romano G. et al. "A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs." IEEE Journal of Emerging and Selected Topics in Power Electronics 4.3, p.978987 (2016).

Maresca, Luca, et al. "TCAD model calibration for the interface trap distribution of a planar SiC MOSFET." 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia). IEEE, 2020.

CMF20120, .html

12M1H140,

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 676-682

doi: 10.4028/p-794hb3

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-15

Revised:
2022-02-21

Accepted:
2022-03-07

Online:
2022-05-31

Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

The original version of this paper is available on https://www.scientific.net/MSF.1062.676.pdf

Yusuke Yamashiro , Masakazu Okada , Masakazu Baba , Takanori Tanaka , Shingo Tomohisa , Hiroshi Watanabe , Kazutoshi Kojima , Shinsuke Harada and Hiroshi Yamaguchi

National Institute of Advanced Industrial Science and Technology, Japan

Mitsubishi Electric Co., Ltd., Japan

Yamashiro.Yusuke@da.MitsubishiElectric.co.jp, masakazu-okada@aist.go.jp, masakazu-baba@aist.go.jp, takanori.tanaka@aist.go.jp, Tomohisa.Shingo@cw.MitsubishiElectric.co.jp, 'Watanabe.Hiroshi@dh.mitsubishielectric.co.jp, kazu-kojima@aist.go.jp, s-harada@aist.go.jp, ihiroshi-yamaguchi@aist.go.jp

Keywords: Super junction, Stacking fault, Body diode, Photoluminescence

Abstract

We evaluated stacking faults expanding by body diode current stress in the SiC Semi-SJ MOSFET for the first time. It was found that body diode degradation of the SJ MOSFETs tends to be smaller than that of conventional Non-SJ MOSFETs. Detailed crystal evaluations revealed that the stacking faults did not expand into the SJ structure. It is assumed that the expansion stops due to low carrier densities. The result suggests that the SJ device has a high potential as a device for suppressing the body diode degradation.

Introduction

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Silicon carbide ( SiC ) has excellent properties such as high maximum electric field and high thermal conductivity. The SiC MOSFET shows lower power loss characteristics than Si MOSFET and has been used as a commercial power device. SiC superjunction (SJ) MOSFET is promising as the next-generation power device with further low on-resistance. In recent years, excellent electrical characteristics of 1.2 kV - and 3.3 kV -class SJ MOSFETs have been demonstrated [1-3]. On the other hand, it is well known that the electrical characteristics of SiC MOSFETs such as on-resistance and forward voltage ( ) are degraded by the expansion of stacking faults (SSFs) due to body diode current stress [4, 5]. The mechanism and suppressing methods for the expansion of SSFs have been investigated in the Non-SJ SiC MOSFET. In this study, we investigated the behavior of SSFs in the SiC SJ MOSFET for the first time, which expands by body diode current stress. The attractive advantages of SJ MOSFET were discussed in comparison to Non-SJ MOSFETs.

Experiment

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Figure 1 shows a cross-sectional schematic of the 1.2 kV -class SJ MOSFET and Non-SJ MOSFET used in this study. The fabrication flow of a 1.2 kV -class Semi-SJ MOSFET is as follows. First, an n-epi layer was grown on a n-type substrate with an off-cut angle of toward the [11-20] direction. Next, the SJ layer, an epitaxial layer containing the p-type pillar, was fabricated on the nepi layer by multi-epitaxial method with aluminum ion (Al+) implantation. We defined the p-type pillar as p -pillar and the remaining n -type region as n -pillar. The doping concentrations of the n -epi, p-pillar, and n-pillar are , and . The thicknesses of n-epi layer and SJ layer are and . The p-pillar was patterned in stripes in parallel to [11-20] direction with a pitch of . A trench gate MOSFET with a cell pitch of was employed as the MOSFET structure. The trench bottom p-region functioning as a gate shielding structure is in contact with the source electrode. A buffer layer that enhances hole recombination was not introduced
on the substrate to intentionally expand the SSF from the epi/sub interface [6]. All SJ devices used in this study are Semi-SJ type MOSFET, which consists of an n-epi layer and SJ layer. Non-SJ MOSFETs were prepared as reference samples, with a thick drift layer and same chip size as SJ.

The body diode current was applied under stress conditions with current densities of and the chip temperature of . The stress of was applied in pulses with the total on-state time of 5 minutes, and the other current stresses were applied in DC for 10 minutes. The forward I-V characteristics of the MOSFETs were measured before and after the body diode current stresses using a curve tracer Keysight B1505A. The chip temperature and the gate voltage were set to and -5 V , respectively. After the current stresses and I-V measurements, the electrodes and the oxides were removed and photoluminescences were measured. A band pass filter of 460 nm was used to observe SSFs in the SJ MOSFET. Some samples were evaluated in more detail by using the synchrotron radiation topography and cross-sectional TEM. Carrier densities during body diode current stress were calculated by using Sentaurus TCAD simulation.

Fig. 1. Schematic of the 1.2 kV-class SJ MOSFET and Non-SJ MOSFET.

Fig. 1. Schematic of the 1.2 kV-class SJ MOSFET and Non-SJ MOSFET.

Results and Discussion

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Body diode current stresses were applied in the order of 50,300 , and . Figure 2 shows the shift of the against the body diode current stresses. The is defined as the voltage at the current density of in the I-V characteristics. The shift in typical Non-SJ MOSFET are 3.6 mV for and 4.5 mV for . In contrast, the shifts in the SJ MOSFET is 2.0 mV for , which is smaller than that of Non-SJ MOSFETs, and there is no further significant increase even by applying .

Fig. 2. Shift of forward voltage plotted against current density of the body diode current stresses of the Non-SJ and SJ MOSFETs.

Fig. 2. Shift of forward voltage plotted against current density of the body diode current stresses of the Non-SJ and SJ MOSFETs.

The shift is caused by SSFs expansion because the SSFs have high resistance and prevent the current path. Thus, the size of SSFs correlates with the shift. The sizes of the triangular SSFs after the stress were evaluated by PL images. Figure 3 shows PL images of typical triangular SSFs in Non-SJ and SJ MOSFETs measured for various current densities. The SSF expands in a basal plane with a tilt. Therefore the thickness of the epitaxial layer where the SSF expands is estimated by the width of the horizontal direction. The width of SSF in Non-SJ is , which is equivalent to the thickness of the drift layer. On the other hand, the width of SSF in SJ MOSFETs is only , which is less than the entire thickness including the SJ layer and n-epi layer. This means that the SSF does not expand throughout the entire drift layers. The width of SSF is equivalent to the thickness of the n-epi layer and is almost the same when the current density is increased up to 1200 .

Fig. 3. Photoluminescence images of epitaxial layer of Non-SJ and SJ MOSFETs.

Fig. 3. Photoluminescence images of epitaxial layer of Non-SJ and SJ MOSFETs.

Fig. 4. Synchrotron radiation topographic image of SSF in SJ MOSFET.

Fig. 4. Synchrotron radiation topographic image of SSF in SJ MOSFET.

Fig. 5. (a) PL image of SJ MOSFET. A-D indicates the area for crosssectional TEM observation. (b) Magnified image near the line segments A and B

Fig. 5. (a) PL image of SJ MOSFET. A-D indicates the area for crosssectional TEM observation. (b) Magnified image near the line segments A and B

The PL images of SSFs are not clear in SJ MOSFETs because the high doping densities of p- and n-pillars weaken the contrast of the SSFs. Therefore it is uncertain whether the SSF is really small or same size as Non-SJ but invisible due to the high doping density. The overall shape of SSFs was confirmed by synchrotron radiation topography, which allows observation of partial dislocations and basal plane dislocations (BPDs) without the effect of doping density. Figure 4 shows the synchrotron radiation topographic image of SSFs with the SiC [0-2210] as the diffraction surface in the SJ MOSFET sample. The current density of has been applied at the chip temperature of . Partial dislocations were clearly observed at the boundary around the SSF. The width of the SSF indicated by the yellow arrow is almost the same as that observed by the PL. The BPD is also observed near the corner of the SSF, indicated by the red arrow. It was confirmed that the SSF starts expanding from the BPD and the width in SJ MOSFETs is less than that assumed from the thickness of the entire drift layer.

Cross-sectional TEM images of SJ MOSFETs were taken to confirm the position where SSF stopped. Figure 5(a) shows a PL image in the SJ MOSFETs after current stress of . The yellow dashed line indicates the size of SSFs observed by PL and the blue dashed line indicates the size of SSF if it had expanded to the entire drift layer. However, no SSFs are visible inside the blue dashed line. Figure 5(b) is a magnified image near the line segments A and B that are inside the ppillar and n -pillar, respectively, and cross the boundary of visible SSFs.

Figure 6(a) and (b) show cross-sectional TEM images and schematics correspond to the line segments A and B . The SSFs were found in both images at a depth position of from the SJMOSFET surface, indicating the presence of a SSF in the n-epi layer. Figure 6(c) is a cross-sectional TEM image corresponding to line segment C, which is the position shifted by from line segment A toward the [11-20] direction. No SSFs were observed in the TEM image, indicating the SSFs are not present in the p-pillar. Figure 6(d) is cross-sectional TEM images corresponding to line segment D , which has the orthogonal direction to the line segment C . SSFs were not observed in the p- and the n-pillars. These results indicate that the expansion of SSF is stopped near the interface between the n-epi layer and the SJ layers. It is expected that the SJ structure or its fabrication process is causing the suppression of the SSF expansion.

Fig. 6. Cross section TEM images and their schematics of SJ MOSFET. The cross-sectional TEM images (a-d) correspond to the line segments A-D.

Fig. 6. Cross section TEM images and their schematics of SJ MOSFET. The cross-sectional TEM images (a-d) correspond to the line segments A-D.

We consider the mechanism for stopping the expansion of SSFs in terms of carrier density because carrier density is one of the most important factors for the expansion of SSF. Electron and hole densities under the body diode current stress were estimated by using a device simulator. Figure 7 shows the cross-sectional structure and cut line plots under stress conditions with the current density of and the chip temperature of . The cut line positions are inside the p-pillar for the electron density, and inside the n-pillar for the hole density. The carrier lifetime of SiC is assumed to be shortened by the ion implantation damage and high doping density, so it is set to of the typical value within the p -pillar and n -pillar [7]. In the Non-SJ, the electron and hole densities are estimated to be and over the whole area of the drift layer. They are high enough to expand SSFs because threshold excess carrier density at is estimated at around [8, 9]. On the other hand, in the SJ MOSFETs, the electron and hole densities near the interface between the n-epi layer and the SJ layer are estimated to be much lower than those of Non-SJ, and close to the threshold excess carrier density.

Fig. 7. Cross-sectional structure of Non-SJ and SJ MOSFETs. Right figures show electron and hole density profiles along the cut lines.

Fig. 7. Cross-sectional structure of Non-SJ and SJ MOSFETs. Right figures show electron and hole density profiles along the cut lines.

Figure 8 shows a 3D cross-sectional schematic of the SSF in the SJ MOSFET. Most of BPDs propagating from substrates are converted to threading edge dislocations (TEDs) at the n-epi layer/substrate interface. The SSFs expand along the basal plane from the BPDs near the n-epi layer/substrate interface. The expansion of SSF goes through the n-epi layer due to the high carrier density in the n-epi layer. When the SSFs reach the bottom of the SJ layer, the expansion stops in [11-20] direction due to the low carrier density which is shorted by the ion implantation damage and high doping density. It is expected that in the case of full-SJ with a long p-pillar, the expansion of SSFs is further small and the body diode degradation is more suppressed. If the SJ structure suppresses the expansion of SSFs even in a wide temperature range and high current density, it is possible to use body diode without Shottky diode in parallel with MOSFET. This may lead to chip cost deduction. This suppression of body diode degradation is an attractive advantage of SJ-MOSFET.

Fig. 8. 3D cross-sectional schematic of SSF in the SJ MOSFET.

Fig. 8. 3D cross-sectional schematic of SSF in the SJ MOSFET.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1062.676.pdf

In this study, we investigated the behavior of SSFs expanding by body diode current stress in the SiC SJ MOSFET for the first time. It was demonstrated that the expansion of SSF was effectively suppressed even at the high current density of and found that SJ MOSFET had a smaller SSF size and lower forward voltage shift than Non-SJ MOSFET. The expansion of SSFs stops near the interface between the n-epi layer and SJ layers due to low carrier densities in the SJ layers. The MOSFET with the SJ structure has a high potential as a device not only reducing the on-resistance but also for suppressing the body diode degradation. In the future, the attractive advantage of SJMOSFET will contribute to expanding the application area of SiC SJ devices. We will investigate in detail high voltage class devices and Full-SJ devices in the future.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1062.676.pdf

This work was performed under a joint research project with Tsukuba Power Electrics Constellations (TPEC). The author, Y. Yamashiro is assigned from Mitsubishi Electric Co., Ltd.; M. Okada is assigned from Toyota Motor Corporation; M. Baba is assigned from Fuji Electric Co., Ltd.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.676.pdf

S. Harada, Y. Kobayashi, S. Kyogoku, T. Morimoto, T. Tanaka, M. Takei and H. Okumura, First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multiepitaxial Growth Method, 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 8.2.1-8.2.4, 2018.

M. Baba, T. Tawara, T. Morimoto, S. Harada, M. Takei and H. Kimura, Ultra-Low Specific onResistance Achieved in 3.3 kV -Class SiC Superjunction MOSFET, 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 83-86, 2021.

T. Masuda, Y. Saito, T. Kumazawa, T. Hatayama and S. Harada, 4H-SiC Super Junction V-Groove Trench MOSFET, 2018 IEEE International Electron Devices Meeting (IEDM), pp. 8.1.1-8.1.4, 2018.

K. Konishi, S. Yamamoto, S. Nakata, Y. Nakamura, Y. Nakanishi, T. Tanaka, Y. Mitani, N. Tomita, Y. Toyoda and S. Yamakawa, Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in epilayers under high current stress, Journal of Applied Physics 114, 014504, 2013.

A. Agarwal, H. Fatima, S. Haney and S. Ryu, A New Degradation Mechanism in High-Voltage SiC Power MOSFETs, IEEE Electron Device Letters, 28, 7, pp. 587-589, 2007.

T. Tanaka, N. Kawabata, Y. Mitani, N. Tomita, M. Tarutani, T. Kuroiwa, Y. Toyoda, M. Imaizumi, H. Sumitani and S. Yamakawa, Demonstration of High Quality 4H-SiC Epitaxial Growth with Extremely Low Basal Plane Dislocation Density, Materials Science Forum, 778-780, pp. 91-94, 2014.

T. Fukui, T. Tawara and M. Kato, Effects of the ion implantation process on carrier lifetimes in 4H-SiC SJ-MOSFET, 2021 International Conference on Solid State Devices and Materials (SSDM), online, D-4-07, 2021.

A. Iijima and T. Kimoto, Theoretical and experimental investigation of critical condition for expansion/contraction of a single Shockley stacking fault in 4H-SiC, Europ. Conf. on Silicon Carbide and Related Materials (ECSCRM), Birmingham, UK, MO.04.02, 2018.

T. Tawara, S. Matsunaga, T. Fujimoto, M. Ryo, M. Miyazato, T. Miyazawa, K. Takenaka, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto and H. Tsuchida, Injected carrier concentration dependence of the expansion of single Shockley-type stacking faults in PiN diodes, Journal of Applied Physics 123, 025707, 2018.

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The original version of this eBook is available on https://www.scientific.net/book/silicon-carbide-and-related-materials-2021/978-3-0357-3824-7

Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 683-687

doi: 10.4028/p-uf94le

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-18

Accepted:
2022-02-16

Online:
2022-05-31

Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

The original version of this paper is available on https://www.scientific.net/MSF.1062.683.pdf

Joseph A. McPherson , Andrew A. Woodworth , T. Paul Chow , Wei Ji

¹Department of Mechanical, Aerospace, and Nuclear Engineering, Rensselaer Polytechnic Institute, Troy, New York, 12180, U.S.A.

NASA Glenn Research Center, Cleveland, Ohio, 44135, U.S.A.

Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York, 12180, U.S.A.

mcphej4@rpi.edu, andrew.a.woodworth@nasa.gov, chowt@rpi.edu, diw2@rpi.edu

Keywords: Power MOSFET, DMOSFET, Single-event burnout, Heavy lons, Single-event effects, Superjunction

Abstract

We compare the failure mechanism and performance of a silicon carbide (SiC) semisuperjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P -pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage ( ). The varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of is reached when the pillar to drift layer ratio is 0.9 and the pillar width is . The semi-SJ SEB/breakdown voltage ratio is and higher than the pure SJ and conventional DMOSFET, respectively. Using a new Figure of Merit (FoM), which accounts for the tradeoff between V SEB and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FoM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.

Introduction

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Vertical based power devices are of interest in power electronics applications that require breakdown voltages (BV) greater than 300 V by providing improved efficiency compared to Si-based devices. Even greater efficiency can be achieved using a superjunction (SJ) design, which can reduce significantly below the 1-D limit [1]. In space applications, however, high-voltage power devices are susceptible to the single-event burnout (SEB) due to heavy ion strikes, causing the catastrophic destruction of the device. It has been shown experimentally that SEB, in conventional DMOSFETs, can occur at less than of the device rated blocking voltage [2]. The failure process has been analyzed by simulations, and it is initiated by the generation of an electronhole plasma from the heavy ion strike, enhancing the electric field at the N epitaxial/N+ substrate interface (Kirk effect), leading to the formation of a mesoplasma at the interface [3]. Further simulation study shows that the SEB threshold voltage ( ), for conventional DMOSFETs, can be increased by inserting a buffer layer between the epitaxial and substrate layers, which helps suppress the electric field enhancement [4]. In this paper, we demonstrate that the Vseb can be increased substantially in semi-SJ devices which are derived from SJ devices by adding a uniformly doped layer between SJ pillars and substrate.

Semi-SJ Simulation Models

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The semi-SJ model investigated has a thick drift layer ( ), with a portion of the drift taken up by the alternating N+/P+ SJ pillars ( ) and the remaining thickness having a uniformly
doped layer ( ) labeled as triangular field layer (TFL) seen in Fig. 1b. The TFL is designed so that a triangular electric field profile forms across the TFL when the device undergoes avalanche breakdown. Two different pillar widths for the SJ portion were explored ( and ) along with 3 different semi-SJ ratios ( , and 0.5 ), which is calculated by dividing by . The semi-SJ structure was also compared against a pure SJ and conventional DMOSFETs with equal total drift region thickness seen in Fig. 1c and 1d.

Fig. 1. Simulation models showing a) 3-D view of the semi-SJ, 2-D cross-section of b) semi-SJ, c) SJ, and d) conventional DMOSFETs. Black dotted lines denote simulated heavy ion path. Axis in .

Fig. 1. Simulation models showing a) 3-D view of the semi-SJ, 2-D cross-section of b) semi-SJ, c) SJ, and d) conventional DMOSFETs. Black dotted lines denote simulated heavy ion path. Axis in .

Single-Event Burnout Simulations and Results

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The SEB event was simulated using 3-D transient electro-thermal models described in prior work [3]. The heavy ion used in these simulations is a 1289 MeV silver ion with a linear energy transfer of . Center of the P- and N-pillar strike locations were investigated, however it was found that the P-pillar is the weakest location and only these results will be presented. SEB was declared when the lattice temperature reaches 3000 K in simulation, which is the decomposition temperature of SiC and has previously been found to produce SEB results that are in agreement with test results from conventional DMOSFETs [3].

Fig. 2 shows the for various pillar widths and semi-SJ ratios used for the semi-SJ DMOSFET. The pure SJ and the conventional DMOSFET results are for semi-SJ ratios of 1 and 0 in the figure, respectively. The maximum occurs when the semi-SJ ratio is 0.9 , and the is 2050 V . This configuration is used to discuss the SEB failure mechanism. When the heavy ion strikes the SiC crystalline lattice, electron-hole pairs are generated [5,6], and the resulting density exceeds the background doping concentration by several orders in the drift region. These charge carriers traverse the devices to their respective terminals, with the electrons going towards the drain

Fig. 2. V Seb dependence on semi-SJ ratio for 2.4 and pillar widths.

Fig. 2. V Seb dependence on semi-SJ ratio for 2.4 and pillar widths.

Fig. 3. 1-D time evolution of electric field for 0.9 semi-SJ ratio and pillar width along the heavy ion track at 2100 V .

Fig. 3. 1-D time evolution of electric field for 0.9 semi-SJ ratio and pillar width along the heavy ion track at 2100 V .

Fig. 4. 2-D lattice temperature graphs showing the failure location (formation of the mesoplasma) for P-pillar strikes of widths of a) Semi-SJ, b) SJ, and c) conventional DMOSFET designs. Axis in .

Fig. 4. 2-D lattice temperature graphs showing the failure location (formation of the mesoplasma) for P-pillar strikes of widths of a) Semi-SJ, b) SJ, and c) conventional DMOSFET designs. Axis in .

and the holes towards the source contact. This movement results in the distortion of the electric field profile, a typical phenomenon of the Kirk effect, as seen in Fig. 3 . By 2.5 ps, an enhancement is seen under the source contact ( ) and at the TFL/substrate interface ( ). This behavior is due to the buildup of excess holes and electrons under the source contact and TFL/substrate interface, respectively. The field under the source contact is short-lived and by 63 ps , it effectively disappears because the carriers short the source/body and body/drift junctions, causing an injection of electrons from the source region. These electrons help to balance the excess holes and effectively neutralize the surface electric field.

Fig. 5. FoM dependence on semi-SJ ratio for 2.4 and .

Fig. 5. FoM dependence on semi-SJ ratio for 2.4 and .

Despite the surface field reduction, the field at the TFL/substrate interface continues to increase and reaches a maximum value of by 63 ps . This field enhancement would normally lead to significant impact ionization causing additional carriers to be generated yielding high localized current densities and eventually the formation of a mesoplasma [3,4]. This is the failure mechanism and location for both the conventional and pure SJ DMOSFET seen in Fig. 4b and 4c. However, with the introduction of the TFL, the electric field starts to shift from the TFL/substrate interface to the SJ/TFL interface by 100 ps . Despite the shifting of the electric field and the reduction from 3.1 to by 490 ps , the semi-SJ DMOSFET experiences SEB near SJ/TFL interface as seen in Fig. 4a. The failure mechanism is due to the sustained heating near the interface from the charge carriers generated from the impact ionization event leading to the formation of a mesoplasma
deep in the SJ layer. This shifting of the electric field and the resulting mesoplasma significantly improves the to almost twice that of the pure SJ and conventional DMOSFETs.

Table 1. Summary of static and SEB performance of SJ, conventional, and semi-SJ DMOSFETs

Semi-
SJ
Ratio
VSEB
(V)
BV
(V)
Ron,sp
(mΩ-cm²)
RIDLimit
(mΩ-cm²)
FoM:
SEB/BV*RIDLimit/Ron,sp

2.4
μm
1.2
μm
2.4
μm
1.2
μm
2.4
μm
1.2
μm
2.4
μm
1.2
μm
2.4 μm
1.2 μm

1.0
1050
950
5103
5077
4.2
3.2
13.6
13.5
0.7
0.9

0.9
2050
1750
4911
4897
4.1
3.2
11.7
11.6
1.3
1.6

0.75
2050
1850
4631
4619
4.2
3.4
8.8
8.8
1.2
1.4

0.5
1850
1350
4145
4146
4.9
4.3
6.3
6.5
0.8
0.6

0.0
1250
3354
8.0
5.2
0.2

Performance Comparison

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Table 1 summarizes the simulated static on-state and blocking characteristics, SEB performance, and a new Figure of Merit (FoM) for all three DMOSFET (conventional, SJ, and semi-SJ) designs. This new FoM highlights the tradeoff between SEB and on-state performances. In Fig. 5, we can see, using this new FoM, that the overall performance of these Semi-SJ DMOSFETs is better than that of SJ devices. This is due to the substantial, 64-116%, improvement in the VSEB in both SJ and conventional devices (Fig. 2), with only a small, less than , increase in specific onresistance. In addition, the failure (mesoplasma formation) location has shifted to a spot about 26 from the surface within the P-pillar for the Semi-SJ case, as illustrated in Fig. 4a. This change in mesoplasma location allows a higher blocking voltage to be supported during heavy ion bombardment by mitigating the peak electric field and suppressing carrier impact ionization cascades. Additionally, when compared to commercially available 1200 V rated conventional DMOSFETs [7], the specific on-resistance is only higher when using the best FoM design with pillar width of and a semi-SJ ratio of 0.9 .

Summary

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Using simulations, the mechanisms for SEB failure in semi-SJ power devices from a single heavy ion strike have been investigated. We have shown that the failure is due to the enhancement of the electric field at the SJ/TFL interface causing thermal runaway from impact ionization leading to the formation of a mesoplasma. When compared to the pure SJ and conventional DMOSFET designs, the semi-SJ can achieve superior SEB performance that is almost twice that of either SJ or conventional and a specific on-resistance that is lower than the conventional. This makes the semi-SJ DMOSFET design a suitable candidate for applications requiring radiation hardening.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1062.683.pdf

The first author is supported by the Nuclear Regulatory Commission Fellowship Program under the grant 31310018M0003.

References

The original version of this paper is available on https://www.scientific.net/MSF.1062.683.pdf

X. Zhou et al., Performance Limits of Vertical and Superjunction Devices, Materials Science Forum 963, 693 (2019).

J.-M. Lauenstein et al., Space Radiation Effects on SiC Power Device Reliability, in 2021 IEEE International Reliability Physics Symposium, Monterey, CA, 1.

J. A. McPherson et al, Mechanisms of Heavy Ion-Induced Single Event Burnout in 4H-SiC Power MOSFETs, Materials Science Forum 1004, 889 (2020).

J. A. McPherson et al., Ion-Induced Mesoplasma Formation and Thermal Destruction in 4HSiC Power MOSFET Devices, IEEE Trans. Nucl. Sci. 68, 651 (2021).

D. K. Avasthi, G. K. Mehta, Ion Matter Interaction, in Swift Heavy Ions for Materials Engineering and Nanostructuring, 145, 47 (2011).

T. Nitta et al., Cosmic Ray Failure Mechanism and Critical Factors for 3.3 kV Hybrid SiC Modules, in PCIM Europe 2016; International Exhibition and Conference Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 566.

B. Hull et al., Reliability and stability of SiC power MOSFETs and Next-Generation SiC MOSFETs, in 2014 IEEE Workshop on Wide Bandgap Power Devices and Applications, Knoxville, TN, 139.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1062, pp 688-695

doi: 10.4028/p-pijkeu

© 2022 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2021-10-20

Revised:
2022-03-07

Accepted:
2022-03-07

Online:
2022-05-31

Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

The original version of this paper is available on https://www.scientific.net/MSF.1062.688.pdf

Michael Waltl , Yoanlys Hernandez ,

Christian Schleich , Katja Waschneck , Bernhard Stampfer , Hans Reisinger and Tibor Grasser

Christian Doppler Laboratory for Single-Defect Spectroscopy at the Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29, 1040 Vienna, Austria

Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29, 1040 Vienna, Austria

Infineon Technologies AG, Am Campeon 1-15, 85579 Munich, Germany

waltl@iue.tuwien.ac.at, hernandez@iue.tuwien.ac.at, schleich@iue.tuwien.ac.at, Katja.Waschneck@infineon.com, stampfer@iue.tuwien.ac.at, Hans.Reisinger@infineon.com, grasser@iue.tuwien.ac.at,

*corresponding author

Keywords: SiC Transistors, Inverter Circuits, Spice Simulation, Charge Trapping, Bias Temperature Instabilities, AC Stress.

Abstract

For the analysis of the characteristics and behavior of circuits prior to fabrication and to improve circuit performance, simulations using Spice tools are typically performed. Such tools rely on static compact models describing the behavior of the individual circuit components such as transistors. In reality, the behavior of the transistors changes over time due to aging, for instance, as a consequence of bias temperature instabilities (BTI). BTI is typically referred to as a drift of the threshold voltage of a transistor due to charge trapping at oxide and interface defects. To explain BTI, power-law-like mathematical expressions are often employed. However, using these simple formulas, the experimental data can only be replicated with limited accuracy. To evaluate the performance of logic inverter circuits made from CMOS transistors with high precision, we use a physicsbased defect model to describe the change of the device behavior from a defect-centric perspective. Our results indicate the limitations of using power-law-like formulas as they lead to an overly pessimistic estimation for circuit parameters.

Introduction

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Transistors fabricated on 4H-SiC substrates exhibit superior properties, such as high blocking voltage capabilities, high thermal conductivity, etc., making them perfect candidates for high-power switching applications. In the recent past, lots of research has been conducted towards consistently improving the performance of SiC devices. Despite the numerous advantages over silicon devices, it has to be noted that the defect densities observed for various SiC technologies are considerably larger. Consequently, specific reliability issues, e.g., bias temperature instabilities (BTI) and gate leakage currents appear to be more prominent for SiC technologies [1], [2]. However, even though a more pronounced change in the device performance during operation can be observed than for Si transistors, not all reliability issues are a severe threat for circuits and applications. For instance, BTI, which is referred to as a drift of the threshold voltage of the transistor over time, can be mitigated in switching applications by using large gate overdrive voltages. It is evident that this is not optimal and leads to a slightly increased power consumption of the transistor during the switching cycles, which should be avoided.
The origin of BTI and the related drift of the threshold voltage lies in the charge trapping of defects located at the interface between the insulator and the SiC substrate [3]. Compared to Si technology, an approximately two orders of magnitude larger defect densitiy can be observed for SiC transistors. To improve the quality of the interface and oxide, post-oxidation annealing has been added to
the fabrication process. The impact of POA using different ambients has been studied recently. Using nitric oxide (NO) for POA, the electrical properties of the could be significantly improved, enabling commercially available SiC MOS transistors [4]-[6]. However, there is still room for further improvement of the quality of the interface between the insulator and the SiC substrate to exploit the full potential of SiC technology.

Fig. 1: The circuit diagram of the Pseudo-D CMOS inverter using 4H-SiC nMOS transistors is shown in [7]. The inverter consists of an input and an output stage. In our work, we analyze the inverter performance considering the degradation of the threshold voltage of the SiC transistors.

Fig. 1. The circuit diagram of the Pseudo-D CMOS inverter using 4H-SiC nMOS transistors is shown in [7]. The inverter consists of an input and an output stage. In our work, we analyze the inverter performance considering the degradation of the threshold voltage of the SiC transistors.

Based on the results from investigating reliability issues at the transistor level, one can evaluate their impact on the performance of circuits and applications. While computer simulations using physicsbased TCAD software are primarily used to explain the characteristics of devices, circuit simulations are often carried out using Spice software. Spice simulations are vital for optimizing circuit performance and verifying designs operating stably under various operating conditions. In such simulations, compact models are typically used to mimic the behavior of the devices to evaluate the behavior of applications [8].
This work closely examines the pseudo-D CMOS inverter [7] shown in Fig. 1 using a commercially available technology, i.e., C3M0065090J manufactured by Cree. For this, a combination of Spice simulations based on a compact model provided by Cree and our reliability tools, that are calibrated to explain BTI under DC and AC operating conditions for single transistors [9], are used. Afterward, the susceptibility of the signal propagation delay of the D-inverter circuit is evaluated.

Characterization of Reliability Issues of SiC Transistors

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For the characterization of BTI, the measure-stress-measure (MSM) scheme is typically used [10], [11]. The MSM scheme consists of a series of stress and recovery phases where the stress and recovery times are continuously increased, as shown in Fig. 2. During the stress phase (red), the drainsource voltage is kept at 0 V to prevent any hot-carrier degradation-related effects and ensure a homogenous carrier distribution at the interface along the channel. In the stress phase, where a high gate voltage is applied, many interface and oxide defects can become charged. Subsequently, recovery biases are used at the gate terminal (near the threshold voltage) and drain-source terminals (in the range of 0.1 V ), and the drain-source current is monitored. Even though constant biases are applied during the recovery phase, a drift of the drain-source current can be observed due to charge emission of defects that became charged during the prior stress phase. With increasing number of stress/recovery cycles, the observed drift becomes more and more prominent as longer stress and recovery times enable more defects to become charged. This is a consequence of the fact that discharging typically takes considerably longer than charging, meaning that even for an AC signal with a duty factor , defects become charged with time. It has to be noted that this DC-MSM scheme is carried out using various gate stress biases and temperatures to evaluate the impact of charge trapping on the performance of the device as accurately as possible. For each measurement series, a fresh transistor has to be used as precise knowledge of the history of the drain and gate biases of the transistor are of utmost importance for the accuracy of the model parameters. Note that an initial IDVG characteristic is measured within a narrow gate bias range, and therefrom the time-zero is extracted. The limited bias range is vital to avoid altering the charge state of the defects. This procedure allows accounting for device-to-device variability issues when the drift of is extracted
from the MSM measurement. For discussion of the experimental data, the measured drift of the drainsource current is often represented as a change in the threshold voltage . This can be achieved by converting the current to an equivalent gate voltage using an initially measured IDVG characteristic [12], [13].
The most application-relevant gate bias patterns for SiC transistors are AC signals. To monitor the drift of the threshold voltage under AC bias conditions, a switching gate voltage is applied and interrupted at well-defined time points to measure and extract the current value of the device threshold voltage [14].

Fig. 2: Two typical gate voltage patterns are used to extract the behavior of SiC transistors under the most application-relevant operating conditions. (top) Characteristic for the DC-MSM scheme is a constant stress bias applied before the recovery phase is recorded [15]. (bottom) For the selected AC measurement scheme, the AC signal is interrupted precisely at the end of the high-phase to consistently measure the drift of the threshold voltage [9], [14].

Fig. 2. Two typical gate voltage patterns are used to extract the behavior of SiC transistors under the most application-relevant operating conditions. (top) Characteristic for the DC-MSM scheme is a constant stress bias applied before the recovery phase is recorded [15]. (bottom) For the selected AC measurement scheme, the AC signal is interrupted precisely at the end of the high-phase to consistently measure the drift of the threshold voltage [9], [14].

The experimental results for DC and AC-MSM measurements from a commercial transistors technology are shown in Fig. 3. As can be seen, a drift of the threshold voltage of more than for the DC/AC-MSM case can be observed. The solid lines are extracted from our simulations using our defect model that accurately replicates the experimental data and will be discussed in the next section in further detail.

Fig. 3: The transient behavior of a SiC transistor obtained from applying the schemes of Fig. 2. (top) DC stress/recovery. (bottom) AC stress experiments. As can be seen for both cases, the drift characteristics of the (symbols) of the devices can be accurately explained by our physical model (lines). The data has been measured at different biases and temperatures to calibrate the models for a large variety of operating conditions [9]. It has to be noted that all trends can be consistently explained by our model using the same trap parameters, enabling fully accurate analysis of the impact of degradation on the performance of circuits.

Fig. 3. The transient behavior of a SiC transistor obtained from applying the schemes of Fig. 2. (top) DC stress/recovery. (bottom) AC stress experiments. As can be seen for both cases, the drift characteristics of the (symbols) of the devices can be accurately explained by our physical model (lines). The data has been measured at different biases and temperatures to calibrate the models for a large variety of operating conditions [9]. It has to be noted that all trends can be consistently explained by our model using the same trap parameters, enabling fully accurate analysis of the impact of degradation on the performance of circuits.

Modeling of Bias Temperature Instabilities

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To provide an explanation for the experimental data, simple power-law or exponential-like functions are often used [17]-[19] as they offer a fast and straightforward method to quantify the results with a reduced parameter set. However, such empirical formulations must be treated with care as they do not provide a physics-founded description of the underlying mechanisms. For instance, a serious limitation of power-law expressions is that the saturation of the drift of the threshold voltage with increasing stress time can not be explained, see Fig. 4. As a consequence, the extrapolations may not

Fig. 4: Our physical charge trapping model [16] and a powerlaw, i.e., , is applied to explain the experimental data. As can be seen, the power-law function does not account for saturation of , which is one of the weaknesses of this approach. Ultimately, this leads to a considerable overestimation of the measured degradation. In contrast, the physical defect model can be calibrated to replicate the measurement results. (The dashed line serves as guide for the eye).

Fig. 4. Our physical charge trapping model [16] and a powerlaw, i.e., , is applied to explain the experimental data. As can be seen, the power-law function does not account for saturation of , which is one of the weaknesses of this approach. Ultimately, this leads to a considerable overestimation of the measured degradation. In contrast, the physical defect model can be calibrated to replicate the measurement results. (The dashed line serves as guide for the eye).

be accurate. As has been mentioned, a more accurate description of BTI can be achieved when the non-radiative multi phonon (NMP) model is considered [20]. In the recent past, it has been demonstrated that using this model, the drift of the threshold voltage can be explained properly employing various large-area and scaled transistor technologies [16], [21]. The two-state defect model, see Fig. 5, is available via our reliability simulator Comphy [22]. Quite recently, an effective

Fig. 5: The physical defect model which we employ to calculate the charge trapping dynamics of the defects calculates the charge state of a defect considering a two-state system. State 1 accounts for the carrier reservoir, i.e., the conduction band edge, and state 2 describes the defect. The transitions between the two states are calculated using potential energy sufaces. Note that this model has to be solved for a large ensemble of oxide defects to mimic the experimentally observed degradation [15].

Fig. 5. The physical defect model which we employ to calculate the charge trapping dynamics of the defects calculates the charge state of a defect considering a two-state system. State 1 accounts for the carrier reservoir, i.e., the conduction band edge, and state 2 describes the defect. The transitions between the two states are calculated using potential energy sufaces. Note that this model has to be solved for a large ensemble of oxide defects to mimic the experimentally observed degradation [15].

single defect decomposition algorithm has been built around Comphy [23], enabling the efficient computational extraction of a defect distribution to explain both the DC and AC data sets from Fig. 3. As the name suggests, the model consists of two states where state 1 refers to the situation where the charge carrier resides at the channel, i.e., the conduction band edge, and the defect is neutral. If the carrier dwells in state 2 the defect is considered to be charged. For a charge transfer to take place, the carrier has to overcome the energetic barrier determined by the intersection point of the two parabolas describing the energy of the states. In the case of , the barrier and thus the defect remains neutral. However, when a gate bi as is applied, the energetic position of becomes lowered with respect to and thus . In this case, the defect can become charged. Next to the trap level of the defect, which is given by , the trapping kinetics is also determined by the relaxation energy and the curvature ratio of the parabolas , which is typically considered as . The
detailed defect parameters of the interface and oxide traps used to explain the experimental data are extracted and discussed in [9]. The impact of charge trapping on the inverter circuit is analyzed next with the defect parameters and the calibrated Comphy simulation framework at hand.

Impact of Bias Temperature Instabilities on the Performance of Inverter Circuits

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To quantify the impact of BTI on the behavior of a pseudo-D CMOS inverter circuit, the signal propagation delay between the input and the output voltage is analyzed, see Fig. 6. The open-source tool ngspice is used for the circuit simulations, and the propagation delay is extracted in a post-

Fig. 6: The signal propagation delay of the inverter circuit is extracted as the time difference between the output and input voltage at . For the evaluation of this delay under application-relevant operating conditions, an signal frequency of 50 kHz is considered.

Fig. 6. The signal propagation delay of the inverter circuit is extracted as the time difference between the output and input voltage at . For the evaluation of this delay under application-relevant operating conditions, an signal frequency of 50 kHz is considered.

processing step at . In order to consider the drift of the threshold voltage during circuit operation, the Spice simulations are combined with our reliability models. For the circuit simulations, a threshold voltage of is considered for each of the transistors, where is calculated employing Comphy for each transistor individually, depending on the applied bias history. Although this approach is not overly computational efficient, it accurately calculates the degradation of the circuit signal propagation delay due to BTI. Note that the compact transistor model used for the simulations is provided by the device manufacturer [24].
In Fig. 7, the results of our simulations are shown. It becomes evident that when physical defect

Fig. 7: The comparison of the simulated signal propagation delay shows a considerable deviation between simple models and physical defect models. The simple models predict an overly pessimistic signal propagation delay. Note that the low phases of the AC signal cause recovery of the devices, which has to be considered in the simulations. Otherwise, the signal propagation delay will be significantly overestimated by the simulations.

Fig. 7. The comparison of the simulated signal propagation delay shows a considerable deviation between simple models and physical defect models. The simple models predict an overly pessimistic signal propagation delay. Note that the low phases of the AC signal cause recovery of the devices, which has to be considered in the simulations. Otherwise, the signal propagation delay will be significantly overestimated by the simulations.

models are used, a considerably lower degradation of the signal propagation delay can be observed. Furthermore, a severe limitation of frequently applied approaches is that device recovery during the low bias phase under AC operating conditions is omitted [25]. This leads to overly pessimistic estimates for the signal propagation delay of the investigated circuit. We also evaluate the degradation of each transistor individually in Fig. 8. One can see that N 2 and N 4 show a similar impact on the signal propagation delay while the circuit is less sensitive to a drift of N1 and N3.

A final important aspect we observed in our simulations is that an overestimation of may lead to a misbalance of the impedances of the series connection of N3 and N4. In summary, the shown lack in prediction accuracy, which simple empirical models can

Fig. 8: An analysis of the impact of the transistors N1 to N4 on the signal propagation delay of the inverter circuit is shown. While N1 and N3 do not impact the signal propagation delay, a degradation of N2 and N4 affects the signal propagation delay similarly.

Fig. 8. An analysis of the impact of the transistors N1 to N4 on the signal propagation delay of the inverter circuit is shown. While N1 and N3 do not impact the signal propagation delay, a degradation of N2 and N4 affects the signal propagation delay similarly.

introduce, is a clear indicator of the need for precise simulation models to avoid potential circuitry overhead.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1062.688.pdf

Circuit simulations using Spice software are vital for optimizing the performance of circuits and for verifying that designs can operate in a stable manner under various operating conditions. In our work, we analyze a pseudo-D CMOS inverter circuit made employing 4H-SiC transistors. We combine circuit simulations with physics-based defect simulations to account for the impact of charge trapping on the performance of SiC transistors and examine the signal propagation delay of the inverter. Our results indicate that the performance degradation of the transistors leads to an increase in circuit delay. Also, one can see that empirical models often lead to a significant overestimation of the performance loss of the inverter circuit. Finally, it has to be noted that considering the device recovery during low phases of AC input signals is vital as otherwise too pessimistic values for the signal propagation delay are obtained from theoretical investigations.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1062.688.pdf

The financial support by the Austrian Federal Ministry for Digital and Economic Affairs, the National Foundation for Research, Technology and Development, and the Christian Doppler Research Association are gratefully acknowledged. Furthermore, The research leading to these results has received funding from the Take-off program of the Austrian Research Promotion Agency FFG (projects no. 867414 and 861022).

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Keywords Index

#

200 Mm Advances in 200 mm 4H SiC Wafer Development and Production; SiC Mass Commercialization: Present Status and Barriers to Overcome; Opening Through 200 mm Silicon Carbide Epitaxy

2d Simulation Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices; Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

3 C -sic Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride

3c-sic 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations; Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

3c-sic Microcantilevers A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

3c-sic; Stacking Faults; Dislocations; Molten Koh; Defect Reduction; Nitrogen Doping; Sem Impact of N Doping on 3C-SiC Defects

3c-sic; Stacking Faults; Doping; Ai; Ni; Defect; Koh Etching; Sem; Μ-raman Effect of N and AI Doping on 3C-SiC Stacking Faults

3c-sic; Sublimation Growth; Large-area Growth; Bow Reduction; Stress Reduction Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding

3D Thermal Simulations Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

4 H Advances in 200 mm 4H SiC Wafer Development and Production

4 H -sic Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers; Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

4 H -sic Bipolar Diode 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

4 H -sic; Neutron Detector; Epitaxial Growth; Micro-raman; I-lopc Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection

4h Measurement of Dislocation Density in SiC Wafers Using Production XRT

4h-sic Opening Through 200 mm Silicon Carbide Epitaxy; Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics; Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

4h-sic; Laser Annealing; Xecl; Dopant Activation; Phosphorus; Aluminum; Defects; Tem; Raman; Sem; Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

6 H -sic Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

A

Ab-initio Methods Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Ac Stress Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Activation Anneal Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

Afm KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Al Memory Effect Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride

Aluminum Acceptor Ionization Energy Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Aluminum Activation Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Amplifying Gate Investigation of SiC Thyristors with Varying Amplifying Gate Design

Annealing Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics; Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

Automotive Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

B

Barrier Modulation Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

Basal Plane Dislocation Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Basal Plane Dislocation (bpd) Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy

Basal Plane Dislocations SiC Mass Commercialization: Present Status and Barriers to Overcome; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Bias Temperature Instabilities Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Bias Temperature Instability (bti) Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Biosensor Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Bipolar Degradation SiC Mass Commercialization: Present Status and Barriers to Overcome; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Bipolar Power Devices Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Birefringence Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Body Diode Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Body Diode Stress Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Bonding Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Bottom Gate Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Brain Implants The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Breakdown Voltage Edge Terminations for -SiC Power Devices: A Critical Issue

Bulk Crystal Growth Advances in 200 mm 4H SiC Wafer Development and Production; Measurement of Dislocation Density in SiC Wafers Using Production XRT

C

C-v Curves SiC MOSFET C-V Characteristics with Positive Biased Drain

Capacitance SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Capacitance-voltage Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence; Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Capacitance-voltage Measurements Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

Carbon Antisite-vacancy Pair Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Carbon Interstitial Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Carrier Lifetime Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection

Channeled Implant SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Charge Balance SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Charge Neutrality Equation Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Charge To Failure Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Charge Trapping Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Chemical Mechanical Polishing 7478f2b2-3540-4f37-83b2-304b331b6df5

Classification A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Cluster Correlation Expansion Theory Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Cold Wall Reactor Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Compact Modeling A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

Comparison Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

Comsol DC Modeling of -SiC nJFET Gate Length Reduction at

Crack Reduction A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Crystal Defects A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Ctlm Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Current Sharing Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Cvd Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications; Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

D

Decoherence Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Deconvolution Identification of High Resolution Transient Thermal Network Model for Power Module Packages

Deep Level Transient Spectroscopy Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Defect Polish Scratch Simulation vs. Polish Tool Type

Defect Classification Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Defect Density The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Defect Detection Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Defects Advances in 200 mm 4H SiC Wafer Development and Production; Opening Through 200 mm Silicon Carbide Epitaxy; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Density Functional Theory Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Detection Limit Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

Detector Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Detectors Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Device Design Impact of Device Design Parameters on 15 kV SiC MOSFETs

Device Fabrication Investigation of SiC Thyristors with Varying Amplifying Gate Design

Device Under Test - Dut Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Diamond Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

Diamond Semiconductor Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Differential Scanning Calorimetry Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Diode Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

Dislocation Contrast Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography

Dislocations High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer

Dmosfet Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs; Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Dna Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Dopant Ionization Energy Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Doping Uniformity Opening Through 200 mm Silicon Carbide Epitaxy

E

Edge Termination Edge Terminations for -SiC Power Devices: A Critical Issue; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Effective Critical Breakdown Field Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices

Electric Vehicle Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Electrical Activation Efficiency Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Electrical Test A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Electro-physical Characterisation 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

Electrochemical Porosification A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Electromagnetic Actuation And Inductive Detection A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Electron Spin Echo Envelope Modulation Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Electron-nuclear Spin Bath Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Electronic Devices Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Emissivity Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Epitaxial Graphene Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC; Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications; Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Epitaxial Layer Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Epitaxy SiC Mass Commercialization: Present Status and Barriers to Overcome; Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition; Opening Through 200 mm Silicon Carbide Epitaxy; A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability; AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Etch SiC Mass Commercialization: Present Status and Barriers to Overcome

Etched Jte Investigation of SiC Thyristors with Varying Amplifying Gate Design

Extended Defects A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

F

Fabless SiC Mass Commercialization: Present Status and Barriers to Overcome

Fabrication SiC Mass Commercialization: Present Status and Barriers to Overcome

Failure Analysis Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules; Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Fet Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Field-effect Transistor (fet) Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Flatness 7478f2b2-3540-4f37-83b2-304b331b6df5

Flexible SiC Substrate A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Flexural Strength The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Floating Field Rings Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Fluka Neutron Detection Study Through Simulations with Fluka

Forward Voltage Drop Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Foundrycompatible Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

G

Gallium Nitride; X-ray Topography; Power Electronics; Substrates; Selective Area Doping; Ion Implantation; Etching And Regrowth Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Gan High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition; Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Gan Hemt AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Gas Sensing Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

Gate Bias Stress Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Gate Current Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Gate Synchronisation Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Germanium A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Grinding Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Growth Parameters Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

H

H3trb Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

Heated Implantation SiC Mass Commercialization: Present Status and Barriers to Overcome

Heavily-doped 4h-sic Ni/Heavily-Doped 4H-SiC Schottky Contacts

Heavy Lons Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Hetero-epitaxial Growth A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Heteroepitaxy 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations; Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

High Electric Field Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

High Frequency AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

High Humidity High Temperature Reverse Bias Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

High Index 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

High Power Density Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

High Temperature High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer

High Temperature Gate Bias Test Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

High Voltage Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

High Voltage Device 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

High-k Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

High-k Gate Dielectrics Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

High-resistivity A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Hydrogen Sensor A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Hysteresis Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

I

Icp Etch Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Igbt Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low; Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules; Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Image Analysis Measurement of Dislocation Density in SiC Wafers Using Production XRT

Image Segmentation Automatic Image Analysis of Stackingfault

Impact Lonization Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices

Implantation A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Impurity Models for Impurity Incorporation during Vapor-Phase Epitaxy

Incomplete Ionization Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Inductive Load Switching Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Inter-electrode Capacitance Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Inter-terminal Capacitance Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Interface Characterization Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements; SiC MOSFET C-V Characteristics with Positive Biased Drain

Interface Defect Density Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence

Interface Defects Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy; Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Interface States Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

Interface Traps Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Interfaces Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

Interfacial Dislocation (id) Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy

Inverter Circuits Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Ion Implantation Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies; Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

Ion-implantation Ni/Heavily-Doped 4H-SiC Schottky Contacts

J

Jte Edge Terminations for -SiC Power Devices: A Critical Issue

Junction Barrier Schottky (jbs) Diode Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

Junction Termination Extension Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

K

Kinetic Monte Carlo Methods Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Koh Etching High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Kpfm KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

L

Laser Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Laser Annealing Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

Lattice Strain Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

Line-shape Defect Evaluation of Line-Shape Defect in Epitaxial Wafer

Liquid Silicon Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

Local Capacitance-voltage Profiling Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Loss Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Low Temperature Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

M

Material Removal Rate (mrr) 7478f2b2-3540-4f37-83b2-304b331b6df5

Mems The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation; A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Metallization Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Mocvd Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Model Polish Scratch Simulation vs. Polish Tool Type

Morphology 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Mos Capacitor Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

Mos Capacitors Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

Mosfet Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs; Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation; Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout; Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules; Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Mosfet Gate Capacitance SiC MOSFET C-V Characteristics with Positive Biased Drain

Multi Stacks Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Multi-scale Simulation Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Multichip Power Module Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Muon Spin Rotation Spectroscopy Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

N

Nano-gratings Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Nanostructures Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Neural Interface The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Neutron Detection Neutron Detection Study Through Simulations with Fluka

Neutrons Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET; Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Nitrogen Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

No-annealing Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Non-destructive Dislocation Density Measurement Measurement of Dislocation Density in SiC Wafers Using Production XRT

Nwfet Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

O

Obic 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method; Edge Terminations for -SiC Power Devices: A Critical Issue

Ohmic Contact SiC Mass Commercialization: Present Status and Barriers to Overcome; Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

Ohmic Contact Formation Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Ohmic Contacts Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

On-resistance Impact of Device Design Parameters on 15 kV SiC MOSFETs

Onstate Characteristic Investigation of SiC Thyristors with Varying Amplifying Gate Design

Oxidation Process Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection

Oxidation Rate Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

Oxide Reliability Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout; Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Oxide Traps Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

P

P-type Doping Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride

Package Design Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Package Inductance Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Parallel-connected Mosfets Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Parasitic Element Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Penetration Depth Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Performance Evaluation Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

Periphery Protection 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

Phase Transition Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Phosphorous Implant DC Modeling of -SiC nJFET Gate Length Reduction at

Photoluminescence Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence; Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Physical Gas Detector A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Physical Vapor Transport Advances in 200 mm 4H SiC Wafer Development and Production; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Pin Diode Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

Planar Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Plasma Etching Processes Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Plasmonic Nanoparticles Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Point Defects Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Polish Polish Scratch Simulation vs. Polish Tool Type

Polishing Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Post-oxidation Annealing Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

Power Device Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis; Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Power Module Identification of High Resolution Transient Thermal Network Model for Power Module Packages; A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

Power Mosfet Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET; Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Proton Implantation Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Pvt Advances in 200 mm 4H SiC Wafer Development and Production; Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Q

Quasi-static Capacitance Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

R

Radiation Hardness Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Raman Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Raman Scattering Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Raman Spectroscopy KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Ray-tracing Simulation Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Reaction Enthalpy Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Reactive Materials Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Recombination-enhanced Dislocation Glide Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Recovery Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Reliability A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability; Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules; Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application; Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Resistivity Advances in 200 mm 4H SiC Wafer Development and Production; Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology; Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Reverse Recovery Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Run-to-run Opening Through 200 mm Silicon Carbide Epitaxy

S

Sandwich Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

Sbd Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Scanning Capacitance Microscopy; Conductive Atomic Force Microscopy; 3c-sic; Schottky; Mos Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon

Scanning Nonlinear Dielectric Microscopy Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy; Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Schottky Barrier Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

Schottky Barrier Diode A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

Schottky Diode Ni/Heavily-Doped 4H-SiC Schottky Contacts

Scratch Polish Scratch Simulation vs. Polish Tool Type

Segregation Models for Impurity Incorporation during Vapor-Phase Epitaxy

Self-turn-on Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation

Semi-insulating A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Semi-superjunction A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

Semiconductors Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Series-connection Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

Sers Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Shallow Implantation Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation

Shallow Nitrogen Implant DC Modeling of -SiC nJFET Gate Length Reduction at

Shockley-read-hall (srh) Lifetime Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Shockley-type Stacking Fault Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Si Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

SiC SiC Mass Commercialization: Present Status and Barriers to Overcome; Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition; Multiscale Simulations of Plasma Etching in Silicon Carbide Structures; Automatic Image Analysis of Stackingfault; Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis; Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation; Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

SiC Biomedical The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

SiC Device Characterization KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

SiC Fab Infrastructure SiC Mass Commercialization: Present Status and Barriers to Overcome

SiC Foundry SiC Mass Commercialization: Present Status and Barriers to Overcome

SiC Mosfet Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology; Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements; SiC MOSFET C-V Characteristics with Positive Biased Drain; SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

SiC Mosfet Reliability Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

SiC Mosfet; Tcad Modelling; 3D Cell Geometry; Short Circuit Robustness On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

SiC Mosfet; Tcad Modelling; Cell Geometry; Inductive Switching; Uis Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts

SiC Mosfets Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

SiC Power Mosfet Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

SiC Transistors Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Sic-mosfet Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy; Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

Sic-mosfets Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Silicide SiC Mass Commercialization: Present Status and Barriers to Overcome

Silicon Carbide Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers; Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC; Polish Scratch Simulation vs. Polish Tool Type; Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics; 7478f2b2-3540-4f37-83b2-304b331b6df5; Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC; Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide; Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout; Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes; Neutron Detection Study Through Simulations with Fluka; Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs; Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate; Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures; Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs; Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Silicon Carbide (sic) Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET; Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Silicon Carbide (sic) Mosfet A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

Silicon Carbide Epitaxy Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy

Silicon Carbide Mosfet Impact of Device Design Parameters on 15 kV SiC MOSFETs

Silicon Carbide; Igbt; 10 Kv ; Power Device; Short Circuit Robustness; Reliability; Carrier Lifetime Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design

Sims Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

Simulation A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

Single Event Burnout (seb) Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Single Shockley Stacking Fault Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

Single Side Processing A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Single-event Burnout Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Single-event Effects Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Spice A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

Spice Simulation Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Stacking Fault Automatic Image Analysis of Stackingfault; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations; Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Stacking Fault Defect Evaluation of Line-Shape Defect in Epitaxial Wafer

Static Behavior Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

Statistics A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Step Kinetics Models for Impurity Incorporation during Vapor-Phase Epitaxy

Step-bunched Morphology Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

Stress Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Substrate SiC Mass Commercialization: Present Status and Barriers to Overcome

Substrate Orientation 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Substrate Thinning The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Super Junction Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Superjunction Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Superjunction (sj) Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices; Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

Superjunction Diode Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Surface Diffusion Models for Impurity Incorporation during Vapor-Phase Epitaxy

Surface Potential Fluctuations Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Surface Roughness (ra) 7478f2b2-3540-4f37-83b2-304b331b6df5

Surface Structuring Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

Switching Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs; Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation

Switching Behavior Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

Switching Losses Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Synchrotron X-ray Rocking Curve Topography Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

T

Tac Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Tcad Model SiC MOSFET C-V Characteristics with Positive Biased Drain

Tcad Modeling Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Tcad Simulation Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Tddb Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Temperature SiC MOSFET C-V Curves Analysis with Floating Drain Configuration

Temperature Dependent Hall Effect Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Thermal Oxidation Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology; Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

Thermal Stress Relaxation A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Thermal Treatment The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Thermionic Field Emission Ni/Heavily-Doped 4H-SiC Schottky Contacts

Thickness Uniformity Opening Through 200 mm Silicon Carbide Epitaxy

Thin Layers Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Thinning Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Threading Edge Dislocation Evaluation of Line-Shape Defect in Epitaxial Wafer

Threading Mixed Dislocation Evaluation of Line-Shape Defect in Epitaxial Wafer

Threading Screw Dislocation Evaluation of Line-Shape Defect in Epitaxial Wafer

Threshold Voltage Mismatch Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Threshold Voltage Stability Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

Thyristor Investigation of SiC Thyristors with Varying Amplifying Gate Design

Time-dependent Dielectric Breakdown (tddb) Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Titanium Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

Transient Thermal Resistance Identification of High Resolution Transient Thermal Network Model for Power Module Packages

Transmission Electron Microscopy Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

Traps SiC MOSFET C-V Curves Analysis with Floating Drain Configuration

Trench Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Trench Corner Rounding Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Trench Device Simulation Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Trench Processing Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Turn-off Characteristics DC Modeling of -SiC nJFET Gate Length Reduction at

Turn-on Characteristic Investigation of SiC Thyristors with Varying Amplifying Gate Design

U

Uis SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Ultra-high Voltage Impact of Device Design Parameters on 15 kV SiC MOSFETs

Ultraviolet Irradiation Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Ultraviolet Photoluminescence Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Umosfet Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

Usable Area Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Uv Illumination Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

V

Vanadium Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Vapor-phase Epitaxy Models for Impurity Incorporation during Vapor-Phase Epitaxy

Vitrified Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Void Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

W

Wafer Polish Scratch Simulation vs. Polish Tool Type

Weak Beam Topography Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography

Wet Chemistry A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

X

X-ray Diffraction Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

X-ray Topography Advances in 200 mm 4H SiC Wafer Development and Production; Measurement of Dislocation Density in SiC Wafers Using Production XRT; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Xrt Measurement of Dislocation Density in SiC Wafers Using Production XRT

Y

Yield A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Authors Index

A

Abid, H. Structural, Electronic and Optical Properties of 6H-SiC and 3C-SiC with the Application in Solar Cell Devices

Adam, P. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis; KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Agati, M. Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

Alatise, O. Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Alawieh, H. Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Alberti, A. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Albonetti, C. Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap

Alfieri, G. Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

Ali, F. Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Allen, S. Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Allerstam, F. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Allibert, F. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Alquier, D. Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues; Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC; AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications; A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Amishiro, H. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Ammar, A. Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Antoniou, M. Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Anzalone, R. High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects; Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding; Impact of Dislocation on Warpage of Thinned -SiC Wafers

Arango, Y. Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

Arzig, M. Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide; Review of Sublimation Growth of SiC Bulk Crystals

Ashraf, H. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Aslanidou, S. Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Asllani, B. 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method; Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

Assoufid, L. Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography

Avenas, Y. Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Azadmand, M. Opening Through 200 mm Silicon Carbide Epitaxy

B

Baba, M. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Badalà, P. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Bah, M. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Bai, Y. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Baierhofer, D. Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Baker, G. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Bakowski, M. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Balland, B. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Bano, E. Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Bassi, A. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Bathen, M. Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy; Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Bauersfeld, D. Investigation of SiC Thyristors with Varying Amplifying Gate Design

Bay, N. A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Bellocchi, G. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Belsito, L. Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Bera, L. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Bercu, N. KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Berger, C. Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC

Bernardin, E. The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Berre, G. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Bethoux, J. 5c08d086-2273-42e8-a226-e67b09c9e4fd

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Bevilacqua, P. 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

Beygi, M. The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Bhargava, S. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Boch, J. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Bockowski, M. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Boldrini, V. Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Bolton, C. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Bonafe, F. Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap; Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

Bongiorno, C. Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry; Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Boninelli, S. Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects; Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

Bonyadi, Y. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment

Borghese, A. A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

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Briot, O. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Brosselard, P. 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

Brouillard, M. KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Bussel, M. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

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Cafra, B. The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates; Impact of Dislocation on Warpage of Thinned -SiC Wafers

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Camarda, M. Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence

Canino, M. Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap; Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Cannizzaro, A. Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects

Cao, Q. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment

Carette, C. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Carette, M. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Carria, E. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Castellazzi, A. SiC MOSFET C-V Characteristics with Positive Biased Drain

Castorina, S. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Cauwet, F. Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration; 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Cela, E. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Certon, D. A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

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Chaussende, D. Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Chen, Z. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers; Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Cheng, Q. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Chenot, S. Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues

Cho, Y. Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy; Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Chochol, J. SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Choi, J. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Chong, K. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Chow, T. Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants; Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices; Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs; Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Chui, K. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Chung, G. Advances in 200 mm 4H SiC Wafer Development and Production; Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy; Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Chung, S. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Coindeau, S. 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Collazo, R. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Contreras, S. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Cordier, Y. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Corticelli, F. Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap

Crippa, D. Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects; Review of Sublimation Growth of SiC Bulk Crystals; Opening Through 200 mm Silicon Carbide Epitaxy

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Daher, M. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Dai, T. The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Daliento, S. SiC MOSFET C-V Characteristics with Positive Biased Drain; SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Danilewsky, A. Review of Sublimation Growth of SiC Bulk Crystals; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Das, H. A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Decams, J. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Deeb, P. Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants

Defrance, N. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Delahaye, F. A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Deretzis, I. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures; Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Dimitrijev, S. Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

Dojima, D. A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Domeij, M. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Dominguez-Viqueria, W. The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Donato, N. Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Drouin, A. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Duboiskaya, N. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Duboust, A. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Dudley, M. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Dufour, I. A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Döll, J. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

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Encinas, T. 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Erlbacher, T. Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth; Via Size-Dependent Properties of TiAI Ohmic Contacts on 4H-SiC

Evans, J. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

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Fan, W. Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications; Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Fazio, T. Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Feezell, D. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Feng, C. The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Feng, W. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Ferri, M. Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Ferro, G. Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration; 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Fiorenza, P. High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon; Ni/Heavily-Doped 4H-SiC Schottky Contacts

Fisicaro, G. Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Franchi, J. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Franco, S. Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon; Ni/Heavily-Doped 4H-SiC Schottky Contacts

Frayssinet, E. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Frewin, C. The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Fukunaga, S. Identification of High Resolution Transient Thermal Network Model for Power Module Packages

Funaki, T. Identification of High Resolution Transient Thermal Network Model for Power Module Packages

Förster, C. Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

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Gajewski, D. Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Gallino, I. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Galyukov, A. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Gammon, P. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

García-García, A. Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Gaudin, G. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Gave, M. Advances in 200 mm 4H SiC Wafer Development and Production; Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy; Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Gay, X. A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Gelineau, G. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Germanicus, R. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Ghandi, R. Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants; Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

Ghorbanzadeh-Bariran, M. Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues

Giannazzo, F. Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon; Ni/Heavily-Doped 4H-SiC Schottky Contacts

Giraudet, L. KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Givens, J. 7478f2b2-3540-4f37-83b2-304b331b6df5

Godignon, P. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications; Edge Terminations for -SiC Power Devices: A Critical Issue; Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Grant, N. The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2

Grasser, T. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Grasso, A. The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Greco, G. High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; Ni/Heavily-Doped 4H-SiC Schottky Contacts

Green, D. Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

Grieseler, R. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Grossner, U. Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology; Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy; Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements; Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC; Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence; Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Guadas, M. Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology; Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

Guerra, J. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Gumaelius, K. SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Guo, L. Evaluation of Line-Shape Defect in Epitaxial Wafer

Guy, O. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Gélard, I. Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

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Haasmann, D. Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

Hallén, A. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Hamann, D. A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability

Han, J. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Han, K. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Hansen, S. A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Harada, S. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Hassdorf, R. Investigation of SiC Thyristors with Varying Amplifying Gate Design

Hernandez, Y. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Hitchcock, C. Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants; Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

Hock, R. Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Hoffmann, F. Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

Honig, H. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Hopfeld, M. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Horikiri, F. Models for Impurity Incorporation during Vapor-Phase Epitaxy

Hrich, H. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Hu, J. 7478f2b2-3540-4f37-83b2-304b331b6df5

Hu, S. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Hu, X. Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Huang, X. Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography

Hull, B. Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Hähnlein, B. Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

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Igarashi, Y. Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Iglesias, L. A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Ihle, J. In Situ Monitoring of Unintentionally Released Nitrogen Gas in the Initial PVT Silicon Carbide Growth Process Using Mass Spectrometry; Review of Sublimation Growth of SiC Bulk Crystals

Iijima, R. Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

Irace, A. SiC MOSFET C-V Characteristics with Positive Biased Drain; A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs; SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Italia, M. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Iwamatsu, T. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

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Jacobs, K. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Jaeger, J. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Jeannin, P. Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration; Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Jennings, M. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Ji, W. Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Johnson, B. Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence

Jomard, F. Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

Jones, B. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Jouha, W. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Jousseaume, Y. Liquid Si-Induced 4H-SiC Surface Structuring Using a Sandwich Configuration

Ju, M. Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy; Polish Scratch Simulation vs. Polish Tool Type

Justice, J. A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

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Kamei, K. Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method

Kaminski, N. Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

Kaneko, T. A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Kaplan, W. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Karker, O. Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Karsthof, R. Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Kennerly, S. Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants; Demonstration of 2kV SiC Deep-Implanted Super-Junction PiN Diodes

Khazaka, R. Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues

Kicin, S. A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs

Knoll, L. Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation; Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs; Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes; Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Kochoska, S. Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Kodolitsch, E. Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

Kojima, K. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Kollmuss, M. Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding; Review of Sublimation Growth of SiC Bulk Crystals; Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Kotamraju, S. Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

Kozak, B. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Krieger, M. Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

Kuehnlein, H. A Novel Tool Layout and Process for Single Side Wet Electrochemical Processing of Porous Silicon Carbide Layers without Edge Exclusion

Kumar, P. Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy; Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements

Kuroi, T. SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Kwong, D. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Köhler, J. Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Künecke, U. Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide

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Lamontagne, C. Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

Landois, P. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Latry, O. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Lavaitte, G. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Lawson, J. DC Modeling of -SiC nJFET Gate Length Reduction at

Lazar, M. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis; KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Lebedev, A. Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Lebedev, S. Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Lee, C. Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Lee, H. Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Lefebvre, B. Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

Lefranc, P. Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration; Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Leighton, J. 7478f2b2-3540-4f37-83b2-304b331b6df5

Lennartz, J. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Leow, Y. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Lesecq, M. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Lettens, J. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Lewke, D. Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Li, B. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Li, C. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Li, F. The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Lichtenwalner, D. Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Liu, E. 7478f2b2-3540-4f37-83b2-304b331b6df5

Liu, M. 7478f2b2-3540-4f37-83b2-304b331b6df5

Liu, X. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Liu, Y. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Lophitis, N. Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Lu, J. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Lyoussi, A. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

López, J. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Lüders, U. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

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Magna, A. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures; Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies; Ni/Heavily-Doped 4H-SiC Schottky Contacts; Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Maleville, C. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Maloušek, R. SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Mancarella, F. Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap

Mank, H. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon

Manning, I. Advances in 200 mm 4H SiC Wafer Development and Production; Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Manske, E. Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Marchetti, B. Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Maresca, L. SiC MOSFET C-V Characteristics with Positive Biased Drain; A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs; SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Martins, M. Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

Maslougkas, S. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Matacena, I. SiC MOSFET C-V Characteristics with Positive Biased Drain; SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Mathew, S. Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Matsubara, M. A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Matsumoto, T. Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Mauceri, M. Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects; Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding; Review of Sublimation Growth of SiC Bulk Crystals; Opening Through 200 mm Silicon Carbide Epitaxy

Mawby, P. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

May, A. Via Size-Dependent Properties of TiAI Ohmic Contacts on 4H-SiC

McPherson, J. Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Meda, L. Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection; Neutron Detection Study Through Simulations with Fluka

Mehta, M. DC Modeling of -SiC nJFET Gate Length Reduction at

Meli, A. Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection; Neutron Detection Study Through Simulations with Fluka

Mendy, S. Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Mescot, X. Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Messina, A. Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry

Meyers, V. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Michaud, J. Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues; Optimisation of Ti Ohmic Contacts Formed by Laser Annealing on 4H-SiC; A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Michez, A. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Michon, A. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

Mihaila, A. Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs; Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes; Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Minamisawa, R. Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

Minamiyama, H. A Novel Approach of Utilizing Mechanically Flexible SiC Substrate to Grow Crack-Free AIN Bulk Crystal by Thermal Strain Relaxation Functionality

Ming, C. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Mishima, T. Models for Impurity Incorporation during Vapor-Phase Epitaxy

Mitchell, J. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Miura, N. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Mletschnig, K. Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer

Mochizuki, K. Models for Impurity Incorporation during Vapor-Phase Epitaxy

Moeggenborg, K. Advances in 200 mm 4H SiC Wafer Development and Production; Polish Scratch Simulation vs. Polish Tool Type

Moens, P. Gate Oxide Reliability and V Stability of Planar SiC MOS Technology

Moisson, C. Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material

Momose, K. Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method

Monaghan, F. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Monnoye, S. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon

Montserrat, J. Edge Terminations for -SiC Power Devices: A Critical Issue

Moon, A. The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Morel, H. Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Moret, M. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Moultif, N. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Moussa, H. Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Mulpuri, V. Impact of Device Design Parameters on 15 kV SiC MOSFETs

Muoio, A. Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing; Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection; Automatic Image Analysis of Stackingfault; Neutron Detection Study Through Simulations with Fluka

Murakami, E. Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Muravitskaya, A. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Murphy, J. The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2

N

Nakao, Y. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Nakata, S. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs; Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation

Nastasi, A. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Navone, C. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Naydenov, K. Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Ndohi, A. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Nee, H. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Negri, M. Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

Neudeck, P. DC Modeling of -SiC nJFET Gate Length Reduction at

Neyer, T. Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Ngo, T. AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Nguyen, B. Review of Sublimation Growth of SiC Bulk Crystals; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Nguyen, L. Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues

Nicholls, J. Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

Nipoti, R. Mechanism Governing Surface Roughening of AI Ion Implanted 4H-SiC during Annealing under a C-Cap; Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies; Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

Nishihara, Y. Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method

Nishio, J. Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

Niskanen, K. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Nistor, I. Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

O

Oda, K. Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Ogata, Y. Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Ohta, H. Models for Impurity Incorporation during Vapor-Phase Epitaxy

Okada, M. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Ortiz-Gonzalez, J. Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

Osuna, A. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Ota, C. Transmission Electron Microscopy Study of Single Shockley Stacking Faults in -SiC Expanded from Basal Plane Dislocation Segments Accompanied by Threading Edge Dislocations on Both Ends

Ottaviani, L. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Ou, H. Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

P

Pagano, D. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Paillet, M. Toward the Reproducible Growth of Graphene on Wide SiC Steps: A Study of the Geometric Properties of -SiC (0001) Substrates

Paladino, E. Computational Study of the Silicon Vacancy in 3C-SiC and Perspectives for Quantum Technologies

Palmour, J. Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

Parisi, M. Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection; Neutron Detection Study Through Simulations with Fluka

Parisini, A. Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Park, J. Impact of Device Design Parameters on 15 kV SiC MOSFETs

Pathirana, V. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment

Pecora, A. Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

Pellegrini, G. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Peng, H. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Pezoldt, J. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers; Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Pham, T. Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Phung, L. 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method; Investigation of SiC Thyristors with Varying Amplifying Gate Design; Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Pichler, P. Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer

Piluso, N. High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates

Pinault-Thaury, M. Nitrogen Investigation by SIMS in Two Wide Band-Gap Semiconductors: Diamond and Silicon Carbide

Pirnaci, M. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Planson, D. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis; 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method; Investigation of SiC Thyristors with Varying Amplifying Gate Design; Edge Terminations for -SiC Power Devices: A Critical Issue; Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Pobegen, G. Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer

Portail, M. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Designing SiC Based CMUT Structures: An Original Approach and Related Material Issues; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications; A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Potiron, S. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Preti, S. Opening Through 200 mm Silicon Carbide Epitaxy

Privitera, S. Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing

Prokscha, T. Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy

Puglisi, M. Opening Through 200 mm Silicon Carbide Epitaxy

Pérez-Tomás, A. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment

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Qi, Y. A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

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Radu, I. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Radulović, V. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Rafi, J. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Raghothamachar, B. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials; Dislocation Contrast Analysis in Weak Beam Synchrotron X-Ray Topography; Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms; Ray-Tracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in -SiC Wafers

Rahimo, M. Advanced V SiC MOSFET Concept Based on Singular Point Source MOS (S-MOS) Technology

Ramos, M. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Rana, T. Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy

Ransom, J. Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Ranstad, P. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Rascunà, S. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Rebollo, J. Edge Terminations for -SiC Power Devices: A Critical Issue

Reiprich, J. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Reisinger, H. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Reitano, R. Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection

Renz, A. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Reshanov, S. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Riccio, M. SiC MOSFET C-V Characteristics with Positive Biased Drain; A Scalable SPICE-Based Compact Model for 1.7 kV SiC MOSFETs; SiC MOSFET C-V Curves Analysis with Floating Drain Configuration; Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs

Riddel, K. Introducing Foundry-Compatible SiC and GaN Trench Processing Technologies for Reliable Automotive Application

Ringleben, M. Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Rius, G. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications; Fabrication and Characterization of Epitaxial Graphene Field Effect Transistor Devices Based on a Monolithic Bottom Gate

Roccaforte, F. High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon; Ni/Heavily-Doped 4H-SiC Schottky Contacts

Roder, M. Review of Sublimation Growth of SiC Bulk Crystals; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Rolland, E. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Romano, G. Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs; Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Rommel, M. Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer; Via Size-Dependent Properties of TiAI Ohmic Contacts on 4H-SiC; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Roncaglia, A. Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Rouchier, S. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Ruiz, D. Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Rumyantseva, A. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis

Ryu, S. Gate Bias Effects on SiC MOSFET Terrestrial-Neutron Single-Event Burnout

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Saddow, S. The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation

Saggio, M. Charge Trapping Mechanisms in Nitridated -SiC MOSFET Interfaces: Threshold Voltage Instability and Interface Chemistry

Salamon, M. Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide; Review of Sublimation Growth of SiC Bulk Crystals

Sanchez, E. Advances in 200 mm 4H SiC Wafer Development and Production; Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Sandfeld, S. Review of Sublimation Growth of SiC Bulk Crystals; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Sapienza, S. Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Sato, Y. Self-Turn-on Phenomenon of SiC MOSFETs by Fast Switching Operation

Scalese, S. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Schaaf, P. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Scharnholz, S. Investigation of SiC Thyristors with Varying Amplifying Gate Design

Schiliro, E. Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon

Schleich, C. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Schmidt-Sane, P. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition

Schmitt, S. Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules

Schustereder, W. Aluminum Activation in -SiC Measured on Laterally Contacted MOS Capacitors with a Buried Current-Spreading Layer

Schwarzenbach, W. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Schöler, M. Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding

Schöner, A. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

Scuderi, V. Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects; Automatic Image Analysis of Stackingfault; Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator

Searson, J. Advances in 200 mm 4H SiC Wafer Development and Production

Servant, F. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Severino, A. High Temperature Etching for Threading Dislocation Investigation on GaN Epi-Layer; The Impact of Defect Density on Mechanical Characteristics of 4H-SiC Substrates; Impact of Dislocation on Warpage of Thinned -SiC Wafers

Shah, V. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Shahedipour-Sandvik, F. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Shanmugam, P. A New Approach in the Field of Hydrogen Gas Sensing Using MEMS Based 3C-SiC Microcantilevers

Shekhawat, D. Silicon Carbide Formation in Reactive Silicon-Carbon Multilayers

Sheng, Y. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Shiomi, D. Evaluation of Defects in a SiC Substrate Using the Photoluminescence Measurement Method; Evaluation of Line-Shape Defect in Epitaxial Wafer

Sileno, C. Novel Vitrified-Bond Ultra-Fine Grinding Technology for SiC Polishing

Simonetti, O. KPFM - Raman Spectroscopy Coupled Technique for the Characterization of Wide Bandgap Semiconductor Devices

Singh, N. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs

Singh, R. Multi-Layer High-K Gate Stack Materials for Low D 4H-SiC Based MOSFETs; Impact of Device Design Parameters on 15 kV SiC MOSFETs

Sitar, Z. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

Smecca, E. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Snoj, L. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Sodan, V. Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

Sonneville, C. Enhanced Resonant Raman Scattering of GaN Functional Layers Using Al Thin Films - A Versatile Tool for Multilayer Structure Analysis; 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method; Design and Methodology of Silicon Carbide High Voltage Termination Extension for Small Area BJTs

Soukhojak, A. Advances in 200 mm 4H SiC Wafer Development and Production; Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy; Decoration and Density Increase of Dislocations in PVT-Grown SiC Boules with Post-Growth Thermal Processing; Measurement of Dislocation Density in SiC Wafers Using Production XRT

Soulière, V. 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Spejo, L. Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

Staiger, F. Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Stambouli, V. Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Stampfer, B. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Stannard, T. Measurement of Dislocation Density in SiC Wafers Using Production XRT

Stark, R. Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements; Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence; Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Stauffenberg, J. Silicon Carbide - Graphene Nano-Gratings on 4H and 6H Semi-Insulating SiC

Steiner, J. Review of Sublimation Growth of SiC Bulk Crystals; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers

Sundaramoorthy, V. Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation; Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs; Performance Comparison of 6.5 kV SiC PiN Diode with 6.5 kV SiC JBS and Si Diodes

Sundaresan, S. Impact of Device Design Parameters on 15 kV SiC MOSFETs

Sunkari, S. A Deeper Look into the Effects of Extended Defects in SiC Epitaxial Layers on Device Performance and Reliability; SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth; Pulsed Forward Bias Body Diode Stress of Individual Mapping of Basal Plane Dislocations

Supplieth, F. Study of Laser Backside Ohmic Contact Formation of SiC-Ni Interface to Evaluate the Process Influence on the Electrical Characteristics

Sveinbjörnsson, E. Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

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Taibi, I. Structural, Electronic and Optical Properties of 6H-SiC and 3C-SiC with the Application in Solar Cell Devices

Takano, K. Effective Method (Selective E-V-C Technique) to Screen out the BPDs that Cause Reliability Degradation

Takeshita, T. Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Tamarri, F. Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Tanaka, T. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Tenaglia, D. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Thieberger, P. Investigation of Lattice Strain in High Energy Implanted 4H-SiC Wafers by AI or N Atoms

Thomas, B. Defect Reduction in Epilayers for SiC Trench MOSFETs by Enhanced Epitaxial Growth

Thomas, S. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Tian, X. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Tiwari, A. Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Tokuda, N. Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Tominaga, T. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Tomohisa, S. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Torky, M. Aluminum Acceptor Ionization Energies in 4H-SiC for Low Dose, Ultra-High Energy (> 1MeV) Implants; Determination of Effective Critical Breakdown Field in 4H-SiC Superjunction Devices; Comparative Performance Evaluation of Conventional and Superjunction Vertical 4H-SiC High-Voltage Power MOSFETs

Touboul, A. Failure Analysis of Atmospheric Neutron-Induced Single Event Burnout of a Commercial SiC MOSFET

Tournier, D. 4H-SiC PiN Diode Protected by Narrow Field Rings Investigated by the Micro-OBIC Method

Trajkovic, T. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs

Tringali, C. Structural and Electrical Characterization of Ni-Based Ohmic Contacts on 4H-SiC Formed by Solid-State Laser Annealing

Trotta, A. Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection; Neutron Detection Study Through Simulations with Fluka

Troutot, N. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Tsavdaris, N. Impact of Epitaxial Defects on Device Behavior and their Correlation to the Reverse Characteristics of SiC Devices

Tsibizov, A. Temperature Dependence of On-State Inter-Terminal Capacitances ( and ) of SiC MOSFETs and Frequency Limitations of their Measurements

Tweedie, J. Synchrotron X-Ray Topography Characterization of Power Electronic GaN Materials

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Udrea, F. Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; Compact Trench Floating Field Rings Termination for Rated SiC n-IGBTs; Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Ugobono, S. Monolithic Integration of Graphene in SiC Radiation Sensors for Harsh-Environment Applications

Uhlmann, N. Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide; Review of Sublimation Growth of SiC Bulk Crystals

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Valero, V. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Vantaggio, S. Estimation of Activation and Compensation Ratios in Ion Implanted 4H-SiC: Comparison of Two Methodologies

Vasquez, P. Multiscale Simulations of Plasma Etching in Silicon Carbide Structures

Vavasour, O. Engineering the Schottky Interface of 3.3 kV SiC JBS Diodes Using a Surface Passivation Treatment; The Improved Reliability Performance of Post-Deposition Annealed ALD-SiO2; A Study of High Resistivity Semi-Insulating 4H-SiC Epilayers Formed via the Implantation of Germanium and Vanadium

Vecchio, C. Opening Through 200 mm Silicon Carbide Epitaxy

Veliadis, V. SiC Mass Commercialization: Present Status and Barriers to Overcome

Vergne, B. Investigation of SiC Thyristors with Varying Amplifying Gate Design

Via, F. Effect of N and AI Doping on 3C-SiC Stacking Faults; Impact of N Doping on 3C-SiC Defects; Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding; Review of Sublimation Growth of SiC Bulk Crystals; The Development of Monolithic Silicon Carbide Intracortical Neural Interfaces for Long-Term Human Implantation; Graphite Assisted P and Al Implanted 4H-SiC Laser Annealing; Optical Characterization of 4H-SiC Thick Epitaxial Layer for Particle Detection; Automatic Image Analysis of Stackingfault; Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon; Neutron Detection Study Through Simulations with Fluka

Vidarsson, A. Observation of Fast Near-Interface Traps in 4H-SiC MOS Capacitors Using Capacitance Voltage Analysis at Cryogenic Temperatures

Vienne, C. Experimental Investigation of a -70A Switch with Six SiC-MOSFETs in a Series-Connection Configuration

Vines, L. Stability, Evolution and Diffusion of Intrinsic Point Defects in -SiC

Viravaux, L. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Vivona, M. Ni/Heavily-Doped 4H-SiC Schottky Contacts

Vladimirova, K. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Volte, A. Thermal Simulations of a New SiC Detector Design for Neutron Measurements in JSI Nuclear Research Reactor

Vudumula, P. Visualization of Interface Trap Distribution for Pd/AIN/6H-SiC and -SiC MOS Capacitors at

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Wada, R. SiC Diode with Vertical Superjunction Realized Using Channeled Implant and Multi-Step Epitaxial Growth

Waltl, M. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Waschneck, K. Performance Analysis of 4H-SiC Pseudo-D CMOS Inverter Circuits Employing Physical Charge Trapping Models

Watanabe, H. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs; Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Wehrle, M. Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs

Wellmann, P. Large Area Growth of Cubic Silicon Carbide Using Close Space PVT by Application of Homoepitaxial Seeding; In Situ Monitoring of Unintentionally Released Nitrogen Gas in the Initial PVT Silicon Carbide Growth Process Using Mass Spectrometry; Analysis of the Morphology of the Growth Interface as a Function of the Gas Phase Composition during the PVT Growth of Silicon Carbide; Review of Sublimation Growth of SiC Bulk Crystals; Applicability of a Flat-Bed Birefringence Setup for the Determination of Threading Dislocations of Silicon Carbide Wafers; Chemical Vapor Deposition of 3C-SiC on [100] Oriented Silicon at low Temperature for Photonic Applications

Widiez, J. 5c08d086-2273-42e8-a226-e67b09c9e4fd

Wirths, S. Ohmic Contact Formation on -SiC with a Low Thermal Budget by Means of Shallow Phosphorous Ion Implantation; Latest Advances in the Implementation and Characterization of High-K Gate Dielectrics in SiC Power MOSFETs; Clamped and Unclamped Inductive Switching of 3.3 kV 4H-SiC MOSFETS with 3D Cellular Layouts; On the Short Circuit Electro-Thermal Failure of 4H-SiC MOSFETs with 3D Cell Layouts

Woerle, J. Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology; Depth-Resolved Study of the -SiC Interface Using Low-Energy Muon Spin Rotation Spectroscopy; Sensitivity of Extraction at the Interface Using Quasi-Static Capacitance-Voltage Measurements; Fast Defect Mapping at the SiO2/SiC Interface Using Confocal Photoluminescence

Woodworth, A. Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

Wu, R. Electrothermal Modelling and Measurements of Parallel-Connected VTH Mismatched SiC MOSFETs under Inductive Load Switching

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Xu, L. 7478f2b2-3540-4f37-83b2-304b331b6df5

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Yamaguchi, H. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Yamakawa, S. Impact of Recovery Characteristics on Switching Loss of SiC MOSFETs

Yamashiro, Y. Behavior of Shockley-Type Stacking Faults in SiC Superjunction MOSFET under Body Diode Current Stress

Yamasue, K. Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy; Surface Potential Fluctuations of Interfaces Investigated by Local Capacitance-Voltage Profiling Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy

Yang, C. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Yang, Y. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Yeghoyan, T. 3C-SiC Heteroepitaxial Layers Grown on Silicon Substrates with Various Orientations

Youssef, T. Design of an Integrated Power Module for Silicon Carbide MOSFET with Self-Compensation of the Magnetic Field

Yu, S. 7478f2b2-3540-4f37-83b2-304b331b6df5

Yuan, Z. Localized Lifetime Control of 10 kV -SiC PiN Diodes by MeV Proton Implantation

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Zekentes, K. Modelling and Development of 4H-SiC Nanowire/Nanoribbon Biosensing FET Structures

Zhang, L. Investigations of Short Circuit Robustness of SiC IGBTs with Considerations on Physics Properties and Design; A Study of 4H-SiC Semi-Superjunction Rectifiers for Practical Realisation

Zhang, X. Microscopic Evaluation of -Type Diamond (111) Interfaces Using Scanning Nonlinear Dielectric Microscopy

Zheng, C. Design and Characterization of 10 kV High Voltage 4H-SiC p-Channel IGBTs with Low

Zielinski, M. Precise Control of AI Incorporation during CVD Growth of SiC Epilayers by Using Hydrogen Chloride; Vanadium Incorporation in 3C-SiC Epilayers and its Consequences for Electrical Properties of 3C-SiC Material; Residual Stress Measurement by Raman on Surface-Micromachined Monocrystalline 3C-SiC on Silicon on Insulator; Electrical Scanning Probe Microscopy Investigation of Schottky and Metal-Oxide Junctions on Hetero-Epitaxial 3C-SiC on Silicon; AIGaN/GaN High Electron Mobility Transistors Grown by MOVPE on 3C-SiC/Si(111) for RF Applications

Zimbone, M. Automatic Image Analysis of Stackingfault

Zimina, D. Impact of Surface Emissivity on Crystal Growth and Epitaxial Deposition