Structural Defects in Silicon Carbide

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Structural Defects in Silicon Carbide

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

All rights reserved. No part of the contents of this publication may be reproduced, processed or transmitted in any form or by any means without the written permission of the publisher.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-04

Online:
2025-09-05

Preface

The original version of this paper is available on https://www.scientific.net/SSP.375.-1.pdf

This special edition is devoted to recent advances in the control, monitoring, and effects analysis of structural defects in silicon carbide, which is a critical challenge for providing the performance and reliability of wide-bandgap semiconductor devices. Articles address fundamental and applied aspects of defect inspection methods and the impact of defects such as micropipes, bipolar degradation, lattice damage, and forward bias degradation on the power devices' functionality.

Attention was also paid to bonded substrate technologies and ion implantation technique and their influence on carrier mobility and long-term device performance.

This special edition provides a focused overview of the state of the art in the areas of control, analysis of characteristics, and effect compensation of silicon carbide structure defects, highlighting the scientific foundations and technological solutions that underpin the development of high-quality SiC devices.

Table of Contents

Preface

Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Enrica Cela, Walter Schwarzenbach, Ramesh Shrestha, Gerhard Bast, Sam Shahidi, Gavin Simpson

Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

An Min Amanda Lee, Xin Yi Li, Qin Gui Roth Voo, Shiv Kumar, Eng Soon Tok, Umesh Chand, Lakshmi Kanta Bera, Hema Lata Rao Maddi, Surasit Chung, Francois Hébert, Navab Singh, Yee Chia Yeo

Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

Hitesh Jayaprakash, Constantin Csato, Masashi Kato, Tong Li, Florian Krippendorf, Michael Rueb

Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Hidetsugu Uchida, Motoki Kobayashi, Naoki Hatta, Seiji Ishikawa, Yuta Higashi, Hiroshi Sezaki, Shinsuke Harada, Kazutoshi Kojima

Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Ze Yu Chen, Qian Yu Cheng, Shan Shan Hu, Balaji Raghothamachar, Charles Carlson, Dannie Steski, Thomas Kubley, Florian Krippendorf, Michael Rüb, Robert Koch, Reza Ghandi, Stacey Kennerly, Michael Dudley

Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Ze Yu Chen, Nadeemullah A. Mahadik, Michael Dudley, Balaji Raghothamachar, David A. Scheiman, Robert E. Stahlbush, Young Sang Kim, Michael W. Owen

Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Chiara Nania, Domenica Raciti, Cristiano Calabretta, Fabiana Vento, Ruggero Anzalone, Enzo Fontana, Andrea Severino

Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Suman Das, Daniel J. Lichtenwalner, Shane R. Stein, Sei Hyung Ryu

Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Yasuyuki Igarashi, Kazumi Takano, Yohsuke Matsushita, Takuya Morita

Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Hiroki Niwa, Takanori Tanaka, Kazuya Ishibashi, Hiroyuki Amishiro, Akifumi Imai, Yasuhiro Kagawa, Katsutoshi Sugawara, Tatsuro Watahiki

Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Atsushi Shimbori, Ryota Wada, Nobuhiro Tokoro, Takashi Kuroi, Hiu Yung Wong, Alex Q. Huang

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/structural-defects-in-silicon-carbide/978-3-0364-1917-6

Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 1-6

doi: 10.4028/p-Z2bqVH

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Revised:
2025-08-20

Accepted:
2025-08-21

Online:
2025-09-05

Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

Enrica Cela , Walter Schwarzenbach , Ramesh Shrestha , Gerhard Bast , Sam Shahidi and Gavin Simpson

Soitec, Chemin des Fontaines, Bernin, France

KLA Corporation, Technology Drive, Milpitas, US

enrica.cela@soitec.com, walter.schwarzenbach@soitec.com, ramesh.shrestha@kla.com, gerhard.bast@kla.com, sam.shahidi@kla.com, gavin.simpson@kla.com

*corresponding author

Abstract

Power devices electronics based on silicon carbide ( SiC ) are emerging as a breakthrough technology for a wide range of applications [1]. SiC engineered substrates provide a solution that fulfills power devices requirements, namely supplying high quality, ultra low resistivity materials. SmartSiC substrates, based on Smart Cut technology, combine the advantages of high quality single-crystal SiC and innovative pSiC handle material [2]. To achieve high volume manufacturing (HVM) of prime grade SiC engineered substrates, defects monitoring is crucial. This paper explains how a commercially available Deep-Ultraviolet (DUV) laser-based inspection system (KLA Surfscan SC1) was successfully used for the quality control of SmartSiC and single-crystal 4HSiC in a production environment. Detection of both surface and grown-in defects was investigated, on 150 mm and 200 mm substrates. Statistical data were collected and utilized for driving quality and yield continuous improvement.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

In the last decade, SiC power devices have emerged as an innovative solution for various applications such as traction inverters for automotive, DC/DC converters, on-board chargers and charging stations. Despite recent advances in the quality and supply of single-crystal wafers, progress regarding defect density and material performance is still needed and high volume production of prime crystal grade substrates remains a challenge [3-4].

To fulfill the requirements of the SiC industry, the substrate proposes to combine the high quality of a single-crystal device layer and the ultra-low resistivity of a handle wafer [5], as illustrated in Fig. 1. In addition, as detailed in [6], Smart Cut technology can be scaled to 200 mm wafers to overcome the risk of large size SiC substrates shortage.

Fig. 1. Typical SmartSiC structure

Fig. 1. Typical SmartSiC structure

Smart Cutfor SiC

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

The Smart Cut process (Fig. 2) consists of several steps, including hydrogen implantation of the starting material (donor material) which enables control of the transferred thickness (typically less than ). The implanted wafer is bonded to a handler material before splitting (step 5) and proceeding to finishing steps (step 6).

Fig. 2. Smart Cut process description, as adapted to SiC

Fig. 2. Smart Cut process description, as adapted to SiC

To target high volume manufacturing (HVM) of bonded SiC engineered substrates, inline defect monitoring and final quality control is key to guarantee device epitaxy yield. In this work, we focused on two crucial steps: the automatic defect inspection of the starting single-crystal donor material and the monitoring of the final epi-ready engineered substrate.

Surface Defects Monitoring Based on DUV Laser Light Scattering

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

As described in [7], a DUV laser-based system can be used to detect scratches and surface defects down to 50 nm on SiC wafers. Using a DUV source limits the noise related to SiC material transparency. When visible and near UV spectral ranges are used, this noise causes sub-surface signal detection and local reflectance variation. In this study, a DUV inspection tool (KLA Surfscan SC1) was used in a HVM environment for high sensitivity defect inspection of 150 and 200 mm SiC substrates.

Laser light scattering inspection technology is commonly used to detect surface defects on semiconductor substrates, including engineered substrates [8]. In this work, the Surfscan SC1 inspection system, which leverages a 266 nm laser light source, was utilized to characterize defectivity and surface quality of both SiC single-crystal donor wafers and SmartSiC engineered substrates. The optical configuration on the system was selected to gather the entire laser light scattering and spectral range. In this configuration a surface defect can be identified as a location where the scattered intensity is above the scattered signal from the surface, as illustrated in Fig. 3.

Particle (surface defect),

Figure 3. Particle (surface defect),

SC1 patch image, 0.5 mm FOV

Collected signal (a.u.)

Figure 4. Collected signal (a.u.)

Fig. 3. Signal processing used to identify surface defects based on laser light scattering

As the laser light scattering of surface defects is strongly dependent on substrate's optical properties, when using the laser light scattering configuration, it is important to calibrate the scattered intensity to estimate the size of the detected defects. For this experiment, calibrated Polystyrene Latex Spheres (PSL) were deposited both on single-crystal SiC and SmartSiC stack and the scattered intensity was correlated to defects size as illustrated in Fig. 4 and Fig. 5.

Fig. 4. PSL spheres deposited on a single-crystal (left) and scattering response calibration (right)

Fig. 4. PSL spheres deposited on a single-crystal (left) and scattering response calibration (right)

Fig. 5. PSL spheres deposited on a SmartSiC substrate (left) and scattering response calibration (right)

Fig. 5. PSL spheres deposited on a SmartSiC substrate (left) and scattering response calibration (right)

This procedure allowed us to collect statistical and comparable data in a production environment both for donor wafers (single-crystal SiC ) and for engineered substrates. Fig. 6 shows the statistical data for both populations at 300 nm minimum threshold.

Fig. 6. Statistical distribution of surface defect counts for prime donor wafers ( 360 wafers, left) and SmartSiC engineered substrates ( 396 wafers, right) (Surfscan SC1 scan, PSL threshold 300 nm )

Fig. 6. Statistical distribution of surface defect counts for prime donor wafers ( 360 wafers, left) and SmartSiC engineered substrates ( 396 wafers, right) (Surfscan SC1 scan, PSL threshold 300 nm )

On this sample, SiC engineered substrates surface defect density is comparable to single-crystal bulk substrates used as donors down to 300 nm inspection threshold. This performance is achieved thanks to specific surface finishing process, allowed by thin transferred layer surface treatment used for SmartSiC manufacturing.

Crystal originated defects monitoring based on PL intensity mapping

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

A crucial step of the Smart Cut process consists of splitting a thin monocrystalline SiC layer from a donor (refer to Fig. 2, step 1): the defectivity of the starting material has an impact on the total usable area of SmartSiC wafers. Depending on its quality, the donor substrate can show different grown-in defect types, like micro-pipes and inclusions [9-10]. As detailed in [11] and illustrated in Fig. 7, donor material defects may cause the generation of crystal originated defects (COD) on bonded engineered substrates. For this reason the HVM of SiC engineered substrates needs a fast and sensitive detection for this failure mode.

Fig. 7. Crystal Originated Defect generation on engineered substrates from a donor

Fig. 7. Crystal Originated Defect generation on engineered substrates from a donor

SiC photoluminescence (PL) imaging has been used for decades to characterize SiC crystal defects [12]: for this application the photon energy of the excitation source must be larger than the bandgap of the material, therefore an ultraviolet lamp or laser showing a wavelength shorter than 370 nm should be used. For this experiment, the Surfscan SC1 system, including a 266 nm laser and a PMT sensor, was utilized to characterize both SiC single-crystal donor wafers and SmartSiC engineered substrates. Because active defects affect carrier recombination, PL measurements provide a method to detect extended defects: PL intensity is locally reduced in defective areas, as defects act as nonradiative recombination centers. In this study, the optical configuration of the system was selected to avoid the collection of the scattered signal, by defining a defect as a location where the captured intensity is lower than the signal gathered from the surface, as illustrated in Fig. 8. The usage of a negative threshold algorithm allowed us to flag material grown-in defects in contrast to pure crystal.

Fig. 8. Signal processing used to identify crystal defects based on PL intensity mapping

Fig. 8. Signal processing used to identify crystal defects based on PL intensity mapping

A high resolution optical bench including a 266 nm excitation source and a CCD camera was used to image the defects identified thanks to negative threshold algorithm, as illustrated in Fig. 9.

Fig. 9. Examples of PL defects on as imaged by SC1 (left image) and using an optical bench (right image)

Fig. 9. Examples of PL defects on as imaged by SC1 (left image) and using an optical bench (right image)

PL signal intensity was mapped on a full wafer, on a broadband including visible and UV spectrum. To enhance the selectivity versus scattered signal the 266 nm peak was filtered. As illustrated in Fig. 10, this characterization revealed both crystal extended defects (such as species inclusions and micro-pipes) on incoming single-crystal donors and crystal originated defects on SmartSiC substrates.

Fig. 10. Surfscan SC1 PL intensity mapping of a donor grown-in defect (species inclusion) (left) and SmartSiC crystal originated defects (right), 0.5 mm field of view, 266 nm source

Fig. 10. Surfscan SC1 PL intensity mapping of a donor grown-in defect (species inclusion) (left) and SmartSiC crystal originated defects (right), 0.5 mm field of view, 266 nm source

Summary

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

This work showed that a DUV laser-based inspection system, the Surfscan SC1, can be used in a production environment for inline defect monitoring for manufacturing high-quality SmartSiC engineered substrates, at both 150 mm and 200 mm wafer sizes.

Both surface and extended crystal defects should be monitored to allow quality continuous improvement. In this study, surface defects were captured using the laser light scattered signal, while grown-in defects were revealed by PL intensity mapping. Statistical data collected showed that SiC engineered substrates surface defect density is comparable to single-crystal bulk substrates used as donors down to 300 nm inspection threshold.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

This work is supported by the H2020 - ECSEL JU program of the European Union under the grant of the TRANSFORM project 'Trusted European SiC Value Chain for a greener Economy' (ECSEL JU Grant No. 101007237).

References

The original version of this paper is available on https://www.scientific.net/SSP.375.1.pdf

T. Kimoto, Jpn. J. Appl. Phys. 54040103 (2015).

C. Maleville, "SmartSiC : a greener, faster and better technology for SiC" ICSCRM Conference, 2023.

M. Musolino et al., Microelectronic Engineering 274, 111976 (2023).

I. Manning et al., Mat. Sc. Forum 1062 (2022), pp 54-58.

S. Rouchier et al. "150 mm SiC engineered substrates for high-voltage power devices" ICSCRM Conference, 2021.

W. Schwarzenbach et al., "SmartSiCTM: Boosting SiC performance for high-voltage power applications," ICSCRM 2022.

E. Cela et al., Defect and diffusion forum 425 (2023), pp 57-61.

R. Brun et al., in Proceedings of the 2012 SEMI Advanced Semiconductor Manufacturing Conference, p. 67.

J. Fan and P. K. Chu, Silicon Carbide Nanostructures, (Springer International Publishing Switzerland, 2014) pp 35-37.

T.Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology, (John Wiley and Sons, Singapore, 2014) p. 51.

E. Cela et al., "Crystal originated defect monitoring and reduction in production grade SmartSiC™ engineered substrates." ICSCRM Conference, 2023.

T.Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology, (John Wiley and Sons, Singapore, 2014) p. 147-149.

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The original version of this eBook is available on https://www.scientific.net/book/structural-defects-in-silicon-carbide/978-3-0364-1917-6

Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 7-11

doi: 10.4028/p-d3Ksws

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-05

Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

The original version of this paper is available on https://www.scientific.net/SSP.375.7.pdf

An Min Amanda Lee , Xinyi Li , Voo Qin Gui Roth , Shiv Kumar , Eng Soon Tok , Umesh Chand , Lakshmi Kanta Bera , Hema Lata Rao Maddi , Surasit Chung , Francois Hébert , Navab Singh , and Yee Chia Yeo

Institute of Microelectronics, Agency for Science, Technology, and Research (A*STAR), Singapore 138634

Department of Physics, National University of Singapore, 2 Science Drive 3, Singapore 117542

Global Foundries 1000 River St. Essex Junction, VT 05452

Global Foundries 2600 Great America Way, Santa Clara, CA 95054

shiv_kumar@ime.a-star.edu.sg; glakshmi_kanta_bera@ime.a-star.edu.sg; hemalatarao.maddi@globalfoundries.com; surasit_chung@ime.a-star.edu.sg; francois.hebert@globalfoundries.com;

Abstract

This paper details the defect inspection and characterization of the n-type substrate pre- and post-epitaxy. The findings in this paper focus on the characterization of the micropipes (MPs) present in the 200 mm SiC substrate. Following epitaxy, the observations include how the micropipes were propagated from the substrate to the epilayer. This study explores the closing of micropipes during epitaxial growth. As a part of our efforts to better understand the crystal structure and elemental composition of the micropipes in the epilayer, we have conducted SAED and EDX experiments. To the best of our knowledge, it is the first report to demonstrate the region near the micropipe sidewall surface, is remarkably Si-rich ( ) than in the region towards the bulk ( ) after SiC epitaxial growth.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.7.pdf

Over the years, substantial research has been carried out on SiC defects and the production 4 H SiC wafers [1,2]. Micropipes (MP) are well-known defects in the substrates and have proven particularly troublesome. There has been some recent discussion that micropipe density has been reduced to a value lower than on 150 mm SiC substrates [3], but this may not be true for 200 mm wafers. High-quality wafers are still scarce. The quality of 200 mm wafers is questionable, and it is crucial to investigate these defects to achieve higher yields. According to Frank's theory [4], micropipes are hollow-core tubes that extend along the c-axis. Additionally, research on filling micropipes during homoepitaxy on SiC wafers remains unexplored. The performance of high-power devices is adversely affected by micropipes, making this an important area of study [5,6]. The objective of this research is to investigate the process of filling and closing micropipes during epitaxial growth.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.375.7.pdf

The epilayer has a thickness of approximately and is grown on a off-axis 4 H SiC (0001) wafer. Its dopant concentration is around , which is two orders of magnitude lower than that of the substrate (approximately ). The surface of the epilayer was examined using atomic force microscopy (AFM) and a root-mean-square (RMS) roughness of ( ) nm was obtained at a scan size of . The average width of the terraces was determined to be (8.3 , with a corresponding step height of . This indicates a dominant step height of two SiC bilayers, which is consistent with previous research [7].

The KLA Candela 8520 tool was used to examine both the substrate and epilayer. This tool is equipped with an integrated photoluminescence (PL) and surface inspection system, making it ideal for characterizing defects on SiC substrates and epilayers. Since the defects on the epilayers often show visible differences in height, we consider the topographic response as the main signal. We also use the scattered light response as a secondary signal to help identify the micropipe defects. For detailed micropipe defect inspection, we used high-resolution transmission electron microscopy (TEM), selected area electron diffraction (SAED), and energy dispersive X-ray (EDX) to understand the crystallographic information and elemental composition.

Fig. 1(a, b) depicts Nomarski microscope images of a micropipe on the substrate and after epitaxy growth. A micropipe is a screw dislocation with a large Burgers vector that traverses the SiC crystal in a direction parallel or close to the (0001) axis. It manifests as a void on the surface [8]. In the dark field mode, MPs appear as dark spots and scatter light around them, illustrating the high strain fields associated with MPs, as shown in Fig. 1(a). Consequently, a micropipe appears as a bright elongated streak in the scattered light image, extending along the direction of the incident beam. Fig. 1(c, e) shows the micropipe image on the substrate, and Fig. 1(d, e) shows the same location on the epilayer using Candela 8520 for two-channel specular oblique and raw radial topography oblique channels, respectively.

Fig.1. Examined MPs (a-b) Candela two-channel specular oblique channel, (c-d) raw radial topography oblique channel, (e-f) OM dark-field, (g) MP from the top and bottom from OM darkfield. (h) Schematic of the FIB cut direction for TEM measurement.

Fig.1. Examined MPs (a-b) Candela two-channel specular oblique channel, (c-d) raw radial topography oblique channel, (e-f) OM dark-field, (g) MP from the top and bottom from OM darkfield. (h) Schematic of the FIB cut direction for TEM measurement.

The micropipe on the substrate initially had a diameter of , as seen in Fig. 1(g). However, after of epitaxial layer growth, the diameter decreased to less than . This indicates that material growth is occurring on the sidewall of the micropipe. To examine the material on the sidewall and its crystal structure in more detail, we conducted cross-section TEM experiments. We used a focused ion beam (FIB) to cut the sample at the edge of the micropipe along ( ) direction for structure and composition analysis. We employed SAED to understand the crystal nature of the grown sidewall material. To better understand the diffraction pattern, it was simulated using CrystalMaker software.

Fig. 2(a) shows the TEM image of the bulk epilayer, and the simulated electron diffraction results are shown in Fig. 2(b). It is noticeable that a distinct clear diffraction pattern from several crystal planes confirms the high-quality crystallinity of the epitaxial film. The material composition, verified by EDX as seen in Fig. 2(c), shows the stoichiometry of SiC material. Fig. 3(a) shows the TEM image close to the micropipe location. Fig. 3(b,c) shows the SAED patterns extracted near the micropipe sidewall. The simulated diffraction pattern shows that additional crystal planes appear, suggesting that the sidewall material is not or that the stoichiometry of SiC changes. To examine this, EDX analysis was conducted, and the results shown in Fig. 3(d) reveal that the surface region close to the micropipe location is remarkably Si-rich than in the region towards the bulk . Our study is the first to show that Si-rich sidewalls of micropipes grow during SiC growth. Further study is needed to understand the phenomena of the filing of MPs.

Fig. 2. (a) TEM image of the bulk epilayer, (b) SAED patterns, (c) EDX measurement at two different locations in bulk.

Fig. 2. (a) TEM image of the bulk epilayer, (b) SAED patterns, (c) EDX measurement at two different locations in bulk.

Fig. 3. (a) TEM image of the side wall of MP, (b) SAED patterns, (c) zoom of the Fig.b inset shows the diffraction pattern along the line. (d) EDX measurement at two different locations on the side wall of the MP.

Fig. 3. (a) TEM image of the side wall of MP, (b) SAED patterns, (c) zoom of the Fig.b inset shows the diffraction pattern along the line. (d) EDX measurement at two different locations on the side wall of the MP.

Conclusion

The original version of this paper is available on https://www.scientific.net/SSP.375.7.pdf

This study investigated the closing of micropipes during epitaxial growth. We observed that the stoichiometry of SiC close to the MP sidewall location is remarkably Si-rich.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/SSP.375.7.pdf

This work was supported by A*STAR (Agency for Science, Technology and Research Singapore) under Grant No. A20H9A0242

References

The original version of this paper is available on https://www.scientific.net/SSP.375.7.pdf

P.C. Chen, W.-C. Miao, T. Ahmed, Y.-Y. Pan, C.-L. Lin, S.-C. Chen, H.-C. Kuo, B.-Y. Tsui, D.-H., Lien, Defect inspection techniques in SiC, Nanoscale Res. Lett., 17 (2022) 30.

H. Matsuhata, N. Sugiyama, B. Chen, T. Yamashita, T. Hatakeyama, T. Sekiguchi, Surface defects generated by intrinsic origins on epitaxial wafers observed by scanning electron microscopy, Microscopy, 66 (2017) 95.

M. Musolino, X. Xu, H. Wang, V. Rengarajan, I. Zwieback, G. Ruland, D. Crippa, M. Mauceri, M. Calabretta, A. Messina, Paving the way toward the world's first 200 mm SiC pilot line, Materials Science in Semiconductor Processing, 135 (2021) 106088.

F.C. Frank, Capillary equilibria of dislocated crystals, Acta Cryst., 4 (1951) 497.

T. Kimoto, Bulk and epitaxial growth of silicon carbide, Progress in Crystal Growth and Characterization of Materials, 62 (2016) 329.

J.D. Blevins, Development of a world class silicon carbide substrate manufacturing capability, IEEE Transactions on Semiconductor Manufacturing, 33 (2020) 539.

T. Kimoto, A. Itoh, H. Matsunami, T. Okana, Step bunching mechanism in chemical vapor deposition of 6H- and 4H-SiC {0001}, J. Appl. Phys., 81 (1997) 3494.

P.G. Neudeck, W. Huang, M. Dudley, Breakdown degradation associated with elementary screw dislocations in 4H-SiC p junction rectifiers, Sol. St. Electr., 42 (1998) 2157.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 13-20

doi: 10.4028/p-kLR0jq

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-05-06

Accepted:
2025-05-06

Online:
2025-09-05

Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

The original version of this paper is available on https://www.scientific.net/SSP.375.13.pdf

Hitesh Jayaprakash , Constantin Csato , Masashi Kato , Li Tong , Florian Krippendorf , Michael Rueb

mi2-factory GmbH, Moritz-von-Rohr Str. 1a, 07745 Jena, Germany

Ernst Abbe Hochschule, Carl-Zeiss-Promenade 2, 07745 Jena, Germany

Nagoya Institute of Technology, Gokiso, Showa, Nagoya 466-8555, Japan

Friedrich Alexander Universität, Cauerstr. 6, 91058 Erlangen, Germany

hitesh.jayaprakash@eah-jena.de, constantin.csato@mi2-factory.com, kato.masashi@nitech.ac.jp, li.tong@nitech.ac.jp, florian.krippendorf@mi2-factory.com, michael.rueb@mi2-factory.com

Keywords: 1SSF, BPD, Bipolar degradation, Ion Implantation, Carrier Lifetime

Abstract

Bipolar degradation poses a significant concern for the reliability of SiC bipolar power devices. The basic cause for bipolar degradation is expansion of Shockley Stacking Faults SSFs. These glide planes can be pinned and prevented from expansion. This study involves 19 MeV Energy Filtered Ion Implantation of Nitrogen (i.e. resulting in an energy spectrum ranging from 0 MeV to nearly 19 MeV in one shot) to explore the pinning effect of Nitrogen ions that suppresses recombination glide, which minimizes SSF growth, while providing precise doping of the entire drift region by the same Nitrogen implantation. All is performed in one single step. This procedure paves the path to immobilize any nucleation sites in the entire drift layer, this way enhancing the reliability and facilitating mass production of SiC power devices. This study employs UV illumination as an optical stressing method to create e-/h+ pair, which subsequently induce 1SSF expansion. Both, UV induced 1SSF expansion and pining were observed by photoluminescence. Carrier lifetime measurements were employed for understanding the mechanism of pinning defects.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.13.pdf

In recent years, there has been an increase in demand for wide band gap semiconductor for power device manufacturing [1], in particular to its superior physical properties that outperform conventional silicon for high voltage and high current device applications [2]. The power devices that are fabricated from suffer from several potential reliability issues [3-6]. These issues arise from material defects, gate-oxide reliability and other process related defects. Bipolar degradation as another very critical reliability mechanism is caused by material defects [7] under bipolar (electron hole plasma) current stress. Mitigation of this degradation effect can significantly improve the overall reliability of the SiC power devices.

The expansion of 1SSF by the mechanism of recombination enhanced dislocation glide (REDG) is considered to be the root cause and has been well understood in the recent decade [8-12]. The earliest approaches on pinning glide planes with ion implantation demonstrated that the material defects are pinned by certain ion species. Chen [13] reported the first pinning of such defects in 4H-SiC using Cu implantation, where Cu was found to pin BPDs from expansion. Due to high energy requirements for Cu ion to penetrate thicker 4H-SiC epitaxial layers for application in higher voltage class, Kato [14, 15] recently demonstrated that the deep implantation of protons in at the buffer-substrate interface pins the stacking faults extending from substrate into drift layer and thus avoiding bipolar degradation. The mechanism suggested is that the carrier lifetime is reduced and thus stacking fault expansion is suppressed [16,17]. The method is suitable for optimal suppression of SF when the implanted proton dose is and at the cost of additional ion species in the fabrication process.

In this study, Energy Filtered Ion Implantation (EFII) technology was employed to implant 0-19 MeV equivalent energies of nitrogen in one step to improve the material property significantly by making the material defects such as 1SSF and Partial Dislocations (PD) dormant to recombination enhanced dislocation glide in one process step. At the same time, EFII also offers custom specific drift zone doping, with superior precision control on doping homogeneity from batch to batch and wafer to wafer in mass production [18].

Experimental Approach

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To study the influence of suppressing 1SSF expansion in commercially available 4H-SiC material using EFII technology, optical stressing was employed [19-21]. This technique visualizes/reveals any nucleation sites or potential killer defects present in the epitaxial layer with UV excitation which are not usually detectable with conventional photoluminescence scan. In our experiments, we examined commercial epitaxial wafers from different vendors, by varying parameters such as Nitrogen implant concentration, epitaxial layer thickness, and taking into account defect correlation before and after EFII process.
Approach 1: Nominally un-doped epitaxial wafers with a thick epitaxial layer and a buffer layer were used to study defect correlations across different regions on the wafer under varying implant concentrations. 19 MeV Nitrogen ions were implanted on three wafers (A, B, C) using EFII Technology. Wafers A and B were implanted identically in each quadrant with concentrations between 1E15 and 1E16cm-3, while Wafer C was implanted with a lower concentration range of 1E14 to 1E15 cm-3. The implantation depth was , which extended beyond the epitaxial layer into the substrate. Followed by dopant activation annealing for 30 minutes in Ar ambient. Wafer description and implant parameters are detailed in Table 1 illustrated in Fig. 1. UV stressing conditions are described further.

Table 1: Description of wafer properties with N epitaxy and region of implanted concentrations of 19 MeV Nitrogen with EFII technology on the wafers.

Wafer label | BPD density* [cm⁻²] | Epitaxial concentration [cm⁻³] | Epitaxial thickness [μm] | Implanted Nitrogen Concentration [cm⁻³]
|  |  |  | Quadrant 1 | Quadrant 2 | Quadrant 3 | Quadrant 4
A | 68 | <5E14 | 5.01 | 1E+15 | 5E+15 | No implant | 1E+16
B | 3 | <5E14 | 5.17 | 1E+15 | 5E+15 | No implant | 1E+16
C | 2 | <5E14 | 5.04 | 5E+14 | 1E+14 | No implant | 1E+15
D | 80 | 5E+15 | 8.05 |  | 5E+15 |  |

*Claimed by wafer vendor
Approach 2: A wafer from a different vendor, with an epitaxial layer and 5E15 cm-3 nitrogen doping concentration, was analyzed for 1SSF expansion under stressing before and after the EFII process. This means the non-implanted wafer initially was UV stressed, density of expanded 1SSF defects were measured, then annealed at for 1 hour to contract (remove) the defects[19]. After implantation with 19 MeV Nitrogen using EFII technology and subsequent activation annealing, the same positions were UV stressed again to observe changes in 1SSF expansion density.

Details of the UV stress tests are described in the Table 2. We have estimated, that these intensities correspond to an electrical current density in the range for and from formula provided in [21] considering the highest surface recombination velocity (for , ) and correlating the results from other studies [22-24]. However, direct correlation of UV

Fig. 1: Illustration of implanted regions on Wafer A,B,C left and Wafer D right with EFII Technology corresponding to the data as mentioned in Table. 1

Fig. 1. Illustration of implanted regions on Wafer A,B,C left and Wafer D right with EFII Technology corresponding to the data as mentioned in Table. 1

intensity to electrical current density is still in discussion [20,21]. Comparing this study to earlier optical UV stress intensities, it can be considered that the epitaxial layers are under high UV stress conditions.

Table 2: Summary of UV illumination stress experiments done on the wafers with test areas of size .

Wafer
label
BPD
density*
[cm⁻²]
Epitaxial
concentration
[cm⁻³]
Epitaxial
thickness
[μm]
Implanted Nitrogen Concentration [cm⁻³]

Quadrant 1
Quadrant 2
Quadrant 3
Quadrant 4

A
68
<5E14
5.01
1E+15
5E+15
No implant
1E+16

B
3
<5E14
5.17
1E+15
5E+15
No implant
1E+16

C
2
<5E14
5.04
5E+14
1E+14
No implant
1E+15

D
80
5E+15
8.05

5E+15

Carrier lifetime measurements were performed on these EFII implanted regions to study the mechanism of pinning BPD/PD from expanding. -PCD measurements with 349 nm laser source and channel frequency of 26 GHz was used for wafer maps of A, B and C. For Wafer D, single point measurements at implanted and non implanted region were performed with -PCD with YAG266 nm as the excitation source and channel frequency of 10 GHz and compared to its Time Resolved Photoluminescence (TRPL) measurements. [14].

Results and Discussions

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Approach 1 The UV stressing with an intensity of not reveal any expanded 1SSF at any positions on wafers A and B . This could be due to the threshold density of carrier concentrations necessary for 1SSF expansion was not met in these thin layer [25]. However, after UV stressing with 142 Wcm-2, Fig. 2 shows the density of expanded 1SSF in no implant region, compared to EFII implanted regions at all test locations for wafer A, B and C. In Wafer A, a significantly higher density of the expanded 1SSF defects in no implant region is observed in contrast to the EFII implanted regions at all test positions. In case of Wafer B, there was only expansion of 1SSF in the non implanted region and no signature of 1SSF in any of the EFII implanted quadrants except negligible change around triangular defects was detected. On the other hand, Wafer C (where the implant concentrations were -3) revealed that there were expanded 1SSF both in non implanted region and EFII implanted region but the difference being the density was lower compared to the no implant region.

Approach 2 Photoluminescence (PL) images of the defect behavior from wafer D is summarized in Fig.3. All test regions illuminated with UV are in size. Region 1 was a random location on the wafer. At selected positions in this region, there were no observed at 420 nm and on as-grown epitaxial material before UV stressing. Many expanded 1SSF were detected after UV stressing with . The nucleation sites for these expanded defects were previously undetected. Fabrication of devices at such locations result in device degradation. These

Fig. 2: Measured density of expanded 1 SSF density on wafer A , B and C corresponding to EFII implant concentration at positions of area as illustrated (inset) for each wafer.

Fig. 2. Measured density of expanded 1 SSF density on wafer A , B and C corresponding to EFII implant concentration at positions of area as illustrated (inset) for each wafer.

are considered to be the BPD-TED conversion points. However after contracting these expanded 1SSF with anneal for 1 hour, EFII implantation with activation annealing was performed. To observe the effect of EFII on nucleation sites, UV stress was repeated under the same conditions as before. The PL images reveal that EFII process made significant number of these nucleation sites immune to REDG in contrast to earlier observation.

Fig. 3: PL images from wafer D reveal, previously undetected nucleation sites which expand after UV stress on as-grown material were successfully suppressed from expanding into 1SSF after the EFII process, as observed in both images corresponding to 1SSF and PD respectively. On region 2, PL images of cluster defects demonstrates the extent to which EFII restricts the movement of mobile PDs from nucleation sites in all lateral crystal directions, even under identical stress conditions.

Fig. 3. PL images from wafer D reveal, previously undetected nucleation sites which expand after UV stress on as-grown material were successfully suppressed from expanding into 1SSF after the EFII process, as observed in both images corresponding to 1SSF and PD respectively. On region 2, PL images of cluster defects demonstrates the extent to which EFII restricts the movement of mobile PDs from nucleation sites in all lateral crystal directions, even under identical stress conditions.

On region 2, (which is a cluster defect) the extent of PD (bright lines in PL images after UV stress corresponding to 1SSF in 420 nm image) expansion length shows that for same stressing conditions the material is less susceptible to dislocation glide. In Fig. 4(a), the implantation profile of Nitrogen can be seen extending into the buffer layer at measured with SIMS and in Fig. 4(b) the total density of expanded 1SSF before and after the EFII process at these two regions are compared. Hence, it is evident that in all the wafers the trend remains similar. The expanded density of 1SSF corresponding to Nitrogen implanted regions with EFII, irrespective of epitaxial layer thickness show immunity to REDG to a significant extent. The summary of these results are exhibited in Fig. 6(a) excluding cluster defect data for a fair comparison of usable wafer regions in power device manufacturing.

Fig. 4: (a) Illustration of implantation depth with EFII using GEANT4 simulation and SIMS measurement showing the Nitrogen profile on wafer D. (b) Significant reduction in density of expanded 1SSF witnessed before and after EFII process at both the regions. (c) Carrier life-time measurements with both TRPL and -PCD is compared on epitaxial layer at test points with EFII and without EFII locations. It is observed that the lifetime is decreased from 77.2 to 23.8 ns after EFII process which implanted 5E15 cm-3 N over an existing 5E15 cm-3 N concentration.

Fig. 4. (a) Illustration of implantation depth with EFII using GEANT4 simulation and SIMS measurement showing the Nitrogen profile on wafer D. (b) Significant reduction in density of expanded 1SSF witnessed before and after EFII process at both the regions. (c) Carrier life-time measurements with both TRPL and -PCD is compared on epitaxial layer at test points with EFII and without EFII locations. It is observed that the lifetime is decreased from 77.2 to 23.8 ns after EFII process which implanted 5E15 cm-3 N over an existing 5E15 cm-3 N concentration.

Carrier lifetime measurements: measurements done on wafer and C reveal that the regions with higher concentrations >5E15 cm-3 of Nitrogen implanted with EFII reduced the carrier lifetime values lower than the non-implanted region mapped in Fig. 5 which remains valid for reduction of life-time as a mechanism that suppresses 1SSF expansion from previous studies. This is also evident in Wafer D which was measured with TRPL and -PCD at two points (with EFII and without EFII) shown in Fig. 4 (c). Carrier lifetimes in the un-implanted regions of Wafer D and the EFII-implanted regions of Wafer A and B (with a total N concentration of 5E15 cm-3) were found to be similar, approximately . The results indicate that the carrier lifetime is primarily influenced by factors other than the presence of implanted nitrogen at the given concentration. This suggests that the implantation process itself did not significantly alter the carrier lifetime in the regions compared. However, at lower concentrations , the carrier lifetime is slightly higher than in non implanted region and yet effective suppression of 1SSF is observed, where the mechanism is not well understood. The lifetime corresponding to implanted nitrogen concentrations are summarized in Fig. 6(b).

Fig. 5: Carrier lifetime maps of thick epitaxial layer on Wafer A (a), Wafer B (b) and Wafer C (c) were measured with -PCD (with 3 mm edge exclusion) after the UV illumination tests. It is witnessed that at lower implant concentration the lifetime apparently improves provided the material is also having lower intrinsic defect density. Median values of the quadrants with implanted concentrations are labeled inset.

Fig. 5. Carrier lifetime maps of thick epitaxial layer on Wafer A (a), Wafer B (b) and Wafer C (c) were measured with -PCD (with 3 mm edge exclusion) after the UV illumination tests. It is witnessed that at lower implant concentration the lifetime apparently improves provided the material is also having lower intrinsic defect density. Median values of the quadrants with implanted concentrations are labeled inset.

Fig. 6: Expanded 1SSF defect density vs implanted nitrogen concentration, excluding cluster defects. EFII-implanted regions showed 10 times fewer defects than non-implanted areas. (b) Carrier lifetime vs implanted nitrogen concentration, improved by 10 times at the lowest concentration and decreased exponentially with increasing concentration, influenced by intrinsic material properties.

Fig. 6. Expanded 1SSF defect density vs implanted nitrogen concentration, excluding cluster defects. EFII-implanted regions showed 10 times fewer defects than non-implanted areas. (b) Carrier lifetime vs implanted nitrogen concentration, improved by 10 times at the lowest concentration and decreased exponentially with increasing concentration, influenced by intrinsic material properties.

We expect that the improvement in carrier lifetime is related to Nitrogen atoms preferentially filling carbon vacancies making the material more useful, similar to carbon implantation [26,27]. Hence, carrier lifetime reduction mechanism is considered to be one of the contributing factor to the suppression of stacking fault expansion.

Lattice work hardening seems to be the other contributing factor that could getter the defects from expanding by introduction of Nitrogen atoms in implanted material increasing the critically resolved shear stress (CRSS) in SiC matrix [14, 28-30]. The exact mechanism that significantly contributes to the pinning effect of these glide planes is yet to be studied, careful deep level transient spectroscopy (DLTS) measurements compared with PL spectrum data could reveal more information on how the defects caused by ion implantation that interact with recombination centers or trap levels that hinders the dislocation glide.

Summary

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Demonstration of Nitrogen implantation using EFII technology to effectively suppresses the recombination enhanced dislocation glide (REDG) of 1SSF is shown. These results indicate approximately 10 times lower defect concentration expanded in implanted regions compared to non-implanted areas for concentration range between 1E14-1E16 cm-3. Furthermore, significant improvement in carrier lifetime is observed in the as grown epitaxial material following the EFII process at lower concentrations below 1E15 . These findings suggest that REDG is influenced not only by a reduction in carrier lifetime but also by complex recombination mechanism involving the interaction between implanted defects and pre-existing recombination centers, warranting further investigation. Thus, a single EFII processing step not only enables the achievement of a highly homogeneous doping profile in SiC epitaxial layers but also enhances the material's resistance to bipolar degradation, outperforming as-grown epitaxial layers.

Acknowledgements

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All the ion implantations were conducted at the Ion Beam Center (IBC) of Helmoltz-Zentrum Dresden-Rossendorf (HZDR). The standard dopant activation annealing was performed at Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie (IISB), Erlangen.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 21-27

doi: 10.4028/p-7L8fIz

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-05

Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

The original version of this paper is available on https://www.scientific.net/SSP.375.21.pdf

H.Uchida , M. Kobayashi , N. Hatta , S. Ishikawa , Y. Higashi , H. Sezaki , S. Harada and K. Kojima

SICOXS Corporation, 5-11-3, Shimbashi, Minato-ku, Tokyo 105-0004, Japan

Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki 305-8568, Japan

PHENITEC SEMICONDUCTOR Corp., 6833, Kinoko-cho, Ibara, Okayama 715-8602, Japan

a*hidetsugu.uchida.x7@smm-g.com, motoki.kobayashi.x2@smm-g.com,

hiroshi-sezaki@phenitec.co.jp, s-harada@aist.go.jp, kazu-kojima@aist.go.jp

Keywords: Bonded substrate, Forward bias degradation, Shockley-type stacking fault (SSF), Hydrogen implantation, Carrier lifetime, Trap center, Deep level transient spectroscopy (DLTS)

Abstract

In this study, we investigated the generation of trap centers through hydrogen implantation to understand its role in the suppression of forward bias degradation in 4 H -silicon carbide bonded substrates. During the production of bonded substrates, hydrogen implantation is used for layer splitting. Transmission electron microscopy (TEM) observations revealed that the basal plane dislocation (BPD) in the bonded substrate did not extend into the Shockley-type stacking fault (SSF) and remained stable in the transferred layer below the epitaxial interface even under high forward current stress. Additionally, carrier lifetime, measured using microwave photoconductivity decay ( PCD), was considerably reduced by hydrogen implantation. Annealing at reduced the implanted hydrogen to levels below the detection limit of secondary ion mass spectrometry (SIMS), yet the carrier lifetime remained short. Deep level transient spectroscopy (DLTS) revealed that, after annealing at following hydrogen implantation, the concentration of the center increased by more than two orders of magnitude compared to pre-implantation levels. Trap centers, including the center, are believed to help prevent forward bias degradation in the bonded substrates by inhibiting the expansion of SSFs in the transferred layer.

Introduction

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is a highly promising wide-bandgap material for high-power electrical devices owing to its high dielectric breakdown field and excellent thermal conductivity. In recent years, bonded 4 H SiC substrates have been used in power devices. The SICOXS bonded substrate ( ) is produced by bonding a thin monocrystalline SiC layer, less than thick, to a low-resistance ntype polycrystalline substrate. This bonded structure offers the advantages of lowering the onresistance in power devices [1] and mitigating forward bias degradation in PiN diodes [2,3].

Forward bias degradation is commonly observed during bipolar operation. In PiN diodes, the forward voltage shift increases under forward current stress. This degradation is attributed to the expansion of Shockley-type stacking faults (SSFs) originating from basal plane dislocations (BPDs) [4]. During epitaxial growth, many BPDs are converted into threading edge dislocations (TEDs) [5, 6]. As the forward current density increases, holes can reach the BPDs in the substrate, causing SSFs to expand from these BPDs owing to electron-hole pair recombination, leading to forward bias degradation [7-9]. The proposed driving force behind SSF expansion is the energy gain from electron trapping and carrier recombination in the SSFs [10]. To counteract this issue, techniques such as recombination-enhancing buffer layers, which shorten carrier lifetime, are used to suppress SSF expansion [11]. We have demonstrated that bonded substrates considerably reduce forward bias degradation in PiN diodes, even under high forward current stress [2]. In bonded substrates, forward voltage shifts showed minimal increase, even at a high forward current stress of . Cross-
sectional TEM analysis of the PiN diode revealed that in the transferred layer of the bonded substrate, SSF expansion from BPDs was effectively prevented, even under high forward current stress [3].

Recently, the effect of hydrogen implantation on suppressing forward bias degradation has attracted attention. Studies have shown that hydrogen implantation can inhibit SSF expansion during forward current stress. The point defects introduced by hydrogen implantation have been reported to restrict dislocation glide motion, thereby preventing SSF expansion [12, 13]. Hydrogen implantation also plays a key role in the fabrication of bonded substrates. The bonded substrate is fabricated by implanting hydrogen ions into a monocrystalline substrate, bonding it to a polycrystalline substrate, and then performing layer splitting. The separated monocrystalline layer becomes the transferred layer, with most of the implanted hydrogen passing through it, while some remains within it. Point defects caused by hydrogen implantation can serve as trap centers, potentially promoting carrier recombination. Because the mechanism behind the suppression of SSF expansion and forward bias degradation in bonded substrates remains unclear, this study focuses on the generation of trap centers by hydrogen implantation to investigate the cause.

Experimental

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The analysis methods include transmission electron microscopy (TEM), deep level transient spectroscopy (DLTS), secondary ion mass spectrometry (SIMS), and microwave photoconductive decay ( -PCD). The bonded substrate was examined using TEM after applying forward current stress of to a PiN diode [3]. A vertically tilted cross-sectional TEM was used to clearly visualize the moiré fringes of SSFs, enabling the distinction between SSFs and BPDs.

DLTS measurements were performed to identify the types of trap centers generated by hydrogen implantation. In the transferred layer, which has a high carrier concentration, the depletion layer barely expands and the sensitivity is poor during DLTS measurements. To overcome this, an epitaxial layer with a low carrier concentration was grown on the bonded substrate for analysis. The dopant concentration and thickness of the epitaxial layer were and , respectively. Hydrogen implantation was performed on these epitaxial layers, followed by annealing at for 5 min in argon atmosphere on some samples to assess the effects of high-temperature activation annealing on reducing bonding interface resistance. The hydrogen concentration depth profile was measured using SIMS, while the carrier lifetime was evaluated by -PCD. For the DLTS measurements, Schottky barrier diodes with nickel electrodes were formed on the samples.

Results and Discussion

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1. Cross-sectional TEM image of bonded substrate after high forward current stress

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Fig. 1(a) shows a cross-sectional TEM image of the bonded substrate after applying a high forward current stress of . The expected BPD state before the stress is depicted in Fig. 1(b), and the BPD expansion after the stress observed in the TEM image is illustrated in Fig. 1(c). The BPD observed originated in the transferred layer and extended into the epitaxial layer during growth. Despite the high forward current stress, the BPD in the transferred layer remained stable and did not expand into the SSF, whereas the BPD in the epitaxial layer expanded into the SSF. In contrast, with a monocrystalline substrate, the SSF expanded by more than under forward current stress of [3]. These findings suggest that SSF expansion can be effectively prevented in the transferred layer of the bonded substrate.

Fig. 1. (a) Cross-sectional TEM image of a PiN diode in a bonded substrate after high forward current stress at and schematic diagrams (b) before forward current stress and (c) after forward current stress.

Fig. 1. (a) Cross-sectional TEM image of a PiN diode in a bonded substrate after high forward current stress at and schematic diagrams (b) before forward current stress and (c) after forward current stress.

2. Evaluation of Hydrogen Implantation

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TEM observations indicated that BPD expansion was suppressed in the transferred layer. To investigate the underlying reasons, we examined samples with hydrogen ions implanted into the epitaxial layer, as illustrated in Fig. 2.

Fig. 2. Schematic diagram of the cross-sectional sample structure

Fig. 2. Schematic diagram of the cross-sectional sample structure

Fig. 3 shows the hydrogen concentration depth profiles in the epitaxial layers. Hydrogen ions were implanted to a depth of approximately from the surface of the epitaxial layer, which was adjusted to match the thickness of the transferred layer in the bonded substrate. After annealing at , the concentration of implanted hydrogen decreased to below the detection limit of approximately . The bonded substrate subjected to forward current stress was also annealed at to reduce interface resistance, which likely removed hydrogen from the transferred layer. Despite this, SSF expansion in the transferred layer remained suppressed, indicating that factors other than hydrogen were responsible for the suppression of SSF expansion.

Fig. 3. Depth profiles of hydrogen concentration measured by SIMS after (a) hydrogen implantation and (b) annealing at after hydrogen implantation

Fig. 3. Depth profiles of hydrogen concentration measured by SIMS after (a) hydrogen implantation and (b) annealing at after hydrogen implantation

Fig. 4 shows the photoconductivity decay curves measured by -PCD. The carrier lifetime was defined as the time required for the photoconductivity to decay to of its initial value. Hydrogen implantation considerably reduced the carrier lifetime from 0.376 to . Despite the removal of hydrogen through annealing, as indicated in Fig. 3, the carrier lifetime remained relatively short at .

Fig. 4. Photoconductivity decay curves measured by - PCD after (a) epitaxial growth, (b) hydrogen implantation, and (c) annealing at following hydrogen implantation. The laser used has a wavelength of 266 nm , with a penetration depth of approximately into 4H-SiC.

Fig. 4. Photoconductivity decay curves measured by - PCD after (a) epitaxial growth, (b) hydrogen implantation, and (c) annealing at following hydrogen implantation. The laser used has a wavelength of 266 nm , with a penetration depth of approximately into 4H-SiC.

It is well established that the carrier lifetime of is influenced by the density of trap centers, such as the center [14,15]. To investigate this, we measured the trap densities and the energy levels of various trap centers from the conduction band using DLTS. The DLTS spectra and the Arrhenius plot of are presented in Figs. 5 and 6, respectively. In the plot, represents the emission time constant, T is the absolute temperature, and is the energy level of the trap center. The Arrhenius plots exhibit good linearity for all samples, allowing for the calculation of trap center energy levels from the slope. Immediately after epitaxial growth, the trap center with an energy level of 0.66 eV was detected. The energy level closely matches that of the center, which is associated
with carbon vacancies [15, 16]. The density of the center was measured at . After hydrogen ion implantation, the specific trap center with an energy level of 0.97 eV increased considerably to . Annealing at caused the specific trap center to disappear, but the center density increased by more than two orders of magnitude to compared to before implantation. SIMS analysis confirmed that hydrogen was removed during the annealing process at , showing similar thermal behavior to the specific trap center, suggesting a possible association with hydrogen atoms. Further studies will be required to clarify the origin of the specific trap center. Conversely, because the center is formed during annealing at , it is expected to remain in the transferred layer of the bonded substrate even after activation annealing during the fabrication of SiC devices. The suppression effect of SSF expansion may be associated with the center, formed by hydrogen implantation and the subsequent annealing.

Fig. 5. Deep level transient spectroscopy (DLTS) spectra (with a period width of 192 ms ) for Schottky barrier diodes after (a) epitaxial growth, (b) hydrogen implantation, and (c) annealing at following hydrogen implantation

Fig. 5. Deep level transient spectroscopy (DLTS) spectra (with a period width of 192 ms ) for Schottky barrier diodes after (a) epitaxial growth, (b) hydrogen implantation, and (c) annealing at following hydrogen implantation

Fig. 6. Arrhenius plot of for Schottky barrier diodes after (a) epitaxial growth, (b) hydrogen implantation, and (c) annealing at following hydrogen implantation. In the plot, is the emission time constant, T is the absolute temperature, and is the energy level of the trap center.

Fig. 6. Arrhenius plot of for Schottky barrier diodes after (a) epitaxial growth, (b) hydrogen implantation, and (c) annealing at following hydrogen implantation. In the plot, is the emission time constant, T is the absolute temperature, and is the energy level of the trap center.

3. Discussion on Suppression of SSF Expansion in Bonded SiC Substrates

The original version of this paper is available on https://www.scientific.net/SSP.375.21.pdf

Fig. 7 shows hole movement under forward current stress in the bonded substrate. Despite the presence of BPDs in the transferred layer, which are expected to convert into TEDs near the epitaxial interface, cross-sectional TEM images in Fig. 1 confirm that BPDs did not expand into SSFs in the transferred layer even under high forward current stress. The suppression of SSF expansion is likely associated with trap centers, including the center, formed by hydrogen implantation and subsequent annealing. When forward bias is applied, holes flow through the epitaxial layer and into the transferred layer. Upon reaching the transferred layer under stress, the holes are annihilated at trap centers near the epitaxial interface owing to the recombination of electron-hole pairs. Because holes do not reach the BPDs in the transferred layer, SSFs do not expand from BPDs as a result of recombination.

We have reported that no near-band-edge emission is observed in the transferred layer [3], suggesting that the presence of trap centers is likely responsible for the absence of this emission. The trap centers created by hydrogen implantation are expected to be present in the transferred layer, where they help suppress forward bias degradation in the bonded substrates by preventing SSF expansion.

Fig. 7. Schematic diagram of hole movement under forward current stress. In the diagram, circles represent holes, arrows indicate the direction of hole movement, short lines denote trap centers, and stars represent the recombination of electrons and holes.

Fig. 7. Schematic diagram of hole movement under forward current stress. In the diagram, circles represent holes, arrows indicate the direction of hole movement, short lines denote trap centers, and stars represent the recombination of electrons and holes.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.375.21.pdf

The generation of trap centers owing to hydrogen implantation was investigated to understand the suppression effect of forward bias degradation in bonded substrates. TEM observations revealed that in the bonded substrate, the BPD did not expand into the SSF and remained unchanged in the transferred layer below the epitaxial interface, even under high forward current stress. Hydrogen implantation considerably shortened the carrier lifetime as measured by -PCD. Although annealing at reduced the hydrogen concentration to below the detection limit of SIMS, the carrier lifetime remained short. DLTS measurements indicated that, following annealing at after hydrogen implantation, the center density increased by more than two orders of magnitude compared to before hydrogen implantation. It is believed that the trap centers generated by hydrogen implantation help suppress forward bias degradation in the bonded substrate by preventing the expansion of SSFs in the transferred layer.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/SSP.375.21.pdf

This paper has been implemented under a joint research project of Tsukuba Power Electronics Constellations (TPEC). The co-authors, S. Ishikawa and Y. Higashi are assigned to AIST from PHENITEC SEMICONDUCTOR Corp.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.21.pdf

T. Shimono, H. Uchida, A. Onogi, and H. Fujiwara, 7th Meeting on Advanced Power Semiconductors, IB-18, Japan (2020)

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 29-34

doi: 10.4028/p-99wz0T

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-07

Accepted:
2025-08-07

Online:
2025-09-05

Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

Zeyu Chen , Qianyu Cheng , Shanshan Hu , Balaji Raghothamachar , Charles Carlson , Dannie Steski , Tomas Kubley , Florian Krippendor , Michael Rüb , Robert Koch , Reza Ghandi , Stacey Kennerly and Michael Dudley

Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794 USA

Brookhaven National Laboratory, Upton, NY, 11973 USA

MI2-Factory GmbH, Moritz-von-Rohr-Straße 1A, Jena, 07745 Germany

University of Applied Sciences Jena, Carl-Zeiss Promenade 2, Jena, 07745 Germany

GE Research, Niskayuna, NY, 12309, USA

zeyu.chen@stonybrook.edu, qianyu.cheng@stonybrook.edu, shanshan.hu@stonybrook.edu, balaji.raghothamachar@stonybrook.edu, ccarlson@bnl.gov, steski@bnl.gov, tkubley@bnl.gov, florian.krippendorf@mi2-factory.com, michael.rueb@mi2-factory.com, michael.rueb@eah-jena.de, robert.koch@eah-jena.de, mStacey.kennerly@ge.com, , michael.dudley@stonybrook.edu

Keywords: 4 H -SiC; Heated high energy ion implantation; Lattice strain; HRXRD

Abstract

Multi-step high energy ion implantation enables uniform doping to depths up to in epiwafers for superjunction devices but extent of lattice damage is of significant concern for device fabrication. 4H-SiC wafers with thick epilayers implanted with Al ions at a concentration of using the Tandem Van de Graaff accelerator at Brookhaven National Laboratory across an energy range of 13.8 to 65.7 MeV and at different temperatures: room temperature, , and were analyzed by reciprocal space mapping measurements. Implanted layers exhibited tensile strains that decreased with increasing implantation temperature indicating dynamic annealing effect reduces lattice damage. On annealing at , for recovery of the lattice strain, RSM measurements show that the highest implantation temperatures have the lowest residual strains. In addition, the use of a Silicon Energy-Filter for Ion Implantation (EFII) for Al implantation in a single stage to the depth of is found to further reduce lattice strain compared to wafers implanted without EFII to the same doping concentration. This preliminary study will assist in optimizing the implantation and annealing conditions for the development of superjunction devices.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

Silicon Carbide ( SiC ) is a wide bandgap semiconductor with exceptional properties that make it ideal for power devices, including wide bandgap, high breakdown voltage, and excellent thermal stability [1]. The demand for devices capable of handling voltages ranging from 1.7 to 6.5 kV is increasing, driven by their applications in hybrid systems, shipboard and power grid configurations, and high-speed trains. These devices are generally fabricated on wafers with thick epilayers to improve breakdown voltages [2], but uniformly doping such thick epilayers poses significant challenges. A promising approach to address this involves using multi-step high-energy ion implantation, utilizing the system at Brookhaven National Laboratory's Tandem Van de Graaff accelerator facility [3], which can implant ions with energies up to 150 MeV . This technique has successfully produced medium voltage charge balance devices, including 2 kV and 3.8 kV superjunction structure PIN diodes [4]. Nonetheless, high-energy ion implantation introduces
considerable lattice strain by displacing host atoms in the epilayer, making it crucial to characterize this strain to understand the damage induced by high-energy implantation. One way to reduce lattice damage is by employing high temperature annealing process, however, annealing temperature of up to is needed to fully recover the strain [5] and these elevated temperatures can result in rough wafer surfaces, which is detrimental for device fabrication. Another approach to reduce the annealing temperature is to perform high-energy implantation at elevated temperatures, as the dynamic annealing effect can partially reduce lattice strain in the as-implanted wafer. The dynamic annealing effect has been extensively studied over the years. Kuznetsov and colleagues [6] suggested that this reduction in lattice damage is due to the annihilation of vacancies and interstitials created during implantation. The level of lattice damage following heated implantation is influenced by the balance between the generation and annihilation rates of these point defects. Conventional implantations at temperatures up to have been demonstrated to mitigate the formation of basal plane dislocations (BPDs) caused by the strain induced during implantation [7].

Synchrotron X-ray plane wave topography (SXPWT) and reciprocal space mapping (RSM) techniques have demonstrated their capability to evaluate the strain distribution in a epilayer of a epiwafer subjected to multi-step, high-energy implantation with ions at room temperature. The results indicated that the strain in the implanted region was approximately higher than in the non-implanted region [8]. To reduce the damage caused by implantation, multi-step implantation with ions was conducted at room temperature, , and . Strain measurements from RSM showed values of , and , respectively [9]. The data clearly demonstrate a reduction in strain with increasing implantation temperature due to the dynamic annealing effect. Recently, Steinbach and colleagues reported that using a jagged Energy-Filtered for Ion Implantation (EFII) device manufactured by MI2-Factory can produce a box-shaped concentration profile with a single implantation [10]. This technique may further reduce the strain level in the implanted wafer. Characterization of post-annealed wafers multistep high-energy implanted with Al ions and as-single-step implanted wafer with EFII will be discussed in this paper.

Experiment

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

4H-SiC wafers with epilayers were blanket implanted with Al ions by multi-step high energy implantation at room temperature (RT), and at BNL via the Tandem Van de Graaff accelerator with energy range of 13.8 to 65.7 MeV . The concentration of the implanted Al ions is 5 x . Following implantation, the wafers were annealed at (typical temperature for implanted SiC wafers). Besides, another wafer was subjected to single-step high energy implantation at RT with EFII manufactured by MI2-Factory at 60 MeV , then Secondary Ion Mass Spectrometry (SIMS) analysis was carried out to confirm the concentration and depth of the Al ions.

The wafers were characterized by high resolution X-ray diffraction (HRXRD) to analyze the effect of temperature on the lattice strain generated by the implantation. Rocking curves and reciprocal space mapping (RSM) in (0008) reflections were carried out on a Bede D1 diffractometer with Cu . The beam was conditioned by a MaxFlux multilayer mirror and channel-cut Ge (004) monochromator at 40 kV and 30 mA . For triple axis scan and RSM, a channel-cut Si (111) analyzer was placed in front of the detector (see Fig. 1 for schematic of the experimental setup).

Fig. 1. Schematic of experimental setup of HRXRD.

Fig. 1. Schematic of experimental setup of HRXRD.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

Multistage high energy implantation has previously been shown to achieve box implantation [11]. Therefore, SIMS analysis was performed for wafer subjected to single-step high energy implantation with EFII as shown in Fig. 2 to measure the doping profile. The result shows a box profile with Al concentration of to the depth of , proving the effectiveness of employing EFII to achieve box profile with a single-step implantation. The corresponding triple axis scan by HRXRD shown in Fig. 3 displays main and satellite peaks with a peak separation of , indicating tensile strain in the epilayers after implantation. RSMs were recorded to analyze the strain characteristics of the wafers implanted with multi-step implantation at , as well as the single-step implantation with EFII at RT, as illustrated in Fig. 4. The RSMs reveal two peaks, with the satellite peak diffracted from damaged epilayer yielding higher intensity compared to the substrate peak due to the relatively thick epilayers that attenuate diffracted intensity from the substrate. The vertically aligned peaks suggest the absence of lattice tilt, while the satellite peaks, positioned on the negative side of the main peak along the y -axis, indicate that the epilayers experience tensile strain following implantation. This observation is consistent with the results from the triple axis scans [9]. The strain level of and was estimated from RSM by the following equation:

where d is the lattice spacing of and is the change in peak position along the vertical axis in the RSM. The peak separation and estimated strain level of wafer implanted with EFII are comparable to those of wafer implanted with multi-step high energy at , illustrating that the single-step implantation with EFII can reduce the level of as-implanted damages. Kuznetsov and coworkers have discovered that the relative damage due to implantation can be lowered by decreasing the ion flux [6]. By employing EFII, only single-step implantation is needed to create a box profile, which can significantly decrease the accumulated time for implantation compared to multi-step implantation. Therefore, the flux or dose rate of implantation employing EFII can be much smaller
than that of multi-step high energy implantation, leading to reduction of the lattice strain after implantation for wafer implanted with EFII.

Fig. 2. SIMS result of wafer subjected to single-step implantation with EFII.

Fig. 2. SIMS result of wafer subjected to single-step implantation with EFII.

Fig. 3. Triple axis scan wafer implanted with EFII .

Fig. 3. Triple axis scan wafer implanted with EFII .

Fig. 5 shows RSMs of wafers after multi-step implantation at RT, , and and after annealing process. The RSMs of post-annealed wafers, plotted in rotation axis with intensity scaled at and , indicate single peak without satellite peaks, meaning that the damages due to implantation have been recovered, since the high temperature condition increase the mobility of dopant atoms, interstitials and vacancies and encourage them to move to the correct lattice sites. Overall, the RSMs of annealed wafers exhibit symmetric contours along the axis. However, for the contour of of peak intensity (highlighted by orange dashed line), the
width of the contour of wafers implanted at , and are and respectively. The residual strain in the annealed wafer will have a larger effect of diffuse scattering, leading to an increase of width at low intensity. Therefore, implantation at higher temperature can lower the residual strain after annealing process.

Fig. 4. 0008 Reciprocal space maps of wafers as-implanted with multi-step implantation at RT, and single-step implantation with EFII at RT.

Fig. 4. 0008 Reciprocal space maps of wafers as-implanted with multi-step implantation at RT, and single-step implantation with EFII at RT.

Fig. 5. Post-annealed at of wafers with multi-step implantation at . The orange dashed line indicates the contour having maximum intensity.

Fig. 5. Post-annealed at of wafers with multi-step implantation at . The orange dashed line indicates the contour having maximum intensity.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

High resolution X-ray diffraction have been employed to characterize implanted and post-annealed 4 H -SiC wafers implanted at , and . The result shows that the major damages have been recovered, while the residual strain decreases as implant temperature increases. Implantation with Si Energy-Filter for Ion Implantation has been conducted, indicating a box concentration profile can be achieved by single-step implantation and the as-implanted strain is lower due to the effective dose rate is smaller for single-step implantation.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DEAR0001028. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

Work at Brookhaven National Laboratory was sponsored by the U.S. Department of Energy under Contract No. DE-SC0012704 with Brookhaven Science Associates, LLC.

This research used resources of the Advanced Photon Source, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.29.pdf

A.A. Lebedev and V.E. Chelnokov, Semiconductors 33, 999-1001 (1999).

T. Liu, S. Hu, J. Wang, G. Guo, J. Luo, Y. Wang, J. Guo and Y. Huo, IEEE Access, 7 145118145123. (2019)

P. Thieberger, C. Carlson, D. Steski, R. Ghandi, A. Bolotnikov, D. Lilienfeld, P. Losee, Nucl. Instrum. Methods Phys. Res. B: Beam Interact. Mater. At. 442 36-40. (2019)

R. Ghandi, A. Bolotnikov, S. Kennerly, C. Hitchcock, P.-m. Tang, T.P. Chow, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE, 126-129 (2020)

Z. Chen, Y. Liu, H. Peng, Q. Cheng, S. Hu, B. Raghothamachar, M. Dudley, R. Ghandi, S. Kennerly and P. Thieberger, ECS J. Solid State Sci. Technol. 11065003 (2022)

A. Yu. Kuznetsov, J. Wong-Leung, A. Hallen, C. Jagadish, and B. G. Svensson, Journal of Applied Physics 94, 7112 (2003)

S. Mancini, S. Jang, Z. Chen, D. Kim, Y. Liu, B. Raghothamachar, M. Kang, A. Agarwal, N. Mahadik, R. Stahlbush, M. Dudley, W. Sung, proceeding of 2022 IEEE International Reliability Physics Symposium (IRPS) (2022)

Z. Chen, H. Peng, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar, M. Dudley, R. Ghandi, S. Kennerly and P. Thieberger, Materials Science Forum 1062, 361-365 (2022)

Z. Chen, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar, R. Ghandi, S. Kennerly, C. Carlson, D. Steski, M. Dudley, Defect and Diffusion Forum 434, 87-92. (2024)

T. Steinbach, C. Csato, F. Krippendordf, F. Letzkus, M. Rüb, J.N. Burghartz, Microelectronic Engineering 222 (2020) 111203

Z. Chen, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar and M. Dudley, Journal of Crystal Growth 627, 127535(2024)

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 35-41

doi: 10.4028/p-I5U9fS

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-08-08

Accepted:
2025-08-08

Online:
2025-09-05

Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

The original version of this paper is available on https://www.scientific.net/SSP.375.35.pdf

Zeyu Chen , Nadeemullah A. Mahadik , Michael Dudley , Balaji Raghothamachar , David A. Scheiman , Robert E. Stahlbush , Youngsang Kim and Michael. W. Owen

Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794 USA

US Naval Research Laboratory, Washington, DC, 20375, USA

Defense Microelectronics Activity, McClellan Park, CA 95652

zeyu.chen@stonybrook.edu, nadeem.mahadik@nrl.navy.mil, michael.dudley@stonybrook.edu,

balaji.raghothamachar@stonybrook.edu, david.a.scheiman2.civ@us.navy.mil,

robert.e.stahlbush.civ@us.navy.mil, youngsang.kim4.civ@mail.mil, michael.w.owen.civ@mail.mil

Keywords: 4H-SiC; Stacking Fault; Partial Dislocation dipole; UV Photoluminescence Imaging; Xray Topography

Abstract

H}-\mathrm{SiC}) with epilayer was subjected to UV exposure. Stacking fault expanded from basal plane dislocation (BPD) loop generated during growth in the epilayer was observed by UV Photoluminescence Imaging (UVPL) and X-ray Topograph (XRT) techniques. Interactions between partial dislocation, emanating from the BPD loop and gliding via recombination-enhanced dislocation glide mechanism, and threading screw/mix dislocations are detected and analyzed, where stacking faults migrate to different basal plane after the interactions. Such migration increases the faulted volume that can severely degrade reliability and performance of high power SiC devices by increasing reverse leakage current and on-state resistance and could eventually lead to device failure.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.35.pdf

Silicon Carbide ( SiC ) is a wide bandgap semiconductor with considerable potential for power devices due to its high breakdown field and excellent thermal conductivity. These properties enable SiC devices to function effectively under extreme conditions, including high temperatures, voltages, and frequencies [1]. Currently, commercially available devices can handle voltages up to 3.3 kV and are primarily used in automotive and traction control applications. However, there is a need for SiC devices with higher voltage ratings ( ) for use in hybrid systems, shipboard power, grid systems, and defense applications. To achieve the required breakdown voltages, these devices are manufactured on SiC wafers with thick epitaxial layers [2]. As the thickness of the epitaxial layer increases, the density of defects formed during growth also rises [3], which can significantly impact device performance. Recent research by Mahadik et al. has identified a complex stacking fault originating from the substrate and extending into a thick epitaxial layer. This fault generates several Shockley-type stacking faults (SSFs) when carriers are injected via UV excitation, through a recombination-enhanced dislocation glide mechanism . Such stacking faults are detrimental to the device performance, causing decrease of forward voltage during on-state and increase of leakage current during off state.

Additionally, another defect commonly observed in epitaxial layers is the interfacial dislocation (ID) accompanied by half-loop arrays (HLAs) [7]. These HLAs form when screw-oriented basal plane dislocations (BPDs) glide under mismatch stresses, causing bending at the growth front and leading to their conversion into threading edge dislocations (TEDs). When the gliding velocity of BPDs surpasses the growth rate of the epitaxial layer, some of these dislocations protrude through the surface, creating HLAs composed of two TEDs and a segment of BPD that can dissociate into
stacking fault bounded with partial dislocations as well [8]. Therefore, generation of BPDs and SSFs are the major impedances for developing high voltage bipolar devices such as insulated gate bipolar transistors, and they should be carefully characterized and investigated. In this paper, with epilayer was characterized by ultraviolet photoluminescence (UVPL) imaging and Highresolution X-ray topography (XRT). Interaction between threading screw/mixed dislocations and partial dislocation generated from BPD loop during UV excitation was observed and analyzed.

Experiment

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4H-SiC with epilayer doped with n-type was subject to whole wafer UVPL imaging [9], using a 4 Watt, 355 nm UV laser that was coupled to a custom microscope with automated high precision XYZ stage. UVPL images were acquired with spatial resolution, using a 665 nm long pass emission filter, and a liquid N2 cooled CCD detector and sequential images were acquired with spatial resolution on the selected SSF.

High-resolution x-ray topography (XRT) was performed using a Rigaku XRTMicron system equipped with a micro-focus, rotating anode. The system has a vertical 3-circle goniometer with up to 200 mm diameter sample stage, and a pixel x-ray camera. XRT image of the complex defect was acquired using in transmission geometry with MoK radiation.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.375.35.pdf

Fig. 1(a) shows 11-20 XRT image before UV exposure, where a screw BPD ( ) originating from the substrate is replicated into the epilayer forming a BPD loop and ID. However, no HLA is observed associated with the ID. The formation mechanism of such defect is that the screw BPD segment first get replicated into epilayer (Fig. 1(b)) then glides under the misfit stress (Fig. 1(c)). Due to the change in the line direction, the BPD segment at the growth front will deviate from screw type allowing the that the partials to constrict enabling conversion to TED which now acts as a pinning point (Fig. 1(d)). In this case, differing from the formation of HLAs, the relative gliding speed of the BPD is lower than the growth rate of the epilayer due to lower stress, so it propagates as a loop in the epi-layer and forms ID at the epi/sub interface (Fig. 1(e) and 1(f)). Such a BPD loop in the epilayer acts as a single-ended Frank Read source. As the loop expands in the epilayer encounters TSD/TMDs, segments of the BPD loop will migrate to different basal planes via the jog mechanism [10]. Upon UV excitation, stacking faults and partial dislocations will expand from this looping BPD segment on different basal planes. When opposite sign partial dislocations which have same Burgers vectors and opposite line directions located on different basal planes and align on top of each other along [0001] direction, partial dislocation dipole (PDD) can be formed [11], due to the attractive force between the opposite sign partial dislocations. Fig. 2 shows UVPL images (2D projections of 3D microstructure) indicated by the red box, where the red number indicates the basal plane the stacking faults are located on, and the corresponding 3D schematic of the mechanism of interactions between partial dislocations and TSD/TMDs (indicated by the yellow arrows in UVPL image of Fig. 2(b)). In this figure, a total of 4 basal planes (labeled at bottom left corner on each plane) and three TSD/TMDs are involved. TMD1 and TMD3 are assumed to be right-handed with Burgers vector of the screw component of [0001] and TMD2 is left-handed with Burgers vector of the screw component of . When the stacking fault bounded by partial dislocation interacts with right-handed screw TMD, the left side of the fault will stay on the same plane while the right side of the fault will advance to the plane above with respect to the advancing direction due to the to the helical shape with clockwise orientation. On the other hand, if such a fault interacts with left-handed TMD, the left side of the fault remains on the same plane, while the right side of the fault will move to the plane below.

At the start of UV illumination, two double rhombic shape SFF on plane 2 and 4, and a PDD1 are formed due to UV excitation as highlighted in the UVPL image by the red arrow and the red segment in the 3D diagram in Fig. 2(a). Si-core partials with Burgers vector are labeled as P1 to P 3 , where P 1 and P 3 will advance along [1 ], and P 2 and P 4 will advance along upon UV excitation. When P3 advances and interacts with TMD1, resulting in the left side of the fault with P3-2 segment remaining on plane 4 and the right side of the fault with P3-1 segment advancing to plane 3 and forming PDD2 illustrated by the orange solid lines, as shown in Fig. 2 (b). As P2 advance to the right and P3-2 propagate along [1 ], the partials belonging to PDD1 and PDD2 on plane 4 are elongated and shorten segment until it disappears. In addition, as P 2 propagating to the right encounters the advancing P3-1 toward [1̄100], PDD3 is formed, as shown in Fig. 2 (c). After that, P1 keep advancing and then the elongated P2 propagates to the right and interacts with TMD3, resulting in the left side of the fault, with respect to the advancing direction, staying on plane 2 having P2-1 segment and the right side moves to the plane 1 with P2-2 segment, forming PDD4 composed of PDD4-1 and PDD4-2 and indicated by yellow solid line in the 3D schematic.

Fig. 1. (a) High resolution 11-20 XRT image of formation of BPD loop and ID in epilayer due to the original BPD in substrate. (b) to (f) Schematic of formation mechanism of the BPD loop and ID in epilayer.

Fig. 1. (a) High resolution 11-20 XRT image of formation of BPD loop and ID in epilayer due to the original BPD in substrate. (b) to (f) Schematic of formation mechanism of the BPD loop and ID in epilayer.

Fig. 2. (a)-(d) 3D schematic of propagation of partial dislocations of the SSFs interacting with TMD1 and TMD3 forming PDD1 to PDD4, where the black numbers in the images indicate the corresponding basal planes of the SSFs are located at. UVPL images are shown in the red boxes, where the red numbers in the images indicate the corresponding basal planes of the SSFs located at.

Fig. 2. (a)-(d) 3D schematic of propagation of partial dislocations of the SSFs interacting with TMD1 and TMD3 forming PDD1 to PDD4, where the black numbers in the images indicate the corresponding basal planes of the SSFs are located at. UVPL images are shown in the red boxes, where the red numbers in the images indicate the corresponding basal planes of the SSFs located at.

Then, P2-2 segment interacts with TMD2 with Burgers vector of the screw component of [ ], leading to the left side of the fault with P2-2 segment staying on plane 1 and the right side of the fault with P2-3 segment advancing to plane 2 and forming PDD5, as shown in Fig. 3 (a). In addition, a stacking fault on plane 2 expands from the lower part of the crystal as indicated by the green arrows in the 3D schematic and UVPL image. Fig 3(b) indicates movement of the Si-core partials, where PDD3 gets elongated with shortening of P2-3 segment and approaches PDD5. As PDD3 reaches the vicinity of PDD5-1 (shown in Fig.3 (b)), PDD3-1 and PDD3-2 can be disrupted. The interaction force of 9.12 GPa between the screw component of partials of PDD3 can be estimated by the force between screw dislocations (Eq.1) [13] since the line direction is almost parallel to Burgers vector:

Where G is the shear modulus, b is the Burgers vector and r is the distance between the dislocation. The glide force acting due to the partial of PDD5 on plane 1 on PDD3 can be calculated by Eq. 2 [14,15]:

Where and are Burgers vector of the two dislocations, is the shortest distance between the dislocations, v is the Poisson's ratio, is the angle between line direction and , and can be described as , where a is arbitrary length along dislocation with . In this case, partial of PDD5-1 will be dislocation with , as shown in Fig. 4(a). The maximum force that PDD5-1 acts on PDD3-1 is 3.6 GPa and 1.8 GPa on PDD3-2 along the opposite direction since they are opposite sign
pairs, as shown in Fig. 4(b), which is equivalent to PPD3-1 subjected to total force of 5.4 GPa . Next, resolved force from force between screw dislocations is calculated. As shown in Fig. 4(c), the resolved force can be calculated by the following equation modified from Eq.1:

where is the angle between force of screw component ( ) and resolved force ( ), and d is the distance between the dipole along [0001] direction. Based on Eq.3, the maximum resolved force on PDD3-1 is around 4.4 GPa , which is smaller than the 5.4 GPa force acting from PDD5-1 on PDD31. Therefore, the dipole is broken up, and dislocation then migrates to the position having lowest Peierls barrier, where line direction of dislocation is parallel to . Fig. 3(c) shows the 3D schematic after PDD3 has been decomposed, where PDD3-1 will move to the right and PDD3-2 will move to the left, and as PDD3-2 expand, it will interact with TMD2, where the left side of the fault will stay on plane 3 and right side will move to plane 4, rearranging the PDD5-1 and partial on plane 4 to form PDD6. As P5 advances to the right, PDD7 is formed with the partial on plane 2 and 3. Then P6 propagates and interacts with TMD1, where the left side will stay on plane 3. The right side of P6 (P6-2 in Fig. 3(d)) will attract PDD 4-2 to form PDD8, since PDD4-2 will subject to equal but opposite sign force from PDD4-1 and P6-2, and the Si-core PDD4-1 tend to propagate due to UVPL excitation and the PDD4-2 tend to form dipole with P6-2 along [11 ] with lower Peierls barrier, leading to rearrangement of dipole and formation of PDD8. In addition, as PDD4-1 and P6-1 advanced, PDD9 will form, as indicated in Fig. 3(d).

Fig. 3. (a) and (b) 3D schematic of propagation of partial dislocations of the SSFs interact with TMD2 and TMD3 forming PDD5, (c) and (d) schematic showing decomposition of PDD3, and the segment decomposed from PDD3-2 interact with TMD3 .

Fig. 3. (a) and (b) 3D schematic of propagation of partial dislocations of the SSFs interact with TMD2 and TMD3 forming PDD5, (c) and (d) schematic showing decomposition of PDD3, and the segment decomposed from PDD3-2 interact with TMD3 .

Fig. 4. (a) Schematic diagram for interaction force of PDD5-1 acting on PDD3-1. (b) Force on PDD3-1 and PDD3-2 subjected by PDD5-1. (c) Force analysis while PDD3-1 and PDD3-2 separate.

Fig. 4. (a) Schematic diagram for interaction force of PDD5-1 acting on PDD3-1. (b) Force on PDD3-1 and PDD3-2 subjected by PDD5-1. (c) Force analysis while PDD3-1 and PDD3-2 separate.

The SSF originating from lower part of the crystal expands to the vicinity of the partial separated from PDD3-1 (Fig. 5(a)), then the opposite sign partials get annihilated as highlighted in yellow solid line box and the two SSFs merge. Then, P7 from the merged SSF approaches PDD4-2, changing the line direction of PDD7-1, and the line direction of PDD7-2 will follow due to the attraction force between the dipole, as shown in Fig. 5(b). When P7 encounters PDD4-2, part of the partials will get annihilated (yellow dashed box in Fig. 5(b)), then the two faults will merge together and the dislocation segments will join together, as shown in Fig. 5(c). After that, P 8 will advance to the right as P7 shortens in length (Fig. 5(d), until it reaches the surface as indicated in the UVPL image of Fig. 5(d).

Fig. 5. (a) and (b) two annihilation processes of opposite sign partials on plane 2, leading to three different SSFs on plane 2 merging into one. (c) after annihilation processes, PDD7-1 join PDD4-2 while P8 keeps migrating to the right as P7 shortens. (d) the migration of P8 stops at the surface, while PDD6 to PDD9 remain in the epilayer.

Fig. 5. (a) and (b) two annihilation processes of opposite sign partials on plane 2, leading to three different SSFs on plane 2 merging into one. (c) after annihilation processes, PDD7-1 join PDD4-2 while P8 keeps migrating to the right as P7 shortens. (d) the migration of P8 stops at the surface, while PDD6 to PDD9 remain in the epilayer.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.375.35.pdf

The formation of a dislocation loop with associated interfacial dislocation during thick epilayer growth has been observed. Different portions of the loop can migrate to different basal planes via interaction with TMDs during epilayer growth. Upon UV excitation, different portions of the loop expand and form SSFs. Complex mechanisms for interaction between SSFs and TMDs upon UV excitation have been analyzed and explained with 3D schematic diagrams. When SSF interacts with TMD, the fault will be separated in adjacent basal planes leading to formation of partial dislocation dipoles. Dipole-dipole interactions, including rearrangement, separation and annihilation, are observed and reported. The interactions and expansion of SSFs can severely degrade the device performance and reliability of high power SiC devices by increasing reverse leakage current and onstate resistance, which could eventually lead to device failure.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.375.35.pdf

The information, data, or work presented herein was funded in part by the Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy, under Award Number DEAR0001028. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.35.pdf

A.A. Lebedev and V.E. Chelnokov, Semiconductors 33, 999-1001 (1999).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 43-47

doi: 10.4028/p-4RM2er

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-11

Revised:
2025-02-17

Accepted:
2025-02-20

Online:
2025-09-05

Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

The original version of this paper is available on https://www.scientific.net/SSP.375.43.pdf

Chiara Nania , Domenica Raciti , Cristiano Calabretta , Fabiana Vento , Ruggero Anzalone , Enzo Fontana and Andrea Severino

STMicroelectronics, Stradale Primosole, 50, Catania 95100, Italy

chiara.nania@st.com, domenica.raciti@st.com, cristiano.calabretta1@st.com, fabiana.vento@st.com, ruggero.anzalone@st.com, enzo.fontana@st.com,

Keywords: 4 H -SiC, 200 mm , LP-CVD, defectivity, BPD, polytype, EWS.

Abstract

The increasing demand for WBG materials like SiC has led STMicroelectronics to expand wafer diameter from 150 mm to 200 mm , enhancing production yield and reducing costs. However, this expansion poses challenges in preserving crystalline quality. This investigation examines the impact of defects on 200 mm wafers, focusing on Total Usable Area (TUA) and electrical performance, particularly in wafers with polytype inclusions and high basal plane dislocation (BPD) density. Although the results for non-standard wafers show a significant reduction in TUA and an increase in electrical failures, the overall distribution of functional and non-functional devices remains stable, indicating process consistency.

Introduction.

The original version of this paper is available on https://www.scientific.net/SSP.375.43.pdf

The demand for reliable Wide Band Gap (WBG) materials like SiC and GaN for power devices and high-voltage products has been steadily growing over recent decades, driven by their extensive use in various applications [1,2]. SiC and GaN offer an optimal balance between their theoretical advantages - such as high voltage blocking capability, high-temperature operation, and high switching frequencies - and the commercial availability of the base materials (wafers) and the maturity of their manufacturing processes . These materials have significant potential to miniaturize power electronic converters, enabling operation at higher frequencies and temperatures with far greater power conversion efficiency compared to current silicon power devices [5]. The market for SiC power devices has expanded so rapidly in recent years that many suppliers are struggling to keep up with demand, as production has traditionally relied on 150 mm diameter wafers. In response, STMicroelectronics has initiated production of SiC wafers with a 200 mm diameter. The main challenge in scaling up from 150 mm to 200 mm lies in increasing the size of the bulk crystals while maintaining productivity and crystal quality. A 50 mm increase in wafer diameter results in a increase in area, thereby boosting the number of devices per wafer [6-8]. This shift enhances the productivity of front-end manufacturing lines, which in turn lowers the cost of the final devices. The resulting increase in production volume and cost reduction is expected to drive the widespread adoption of SiC-based power devices in the automotive industry, which is rapidly advancing towards electrification [9].

Experiment Set-Up

The original version of this paper is available on https://www.scientific.net/SSP.375.43.pdf

In the view of seed enlargement (from current 150 mm to 200 mm substrates), twenty-four 200 mm SiC substrates were grown with the same process in the same reactor in order to evaluate, mainly in wafers having % polytype ( or 15R-SiC mainly) and BPD values higher than commercial specifications, the impact of defect on Total Usable Area (TUA) and electrical tests.
For this purpose, the substrates were selected as follows: 12 standard wafers, 6 wafers 4 H SiC with polytype inclusion and 6 wafers with BPDs density (in 2 of them there are also polytype inclusion).

Growth. The growth of n-type epitaxial layer on Si-face substrates (0001) at off axis was performed on low-pressure, single-wafer, hot-wall chemical vapor deposition (LPCVD) reactor. The homo-epitaxial growth process is carried out at temperatures of about and involves the use of silane ( ), propane ( ), and ethylene ( ) as silicon and carbon precursors, respectively. Nitrogen ( ) was added as n-type dopant, and high purity industrial grade hydrogen ( ) was used as carrier gas as well as a reducing agent for epitaxial layer growth. The presence of HCl , due to the chemistry system, is required to prevent the formation of Si droplets ( Si C bonds stronger than ones). The epilayer specifications, required for medium/high voltage device technologies, are for thickness and for doping.
The uniformity of thickness and doping concentration distribution in the epitaxial layers, expressed as [maximum value - minimum value]/mean [%], was assessed using Fourier Transform Infrared (FT-IR) spectrometry and Mercury-Probe Capacitance Voltage (Hg-CV), respectively. Bow and warp measurements were conducted using FRT; these parameters after epi are reduced with a typical symmetrical bowl shape reported on all wafers (data not shown). No impact was observed on the epitaxial process concerning the out of spec in % polytype and density of BPDs.

Characterization and EWS analysis. The defectivity characterization was conducted using Candela and Altair tools, both from KLA. The Candela tool uses highly sensitive optical technology able to simultaneously measure scattering intensity at various angles of incidence, topographic variations, surface reflectivity and phase shift, and photoluminescence for the detection and classification of a wide range of defects, such as crystallographic defects. A simultaneous Brightfield and Dark-field optical path to capture a variety of defects in the sub-micron to 5 -micron range is used in the Altair optical microscope.
Defective Die Percentage (DDP) and Total Usable Area (TUA), critical parameters commonly used to evaluate the yield and manufacturing efficiency of semiconductor devices, were analyzed. Using a grid with dimensions similar to the device, the impact of defects on TUA (calculated as DDP by Altair) post epitaxial growth can be quantified. As illustrated in Fig. 1, wafers with a polytype inclusion and BPDs values exceeding commercial specifications exhibit a TUA reduction of approximately for polytype (PT) and for high-BPD (hBPD), respectively.

Fig. 1. On the right is the table with data on the characteristics (% of polytype on the Si face and BPD density) of the substrate and epilayer (thickness and average doping, denoted as THK and DOP respectively) of a sample consisting of twelve wafers. Wafers with polytypical inclusion are displayed in green, standard wafers in yellow, and wafers with high BPDs density in light blue. On the left, the Total Usable Area (TUA) of the 12 wafers is shown.

Fig. 1. On the right is the table with data on the characteristics (% of polytype on the Si face and BPD density) of the substrate and epilayer (thickness and average doping, denoted as THK and DOP respectively) of a sample consisting of twelve wafers. Wafers with polytypical inclusion are displayed in green, standard wafers in yellow, and wafers with high BPDs density in light blue. On the left, the Total Usable Area (TUA) of the 12 wafers is shown.

An example of a wafer with polytype inclusion is shown in Fig. 2. Both the Candela and Altair maps reveal an increased concentration of defects (such as carrots, topo defects, and surface triangles) in the region close to polytype. In this area there is a marked correlation between the defect maps and the EWS (Electrical Wafer Sorting) map, with most defects causing catastrophic failures.

Fig. 2. Composite characterization of an out-of-spec wafer for the polytype percentage. On the left, the Candela map displays various types of defects (crystallographic and morphological) on the wafer surface, categorized by color. The Altair map in the center provides a morphological defect view, with an enlarged region highlighting the EWS map, which illustrates device failures (catastrophic or due to leakage under high voltage) caused by defects, depicted in pink, in the polytype region. On the right, optical images illustrate the most common defects as physical manifestations of these failures.

Fig. 2. Composite characterization of an out-of-spec wafer for the polytype percentage. On the left, the Candela map displays various types of defects (crystallographic and morphological) on the wafer surface, categorized by color. The Altair map in the center provides a morphological defect view, with an enlarged region highlighting the EWS map, which illustrates device failures (catastrophic or due to leakage under high voltage) caused by defects, depicted in pink, in the polytype region. On the right, optical images illustrate the most common defects as physical manifestations of these failures.

The Electrical Wafer Sorting (EWS) phase is critical in the semiconductor manufacturing process, serving to rigorously test all devices with the primary goal of identifying non-functional dies, thereby preventing their integration into final packages. This phase involves a sequence of electrical measurements that classify each device as either "good" or failed. By analyzing the data obtained from the testing of a Power MOSFET of 650 V with area of , the origin of the failures can be traced, identifying both the specific phase of the process and the tools involved. Fig. 3 illustrates the EWS test bin results on a limited sample of wafers. Each graph represents the occurrence of failure or non-failure normalized against the mean value of that event on the standard sample of wafers analyzed. The graphs display the portion of devices classified as "good", i.e., having no failures, "catastrophic" fails, where the devices fail immediately during the first measures of test program, and, finally, the "leakages-related" fails that occur during the check of leakage between drain and source at high biases similar to the device's operating voltage (IR@HV). In (a) it is observed that wafers with polytype inclusion show an occurrence of good devices greater than or at least overlapping with standard wafers (good, PT>1) and that wafers with high density of BPDs an occurrence less than 1 . In (b) the occurrence of catastrophic failures in wafers with hBPDs is much higher than in wafers with PT and STDs. This is consistent with the defect maps shown in Fig. 2 in which polytype inclusion is in a well-localized region and therefore predictable at the catastrophic failure level. In contrast, in wafers with a high density of BPDs, failures are spread across the entire wafer and thus not easily predictable; in this sense, an XRT analysis could assist in establishing a correlation between BPDs and failures. A different trend is observed in graph (c) in which the occurrence of leakage failures is overlapping in wafers with hBPDs and STDs, less than 1 instead in wafers with polytype inclusion, emphasizing the role of BPDs and related defects across the epi in the increase of failure events due to high leakage.

EWS test

Fig. 3. The three vertical bar graphs report the results of EWS tests performed on three types of wafers: standard (STD, yellow left-bar of the graph), with high density of BPDs (hBPD, blue centerbar), and with polytype inclusion (PT, green right-bar). Graph (a): occurrence of devices classified as "good," i.e., free of failures. Graph (b): incidence of catastrophic type failures. Graph (c): occurrence of failures due to leakage. Bars represent normalized values against the standard wafer average, with error bars indicating statistical variability.

Summary/Conclusion. The transition from 150 mm to 200 mm SiC substrate has significant challenges, particularly regarding the impact of polytype inclusions and high densities of BPDs (BPDs) on wafer quality and device performance. Our study shows that these defects contribute to a substantial reduction in total usable area (TUA) compared to standard wafers. On the electrical side, while polytype inclusion is a localized and controlled phenomenon, the high density of BPDs has a considerable impact on the incidence of failures, including catastrophic failures and high-voltage losses. Advanced characterization techniques have revealed a clear correlation between defect
concentrations and the device failure location especially in wafers with polytype inclusion. Despite polytype inclusion, therefore, the overall distribution of functional and nonfunctional devices on wafers remained constant, suggesting a level of process stability even when working with materials outside typical commercial specifications. A prediction on the occurrence of failures in wafers with high density of BPDs, however, is currently not possible since they are distributed throughout the wafer. The future goal is to be able to find a clear correlation between BPDs and failures using advanced non-destructive analysis techniques. These results highlight the importance of ongoing efforts to improve crystalline quality and reduce defects in the production of wafers. Achieving these improvements will be critical to maximizing the yield and ensuring the reliability of SiC-based power devices, particularly as demand increases in high-volume industries such as automotive electrification.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.43.pdf

Shenai, K., Dudley, M., & Davis, R.F. (2013). Current Status and Emerging Trends in Wide Bandgap (WBG) Semiconductor Power Switching Devices. ECS Journal of Solid State Science and Technology, 2.

She, X., Huang, A.Q., Lucía, Ó., & Ozpineci, B. (2017). Review of Silicon Carbide Power Devices and Their Applications. IEEE Transactions on Industrial Electronics, 64, 8193-8205.

Anzalone, R., Piluso, N., Salanitri, M., Lorenti, S., Arena, G., & Coffa, S. (2017). Hydrogen Etching Influence on Homo-Epitaxial Layer for High Power Device. In Materials Science Forum.

Wellmann, P.J. (2018). Review of SiC crystal growth technology. Semiconductor Science and Technology, 33.

R. Anzalone, D. Raciti, M. Arena, C. Calabretta, N. Piluso, A. Severino, Solid State Phenomena (2024) 362, 41-45.

Raciti, D., Anzalone, R., Isacson, M., Piluso, N., & Severino, A. (2024). Buffer Layer Dependence of Defectivity in Homoepitaxy. Defect and Diffusion Forum.

Saddow, S.E., & Agarwal, A.K. (2004). Advances in silicon carbide processing and applications.

Kimoto, Tsunenobu and James A. Cooper (2014). Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications (2014).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 49-53

doi: 10.4028/p-Bwhh0v

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Accepted:
2025-03-10

Online:
2025-09-05

Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

The original version of this paper is available on https://www.scientific.net/SSP.375.49.pdf

Suman Das , Daniel J. Lichtenwalner , Shane R. Stein , and Sei-Hyung Ryu

Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

suman.das@wolfspeed.com, daniel.lichtenwalner@wolfspeed.com, shane.stein@wolfspeed.com, sei-hyung.ryu@wolfspeed.com

Keywords: 4H silicon carbide (SiC), Hall measurement, mobility, interface traps, gate stress.

Abstract

Gated Hall measurements are conducted to calculate interface trap density of a nitric oxide (NO) annealed 4 H silicon carbide MOSFET. The free carriers are measured using split CV method. Application of body bias confirms that the total trap quantity does not change at the interface when changing the electric field through body bias for a given device. The effect of positive gate stress on Hall mobility is also studied. A stress voltage of +36 V is applied for different stress times , and 300 sec . With the increased stress time, the Hall mobility value drops at low gate voltages, while at higher gate voltages they merge. Higher stress creates more interface traps that in turn increase Coulomb scattering which lowers mobility at low gate voltages. The effect of gate stress on Hall mobility provides accurate insight of the channel behavior due to interface traps at interface.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.49.pdf

The performance of silicon carbide MOSFETs is limited by a high density of traps at the oxide semiconductor interface giving rise to low channel mobility for the MOSFETs. Several different gate oxide processes were employed in the past to reduce oxide semiconductor interface traps and to improve channel mobility. Post oxidation nitric oxide annealing [1,2] became the most extensively used industrial annealing treatment for power device fabrication. Some other approaches to change the interface that have been studied are introducing high k dielectrics , high temperature nitrogen annealing [5,6], or buried channel and/or counter doped channel MOSFETs [7,8].
To fully understand device characteristics and improve channel mobility, it is crucial to quantify these traps. Depending on the energetic location of these traps there are several methods [9] that can correctly quantify the traps, although most techniques only access traps at certain regions of the bandgap. One of the most effective methods for computing the total number of interface traps is gated Hall measurements [10-12], which give total trap quantities near the band edges, which directly affect carrier mobility. Hall mobility gives the actual value of carrier mobility which is directly extracted from the free carriers present in the channel. Thus, it gives an idea of how much the field effect mobility could be improved if most/all traps could be passivated, thus how much additional improvement is possible in a planar channel device if trap density could be reduced. Due to the direct measurement of free carriers and mobility in a Hall mobility measurement, it can also be used to characterize interface degradation effects observed when threshold voltage shift is detected after gate stress [13,14].
In this work, gated Hall measurements are performed to quantify interface traps on the upper half of the bandgap. Furthermore, positive gate stress effects have been studied using lateral MOSFET IdV gs evaluation, and gated Hall measurements. Gate stress effects on the field effect mobility has been studied before; however as employed here, the effect of gate stress on real (Hall) mobility can produce more insight.

Experimental Methods

The original version of this paper is available on https://www.scientific.net/SSP.375.49.pdf

Figure 1 shows a MOS Hall bar top-view. The Hall bar is fabricated on a Si -face off-axis SiC (0001) wafer, on a implanted Al-doped p-well, activated around . This is a long channel (Lch , Wch lateral MOSFET with Hall voltage contacts, fabricated with a thermal oxide passivated with a NO anneal. Al was used as contact metal. The Hall bars are wire bonded on a larger sample holder and Hall measurements were performed at in a Lake Shore system with a permanent magnet of 1 Tesla.

Results

The original version of this paper is available on https://www.scientific.net/SSP.375.49.pdf

Figure 2 shows the measured MOS Hall mobility ( ) and field effect mobility ( ) versus gate voltage at room temperature. The lower value of comes due to the high density of interface traps. gives the actual value of the carrier channel mobility, directly measured. The value of the interface trap concentration is calculated in Fig. 3 from the measured Hall data. First, the total carrier concentration ( ) is extracted from a split CV measurement. The free carrier concentration ( ) is obtained from the gated Hall measurements and then subtracted from to extract the total trapped charge density ( ). As the gate voltage increases, increases rapidly due to faster occupation of interface traps, while at high gate voltage the trapped charge density increases at a slower rate but doesn't saturate. These trap levels are in the upper half of the band gap and close to the conduction band edge, the density of which increases exponentially. Hall carrier concentration reveals that about half the channel charge is trapped and not contributing to channel current. Figure 4 shows the Hall and field effect mobilities at different body bias. The values of ntrap are extracted from these measurements as shown in Fig. 5. When the trapped carrier concentrations are plotted as a function of the gate overdrive

Fig. 1. Schematic diagram of Hall bar.

Fig. 1. Schematic diagram of Hall bar.

Fig. 2. Hall and Field effect mobility versus gate voltage for fabricated device.

Fig. 2. Hall and Field effect mobility versus gate voltage for fabricated device.

Fig. 3. Carrier concentration versus gate overdrive voltage showing total, free and trapped carriers.

Fig. 3. Carrier concentration versus gate overdrive voltage showing total, free and trapped carriers.

Fig. 5. Carrier concentration versus gate overdrive voltage at different body bias showing no change in trapped carriers due to different body bias

Fig. 5. Carrier concentration versus gate overdrive voltage at different body bias showing no change in trapped carriers due to different body bias

Fig. 4. Hall and field effect mobility versus gate bias at different body bias.

Fig. 4. Hall and field effect mobility versus gate bias at different body bias.

Fig. 6. Hall mobility versus gate overdrive voltage for a gate stress of +36 V for different times

Fig. 6. Hall mobility versus gate overdrive voltage for a gate stress of +36 V for different times

voltage , all the curves merge onto each other. This proves that body bias does not change the interface trap densities, only the value of transverse electric field changes, thus changing the mobilities.

Next, Hall measurements are used to perform a channel degradation characterization. The gate is stressed at +36 V for different times ( , and 300 sec ) and the Hall measurements are performed in between the stresses. Figure 6 shows Hall mobilities as a function of gate overdrive voltage after each stress condition. At low voltage the mobility reduces due to the stress; however, at high gate voltage they overlap. In addition, trapped charge densities are calculated after each gate stress condition. Figure 7 shows with increasing stress time, the free carrier density drops, indicating an increase of trapped charge carriers at the interface. Figures 6 and 7 are summarized in Fig. 8 which shows the changes of Nit and mobility (extracted at ) with stress time. Mobility decreases, and the value of Nit increases as the stress time increases, proving a direct correlation between and mobility.

It can be concluded that, at zero stress time, half of the carriers are trapped and therefore do not take part in conduction resulting in higher channel resistance and channel mobility. As the stress time increases, more interface states are generated which captures more free carriers that in turn lowers the mobility at low gate voltages. However, Fig. 6 shows that at high gate voltage the mobility curves tend to merge with each other. The change in trap density increases Coulomb scattering at the interface and therefore lowers the mobility at low gate voltages. However, at high gate voltage mobility is governed by phonon scattering and they remain unchanged.

Fig. 7. Carrier concentration versus gate overdrive voltage showing that with the increase of stress time trapped carriers increasing and free carriers are decreasing.

Fig. 7. Carrier concentration versus gate overdrive voltage showing that with the increase of stress time trapped carriers increasing and free carriers are decreasing.

Fig. 8. Summary of calculated Nit and extracted mobility versus stress time shows direct correlation between increased trap levels and decreasing mobility.

Fig. 8. Summary of calculated Nit and extracted mobility versus stress time shows direct correlation between increased trap levels and decreasing mobility.

Conclusion

The original version of this paper is available on https://www.scientific.net/SSP.375.49.pdf

In summary, gated Hall measurements show the effect of traps on carrier mobility and allow the calculation of trap concentration at the interface. The effect of gate stress on channel Hall mobility is observed here. An increase in stress time is seen to generate more traps at the interface. At low voltages mobilities are limited by Coulomb scattering and therefore shows a reduced value at increased stress. Whereas, at high gate bias mobilities are limited by phonon scattering for which the mobilities tend to merge at different stress timing. Overall, gated Hall measurements clearly reveal the free and trapped carrier densities and carrier mobility and is a powerful way to analyze channel degradation under stress, showing the effects on and mobility.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.49.pdf

G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, Robert A. Weller, S. T. Pantelides, Leonard C. Feldman, O. W. Holland, M. K. Das, and John W. Palmour, "Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide," in IEEE Electron Device Letters, vol. 22, no. 4, pp. 176-178, April (2001).

J. Rozen, A. C. Ahyi, Z. Xingguang, J. R. Williams, and L. C. Feldman, IEEE Trans. Electron Devices 58(11), 3808-3811 (2011).

D. J. Lichtenwalner, L. Cheng, S. Dhar, A. Agarwal, and J. W. Palmour, Appl. Phys. Lett. 105, 182107 (2014).

X. Yang, B. Lee, and V. Misra, "Effect of post deposition annealing for high mobility 4H-SiC MOSFET utilizing lanthanum silicate and atomic layer deposited SiO2," in the 2nd IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2014.

K. Tachiki and T. Kimoto, "Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature Annealing," in IEEE Transactions on Electron Devices, vol. 68, no. 2, pp. 638-644, (2021).

S. Das, H. Gu, L. Wang, A. Ahyi, L. C. Feldman, E. Garfunkel, M. A. Kuroda, S. Dhar; Trap passivation of 4H-SiC/SiO2 interfaces by nitrogen annealing. J. Appl. Phys. 7 June 2023; 133 (21): 215701.

M. Okamoto, Y. Makifuchi, M. Iijima, Y. Sakai, N. Iwamuro, H. Kimura, K. Fukuda, and H. Okumura, Appl. Phys. Express 5(4), 041302 (2012).

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M. E. Bathen, C. T.-K. Lew, J. Woerle,1 C. Dorfer, U. Grossner, S. Castelletto, and B. C. Johnson, Characterization methods for defects and devices in silicon carbide, J. Appl. Phys. 131, 140903 (2022).

M. Noguchi, T. Watanabe, H. Watanabe, and N. Miura., Comparative Study of Hall Effect Mobility in Inversion Layer of MOSFETs with Nitrided and Phosphorus-doped gate Oxides, IEEE Trans. Elec. Dev., 68, 12, (2021).

S. Das, Y. Zheng, A Ahyi, M. A. Kuroda, and S. Dhar, Study of carrier mobilities in 4H-SiC MOSFETS using Hall analysis, MDPI Materials, 15, 19 (2022).

S. Das, T. Isaacs-Smith, A Ahyi, MA Kuroda, S Dhar, High temperature characteristics of nitric oxide annealed p-channel 4H-SiC metal oxide semiconductor field effect transistors, JAP 130, 22 (2021).

J. Berens; T. Aichinger, A straightforward electrical method to determine screening capability of GOX extrinsics in arbitrary, commercially available SiC MOSFETs, IEEE IRPS, pp. 1-5 (2021).

A. K. Biswas, D. J. Lichtenwalner, S. Das, C. Isaacson, S. Ganguly, D. A. Gajewski, Effects of High Gate Voltage Stress on Threshold Voltage Stability in Planar and Trench SiC Power MOSFETs, Solid State Phenomena, 1662-9779, 358 (2023).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 55-61

doi: 10.4028/p-g8Pe23

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-16

Accepted:
2025-05-05

Online:
2025-09-05

Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

The original version of this paper is available on https://www.scientific.net/SSP.375.55.pdf

Yasuyuki Igarashi , Kazumi Takano , Yohsuke Matsushita and Takuya Morita

ITES Co., Ltd., 1-60 Kuribayashi, Otsu, Shiga 520-2151, Japan

yiga@ites.co.jp, kazumi_takano@ites.co.jp, yohsuke_matsushita@ites.co.jp,

dtakuya_morita@ites.co.jp

Keywords: basal plane dislocation, single Shockley stacking fault, surface recombination velocity, photoluminescence, UV irradiation, bipolar degradation, screening, recombination-enhanced dislocation glide.

Abstract

We have proposed an E-V-C (Expansion-Visualization-Contraction) method by using UV irradiation, for screening potential defects which causes reliability issue called bipolar degradation in devices. This method is based on the property that the REDG (recombination-enhanced dislocation glide) mechanism causing the bipolar degradation can be reproduced by UV irradiation. However, in order to apply this method as a screening, accurate quantification of the correlation between current density in forward bias and UV irradiance is required. This article describes how to set UV irradiation conditions (irradiance and irradiation time) to simulate forward biased current conditions.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.55.pdf

As part of efforts to curb emissions to prevent global warming, the expansion of renewable energy sources such as solar and wind power generation, as well as the electrification of automobiles such as HEVs and EVs, is being promoted at a rapid pace on a global scale. Power semiconductors, which are the basic elements that make up these technologies, are the driving force behind their realization, and currently more than of their base materials are made of silicon . However, Si is beginning to show its limitation of device performance coming from the limitation of the material constant, and new materials such as SiC (silicon carbide), GaN (gallium nitride), and (gallium oxide), which excel in high breakdown voltage, low loss, high-frequency operation, and high temperature operation, are drawing attention. Among these, SiC is currently attracting the most attention for its functionality, reliability, and ease of mass production, with the aim of expanding its mass production. However, the devices currently widely used in products have been found to have a reliability issue called bipolar degradation. This degradation is caused by the nucleation and expansion of single Shockley stacking faults (1SSFs) derived from line defects called basal plane dislocations (BPDs) in the epilayer or near the epilayer/substrate interface. The 1SSF expansion is explained by the REDG mechanism in which excess minority carriers injected into the BPD region are expanded by the recombination energy of electrons and holes. Various process improvements have been made to convert BPDs to benign dislocation TEDs (threading edge dislocations) at the epilayer/substrate interface, which does not expand. However, it is known that at high current densities, expansion occurs from the BPD-to-TED conversion point, and the issue has not yet been fully resolved.

So far, in some device manufacturers so-called "burn-in" screening is performed, in which the bipolar degradation is checked, chip by chip, by applying accelerated current stress for a certain period. This is a very time-consuming process which raises a total cost of production. In order to replace the time-consuming "burn-in" screening, we have proposed the E-V-C method as a means of screening out TED-converted BPDs [1]. The E-V-C method is a technique to visualize and screen TED-converted BPDs by utilizing UV irradiation and PL observation. In order to make the use of UV irradiation to be useful and practical as a screening method, it is required that the UV irradiation
conditions must match the specifications of each product, specifically, the absolute maximum current rating of the product. This is because, if UV irradiance is unnecessarily intense, even devices that would not show any degradation within the rated current in normal usage will be screened out (overkill). Therefore, it is essential to derive an accurate quantitative correlation between forward bias condition and UV irradiation condition to avoid overkill situation. It is relatively easy to experimentally derive the correlation if it is only for one specific wafer. The authors' team has reported the quantitative derivation of the correlation for PiN diodes fabricated on a single 4 " wafer [2]. However, in order to make the correlation to be more general and versatile, the correlation should be formulated physical theory based. In this article, the correlation between forward bias and UV irradiation is derived in terms of intensity (current density and irradiance) and time (current flowing time and irradiation time) based on physical model.

UV Irradiance Determination (Equal Hole Density at Drift/Buffer Interface)

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It has been reported that the expansion of a TED-converted BPD depends on whether the hole density near the conversion point exceeds a certain threshold or not [3]. That is, the key indicator bridging forward bias and UV irradiation is the hole density near the BPD-to-TED conversion point. Taking PiN diodes as an example, since most BPDs are converted near the drift buffer interface, the UV irradiation conditions should be so determined that the hole density at the interface becomes the same between UV irradiation and forward bias. When the current flow is constant, the hole density does not change over time, meaning in a steady state. The spatial distribution of hole density inside the i-layer during high current injection is given by Eq. 1 [4].

where : distance from drift interface, J: current density
: recombination current density ratio in drift layer
: carrier lifetime in drift layer, : drift layer thickness
: ambipolar diffusion length, : elementary charge
: shape factor
On the other hand, in UV irradiation, a nanosecond pulsed laser is used, and a large number of electron-hole pairs are generated along the trajectory of the UV light immediately after UV irradiation, and the hole density then decreases by diffusion and recombination, meaning that the hole density is a function of space and time, . At time zero (immediately after the irradiation), the depth profile of hole density is determined by the number of photons injected by UV light and the optical properties of the irradiated object, such as reflectivity and absorption coefficient, as in Eq. 2. As a general solution, the hole density generated by a single pulse is expressed as Eq. 3 by solving the diffusion equation [ 4, 5] and it appears repeatedly according to the frequency of the UV pulse.

where is an absorption coefficient of excitation source (laser light) and

where are spatial functions with parameters of drift layer width, surface/interface recombination velocities and ambipolar diffusion coefficient.
are time dependent terms with parameters of ambipolar diffusion coefficient and lifetime in drift layer.
are constants including initial hole density at and absorption coefficient of excitation source (laser light).

Therefore, the UV irradiance should be set so that the peak value of hole density induced by UV irradiation ( ) is equal to the hole density at the interface during forward biased.

The Eq. 4 was compared with the results of the correlation experiments performed by the authors on the PiN diodes fabricated on a 4 " particular wafer [2]. The sample was a commercially available ntype wafer with a off-cut angle. The structure of the PiN diode was formed by doping aluminum ( ) on the Si face of the epi wafer (buffer layer ( ), drift layer ( )) with a nickel electrode on the entire backside of the wafer. An aluminum electrode array of comb pattern ( 2 mm square chip) was formed in half of the wafer for accelerated current stress, and the other half has no electrode pattern for UV irradiation stress, as shown in Fig. 1. In the UV irradiation, the excitation source was 355 nm Nd: YAG-3HG (Yttrium Aluminum Garnet-third Harmonic Generation) pulsed laser with 10 ns pulse width per cycle (duty ) with beam diameter of .

Fig.1. Schematic diagram of the PiN diode and photos of aluminum electrode pattern on SiC Epi wafer

Fig.1. Schematic diagram of the PiN diode and photos of aluminum electrode pattern on SiC Epi wafer

In the experiment, the expansion velocity (glide velocity of the core partial dislocation at the leading edge of the 1SSF in the direction) was measured for 329 bar shaped defects expanded by forward bias stress test with multiple levels of current density and for 11 bar shaped
defects expanded by UV irradiation stress with multiple levels of irradiance. From the data obtained, the point at which the expansion velocity becomes zero was estimated by regression analysis, and that value was determined as the threshold value at which the expansion occurs, with the results that and were the estimated thresholds in forward bias and in UV irradiation, respectively. Then, the hole densities for both cases were calculated. Although Eq. 1 is an equation for a simple structure for a PiN diode, the sample used in the experiment has a structure with a buffer layer as shown in Fig. 1, and Eq. 1 cannot be used to accurately calculate the hole density. Therefore, a one-dimensional device simulator, AFORS-HET was used in forward bias case, and in UV irradiation case, Eq. 2 was used. The calculated hole densities were:

This means the relationship of

It differs from Eq. 4 and there are two possible reasons why .
(i) It is just an experimental error and .
(ii) The peak of hole density induced by UV pulse irradiation certainly matches the hole density in forward bias case, but the hole density rapidly decays after the pulse irradiated. If the density must remain above the threshold for a certain period of time in order for the core to glide, the peak of the hole density by UV irradiation must be somewhat above the threshold. Therefore, a correction term is needed in Eq. 5.
Since this can only be determined by future research and experimental validation, Eq. 5 with the condition of is employed at this point, instead of Eq. 4 to express the correlation. From the above, for a given current density, the irradiance can be set by replacing the right side of Eq. 5 with the irradiation conditions,

where one photon energy at
laser pulse requency
The results are shown in Fig. 2. The solid line shows the case where the peak hole density by UV radiation coincides with the hole density by forward bias ( ), and the dashed line shows the case where the experimental value ( ) is reflected in Eq. 5. Thus, the irradiance can be set according to the forward bias condition.

Fig.2. Irradiance-current density equivalence curve

Fig.2. Irradiance-current density equivalence curve

Irradiation Time Determination (Equivalent Time Corresponding to Forward Bias)

The original version of this paper is available on https://www.scientific.net/SSP.375.55.pdf

The irradiation time of UV pulsed laser is thought to be shortened by increasing the pulse width and/or increasing the frequency to elicit the same effect of defect expansion, but the pulse width and frequency are optimized in the laser system to obtain stable output and cannot be much changed. This means that UV irradiation time cannot be significantly reduced while maintaining the same peak hole density. Therefore, here is calculated that how long the UV irradiation time would be if it is converted in case of forward bias. In other words, calculate what the ratio of the time (forward biasing time to irradiation time) to reach an equivalent defect expansion (the same length of 1SSF expansion) would be if the current density and UV irradiance are set to meet Eq. 5 in the previous section.

Since the hole density is in a steady state under a constant current flow at forward bias, 1SSF always expands as long as the current density exceeds a certain threshold. In the case of UV irradiation, on the other hand, the hole density decays to a level below the threshold right after the UV pulse irradiation, so 1SSF expands only during it exceeds the threshold. Therefore, the total amount of expansion during in forward bias or in UV irradiation is expressed by (hole density above the threshold) × (period during which the density is above the threshold), i.e. the integral of the hole density exceeding the threshold over time, as shown in Fig. 3 (the shaded area in UV irradiation case). Accordingly, the total amount of expansion in unit time by forward bias and that in unit time by UV irradiation are independently calculated and can be connected via equal amount of expansion as follows.

Fig.3. Duration of 1SSF expansion (shaded area)

Fig.3. Duration of 1SSF expansion (shaded area)

where : UV irradiation time multiplier

:period during which the hole density exceeds the threshold

The original version of this paper is available on https://www.scientific.net/SSP.375.55.pdf

Clearly, the term , which is referred to as UV irradiation time multiplier, is more than unity. This means that to create a condition equivalent to forward bias by UV irradiation, the UV irradiation time can be set to req. times the forward bias time.
From equations (2), (3) and (7),

After the UV pulse is applied, the decay curve of the hole density depends on carrier lifetime and surface recombination velocity of the specimen, which affects the UV irradiation time multiplier req. in Eq.8. The variation of when the surface recombination velocity of the specimen is varied from to is shown in Fig. 4, which indicates that even though the surface recombination velocity is not precisely known, the same amount of expansion can be achieved between forward bias and UV irradiation if the UV irradiation time is set one or two digits longer than forward bias time.

Fig.4. UV irradiation time multiplier: ratio of time required for UV irradiation to time required for forward bias

Fig.4. UV irradiation time multiplier: ratio of time required for UV irradiation to time required for forward bias

Summary

The original version of this paper is available on https://www.scientific.net/SSP.375.55.pdf

In this article were described the setting values of UV irradiation conditions (irradiance and irradiation time) corresponding to forward bias conditions to simulate the bipolar degradation. As for the irradiance, it was so determined that the hole density at the interface is equal to that in forward bias case, but regarding the irradiation time, it was found that one to two digits more time is required to expand 1SSF by the same amount as in forward bias case. Although UV irradiation may seem to be less efficient for defect expansion than forward bias, for the defect screening purpose, it is sufficient if the defects expand to the point where they can be identified as defects. Since the expansion rate (glide velocity of core) at several hundred is reported to be about several hundred microns per minute [2], even if converted to UV irradiation case, it is within the time range that can be adoptable as a screening process and UV irradiation can be effectively used for screening.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.55.pdf

Y. Igarashi, K. Takano, Y. Matsushita, C. Shibata, Defect and Diffusion Forum 425, 75 (2023).

Y. Igarashi, K. Takano, Y. Matsushita, C. Shibata, Defect and Diffusion Forum 434, 23 (2024).

T. Tawara, S. Matsunaga, T. Fujimoto, M. Ryo, M. Miyazato, T. Miyazawa, K. Takenaka, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto, and H. Tsuchida, J. Appl. Phys. 123, 025707 (2018).

A. Herlet, Solid-State Electron. 11, p. 717 (1968).

Y. Ogita, J. Appl. Phys., 79, p. 6954 (1996).

S. Sumie, F. Ojima, K. Yamashita, K. Iba, and H. Hashizume, J. Electrochem. Soc. 152 G99 (2005).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 63-68

doi: 10.4028/p-1N8gYx

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-05

Accepted:
2025-08-05

Online:
2025-09-05

Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

The original version of this paper is available on https://www.scientific.net/SSP.375.63.pdf

Hiroki Niwa , Takanori Tanaka , Kazuya Ishibashi , Hiroyuki Amishiro , Akifumi Imai , Yasuhiro Kagawa , Katsutoshi Sugawara , and Tatsuro Watahiki

Advanced Technology R&D Center, Mitsubishi Electric Corp., Tsukaguchi-Honmachi 8-1-1, Amagasaki, Hyogo, 661-8661, JAPAN

Power Device Works, Mitsubishi Electric Corp., Imajuku-Higashi 1-1-1, Nishi-ku, Fukuoka, 819-0192, JAPAN

Niwa.Hiroki@dp.MitsubishiElectric.co.jp, Tanaka.Takanori@cb.MitsubishiElectric.co.jp, Ishibashi.Kazuya@ak.MitsubishiElectric.co.jp, Amishiro.Hiroyuki@cb.MitsubishiElectric.co.jp, eImai.Akifumi@ys.MitsubishiElectric.co.jp, fKagawa.Yasuhiro@cj.MitsubishiElectric.co.jp, Sugawara.Katsutoshi@ea.MitsubishiElectric.co.jp, Watahiki.Tatsuro@dx.MitsubishiElectric.co.jp

Keywords: Body diode, Bipolar degradation, Leakage current degradation, Micropipe, BPD, Failure analysis, PL imaging

Abstract

In this study, high current stress was applied to the body diode of SiC-MOSFETs, and chips exhibiting leakage current degradation due to the bipolar degradation phenomenon were analyzed to identify the crystal defects responsible for the abnormal leakage current. Failure analysis and defect inspection during the device fabrication process revealed that abnormal leakage occurred at the periphery of extended stacking faults originating from or near the micropipe itself. As these extended stacking faults also increase the forward voltage drop of MOSFETs, these results suggest that micropipe are critical defects in SiC-MOSFETs inducing both forward voltage and leakage current degradation in the bipolar degradation phenomenon.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.375.63.pdf

For decades, the bipolar degradation phenomenon has been a key issue faced by SiC-MOSFETs [1-5]. This phenomenon involves two types of degradation: an increase in the forward voltage drop ( of the MOSFET and of body diode (BD)) and an increase in the leakage current of MOSFETs in blocking mode ( ). Such degradation can cause MOSFET characteristics to deviate from datasheet values during operation, raising reliability concerns. The impact of bipolar degradation is particularly pronounced in high-power applications, where chips have large active areas and/or thick epitaxial layers to handle high currents and voltages. Therefore, careful consideration of this phenomenon is crucial for devices used in these applications.

Screening MOSFETs degraded by high current stress to the BD (BD stress) is the most direct and reliable method for managing this degradation. Consequently, this approach has been applied for many years in the screening process for some of high-voltage SiC-MOSFETs in mass production [6, 7]. However, because this method is relatively time-consuming, various alternative methods have been proposed to control this degradation mode [8-13]. Despite these efforts, fundamental studies on the bipolar degradation phenomenon itself are becoming increasingly important for addressing this issue more competitively. Although numerous studies on degradation have been conducted over the years, research on degradation remains limited [3-5,7], and the defects responsible for this degradation are still unclear. Therefore, to fully understand the bipolar degradation phenomenon in SiC, studies focusing on degradation are essential.

In this study, high current stress was applied to the BD of many 3.3 kV SiC-MOSFETs, and Idsx degraded chips were identified. These degraded MOSFETs were then analyzed in detail, and the crystal defects responsible for this degradation phenomenon were identified.

Experimental

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Figure 1(a) shows the planar-type 3.3 kV SiC-MOSFET fabricated on an -type 4 H -SiC substrate in this study. The size of the MOSFET was approximately . During device fabrication, defect inspection using photoluminescence (PL) was performed after epitaxial growth and activation annealing. Figure 1(b) illustrates the experimental flow of this study. After the device fabrication process, an initial chip test was conducted to select "good" chips for the BD experiment. At this stage, these "good" chips exhibited no abnormal characteristics or signs of degradation. Subsequently, a high current stress of at was applied to the BD of each chip. In the following chip test, chips with increased leakage current compared to the initial test were characterized as "IDSX degraded chips", while those showing only an increase of (without degradation) were characterized as " degraded chips". Furthermore, some of the degraded chips were selected for failure analysis.

In the failure analysis, the points of abnormal leakage in the degraded chips were first identified using photoemission microscopy from the backside of the chip after removing the backside electrode. Following this, the frontside electrodes and gate structures were removed, and PL imaging was performed to analyze the expanded single Shockley stacking fault ( 1 SSF ). The result of photoemission microscopy and PL imaging were then overlaid to identify the crystal defects causing abnormal leakage. In addition, defect inspection results from the device fabrication process were reviewed, and the crystal defects responsible for the degradation were determined.

Fig. 1. (a) Schematic cross-section of the planar-type 3.3 kV SiC-MOSFET investigated in this study. (b) Flow-chart of the experimental procedure. During failure analysis, photoemission microscopy and PL imaging were conducted to identify the crystal defects.

Fig. 1. (a) Schematic cross-section of the planar-type 3.3 kV SiC-MOSFET investigated in this study. (b) Flow-chart of the experimental procedure. During failure analysis, photoemission microscopy and PL imaging were conducted to identify the crystal defects.

Analysis ofDegraded Chips

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BD stress was applied to more than 1,500 chips, and out of the 159 degraded chips, 45 showed degradation. Figure 2 shows the leakage current characteristics of the degraded chips selected for failure analysis. Compared to the passing chip, a clearly abnormal leakage current was observed. Two types of leakage current characteristics were identified: chips with abnormal leakage starting at a relatively low drain voltage ( ) are referred to as Type A (Fig. 2 (a)), while those with leakage starting at a high are categorized as Type B (Fig. 2 (b)).

Fig. 2. Leakage current characteristics of degraded chips. The compliance current in the measurement was set to . (a) Type A: Chips with abnormal leakage starting at low . (b) Type B: Chips with abnormal leakage starting at high .

Fig. 2. Leakage current characteristics of degraded chips. The compliance current in the measurement was set to . (a) Type A: Chips with abnormal leakage starting at low . (b) Type B: Chips with abnormal leakage starting at high .

Type A. Figure 3 shows the PL image and the results of photoemission microscopy for Chip A1, as shown in Fig. 2 (a). In the initial PL image taken during defect inspection (after epitaxial growth), a white dot was detected, identified as a micropipe [12]. After activation annealing, basal plane dislocations (BPDs) propagated from the micropipe, and 1SSFs expanded from the propagated BPDs and micropipe itself (more precisely, from the BPDs surrounding it) after the high current stress. Notably, the strain associated with the micropipe generates a BPD cluster around the micropipe in the epitaxial layer [14]. Overlaying the photoemission and PL image revealed abnormal leakage near the periphery of the expanded 1SSF originating from the BPDs.

Fig. 3. PL images and photoemission microscopy results of Chip A1.

Fig. 3. PL images and photoemission microscopy results of Chip A1.

Figure 4 shows the analysis results for Chip A2 shown in Fig 2 (a). In this chip, BPDs also propagated after activation annealing, and photoemission was observed near the periphery of the expanded 1SSFs originating from these BPDs. Notably, the micropipe itself is in a neighboring chip, not within Chip A2. This indicates that the micropipe does not directly cause degradation; rather, the propagated BPDs are responsible for the degradation in Chip A2. Although failure analysis was not conducted on the neighboring chip containing the micropipe, it was categorized as an Idsxdegraded chip after BD stress. This finding further supports the idea that BPDs propagate from the micropipe, leading to degradation.

Analysis of other Type A chips, as shown in Fig. 2 (a), revealed that abnormal leakage in all such chips occurred similarly at the periphery of the expanded 1SSFs. In each case, the origins of the expanded 1SSFs were BPDs either propagating from the micropipe inside the chip or from a neighboring chip, indicating that these BPDs around the micropipe are the primary cause of the degradation observed in Type A chips.

Fig. 4. PL images and photoemission microscopy results of Chip A2.

Fig. 4. PL images and photoemission microscopy results of Chip A2.

Type B. In Type B, abnormal leakage begins at a high , unlike Type A. Figure 5 shows the analysis results for Chip B1 to determine if this type of degradation is also caused by the BPDs propagating from the micropipe, similar to Type A. The results in Fig. 5 show that 1SSF expanded from a micropipe, as observed in Type A; however, photoemission was detected near the micropipe itself. Unlike Type A, BPDs did not propagate from the micropipe after activation annealing in Chip B1, although BPDs are expected to be present around the micropipe since the 1SSF expanded following BD stress. This suggest that the specific BPDs causing degradation in Type A may remain around the micropipe even after activation annealing, leading to degradation near the micropipe after BD stress. Similar results were observed for other Type B chips, as shown in Fig. 2 (b), where BPDs did not propagate from the micropipe after activation annealing. Thus, degradation in both Types A and B is believed to be caused by similar BPDs around the micropipe.

Fig. 5. PL images and photoemission microscopy results of Chip B1.

Fig. 5. PL images and photoemission microscopy results of Chip B1.

The difference in characteristics can be discussed by the photoemission point: the periphery of 1SSF in Type A and near the micropipe in Type B. In Type A, emission is observed near the periphery of 1SSF, especially at the surface side of the chip. This indicates that the defective area causing degradation is near the surface of the chip, requiring a very low to create a high electric field sufficient to initiate abnormal leakage. In contrast, for Type B, the defective area causing abnormal leakage is likely near the starting point of 1SSF around the micropipe. Since the starting point of 1SSF is deep within the drift layer, a high is needed to achieve a sufficiently strong electric field to induce abnormal leakage at that depth. Thus, although the characteristics of Types A and B are different, the underlying physical mechanisms of the leakage current may be similar, with the observed differences attributed to the varying depths of the defective areas.

Discussion

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Analysis of all chips shown in Fig. 2 revealed that IDSX degradation was associated with BPDs around the micropipe. To estimate the origin of other -degraded chips identified in this study, defect inspection results from the device fabrication process were examined to confirm whether a micropipe was present in each chip. Table 1 shows the number of degraded chips due to BD stress and those containing micropipes. Among the degraded chips, 43 contained micropipes. The two chips without micropipes were similar to Chip A2, where BPDs propagating from a micropipe in a neighboring chip caused degradation. These results suggest BPDs around the micropipe were responsible for degradation in all cases studied, as shown in Figs. 3-5.

Notably, degradation is not caused by all micropipes. Table 1 shows that nearly twice as many degradation. PL analysis of these degraded chips revealed the presence of expanded 1SSFs originating from the micropipe, similar to those in -degraded chips shown in Fig. . In addition, -degraded chips without micropipes were associated with conventional 1SSFs, such as a bar-shaped 1SSFs originating from BPDs in the substrate [15], or triangular-shaped 1SSFs from BPDs that did not convert to threadingedge dislocations (TEDs) during epitaxial growth. This suggest that most BPDs frequently observed in past studies do not induce 1SSFs with abnormal leakage. Instead, a specific structure of "killer" BPDs is likely responsible for IDSX degradation. These "killer" BPD may occur within micropipe or in the half-loop arrays observed in previous studies [4]. Identifying these structures is crucial for better understanding the bipolar degradation phenomenon and enhancing the reliability of SiCMOSFETs. The high probability that such BPDs arise from the presence of a micropipe indicates that micropipes are a major crystal defect responsible for IDSX degradation. Since expanded 1SSFs also cause degradation, micropipes are critical for contributors to both and degradation in the bipolar degradation phenomenon.

Table 1. Result of high current stress testing (BD stress) and the number of degraded chips containing micropipes.

Test Chips [pcs] | After High Current Stress
| IDSX Degradation [pcs] | VDSon Degradation [pcs] | Total [pcs]
>1500 | 45 | 114 | 159

*Degradation due to micropipe in the neighborhood chip

Summary

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To further understand the bipolar degradation phenomenon in SiC , degraded SiC -MOSFETs after BD stress were analyzed in detail. The findings suggested that micropipes was the root cause of all degradation observed in this study. BPDs propagating from the micropipe after activation annealing led to degradation in many chips, and even BPDs from neighboring chips could cause degradation, despite the absence of micropipes in the degraded chips themselves. Given the micropipes can also induce degradation, they must be considered as one of the most critical crystal defects in the bipolar degradation phenomenon.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.63.pdf

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Solid State Phenomena, ISSN: 1662-9779, Vol. 375, pp 69-75

doi: 10.4028/p-XiWp4f

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-03-20

Accepted:
2025-04-03

Online:
2025-09-05

Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

The original version of this paper is available on https://www.scientific.net/SSP.375.69.pdf

Atsushi Shimbori *, Ryota Wada , Nobuhiro Tokoro , Takashi Kuroi , Hiu Yung Wong and Alex Q. Huang

J.J. Pickle Research Center, The University of Texas at Austin, Bldg. #160, 10100 Burnet Rd. Austin, TX 78758, USA

Nissin Ion Equipment Co., LTD., 75 Nishikujo Higashihieijo-cho, Minami-ku, Kyoto, Japan

San Jose State University, One Washington Square, San José, CA 95192, USA

ashimbo@utexas.edu, wada_ryota@nissin.co.jp, kuroi_takashi@nissin.co.jp, ehiuyung.wong@sjsu.edu, faqhuang@utexas.edu

Keywords: SiC PiN Diode, Bipolar Degradation, Proton Implantation, Forward Voltage Drop, TCAD, Basal Plane Dislocation, Stacking Fault, Minority Carrier Lifetime, and Electroluminescence

Abstract

In this paper, a method for suppressing bipolar degradation through proton implantation was investigated. Previous work suggests implantation applied to the full thickness of the epi layer [1], which results in unwanted defects leading to a deterioration in performance. In this work, proton implantation to the buffer layer was successful in reducing the forward-voltage drift of the fabricated SiC PiN diode by at a current density of , when applying room temperature (RT) proton irradiation at a dose of . Irradiation solely to the buffer layer keeps the deterioration of forward current performance to a minimum, while the fabricated SiC PiN diodes are more robust against bipolar degradation at higher current density. In addition, RT proton irradiated PiN diodes show full recovery from their bipolar degraded characteristics within 2.5 h of annealing at under vacuum. This indicates proton irradiation alters the crystal structure for the stacking fault (SF) to "shrink" back with ease to their initial basal plane dislocations (BPD) state.

Introduction

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Long-term reliability of MOSFETs has always been a concern, and one major issue is the increase of its body diode's (forward voltage drop) from bipolar degradation phenomenon. This is caused by the expansion of SFs that originated from BPDs in the SiC substrate. Inserting a buffer layer with a short carrier lifetime is one way to prevent electron-hole recombination from triggering SFs growth [2]. However, at higher current density, the hole concentration can be much higher and reach the n -buffer substrate interface where BPD-TED (threading edge dislocation) conversion points are present (Fig. 1).

Fig. 1. Hole density distribution of the diode and the location of proton irradiation

Fig. 1. Hole density distribution of the diode and the location of proton irradiation

This threshold hole density is estimated to be around , where we start to observe drifts within the 2 h accelerated stress evaluation period. Proton irradiation hinders the recombinationenhanced dislocation glide motion and is implemented for the suppression of SF expansion. In addition, proton implantation through the buffer layer creates a tail of recombination centers, i.e. centers, which are known to be carrier lifetime killers (Fig. 2b). Because of these recombination centers, an even shorter minority carrier lifetime ( ) is achieved, leading to less injected holes reaching the buffer layer/substrate interface (Fig. 6).

Fabrication

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An epitaxial layer, with a thickness of and a nitrogen doping concentration of , was grown by the CVD method with a high growth rate of . BPD density was further decreased by fast epitaxy as well as adding a buffer layer with a thickness of and a doping concentration of . The wafers were irradiated at and RT with 170 keV or 50 keV protons at a dose of and , before and after the epitaxial growth of the buffer layer. The anticipated hydrogen distribution profiles were confirmed through SRIM simulation (Fig. 2a), ensuring maximum peaks occurring at the buffer layer/substrate interface or in a 300 nm depth of the substrate surface. For PiN diode fabrication, the anode region with a concentration of was formed through high temperature Al implantation at , and then an activation anneal was performed at for 30 min . Circular Al -based metal contact stacks ( ) were patterned on the anode region, and Ni-based metal contact stacks were deposited on the back side of substrate for cathode electrode. Post metallization annealing was performed at for 90 sec .

Fig.2. SRIM simulation of the hydrogen implantation profile ((a) Linear plot shows profile of 170 keV with a dose of to the buffer layer and profile of 50 keV with a dose of to the substrate. (b) Log plot shows a long tail of hydrogen ions within the buffer layer from implantation at 170 keV with a dose of )

Fig.2. SRIM simulation of the hydrogen implantation profile ((a) Linear plot shows profile of 170 keV with a dose of to the buffer layer and profile of 50 keV with a dose of to the substrate. (b) Log plot shows a long tail of hydrogen ions within the buffer layer from implantation at 170 keV with a dose of )

Results and Discussion

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For the bias stress, a long 11 V voltage pulse, equivalent to roughly in current density, was injected at a frequency of 3.33 pulses/s for 2 h to observe bipolar degradation. The duty cycle was kept low to prevent thermomechanical failure from elevated junction temperature. While the reference PiN diode without proton implantation showed forward-voltage drift of 1.40 V after 2 h stress, RT proton implantation at a dose of to the buffer layer was successful in reducing the forward-voltage drift of the fabricated SiC PiN diode by at a current density of (Fig.3). Additionally, by comparing the before stress characteristics of reference PiN diode and PiN diode with proton implantation to the buffer layer, it is apparent that irradiation solely to the buffer layer keeps the deterioration of forward current performance to a minimum. On the other hand, proton implantation onto the substrate did not significantly influence the suppression of bipolar degradation, exhibiting comparable levels of decline in forward current performance. Finally, the amount of forward voltage drop shift was expressed in percentage increase from the original value ( ) to compare the performance degradation between different irradiation conditions within the 2 h accelerated stress evaluation period. Figure 4 a shows an increase in which was observed at current density of , while Figure 4b shows an increase in observed at current density of . As shown in Fig. 4, when the proton dose increases

Fig. 3. Bipolar degradation comparison of (a) reference PiN diode and (b) PiN diode with proton implant to the buffer layer (RT, dose of )

Fig. 3. Bipolar degradation comparison of (a) reference PiN diode and (b) PiN diode with proton implant to the buffer layer (RT, dose of )

, it becomes more difficult for the partial dislocations to move, which results in less drifts. It is also worth mentioning that room temperature implant has more effect on suppressing bipolar degradation over heated implant, indicating the additional damage created introduces an increased number of point defects such as proton impurities, vacancies, and interstitials which all play a significant role in hindering the dislocation glide motion. The forward voltage drop shift does not show an immediate rise, but it involves an initial activation phase up to 90 min of stress time. This activation time is dependent on the stress current density. In other words, the higher the value, the faster the bipolar degradation occurs with less activation time [3]. This suggests that there exists a specific threshold for hole density, as well as a total cumulative energy requirement from the electron-hole recombination process that must be met for bipolar degradation to commence. Electroluminescence (EL) images were additionally obtained under identical stress to a mesa-isolated PiN diode without proton implantation capturing an expansion of dark regions originating from the glide of stacking faults (Fig. 5).

Fig. 4. Plots of stress time vs forward voltage drop shift in percentage, showing forward biased performance degradation (a) , (b)

Fig. 4. Plots of stress time vs forward voltage drop shift in percentage, showing forward biased performance degradation (a) , (b)

Fig. 5. Time evolution of electroluminescence microscopy images under bias stress, capturing expansion of stacking faults

Fig. 5. Time evolution of electroluminescence microscopy images under bias stress, capturing expansion of stacking faults

Simulation and Numerical Analysis

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The carrier density distribution of the designed PiN diode was calculated at different current densities through TCAD simulation to estimate the hole concentration present at the buffer layer/substrate interface when bipolar degradation starts to occur. The simulation model was set having a anode region with a depth of and a peak hole density of , a drift layer in the thickness of and doping concentration of , and a buffer layer with a thickness of and a doping concentration of . Carrier density distributions were plotted with two different current density conditions and , just below and above the trigger current density when bipolar degradation starts to occur. The estimated threshold hole density is calculated to be around , where we start to observe drifts within the 2 h accelerated stress evaluation period [4]. Furthermore, it is assumed that the carrier lifetime reduction was caused by the introduction of centers through the hydrogen implantation tail in the buffer layer. From referencing past publications on carrier lifetime dependence on proton dose, the estimated carrier lifetime is less than of the original value ( ), in the irradiated buffer layer with the proton dose of [5]. The simulation indicates this reduction of carrier lifetime may also play a role in suppressing SF expansion, as enhanced recombination in the buffer layer further reduces the holes from reaching the buffer layer/substrate interface [6].

Fig. 6. Carrier density distribution of the designed PiN diode with thick epi layer with doping concentration of and thick buffer layer with doping concentration of

Fig. 6. Carrier density distribution of the designed PiN diode with thick epi layer with doping concentration of and thick buffer layer with doping concentration of

Fig. 7. Forward characteristics of the fabricated PiN diodes before and after 2.5 h of stressing at pulse current and recovery behavior observed through annealing at under vacuum

Fig. 7. Forward characteristics of the fabricated PiN diodes before and after 2.5 h of stressing at pulse current and recovery behavior observed through annealing at under vacuum

Reversal of Forward-Voltage Drift

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Reversal of the forward voltage drifts has been reported in the past by ways of low temperature annealing [7],[8], and, through the following experiment, the effects of proton implantation in the recovery process have been investigated. Both the reference PiN diode and proton implanted diode were stressed in a similar manner, applying voltage pulse, equivalent to roughly ~ in current density, and were injected at a frequency of 3.33 pulses for 30 min . A current density of is associated with a hole density value that is significantly higher than the threshold value . At this level of stress, the BPDs located in deeper region, beyond the effective range of the hydrogen implant profile, and within the substrate, are presumably being activated. This activation leads to both the reference diodes and those implanted with to exhibit comparable levels of bipolar degradation [9]. Both fabricated PiN diodes were then annealed at 350 under a vacuum pressure of bar for 2.5 h and slowly cooled to room temperature. Subsequently, to assess the impact of annealing on the degraded forward characteristics of the stressed PiN diodes, electrical characteristics were measured once more. The RT proton irradiated PiN diode showed full recovery from their bipolar degraded characteristics within 2.5 h of annealing (Fig. 7b), while the reference PiN diode was only midway of full recovery (Fig. 7a). This indicates proton irradiation alters the crystal structure for the stacking fault (SF) to "shrink" back with much ease to their initial basal plane dislocations (BPD) state.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.375.69.pdf

In conclusion, this study investigated the method for suppressing bipolar degradation through proton implantation. Proton implantation to the buffer layer was successful in reducing the forwardvoltage drift of the fabricated SiC PiN diode by at a current density of , by applying room temperature proton irradiation at a dose of . Implantation at higher dose ( over ) and RT over heated implant was more effective in suppressing stacking fault expansion, indicating the additional damage created hindered the recombinationenhanced dislocation glide motion, resulting in less drifts. Furthermore, it is assumed that the carrier lifetime degradation is due to the introduction of centers associated with the hydrogen implantation tail across the whole thickness of the buffer layer. The estimated carrier lifetime in the buffer layer is less than 10 ns and this reduction in lifetime may also have played a role in suppressing SF expansion. The estimated threshold hole density through TCAD simulation is to be around . In addition, RT proton irradiated PiN diodes showed full recovery from their bipolar
degraded characteristics within 2.5 h of annealing at under vacuum. This indicates proton irradiation alters the crystal structure for the stacking fault (SF) to "shrink" back with much ease to their initial basal plane dislocations (BPD) state.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/SSP.375.69.pdf

The authors of this paper would like to thank Nissin Ion Equipment Co. Ltd for their support in the implantation process.

References

The original version of this paper is available on https://www.scientific.net/SSP.375.69.pdf

Kato, M., Watanabe, O., Mii, T., Sakane, H., and Harada, S., "Suppression of stacking-fault expansion in 4 H -SiC PiN diodes using proton implantation to solve bipolar degradation", Sci Rep 12, 18790 (2022), doi: 10.1038/s41598-022-23691-y.

T. Kimoto et al., "Understanding and reduction of degradation phenomena in SiC power devices," 2017 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2017, pp. 2A-1.1-2A-1.7, doi: 10.1109/IRPS.2017.7936253.

Long, Y., Chen, Y., Wang, P., Hou, B., and He, H., "A Novel Insight Into the Mechanism of Bipolar Degradation in 4H-SiC MOSFET," in IEEE Electron Device Letters, vol. 46, no. 3, pp. 464-467, March 2025, doi: 10.1109/LED.2025.3528065.

Mii, T., Sakane, H., Harada, S., and Kato, M., "Analysis of carrier lifetime in a drift layer of class devices toward complete suppression of bipolar degradation" Materials Science in Semiconductor Processing (2023), doi: 153. 107126. 10.1016/j.mssp.2022.107126.

Harada, S., Mii, T., Sakane, H., and Kato, M., "Suppression of stacking fault expansion in a 4H-SiC epitaxial layer by proton irradiation", Sci Rep 12, 13542 (2022), doi:10.1038/s41598-022-17060-y

Li, T., Sakane, H., Harada, S., and Kato, M., "Suppression of stacking-fault expansion in 4HSiC diodes by helium implantation", Applied Physics Express, vol. 17, no. 8, Art. no. 086503, IOP, 2024, doi:10.35848/1882-0786/ad6be5

V. Veliadis et al., "Degradation and Full Recovery in High-Voltage Implanted-Gate SiC JFETs Subjected to Bipolar Current Stress," in IEEE Electron Device Letters, vol. 33, no. 7, pp. 952954, July 2012, doi: 10.1109/LED.2012.2196674.

Caldwell, J.D., Stahlbush, R.E., Hobart, K.D., Glembocki, O.J., and Liu, K.X., "Reversal of forward voltage drift in 4H-SiC p-i-n diodes via low temperature annealing," Appl. Phys. Lett., vol. 90, no. 14, pp. 143 519-143 522, Apr. 2007, doi: 10.1063/1.2719650

Hayashi, S., Yamashita, T., Senzaki, J., Kato, T., Yonezawa, Y., Kojima, K., and Okumura, H., "Relationship between depth of basal-plane dislocations and expanded stacking faults by application of forward current to p-i-n diodes", Applied Physics Express, vol. 12, no. 5, Art. no. 051007, IOP, 2019, doi: 10.7567/1882-0786/ab1305

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Keywords Index

1

1ssf Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

2

200 Mm Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

4

4 H -sic Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

4 H -sic; Heated High Energy Ion Implantation; Lattice Strain; Hrxrd Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

4h Silicon Carbide (sic) Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

4h-sic; Stacking Fault; Partial Dislocation Dipole; Uv Photoluminescence Imaging; Xray Topography Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

A

And Electroluminescence Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

B

Basal Plane Dislocation Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes; Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Bipolar Degradation Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation; Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes; Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET; Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Body Diode Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Bonded Substrate Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Bpd Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation; Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications; Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

C

Carrier Lifetime Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation; Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

D

Deep Level Transient Spectroscopy (dlts) Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Defectivity Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

E

Ews Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

F

Failure Analysis Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Forward Bias Degradation Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Forward Voltage Drop Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

G

Gate Stress Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

H

Hall Measurement Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Hydrogen Implantation Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

I

Interface Traps Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Ion Implantation Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

L

Leakage Current Degradation Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Lp-cvd Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

M

Micropipe Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Minority Carrier Lifetime Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Mobility Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

P

Photoluminescence Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Pl Imaging Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Polytype Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Proton Implantation Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

R

Recombination-enhanced Dislocation Glide Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

S

Screening Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Shockley-type Stacking Fault (ssf) Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

SiC Pin Diode Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Single Shockley Stacking Fault Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Stacking Fault Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Surface Recombination Velocity Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

T

Tcad Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Trap Center Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

U

Uv Irradiation Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Authors Index

A

Amishiro, H. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Anzalone, R. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

B

Bast, G. Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Bera, L. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

C

Calabretta, C. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Carlson, C. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Cela, E. Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Chand, U. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Chen, Z. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation; Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Cheng, Q. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Chung, S. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Csato, C. Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

D

Das, S. Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Dudley, M. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation; Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

F

Fontana, E. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

G

Ghandi, R. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

H

Harada, S. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Hatta, N. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Higashi, Y. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Hu, S. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Huang, A. Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Hébert, F. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

I

Igarashi, Y. Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Imai, A. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Ishibashi, K. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Ishikawa, S. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

J

Jayaprakash, H. Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

K

Kagawa, Y. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Kato, M. Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

Kennerly, S. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Kim, Y. Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Kobayashi, M. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Koch, R. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Kojima, K. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Krippendorf, F. Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation; Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Kubley, T. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Kumar, S. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Kuroi, T. Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

L

Lee, A. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Li, T. Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

Li, X. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Lichtenwalner, D. Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

M

Maddi, H. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Mahadik, N. Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Matsushita, Y. Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Morita, T. Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

N

Nania, C. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Niwa, H. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

O

Owen, M. Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

R

Raciti, D. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Raghothamachar, B. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation; Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Rueb, M. Demonstration of Suppressing 1SSF Expansion Using Energy Filtered Ion Implantation

Ryu, S. Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Rüb, M. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

S

Scheiman, D. Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Schwarzenbach, W. Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Severino, A. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Sezaki, H. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

Shahidi, S. Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Shimbori, A. Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Shrestha, R. Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Simpson, G. Deep-Ultraviolet Laser-Based Defect Inspection of Single-Crystal 4H-SiC and SmartSiC Engineered Substrates for High Volume Manufacturing

Singh, N. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Stahlbush, R. Formation Mechanism and Complex Faulting Behavior of a BPD Loop in Thick -SiC Epitaxial Layer

Stein, S. Characterization of Interface Trap and Mobility Degradation in SiC MOS Devices Using Gated Hall Measurements

Steski, D. Analysis of Lattice Damage in 4H-SiC Epiwafers Implanted with High Energy AI Ions with Silicon Energy-Filter for Ion Implantation

Sugawara, K. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

T

Takano, K. Numerical Analysis of Correlation between UV Irradiation and Current Injection on Bipolar Degradation in PiN Diodes

Tanaka, T. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Tok, E. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

Tokoro, N. Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

U

Uchida, H. Analysis of Trap Centers Generated by Hydrogen Implantation in 4H-SiC Bonded Substrates

V

Vento, F. Evaluation of 4HSiC Epitaxial CVD Process on Different 200 mm Substrates for Power Device Applications

Voo, Q. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate

W

Wada, R. Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Watahiki, T. Investigation on Bipolar Degradation Caused by Micropipe in 3.3 kV SiC-MOSFET

Wong, H. Suppression and Analysis of Bipolar Degradation in 4H-SiC PiN Diodes through Proton Implantation

Y

Yeo, Y. Study of In-Grown Micropipes in 200 mm 4H-SiC (0001) Epitaxial Substrate