Substrates and Substrates Manufacturing

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Substrates and Substrates Manufacturing

Special topic volume with invited peer-reviewed papers only

Edited by
Prof. Victor Veliadis and Dr. Arash Salemi

Sócientific.Net

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Volume 1156 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

Full text available online at https://www.scientific.net/book/substrates-and-substrates-manufacturing/978-3-0364-1761-5

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-03

Online:
2025-09-04

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1156.-1.pdf

This special edition presents recent technological advances, research results, and engineering solutions in substrate and epitaxial layer manufacturing, addressing the fundamental and technological aspects underpinning modern manufacturing of power electronic devices based on silicon carbide and gallium nitride. The articles highlight a broad spectrum of topics, ranging from epitaxial layer growth and crystal growth to substrate finishing technologies that ensure the final products' high structural and electronic properties.

The special edition aims to serve as a valuable resource for researchers and engineers engaged in developing and producing advanced semiconductor power devices, and provides readers with a balanced view of the scientific foundations and applied methodologies in this field.

Table of Contents

Preface

Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Philip Hens, Kevin M. Albrecht, Birgit Kallinger, Robin Karhu, Jürgen Erlekampf

A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Tawhid Rana, Kevin Moeggenborg, Luis Reyes, Katarzyna Izabela Stokeley, Sam Johnson, Ed Sanchez

Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

Hitesh Jayaprakash, Constantin Csato, Robert Koch, Florian Krippendorf, Michael Rueb

Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Yafei Liu, Campbell Bouch, Pete Schunemann, Ryan Philpott, Mary Safko, Danielle Hamann, Mason Dupre, Andrew Goldberg

New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Cristiano Calabretta, Nicolo Piluso, Simona Boninelli, Cristophe Iatosti, Emmanuel Roy, Daniele Calabriso, Louise Lilja, Alexandre Ellison, Carlo Riva, Ferdinando Iucolano, Andrea Severino

Process Gas Control for High-Resistance HPSI-SiC Growth

Seung Jun Lee, Su Ho Kim, Chae Young Lee, Jong Hwi Park, Jung Woo Choi, Jung Gyu Kim, Kap Ryeol Ku, Gi Uk Lee, Won Jae Lee

High-Temperature Adhesive Bonding of -SiC Substrates

Priyank Parmar, Manoj Kumar Yadav, Christopher Zellner, Guenter Wedl, Georg Pfusterschmied, Ulrich Schmid

New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Shan Shan Hu, Balaji Raghothamachar, Ze Yu Chen, Kevin W. Kayang, Dilip Gersappe, Michael Dudley, Victor Torres, Douglas Dukes, Diana Lang, Andy Martin, Hunter Briccetti, Samantha Griswold, Thomas Kegg, Nicholas Griffin

SmartSiC & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Eric Guiot, Gonzalo Picun, Frédéric Allibert, Alexis Drouin, Walter Schwarzenbach

Development of a Novel Warpage Control Method for Epi-Ready -SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Daichi Dojima, Seyoon Jeong, Kohei Toda, Tadaaki Kaneko

Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

Sven Strüber, Jonas Ihle, Julian Zöcklein, Johannes Steiner, Peter J. Wellmann

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/substrates-and-substrates-manufacturing/978-3-0364-1761-5

Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 1-9

doi: 10.4028/p-WvRa7Y

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-12

Revised:
2025-08-08

Accepted:
2025-08-08

Online:
2025-09-04

Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

Philip Hens , Kevin M. Albrecht , Birgit Kallinger , Robin Karhu and Jürgen Erlekampf

AIXTRON SE, Schottkystraße 10, 91058 Erlangen, Germany

Fraunhofer IISB, Schottkystraße 10, 91058 Erlangen, Germany

p.hens@aixtron.com, k.albrecht@aixtron.com, birgit.kallinger@iisb.fraunhofer.de, robin.karhu@iisb.fraunhofer.de, ej.erlekampf@aixtron.com

*corresponding author

Keywords: Epitaxial Growth, Substrate, Epitaxial Defects, Bonded Substrate, Engineered Substrate

Abstract

Engineered SiC wafers with a thin layer bonded on a polycrystalline carrier substrate for the application as substrate in epitaxy are investigated. Epitaxial layers grown on such substrates in 150 mm and 200 mm diameter are compared to those on state-of-the-art conventional substrates from different vendors. The performance of the engineered wafers is judged by doping and thickness uniformities as well as the number and statistics of killer defects in the epitaxial layer.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

The fast growth of the silicon carbide ( SiC ) power device market is relying on a sufficient supply of high quality SiC substrate wafers to achieve low epi defect numbers [1]. A reduction of monocrystalline SiC material usage for substrates is highly desirable to reduce device and material costs and secure a steady supply chain. One strategy, among others, is to use a very thin layer bonded onto a mechanical carrier. These so-called engineered substrates are regarded as sufficient for epitaxy and device production.
In addition to reduced SiC crystal consumption, the device performance can be improved further thanks to lower conduction and switching losses [2] in the device using ultra high conductivity receiver substrates. SOITEC's SmartCut process [3] uses such a below thin monocrystalline SiC layer, which is transferred to a polycrystalline SiC carrier substrate [4] and bonded utilizing a conductive bonding.
This study extends a benchmark performed on early samples [5] and looks more into the feasibility for high volume manufacturing using a full cassette to cassette (C2C) epitaxy line. Sets of current generation 150 mm and 200 mm SOITEC engineered substrates will be compared with industry standard bulk wafers from multiple vendors.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

In this benchmark study we are aiming to compare SOITECs SmartSiC engineered SiC substrates in 150 mm and 200 mm diameter as well as SOITEC Advanced SiC Engineered Substrates in 150 mm (abbreviated to "Soitec Advanced" in the graphs) to comparable monocrystalline substrates from four industry standard suppliers. These reference wafers were supplied partially by the TRANSFORM project partner STMicroelectronics, and partially bought from three external vendors:

150 mm : prime grade from vendor A and vendor B

200 mm : prime grade from vendor A and vendor C

From SOITEC we received different generations of their engineered substrates to be included:

150 mm : SmartSiC and Advanced SiC Engineered Substrates

SmartSiC

The epitaxy was performed in AIXTRON G10-SiC reactors in 9x150 mm and 6x200 mm configurations respectively. This allows a direct comparison between different substrates in the same process run under the same conditions and epitaxy process parameters. Two runs per substrate diameter were performed with the different substrate types distributed over both runs per diameter. Like this a total number of 18 wafers of the 150 mm size and 12 wafers of the 200 mm size were included in this study.

Table 1. Overview of substrate vendors and number of substrates included in this study

Vendor/type | 150 mm | 200 mm
SOITEC SmartSiC | 4× | 3×
SOITEC Advanced | 4× | ---
STMicroelectronics | 4× | 3×
Vendor A | 3× | 3×
Vendor B | 3× | ---
Vendor C | --- | 3×

On both substrate diameters, a thick buffer with a doping level was grown, followed by a thick drift layer. This was doped at and on 150 mm and 200 mm respectively.
After epitaxy, all wafers were then characterized regarding epilayer thickness and doping concentrations by FTIR spectrometry and mercury probe capacitance-voltage ( ) measurements, respectively. All wafers were characterized with ultraviolet photo luminescence (UVPL) imaging and surface inspection with a Lasertec SICA88 system to obtain the defect statistics. For all characterization methods an edge exclusion of 5 mm was applied.
The defect scans on the SmartSiC™ wafers were performed with slightly changed settings compared to the conventional substrates. This was done to adopt the defect recognition to the different surface morphology of the epilayer on the engineered substrates [5]. Main changes were a reduced brightness of the differential interference contrast channel and shifted thresholds for the adaption and optimization of the defect recognition algorithm. Due to this, there is no reliable detection of small surface defects like micropits and bumps on epilayers on SmartSiC™ substrates.

Wafer behavior in process

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

The AIXTRON G10-SiC reactor type used in this study is equipped with a full cassette-to-cassette automated wafer handling and loading system. All wafers were loaded and unloaded using the automated system at elevated temperatures. No problems occurred during these procedures and the engineered substrates can be handled using the automated system.

Fig. 1. Curvature in [ ] of the 150 mm substrates during process.

Fig. 1. Curvature in [ ] of the 150 mm substrates during process.

The AIXTRON systems also allow to measure the wafer curvature during the epitaxy at full process temperature. This allows to judge the substrates for internal strain and the potential risk of breakages or wafer slipping due to excessive curvature.
All 150 mm wafer exhibited a curvature between and under epitaxy process conditions (see Figure 1). On the 200 mm substrates we observed curvatures in a window of around the average for all the monocrystalline wafers, with the SOITEC SmartSiC™ substrates showing less curvature at roughly lower than the average of standard wafers under the same conditions. All wafers stayed in the expected range of curvature during process and no slippage was detected.

Epilayer characterization onsubstrates

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

Doping and Thickness: For this comparison between standard substrates and engineered wafers we are not only looking at defect performance and predicted device yield but also at the doping and thickness uniformity. As seen in Figure 2 and Figure 3, which show two substrates processed in the same epitaxy run, the performance in the doping uniformity is very good and comparable between conventional and engineered substrates on 150 mm .

Fig. 2. Doping uniformity on a 150 mm conventional reference wafer from STMicroelectronics. At a mean doping of the uniformity is sigma/mean.

Fig. 2. Doping uniformity on a 150 mm conventional reference wafer from STMicroelectronics. At a mean doping of the uniformity is sigma/mean.

Fig. 4. Thickness uniformity on a 150 mm conventional reference wafer from STMicroelectronics. At a mean thickness of the uniformity is sigma/mean.

Fig. 4. Thickness uniformity on a 150 mm conventional reference wafer from STMicroelectronics. At a mean thickness of the uniformity is sigma/mean.

Fig. 3. Doping uniformity on an engineered 150 mm SmartSiC wafer from Soitec. At a mean doping of the uniformity is 1.34 % sigma/mean.

Fig. 3. Doping uniformity on an engineered 150 mm SmartSiC wafer from Soitec. At a mean doping of the uniformity is 1.34 % sigma/mean.

Fig. 5. Thickness uniformity on an engineered 150 mm SmartSiC wafer from Soitec. At a mean thickness of the uniformity is 0.96 % sigma/mean.

Fig. 5. Thickness uniformity on an engineered 150 mm SmartSiC wafer from Soitec. At a mean thickness of the uniformity is 0.96 % sigma/mean.

The same comparability is evident on the thickness measurements. In Figure 4 and Figure 5 are two thickness profiles from a standard substrate and a SOITEC SmartSiC substrate. While the uniformities are comparable in the range of the measurement error, we can see a slight artefact in the average thickness measured on the engineered substrate, as the FTIR systems makes its fit to the bonded interface. Due to this the epitaxial layer appears thicker by , which equals the bonded single crystalline layer. This must be accounted for in tuning the epitaxial process.

Defects: In Figure 6 you can see a boxplot of the killer defect density. Counted here are polytype inclusions, stacking faults, PL stacking faults, propagated stacking faults and downfalls. One can see that the SmartSiC substrates perform on par with the monocrystalline substrates when looking at the total killer defect density.
The substrates from STMicroelectronics and from vendor A had one outlier wafer each with a higher killer defect density. Excluding those outliers, vendor A would perform the best in this factor.

Fig. 6. Normalized killer defect density on 150 mm with the worst wafer in the study set to unity. Counted are polytype inclusions, stacking faults, PL stacking faults, propagated stacking faults and downfalls.

Fig. 6. Normalized killer defect density on 150 mm with the worst wafer in the study set to unity. Counted are polytype inclusions, stacking faults, PL stacking faults, propagated stacking faults and downfalls.

Fig. 7. Normalized BPD density on 150 mm with the worst wafer in the study set to unity. The insert shows BPDs within bar shaped stacking faults on SmartSiC .

Fig. 7. Normalized BPD density on 150 mm with the worst wafer in the study set to unity. The insert shows BPDs within bar shaped stacking faults on SmartSiC .

The density of basal plane dislocations (BPDs) appears to be very high in the epilayers on SmartSiC substrates (Figure 7). This could be assigned to a faulty defect recognition and dislocation features connected mainly to bar shaped (propagated) stacking faults.

Fig. 8. Projected device yield for and on epilayers on the tested 150 mm substrates of different vendors.

Fig. 8. Projected device yield for and on epilayers on the tested 150 mm substrates of different vendors.

The SOITEC Advanced SiC Engineered Substrates were not included in the statistics for the killer defects. This decision was made as these are early prototypes that still show some bonding failures leading to localized polycrystalline growth in the epi process. These poly regions cannot be analyzed with the automated Lasertec system as there is a high number of false recognitions. But as these poly regions only make up a small part of the wafer, we can still look at the projected yield, as only a few devices would be affected.
Despite these small areas with polycrystalline growth the SOITEC Advanced SiC Engineered Substrates give a higher predicted yield both on and grids compared to the SmartSiC substrates (see Figure 8). STMicroelectronics substrates and wafers from vendor B have a wider spread, but in general perform on a similar level to the SOITEC SmartSiC™ engineered substrates. Vendor A is superior though when it comes to predicted device yield and the consistency of the results.

Epilayer Characterization on 200 mm Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

Doping and Thickness: As seen in Figure 9 and Figure 10, which show two 200 mm substrates processed in the same epitaxy run, the performance in the doping uniformity is very good and comparable between conventional and engineered substrates.

Fig. 9. Doping uniformity on a 200 mm conventional reference wafer from STMicroelectronics. At a mean doping of the uniformity is sigma/mean.

Fig. 9. Doping uniformity on a 200 mm conventional reference wafer from STMicroelectronics. At a mean doping of the uniformity is sigma/mean.

Fig. 11. Thickness uniformity on a 200 mm conventional reference wafer from STMicroelectronics. At a mean thickness of the uniformity is sigma/mean.

Fig. 11. Thickness uniformity on a 200 mm conventional reference wafer from STMicroelectronics. At a mean thickness of the uniformity is sigma/mean.

Fig. 10. Doping uniformity on an engineered 200 mm SmartSiC wafer from Soitec. At a mean doping of the uniformity is 2.48 % sigma/mean.

Fig. 10. Doping uniformity on an engineered 200 mm SmartSiC wafer from Soitec. At a mean doping of the uniformity is 2.48 % sigma/mean.

Fig. 12. Thickness uniformity on an engineered 200 mm SmartSiC wafer from Soitec. At a mean thickness of the uniformity is sigma/mean.

Fig. 12. Thickness uniformity on an engineered 200 mm SmartSiC wafer from Soitec. At a mean thickness of the uniformity is sigma/mean.

In the thickness measurements the same offset applies as for the 150 mm substrates. In Figure 11 and Figure 12 are two thickness profiles from a standard substrate and a SOITEC SmartSiC substrate. While the uniformities are comparable in the range of the measurement error, we can see a deviation in the average thickness measured on the engineered substrate. This makes the epitaxial layer appear thicker by due to the included bonded single crystalline layer. This must be accounted for in tuning in the epitaxial process.

Defects: In Figure 13 you can see a boxplot of the killer defect density. Counted here are polytype inclusions, stacking faults, PL stacking faults, propagated stacking faults and downfalls. One can see that the 200 mm SmartSiC substrates perform on par with the monocrystalline substrates from STMicroelectronics and vendor C when looking at the total killer defect density. Vendor A shows a lower killer defect density in the epilayer.

Fig. 13. Normalized killer defect density on 200 mm with the worst wafer in the study set to unity. Counted are polytype inclusions, stacking faults, PL stacking faults, propagated stacking faults and downfalls.

Fig. 13. Normalized killer defect density on 200 mm with the worst wafer in the study set to unity. Counted are polytype inclusions, stacking faults, PL stacking faults, propagated stacking faults and downfalls.

Fig. 14. Normalized BPD density on 200 mm with the worst wafer in the study set to unity.

Fig. 14. Normalized BPD density on 200 mm with the worst wafer in the study set to unity.

Most of the standard monocrystalline substrates perform well in respect to BPDs (Figure 14), except for one significant outlier wafer on vendor C. Epilayers on the substrates exhibit a slightly higher count of BPDs than the average.

Fig. 15. Projected device yield for and on epilayers on the tested 200 mm substrates of different vendors.

Fig. 15. Projected device yield for and on epilayers on the tested 200 mm substrates of different vendors.

While having a larger spread of yield - likely due to the early prototype status of the used substrates - the showed an average yield comparable to STMicroelectronics and vendor C conventional substrates (Figure 15). Like the performance on 150 mm , we can also see the best predicted yield on 200 mm substrates from vendor A.

Vendor Fingerprints in Defects

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

The following graphs (Figure 16 to Figure 25) show a relationship of some relevant defects between three substrate types (SmartSiC , STMicroelectronics and vendor A) in 150 mm and 200 mm sizes. One can see that the different manufacturers have a certain "fingerprint" in the distribution of defects. SOITEC's Advanced SiC Engineered Substrates, vendor B and vendor C are not included in this section as they were not available in both substrate diameters.

Stacking Faults and Polytype Inclusions: SOITEC and vendor A show a lower number than STMicroelectronics

PL Stacking Faults, Propagated Stacking Faults and BPDs: SOITEC has the highest density, followed by STMicroelectronics and with vendor A the best

Fig. 16. Normalized Stacking Fault density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 16. Normalized Stacking Fault density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 18. Normalized Polytype Inclusion density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 18. Normalized Polytype Inclusion density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 17. Normalized Stacking Fault density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 17. Normalized Stacking Fault density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 19. Normalized Polytype Inclusion density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 19. Normalized Polytype Inclusion density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 20. Normalized PL Stacking Fault density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 20. Normalized PL Stacking Fault density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 22. Normalized Propagated (Bar Shaped) Stacking Fault density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 22. Normalized Propagated (Bar Shaped) Stacking Fault density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 24. Normalized BPD density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 24. Normalized BPD density on 150 mm substrates from different vendors with the worst wafer set to unity.

Fig. 220. Normalized PL Stacking Fault density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 220. Normalized PL Stacking Fault density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 23. Normalized Propagated (Bar Shaped) Stacking Fault density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 23. Normalized Propagated (Bar Shaped) Stacking Fault density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 21. Normalized BPD density on 200 mm substrates from different vendors with the worst wafer set to unity.

Fig. 21. Normalized BPD density on 200 mm substrates from different vendors with the worst wafer set to unity.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

Across both substrate diameters we have observed a very similar performance of the SOITEC engineered substrates compared to conventional substrates from different industry vendors. Doping performance in average level and uniformity is not affected by the substrate type. Thickness uniformity is also not affected while we see an offset in the average layer thickness caused by the bonded layer, which gets included in the fit of the FTIR data. Epitaxy defects cause a certain yield loss. Here SmartSiC substrates perform on par with STMicroelectronics and vendors B and C. Vendor A typically delivers the best defect performance in this comparison. The fact that ratios of defects between different suppliers seem very similar between 150 mm and 200 mm indicates that the defect performance is mainly given by the crystal and surface quality and not dominated by outliers and random effects.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

This project has received funding from the Key Digital Technologies (KDT) under Grant Agreement No 101007237 (TRANSFORM). The KDT receives support from the European Union's Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain. We thank our partners Soitec (France) and STMicroelectronics Silicon Carbide AB (Sweden).

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.1.pdf

H. Das et al. "The Role of Defects on SiC Device Performance and Ways to Mitigate Them", Defect and Diffusion Forum 434 (2024): 51-59

E. Guiot et al. „SmartSiC™ engineered substrate: increasing SiC power device current density up to ", PCIM Europe 2024; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nürnberg, Germany (2024): 1599-1604

S. Rouchier et al. " 150 mm SiC engineered substrates for high-voltage power devices", Materials Science Forum 1062 (2022): 131-135

H. Biard et al. „Poly-SiC Characterization and Properties for SmartSiC Materials Science Forum 1124 (2024): 21-25

B. Kallinger et al. "Benchmarking Experiment of Substrate Quality Including SmartSiC Wafers by Epitaxy in a Batch Reactor", Solid State Phenomena 342 (2023): 91-98

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The original version of this eBook is available on https://www.scientific.net/book/substrates-and-substrates-manufacturing/978-3-0364-1761-5

Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 11-16

doi: 10.4028/p-Shye9P

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-17

Revised:
2025-08-22

Accepted:
2025-08-22

Online:
2025-09-04

A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

The original version of this paper is available on https://www.scientific.net/MSF.1156.11.pdf

Tawhid Rana , Kevin Moeggenborg , Luis Reyes , Katarzyna Izabela Stokeley , Sam Johnson , and Ed Sanchez

SK siltron css, 1311 Straits Drive, Bay City, MI 48706, USA

Oxford Instruments Plasma Technology, North End, Yatton, Bristol, BS49 4AP, UK

E-mail: katarzyna.stokeley@oxinst.com, sam.johnson@sksiltron.com, edward.sanchez@sksiltron.com

Keywords: Silicon carbide epitaxy, plasma etching, PPDE, surface preparation

Abstract

We studied the impact of plasma polish dry etch (PPDE) on SiC substrates and its effect on epilayers grown on PPDE treated substrates. PPDE treatment on chemo mechanical polished (CMP) surface shows no significant degradation in surface roughness even with removal. On the other hand, when a mechanical polished (MP) surface was treated by PPDE, surface roughness was improved, demonstrating that PPDE can smooth a rough surface post MP process. Selective etching of threading screw dislocations (TSD) was evident from pit formation on the substrate surface. These pits may generate extended structural defects (e.g. triangular defects) during the epilayer growth depending on the sizes of the pits. No evidence was found that PPDE selectively etched BPD in the substrate and, hence, no improvement in BPD conversion was seen after epilayer growth. Ideally, PPDE treated surface pits needed to be minimized at TSD sites and mild etching at BPD sites is preferable and subject to future optimization.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.11.pdf

Silicon carbide is an important material for high voltage applications due to its various exceptional electrical and mechanical properties. To achieve reliable high voltage devices, however, defect-free epitaxy is essential. On the other hand, to achieve epitaxy with low defect counts, it is essential to optimize substrate surface preparation prior to epilayer growth. During the wafer processing, e.g. grinding, polishing etc., the substrate is damaged by scratches. This damaged surface is planarized by chemical mechanical polishing (CMP) to achieve a smooth scratch-free surface. Even though the surface is very smooth after CMP (roughness RMS), it is expected that some subsurface damage [1] is still present. Conventionally, hydrogen etching is used prior to the epilayer growth to create atomic steps on the surface. However, etching may not remove adequate material to eliminate subsurface damage due to its low removal rate in conventional epitaxial process.

Subsurface damage has been discussed earlier [2, 3]. Efforts have been made to mitigate subsurface damage by so called "Dynamic Aging", where the substrate is treated at a high temperature [3], have been shown to be beneficial for the reduction of basal plane defects (BPDs) and stacking fault (SF) defects in epitaxy. As an alternative to chemo-mechanical polishing, plasma polish dry etch (PPDE) is currently gaining attention [4] with the potential benefit of removal of subsurface damage. Plasma etching has well known applications in semiconductor industries, especially as a part of lithographic steps during device fabrication [5, 6]. High speed plasma etching on SiC has also been demonstrated [7]. However, detailed study of plasma etching on SiC substrates in terms of defects and their impact on epitaxial growth is not well known. In this research, we explore the effect of plasma polish dry etching (PPDE) on substrates ( off cut) and study its effect on epitaxial growth.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1156.11.pdf

SiC wafers ( 150 mm diameter) were selected from multiple boules to eliminate any effect due to boule-to-boule variations. We divided these wafers into three groups as: mechanical polished wafers or MP, CMP, CMP+PPDE, MP+PPDE and hereby use these abbreviations in this manuscript. Here, plasma polish dry etching (PPDE) was performed using a PlasmaPro 100 Cobra tool from Oxford Instruments [4]. Plasma etch process atomic force microscopy (AFM) was used to measure surface roughness of these wafers prior to and after plasma etching. Finally, epitaxy was grown on these wafers using a commercial epi reactor with fixed growth conditions (thickness target and doping target ). The shape of these wafers was measured using a Tropel Ultrasort and defects were characterized by a SiCA88 tool.

Results

The original version of this paper is available on https://www.scientific.net/MSF.1156.11.pdf

We studied shape, roughness, and surface of the plasma etched wafers. From the total thickness of the wafer, we found that of SiC was removed from the surface by the plasma etching process [Fig. 1 a]. We observed a positive shift in the wafer bow after the plasma treatment [Fig. 1b]. This indicates that PPDE imparting additional stress to the Si face of the wafers. This may be due to a small-scale increase in surface roughness after PPDE. Further study is needed to understand this bow change after PPDE. On the other hand, bow of the epi wafer did not increase further after epilayer growth but, contrarily, the bow reduced. Epilayer bow for PPDE treated wafer was found to be comparable to the epilayer grown on non PPDE treated substrates. It is likely that the residual stress induced by PPDE was removed during epitaxial growth process in a high temperature and ambient.

Fig. 1. a) Substrate thickness measurement shows removal after plasma dry etch. b) The substrate bow increases up to um after the plasma dry etching process but reduced after the epi run. c) Comparative images of the bow of the substrates for CMP, CMP + PPDE and CMP+ PPDE + EPI wafers.

Fig. 1. a) Substrate thickness measurement shows removal after plasma dry etch. b) The substrate bow increases up to um after the plasma dry etching process but reduced after the epi run. c) Comparative images of the bow of the substrates for CMP, CMP + PPDE and CMP+ PPDE + EPI wafers.

When comparing roughness for CMP and CMP+PPDE substrates, we did not see a significant difference between the treatment techniques (Fig. 2). This indicates that the PPDE process does not add damage to the CMP surface. On the other hand, we found that when PPDE was performed on MP wafers, there was improvement in roughness of the surface. This indicates that PPDE has a potential to replace CMP polish for surface smoothing after MP. Post epitaxial surface roughness on epilayers grown on PPDE treated wafers were also found to be comparable to the non PPDE treated wafers (Fig. 2).

Fig. 2. AFM study demonstrates that roughess of the substrate treated by PPDE closely matches to the roughness of the CMP surface, showing plasma etch does not degrade the surface significantly. On the other hand, roughness of the surface was reduced significantly by plasma etching of a mechanically polished (MP + PPDE) surface. Post epi surface roughness of PPDE treated surfaces was also comparable to surface roughness of epilayers grown on non PPDE treated surfaces. b) AFM image on the MP substrate (left) and after treated by PPDE (right) showing surface smothing.

Fig. 2. AFM study demonstrates that roughess of the substrate treated by PPDE closely matches to the roughness of the CMP surface, showing plasma etch does not degrade the surface significantly. On the other hand, roughness of the surface was reduced significantly by plasma etching of a mechanically polished (MP + PPDE) surface. Post epi surface roughness of PPDE treated surfaces was also comparable to surface roughness of epilayers grown on non PPDE treated surfaces. b) AFM image on the MP substrate (left) and after treated by PPDE (right) showing surface smothing.

We studied defects on the PPDE treated substrates and their effect on consequently grown epilayers. We observed an increase in surface pits on the PPDE treated surface (Fig. 3). In the PL image we see TSDs as black dots (confirmed by KOH etch). Typically, TSDs are seen only in PL images as black dots (Fig 3a) in CMP treated surface and they are not seen in surface image (Fig 3b). Similar black dots are seen in PL image after PPDE (Fig. 3c), however, unlike CMP surface, pits are seen at the same location (Fig. 3d). We found that not all TSDs are converted into pits after PPDE. We believe whether PPDE creates etch-pits or not will depend on the sizes of the dislocation and upon plasma etch conditions. Further detailed study is required to understand when certain types of TSDs generate pits after PPDE and the effect of plasma etch conditions, which will be a topic of our future research.

Fig. 3. a) Black dot is seen in the PL image on the substrate prior to epilayer but b) no pit is seen as the surface was planarized by CMP. c) black still exist in the PL image after PPDE treatment. d) PPDE generates a pit at the black dot location seen in the surface image.

Fig. 3. a) Black dot is seen in the PL image on the substrate prior to epilayer but b) no pit is seen as the surface was planarized by CMP. c) black still exist in the PL image after PPDE treatment. d) PPDE generates a pit at the black dot location seen in the surface image.

We found that most of these pits translated into the epilayer as pits. Some, however, acted as a source of triangular defects and related stacking faults in the epilayer (Fig. 4, 5). Hence, it is essential to reduce TSD related pit formation on the substrate by PPDE by optimization of the plasma process. On the other hand, mild etch pit creation at BPD sites may be beneficial so that the conversion of BPDs to TED is enhanced in a similar fashion as BPD reduction by KOH etching [8]. However, no evidence is yet found to demonstrate that PPDE selectively etches BPDs on the surface and reduces BPDs in epilayer grown on PPDE treated substrate based on our results (Fig. 6). Further study is required to optimize the PPDE process so that it selectively etches BPDs (with minimal TSD etch pits) and enhances BPD conversion for low BPDs in the epilayers.

Fig. 4. a) The number of pits increased in the substrates after the plasma treatment. b) The majority of these pits were propagated into epi as pits (A), while a minority of them generated triangular defects and stacking faults ( ).

Fig. 4. a) The number of pits increased in the substrates after the plasma treatment. b) The majority of these pits were propagated into epi as pits (A), while a minority of them generated triangular defects and stacking faults ( ).

Fig. 5. a) Increase in pits for PPDE treated substrates and b) consequent increase of Stacking faults for PPDE treated surface

Fig. 5. a) Increase in pits for PPDE treated substrates and b) consequent increase of Stacking faults for PPDE treated surface

Fig. 6. Basal plane dislocation (BPD) count at different surface conditions is shown. It shows that post PPDE has no clear effect on BPD conversion or reduction.

Fig. 6. Basal plane dislocation (BPD) count at different surface conditions is shown. It shows that post PPDE has no clear effect on BPD conversion or reduction.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1156.11.pdf

The effects of plasma polished dry etch (PPDE) on substrates were studied. We found that surface roughness did not signmificantly worsen for PPDE treated substrate on CMP wafers. PPDE improves surface roughness by smoothing the mechanically polished surface. PPDE selectively etches TSDs in the substrates creating etch pits. These etch pits either propagate into the epilayer as a pit or may work as a source of extended defects (e.g. triangular defects, stacking faults). Our initial goal of the research was to demonstrate that PPDE reduced BPDs by etching BPD sites on the surface similarly as BPD pit creation by KOH etching. However, no clear evidence in BPD reduction was found from our experiments. Since PPDE demonstrates selective etching of TSDs, it has the potential to selectively etch BPD sites as well but further study is required. TSD etch pits need to be minimized by optimizing the process to prevent structural defect formation in the epilayer. These items will be covered in future research.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.11.pdf

Yi Zhang, Linfeng Zhang, Keyu Chen, Dianzi Liu, Dong Lu1 and Hui Deng, International Journal of Extreme Manufacturing 3, 11 (2021)

Koji Ashida, Daichi Dojima, Yasunori Kutsuma, Satoshi Torimi, Satoru Nogami, Yasuhiko Imai, Shigeru Kimura, J. Mizuki, Noboru Ohtani & Tadaaki Kaneko, MRS Advances 1, 3697 (2016).

Kohei Toda, Daichi Dojima, Kiyoshi Kojima, Hiroshi Mihara, Shin-ichi Mitani, and Tadaaki Kaneko, Solid State Phenomena, 344, 9 (2023).

Cardinaud, Christophe, Marie-Claude Peignon, and Pierre-Yves Tessier, Applied Surface Science 164.1-4 (2000): 72-83.

Verdonck, Patrick, Oficina de Microfabricao: Projeto e Construcao de CI's MOS, Swart, JW, Ed., Campinas (Sao Paulo, Brazil): UNICAMP (2006): 9.

Yasuhisa Sano, Koki Tajiri, Yuki Inoue, Risa Mukai, Yuma Nakanishi, Satoshi Matsuyama and Kazuto Yamauchi, ECS Journal of Solid State Science and Technology, Volume 10, Number 1

Haizheng Song, Tawhid Rana, Tangali S. Sudarshan, Journal of Crystal Growth, Volume 320, Issue 1, 2011, Pages 95-102,

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 17-26

doi: 10.4028/p-tzYpX7

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Accepted:
2025-04-08

Online:
2025-09-04

Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1156.17.pdf

Hitesh Jayaprakash , Constantin Csato , Robert Koch , Florian Krippendorf , Michael Rueb

mi2-factory GmbH, Moritz-von-Rohr Str. 1a, 07745 Jena, Germany

Ernst-Abbe-Hochschule Jena, Carl-Zeiss-Promenade 2, 07745 Jena, Germany

Friedrich-Alexander-Universität, Cauerstr. 6, 91058 Erlangen, Germany

hitesh.jayaprakash@eah-jena.de, constantin.csato@mi2-factory.com,

Robert.Koch@eah-jena.de, michael.rueb@mi2-factory.com

Keywords: Semi-Insulating 4H-SiC, Layer transfer, Ion slicing, Engineered substrates

Abstract

The growing demand for substrates in power device fabrication has encouraged the development of engineered substrates to reduce costs and facilitate wafer re-usability for effective material utilization. This work presents a novel approach for manufacturing SiC power devices is to exfoliate the required drift layer thickness from ultra-high-quality Semi Insulating (SI) 4H-SiC material, bond it to a conductive SiC substrate and thus obtain the non-epitaxial engineered substrate. Energy-filtered Ion Implantation (EFII) technology enables custom doping profiles, precise control of doping concentration, and potentially robust material properties compared to as-grown epitaxial layers in the bonded layer. Key steps to exfoliate a thick SiC layer from semi-insulating substrates and bond it to low-cost, highly conductive mono-crystalline SiC are demonstrated. This paper mainly focuses on the physical characterization of demonstrated samples.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.17.pdf

To meet the growing demand for as a next-generation wide band-gap semiconductor and accelerate power device production, novel substrates are needed to reduce production time and manufacturing costs without compromising device characteristics. Currently, epi-ready substrates [1, 2] rely on traditional epitaxial growth methods to grow the voltage-sustaining layer, a crucial step in the fabrication of power devices [3]. SiC-epitaxy is a complex process and requires regular maintenance to achieve uniform doping profiles and material quality in mass production. An alternate solution is to use the novel non-epitaxial engineered substrates introduced in our previous work [4] to fabricate SiC power devices without the need for epitaxy using on-axis SI 4H-SiC. There are several advantages of having the voltage sustaining layer oriented on-axis, <0001>. 1. Trench MOSFETs do not need the tilted trench etch to maximise the channel mobility on c-plane . There exist a possible choice of Si-face or C-face for application specific power device. 3. There is also a possibility to achieve Hu profile [7] for achieving minimum ohmic-resistance and highest breakdown voltage. These profiles can be tailor made by utilizing the choice of doping technology described further.

The proposed non-epitaxial engineered substrate could be a promising alternative to current epiready substrates if the donor material, doping technology and wafer bonding methods are carefully selected. First, vanadium-free, high-quality semi-insulating (SI) is chosen as the donor material for the voltage-sustaining layer to avoid unwanted trap levels in the band structure. This material has been used in power devices for JFET operations [8]. Second, Energy Filtered Ion Implantation (EFII) is used to implant box profiles in this layer [9, 10], replacing conventional drift zone doping done via epitaxy. For layer exfoliation of donor wafers, ion slicing with proton implantation [11, 12] is the suitable method among many methods [13-18], as it allows precise control of layer thickness and achieves surface roughness close to a few nanometers after exfoliation. Lastly, wafer bonding needs to provide a seamless bond with minimal electrical resistance, using a
low-temperature process to preserve the proton concentration for exfoliation. Oxide-free hydrophobic direct bonding [19] with surface activation at room temperature must be chosen over more common hydrophilic bonding [20]. The process flow is illustrated in the Fig. 1

Fig. 1. Illustration of the novel non-epitaxial engineered substrate technology for 4H-SiC power device fabrication. This high quality donor wafer can be used multiple times.

Fig. 1. Illustration of the novel non-epitaxial engineered substrate technology for 4H-SiC power device fabrication. This high quality donor wafer can be used multiple times.

Previous attempts to exfoliate and bond thick SiC layers have failed. This paper details the necessary process steps required to obtain non-epitaxial engineered substrates demonstrated on a chip scale of area. The physical effects of proton implantation on the SiC chips like surface bow, surface roughness, exfoliated layer thickness and bond interface investigations are done. This approach eliminates the need for epitaxy in conventional SiC power device fabrication and is scalable to 200 mm SiC technology.

Experimental Approach

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Two 6-inch, commercially available on-axis (SI) 4H-SiC wafers were chosen from our previous study [4], these wafers had the lowest density of BPD per volume and the surface roughness of RMS on Si-face was critical for bonding applications. A wafer was implanted with a box profile on the Si-face up to a depth of with Nitrogen using EFII technology and activation annealed at for 30 minutes. The implanted wafer served as a doped SI material for the study and the other as an undoped SI material. These samples were prepared to demonstrate that the exfoliation process is suitable for both types of material. Furthermore, wafers were cut into chips to study the critical proton dose requirement and suitable heat treatment parameters to exfoliate the layer from the surface of the chip using ion slicing technique.

For this study, proton energy of 500 KeV was used which has a projected range of , that implies thick layers can be exfoliated from the chip. Based on previous work, to exfoliate the thin layer in the SiC [21-26] at lower proton energies, peak concentration was estimated to be in the range of 3E21-6E21 cm-3 for successful layer exfoliation. GEANT4 simulations were performed to obtain the corresponding maximum concentration for proton implants in the range of 1E17-2E17 cm-2 dose as shown in Fig. 2. The chips were then categorized according to material type, labeled and implanted with proton dose as per the Table. 1.

All these chips were implanted with 500 KeV proton with maximum available tilt angle of at the implanter to avoid channelling on the Si-face. After proton implants, one set of chips were subjected to blister tests to find the optimum exfoliation parameters for heat treatment while the other set were chosen for layer transfer with bonding experiments. Tube furnace with Ar ambient was utilized for both blister tests and bonding tests. The heat treatment parameters, including the critical temperature,

Table 1. 500 KeV proton implantation doses and corresponding peak concentrations obtained using GEANT4 simulation in substrates.

①
High Quality
Semi insulating material
②
Energy filtered Ion Implantation
(Drift Zone doping)
③
Proton Ion implantation
(for splitting)

④
Bonding the layer
to low ohmic handle wafer
⑤
Layer
Splitting process
⑥
Non-Epitaxial
Engineered Substrate
Refurbish & reuse
High Quality material

Fig. 2. GEANT4 simulation of ion stopping and range to obtain effective peak concentration for implant doses of proton at 500 KeV energy into material.

Fig. 2. GEANT4 simulation of ion stopping and range to obtain effective peak concentration for implant doses of proton at 500 KeV energy into material.

optimal hold times and ramp rate to promote Ostwald ripening process was studied [22]. These tests are critical to find the parameters that promote blister formation, which is crucial for the exfoliation process.

Blister test: Chips selected for blister tests underwent heat treatment at two different hold temperatures at (T1) and (T2) with the maximum possible ramp ( ) temperature of the used furnace. T1 was chosen as the minimum activation temperature for blister formation from the arrhenius plot from previous work [25] and higher temperature T2 to enable higher activation rates for blistering. A duration of 30 and 60 minute as hold time at T1 and T2 was tested individually to obtain adequate time for ripening process. The physical aspects of the chip after high proton dose implants were

Fig. 3. The physical effect of high dose proton implantation on chips, where bow of is observed on the highest dose of 2E17 cm-2. Note the measurement points are on the diagonals and the surface is interpolated contour plot from interferrometric measurements.

Fig. 3. The physical effect of high dose proton implantation on chips, where bow of is observed on the highest dose of 2E17 cm-2. Note the measurement points are on the diagonals and the surface is interpolated contour plot from interferrometric measurements.

studied. Convex bow is observed on the implanted chip surface as illustrated in Fig. 3. Similar convex wafer surface can be expected on 6-inch full wafers too with higher magnitude in accordance with previous studies [27]. The blister test results, layer thickness and surface roughness measurement are discussed in the results section.

Bonding experiments: The successful process parameters obtained from the blister tests were used for the bonding experiments. Four bond chip pairs as described in Table. 2 were stuck to a 6-inch Si wafer for handling purpose with kapton tape. The bond equipment MWB-06/08-AX [28] was used for room temperature bonding under ultra high vacuum with in-situ Surface Activation Bonding (SAB) using Ar in Fast Atomic Beam (FAB) gun [29, 30]. An attempt to bond exfoliated SiC to Si chip was also done with Silicon Sputtered Bonding (SSB). Further, bonded layer thickness, surface roughness and cross-section of bond interface with FIB were studied and compared with the blister test results.

Results and Discussion

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Blister tests: With regards to the proton dose requirement for both doped and undoped material, a dose of is suitable for exfoliating thick layers efficiently. Treating the chips at which is higher than the minimum theoretical activation temperature [25], can be used to compensate temperature tolerance errors in the furnaces. Blisters were noticeable for 30 minutes hold time. 60 minutes hold time at T1 did not have any notable difference. Temperature T2 or longer hold times could improve bond strength and diffuse residual hydrogen at the bond interface as noted from earlier studies [31]. The N-doped SI SiC layer showed less curling than undoped SI, indicating lower internal stress compared to bulk substrates. This may be due to the activation anneal after N implantation with EFII. The test results are summarized in Fig. 4.

Fig. 4. Results of blister test at different blister parameters like proton dose, heat treatment temperature and ripening time on undoped and doped chips. The minimum dose requirement for a thick layer blistering is . Darker layers are exfoliated SiC and lighter regions are bare substrate underneath.(some dark regions in S row are reflection on the chips)

Fig. 4. Results of blister test at different blister parameters like proton dose, heat treatment temperature and ripening time on undoped and doped chips. The minimum dose requirement for a thick layer blistering is . Darker layers are exfoliated SiC and lighter regions are bare substrate underneath.(some dark regions in S row are reflection on the chips)

Fig. 5 shows consistent results for exfoliated SiC layer thickness and surface roughness across multiple samples. However, some samples did not exfoliate uniformly throughout the chip area, likely due to the channeling effect during proton implantation, causing lower peak concentration at the projected range. A tilt is insufficient to avoid channeling in on-axis SiC. An optimal anti-channeling angle for on-axis [0001] in must be used during proton implantation to ensure uniform exfoliation [32, 33].

Fig. 5. The blister test measurements promises repeatability of the ion slicing process. left shows the median layer thickness of obtained corresponding to the simulated , for 500 KeV proton implants in SiC. right shows the area surface roughness (Sq) of a area is also consistent at a median of 2.95 nm .

Fig. 5. The blister test measurements promises repeatability of the ion slicing process. left shows the median layer thickness of obtained corresponding to the simulated , for 500 KeV proton implants in SiC. right shows the area surface roughness (Sq) of a area is also consistent at a median of 2.95 nm .

Table 2. The bond pairs involved, undoped and nitrogen-doped SI 4H-SiC (exfoliation layer) from the donor chips, bonded to N-type SiC and Si as acceptor chip. Bonding results, immediately after bonding and post-exfoliation at for 60 minutes, are tabulated.

Bond Pair | Donor material chip | Proton dose | Acceptor Chip | FAB type | Pressure welding | Result (as bonded) | Result (after splitting)
1 | Undoped SI SiC | M | N-type SiC | SAB |  | Failed | -NA-
2 | Undoped SI SiC | L | N-type SiC | SAB | 10 MPa | Success | Success
3 | Doped SI SiC | L | N-type SiC | SAB |  | Success | Success
4 | Doped SI SiC | L | N-Type Si | SAB |  | Success | Failed

Bonding experiments: The bonding experiments results are summarized in the Table. 2 and bond pair 2 image is illustrated in Fig.6a. Due to kapton particle contamination during surface activation step, bond pair 1 failed. Whilst other chips with surface activation bonding were successful. Even the SiC and Si chips were bonded. But during the heating procedure to exfoliate the layers, SiC -Si bond failed due to CTE mismatch. The bond pair 2 and 3 were successful and the exfoliated layer showed robust bond strength even at for 30 minutes. The layer thickness of was measured with interferrometer as shown in the profile plots of Fig. 6b. The surface roughness (Sq) of the exfoliated surface were measured to be and surface morphology from SEM image is shown in Fig. 6c. Further, plasma assisted polishing [34, 35] provides smooth surface for power device fabrication.

The FIB cross-section measurements on bond pair 3 shown in Fig. 7 also reveals layer bonded seamlessly to the N-type SiC substrate with interface thickness of pre-reactivation anneal. This is a necessary step after bonding to re-activate the dopants after proton implants [36]. The measured value in FIB cross-section Fig. 7b is slightly higher than the interferrometric measurements due to measurement artifact in the tool. These thickness measurements on bonded layers are in accordance with the layer thickness measured after blistering tests. The reduction of 80 nm is expected due to the surface cleaning process and the surface activation step before bonding the chips. These results also reveal that the critical peak concentration of hydrogen in needs to be for blistering and >4E21 cm-3 for optimum exfoliation of layers. Due to furnace malfunction during reactivation annealing, bonded SiC chips were completely oxidized and destroyed. Hence,
bond characterization of the bond interface after high temperature anneal was not performed. Our future work includes scaled up demonstration of this technology on a full 6 -inch wafer with further electrical characteristics of the novel non-epitaxial substrates.

Fig. 6. (a) A chip was successfully bonded and exfoliated from a donor onto an N-type 4H-SiC substrate. (b) Profile plots of L1, L2, and L3 show a uniform m layer thickness across the chip surface. (c) SEM image of the exfoliated area reveals a rough surface topology, requiring polishing.

Fig. 6. (a) A chip was successfully bonded and exfoliated from a donor onto an N-type 4H-SiC substrate. (b) Profile plots of L1, L2, and L3 show a uniform m layer thickness across the chip surface. (c) SEM image of the exfoliated area reveals a rough surface topology, requiring polishing.

Fig. 7. FIB cross-section images results indicating the seamless bond interface after exfoliating the layer. Regions marked in red are zoomed in successive images. (a) at the edge of the bonded layer. (b) measured layer thickness. (c) Seamless bond interface (enhanced contrast for visibility)

Fig. 7. FIB cross-section images results indicating the seamless bond interface after exfoliating the layer. Regions marked in red are zoomed in successive images. (a) at the edge of the bonded layer. (b) measured layer thickness. (c) Seamless bond interface (enhanced contrast for visibility)

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.17.pdf

For the first time, exfoliating a thick semi insulating layer and successfully bonding it to a SiC substrate is demonstrated over an area of . This study showcases that for thick layer exfoliation, peak proton concentration must be reached at 500 KeV energy followed by the heat treatment greater than for 30 minutes to sufficiently exfoliate thick layers. Bonding material is also made possible by using in-situ surface activation bonding at ultra high vacuum under room temperature. However, particle contamination plays an important role in bonding step, hence least particle contamination must be maintained for void free bonding. This technology offers optimal accesibility for exfoliating non-epitaxial layers of thickness upto for power device fabrication corresponding to the voltage class of 2 KV .

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1156.17.pdf

All ion implantations were conducted at the Ion Beam Center of Helmholtz-Zentrum Dresden-Rossendorf (HZDR), standard dopant activation annealing was performed at Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie (IISB), Erlangen and bonding tests were performed in cooperation with Nidec Machine Tool with MWB-06/08-AX (WR017) machine. Thanks to Oliver Rüger for preparing the cross-sections and SEM images at Institut für Festkörperphysik Jena.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.17.pdf

Wolfspeed. N-Type SiC Substrates. https://www.wolfspeed.com/products/materials/n-type-sic-substrates/. Accessed: 2024-09-02. 2024.

Soitec. SmartSiC for Automotive Applications. autosmartsic. Accessed: 2024-09-02. 2024.

Séverin Rouchier et al. " 150 mm SiC Engineered Substrates for High-Voltage Power Devices". In: Materials Science Forum 1062 (2022), pp. 131-135.

Hitesh Jayaprakash et al. "Study on Estimation of Device Yield in Non-Epitaxial 4H-SiC Material Relating to Defect Densities Influencing Bipolar Degradation with XRTMeasurements". In: Solid State Phenomena 344 (2023), pp. 53-57.

Ralf Siemieniec et al. "A SiC Trench MOSFET concept offering improved channel mobility and high reliability". In: 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe). 2017, P.1-P.13.

Dethard Peters et al. "Performance and ruggedness of 1200 V SiC - Trench - MOSFET". In: 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). IEEE, 2017, pp. 239-242. ISBN: 978-4-88686-094-1.

Chenming Hu. "Optimum doping profile for minimum ohmic resistance and high-breakdown voltage". In: IEEE Transactions on Electron Devices 26 (1979), pp. 243-244. URL: https: .

M. Kaneko and T. Kimoto. "High-Temperature Operation of n - and p -Channel JFETs Fabricated by Ion Implantation Into a High-Purity Semi-Insulating SiC Substrate". In: IEEE Electron Device Letters 39.5 (2018), pp. 723-726.

Constantin Csato et al. "Energy filter for tailoring depth profiles in semiconductor doping application". In: Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms 365 (2015), pp. 182-186.

Roland Rupp et al. "Alternative Highly Homogenous Drift Layer Doping for 650 V SiC Devices". In: Materials Science Forum 858 (2016), pp. 531-534.

L. Di Cioccio et al. "Silicon carbide on insulator formation by the Smart-Cut Đ process". In: Materials Science and Engineering: B 46.1 (1997), pp. 349-356.

M. Levy et al. "Fabrication of single-crystal lithium niobate films by crystal ion slicing". In: Applied Physics Letters 73.16 (1998), pp. 2293-2295.

Bing Hu et al. 2018 International Flexible Electronics Technology Conference (IFETC): 7-9 Aug. 2018. Piscataway, NJ: IEEE, 2018. ISBN: 9781538633571.

Marko Swoboda et al. "Laser Assisted SiC Wafering Using COLD SPLIT". In: Materials Science Forum 897 (2017), pp. 403-406.

David J. Meyer et al. "Epitaxial Lift-Off and Transfer of III-N Materials and Devices from SiC Substrates". In: IEEE Transactions on Semiconductor Manufacturing 29.4 (2016), pp. 384-389.

Stephen W. Bedell et al. "Layer transfer by controlled spalling". In: Journal of Physics D: Applied Physics 46.15 (2013), p. 152002.

J. A. Bennett et al. "Complete surface exfoliation of by - and -coimplantation". In: Applied Physics Letters 76.22 (2000), pp. 3265-3267.

Shifei Han et al. "Laser slicing of wafers based on picosecond laser-induced micro-explosion via multiphoton processes". In: Optics & Laser Technology 154 (2022), p. 108323.

Jian Li et al. "Direct bonding of silicon carbide with hydrofluoric acid treatment for high-temperature pressure sensors". In: Ceramics International 46.3 (2020), pp. 3944-3948.

Fengxuan Wang et al. "Low-Temperature Direct Bonding of SiC to Si via Plasma Activation". In: Applied Sciences 12.7 (2022), p. 3261.

J. Grisolia et al. "Kinetic aspects of the growth of hydrogen induced platelets in SiC". In: Journal of Applied Physics 87.12 (2000), pp. 8415-8419.

L.-J. Huang et al. "Onset of blistering in hydrogen-implanted silicon". In: Applied Physics Letters 74.7 (1999), pp. 982-984.

R. B Gregory, O.W Holland, D.K. Thomas, T.A Wetterroth, S.R Wilson. "The effect of Damage on Hydrogen-implant-induced thin-film seperation from Bulk Silicon Carbode." In: Mat. Res. Soc. Symp. Proc. 572 (1999), pp. 33-38.

V. P. Amarasinghe et al. "Properties of Implanted as Related to Exfoliation of Thin Crystalline Films". In: ECS Journal of Solid State Science and Technology 3.3 (2014), P37-P42.

Voshadhi Pansilu Amarasinghe. "Single Crystalline Silicon Carbide Thin Film Exfoliation for Power Device Applications". Ph.D. Dissertation. Graduate School-New Brunswick Rutgers, The State University of New Jersey, 2015.

Madan Sharma et al. "Blistering kinetics in H-implanted 4H-SiC for large-area exfoliation". In: Current Applied Physics 31 (2021), pp. 141-150.

Volker Häublein and Heiner Ryssel, eds. IIT 2018 proceedings: 2018 22nd International Conference on Ion Implantation Technology, September 16-21, 2018, Congress Centrum, Würzburg, Germany. Piscataway, NJ: IEEE, 2018. ISBN: 9781538668290.

Nidec Machine Tool Corporation. Room Temperature Wafer Bonding Machine BOND MEISTER. NMTJwafer_bonding_machine/. Accessed: 2024-08-30.

Kensuke Ide et. al. "Wafer Bonder Applicable to Devices in Various Fields,Mitsubishi Heavy Industries Technical Review Vol. 48 No.1(2011)". In: Mitsubishi Heavy Industries Technical Review 48.1 (2011), pp. 48-52.

et. al. S. Langa. "Room Temperature bonding for Vacuum applications : Climatic and long time tests". In: (2004).

Zheng Cui. "Wafer Bonding". In: Encyclopedia of Microfluidics and Nanofluidics. Ed. by Dongqing Li. Boston, MA: Springer US, 2013, pp. 1-7.

J. Wong-Leung et al. "Ion implantation in 4H-SiC". In: Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms 266.8 (2008), pp. 1367-1372.

Manuel Belanche et al. "Aluminum channeling in by high-energy implantation above 10 MeV". In: Materials Science in Semiconductor Processing 179 (2024), p. 108461.

Kazuya Yamamura et al. "High-Integrity Finishing of 4H-SiC (0001) by Plasma-Assisted Polishing". In: Advanced Materials Research 126-128 (2010), pp. 423-428.

K. Yamamura et al. "Plasma assisted polishing of single crystal SiC for obtaining atomically flat strain-free surface". In: CIRP Annals 60.1 (2011), pp. 571-574.

Guillaume Gelineau et al. "Evaluation of Crystal Quality and Dopant Activation of Smart CutTM - Transferred 4H-SiC Thin Film". In: Materials Science Forum 1089 (June 2023), pp. 71-79.

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The original version of this eBook is available on https://www.scientific.net/book/substrates-and-substrates-manufacturing/978-3-0364-1761-5

Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 27-35

doi: 10.4028/p-F06BzD

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-03-19

Accepted:
2025-03-19

Online:
2025-09-04

Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

The original version of this paper is available on https://www.scientific.net/MSF.1156.27.pdf

Yafei Liu , Campbell Bouch , Pete Schunemann , Ryan Philpott , Mary Safko , Danielle Hamann , Mason Dupre and Andrew Goldberg

Onsemi, 55 Executive Drive, Hudson, NH 03051, USA

yafei.liu@onsemi.com, campbell.bouch@onsemi.com, pete.schunemann@onsemi.com, mason.dupre@onsemi.com, andrew.goldberg@onsemi.com

Keywords: SiC, PVT, Crystal Growth, Characterization, X-Ray Topography, Defects

Abstract

Axial sliced samples from boules grown by PVT method were characterized by lab-based X-ray topography systems. Valuable information about dislocation behaviors during crystal growth was revealed. TSD/TMD propagation during PVT growth was studied. The different TSD/TMD propagation directions inside and outside the facet region were identified as the direct cause of the reduced TSD/TMD density at the facet boundary on some c-plane wafers. A defect reduction mechanism was proposed based on this discovery. It was observed that TSDs/TMDs were emitted by a void structure formed during crystal growth, which explained the elevated TSD/TMD density in the center regions of some wafers. The formation mechanism of such defect is different from the previous studies and remains under investigation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.27.pdf

Technological developments in the past decade have driven demand for semiconductor devices that can meet the needs of high-power systems. Traditional silicon (Si)-based power electronic devices are reaching their performance limits. To address the demand of high-power systems, silicon carbide materials have become one of the most promising semiconductor materials with their superior properties such as high saturation electron drift velocity, high thermal conductivity, and high breakdown electric field. As a result, SiC -based systems can achieve much lower losses and faster switching speed with smaller geometries than traditional Si -based systems. Commercially available SiC devices have been successfully adopted in many high temperature, high voltage, and high frequency applications. In recent years, the increased demand of electric vehicles has driven the adoption of SiC power electronic devices such as main traction inverters. Together with other applications for energy infrastructure and the most recent rising demand for data centers that are reliant on artificial intelligence (AI) technology, SiC systems have been giving benefits in a way of saving very large amounts of energy every day.
SiC devices have shown great success in industry. However, SiC materials quality is imperative to improving device yield, reducing the cost, and developing devices that can be used in higher power solutions. Currently, various defects exist in SiC materials grown by physical vapor transport (PVT), which is the most widely used method in industry. 0 -dimensional defects include interstitial or substitutional atoms and vacancies. 1-dimensional defects refer to all kinds of dislocations including basal plane dislocations (BPDs), threading edge dislocations (TEDs), threading screw dislocations (TSDs), and threading mixed dislocations (TMDs). 2-dimentional defects are thin layers of stacking faults. 3-dimentional defects also exist such as voids and inclusions. Various characterization methods on crystalline defects are available including hot chemical etching, optical scans, electron microscopy, and X-ray topography (XRT) [1]. In this study, XRT is mainly used to non-destructively characterize the defects in materials grown by PVT method.

The majority of XRT reported works were conducted at synchrotron facilities around the world [28]. However, the limited access to very few synchrotron sources is not able to meet the test requirements from daily research and production. In this study, Rigaku XRTMicron, a lab-based XRT system was used to characterize the defects in axial sliced samples from boules grown by PVT method. XRT results were used to reveal the causes of distinct dislocation distribution in some c-plane SiC wafers.

Experiments and Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1156.27.pdf

Experimental PVT growth was conducted and some c-plane wafers with an off-cut angle of 4 degrees were cut, chemical mechanical polished (CMP) and characterized with XRT using 0008 reflection geometry on the Si side. Copper target was used as the X-ray source and the K radiation was selected and tuned by a special purpose multi-layer mirror for Cu target. TSD maps were generated by XRT Toolbox software, an automatic XRT data processing tool to generate defect analysis reports. Axial slices of PVT grown 4H-SiC boules were cut along [11-20] direction as shown in Fig. 1. Then the axial samples were fine ground on both sides down to the thickness of . The axial samples were inspected by XRT using 0004 transmission geometry with molybdenum (Mo) Ka1 radiation with another special purpose multi-layer mirror for Mo target. Topography images were enhanced in Fiji ImageJ software to observe defectivity.

Fig. 1. Axial slice sample preparation from a PVT grown SiC boule.

Fig. 1. Axial slice sample preparation from a PVT grown SiC boule.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1156.27.pdf

Reduced TSD Density at the Facet Boundary. Fig. 2 shows a cropped TSD density map of a 150mm c-plane wafer. A reduced TSD density region is observed at the facet boundary marked by a red circle, which was identified by optical inspection of the different coloring effect from different nitrogen ( N ) doping. To investigate the cause of such TSD distribution, an axial sample prepared from another boule with the same growth process was inspected. Fig. 3 is a cropped overall XRT image of the axial sample. On the left side there are some contours because the lattice bending effect is giving some off-peak regions and the measurement recipe did not accommodate the change in this in-plane rotation. According to the and criteria [9], only TSDs or TMDs show strong contrast as linear features in the 0004 topography images. In some selected enlarged images shown in Fig. 4, dislocation behaviors that have been studied previously [10] such as replication from the seed, nucleation at the seed interface, deflection, climbing, and annihilation.

Fig. 2. A cropped TSD density map of a c-plane wafer showing a reduced TSD density around at the edge of the facet region. Note: The scale bar was removed, and the heat map was generated with an arbitrary color scale due to confidentiality.

Fig. 2. A cropped TSD density map of a c-plane wafer showing a reduced TSD density around at the edge of the facet region. Note: The scale bar was removed, and the heat map was generated with an arbitrary color scale due to confidentiality.

Fig. 3. Cropped overall XRT image of the axial sample to study the cause of TSD reduction at the facet boundary. Note: Contours on the left side of the image are caused by lattice bending effect. The scale bar was removed due to confidentiality.

Fig. 3. Cropped overall XRT image of the axial sample to study the cause of TSD reduction at the facet boundary. Note: Contours on the left side of the image are caused by lattice bending effect. The scale bar was removed due to confidentiality.

Fig. 4. Enlarged XRT images showing different dislocation behaviors of: (a) replication from the seed; (b) nucleation at the seed interface (dark horizontal linear contrast); (c) deflection; (d) climbing and (e) annihilation when dislocations with Burgers vectors of opposite signs meet. Note: The scale bar was removed due to confidentiality.

Fig. 4. Enlarged XRT images showing different dislocation behaviors of: (a) replication from the seed; (b) nucleation at the seed interface (dark horizontal linear contrast); (c) deflection; (d) climbing and (e) annihilation when dislocations with Burgers vectors of opposite signs meet. Note: The scale bar was removed due to confidentiality.

Fig. 5 shows two selected regions from the XRT image near the facet boundary. The facet boundary can be precisely depicted by an image from the scanner overlapping on the XRT image. From Fig. 5 (b) and (c), it can be observed that the TSDs inside the facet are strictly along c-direction. However, the TSDs outside the facet region tend to replicate towards other directions. Also, the change in the TSD orientations occurs precisely on the facet boundary. This is true for everywhere along the facet boundaries in this sample.

From this discovery, a schematic shown in Fig. 6 can be used to illustrate the cause of the reduction in TSD density at the facet boundary. It is known that a facet forms at a very early stage of PVT growth [8] due to a different growth rate along different directions. Step flow is the dominant mechanism outside the facet region, while spiral growth occurs mainly in the facet region. During crystal growth, the step flow direction is from the facet region to the rest of the crystal. This step flow can affect the propagation of TSDs so that the directions of TSDs bend towards the step flow direction, as shown in Fig. 6 (a). After a wafer is cut from the boule, the local TSD density at the facet boundary is lower than the nearby regions, shown in Fig. 6 (b). This mechanism is based on the XRT characterization and explains the direct cause of TSD reduction at the facet boundary.

Fig. 5. (a) XRT images were magnified at two different positions on the sample near the facet boundary. (b) The facet boundary was denoted as dark line where the upper left is outside the facet and the lower right is inside the facet. (c) A similar image from another position in which the upper right is inside the facet and the lower left is outside the facet. Note: The scale bar was removed due to confidentiality.

Fig. 5. (a) XRT images were magnified at two different positions on the sample near the facet boundary. (b) The facet boundary was denoted as dark line where the upper left is outside the facet and the lower right is inside the facet. (c) A similar image from another position in which the upper right is inside the facet and the lower left is outside the facet. Note: The scale bar was removed due to confidentiality.

Fig. 6. A schematic showing the cause of TSD reduction at the facet boundary. (a) A perspective view of the region near the facet. (b) A top view of the wafer cut from the boule.

Fig. 6. A schematic showing the cause of TSD reduction at the facet boundary. (a) A perspective view of the region near the facet. (b) A top view of the wafer cut from the boule.

Elevated TSD Density in the Center of the Wafer. Fig. 7 shows a comparison between a production wafer and an engineering wafer with a consistent color scale. In Fig. 7 (b), elevated TSD density can be observed in the center of the wafer. To reveal the source of these TSDs, the same characterization work was done on an axial sample cut from the same boule. Fig. 8 is a magnified XRT image from the same region of the sample. In the red circles mark some 3-dimensional defect contrast spawning TSDs to the downstream of the crystal growth. However, no obvious cause of such defects can be seen in the same image.

Fig. 7. Cropped TSD density maps of (a) a production c-plane wafer and (b) an engineering wafer showing elevated TSD density in the center. Note: The scale bar was removed, and the heat map was generated with an arbitrary color scale due to confidentiality.

Fig. 7. Cropped TSD density maps of (a) a production c-plane wafer and (b) an engineering wafer showing elevated TSD density in the center. Note: The scale bar was removed, and the heat map was generated with an arbitrary color scale due to confidentiality.

Fig. 8. Magnified XRT image taken from the middle region of the sample. Note: The scale bar was removed due to confidentiality.

Fig. 8. Magnified XRT image taken from the middle region of the sample. Note: The scale bar was removed due to confidentiality.

To confirm the structure of the 3-dimensional defects in the XRT image, optical microscopy (OM), scanning electron microscopy (SEM) and focused ion beam (FIB) were employed. Fig. 9 (a) is an OM image showing hexagonal shapes of the defect on a c-plane wafer with high TSD density in the middle region. For a more detailed view, Fig. 9 (b) shows the SEM image of one of the hexagonal shapes. It is confirmed that such 3-dimensional features have void structures with the size of around . Furthermore, Fig. 9 (d) shows the cross-sectional view of the void by imaging the sample prepared by FIB at the location shown in Fig. 9 (c). It is found that the void defect started from a smaller size and developed larger before being overgrown.

Fig. 9. (a) Optical microscopic image of hexagonal shaped defects observed in a c-plane wafer with high TSD density in the middle. (b) SEM image of the 3D feature showing a void structure with a size around . (c) The location of FIB analysis conducted on the void structure. (d) The crosssectional view of the void structure.

Fig. 9. (a) Optical microscopic image of hexagonal shaped defects observed in a c-plane wafer with high TSD density in the middle. (b) SEM image of the 3D feature showing a void structure with a size around . (c) The location of FIB analysis conducted on the void structure. (d) The crosssectional view of the void structure.

Several studies have been conducted on the void defects in SiC crystals. One study [11] has indicated that when a void forms on top of a micropipe, the micropipe can be dissociated into multiple TSDs after the void is overgrown. Together with another study [12], it has been shown that the void can be originated and transported from the backside of the seed crystal. A recent study [13] has indicated that the improper seed mounting can be the root cause of the formation of hexagonal voids. However, observations in these studies were not made in this sample. While further analysis on this sample is in progress, the formation mechanism of such void defects in this study remains unclear.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.27.pdf

In this paper, Lab-based XRT was demonstrated to be a useful characterization method on axial samples from SiC boules grown by PVT method. Dislocation behaviors during crystal growth can be observed, and explanations of the change in dislocation density in SiC substrate wafers can be made. It is found that the change in TSD propagation direction at the facet boundary, which is affected by the step flow direction, is the direct cause of reduced TSD density near the facet region. It is also found that void defects are responsible for the elevated TSD density in the center of some wafers. However, some key observations from previous studies are not made to confirm the void formation mechanism, which is still under investigation.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.27.pdf

B. Raghothamachar, M. Dudley, X-Ray Topography, Materials Characterization, ASM International 2019.

T. Ailihumaer, H. Peng, Y. Liu, B. Raghothamachar, M. Dudley, Characterization of Dislocations in 4H-SiC Single Crystals at the Initial Growth Stage by Synchrotron X-ray Topography, ECS Transactions 98(6) (2020) 125.

Q. Cheng, T. Ailihumaer, H. Peng, Y. Liu, B. Raghothamachar, M. Dudley, Analysis of Dislocations in PVT-Grown 6H-SiC through Grazing-Incidence X-Ray Topographic Images and Ray-Tracing Simulation, ECS Transactions 98(6) (2020) 133.

H. Peng, Y. Liu, T. Ailihumaer, B. Raghothamachar, M. Dudley, K. Sampayan, S. Sampayan, Investigation of Dislocations in 6H-SiC Axial Samples Using Synchrotron X-Ray Topography and Ray Tracing Simulation, ECS Transactions 104(7) (2021) 147-155.

Q.Y. Cheng, H.Y. Peng, S.S. Hu, Z.Y. Chen, Y.F. Liu, B. Raghothamachar, M. Dudley, RayTracing Simulation Analysis of Effective Penetration Depths on Grazing Incidence Synchrotron X-Ray Topographic Images of Basal Plane Dislocations in 4H-SiC Wafers, Materials Science Forum, Trans Tech Publ, 2022, pp. 366-370.

H. Peng, Y. Liu, Z. Chen, Q. Cheng, S. Hu, B. Raghothamachar, M. Dudley, K. Sampayan, S. Sampayan, Synchrotron X-ray topographic characterization of dislocations in axial samples, Journal of Crystal Growth 579 (2022) 126459.

Z. Chen, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar, M. Dudley, Analysis of strain in ion implanted by fringes observed in synchrotron X-ray topography, Journal of Crystal Growth 627 (2024) 127535.

S. Hu, Y. Liu, Q. Cheng, Z. Chen, X. Tong, B. Raghothamachar, M. Dudley, Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals, Journal of Crystal Growth 628 (2024) 127542.

G. Dhanaraj, B. Raghothamachar, M. Dudley, Growth and Characterization of Silicon Carbide Crystals, in: G. Dhanaraj, K. Byrappa, V. Prasad, M. Dudley (Eds.), Springer handbook of crystal growth, Springer Science & Business Media 2010, p. 797.

F.Z. Wu, H.H. Wang, S.Y. Byrapa, B. Raghothamachar, M. Dudley, E. Sanchez, D.M. Hansen, R. Drachev, S.G. Mueller, M.J. Loboda, Synchrotron X-ray Topography Studies of the Propagation and Post-Growth Mutual Interaction of Threading Growth Dislocations with ccomponent of Burgers Vector in PVT-Grown 4H-SiC, Materials Science Forum, Trans Tech Publ, 2012, pp. 343-346.

T.A. Kuhr, E.K. Sanchez, M. Skowronski, W.M. Vetter, M. Dudley, Hexagonal voids and the formation of micropipes during SiC sublimation growth, Journal of Applied Physics 89(8) (2001) 4625-4630.

T. Fujimoto, H. Tsuge, M. Katsuno, S. Sato, H. Yashiro, H. Hirano, T. Yano, A possible mechanism for hexagonal void movement observed during sublimation growth of SiC single crystals, Materials Science Forum, Trans Tech Publ, 2013, pp. 577-580.

A. Arora, A. Patel, B.S. Yadav, A. Goyal, O.P. Thakur, A.K. Garg, R. Raman, Study on evolution of micropipes from hexagonal voids in crystals by cathodoluminescence imaging, Microscopy and Microanalysis 27(1) (2021) 215-226.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/substrates-and-substrates-manufacturing/978-3-0364-1761-5

Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 37-41

doi: 10.4028/p-sTgt8T

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-08-09

Accepted:
2025-08-11

Online:
2025-09-04

New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

The original version of this paper is available on https://www.scientific.net/MSF.1156.37.pdf

C. Calabretta , N. Piluso , S. Boninelli , C. latosti , E. Roy , D. Calabriso , L. Lilja , A. Ellison , C. Riva , F. lucolano and A. Severino

1STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy

CNR-IMM, Strada VIII, 5, 95121 - Catania, Italy

STMicroelectronics, 153 rue des Douets 37100 Tours, France

STMicroelectronics Silicon Carbide AB, Ramshällsvägen 15 SE-602 38 Norrköping, Sweden

cristiano.calabtretta01@st.com, nicolo.piluso@st.com, simona.boninelli@imm.cnr.com, christhophe.iatosti@st.com, emmanuel.roy@st.com, daniele.calabriso@st.com,

mandrea.severino@st.com

Keywords: GaN, SiC, MOCVD, Photoluminescence, Optical Microscopy.

Abstract

This work explores the application of gallium nitride ( GaN )-based solid-state devices for high-power, high-frequency, and high-temperature technologies. It presents an in-depth study of GaN on semi-insulating SiC substrates. The study demonstrates, through bow range investigation, optical microscopy, and X-ray diffraction (XRD), that by adapting growth parameters from those used for Si substrates to those suitable for SiC substrates, it is possible to achieve high-quality crystalline MOCVD growth both under on-axis and -axis substrate orientations.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.37.pdf

Recently, gallium nitride (GaN)-based solid-state devices have demonstrated extraordinary effectiveness for high-power, high-frequency, and high-temperature technology. The basic properties of the AlGaN/GaN material combination make it an excellent choice for microwave devices. Silicon is the most cost-effective adopted substrate for large-scale fabrication [1]. However, interfacial stress, dislocation density and melt-back etching caused by Si out-diffusion remain significant disadvantages. GaN on SiC offers superior thermal performance and fewer defects due to better lattice and thermal matching but comes at a higher cost and with manufacturing difficulties. A further challenge is represented by the common use of SiC off-axis substrates. In the off-axis orientation the two orthogonal directions in the vicinal c-plane, along [11-20] and [1-100] (with and without periodic surface steps, respectively) can stimulate anisotropic epitaxy and amplify the effects of the different thermal expansion rates during the cooling process post-growth, potentially causing additional strain and cracking in the GaN layer [2-3].

Materials and Methods

The original version of this paper is available on https://www.scientific.net/MSF.1156.37.pdf

In this work Trimethylgallium (TMGa), Trimethylaluminum (TMAl) and ammonia ( ) were used as the precursors for Gallium (Ga), Aluminium (Al) and Nitrogen (N) sources respectively. HEMT layer was carried out on 3 processes where the deposition of a GaN buffer layer at was followed by the growth of 16 nm thick AlGaN layer. The epitaxial growth of GaN was conducted employing three distinct methodologies: the Standard Process (SP) method adhered to the established protocol for GaN epitaxy on Si substrates. Subsequently, a specialized procedure was formulated for semi-insulating SiC substrates, which was further bifurcated into two stages,
designated as P1 and P2 on temperature early stage growth parameters. Within the specialized SiC procedure, one of the stages was subjected to trials on SiC substrates measuring , both onaxis and off-axis, as well as on a substrate. Additionally, a control epitaxial growth on a Silicon substrate was performed to serve as a reference point. The resulting HEMT layer structure AlGaN/GaN were optically characterized by means of flatness analysis, Photoluminescence (PL), Optical microscopy and XRD, to characterize the bow range of wafer as well as PL emission spectra.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1156.37.pdf

Upon wafer flatness evaluation, displayed in Fig. 1, distinct behaviors were observed. Adopting the conventional SP process, GaN on SiC wafer exhibited a curvature with a bow range of , whereas the Si wafer demonstrated a bow range of . In the case of on axis SiC substrates, the process variations resulted in flatness values susceptible to thinner SiC substrate thicknesses due to augmented thermal stress during cooling rate, ranging from to in P1 and from to in P2 when transitioning from a to a SiC substrate. Among all processes, it is worth noting that off-axis oriented GaN on SiC growths resulted in the lowest bow range as high as in the P1 and in the revised process P2. GaN on Si range was, instead, increased in both processes to and .

Full Automated Optical microscopy inspection of the wafers revealed a high percentage of Total Usable Area (TUA). Particularly in Fig. 2a, the inspections indicated that the highest TUA was in P2 with defects density. It is noted that the surface remains smooth in the case of GaN on SiC (Fig. 2b), while, in the case of GaN on Si , onset of microcracking is disclosed as the stress can no longer be accommodated elastically, leading to plastic deformation and the generation of slip line and cracks as exhibited in Fig 2c. Full wafer PL analysis, performed with a excitation laser, revealed that the off-axis GaN on SiC underwent P2 growth exhibited a standard deviation in the GaN signal intensity of in band edge spectral region.

Fig. 1 a) Bow maps for 150 mm GaN on SiC and GaN on Si grown under SP, P1 and P2 processes.

Fig. 1. a) Bow maps for 150 mm GaN on SiC and GaN on Si grown under SP, P1 and P2 processes.

As depicted in Fig. 3a, the spatial map of the emission wavelength indicates a localized bandgap emission peak at . As attested for GaN grown under P2 in the PL reported spectra, the emission intensities exhibit variations that rely on crystallographic orientation. Peak intensities are demonstrably higher for the on-axis GaN on SiC sample compared to the off-axis sample, suggesting that the misorientation in the off-axis sample may intensify lattice mismatch and consequently increase the concentration of dislocations. As a result, the off-axis sample manifested a reduced PL intensity. Conversely, for the off-axis, it was attested the rising in PL signal in the intrabandgap region in Fig. 3b. The emission map delineates a specific area indicative of intrabandgap recombination from 500 to 650 nm . This spectral region corresponds to the commonly observed yellow luminescence (YL) band associated with defects in GaN. Potential origins of the YL band in GaN include dislocations as well as various point defects such as Ga vacancies or complexes, such as or and C related point defects [4-6]. The uniformity of this signal across the wafer is quantified by a standard deviation of , with a marginal intensification noted towards the periphery of the wafer. Concurrently, the presence of Fabry-Perot oscillations indicates that uniformity in the arrangement of the grown layers is preserved.

The analyses along the XRD (002) axis revealed that the on-axis samples exhibited rocking curves of 266.04 arcseconds and 281.16 arcseconds for the P1 and P2 processes, respectively. In contrast, the off-axis samples showed variations of 331.92 arcseconds and 333.36 arcseconds. These values are competitive with the parameters found for both on axis and off axis configuration within literature [7-10].

Fig. 2 a) optical microscopy map and image b) for off-axis GaN on SiC grown under P 2 and an image.

Fig. 2. a) optical microscopy map and image b) for off-axis GaN on SiC grown under P 2 and an image.

Fig. 3 a) of GaN on Si under P2; b) Intensity and wavelength PL maps over band edge for off-axis GaN on SiC grown under P2 with band edge related spectra of wafers grown under P2. b) Intrabandgap map for off-axis GaN on SiC grown under P2 and related spectra for wafer grown under P 2 ; c) Al fraction map for for off-axis GaN on SiC grown under P 2 and values for other wafers.

Fig. 3. a) of GaN on Si under P2; b) Intensity and wavelength PL maps over band edge for off-axis GaN on SiC grown under P2 with band edge related spectra of wafers grown under P2. b) Intrabandgap map for off-axis GaN on SiC grown under P2 and related spectra for wafer grown under P 2 ; c) Al fraction map for for off-axis GaN on SiC grown under P 2 and values for other wafers.

The compositional analysis depicted in Fig. 3c illustrates that the off-axis sample from process P2 contains the Al fraction of . This data suggests that the P2 facilitates a higher Al incorporation rate, and exhibit an upward trend in the Al fraction from process P 1 to process P 2 . In light of the results, the research presented herein provides valuable insights into the optimization of 150 mm GaN on SiC MOCVD growth, establishing the off-axis SiC substrate as a promising contender for the improvement of GaN on SiC High Electron Mobility Transistors (HEMTs).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.37.pdf

Within this work, High Electron Mobility Transistor (HEMT) layer deposition involved three processes, starting with a GaN buffer layer at , followed by a 16 nm thick AlGaN layer. GaN epitaxial growth was conducted using three methodologies: the Standard Process (SP) for GaN on Si substrates, and two specialized procedures (P1 and P2) for semi-insulating SiC substrates, differing in early thermal process ramps. Trials were conducted on and substrates, both on-axis and off-axis, with a control growth on a Silicon substrate for reference. Wafer flatness evaluations revealed distinct behaviors: GaN on SiC exhibited a bow range of , while GaN on Si showed . Process variations affected flatness, especially in thinner SiC substrates due to thermal stress. Off-axis GaN on SiC showed the lowest bow ranges ( in P1 and in P2). Optical microscopy indicated high TUA, with P2 achieving 99.57% TUA (grid ) and defect density. GaN on SiC surfaces remained smooth, while GaN on Si exhibited microcracking. PL analysis revealed a standard deviation of in GaN signal intensity for off-axis GaN on SiC under P2. Emission intensities varied with crystallographic orientation, with higher intensities in on-axis samples. The emission map indicated intrabandgap recombination, associated with defects, and a standard deviation of in signal uniformity. XRD analysis showed rocking curves of 266.04 arcseconds and 281.16 arcseconds for on-axis samples (P1 and P2), and 331.92 arcseconds and 333.36 arcseconds for off-axis samples. Compositional analysis indicated higher Al incorporation in P 2 , with an Al fraction of . These findings provide valuable insights into optimizing 150 mm GaN on SiC MOCVD growth, highlighting the potential of offaxis SiC substrates for improving GaN on SiC HEMTs.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.37.pdf

Cai, Yuefei, et al. "Strain analysis of GaN HEMTs on (111) silicon with two transitional AlxGal-xN layers." Materials 11.10, 1968, (2018)

Yao, Lei, et al. "An Inductive Coupling Based CMOS Wireless Powering Link for Implantable Biomedical Applications." International Journal of Electronics and Communication Engineering 6.9 (2012): 931-934

Drechsel, P., and H. Riechert. "Strain controlled growth of crack-free GaN with low defect density on silicon ( 1111 ) substrate." Journal of crystal growth 315.1, 211-215, (2011).

Reshchikov, Michael A., and Hadis Morkoç. "Luminescence properties of defects in GaN." Journal of applied physics (2005), 97.6.

Calabretta, Cristiano, et al. "GaN Cap UV Spectroscopy Assessment in AlGaN/GaN HEMT." Solid State Phenomena 36, 27-31, (2024).

Scandurra, Antonino, et al. "Two-dimensional electron gas isolation mechanism in Al0. 2Ga0. heterostructure by low-energy Ar, C, Fe ion implantation." Applied Surface Science 674 (2024): 160885.

Su, Chung-Wang, et al. Solid-State Electronics 179, 107980, (2021).

Feng, Sirui, et al. "Strain Release in GaN Epitaxy on Off-Axis 4H-SiC." Advanced Materials 34.23, 2201169, (2022).

Cho, E., et al. "Impact of AlN nucleation layer on strain in GaN grown on 4H-SiC substrates." Journal of crystal growth 371, 45-49, (2013).

Susanto, Iwan, Ken-Yuan Kan, and Song Yu. "Temperature effects for GaN films grown on 4H-SiC substrate with miscutting orientation by plasma-assisted molecular beam epitaxy." Journal of Alloys and Compounds 723 (2017): 21-29.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/substrates-and-substrates-manufacturing/978-3-0364-1761-5

Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 43-48

doi: 10.4028/p-3oQwEM

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-13

Accepted:
2025-08-14

Online:
2025-09-04

Process Gas Control for High-Resistance HPSI-SiC Growth

The original version of this paper is available on https://www.scientific.net/MSF.1156.43.pdf

Department of Advanced Materials Engineering, Dong-Eui University, 176, Eomgwang-ro, Busanjin-gu, Busan, Korea

sjlee@senic.co.kr, shkim@senic.co.kr, cylee@senic.co.kr, djhpark@senic.co.kr, ejwchoi@senic.co.kr, fjgkim@senic.co.kr, krku@senic.co.kr, dlrldnr7774@naver.com, i*leewj@deu.ac.kr

Keywords: High resistivity, HPSI-SiC, PVT, Hydrogen

Abstract

In this study, we tried to grow SiC ingots with high resistivity and polytype stability with adoption hydrogen mixed gas flow to the PVT method. Three different types of growth atmosphere of ratio: and were employed. The polytype inclusion, crystal shape and transparency, and their resistivity were systematically investigated by UVF images, exposing backlighting, and high resistivity analysis using COREMA (Contactless Resistivity Mapper), respectively. The SiC ingot grown with adoption exhibited a suppression of polytype inclusion, a convex shape and a lower resistivity. In contrast, the SiC ingot with more higher ratio of than that of shows no polytype inclusion and highest resistivity of . The growth atmosphere of relative higher ratio in SiC crystal growth could be led the way to manufacture HPSI (high-purity semi-insulating)-SiC single crystal with polytype stability.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.43.pdf

The next generation of wireless infrastructure will depend on wide band gap semiconductors owing to their unique materials properties, including: their large bandgap, high thermal conductivity, and high breakdown field [1,2]. To ensure the competitiveness of next generation of materials, it is essential to make SiC MESFET and GaN HEMT microwave devices more suitable for a wide range of applications. The application of high-resistivity HPSI 4H-SiC to microwave devices is absolutely indispensable. To ensure stable quality and high resistivity values of HPSI (high-purity semi-insulating)-SiC single crystal, it is necessary to suppress nitrogen incorporation during growth [3-5]. However, in the universal PVT method, nitrogen flow is essential for polytype stability. Therefore, we aim to obtain high-resistivity HPSI-SiC ingots while maintaining polytype stability without nitrogen flow by applying a new gas flow. To solve the problems caused by such nitrogen inclusion, we apply a hydrogen mixed gas atmosphere to the PVT method to obtain HPSI-SiC ingots with stabilized polytype and high resistivity characteristics [6]. The occurrence of polytype instability is caused by stacking defects resulting from the instability of the ratio due to the Si -rich vapor source sublimated from the raw material powder generated during PVT growth. In a previous study, hydrogen added to the ambient gas during the PVT process can easily diffuse through the graphite crucible walls. Since the reaction rate at typical PVT growth temperature is fast, hydrogen will reach equilibrium status with the graphite hot zone elements. This will result in an increased concentration of gaseous hydrocarbons, mostly , in the growth ambient, as compared to the case of growth in pure argon. Hydrogen will also interact with the SiC charges producing SiH and via the reaction . Through this chemical reaction, we aim to suppress the occurrence of stacking faults by increasing carbon-bearing species ( ) in the Si-rich atmosphere and controlling the ratio to [7-9].

In addition, since the application of gas during growth gives rise to the effect toward etching impurities on the surface of the growth ingot, high-quality SiC ingots can be obtained [10,11].

Experiments

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As shown in Table 1, three types of PVT growth were performed. At a conventional nitrogen and inert gas Ar atmosphere ( ), Method A with gas ( ) and Method B with gas (H/Ar) were added. We tried to find out whether it is possible to achieve polytype stability while maintaining high resistivity during addition of hydrogen mixed gas without nitrogen and to find the optimal mixed gas ratio. Except for the gas flow condition, the hot zone design was identical. As shown in Fig. 1, growth conditions other than the gas atmosphere were the same. The SiC crystals were grown using a off seed as the seed crystal. Three SiC seed crystals were prepared by wafering process from the same ingot grown by under growth temperature of . The mixed inert gas of torr was continuously supplied for 100 hour. The axial thermal gradient of the SiC crystals during the growth is estimated at the range of .

The image of UVF (ultra-violet fluorescence) of the growth ingot was obtained to observe polytype inclusion and their transparency of the ingot was investigated to decide nitrogen incorporation concentration. Resistivity measurements conducted on the three SiC ingots grown after growth run by a Lehighton Resistivity Measurement system(1510EB). In addition, high resistivity measurements were also performed using COREMA (Contactless Resistivity Mapping).

Table 1. Gas flow condition for three different SiC crystal growth using by addition of different gas ratio.

| Conventional | Modified A | Modified B
Gas Flow | For power devices | H/Ar ratio 10% | H/Ar ratio 30%

Fig. 1. The growth condition for SiC single crystal.

Fig. 1. The growth condition for SiC single crystal.

Results and Discussion

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Grown ingot and polytype inclusion
To investigate the effect of hydrogen mixed gas application on polytype incorporation and resistivity characteristics, three PVT growths were performed under identical growth conditions excluding the gas atmosphere. The growth results of the three ingots are shown in Fig. 2. Here, upper and bottom blueish regions of SiC ingots shows illusion caused by interference. First, the UVF measurement results showed that polytype incorporation was suppressed in a nitrogen atmosphere at conventional growth resulting from the effect of suppression of polytype incorporation. In Method A, since the ratio was not optimized due to the absence of nitrogen and low hydrogen mixed gas ratio, polytype incorporation associated with orange color observed. However, in Method B, it was confirmed that the polytype was suppressed due to a relatively high hydrogen mixed gas ratio. This
implies that the ratio is well controlled even under a hydrogen mixed gas atmosphere. Secondly, the shape of the ingot was investigated. The convex shape of ingot suppresses the formation of irregular terraces on the crystal surface. Therefore, it allows uniform diffusion of growth sources and high-quality SiC ingots can be obtained. In the conventional growth under nitrogen atmosphere, the optimized vertical and horizontal temperature gradients produce a convex shape ingot. When hydrogen mixed gas is added in the growth section, generation of a decrease in growth temperature and the stability of the crystal shape. This issue can be secured by controlling the growth power.

Finally, the transparency of the SiC ingots was evaluated. The transparency was conducted by exposing the backlight to the SiC ingot after outer diameter processing of SiC ingot itself. In the conventional growth, there is no polytype inclusion in the whole ingot, showing a single color. However, homogenous greened color of the ingot represents a nitrogen incorporation. In Method A, the greened color within SiC ingot is less than that of the conventional one, however, it is still mixed with nitrogen incorporation. In Method B, since growth under a high hydrogen mixed gas ratio, the transparent ingot with greatly suppressed nitrogen incorporation was grown. In order to find out the correlation between these transparency and resistivity, resistivity and high-resistivity measurements were conducted.

Fig. 2. UVF image of grown SiC ingot, cross-sectional image for SiC ingot and its transparency after growth run with adoption conventional and ratio.

Fig. 2. UVF image of grown SiC ingot, cross-sectional image for SiC ingot and its transparency after growth run with adoption conventional and ratio.

Resistivity measurements

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In order to investigate the correlation between suppression of nitrogen inclusion and resistivity, resistivity measurement was conducted. The resistivity of the SiC ingot obtained from the conventional method using atmosphere was confirmed to be as shown in Fig. 3 (a). In Method A added with a hydrogen mixed gas ratio, the resistivity was relatively higher as as shown in Fig. 3 (b). It reveals that nitrogen incorporation was well inhibited and the resistivity characteristics increases as hydrogen mixture gas is added. However, this value is not an appropriate resistivity to be applied to HPSI-SiC. In contrast, Method B added with a higher hydrogen mixture ratio, it was confirmed to be unmeasurable as shown in Fig. 3 (c). This shows direct evidence for grown HPSI-SiC ingot in this growth condition. High resistivity measurement was additionally conducted toward SiC ingot grown by Method B.

Fig. 3. Resistivity measurement results for three different SiC crystal substrates measured by a Lehighton Resistivity Measurement system (1510EB).

Fig. 3. Resistivity measurement results for three different SiC crystal substrates measured by a Lehighton Resistivity Measurement system (1510EB).

High resistivity measurement results by Contactless Resistivity Mapper

The original version of this paper is available on https://www.scientific.net/MSF.1156.43.pdf

The SiC substrate grown by method B was subjected to high resistivity analysis using COREMA (contactless resistivity mapper) as shown in Fig. 4. The SiC wafers grown by the conventional and Method A could not be measured due to their lowest resistivity about in COREMA measurement. The SiC wafer grown by Method B was properly measured to be . This value is applicable to HPSI-SiC and shows a tendency consistent with the previous transparency evaluation.

(a) Conventional method with adoption N₂+Ar
Resistivity
21~22 mΩ·cm

(b) Method A with adoption H/Ar of 10%
Resistivity
5.7E2~6E2 mΩ·cm

(c) Method B with adoption H/Ar of 30%
Resistivity
N/A

Fig. 4. High resistivity measurement results for three different SiC crystal substrates measured by COREMA (Contactless Resistivity Mapper) system.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.43.pdf

In order to obtain the high-resistivity HPSI-SiC ingot, the SiC crystals were grown using by PVT method at growth temperature of with adoption three different growth atmosphere of ratio: and under growth pressure of torr for 100 h . The SiC ingot grown by conventional growth with adoption atmosphere, it shows convex shape, the polytype incorporation of was suppressed, and resistivity was lower. In contrast, Method A (Method B) adoption of ratio: shows polytype inclusion (no inclusion) relatively higher resistivity of 10E2 (highest of 1.7E11 ). The crystal growth with adoption proper gas ratio can pave the way to manufacture high quality and suppression of polytype inclusion as well as high-resistivity HPSI-SiC crystal.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1156.43.pdf

This work was supported by Technology Innovation Program (Project Number 0: 1415185945, Project Name 0: Development of next-generation power semiconductor based on Si -on-SiC structure), (Project Number 0: 00402234, Project Name : Development of highly flat, highly clean large area polished SiC single crystal wafers by utilizing advanced process technology for power semiconductor application) funded by the Ministry of Trade, Industry and Energy.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.43.pdf

J. R. Jenny, D.P. Malta, St.G. Müller, A.R. Powell, V.F. Tsvetkov, H. McD. Hobgood, R.C. Glass, C. H. Carter, Jr, High-purity semi-insulating 4H-SiC for microwave device applications, Journal Electron Mater 31 (2002) 366.

M.V.S. Chandrashekhar, I. Chowdhury, P. Kaminski, R. Kozlowski, P. B. Klein, T. Sudarshan, High purity semi-insulating 4H-SiC epitaxial layers by defect-competition epitaxy: Controlling Si Vacancies, Applied Physics Express 5 (2012) 025502.

E. Tymicki, K. Grasza, K. Racka, T. Łukasiewicz, M. Piersa, K. Kościewicz, D. Teklińska, R. Diduszko, P.Skupiński, R.Jakieła, J. Krupka, Effect of nitrogen doping on the growth of 4 H polytype on the 6H-SiC seed by PVT method, Material Science Forum 29 (2012) 717-720.

I. Zwieback, D. L. Barrett, A. K. Gupta U. S. Patent No. 9,017,629 (2015).

J.R. Jenny, D.P. Malta, M. R. Calus, St. G. Müller, A. R. Powell, V. F. Tsvetkov, H. McD. Hobgood, R.C. Glass, C.H. Carter. Jr, Development of large diameter high-purity semiinsulating 4H-SiC wafers for microwave devices, Materials Science Forum 457-460 (2004) 3540.

I. Zwieback, T. E. Anderson, A. K. Gupta U. S. Patent No. 8,512,471 (2013).

M. A. Fanton, Q. Li, A. Y. Polyakov, M. Skowronski, R. Cavalero, R. Ray, Effect of hydrogen on the properties of SiC crystals grown by physical vapor transport: Thermodynamic considerations and experimental results, Journal of Crystal Growth 287 (2006) 339-343.

K.l. Mao, Y.M. Wang, R.S. Wei, B. Li, W. Xu, L. Z. Wang, Polytype stabilization of highpurity semi-insulating 4H-SiC crystal via the PVT method, ISSN 1392-1320 Materials Science Vol. 22 (2016) No.2.

Q. Li, A. Y. Polyakov, M. Skowronski, M. A. Fanton, R. C. Cavalero, R. G. Ray, B. E. Weiland, Properties of crystals grown by hydrogen-assisted physical vapor transport, Applied Physics. Letter 86 (2005) 202102.

J.G. Kim, J.H. An, J.D. Seo, J.K. Kim, M.O. Kyun, W.J. Lee, I.S. Kim, B.C. Shin, K.R. Ku, Hydrogen effect on SiC single crystal prepared by the physical vapor transport method, Materials Science Forum 556-557 (2007) 25-28.

W.J. Lee, B.C. Shin, I.S. Kim, K.R. Ku, Korea Patent No. 100, 845, 946 (2008).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 49-56

doi: 10.4028/p-dO4k3J

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-05-18

Accepted:
2025-05-19

Online:
2025-09-04

High-Temperature Adhesive Bonding of -SiC Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1156.49.pdf

P. Parmar , Manoj. K. Yadav , C. Zellner , G.Wedl , G.Pfusterschmied and U.Schmid

¹Institute of Sensor and Actuator Systems, TU Wien, Gusshausstrasse 27-29, 1040 Vienna, Austria

Christian Doppler Laboratory for Sustainable Silicon Carbide Technology, Gusshausstrasse 27-29, 1040 Vienna, Austria

priyank.parmar@tuwien.ac.at, manojyadav.iitmandi@gmail.com, christopher.zellner@tuwien.ac.at, guenter.wedl@hotmail.com, georg.pfusterschmied@tuwien.ac.at, ulrich.e366.schmid@tuwien.ac.at

Keywords: SiC, adhesive bonding, effusion, heterogenous integration

Abstract

This study explores the application of Polycarbosilane (PCS) as an intermediate adhesive bonding technique for substrates aiming to overcome the challenges of producing highquality and cost-effective substrates for high-power electronics. Thin layers of PCS mixed with mxylene and AIBN (azobisisobutyronitrile) were deposited onto substrates via a spin coating. For demonstration purposes, these coated substrates were then bonded with another substrate. A defect-free, high-temperature stable bond is facilitated by annealing at high temperatures. Effusion measurements were conducted to characterize the PCS thin films and examine the organicinorganic transitions and the resulting outgassing at high temperatures. SEM analysis confirmed the uniformity of the bonded layer. These results demonstrate PCS's potential in high-temperature applications and will stimulate further research exploring doped SiC bonding layers and their electrical properties.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.49.pdf

As power electronics technology advances towards higher efficiency, increased power density, and enhanced integration density on system level, traditional silicon-based solutions, which have long been dominant, are increasingly unable to meet the evolving requirements. Recent advancements in wide bandgap (WBG) semiconductor materials, however, particularly silicon carbide (SiC), are driving significant progress in the power electronics industry. SiC, as a WBG material, exhibits superior characteristics, including a significantly higher breakdown electric field and enhanced thermal conductivity than silicon, as summarized in Figure 1, positioning it as a strong candidate for high-voltage, low-loss power devices. However, despite notable advancements in SiC technology, delivering high-quality, cost-effective substrates remains a crucial challenge. [1,2]

Fig. 1. Comparison of material properties of Si and SiC as summarized in [2].

Fig. 1. Comparison of material properties of Si and SiC as summarized in [2].

Engineered substrates present a promising technological approach for achieving this challenging goal. Key techniques for producing such substrates include Smartcut [3], controlled spalling [4, 5], and photoelectrochemical etching [6, 7, 8]. The principle behind the Smartcut process includes the transfer of a high-quality device layer onto a low-resistivity handle wafer. Controlled spalling facilitates layer exfoliation via a mechanical approach, while photoelectrochemical etching utilizes tailored porosification to remove material layers from the mother wafer. The performance and the production yield of these structures significantly depend on the bonding quality of these unconventional heterostructures, which underscores the importance of developing robust, low-cost bonding techniques [9].

Intermediate bonding is a cost-effective and user-friendly alternative to conventional techniques like fusion bonding, offering several key advantages. These include uniform load distribution, tolerance to surface roughness, effective sealing, and resistance to stress and vibrations [10]. Among the various adhesive materials, including polymers, glass, metals, and ceramics, vinyl group-containing polycarbosilanes (PCS) polymers are particularly notable. PCS polymers exhibit strong adhesion to a wide range of substrates, exceptional chemical resistance, UV stability, and thermal durability, making them highly suitable for advanced bonding applications.

In this work, we have utilized the polymer from Starfire Systems Inc., commercially known as SMP10. SMP-10 is a single-component liquid precursor that forms high-purity ceramic SiC , with a 72 amorphous SiC at and nanocrystalline at , thus offering the possibility to realize an electrically conductive bonding interface [11]. SMP-10 was deposited onto monocrystalline substrates to investigate the organic-inorganic transition and to study the outgassing behavior due to thermal loading. Additionally, we investigated the potential of SMP-10 as an intermediate adhesive bonding agent, focusing on its ability to create thermally stable bonds between monocrystalline substrates at high temperatures.

Experimental Details

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For this study, square samples were prepared from a single crystalline n -doped wafer. Sample cleaning was performed using the RCA (Radio Corporation of America) cleaning protocols. The adhesive solution was prepared by mixing 10 g of SMP-10 with 30 g of m-xylene and 0.29 g of azobisisobutyronitrile (AIBN). AIBN is a radical photo-initiator that allows the curing of
the ceramic-forming polymer precursor at a substantially lower temperature. The nitrogen-containing photo-initiator can eventually also increase nitrogen in the formed ceramic layer to improve electrical conductivity.
The solution was spin-coated onto the samples at 3000 rpm for 40 seconds. For demonstration purposes, a second monocrystalline substrate was placed on top of the coated sample, and the assembly was pre-bonded with an EVG bonder, applying a constant force of 350 N . The samples were heated at for one hour to facilitate bonding. Subsequently, the structure was annealed at at 20 mbar back chamber pressure and in an Ar atmosphere in a custom-built hightemperature furnace from HTM Reetz, resulting in a bonded sample. The bonded cross-sectional interface was then analyzed with a Hitachi SU8030 scanning electron microscope (SEM) using an acceleration voltage of 5 kV .
The solution was spin-coated onto the substrate and analyzed using a HIDEN HALO RGA spectrometer to investigate the organic-inorganic transition and the associated outgassing. The samples were maintained at a vacuum pressure of approximately and heated to with a resistive heater element with a ramp rate of . A schematic of the experimental setup for effusion measurement is depicted in Figure 2. During the heating process, the gaseous species released from the sample were analyzed with a quadrupole mass spectrometer and a Faraday cup from HIDEN Analytical for residual gas analysis, enabling, as a function of time, the measurement of the partial pressure of individual elements in the chamber, but close to the sample surface.

Fig. 2. Cross-sectional schematic of the effusion setup [15].

Fig. 2. Cross-sectional schematic of the effusion setup [15].

Polymer-to-ceramic conversion

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The conversion of precursors into pre-ceramics and ceramic materials involves a sequence of reactions which results in changes of their compositions and properties. A cross-linking step is highly required to reduce the volatilization and depolymerization of the precursors and to increase the mass yield during the polymer-to-ceramic transformation. This cross-linking process involves reactions such as hydrosilylation and dehydrocoupling [12], as shown in Figure 3, which creates a threedimensional polymeric network. This network renders the precursor more thermally stable, unmeltable, and insoluble. [13]

Fig. 3. Chemical reactions during the pyrolysis of SMP-10 [12, 14].

Fig. 3. Chemical reactions during the pyrolysis of SMP-10 [12, 14].

Further heat treatment transforms a thermoset polymer into an amorphous ceramic. Heating up to removes low molecular weight polycarbosilanes (PCS). Within the temperature range of to , the formation of linkages increases the molecular weight of PCS. From to , the material undergoes a transformation into an inorganic structure, eliminating Si , and moieties, accompanied by the release of and .

At , the formation of bonds occurs, marking the initiation of the free carbon phase and the creation of dangling carbon bonds. At , the material transitions into an amorphous state. The temperature range between and represents a transitional phase with minimal weight loss. Crystallization begins to emerge between and , while temperatures above correspond to the stage of crystal growth. [14]

Results and Discussions

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From the effusion measurements shown in Figure 4, we observe ionized gas molecules (amu 1) and (amu 16) outgassing from the adhesive bonding layer occurring predominantly up to an annealing temperature of . As the measurements were conducted under high vacuum conditions, we observed a minimal presence of (amu 18), CO (amu 28), and (amu 44).

Fig. 4. Effusion measurement which illustrates the outgassing of and (amu 18), , and (amu 44) with a temperature curve in red with a temperature ramp of .

Fig. 4. Effusion measurement which illustrates the outgassing of and (amu 18), , and (amu 44) with a temperature curve in red with a temperature ramp of .

Additionally, we have analyzed the effect of the temperature ramp on the outgassing behavior, using ramps of and , as shown in Figure 5 and Figure 6. It was observed that a lower temperature ramp results in increased outgassing, as indicated by higher partial pressures. This phenomenon can be attributed to the slower heating rates, which allow the material to stay at intermediate temperatures for an extended time, allowing more time for the gaseous species to diffuse, and resulting in a higher energy input, both effects contributing to the higher pressure observed.

Fig. 5. Effusion measurement with .

Fig. 5. Effusion measurement with .

Fig. 6. Effusion measurement with .

Fig. 6. Effusion measurement with .

Bonded Substrates

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A similar effect of the lower temperature ramp was observed during the bonding of substrates. At a ramp rate of , numerous defects, including voids and disbonded areas, appeared, as shown in Figure 7, which were attributed to the re-organization of the material during the annealing process. To minimize these defects, the procedure was repeated with a slower ramp rate of , and an additional step at for 1 hour to enhance mass loss, allowing for more controlled outgassing and material organization. As shown in Figure 8, this approach resulted in void-free bonded 4 H -SiC substrates, demonstrating the effectiveness of PCS as a bonding interface for SiC at high temperatures.

Fig. 7. The cross-sectional SEM images of the bonded monocrystalline substrates at temperature ramp with the presence of defects like voids and disbands.

Fig. 7. The cross-sectional SEM images of the bonded monocrystalline substrates at temperature ramp with the presence of defects like voids and disbands.

Fig. 8. The cross-sectional SEM images of the bonded monocrystalline substrates at temperature ramp with a uniform bonded area with no defects.

Fig. 8. The cross-sectional SEM images of the bonded monocrystalline substrates at temperature ramp with a uniform bonded area with no defects.

Crystallization of the SMP-10 layer was also studied by spin coating this material onto a monocrystalline substrate, followed by annealing at for one hour with a one-hour dwell time at in a REETZ furnace under an Ar atmosphere. However, XRD results indicated an amorphous phase, potentially due to rapid cooling, which may have inhibited crystal formation. Further investigations are needed to explore this in detail, along with the impact of in-situ nitrogen doping on improving electrical film conductivity.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.49.pdf

This study demonstrates the potential of Polycarbosilane (PCS) as an effective adhesive bonding material for substrates, particularly in high-temperature applications. Using PCS, combined with optimized annealing conditions, enables the formation of defect-free, high-temperature stable bonds. Effusion measurements indicated that lower temperature ramp rates play a critical role in minimizing defect formation, as material re-organization becomes the dominant factor, as even at higher outgassing rates, a defect-free interface was obtained. These findings highlight the importance of controlled outgassing and temperature management in bonding processes. PCS shows promise as a bonding interface for SiC substrates, paving the way for further research into doped SiC layers and their electrical properties for advanced power electronics applications.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1156.49.pdf

The financial support by the Austrian Federal Ministry of Labour and Economy, the National Foundation for Research, Technology and Development, and the Christian Doppler Research Association is gratefully acknowledged.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.49.pdf

I. Giuseppe, et al., "Power electronics based on wide-bandgap semiconductors: Opportunities and challenges," IEEE Access, vol. 9, pp. 139446-139456, 2021.

She X, et al., "Review of Silicon Carbide Power Devices and Their Applications.," IEEE Transactions on Industrial Electronics, vol. 64, pp. 8193-8205., 2017.

S. Rouchier, et al., "150 Mm SiC Engineered Substrates for High-Voltage Power Devices.," Materials Science Forum, vol. 1062, pp. 131-135, 2022.

W.Shan, et al., "A Novel Approach for Thin 4H-SiC Foil Realization using Controlled Spalling from a 4H-SiC Wafer," ICSCRM 2023.

Z. Suo, et al., "Steady-state cracking in brittle substrates beneath adherent films," International Journal of Solids and Structures, vol. 25, no. 11, pp. 1337-1353, 1989.

M. LEITGEB, et al., "Compound Semiconductor Layered Structure And Process For Preparing The Same," 2022.

M. LEITGEB, et al., "Stacked Layers of Different Porosity in 4H SiC Substrates Applying a Photoelectrochemical Approach," J. Electrochem. Soc, vol. 164, p. E337, 2017.

M. Perazzi, et al., "High-Temperature Reorganization Behavior of Single-Crystalline Porous 4H-SiC Thin Foils," Materials Science Forum, pp. 43-49, 2024.

B. e. Kallinger, et al.,"Benchmarking Experiment of Substrate Quality including SmartSiCTM Wafers by Epitaxy in a Batch Reactor," Solid State Phenomena, vol. 342, pp. 91-98, 2023.

F. Campbell, Manufacturing Processes for Advanced Composites, 2003.

[Online]. Available: .

S. Kaur, et al., "Pressureless fabrication of dense monolithic SiC ceramics from a polycarbosilane," Journal of the European Ceramic Society, vol. 34, no. 15, pp. 3571-3578, 2014.

B. Gilvan, et al., "Polymeric and ceramic silicon-based coatings - a review," J. Mater. Chem. A, vol. 7, no. 5, pp. 1936-1963, 2019.

R. M. Laine, et al., "Preceramic polymer routes to silicon carbide," Chemistry of Materials, vol. 5, no. 3, pp. 260-279, 1993.

L. Stöber, et al., "Nitrogen incorporation in sputter deposited molybdenum nitride thin films.," J. Vac. Sci. Technol. A 1, 2016.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 57-64

doi: 10.4028/p-0Vb1Ug

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-08-12

Accepted:
2025-08-12

Online:
2025-09-04

New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

The original version of this paper is available on https://www.scientific.net/MSF.1156.57.pdf

Shanshan Hu , Balaji Raghothamachar , Zeyu Chen , Kevin Kayang , Dilip Gersappe , Michael Dudley , Victor Torres , Douglas Dukes , Diana Lang , Andy Martin , Hunter Briccetti , Samantha Griswold , Thomas Kegg and Nicholas Griffin

Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794, USA

Pallidus, Inc., Albany, NY 12203, USA

shanshan.hu@stonybrook.edu, balaji.raghothamachar@stonybrook.edu, zeyu.chen@stonybrook.edu, kevin.kayang@stonybrook.edu, dilip.gersappe@stonybrook.edu, michael.dudley@stonybrook.edu, victor.torres@pallidus.com, douglas.dukes@pallidus.com, 'sam.griswold@pallidus.com, tom.kegg@pallidus.com, nicholas.griffin@pallidus.com

Keywords: X-ray topography, 4H-SiC, PVT growth, prismatic slip

Abstract

Prismatic slip systems are the secondary slip systems in Silicon carbide ( ) crystals. The previously proposed radial thermal model of the PVT growth process for SiC crystals, which predicts the occurrence of slip in different prismatic planes as a function of the radial position in the boule, has been shown to generally work well. Recent observations of growth interface nucleation of prismatic slip necessitated updating the thermal model to incorporate the effects of the curvature of the growth interface. A 3D finite element model has been developed to include the growth interface curvature complexity. The model predicts high dislocation densities due to prismatic slip near the peripheral regions dropping to zero near the center for wafers from sections of the boule grown with a flatter interface and a less dense distribution of prismatic slip dislocations that extends to the center for wafers from boule sections grown with a more convex interface. Additionally, due to such an interface-initiated prismatic slip, , the asymmetrical step configuration produced by off-axis growth results in an asymmetrical distribution of prismatic slip. The studies suggest that a reduced surface curvature is necessary to suppress the prevalence of interface-related prismatic slip generation.

Introduction

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Silicon carbide ( SiC ) has become the material of choice for next-generation high-power electronic devices[1]. Efforts are ongoing to optimize the physical vapor transport (PVT) growth process with the goal of obtaining 150 mm wafers with reduced dislocation densities, including threading screw/mixed dislocations (TSDs/TMDs), threading edge dislocations (TEDs), as well as basal plane dislocations (BPDs). These defects negatively affect the reliability of high-performance power devices, limiting their widespread adoption in power electronics[2]. SiC crystals grown by PVT possess a low density of dislocations and other structural defects. The basal plane slip system ( ) is the most frequently observed deformation mechanism in SiC crystals grown by PVT, while the prismatic slip systems are activated as well[3-5]. Prismatic slip occurs when threading edge dislocations (TEDs) in prismatic planes glide under the influence of radial thermal gradient stresses[6, 7]. The TED glide leaves behind screw dislocation segments which can then cross-slip onto the basal plane.

Previously, we reported on a radial thermal model of the PVT growth process developed to predict the distribution of prismatic slip[8, 9]. Based on a cylindrical boule, this model predicted the occurrence of slips in different prismatic planes as a function of the radial position in the boule. The predicted distributions showed a good correlation with observed distribution on X-ray topographs, clearly demonstrating the role of radial thermal gradients in activating prismatic slip during PVT growth. However, recent studies of X-ray topography of axial wafers indicate interfacerelated prismatic slip nucleation at work, suggesting the current model must be updated to incorporate the effect of the growth interface curvature to describe the distribution of prismatic slip.

Experimental

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Two off-axis 150 mm PVT-grown 4H-SiC commercial wafers (marked as Sample A and Sample B) were sliced from the same boule. Sample A is from a later growth stage at the position further from the seed, while Sample B is from an early growth stage at the position closer to the seed. Furthermore, several axial slices cut parallel to the [0001] growth axis are prepared to image the distribution of prismatic slip dislocations with respect to the growth interface. All samples were imaged by Synchrotron White Beam X-ray Topography (SWBXT) in transmission geometry with reflection and the images were recorded on AGFA Structurix D3-SC films.

Finite Element Modeling

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A 3D finite element model (FEM) was developed to simulate the thermal stress distribution within the boule. The general-purpose FE modeling analysis software ABAQUS/Standard was used for these simulations[10]. The boule sample was modeled as a circular disc of radius 150 mm with an ellipsoidal surface where the surface curvature varies. The elastic modulus and Poisson ratio used for the simulation were 411 GPa and 0.16 , respectively, with a coefficient of thermal expansion of . Thermal stresses in the sample were induced due to the radial thermal gradient [8] according to:

Where a and b are constants taken as and 10 , respectively. Additionally, the bottom of the sample was fixed such that the sample was free to expand axially and radially only. The sample was meshed using eight-node brick elements (C3D8). The thermal stresses were analyzed in the form of the resolved shear stress distribution through the samples.

Results and Discussion

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The radial thermal model[8]to predict prismatic slip established previously is deduced from the thermal stress components, , induced by the radial temperature gradients, where is along the radial direction, is perpendicular to both radial and growth directions, and is parallel to the growth direction, as indicated by Fig. 1(a). By applying the corresponding Schmid's factor, the estimated thermal stress can resolve onto each of three prismatic slip systems. Thus, the resolved shear stress for prismatic systems can be estimated at any location in the crystal boule. For example, for prismatic system , the resolved shear stress is given by:

Where is the angle between any point on the plane perpendicular to the growth axis at a height of z and [ ] direction.

As a result, the predicted distribution of all three sets of prismatic slip systems on commercial wafers can be obtained as schematically shown in Fig. 1(b). Prismatic slip is observed at the periphery regions with higher resolved shear stress. Two sets of prismatic slip dislocations are observed at each of the twelve different periphery regions around the wafer. In particular, the stress level of the resolved shear stress affects the extent to which the distribution of activated prismatic slip regions extends towards the center of the crystal and the density of prismatic slip dislocations. A higher resolved shear stress level implies prismatic slip extends further into the center of the crystal with higher density.
SWBXT transmission images recorded from the twelve different regions of Samples A and B are compared with predicted results. As shown in Fig. 1(c) for Sample A, prismatic slip dislocations can be clearly identified as straight dark lines running along one of the three directions. An excellent agreement is found between the topograph and prediction for prismatic slip distribution, generally validating the radial thermal model.

Fig. 1. (a)Coordinate system for the thermal model. (b) Predicted map indicating the distribution of prismatic slip dislocations by the radial thermal model. (b) A good correlation is observed between the SWBXT images for Sample A and the predicted map.

Fig. 1. (a)Coordinate system for the thermal model. (b) Predicted map indicating the distribution of prismatic slip dislocations by the radial thermal model. (b) A good correlation is observed between the SWBXT images for Sample A and the predicted map.

Analysis of the axial wafers reveals prismatic slip nucleation from the growth interface. As shown by Fig. 2(a), dislocation loops are observed to nucleate at the as-grown interface and propagate into the crystal from axial slices cut roughly parallel to the [0001] growth axis. The loops are composed of a segment approximately along the growth axis connected with two segments approximately parallel to basal planes at its two ends, suggesting they are generated by the gliding of the TED segments inside prismatic planes, leaving two segments of dislocation in its wake. Four prismatic slip half loops are observed in Fig. 2(a), as indicated by red arrows. Since the axial slice was cut along the direction close to direction, the prismatic slip half loops are confirmed to belong to the prismatic slip system. The loops have weak contrast on the topograph, and a schematic of Fig. 2(a) is constructed, as shown by Fig. 2(b), to clearly indicate the positions of prismatic slip half loops.

Fig. 2. (a) SWBXT image with 0reflection recorded from an axial slice cut parallel to the [0001] growth axis showing nucleation and propagation of prismatic slip half loops from the as-grown interface as marked by red arrows, and (b) a schematic helping locate prismatic slip half loops in (a).

Fig. 2. (a) SWBXT image with 0reflection recorded from an axial slice cut parallel to the [0001] growth axis showing nucleation and propagation of prismatic slip half loops from the as-grown interface as marked by red arrows, and (b) a schematic helping locate prismatic slip half loops in (a).

The previously developed radial thermal model does not take into account such surface nucleated prismatic slips. Therefore, an updated model to include the growth interface curvature complexity is developed to obtain a more comprehensive picture of prismatic slip in the boule.
A 3D FE thermal model that incorporates the shape of the interface is employed. As shown in Fig. 3, the stress distribution across the cross-section of the as-grown interface for the PVT-grown 150 mm 4H-SiC boule is suggested by the modified thermal model with a less convex interface (Fig. 3(a)) and more convex interface (Fig. 3(b)). Clearly, the less convex interface has lower stress, while the more convex interface has high stress even in the middle region of the boule, which was not predicted by the previous model.

Fig. 3. Resolved shear stress distribution across the cross-section of a boule for the prismatic slip system during PVT growth obtained by finite element method for (a) less convex interface and (b) more convex interface, showing that convex interface can introduce higher stress during crystal growth even for the middle region of the boule. Cross-sectional maps are for different radial positions around the boule as indicated by the boule schematic. The same maps can also be used for the other two slip systems by rotating .

Fig. 3. Resolved shear stress distribution across the cross-section of a boule for the prismatic slip system during PVT growth obtained by finite element method for (a) less convex interface and (b) more convex interface, showing that convex interface can introduce higher stress during crystal growth even for the middle region of the boule. Cross-sectional maps are for different radial positions around the boule as indicated by the boule schematic. The same maps can also be used for the other two slip systems by rotating .

The higher stresses can, therefore, induce nucleation of prismatic slip dislocation loops with a more convex-shaped interface. Fig. 4(b) and (c) show transmission images recorded from Sample A and Sample B at regions 1, 2, 3, and 4, ranging from periphery regions to central regions, whose locations are shown in Fig. 4(a). As shown by Fig. 4(b), for Sample A from the later growth stage, a less dense distribution of prismatic slip dislocations extends all the way to the center as they are observed in all regions of 1, 2, 3, and 4. However, Fig. 4(c) indicates that high dislocation densities near the peripheral regions dropping to zero near the center are formed during the early growth stage, as prismatic slip dislocations are not observable in region 4 of Sample B.
The previous radial thermal model is not sufficient to explain such prismatic slip distribution difference between Sample A and Sample B. Based on that model, Sample A has a lower stress level than Sample B since Sample A has lower prismatic slip dislocation densities for regions 1, 2, 3 compared to Sample B. However, the model cannot account for the observation of prismatic slips in region 4 of Sample A and absence in region 4 of Sample B.

Fig. 4. (a) Approximate locations on the 150 mm substrates where x-ray topographs were recorded in four regions ( , and 4 ), and the corresponding transmission topographs with reflection for (b) Sample A from later growth stage, and (c) Sample B from early growth stage. Prismatic slip dislocations protrude into region 4 for Sample A, while no prismatic slip dislocations are observed in region 4 for Sample B. Prismatic slip dislocation densities are indicated in each X-ray topograph.

Fig. 4. (a) Approximate locations on the 150 mm substrates where x-ray topographs were recorded in four regions ( , and 4 ), and the corresponding transmission topographs with reflection for (b) Sample A from later growth stage, and (c) Sample B from early growth stage. Prismatic slip dislocations protrude into region 4 for Sample A, while no prismatic slip dislocations are observed in region 4 for Sample B. Prismatic slip dislocation densities are indicated in each X-ray topograph.

The modified 3D thermal model can now be employed to explain such prismatic slip dislocation distribution in Sample A and Sample B. The interface shape during crystal growth for Sample A and Sample B can be estimated by the position of the facet on the wafer. As schematically shown by Fig. 5, the facet of Sample A is located closer to the center than that of Sample B, suggesting that Sample A has a domed interface while Sample B has a flatter interface as the facet is formed at the position where the interface is away from the horizontal because of the off-cut growth. As predicted by the new model, the domed-shaped interface for Sample A introduces a higher stress level in the center, nucleating prismatic dislocation loops even at the central region of the crystal boule, while the flatter interface for Sample B does not introduce prismatic dislocation loops. The prismatic slip dislocation distribution in Sample A and Sample B thus verifies and justifies the need for the modified 3D thermal model.

Fig. 5. Schematics showing the interface shape can be estimated by the facet position. Sample A has a domed interface, and Sample B has a flatter interface.

Fig. 5. Schematics showing the interface shape can be estimated by the facet position. Sample A has a domed interface, and Sample B has a flatter interface.

It should be noted that the dislocation loop nucleation at the as-grown interface is related to step configurations on the interface. As shown by Fig. 6, kinks on the vertical step risers of the macrosteps may act as sites for nucleation of half loops on prismatic planes, while the junctions between step risers and terraces can introduce BPD half loops.

Fig. 6. Diagram schematically showing the prismatic half loops can be nucleated at the vertical step risers of the macro-steps, and BPD half loops are introduced from the junctions between step risers and terraces.

Fig. 6. Diagram schematically showing the prismatic half loops can be nucleated at the vertical step risers of the macro-steps, and BPD half loops are introduced from the junctions between step risers and terraces.

The domed and flatter interfaces have different step configurations at the as-grown interface. Fig. 7 schematically shows the cross-sectional images for the step configurations of Sample A and Sample B. As shown by Fig. 7(a), with the domed as-grown interface, Sample A has narrower terraces during crystal growth, encouraging the formation of macro-steps, especially at the position further from the facet with a larger tilt angle to the facet. The vertical step risers of the macro-steps can offer the sites for nucleation and propagation of prismatic plane dislocation half loops. Meanwhile, as indicated by Fig. 7(b), macro-steps are less likely to form on the flatter as-grown interface of Sample B, making the nucleation of prismatic plane dislocation half-loops more difficult.

Fig. 7. Schematics showing step configurations for (a) domed as-grown interface of Sample A and (b) flatter as-grown interface of Sample B. Domed as-grown interface can encourage the formation of macro-steps, offering sites for nucleation of prismatic half loops.

Fig. 7. Schematics showing step configurations for (a) domed as-grown interface of Sample A and (b) flatter as-grown interface of Sample B. Domed as-grown interface can encourage the formation of macro-steps, offering sites for nucleation of prismatic half loops.

From Fig. 7(a), we note that the off-cut causes asymmetrical distribution of macro-steps. The left side of Sample A, which is further away from the facet, has more macro-steps, which are large compared to the right side of Sample A. This implies that more prismatic plane dislocation half-loops can nucleate on the left side than on the right side of Sample A. This prediction correlates with observation from Sample A. As shown by Fig. 8(a), when the wafer is cut from the boule of the crystal, different positions on the wafer come from different growth stages. With the domed as-grown interface, the center of the wafer comes from the earlier growth stage, while the peripheral part of the wafer comes from the later growth stage. The asymmetrical distribution of prismatic slip dislocations is observed in Sample A. As shown by Fig. 8(b), in the SWBXT image for the whole Sample A wafer, the outer regions of the wafer have a darker contrast due to the high density of prismatic slip dislocations. On the left side of the wafer, the high-density prismatic slip dislocation region protrudes further towards the center of the wafer than on the right side of the wafer .

Fig. 8. (a) Schematic of the boule showing that the different positions on the wafer come from different growth stages. Domed as-grown interface makes the wafer center region come from the early growth stage, and the peripheral region comes from the later growth stage. (b) Whole SWBXT image for Sample A. The high-density prismatic slip dislocation region is wider for the left side compared to the right side, correlating with the prediction from the step configuration analysis of Sample A.

Fig. 8. (a) Schematic of the boule showing that the different positions on the wafer come from different growth stages. Domed as-grown interface makes the wafer center region come from the early growth stage, and the peripheral region comes from the later growth stage. (b) Whole SWBXT image for Sample A. The high-density prismatic slip dislocation region is wider for the left side compared to the right side, correlating with the prediction from the step configuration analysis of Sample A.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.57.pdf

The limitations of the radial thermal model created previously for prismatic slip interpretation in PVT-grown 4H-SiC crystals are addressed by a modified 3D FEA thermal model by including the influence of as-grown interface shape on prismatic slip during crystal growth. The modified 3D thermal model helps understand the prismatic slip dislocation distribution in the central regions, as well as the asymmetrical distribution of prismatic slip dislocations on PVT-grown 4H-SiC wafers. The results demonstrate that it is necessary to control the as-grown interface shape to restrain the defect generation inside the boule during the PVT growth of .

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1156.57.pdf

This work was supported by Pallidus, Inc.. This research used resources of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. This research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.57.pdf

H. Matsunami, T. Kimoto, Step-controlled epitaxial growth of SiC: High quality homoepitaxy, Mater. Sci. Eng. R Rep. 20 (1997) 125-166.

R. SIngh, M. PEchT, Commercial impact of silicon carbide, IEEE Ind. Electron. Mag. 2 (2008) 19-31.

S. Ha, N. T. Nuhfer, G. S. Rohrer, M. De Graef, M. Skowronski, Identification of prismatic slip bands in 4H SiC boules grown by physical vapor transport, J. Electron. Mater. 29 (2000) L5L8.

H. H. Wang, S. Y. Byrapa, F. Wu, B. Raghothamachar, M. Dudley, E. Sanchez, D. M. Hansen, R. Drachev, S. G. Mueller, M. J. Loboda, Basal plane dislocation multiplication via the hopping frank-read source mechanism and observations of prismatic glide in , Mater Sci Forum 717 (2012) 327-330.

H. Wang, Studies of growth mechanism and defect origins in 4H-silicon carbide substrates and homoepitaxial layers, dissertation, Stony Brook University. 2014.

S. Hu, H. Fang, Y. Liu, H. Peng, T. Ailihumaer, Q. Cheng, Z. Chen, R. Dalmau, J. Britt, R. Schlesser, Prismatic slip in AlN crystals grown by PVT, ECS Transactions 104 (2021) 57-64.

S. Hu, H. Fang, Y. Liu, H. Peng, Q. Cheng, Z. Chen, R. Dalmau, J. Britt, R. Schlesser, B. Raghothamachar, Characterization of prismatic slip in PVT-grown AlN crystals, J. Cryst. Growth 584 (2022) 126548.

J. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quast, I. Manning, Prismatic slip in PVT-grown 4H-SiC crystals, J. Electron. Mater. 46 (2017) 20402044.

J. Guo, Y. Yang, O. Y. Goue, B. Raghothamachar, M. Dudley, Study on the role of thermal stress on prismatic slip of dislocations in crystals grown by PVT method, ECS Transactions 75 (2016) 163-168.

M. Smith, ABAQUS/standard user's manual, version 6.9, (2009).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 65-74

doi: 10.4028/p-7vQ6Zj

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-18

Revised:
2025-02-26

Accepted:
2025-02-28

Online:
2025-09-04

SmartSiC & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

The original version of this paper is available on https://www.scientific.net/MSF.1156.65.pdf

E. Guiot , G. Picun , F. Allibert , A. Drouin , W. Schwarzenbach

SOITEC, Parc technologique des Fontaines, Bernin, France

eric.guiot@soitec.com, gonzalo.picun@soitec.com, alexis.drouin@soitec.com, walter.schwarzenbach@soitec.com

Keywords: SiC MOSFETs, specific on resistance, SiC layer transfer, SmartCut™, SmartSiC™, Low resistivity, Bipolar degradation, Power Cycling.

Abstract

The Smart Cut technology enables the int egration of high-quality SiC layer transfers, thereby optimizing device yield. It employs low resistivity handle wafers (below ) to minimize conduction and switching losses for both 150 mm and 200 mm wafers. Material characterization indicates potential reductions of up to or for advanced 1200 V SiC MOSFETs and JFETs. A improvement for 650 V SiC MOSFETs has been demonstrated, with potential reductions of up to for next-generations 1200 V SiC MOSFETs. Proton irradiation which is inherent to the Smart Cut technology induces an increased ruggedness with regards to bipolar degradation. Additionally, the polycrystalline SiC used as the main material for the die has shown to double power cycling lifetime in silver sintering die attachment An increase of 20 K of the maximum junction temperature could be applied without compromising the reliability of the die attach, allowing for a further current increase of up to .

Introduction

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Power electronics based on Silicon Carbide ( SiC ) technology is now considered as a crucial key technology for the electrification of mobility and the efficient use of renewable energies. With the increasing demand of the market, power semiconductor companies are under pressure to rapidly scale up their production capacity. Although there has been notable improvement in the quality and supply of material, achieving low defect density and reliable wafers for high yields and increased device performances remains a challenge. In response to this, we have introduced a groundbreaking SiC engineered substrate. In this paper, we will demonstrate how SiC engineered substrate is bringing not only performance benefits but also reliability improvements.

Fabrication of SiC Engineered Substrates

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The Smart Cut technology (see Fig 1) enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer ( ) to improve device conduction and/or switching losses [1-4] both for 150 mm and 200 mm wafers diameter (see Fig 2). The SmartSiC engineered substrate is composed of a thin (between 350 and 800 nm ) high-quality 4 H -SiC layer bonded (conductive bonding) on top of a thick polycrystalline SiC handle wafer.

Fig. 1. Smart Cut technology adapted to silicon carbide.

Fig. 1. Smart Cut technology adapted to silicon carbide.

Fig. 2. 150 mm & 200 mm SmartSiC substrate ready for SiC drift epitaxy

Fig. 2. 150 mm & 200 mm SmartSiC substrate ready for SiC drift epitaxy

The initial single crystal donor wafers can be re-used multiple times, leading to efficient usage of the SiC boule materials. Conventional wafering technology can extract a maximum of 50 wafers per boule, whereas our technology enables the preparation of up to 500 wafers out of the same boule. Compared to standard single crystal material with a conductivity around , resistivities well below are achieved (see Fig. 3) for polycrystalline SiC (pSiC) handle wafer. By means of a high material doping, the electrical resistivity of the pSiC substrate is reduced by a factor of at least 4 , up to 10 , compared to conventional single crystal wafers. Less than electrical resistivity is guaranteed, with typical value in the range of 1 to 2 . Through the application of CVD technology, the performance remains consistent across wafers for substrate diameters of both 150 mm and 200 mm . This consistency can be replicated using various material sources, a crucial factor for industrial applications, as illustrated in figure 3.

Fig. 3. Electrical resistivity distribution of polycrystalline SiC ( pSiC from sources) compared to single crystal SiC substrate (mSiC).

Fig. 3. Electrical resistivity distribution of polycrystalline SiC ( pSiC from sources) compared to single crystal SiC substrate (mSiC).

Material characterization of SiC engineered substrates for electron transport

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Such a high electrical conductivity is confirmed from room temperature ( ) to maximum device operating temperature ( ) as stated on Table 1 which compares electrical resistivity on single crystal SiC, pSiC & SiC engineered substrate wafer bonding interface over the whole temperature range [5].

Table 1. Electrical resistivity for each SmartSiC™ layer, from to

Temperature | 25°C | 175°C
4H-SiC bulk [mOhm.cm] | 15 − 25 | 15 − 25
Bonding Interface [mOhm.cm²] | 0.003 − 0.006 | 0.002 − 0.006
Handle pSiC bulk [mOhm.cm] | 1.5 − 2.2 | 1.7 − 2.5

The polycrystalline SiC substrate has a nitrogen dopant concentration higher than the standard level of . Due to this high N concentration (higher than [7]), it is thought that, merely by depositing metal, ohmic contact is obtained by means of a tunneling current, since the barrier between the metal and the semiconductor is thin. The contact resistance is hence lowered and we anticipate a level below . Dedicated characterizations are being pursued. As a result, SiC engineered substrates enable a simplified device fabrication process by eliminating the need for ohmic contact annealing, while still maintaining low backside contact resistance. Furthermore, as discussed later in this paper, the assembly power cycling reliability [3] remains uncompromised.

Device performance results

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Given the materials improved properties highlighted in the previous section, we will show in the following section how this enhanced substrate conductivity impacts the SiC power device performances. As a first step we prepared SiC diodes. In a second step we collaborated with ST Microelectronics to evaluate the performance benefit on a large current state of the art SiC mosfet.

The fabrication of JBS diodes and MPS diodes (with areas of : see figure 4) has been performed in collaboration with Fraunhofer IISB. For 1200 V JBS diodes, we have performed wafer level dies forward and reverse characteristics. No critical change in the reverse characteristics was observed [8].

For 1200 V MPS diodes, we have reported wafer level dies forward characteristics. Voltage drop lowering at the rated current of 9A for (see Fig.4) MPS diodes, is around . A first extraction of the dynamic on resistance of the forward regime (2 to 10A) of the MPS diodes leads to a benefit (linked to SiC engineered substrate transition) around . This is even beyond the expected gain linked to the improved material resistivity: around . This further gain is supposed to be linked to the lower contact resistance of the back side contact coming from the high level of doping in the pSiC as explained in the previous paragraph.

Fig. 4. Forward resistance of Standard SiC and SmartSiC for rated MPS diodes.

Fig. 4. Forward resistance of Standard SiC and SmartSiC for rated MPS diodes.

In parallel, 650 V SiC planar MOSFETs Gen2 planar SiC MOSFETs were manufactured on both types of substrates ( SiC engineered substrates and standard single-crystal 4 H SiC wafers, n-type) and processed simultaneously as a single batch by STMicroelectronics as part of the EU funded program Transform [9]. We have demonstrated a benefit of of (see Fig. 5). This result was obtained without compromising the leakages (see Fig. 6). Such a strong reduction of is close to what can be expected during the transition from a given device generation to the next one.

Fig. 5. Ron comparison for a Gen2 SiC MOSFET manufactured with and SmartSiC [3]

Fig. 5. Ron comparison for a Gen2 SiC MOSFET manufactured with and SmartSiC [3]

Fig.6. Idss comparison for a Gen2 SiC MOSFET manufactured in single-crystal SiC and substrates [3].

Fig.6. Idss comparison for a Gen2 SiC MOSFET manufactured in single-crystal SiC and substrates [3].

We recently evidenced that the switching losses of SiC MOSFETs prepared with SiC engineered substrates are drastically improved in terms of at high temperature [10].

Perspectives for SiC MOSFETs Performance

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The above presented results are showing evidences that SiC engineered substrate enables an increase of the current density at the device level thanks to both the polycrystalline SiC material's low resistivity and the lowered back side contact resistance. Compared to standard single crystal SiC substrate with a material electrical resistivity around , the polycrystalline SiC material can reach material resistivity as low as . In parallel, thanks to the high doping level of polycrystalline SiC , the contact resistance is lowered around . Let's see now how this will impact the upcoming SiC power devices developments.
SiC MOSFET R A specific resistance has been improved by all device suppliers through specific engineering of the active layers (channel, contacts, cell pitch,...) and advanced thinning of the substrate down to . While there is still room for improvement for the active layers (reduced pitch through super junction design, dense cell pitch through trench design,...), the mechanical thinning of the SiC substrate will soon reach its limit especially in the context of the transition to 200 mm diameter SiC semiconductor substrates. This will increase drastically the contribution of the substrate to the device specific resistance (see Fig.7). As device .A specific resistance is lowered the relative contribution of the substrate (considering a thickness) is drastically increasing.

Fig. 7. SiC substrate contribution to MOSFETs specific on resistance.

Fig. 7. SiC substrate contribution to MOSFETs specific on resistance.

Now switching to SiC engineered substrate, the benefit on the electrical parameters as compared to standard material can be calculated as a function of device specific resistance ( ) at room temperature and die thickness. We clearly see that for . A improvement up to for state of the art 1200 V SiC MOSFETs and up to for next generation 1200 V SiC MOSFETs, can be envisioned (see Fig.8). Considering ultimate SiC MOSFET or state of the art JFET, improvement up to is anticipated.

Fig. 8. .A benefit enabled by integration for 1200 V SiC MOSFET.

Fig. 8. A benefit enabled by integration for 1200 V SiC MOSFET.

SiC power device ruggedness; bipolar degradation benefits ofengineered substrate

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Beyond the performance improvements discussed in the previous section, the SiC engineered substrate also helps tackle one of the key challenges in SiC power devices: bipolar degradation. Basal plane dislocations (BPDs) in substrates have emerged as crucial defects in SiC wafers during the past decades. Bipolar degradation in PN diodes and SiC MOSFETs (through the bipolar body diode) has become a significant concern affecting device ruggedness. This phenomenon occurs when BPDs are transformed into single Shockley stacking faults (1SSFs) which expand, leading to an increased device Robon. Two major strategies have been developed to address this issue: first reduce BPD density and minority carrier lifetime through the design of a proper SiC buffer layer, second use an external Schottky diode which can be monolithically integrated [11].

As a first assessment of SiC engineered substrates we have decided to use a newly developed C technique developed by ITES, Co. (Japan) that enables us to stress the material (through UV illumination) without processing and characterizing a real device.
Bipolar degradation of post epitaxy SiC substrates without diode processing was carried out on reference and engineered SiC substrates. This involves initiating bipolar degradation driven by SSF through UV illumination, followed by a focused examination of photoluminescence using a selective band-pass filter (BPF) at approximately 420 nm [12, 13]. Different UV intensities with a wavelength of 355 nm were used ( 38,75 and ).
As the UV illumination power increases, SSFs develop faster in the case of single crystal SiC compared to SiC engineered substrates (ratio of linear regression of SSF area over illumination between the 2 wafer designs) [14]. Fig. 9 provides a comparison of observation fields using the 420 nm band-pass filter (BPF).

Fig.9. Typical 10x10mm observation fields post UV illumination of bipolar degradation severity between single crystal SiC epi (left) vs. SiC engineered substrate + epi (right)

Fig.9. Typical 10x10mm observation fields post UV illumination of bipolar degradation severity between single crystal SiC epi (left) vs. SiC engineered substrate + epi (right)

We have demonstrated that both the number of Shockley stacking faults (SSF), the indicator that bipolar degradation takes place, and their typical size are lower in the case of SiC engineered substrate prepared through Smart Cut™, compared to the results obtained in standard SiC wafers (see fig.5). In parallel, Kato et al. [15] have demonstrated that the movement of partial dislocations can be suppressed by proton implantation. Proton implantation is inherent to the Smart Cut technology. Device assessment is now under evaluation on our side, and electrical stress tests are being carried out.

Power module reliability of SiC engineered substrate based dies

The original version of this paper is available on https://www.scientific.net/MSF.1156.65.pdf

Now looking at the power module integration, the thermo mechanical properties of this new material are driving the reliability of the complete stack. With SiC engineered substrate, we introduce a new semiconductor design embedding a bonded interface and a new material structure for the backside (non annealed back side ohmic contact). Main focus of this study was to assess the compatibility of this new semiconductor substrate with reliability standards, especially at the power module level. When looking at AQG324 [15] (qualification of power electronics modules for use in motor vehicle components) for power module qualification, we focused on the power cycle test (PCT) which assesses the reliability of both front and back side die assembly and connections, and assess any potential weakness at the bonded interface (see Fig.10). By limiting the (on-time of the load current) to a value of , the test exerts targeted stress on the chip - near interconnections (die-attach and top side) and any other structure within the chip itself - thus studying the potential impact of SiC engineer substrate materials properties in a conventional module setup.

Fig. 10. Schematics of conventional setup of power modules used for the AQG324 PC test [15] and the expected location of failures close to the chip marked red (from ECPE training by A.

Fig. 10. Schematics of conventional setup of power modules used for the AQG324 PC test [15] and the expected location of failures close to the chip marked red (from ECPE training by A.

Schletz)

We designed a specific test vehicle [2] with a Schottky contact built on the top side of the substrate. Current is injected in the devices under test (DUT) through this Schottky contact. A conventional metallization stack on the backside has been prepared after thinning down to and NiAl ohmic contact formation annealed by laser. These Schottky contacts act as semiconductor junctions used for heating and temperature sensing within the power cycling test. Substrates were diced into individual chips of . DUTs are mounted onto conventional DCB-substrates by silver-sintering with jetted sinter-paste. The top-side contact is connected through Al bond wires (see Fig.11).
The active power cycling tests were performed to compare the lifetime of the SiC engineered substrate compared to standard SiC reference using a well-validated setup [16]. The DUTs were mounted to a water-cooled Aluminum heatsink with coolant temperature of . The backsides (opposite to the sintered chip) of each individual DCB-substrate were direct-cooled by water-glycol coolant. Calibration of a typical device voltage drop at a given low current , to avoid self heating) at various temperatures allows for direct measurement of junction temperature of the device under test.

Fig. 11. (Left) Schematics of Schottky-Contact on SiC devices used for reliability testing, (Right) Silver-sintered sample on DCB with silver surface with top-side contact by 125 um Aluminum bond wires

Fig. 11. (Left) Schematics of Schottky-Contact on SiC devices used for reliability testing, (Right) Silver-sintered sample on DCB with silver surface with top-side contact by 125 um Aluminum bond wires

The active power cycling tests were performed to compare the lifetime of the SiC engineered substrate compared to standard SiC reference using a well-validated setup. The Power Cycling (PC) test is designed to characterize the lifetime of the semiconductor itself using short cycles ( ) with 3 seconds heating ( ) and 6 seconds cooling ( ) with a temperature swing targeting 120 K and 80 K .
has been validated up to 350 k cycles and 1600 k cycles respectively for 120 K and 80 K of temperature swing, at least for 29 samples prepared from 2 different SiC engineered substrates with silver sintering assembly. On the other side standard SiC samples had reduced lifetime.

A uniform Delta T set point was guaranteed through the adaptation of the current load to the dynamic resistance of the DUTs (reference SiC or SiC engineered substrate): higher current load for DUTs prepared with SmartSiC .
The lifetime data (see Fig.12) exhibit an exponential term as expected from the CIPS 2008 [17] as a major driving term. Looking the other way around, it means that for a given use case having its targeted lifetime, temperature swing could be increased, meaning a higher dissipated power and then an increased current. As shown on figure 12, an increase of 20 K of the maximum junction temperature could be applied without compromising the reliability of the silver sintering die attachment.

Fig. 12. Comparison of SiC standard and engineered substrates lifetime assembly for both silver sintering.

Fig. 12. Comparison of SiC standard and engineered substrates lifetime assembly for both silver sintering.

Polycrystalline SiC used as a receiver for SiC engineered substrates is driving the thermo mechanical properties of the final SiC MOSFET die and will play a crucial role on the die assembly reliability. Our main hypothesis is that elastics and/or thermoplastics properties of the polycrystalline SiC material are modifying the lifetime model (modification of the Young modulus and/or Morrow model parameters [18]). An alternative hypothesis is that either the grain size and orientation distribution of the polycrystalline SiC is modified [19] close to the interface, or polycrystalline SiC is experiencing subcritical crack growth [20]. Both mechanisms could improve lifetime. Coefficient of thermal expansion (CTE), flexural strength and Young's modulus of polycrystalline SiC material are currently performed and modeling is being performed.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1156.65.pdf

SmartSiC engineered substrates demonstrate a significant enhancement of performance and reliability. The low resistivity polycrystalline SiC (as low as vs. for ) enables higher current densities with a demonstrated improvement of SiC MOSFETs specific on resistance by more than . Proton implantation, intrinsic to the Smart Cut process, effectively suppresses Shockley stacking fault (SSF) expansion. Wafer reusability further enhances sustainability. SmartSiC™ is paving the way for next-generation SiC devices with superior efficiency and reliability.

Acknowledgements.

The original version of this paper is available on https://www.scientific.net/MSF.1156.65.pdf

This work is supported by the H2020 - ECSEL JU programme of the European Union under the grant of the TRANSFORM project 'Trusted European SiC Value Chain for a greener Economy' (ECSEL JU Grant No. 101007237).

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.65.pdf

S. Rouchier et al., in Materials Science Forum 1662-9752, Vol. 1062, pp 131-135

E. Guiot et al., International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management 2022 in Nürnberg, Germany,

E. Guiot et al., in Materials Science Forum Vol. 1092, pp 201-207,

T. Shimono et al., proceedings of Intl. Conf. Silicon Carbide and Rel. Mat. Tours 2021

H. Biard et al. in Solid State Phenomena (Vol. 344, pp. 47-52),

Yole analysis report, Power SiC manufacturing, 2024

H. Biard et al, Materials Science Forum 2024, Vol. 1124, pp 21-25, 1124, pp 21-25 doi:10.4028/p-qdRkZ7

E. Guiot et al, APEC 2024 Industry session.

G. Picun et al., Eng. Sub. with ultra-low resistivity Polycrystalline SiC Base, Bodo's Power, June 2024

M. Alaluss et al., to be published in Materials Science Forum 2025, ICSCRM 2024, Raleigh, October 2024

J.P. Konrath, Power Electronic Devices and Components 7 (2024) 100062

Y. Igarashi et al., Defect and Diffusion Forum. Vol. 425. 75-82 (2022) doi:10.4028/p-krt011

K. Takano et al, in Materials Science Forum, Vol. 1062, pp 273-277

A. Drouin et al., Materials Science Forum, Vol. 1124, pp 27-34 (2024) doi:10.4028/p-Bf6cd7

U.Scheuermann et al., Microelectronics Reliability 2010;50 (9-11):1203-9

U. Waltrich et al., CIPS 2018 - pp. 547-551 (2018)

R. Bayerer et al., Conference on Integrated Power Systems, (CIPS) 2008

B. Hu et al., IEEE Transactions on Device and Materials Reliability, Vol. 17, NO. 4, December 2017

A. Halouani et al., Microelectronics Reliability 138 (2022) 114610

F. Hild, Journal of Engineering Materials and Technology, July 1996, Vol. 118/343

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 75-81

doi: 10.4028/p-Js5aAM

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-04-03

Accepted:
2025-04-03

Online:
2025-09-04

Development of a Novel Warpage Control Method for Epi-Ready -SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

The original version of this paper is available on https://www.scientific.net/MSF.1156.75.pdf

Daichi Dojima , Seyoon Jeong , Kohei Toda , and Tadaaki Kaneko

Kwansei Gakuin University, 1, Gakuen Uegahara, Sanda, Hyogo, 669-1330, Japan

QureDA Research, Inc., 1, Gakuen Uegahara, Sanda, Hyogo, 669-1330, Japan

d.dojima@kwansei.ac.jp, jeong@kwansei.ac.jp, k.toda@kwansei.ac.jp, kaneko@kwansei.ac.jp

Abstract

We have demonstrated a novel process that precisely controls the wafer bow, a key parameter of overall warpage, of wafers to any desired value by integrating a thermal sublimation process, Dynamic AGE-ing (DA), immediately prior to the CVD epitaxial process. This method achieves atomic-level flatness of the CMP-finished surface independent of the growth and etching amounts, while concurrently eliminating sub-surface damage (SSD). When DA is applied to simultaneously etch the Si-face and grow the C-face, the wafer bow decreases linearly with increasing C-face growth. In wafers with poorer mechanical processing quality, an increase in bow is observed for C-face growth below 120 nm , likely due to the relaxation of SSD on that side. The process also removes SSD from the Si-face, ensuring that both sides are sufficiently cleared of damage. Furthermore, for wafers with an initially negative bow, simultaneous Si-face growth and C-face etching using DA produces a linear increase in bow. By applying these processes, we successfully adjusted the bow to on an 8-inch wafer that initially measured . These results indicate that, regardless of the initial bow severity, precise control of the wafer bow can be achieved without adversely affecting subsequent CVD epitaxy processes by appropriately managing the growth layer thicknesses on both faces using DA.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.75.pdf

In device manufacturing, active control of wafer bow, curvature component of the wafer warpage, is essential for improving yield. This is because the significant Bow hinders uniform resist deposition in the lithography process and causes vacuum chuck failure in the device fabrication process. [1].

Wafer bow arises when the stress states on the front and back surfaces differ. Such stress differences originate from residual effects introduced during ingot growth, the Twyman effect resulting from variations in mechanical processing quality, and uneven film deposition (Fig. 1) [2]. Residual stress in ingots is generated by thermal gradients, cooling rates, and impurity distributions during growth [3]. For example, if the C -face experiences higher temperatures during the ingot growth, defect formation to relieve thermal stress can lead to tensile stress and a positive bow bias.

If the backside surface of the wafer has a rougher processing state than the frontside, the wafer shape will have a concave shape due to the strong compressive stress originate from sub-surface damage (SSD). This effect is referred to as the Twyman effect [2, 4]. During the device fabrication process of the wafers, epitaxial growth is performed on the Si-face, and it is essential to sufficiently remove sub-surface damage (SSD) introduced by machining to prevent defects. Therefore, the mechanical processing accuracy of the Si -face tends to be emphasized more than that of the C -face.

It is important to note that the bow of "bare" wafers is determined by both internal stress and the polishing state. This variability may differ not only between manufacturers but even from wafer to wafer, complicating bow control. Furthermore, especially with the push toward large diameter such as 8 -inch processing, can further increase the challenge of maintaining uniform bow.

Deposition of thin films also influences wafer bow through intrinsic film stress. According to Stoney's formula, the bow depends on both the substrate and the epitaxial growth layer thicknesses [5]. For instance, growing a lower N-doped homoepitaxial layer can induce tensile stress, increasing the bow to form a convex shape [6]. High-temperature processes like CVD epitaxy and post-implant annealing disturb the stress balance on the wafer surfaces. Because mechanical strain is concentrated at the surface, even incremental etching (on the order of less than 100 nm , the limit of etching) can significantly alter the strain distribution and thus the bow.

Our innovative method actively controls wafer bow by relieving stress on both surfaces simultaneously. We have developed Dynamic AGE-ing (DA), a thermal sublimation etching and epitaxial growth technique that anneals SiC wafers in a quasi-closed space, enabling simultaneous etching on one side and growth on the other (Fig. 2). A key feature of DA is that it allows independent control of surface roughness regardless of the etching depth of over [7]. By removing strain from the Si-face via etching and relaxing strain on the C-face through homoepitaxial growth, SSD could be relieved, thereby minimizing its effect on wafer bow. Consequently, by optimizing the thicknesses of the epitaxial layers on both sides, the wafer bow can be tuned to any desired value (Fig. 3).

To quantitatively assess mechanical processing quality, we have also developed a laser light scattering (LLS) method [8]. By irradiating the wafer at oblique angles, the LLS intensity distribution correlates with the depth of sub-surface damage (SSD) and the processing quality, enabling a comprehensive evaluation of the balance in mechanical processing across different vendors.

In this study, we demonstrate stress relaxation on both wafer surfaces using the DA process and focus on controlling the wafer bow. We further correlate the mechanical processing quality evaluated via LLS on both the Si-face and C-face with the resulting wafer bow.

Factors affecting the bow of a single-crystal wafer

Fig. 1. Factors causing stress and warpage in singlecrystal wafer.

Fig. 2. Schematic of simultaneous control of both sides of a SiC wafer using the Dynamic AGE-ing (DA).

Fig. 2. Schematic of simultaneous control of both sides of a SiC wafer using the Dynamic AGE-ing (DA).

Fig. 3. Differences between CVD epitaxy and DA process and their impact on wafer bow.

Fig. 3. Differences between CVD epitaxy and DA process and their impact on wafer bow.

Experiments

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The samples were off-cut towards [11-20] direction and epi-ready polished on the (0001) Si-face wafers purchased from several vendors. The wafer sizes were 6 - and 8 -inch, and the details of sample information used for the DA process are summarized in Table 1.

The samples were measured for LLS intensity. The incident laser was -polarized to the wafer and wavelength of 355 nm . The obtained LLS intensity values were calibrated by the amplification factor. The same samples were also measured by laser interferometry using the NIDEK Slanting Incidence Interference Method Flatness Tester. This equipment measures the sample in a vertical position. The mode values of the LLS intensities for the Si - and C -faces were then determined. Photoluminescence imaging (PLI-200) was also used to observe defects across the entire surface.

DA process was used for sublimation etching and sublimation epitaxial growth. The DA etching was performed on the Si -face at a temperature of for minutes, with an etching depth of approximately 80 nm to set for the Si-face. During the etching of the surface, an epitaxial growth layer was simultaneously grown on the back surface. Sublimation epitaxial growth was then used to attach an epitaxial growth layer (carrier concentration: 1.0 to ) of about to to the Si-face. After each experiment, the bow of the wafer was measured.

Table 1. Details of sample information used in the DA process.

| Wafer I | Wafer II | Wafer III | Wafer IV | Wafer V | Wafer VI
Vendor | A | D | A | A | B | D
Grade | Production | Production | Research | Research | Production | Research
Diameter [mm] | 150.1 | 150.0±0.2 | 150.1 | 150.1 | 149.9 | 200.0±0.2
Thickness [μm] | 370 | 367 | 375 | 365 | 348 | 497
Resistivity [Ω·cm] | 1.7×10⁻² | 1.9×10⁻² | 1.7×10⁻² | 1.7×10⁻² | 1.7×10⁻² | 2.0×10⁻²
C-face LLS intensity [mV] | 3.5×10⁻¹ | 2.3×10⁻¹ | 1.0×10¹ | 8.4×10⁰ | 7.3×10¹ | N/A
Si-face LLS intensity [mV] | 2.1×10⁻² | 2.2×10⁻⁴ | 1.4×10⁻² | 2.0×10⁻² | 1.2×10⁻² | 1.7×10⁻²

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1156.75.pdf

To investigate vendor strategies for controlling wafer warpage, the process quality balance of both sides of a 6-inch wafer from each vendor was quantified and related to the bow. Fig. 4 shows a graph relating the bow to the mode value of the LLS intensity for both Si- and C-faces of wafers from several vendors; colors represent vendors, with circles and crosses for Si - and C -face, respectively.

Fig. 4. Laser light scattering (LLS) intensity mode value - bow value graph for the Si-face and C-face of -inch 4 H -SiC wafers from vendors A to D.

Fig. 4. Laser light scattering (LLS) intensity mode value - bow value graph for the Si-face and C-face of -inch 4 H -SiC wafers from vendors A to D.

For the 6-inch wafers used in the DA process, the values for the Si- and C-faces are connected by lines. From the graph, it can be observed that wafers from the same vendor have similar scattering intensities on both the Si- and C-faces. It also shows that the bow is biased in the positive direction, which is due to residual stresses introduced during bulk growth. The SSD and rough surface on the C-face tend to reduce the bow, while the residual stress within the wafer increases it. In other words, wafers with an initially high positive bow caused by residual stress are controlled by adjusting the mechanical processing quality of the C-face. This suggests that, different vendors have different strategies for controlling wafer warpage and may utilize the Twyman effect.

Fig. 5 shows the evolution of wafer bow for two wafers processed by DA-growth on the C-face and DA-etching on the Si-face over 2-2.5 hours. Both Wafer I and Wafer II exhibit a linear bow change with increasing epitaxial thickness as predicted by Stoney's formula-except for the initial DA process on Wafer I. In that first process, Wafer I shows a non-linear bow change when DA-growth and DA-etching are applied simultaneously. Since the SSD on the Si-face is negligible (LLS intensity ), this non-linearity is attributed to defect formation at the C-face interface due to high SSD. Photoluminescence images support this, revealing an epitaxial defect density of on Wafer I versus 0/ on Wafer II. These results suggest that early defect formation relieves stress from C-face SSD and that DA epitaxial growth both mitigates SSD and calibrates stress variations from doping differences. Additionally, the reversal of bow from positive to negative in Wafer II indicates that the initial bow can be adjusted to specifications, potentially reducing yield losses. In a related experiment with Wafer III, where 80 nm of the Si-face was etched and 120 nm of the C-face grown, the bow peaked at 120 nm before decreasing linearly, further confirming that changes in SSD distribution during thermal processing drive bow behavior via early defect formation.

If the cause of the exceptional bow changes observed at the beginning of DA-growth on the C-face of wafer I is defect formation at the interface between the substrate and the epitaxial growth layer, it should impact the initial stage of epitaxial growth on the C-face. To investigate the effect of SSD concentrated on the surfaces of both sides of the wafer on the bow during thermal sublimation etching and epitaxial growth, the DA process was used to simultaneously etch the Si-face by 80 nm and grow the epitaxial layer on the C-face by 120 nm . The results of the bow changes are shown in Fig. 5. Wafer III. The bow value reached a maximum at 120 nm of epitaxial growth on the C -face and then decreased linearly. This result indicates that the bow is significantly affected by changes in the SSD distribution on both sides of the wafer during the thermal sublimation etching of the Si -face and the epitaxial growth on the C-face. This suggests that the stress caused by the SSD on the C-face is released through defect formation, which occurs at the very beginning when the interface with the growth layer is formed.

Fig. 5. Measurement results of the bow values during the DA process for wafers I - III. PL images of the epi-layer formed on the C-face of wafer I and II.

Fig. 5. Measurement results of the bow values during the DA process for wafers I - III. PL images of the epi-layer formed on the C-face of wafer I and II.

Fig. 6. Measurement results of bow change when etching the Si -face and growing the C -face using DA for wafers IV and V and then growing the Si-face and etching the C-face.

Fig. 6. Measurement results of bow change when etching the Si -face and growing the C -face using DA for wafers IV and V and then growing the Si-face and etching the C-face.

Fig. 6. shows the change in wafer bow when wafers from vendors A and B are processed by performing DA-growth on the C-face while DA-etching the Si-face for 2 hours using the DA process. This is followed by DA-growth on the Si-face and DA-etching of the C-face for a total of 40 to 80 minutes over multiple sessions. The graph shows that, when wafers from vendors A and B are processed by DA-growth on the Si-face and DA-etching of the C -face, the bow increases linearly with the epitaxial layer thickness on the Si-face for both wafers (circled by the blue dotted line), despite differences in C-face process quality.

Fig. 7 shows bow control using the DA process on an 8 -inch wafer from Vendor D. The initial bow was . After Si-face etching and C-face growth using DA, the bow decreased to , but after Si-face growth and C-face etching, it recovered to . Fig. 8 shows a smooth surface obtained from the LLS mapping after DA-etching of the Si-face [9]. It has also been reported that DA is a method capable of controlling surface roughness, regardless of etching depth and the amount of epitaxial growth [7]. This process allows for the mitigation of device-killer defects on the wafer and consistent control of the bow.

As wafer diameters increase, large warpage is becoming a serious issue. In this study, the demonstrated control of warpage using the DA process for 8 -inch large-diameter wafers can significantly contribute to cost savings for large-diameter wafers and improve wafer yield.

Fig. 7. Bow control results for wafer VI using the DA process.

Fig. 7. Bow control results for wafer VI using the DA process.

Fig. 8. LLS images of the Si-face of wafer VI after DA-etching.

Fig. 8. LLS images of the Si-face of wafer VI after DA-etching.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.75.pdf

This study demonstrates a novel process to control the wafer bow, i.e., the key aspect of overall warpage, of wafers to any desired value by incorporating Dynamic AGE-ing (DA) between polishing and CVD epitaxy. Measurements on epi-ready polished wafers from vendors A, B, C, and D revealed a consistent positive bow bias. Laser light scattering (LLS) evaluations showed that all vendors processed the C-face more roughly than the Si-face, suggesting that residual stress from ingot fabrication induces positive bowing and that vendors may intentionally roughen the C-face (via the Twyman effect) to counteract this stress.

Using the DA process for simultaneous Si-face etching and C-face growth, the wafer bow decreased linearly with increasing C-face growth, while surface roughness was independently controlled. This indicates that wafers with a positive bow can be adjusted to zero or even negative values. Notably, only one wafer with a rough C-face exhibited an increased bow at 120 nm C -face growth, likely due to defect formation mitigating SSD. Additionally, 8-inch wafer bow was controlled from to in this mechanism.

Importantly, these results not only confirm that the bow can be tuned to 0 nm but also suggest a new process strategy for high-thickness epitaxy: pre-adjusting the wafer bow to a negative value prior to epitaxial growth. This approach could help to optimize film deposition and improve overall process yields without adversely affecting subsequent CVD epitaxy.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1156.75.pdf

The authors are grateful to Toyota Tsusho Corporation for technical support, YGK Corporation, and EpiQuest, Inc. for equipment support.

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.75.pdf

N. Piluso, S. Rinaldi, S. Lorenti, A. Bassi, A. Severino, S. Coffa, An Approach to Predict 4HSiC Wafer Bending after Back Side Thinning by Substrate Resistivity Analysis, Materials science forum 1004 (2020) 57-62.

F. Guo, C. Shao, X. Chen, X. Xie, X. Yang, X. Hu, X. Xu, Shape modulation due to sub-surface damage difference on N-type wafer during lapping and polishing, Mater. Sci. Semicond. Process 152 (2022) 107124.

B. Gao, K. Kakimoto, Three-Dimensional Modeling of Basal Plane Dislocations in 4H-SiC Single Crystals Grown by the Physical Vapor Transport Method, Cryst. Growth Des. 14 (2014) 1272-1278.

F. Twyman, Prism and lens making, 2nd ed., Hilger & Watts, London, 1952.

G.G. Stoney, The tensions of metallic films deposited by electrolysis, Proc. R. Soc. Land. A82 (1909) 172-175.

B. Kallinger, P. Berwian, J. Friedrich, G. Muller, A. Weber, E. Volz, G. Trachta, E. Spiecker, B. Thomas, Doping induced lattice misfit in 4H-SiC homoepitaxy, J. Cryst. Growth, 349 (2012) 43-49.

D. Dojima, K. Tayake, K. Shigematsu, K. Toda, T. Kaneko, Macro Step Bunching/Debunching Engineering on off (0001) to Control the BPD-TED Conversion Ratio by Dynamic AGE-ing , Defect and diffusion forum, 434 (2024) 165-172.

D. Dojima, K. Shigematsu, K. Tayake, K. Toda, T. Kaneko, Non-Destructive Quantification of In-Plane Depth Distribution of Sub-Surface Damage on Wafers Using Laser Light Scattering, Defect and diffusion forum 434 (2024) 157-163.

D. Dojima, D. Dansako, M. Maki, K. Toda, T. Kaneko, 4H-SiC Full Wafer Mapping Image of CMP-Finished Sub-Surface Damage by Laser Light Scattering, Defect and diffusion forum 343 (2023) 43-50.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1156, pp 83-92

doi: 10.4028/p-qcdYf7

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-05-22

Accepted:
2025-05-28

Online:
2025-09-04

Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

Sven STRÜBER , Jonas IHLE , Julian ZÖCKLEIN , Johannes STEINER , Peter J. WELLMANN *

¹Crystal Growth Lab, Materials Department 6, University of Erlangen-Nürnberg (FAU), Martensstr. 7, 91058 Erlangen, Germany

sven.strueber@fau.de, bjonas.ihle@fau.de, cjulian.zoecklein@fau.de, djohannes.steiner@fau.de, epeter.wellmann@fau.de

*Corresponding author

Keywords: Bulk growth, Physical vapor transport, PVT, Yield.

Abstract

This work discusses three aspects of the PVT growth process to reach a higher SiC crystal yield: (i) Type of carbon isolation material and procedure to maintain reproducible growth conditions from one process to the next. (ii) The pros and cons of temperature and power control (or a mixture of both) during the SiC crystal growth phase of the PVT process; and (iii) the selection of a set of process parameters and the specifications of the grown SiC crystal, which serve as a fingerprint of reproducible growth conditions (related to the selection and design of hot zone isolation components).

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

The bulk growth process of SiC using the physical vapor transport (PVT) method may be called mature [1-3]. A single-crystalline diameter of 150 mm is state of the art, while a crystal diameter of 200 mm is being promoted as the new standard. Major R&D efforts focus on reducing the dislocation density even further. In this context, improving the yield of the PVT process is a key task. In this paper, we discuss the role of carbon isolation, a key element in achieving the desired growth temperature at a given heating power. To ensure consistent growth conditions throughout the process, which typically takes over 10 days, we discuss the pros and cons of power- or temperature-based process control. Finally, we suggest a procedure to classify reproducible growth processes. Please note that other sources of process instability, such as graphite quality, carbon crucible quality, and SiC seed quality and mounting, are not addressed in this work.

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

In our study, we analyzed forty 150 mm PVT growth processes, all of which used the same fundamental hot-zone design. Two minor design variations were conducted: cooling channels A and B and crucible variants related to seed mounting #1 and #2 (Fig. 1). Compared to an industrial standard growth process, the number of crystals analyzed is rather low. Nevertheless, the study yields clear recommendations for increasing process reproducibility and yield related to the challenging isolation components of the hot zone.

PVT Furnace. The study was carried out using the 150 mm PVT furnace "Sicma 3" provided by the company PVA Crystal Growing Systems GmbH (Wettenberg, Germany), and installed in the crystal growth lab at FAU.

Hoz-Zone Design. The basic SiC PVT-technology developed in the crystal growth lab at FAU over the last 15 years makes use of the hotzone design I which is highly scalable for crystal diameters from 100 to 150 mm and even 200 mm . In addition, it is hardly sensitive to the heating geometry (shape of induction coil or arrangement of resistive heaters). As a result, the hotzone may be used in many different PVT furnaces with no or only small adaptation. As a previous example, in [4] we have shown, that 100 mm SiC boules can be grown in two different PVT furnaces, i.e. water cooled (FAU

PVT machine) and air cooled (Sicma 3 PVT system from PVA Crystal Growing Systems GmbH) growth chamber, without any adaptation (Fig. 2). The hotzone design developed at FAU aims to serve crystal growth industries with a basic starting growth technology. A SiC crystal recently grown for the presented study is depicted in Fig 3. The fact that the crystalline R&D quality falls behind the industrial standard is related to the lab mission where usually special growth runs stand in the foreground compared to optimization of one special setting. Best areas ( ) in the 150 mm SiC boules presented in this study are MPs , TSDs TEDs and BPDs , respectively.

Fig. 1. Sketch of the hot zone design variations used within the presented study.

Fig. 1. Sketch of the hot zone design variations used within the presented study.

Fig. 2. The basic hotzone design I designed by FAU is compatible with different PVT furnace designs like the Sicma series of the company PVA Crystal Growing Systems GmbH.

Fig. 2. The basic hotzone design I designed by FAU is compatible with different PVT furnace designs like the Sicma series of the company PVA Crystal Growing Systems GmbH.

Fig. 3. Example of the side-view of an as-grown (grown using basic hotzone configuration I, cooling channel B and crucible variant #2).

Fig. 3. Example of the side-view of an as-grown (grown using basic hotzone configuration I, cooling channel B and crucible variant #2).

PVT Process Control. Computer simulation of the temperature field and optionally also of the mass transport and/or resulting stress in the grown crystal, is an essential standard tool in SiC PVT-growth. For some original publications see [5-10]. The growth process at temperatures above in a closed graphite crucible allows only limited sensory access to the physical conditions inside the growth cell. Despite the fundamental hot zone design, the PVT growth process is usually controlled only by setting of the heating power and inert-gas pressure. By measurement of the temperatures at the crucible top and bottom using optical pyrometers, feedback is given to control the progress of the growth process. In principle, X-ray in-situ visualization methods in 2D and 3D [11-13] have been demonstrated since many years, but only few growth facilities are using these advanced methods.

T-Field Calculation. Computer simulation has proved to give valuable insight into the growth conditions in front of the crystal growth interface. However, the reliability and technical applicability of the temperature field and mass transport calculations strongly depend on the proper knowledge of the temperature dependent materials data like the temperature dependent heat conductivity, the coefficient of thermal expansion and the electrical conductivity (in case of inductive heating), to name a few important parameters. Often those values are not known from the material provider data sheets. Therefore, we have conducted intense investigations of the thermal properties of carbon materials in the growth temperature regime which have been published in [4, 14, 15].

In addition, also the heat conductivity of the source material has been studied using advanced physical models [4, 16]. It turned out for practical reasons that the source material may be treated quite precisely using a two-zone model where the condensed and partially sintered SiC source may be treated as a porous media (pore size ) using Eq. 1 (see [17, 18]):

The fluffy residual carbon which surrounds the source materials with evolving process time may be approximated with the physical thermal properties of a typical carbon soft felt isolation. Using this approach, temperature field calculations which match the experimental conditions quite well have been recently demonstrated (see e.g. [19]. Usually the T-field calculation (for a given heating power) in the crystal growth lab at FAU match with experimental finding with a deviation of 10 to which is an error less than at the growth temperature above .

Note on impact of SiC source material on process yield. In [20] it was shown that the heat conductivity of the starting SiC source material, which is strongly related to the SiC powder size distribution, has a significant influence on the temperature gradient at the crystal growth interface in a standard growth cell configuration as shown in Figs. 1 and 2. In terms of growth process yield this is a tremendous impact. In a growth run to growth run sequence, a changing SiC source heat conductivity causes varying axial temperature gradients and SiC species supersaturation at the growth interface. As reported in [20], the growth rate and even the crystal shape will vary which itself is a source for the enhanced occurrence of crystal defects lowering the growth process yield. Therefore, from the perspective of process yield it is mandatory that the SiC source properties do not vary much. It is self-explanatory that an inhomogeneous SiC source material also reduces the process yield.

Yield Limitation during SiC PVT Bulk Growth

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

Role of Heat Conductivity Carbon Isolation. At process temperatures above mainly carbon isolations are applied which withstand the growth conditions. At such high temperatures, degradation because of microscopic morphologic changes and aging related to Si-containing leakage of vapor from the growth cell are very common. We have designed the hotzone in a way that about of the carbon isolation is replaced by new material before each growth run (Fig. 5). We rather prefer this procedure than adapting the heating power in a growth run to growth run manner, until the isolation unit is basically "consumed".

Fig. 4. Illustration of the areas where the carbon isolation ages significantly during a PVT growth process.

Fig. 4. Illustration of the areas where the carbon isolation ages significantly during a PVT growth process.

Table 1. Heating Power versus growth temperature (top of crucible) (basic hot-zone configuration I, cooling channel B, crucible variant #2,) of 4 nominally equal growth processes.

Power set point [kW] | T at crucible top [°C] | Growth rate [μm/h]
15.5 +/- 0.1 | 2020 +/- 20 | 143 +/- 4

Hereby we are able to start each growth process with extremely high reproducibility using the power process control mode (see section on "Power versus temperature process control" and example presented in Table 1). Using these procedures, the T-measurement by optical pyrometers on top of the growth cell indicated a high process reproducibility. In the case of an induction heating power of 15.5 kW , we observed a constant temperature of at the crucible top which varied only by (see Table 1). This value fluctuation is less than which comes close to measurement precision of optical ratio pyrometers. In addition, the observed crystal growth rate of ca. (determined in the center of the boule) varied less than . Both values indicate that the evolution of the SiC crystal growth process has become very reproducible with the routinely replacement of of the most aged carbon isolation.

Fig. 5. Relation of growth rate versus Temperature at crucible top for two different cooling channels A and B (crucible variant #1, basic hotzone configuration I).

Fig. 5. Relation of growth rate versus Temperature at crucible top for two different cooling channels A and B (crucible variant #1, basic hotzone configuration I).

Experimentally, in several different hot-zone designs (this study and also former studies not shown here) and fixed inert-gas pressure we observed an almost linear growth rate to temperature (or heating power) relation. Since the growth rate is dependent on many thermodynamic as well as growth-kinetic phenomena, this finding represents more like a rule of practice, which proved to be valuable for the planning of new PVT growth processes. Fig. 5 depicts the temperature to growth rate evolution for two 150 mm hot-zone designs (=different cooling isolation settings A and B) of this study. The result indicates on one hand that a quite precise tuning of the SiC crystal growth rate is possible which is intended to lay around . On the other hand, the result also supports the constant power process control which enables a steady (= undisturbed) growth process (detailed discussion see in the forthcoming section on "Power versus temperature process control").

To further elucidate the role of the carbon isolation properties and to deduce a more general understanding of the experimental results presented in Table 1 and Fig. 5, we have carried out computer simulation of the thermal field of our growth setup. The area of the carbon isolation which suffers most during a high temperature PVT process is located directly in contact with the dense graphite crucible. The hottest areas are located in the cylindric part which surround the crucible as indicated in Fig. 4 (center image).

During aging of fibrous carbon isolation, densification and a kind of sintering of the fiber is observed, which causes a local increase of the material heat conductivity. To account for this aging / degradation we adapted the temperature heat conductivity by a constant factor. As definition, an increase of the heat conductivity due to sintering of the isolation fibers by the factor 1.2 or 1.5 equals an isolation degradation by or , respectively. From an experimental point of view, we often observed an aging of the directly to the crucible attached fibrous isolation by (comparison of 11 processes with identical settings) for growth runs of ca 100 hours. The aging value will further increase for longer growth runs (or repeated growth runs with no exchange of the aged isolation parts).

Computer simulation of the temperature field of the 150 mm PVT hotzone shows that the temperature at the crucible top increases linearly with the heating power at typical growth regimes at (Fig. 6). Due to fact that the thermal properties of the hotzone components are nonlinear, this finding is surprising and reflects a special feature of the FAU hotzone design. Interestingly, in case of aging, this linear behavior remains, however, the temperature drops at a constant heating power due to the altered thermal isolation.

Calculated Temperature & Heating Power relationPVT hotzone)

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

Fig. 6. Computer simulation of the Temperature field: Analysis of the temperature on of the growth cell as a function of the heating power for two cases of carbon isolation aging (new and aging of in the vicinity of the crucible).

Fig. 6. Computer simulation of the Temperature field: Analysis of the temperature on of the growth cell as a function of the heating power for two cases of carbon isolation aging (new and aging of in the vicinity of the crucible).

Table 2. Computer simulation of the temperature field: Impact of the heating power on the crucible top temperature, the temperature gradients and related supersaturation at the growth interface.

P coil [kW] | T crucible top [°C] | T diff crucible top-bottom [°C] | T radial gradient [°C/cm] | Supersaturation σ of growth limiting species SiC₂ | Δσ compared to 16 kW heating [%]
16.0 | 2002 | 239 | 1.2 | 0.41 | 0
16.1 | 2007 | 239 | 1.1 | 0.40 | -0.5
16.2 | 2012 | 240 | 1.1 | 0.40 | -0.9
16.3 | 2017 | 240 | 1.1 | 0.40 | -1.4
16.4 | 2022 | 240 | 1.1 | 0.40 | -1.8
16.5 | 2027 | 241 | 1.1 | 0.40 | -2.3
16.7 | 2037 | 241 | 1.1 | 0.39 | -3.2
17.0 | 2052 | 242 | 1.1 | 0.39 | -4.5
17.5 | 2076 | 244 | 1.1 | 0.38 | -6.5
18.0 | 2099 | 246 | 1.1 | 0.37 | -8.5

Interestingly, during power increase (Table 2) the calculated temperature difference between crucible top and bottom as well as the radial temperature gradient at the seed remain almost constant at around and , respectively. As expected, the supersaturation (driving force for crystallization) at the seed slightly drops. Note: The SiC growth process is carried out with low inert gas pressure ( 200 to 1000 Pa ) which lies in the same range as the subliming SiC-related gas species and . Therefore, the growth rate is only slightly diffusion limited but rather determined by the sublimation rate of the SiC powder. This coincides with the experimental finding in Fig. 5 that the growth rate increases with process temperature.

In the next step we have analyzed our modelling data with the aim to identify the necessary higher heating power to compensate the heat loss in the case of an aged isolation (plot in Fig. 7 and data set in Table 3). To maintain a constant crucible temperature, the aging of the carbon isolation can be compensated by a higher heating power. Up to an aging of a linear heating power to aging relation is found. At aging values of and higher a sublinear relation is found. The latter indicates that the outer, not aged isolation retains a further heat loss once the inner part is basically "consumed" (compared to the unaged outer isolation part).

Table 3. Computer simulation of the temperature field: Impact of aging of the carbon isolation in the vicinity of the crucible on the T-field at constant heating power.

Aging
1=new
1.5=50% aging
2.0=100% aging
P coil
[kW]
T crucible
top [°C]
T diff crucible
top-bottom [°C]
T radial gradient
[°C/cm]

1.0
16.0
2002
239
1.2

1.1
16.0
1992
238
1.2

1.2
16.0
1980
238
1.2

1.3
16.0
1971
237
1.2

1.5
16.0
1954
237
1.2

1.7
16.0
1940
236
1.2

2.0
16.0
1923
235
1.2

Heating Power to stabilize Tcrucible-top at

Fig. 7. Computer simulation of the temperature field: Compensation of the heat loss due to aging by increase of the heating power (case: constant temperature at crucible top).

Fig. 7. Computer simulation of the temperature field: Compensation of the heat loss due to aging by increase of the heating power (case: constant temperature at crucible top).

Table 4. Computer simulation of the temperature field: Compensation of the heat loss due to aging by increase of the heating power (case: constant temperature at crucible top) and influence on temperature gradients and SiC growth conditions inside the crucible.

Table 3 shows a further import property of the FAU hot zone design to reach reproducible growth runs. The axial and radial temperature gradients inside the growth cell remain "untouched" by the aging of parts of the thermal isolation and heating power compensation. Again, due to the nonlinear T-dependency of the thermal carbon materials properties, one would have expected a more complex system reaction. In the case of a heating power adaptation to compensate the isolation aging related heat losses (Table 4) even a constant supersaturation at the growth front of the seed is observed. These constant values prove that the thermal management how to heat and how to maintain the outflow of heat has been resolved in the FAU hotzone in a very good manner. The latter being a prerequisite for a high crystal growth yield. From the reported finding one may conclude that the FAU hotzone is quite feasible to be used in a mainly temperature-based process control. Because of the risk of a temperature measurement error, however, we favor the mainly power controlled PVT process.

Power versus temperature process control. Considering a T-measurement error of optical pyrometers of at least at and potential distortions in the optical alignment of the system during the growth process, a total T -measurement error of is typical, Nevertheless, distortions in the T-measurement above may occasionally occur. In addition, a thermally highly isolated hot-zone (to save heating energy) exhibits long reaction intervals before a change in the heating power affects the hot-zone temperature. Therefore, it is recommended to use the temperature measurement/control as an indicator that the right T-value for a given heating power has been reached at the beginning of the growth process. Throughout the growth process a constant heating power mode is recommended for stable growth process conditions (Fig. 8). This includes a precise monitoring of the temperature of the hotzone and an optional soft feedback-loop to power control like a soft power adaption to keep the supersaturation at the growth front constant.

Fig. 8. Sketch of the suggested Power controlled PVT growth process.

Fig. 8. Sketch of the suggested Power controlled PVT growth process.

Indicators for reproducible growth conditions. The simple dataset of heating power, temperature of the hot-zone (top and/or bottom pyrometer) and the growth rate (or final crystal height/weight at a given duration of the growth period, see Fig. 3) as used in Table 1 proved to be powerful to validate reproducible growth condition. Additional valuable data to be monitored (not discussed in this paper) are weight changes of the crucible and other hot zone components and inspection of the carbon isolation parts to identify/quantify aging.

Other indicators, like shape of the crystal cap (= growth interface), position and size of crystal facets or macroscopic morphologic features of the crystal cap are more related to hotzone design, the seed mounting/pre-preparation or the impacts of the source material which were not in the scope of this study.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

We reported on how heating isolation improves the yield during SiC crystallization using the PVT method. Systematic monitoring of the aging of the carbon isolation and partial renewal of distorted areas are crucial to maintaining stable, reproducible growth conditions. This partial material exchange procedure enables nearly complete recovery of aging carbon isolation. Therefore, the authors strongly favor this procedure over continuous usage of carbon isolation, which requires steady aging to be
compensated for by adapting the heating power from one growth run to the next. In addition to partially renewing the carbon isolation, we favor a power-controlled growth process over the temperature-controlled process. However, a soft, optional releveling of the power to maintain a constant temperature on the crucible top or bottom is believed to increase the yield of the growth process.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

This work has been partially funded by the German Science Foundation (contracts WE210712/2, WE 2107-15/2) and PVA Crystal Growing Systems GmbH (Wettenberg, Germany)(contract wtt-19174).

References

The original version of this paper is available on https://www.scientific.net/MSF.1156.83.pdf

P. J. Wellmann, J. Steiner, S. Strüber, M. Arzig, M. Salamon, N. Uhlmann, B. D. Nguyen,S. Sandfeld, Diamond and Related Materials, 109895 (2023)

P. J. Wellmann, M. Arzig, J. Ihle, M. Kollmuss, J. Steiner, M. Mauceri, D. Crippa, F. La Via, M. Salamon, N. Uhlmann, M. Roder, A. N. Danilewsky, B. D. Nguyen,S. Sandfeld, Materials Science Forum, 1062, 104 (2022)

P. Wellmann, M. Schöler, P. Schuh, M. Jennings, F. Li, R. Nipoti, A. Severino, R. Anzalone, F. Roccaforte, M. Zimbone,F. La Via, "Status of 3C-SiC Growth and Device Technology," in Wide Bandgap Semiconductors for Power Electronics, 2021, pp. 93.

J. Steiner, M. Arzig, A. Denisov,P. J. Wellmann, Crystal Research and Technology, 55, 2, 1900121 (2020)

M. Pons, E. Blanquet, J. M. Dedulle, I. Garcon, R. Madar,C. Bernard, J.Electrochem.Soc., 143, 11, 3727 (1996)

D. Hofmann, R. Eckstein, M. Kölbl, Y. Makarov, S. G. Müller, E. Schmitt, A. Winnacker, R. Rupp, R. Stein,J. Völkl, Journal of Crystal Growth, 174, 669 (1997)

Y. E. Egorov, A. O. Galyukov, S. G. Gurevich, Y. N. Makarov, E. N. Mokov, M. G. Ramm, M. S. Ramm, A. D. Roenkov, A. S. Segal, Y. A. Vodakov, A. N. Vorob'ev,A. I. Zhmakin, Mat.Sci.Forum, 264-268, 61 (1998)

M. Selder, L. Kadinski, Y. Makarov, F. Durst, P. Wellmann, T. Straubinger, D. Hofmann, S. Karpov,M. Ramm, Journal of Crystal Growth, 211, 333 (2000)

P. J. Wellmann, M. Pons, Journal of Crystal Growth, 303, 337 (2007)

R. Ma, H. Zhang, V. Prasad,M. Dudley, Crystal Growth & Design, 2, 3, 213 (2002)

P. J. Wellmann, M. Bickermann, D. Hofmann, L. Kadinski, M. Selder, T. L. Straubinger,A. Winnacker, Journal of Crystal Growth, 216, 263 (2000)

P. Wellmann, G. Neubauer, L. Fahlbusch, M. Salamon,N. Uhlmann, Crystal Research and Technology, 50, 1, 2 (2015)

M. Arzig, M. Salamon, N. Uhlmann,P. J. Wellmann, Advanced Engineering Materials, ja, 1900778 (2019)

M. Schöler, P. Schuh, J. Steiner,P. J. Wellmann, Materials Science Forum, 963, 157 (2019)

J. IhleP. J. Wellmann, Crystal Research and Technology, n/a, n/a, 2400080 (2024)

M. Arzig, J. Steiner, M. Salamon, N. Uhlmann,P. J. Wellmann, Materials, 12, 16, 2591 (2019)

A. L. Loeb, Journal of the American Ceramic Society, 37, 2, 96 (1954)

R.-H. Ma, Q.-S. Chen, H. Zhang, V. Prasad, C. M. Balkas,N. K. Yushin, Journal of Crystal Growth, 211, 352 (2000)

J. Schultheiß, J. Ihle, S. Nanot, S. Bonanomi, D. Munoz, R. Hammer,P. Wellmann, Solid State Phenomena, 362, 65 (2024)

M. Arzig, M. Salamon, N. Uhlmann, B. A. Johansen,P. J. Wellmann, Materials Science Forum, 924, 245 (2018)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Keywords Index

4

4h-sic New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

A

Adhesive Bonding High-Temperature Adhesive Bonding of -SiC Substrates

B

Bipolar Degradation SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Bonded Substrate Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Bulk Growth Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

C

Characterization Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Crystal Growth Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

D

Defects Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

E

Effusion High-Temperature Adhesive Bonding of -SiC Substrates

Engineered Substrate Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Engineered Substrates Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

Epitaxial Defects Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Epitaxial Growth Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

G

Gan New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

H

Heterogenous Integration High-Temperature Adhesive Bonding of -SiC Substrates

High Resistivity Process Gas Control for High-Resistance HPSI-SiC Growth

Hpsi-sic Process Gas Control for High-Resistance HPSI-SiC Growth

Hydrogen Process Gas Control for High-Resistance HPSI-SiC Growth

I

Ion Slicing Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

L

Layer Transfer Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

Low Resistivity SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

M

Mocvd New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

O

Optical Microscopy New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

P

Photoluminescence New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Physical Vapor Transport Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

Plasma Etching A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Power Cycling SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Ppde A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Prismatic Slip New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Pvt Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method; Process Gas Control for High-Resistance HPSI-SiC Growth; Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

Pvt Growth New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

S

Semi-insulating 4h-sic Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

SiC Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method; New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT; High-Temperature Adhesive Bonding of -SiC Substrates

SiC Layer Transfer SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

SiC Mosfets SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Silicon Carbide Epitaxy A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Smartcut™ SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Smartsic™ SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Specific On Resistance SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Substrate Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Surface Preparation A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

X

X-ray Topography Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method; New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Y

Yield Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

Authors Index

A

Albrecht, K. Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Allibert, F. SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

B

Boninelli, S. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Bouch, C. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Briccetti, H. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

C

Calabretta, C. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Calabriso, D. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Chen, Z. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Choi, J. Process Gas Control for High-Resistance HPSI-SiC Growth

Csato, C. Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

D

Dojima, D. Development of a Novel Warpage Control Method for Epi-Ready -SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Drouin, A. SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Dudley, M. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Dukes, D. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Dupre, M. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

E

Ellison, A. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Erlekampf, J. Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

G

Gersappe, D. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Goldberg, A. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Griffin, N. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Griswold, S. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Guiot, E. SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

H

Hamann, D. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Hens, P. Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Hu, S. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

I

Iatosti, C. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Ihle, J. Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

Iucolano, F. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

J

Jayaprakash, H. Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

Jeong, S. Development of a Novel Warpage Control Method for Epi-Ready -SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Johnson, S. A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

K

Kallinger, B. Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Kaneko, T. Development of a Novel Warpage Control Method for Epi-Ready -SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Karhu, R. Study on Homoepitaxy Performance of Engineered 150 mm and 200 mm SiC Substrates in a Multi-Wafer Batch Reactor

Kayang, K. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Kegg, T. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Kim, J. Process Gas Control for High-Resistance HPSI-SiC Growth

Kim, S. Process Gas Control for High-Resistance HPSI-SiC Growth

Koch, R. Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

Krippendorf, F. Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

Ku, K. Process Gas Control for High-Resistance HPSI-SiC Growth

L

Lang, D. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Lee, C. Process Gas Control for High-Resistance HPSI-SiC Growth

Lee, G. Process Gas Control for High-Resistance HPSI-SiC Growth

Lee, S. Process Gas Control for High-Resistance HPSI-SiC Growth

Lee, W. Process Gas Control for High-Resistance HPSI-SiC Growth

Lilja, L. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Liu, Y. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

M

Martin, A. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Moeggenborg, K. A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

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Park, J. Process Gas Control for High-Resistance HPSI-SiC Growth

Parmar, P. High-Temperature Adhesive Bonding of -SiC Substrates

Pfusterschmied, G. High-Temperature Adhesive Bonding of -SiC Substrates

Philpott, R. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Picun, G. SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Piluso, N. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

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Raghothamachar, B. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

Rana, T. A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Reyes, L. A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Riva, C. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Roy, E. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Rueb, M. Thick Semi-Insulating 4H-SiC Layer Exfoliation for Non-Epitaxial Engineered Substrates

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Safko, M. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Sanchez, E. A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Schmid, U. High-Temperature Adhesive Bonding of -SiC Substrates

Schunemann, P. Lab-Based X-Ray Topography Characterization of Axial Samples from 4H-SiC Boules Grown by PVT Method

Schwarzenbach, W. SmartSiC ™ & 200mm Engineered Substrate: Enabling SiC Power Devices with Improved Performances and Reliability

Severino, A. New Insights in Orientation and Growth of 150 mm GaN on SiC for HEMT

Steiner, J. Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

Stokeley, K. A Study of Epitaxial Growth on 4H-SiC Substrates Treated by Plasma Polish Dry Etch (PPDE) Process

Strüber, S. Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

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Toda, K. Development of a Novel Warpage Control Method for Epi-Ready -SiC Wafers by Depositing Homoepitaxial Layers on both Si- and C-Faces

Torres, V. New Insights into the Occurrence of Prismatic Slip During PVT Growth of SiC Crystals

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Wedl, G. High-Temperature Adhesive Bonding of -SiC Substrates

Wellmann, P. Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components

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Yadav, M. High-Temperature Adhesive Bonding of -SiC Substrates

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Zellner, C. High-Temperature Adhesive Bonding of -SiC Substrates

Zöcklein, J. Improvement of the Yield during Crystal Growth of SiC by PVT by Proper Selection and Design of Hot Zone Isolation Components