Technological Improvements in Devices Fabrication

Edited by
Prof. Victor Veliadis
Dr. Arash Salemi

Technological Improvements in Devices Fabrication

Special topic volume with invited peer-reviewed papers only

Edited by

Prof. Victor Veliadis and Dr. Arash Salemi

Sócientific.Net

Copyright © 2025 Trans Tech Publications Ltd, Switzerland

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Volume 1159 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

Full text available online at https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

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Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp -1-0

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2025-09-09

Online:
2025-09-09

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1159.-1.pdf

The special edition highlights recent technological improvements in fabricating silicon carbidebased power electronics devices. The articles cover advances in Schottky contacts, the development of high-performance Schottky barrier diodes, and methods to reduce contact resistance through processes such as sulfurization, argon plasma treatment, and optimised contact formation.

Further emphasis is placed on innovations in trench etching, gate oxide engineering, and techniques to extend gate oxide lifetime, alongside modern approaches in wafer dicing, including plasma dicing, laser ablation, and laser annealing.

This special edition provides a comprehensive overview of the latest process enhancements that underpin the continued advancement of SiC-based device technologies by addressing methods of compound semiconductor processing and technologies of electronics device structure forming with a focus on end-device reliability.

Table of Contents

Preface

Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Fabrizio Roccaforte, Marilena Vivona, Salvatore Ethan Panasci, Salvatore di Franco, Giuseppe Greco, Patrick Fiorenza, Attila Sulyok, Antal Koos, Béla Pécz, Filippo Giannazzo

C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Qin Gui Roth Voo, Abdul Hannan Yeo, Lakshmi Kanta Bera, Umesh Chand, Yu Chieh Chien, Xuan Sang Nguyen, Wen Dong Song, Shiv Kumar, Hung Ming Chua, Navab Singh, Surasit Chung, Shane Kam, Marcin Zielinski, Loic Kabelaan, Walter Schwarzenbach, Ionut Radu, Loann Boudin

Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Abdul Hannan Yeo, Qin Gui Roth Voo, Lakshmi Kanta Bera, Umesh Chand, Navab Singh, Xuan Sang Nguyen, Shiv Kumar, Surasit Chung, Jia Wei Xie, Yee Chia Yeo, Xiao Gong

Trench Etch Processing for SiC Superjunction Schottky Diodes

Qin Ze Cao, Arne Benjamin Renz, Peter Michael Gammon, Neophytos Lophitis, Kyrylo Melnyk, Marina Antoniou

Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing

Clément Berger, Daniel Alquier, Jean François Michaud

Analysis of Ohmic Contacts Simultaneously Formed on both -Type and -Type -SiC

Atsushi Shimbori, Rahul Valecha, Alex Q. Huang

Gate Oxide Performance and Reliability on SmartSiC Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Tom Becker, Mathias Rommel, Holger Schlichting, Leander Baier, Eric Guiot, Frédéric Allibert

Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Shuzo Masui, Shotaro Kadoya, Satoru Takahashi, Masaki Michihata, Noboru Ohtani, Kozo Abe, Shunya Hirano, Shunsuke Arimura

Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

Carsten Hellinger, Michael Thum, Mathias Rommel

Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Takanori Amamiya, Masayuki Yamamoto, Hitoshi Umezawa, Koji Nakayama, Takeharu Kuroiwa, Shinichiro Kuroki, Yasunori Tanaka

Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

Johannes Ziegler, Dick Scholten, Holger Bartolf, Andrii Voznyi, Patrick Rabinzohn, Jörg Schulze

Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

Shigeaki Takagi, Hideo Yoshihashi, Katsuhisa Tanaka, Tomomi Imamura, Hiroshi Kono

SiC Plasma Dicing for Future High Yield Die Singulation

Ben Jones, Alex Croot, Jacob Mitchell, Samira Kazemi, Chris Bolton, Huma Ashraf, Mike Jennings, Owen James Guy

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 1-7

doi: 10.4028/p-j9hDA2

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-07

Revised:
2025-08-01

Accepted:
2025-08-04

Online:
2025-09-09

Effects of Sulfurization on the Properties of -SiC Schottky Contacts

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

Fabrizio Roccaforte , Marilena Vivona , Salvatore Ethan Panasci , Salvatore Di Franco , Giuseppe Greco , Patrick Fiorenza , Attila Sulyok , Antal Koos , Béla Pécz and Filippo Giannazzo

CNR-IMM, Strada VIII n.5, Zona Industriale, I-95121, Catania, Italy

HUN-REN Centre for Energy Research, Institute for Technical Physics and Materials Science, Konkoly-Thege M. út 29-33, 1121 Budapest, Hungary

salvatore.difranco@imm.cnr.it, giuseppe.greco@imm.cnr.it, patrick.fiorenza@imm.cnr.it, sulyok.attila@ek.hun-ren.hu, koos.antal@ek.hun-ren.hu, 'pecz.bela@ek.hun-ren.hu, jfilippo.giannazzo@imm.cnr.it

*corresponding author

Keywords: Sulfurization, Schottky barrier, Kelvin Probe Force Microscopy, Fermi Level Pinning

Abstract

This paper reports on the effect of a sulfurization thermal process of the silicon carbide surface on the properties of Ni/4H-SiC Schottky barrier. In particular, the incorporation of sulfur ( S ) in the near-surface region was observed at the process performed at , without any significant effect on the surface morphology. On the other hand, Schottky contacts fabricated on the sulfurized surface showed a 0.3 eV reduction of the average barrier height with a narrower distribution, with respect to the untreated sample. These results were explained by an increase of the electron affinity after sulfurization, and a Fermi level pinning effect.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

Controlling the electrical properties of metal/SiC interfaces is a challenging issue, because of the numerous implications in Schottky barrier diodes technology [1]. In particular, tailored barrier characteristics and reduced power losses are among the main goals in this technology [2]. In this context, over the years, metals with different work function ( ) have been employed for obtaining the desired metal/4H-SiC Schottky Barrier Height (SBH), due to the linear dependence of the SBH on the metal work function often observed in SiC [3]. However, the occurrence of Fermi-levelpinning (FLP) may reduce the dependence of the SBH on the metal work function . Hence, several surface/interface processes have been also investigated to exploit this effect. For example, plasma treatments in combination with thermal annealings have been used to control the reduction of the SBH in and to achieve more uniform current-voltage characteristics with acceptable leakage current values [5-7]. In particular, using a CF4 plasma treatment, a significant barrier lowering was observed, which could be completely recovered after appropriate silicidation annealings leading to the consumption of a surface layer [8]. More recently, the insertion of an ultrathin a- interlayer below the metal was also used to modify the SBH in 4H-SiC Schottky diodes, using the strong FLP effect occurring in the presence of the defect-rich amorphous layer [9]. Finally, also ionimplantation of foreign species in layer was used to modify the SBH properties, either by near-surface dopant deactivation [10] or by the creation of electrically active interface defects [11].

In this context, since almost two decades sulfur ( S ) is known to act as a deep donor of [12], and the electrical activation of S double donors introduced in by ion implantation has been recently object of interest for transistors applications [13]. Besides ion-implantation, also thermal treatments in S -atmosphere of ultra-thin deposited Mo films on surface have been recently considered for developing novel device concepts based on atomically thin molybdenum disulfide heterojunctions with . However, the effects of these sulfurization treatments on the electrical properties of surface are still unclear and need to be investigated.

In this paper, the effects of a sulfurization treatment of the surface were evaluated by detailed chemical, morphological and electrical analyses of Schottky contacts. In particular, a chemical analysis demonstrated an incorporation of sulfur ( S ) in the surface treated at . The Schottky contacts fabricated on the "sulfurized" surface exhibited a 0.3 eV reduction of the Schottky barrier with respect to the "untreated" sample (not subjected to sulfurization). This effect was explained by a decrease of the electron affinity and Fermi level pinning effect induced by the sulfurization.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

In this experimental investigation, we used silicon carbide ( ) samples, consisting of an n-type epitaxial layer ( ) grown onto a doped substrate.

The surface of the samples was exposed to a "sulfurization" treatment in a two-heating zones quartz tube. This procedure is described in more detail in the next section.

The chemical impact of the sulfurization was evaluated by X-ray photoelectron spectroscopy (XPS) analyses performed by using an Escalab Xi+ equipment by Thermo Fisher with a monochromatic Al K X-ray source. Spectra were recorded with 0.1 eV steps for the main components of the system like Si and sulfur . Since the expected small peak of low sulfur content, the sensitivity was raised by applying: (i) a high pass energy ( 60 eV ) resulting in a resolution of 1.1 eV ; (ii) a long measurement time ( point); (iii) a large X-ray spot to provide high count rate.

The morphology and the surface potential of surfaces were monitored by Atomic Force Microscopy (AFM) and Kelvin Probe Force Microscopy (KPFM) carried out in Peak Force Tapping Mode with a Dimension Icon system by Bruker. For KPFM measurements, silicon tips with a nominal radius of 5 nm and a spring constant of supported on a silicon nitride cantilever were employed.

The effect of the sulfurization on the electrical properties of Schottky contacts was studied by means of test Schottky diodes. In particular, first a back-side Ohmic contact was fabricated by sputtering 100 nm -thick Ni film, followed by a rapid thermal annealing at in . Then, the sample surface was subjected to the sulfurization process identified as the most suitable for S incorporation ( ). Finally, the front-side circular Schottky contacts (active area of ) were formed by 100 nm -thick Ni layer, followed by a thermal annealing at .

The current voltage (I-V) electrical characterization of these diodes was carried out on a set of equivalent devices, using a probe station equipped with a parameter analyzer.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

A schematic illustration of the experimental set-up used for the sulfurization processes is depicted in Fig. 1a. It consists in a two-heating zones quartz tube, containing a crucible filled with Sulphur (S) powder. The crucible is placed in the lower-temperature zone kept at , whereas the sample is placed in the higher-temperature zone (which could be varied in the range ). Argon (Ar) was used as carrier gas at flow rate of 50 sccm . The sulfurization time was 90 minutes, thus producing the evaporation of about 1 g of S from the crucible.

[picture]

Fig. 1. (a) Schematic of the experimental set-up of the quartz tube furnace used for the sulfurization process of SiC surface; (b) S2p peak of XPS spectra obtained on samples subjected to sulfurization at and . The spectrum of an untreated sample (reference) is shown for comparison.

Fig. 1. (a) Schematic of the experimental set-up of the quartz tube furnace used for the sulfurization process of SiC surface; (b) S2p peak of XPS spectra obtained on samples subjected to sulfurization at and . The spectrum of an untreated sample (reference) is shown for comparison.

The samples were subjected to sulfurization at three different temperatures, i.e. 800,900 and . After these processes, the sulfurized samples were studied by XPS analyses to verify the presence of sulfur ( S ) in the near-surface region. An untreated sample was analyzed as a reference. The corresponding XPS spectra are reported in Fig.1b. In particular, the acquired XPS spectra showed a visible presence of sulfur only after the process carried out at . Here, the expected S 2p doublet is broadened onto a wide peak visible at 162.5 eV . The background shape originates from the proximity of the plasmon satellites of the Si 2s. Interestingly, the binding energy of this peak is consistent with S atoms bonded to the topmost Si atoms of the SiC lattice, as recently reported in Ref. [15]. Since the S 2p peak is a low intensity peak with noisy condition on top of a bended background, only an estimate can be given for its quantity. Considering the low diffusion coefficients of foreign species in SiC , it is reasonable to assume the sulfur being distributed within a depth of 1 nm . Hence, by assuming a homogeneous distribution of sulfur in such a thin surface region, a concentration in the range of 0.6-1.6 at. % could be estimated. It must be noted that the spectra detected on the and annealed samples showed a sulfur peak at the noise level, i.e. 10 times lower sulfur concentrations (if any) than that of annealed sample. Hence, we speculate that, while at low temperatures sulfur is incorporated in the near-surface region of SiC , with increasing temperature ( ) the competitive effect of its evaporation becomes dominant, and no sulfur is observed by our chemical analysis.
Figs. 2a and 2b report the AFM surface morphology of before and after the sulfurization process carried out at , respectively. In particular, the typical steps associated to the -off-cut angle of epilayers are visible. More interestingly, the surface roughness of the epilayer is almost unaffected by the sulfurization, since very similar root mean square (RMS) values are found, i.e., 0.15 nm before and 0.17 nm after the process.

[picture]

Fig. 2. Surface morphology of samples before (a) and after (b) the sulfurization process at .

Fig. 2. Surface morphology of samples before (a) and after (b) the sulfurization process at .

To monitor the effects of the sulfurization on the electrical properties of the surface, first Schottky didoes were fabricated and characterized by I-V measurements.
Fig. 3a shows a collection of different forward I-V curves of Ni/4H-SiC Schottky diodes fabricated on the reference (untreated) and the sulfurized ( ) sample.

[picture]

Fig. 3. (a) Forward I-V curves of Ni/4H-SiC Schottky diodes fabricated on the untreated sample (reference) and on the sample subjected to sulfurization at (sulfurized). (b) Statistical distributions of the Schottky barrier height values determined in the reference and in the sulfurized diodes. (c) Plot of the Schottky barrier as a function of the ideality factor n determined in the Schottky diodes fabricated on reference and on a sulfurized ( ) sample. The continuous lines are a linear fit of the experimental data, from which the ideal values of the Schottky barrier height can be extrapolated (at ).

Fig. 3. (a) Forward I-V curves of Ni/4H-SiC Schottky diodes fabricated on the untreated sample (reference) and on the sample subjected to sulfurization at (sulfurized). (b) Statistical distributions of the Schottky barrier height values determined in the reference and in the sulfurized diodes. (c) Plot of the Schottky barrier as a function of the ideality factor n determined in the Schottky diodes fabricated on reference and on a sulfurized ( ) sample. The continuous lines are a linear fit of the experimental data, from which the ideal values of the Schottky barrier height can be extrapolated (at ).

As can be seen, the I-V curves of the sulfurized samples ( ) are shifted towards lower forward voltage values, thus indicating a lowering of the SBH. In addition, the measured I-V curves appear more reproducible with respect to those of the reference diodes, thus suggesting that a more uniform distribution of the barrier is occurring. This is well visible in Fig. 3b, showing the statistical distributions of the SBH values in the two cases. As can be seen, while the distribution of the SBH values of the reference diodes is peaked at 1.58 eV , the average of the SBH distribution in the sulfurized sample is 1.32 eV , i.e. with a lowering of about 0.26 eV with respect to the reference. Moreover, the SBH distribution of the sulfurized diodes appears narrower with respect to the reference, as expected by the forward I-V curves reported in Fig. 3a.

Finally, Fig. 3c reports the experimental values of the SBH as a function of the ideality factor n , for the reference and the sulfurized sample. Interestingly, a linear correlation between these two parameters ( and n ) is observed, which is a typical macroscopic signature of the barrier inhomogeneity at a microscopic level [5,16]. From this plot, it was possible to extrapolate the "ideal values" (at ) of homogeneous barrier, i.e. 1.76 eV for the reference sample and 1.46 eV for the sulfurized one. The different slope of the vs n plots reflects the different degree of homogeneity of the barrier [17], and it is fully coherent with the narrower SBH distribution of the barriers observed in the sulfurized sample (Fig. 3b).
Finally, the get further insights on the effect of S incorporation on the electrical properties of surface, a surface potential mapping of the samples was carried out using KPFM. As a reference value of the surface potential, a pattern of gold (Au) stripes was created on the sample surface by optical lithography and lift off.
Figs. 4a and 4b report the two-dimensional surface potential maps collected on regions including the Au stripe and the bare surface, for the reference and the sulfurized sample, respectively. The surface potential line-profiles across the two regions are also reported in the inserts of the two figures, showing a reduced surface potential difference with respect to Au in the sulfurized surface with respect to the untreated one . To obtain statistically relevant information on the entire scanned areas, the histograms of surface potential values extracted from these KPFM maps are also reported in Fig. 4c and 4d. The two distributions include a peak associated to Au surface and a second peak associated to bare SiC surface (reference and sulfurized). A Gaussian fit of these distributions enables to better quantify the shift of the surface potential with respect to the reference Au stripe. From this analysis, a 0.3 V increase of the surface potential of sulfurized with respect to the untreated surface could be estimated, which corresponds to an increase of the electron affinity induced by the sulfurization process.

[picture]

Fig. 4. (a) Surface potential maps of the Au stripe (cyan region) compared to (a) the untreated SiC (blue region) and (b) to the sulfurized SiC (red region). Surface potential line profiles across the Au coated and bare SiC regions are reported as inserts of the two maps (c) Histograms of the surface potential values extracted from the KPFM maps on (c) untreated SiC and (d) after sulfurization. Here, a reduction of the surface potential of is observed on the sulfurized SiC.

Fig. 4. (a) Surface potential maps of the Au stripe (cyan region) compared to (a) the untreated SiC (blue region) and (b) to the sulfurized SiC (red region). Surface potential line profiles across the Au coated and bare SiC regions are reported as inserts of the two maps (c) Histograms of the surface potential values extracted from the KPFM maps on (c) untreated SiC and (d) after sulfurization. Here, a reduction of the surface potential of is observed on the sulfurized SiC.

The experimentally observed scenario is graphically depicted in Fig. 5, which reports the schematic band diagram of the metal/4H-SiC system before and after the sulfurization process. As can be seen, a reduction of the electron affinity and Fermi level pinning at the surface induce a lowering of the Schottky barrier height in the sulfurized sample.

[picture]

Fig. 5. Schematic band diagram of the band diagram before and after sulfurization process at , showing the barrier lowering of 0.3 eV .

Fig. 5. Schematic band diagram of the band diagram before and after sulfurization process at , showing the barrier lowering of 0.3 eV .

It is worth mentioning that capacitance-voltage analyses of the diodes, not reported here, did not reveal any variation of the doping level upon sulfurization process [18].

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

In summary, the effects of a sulfurization of the surface on Schottky barrier was studied by the cross-correlation of several chemical, morphological and electrical analyses.
In particular, the incorporation of sulfur ( S ) in the surface occurs after sulfurization at , without causing any significant degradation on the surface morphology. On the other hand, Schottky contacts fabricated on the sulfurized surface exhibit a 0.3 eV reduction of the average barrier height with a narrower distribution, with respect to the untreated sample. These results, explained by an increase of the electron affinity after sulfurization, and a Fermi level pinning effect, can be useful for power device technology and for the integration of S -based layered materials (e.g. ) on SiC surfaces for novel devices concepts.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

This work was supported by the European Union (NextGeneration EU), through the MUR-PNRR projects SAMOTHRACE (PNRR-M4C2, ECS00000022) and iENTRANCE@ENL (IR00000027). Funding for travels from CNR/HAS (2023-25) bilateral project GHOST-III is also acknowledged. B. P. acknowledges the support of TKP2021-NKTA-05.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.1.pdf

F. Roccaforte, P. Fiorenza, G. Greco, R. Lo Nigro, F. Giannazzo, F. Iucolano, M. Saggio, Emerging trends in wide band gap semiconductors ( SiC and GaN ) technology for power devices, Microelectronic Engineering 187-188 (2018) 66-77.

M. Vivona, F. Giananzzo, F. Roccaforte, Materials and Processes for Schottky Contacts on Silicon Carbide, Materials 15 (2022) 298.

F. Roccaforte, F. Giannazzo, V. Raineri, - Nanoscale transport properties at silicon carbide interfaces, J. Phys. D: Appl. Phys. 43 (2010) 223001.

S-Y. Han, J-L. Lee, Interpretation of Fermi level pinning on using synchrotron photoemission spectroscopy, Appl. Phys. Lett. 84 (2004) 538-540.

B.J. Skromme, E. Luckowski, K. Moore, S. Clemens, D. Resnick, T. Gehoski, D. Ganser, Fermi Level Pinning and Schottky Barrier Characteristics on Reactively Ion Etched 4H-SiC, Mater. Sci. Forum 338-342 (2000) 1029-1032.

B-Y. Tsui, J-C. Cheng, C-T. Yen, C-Y. Lee, Strong Fermi-level pinning induced by argon inductively coupled plasma treatment and post-metal deposition annealing on 4H-SiC, SolidState Electronics 133 (2017) 83-87.

J-C. Cheng, B-Yue Tsui, Effects of Rapid Thermal Annealing on Ar Inductively Coupled PlasmaTreated n-Type 4H-SiC Schottky and Ohmic Contacts, IEEE Transactions on Electron Devices 65(9) (2018) 3739-3745.

F. Roccaforte, F. La Via, V. Raineri, P. Musumeci, L. Calcagno, G.G. Condorelli, Highly reproducible ideal SiC Schottky rectifiers: effects of surface preparation and thermal annealing on the Ni/6H-SiC barrier height, Appl. Phys. A 77 (2003) 827-833.

F. Triendl, G. Pfusterschmied, C. Berger, S. Schwarz, W. Artner, U. Schmid, Ti/4H-SiC schottky barrier modulation by ultrathin a-SiC:H interface layer, Thin Solid Films 721 (2021) 138539.

F. Roccaforte, S. Libertino, F. Giannazzo, C. Bongiorno, F. La Via, V. Raineri, Ion irradiation of inhomogeneous Schottky barriers on silicon carbide, J. Appl. Phys. 97 (2005) 123502.

J. Yang, H. Li, S. Dong, X. Li, Pinning Effect on Fermi Level in 4H-SiC Schottky Diode Caused by 40-MeV Si Ions, IEEE Transactions on Nuclear Science 66(9) (2019) 2042-2047.

S.A. Reshanov, G. Pensl, H. Nagasawa, A. Schoener, Identification of sulfur double donors in 4H, 6H-, and 3C-silicon carbide, J. Appl. Phys. 99 (2006) 123717.

T. Matsuoka, M. Kaneko, T. Kimoto, Physical properties of sulfur double donors in 4H-SiC introduced by ion implantation, Jpn. J. Appl. Phys. 62 (2023) 010908.

F. Giannazzo, S.E. Panasci, E. Schilirò, F. Roccaforte, A. Koos, M. Nemeth, B. Pécz, Esaki Diode Behavior in Highly Uniform Silicon Carbide Heterojunctions, Adv. Mater. Interfaces 9 (2022) 2200915.

S. Wolff, N. Tilgner, F. Speck, P. Schädlich, F. Göhler, Th. Seyller, Quasi-Freestanding Graphene via Sulfur Intercalation: Evidence for a Transition State, Adv. Mater. Interfaces 11 (2024) 2300725.

F. Roccaforte, F. La Via, V. Raineri, R. Pierobon, E. Zanoni, Richardson's constant in inhomogeneous silicon carbide Schottky contacts, J. Appl. Phys. 93 (2003) 9137-9144.

J.P. Sullivan, R.T. Tung, M.R. Pinto, W.R. Graham, Electron transport of inhomogeneous Schottky barriers: A numerical study, J. Appl. Phys. 70 (12) (1991) 7403-7424.

F. Roccaforte, M. Vivona, S.E. Panasci, G. Greco, P. Fiorenza, A. Sulyok, A. Koos, B. Pecz, F. Giannazzo, Schottky contacts on sulfurized silicon carbide ( ) surface, Appl. Phys. Lett. 124 (2024) 102102.

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The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 9-13

doi: 10.4028/p-XywF2P

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-15

Accepted:
2025-08-15

Online:
2025-09-09

C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

The original version of this paper is available on https://www.scientific.net/MSF.1159.9.pdf

Voo Qin Gui Roth , Abdul Hannan Yeo , Lakshmi Kanta Bera , Umesh Chand , Yu-Chieh Chien , Nguyen Xuan Sang , Wen Dong Song , Shiv Kumar , Hung Ming Chua , Navab Singh , Surasit Chung , Shane Kam , Marcin Zielinski , Loic Kabelaan , Walter Schwarzenbach , lonut Radu , Loann Boudin

Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore 138634

SOITEC, Parc Technologique des Fontaines, 38190 Bernin, France

roth_voo@a-star.edu.sg, hannan_yeo@a-star.edu.sg, chand_umesh@a-star.edu.sg, chien_yu_chieh@a-star.edu.sg,

fnguyen_xuan_sang@a-star.edu.sg,

shiv_kumar@a-star.edu.sg, chuahm@a-star.edu.sg, navab@a-star.edu.sg,

surasit_chung@ime.a-star.edu.sg, shane.kam@soitec.com, marcin.zielinski@soitec.com, 'loic.kabelaan@soitec.com, walter.schwarzenbach@soitec.com, pionut.radu@soitec.com, loann.boudin@soitec.com

Keywords: Carbon face epitaxy, C-face 4 H -SiC, Schottky Barrier Diode

Abstract

This study focuses on analyzing the electrical performance and characteristics of Schottky Barrier Diodes (SBDs) on the carbon face ( C -face) epitaxial layer. The C -face epitaxial layer is grown on monocrystalline and has a thickness of . It displayed minimal surface roughness, with an of . The C-face termination epitaxy was examined using grazing-angle X-ray photoelectron spectroscopy (XPS) analysis. SBDs were fabricated using a Ti/Al metal stack. Schottky Barrier Height ( ) of about 1.2 eV was extracted from measurements. Temperature-dependent - measurements demonstrated a forward voltage decrease as the temperature rises when the forward current is . However, for forward currents , the forward voltage increases with temperature. This rise in forward voltage could lead to a reduction in reverse recovery time and thus enhancing the switching speed. Additionally, the diode exhibits remarkable immunity to reverse leakage current up to , surpassing the performance of the 6.5 kV JBS diode on Si-face [1].

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.9.pdf

Wide-band gap (WBG) semiconductors are widely regarded as the building blocks for the future of power electronics devices. Among all WBG materials, stands out as the most promising for power devices. Various types of devices fabricated on the Si -face of have achieved a high level of technological maturity. However, the carbon-face ( ) crystallographic orientation offers significant advantages over the conventional Si-face, particularly in terms of enhanced thermal stability and carrier mobility [2]. The C -face of SiC exhibits fewer surface defects than Si -face.

Despite these advantages, device fabrication on C-face epitaxy has not been thoroughly explored to fully exploit the high electron mobility, superior switching characteristics, power efficiency, and expanded operational frequencies. Several factors play a part in the lack of motivation for development of C -face SiC devices such as the difficulty to achieve a reliable gate oxide layer with standard gate oxidation processes on C -face SiC due to the high oxidation rate. A poor gate oxide interface would compromise the device quality and negatively impact the performance of SiC devices. Among the different types of devices, Schottky diodes have shown remarkable performance as power diodes for fast switching applications, with minimal power loss. The overall performance of a Schottky diode is influenced by various conditions, including the semiconductor surface
characteristics, the metal work function used, and the metal-semiconductor interface [3,4]. The objective of this study is to investigate the electrical characteristics of a C-face epitaxilly grown 4HSiC using a Ti-based Schottky diode.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.9.pdf

A 150 mm epi-ready n-type 4H-SiC substrate with a C-face orientation obtained from SOITEC, was used as the initial substrate for epitaxial growth. Subsequently, a SiC epilayer was grown with C-face termination as visualized in Fig. 1(a).

[picture]

Fig. 1. (a) C-face 3D Crystal Structure, (b) Atomic Force Microscopy (AFM) image showing the surface morphology of the C-face epitaxial layer, (c) XPS analysis (C1s peak to peak ratio).

Fig. 1. (a) C-face 3D Crystal Structure, (b) Atomic Force Microscopy (AFM) image showing the surface morphology of the C-face epitaxial layer, (c) XPS analysis (C1s peak to peak ratio).

This growth utilized a standard buffer layer of approximately and was performed in a commercial hot-wall chemical vapor deposition (CVD) system. Low surface roughness of the epitaxial layer with an value of approximately 0.3 nm was obtained from atomic force microscopy (AFM) as shown in Fig. 1(b). To confirm the termination of the grown epitaxial layer, X-ray photoelectron spectroscopy (XPS) analysis revealed an increase in the carbon, peak-peak ratio of the two peaks, indicating C -face termination outlined in Fig. 1 (c). This ratio was higher in comparison with another Si-face terminated grown epilayer. SBDs were fabricated as shown in Fig. 2 (a) with a metal contact. A sacrificial oxide layer was deposited on the frontside of the sample to ensure the interface remains clean when processing the backside Ni ohmic contact. A Ni ohmic backside contact was formed through PMDA at . The sacrificial oxide layer on the frontside was then stripped with dilute hydrofluoric acid (DHF) followed by subsequent metallization right after. This maintained the integrity of the MS interface prior to metallization. was then removed with DHF, followed by Ti/Al deposition in a commercial physical vapour deposition (PVD) chamber right after. The thickness and integrity of the metal-SiC (MS) interface was observed with TEM as shown in Fig. 2 (b). An atomically smooth interface layer was observed. A Ni ohmic contact was formed on the backside of the device after post-metal deposition annealing (PMDA) at , prior to Schottky contact deposition [5].

[picture]

Fig. 2. (a) Schematic of the Schottky Barrier Diode fabrication process, highlighting the Ti/Al metal contact and post-metal deposition annealing steps.

Fig. 2. (a) Schematic of the Schottky Barrier Diode fabrication process, highlighting the Ti/Al metal contact and post-metal deposition annealing steps.

[picture]

Fig. 2. (b) Transmission Electron Microscopy of Metal-SiC Interface.

Fig. 2. (b) Transmission Electron Microscopy of Metal-SiC Interface.

The doping concentration ( ) of the C -face epilayer was extracted electrically from the measured of SBDs in Fig. 3 (a-b) [6]. was measured at 1 MHz on radius devices. From the linearity of the vs plot, uniform doping can de deduced across the 150 mm wafer. Table 1 shows the barrier height extracted from several SBDs using techniques with good uniformity and distribution. The barrier heights correlate to the increased knee voltage ( ) observed from plots shown in Fig. 4 (a-b).

[picture]

Fig. 3. (a) of 5 Devices (b) vs .

Fig. 3. (a) of 5 Devices (b) vs .

[picture]

Fig. 4. (a) Linear , (b) , (c) Arrhenius plot.

Fig. 4. (a) Linear , (b) , (c) Arrhenius plot.

Table 1. obtained from 5 devices, Table 2: vs Temperature.

As Deposited/Room Temperature | ΦB [eV] from I-V
Device 1 | 1.15
Device 2 | 1.20
Device 3 | 1.15
Device 4 | 1.22
Device 5 | 1.19

As Deposited/Room Temperature | ΦB [eV] from I-V
Device 1 | 1.15
Device 2 | 1.20
Device 3 | 1.15
Device 4 | 1.22
Device 5 | 1.19

Furthermore, from the SBDs characterizations, we derived the barrier height from Arrhenius plots and demonstrated its strong correlation with data obtained from extraction. Our findings closely matched those of a previous study ( 1.97 eV ) for Ni-based materials, whereas this study, focused on Ti-based materials ( 1.15 eV ) [3]. This variance can stem from the use of different metal stacks and doping concentrations of the C-face epi layer, which would influence the barrier height. The SBDs fabricated on C-face epitaxial layers demonstrated significantly low leakage current, less than 6 pA , even at elevated measurement temperatures up to as shown in Table 2 . Forward current was observed to be lowered with increased temperature in Fig. 4(a). This change in the forward current could be caused by increased phonon scattering at high temperatures. The strong bonding force promotes large lattice vibrations, making excitation of donors difficult. Current enhancement in the subthreshold region as seen in Fig 4(b) could indicate that the thermal emission is encouraging this change. We observed a remarkable immunity to reverse leakage increase with temperature, which is superior to 6.5 kV JBS diodes fabricated on Si-face 4H-SiC [1].

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1159.9.pdf

In this work, we have demonstrated the electrical characteristics of SBDs on C-face epitaxy substrates with excellent mobility and slight increase in barrier height with temperature. Immunity against temperature dependent reverse leakage current was observed and attributed to the high quality C-face epitaxial grown layer as well as the clean metal-semiconductor interface before metallization. Lowered forward current with increasing temperature as a possible result of increased phonon scattering with high temperature was also observed and discussed. This work demonstrates the viability of implementing Schottky diodes on C-face epitaxial layers to exploit its excellent intrinsic material properties in comparison with Si -face devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1159.9.pdf

This work was supported by A*STAR (Agency for Science, Technology and Research Singapore), under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.9.pdf

X. Niu, Effect of Schottky annealing temperature on reverse leakage current of 6500 V 4H-SiC JBS diodes, Journal of Crystal Growth 608 (2023) 127103.

Kodigala Subba Ramaiah et al., "Growth and characterization of SiC epitaxial layers on Si- and C-face 4H SiC substrates by chemical-vapor deposition," Journal of Applied Physics, 98, no. 10 (2005).

A. Itoh, T. Kimoto, and H. Matsunami, "High performance of high-voltage 4H-SiC Schottky barrier diodes," IEEE Electron Device Letters, 16, 6 (1995) 280-282.

M. Furno, Design, Fabrication and Characterization of 4H-SiC n-Type Schottky Barrier Diodes, Materials science forum, 483-485 (2005) 941-944.

A. Hannan, The Effect of Nitrogen Plasma Treatment Process on Ohmic Contact Formation to N-Type 4H-SiC, Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena, 359 (2024) 59-63.

Tsunenobu Kimoto and J. A. Cooper, Fundamentals of silicon carbide technology: growth, characterization, devices and applications. Singapore: John Wiley & Sons (2014).

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The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 15-20

doi: 10.4028/p-omYG0i

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-07

Accepted:
2025-08-08

Online:
2025-09-09

Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

The original version of this paper is available on https://www.scientific.net/MSF.1159.15.pdf

Abdul Hannan Yeo*1,2,a , Voo Qin Gui Roth , Lakshmi Kanta Bera , Umesh Chand , Navab Singh , Nguyen Xuan Sang , Shiv Kumar , Surasit Chung , Xie Jiawei , Yeo Yee Chia , and Gong Xiao

Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore 138634

Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117583

ahannan_yeo@a-star.edu.sg, Roth_Voo@a-star.edu.sg, clakshmi_kanta_bera@a-star.edu.sg, Chand_Umesh@a-star.edu.sg, navab@a-star.edu.sg, Nguyen_Xuan_Sang@a-star.edu.sg, shiv_kumar@a-star.edu.sg, Surasit_chung@a-star.edu.sg, jijaweix@u.nus.edu, Yeo_Yee_Chia@a-star.edu.sg, Gong_Xiao@a-star.edu.sg

Keywords: Ohmic contacts, n-type SiC, ITO interlayer, barrier height, metal-SiC interface

Abstract

This study investigates the role of ultra-thin conductive Indium-Tin-Oxide (ITO) as an interlayer at the Metal-SiC (MS) junction to lower the overall specific contact resistance (SCR) for source drain metallization applications on n-type substrates. In this work, we demonstrate an improvement in SCR by about 1 order of magnitude from to through the integration of an ultra-thin ITO interlayer. Barrier height ( ) lowering by was observed at the MS interface as deposited which could have assisted in the reduction of the SCR. Titanium-based Ohmic contacts were subsequently formed at . Various thicknesses of ITO were examined to assess their influence on the formation of ohmic contacts to n-type SiC. An SCR ( ) of was achieved through integration of an ultra-thin conductive ITO interlayer at the MS interface.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.15.pdf

The specific on-resistance (Rov) in SiC devices consists of various components: contact, channel, JFET, drift, and substrate resistances. In 4H-SiC power JBSFETs, the contact resistance accounts for roughly of the total resistance, given a contact width of . Therefore, minimizing the SCR becomes crucial for reducing overall Ron as devices scale. The Specific Contact Resistance (SCR) in 7 nm CMOS node is much lower in comparison to SiC metal contacts due to the ease of silicide formation [2]. Hence, more studies are still needed to further improve the contact resistance to N -type SiC . The aim of this work was to minimize carbon at the Metal- SiC (MS) interface to achieve a lower SCR.

Indium Tin Oxide (ITO) is a widely used transparent conductive oxide known for its electrical conductivity. Through optimized deposition techniques, a high carrier concentration in the ITO can be obtained with low resistivity making it an ideal candidate for electrode applications. Furthermore, ITO is a CMOS compatible material which has been widely used in the industry [3].

In this study, a conductive Indium Tin Oxide (ITO) was proposed and employed to facilitate the reduction of carbon during post metal deposition annealing (PMDA). Additionally, conductive ITO enables efficient charge transport across interfaces, acting as an effective passivation layer that can reduce surface states and enhance device performance [3]. This paper further investigates the role of ITO as a conductive interlayer at the MS interface for SCR reduction and its effects as a contact material to n-type SiC.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.15.pdf

In this study, off-cut n-type substrates ( 0001 ), with a doping concentration of , were cleaned by standard Sulfuric-Peroxide Mix (SPM) and Buffered Oxide Etchant (BOE) chemistries as per previous work prior to fabrication [4]. This step is crucial to ensure a clean surface prior to fabrication of the test structures to prevent defects from remaining at the MS interface. Schottky barrier diodes (SBDs) were fabricated, as shown in Fig. 1 (a), with different ITO interlayer thicknesses followed by formation of Ti/Al Schottky contacts with similar thicknesses for comparison. Ni ohmic contacts were formed on the backside of the substrate after post-metal deposition annealing (PMDA). It is noteworthy that the backside contacts were formed prior to Schottky contacts on the front-side. Subsequently, circular transmission line method (CTLM) structures (top-to-top) for contact resistance measurement and extraction were also fabricated using a Ti-based metal stack ( ) as shown in Fig. 1 (b) with several splits with the incorporation of various ITO interlayer thicknesses.

[picture]

Fig. 1. Cross section of (a) SBD with Ti/Al Schottky contact (b) CTLM structures for SCR extraction.

Fig. 1. Cross section of (a) SBD with Ti/Al Schottky contact (b) CTLM structures for SCR extraction.

[picture]

Fig. 2. I-V of SBDs with different ITO interlayer thickness as deposited in the (a) linear scale and (b) log-scale.

Fig. 2. I-V of SBDs with different ITO interlayer thickness as deposited in the (a) linear scale and (b) log-scale.

In Fig. 2 (a-b), I-V measurements on the SBD samples indicate a reduction in barrier height ( ) by with the incorporation of an ITO interlayer as deposited. It was observed that the samples with ITO interlayer displayed a lower as compared to the control sample, without any ITO. This supported the finding of the extracted to be lower with the incorporation of ITO interlayer. However, the Ion was not changed with the incorporation of the interlayer which was expected. Following the subsequent PMDA at , it was interesting to observe that only the ultra-thin ITO sample exhibited ohmic behaviour, as depicted in Fig. 3 (a) below. In thicker samples, a rectifying behaviour instead was observed. This rectifying behaviour was further pronounced with thicker ITO interlayer thickness as shown in Fig. 3 (a) below. This implies that a much thicker ITO interlayer could have hindered the intermetallic diffusion of the Ti-based metal stack into the SiC lattice which may have resulted in the undesired rectifying behaviour. Hence, careful optimization was needed to ensure a suitable thickness for desirable low SCR ohmic contacts.

[picture]

Fig. 3. (a) I-V of SBDs with different ITO thicknesses after PMDA at (b) UPS Spectra of samples with and without ITO after PMDA at .

Fig. 3. (a) I-V of SBDs with different ITO thicknesses after PMDA at (b) UPS Spectra of samples with and without ITO after PMDA at .

The deposited thickness of ITO had a notable impact on the ohmic behaviour of the sample. This could be due to the conductive nature of the ITO interlayer which was deposited prior to metallization. Another reason could be that the ITO interlayer was responsible in passivating the interface and surface states which could have lowered at the MS interface as deposited [3]. This would have a significant correlation to the overall extracted SCR [5]. Results from ultraviolet photoelectron spectroscopy (UPS) analysis indicated a slight decrease in the work function of the silicide, as shown in Fig. 3 (b) above. This further supports the role of the ITO interlayer in lowering the as deposited since the work function of the metal is closely related to the [4].

[picture]

Fig. 4. I-V Measurements of CTLM structures with gap spacings (a) without ITO interlayer and (b) with ITO interlayer.

Fig. 4. I-V Measurements of CTLM structures with gap spacings (a) without ITO interlayer and (b) with ITO interlayer.

[picture]

Fig. 5. Ave R vs Gap out of 3 sets of CTLM structures (a) without ITO interlayer and (b) with ITO interlayer.

Fig. 5. Ave R vs Gap out of 3 sets of CTLM structures (a) without ITO interlayer and (b) with ITO interlayer.

Electrical measurements (I-V) on the CTLM structures (top-to-top) with varying gap spacings of were measured as shown in Fig. 4 (a-b). There was an observable decrease in the steepness of the I-V curve which correlates to a reduced contact resistance with the incorporation of the ITO interlayer. The results extracted out of 3 CTLM sets revealed a of with the ITO interlayer, leading to a significant reduction by almost one order of magnitude as compared to samples without ITO [Fig. ]. The conductive nature of the deposited ITO interlayer could have also provided additional carriers which would have helped improve carrier injection across the MS interface. Additional carriers to present at the MS interface could enhance tunnelling across the interface. Another contributing factor could be the passivating nature of ITO. The passivating nature of the film could have reduced surface states and minimized fermi-level pinning. This would then lower charge trapping and could improve carrier injection and reduce contact resistance [3]. However, more studies on the role of ITO can be further investigated in future work. Combining the beneficial physical and electrical properties of the conductive ITO interlayer incorporated had assisted in the formation of better low SCR contacts to SiC.

[picture]

Fig. 6. (a-h) TEM-EDX with colour mapping of MS interface after PMDA.

Fig. 6. (a-h) TEM-EDX with colour mapping of MS interface after PMDA.

Intermetallic diffusion and silicide formation at the MS interface after PMDA was investigated with Transmission Electron Microscopy (TEM-EDX) colour mapping as illustrated in Fig. . The silicide layer was measured to be after PMDA due to the annealing conditions used. We observed the clear formation of phase in the sample which predominantly forms the ohmic contact to the n-type SiC. An absence and clear out diffusion of carbon atoms from the silicide layer was also observed. This out diffusion could have been further promoted by positively charged indium atoms from the ITO interlayer. Previous studies have found that Indium may form complexes with carbon which could have increased the rate of carbon out diffusion [10]. These carbon vacancies which are formed after PMDA can serve as electron donors, potentially contributing to the improvement in ohmic contact formation, thereby achieving a lower SCR value. This reported value indicates a relatively low SCR as benchmarked in Fig. 7 [6-9].

[picture]

Fig. 7. Benchmarking of this work with previous studies on highly doped n-type regions.

Fig. 7. Benchmarking of this work with previous studies on highly doped n-type regions.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1159.15.pdf

In this work, an ITO interlayer for ohmic contact enhancement was studied to n-type SiC. We have demonstrated that the incorporation of ultra-thin conductive ITO at the MS interface as an interlayer material, had reduced the SCR by almost 1 order of magnitude to of on n-type SiC. Careful selection and optimization of the interlayer was critical to achieve favourable ohmic contacts. This was achieved through the reduction of as deposited. In addition, carrier injection was promoted through the incorporation of a conductive interlayer at the MS junction. Furthermore, a low SCR was also achieved through the controlled promotion of carbon out diffusion by the ITO interlayer.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1159.15.pdf

This work was supported by A*STAR (Agency for Science, Technology and Research Singapore), under Grant No. A20H9A0242.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.15.pdf

A. Agarwal and B. J. Baliga, "Optimization of linear cell 4H-SiC power JBSFETs: Impact of N+ source contact resistance," Power Electronic Devices and Components, vol. 2, p. 100008, (2022)

H. Yu et al., "Titanium (germano-)silicides featuring contact resistivity and improved compatibility to advanced CMOS technology," 2018 18th International Workshop on Junction Technology (IWJT), Shanghai, China, pp. 1-5, (2018)

A. Benhaya, F. Djeffal, K. Kacha, H. Ferhati, and A. Bendjerad, "Role of ITO ultra-thin layer in improving electrical performance and thermal reliability of structure: An experimental investigation," Superlattices and Microstructures, vol. 120, pp. 419-426, (2018)

A. Hannan et al., "The Effect of Nitrogen Plasma Treatment Process on Ohmic Contact Formation to N-Type 4H-SiC," Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena, vol. 359, pp. 59-63, (2024)

F. Roccaforte, F. La Via, and V. Raineri, "Ohmic Contacts to SiC," International Journal of High-Speed Electronics and Systems, vol. 15, no. 04, pp. 781-820, (2005)

R. Kakanakov, L. Kassamakova-Kolaklieva, N. Hristeva, G. Lepoeva and K. Zekentes, "Thermally stable low resistivity ohmic contacts for high power and high temperature SiC device applications," 2002 23rd International Conference on Microelectronics, pp. 205-208 vol.1, (2002)

W. Lu, W. E. Collins, and W. C. Mitchel, "Material Selection and Interfacial Reaction in OhmicContact Formation on SiC," Springer series in materials science, pp. 303-343, (2024)

S. Tanimoto and Hiromichi Oohashi, "High-Temperature Reliable -Based Contacts on SiC Connected to Si-Doped Al Interconnect via Ta/TaN Barrier," Materials science forum, vol. 615617, pp. 561-564, (2009)

B.-Y. Tsui and J.-C. Cheng, "Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC with Ar Plasma Treatment," IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1464-1467, (2019)

J. Meier, N. Achtziger, T. Licht, M. Uhrmacher, and W. Witthuhn, "Annealing behaviour of In impurities in SiC after ion implantation," Physica B: Condensed Matter, vol. 185, no. 1-4, pp. 207-210, (1993)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 21-29

doi: 10.4028/p-kHnn3Q

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-04-12

Accepted:
2025-04-14

Online:
2025-09-09

Trench Etch Processing for SiC Superjunction Schottky Diodes

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

Qinze Cao , Arne Benjamin Renz , Peter M. Gammon , Neophytos Lophitis , Kyrylo Melnyk and Marina Antoniou

School of Engineering, University of Warwick, Coventry, UK

Faculty of Engineering and Technology, Cyprus University of Technology, Limassol, Cyprus

Q.Cao.2@warwick.ac.uk, arne.renz@warwick.ac.uk, p.m.gammon@warwick.ac.uk, Neophytos.lophitis@cut.ac.cy, kyrylo.melnyk@warwick.ac.uk, marina.antoniou@warwick.ac.uk

Keywords: Silicon carbide, Superjunction, Schottky Diode, superjunction, device fabrication, inductively coupled plasma and reactive ion etching, trench devices

Abstract

This study focuses on the trench etching process for the fabrication of SiC Superjunction Schottky diodes, utilizing an ICP-RIE technique. Through a series of experiments, we optimized the etching parameters, including ICP power, RF power, and gas flow rates, to achieve etching rates ranging from to . Additionally, the study identified the performance of the hard mask as a critical issue during the etching process, which was improved by reducing the RF power below 80 w . The deepest trench achieved reached a depth of at 75 w RF power, 1000 w ICP power and , confirming the feasibility of this approach for fabricating high-performance SiC superjunction devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

Silicon carbide ( SiC ) has increasingly replaced silicon devices in power semiconductor applications due to its superior physical and chemical properties [1]. SiC unipolar devices, such as SiC Schottky diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs), exhibit faster switching speeds and lower switching losses compared to their bipolar silicon counterparts within the current commercialized range of 400 V to 3300 V [2], [3]. However, at voltages above 3300 V , the on-state voltage drop of a SiC unipolar device is high compared to Si bipolar devices of equivalent blocking voltage, due to the absence of conductivity modulation and the high resistance in the thick drift region [4]. Superjunction (SJ) MOSFETs that comprise of alternating, charge-balanced p-type and n-type columns, offer lower device resistance at a given breakdown voltage in exchange for higher output capacitance and hence slower switching. However, the common multi-epitaxial growth method [5] used in Si SJ fabrication is impractical in SiC due to limited implantation depths. Therefore, SiC superjunction MOSFETs [6] and Schottky diodes [7] have been produced using a trench etch and refill process, which overcomes these limitations by trench etching and ion implantation along the trench walls, effectively increasing the implantation depth. These trenches then need to be refilled with dielectrics, such as silicon dioxide ( ), finely tuned so additional charge states don't interfere negatively with the charge balancing principle.

In this study, we show that, because of changes in air flow in the chamber, the etch rate significantly decreases when the trench width is reduced to less than . This trend highlights the importance of refining trench etching techniques for narrow and deep trench fabrication, as precise trench quality directly impacts the performance of superjunction devices. The challenge of maintaining high etch rates while ensuring trench depth uniformity and sidewall smoothness remains a key area of research, as these factors directly affect the electrical characteristics of the device, such as charge balance and breakdown voltage.

[picture]

Fig. 1. (1): Flow chart for trench etching using a hard mask; (2) microscope image of Schottky diode active region after photolithography, amber color represents sample surface and light blue represents photo resist; (3) & (4) overlook and conner microscope image after metal lift off, white represents Ni and dark brown represents sample surface.

Fig. 1. (1): Flow chart for trench etching using a hard mask; (2) microscope image of Schottky diode active region after photolithography, amber color represents sample surface and light blue represents photo resist; (3) & (4) overlook and conner microscope image after metal lift off, white represents Ni and dark brown represents sample surface.

Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

Samples were fabricated on square chips that had a thick, lightly n-type doped epilayer grown on top of it, with the process flow illustrated in Fig. 1.1. After completing a full RCA cleaning sequence ( ), and ), a 250 nm thick blanket layer of silicon dioxide ( ) was deposited on the sample surface. Photolithography was then performed as shown in Fig. 1.2, followed by sputter deposition of 700 nm of nickel (Ni). Dimethyl sulfoxide (DMSO) and acetone were used for metal lift-off to form the metal mask on the sample surface (shown in Fig. 1.3 & 1.4). The use of this composite mask of and Ni was primarily to prevent nickel from directly penetrating the SiC surface during sputtering, thereby avoiding metal contamination. Additionally, the nickel mask prevents high-energy fluorine ions from penetrating the film and diffusing to the SiC surface during dry etching [8]. In the manufacture of Schottky diodes, the remaining mask also serves as a mask for ion implantation, thus eliminating errors associated with repeated alignment in subsequent processes.

A Corial 210IL ICP-RIE etcherwas used, with the chiller temperature fixed at . In SiC , there are strong covalent bonds between silicon and carbon. The mainstream approach for ICP-RIE dry etching employs a fluorine-based plasma, in this experiment is sulphur hexafluoride ( ) consisting of a mix of oxygen ( ) and argon (Ar) gases [9]. The main chemical reaction involved during etching process are [10]:

The addition of oxygen not only promotes the other way of volatilization of carbon atoms, forming , and , which enhances the etching rate [11]; but also leads to the formation of an layer on the trench sidewalls due to reactions between O ions and the F ions with Si atoms in SiC [12]. This layer, being more ion-attractive than SiC , results in uneven chemical reaction rates at the trench corners, an effect which has been shown to create micro-trenches [13]. These microtrenches increase the electrical field on super junction structure during voltage blocking and affect the charge balance and the complexity of ion implantation into the sidewalls [14]. Consequently, we discontinued the etching approach using . While Ar , as a stable inert carrier gas, which also contributes to enhancing the smoothness of the etched surface [15] and He which effectively reduces the heat generated during etching and serves as an excellent medium for ionization [16] are used in recipe.

The first experiment investigates the relationship between trench width and etch rate. Four different etching recipes were applied to the samples, with specific parameters detailed in Table 1. he second experiment focuses on optimizing deep trench etches for openings less than , which are representative of the dimensions expected in the final SJ device structure (around ). After etching, the cross-sections of the samples were captured using a Zeiss Gemini scanning electron microscope (SEM), and the depth, width and sidewall angles of the trenches were recorded.

Table I. Parameters for Each Etching Recipe.

Fig. 2. Left: Calculated average etching rate of Sample 1-4 against various trench widths; right: example SEM image of Sample 3 after etching.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

Fig. 2 shows the SEM image of the trench cross-section for Sample 3 (see Table I) after etching, along with the average etching rate calculated from the measured trench depth. It is evident that, when the trench width decreases below , the etching rate significantly drops. This indicates that, in a real power SiC SJ device, batch etching is necessary when there are trenches with large width variations in the device. We selected the etching recipe used for Sample 4 to fabricate the Superjunction active region [3]. In this experiment, the observed region comprises trenches with a width of and mesas with a width of , as shown in Fig.

[picture]

Fig. 3. Cross section of trench after 30 min etching under recipe 4.

Fig. 3. Cross section of trench after 30 min etching under recipe 4.

1.2 to 1.4. Ideally, the trenches in the active region should have smooth walls and rounded corners, and each trench should be as uniform as possible to facilitate particle implantation and ensure uniform electric field distribution under reverse bias. Considering the anisotropy present during trench etching, the etching process should not excessively reduce the width of the mesas, as they play a crucial role in current transport. The cross-section of the resulting trench is shown in Fig. 3, with an etch rate of . Notably, one important issue observed was the darkening of the metal mask on the sample surface after etching, as shown in Fig. 4.1. Even after a 6-hour wet etching in hydrofluoric acid (HF) and non-dilute aqua regia , some black residue remained on the sample (see Fig. 4.2). To investigate this residue, Energy-dispersive X-ray (EDX) elemental spectral analysis was conducted on the post-etched surface (point a in Fig. 4.3) and the acid-cleaned sample (points b, c, d in Fig. 4.4). According to the elemental composition displayed in Fig. 4.5, points a and b appear to be the same substance which is the rest Ni mask and trace amounts of nickel fluoride ( ). Point d is the sample surface of silicon carbide, while point c consists mainly of nickel and silicon, suggesting the formation of nickel silicide due to temperature increases during etching with the following reaction [17]:

Nickel silicide (NiSi), being highly stable, makes the residues difficult to completely remove, leading to metal contamination in subsequent device production. During the etching process, contact between silicon and nickel is unavoidable. To address this issue, reducing the sample temperature is crucial. One of the main sources of heat leading to increased sample temperature is ion bombardment from plasma [18]. In the ICP-RIE system, reactive ions (fluorine ions from in this experiment) are accelerated towards the sample surface by the electric field in the reactor. The kinetic energy of these ions, especially under the influence of a bias voltage, transfers to the substrate upon impact, resulting in heating. However, under purely thermal conditions, the formation of NiSi typically requires temperatures in the range of . In this experiment, we were unable to directly measure the surface temperature during etching, though it is likely that the wafer did not reach such high values. We hypothesize that the combined effect of high-energy ion bombardment and the presence of chemically active species in the plasma may facilitate a plasma-enhanced reaction pathway, enabling the formation of NiSi at lower effective temperatures. Based on this hypothesis and consistent experimental observations, we chose to reduce the RF power to lower the ion energy, thereby controlling the thermal load during etching and effectively minimizing NiSi formation. Fig. 5.1 shows the surface of the sample etched for 30 minutes under an ICP power of 800 W , an RF power of 60 W , and an SF6 flow rate of 10 sccm . No significant discoloration was observed on the surface, but due to the reduced RF power, the etching rate decreased to , as shown in

Fig. 5.2. To enhance the etching rate, we kept the RF power and increased the ICP power to 1000 W and adjusted the flow to 20 sccm and 40 sccm , which resulted in increased etching rates of and , respectively. Based on these rates, we performed a 45 -minute etch with an SF6 flow rate of 40 sccm , aiming for a trench depth exceeding . However, the average etching rate dropped sharply to . We hypothesize that this is due to the relatively low RF power, which is insufficient to effectively etch deeper trenches. Therefore, we gradually increased the RF power. Fig. 6.1 shows a trench with a depth of approximately after 30 minutes of etching at an RF power of 75 W , with an average etching rate of .

[picture]

Fig. 4. (1) & (2) shows sample (in Fig. 3) surface outlook under microscope before and after wet etching by acid; (3) & (4) shows the sample surface under SEM respectively; (5) shows the element composition of points from point a to d by EDX.

Fig. 4. (1) & (2) shows sample (in Fig. 3) surface outlook under microscope before and after wet etching by acid; (3) & (4) shows the sample surface under SEM respectively; (5) shows the element composition of points from point a to d by EDX.

[picture]

Fig. 5. The Sample after 30 min etching under ICP Power , RF Power , SF6 . (1) sample surface by microscope; (2) sample cross section by SEM.

Fig. 5. The Sample after 30 min etching under ICP Power , RF Power , SF6 . (1) sample surface by microscope; (2) sample cross section by SEM.

To test the controllability of this etching recipe, we performed a 21 -minute etch, aiming to fabricate a deep trench. The result, as shown in Fig. 6.3, indicates a trench depth of , confirming process repeatability. At the same time, we observed curvature at the upper part of the trench, likely due to under-cutting caused by on the high-resistance mask (such as the nickel used in this experiment). One feasible method to reduce the impact of under-cutting on the structure is to increase the thickness of the mask. As shown in Fig. 6.4, by significantly increasing the thickness of , the trench depth remained after etching, but the curvature at the trench opening was noticeably reduced. Finally, we conducted a longer etching process, and the deepest trench achieved reached a depth of with the average etching rate .

[picture]

Fig. 6. SEM image: (1) Cross section of trench after 30 min etching under ICP Power , RF Power . (2) The sample surface of sample in Fig.6.1. from angle. (3) Cross section of trench with same recipe after 21 min etching. (4) Cross section of trench with same recipe and thicker mask.

Fig. 6. SEM image: (1) Cross section of trench after 30 min etching under ICP Power , RF Power . (2) The sample surface of sample in Fig.6.1. from angle. (3) Cross section of trench with same recipe after 21 min etching. (4) Cross section of trench with same recipe and thicker mask.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

In this paper, we successfully demonstrated the fabrication of deep trenches in wafer for Superjunction Schottky diodes using ICP-RIE etching techniques. By optimizing the etching parameters, particularly the ICP and RF power levels and flow rates, we achieved a maximum etching rate of and trench depths of up to . The experiments revealed that trench width significantly influences the etching rate, with a notable decrease when the width is below . Furthermore, the formation of nickel silicide during the etching process was addressed by controlling the RF power, preventing excessive heating. These findings offer a robust foundation for further improving the fabrication of SiC super junction devices. Future work will focus on refining the trench profile and addressing the remaining challenges associated with under-cutting and sidewall roughness.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

The AdvanSiC project has received funding from the European Union's Horizon Europe programme under grant agreement No 101075709. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union. Neither the European Union nor the granting authority can be held responsible for them.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.21.pdf

A. Bolotnikov et al., "Overview of SiC MOSFETs targeted for industrial power conversion applications," Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC, vol. 2015-May, no. May, pp. 2445-2452, 2015, doi: 10.1109/APEC.2015.7104691.

T. Kimoto, "Material science and device physics in SiC technology for high-voltage power devices," Jpn J Appl Phys, vol. 54, no. 4, p. 040103, Apr. 2015, doi: 10.7567/JJAP.54.040103.

K. Melnyk et al., " 3.3 kV 4H-SiC Trench Semi-Superjunction Schottky Diode With Improved ON-State Resistance," IEEE Trans Electron Devices, vol. 71, no. 9, pp. 5573-5580, 2024, doi: 10.1109/TED.2024.3435181.

X. Zhong, B. Wang, and K. Sheng, "Design and experimental demonstration of 1.35 kV SiC super junction Schottky diode," Proceedings of the International Symposium on Power Semiconductor Devices and ICs, vol. 2016-July, pp. 231-234, 2016, doi: 10.1109/ISPSD.2016.7520820.

R. Kosugi et al., "First experimental demonstration of SiC super-junction (SJ) structure by multi-epitaxial growth method," in 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD), IEEE, Jun. 2014, pp. 346-349. doi: 10.1109/ISPSD.2014.6856047.

R. Kosugi et al., "Breaking the Theoretical Limit of 6.5 kV -Class 4H-SiC Super-Junction (SJ) MOSFETs by Trench-Filling Epitaxial Growth," Proceedings of the International Symposium on Power Semiconductor Devices and ICs, vol. 2019-May, pp. 39-42, 2019, doi: 10.1109/ISPSD.2019.8757632.

B. Wang, H. Wang, C. Wang, N. Ren, Q. Guo, and K. Sheng, "Design and Fabrication of 1.92 kV 4H-SiC Super-Junction SBD With Wide-Trench Termination," IEEE Trans Electron Devices, vol. 68, no. 11, pp. 5674-5681, Nov. 2021, doi: 10.1109/TED.2021.3109107.

J. Li et al., "Morphology improvement of SiC trench by inductively coupled plasma etching using Ni/Al 2 O 3 bilayer mask," Mater Sci Semicond Process, vol. 67, no. February, pp. 104109, Aug. 2017, doi: 10.1016/j.mssp.2017.05.022.

K. Racka-Szmidt, B. Stonio, J. Żelazko, M. Filipiak, and M. Sochacki, "A Review: Inductively Coupled Plasma Reactive Ion Etching of Silicon Carbide," Materials, vol. 15, no. 1, p. 123, Dec. 2021, doi: 10.3390/ma15010123.

R. Liu et al., "A dry etching method for 4H-SiC via using photoresist mask," J Cryst Growth, vol. 531, no. November 2019, p. 125351, Feb. 2020, doi: 10.1016/j.jcrysgro.2019.125351.

F. A. Khan and I. Adesida, "High rate etching of SiC using inductively coupled plasma reactive ion etching in SF6-based gas mixtures," Appl Phys Lett, vol. 75, no. 15, pp. 2268-2270, Oct. 1999, doi: 10.1063/1.124986.

G. M. Beheim and L. J. Evans, "Control of Trenching and Surface Roughness in Deep Reactive Ion Etched 4H and 6H SiC," MRS Proceedings, vol. 911, no. 1, pp. 0911-B10-15, Feb. 2006, doi: 10.1557/PROC-0911-B10-15.

J.-H. Min, G.-R. Lee, J.-K. Lee, S. H. Moon, and C.-K. Kim, "Effect of sidewall properties on the bottom microtrench during SiO2 etching in a CF4 plasma," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 23, no. 2, pp. 425-432, Mar. 2005, doi: 10.1116/1.1865113.

X. Zhong, B. Wang, J. Wang, and K. Sheng, "Experimental Demonstration and Analysis of a Omega \cdot text SiC Superjunction Schottky Diode," IEEE Trans Electron Devices, vol. 65, no. 4, pp. 1458-1465, Apr. 2018, doi: 10.1109/TED.2018.2809475.

A. A. Osipov, S. E. Aleksandrov, Yu. V Solov'ev, A. A. Uvarov, and A. A. Osipov, "Etching of SiC in Low Power Inductively-Coupled Plasma," Russian Microelectronics, vol. 47, no. 6, pp. 427-433, 2018, doi: 10.1134/S1063739719010074.

S. H. Kuah and P. C. Wood, "Inductively coupled plasma etching of poly-SiC in SF6 chemistries," Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol. 23, no. 4, pp. 947-952, Jul. 2005, doi: 10.1116/1.1913682.

M. Tinani, A. Mueller, Y. Gao, E. A. Irene, Y. Z. Hu, and S. P. Tay, "In situ real-time studies of nickel silicide phase formation," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 19, no. 2, pp. 376-383, Mar. 2001, doi: 10.1116/1.1347046.

S. Il Cho, H. K. Park, S. An, and S. J. Hong, "Plasma Ion Bombardment Induced Heat Flux on the Wafer Surface in Inductively Coupled Plasma Reactive Ion Etch,"Applied Sciences, vol. 13, no. 17, p. 9533, Aug. 2023, doi: 10.3390/app13179533.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 31-36

doi: 10.4028/p-NWvo3B

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-07

Accepted:
2025-02-20

Online:
2025-09-09

Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

Clément Berger , Daniel Alquier and Jean-François Michaud

GREMAN UMR-CNRS 7347, Université de Tours, INSA Centre Val de Loire, 16 rue Pierre et Marie Curie, 37071 TOURS Cedex 2, France

clement.berger@univ-tours.fr, daniel.alquier@univ-tours.fr, cjean-francois.michaud@univ-tours.fr

Keywords: Surface preparation, Ohmic contact, Laser annealing, 4H-SiC

Abstract

Laser Thermal Annealing (LTA) is a necessary fabrication step to improve the devices by reducing their ON-state resistance. Because the LTA annealing is achieved at the end of the front-end fabrication, the classical Radio Corporation of America cleaning (RCA) cannot be used without affecting the material deposited on the frontside. Therefore, in this study, we investigate the argon (Ar) plasma surface treatment, achieved in our sputtering tool, before the ohmic contact fabrication, as an alternative surface preparation to the RCA sequence. As the Ar plasma modifies the SiC surface morphology, it affects its wetting properties. That can play a key role in the ohmic contact formation by LTA since the nickel turns into liquid phase during the laser irradiation. For an Ar plasma treatment of 30 min , a specific contact resistance of has been obtained for an annealing at 5.0 J.cm-2, which is in the same range than the contact fabricated by LTA involving a classical RCA cleaning.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

Silicon carbide (SiC) is a wide bandgap semiconductor, with superior physical and chemical properties allowing the fabrication of devices able to work at high voltage and high temperature [1]. To further improve devices, the fabrication of vertical devices includes a grinding step of the substrate backside (C-face) reducing the device ON resistance. This implies a modification of the process flow and of the ohmic contact fabrication [2]. In this case, since the ohmic contact is performed at the end of the process flow, Rapid Thermal Annealing (RTA) cannot be used anymore without affecting the frontside materials. Then, to preserve the materials integrity, Laser Thermal Annealing (LTA) is currently used to achieve the backside ohmic contact. Several investigations were performed to study such contacts formed from titanium (Ti) or nickel (Ni) layers by LTA [3], [4], [5]. From the literature, nickel seems the most favorable metal to form efficient ohmic contact by LTA, with specific contact resistances in the range. Based on our previous results on titanium and nickel, these contacts reached the ohmicity since they turn into their liquid phase. Therefore, the wetting properties of -face may play a role in the reaction between metal and SiC surface.

Generally, researches focused on the ohmic contacts involve a cleaning step with acid mixtures, like the Radio Corporation of America (RCA) sequence. Nevertheless, due to the elaboration of the backside ohmic contact at the end of the device fabrication, those chemical solutions can affect materials deposited on the wafer frontside. As a consequence, either a sacrificial layer has to be deposited on the front face before the cleaning sequence or a new surface preparation must be performed before the metal deposition, keeping the wafer frontside integrity.

In this study, we investigated the effect of a plasma treatment of the SiC surface before the nickel deposition though structural, morphological and electrical characterizations. Results will be compared with our best ohmic contact fabricated by LTA [6].

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

For the physical characterizations, we fabricated the contacts on the C -face of samples diced from bulk substrates, since C -face is classically used for the ohmic contact fabrication of the devices. Contrary to the classical ohmic contact achievement by RTA, we did not perform any acid cleaning such as Caro's or RCA sequence. Instead, we only dipped the sample in acetone to remove large particles on the surface. Then, samples were treated with an argon (Ar) plasma, generated in the chamber of the sputtering equipment (Plassys M650S) used for the metal deposition, for durations till 60 min . The chamber pressure was kept at 17 mTorr and the RF power was 100 W . In these conditions, the etching rate of the SiC substrate was estimated to , by measuring a step with an Atomic Force Microscope (AFM). Consecutively to this Ar plasma processing, a 100 nm-thick nickel layer was deposited on the SiC at 5 mTorr under Ar . Finally, samples were irradiated with a tripled frequency YAG laser ( 355 nm ) at a fluence of . The irradiations were performed at 30 kHz with a scanning speed of . Those irradiations conditions allow to form efficient nickel ohmic contact as presented in [6].

For the electrical characterizations, we used an isolated substrate configuration to prevent the current circulation through the substrate thickness that could affect the electrical performance determination [7]. Therefore, using the same protocol as described previously, contacts were fabricated on a highly nitrogen-doped epilayer ( at. ) grown onto a non-intentionally doped epilayer ( thick - ) on the Si-face of a substrate. After the irradiation of the unpatterned Ni layer, circular Transfer Length Method (cTLM) structures were fabricated by Ion Beam Etching (IBE). The measured real spacings vary from 14 to with a constant inner electrode presenting a diameter of . Finally, an aluminum layer was deposited on the cTLM patterns to thicken the contacts.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

First, consecutively to the Ar plasma treatment, we evaluated the wetting properties of a deionized (DI) water drop on the treated SiC surface. To do so, we used the contact angle method on both SiC faces. The contact angle obtained for several SiC surface conditions are shown on the Figure 1 and on the Table 1. For the SiC only degreased in acetone, without plasma treatment, the water drop shape is almost spherical, resulting in a contact angle of and , respectively on the C - and Si-face, demonstrating a hydrophobic behavior. This measurement highlights the presence of a native oxide at the surface [8]. For the Ar plasma exposed samples, even for the smallest duration of 1 min , the drop spreading leads to an angle lower than on both faces. As a comparison, we removed the native oxide by dipping a sample in hydrofluoric acid (HF) during 5 min , rinsed with DI and dry under nitrogen flow, resulting in a contact angle of 20 and on both C - and Si -face respectively. It is worth to mention that a high dispersion was observed with HF treatment because of erratic drop shape. Thus, we note that the plasma processing reaches to a higher SiC wettability than the oxide removal only. It is even clearer when the measurement is not performed directly after the treatment. Indeed, for the sample exposed to HF , after only 15 min , the contact angle significantly increases, probably due to the native oxide regrowth, whenever the 20 min Ar treated sample still shows a high wettability several hours after. Therefore, the plasma treatment leads to higher wetting properties than HFtreatment, even more at a long-time scale. This could be attributed to topological roughness changes that alter the native oxide regrowth. To investigate the origin of such changes, we analyzed the SiC surface at nanoscale by AFM measurement.

[picture]

Fig. 1. Images of the contact angle of a water drop on SiC , with a camera tilt angle of , (a) without treatment, (b) after a Ar plasma processing of 1 min and (c) 20 min .

Fig. 1. Images of the contact angle of a water drop on SiC , with a camera tilt angle of , (a) without treatment, (b) after a Ar plasma processing of 1 min and (c) 20 min .

Table 1. Measurements of contact angles of a water drop on SiC for several surface conditions. The measurements were performed immediatly, 15 min and 24 hours after the treatment. "-" symbol refers to condition not measured.

Measured immediatly (C-face / Si-face) | After 15 min (C-face / Si-face) | After 4 hours (C-face / Si-face) | After 24 hours (C-face / Si-face)
Acetone cleaning | 72° / 77° | - | - | -
HF(1%) – 5 min | 20° / 24° | 44° / 44° | 50° / 32° | 42° / 34°
Ar plasma – 1 min | <5° / <5° | <5° / <5° | 12° / 16° | 69° / 71°
Ar plasma – 20 min | <5° / <5° | <5° / <5° | 17° / 18° | 20° / 22°
Ar plasma – 30 min | 10° / 10° | 12° / 13° | 26° / 29° | 39° / 44°

The Figure 2 presents AFM characterizations of the surface before and after different Ar plasma treatments. The surface of the shortest plasma treated sample is very similar to the one of the non-treated samples. Both present scratches, coming from the polishing stage. More, their roughness value are identical and evaluated to 0.62 nm . Therefore, for this condition, the roughness and the surface morphology evolution do not seem to be responsible for the SiC wettability increase. The better wettability observed previously for this condition is then mostly attributed to the native oxide removal leaving a clean surface without the need of rinsing/drying that could bring some particles on the substrate. This might be why this sample behavior, 24 hours after the plasma exposure, was similar to the non-treated SiC due to the natural native oxide regrowth. After 10 min treatment, the minor scratches seem to be softened but the roughness was kept. From 20 min , the surface morphology strongly evolves by starting to present grains. The roughness slightly increases to 0.72 nm . Finally, for durations of 30 and 60 min , the grains become greater and greater, leading to a massive roughness increase for the longest plasma exposure ( ). For long treatment duration, SiC surface is clearly affected by the Ar plasma, which might be responsible for the wettability modification observed. Then, it could influence the metal spreading during its melting under the high power laser annealing required to form ohmic contact.

[picture]

Fig. 2. AFM images of the surface after an Ar plasma duration of (a) 0 min , (b) 1 min , (c) 10 min , (d) 20 min , (e) 30 min and (f) 60 min . The roughness (Rq) is noted for each condition.

Fig. 2. AFM images of the surface after an Ar plasma duration of (a) 0 min , (b) 1 min , (c) 10 min , (d) 20 min , (e) 30 min and (f) 60 min . The roughness (Rq) is noted for each condition.

Consecutively to the AFM measurements, a 100 nm -thick Ni layer was deposited on the treated SiC for several plasma durations. The Ni layer was then laser annealed at . Scanning Electron Microscope (SEM) images of contacts are presented on Figure 3. Without any surface treatment, the contact surface seems homogeneous, fully covering the SiC surface. However, a lot of nanoparticles are fully covering the contact after the irradiation (not visible at the magnification presented here). Then, surface morphology of the Ni contact evolves with the plasma duration. For a 20 min treatment, the gap between the irradiations is partially filled, suggesting a higher wetting of the liquid nickel onto the SiC . After 60 min of Ar plasma treatment, the contact morphology is the most regular among all the treated SiC , especially at the pulse center. Also, the nanoparticles density, covering the contact, is massively reduced compared to other conditions, highlighting a higher reaction between Ni and the substrate. In this case, the higher effective contact surface should be beneficial to reach better electrical performance and contact reliability.

Finally, electrical characterizations were performed on the Ni contacts by the means of TLM structures. The Figure 4(a) presents the current-voltage (I-V) characteristics for the contacts prepared on SiC exposed to an Ar plasma during 30 min . The curves start to be linear from , highlighting the Schottky to ohmic transition. For the ohmic contacts prepared on the 30 min plasma treated SiC, the Specific Contact Resistance (SCR) was extracted for each fluence on the Figure 4(b). Reference contacts, presented in [6], fabricated with a classical cleaning, is also plotted. For the Ar plasma surface preparation sample, the SCR decreases with the increase of the fluence till indicating an improvement of the ohmic properties.

[picture]

Fig. 3. SEM images of contacts annealed at after a plasma treatment duration of (a) 0 min , (b) 1 min , (c) 10 min , (d) 20 min , (e) 30 min and (f) 60 min .

Fig. 3. SEM images of contacts annealed at after a plasma treatment duration of (a) 0 min , (b) 1 min , (c) 10 min , (d) 20 min , (e) 30 min and (f) 60 min .

The optimal SCR value reaches , that is in the same range with the best reference value . This result is hopeful considering that it is compatible with the device fabrication on thin substrate that prevents the use of chemical etching treatment before the metal deposition.

[picture]

Fig. 4. (a) Current-Voltage characteristics of Ni contacts fabricated by LTA on a 30 min plasma exposed SiC surface. (b) Evolution of the specific contact resistance for the 30 min treated sample (black symbols) and a reference sample processed with a classical cleaning (red symbols) described in [6]. Error bars represent the min/max SCR value for each annealing condition.

Fig. 4. (a) Current-Voltage characteristics of Ni contacts fabricated by LTA on a 30 min plasma exposed SiC surface. (b) Evolution of the specific contact resistance for the 30 min treated sample (black symbols) and a reference sample processed with a classical cleaning (red symbols) described in [6]. Error bars represent the min/max SCR value for each annealing condition.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

The obtention of ohmic contact on thinned substrate is currently achieved by laser irradiation, after the frontside fabrication. The classical acid cleaning could not be performed without affecting the materials located on the frontside. Therefore, we proposed to prepare the backside surface by using a plasma treatment before the metal deposition as an alternative to the wet cleaning. Surface characterizations demonstrated a modification of the SiC morphology, which might be responsible for its wetting properties modification. Therefore, when a nickel layer is annealed at high fluence, it reacts differently, after going through its liquid phase with SiC , depending on the Ar plasma treatment. Thanks to this plasma etching procedure, Ni ohmic contacts have been successfully fabricated with a 30 min treatment, presenting SCR values in the same range than the ones reached with a classical wet cleaning sequence. Samples with other plasma treatment durations are under electrical characterization.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

The authors acknowledge the financial support provided by the "Agence Nationale de la Recherche" (ANR) through the project TempoScopy (ANR-19-CE42-0008).

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.31.pdf

T. Kimoto and J. A. Cooper, "Fundamentals of Silicon Carbide Technology: growth, characterization, devices and applications", Wiley, Singapore, 2014.

S. Rascunà, P. Badalà, C. Tringali, C. Bongiorno, E. Smecca, A. Alberti, S. Di Franco, F. Giannazzo, G. Greco, F. Roccaforte, M. Saggio, "Morphological and electrical properties of Nickel based Ohmic contacts formed by laser annealing process on n-type 4H-SiC", Mater. Sci. Semicond., vol. 97, p. 62, 2019, doi: 10.1016/j.mssp.2019.02.031.

M. De Silva, T. Kawasaki, T. Miyazaki, T. Koganezawa, S. Yasuno and S.-I. Kuroki, "Formation of epitaxial Ti-Si-C Ohmic contact on 4H-SiC C face using pulsed-laser annealing", Appl. Phys. Lett., vol. 110, no. 25, p. 252108, 2017, doi: 10.1063/1.4987136.

C. Berger, D. Alquier, M. Bah and J.-F. Michaud, "Electrical, morphological and structural properties of Ti ohmic contacts formed on n-type 4H-SiC by laser thermal annealing", Mater. Sci. Semicond., vol. 151, p. 106983, 2022, doi: 10.1016/j.mssp.2022.106983.

P. Badalà, S. Rascunà, B. Cafra, A. Bassi, E. Smecca, M. Zimbone, C. Bongiorno, C. Calabretta, F. La Via, F. Roccaforte, M. Saggio, G. Franco, A. Messina, A. La Magna, A. Alberti, "Ni/4HSiC interaction and silicide formation under excimer laser annealing for ohmic contact", Materialia, vol. 9, p. 100528, 2020, doi: 10.1016/j.mtla.2019.100528.

J. F. Michaud, C. Berger and D. Alquier, "Nickel Ohmic Contacts Formed on by UV Laser Annealing", Solid State Phenomena, vol. 359, p. 91, 2024, doi: 10.4028/p-xqh9xB.

C. Berger, D. Alquier and J.-F. Michaud, "How to Accurately Determine the Ohmic Contact Properties on n-Type 4H-SiC", Electronics, vol. 13, no. 1, p. 217, 2024, doi: 10.3390/electronics 13010217.

J. G. Kim, W. S. Yoo, J. Y. Park and W. J. Lee, "Quantitative Analysis of Contact Angle of Water on SiC: Polytype and Polarity Dependence", ECS J. Solid State Sci. Technol., vol. 9, no. 12, p. 123006, 2020, doi: 10.1149/2162-8777/abcd0b.

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The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 37-43

doi: 10.4028/p-Dlp4Ka

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-21

Revised:
2025-03-20

Accepted:
2025-03-20

Online:
2025-09-09

Analysis of Ohmic Contacts Simultaneously Formed on both -Type and -Type -SiC

The original version of this paper is available on https://www.scientific.net/MSF.1159.37.pdf

Atsushi Shimbori , Rahul Valecha and Alex Q. Huang

J.J. Pickle Research Center, The University of Texas at Austin Bldg. #160, 10100 Burnet Rd. Austin, TX 78758, USA

ashimbo@utexas.edu, rahul.valecha@utexas.edu, aqhuang@utexas.edu

Abstract

In this paper, various annealing conditions using Al-based ( ) and Ni-based ( ) metal contacts to n-type and p-type ion-implanted epi layers have been studied in the effort to optimize simultaneous ohmic contact formation with the lowest specific contact resistance (SCR) values. Values of and were achieved using Al-based Ohmic metal contacts for p-type and n-type 4H-SiC, respectively, at an annealing temperature of and under vacuum for 90 sec. Ohmic formation mechanisms were analyzed using the X-Ray Diffraction (XRD) surface analysis method, indicating alloys to be the key intermediate layer formed at interface, responsible for Ohmic properties to p-type SiC. The paper summarizes the metal process combinations possible for the formation of Ohmic contacts to both n-type and p-type , offering various options in either using the same metal materials and/or common annealing conditions.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.37.pdf

Simultaneous formation of Ohmic contacts to both n-type and p-type 4 H SiC is essential to simplifying the fabrication process and optimizing the device size of SiC MOSFETs and PiN diodes. Especially for vertical power SiC MOSFETs, in order to effectively reduce the cell pitch to further increase channel density and improve device performance, simultaneous formation of ohmic contacts both on source region and p -well region with low specific contact resistance using the same contact metal and/or common annealing condition is essential. Not only device performance is dependent on drain/source contact resistance and its current conduction capability, quality p -well contact is also required to short out the base and emitter through source metallization to disable the parasitic NPN transistor and provide the substrate contact for the inversion channel in the MOSFET structure.

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Fig. 1. Two-terminal differential resistance value at various annealing temperature.

Fig. 1. Two-terminal differential resistance value at various annealing temperature.

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Fig. 2. Fabricated Transfer Length Method (TLM) pattern with mesa-isolation etch.

Fig. 2. Fabricated Transfer Length Method (TLM) pattern with mesa-isolation etch.

Fabrication

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In this experiment, a substrate with an epi layer in a thickness of and a nitrogen doping concentration of was used. The implantations of phosphorus ions were performed at room temperature, using different ion energies ( ) and doses of to create a box profile with a depth of roughly 280 nm and a concentration of for the formation of layer (Summarized in Table I and Fig. 3(a)). The implantations of aluminum ions were performed at , using different ion energies ( ) and doses of to create a box profile with a depth of approximately 250 nm and a concentration of for the formation of layer (Summarized in Table II and Fig. 3(b)). Both layers were formed on opposite polarity well of a epi wafer.

The activation process involves the deposition of a Diamond-Like Carbon (DLC) layer through the method of plasma-based ion implantation and deposition (PBIID) in a thickness of 70 nm as the cap layer, followed by annealing at for 30 min to electrically activate both implanted dopants. It is known that high-temperature annealing at is necessary to obtain an activation ratio higher than .

In this paper, we will be exploring two different types of Ohmic metal stacks: Al-based Ohmic metal contact stacks ( ) and Ni-based Ohmic metal contact stacks . The role of the thin Ti layer (thickness of 5 nm ) is to prevent oxidation from occurring further inward by forming titanium oxides [2]. Titanium oxide can take oxygen away from , and SiC to prevent further oxidation. Transfer Length Method (TLM) patterns were formed through photolithography and then mesa-isolated with a shallow fluorine-based ICP etch as shown in Fig. 2. The annealing temperature was optimized using the twoterminal differential resistance method shown in Fig. 1. All contacts were annealed under a vacuum of Torr using Annealsys Rapid Thermal Processor (RTP).

Table I. Phosphorus implantation series for n-type ohmic contact.

Dopant | Dose [cm⁻²] | Energy [keV] | Angle/Twist [degree]
Phosphorus | 2.7×10¹⁵ | 200 | Tilt 7, Twist 23
Phosphorus | 1.4×10¹⁵ | 100 | Tilt 7, Twist 23
Phosphorus | 9.0×10¹⁴ | 50 | Tilt 7, Twist 23

Table II. Aluminum implantation series for p-type ohmic contact.

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Fig. 3. Secondary Ion Mass Spectrometry (SIMS) profiles of Phosphorus and Aluminum implantation to the epi wafers.

Fig. 3. Secondary Ion Mass Spectrometry (SIMS) profiles of Phosphorus and Aluminum implantation to the epi wafers.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.37.pdf

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Fig. 4. TLM evaluation of Al-based ohmic contact to p-type SiC annealed at .

Fig. 4. TLM evaluation of Al-based ohmic contact to p-type SiC annealed at .

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Fig. 5. TLM evaluation of Al-based ohmic contact to n-type SiC annealed at .

Fig. 5. TLM evaluation of Al-based ohmic contact to n-type SiC annealed at .

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Fig. 6. Comparison of Ni-based ohmic contact to n-type SiC at various annealing temperature.

Fig. 6. Comparison of Ni-based ohmic contact to n-type SiC at various annealing temperature.

The fabricated TLM structures were electrically characterized and the sheet resistance Rs, the contact resistance , as well as the specific contact resistance were extracted. The nickel silicide layers formed from Ni-based metal contacts, at an annealing temperature above , exhibited good ohmic behavior to heavily doped n-type layer and continued to show lower specific contact resistance with respect to the increasing annealing temperature (Fig. 6). This is because the outdiffusion of C atoms during high temperature annealing ( ) creates carbon vacancies in SiC , which acts as donors, thus contributing to even lower specific contact resistance [3]. On the other hand, this is not the same against p-type layer, as Ni-based ohmic metal shows slightly non-linear - characteristics. A different system is necessary for forming quality ohmic contacts to p-type and Ohmic formation mechanism will be explained in the following XRD spectra results. The obtained specific contact resistance against p -type SiC layer using the alternative Al -based metal contacts was at an annealing temperature of (Fig. 4). Additionally, the Al-based metal contact was also effective against n-type SiC layer, showing specific contact resistance value of achieving simultaneous formation (i.e., using the same contact materials and a one-step annealing process) of Ohmic contacts to both n-type and p-type 4H-SiC (Fig.5). Table III below summarizes past reports of specific contact resistance for ohmic contacts simultaneously formed on , indicating the competitiveness of the values obtained from our current work.

Table III. Reported specific contact resistance for ohmic contacts simultaneously formed on .

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Fig. 7. XRD spectra of Al-based ( ) Ohmic contact to p-type SiC annealed at , and .

Fig. 7. XRD spectra of Al-based ( ) Ohmic contact to p-type SiC annealed at , and .

Fig. 7 illustrates the XRD spectra of Al-based Ohmic contacts formed on p-type at various annealing temperatures. Rapid thermal annealing (RTA) at , under vacuum, forms alloys, which grow at the interface responsible for Ohmic properties to p-type SiC . These alloys have a work function of 5.07 eV , which corresponds to an intermediate value between Ti and p-type SiC , dividing the large barrier height into two smaller ones as shown in Fig. 8 [9]. As a result, the height of the original Schottky barrier is lowered and the carrier transport is enhanced through thermionic emission for Ohmic conduction.

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Fig. 8. Schematic of band offsets for metal/ alloy/p-type SiC sequence.

Fig. 8. Schematic of band offsets for metal/ alloy/p-type SiC sequence.

Consequently, it becomes easier for holes, whose movement is represented by the red arrows in Fig. 8, to transport from the metal electrode to the valence band of p-type . The peak of is only clearly visible in the sample (blue spectrum in Fig. 7), and this alloy contributes to the decrease of differential resistance value observed in Fig. 1. In addition, the main role of the Al mid layer in the Al-based Ohmic metal stacks ( ) is to assist the formation of a liquid alloy that both facilitates and accelerates the reaction between the SiC and the Ti to form alloys [10]. The intense reflection peaks, observed around degrees, correspond to the pure Al , which increases with annealing temperature. Al starts to melt to the surface at in vacuum and this phenomenon accelerates as the annealing temperature increases, which results in intensifying peaks observed through XRD surface analysis. Large droplets of Al can also be confirmed with the microscope image in Fig. 9. These surface morphology transitions only take place under annealing at a high temperature, high vacuum condition due to the evaporation of the liquid phase, such as the Al-based liquid alloy with a low melting point and high vapor pressure.

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Fig. 9. Microscope image of Al based electrodes .

Fig. 9. Microscope image of Al based electrodes .

Table IV. Summary of various Ohmic metal process to -type and -type 4 H -SiC and extracted parameters.

Table IV summarizes the metal process combinations possible in the formation of ohmic contacts to both and -type 4 H -SiC, offering various options in either using the same metal materials and/or common annealing conditions. Although Al-based metal contact forms quality Ohmic contact with a relatively low specific contact resistance (SCR) value, system alone may not be ideal for the ntype Ohmic contact formation (Metal Process 3 and Fig. 5 comparison). The adaptation of an additional Ni layer within the system to form nickel silicide is expected to further reduce the SCR values close to that of Metal Process 4 or 5. On the other hand, for p-type SiC, the Ni atoms added to the system will react with SiC to form , leaving more unreacted C atoms to react with Ti and Si atoms to form . Thus, the combined blend of Al -based and Ni -based metal contact through thickness optimization may offer further benefits (lower SCR values, lower annealing temperature, etc.) in achieving simultaneous formation (i.e., using the same contact materials and a one-step annealing process) of Ohmic contacts to both n-type and p-type 4H-SiC.

To summarize the obtained results, the formation of nickel silicide ( ) layers is necessary in forming quality ohmic contacts to n-type SiC. Ni-based metal contacts continue to show lower specific contact resistance with respect to increasing the annealing temperature up to and possibly even at a higher temperature until surface deterioration cannot be ignored any further. Ohmic contacts to p-type SiC requires an system (Al-based), and the optimal annealing temperature
for the formation of necessary alloys is at . Additionally, the Al-based metal contact is also effective against the n-type SiC layer, achieving simultaneous formation of Ohmic contact to both n-type and p-type 4H-SiC.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.37.pdf

In conclusion, various annealing conditions using Al-based ( ) and Ni-based ( ) metal contacts to n-type and p-type ion-implanted epi layers have been investigated in the effort to optimize simultaneous ohmic contact formation with the lowest specific contact resistance (SCR) values. Values of and were obtained using Al-based Ohmic metal contacts for p-type and ntype , respectively, at an annealing temperature of and under vacuum for 90 sec , achieving simultaneous formation. Ohmic formation mechanisms were analyzed using the X-Ray Diffraction (XRD) surface analysis method, indicating alloys to be the key intermediate layer formed at interface, responsible for Ohmic properties to p-type SiC . We have successfully investigated the metal process combinations possible in forming Ohmic contacts to both n-type and p-type , offering various options in either using the same metal materials and/or common annealing conditions.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1159.37.pdf

The authors of this paper would like to thank Nissin Ion Equipment Co. Ltd for their support throughout the implantation process.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.37.pdf

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Kuchuk, A. V., Borowicz, P., Wzorek, M., Borysiewicz, M., Ratajczak, R., Golaszewska, K., Kaminska, E., Kladko, V., and Piotrowska, A., "Ni-Based Ohmic Contacts to n-Type 4H-SiC: The Formation Mechanism and Thermal Stability", Advances in Condensed Matter Physics, 2016, 9273702, 26 pages, 2016. doi:10.1155/2016/9273702

Tsukimoto, S., Onishi, T., Ito, K., and Murakami, M., "Simultaneous Formation of Ohmic Contacts for Both N- and P-Type 4H-Sic Using Nial-Based Contact Materials", MRS Proceedings, vol. 911, pp. 0911-B11-05, 2006. doi:10.1557/PROC-0911-B11-05

Vivona, M., Greco, G., Giannazzo, F., Lo Nigro, R., Rascunà, S., Saggio, M., and Roccaforte, F., "Thermal stability of the current transport mechanisms in Ni-based Ohmic contacts on n- and pimplanted 4H-SiC", Semiconductor Science Technology, vol. 29, no. 7, Art. no. 075018, IOP, 2014. doi:10.1088/0268-1242/29/7/075018.

Ito, K., Onishi, T., Takeda, H. et al. "Simultaneous Formation of Ni/Al Ohmic Contacts to Both n- and p-Type 4H-SiC", J. Electron. Mater. 37, 1674-1680 (2008). doi:10.1007/s11664-008-0525-1

Kragh-Buetow, K. C., Okojie, R. S., Lukco, D., and Mohney, S. E., "Characterization of tungstennickel simultaneous Ohmic contacts to p- and n-type , Semiconductor Science Technology, vol. 30, no. 10, Art. no. 105019, IOP, 2015. doi:10.1088/0268-1242/30/10/105019

Okojie, R. S., and Lukco, D., "Simultaneous ohmic contacts to p- and n-type 4H-SiC by phase segregation annealing of co-sputtered Pt-Ti", J. Appl. Phys. 7 December 2016; 120 (21): 215301. doi:10.1063/1.4968572

Johnson, B., and Capano, M., "Mechanism of ohmic behavior of Al/Ti contacts to p-type 4H-SiC after annealing", J. Appl. Phys. 15 May 2004; 95 (10): 5616-5620. doi:10.1063/1.1707215

Buchholt, K., Ghandi, R., Domeij, M., Zetterling, C.-M., Lu, J., Eklund, P., Hultman, L., and Lloyd Spetz, A., "Ohmic contact properties of magnetron sputtered on - and p-type 4Hsilicon carbide", Appl. Phys. Lett. 24 January 2011; 98 (4): 042108. doi:10.1063/1.3549198

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The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 45-53

doi: 10.4028/p-nh88kE

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-10

Accepted:
2025-02-19

Online:
2025-09-09

Gate Oxide Performance and Reliability on SmartSiC Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

The original version of this paper is available on https://www.scientific.net/MSF.1159.45.pdf

T. Becker , M. Rommel , H. Schlichting , L. Baier , E. Guiot and F. Allibert

Fraunhofer IISB, Schottkystr. 10, 91058 Erlangen, Germany

Soitec, Parc Technologique des Fontaines, 38190 Bernin, France

tom.becker@iisb.fraunhofer.de, mathias.rommel@iisb.fraunhofer.de,

Keywords: Gate Oxide, Reliability, SiC, MOS, TDDB, Annealing, SmartSiC ™, RTA, QBD

Abstract

In this work, a comparison of standard bulk epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent high temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The VFB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.45.pdf

With silicon carbide (SiC) power devices becoming more and more relevant in the electrification of the automotive sector as well as for renewable energies, a demand for more cost-efficient ways to manufacture these devices, in addition to a fabrication yield increase will be necessary. For this purpose, Soitec introduced its SmartSiC technology (see Fig. 1), which combines low resistivity polycrystalline SiC substrates with high-quality monocrystalline top-layers, to minimize devices on-resistance and cost of ownership [1]. In this paper we evaluate the compatibility of this SiC engineered substrate with gate oxide fabrication in terms of capacitor yield, and reliability. We also investigate the impact of including, or not, an RTA step in the capacitor fabrication process, for comparability to full MOS-transistor processes, where this step is necessary. The annealing step required on standard bulk SiC substrates to ensure good backside metal contact can be skipped on SmartSiC wafers [2] but the resulting lower dopant activation in the polycrystalline silicon gate electrode adversely impacts the gate oxide evaluation. For structured ohmic contacts with low resistivity on the epitaxial surface, RTA is still necessary.

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Fig. 1. Wafer types used for this study are standard single crystal bulk (left) and SmartSiC engineered substrates composed of a layer of high quality monocrystalline 4 H SiC on an ultra-high conductivity ( ) polycrystalline SiC substrate. [3]

Fig. 1. Wafer types used for this study are standard single crystal bulk (left) and SmartSiC engineered substrates composed of a layer of high quality monocrystalline 4 H SiC on an ultra-high conductivity ( ) polycrystalline SiC substrate. [3]

Sample Preparation

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To be able to evaluate the performance and reliability of gate oxides on engineered SiC substrate (SmartSiC™) wafers in comparison to standard (bulk) wafers and investigate the influence of RTA processing, a design of experiment with four major splits was implemented (see table 1 ).

The 150 mm wafers used had an epitaxial n -doped layer stack of a buffer and a drift layer. The 52 nm gate oxide was thermally grown at and a 500 nm in-situ phosphorous-doped polycrystalline silicon layer was deposited at as the gate electrode. To avoid high temperature steps other than the RTA after gate oxidation for selected wafers, a 600 nm thick field oxide was deposited using a plasma enhanced CVD process at about . After the opening of the field oxide above the polycrystalline gate electrode via dry etching, the wafers A and C were processed in an RTA tool for 2 minutes at in Argon atmosphere in order to establish comparability to full SiC MOS-transistor processes. To complete the front side process, a power metallization consisting of a stack was sputtered and structured above the vias in the field oxide. On the wafer backside, NiAl was deposited and an ohmic contact was created by laser annealing of all standard bulk wafers (not needed on engineered SiC substrate [2]. A thick aluminum layer was then deposited on all wafers on the backside and a forming gas tempering for 30 minutes at was performed.

Table 1. Wafer type and process split.

# | Wafer type | RTA
A | Standard bulk SiC | yes
B | Standard bulk SiC | no
C | Engineered SiC substrate | yes
D | Engineered SiC substrate | no

In parallel to these SiC MOS-Cap wafers, four Silicon dummy wafers with a 100 nm oxide layer underneath a 500 nm doped polycrystalline silicon layer were processed and characterized with regards to the sheet resistance of the polycrystalline layers before and after being processed in the RTA, via a four-point probe measurement.

Electrical Characterization

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After the manufacturing of these MOS-Caps, several electrical characterization methods were used to determine the flat band voltage, breakdown properties and reliability on forty devices per parameter investigated.

On the largest capacitors with areas of and -measurements were conducted from +10 V to -20 V to determine the impact of the RTA. Fig. 2 (left) shows exemplary CV-curves at 100 kHz on wafer A. The tight distribution obtained on all capacitor sizes and on all wafers (not shown here) allows significant comparison between the various wafer flavors, using typical curves. Fig. 2 (right) shows typical quasi-static (QS), 100 kHz and 1 MHz back-and-forth CV-curves. The lack of hysteresis demonstrates the absence of slow traps. The only impact of frequency is the small shift between QS and higher frequencies (typical for the expected ) observed close to flat band capacitance.

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Fig. 2. 100 kHz CV measurement for three different capacitor sizes (left), and QS, 100 kHz and 1 MHz back-and-forth measurements (right) on wafer A .

Fig. 2. 100 kHz CV measurement for three different capacitor sizes (left), and QS, 100 kHz and 1 MHz back-and-forth measurements (right) on wafer A .

The comparison of the capacitance characteristic of all tested wafers (see Fig. 3) makes obvious that the shift is linked to the thermal budget the gate stack (oxide and polysilicon electrode) was exposed to during processing, while there was no difference of substrate type used.

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Fig. 3. Typical CV measurements at 1 MHz for all studied wafers, depicting a clear shift between wafer subjected to RTA and not.

Fig. 3. Typical CV measurements at 1 MHz for all studied wafers, depicting a clear shift between wafer subjected to RTA and not.

We suspect that the dopant activation in the polycrystalline silicon electrode is not complete after Poly-Si deposition [4]. During the short RTA the active doping is estimated to be roughly doubled, partially leading to the observed shift of about 1.1 V . To support this theory, measurements were done after deposition of the doped polysilicon layer on the SiC process wafers and silicon dummy wafers via four-point probe measurement. The Rsh values extracted were about . The silicon dummy wafers were again measured after RTA processing, producing an of about . The same values were also calculated after electrical measurements of polysilicon meander structures on fully processed SiC wafers both with and without RTA. The entire origin of this large shift is still unclear.

The density of interface states/traps was extracted by both the Terman [5] (left) and high-low [6] (right) method for all four wafer and process splits, as shown in Fig. 4 and table 2.

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Fig 4. Interface trap density from the conduction band ( ) to 1.5 eV deep into the gap, evaluated with the Terman- (left) and High-Low- (right) method for both wafer types with and without exposure to RTA processing.

Fig 4. Interface trap density from the conduction band ( ) to 1.5 eV deep into the gap, evaluated with the Terman- (left) and High-Low- (right) method for both wafer types with and without exposure to RTA processing.

0.2 eV is suggested to be the limit of reliable value extraction this close to the conduction band edge . For this reason, table 2 displays values extracted from Fig. 4 at 0.25 eV (near Ec) and 1.5 eV (near mid-gap) to compare concentrations at the same energy level for all wafers. Extracted values for both Terman and high-low method lie in a narrow range for wafers A-D. It is noticeable that neither the wafer type (bulk and engineered SiC substrate) nor the RTA process has any significant influence on the density of interface states or traps.

Table 2. value comparison of both wafer types, with and without RTA, near the band gap ( 0.25 eV ) and near the mid-gap ( 1.5 eV ).

Dit [1/cm²/eV] | Band energy depth from conduction band (EC - E) [eV]
0.25 (near EC) | 1.5 (near mid-gap)
| Terman | QS/HF | Terman | QS/HF
A | 2.90·10¹¹ | 4.04·10¹¹ | - | noise (~ 1.0·10¹⁰)
B | 1.85·10¹¹ | 3.33·10¹¹ | - | noise (~ 1.0·10¹⁰)
C | 3.00·10¹¹ | 4.04·10¹¹ | - | noise (~ 1.0·10¹⁰)
D | 2.35·10¹¹ | 3.64·10¹¹ | - | noise (~ 1.0·10¹⁰)

To determine the yield and breakdown voltage, TZDB (time-zero dielectric breakdown) measurements up to a current compliance of 10 mA were performed at different temperatures. Fig. 5 depicts the current density over electric field for forty devices each of the wafers A (left) and C (right) at room temperature (RT), and , with the different values taken into account by the calculation of the electric field.

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Fig. 5. Current density over electric field in the oxide layer from TZDB-measurements for both wafer A (left) and C (right) on capacitors.

Fig. 5. Current density over electric field in the oxide layer from TZDB-measurements for both wafer A (left) and C (right) on capacitors.

Above the Fowler-Nordheim tunneling dominates the charge transport through the oxide and at about the kinks in the curve at RT and suggest the beginning of impact ionization due to hole injection at the gate electrode [8, 9]. At and this effect gets pushed to higher fields, not reached here, due to lattice vibrations [10]. When comparing exemplary curves of different wafer types as well as with and without RTA processing in Fig. 6, no noticeable differences can be noticed in the current density over electric field performance for RT nor for .

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Fig. 6. Current density over electric field comparison of wafers A, B, C, and D. The plot shows no significant diversions in behavior for the three wafers at the same temperature, proposing that neither the influence of the RTA, nor the wafer type affects the breakdown properties seen in TZDB measurements.

Fig. 6. Current density over electric field comparison of wafers A, B, C, and D. The plot shows no significant diversions in behavior for the three wafers at the same temperature, proposing that neither the influence of the RTA, nor the wafer type affects the breakdown properties seen in TZDB measurements.

Due to constraints in time and resource availability, high temperature TZDB and CCS-TDDB measurements on wafer D could not be conducted in the scope of this work. In terms of capacitor yield, no notable difference is seen between standard bulk wafer A and engineered SiC substrate wafer C. Wafer B, which has not seen the RTA process shows a significant B-mode (intermediate breakdown mode) failure rate, as shown in Fig. 7.

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Fig. 7. Weibull plot depicting the yield according to maximum electrical field reached during TZDB measurements on wafers , and C on capacitors. There seem to be a few earlier failures for wafer B , but no noticeable difference between A and C .

Fig. 7. Weibull plot depicting the yield according to maximum electrical field reached during TZDB measurements on wafers , and C on capacitors. There seem to be a few earlier failures for wafer B , but no noticeable difference between A and C .

For most sizes on all three wafers, over were reached during the TZDB measurement of 40 devices per size and wafer (Table 3). The failures on wafer B occur on the devices at RT and on both and capacitors at . This trend does not correlate with expectations relating a lower yield with larger device sizes induced by randomly distributed defects (such as crystal defects in the SiC) and could stem from processing issues or edge effects.

Table 3. Yield values for the test-pass-condition of over before reaching the current compliance for wafers , and C on three device sizes each.

Capacitor Size [mm²] | E > 10 MV/cm at RT | E > 10 MV/cm at 175 °C
| A | B | C | A | B | C
0.0316 | 100 % | 100 % | 100 % | 100 % | 100 % | 100 %
0.01 | 100 % | 83 % | 98 % | 100 % | 85 % | 100 %
0.00316 | 100 % | 100 % | 100 % | 100 % | 68 % | 100 %

When comparing the quality of gate oxides, not only TZDB, but also reliability focused measurement methods like time-dependent dielectric-breakdown (TDDB) are of great interest. To be able to confidently calculate the charges to breakdown ( ) for these wafers, the constant-current stress (CCS) TDDB was chosen. The CCS-TDDB was performed at RT and on three different capacitor sizes , and and four different current densities , and . Fig. 8 displays the Weibull plots of wafers A and B (left) and wafers A and C (right) for the three capacitor sizes each, measured at RT with an injected current density of . A clear shift in oxide lifetime is noticeable between A and B (the standard bulk wafers with and without RTA respectively). This significant reduction in reliability could be explained by the above-mentioned, but not fully understood, influence of the RTA and partially by its effect on the concentration of activated phosphorous ions inside the polycrystalline silicon gate electrode, by influencing the electric field at the gate/oxide interface and the carrier injection mechanism. The comparison of wafers A and C , the standard SiC wafer and engineered SiC substrate, on the left of Fig. 8 shows an overlapping of the intrinsic population for all device sizes independent on the wafer type. This leads to the conclusion, that there is no difference in oxide quality and reliability between these two wafers. The origin of the significantly better yield on wafer C (much lower extrinsic failure rate) is not identified yet.

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Fig. 8. Weibull plots of gate oxide lifetime after CCS-TDDB at RT with a current density of for wafers A and B (left) as well as wafers A and C , to investigate the influence of RTA processing and wafer type on the MOS reliability.

Fig. 8. Weibull plots of gate oxide lifetime after CCS-TDDB at RT with a current density of for wafers A and B (left) as well as wafers A and C , to investigate the influence of RTA processing and wafer type on the MOS reliability.

To validate the conclusions of the RT measurements above, Fig. 9 present results from CCS-TDDB with the same injected current density of but at . Consistent results are obtained, with a significant reduction of both the lifetime and the B -mode failures compared to RT .

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Fig. 9. Weibull plots of gate oxide lifetime after CCS-TDDB at at an injected current density of for wafers A and B (left) as well as wafers A and C (right).

Fig. 9. Weibull plots of gate oxide lifetime after CCS-TDDB at at an injected current density of for wafers A and B (left) as well as wafers A and C (right).

To evaluate the oxide lifetime of wafers , and C , an assessment of for each measurement condition is shown for the capacitors at a failure rate of . Fig. 10 displays over current density for both RT (left) and (right) and it can be noticed that the shift to shorter lifetimes in the Weibull plot for wafer B in comparison to A and C translated to a major reduction in of to , depending on temperature and injected current density.

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Fig. 10. over injected current density at both RT and displayed for devices for wafers , and C .

Fig. 10. over injected current density at both RT and displayed for devices for wafers , and C .

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1159.45.pdf

We conducted a thorough investigation of thermally grown gate oxide quality in terms of flat band voltage, interface states density, breakdown behavior and yield, as well as oxide reliability on both standard bulk and wafers. We concomitantly evaluated the impact of including, or not, an RTA step in the test capacitors fabrication process. Our results non-ambiguously lead to the following conclusions: (i) Gate oxides grown on standard bulk and SmartSiC wafers exhibit the same , failure rate, breakdown field and , whatever the injected current density or stress temperature. (ii) Skipping the RTA step in the test capacitors fabrication process induces a shift in flat-band voltage of over 1 V towards more positive voltages and a strong reduction in oxide lifetime as presented by CCS-TDDB measurements and analysis. This could be partially attributed to degradation of an incomplete dopant activation in the polycrystalline silicon gate but needs further investigating due to its importance for MOS-transistor processing. No impact was observed on the . The origin of the lower TZDB yield when skipping the RTA step or the lower extrinsic failure rate on SmartSiC™ at RT are not identified and could be process related.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1159.45.pdf

This work has been carried out within TRANSFORM project which has received funding from the Key Digital Technologies Joint Undertaking (KDT JU) under Grant Agreement No101007237. The JU receives support from the European Union's Horizon 2020 research and innovation program and Germany, France, Italy, Sweden, Austria, Czech Republic, Spain.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.45.pdf

E. Guiot et al., PCIM Europe 2022, 2022, pp. 1-7

E. Guiot et al., Materials Science Forum, Volume 1092, 2023, pp. 201-207

N. Daval et al., 6th IEEE Electron Devices Tech. & Manufacturing Conf., 2022, pp. 85-87

S. Kallel, Materials Science in Semiconductor Processing, Vol. 1, Iss. 3-4, 1998, pp. 299-302

L. M. Terman, Solid-State Electronics, Volume 5, Issue 5, 1962, pp. 285-299

R. Castagné, A. Vapaille, Surface Science, Volume 28, Issue 1, 1971, pp. 157-193

T. Kimoto, J. A. Cooper, Fundamentals of Silicon Carbide Tech., Wiley, 2014, pp. 225-228

H. L. R. Maddi et al., Energies, Volume 14, Issue 24, 2021

E. Efthymiou et al., Microelectronics Reliability, Volume 58, 2016, pp. 26-32

T. Kimoto, J. A. Cooper, Fundamentals of Silicon Carbide Tech., Wiley, 2014, pp. 418-419

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Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 55-59

doi: 10.4028/p-ItA5UL

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-15

Accepted:
2025-08-15

Online:
2025-09-09

Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

Shuzo Masui , Shotaro Kadoya , Satoru Takahashi , Masaki Michihata , Noboru Ohtani , Kozo Abe , Shunya Hirano , Shunsuke Arimura

The University of Tokyo, Dept. of Precision Engineering, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

Kwansei Gakuin University, School of Engineering, 1 Gakuen Uegahara, Sanda, Hyogo 669-1330, Japan

MAKINO Milling Machine Co., Ltd., Business Development of LASER Division 3-19 Nakane 2-chome, Meguro-ku, Tokyo, 152-8578, Japan

masui.s@nanolab.t.u-tokyo.ac.jp, shotarokadoya@gmail.com, takahashi@nanolab.t.u-tokyo.ac.jp, michihata@nanolab.t.u-tokyo.ac.jp, ohtani.noboru@kwansei.ac.jp, fnsmat_abekz@yahoo.co.jp, hiranosh@makino.co.jp, arimuras@makino.co.jp

*corresponding author

Keywords: wafer dicing, water jet guided laser, laser ablation, basal plane dislocations

Abstract

Low-process damage dicing technologies are required to improve the reliability of silicon carbide (SiC) devices. Existing methods, such as ultrasonic diamond blade dicing, dry laser dicing, and stealth dicing, introduce mechanical or thermal stresses that lead to cracks and dislocations, including basal plane dislocations (BPDs), which degrade device quality. In this study, we assess the crystalline defects induced by water jet guided laser (WGL) processing on a SiC wafer using X-ray topography (XRT) and investigate the underlying processing mechanisms through Energy Dispersive X-ray Spectroscopy (EDX). The asymmetric contrast observed along the processed grooves in the XRT images was due to the X-ray irradiation direction, and no significant BPD formation was observed. The EDX results showed that the processed surface was oxidized by laser ablation. Thus, WGL processing can provide damage-free dicing of SiC wafers with minimal mechanical stress and defects.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

In the silicon carbide ( SiC ) device manufacturing process, technological improvements have been made to reduce defects, especially basal plane dislocations (BPD) on the wafer surface. However, there has been little discussion about BPD on the cut surface of the diced SiC chips after device manufacturing. To ensure high reliability in the long-term use of power devices, damage-free dicing technology that avoids brittle fractures is essential. Conventional dicing methods such as ultrasonicassisted blade dicing, dry laser dicing, and stealth dicing have been employed to dice the hard and brittle SiC wafers . While these methods can effectively cut through SiC , they typically induce mechanical and/or thermal stresses that can lead to microcracks, chipping, and the formation of dislocations, such as basal plane dislocations (BPDs). In power devices, these defects are detrimental, as they can propagate during device operation, leading to performance degradation, reduced reliability, and ultimately device failure [4]. Therefore, developing a dicing method that minimizes or eliminates these defects is crucial for the industrial application of SiC wafers.

Among the various approaches explored to overcome these challenges, water-jet guided laser (WGL) processing has attracted attention as a promising alternative.

Water Jet Guided Laser Technology

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

WGL processing utilizes a fine water jet, on the order of tens of microns in diameter, to act as an optical waveguide for a pulsed laser beam (Fig. 1) [5]. The laser's optical energy is absorbed by the SiC wafer, resulting in material ablation, while the water jet simultaneously cools the material, mitigating thermal damage and reducing the introduction of mechanical stresses. Finally, the scanning water jet laser removes material from the top to the bottom of the wafer, non-mechanical WJGL dicing can be achieved without the need for cleaving. This dual-action mechanism makes WGL particularly effective for processing materials like SiC, where maintaining structural integrity is critical. Additionally, the water jet removes debris and prevents the redeposition of ablated material, further contributing to a cleaner dicing process with fewer defects.

[picture]

Fig. 1. Schematic illustration of WGL processing of a groove on a SiC wafer.

Fig. 1. Schematic illustration of WGL processing of a groove on a SiC wafer.

Progress of Research

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

Our previous study demonstrated that WGL processing can significantly reduce the incidence of chipping and BPDs compared to conventional blade dicing techniques. Although asymmetric dark and light contrasts were observed in X-ray topography (XRT) images along the WGL-processed grooves (Fig. 2), these contrasts were less severe than those typically observed with traditional methods, indicating that fewer or almost no BPDs were generated during the WGL process [6]. The asymmetric contrast pattern observed in XRT suggested the possibility of localized changes in crystal structure or the X-ray incident direction.

In this report, to elucidate the origin of this asymmetry and further validate the effectiveness of WGL processing, we conducted a more detailed investigation involving XRT from two opposing directions and energy-dispersive X-ray (EDX) analysis of cleaved wafer cross-sections. We present the results of these investigations, focusing on the underlying mechanisms that contribute to the observed contrast variations in XRT and their implications for the

[picture]

Fig. 2. Asymmetric contrast pattern observed in XRT image along WGL processed grooves on SiC wafer.

Fig. 2. Asymmetric contrast pattern observed in XRT image along WGL processed grooves on SiC wafer.

dicing process.

Methods and Results

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

Experimental condition of slit machining

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

Figure 1 shows a schematic diagram of a grooving experiment on a wafer using a WGL system (MCS300; Makino Milling Machine Co., Ltd.). The wafer was fixed on a glass base plate, the water pressure was 20 MPa , the assist gas (He) flowed at , and the distance between the nozzle and the wafer was . The laser irradiation conditions were a wavelength of 532 nm , pulse width of about 200 ns , pulse frequency of 10 kHz , and output power of . The water jet was scanned at the speed of 10-60 mm/s, which was almost same speed of the typical blead dicing method

XRT observation

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

To confirm whether BPDs are formed by WGL processing, SiC with grooves was measured using reflective XRT (XRTmicron, Rigaku). The pixel size is , and the XRT image is displayed in a negative tone. Therefore, crystal defects, strain, and BPDs appear dark. The contrast variation depending on the incident direction was clarified by comparing the reflected XRT images from the two opposing directions (11-28 and 1-128 reflection).

XRT images of WGL grooved wafers with opposite X-ray illumination are shown in Fig. 3. Some background BPDs were seen throughout the wafers as gray line contrasts. Although dark contrast can be seen on one side of the processed groove, the asymmetric contrast was swapped by reversing the incident direction.

[picture]

Fig. 3. XRT images with X-ray illumination from (a) right and (b) left sides.

Fig. 3. XRT images with X-ray illumination from (a) right and (b) left sides.

EDX analysis

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

The grooved wafer was cleaved parallel to the 2nd orientation flat. The processed SiC wafer was evaluated by scanning electron microscopy (SEM; JSM-6010LA, JEOL) and EDX analysis. Since the cross-section is composed of an ablation layer at the upper part and a bulk layer at the lower part, we performed mapping of the elemental distribution by area measurement. Furthermore, to clarify the crystal structure change of the ablation layer, we obtained quantitative elemental composition ratios at four locations #1-4 from the top to the bottom of the wafer.

[picture]

Fig. 4. Cross-sectional SEM images and EDX analysis of groove-processed SiC wafers.
(a) Schematic illustration of the cleavage of a grooved SiC wafer.
(b) SEM image. EDX results of (c) C, (d) Si, and (e) O.
Processing parameters are follows: 6 scans, , and 80 W .

Fig. 4. Cross-sectional SEM images and EDX analysis of groove-processed SiC wafers. (a) Schematic illustration of the cleavage of a grooved SiC wafer. (b) SEM image. EDX results of (c) C, (d) Si, and (e) O. Processing parameters are follows: 6 scans, , and 80 W .

[picture]

Fig. 5. Point EDX analysis of location #1-4.

Fig. 5. Point EDX analysis of location #1-4.

Next, to clarify the processed groove morphology and processing mechanism, SEM observation and EDX analysis were performed on the cross-section of the groove-processed SiC wafer, as shown in Fig. 4a. By observing the cross-section of the cleaved SiC wafer, the ablation layer was observed in the processed groove of depth (Fig. 4b). A 2D elemental maps shown in Fig. 4c-e were obtained from the ablation groove on the upper side to the lower the bulk SiC part. As shown in Figure 4c-e, carbon and silicon were observed equally in both areas, but oxygen was detected only in the processed area. Fig. 5 shows the point measurement of the EDX quantitative elemental analysis. The results show that carbon and silicon were approximately 59 and on the cleaved SiC surface (#4), and no oxygen was detected. On the grooved surface, carbon, silicon, and oxygen were , , and , respectively.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

The asymmetric contrast along the grooves were caused by the difference of the incident direction of X-rays. The contrast variation along the groove may be due to the surface texture and the crystal structure. Therefore, it is necessary to investigate the change in crystal structure using the following EDX analysis, among others. It should be emphasized that, excluding the background BPD, almost no BPD originating from the WGL groove can be confirmed.

According to the EDX result, three times more oxygen was detected in the upper #1 area than in lower #3 area. The results are also consistent with previous reports, such as the generation of and amorphous carbon through laser ablation of SiC [7]. This result suggests that the light contrast along the grooves observed in the XRT was caused by oxidation and graphitization of SiC during the laser ablation process. As a result, BPD-free groove processing can be performed by the WGL processing with laser ablation of the SiC substrate without mechanical stress.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

In this study, to verify the damage-free dicing of SiC wafers using the WGL process, the grooved SiC wafer was incident from two directions, the XRT images were analyzed, and the cleavage surface was subjected to EDX analysis to estimate the processing mechanism. As a result, BPD was hardly observed in the WGL grooves of SiC by XRT, and oxidation due to the laser ablation process was confirmed by EDX analysis. For future work, the processing conditions should be optimized regarding wafer damage and processing efficiency.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.55.pdf

Y.H. Wang et al., Proceedings of CSS MANTECH (Denver, Colorado, USA, 2014), 271-274.

E. Ohmura et al., J. Achiev. Mater. Manuf. Eng., 17, 381-384 (2006).

A. Bauer, H. Ryssel, Mater. Sci. Forum, 821-823, 528-532 (2014).

M. Skowronski et al., J. Appl. Phys. 99, 011101 (2006).

B. Richerzhagen, U. S. Patent No. 5, 902, 499 (11 May 1999).

S. Kadoya et al., Mater. Sci. Forum, 1124, 85-89 (2024).

Z. Zhai, et al., Appl. Surf. Sci., 502, 144131 (2024).

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The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 61-66

doi: 10.4028/p-Zdgj7m

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-04-30

Accepted:
2025-04-30

Online:
2025-09-09

Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

The original version of this paper is available on https://www.scientific.net/MSF.1159.61.pdf

Carsten Hellinger , Michael Thum and Mathias Rommel

Fraunhofer Institute of Integrated Systems and Device Technology (IISB)

Schottkystrasse 10, 91058 Erlangen, Germany

carsten.hellinger@iisb.fraunhofer.de, michael.thum@iisb.fraunhofer.de, mathias.rommel@iisb.fraunhofer.de

Keywords: Laser annealing, ohmic contact, structured contact, p-type, 4H-SiC

Abstract

In this work, a method is presented to form structured low-ohmic p-type contacts on Alimplanted by laser annealing. A metal layer sequence for p -type contacts suitable for UV laser treatment was developed. Furthermore, a method to protect thermosensitive layers from damages by laser treatment is presented. By structuring the top metallization layer, it is possible to use the metal stack as a self-aligned mask. That makes it possible to laser the entire surface of the wafer, whereby thermosensitive layers are protected from damages by laser annealing by utilizing the optical properties of the individual metal layers. To evaluate the method, TLM structures were electrically characterized. TLM structures were electrically characterized successfully demonstrating the feasibility of the presented approach.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.61.pdf

The ohmic contact between the metal contact layer and the semiconductor is of utmost importance for low power electronic devices [1]. Therefore, the fabrication of low ohmic contacts is one of the essential aspects in the manufacturing and development of highly energy efficient SiC power semiconductor devices, especially for vertical devices. For low p-type ohmic contacts on the frontside usually titanium-aluminum compounds are being used for p-type contacts [1,2,3]. A following temperature treatment of the metal layer is necessary for the titanium-aluminum layer to react with the SiC substrate. Thereby the semiconductor is formed, which results in a low-ohmic contact on p-type . This temperature step is generally performed by RTA (rapid thermal annealing) [1], although laser processing of full-surface n-type backside contacts is now established [6, 7, 8]. However, laser annealing for alloying structured frontside contacts is difficult. Either only the ohmic contact areas are annealed, which requires good alignment of metallized areas and laser processing, or the entire surface is annealed, which can lead to damage or degradation of the layers outside the contact area. Another challenge is the laser processing of the titanium-aluminum layer itself. According to literature, a commonly used metal stack for the fabrication of p-type contacts is , resulting in a layer after an annealing step [1]. However, aluminum has a reflectivity of over at a wavelength of 355 nm [9], which is the wavelength of commonly used short-pulse lasers [8]. As a result, only a small part of the laser radiation is absorbed and the metal layer hardly heats up. Therefore, a different layer composition or layer sequence must be used to produce p-type contacts using laser processing.

In this work, a solution was developed to produce structured ohmic contacts on p-type SiC using laser annealing. For this purpose, metal stacks were investigated for p-type contact formation by laser annealing. To characterize resulting contacts electrically, TLM structures were prepared, measured and analyzed.

Experimental

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TLM structures were manufactured on a commercial wafer with a n-type epitaxial layer of thickness and doping concentration. The layout of the TLM test structures is shown in fig. 1. Al was implanted in the area of the TLM structures (see fig. 1 with a surface
concentration of approx. 5E19 using three individual ion implantation steps (see table 1). To activate the dopants the wafers were subsequently annealed at for 30 minutes in Ar atmosphere.

[picture]

Fig. 1. TLM test structures in top view, where Z is the width and L the length of the TLM pattern, W the wide of the implanted tub and d the distance between the TLM pattern (dark grey: contact structures, light grey: -doped area).

Fig. 1. TLM test structures in top view, where Z is the width and L the length of the TLM pattern, W the wide of the implanted tub and d the distance between the TLM pattern (dark grey: contact structures, light grey: -doped area).

Table 1. Parameters of p-type implantation.

Energy [keV] | Dose [1/cm²]
90 | 2.8E14
60 | 1.8E14
30 | 1.4E14

Afterwards the metallization layer was deposited. Therefore, a stack of 20 nm Titanium and 75 nm Aluminum was evaporated and a photoresist was spin coated and structured, before the uppermost 20 nm Ni layer was deposited (see fig. 2). Then the uppermost Ni layer was structured by lift-off (see fig. 3a) and the whole wafer was laser annealed with different energy densities. Therefore a Sumitomo SWA20US-M laser annealing tool with a frequency-tripled Nd:YVO4 laser with 355 nm wavelength, a beam size of and a pulse duration of 50 ns was used. The energy density was varied from 1.4 to , whereby the overlap in x-direction was varied from 67 to and in y -direction from 50 to .

[picture]

Fig. 2. Process flow to produce TLM structures.

Fig. 2. Process flow to produce TLM structures.

Since the used stack has only a reflectivity of compared to Aluminum with over at 355 nm [9], significantly more radiation is absorbed in the ohmic contact areas with Ni layer on top, causing a reaction of the metal layers with the SiC substrate (see fig. 3b). In the area between the contacts, however, where aluminum is the top layer, most of the radiation is reflected and no reaction takes place until very high energy densities are being used for the laser annealing (see fig. 3b). After irradiation the non-reacted Al-Ti-layer between the ohmic contact areas was removed wet-chemically (see fig. 3c and fig. 4). Finally, a titanium and platinum layer is deposited and structured as contact metal.

[picture]

Fig. 3. Images of TLM structures after (a) lift-off, (b) laser annealing with different energy densities and overlaps and (c) wet chemical etching of unreacted Aluminum and Titanium.

Fig. 3. Images of TLM structures after (a) lift-off, (b) laser annealing with different energy densities and overlaps and (c) wet chemical etching of unreacted Aluminum and Titanium.

[picture]

Fig. 4. Microscope images of lasered TLM structures depending on energy densities after wet chemical etching of unreacted aluminum and titanium.

Fig. 4. Microscope images of lasered TLM structures depending on energy densities after wet chemical etching of unreacted aluminum and titanium.

[picture]

Fig. 5. Microscope images of lasered TLM structures depending on energy densities and laser spot overlap in x - and y-direction after wet chemical etching of unreacted aluminum and titanium.

Fig. 5. Microscope images of lasered TLM structures depending on energy densities and laser spot overlap in x - and y-direction after wet chemical etching of unreacted aluminum and titanium.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.61.pdf

The optical analysis of the samples (fig. 4 and 5) shows that the reflectivity of the aluminum layer is high enough at 355 nm wavelength for energy densities up to . The non-reacted metal can be completely removed after thermal treatment. For higher energy densities, the metallization between the TLM structures reacts with the silicon carbide substrate and could not be etched wetchemically. This means that the TLM patterns are short-circuited. For energy densities of 2.2 and it is noticeable that the lateral spread of the contacts is increased beyond the original contact length L after laser treatment (see fig. 4 and 5). For , the contacts up to apart and for the contacts up to apart are short-circuited. Also, for a lateral spread can be seen in fig. 4. This observation and the associated reduction in the distance between the TLM patterns must be considered when evaluating the I(V) characteristics. Fig. 6 exemplary shows the resistance as a function of the distance between the TLM patterns for different energy densities and a linear fit. Only the non-short-circuited TLM patterns were used for the evaluation and the distance between the TLM patterns was corrected according to the lateral spread. The fit line shows a high coefficient of determination. It can be used to calculate the sheet resistance and the specific contact resistance.

[picture]

Fig. 6. R(d) plot for an exemplary TLM test structure as a function of energy density.

Fig. 6. R(d) plot for an exemplary TLM test structure as a function of energy density.

Fig. 7 shows the specific contact resistivity and sheet resistance for different energy densities. The sheet resistance depends on the dopant concentration [11]. Since all test structures were produced according to the implantation values in table 1, the sheet resistance should be independent of the energy densities during the laser treatment. Due to the significantly large lateral spread, only the values for energy densities lower than are plotted. The specific contact resistivity shows the lowest values with for 1.9 and for in average. At , the energy density does not appear to be high enough to produce low-resistance contacts as the average specific contact resistivity is . For , the average specific contact resistivity is and is more than eight times higher than for . At the same time, the test structures with have significantly higher standard errors. Due to the manual insertion of the wafer into the laser tool, it is possible that the transitions between the sectors with and do not correspond exactly to the mask layout, whereby structures in the transition were processed with the surrounding energy densities (see fig. 5) and consequently falsify the measurement results.

[picture]

Fig. 7. Determined specific contact resistivity and sheet resistance depending on energy density.

Fig. 7. Determined specific contact resistivity and sheet resistance depending on energy density.

To further narrow down the process window for the laser parameters and metal stack thicknesses to optimize the specific contact resistance, further tests are necessary. To find out which reaction products, i.e. and compounds, are responsible for the ohmic contact formation additional XRD and TEM analyses are essential.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.61.pdf

In this work, titanium-based ohmic contacts were produced on p-doped using a UV short pulse laser. Due to the optical properties of the commonly used metal stack a novel Ni ( 20 nm / Al / Ti stack optimized for UV lasers was used, whereby the Ni layer was structured by lift-off. The use of the structured metal stack as a self-aligned mask makes it possible to laser the entire surface of the wafer, whereby thermosensitive layers are protected from damages by laser annealing by utilizing the high reflectivity of the top Al layer, where the Ni was removed. With this method contact pads with a size between and could be realized. It was shown that structured contacts with a specific contact resistance of for and for on average on p-doped 4 H -SiC could be produced using this method.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.61.pdf

T. Kimoto and J. Cooper. Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, IEEE Press, Wiley, Singapore (2014).

F. Roccaforte et al. Critical issues for interfaces to p-type SiC and GaN in power devices. Appl. Surface Science 258, 2012

T. Abi-Tannous et al. A Study on the Temperature of Ohmic Contact to p-type SiC based on Phase. IEEE Transactions on Electron Devices 63, 2016

M. Gao et al. Role of Interface Layers and Localized States in TiAl-based Ohmic Contacts to ptype . Journal of Electronic Materials 36, 2007

C.A. Fisher and M.R. Jennings. On the Schottky Barrier Height Lowering Effect of in Ohmic Contacts to p-type 4H-SiC. International Journal of Fundamental Physical Sciences, 2014

R. Rupp, R. Kern and R. Gerlach. Laser backside contact annealing of SiC Power devices: A Prerequisite for SiC thin wafer technology. Kanazawa, Japan: Wiley IEEE, IEEE Xplore, 2014

O. Rusch et al. Reducing On-Resistance for SiC Diodes by Thin Wafer and Laser Anneal Technology, Material Science Forum 1004 (2020).

G. Li et al. Fabrication of Ohmic Contact on N-Type SiC by Laser Annealed Process: A Review, Crystals 13(7):1106 (2023)

A. D. Rakić. Algorithm for the determination of intrinsic optical constants of metal films: application to aluminum, Appl. Opt. 34, 4755-4767 (1995).

A. D. Rakić, A. B. Djurišic, J. M. Elazar and M. L. Majewski. Optical properties of metallic films for vertical-cavity optoelectronic devices, Appl. Opt. 37, 5271-5283 (1998).

D. K. Schroder. Semiconductor material and device characterization. Wiley-Interscience IEEE Press, Hoboken, N.J, Piscataway, NJ, (2006)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 67-72

doi: 10.4028/p-xm5gzM

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-02-12

Accepted:
2025-03-10

Online:
2025-09-09

Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

Takanori Amamiya , Masayuki Yamamoto , Hitoshi Umezawa , Koji Nakayama , Takeharu Kuroiwa , Shin-Ichiro Kuroki , Yasunori Tanaka

Advanced Power Electronics Research Center (ADPERC), AIST, Japan

Department of Electrical and Electronic Engineering, University of Yamanashi, Japan

Research Institute for Semiconductor Engineering, Hiroshima University, Japan

at.amamiya@aist.go.jp, byamamoto.masayuki@aist.go.jp, chitoshi.umezawa@aist.go.jp

koji.nakayama@aist.go.jp, kuroiwa.takeharu@aist.go.jp, skuroki@hiroshima-u.ac.jp, yasunori-tanaka@aist.go.jp

Keywords: Silicon Carbide (SiC), Gate-all-around (GAA), JFET, common-source amplifier, harsh environment

Abstract

Currently, silicon carbide ( SiC ) is widely recognized as a wide bandgap semiconductor, with expanding applications in harsh environments, such as high temperature and radiation exposure. In this study, we fabricated a planar structure gate-all-around junction field-effect transistor (JFET), wherein the channel region is formed through ion implantation at varying doses. We successfully produced both normally-on and normally-off JFETs. Moreover, we constructed a JFET common source amplifier. The amplifiers achieved a maximum gain of -226.7 ( 47.1 dB ) at a supply voltage of .

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

At present, siliocon carbide ( SiC ) is known as a leading wide bandgap semiconductor material because of its high tolerance to harsh environments, such as high temperature and radiation [1]. Realizing SiC integrated circuits (ICs), such as operational amplifiers, will enable devices based on SiC ICs to operate in harsh environments. Currently, four types of SiC transistors are mainly studied: bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), metal-oxidesemiconductor field-effect transistors (MOSFETs), and metal-semiconductor field-effect transistors (MESFETs) [2-10]. The advantage of SiC JFETs is that they have no gate oxide layer. It has been reported that gate oxide layers can be easily degraded by radiation [11]; therefore, SiC JFETs are preferable to SiC MOSFETs in radiation environments. Meanwhile, SiC MESFETs have an inadequate interface contact between the N-channel and P-type buried back gate layer, which causes backgating [10]. For these reasons, SiC JFETs are likely the prime choice for SiC ICs operating in harsh environments. Recently, not only n-type but also p-type SiC JFETs have been demonstrated [12].

Increasing channel density is beneficial for enhancing device performance [13]. However, it raises the pinch-off voltage, leading to higher power consumption in ICs due to the need for elevated supply voltages. Therefore, to fabricate the gate region, double-gate and gate-all-around (GAA) structures are preferable to single-gate structures because a lower pinch-off voltage is suitable for the same channel density. Recently, we developed a SiC JFET featuring a GAA design, which theoretically optimizes transconductance [14]. In the design, fabricating the bottom layer required extremely high-energy ion implantation, such as 3 MeV , and oblique ion implantation after gate trench etching, making unconventional processes significantly challenging.

To overcome these challenges, we propose and evaluate the characteristics of a JFET with a new planar GAA structure. In this design, the gate region is fabricated by ion implantation at varying doses without the need for such high-energy implantation. In addition, two types of JFETs, normally- on and normally-off JFETs, can be customized by varying the dose amount. Further, we
constructed a common-source amplifier as a simple electronic circuit using the JFETs and assessed the maximum voltage gain.

[picture]

Fig. 1. (a) Top and (b) cross-sectional schematics of the planar n-type SiC GAA JFET. Five n-type channel stripes (orange) are embedded beneath the source/drain (dark orange) and gate top (blue) regions in the n - epitaxial layer (light yellow). The gate length and width are and , respectively. The device is isolated by trenches around it.

Fig. 1. (a) Top and (b) cross-sectional schematics of the planar n-type SiC GAA JFET. Five n-type channel stripes (orange) are embedded beneath the source/drain (dark orange) and gate top (blue) regions in the n - epitaxial layer (light yellow). The gate length and width are and , respectively. The device is isolated by trenches around it.

Device Fabrication

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Fig.1(a) and (b) show the top and cross-sectional schematics of the proposed JFET, respectively. Five n -type channel stripes are embedded beneath the source/drain and gate top regions in the n - epitaxial layer. The n-type channels (width: ) are separated by the gate side region ( ). The gate length and width are and , respectively. The margin between the p+ gate and source/drain regions is , and the width of the contact holes is . The device is isolated by trenches (width: , depth: ) around it.

First, the gate bottom region is firstly formed by Al-ion implantation into the entire epitaxial layer ( ) grown on a -SiC wafer. The n -type channels, source/drain, gate side, gate top regions are then formed. We use six channel doses ( , 1.4, 1.6, and ) to control the gate threshold voltage. When the channel dose is , the target channel density is approximately .

After device isolation by SiC trench etching, we performed activation annealing , 10 min .). Ni contact metal is deposited on both sides of the wafer and sintered at 500 . The device fabrication is completed by attaching a thick Al electrode on the surface side while the back side is covered with Ti, Ni, and Au layers.

IV-Characteristics of JFET

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We fabricated two types of JFETs: normally-on and normally-off JFETs, by varying the channel dose amount. These are fabricated on two wafers, named 10 SY and 11 SY . For 10SY, three channel doses , and , were selected to achieve normally-off operation; meanwhile, for 11SY, , and were chosen to achieve normally-on operation. The device characteristics were measured with Semiconductor Parameter Analyzer Agilent 4156C. Fig. 2 shows an optical microscope image of an actual GAA JFET being measured using a manual prober. The substrate is connected to GND. The transfer and output characteristics were measured for the six doses. For the transfer characteristics, was set to 10 V and was swept from -7.5 to 2.5 while measuring . For the output characteristics, for each dose, was varied from 0 to 2 V for normally-off and from -3 to 2 V for normally-on in steps of 1 V while was swept from 0 to 20 to measure .

[picture]

Fig. 2. Optical microscope of actual SiC GAA JFETs.

Fig. 2. Optical microscope of actual SiC GAA JFETs.

Fig. 3 illustrates the characteristics of JFETs. Fig. 3 (a) shows the transfer characteristics of JFETs with different channel doses, indicating a shift in the gate-threshold voltage from 2.11 to - 3.76 V as the channel dose increases from to , and Fig. 3 (b) shows the logarithmic plot of the transfer characteristics of JFETs with different channel doses. As the channel dose amounts increases, the threshold voltage shifts toward negative values.

Figs. 3 (c) and (d) display the output characteristics of the normally-off JFET with a channel dose of and the normally-on JFET with a channel dose of , where the drain current in the saturation region remains nearly constant across the drain-source voltage . The device parameters are listed in Table 1. The drain current was measured for the normally-off and normally-on JFETs when and , respectively. and are calculated when and

Large-Signal Behaviors of JFET Common-Source Amplifier and Source Follower

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To test the fabricated JFETs, simple circuits - a common-source amplifier and a sourcefollower amplifier - were constructed and tested. The circuit diagrams are shown in Fig. 4 (a) and Fig. 5 (a). Fig. 4 (a) is a common-source amplifier and Fig. 5 (a) is a source-follower circuit. This measurement is also conducted using Semiconductor Parameter Analyzer Agilent 4156C. In the measurement of the common-source amplifier, was set to 10,20 , and 30 V with swept from -2 to 2 V while the corresponding output was measured. Similarly, for the source-follower amplifier, was swept from -2 V to the maximum under the same settings while the output was recorded.

Fig. 4 (b) shows the output voltage of the common-source amplifier under large-signal analysis. As verified in the figure, turns off when reaches 0 V , as expected. The maximum gain of the amplifier around was calculated, resulting in values of , and for , and 30 V , respectively. The gain can be determined using , calculated from the slope of the I/O characteristics. In Fig. 5 (b), the output voltage Vout of the source-follower amplifier is shown. The circuit's correct operation is confirmed by the manner the output rises in response to the input, effectively following it.

[picture]

Fig. 3. (a) Transfer characteristics of normally-on and normally-off JFETs per channel dose when . (b) Logarithmic plot of transfer characteristics of normally-on and normally-off JFETs per channel dose amounts when . The color legend is the same as in (a). (c) Output characteristics of normally-off JFET for gate-source voltages ( ) of 0,1 , and 2 V . The channel dose is . (d) Output characteristics of normally-on JFET for gate-source voltage steps from -3 V to 2 V in increments of 1 V . The channel dose is .

Fig. 3. (a) Transfer characteristics of normally-on and normally-off JFETs per channel dose when . (b) Logarithmic plot of transfer characteristics of normally-on and normally-off JFETs per channel dose amounts when . The color legend is the same as in (a). (c) Output characteristics of normally-off JFET for gate-source voltages ( ) of 0,1 , and 2 V . The channel dose is . (d) Output characteristics of normally-on JFET for gate-source voltage steps from -3 V to 2 V in increments of 1 V . The channel dose is .

Summary

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In this study, normally-on and normally-off JFETs with a planar GAA structure were fabricated and demonstrated. By varying the channel dose, we successfully produced both types of JFETs. Their characteristics were measured using the Semiconductor Parameter Analyzer Agilent 4156C. In addition, simple electronic circuits, including a common-source amplifier and a source-follower amplifier, were constructed and tested using the JFETs. The maximum gains of the amplifiers near was found to be , and for , and 30 V , respectively.

Table 1. Device parameters per varied dose.

Dose [cm⁻²] | ID [μA] | r₀ [MΩ] | gm [μS] | Av = r₀gm
1.0 × 10¹³ | 1.98 | 110 | 6.10 | 671
1.2 × 10¹³ | 10.0 | 23.8 | 14.8 | 352
1.4 × 10¹³ | 2.78 | 192 | 6.06 | 1164
1.6 × 10¹³ | 16.1 | 22.5 | 17.1 | 385
1.8 × 10¹³ | 45.0 | 6.79 | 29.6 | 201

[picture]

Fig. 4. (a) Common-source amplifier circuit diagram and (b) transfer characteristics of the common source amplifier. In the circuits, normally-on JFET devices are used, where the typical resistor is replaced by shorting the JFET's source and gate. The maximum gain around was observed at , and 30 V .

Fig. 4. (a) Common-source amplifier circuit diagram and (b) transfer characteristics of the common source amplifier. In the circuits, normally-on JFET devices are used, where the typical resistor is replaced by shorting the JFET's source and gate. The maximum gain around was observed at , and 30 V .

[picture]

Fig. 5. (a) Source-follower amplifier diagram and (b) transfer charactristics of the source-follower amplifier circuit.

Fig. 5. (a) Source-follower amplifier diagram and (b) transfer charactristics of the source-follower amplifier circuit.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

This work was partially supported by MEXT Initiative to Establish Next-generation Novel Integrated Circuits Centers (X-NICS) Grant Number JPJ011438, the commissioned research fund provided by F-REI, and JSPS KAKENHI (S), Grant Number JP24H00035.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.67.pdf

P. G. Neudeck et. al.: Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions, IEEE J-EDS, vol.7, pp.100-110 (2019)

M. Shakir et. al.: Towards silicon carbide VLSI circuits for extreme environment applications, Electronics, vol. 8, no. 5, p. 496 (2019)

A. Takeyama et. al.: Threshold voltage instability and hysteresis in gamma-rays irradiated junction field effect transistors, J. Appl. Phys. 131, 244503-1 -244503-8 (2022)

M. J. Krasowski and P. G. Neudeck: Practical SiC JFET-R analog integrated circuit design for extreme environment applications, NASA Technical Memorandum E-19934 (2021)

Vuong Van Cuong et. al.: Amplifier Based on 4H-SiC MOSFET Operation at for Harsh Environment Applications, IEEE Trans. Electron Devices, 69(8), 4194-4199(2022) DOI: 10.1109/TED.2022.3184663

S-I. Kuroki et. al.: Characterization of nMOSFETs in Harsh Environments, HighTemperature and High Gamma-Ray Radiation, Mat. Sci. Forum, 858, pp864-867 (2016)

M. Barlow et. al.: An integrated SiC CMOS gate driver for power module integration, IEEE Transactions on Power Electronics, vol. 34, no. 11, pp. 11191-11198 (2019)

M. Ekström, B. G. Malm, and C.-M. Zetterling: High-temperature recessed channel SiC CMOS inverters and ring oscillators, IEEE Electron Device Letters, vol. 40, no. 5, pp. 670673 (2019)

M. Okamoto et. al.: First demonstration of a monolithic SiC power IC integrating a vertical MOS- FET with a CMOS gate buffer, 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), pp. 71-74 (2021)

M.Tomana et. al.: A hybrid silicon carbide differential amplifier for 350 degrees C operation, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, no. 5, pp. 536-542 (1993)

T. R. Oldham and F. B. McLean: Total ionizing dose effects in MOS oxides and devices, IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 483-499 (2003)

M. Nakajima, M. Kaneko, and T. Kimoto: Normally-off Operation of n- and p-JFETs With a Side-Gate Structure Fabricated by Ion Implantation Into a High-Purity Semi-Insulating SiC Substrate, IEEE Electron Device Letters, vol. 40, no. 6 (2019)

Pak, Amin and Orouji, Ali A.: A novel high performance LDMOS transistor with high channel density, Journal of Computational Electronics, vol. 17, pp 217-223 (2018)

M. Mochizuki et. al.: Fabrication of the SiC Gate-All-Around JFET, IEEE T-ED, vol.70, pp.4612-4617 (2023)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 73-79

doi: 10.4028/p-H74nVN

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-19

Revised:
2025-02-27

Accepted:
2025-02-28

Online:
2025-09-09

Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

The original version of this paper is available on https://www.scientific.net/MSF.1159.73.pdf

Johannes Ziegler , Dick Scholten , Holger Bartolf , Andrii Voznyi , Patrick Rabinzohn and Jörg Schulze

Robert Bosch GmbH, Mobility Electronics, 72762 Reutlingen, Germany

Robert Bosch GmbH, Corporate Research, 71272 Renningen, Germany

Beneq Oy, 02200 Espoo, Finland

Fraunhofer IISB, 91508 Erlangen, Germany

Chair of Electron Devices (LEB), FAU Erlangen-Nürnberg, 91508 Erlangen, Germany

ajohannes.ziegler2@de.bosch.com, dick.scholten@de.bosch.com, holger.bartolf@de.bosch.com,

Abstract

In this paper, we investigate the electrical and structural characteristics of -based high- gate dielectrics, which were integrated into a gate-first, high-temperature manufacturing process having comparable thermal budget as needed in metal-oxide-semiconductor fieldeffect transistor (MOSFET) production. MOS capacitors were chosen as test devices to examine the electrical performance in terms of current-voltage ( ) and capacitance-voltage ( ) behavior. Remarkably, even after processing temperatures of up to for ohmic contact formation, the layers revealed highly uniform breakdown characteristics, low hysteresis and a flat-band voltage ( ) that closely aligns with the theoretical value. Time-dependent dielectric breakdown (TDDB) measurements of the MOS capacitors, however, showed a clear reliability disadvantage concerning the intrinsic dielectric lifetime when comparing with the counterpart from commercial SiC production. Finally, to better understand the electrical behavior, transmission electron microscopy (TEM) analysis was conducted, pointing out that high-temperature processing causes the films to transition from an amorphous state to an ordered, polycrystalline structure.

Introduction

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Even though the SiC power MOSFET is an established product by now, there is still plenty of room for improving the transistor's performance. To exploit the full potential of the superior material properties of SiC, namely the low drift zone resistance due to the high breakdown field strength, other series resistance contributions, such as the channel resistance, must be kept as small as possible. Despite the continuous progress in improving the interface and therefore the channel mobility, the channel contribution to the overall on-state resistance ( ) remains considerable for most of the SiC power MOSFET products [1].

An innovative approach to minimize the channel contribution is to utilize high- insulators as gate dielectric material. Due to their higher dielectric constant, the induced inversion charge is increased for the same applied voltage, leading to a reduced channel resistance. Furthermore, most of the high- dielectrics are deposited by using an atomic layer deposition (ALD) process, which is known for precise thickness control, high uniformity, conformality and reproducibility and offers unique possibilities for in-situ interfacial engineering.

However, there are still major challenges, which complicate the integration of these dielectrics into commercially available SiC power MOSFETs. One of them is the relatively low thermal stability of the commonly used high- materials. During typical SiC power MOSFET production, temperatures up to are needed for ohmic contact formation. Moreover, compatibility with poly-Si gate electrode formation must be ensured. According to literature, these processes often lead
to crystallization of the high- layers, hampering their usage as gate dielectric due to inacceptable leakage currents and reliability issues [2].

In this work, we study the influence of the typical high-temperature processes on the electrical characteristics of poly-Si gated, -based MOS capacitors. We have chosen as the main gate dielectric material due to the relatively high thermal stability as well as the large conduction and valence band-offsets to . We modified the interfacial properties by using gate dielectric stacks, consisting of thin interfacial layers ( and AlN ), followed by subsequent deposition.

Experimental Details

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Device Fabrication. The MOS capacitors characterized in this work were fabricated on epitaxial n-type layers, grown on conventional -off axis ( 0001 ) 4 H -SiC 6 " substrates. The fabrication, except the gate dielectric depositions, took place in the corporate research cleanroom of the Robert Bosch GmbH . A schematic cross-section of the devices as well as the processing sequence including the applied thermal budget is shown in Fig. 1.

Prior to the gate dielectric deposition, the SiC wafers were cleaned and subsequently etched in a diluted HF acid solution to remove any oxidized surface species. Right after, the -based gate dielectric layers and stacks were deposited according to the wafer overview in Fig. 1 using ALD technology from Beneq TFS 200 R&D. For selected wafers, the interfacial properties were modified by depositing a 5 nm layer of either plasma-enhanced ALD (PEALD) or PEALD AlN prior to the deposition. The films of all samples were grown by means of thermal ALD using trimethylaluminium (TMA) and as precursors. For PEALD AIN, TMA and a plasma mixture of and was utilized. In the case of growth, Bis(diethylamino)silane and plasma were employed as precursors. The process temperature for all depositions was maintained at to ensure the production of high-purity films.

[picture]

Fig. 1. Process flow including the corresponding thermal budget, cross-section and wafer overview of the fabricated -based MOS capacitors.

Fig. 1. Process flow including the corresponding thermal budget, cross-section and wafer overview of the fabricated -based MOS capacitors.

Except for the ALD process, all three wafers underwent exactly the same fabrication process. After post deposition annealing (PDA) in ambient at for 30 min , in-situ P -doped poly-Si was deposited by means of low-pressure chemical vapor deposition (LPCVD) to form the gate electrode layer. Subsequently, a reactive ion etching (RIE) process was used to structure the poly-Si layer, followed by encapsulating the MOS stack in a high-temperature oxide (HTO), deposited via LPCVD at elevated temperature to enhance the deposition rate. This additional layer was primarily applied to attenuate the electric field strength at the edges of the poly-Si pads to make the MOS capacitor devices suitable for reliable TDDB measurements.

Forming the backside ohmic contact consists of sputter deposition of a thin Ni layer, combined with a rapid thermal annealing (RTA) process at for 3 min afterwards. Finally, the Al pads were formed on the frontside and backside to contact the MOS capacitor devices during electrical characterization. As the overall applied thermal budget is comparable to SiC MOSFET fabrication, the obtained electrical results are expected to be transferable to transistor devices.

Electrical Characterization. The fabricated MOS capacitor devices were electrically characterized in a Cascade Microtech probe station equipped with different measurement instruments. For I-V breakdown characteristics as well as constant voltage TDDB measurements, a Keithley 2636 sourcemeter was connected to the MOS devices. Quasi-static measurements were conducted by using a measurement setup consisting of a Keithley 6517 electrometer and a Keithley 2010 multimeter. In this configuration, the electrometer was used to measure the charge on the gate electrode while the applied, stairs-like voltage profile was traced with the additional multimeter.

Structural Characterization. To investigate the atomic structure of the gate dielectrics after hightemperature processing, TEM analysis was carried out in a Thermo Fisher Scientific Talos F200X equipment. All inspections were performed using an acceleration voltage of 200 kV . Electron diffraction patterns of the SiC crystal were taken to align the samples accordingly.

Results and Discussion

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For precise evaluation of the device parameters, the final thickness of the gate dielectric layer after the fabrication process is needed. Therefore, we made TEM images of the samples, as shown in Fig. 2 a)-c). For all three samples, the ALD gate dielectrics got densified during MOS capacitor device fabrication, leading to an overall thickness decrease of approximately . Similar behavior was already observed previously when annealing layers under high temperatures [3].

[picture]

Fig. 2. TEM overview images of a) sample , b) sample and c) sample . The shown thickness values are averaged by using several measurements at different positions of one MOS capacitor from the middle of each wafer.

Fig. 2. TEM overview images of a) sample , b) sample and c) sample . The shown thickness values are averaged by using several measurements at different positions of one MOS capacitor from the middle of each wafer.

Electrical Results. Fig. 3 a) shows the - breakdown measurements, which were conducted for numerous MOS capacitor devices per sample in a cross-shape over the whole wafer. Interestingly, samples 1 and 3 show a high uniformity and a Fowler-Nordheim-shaped current increase with an average breakdown field strength of around , whereas sample 2 depicts a much higher spread including premature breakdowns. Comparing all three samples, the only notable difference is the interfacial material in direct contact to the underlying SiC. Accordingly, the results indicate that this interfacial layer is crucial, impacting not only the interface trap density, but also the current blocking capability of the layer.

Besides the analysis, quasi-static measurements were performed. The corresponding results are shown in Fig. 3 b) for five different devices per wafer. The gate voltage was swept between +7 V and -7 V to stay below the dielectric breakdown of sample 2. Especially in terms of accumulation capacitance, flat-band voltage and hysteresis , a clear difference between the samples is observed. Sample 1 exhibits the highest accumulation capacitance, whereas the value gradually decreases from sample 3 to sample 2 owing to the lower dielectric constant 8 r of the interfacial AlN and layer with respect to the . Together with the thickness data of Fig. 2 a), measuring the accumulation capacitance of sample 1 allows the r extraction of the layer. The resulting value of is comparably high and may be attributed to a crystallization of the layer during the high-temperature processes of the fabrication sequence [4].

[picture]

Fig. 3. a) breakdown measurements for MOS capacitors distributed in a cross-shape over the whole wafer, b) quasi-static measurements for five devices per wafer in up- and down-sweep direction.

Fig. 3. a) breakdown measurements for MOS capacitors distributed in a cross-shape over the whole wafer, b) quasi-static measurements for five devices per wafer in up- and down-sweep direction.

Nevertheless, especially sample 1 without an intentionally modified interface reveals promising - characteristics with low hysteresis and a value that closely approximates the theoretical value of a poly-Si gated dielectric on SiC . All extracted parameters from Fig. 3 a) and b) are summarized in Table 1. Compared to published analysis on gate dielectrics on SiC [5], the results are notably promising, especially when taking the high thermal load into account, which the devices experienced during the fabrication process. Processing at such high thermal budgets typically leads to crystallization of the layers, accompanied by deteriorated electrical characteristics, such as high leakage currents [6] and/or a large shift in [7].

Table 1. Summary of the sample parameters breakdown field strength , flat-band voltage in both sweep directions and and hysteresis at the flat-band capacitance. Values are averaged and given with the respective standard deviation. for sample 2 is not listed due to the high spread of values across the wafer.

| Sample 1 | Sample 2 | Sample 3
EBD (MV/cm) | 7.13 ± 0.08 | - | 6.97 ± 0.08
VFB,low (V) | -0.36 ± 0.03 | 0.64 ± 0.02 | -3.32 ± 0.01
VFB,high (V) | 0.34 ± 0.01 | 1.46 ± 0.01 | -1.72 ± 0.01
ΔVFB = VFB,high - VFB,low (V) | 0.71 ± 0.03 | 0.82 ± 0.02 | 1.60 ± 0.01

Due to the excellent uniformity of the results, constant voltage TDDB measurements at three different temperatures were carried out for MOS capacitors of sample 1. The corresponding results are shown in Fig. 4. In Fig. 4 a), measurements of different devices at stress voltages between 12 V and 17 V and a temperature of are plotted in a double-logarithmic Weibull plot. As the time to dielectric breakdown increases exponentially with lowering the applied gate voltage, we showed only for one voltage ( 13 V ), that stressing of 62 instead of nine devices ends up in the same Weibull slope of the intrinsic failure branch. Therefore, we conclude that a lower statistic is sufficient to obtain a reliable lifetime estimation.

To get a prognosis of the intrinsic lifetime at typical operation conditions, the values, at which of the devices broke ( lifetime), were extracted out of Fig. 4 a) and used for the lifetime extrapolation shown in Fig. 4 b). When comparing the lifetime of different gate dielectrics, it is mandatory to consider variations in the oxide thickness as well as the value. Therefore, the lifetime is plotted over the electric displacement field strength , which can be calculated by using the following expression.

The -field value thereby describes the charge carrier density at the oxide semiconductor interface and allows for a fair comparison between the gate dielectric of sample 1 and the counterpart, used in commercial SiC production. The extracted values at different stress voltages and temperatures are extrapolated to a -field of , which represents a typical on-state condition when assuming a gate dielectric in SiC MOSFET technology. The estimated intrinsic lifetime at and a stressing temperature of yields values in the range of years, which is orders of magnitude below the counterpart [8]. Nevertheless, the conducted measurements are highly consistent and scale perfectly with temperature, as shown in the inset of Fig. 4 b).

Especially due to the large number of extrinsic defects in SiC technology, the lifetime should lie well above the typical operation lifetime to ensure the reliability requirements for automotive applications [8]. The typical operation lifetime in on-state is represented by the red star in Fig. 4 b). The comparably lower projected lifetime of the , therefore, leads to a reduced "safety margin" with respect to a typical operation lifetime of a SiC MOSFET.

[picture]

Fig. 4. a) Weibull plot for constant voltage TDDB measurements of sample 1 at , b) extracted and extrapolated lifetime over -field strength for sample 1 as well as a comparison with the published values of a gate oxide on planar [8].

Fig. 4. a) Weibull plot for constant voltage TDDB measurements of sample 1 at , b) extracted and extrapolated lifetime over -field strength for sample 1 as well as a comparison with the published values of a gate oxide on planar [8].

The integration of -based high- dielectrics into SiC MOSFETs, used for automotive application, would require additional effort to improve the TDDB behavior of these layers. Therefore, it is crucial to understand the reason behind the above-mentioned lifetime issue. Previously, the effect of the PDA temperature on the reliability of dielectrics on GaN was investigated [9]. The published results show that the transition from an amorphous to a crystalline structure by hightemperature annealing comes along with a decrease in reliability. To check whether a similar phenomenon could explain our results, we performed TEM analysis for all three samples.

Structural Results. Exemplary high-resolution TEM images of sample 1 with different magnification are shown in Fig. 5. The atomic arrangement within the layer clearly points out that crystallization happened during the MOS capacitor fabrication process. The fast Fourier transformation (FFT) pattern, represented in the inset of Fig. 5 c ), supports this observation. Besides the contributions of the SiC substrate, the FFT pattern contains extra reflections, which are attributed to the crystallized film. Furthermore, polycrystalline grains and defects are visible. These nonidealities potentially promote the formation of leakage paths, that lead to a comparably low lifetime of the gate dielectrics.

As a result of the crystallization process, the atoms inside the film rearrange, causing mechanical stress on the underlying SiC substrate. The effect of the stress potentially shows up in the strain fields, which are observed in Fig. 5 a) at the interface inside the semiconductor.

[picture]

Fig. 5. High-resolution TEM images of sample 1 with increasing magnification from a) to c).

Fig. 5. High-resolution TEM images of sample 1 with increasing magnification from a) to c).

Comparing the thermal budget of the fabrication process used in this work with published results regarding the annealing of layers on SiC , it is not surprising that crystallization happened during processing. Typically, the crystallization temperature of is reported to lie around 800 [10]. Especially the ohmic contact annealing and the insulation layer deposition process clearly exceeded this temperature (comp. Fig. 1). Additionally, several studies revealed an unintentional formation of a thin layer at the boundary between and SiC due to an interfacial reaction during high-temperature annealing [11,12]. Such an interfacial , however, could not be observed in our studies.

The TEM investigations of samples 2 and 3 showed similar observations in terms of crystallization and strain fields. Therefore, only TEM images at higher magnification are shown in Fig. 6. As expected, the interlayer of sample 2 in Fig. 6 a) is still amorphous, whereas the AlN interlayer of sample 3 in Fig. 6 b) shows areas that seem to have a crystalline atomic arrangement. Accordingly, the film is only for sample 2 in vicinity of an amorphous layer. This might possibly change the onset of the crystallization transition, leading to different grain size, more leakage paths and therefore worse breakdown results (comp. Fig. 3 a)).

[picture]

Fig. 6. High-resolution TEM images showing the interfacial arrangement of a) sample 2 and b) sample .

Fig. 6. High-resolution TEM images showing the interfacial arrangement of a) sample 2 and b) sample .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.73.pdf

In this work, the influence of a typical, high-temperature SiC fabrication process on the electrical and structural properties of -based high- dielectrics was investigated. Gate-first MOS capacitors with poly-Si gate electrode and NiSi backside contact were chosen as test vehicles. Especially for dielectrics without an interfacial layer, we showed promising electrical results, consisting of highly uniform breakdown characteristics, high dielectric constant, low hysteresis and a nearly ideal flat-band voltage. Nevertheless, TDDB measurements revealed a rather low intrinsic lifetime at typical operation conditions when comparing with a gate dielectric from commercial SiC production. A possible root cause for the comparably low lifetime was found by performing high-
resolution TEM analysis, where all layers turned out to be polycrystalline. Furthermore, our work underlined the crucial role of carefully designing the gate dielectric-semiconductor-interface, not only in terms of interface defects, but also for tailoring the crystallization behavior of high- dielectrics.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1159.73.pdf

This work has received funding from the IPCEI ME/CT project. The IPCEI ME/CT project itself is supported by the Federal Ministry for Economic Affairs and Climate Action on the basis of a decision by the German Parliament, by the Ministry for Economic Affairs, Labor and Tourism of BadenWürttemberg based on a decision of the State Parliament of Baden-Württemberg, the Free State of Saxony on the basis of the budget adopted by the Saxon State Parliament, the Bavarian State Ministry for Economic Affairs, Regional Development and Energy and financed by the European Union NextGenerationEU.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.73.pdf

T. Kimoto, "High-voltage SiC power devices for improved energy efficiency", Proceedings of the Japan Academy. Series B, Physical and Biological Sciences, Vol. 98, p. 161-189 (2022).

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T. Aichinger et al., "Gate-oxide reliability and failure-rate reduction of industrial SiC MOSFETs", IEEE International Reliability Physics Symposium, p. 1-6 (2020).

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L. Tian et al., "Influences of annealing on structural and compositional properties of thin films grown on 4H-SiC by atomic layer deposition", Chinese Physics B, Vol. 25, p. 128104 (2016).

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 81-86

doi: 10.4028/p-7NEtpc

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-13

Revised:
2025-05-07

Accepted:
2025-05-08

Online:
2025-09-09

Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

Shigeaki Takagi , Hideo Yoshihashi, Katsuhisa Tanaka, Tomomi Imamura and Hiroshi Kono

Semiconductor Div., Toshiba Electronic Devices & Storage Corporation, 300, Ikaruga, Taisi-cho, Ibo-gun, Hyogo 671-1595, Japan

shigeaki.takagi@toshiba.co.jp, hideo1.yoshihashi@toshiba.co.jp, katsuhisa1.tanaka@toshiba.co.jp, tomomi.imamura@toshiba.co.jp, hiroshi.kono@toshiba.co.jp

Abstract

This report describes the application of titanium nitride (TiN) with a silicon nitride (SiN) intervening layer as a Schottky electrode in a Schottky barrier diode (SBD) made of 4 H -silicon carbide (SiC). This reduced the Schottky barrier height ( ) to 0.74 eV at room temperature, and it was confirmed that the reduction in was due not only to the application of TiN but also to the intervening layer containing SiN at the interface. Furthermore, TiN with SiN was applied to a device as a Schottky electrode, and the electric field reduction effect was verified by changing the high energy implantation and JBS width. As a result, the forward voltage ( ) was found to be reduced by a maximum of 0.23 V while suppressing leakage current. The reason for describing the interlayer as "intervening layer containing SiN" is that there may be other substances besides SiN.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

Silicon carbide (SiC) devices have the advantages of high breakdown voltage, low on-resistance, high-speed switching and high-temperature operation compared with silicon ( Si ) devices, and are expected to further expand the market to photovoltaic inverters (PVs), electric vehicle (EV) charging stations and on-board chargers (OBCs). For these applications, SiC Schottky barrier diodes are useful devices that take advantage of the excellent properties of SiC, such as low , and various materials have been evaluated as a Schottky electrode [1,2]. However, it is necessary to select a material with a low work function and lower Schottky barrier height . Metal nitrides are known to have a lower work function than pure metals [3,4], and it has also been reported that, for the case of Si, can be reduced by inserting an extremely thin insulating film between the Schottky electrode and the substrate [5]. In order to reduce in SiC devices, we adopted TiN as the Schottky electrode. In addition, we formed intervening layers containing SiN of different thicknesses as ultrathin films and investigated their impact on . Furthermore, we applied TiN with SiN as a Schottky electrode in a device and verified the electric field reduction effect by changing the high energy injection and JBS width.

Sample Structure

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

Fig. 1 shows a sample structure used to confirm the effect of reducing . We prepared (0001) wafers and formed an oxide film, and then exposed part of the SiC surface by performing a contact opening. Intervening layers of different thicknesses were then formed at the interface, after which a back electrode was formed. "Intervening layer of different thickness" mean that the thickness of the SiN layer has been varied.

[picture]

Fig. 1. Sample structure used to confirm the .

Fig. 1. Sample structure used to confirm the .

Experimental Methods

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

Cross-sectional observation was performed using high-resolution scanning transmission electron microscopy (STEM) to confirm the details of the SiC/Schottky electrode interface. STEM is a technique in which a thin sliced sample is irradiated with an electron beam, and the electrons that pass through or are scattered by the sample are imaged and observed at high magnification, making it possible to observe and analyze the microstructure of and lattice defects in the sample at nano-level high resolution. The results are shown in Fig. 2. In both Fig. 2(a) and 2(b), it can be seen that an intervening layer was formed between the SiC and the Schottky electrode. Moreover, the thickness of the intervening layer differed between Fig. 2(a) and 2(b), with that in Fig. 2(b) being thicker. The thickness was at the atomic layer level under all conditions. In addition, as the intervening layer thickened, the TiN crystal orientation changed from a uniform azimuth to polycrystalline with strong anisotropy. Uniform azimuth means that TiN is in the same direction as SiC, polycrystalline with strong anisotropy means that TiN has different orientations than SiC.

[picture]

Fig. 2. High-resolution STEM images of the SiC/Schottky electrode interface.

Fig. 2. High-resolution STEM images of the SiC/Schottky electrode interface.

Next, in order to observe the bonding state of atoms in the intervening layer, we performed electron energy-loss spectroscopy (EELS) analysis using the samples observed by STEM. EELS is a technique that measures the energy lost by electrons as they pass through a thin film, allowing the analysis of atoms and electronic structure. The results are shown in Fig. 3. Regardless of the thickness of the intervening layer, peaks were observed near 405 eV . It was found that these peaks originated from SiN . The intensity of the peak near 405 eV increased as the intervening layer became thicker.

The results of these high-resolution STEM and EELS analyses revealed that intervening layers of different thicknesses were formed at the SiC/TiN interface, and that the amount of SiN was greater when the intervening layer was thicker.

[picture]

Fig. 3. EELS spectrum at the SiC/Schottky electrode interface.

Fig. 3. EELS spectrum at the SiC/Schottky electrode interface.

In order to confirm the effect of using TiN with SiN, the current-voltage (IV) curve and were investigated for the above sample and conventional sample. "Conventional sample" refers to SBDs that use TiN electrodes without an intervening layer. The IV curve was measured using a semiconductor parameter analyzer after assembling individual chips onto a direct bonded copper (DBC) substrate after forming the back electrode. was calculated by calculating the saturation current density ( ) from the IV curve measured at -1.0 to 1.0 V using the Shockley diode equation shown in equation (1), and then calculating from using equation (2), where J is the current density, V is the applied forward voltage, q is the elementary electric charge, k is the Boltzmann constant, T is the measurement temperature and n is an ideality factor. A Richardson constant of was assumed [6]. The results are shown in Fig. 4.

was 0.74 eV for a thick intervening layer and 0.89 eV for a thin intervening layer. Compared with the 1.25 eV of a conventional sample, was therefore reduced by 0.51 eV by the thick intervening layer. In all conditions, the current of SBD is constant at , but this is due to the measurement conditions.

[picture]

Fig. 4. IV curve and .

Fig. 4. IV curve and .

It was found that the anisotropy of TiN changed as the intervening layer became thicker and the amount of SiN increased. Even for metals with the same work function, the value of the work function changes depending on the crystal orientation. When the crystal orientation is aligned, electrons easily jump out of the crystal, and the crystal has a positive charge. Therefore, a lot of energy is required to produce residual electrons in the crystal, and the work function becomes larger. However, if the crystal orientation is not aligned, electrons are attracted between the crystals, and the crystals becomes close to neutral. Therefore, energy is not required for the emission of residual electrons, and it is thought that the work function decreases. This suggests that when the intervening layer was thick, may have been significantly reduced.

Application to Devices

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

Although it was confirmed that it is possible to reduce by using TiN with SiN, it is important to understand the degree of impact on and when applied to a device. While the device created in Fig. 4 has a simplified SBD structure, the device in this chapter is a full device. Fig. 5 shows the curve and the curve when a TiN with SiN electrode is applied to a conventional device structure. and were checked at 12 A and 650 V . As shown in Fig. 5(a), it can be seen that is 0.23 V lower for TiN with SiN. This is believed to be due to the reduction of by TiN with SiN. However, as shown in Fig.5(b), in the TiN with SiN sample, is on the order of , which is two orders of magnitude larger than that in the conventional sample. This is due to low , and it is clear that suppressing leakage is an issue.

[picture]

Fig. 5. (a) curve and (b) curve when using a conventional device structure.

Fig. 5. (a) curve and (b) curve when using a conventional device structure.

The device structure was therefore changed to suppress leakage. Fig. 6 shows a schematic diagram of the device model. This device has a JBS structure in which a p-layer is embedded in a part of the n -layer on the semiconductor surface, with the length of the n -layer being and the length of the p -layer being . High energy implantation was performed to change the JBS width. During this process, the half-width of the n -region was changed while keeping the cell pitch constant.

[picture]

Fig. 6. Schematic diagram of a device model with modified element structure.

Fig. 6. Schematic diagram of a device model with modified element structure.

Fig. 7 shows the correlation between and when and are changed. Ir was less than regardless of the ratio of the n -region. This shows that it is possible to suppress leakage current by more than two orders of magnitude by changing the device structure. Moreover, as the proportion of the n -region increased, decreased and increased. This shows that by adjusting the widths in a device with a modified element structure, it is possible to optimize while suppressing leakage.

[picture]

Fig. 7. Relationship between and .

Fig. 7. Relationship between and .

Finally, Fig. 8 shows the relationship between and compared with a conventional sample when a modified device structure was applied using a TiN with SiN Schottky electrode. Compared with the conventional samples, at 12 A was reduced by a maximum of 0.23 V . at 650 V was on the order of , which was equal to or lower than that of conventional sample. From the above, it was possible to achieve both low and suppression even when applying TiN with SiN that can reduce to a device.

[picture]

Fig. 8. Relationship between at 12 A and at 650 V .

Fig. 8. Relationship between at 12 A and at 650 V .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

It was found that a significant reduction in in can be achieved by selecting TiN with a low work function and by forming an intervening layer containing SiN. This is believed to be because the crystal orientation changes as the intervening layer becomes thicker, causing a change in the Schottky work function. Furthermore, TiN containing an intervening layer was applied to a device as a Schottky electrode, and the electric field reduction impact was verified by changing the energy implantation and JBS width. As a result, it was confirmed that the was reduced by up to 0.23 V while suppressing leakage, demonstrating that it is possible to achieve both a low and suppression.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.81.pdf

K. Tanihira, Y. Hori, Y. Yamamoto, Y. Adachi, T. Ogata, S. Asaba, M. Kobayashi, H. Kono, H. Hayakawa, A. Tsuyuguchi and G. Tchouangue, Improving the VF-IR trade-off in 650-V/1200V SiC SBD by development of Schottky metal and optimization of device structure, in: PCIM Europe 2022; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2022, pp. 1-6.

L. Stöber, J.P. Konrath, F. Patocka, M. Schneider and U. Schmid, Controlling 4H-SiC Schottky barriers by molybdenum and molybdenum nitride as contact materials, IEEE Trans. Electron Dev. 63 (2016) 578-583.

M. Yoshitake, Examination of work function of transition metal carbides and nitrides, J. Vac. Soc. Jpn. 55 (2012) 349-353.

H.B. Michaelson, The work function of the elements and its periodicity, J. Appl. Phys. 48 (1977) 4729-4733.

D. Connelly, C. Faulkner, PA. Clifton and D.E. Grupp, Fermi-level depinning for low-barrier Schottky source/drain transistors, Appl. Phys. Lett. 88 (2006) 012105.

A. Itoh, T. Kimoto and H. Matsunami, High performance of high-voltage 4H-SiC Schottky barrier diodes, IEEE Electron Dev. Lett. 16 (1995) 280-282.

M. Yoshitake, How work function is determined, modified and applied for band alignment, Surf. Sci. 29 (2008) 64-69.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/technological-improvements-in-devices-fabrication/978-3-0364-1912-1

Materials Science Forum, ISSN: 1662-9752, Vol. 1159, pp 87-93

doi: 10.4028/p-bFMZ3S

© 2025 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2024-09-20

Revised:
2025-08-11

Accepted:
2025-08-11

Online:
2025-09-09

SiC Plasma Dicing for Future High Yield Die Singulation

The original version of this paper is available on https://www.scientific.net/MSF.1159.87.pdf

B. Jones , A. Croot , J. Mitchell , S. Kazemi , C. Bolton , H. Ashraf , M. Jennings , O. J. Guy

Swansea University, Singleton Park, SA2 8PP, Swansea, UK

KLA Corporation (SPTS Division), Ringland Way, NP18 2TA, Newport, UK

alex.croot@kla.com, cjacob.mitchell@kla.com,

samira.kazemi@kla.com, chris.bolton@kla.com, huma.ashraf@kla.com, o.j.guy@swansea.ac.uk

Keywords: Dicing. Plasma Dicing. Etch. RIE. Saw Dicing. Yield. Singulation.

Abstract

Silicon Carbide is an exceptionally hard and challenging to process semiconductor material. Effective device singulation retaining 100% die yield is hard to achieve with conventional saw dicing. Chips, microcracks and machining abrasions lead to reduced die strength and increased scrap. With rapid advancements in SiC device processing, resolving many fabrication issues, dicing yield losses are becoming an area of industrial concern. Plasma dicing has a proven track record in silicon and presents a potential solution to low yields during SiC dicing. Smooth vertical sidewalls with no machining damage, with etch rates approaching , position SiC plasma dicing as a viable alternative ready for industrial uptake. Plasma etch processes development using Ni and Cu etch masks, with full singulation have been demonstrated, resulting in improved die strength compared to saw diced samples.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1159.87.pdf

Silicon carbide power MOSFETs with blocking voltage ratings between 650 V and 1200 V are increasingly being used for applications in electric vehicles, while SiC is also utilized as a substrate for high frequency GaN RF devices. Effective singulation of SiC die, with reduced dicing lane widths and subsequent increase in die per wafer is an important technological development for device production. Conventional saw dicing is known to introduce chips and abrasions which serve as sites for crack propagation, significantly weakening the individual SiC die with a detrimental impact on yield by on average across the industry [1]. Given the rapid advancements in SiC device processing and a focus on reducing defects for automotive applications [2], SiC die singulation yield losses stand to become a focal area of improvement in the future.

Laser-based die singulation technologies such as stealth dicing show promise but can introduce localized heating and stress to the wafer in the form of increased dislocation density around the diced region [3]. Plasma dicing of SiC offers an alternative avoiding edge chipping, surface particle damage, tooling losses related to saw dicing [4] and thermal stresses and particulates associated with laser dicing. Assuming a dicing lane width reduction to from (saw dicing), and a die size of translates to a yield increase across a 150 mm wafer. This predicted yield improvement is compounded by the established yield loss typical of saw dicing, suggesting an overall yield improvement of up to if plasma dicing was utilized over saw dicing. This is depicted graphically in Fig. 1. Additionally, the projected plasma dicing yield improvements willenefit from economies of scale when industry adopts larger wafer sizes and reduced wafer thickness, while the throughput will also increase compared to saw dicing as lanes will not need to be diced individually. The ability to singulate SiC die with maximised die yield, minimal defects and at a cost-effective throughput is an industry priority.

This work presents SiC dicing etch optimisation building on previously reported results [5] while demonstrating use of Cu etch masking and providing insight into on-wafer processing temperatures. The capabilities of plasma dicing technology are outlined with a goal of providing an industry-ready solution to the issues associated with current wafer dicing processes.

[picture]

Fig. 1. Plotted 150 mm die yield comparison between A ) saw dicing and B ) plasma dicing, if die size is and lane width for saw dicing is , while plasma dicing lanes are wide. This results in a theoretical yield increase for the plasma diced wafer.

Fig. 1. Plotted 150 mm die yield comparison between A ) saw dicing and B ) plasma dicing, if die size is and lane width for saw dicing is , while plasma dicing lanes are wide. This results in a theoretical yield increase for the plasma diced wafer.

Methods

The original version of this paper is available on https://www.scientific.net/MSF.1159.87.pdf

For this study bulk and thinned 150 mm SiC wafers with Cu etch masks were used, with examples of Ni etch masks also used for comparison. A dicing lane width of was used to singulate die, and to perform etch process trend development work on die. All development work was performed using bulk SiC pieces on Cu-coated Si carrier wafers, bonded with an adhesive stable up to . An SPTS SynapsEtch module was used for the RIE processing, capable of maximum 2.5 kW source and 1.5 kW bias powers. This process module facilitates a high-density plasma, with a readily changeable wafer-source distance to maximise high energy ions interacting with the wafer. and etch chemistry was used for this backside etch. SEM imaging was used to obtain etch rate, profile angle and etch rate uniformity data while bias power, flow and process pressure were varied over the course of this study.

On-wafer process temperature data was acquired using an FLIR T530 thermal camera with temperature range set to . The process module top view port was fitted with a ZnSe window to allow emission of infrared spectra. The Cu coated SiC pieces used for the temperature study were mounted alongside an IR emissive material ( Cu has an IR emissivity of ) to obtain accurate temperature readings.

For the die strength testing a Mecmesin MultiTest-dV 2.5 force tester fitted with an AFG gauge was used. The strength test criteria was a 3 point break test, performed flat, lengthways on the singulated SiC die.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1159.87.pdf

SiC dicing etch process tests were performed to optimise etch rate and examine profile angle and etch uniformity. Etch process trends shown in Fig. 2. A) show the SiC etch characteristics of Cu and Ni masks with respect to varied bias power, with maximum source power. The etch rate for the Cu masked samples is almost double that of the Ni-masked samples, while the profile angle and uniformity are also improved on average. For efficient whole wafer singulation, low percentage etch rate uniformity is highly desirable, as the processing time will be limited to the slowest etch rate (typically at the wafer edges).

The improved etch rate and profile angle of the Cu -masked samples could be explained by the difference in metal sputtering and re-deposition behaviour during processing - effectively reducing masking by re-deposited metal. From previous work [5] it is understood that the Cu redeposition is less than that of the Ni . The reduction in sidewall redeposition results in an etch profile angle closer to . Cu sputter yield is typically higher than that of Ni, so the reduced Cu redeposition could be
caused by the fact it is more easily removed by the ongoing etch [6]. This could also explain the increased etch rate of the Cu masked sample - sputtered Cu at the base of the trench being more easily removed by the ongoing etch, compared to the Ni counterpart.

Given the improvements offered by the Cu mask, all subsequent process development was performed on Cu -masked SiC . Fig. 2. B) shows the effects of altering flow. The depicted trend presents an etch rate plateau at of total applied flow, while the uniformity continues to improve at maximum applied flow. Increased flow improving the etch uniformity is likely due to an increase in fluorine ions available to interact with the SiC. The influence of process pressure on etch outputs is shown in Fig. 2. C). A marked improvement in etch rate at higher process pressures is seen, likely owing to increased etchant density at the trench base. However, etch uniformity suffers with increasing process pressure.

Based on the results in Fig. 2. it was presumed that a cumulative benefit could be attained by combining increased flow and raising process pressure. Fig. 3. A) shows the etch trends when high process pressure is maintained and flow is varied, while Fig. 3. B) shows changing process pressure with maintained high flow. Contrary to the assumption that combined increases in process pressure and flow should improve the etch rate, Fig. 3. shows that the etch rate and uniformity decrease at this process regime.

Table 1 summarises a proposed hypothetical etch mechanism for the differences in results found at the range of applied process conditions. At high flow the Cu mask undergoes more aggressive chemical etching which promotes increased Cu sputtering and redeposition in the trench, as the byproduct is not significantly volatile. At lower process pressures we propose that the removal rate of redeposited material increases, owing to the greater ability of ions to reach the base of the trench. When both flow and process pressure are high, Cu sputtering into the trench is high but its removal is hindered by the high process pressure (short mean free path for ions), perhaps explaining the reduced etch rates seen in Fig. 3. Requiring validation by further tests, this explanation suggests that the etch mechanism of the Cu mask in fluorine is predominantly chemical, which is plausible as Cu readily forms bonds with fluorine in solution.

[picture]

Fig. 2. Etch trend data for etch rate, sidewall profile angle and depth uniformity. A) Baseline data for Cu and Ni masked SiC depicted for varying bias power while source power is kept constant, with low process pressure and flow. B) Cu masked samples etch data, varying flow at constant source and bias powers with low process pressure. C) Cu masked samples etch data, varying process pressure at constant source and bias powers with low flow.

Fig. 2. Etch trend data for etch rate, sidewall profile angle and depth uniformity. A) Baseline data for Cu and Ni masked SiC depicted for varying bias power while source power is kept constant, with low process pressure and flow. B) Cu masked samples etch data, varying flow at constant source and bias powers with low process pressure. C) Cu masked samples etch data, varying process pressure at constant source and bias powers with low flow.

[picture]

Fig. 3. Etch trend data for etch rate, sidewall profile angle and depth uniformity. A) Cu masked sample data for variable flow with process pressure held at of max and constant source and bias powers. B) Cu-masked sample data for variable process pressure with held at of max and constant source and bias powers.

Fig. 3. Etch trend data for etch rate, sidewall profile angle and depth uniformity. A) Cu masked sample data for variable flow with process pressure held at of max and constant source and bias powers. B) Cu-masked sample data for variable process pressure with held at of max and constant source and bias powers.

Table 1. Process conditions influence on SiC etch rate.

Process Condition | Low SF₆ Flow | High SF₆ Flow

Low Process Pressure
➤ Low fluorine density in trench.
➤ Low mask resputtering.
➤ High trench redeposition removal.
❖ Low SiC etch rate.
➤ High fluorine density in trench.
➤ High mask resputtering.
➤ High trench redeposition removal.
❖ High SiC etch rate.

High Process Pressure
➤ High fluorine density in trench.
➤ Low mask resputtering.
➤ Low trench redeposition removal.
❖ High SiC etch rate.
➤ High fluorine density in trench.
➤ High mask resputtering.
➤ Low trench redeposition removal.
❖ Low SiC etch rate.

On-wafer temperature data obtained during etch processing using a thermal camera is shown in Fig. 4. with the temperature increasing with applied bias power. Between points ) and ) the temperature increase is minimal, but when the bias power is set to max (point ), the wafer temperature jumps dramatically. For SiC devices, certain metallizations such as Schottky contacts are temperature sensitive, depending on the metal, so understanding the relative temperature changes with etch parameters is valuable for a process intended to be performed post device fabrication. The impact of processing temperature on the fabricated devices is still proposed to be minimal due to the dicing etch being a backside process.

Additionally, measurements were taken of the Cu coated carrier wafer temperature ( and on Fig 4). The slight temperature decrease of the carrier compared to the mounted pieces implies that on the pieces the underlying Cu mask layer, the bulk thickness of the mounted piece and the bonding agent are acting as insulating layers, slightly reducing the effect of the chuck cooling (set to ). In production, mounted, thinned and masked SiC device wafers are expected to etch at a temperature somewhere between that of the carrier and piece as presented here.

Fig. 5. shows the result of an optimised SiC dicing etch prior to sidewall passivation removal using nitric acid. An etch rate of was achieved at a process pressure of of max, while maintaining low flow and bias. For an industry viable dicing process an etch rate of
is desirable to compete with saw dicing throughput, while maintaining effectively low process temperatures. However, given the imminent industry scale up of SiC to 200 mm substrates and the associated increase in yield, plasma dicing could realise a throughput advantage over conventional saw dicing. This is largely due to the requirement of saw dicing to individually dice each lane on the substrate.

[picture]

Fig. 4. Measured temperature data for Cu -masked bonded SiC samples and Cu carrier wafers using infrared imaging mid-process, for varying bias power. Infrared images shown inset with marker to the plot.

Fig. 4. Measured temperature data for Cu -masked bonded SiC samples and Cu carrier wafers using infrared imaging mid-process, for varying bias power. Infrared images shown inset with marker to the plot.

[picture]

Fig. 5. SEM cross section of optimised SiC dicing etch, exhibiting an average etch rate of , and cross wafer uniformity while the Cu mask etch rate was .

Fig. 5. SEM cross section of optimised SiC dicing etch, exhibiting an average etch rate of , and cross wafer uniformity while the Cu mask etch rate was .

SiC die were singulated using the etch process outlined in Fig. 5. The individual die can be seen in Fig. 6. A) prior to debonding from the Si carrier wafer. An example of a de-bonded, singulated die is depicted in Fig. 6. B) following mask and passivation removal.

More detailed sidewall topography can be seen in Fig. 7. A), which compares die edge surfaces of saw-diced and plasma-diced samples. The evident machining damage and chipping on saw-diced
sample is understood to be typical of saw-diced SiC, and likely has a detrimental effect on the die strength. By contrast, the surface of the plasma-diced sample has very little evident surface damage.

Fig. 7. B) demonstrates the die strength improvement afforded by plasma dicing compared to saw dicing. The microcracks and abrasions caused by saw dicing likely act as sites of crack propagation, weakening the die. The improved die strength afforded to plasma dicing should translate to improved wafer-die yield were this processing method adopted by the industry.

[picture]

Fig. 6. A) Complete 150 mm Cu masked thinned SiC wafer, bonded to a carrier wafer, post singulation etch. The individual die are visible, along with the dicing lanes. B) SEM image of individual die, post etch following mask removal and passivation removal in nitric acid.

Fig. 6. A) Complete 150 mm Cu masked thinned SiC wafer, bonded to a carrier wafer, post singulation etch. The individual die are visible, along with the dicing lanes. B) SEM image of individual die, post etch following mask removal and passivation removal in nitric acid.

[picture]

Fig. 7. A) SEM image side-view of saw-diced (top) & plasma-diced (bottom) SiC die. While handling debris is visible on both, there is also evident saw damage on the saw-diced sample. B) Plot comparing die break stress for plasma- and saw-diced samples. The plasma-diced die exhibited greater overall strength than their saw-diced counterparts.

Fig. 7. A) SEM image side-view of saw-diced (top) & plasma-diced (bottom) SiC die. While handling debris is visible on both, there is also evident saw damage on the saw-diced sample. B) Plot comparing die break stress for plasma- and saw-diced samples. The plasma-diced die exhibited greater overall strength than their saw-diced counterparts.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1159.87.pdf

The rapid advancements in SiC device processing, particularly for the power electronics sector mean that as issues are solved, new problems quickly become a focal point for industry. Efficient singulation of SiC devices is a targeted area for development, with projected yield improvements associated with plasma dicing, compared to saw dicing, as high as . In this paper, a backside dicing process with an etch rate of has been demonstrated. Processing temperature considerations have also been investigated - particularly the relationship between applied bias power
and on-wafer process temperature. Finally, the relative die strengths have been compared for sawand plasma- singulated die. In this instance, we suggest that the vastly improved die edge surface smoothness is the defining factor in the improved die strength following plasma dicing.

References

The original version of this paper is available on https://www.scientific.net/MSF.1159.87.pdf

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L. Shi et al., Investigation of different screening methods on threshold voltage and gate oxide lifetime of SiC Power MOSFETs, 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023, Pp. 1-7

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Keywords Index

4

4h-sic Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing; Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

A

Annealing Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

B

Barrier Height Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Basal Plane Dislocations Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

C

C-face 4 H -sic C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Carbon Face Epitaxy C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Common-source Amplifier Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

D

Device Fabrication Trench Etch Processing for SiC Superjunction Schottky Diodes

Dicing. Plasma Dicing. Etch. Rie. Saw Dicing. Yield. Singulation SiC Plasma Dicing for Future High Yield Die Singulation

F

Fermi Level Pinning Effects of Sulfurization on the Properties of -SiC Schottky Contacts

G

Gate Oxide Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Gate-all-around (gaa) Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

H

Harsh Environment Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

I

Inductively Coupled Plasma And Reactive Ion Etching Trench Etch Processing for SiC Superjunction Schottky Diodes

Ito Interlayer Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

J

Jfet Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

K

Kelvin Probe Force Microscopy Effects of Sulfurization on the Properties of -SiC Schottky Contacts

L

Laser Ablation Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Laser Annealing Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing; Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

M

Metal-sic Interface Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Mos Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

N

N-type SiC Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

O

Ohmic Contact Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing; Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

Ohmic Contacts Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

P

P-type Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

Q

Qbd Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

R

Reliability Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Rta Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

S

Schottky Barrier Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Schottky Barrier Diode C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Schottky Diode Trench Etch Processing for SiC Superjunction Schottky Diodes

SiC Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Silicon Carbide Trench Etch Processing for SiC Superjunction Schottky Diodes

Silicon Carbide (sic) Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Smartsic ™ Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Structured Contact Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

Sulfurization Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Superjunction Trench Etch Processing for SiC Superjunction Schottky Diodes

Surface Preparation Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing

T

Tddb Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Trench Devices Trench Etch Processing for SiC Superjunction Schottky Diodes

W

Wafer Dicing Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Water Jet Guided Laser Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Authors Index

A

Abe, K. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Allibert, F. Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Alquier, D. Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing

Amamiya, T. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Antoniou, M. Trench Etch Processing for SiC Superjunction Schottky Diodes

Arimura, S. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Ashraf, H. SiC Plasma Dicing for Future High Yield Die Singulation

B

Baier, L. Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Bartolf, H. Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

Becker, T. Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Bera, L. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Berger, C. Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing

Bolton, C. SiC Plasma Dicing for Future High Yield Die Singulation

Boudin, L. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

C

Cao, Q. Trench Etch Processing for SiC Superjunction Schottky Diodes

Chand, U. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Chien, Y. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Chua, H. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Chung, S. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Croot, A. SiC Plasma Dicing for Future High Yield Die Singulation

F

Fiorenza, P. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Franco, S. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

G

Gammon, P. Trench Etch Processing for SiC Superjunction Schottky Diodes

Giannazzo, F. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Gong, X. Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Greco, G. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Guiot, E. Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Guy, O. SiC Plasma Dicing for Future High Yield Die Singulation

H

Hellinger, C. Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

Hirano, S. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Huang, A. Analysis of Ohmic Contacts Simultaneously Formed on both -Type and -Type -SiC

I

Imamura, T. Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

J

Jennings, M. SiC Plasma Dicing for Future High Yield Die Singulation

Jones, B. SiC Plasma Dicing for Future High Yield Die Singulation

K

Kabelaan, L. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Kadoya, S. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Kam, S. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Kazemi, S. SiC Plasma Dicing for Future High Yield Die Singulation

Kono, H. Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

Koos, A. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Kumar, S. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Kuroiwa, T. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Kuroki, S. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

L

Lophitis, N. Trench Etch Processing for SiC Superjunction Schottky Diodes

M

Masui, S. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Melnyk, K. Trench Etch Processing for SiC Superjunction Schottky Diodes

Michaud, J. Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing

Michihata, M. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Mitchell, J. SiC Plasma Dicing for Future High Yield Die Singulation

N

Nakayama, K. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Nguyen, X. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

O

Ohtani, N. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

P

Panasci, S. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Pécz, B. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

R

Rabinzohn, P. Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

Radu, I. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Renz, A. Trench Etch Processing for SiC Superjunction Schottky Diodes

Roccaforte, F. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Rommel, M. Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime; Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

S

Schlichting, H. Gate Oxide Performance and Reliability on SmartSiC ™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Scholten, D. Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

Schulze, J. Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

Schwarzenbach, W. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Shimbori, A. Analysis of Ohmic Contacts Simultaneously Formed on both -Type and -Type -SiC

Singh, N. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Song, W. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes

Sulyok, A. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

T

Takagi, S. Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

Takahashi, S. Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser

Tanaka, K. Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

Tanaka, Y. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Thum, M. Formation of Structured Low-Ohmic p-Type Contacts on AI-Implanted 4H-SiC by Laser Annealing

U

Umezawa, H. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

V

Valecha, R. Analysis of Ohmic Contacts Simultaneously Formed on both -Type and -Type -SiC

Vivona, M. Effects of Sulfurization on the Properties of -SiC Schottky Contacts

Voo, Q. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Voznyi, A. Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

X

Xie, J. Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Y

Yamamoto, M. Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation

Yeo, A. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes; Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Yeo, Y. Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance

Yoshihashi, H. Effect of Inserting an Intervening Layer on Reduction in TiN Schottky

Z

Ziegler, J. Investigation of Poly-Si Gated, -Based High- Dielectrics on -SiC

Zielinski, M. C-Face Epitaxy for Enhanced SiC Device Performance: Insights from Schottky Barrier Diodes