Cover

ISBN print: 978-3-0364-0825-5
ISBN eBook: 978-3-0364-1825-4
DOI book: 10.4028/b-0FifaI
© 2026 Trans Tech Publications Ltd, All Rights Reserved

The 22nd  International Conference on Silicon Carbide and Related Materials (ICSCRM)

Selected peer-reviewed extended articles based on abstracts presented at the
22nd  International Conference on Silicon Carbide and Related Materials
(ICSCRM 2025)

Edited by
Prof. Sang-Mo Koo
Prof. Hoon-Kyu Shin
Dr. Moonkyong Na
Prof. Won-Jae Lee
Dr. Jeong Hyun Moon

The 22nd  International Conference on Silicon Carbide and Related Materials (ICSCRM)

Selected peer-reviewed extended articles based on abstracts presented at the 22nd  International Conference on Silicon Carbide and Related Materials
(ICSCRM 2025)

Aggregated Book

Edited by
Prof. Sang-Mo Koo, Prof. Hoon-Kyu Shin, Dr. Moonkyong Na, Prof. Won-Jae Lee and Dr. Jeong Hyun Moon
Scientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volume 259 of
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ISBN 978-3-0364-0825-5

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Scientific Books Collection, Vol. 259, pp -5-0

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Accepted:
2026-05-21

Online:
2026-06-02

Preface

On behalf of the Organizing Committee and the ICSCRM Steering Committee, it is our great privilege and honor to present the peer-reviewed proceedings of the 22nd International Conference on Silicon Carbide and Related Materials (ICSCRM 2025), held from 14 to 19 September 2025 at BEXCO, Busan, Korea.

These proceedings present recent advances in silicon carbide and related materials, covering key topics such as material growth, defects and characterization, device processing, device physics and design, quantum applications and sensors, and reliability, applications, and packaging. Together, they reflect both the scientific progress and the growing industrial importance of SiC technologies.

Since its beginning in Washington, D.C. in 1987, ICSCRM has served as a leading international forum for the exchange of cutting-edge research and ideas in the field. Under the theme "Industrial Innovation and Convergence through SiC Technology," ICSCRM 2025 continued this tradition by bringing together researchers, engineers, and industry leaders from around the world. The conference served as a meaningful venue to explore the present and future of industrial innovation and convergence centered on SiC technology.

The vital role of SiC and related materials was reaffirmed across diverse and critical application fields, spanning electric vehicles (EVs) and e-mobility, AI data centers, energy infrastructure, as well as advanced robotics, high-speed railway systems, and aerospace.

ICSCRM 2025 welcomed over 2,200 attendees and 170 companies exhibiting their products and services, highlighting the strong global momentum of the silicon carbide community. Hosted in Korea, a major hub of semiconductor innovation, the conference provided an excellent setting for technical exchange, collaboration, and inspiration.

We sincerely thank all authors, reviewers, committee members, speakers, participants, exhibitors, and sponsors for their valuable contributions to ICSCRM 2025. We also gratefully acknowledge the support of Busan Metropolitan City and KIEEME, whose support was essential to the success of this conference.

We hope that this volume will serve as a valuable reference for researchers, engineers, and students, and will contribute to the continued advancement of silicon carbide and related materials worldwide.

Sincerely,
Prof. Sang-Mo Koo
General Chair, ICSCRM 2025
Kwangwoon University
Prof. Hoon-Kyu Shin
General Chair, ICSCRM 2025
Pohang University of Science and Technology (POSTECH)

Committee

Organizing Committee
General Chairs
Sang-Mo Koo, Kwangwoon University
Hoon-Kyu Shin, Pohang University of Science and Technology (POSTECH)
Honorary Chairs
Hyeong Joon Kim, Seoul National University
Nam Kyun Kim, Korea Electrotechnology Research Institute (KERI)
Industrial Committee
Gwonje Kim, EYEQ Lab
Chang-Heon Yang, SK Powertech
Su-Sung Kim, Powermaster Semiconductor
Seoyong Ha, LS semiconductor
Seyul Oh, Siltron
Hyundon Jeong, EtaMax
Seokjun Hong, Samsung Electronics
Sinsu Kyung, PCS
Yoonhwa Choi, JMJK
Donggeun Jang, Semi-Powerex
Taekyung Kim, SemiLab
Gabryeol Koo, Senic
Publication Committee
Moonkyong Na, Korea Electrotechnology Research Institute (KERI)
Hyemin Kang, Korea Institute of Energy Technology (KENTECH)
Youngjun Yoon, Andong National University
Yunji Shin, Korea Institute of Ceramic Engineering and Technology (KICET)
Jeongsik Kim, Gyeongsang National University
Ogyun Seok, Pusan National University
Tutorial Committee
Soon-Ku Hong, Chungnam National University
Wook Bahng, Korea Electrotechnology Research Institute (KERI)
Jihyun Kim, Seoul National University
Hanseok Seo, Research Institute of Industrial Science & Technology (RIST)
International Advisory Board
Sang-Mo Koo, Kwangwoon University
Hidekazu Tsuchida, Central Research Institute of Electric Power Industry (CRIEPI)
Tsunenobu Kimoto, Kyoto University
Eui-joon Yoon, Korea Institute of Energy Technology (KENTECH)
Executive Committee
Hoon-Kyu Shin, Pohang University of Science and Technology (POSTECH)
Jeong Hyun Moon, Korea Electrotechnology Research Institute (KERI)
Namseok Lee, NINT
Jaehwa Seo, Korea Electrotechnology Research Institute (KERI)
Research Committee
Wook Bahng, Korea Electrotechnology Research Institute (KERI)

Taehee Eun, Research Institute of Industrial Science & Technology (RIST)
Won-Jae Lee, Dong-eui University
Soon-Ku Hong, Chungnam National University
Hyoung Woo Kim, Korea Electrotechnology Research Institute (KERI)
Jihyun Kim, Seoul National University
Seungcheol Lee, Samsung Electronics
Jaegil Lee, Powermaster Semiconductor
Hyungtak Kim, Hongik University
Hoyoung Cha, Hongik University
Hyung-Seok Lee, Electronics and Telecommunications Research Institute (ETRI)
Hyemin Kang, Korea Institute of Energy Technology (KENTECH)
Siyoung Bae, Pukyong National University
Ogyun Seok, Pusan National University
Kwangeun Kim, Korea Aerospace University
Sola Woo, Pukyong National University
Myounggon Kang, University of Seoul

ICSCRM Steering Committee

Philip G. Neudeck (Chair), NASA Glenn Research Center, USA
Michael Krieger, Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany
Elif Balkas, Wolfspeed, USA
Peder Bergman, Linköping University, Sweden
Didier Chaussende, CNRS / Université Grenoble Alpes, France
Danilo Crippa, Vishay, Italy
Hrishikesh Das, Silectric Semiconductor, USA
Sima Dimitrijev, Griffith University, Australia
Michael Dudley, Stony Brook University, USA
Peter Friedrichs, Infineon, Germany/Austria
Adam Gali, Wigner Research Centre for Physics, Hungary
Hisayoshi Itoh, National Institutes for Quantum Science and Technology (QST), Japan
Nam Kyun Kim, Korea Electrotechnology Research Institute, Korea
Alexander Lebedev, Ioffe Institute, Russia
Kung-Yen Lee, National Taiwan University, Taiwan
Nadeem Mahadik, United States Naval Research Laboratory, USA
Phil Mawby, University of Warwick, UK
Noboru Ohtani, Kwansei Gakuin University, Japan
Hajime Okumura, National Institute of Advanced Industrial Science and Technology (AIST), Japan
Dominique Planson, University of Lyon, France
Fabrizio Roccaforte, CNR-IMM, Italy
Adolf Schöner, Coherent, Sweden
Kuang Sheng, Zhejiang University, China
Ljubisa Stevanovic, GE Aerospace, USA
Hidekazu Tsuchida, Central Research Institute of Electric Power Industry (CRIEPI), Japan
Victor Veliadis, PowerAmerica, USA
Hiroshi Yano, University of Tsukuba, Japan

Advisory Panel

Wolfgang Jim Choyke, University of Pittsburgh, USA
Robert P. Devaty, University of Pittsburgh, USA
Philippe Godignon, CEA Leti, France
Francesco La Via, CNR-IMM, Italy
Hiroyuki Matsunami, Kyoto University, Japan
Robert Stahlbush, United States Naval Research Laboratory, USA

ICSCRM Lifetime Members

Calvin H. Carter, USA
Roland Madar, France
Roberta Nipoti, Italy
Roland Rupp, Germany
Sadafumi Yoshida, Japan

Technical Program Committee

Chair

Won-Jae Lee, Dong-eui University

Vice-Chair

Jeong Hyun Moon, Korea Electrotechnology Research Institute (KERI)

Track 1: Material and Growth

Seong-Min Jeong (Track Lead), Korea Institute of Ceramic Engineering and Technology Didier Chaussende, CNRS
Noboru Ohtani, Kwansei Gakuin University
Francesco La Via, CNR-IMM
Hidekazu Tsuchida, Central Research Institute of Electric Power Industry (CRIEPI)
Xiangang Xu, Shandong University
Andy Souzis, Coherent
Adrian Powell, Wolfspeed
Jon Leist, Momentive Technologies
Gilyong Chung, SK siltron css
Elif Balkas, Wolfspeed
Bernd Thomas, Bosch
Peter Wellmann, Friedrich-Alexander Universität Erlangen-Nürnberg
Gabriel Ferro, Université Claude Bernard Lyon

Track 2: Defects and Characterization

Soon-Ku Hong (Track Lead), Chungnam National University
Tsunenobu Kimoto, Kyoto University
Gregor Pobegen, KAI GmbH
Peder Bergman, Linkoping University
Michael Dudley, Stony Brook University
Masashi Kato, Nagoya Institute of Technology
Wook Bahng, KERI
Albert Burk, Coherent
Nadeemullah Mahadik, Naval Research Laboratory
Ulrike Grossner, ETH Zurich
Adolf Schöner, Coherent

Track 3: Device Process and Characterization

Woongje Sung (Track Lead), University at Albany
Fabrizio Roccaforte, CNR-IMM
Jun Zeng, Vishay Siliconix
Hiroshi Yano, University of Tsukuba
Philippe Godignon, French Atomic Energy Commission
Peter Gammon, University of Warwick
Daniel Alquier, University of Tours
Takuji Hosoi, Kwansei Gakuin University
Chih-Fang Huang, National Tsing Hua University
Sima Dimitrijev, Griffiths University

David Spry, NASA Glenn
Brett Hull, Wolfspeed
Jang-Kwon Lim, Research Institute of Sweden
Carl-Mikael Zetterling, KTH Royal Institute of Technology
Jean-François Michaud, University of Tours
Kevin Speer, US Army Research Laboratory
Track 4: Devices Physics, Design, and Characterization
Hyoung Woo Kim (Track Lead), Korea Electrotechnology Research Institute (KERI)
Naruhisa Miura, Mitsubishi Electric Corporation
Marina Antoniou, University of Warwick
Victor Veliadis, PowerAmerica
Andrei Mihaila, StarpowerEurope
Yoshiyuki Yonezawa, Advanced Industrial Science and Technology (AIST)
Peter Friedrichs, Infineon
Andrea Irace, University of Naples Federico II
Kung-Yen Lee, National Taiwan University
Sei-Hyung Ryu, Wolfspeed
Kyeongseok Park, onsemi
Peter Losee, Qorvo
Jihyun Kim, Seoul National University
Philip G. Neudeck, NASA
David Clark, ClasSiC
Anant Agarwal, Ohio State Univ.
Sid Sundaresan, Navitas Semiconductor
Dethard Peters, Infineon

Track 5: Quantum Applications, Sensor and Related Materials

Sang-Yun Lee (Track Lead), Gwangju Institute of Science and Technology (GIST)
Ho-Young Cha, Hongik University
Michael Krieger, Friedrich-Alexander-Universität
Michel Bockstedte, Johannes Kepler University Linz
Adam Gali, Wigner Research Centre
Takeshi Ohshima, National Institutes for Quantum Science and Technology (QST)
Rachael Myers-Ward, US Naval Research Lab
Brenda Vanmil, US Army Research Laboratory
Hannes Kraus, NASA Jet Propulsion Laboratory

Track 6: Reliability, Applications and Packaging

Sang Won Yoon (Track Lead), Seoul National University
Hyuncheol Bae, ETRI
Dominique Planson, Ampere Laboratory
Don Gajewski, Wolfspeed
Kimimori Hamada, HUAWEI Technologies Japan
Nando Kaminski, University of Bremen
Aivars Lelis, US Army Research Laboratory
Shiori Idaka, Mitsubishi Electric Europe
Hrishikesh Das, Silectric Semiconductor
Mike Jennings, Swansea University
Mikael Östling, KTH Royal Institute of Technology
Adam Morgan, NoMIS Power

Sponsors and Supporters

Organized by

KIEEME（The Korean Institute of Electrical and Electronic Material Engineers）

Supported by

Busan Metropolitan City

Sponsor List

Star Sponsor

（1）∈Y∈QLคำLНь

Diamond Sponsor

Gold Sponsors

RIXTROM
centrotherm
SEMILAB
sɪcc

DB HiTek

Silver Sponsors

EpiWorld
International Co．，Ltd．

TANKEELUE天科合达

STi）STI CO．，LTD

Bronze Sponsors

Table of Contents

Preface

Chapter 1: Bulk and Epitaxial Growth of SiC

Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Fu Sheng Zhang, Yong Liang Shao, Yong Zhong Wu, Bao Guo Zhang, Dong Shi, Hai Xiao Hu, Xiao Peng Hao

300 mm4H-SiC Crystal and Substrate Development

Ya Ni Pan, Chao Gao, Yu Zhou, Xiu Xiu Ning, Yin Li, Ying Guo, Hong Yu Peng, Yan Min Zong

Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates

Chiara Nania, Ruggero Anzalone, Domenica Raciti, Nicolò Piluso, Fabiana Vento, Cristiano Calabretta, Andrea Severino

Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers 

Wei Ning Qian, Fei Hong Huang, Jin An Li, Gan Feng, Jian Hui Zhao, Jun Yong Kang

Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Michael Schley, Friedrich Schaaff, Jan Richter

Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Tawhid Rana, Taskin Karim, Jonas P. Murphy, Sam Johnson, Nicolas Thierry-Jebali, Edward Sanchez

Solution Growth Technique of Silicon Carbide with In Situ Observation

Yoshihisa Abe, Akihisa Kawabe, J. Osada, K. Kurashige, H. Nakanishi, H. Ishibashi, Toru Ujihara

Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Sven Strüber, Cristina Grazzi, Lucrezia Tana, Ole Schneider, Tobias Wagner, Jakob Wiedemann, P. Wunder, P. J. Wellmann

Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Julian Zöcklein, Sven Strüber, Cristina Grazzi, Nils Christian Arneberg, Tobias Straub, Siegmund Greulich-Weber, Peter J. Wellmann

Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Chae Young Lee, Su Ho Kim, Jung Woo Choi, Myung Ok Kyun, Jung Gyu Kim, Kap Ryeol Ku, Yeon Suk Jang, Jung Gon Kim, Won Jae Lee

Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

Birgit Kallinger, Christian Gobert, Maximilian Titl, Robin Karhu, Johannes Köhler, Jürgen Erlekampf

Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways

Misagh Ghezellou, Justinas Palisaitis, Jawad Ul-Hassan

Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

Shota Tani, Masato Urakami, Wataru Saito, Shin Ichi Nishizawa

Chapter 2: Defects Evaluation

The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Jimmy Thörnberg, Björn Magnusson

Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Wei Ning Qian, Fei Hong Huang, Ji Nan Li, Gan Feng, Yong Qiang Sun, Jian Hui Zhao, Jun Yong Kang

Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Christian Wißgott, Birgit Kallinger, Mathias Rommel

DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Lan Luo, Yu Zhong, Xiao Shuang Yang, Quan Xin Zhao, Peng Cui, Ying Xin Cui, Ming Sheng Xu, Xian Gang Xu, Ji Sheng Han

Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Zhen Xing Fu, Xiang Long Yang, Xiu Fang Chen, Xue Jian Xie, Li Sun, Hong Yu Shao, Wen Hao Han, Hong Xi Wang, Guo Jian Yu, Xian Gang Xu

DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Rosine Coq Germanicus, Gabriel Ferro

Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Nicolo Piluso, Cristiano Calabretta, Fabiana Vento, Ruggero Anzalone, Chiara Nania, Domenica Raciti, Antonio Rossitto, Alice Lombardo, Mario Coppola, Annalisa Cannizzaro, Andrea Severino, Giuseppe Arena, Matteo M. Salamone, Federico Giuffrida, Luca Barbisan, Parikshit Sharma, Jeff Per, Manoj Kumar Dayyala, Paola Parisi

Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Zimo Yuan, Alex Metreveli, Lasse Vines, Orazio Samperi, Misagh Ghezellou, Jawad Ul-Hassan, Anders Hallén

Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Li Sun, Xue Jian Xie, Xiu Fang Chen, Xiang Long Yang, Yan Peng, Xiao Bo Hu, Xian Gang Xu

High Quality P-Type 4H-SiC Growth by PVT Method

Shan Shan Hu, Hao Chi Wang, Ze Yu Chen, Kai Xuan Zhang, Yu Zhuo Li, Jian Pei Zhang, Balaji Raghothamachar, Michael Dudley, Douglas Dukes, Victor Torres

Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Hitesh Jayaprakash, Manuel Belanche, Constantin Csato, Florian Krippendorf, Ulrike Grossner, Michael Rueb

Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Kai Xuan Zhang, Ze Yu Chen, Shan Shan Hu, Jian Pei Zhang, Yu Zhuo Li, Dong Lin Wu, Hao Chi Wang, Balaji Raghothamachar, Michael Dudley, Andrey Soukhojak

Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Yu Zhuo Li, Jian Pei Zhang, Ze Yu Chen, Hao Chi Wang, Kai Xuan Zhang, Shan Shan Hu, Balaji Raghothamachar, Albert A. Burk Jr, Kanwar Singh, Muhammad Ali Johar, Nadeemullah A. Mahadik, Robert E. Stahlbush, Michael Dudley

Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Dong Lee, Kirby Schmidt, Muhammad Ali Johar, Shanthi Subramanian, Albert Burk, Andy Souzis

Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Cristiano Calabretta, Nicolo Piluso, Ruggero Anzalone, Enzo Fontana, Giovanni Maira, Gabriele Bellocchi, Mario S. Alessandrino, Fabiana Vento, Chiara Nania, Salvatore Adamo, Sonia Zappalà, Giuseppe D'Arrigo, Elisa Vitanza, Nella Bentivegna, Alfio Russo, Giuseppe Arena, Andrea Severino

Chapter 3: Stacking Faults

Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers

Kazumi Takano, Yasuyuki Igarashi, Yohsuke Matsushita, Takuya Morita

Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Hiroki Niwa, Takanori Tanaka, Kazuya Tojima, Hiroyuki Amishiro, Yasuhiro Kagawa, Katsutoshi Sugawara, Tatsuro Watahiki

Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Nadja Kölbel, Birgit Kallinger, Christian Kranert, Stephan G. Müller, Alesa Fuchs, Tobias Erlbacher, Firas Faisal, Jörg Schulze

Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

Kazumi Takano, Yasuyuki Igarashi, Yohsuke Matsushita, Takuya Morita

Quantitative Analysis of Excess Minority Carrier Density and Critical Duration in UV Irradiation-Based Screening for Bipolar Degradation in 4H-SiC

Yasuyuki Igarashi, Kazumi Takano, Yohsuke Matsushita, Takuya Morita

Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Cristiano Calabretta, Cettina Bottari, Salvatore Adamo, Beatrice Carbone, Giovanni Maira, Fabiana Vento, Enzo Fontana, Nicolo Piluso, Mario S. Alessandrino, Alfio Russo, Patrick Fiorenza, Fabrizio Roccaforte, Andrea Severino

Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Takashi Yoda, Masaki Sano, Jun Kojima, Shoichi Onda, Anton Myalitsin, Kuniyuki Kakushima, Takayuki Ohba, Atsushi Oshiyama, Kenji Shiraishi

Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method

Ze Yu Chen, Jian Pei Zhang, Shan Shan Hu, Kai Xuan Zhang, Yu Zhuo Li, Hao Chi Wang, Balaji Raghothamachar, Ya Fei Liu, Campbell Bouch, Ryan Philpott, Scott Turchetti, Pete Schunemann, Michael Dudley

Micropipes in SiC die Observed by Molten KOH Etching

Fabiana Vento, Nicolò Piluso, Cristiano Calabretta, Chiara Nania, Domenica Raciti, Ruggero Anzalone, Andrea Severino

Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Jian Pei Zhang, Ze Yu Chen, Yu Zhuo Li, Shan Shan Hu, Balaji Raghothamachar, Ya Fei Liu, Campbell Bouch, Ryan Philpott, Scott Turchetti, Pete Schunemann, Michael Dudley

Polytype Transitions in Silicon Carbide: A Macroscopic View

Jörg Pezoldt, Vladislav Kurtash, Frank Neubert

Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Atsushi Shimbori, Ryota Wada, Nobuhiro Tokoro, Takashi Kuroi, Hiu Yung Wong, Alex Q. Huang

Chapter 4: Material Characterisation and Devices Processing

Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Alexander A. Lebedev, Klavdia S. Davydovskaya, V.V. Kozlovski, Michael E. Levinstein, D.A. Malevsky, Andrey E. Nikolaev, Alexey V. Sakharov, N.S. Solonitsyn

Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Lin Dong, Qi Qi Wu, Stefan Nufer

Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

László Makai, Julien Körfer, Zsombor Pap, Bálint Fodor, Mathias Rommel

A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Christian Stefan Gruber, Gregor Pobegen, Jürgen Smoliner

Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Robin Karhu, Volker Häublein, Marshall Wilson, Mathias Rommel, Birgit Kallinger

Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Saverio de Luca, Alfio S. Mancuso, Annamaria Muoio, Enrico Sangregorio, Francesco La Via

A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Han Wei Chen, Chiao Yang Cheng, Wei Liang Lai, Yew Chung Sermon Wu, Bing Yue Tsui

Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

Nicola Rinaldi, Luigi di Benedetto, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Mohamed Torky, Justin Lynch, Nick Yun, Stephen Mancini, Miguel Hinojosa, Aivars Lelis, Woongje Sung

Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Minori Matsuoka, Daiki Soda, Kosuke Miyazaki, Toshikazu Tanioka, Kazuya Tojima, Akira Kiyoi, Yasuhiro Kagawa, Tetsuya Nitta

4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Virginia Boldrini, Marica Canino, Marco Pieruccini, Vincenzo Carrano, Heinz C. Neitzert, Luigi di Benedetto, Claudio Santonastaso, Raffaele Buompane, Maria Lucia Mitsou, Nicola Casali, Ravi Prakash Yadav, Matthias Laubenstein, Cristian Degli Esposti Boschi, Alfredo Rubino, Alba Formicola, Lucio Gialanella

Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Shui You Zheng, Xing Jun Luo, Hua Xing Jiang

Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Dinuth C.Y.B. Yapa Mudiyanselage, Skylar deBoer, Stephen A. Mancini, Justin Lynch, Seung Yup Jang, Adam J. Morgan, Woongje Sung

Chapter 5: Wafer Processing

Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Bi Xue Li, Xing Zhang, Qiu Chen, Lin Lin Che, Jian Fei Zhang, Hao Yu Fan, Xian Gang Xu, Rong Kun Wang, Xiu Fang Chen

Effects of Processing Passes on Laser-Sliced SiC

Jian Fei Zhang, Bi Xue Li, Qiu Chen, Lin Lin Che, Xing Zhang, Hao Yu Fan, Yang Yang Jia, Jia Wei Wang, Yu Feng Xue, Rong Kun Wang, Xiu Fang Chen

Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Takanori Tanaka, Kyohei Akiyoshi, Kazumasa Iwanaga, Shunta Takahashi, Hiroshi Watanabe, Kenichi Hamano, Akihiko Furukawa

Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Kyohei Akiyoshi, Takanori Tanaka, Shunta Takahashi, Kazumasa Iwanaga, Kenichi Hamano, Akihiko Furukawa

A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Myung Beom Park, Jungwon Kim, Yigil Cho, Yun Ho Kim, Sam Jong Choi

Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Yuken Matsumura, Shunto Iden, Daisetsu Toh, Jumpei Yamada, Yasuhisa Sano

Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

David M. Lynch, Gregory L. Keaton, Christopher A. Lee, Alexander T. Bean

Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Tamara Fidler, Patrick Schmid

Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Norbert Bay, Athul Rathnakar, Xavier Gay, Wyatt Engler, Rahim Hamid, Franck Delahaye, Oliver Whear, Vishal A. Shah, Holger Kuehnlein

CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Georg Pfusterschmied, Michael Kusolitsch, Christopher Zellner, Marco Perazzi, Ting Qiang Yang, Ulrich Schmid

BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Shunya Hirano, Hyuk Kim, Satoru Takahashi, Shuzo Masui, Noboru Ohtani, Kozo Abe

Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Chen Hang Wu, Chao Jun Zhang, Shao Yuan Huang, Chao Chang Arthur Chen

Chapter 6: Interface, Dielectrics and Ohmic Contact in SiC Power Devices

Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Chia Lung Hung, Patrick Rabinzohn, Andrii Vozny, Tatiana Ivanova, Mikko Söderlund, Yi Kai Hsiao, Hao Chung Kuo

Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

Bongmook Lee, Veena Misra

Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Wei Chen Yu, Chia Lung Hung, Wei Cheng Lin, Wei Ting Lin, Tejender Singh Rawat, Yi Kai Hsiao, Tian Li Wu, Hao Chung Kuo

Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Harsha Vardhan Manchineni, Andre Wachowiak, Thomas Mikolajick

Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Maximilian Szabo, Tom Becker, Michael Jank, Tobias Erlbacher

Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Masao Sakuraba, Tatsunori Oki, Satoshi Watanabe, Shigeo Sato, Iori Morita, Tetsuya Ueno, Seima Sato, Hiroyuki Nagasawa, Yukimune Watanabe, Maki Suemitsu

Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Koushik Ramadoss, Joshua Holt, Lucien Date, Safdar Muhammad, Jesse Kalliomaki, Fernanda Albrechtvechietti, William Charles, Athena Pang, Shubhendra Jain, Benjamin Briggs, Ludovico Megalini, Michael Chudzik, Dallas Morisette, James A. Cooper

Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Heng Wang, Yang Ming Du, Ji Shu, Peng Wei Zhou, Ying Chen Yang, Kevin J. Chen

Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Xinkai Tian, Arne Benjamin Renz, Kyrylo Melnyk, Mustafa Akif Yildirm, Marco Boccarossa, Luca Maresca, Andrea Irace, James A. Gott, Nereus S. Agbo, Paul Taylor, Marina Antoniou, Philip Andrew Mawby, Peter M. Gammon

High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

Johannes Ziegler, Dick Scholten, Holger Bartolf, Jörg Schulze

Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Marilena Vivona, Salvatore Ethan Panasci, Marco Zignale, Valerio Votadoro, Salvatore di Franco, Emanuela Schilirò, Giuseppe Greco, Raffaella Lo Nigro, Patrick Fiorenza, Filippo Giannazzo, Fabrizio Roccaforte

NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Paolo Badalà, Corrado Bongiorno, Salvatore Sanzaro, Anna Bassi, Simone Rascunà, Gabriele Bellocchi, Massimo Boscaglia, Antonino La Magna, Alessandra Alberti

Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Maximilian Ley, Julian Kauth, Mathias Rommel, Björn Fischer, Alexander May, Jörg Schulze

Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Motoki Kobayashi, Seiji Ishikawa, Yuta Higashi, Hiroshi Sezaki, Mitsuo Okamoto, Shinsuke Harada, Kazutoshi Kojima

Chapter 7: Performance Analysis of SiC Power Devices

Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Suman Das, Daniel J. Lichtenwalner, Shane R. Stein, Sei Hyung Ryu

Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Andrei Konstantinov, Shagufta Naureen, Sergey Reshanov, Jang Kwon Lim

Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Yang Liu, Lei Yuan, Xue Song Liu, Tong Xiao Hou, Bo Peng, Ren Xu Jia, Yu Ming Zhang

1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Tommaso Stecconi, Roger Stark, Paula Reigosa, Nick Schneider, Coris Li, Leon Liang, Lars Knoll

Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Ilaria Matacena, Luca Maresca, Alessandro Borghese, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento

Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Shane R. Stein, Suman Das, Daniel J. Lichtenwalner, Sei Hyung Ryu

Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

Luigi di Benedetto, Nicola Rinaldi, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Nicola Rinaldi, Luigi di Benedetto, Mathias Rommel, Alexander May, Leander Baier, Rosalba Liguori, Alfredo Rubino, Gian Domenico Licciardo

Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Jenny Damcevska, Sima Dimitrijev, Daniel Haasmann, Philip Tanner, Fan Peng Zeng, Lan Luo, Ying Xin Cui, Yu Zhong, Ji Sheng Han

Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Pei Chun Liao, Kung Yen Lee, Ruei Ci Wu, Yan Yu Wen, Po Yu Cheng, Wei Xiang Wang

Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Hojung Lee, Justin Lynch, Stephen A. Mancini, Skylar deBoer, Miguel Hinojosa, Aivars Lelis, Woongje Sung

Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Dick Scholten, Johannes Ziegler, Wolfgang Feiler

Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Takeshi Tawara, Kensuke Takenaka, Syunki Narita, Shinsuke Harada

Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Boglárka Dikó, Oleg Rusch, Julien Körfer, Zsófia Kiss, Attila Sütő, Emeric Balogh

Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Kyrylo Melnyk, Arne Benjamin Renz, Mustafa Akif Yildirim, Nikolaos Iosifidis, Qin Ze Cao, Jose Ortiz-Gonzalez, Vishal A. Shah, James A. Gott, Peter Michael Gammon, Marina Antoniou

An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

Giorgian Borca-Tasciuc, T. Paul Chow

Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Giorgian Borca-Tasciuc, Reza Ghandi, Collin W. Hitchcock, Tat Sing Paul Chow

Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Marvin Gloth, Drinas Kelmendi, Hamed Azimi, Benjamin Weigt, Tobias Erlbacher

Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Ruei Ci Wu, Kung Yen Lee, Pei Chi Liao, Pei Chun Liao, Jui Chi Chu

Chapter 8: Design of SiC Power Devices

Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Marco Zignale, Patrick Fiorenza, Lucia Calcagno, Marina Antoniou, Filippo Giannazzo, Fabrizio Roccaforte

The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Jan Frederik Dick, Jannik Schwarberg, Mathias Rommel, Jörg Schulze

Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Jeff Joohyung Kim, Jae Hyung Park, Shane Stein, Daniel Lichtenwalner, Sei Hyung Ryu

High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

Shariare Hossain Rabbi, Justin Lynch, Stephen A. Mancini, Woongje Sung

Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Zhao Wen He, Giorgian Borca-Tasciuc, T. Paul Chow

Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Stephen A. Mancini, Dai Xin Chen, Seung Yup Jang, Andrew Binder, Richard Floyd, Robert Kaplar, Jack Flicker, Adam Morgan, Xiao Qing Song, Woongje Sung

Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Lan Luo, Yu Zhong, Peng Cui, Ziang Zhao, Lei Ge, Ying Xin Cui, Ming Sheng Xu, Xian Gang Xu, Ji Sheng Han, Yao Hao Wang

Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Seung Yup Jang, Skylar deBoer, Woongje Sung

Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Daichi Dansako, Tetsuya Abe, Kosuke Miyazaki, Toshikazu Tanioka, Yasuhiro Kagawa, Tetsuya Nitta

JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Zi Han Zhang, Lei Yuan, Kai Yu Chen, Xiao Wen Wang, Xue Song Liu, Tong Xiao Hou, Bo Peng, Gui Bao Wang, Mi Ao Yu, Ren Xu Jia, Yu Ming Zhang

2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Yuniarto Widjaja, Valerii Nebesnyi, Oleksandr Maistriuk, Asen Asenov, Nikolas Xeni, Tapas Dutta, Djamel Bensouiah, Servin Rathi, Leo Laborie, Robert Young, Yunyi Qi, David T. Clark

Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Hai Zhao Zhi, Si Rui Feng, Xiao Ping Wang, Xin Peng Lin, Yi Tian Jiang, Hao Lin Hu, Yu Xi Wan

Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Kailun Zhong, Vamsi Mulpuri, Vishank Talesara, Arash Salemi, Sumit Jadav, Siddarth Sundaresan

Study of SiC Thyristors with Integrated Temperature Sensors

Shu Hao Cheng, Kai Yu Chen, Zi Han Zhang, Xiao Wen Wang, Lei Yuan, Da Huo, Xue Song Liu, Tong Xiao Hou, Ren Xu Jia, Yu Ming Zhang

Chapter 9: SiC Devices for Quantum Applications and Harsh Radiation Environments

Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Luke Shoen, Jarod Remy, Lei Raymond Cao

Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters

Jannik H. Schwarberg, Jan Dick, Alexander May, Paweł Michałowski, Birgit Kallinger, Robert Kammel, Mathias Rommel, Jörg Schulze

Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Jannik H. Schwarberg, Christian Gobert, Fedor Hrunski, Alexander May, Wolfgang Knolle, Birgit Kallinger, Fabian Schmid, Mathias Rommel, Jörg Schulze

4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Jan Frederik Dick, Samuel Ultsch, Mathias Rommel, Jörg Schulze

A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

Fabian J. Magerl, Christophe Pixius, Julietta Förthner, Patrick Berwian, Eberhard Bär, Jörg Schulze

Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Zhi Wen Zhang, Hao Yuan, Xiao Yan Tang, Qing Wen Song

Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Chuan Han Chen, Cheng Shu Chang, I Chen Tsai, Der Sheng Chao, Bing Yue Tsui

High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Takahiro Makino, Tomoki Taoka, Kaito Yamamura, Takuro Tomita

Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Zhao Xu Song, Yu Tian, Zhe Yuan Zhang, Su Yu Xu, Xian Grui Fan, Yi Ren Yu, Jia Xing Wei, Si Yang Liu, Wei Feng Sun

Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

Virendra Kotagama, Arne Benjamin Renz, Kyrylo Melnyk, Zhao Xue Yuan, Valeria Kilchytska, Denis Flandre, Vishal A. Shah, Marina Antoniou, Peter Michael Gammon

In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Masayuki Yamamoto, Takanori Amamiya, Akinori Takeyama, Ryuya Hirose, Mikihiro Yuzuriha, Koji Nakayama, Hitoshi Umezawa, Takeharu Kuroiwa, Takahide Sato, Takahiro Makino, Takeshi Ohshima, Shin Ichiro Kuroki, Yasunori Tanaka

1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Zhao Xue Yuan, Virendra Kotagama, Bai Ling Zhou, Peter Gammon, Marina Antoniou

Chapter 10: Robustness and Reliability of SiC MOSFET Devices, SiC MOSFET Power Modules

Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Ruben Schnitzler, Tobias Fink, David Halmer, Dominik Koch, Ingmar Kallfass

Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Jeong Hwan Jang, Jang Kwon Lim, Kalle Ilves, Ki Sun Song, Dong In Yang, Young Jin Kim, Kyu Bong Yeon

A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages

Felix Hoffmann, Nando Kaminski

Temperature Dependence of the AC-BTI in SiC MOSFETs

Kohei Takei, Hideya Kishigami, Takashi Setoya

Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Ji Hong Zhu, Jing Jing Cui, Jin Ying Yu, Bao Hu, Ming Jiang, Bao Cheng Yuan

Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

Rajrupa Paul, Reza Soleimanzadeh, Stephan Wirths

Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Saeed Jahdi, Konstantinos Floros, Ingo Ludtke, Olayiwola Alatise, Martin Kuball

Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Madhu Lakshman Mysore, Rahul Vijaybhai Chavda, Josef Lutz, Thomas Basler

Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

Jia Le Wu, Zhi Wei Wang, Zhong Yuan Chen, Ran Li

Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Ayan K. Biswas, Callie Woods, Daniel J. Lichtenwalner, Shadi Sabri, Sei Hyung Ryu, Brett Hull, Adam Barkley, Donald A. Gajewski, Elif Balkas

Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Ke Wei, Wang Chen Li, Chen Xi Li, Hua Xing Jiang

Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Kung Yen Lee, Pei Chi Liao, Tsai Pei Lu, Ruei Ci Wu, Pei Chun Liao, Sang Mo Koo, Yi Pin Lee

Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Madhu Lakshman Mysore, Maximilian Goller, Rahul Vijaybhai Chavda, Mohamed Alaluss, Josef Lutz, Thomas Basler

Design Space Exploration of SiC Power Module Package via Surrogate Model

Lu Wan, Nicolo Ripamonti, Yan Fei Zhao, Reza Soleimanzadeh, Arne Schröder

Dynamic HV-H 3 TRB Test on 3.3 kV SiC MOSFET Modules 

Jan Hendrik Peters, Michael Hanf, Sven Clausner, Nando Kaminski

Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Peter S. Ying, Darwin Tsai, Alex Ma, George Wu, Akira Kamisawa, Shuichi Miyaoka, Nobuo Machida, Jimmy Wu

Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with  Different Wire Bond Layouts

Masaki Takahashi, Zhong Chao Sun, Stig Munk-Nielsen, Asger Bjørn Jørgensen

Low-Inductance Packaging Design for SiC Power MOSFET Modules

Zhao Bo Zhang, Renze Yu, Saeed Jahdi, Olayiwola Alatise, Francesco Iannuzzo, Bernard Stark

Keywords Index

Authors Index

Chapter 1: Bulk and Epitaxial Growth of SiC

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 1-5

doi: 10.4028/p-9Ysg3T

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-25

Revised:
2025-12-06

Accepted:
2026-02-28

Online:
2026-05-18

Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

Fusheng Zhang a*, Yongliang Shao b, Yongzhong Wu c, Baoguo Zhang d, Dong Shi e, Haixiao Hu f and Xiaopeng Hao g*

School of Materials Science and Engineering, Shandong Key Laboratory of Silicon Carbide Material, Qilu University of Technology (Shandong Academy of Science), Jinan 250353, China

a zfs@qlu.edu.cn, b  shaoyongliang@qlu.edu.cn, c  wuyz@qlu.edu.cn, d  zbg@qlu.edu.cn, e  shidong@qlu.edu.cn, f  huhaixiao@qlu.edu.cn, q  xphao@qlu.edu.cn

Keywords: basal plane dislocation, tantalum carbide coating, thermal gradient, defect reduction.

Abstract

Silicon Carbide ( SiC ) is a pivotal wide-bandgap semiconductor for high-power and highfrequency electronics. However, crystalline defects, particularly Basal Plane Dislocations (BPDs), severely degrade the performance and reliability of bipolar devices by nucleating stacking faults that cause fatal forward voltage drift. This work presents the successful growth of 8 -inch, 4∘ off-axis, ntype 4 H -SiC single crystals with significantly reduced BPD density via the Physical Vapor Transport (PVT) method using an improved reactor design. The key innovation involves replacing traditional graphite components with single or polycrystalline SiC for the seed holder and guide tube, subsequently coated with a thin ( 10μ m ) tantalum carbide ( TaC ) film. This design ensures thermal expansion coefficient matching and reduces thermal radiation emissivity. Etch pit density analysis revealed that the improved design reduced the overall BPD density from over 1027 cm−2 to a remarkably low 78 cm−2. Furthermore, it drastically improved the radial uniformity of BPD distribution by stabilizing the thermal gradient and suppressing parasitic polycrystalline nucleation, marking a critical advancement towards high-yield production of high-quality, large-diameter SiC substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

The relentless pursuit of greater energy efficiency and miniaturization in power electronics has propelled the adoption of wide-bandgap semiconductors, among which SiC stands as a cornerstone material. Its superior properties, including a wide band gap ( ~3.26eV for 4H−SiC ), high thermal conductivity ( ~4.9 W/cm·K ), exceptionally high electric breakdown field ( ~3MV/cm ), and large saturated electron drift velocity, enable devices to operate at higher temperatures, voltages, and switching frequencies with lower losses than traditional silicon-based devices [1,2]. These characteristics make SiC indispensable for a new generation of power converters, electric vehicle powertrains, and renewable energy systems.
However, the performance and reliability of SiC-based devices, particularly bipolar devices like PiN diodes and Insulated Gate Bipolar Transistors (IGBTs), are critically sensitive to crystalline imperfections in the substrate. Among these defects, Basal Plane Dislocations (BPDs) are notoriously detrimental. While a significant portion (>90%) of BPDs from the substrate can be converted into less harmful Threading Edge Dislocations (TEDs) in the initial epitaxial layer, the remaining BPDs pose a severe threat [3]. A perfect BPD in the hexagonal SiC crystal structure can readily dissociate into two partial dislocations, with a single Shockley-type stacking fault (SF) forming between them [4]. Under the injection of charge carriers during device operation, these stacking faults can nucleate and expand, leading to a progressive increase in the forward voltage drop ( Vf drift), ultimately causing device failure [5].
The formation and distribution of BPDs during bulk crystal growth are heavily influenced by the thermo-mechanical environment within the PVT furnace. Non-uniform temperature gradients, thermal stress induced by mismatched coefficients of thermal expansion (CTE) between the crystal and crucible components, and parasitic nucleation can all promote BPD generation and clustering,
especially at the crystal's periphery. Therefore, controlling the thermal field is paramount to reducing BPD density and improving its uniformity. This study addresses this challenge by introducing a novel reactor design that fundamentally alters the thermal and chemical environment, enabling the growth of 8 -inch SiC crystals with record-low and highly uniform BPD densities, a vital step towards unlocking the full potential of SiC power devices.

The Critical Challenge of BPDs

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

To fully appreciate the significance of this work, one must understand the nature of the BPD problem. BPDs are line defects whose Burgers vector lies in the {0001} basal plane of the 4H−SiC crystal structure. Their danger lies not in their existence as perfect dislocations in the substrate, but in their behavior during device fabrication and operation. During the epitaxial or bulk growth process, the high temperatures can cause a perfect BPD (with a Burgers vector of 1/3<11−20> ) to dissociate into two partial dislocations (e.g., 1/3<10−10> and 1/3<01−10> ), creating a stacking fault ribbon in between [6]. This is a metastable configuration. When a bipolar device is forward-biased, electronhole pair recombination provides the energy necessary for these partials to move, expanding the stacking fault area. This expanding fault acts as a carrier recombination center, reducing minority carrier lifetime and increasing the series resistance of the device, manifesting as the well-documented Vf drift [5]. This degradation is irreversible and fatal to the device's long-term reliability.
Consequently, the target for high-performance, high-reliability bipolar devices is a substrate with a BPD density as close to zero as possible. The industry standard, often achieved through various insitu or ex-situ conversion techniques during epitaxy, is to reduce BPDs in the epilayer to below 0.1 cm−2. However, this process is far more effective if the starting substrate has a low and uniform BPD density to begin with. Eliminating the problem at its source-the bulk crystal growth stage-is the most robust and economically viable strategy for high-yield manufacturing.

[picture]

(a)

Figure 1. (a)

[picture]

(b)

Figure 2. (b)

Fig. 1. The schematic diagrams of (a) traditional design and (b) improved design.

Experimental Setup: Traditional vs. Improved Design

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

The bulk growth of 4H−SiC single crystals is predominantly conducted using the PVT method. In a typical PVT setup, a polycrystalline SiC source is sublimated at high temperatures ( >2200∘C ) in a sealed graphite crucible. The resulting vapor species are transported to a cooler seed crystal, where they condense and form a single-crystal boule.
The experimental work presented here involved a direct comparison between two crucible designs: Traditional Design (Fig. 1a): This configuration utilized a seed holder and a surrounding guide tube fabricated from high-purity graphite. Improved Design (Fig. 1b): This novel configuration replaced the graphite components with parts machined from solid polycrystalline SiC or high-purity singlecrystal SiC ( N -doping concentration:4.0-12.0E+19 atoms cm−3 ). Critically, these SiC-based components were then uniformly coated with a ~10μ m thick film of TaC via a CVD process. Using both designs, 8 -inch, n-type, 4∘ off-axis 4 H -SiC single crystals were grown under otherwise identical process conditions (temperature, pressure, growth rate) to ensure a fair comparison. The SiC single crystal grown through improved design are shown in Fig. 2a. After cutting, grinding and polishing, a 200 mm SiC wafer was obtained (Fig. 2b).

[picture]

Fig. 2. The Photos of (a) SiC crystal grown through improved design and (b) processed SiC wafer.

Fig. 2. The Photos of (a) SiC crystal grown through improved design and (b) processed SiC wafer.

Defect Characterization Methodology

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

To quantify and visualize the BPD density in the grown crystals, standard wet chemical etching was employed. Wafers sliced from the grown boules were subjected to molten Potassium Hydroxide (KOH) at a temperature of approximately 500∘C for several minutes. KOH etches the SiC crystal at a much higher rate at dislocation sites than in the perfect crystal, creating characteristic hexagonal etch pits that correspond to the locations of Threading Screw Dislocations (TSDs) and oval-shaped pits that correspond to BPDs.
The etched surfaces were then analyzed using the FabXLab optical microscope equipped with automated image recognition software. This system scans the wafer surface, identifies and classifies the etch pits based on their morphology and size, and calculates their areal density ( cm−2 ), providing a precise and statistically robust map of defect distribution across the entire wafer.

[picture]

Fig. 3. The distribution of BPDs density in SiC crystal grown in (a) traditional design and (b) improved design.

Fig. 3. The distribution of BPDs density in SiC crystal grown in (a) traditional design and (b) improved design.

Results: Dramatic Reduction in BPD Density

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

The results of the etch pit density (EPD) mapping were striking and unequivocal. Crystal from Traditional Design (Fig. 3a): The BPD density was measured to be as high as 1027 cm−2. More importantly, the distribution was highly non-uniform. The edge of the wafer showed a very high density of BPDs, forming a pronounced ring-of-fire pattern. While the central region exhibited a moderately lower density. This radial gradient is a classic signature of thermo-mechanical stressinduced defect generation.
Crystal from Improved Design (Fig. 3b): Conversely, the improved design yielded crystals with a markedly lower BPD density, averaging only 78 cm−2. This represents a reduction of more than an order of magnitude and a significantly more uniform radial distribution. The extreme clustering at the edge was eliminated, resulting in a wafer with consistent low defect density from center to edge.

Mechanism: The Role of Thermal Management and CTE Matching

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

The dramatic improvement in crystal quality can be attributed to the superior thermal and mechanical properties of the new crucible components.

Problems with the Traditional Graphite Design

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

Coefficient of Thermal Expansion (CTE) Mismatch: Graphite has a CTE of ~4−6×10−6/K (in-plane), while 4 H -SiC has a CTE of ~4.2×10−6/K along the a-axis and ~4.7×10−6/K along the c-axis. While these values seem close, any slight mismatch, combined with the extreme temperature gradients (often 5−20∘C/cm ) during growth and cool-down, generates significant shear stress at the interface between the crystal and the holder. This stress is a primary driver for the nucleation and propagation of dislocations, particularly at the vulnerable edge of the growing crystal.
High Thermal Emissivity and Conductivity: Graphite has a high thermal radiation emissivity ( 0.7 0.8 ) and is a good thermal conductor. This leads to two issues: Firstly, it creates a steeper and potentially unstable lateral temperature gradient ( ∂2 T/∂x2 ) at the crystal's periphery. Secondly, it causes excessive heat loss through the walls, cooling the inner surface of the guide tube. This cooling promotes the unwanted condensation and parasitic nucleation of SiC polycrystals on the graphite surface. These parasitic crystals disrupt the vapor flow, create local hot spots, and further distort the thermal field, exacerbating the non-uniform stress and BPD formation at the crystal edge.

Advantages of the Improved SiC/TaC Design

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

Perfect CTE Matching: By manufacturing the seed holder and guide tube from SiC (either poly or single crystal), their thermal expansion is perfectly synchronized with that of the growing SiC boule. This eliminates the interfacial shear stress caused by CTE mismatch during temperature changes, providing a much more stable and mechanically benign environment for crystal growth.
Low Emissivity TaC Coating: TaC is a refractory ceramic with a very low thermal radiation emissivity of approximately 0.3 . This coating acts as a thermal barrier. It reduces radial heat loss from the crystal and crucible assembly, leading to a flatter, more stable, and more axially symmetric thermal profile. A smaller second derivative of temperature ( ∂2 T/∂x2 ) means reduced thermal stress. Suppression of Parasitic Nucleation: The combination of a stable, hotter wall temperature (due to lower heat loss) and the chemical inertness of the TaC surface makes it extremely difficult for SiC vapor species to nucleate and form polycrystalline deposits on the guide tube. This maintains a clean, predictable vapor transport path and a consistent thermal field throughout the long growth process. In essence, the improved design transforms the growth environment from one prone to fluctuations and steep gradients (traditional) to one that is stable, uniform, and minimally stressful (improved). This directly translates to a reduction in the driving force for dislocation generation and multiplication, yielding a crystal with far fewer defects and exceptional radial uniformity.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

This study achieved a significant reduction in harmful BPDs in 8-inch 4H-SiC crystals by innovating the PVT reactor design. Traditional graphite components (seed holder and guide tube) were replaced with SiC-based parts coated with a thin TaC layer. This modification eliminated thermal expansion mismatch stress and stabilized the thermal gradient due to TaC's low emissivity, thereby suppressing parasitic nucleation. Results confirmed an order-of-magnitude reduction in average BPD density, from 1027 cm−2 to just 78 cm−2, while drastically improving radial uniformity by eliminating edgeclustering defects. This work provides a highly effective method for producing high-quality, largediameter substrates, directly addressing the major bottleneck for reliable SiC bipolar power devices and facilitating their broader industrial application.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.1.pdf

Choyke, W. J., and G. Pensl. Physical properties of SiC, Mrs Bulletin, 22.3 (1997): 25-29.

Kimoto T., Cooper J. A., Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, Wiley, 2014.

Bergman J P, Lendenmann H, Nilsson P Å, et al., Crystal Defects as Source of Anomalous Forward Voltage Increase in 4H-SiC Diodes, Materials Science Forum, 353(2001).

T Stahlbush, Robert E., et al. Evolution of basal plane dislocations during 4H-SiC epitaxial growth. Materials Science Forum, 600(2009).

Stahlbush, R. E., et al. Effects of basal plane dislocations on SiC power device reliability. 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 2018.

Pirouz, Pirouz, and Augustinas Galeckas. Degradation of SiC bipolar devices: a review of likely causes and recent advances in its understanding. ECS Transactions, 41.8 (2011): 225.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 7-13

doi: 10.4028/p-L2E5l7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-12

Accepted:
2026-02-23

Online:
2026-05-18

300 mm4H-SiC Crystal and Substrate Development

The original version of this paper is available on https://www.scientific.net/SSP.393.7.pdf

Yani Pan 1,a, Chao Gao 1, b*, Yu Zhou 1,c, Xiu Xiu Ning 1, d, Yin Li 1,e, Ying Guo 1,f, Hong Yu Peng 1,g, Yanmin Zong 1,2,h

1 SICC Co., Ltd, Jinan 250000, China.

2 Shandong Provincial Key laboratory of Silicon Carbide Materials, Jinan 250000, China.

a  panyani@sicc.cc, b  gaochao@sicc.cc, c  zhouyu@sicc.cc, d  ningxiuxiu@sicc.cc, eliyin@sicc.cc, f  guoying@sicc.cc, g  penghongyu@sicc.cc, h  zym@sicc.cc,

Keywords: 300 mm 4 H -SiC crystal, Crystal diameter expansion, 12-inch 4H-SiC substrate, thermal stress, radial temperature gradient.

Abstract

The development of integrated circuits (IC) is mainly driven by the advanced processes and increased silicon wafer diameter in the past several decades. It is technically believed that the diameter of 300 mm for SiC wafer is too difficult to be achieved since SiC crystal diameter expansion is a long and tough process, the growth process of which is different from that of silicon crystal. Herein, we demonstrate the diameter expansion process of SiC crystal from 200 mm to 300 mm using physical vapor transportation (PVT) method and show the world's first 300 mm4H−SiC single crystal substrate with 100%4H polytype. The driving force of crystal diameter expansion and resultant thermal stress are discussed in this paper. Based on the successful preparation of 300 mm SiC seed crystal, 12-inch high-purity, conductive n-type & p-type SiC substrates are subsequently fabricated. Quality characterization of the 300 mm SiC substrate shows very low micropipe and threading screw dislocation density below 0.05 cm−2 and 120 cm−2, respectively. Furthermore, both 500μ m and 750μ m thickness substrates are fabricated with bow and warp values lower than 10μ m and 30μ m, indicating high quality 300 mm substrates applicable in power devices and other emerging areas.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.7.pdf

4H−SiC is one of the most important and promising semiconductor materials due to its excellent electrical, thermal, mechanical and optical properties[1]. Semi-insulating SiC substrates are now used to fabricate radio frequency devices applied in 5G station, while conductive SiC substrates are used in powder devices which plays important roles in electrical vehicles (EVs), photovoltaics (PVs) etc. Meanwhile, new SiC applications such as waveguide in AR glasses and interposer in advanced packaging[2] are emerging which require even larger diameter SiC substrates. Obtaining the first 300mm SiC substrate requires fabricating a starting 300 mm SiC seed crystal through diameter expansion-a process that is particularly challenging in PVT growth due to the frequent occurrence of polycrystal/defect formation and crystal stress during the multiple dynamic stages of crystal enlargement[3,4]. To suppress crystal breakage and polytype formation during SiC crystal diameter expansion, multiple runs of diameter expansion processes is necessary to obtain enlarged crystal diameter. This requires continuously new designs of crystal growth chamber, thermal field, growth process, wafering tools and processes since each iteration generates new crystals with non-standard diameters (e.g. 260 mm ).
Herein, we demonstrate successfully prepared 300 mm SiC substrates through diameter expansion process from 200 mm to 300 mm . Lateral growth of SiC crystal driven by the radial temperature gradient (RTG) is elaborated, where maximum growth diameter expansion and minimum residual thermal stress are well balanced[5,6,7]. The quality of 300 mm SiC substrates are characterized with Raman microscopy and Synchrotron X-ray Topography. Furthermore, 300 mm high-purity and conductive n&p type SiC substrates are shown in this paper.

Experiment

The original version of this paper is available on https://www.scientific.net/SSP.393.7.pdf

To simulate SiC crystal growth process and calculate the temperature distribution in the growth chamber, commercial STR_VR software is adopted[8]. The software is also used to analyze the thermal stress in the grown SiC crystal in the models. Based on the thermal field and crystal thermal stress analysis, temperature gradient and chamber structure used for each run of crystal diameter expansion are developed and optimized.
4H−SiC crystals in the diameter expansion process are grown with PVT method. The growth temperature and pressure are set at 2000−2300∘C and 5−50mbar respectively. Nitrogen and argon are introduced into the growth chamber as doping and protective gases[9]. A self-produced 200 mm4H− SiC seed crystal with 4∘ off-cut is used at the beginning of crystal diameter expansion process. After each run of crystal growth, newly grown SiC crystal with expanded diameter is fabricated into seed crystal used in the next generation. Meanwhile, the internal structure of crystal growth chamber and the external insulation structure have been modified at each generation[10,11]. Simultaneously, corresponding wafering tools are also customized for this process.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.393.7.pdf

It's crucial to set up proper temperature gradients to drive the crystal grow in both radial and axial direction in SiC crystal diameter expansion process. Theoretically, larger RTG is preferred for lateral growth, however, a large RTG will inevitably introduce thermal stress in crystal which leads to the formation of defects or even crystal breakage. On the other hand, a small RTG will not drive monocrystal grow efficiently and polycrystal may appear in the periphery instead. Therefore, it is of great importance to balance temperature gradient and thermal stress during the continuous diameter processes.

[picture]

Fig. 1. (a) Calculation of SiC crystal thermal stress under different conditions, (b) Constant diameter crystal growth, (c) Diameter expansion crystal growth.

Fig. 1. (a) Calculation of SiC crystal thermal stress under different conditions, (b) Constant diameter crystal growth, (c) Diameter expansion crystal growth.

Based on the discussion above, the design of the crystal diameter expansion process is schematically shown in Fig.1. Different from the constant diameter crystal growth (CDCG) process, a tilt angle in the crystal growth periphery and corresponding RTG is designed in expanded diameter crystal growth (EDCG), which allows crystal diameter to increase gradually at the start of crystal growth. Fig. 1 (a) shows the calculation of the crystal thermal stress of CDCG and EDCG process (Fig. 1 (b) and (c)), respectively. Calculation results indicate that crystal thermal stress increases with thickness due to
the stress accumulation. Even with the same temperature gradient, SiC crystal diameter expansion process has larger thermal stress in the crystal from the start of the growth, and its stress increasing rate is almost twice of that in constant-diameter grown crystal. The calculation result in Fig. 1 indicates that the maximum RTG should be carefully designed according to the thermal stress in the diameter expanded crystal.
In order to further illustrate the correlation between lateral driving force and crystal thermal stress, different RTG curve is set on the seed surface to perform diameter expansion growth by modifying the thermal field structure (Fig. 2 (a)). Thermal stress distribution in grown crystal and corresponding RTG curve along the radial direction on the seed crystal surface are shown in Fig.2(b) and (c) respectively. As shown in Fig. 2 (c), RTG value is larger at the edge of crystal compared to that in the center, which facilitates the lateral growth of the crystals while maintaining relatively small stress in the entire crystal lattice. Calculated thermal stress in the diameter expansion area of the crystal is marked by the red dotted box in Fig. 2 (b), which is in good correlation with the plot of the RTG.

[picture]

Fig. 2. (a) Schematic illustration of diameter expansion crystal. (b) The distribution of the thermal stress in crystal. (c) The RTG curve at seed crystal surface.

Fig. 2. (a) Schematic illustration of diameter expansion crystal. (b) The distribution of the thermal stress in crystal. (c) The RTG curve at seed crystal surface.

A suitable temperature gradient range should be derived for various diameter of crystals. A tougher balance between temperature gradient and crystal stress is speculated with diameter increasing in the EDCG process, as shown in Fig. 3 (a). The best scheme for a successful crystal diameter expansion process should be the optimized combination of enlarged diameter, temperature gradient and thermal stress. Theoretically, free-style crystal growth without constraints in diameter is beneficial for both diameter enlargement and quality control. However, the actual situation is that hexagonality of 4H− SiC and the distribution of vapor species lead to much larger convexity, causing larger thermal stress with less effective diameter enlargement. To resolve this problem, a tilt graphite ring which guides crystal growth with expansion angle ( θ ) is applied. The correlation between θ and thermal gradient can be expressed as,

θ=arctanGrGa.(1)

where Gr is radial temperature gradient and Ga is axial temperature gradient. During crystal growth, the expansion angle θ depends on the other two parameters and a desirable diameter increase can be realized by adjusting Gr and Ga. Furthermore, curve fitting between the increase of crystal diameter (d) and temperature gradient ( Gr/Ga ) in Fig. 3 (b) is derived as below,

d=115.3GrGa−13.16(2)

When the Gr/Ga value exceeds 0.25 , an effective monocrystal diameter expansion larger than 15 mm can be achieved. which comes with a high ratio of crystal breakage (Fig. 3 (c)) caused by thermal stress. If Gr/Ga value is set to be smaller than 0.15 , insufficient driving force will lead to extremely slow monocrystal growth in radial direction, resulting in polycrystal deposition (Fig.3(d)). Then, RTG value in the range of 0.7~2.4∘C/cm and diameter expansion angle in the range of 8∘~14∘ is set up. In order to achieve desirable crystal diameter expansion at different process nodes, it is important to design corresponding crucibles, insulation structures and RTG values based on the achieved diameter of the seed crystal. Therefore, various thermal field structures and temperature gradient are designed for each iteration of EDCG process.

[picture]

Fig. 3. (a) Calculation of the thermal stress during crystal expansion process. (b) The correlation between the effective expansion diameter of the crystal, the edge Gr/Ga value and guide tube angle. (c) Cracked crystals. (d) Crystal peripheral region with failed expansion.

Fig. 3. (a) Calculation of the thermal stress during crystal expansion process. (b) The correlation between the effective expansion diameter of the crystal, the edge G r / G a value and guide tube angle. (c) Cracked crystals. (d) Crystal peripheral region with failed expansion.

Based on theoretical analysis and crystal growth experiments, SiC crystal diameter is successfully enlarged from 200 mm to 300 mm . Each generation of expanded SiC crystal, fabricated SiC substrates and the eventually obtained 300 mm SiC crystal and substrate are shown in Fig.4. As the 300 mm SiC seed substrates are ready, CDCG process is carried out for 300 mm SiC crystal growth. As shown in Fig. 5, high-purity and conductive n-type & p-type SiC substrates are successfully fabricated, which covers all series of SiC substrates and all areas in which SiC material can be adopted.

[picture]

Fig. 4. SiC crystals and corresponding substrates with various diameter during expansion process.

Fig. 4. SiC crystals and corresponding substrates with various diameter during expansion process.

[picture]

Fig. 5. Images of fabricated 12 inch n-type SiC substrate, 12 inch high-purity SiC substrate and 12 inch p-type SiC substrate.

Fig. 5. Images of fabricated 12 inch n-type SiC substrate, 12 inch high-purity SiC substrate and 12 inch p-type SiC substrate.

The polytype and thermal stress of the 300 mm SiC substrate are characterized using micro-Raman. Fig. 6 (a) shows a FTO (2/4) E2 peak locates at 776−777 cm−1, which is the typical 4H−SiC crystal. Mapping data (Fig. 6 (b)) of the whole 300 mm substrate shows consistent 776.5 cm−1 Raman spectrum peak, indicating that the 300 mm SiC substrate is 100%4H polytype. Additionally, negilible peak shift is observed at 776.5 cm−1 in the Raman spectrum, indicating that the thermal stress is small in 300 mm substrate since Raman spectrum is sensitive to the crystal lattice strain[12]. Calculation from the spectrum shift results in a typical stress value of 3.5 MPa , which is comparable to the current 200 mm SiC substrates. Fig. 6 (c) further shows the threading screw dislocation (TSD) density characterization by XRT. Average micropipe and TSD density in the 300 mm n type 4H-SiC substrate is measured to be less than 0.05 cm−2 and 120 cm−2, this almost replicates the TSD density of initial 200 mm4H−SiC seed substrate when diameter expansion process started, which further shows the diameter expansion process is well designed without deteriorating the initial crystal quality.

[picture]

Fig. 6. Raman and XRT characterization of the 300 mm4H−SiC substrates.

Fig. 6. Raman and XRT characterization of the 300 m m 4 H − S i C substrates.

One concern of 300 mm SiC substrates is the warpage increase. Fig. 7 shows the typical values of fabricated 750μ m SiC substrates, in which the bow and warp values are controlled well below 10μ m and 30μ m, respectively. Besides, the total thickness variation (TTV) value is controlled below 6μ m, which indicates applicable substrates for device fabrication process.

[picture]

Fig. 7. Wafering quality characterization of 750μ m thickness 300 mm4H−SiC substrates

Fig. 7. Wafering quality characterization of 750 μ m thickness 300 m m 4 H − S i C substrates

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.7.pdf

The first 300 mm 4H-SiC substrates is demonstrated in November 2024 by SICC. Detailed diameter expansion process of 4H−SiC crystals from 200 mm to 300 mm is shown in this paper. Correlation between the temperature gradient and thermal stress as well as the process window for successful diameter expansion process is elaborated based on simulation and experiments. Based on the expansion obtained 300 mm 4H-SiC seed, high quality 300 mm high-purity and conductive n-type & p-type SiC substrates are subsequently fabricated. The 300 mm SiC substrate is 100%4H polytype with TSD density below 120 cm−2. Substrates with both thickness 500μ m and 750μ m are fabricated with bow and warp values smaller than 10μ m and 30μ m, respectively. High quality of 300 mm SiC substrates will support future development of power devices, waveguide in AR glass as well as thermal management in advanced packaging.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.7.pdf

Wellmann, P. J., Arzig, M., Ihle, J., Kollmuss, M., Steiner, J., & Mauceri, M., et al. "Review of Sublimation Growth of SiC Bulk Crystals," Materials Science Forum. (2022).

Chen, Boqu, et al. "Ultra-Thin, Ultra-Light, Rainbow-Free AR Glasses Based on Single-Layer Full-Color SiC Diffrcative Waveguide," (2024).

Hahn, Peter O. "The 300 mm silicon wafer-a cost and technology challenge," Microelectronic Engineering. 56(1/2), 3-13 (2001).

Yang, X.L., Pan, Y.N., Gao, C., Liang, Q.R., Wang, L.P., et al. "Development of High Quality 8 inch 4H-SiC Substrates," Solid State Phenomena. 344, 41-46 (2023).

Miyazaki, K, et al. "Effect of crucible thermal conductivity on dislocation distribution in crystals in a silicon carbide physical vapor transport furnace," Journal of Crystal Growth. 603, (2023).

Choi, Jung Woo, et al. "Modified Hot-Zone Design for Large Diameter 4H-SiC Single Crystal Growth," Materials Science Forum. 963, 18-21 (2019).

Steiner, Johannes, and P. J. Wellmann. "Impact of Mechanical Stress and Nitrogen Doping on the Defect Distribution in the Initial Stage of the PVT Growth Process," Materials (Basel, Switzerland) 15, 5 (2022).

Ha, Minh Tan, and S. M. Jeong. "A review of the simulation studies on the bulk growth of silicon carbide single crystals." Journal of the Korean Ceramic Society, 2, 59 (2022).

Hu, S., Liu, Y., Cheng, Q., Chen, Z., Tong, X., & Raghothamachar, B., et al. "Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals," Journal of Crystal Growth. 628 (2024).

Xu B., Han X.F., Xu S.C., et al., "Optimization of the Thermal Field of 8-Inch SiC Crystal Growth by PVT Method with "3 Separation Heater Method," SSRN Electronic Journal. (2023).

Yang N., Song B., Wang W., et al. "Control of the temperature field by double induction coils for growth of large-sized SiC single crystals via the physical vapor transport technique," (2022)

Chen P.C., Miao W.C., Ahmed T., et al. "Defect Inspection Techniques in SiC," Nanoscale Research Letters. 17, 30 (2022).

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 15-20

doi: 10.4028/p-z4K8Ju

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-18

Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates

The original version of this paper is available on https://www.scientific.net/SSP.393.15.pdf

Chiara Nania 1,a*, Ruggero Anzalone 1, b, Domenica Raciti 1,c, Nicolò Piluso 1, d, Fabiana Vento 1,e, Cristiano Calabretta 1,f and Andrea Severino 1, g

1 STMicroelectronics, Stradale Primosole, 50, Catania 95100, Italy

a* chiara.nania@st.com, b  ruggero.anzalone@st.com, c  domenica.raciti@st.com, d  nicolo.piluso@st.com, efabiana.vento@st.com, f  cristiano.calabretta01@st.com, g  andrea.severino@st.com

Abstract

H}-\mathrm{SiC}) is a wide-bandgap semiconductor that has become essential for power electronics due to its large bandgap, high critical electric field, and excellent thermal stability. Within the {0001} basal orientation, the two polar surfaces - Si-face and C-face - exhibit distinct behaviours during chemical vapor deposition (CVD) homoepitaxy, with direct implications for device performance and manufacturing. In this work, n-type epitaxial layers were deposited on 150 mm,4∘ off-axis Si-face and C-face substrates under identical conditions in a single-wafer hot-wall LP-CVD reactor ( T>1600∘C,P=3.0kPa,C/Si=1.05, silane/propane/ethylene precursors, N2 doping, HCl additive). Characterization analysis revealed pronounced polarity-dependent differences. AFM analysis showed that C-face epilayers exhibited smoother surfaces and reduced step bunching compared with Si-face layers. Optical and photoluminescence inspections show polarity-dependent defect propagation, with the C-face displaying reduced replication of extended defects under the explored conditions. However, nitrogen incorporation on the C-face orientation was more than 25× higher than Si-face orientation and displayed poor uniformity, highlighting the limited effectiveness of site-competition epitaxy on this orientation. In contrast, the Si-face provides tighter control of doping concentration and lateral uniformity, albeit with higher step bunching and rougher surfaces. These findings emphasize a fundamental trade-off in 4H−SiC homoepitaxy: the C -face offers morphological and structural advantages, while the Si -face ensures superior doping control and process stability. A deeper understanding of these polarity-dependent mechanisms is essential to optimize epitaxial growth strategies and to enable the design of high-performance SiC power devices.

Keywords: 4H−SiC, LP-CVD, epitaxial growth, defectivity, surface roughness, N2 incorporation.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.15.pdf

Silicon carbide ( SiC ), and notably the 4 H polytype, has emerged in the power semiconductor market due to its excellent physical properties, such as wide bandgap and high electrical breakdown field, which make it ideal for high-power, high-frequency and high-temperature applications. Among the different crystallographic orientations of 4H−SiC, the {0001} plane has two distinct polar faces: the Si -face (silicon termination) and the C -face (carbon termination). Although the Si -face is currently the most widely used in industrial production and research, the C-face exhibits structural and chemical features making it of growing interest, especially regarding the epitaxial growth and performance of MOS (metal-oxide-semiconductor) structures [1,2].

From an epitaxial growth perspective, the two polarities show markedly different behaviours. The Si-face has been extensively studied and optimized, largely because it offers a relatively wide process window for step-flow homoepitaxy under chemical vapor deposition (CVD), particularly when off-axis substrates are used to suppress polytype inclusions [3-5]. The introduction of chlorinated chemistries (e.g., HCl , dichlorosilane, methyltrichlorosilane) has further stabilized
growth on the Si-face, enabling high growth rates (up to ~100μ m/h ) while suppressing silicon droplet formation and 3C-SiC inclusions. The C-face, on the other hand, is characterized by a higher chemical reactivity and faster etching in hydrogen ambient, which can result in smoother step structures and lower surface roughness compared to the Si -face under optimized conditions. These characteristics are also linked to differences in step bunching behaviour, terrace stability, and surface free energy.

Defect formation is another crucial factor distinguishing the two polarities. On Si-face substrates, triangular defects and inclusions of 3C-SiC are typical, although several strategies involving growth rate optimization, C/Si ratio control, and Cl -based chemistry have been developed to mitigate them. In contrast, the C-face has been reported to promote lower replication of basal plane dislocations (BPDs) and a higher probability of their conversion into threading edge dislocations (TEDs), which is beneficial for device reliability, particularly in bipolar devices where BPDs are known to degrade performance. However, the C -face remains more susceptible to 3C inclusions when growth parameters are not tightly controlled, and its epitaxial layers may suffer from non-uniformities at very high growth rates [5, 6].

Doping incorporation is strongly polarity-dependent. As well known, nitrogen incorporation is more efficient on the C-face, leading to higher and less controllable background doping levels compared to the Si-face under identical conditions. This behaviour has been linked to differences in surface kinetics and adsorption mechanisms, with simulations suggesting that the Si-face exhibits a stronger dependence on the C/Si ratio and growth temperature, whereas the C-face is governed by more complex surface-chemistry interactions. Aluminium incorporation ( p-type doping) is also influenced by polarity, with distinct activation energies and incorporation pathways reported on the two surfaces. These differences make doping control on the C-face more challenging, despite its potential advantages in structural quality [7,8].

Finally, the SiO2/SiC interface quality is another critical parameter. The Si-face generally provides more stable and lower-defect-density MOS interfaces, while the C-face, although exhibiting a significantly faster oxidation rate (approximately an order of magnitude higher), typically shows higher interface trap densities and degraded channel mobility [7, 9]. Nevertheless, the unique chemical and structural features of the C-face suggest that, with improved understanding of epitaxial mechanisms and interface engineering, it could open new opportunities for enhancing MOS performance, particularly in applications where high mobility is essential.

Experiment Set-Up

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In order to obtain a systematic and direct comparison of the effects of crystallographic polarity on the homoepitaxial growth of 4H−SiC, with particular attention to their relevance in the fabrication of power electronic devices, n-type epitaxial layers were grown on 150 mm substrates, cut at 4∘ offaxis, with opposite polar terminations (Si-face and C-face). Both surfaces of the {0001} basal plane, although being of great technological interest, are known to exhibit substantial differences in terms of surface energy, chemical reactivity, and dopant incorporation mechanisms. Understanding these differences under controlled and comparable experimental conditions is therefore crucial to defining the advantages and limitations of each orientation in epitaxy for industrial applications. To ensure that the observed variations could be attributed solely to the substrate polarity, all other process parameters - growth temperature, reactor pressure, precursor flows, C/Si ratio, and dopant flow were kept constant in all depositions.

Growth

The original version of this paper is available on https://www.scientific.net/SSP.393.15.pdf

Growth was carried out in a single-wafer hot-wall LP-CVD reactor at temperature above 1600∘C, a total pressure of 3.0 kPa , and a fixed C/Si ratio of 1.05. Silane (SiH4), propane (C3H8), and
ethylene (C2H4) were employed as silicon and carbon precursors, with nitrogen (N2) introduced as the dopant to achieve n-type conductivity and hydrogen (H2) as carrier gas. Hydrogen chloride (HCl) was added to suppress silicon droplet formation on the growing surface.

The target epilayer specifications, consistent with requirements for medium- and high-voltage devices, included a thickness of approximately 9.5μ m and a doping concentration of ~6×1016 cm−3.

A total of six epitaxial runs were performed - three on Si-face and three on C-face substrates allowing a controlled assessment of growth morphology, defectivity, and dopant incorporation as a function of crystallographic polarity.

Characterization

The original version of this paper is available on https://www.scientific.net/SSP.393.15.pdf

The thickness and doping concentration distribution in the epitaxial layers, expressed as [maximum value - minimum value]/mean [%], was assessed using Fourier Transform Infrared (FTIR) spectrometry and Mercury-Probe Capacitance Voltage (Hg-CV), respectively.

The defectivity characterization was conducted using Candela and Altair tools, both from KLA. The Candela tool uses highly sensitive optical technology able to simultaneously measure scattering intensity at various angles of incidence, topographic variations, surface reflectivity and phase shift, and photoluminescence for the detection and classification of crystallographic defects as stacking faults. A simultaneous Bright-field and Dark-field optical path to capture a variety of defects in the sub-micron to 5 -micron range is used in the Altair optical microscope. The surface roughness was tested by Atomic Force Microscopy (AFM).

AFM analysis highlights substantial morphological differences between the two polarities. On the Si-face, epitaxial growth exhibits a pronounced tendency toward step bunching, which results in a significant increase in surface roughness compared to that measured on the C-face. Moreover, surface roughness on the Si-face is not uniform across the wafer diameter: greater roughness is observed towards the edges, caused by thermal gradients and precursor flow distribution within the reactor (Fig. 1). Conversely, growth on the C-face produces more regular surfaces, characterized by lower roughness and the absence of macroscopic step bunching. This difference is attributable to the higher chemical reactivity of the carbon termination, which promotes more isotropic growth. However, this enhanced reactivity is coupled with greater susceptibility to the formation of point defects, limiting the ability to achieve electrically uniform and well-controlled epilayers.

[picture]

Fig. 1. AFM images of 4H−SiC epitaxial layers grown at same growth conditions on 4∘ off-axis C face and Si -face substrates in two different wafer position (center and edge). Scan size is 5×5e20×20μ m2, respectively, for the samples.

Fig. 1. AFM images of 4 H − S i C epitaxial layers grown at same growth conditions on 4 ∘ off-axis C face and Si -face substrates in two different wafer position (center and edge). Scan size is 5 × 5 e 20 × 20 μ m 2 , respectively, for the samples.

Defectivity inspections further confirmed the crystallographic polarities dependence of epitaxial quality. Samples grown on C-face substrates exhibit higher density of triangular defects than their counterparts deposited on Si-face substrates. These triangular features, associated with stacking faults and local lattice instabilities, originate from the enhanced chemical reactivity and the less controlled growth dynamics typical of carbon termination. The higher incidence of these defects on the C-face represents a significant limitation in terms of application, as it can compromise the electrical stability of the epilayers, inducing preferential leakage paths, and reducing the reliability of power devices manufactured on this orientation.

In addition to morphological and defectivity differences, doping incorporation strongly depends on polarity. Despite identical epitaxial growth conditions - including precursor fluxes, dopant flow, and C/Si ratio - the nitrogen concentration in layers grown on the C-face was found to be more than 25 times higher than in those grown on the Si-face, significantly exceeding the target value. This discrepancy is linked to the distinct surface structure and higher reactivity of the C-face, which make nitrogen incorporation far less controllable. On the Si-face, the site competition mechanism between carbon and nitrogen allows the C/Si ratio to effectively modulate dopant incorporation, leading to more reproducible and uniform doping profiles. In contrast, nitrogen on the C-face incorporates more readily and non-selectively, irrespective of the C/Si ratio. As a result, the doping distribution on the C-face shows greater dispersion and irregularity, whereas the Si-face displays a flatter and more controlled profile (Fig. 2). By comparison, the thickness distribution appears unaffected by polarity, showing no measurable difference between C -face and Si -face growth.

[picture]

Fig. 2. The left graph depicts the doping distribution, normalized against the target value ( ~6×1016 cm−3 ), along the wafer diameter grown on the C -face (in orange) and Si -face (in blue) 4H−SiC, respectively. Doping distribution maps for growth on the Si and C -face are displayed on the right.

Fig. 2. The left graph depicts the doping distribution, normalized against the target value ( ~ 6 × 10 16 c m − 3 ), along the wafer diameter grown on the C -face (in orange) and Si -face (in blue) 4 H − S i C , respectively. Doping distribution maps for growth on the Si and C -face are displayed on the right.

Summary/Conclusion

The original version of this paper is available on https://www.scientific.net/SSP.393.15.pdf

The comparative study of 4H−SiC homoepitaxy on Si - and C -face substrates demonstrates a clear polarity-dependent trade-off. The C -face enables smoother surfaces and reduced step bunching, suggesting potential advantages for structural quality and defects mitigation. However, it suffers from excessive and poorly controllable nitrogen incorporation, resulting in poor doping uniformity. The Si-face, while yielding rougher surfaces, offers superior doping control through site-competition mechanisms, making it more suitable for device-oriented epitaxy where doping precision is critical. These results emphasize the need for polarity-specific growth strategies and provide insights into optimizing epitaxial processes for next-generation SiC power devices.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.15.pdf

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications. Hoboken, NJ, USA: Wiley-IEEE, 2014.

K. Kojima, T. Suzuki, S. Kuroda, J. Nishio, and K. Arai, Epitaxial Growth of High-Quality 4HSiC Carbon-Face by Low-Pressure Hot-Wall Chemical Vapor Deposition, Japanese Journal of Applied Physics, vol. 42, no. 6B, IOP, pp. L637-L639, 2003. doi:10.1143/JJAP.42.L637.

Kodigala Subba Ramaiah, I. Bhat, T. P. Chow, J. K. Kim, E. F. Schubert, D. Johnstone, S. Akarca-Biyikli, Growth and characterization of SiC epitaxial layers on Si- and C-face SiC substrates by chemical-vapor deposition, J. Appl. Phys. 15 November 2005; 98 (10): 106108, .

K. Kojima, H. Okumura, S. Kuroda, K. Arai, Homoepitaxial growth of 4 H -SiC on on-axis (0001) C-face substrates by chemical vapor deposition, Journal of Crystal Growth, vol. 269, issues 2-4, 2004, pp. 367-376, .

S. Nishizawa, K. Kojima, S. Kuroda, K. Arai, M. Pons, Modeling of SiC-CVD on Si-face/Cface in a horizontal hot-wall reactor, Journal of Crystal Growth, vol. 275, 2005, pp. e515-e520, .

K. Kojima, S. Kuroda, H. Okumura, K. Arai, Homoepitaxial Growth on a 4H-SiC C-Face Substrate, Chem. Vap. Deposition, 2006, 12: 489-494. .

J. Hassan, J.P. Bergman, A. Henry, E. Janzén, On-axis homoepitaxial growth on Si-face 4HSiC substrates, Journal of Crystal Growth, vol. 310, issue 20, 2008, pp. 4424-4429, .

W. Chen, K. Lee, M. A. Capano, Growth and characterization of nitrogen-doped C-face 4HSiC epilayers, Journal of Crystal Growth, vol. 297, issue 2, 2006, pp. 265-271, .

Z. Zhao, Y. Li, X. Xia, Y. Wang, P. Zhou, Z. Li, Growth of high-quality 4H-SiC epitaxial layers on off-axis C-face 4H-SiC substrates, Journal of Crystal Growth, vol. 531, 2020, .

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 21-25

doi: 10.4028/p-kXxK8f

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers 

The original version of this paper is available on https://www.scientific.net/SSP.393.21.pdf

Weining Qian 1,2,a*, Feihong Huang 2, b, Jinan Li2,c, Gan Feng 2, d, Jianhui Zhao 1,2,e and Junyong Kang 1,f

¹College of Physical Science and Technology, Xiamen University, Xiamen, 361005, Fujian, China

2 Epiworld International Co., LTD, Xiamen 361101,Fujian, China

a* qianwn@epiworld.com.cn, b  huangfh@epiworld.com.cn, clija@epiworld.com.cn, dfengg  @epiworld.com.cn, e  zhaojh@epiworld.com.cn, f  jykang @ xmu.edu.cn

Abstract

This study focuses on addressing the challenge of poor doping concentration uniformity during the epitaxial growth of 200 mm4H−SiC substrates, which is primarily caused by difficulties in thermal field and flow field control. By systematically optimizing key process parameters, including H2 flow rate, C/Si ratio, and growth temperature, a high uniformity concentration technology was developed. This technology has enabled a breakthrough in the performance of n-type epitaxial layers, with the doping concentration uniformity significantly improved to 0.67%. Based on the validation of this technology-encompassing 8,000 epitaxial wafers and thick epitaxial layers ( ≥30μm )-the technology demonstrates excellent doping concentration uniformity. This research provides a reliable technical foundation for the large-scale application of large-size SiC materials in power devices.

Keywords: 200 mm4H−SiC, hot-wall reactor, high concentration uniformity.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.21.pdf

Silicon carbide (SiC), with its exceptional electrical properties such as wide energy band gap, high breakdown electric field strength, and high thermal conductivity, exhibits revolutionary advantages over silicon ( Si ) in numerous applications [1]. As is well known, larger-diameter SiC wafers enable higher device counts per wafer with driving down per-unit device costs [2]. Therefore, in order to reduce the device cost and improve device performance, SiC wafer diameters have progressively evolved from 100 mm ( 4 inch) to 150 mm ( 6 inch), and are now advancing toward 200 mm ( 8 inch) technology [3].

The performance of power devices depends to a large extent on the quality of 4H−SiC epitaxial wafers [4], so the homoepitaxial growth of 4H−SiC is critical for the fabrication of 4H−SiC power devices. As the diameter of the 200 mm substrates increases, the difficulty of controlling multiple physical fields significantly multiplies in epitaxial growth process, especially with respect to the thermal field and flow field. The radial temperature gradient increases and the gas flow dynamics within the reaction chamber become more complex, which makes the problem of uneven nitrogen doping even more apparent [5]. Therefore, achieving high doping concentration uniformity ( σ/ mean ) of epitaxial layers on 200 mm substrates is critical factor for minimizing device performance variation across large-diameter substrates.

In this work, a significant improvement in concentration uniformity are achieved by optimizing the epitaxial process parameters and introducing ammonia as n-type doping Source. And the latest results of 200 mm4H−SiC epitaxial wafers are shown.

Experimental

The original version of this paper is available on https://www.scientific.net/SSP.393.21.pdf

A horizontal hot-wall reactor was employed for epitaxial growth. The silicon precursor is trichlorosilane (TCS), while Ethylene ( C2H4 ) serves as the carbon precursor. Hydrogen ( H2 ) acts as both the dilution and carrier gas, and ammonia (NH3) provided n -type doping. Featuring an automatic loading/unloading system operating at 900∘C, the reactor enabled high growth rates. Substrates are
commercial domestic-made n-type 200 mm 4H-SiC substrates with a 4∘ off-cut toward the [11-20] direction.

Thickness and doping concentration of 4H−SiC epitaxial layer are evaluated by Fourier-Transform Infrared spectroscopy (FTIR) and Mercury Capacitance-Voltage (MCV) with 5 mm edge exclusion. Because the thickness and doping concentration show concentric distribution, these measurements are performed along the radial direction. Surface defect are evaluated with SICA88 with 3 mm edge exclusion.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.393.21.pdf

There is a significant challenge in achieving high concentration uniformity for epitaxial layers on 200 mm substrates. When scaling the substrate size from 150 mm to 200 mm , thermal field inhomogeneities and gas flow distribution inhomogeneities increase significantly. Meanwhile, the enlargement of the epitaxial chamber leads to elevated background concentration and reduced concentration stability.

Based on our previous research findings and epitaxial growth experience, these parameters (growth temperature, main H2 flow rate, C/Si ratio) exert a significant influence on the epitaxial doping concentration. Increasing the main H2 flow rate and optimizing the H2 flow distribution between the central and side channels can suppress flow disturbances and improve the uniformity of flow field distribution [6]; Elevating the growth temperature can reduce temperature differences across different regions of the wafer surface and enhance the uniformity of thermal field distribution on the wafer surface [7]; According to the C/N site-competition theory [8], a slightly C-rich growth environment can suppress concentration fluctuations [9]. Following the optimization of the abovementioned parameters, we finalized a comprehensive processing protocol. The detailed process parameters are provided in Table 1. This optimized process named as a high concentration uniformity (HCU) epitaxial growth technology for 200 mm4H−SiC wafers.

As a result of the above process optimizations, the doping concentration uniformity ( σ/ mean ) of the 10μ m epitaxial layer has been improved from an initial 3.56% to an exceptional 0.67%, as illustrated in Fig. 1(a). Meanwhile, an extremely high thickness uniformity ( σ/ mean ) lower than 0.81% and low surface defect count fewer than 3 pieces (pcs) have been achieved on the epitaxial layer, as shown in Fig. 1(b) and (c). The stability verification of the HCU technology was evaluated with 25 consecutive runs (one PM (preventive maintenance) cycle). As shown in Fig. 1(d), the doping concentration uniformity of epitaxial layers were consistently maintained below 1.5% with an average value of 0.88%. The data confirmed the robustness of the HCU technology in maintaining superior uniformity control throughout one PM cycle.

Using the HCU technology, over 8,000200 mm epitaxial wafers have been produced. The statistical analysis of these epitaxial wafers is shown in Figs. 2(a) to (c). In Fig. 2(a), the mean doping concentration uniformity of the epitaxial wafers is approximately 1.59%, with over 75% of the wafers exhibiting concentration uniformity below 2%. Fig. 2(b) reveals that the mean thickness uniformity is approximately 1.39%, with over 75% of the epitaxial wafers demonstrating thickness uniformity below 1.57%. What is more, Fig. 2(c) shows that the mean total usable area (TUA) is approximately 97.6%, with over 75% of the epitaxial wafers achieving a TUA exceeding 97.1%. The TUA is calculated by ideally dividing the wafer surface in 5×5 mm2 and counting the percentage of squares not containing any defect (defects considered include downfalls, triangles, carrots, and micropipes). During mass production, slight quality fluctuations of the epitaxial wafers are unavoidable due to factors such as variations in PM operations, equipment differences, and personnel operation inconsistencies in the production process. Thus, the mass production data are slightly inferior to the experimental data. These mass production data demonstrate industry-leading repeatability in our 200 mm4H−SiC epitaxial growth process.

It is well-known that the higher the voltage rating of power device, the lower the doping concentration of the epitaxial layer, and the greater the difficulty in controlling the uniformity of the doping concentration. To further evaluate the HCU technology, 3300 V epitaxial wafers have also been grown using this technology with a doping concentration of 3E15 cm−3 and thickness of 30μ m.

As shown in Fig. 3(a) the doping concentration uniformity of epitaxial layers were consistently maintained below 1.7%. Fig. 3(b) shows the thickness uniformity were consistently maintained below 1.3%, Fig. 3(c) shows TUA ( 5 mm×5 mm ) were consistently maintained exceeding 98.56%. These results confirm that the HCU epitaxial growth technology is applicable to a wide range of doping concentrations.

Table 1. Specific process parameters of HCU growth technology for 200 mm4H−SiC wafer.

Growth

Temperature

Pressure

mathematical formula mbar mathematical formula

Main superscript number flow

rate mathematical formula

C/Si ratio

superscript number | 100 | superscript number | mathematical formula

[picture]

Fig. 1. (a) The radial doping concentration distribution before and after optimization. (b) The radial thickness distribution after optimization. (c) The map of triangle and downfall defects after optimization. (d) The doping concentration uniformity statistics of continuous 25 runs epitaxial wafers.

Fig. 1. (a) The radial doping concentration distribution before and after optimization. (b) The radial thickness distribution after optimization. (c) The map of triangle and downfall defects after optimization. (d) The doping concentration uniformity statistics of continuous 25 runs epitaxial wafers.

[picture]

Fig. 2. The statistical results of : (a) doping concentration uniformity, (b) thickness uniformity and (c) TUA ( 5 mm×5 mm ), based on over 8,000 epitaxial wafers.

Fig. 2. The statistical results of : (a) doping concentration uniformity, (b) thickness uniformity and (c) TUA ( 5 m m × 5 m m ), based on over 8,000 epitaxial wafers.

[picture]

Fig. 3. Results for 30μ m-thick 4H−SiC epitaxial growth: (a) average concentration and uniformity per run; (b) average thickness and uniformity per run; (c) killer defect density (KDD) and TUA ( 5 mm×5 mm ). All measurements were based on HCU technology.

Fig. 3. Results for 30 μ m-thick 4 H − S i C epitaxial growth: (a) average concentration and uniformity per run; (b) average thickness and uniformity per run; (c) killer defect density (KDD) and TUA ( 5 m m × 5 m m ). All measurements were based on HCU technology.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.21.pdf

This study successfully resolved the thermal/flow field co-control challenges in the epitaxial growth of 200 mm 4 H -SiC substrates. Through optimization of process parameters, it significantly improved the doping concentration uniformity to 0.67%, while achieving a thickness uniformity of 0.81% and an ultra-low defect density. Mass production validation ( >8,000 wafers) confirmed process stability, with 75% of wafers meeting stringent specifications of doping uniformity <2% and TUA >97.1%. The developed HCU technology further overcame process window limitations for high-voltage thick epitaxial layers ( 30μ m,3E15 cm−3 ) under low doping conditions. It achieved the simultaneous optimization of inter-wafer/intra-wafer doping and thickness uniformity along with fatal defect density <0.1 cm−2 and TUA >98.56%, laying the foundation for mass production of highvoltage SiC devices. This technological breakthrough comprehensively advances the industrialization of 200 mm SiC epitaxial processes and provides core material support for next-generation power semiconductor applications.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.21.pdf

J. B. Casady, R. W. Johnson, Status of silicon carbide (SiC) as a wide-bandgap semiconductor for high-temperature applications A review, Solid-State Electron., 39 (1996) 1409-1422.

M. Musolino, E. Carria, D. Crippa, et al, Development of n-type epitaxial growth on 200 mm 4H-SiC wafers for the next generation of power devices, Microelectron. Eng., 274 (2023) 111976.

M. Musolino, E. Carria, D. Crippa, et al, Paving the way toward the world's first 200 mm SiC pilot line, Mat. Sci. Semicon. Proc., 2021, 135 (2021) 106088.

J. Li, C. Meng, L. Yu, et al, Effect of various defects on 4H-SiC Schottky diode performance and its relation to epitaxial growth conditions, Micromachines-basel, 11 (2020) 609.

G. Hu, G. Zhong, X. Xiong, et al, Improvement of the resistivity uniformity of 8-inch 4H-SiC wafers by optimizing the thermal field, Vacuum, 222 (2024) 112961.

J. Zhang, J. Mazzola, C. Hoff, et al, High growth rate (up to ) SiC epitaxy in a horizontal hot-wall reactor, Mater. Sci. Forum, 77 (2005) 483-485.

X. Gong, P. Li, T. Xie,et al, High uniform N-type doping of homoepitaxy based on a horizontal hot-wall reactor, J. Cryst. Growth, 648 (2024) 127877.

D.J. Larkin, P.G. Neudeck, J.A. Powell, L.G. Matus, Appl. Phys. Lett., 65 (1994) 1659-1661.

G. Ferro, D. Chaussende, Revisiting the site-competition doping of : cases of N and Al , Mater. Sci. Forum, 1004 (2020) 96-101.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 27-33

doi: 10.4028/p-1jrfAp

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-10

Accepted:
2026-01-31

Online:
2026-05-18

Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

Michael Schley 1,a, Friedrich Schaaff 1, b and Jan Richter 2,c*

1 Silicon Products Bitterfeld GmbH, Alustrasse 5, 06749 Bitterfeld, Germany

2 Zadient Technologies SAS, Chambery, France

a  Michael.Schley@silicon-products-gmbh.com, b  Friedrich.Schaaff@silicon-products-gmbh.com,

c*Jan.richter@zadient.com

Keywords: silicon carbide (SiC), ultra-high purity, chemical vapor deposition (CVD), physical vapor transport (PVT) growth, polycrystalline 3C-SiC, trace impurities, glow discharge mass spectrometry (GDMS), secondary ion mass spectrometry (SIMS), neutron activation analysis (NAA), optical applications, transparent wafers, augmented reality (AR).

Abstract

We report on the development and systematic validation of an ultra-pure silicon carbide (SiC) source material specifically engineered for physical vapor transport (PVT) growth of opticaland electronic-grade single crystals. The material is synthesized by chemical vapor deposition (CVD) using high-purity chlorosilane and methane precursors, yielding dense, void-free polycrystalline 3CSiC with precise 1:1 stoichiometry. Over more than two years of continuous production, bulk metallic impurities across 17 monitored elements were consistently maintained below 100 parts per billion by weight (ppbw), with most batches achieving <50ppbw. Surface metals, assessed after proprietary crushing and cleaning processes, were similarly controlled to <100ppbw. Nitrogen levels, determined by secondary ion mass spectrometry (SIMS), remained stable in the low 1015 cm−3 range, enabling semi-insulating or precisely doped crystal growth. Purity and reproducibility were verified by a crosstechnique analytical approach including glow discharge mass spectrometry (GDMS), and inductively coupled plasma mass spectrometry (ICP-MS). Microstructural investigations confirmed dense, voidfree grains and high crystallographic uniformity. With production capacity scaling toward 60 tons per month, this CVD-based SiC source material establishes a robust platform for next-generation PVT growth. Its combination of ultra-low contamination, structural integrity, and scalable manufacturing positions it as a key enabler for optical SiC applications such as transparent wafers for augmented reality (AR) systems, as well as advanced power and RF devices.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

Silicon carbide (SiC) has become one of the most critical semiconductor materials for advanced applications in power electronics, radio frequency (RF) devices, and optical systems 1−3. Its wide bandgap, high thermal conductivity, and mechanical robustness make it the preferred substrate for high-performance devices that must operate under extreme thermal and electrical conditions. Beyond traditional electronic applications, recent interest in transparent and semi-insulating SiC has opened new opportunities in optoelectronics and augmented reality (AR) systems, where crystal transparency and ultra-low contamination are essential requirements 4,5.

A fundamental prerequisite for high-quality SiC crystal growth is the availability of ultra-pure feedstock material 6−8. Physical vapor transport (PVT) growth, the dominant industrial method for producing single-crystalline 4 H - and 3C-SiC, is highly sensitive to the purity and stoichiometry of the source. Even trace amounts of metallic impurities, uncontrolled nitrogen incorporation, or residual free silicon and carbon can destabilize sublimation chemistry, increase defect density, and compromise device performance. Consequently, developing reliable and scalable SiC source materials with exceptionally low impurity levels has become a critical challenge for the industry.

Conventional polycrystalline SiC powders, often produced via carbothermal reduction, suffer from limitations in chemical purity, batch-to-batch reproducibility, and structural homogeneity. Alternative approaches, such as advanced chemical vapor deposition (CVD), have emerged as promising routes to engineer feedstock with controlled stoichiometry, dense microstructure, and minimal defect density. CVD-based processes further offer the potential for scalability and independence of supply-
factors that are increasingly relevant as demand for SiC substrates accelerates across multiple industries.

In this work, we present the development and validation of a new CVD-derived SiC source material tailored for PVT growth of high-quality crystals. Using ultra-high-purity chlorosilane and methane precursors, we deposit dense, void-free polycrystalline 3C-SiC with precise atomic stoichiometry. Over a multi-year production period, we demonstrate outstanding reproducibility and impurity control, with bulk metallic concentrations consistently below 100 parts per billion by weight (ppbw) and nitrogen incorporation stabilized in the low 1015 cm−3 range. A multi-technique analytical strategy-including glow discharge mass spectrometry (GDMS), secondary ion mass spectrometry (SIMS), and inductively coupled plasma mass spectrometry (ICP-MS)-was employed to establish the reliability of impurity quantification and to validate surface cleaning processes.

The results confirm that this material platform provides one of the purest and most structurally uniform polycrystalline SiC feedstocks available today. Its reproducibility, combined with ongoing capacity expansion toward industrial-scale volumes, positions it as a robust and cost-effective enabler for next-generation optical SiC applications, as well as for advanced power and RF devices.

Materials and Methods

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

The production of the ultra-pure SiC source material was carried out in a former CVD silicon facility located within the chemical infrastructure of Chemiepark Bitterfeld, Germany. The complete process flow, comprising CVD synthesis, comminution, surface treatment, and packaging, is illustrated in Figure 1.

[picture]

Fig. 1. Process steps for the production of ultra-pur SiC source material.

Fig. 1. Process steps for the production of ultra-pur SiC source material.

CVD Synthesis

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

The SiC source material was produced by chemical vapor deposition (CVD) using ultra-high purity chlorosilane and methane as precursors. The process yields dense, void-free polycrystalline 3C-SiC layers with precise 1:1 Si to C stoichiometry, free of elemental silicon or carbon inclusions. The deposition was carried out under tightly controlled conditions in a dedicated CVD facility in Germany, ensuring reproducibility and scalability across extended production campaigns 6−8.

Comminution

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

Following deposition, the bulk polycrystalline SiC blocks were subjected to a comminution step. Mechanical crushing and milling were optimized to preserve microstructural integrity while achieving controlled particle size distributions. Tailored particle sizes ranging from 0.5 to 15 mm were produced, with bulk densities up to 1.9 g/cm3. This flexibility allows the feedstock to be adapted to diverse PVT loading strategies and crystal growth systems.

Surface Treatment

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To remove any residual surface contamination introduced during comminution, a proprietary surface treatment protocol was applied. This included multi-stage acid leaching designed to dissolve trace metallic residues without altering the SiC bulk. Surface analysis confirmed that metallic contamination after treatment remained consistently below 100 ppbw .

Packaging

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

Finally, the purified SiC granules were packaged in contamination-controlled environments to ensure preservation of purity during storage and shipping. The packaging design minimizes environmental exposure and enables reliable long-distance transport for both industrial and research use.

Analytics and Characterization

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

To rigorously validate the purity and structural quality of the SiC source material, a multitechnique analytical strategy was implemented. This cross-validation approach ensured high confidence in both bulk and surface measurements and minimized the risk of systematic error from any single method.

Bulk Impurity Analysis

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

Used to quantify metallic impurities within the bulk polycrystalline SiC Glow Discharge Mass Spectrometry (GDMS) offered high sensitivity, with detection limits in the low parts-per-billion by weight (ppbw) range 9. Here we were able to optimize the characterization process and sample preparation to achieve detection limits in the single digit ppbw (parts per billion weight) region. Across more than two years of production, all 17 monitored elements were consistently maintained below 100 ppbw , with most batches showing <50ppbw (see figure 2).

[picture]

Fig. 2. Bulk concentration for selected elements of concern in ppbw (parts per billion weight) shown in boxplots over the last 12 months.

Fig. 2. Bulk concentration for selected elements of concern in ppbw (parts per billion weight) shown in boxplots over the last 12 months.

Nitrogen Incorporation

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

High-sensitivity Secondary Ion Mass Spectrometry (SIMS) was used to quantify nitrogen concentrations 10, which remained in the low 1015 cm−3 range. In figure 3 a production chart is given to show the consistency of the incorporation level over time (please note that 30 ppba correspond to 2.9*1015 atoms /cm3 ). This enables both semi-insulating material growth and controlled doping strategies for device applications.

[picture]

Fig. 3. Nitrogen concentration in ppba (parts per billion atoms) < 30 ppba corresponding to 2.9*1015 atoms /cm3.

Fig. 3. Nitrogen concentration in ppba (parts per billion atoms) < 30 ppba corresponding to 2.9 * 10 15 atoms / c m 3 .

Surface Purity Determination

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

We applied inductively coupled plasma mass spectrometry (ICP-MS) to quantify residual surface contamination following the proprietary cleaning process 11−13. Prior to analysis, hot acid leaching was employed to dissolve trace residues from the SiC surface. The completeness of this procedure was verified through successive leaching steps, which showed no detectable contamination (i.e., below the instrument detection limit), confirming the effectiveness of the initial treatment. Across all batches, the combined concentration of surface metals remained consistently below 100 ppbw (see Figure 4). Through a combination of optimized sample preparation and refined analytical methodology, absolute detection limits below 1 ppbw were achieved for all elements of concern.

[picture]

Fig. 4. Surface concentration for selected elements of concern in ppbw (parts per billion weight) shown in boxplots over the last 12 months.

Fig. 4. Surface concentration for selected elements of concern in ppbw (parts per billion weight) shown in boxplots over the last 12 months.

Structural and Stoichiometric Analysis

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

The High-Resolution Scanning Electron Microscopy (HRSEM) revealed dense, void-free microstructures with average grain sizes of ~50μ m (see figure 5). The analysis was provided by the Fraunhofer IKTS in Dresden, Germany.

[picture]

Fig. 5. High resolution TEM image of the polycrystalline SiC structure.

Fig. 5. High resolution TEM image of the polycrystalline SiC structure.

The crystalline structure of the material was analyzed by X-ray diffraction (XRD). The resulting diffraction pattern confirmed the presence of a single polycrystalline 3C-SiC phase, with no detectable secondary phases. The slight broadening of the dominant diffraction peak at 35.4∘ is attributed to the limited grain size and the associated grain boundary effects. Notably, the typical side peaks characteristic of 4 H - and 6H−SiC polytypes-appearing around 38∘ and below 35∘-were completely absent. Furthermore, the peak observed at 41.3∘ is uniquely consistent with the 3 C polytype and does not occur in 4 H or 6 H samples, reinforcing the phase purity of the deposited material 14−17.

[picture]

Fig. 6. XRD scan confirming the 3 C structure of the polycrystalline SiC .

Fig. 6. XRD scan confirming the 3 C structure of the polycrystalline SiC .

The precise 1:1 Si:C atomic ratio was confirmed by the exclusion of excess silicon and carbon within the material. Excess silicon was investigated using XRD on finely powdered samples, which would reveal any residual elemental silicon on the surface. However, it should be noted that the detection limit of this method remains relatively high, in the range of 100−500ppmw, leaving room
for further sensitivity improvements. Excess carbon was assessed by combustion analysis, which did not indicate any detectable carbon inclusions above the method's detection threshold. Similar to silicon, the current detection limit for free carbon lies in the ~500ppmw range, highlighting the need for enhanced analytical resolution in future studies.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

This work demonstrates that chemical vapor deposition (CVD) is the most effective route to produce ultra-pure silicon carbide (SiC) source material for physical vapor transport (PVT) growth. Unlike conventional synthesis methods, CVD enables precise control over stoichiometry, microstructure, and impurity levels, resulting in dense, void-free 3C-SiC with reproducible properties across multiple production batches.
Extensive characterization is essential to optimize the production process and to ensure reproducibility. A multi-technique analytical framework, combining GDMS, SIMS, ICP-MS, SEM, and XRD, provides the resolution and confidence required to confirm trace-level purity and structural integrity. This systematic validation not only guarantees the material's suitability for advanced optical and electronic applications but also builds a robust foundation for further process optimization.
Finally, CVD offers a straightforward and scalable path to mass production. With demonstrated longterm reproducibility and ongoing capacity expansion, the technology is positioned to support industrial-scale volumes while maintaining the highest levels of purity. This makes CVD-derived SiC source material a reliable and future-proof enabler for next-generation applications ranging from augmented reality optics to high-performance power and RF devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

This work was supported by the project FastLane. The project is supported by the Chips Joint Undertaking (JU) and its members, including top-up funding by Austria, France, Germany, Romania, and Slovakia, under grant agreement No 101139788.

FAST|ANE
hipsJU

Co-funded by the European Union

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

References

The original version of this paper is available on https://www.scientific.net/SSP.393.27.pdf

Kimoto, T., & Cooper, J. A. (2014). Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications. Wiley-IEEE Press.

Choyke, W. J., Matsunami, H., & Pensl, G. (Eds.). (2004). Silicon Carbide: Recent Major Advances. Springer.

Kordina, O., Saddow, S. E., Kimoto, T., & Agarwal, A. (2021). Silicon Carbide Power Devices. Elsevier.

Rupp, R., et al. (2018). "Ultra-high-purity SiC and its role in power electronics." Journal of Crystal Growth, 498, 380-387.

Murakami, H., et al. (2020). "Advances in bulk SiC crystal growth for optical and power applications." Applied Physics Express, 13(12), 120101.

Größmann, I., et al. (2021). "Method and device for producing a SiC solid material." International patent application WO 2022123072.

Ceran, K., et al. (2022). "Method for producing at least one crack-free SiC piece." International patent application WO 2023222787.

Größmann, I., et al. (2024). "Method and system for SIC production and improved vent gas recycling." International patent application WO2025051945.

Hofmann, S., & Rauschenbach, B. (1990). "Glow discharge mass spectrometry in materials science." Surface and Interface Analysis, 16(9), 577-582.

Itoh, A., Okumura, H., & Matsunami, H. (1995). "Quantitative analysis of nitrogen in 4H-SiC epilayers by secondary ion mass spectrometry." Journal of Applied Physics, 77(11), 837-843.

Rossotti, F. J., et al. (2023). "Tackling the Challenging Determination of Trace Elements in Ultrapure SiC via LA-ICP-MS." Molecules, 28(6), 2845.

Fraunhofer Center for Silicon Photovoltaics CSP. (n.d.). "Surface contamination analysis, highsensitivity ICP-MS of SiC materials." Fraunhofer CSP Ultratrace Analysis Service. .

Toray Research Center, Inc. (2016). "High-sensitive analysis of metal impurities on Si & SiC substrates-ICP-MS methods." Toray Technical Information Series.

Ruska, J., Lugovy, M., & Kordina, O. (2001). "Accuracy of X-ray diffraction SiC polytypecomposition analyses." Journal of Materials Synthesis and Processing, 9(4), 211-218.

Gauckler, L. J., & Scherrer, P. (2003). "Quantitative polytype-composition analyses of SiC using X-ray diffraction." Journal of Materials Processing Technology, 136(1-3), 191-197.

Wyatt, C. N., & Blackson, J. (2016). "Using XRD and TGA-DSC to characterize a silicon carbide powder." Kansas State University Undergraduate Research Reports, 12, 1-7.

Kumar, G., Chen, J.-W., Ma, H.-H., Huang, X.-F., & Huang, M. H. (2022). Facet-dependent electrical conductivity properties of a wafer. Journal of Materials Chemistry C, 10(28), 10424-10428.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 35-39

doi: 10.4028/p-g7vlrZ

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2026-01-06

Accepted:
2026-02-23

Online:
2026-05-18

Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

The original version of this paper is available on https://www.scientific.net/SSP.393.35.pdf

Tawhid Rana 1,a, Taskin Karim 1, b, Jonas P. Murphy 1,c, Sam Johnson 1, d, Nicolas Thierry-Jebali 1,e and Edward Sanchez 1,f

1 SK siltron css, 1311 Straits Drive, Bay City, MI 48706, USA

a tawhid.rana@sksiltron.com, b taskin.karim@sksiltron.com, c jonas.murphy@sksiltron.com, d sam.johnson@sksiltron.com, e nicolas.thierry@sksiltron.com, f edward.sanchez@sksiltron.com

Keywords: silicon carbide epitaxy, thick epitaxy, edge exclusion, ultra thick epitaxy, polishing of epilayers, pits, bumps, BPD pileup, BPD crowding.

Abstract

Thick epitaxy with different buffer and drift layer growth rates are studied. Epilayer with higher growth rates demonstrates lower basal plane dislocaiton (BPD) but higher stacking faults. We use the optimum growth rate found from the aforesaid experiments to achieve 100 um and 200 um epilayers. BPD pileup was observed, especifally at the edges of the epilayer rendering an exclusion area upto 15 mm from the edge. Hence, we argue that it is essential to consider higher exclusion region for thicker epilayers. Large, pits and bumps are observed for thicker epitaxy, upto a diameter of 48μ m for 200μ m epilayers. Finally, we polish the epilayers and demonstrated 98% and 95% total usable area (TUA) for 100μ m and 200μ m epitalayers respectively.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.35.pdf

Silicon carbide is an important material for high voltage applications due to its various exceptional electrical and mechanical properties [1]. Currently SiC crystal is widely used in electric vehicle (EV) related electronic applications. Typically, operational voltages of these power devices are in the range of 0.6−1.5kV, where typically 6μ m−15μ m epitaxial layers are used. However, to block high voltage ( >5kV ), much thicker epitaxy ( >50μ m ) is required. Thick SiC epitaxy is extremely challenging due to severe surface degradation by formation of larger morphological and extended defects, as well as various complex dislocations (half loop array or HLA, BPD pileup, etc.). Thick epitaxy in the range of 50−100μ m is demonstrated in earlier literature [2]. In this research, we study epitaxy in the range of 60−200μ m on 150 mm4H−SiC wafers for surface, defectivity, wafer shape, etc.

Experimental

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A commercial, single wafer epi reactor is used to grow epilayers with various thicknesses. We compare the results with various growth rates. We increase growth rates for buffer and drift layers ( 3 times ( 3 x ) and 2 times ( 2 x ) respectively) by increasing precursor gases. We adjust growth time to achieve the target thicknesses (60μ m,100μ m and 200μ m), whereas adjust nitrogen flow rate to achieve a doping target of ~1e15 cm−3. We select wafers from adjacent slices in a boule to minimize the wafer-to-wafer variations. Wafer shapes are measured using Tropel Ultrasort and defects are characterized by a SiCA88 tool. Chemo-mechanical polishing (CMP) was performed on these epilayers with a removal of ~1μ m to improve roughness of the surface, associated with the thick epitaxy.

Results

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Higher growth rate is needed for thicker epitaxies to minimize the growth time. To study the effect of higher growth rates on defects, first, we increase growth rate by increasing precursor gas flow rates.

We find that higher growth rates reduce basal plane dislocations (BPD) in the epilayer, however increases stacking faults (SF) (Fig. 1). We further optimize the process for the higher growth rates to reduce SF by optimizing process conditions.

[picture]

Fig. 1. Optimization of the buffer and drift layer growth rates (GR) are performed. a) BPD is reduced with higher growth rate and b) stacking faults are increased with higher growth rates.

Fig. 1. Optimization of the buffer and drift layer growth rates (GR) are performed. a) BPD is reduced with higher growth rate and b) stacking faults are increased with higher growth rates.

We study surface defects on the epitaxy grown at different thicknesses using Sica88. We find that surface degrades with increased roughness with thicker epitaxies, visible from the surface images with pits and bumps. Threading screw/edge dislocations (TSD/TED) in the substrates can introduce pits in the epilayers [3]. These pits grow significantly larger for the thicker epitaxies (60μ m,100μ m, 200μ m ). We observe that for thicker epitaxies, these pits also create bump and wave-like features from the pit center, towards 112―0 direction (Fig.2).

[picture]

Fig. 2. Examples of pits in the epi at different thicknesses. a) smaller ( 21μ m ) size epi pits are seen for ~60μ m epilayer, with waviness on the right side of the pit towards 112―0 direction. These pits and the consequent wave shapes becomes larger for thicker epitaxy ( b and c ).

Fig. 2. Examples of pits in the epi at different thicknesses. a) smaller ( 21 μ m ) size epi pits are seen for ~ 60 μ m epilayer, with waviness on the right side of the pit towards 11 2 ― 0 direction. These pits and the consequent wave shapes becomes larger for thicker epitaxy ( b and c ).

On the other hand, intricate shapes of basal plane dislocations (BPD) as pileups are seen in the PL images as described in [4]. We find that these BPD pileups are mainly seen at the edge of the wafers (Fig. 3), or around any obstructions on the step flow (e.g. particle, triangular defects etc.).

[picture]

Fig. 3. PL images are shown for the epilayers grown with different thicknesses. Intricate lines of PL BPDs are seen for the thicker epi (100μ m,200μ m). The width of the impact increases for thicker epi, extending upto 15μ m from the edge. Shaded region shown as typical edge exclusion ( 3μ m ).

Fig. 3. PL images are shown for the epilayers grown with different thicknesses. Intricate lines of PL BPDs are seen for the thicker epi ( 100 μ m , 200 μ m ) . The width of the impact increases for thicker epi, extending upto 15 μ m from the edge. Shaded region shown as typical edge exclusion ( 3 μ m ).

Initially, we study on the effect of polishing for 60μ m epilayers to smooth out the pits and high step bunching associated with the thick epitaxy. We find that a surface removal of ~0.5um by polishing effectively removes pits on the surface for 60μ m epi (Fig. 4).

[picture]

Fig. 4. Surface images are shown for a ~60μ m epilayer. a) large pits and step bunching are seen for the epilayer b) These pits and step bunchings are removed by planarization technique (polishing).

Fig. 4. Surface images are shown for a ~ 60 μ m epilayer. a) large pits and step bunching are seen for the epilayer b) These pits and step bunchings are removed by planarization technique (polishing).

We conduct similar polishing study for the 100μ m and 200μ m epitaxy with a ~1μ m removal to have the similar effect to remove pits and bumps (Fig. 5).

[picture]

Fig. 5. a) Pits and b) bump reduction by polishing in 100μ m and 200μ m epilayer.

Fig. 5. a) Pits and b) bump reduction by polishing in 100 μ m and 200 μ m epilayer.

Larger sized pits and bumps in 200μ m epilayers render total usable area (TUA) poorly ( ~2% ). Hence, Si face polishing was essential to smooth out the surface. Si face polishing ( 1μ m removal) significantly reduces pits and bumps in the epilayer (Fig. 5). With polishing, we demonstrate TUA of 98% for 100μ m and 95% for the 200μ m epilayer, respectively. Even though polishing removes pits and bumps from the surfaces, it cannot remove particle-induced [5], larger morphological defects, like carrot, triangles etc., especially which originate closer to substrate-epilayer interfaces (Fig. 6).

Finally, we study the effect of polishing on the wafer shape. We find that wafer bows are reduced after polishing (Fig. 7). This is due to stress reduction by removal of Si and C faces.

[picture]

Fig. 6. a) Polishing steps increase total usable area (TUA) for thick epitaxy by eliminating pits and bumps in the epilayer (b, c).

Fig. 6. a) Polishing steps increase total usable area (TUA) for thick epitaxy by eliminating pits and bumps in the epilayer (b, c).

[picture]

Fig. 7. a) Shape transformation is shown for substrate to epilayer after the polishing of 200μ m epilayer b) Polishing reduces the bow for both 100μ m and 200μ m epitaxy.

Fig. 7. a) Shape transformation is shown for substrate to epilayer after the polishing of 200 μ m epilayer b) Polishing reduces the bow for both 100 μ m and 200 μ m epitaxy.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.35.pdf

Higher growth rate is found to be beneficial for BPD conversion but may have adverse effect on stacking fault generation. Pit and bump sizes increase with higher thickness and polishing is essential to smooth out the surface. BPD crowding or pileup at the edge increases for thicker epitaxy and may impact up-to 15 mm from the edge for 200μ m epitaxy. We demonstrate 95%−98% TUA after polishing for 100μ m and 200μ m epitaxy. Thick epitaxy is challenging due to higher morphological and extended defects, which critically impact TUA of the ultra-thick epitaxy. Further optimization is required to reduce particle related defects and improve surface quality (pit, bumps etc.) for ultra thick epitaxy.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.35.pdf

P. G. Neudeck, The VLSI Handbook, CRC Press LLC, 2006.

Jie Zhang, G. Chung, Edward Sanchez, Mark J. Loboda, Materials Science ForumMaterials Science Forum Vols. 717-720 (2012).

G Chung, C Lee, A Soukhojak, T. Rana, Materials Science Forum 1089, 31-35 (2023).

Nadeemullah A. Mahadik, Robert E. Stahlbush and, Woongje Sung, J. Appl. Phys. 131, 225702 (2022).

Rana, Tawhid, Hai Zheng Song, M.V.S. Chandrashekhar, and Tangali S. Sudarshan. Materials Science Forum 717-720 (May 2012): 153-56.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 41-46

doi: 10.4028/p-X6hfof

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-15

Accepted:
2026-02-23

Online:
2026-05-18

Solution Growth Technique of Silicon Carbide with In Situ Observation

The original version of this paper is available on https://www.scientific.net/SSP.393.41.pdf

Y. Abe 1,a*, A. Kawabe 1,b, J. Osada 1,c, K. Kurashige 1,d, H. Nakanishi 1,e, H. Ishibashi 1,f and T. Ujihara 2, g

1 OXIDE Power Crystal Corporation 1741-8 Maginohara, Mukawa, Hokuto, Yamanashi, 408-0302, Japan

2 Graduate School of Engineering, Nagoya University, Furo-cho, Chikusa-ku, Nagoya, Aichi, 464-8603, Japan

a*abe.yoshihisa@opt-oxide.com, b kawabe.akihisa@opt-oxide.com, c osada@opt-oxide.com, d  kurashige.kazuhisa@opt-oxide.com, èhideo.nakanishi@opt-oxide.com, fishibashi@opt-oxide.com, q  ujihara@nagoya-u.jp

Keywords: solution growth, In-situ observation, meniscus, Induction heating.

Abstract

In the solution growth method for silicon carbide ( SiC ) single-crystal fabrication, in-situ observations were performed inside the furnace to monitor the meniscus at the seed-solution interface. A meniscus formed at the contact between the seed crystal and the solution, and variations in the reflections on the solution surface enabled optical monitoring and control of this interface. The observed surface images were also dependent on the frequency of the induction heating. Computational fluid dynamics (CFD) simulations indicated that lowering the heating frequency causes an upward displacement of the solution surface at its central region, producing a locally elevated contact position between the seed crystal and the solution. These findings demonstrate that in-situ observation constitutes an effective approach for precise control of meniscus shape during solution growth of SiC single crystals.

Introduction

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Silicon carbide ( SiC ) is expected to play an increasingly important role in power devices owing to its superior electrical and physical properties compared with silicon (Si). However, various crystal defects in SiC adversely affect device performance and reliability [1]; therefore, reduction of defect density is required. Solution growth is considered to suppress defect formation because it proceeds near thermodynamic equilibrium at the growth interface, and it has thus been applied to SiC crystal growth [2]. Furthermore, incorporation of aluminum (Al) into the solution enables relatively facile ptype heavy doping for SiC single crystals, making solution growth advantageous for producing Al heavy doped p-type SiC substrates required for high-voltage devices such as insulated gate bipolar transistors (IGBTs) [3].
In SiC solution growth, the meniscus formed at the solution-crystal interface significantly influences crystal shape and growth kinetics [4]. In the top-seeded solution growth (TSSG) method, a Si-based alloy solution is contained in a graphite crucible, and a SiC single crystal seed is brought into contact with the solution to grow the SiC single crystal. In this method carbon for SiC growth is supplied by dissolution of the graphite crucible; as the crucible wall dissolves into the solution, carbon is transported to the seed via the solution. Consequently, the inner wall of the graphite crucible is eroded during the growth period. Moreover, because the solution is held at approximately 2000∘C well above the melting point of Si and the other metal elements, an evaporation of the solution is inevitable. For the reasons mentioned above, the solution surface is expected to change continuously throughout the growth period. Because crystal growth proceeds simultaneously, understanding solution behavior is crucial to maintaining precise control of the meniscus over prolonged growth durations.
However, maintaining the solution at around 2000∘C requires enclosing the crucible within an insulating hot zone, which complicates direct observation of the crucible interior. Previously, X-ray transmission imaging inside the furnace was explored to determine the solution shape [5]; however, the required apparatus is too complex for practical manufacturing equipment. Accordingly, this study
investigated the feasibility of observing the solution state inside the crucible and conducted preliminary crystal growth experiments with in-situ observations.

Experimental Methods

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As shown in Figure 1, an observation port (30 mm×40 mm ) was provided at the top of the hot zone in the induction-heating furnace, and the interior of the hot zone was imaged in real time by a camera positioned outside the chamber. The camera was positioned at an angle of several degrees to the vertical axis of the chamber so that it could observe the area near the contact between the seed crystal and the solution. The camera was equipped with an ND filter to observe high-temperature environments around 2000∘C. A common Si−40%Cr alloy was used as the solution and contained in a graphite crucible. The solution was heated to 2000∘C using mid-frequency induction heating, after which it was brought into contact with the seed crystal. The furnace atmosphere was argon at atmospheric pressure. The crystal growth time was set to 20 hours.
A 4H−SiC seed crystal was bonded to a graphite holder. Contact between the seed crystal and the solution was performed manually while monitoring the in-situ images. Note that

[picture]

Fig. 1. Solution growth apparatus with an in-situ observation system.

Fig. 1. Solution growth apparatus with an in-situ observation system.

rotation of the seed crystal and crucible was not performed in order to prioritize the in-situ observation.
Computational fluid dynamics (CFD) simulations were also performed to elucidate the solution free-surface and the solution flow behaviors. Simulations were carried out using STAR-CCM+ (Siemens Digital Industries Software), and the volume-of-fluid (VOF) method was employed to simulate the free surface of the solution. Because induction heating was used, surface tension and Lorentz forces arising from the electromagnetic field were included in the calculation of the free-surface shape. Regarding the wetting angle between the solution and the graphite crucible wall, a value of 45∘ was used in the present simulation, corresponding to the wetting angle between Si melt and SiC [6]. This choice is based on the assumption that the crucible wall reacts rapidly, resulting in the formation of SiC on the crucible surface.

Results and Discussion

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As shown in Figure 2(a) and (b), the solution surface is presented for a relatively high induction heating frequency and after contact between the seed crystal and the solution, respectively. Owing to the high reflectivity of the Si−Cr alloy solution, the solution surface was clearly visible. In Figure 2(a) the surface remained nearly stationary; however, when the seed was brought into contact with the solution, the reflected image changed markedly (Figure 2(b)), with the observation port aperture mirrored on the solution surface. This change results from meniscus formation upon contact, which substantially alters the surface curvature. Moreover, the inverted appearance of the aperture in Figure 2(b) indicates a concave meniscus with relatively small curvature. As the seed crystal was continuously lowered, this meniscus eventually disappeared, and the solution climbed up onto the graphite holder. Therefore, by observing this meniscus, the contact condition between the seed crystal
and the solution can be precisely controlled. We consider that maintaining this contact condition throughout the entire crystal growth process is a critically important technique.

[picture]

Fig. 2. (a) Image of the solution surface (yellow-shaded region) before contacting the seed. (b) Image after contact; a reflected image of the observation port (dark shape within the yellow region) appears on the solution surface. A schematic diagram of the reflected image is shown in the upper right.

Fig. 2. (a) Image of the solution surface (yellow-shaded region) before contacting the seed. (b) Image after contact; a reflected image of the observation port (dark shape within the yellow region) appears on the solution surface. A schematic diagram of the reflected image is shown in the upper right.

[picture]

Fig. 3. Before (upper images) and after (lower images) touching between the seed and the solution. (a) In case of higher frequency, the solution surface is stationary.
(b) In case of lower frequency, the solution surface is vibrating.

Fig. 3. Before (upper images) and after (lower images) touching between the seed and the solution. (a) In case of higher frequency, the solution surface is stationary. (b) In case of lower frequency, the solution surface is vibrating.

Next, we investigated the effect of changing the induction heating frequency to one-third of the higher frequency; the results before and after the change of the induction heating frequency are summarized in Figure 3 (a) and (b), respectively. At the lower frequency the solution exhibited clearly oscillations and the observed image became highly vibrating. Nevertheless, contact between the seed and the solution could still be identified from small changes in the image. We confirmed that contact between the seed crystal and the solution can be observed regardless of the induction heating frequency. Lowering the frequency also caused the seed-solution contact to occur at a higher position. In the next paragraph, we will use CFD simulations to explain the vibration of the solution and that difference in contact position.
According to the CFD simulations, in our case, the dominant factor in solution flow was the Lorentz force due to the induction heating. At lower frequency in the induction heating, the velocity of this flow was several times greater than at higher frequency. Therefore, we believe that the magnitude of the solution agitation caused the vibration. Simulation results prior to the contact are shown in Figure 4(a) and those after the contact in Figure 4(b). The vertical axis in Figure 4 denotes relative displacement (initial solution surface set to zero), and the horizontal axis denotes distance from the

[picture]

Fig. 4. Simulation results of solution surface profiles. (a) Before and (b) after the solution contacts the seed.

Fig. 4. Simulation results of solution surface profiles. (a) Before and (b) after the solution contacts the seed.

crucible center. Solution surface profiles at the two frequencies are plotted as black (higher frequency) and red (lower frequency) curves. In Figure 4(a), the lower frequency profile exhibits a central upward rise, indicating a higher contact position of the seed-solution than that of the higher frequency one. Lorentz forces at lower frequency act more uniformly on the solution, raising its central region. This behavior is attributed to increased electromagnetic skin depth at lower frequency, which reduces power dissipation in the crucible and allows the electromagnetic field to be applied to the solution more efficiently. As described above, differences in the solution surface shape occur depending on the induction heating frequency, so it is important to directly observe the contact state between the seed crystal and the solution. In particular, since this method uses a large-diameter wafer as a seed crystal, if the contact between the seed crystal and the solution is only partial, the possibility of voids formation increases.
This paragraph describes the influence of these differences in meniscus shapes on crystal growth. At lower frequency, the meniscus curvature is larger than at higher frequency, which likely affects heat removal from the meniscus. This process operates at temperatures around 2000∘C, and thus heat removal from solid or liquid surfaces is considered to be dominated by radiative heat transfer. As shown the red line in Figure. 4(b), at lower frequency, the meniscus surface is oriented further upward on the crystal side compared with that at higher frequency. Consequently, the radiative energy emitted from the meniscus at lower frequency is directed upward toward the crucible wall. In contrast, as shown the black line in Figure. 4(b), the meniscus surface on the crystal side is oriented more horizontally at higher frequency. As a result, the radiative energy emitted from the meniscus is directed downward compared with the lower frequency case. The crucible exhibits a vertical
temperature distribution depending on the relative positions of the crucible and the induction coil. Therefore, changes in the relative angle between the meniscus surface and the crucible wall alter the amount of heat extracted from the meniscus, which is considered to lead to differences in the lateral growth rate of the crystal. We believe that optimal growth conditions may depend on the induction heating frequency.
Figure 5 presents images of crystal growth recorded during the experiment; lateral crystal growth was observed in real time. Figure 5(b) shows the results 20 hours after Figure 5(a). Figure 6 shows a comparison of the crystal with the graphite holder obtained after the experiment and the image during crystal growth. As SiC crystal had grown about 3 mm in the lateral direction, the adjacent solution region shifted laterally. The crystal grows laterally, causing part of the crystal surface to become exposed above the solution. The emissivity of SiC differs from that of the solution surface, with the SiC surface exhibiting a higher emissivity. Consequently, significant heat removal due to thermal

[picture]

Fig. 5. (a) Initial state of the crystal growth and (b) after 20 hours of the crystal growth.

Fig. 5. (a) Initial state of the crystal growth and (b) after 20 hours of the crystal growth.

radiation occurs at the SiC crystal surface exposed from the solution surface, raising concerns about an increased crystal growth rate in that region. If the crystal growth rate becomes excessive, there is a high likelihood of inducing undesired crystal growth directions or polycrystallization. We believe that such phenomena can be prevented in advance through in situ observation. In other words, maintaining the required crystal shape becomes possible, which is expected to contribute to an improvement in the crystal growth yield. On the other hand, a comparison of the solution surface conditions shown in Figures 5(a) and (b) reveals that fluctuations of the solution were suppressed as the crystal expanded laterally. This behavior is presumed to result from a reduction in the free surface area of the solution. In future work, we plan to investigate changes in the surface condition as a function of solution composition.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.41.pdf

[picture]

Fig. 6. Photograph of the graphite holder and the grown crystal edge with the in-situ observed image(under).

Fig. 6. Photograph of the graphite holder and the grown crystal edge with the in-situ observed image(under).

As a result of employing in-situ observation for SiC crystal growth by the solution method, changes in the solution surface morphology led to variations in the reflected images, enabling observation of the contact state between the seed crystal and the solution. The solution surface geometry was found to vary with the frequency of induction heating,
which was also confirmed by numerical simulations. The contact state between the crystal and the solution not only changes continuously over time due to factors such as crucible erosion and solution evaporation, but also depends strongly on the frequency of induction heating. Furthermore, it was pointed out that changes in the meniscus shape alter the radiative heat transfer between the solution surface and the crucible wall, indicating the potential for a significant impact on crystal growth. From these results, in-situ observation can be regarded as a useful tool for maintaining the meniscus formed between the solution and the crystal over long periods.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/SSP.393.41.pdf

This paper is based on results obtained from a project, JPNP21029, subsidized by the New Energy and Industrial Technology Development Organization (NEDO).

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T. Kimoto, H.Watanabe, Appl. Phys. Express 13120101 (2020).

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T. Sakai1, M. Kado, H. Daikoku, S. Harada, T. Ujihara, The 77th Japan Society of Applied Physics Autumn Meeting, 15a-C302-1, 2016 [in japanese].

G. W. Liu, M. L. Muolo, F. Valenza, A. Passerone, Ceram. Int. 36 (2010) 1177-1188.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 47-52

doi: 10.4028/p-Ro32jp

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-20

Accepted:
2026-02-23

Online:
2026-05-18

Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

The original version of this paper is available on https://www.scientific.net/SSP.393.47.pdf

S. Strüber 1,a, C. Grazzi 1,b, L. Tana 1,c, O. Schneider 1,d, T. Wagner 1,e, J. Wiedemann 1,f, P. Wunder 2, g, P. J. Wellmann h*

¹Crystal Growth Lab, Materials Department 6, ²Engineering Workshop, Faculty of Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, 91058 Erlangen, Germany

a  sven.strueber@fau.de, b  cristina.grazzi@fau.de, clucrezia.tana@fau.de, d  ole.schneider@fau.de, 

e wato.t.wagner@fau.de, f jakob.wiedemann@fau.de, g philipp.wunder@fau.de, h*peter.wellmann@fau.de

Keywords: close space PVT, CS-PVT growth, 4H-SiC, bulk growth, thick epitaxy, doping.

Abstract

Close Space PVT (CS-PVT) is a modification of standard PVT exhibiting a short source-to-seed-distance and enabling a large variety of growth process variations to meet the specific requirements of the SiC material (i.e. special polytype and/or doping) to be grown. In this work, we study the growth of 4H−SiC p-i-n structures exhibiting thick SiC layers to be used as SiC photovoltaic cells for remote power transfer in space. Nevertheless, the found results are also applicable (i) to the SiC thick layer growth of power electronic devices and (ii) SiC pucks with a thickness of up to 10 mm . In addition, we present the new type of growth machine TableTopCS TM in its design being dedicated for the special crucible configuration of CS-PVT.

Introduction

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Recently silicon carbide (SiC) has proven to offer physical properties which are not only advantageous for power electronics, but also for photonic applications like photocatalytic water splitting, fluorescent SiC, and waveguide applications. In this field of application, special SiC bulk materials exhibiting intrinsic properties and p-type doping are needed. In addition to 4H−SiC, also 3C-SiC and 6 H -SiC are of importance. Close Space PVT (CS-PVT), which is a modification of standard PVT exhibiting a short source-to-seed-distance, enables a large variety of growth process variations to meet the specific requirements of the SiC material (i.e. special polytype and/or doping) to be grown. This for example enabled the bulk growth of 3C-SiC [1] which profits from a high supersaturation and a Si-rich gas phase composition. Indication for the high crystalline quality of CSPVT grown hexagonal SiC was already proven in the early work of Syväjärvi and Yakimova [2, 3].

In this work, we study the growth of 4H−SiCp−i−n structures to be used as SiC solar cells for remote power transfer in space using laser power converter (LPC) devices. Note: The presented growth method is also applicable for the fabrication of large area SiC wafers and p−/i−/n-layer stacks as used in power electronics. We used the CS-PVT method [4], which bridges the gap between the state-of-the-art bulk growth of SiC using the PVT method (boule thickness of 1−50 mm ) and the chemical vapor deposition (CVD) of thin SiC films in the thickness range of ca. 1 to 100μ m. In addition to the SiC growth study, we will also introduce the newly developed TableTopCS TM growth machine which meets special requirements for advanced CS-PVT growth. While this work mainly shows results of 100 mm4H−SiC layer deposition, growth cells of 150 mm CS-PVT are already applied in the lab.

In the following we are addressing in this study (i) the achieved 4H−SiC polytype stability and (ii) new aspects of advanced p-type doping by aluminum which are possible in the ballistic mass transport regime of CS-PVT.

Growth Experimental Procedure

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CS_PVT process.

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The CS-PVT growth configuration makes use of a solid SiC (single-)crystalline source and a single-crystalline seed which are separated by a spacer in the range of 0.5 to 2 mm . Mass transport from source to seed is established by establishment of a T-difference between source and seed. Typical axial T-gradients can be as low as a few ∘C/cm but may reach above 100∘C/cm. One technical solution to realize CS-PVT growth is to place basic CS-PVT stack out of SiC source, spacer and SiC seed in a standard PVT growth crucible as sketched in Fig. 1.

[picture]

Fig. 1. (a) Sketch of the CS.PVT growth cell [1]. (b) Examples of a standard PVT growth reactor hosting the CS-PVT growth cell.

Fig. 1. (a) Sketch of the CS.PVT growth cell [1]. (b) Examples of a standard PVT growth reactor hosting the CS-PVT growth cell.

TableTopCSTMGrowth Machine.

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In order to have more control of the growth parameters in CS-PVT, a new growth machine was designed and produced which heating system and technical implementation match the needs of the close space sublimation process. As indicated in the name "TableTopCS TM " the new system is a  compact setup with small footprint (Fig.2a) and which is designed for optional usage in cleanroom for electronic device fabrication.

[picture]

Fig. 2. (a) Sketch of the outer view of the new CS-PVT growth tool TablTopCS TM. (b) Greyscale optical image of one of the first 150 mm4H−SiC samples prepared in the new growth tool.

Fig. 2. (a) Sketch of the outer view of the new CS-PVT growth tool TablTopCS T M . (b) Greyscale optical image of one of the first 150 m m 4 H − S i C samples prepared in the new growth tool.

CS-PVT Growth Process Parameter Setting.

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The p-i-n structures were fabricated in two consecutive CS-PVT growth runs. As substrate we used 100 mm4H−SiC wafers ( 4∘ off-axis) either C -face or Si -face oriented to carry out homoepitaxial nucleation and growth of 4H−SiC (figure 1), respectively. The growth temperature measured at the top of the CS-PVT growth cell was 1900∘C (growth rate ca. 50μ m/h ). The background gas pressure was <0.1mbar. In the first step nitrogen doped n-type or nominally undoped, quasi-intrinsic layers (either residual n-type or residual p-type) with a thickness of ca. 100μ m layer were deposited (growth time =2 h ). Intentional p -type doping of the second thin top layer (growth time =10 min to 2 h ) was performed by using aluminum doped solid 4H−SiC:Al and 6H−SiC:Al sources which were prepared by the M-PVT method [5].

Results and Discussion

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Properties of4H−SiClayer stacks onC−faceseeds.

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In standard PVT growth above 2000∘C it is standard to grow a 4H−SiC crystal on c-face seeds. However, Si-face seeding fails, because of a heteroepitaxial transition of the polytype to 6H−SiC and 15−SiC.

[picture]

Fig. 3. (a) Examples of a high quality 4H−SiC layer (ca. 100μ m ) deposited on 100 mm4H−SiC Substrate (c-face). (b) Raman spectra of two CS-PVT grown 100μ m thick 4H−SiC layer on a Siface 4H−SiC ( 4∘ off-axis) substrate.

Fig. 3. (a) Examples of a high quality 4 H − S i C layer (ca. 100 μ m ) deposited on 100 m m 4 H − S i C Substrate (c-face). (b) Raman spectra of two CS-PVT grown 100 μ m thick 4 H − S i C layer on a Siface 4 H − S i C ( 4 ∘ off-axis) substrate.

Intentional p-type doping of the second thin top layer (growth time =10 min ) was performed by using aluminum doped solid 4H−SiC:Al and 6H−SiC:Al sources which were prepared by the M-PVT method [5] (see section "Doping during CS-PVT growth"). Also in this case, the 4H-SiC polytype prevailed.

Polytype stability of4H−SiClayers on Si-face seeds.

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As mentioned above, in standard PVT at temperatures above 2000∘C growth of bulk 4H−SiC fails, a polytype switching to 6H−SiC and 15R−SiC is observed. However, chemical vapor deposition (CVD) growth of 4H−SiC performed at 1600 to 1700∘C is routinely performed on Si -face SiC seed wafers. One important finding of this work is that 4H−SiC CS-PVT growth at 1900∘C is possible on Si -face substrates making CS-PVT growth compatible with the SiC device processing routine (on Si face substrates) exhibiting comparably high growth rates of 50 to 200μ m/h. The Raman spectrum in Fig. 4 proves the high 4H−SiC polytype stability when growth is carried out on the Si -face. This finding was not expected because often we find reports in literature indicating CS-PVT on Si -face (0001) oriented SiC wafers being favorable to switch to the cubic polytype 3C-SiC [6, 7].

[picture]

Fig. 4. Raman spectra of a CS-PVT grown 100μ m thick 4H−SiC layer on a Si-face 4H−SiC(4∘ offaxis) substrate.

Fig. 4. Raman spectra of a CS-PVT grown 100 μ m thick 4 H − S i C layer on a Si-face 4 H − S i C ( 4 ∘ offaxis) substrate.

The result suggests further exploration of the applicability of CS-PVT for the growth of intrinsic, thick 4H−SiC layers for power electronic applications. One of the challenges will be to limit the residual charge carrier concentration to values in the 1014−1015 cm−3 range.

Doping during CS-PVT growth.

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In sublimation growth doping of SiC by aluminum is rather challenging because of the much greater partial pressure of the Al gas species compared to Si - and C -related gas species (i.e. Si,Si2C and SiC2 ). Without special emphasis like in the M-PVT growth process, it is basically impossible to obtain homogeneous dopant incorporation. CS-PVT, however, enables a new growth mode for advanced doping which makes use of ballistic mass transport. At a low background gas pressure of <0.1 mbar we showed earlier [8] that ballistic mass transport dominates the mass transport between the closely spaced SiC source and SiC seed (distance <1 mm ). In such ballistic growth mode, the phenomenon of the partial pressure of atomic or molecular species does not exist and the species are directly transported from source to seed.

In this study, we demonstrate dopant transfer from the source to the seed using nitrogen. Unlike standard PVT, where nitrogen is added as a gaseous source, CS-PVT uses intentionally nitrogendoped SiC sources.

Table 1. Overview of the transfer of N dopants from the SiC source to the SiC seed/crystal in the CS-PVT growth system under ballistic growth conditions. Note that the dopant concentration was determined using Raman spectroscopy by analyzing the energetic position and shape of the LOPC peak.

Sample | SiC Source | T-growth | Ambient | Charge carrier concentration [cm⁻³]
|  |  |  | SiC source | SiC layer
K.170CS | n-type (N) | 1900°C | Vacuum | 1.7(±0.2)10¹⁸ | 1.1(±0.2)10¹⁸
K.187CS | n-type (N) | 1900°C | Vacuum | 2.8(±0.3)10¹⁷ | 7.7(±0.3)10¹⁷

4H-SiC p-i-n-layer stacks.

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Using the above describe deposition, p-i-n layer stacks were prepared comprising two subsequent growth runs for the nominally first intrinsic or better to say slightly n-type 4H−SiC layer and a second highly p-type doped 4H−SiC:Al layer. The growth time and layer thicknesses were 2 hours and 125 μm for the n-type layer and 10 minutes and 6μ m for the p-type layer (see sample cross section in Fig. 5), respectively.

[picture]

Fig. 5. Cross-sectional optical images of 4H−SiCp−i−n structure.

Fig. 5. Cross-sectional optical images of 4 H − S i C p − i − n structure.

Summary

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We have shown that CS-PVT has been successfully applied to grow thick C-face 4H−SiCp−i−n− layer stacks and with high polytype stability for application in photonic LPC devices.

We have demonstrated that even growth of 4H−SiC on Si -face 4H−SiC is possible with high polytype stability suggesting the usage of CS-PVT for the growth of thick intrinsic 4H−SiC layers for power electronic applications.

The establishment of a ballistic mass transport regime in CS-PVT enabled the efficient direct aluminum dopant transfer for fabrication of p-type SiC.

While the presented results are mainly shown for layers below 150μ m, in a previous study we already emphasized that CS-PVT is applicable to grow bulk SiC pucks of 3−5 mm in height. Technologically, to keep constant growth conditions a crystal height of ca. 10 mm should be achievable.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.393.47.pdf

This work is funded by the European Union, Horizon Europe contract #101160868 (RePowerSiC).

References

The original version of this paper is available on https://www.scientific.net/SSP.393.47.pdf

F. La Via, M. Zimbone, C. Bongiorno, A. La Magna, G. Fisicaro, I. Deretzis, V. Scuderi, C. Calabretta, F. Giannazzo, M. Zielinski, R. Anzalone, M. Mauceri, D. Crippa, E. Scalise, A. Marzegalli, A. Sarikov, L. Miglio, V. Jokubavicius, M. Syväjärvi, R. Yakimova, P. Schuh, M. Schöler, M. Kollmuss,P. Wellmann, Materials, 14, 18, 5348 (2021).

M. Syväjärvi, R. Yakimova, P.-A. Glans, A. Henry, M. F. MacMillan, L. I. Johansson,E. Janzen, Journal of Crystal Growth, 198-199, 1-4, 1019 (1999).

R. Yakimova, N. Vouroutzis, M. Syväjärvi, J. Stoemenos, Journal of Applied Physics, 98, 3, 034905 (2005).

M. Kollmuss, M. Schöler, R. Anzalone, M. Mauceri, F. La Via, P. J. Wellmann, Materials Science Forum, 1062, 74 (2022).

P. Wellmann, P. Desperrier, R. Mueller, T. Straubinger, A. Winnacker, F. Baillet, E. Blanquet, J. M. Dedulle, M. Pons, Journal of Crystal Growth, 275, 1-2, e555 (2005).

V. Jokubavicius, G. R. Yazdi, R. Liljedahl, I. G. Ivanov, R. Yakimova, M. Syväjärvi, Crystal Growth and Design, 14, 12, 6514 (2014).

V. Jokubavicius, G. R. Yazdi, R. Liljedahl, I. G. Ivanov, J. Sun, X. Liu, P. Schuh, M. Wilhelm, P. Wellmann, R. Yakimova, M. Syväjärvi, Crystal Growth & Design, 15, 6, 2940 (2015).

T. Hupfer, P. Hens, M. Kaiser, V. Jokubavicius, M. Syväjärvi, P. J. Wellmann, Materials Science Forum, 740-742, 52 (2013).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 53-58

doi: 10.4028/p-LHD7xc

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-20

Accepted:
2026-03-21

Online:
2026-05-18

Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

The original version of this paper is available on https://www.scientific.net/SSP.393.53.pdf

J. Zöcklein 1,a, S. Strüber 1,b, C. Grazzi 1,c, N.-C. Arneberg 2,d, T. Straub 2,e, S. Greulich-Weber 2,f, P. J. Wellmann 1, g*

1 Crystal Growth Lab, Materials Department 6, Friedrich-Alexander-Universität Erlangen-Nürnberg, 91058 Erlangen, Germany

2 The Yellow SiC Company GmbH, Römereschstr. 33, 49090 Osnabrück, Germany

ªjulian.zoecklein@fau.de, b sven.strueber@fau.de, c cristina.grazzi@fau.de, d arneberg@yellowsic.com, e straub@yellow-sic.com, f greulich-weber@yellow-sic.com, g peter.wellmann@fau.de

Abstract

We have investigated the applicability of a new type of 3C−SiC powder source material during PVT growth which consist of a particle size of ca. 10μ m (aggregates up to ca. 150μ m ). Insitu X-ray visualization of 75 mm and 100 mm PVT growth runs showed a smooth SiC powder consumption during growth. Using Raman spectroscopy, we have found a high 4H−SiC polytype stability and a low residual stress distribution in the intentionally n-type doped grown crystals.

Keywords: PVT growth, 4H−SiC, source material, 3C−SiC, in-situ X-ray visualization.

Introduction

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In PVT growth of SiC crystals, the proper choice of the SiC source material plays an important role because the grain size distribution and the effective packing density have a strong impact on the effective heat conductivity of the SiC source and therefore on the temperature field inside the growth cell [1]. Additionally, the effective surface area and the SiC polytype influence the gas phase composition and C/Si ratio. The latter being related to the different formation energy and surface energies of the various SiC polytypes [2]. Although SiC crystal growers hardly comment on their choice of the SiC powder source, often grain sizes above 500μ m are applied exhibiting a comparatively larger heat conductivity and lower effective surface of the SiC powder assembly [3]. Concerning the SiC source polytype, by trend the 6H−SiC polytype from direct Si+C synthesis or from purified Acheson material plays an important role in the global market. In addition, 3C−SiC stemming from a chemical vapor deposition synthesis is also applied in PVT growth.

In this work we have studied the application of a new type of small grain 3C-SiC powder source during PVT growth (aggregates of ca. 150μ m, single particle size of ca. 10μ m, The Yellow SiC Company GmbH ). In conjunction with the new patented [4] development of the 3 C SiC powder source, small batches of the material have been used in a 75 mm and 100 mm PVT system consisting of an in-situ 2D/3D computed tomography X-ray visualization tool [5].

Experiments

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PVT Growth Process.

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Four PVT growth were carried out in a standard 75 mm and 100 mm PVT configuration [3] for 120 h at the growth temperature of ca. 2050∘C (crucible top) using nitrogen gas for n-type doping. The average growth rate was 125μ m/h. As seeds 4∘ off-axis (000-1) oriented 4H−SiC material was applied. Intentionally, no special efforts were made to adapt the growth process to the properties of the newly applied SiC source. Because of the variability of the thermal conductivity of the SiC source (e.g. expected lower thermal conductivity of the used small grain powder used in this study), the process window of 4H−SiC may slightly shift. Such issue could be addressed in a forthcoming iteration step, by slightly adjusting the hot zone design. All growth runs were monitored using in-situ X-ray visualization of the growth process [5].

SiC source Material.

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An ultra-pure fine-grain 3C-SiC powder source (Fig. 1) for 4 H -PVT growth, with single particle sizes of about 10μ m (aggregates up to approximately 150μ m )(Table 1). The material can be converted from 3 C into 6 H . Both SiC powder sources have already been successfully proven for 4 H -PVT growth and are available in large custom-made quantities.

[picture]

Fig. 1. Microscopic image of the 3C-SiC powder.
Table 1. Size distribution of the 3C−SiC powder source particles.

Fig. 1. Microscopic image of the 3C-SiC powder. Table 1. Size distribution of the 3 C − S i C powder source particles.

Results and Discussion

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SiC powder and crystal evolution.

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Fig. 2 and 3 depict the evolution of the SiC crystal shape and the SiC source morphology using insitu X-ray visualization.

[picture]

Fig. 2. In-situ X-ray images of the gas-room area including the growing SiC-crystal ( 75 mm system) of the growth crucible. The evolution of a smooth and slightly convex growth interface is observed which indicated stable growth conditions.

Fig. 2. In-situ X-ray images of the gas-room area including the growing SiC-crystal ( 75 mm system) of the growth crucible. The evolution of a smooth and slightly convex growth interface is observed which indicated stable growth conditions.

[picture]

Fig. 3. In-situ X-ray images of the SiC-source area of the crucible at the beginning and at the end (before cooling down) of the growth process. As intended, the SiC source shrinks in the central area.

Fig. 3. In-situ X-ray images of the SiC-source area of the crucible at the beginning and at the end (before cooling down) of the growth process. As intended, the SiC source shrinks in the central area.

The SiC crystal (Fig. 2) exhibits throughout the complete growth process a stable and slightly convex growth interface, which enables outgrowth of structural defects. The corresponding X-ray images of the SiC source (Fig. 3) confirm the overall favorable growth conditions. The final shape of the residual SiC source material indicates that a steady SiC gas species transport took place from the hot crucible walls (inner side wall and crucible bottom) towards the central SiC source core and upward to the SiC source top. In addition, no upgrowth into the gas room is observed, which would interfere with the growing SiC crystal.
Fig. 4 depicts a series of in-situ X-ray images of the SiC powder evolution in the 100 mm PVT system. The packing density of the SiC source material inside the growth cell is ca. 45%. Note: This value is currently further increased to the widely desired value between 50 and 60%. From the beginning of the growth process, a dense disk-like structure is formed on the top of the SiC powder which shields the crystal growth area above from the further SiC source evolution below [6, 7]. Allover, a smooth consumption of the SiC powder is observed throughout the growth process. Like in the 75 mm system (Fig. 3), again no upgrowth into the gas room is observed, which would interfere with the growing SiC crystal. Also in the 100 mm PVT system, the crystal growth interface exhibits the targeted, only slightly convex growth interface ( 91 h growth stage in Fig. 4). The observed SiC powder consumptions in the 75 mm and 100 mm system follow quite well the reference growth runs in the former reports in [8] and [9], respectively.

[picture]

Fig. 4. In-situ X-ray images of the SiC-source area of the growth crucible ( 100 mm system) at three stages (shortly after start, mid-time, almost end) of the growth process.

Fig. 4. In-situ X-ray images of the SiC-source area of the growth crucible ( 100 mm system) at three stages (shortly after start, mid-time, almost end) of the growth process.

The fine grain 3C−SiC powder studied in this work performs in both PVT systems ( 75 mm and 100 mm) in a way that stable growth conditions are observed. Note: It was not investigated at which growth stage the 3C−SiC powder may have switched to 6H−SiC polytype by sublimation and recrystallization.

Properties of the grown crystals and prepared wafers.

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Fig. 5 a depicts an optical image of a 75 mm SiC wafer cut from the SiC boule shown in the in-situ X-ray image in Fig. 2 ( 120 h stage). Although the SiC source deviates in its morphologic properties from "unofficial" specks of many crystal growers in the SiC PVT field, a very high 4H-SiC polytype stability is observed during PVT growth. The brownish-orange color in the optical wafer image in Fig. 5a indicates the 4H-SiC polytype stability. No unintentional polytype switches to 6H−SiC or 15 R SiC are observed. Raman measurements (Fig. 5b) further confirm the high 4H−SiC polytype stability and indicate a charge carrier concentration of 2*1018 cm−3 which (because of incomplete electrical activation of the donors) corresponds to an intended high chemical nitrogen incorporation of ca. 68*1018 cm−3, almost 1019 cm−3, as typical in commercial wafers.

[picture]

Fig. 5. (a) Optical mapping of a wafer ( 75 mm growth run) close to the crystal cap. (b) Raman spectrum of the sample.

Fig. 5. (a) Optical mapping of a wafer ( 75 mm growth run) close to the crystal cap. (b) Raman spectrum of the sample.

The SiC wafer exhibits a residual stress level of 25(+/−10)MPa which is quite a low value for the special small growth cell used in this study. In principle, the low value could also be related to stress relaxation after cracking.

[picture]

Fig. 6. Optical image of the step structure of the crystal cap of a 75 mm (a) and 100 mm (b) SiC crystal presented in the in-situ X-ray images of Fig. 2 and Fig. 4. The macro-step height is about 3−10(±0.5)μm(a) and 1.5−2.5(±0.5)μm(b), respectively.

Fig. 6. Optical image of the step structure of the crystal cap of a 75 mm (a) and 100 mm (b) SiC crystal presented in the in-situ X-ray images of Fig. 2 and Fig. 4. The macro-step height is about 3 − 10 ( ± 0.5 ) μ m ( a ) and 1.5 − 2.5 ( ± 0.5 ) μ m ( b ) , respectively.

Nevertheless, the reported low values in this study were found in the center of the large wafer piece in Fig. 5a which already reflects very good bulk property and cannot be explained by stress-release due to the cracking phenomena alone.
The post growth analysis of the growth step structure at the crystal cap (Fig. 6) indicate ideal conditions for 4H−SiC growth stability as they have been documented in literature for a high C/S ratio in the gas phase and nitrogen doping (see e.g. [10]). The smooth growth interface exhibits macrosteps with a varying distance of 50 to 500μ m (macro-step height of ca. 3−10(±0.5)μm ) and 20 to 100μ m (macro-step height of ca. 1.5−2.5(±0.5)μm ), respectively. Because of the asymmetric motion kinetics of the steps due to nitrogen doping [11, 12] the probability of unintentional polytype changes is reduced and 4H−SiC growth is stabilized.

Summary

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We have found that the newly developed fine grain 3C−SiC source material enables a smooth sublimation-recrystallization evolution of the SiC powder source. Noteworthy, no adaption of the hotzone design was carried out compared to the often used FAU 6H−SiC powder with a larger grain size in the 300−500μ m range. Hence, the application of the new 3C−SiC source did not demand any growth procedure adaptation.
A technologically relevant high 4H−SiC polytype stability is observed which is supported by the quantitative analysis of the step structure at the crystal cap proving stable/smooth 4H−SiC growth conditions

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.393.53.pdf

This work was financially supported by The Yellow SiC Company GmbH, Germany.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.53.pdf

M. Arzig, M. Salamon, N. Uhlmann, B. A. Johansen, P. J. Wellmann, Materials Science Forum, 924, 245 (2018), 10.4028/www.scientific.net/MSF.924.245.

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P. J. Wellmann, M. Bickermann, D. Hofmann, L. Kadinski, M. Selder, T. L. Straubinger, A. Winnacker, Journal of Crystal Growth, 216, 263 (2000), 10.1016/s0022-0248(00)00372-9.

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J. Steiner, M. Arzig, T. C. Hsiao, P. J. Wellmann, Materials Science Forum, 963, 42 (2019), 10.4028/www.scientific.net/MSF.963.42.

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 59-64

doi: 10.4028/p-NdIf3k

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-23

Revised:
2026-02-04

Accepted:
2026-02-23

Online:
2026-05-18

Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

Chae-Young Lee 1,a*, Su-Ho Kim 1,b, Jung Woo Choi 1,c, Myung-Ok Kyun 1,d, Jung Gyu Kim 1,e, Kap-Ryeol Ku 1,f, Yeon-Suk Jang 1, g, Jung-Gon Kim 2, h, Won Jae Lee 2,, *

1 Senic, 17-15, 4sandan 7-ro, Jiksan-eup, Seobuk-gu, Cheonan-si, Chungcheongnam-do, Republic of Korea

2 Dong-Eui University, 176, Eomgwang-ro, Busanjin-gu, Busan, Republic of Korea

a  cylee@eincrystal.co.kr, b  shkim@eincrystal.co.kr, c  jwchoi@senic.co.kr, d  bjk006@eincrystal.co.kr, ejgkim@senic.co.kr,  krku@senic.co.kr, g  ysjang@senic.co.kr, h  kimjg@deu.ac.kr, ileewj@deu.ac.kr 

Abstract

Seed crystal stabilization during the initial stage of 200−mm4H−SiC crystal growth is critical for achieving high-quality wafers with large diameters. This study investigated the effects of heating ramp rates ( 0−6∘C/min ) and SiC source powder porosity through both simulation and experimental approaches. Low ramp rates resulted in surface degradation of the seed crystal, whereas high ramp rates induced significant thermal stress, leading to cracking. Optimal ramp rates of 3−5∘C/ min significantly minimized damage caused by seed crystal loss. Furthermore, high-porosity source powder facilitated adequate gas transport channels, thereby enhancing seed crystal stability. Crystals grown under these optimized conditions demonstrated improved edge morphology, absence of polycrystalline inclusions, and low dislocation densities, with threading screw dislocations (TSD) below 500 cm−2 and basal plane dislocations (BPD) below 1,000 cm−2. These results demonstrate that precise control of thermal parameters and source powder porosity offers an effective strategy for stable seed attachment and reproducible growth of high-quality, large-diameter SiC single crystals.

Keywords: 4H−SiC,8-inch SiC growth, Physical vapor transport, Single crystal, Ramp rates, Gas flow, Source powder

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

The next generation of wireless infrastructure will rely on wide bandgap semiconductors such as SiC and GaN due to their superior physical properties, including a large bandgap, high thermal conductivity, and high breakdown field. [1,2] In the SiC wafer-based device industry, increasing the wafer diameter is critically needed to enhance economic viability and production efficiency. [3, 4] Current research is intensively aimed at producing high-quality 8 -inch SiC crystal ingots, with a strong focus on preventing internal polycrystalline inclusions. Ensuring the stability of the seed crystal during the initial growth stage is essential for achieving reliable and consistent crystal growth. In this study, we investigated the effects of heating ramp rates and source powder porosity on the growth of 8-inch 4H-SiC crystals. These factors can influence damage to the seed crystal during the initial growth stage, as well as affect the quality of the final crystal. Prolonged thermal exposure at low ramp rates leads to surface degradation and seed crystal detachment at the initial growth stage. In contrast, a fast ramp rate can induce steep thermal gradients, increasing the thermal stress mismatch between the seed crystal and the graphite lid, which often leads to cracking and seed detachment. [5, 6] To address these issues, SiC powders with varying porosities were utilized to optimize gas transport channels under appropriate heating ramp rates, aiming to stabilize the flow of sublimated gas species during the initial growth stage.

Experiments

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

The growth of 200−mm4H−SiC crystals was conducted at temperatures ranging from 2300 to 2400∘C under a growth pressure of 20 torr, using both N2 and Ar atmospheres. 4∘ off-axis, c-face substrates were used as seed crystals. Simulations were conducted using Virtual Reactor software (STR Software) during the initial growth process with heating ramp rates ranging from 0 to 6∘C/min. Additionally, seed crystal damage tests were performed based on the porosity of the SiC source powder. The defect density near the top (facet region) and bottom (near seed region) of SiC crystals grown under high gas flow conditions was examined following KOH etching. The spatial distribution of defects, including micropipes, inclusions, and stacking faults, was analyzed using a Candela system (KLA-Tencor Corp.).

Result and Discussion

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

Figure 1 (a) presents a schematic diagram of the experimental setup. The left diagram shows the thermal field at higher ramp-up rate, while the right one depicts that at a lower ramp-up rate near the seed region. Simulations were performed in the initial process with heating ramp rates ranging from 0 to 6∘C/min. Figurel (b) exhibited the relationship between the seed loss-induced damage width (mm) and the heating ramp rate ( ∘C/min ) during the initial stage of crystal growth. The damage width represents the actual measured length from the single crystal toward the crystal edge where degradation begins, as identified through optical microscopy of the grown ingot. It is clear that ramp rates of 3~5∘C/min can effectively decrease the damage width of seed crystal. Compared with the narrower thermal field at a lower ramp-up rate, a higher ramp-up rate broadens the thermal field, thereby reducing thermal etching in the seed region and consequently decreasing seed damage. The determination coefficient (R2=0.9433) signifies that the trend line accounts for approximately 94.3% of the variation in damage width ( mm ) relative to ramp rate ( ∘C/min ), demonstrating a strong correlation between ramp rate adjustments and the extent of seed crystal damage reduction.

[picture]

Fig. 1 Schematic diagram of the experimental setup configuration and (b) plot of seed loss-induced damage width ( mm ) as a function of heating ramp rates ( ∘C/min ) at the initial growth stage. R2 shows the result of quadratic curve-fitting.

Fig. 1. Schematic diagram of the experimental setup configuration and (b) plot of seed loss-induced damage width ( mm ) as a function of heating ramp rates ( ∘ C / m i n ) at the initial growth stage. R 2 shows the result of quadratic curve-fitting.

Figure 2 shows (a) a schematic illustration of gas flow channel distributions in the SiC source powder region under low and high porosity conditions, and (b) the variation of damage width (mm) as a function of the gas flow channel formed within the source powder. The damage width of the seed crystal was significantly reduced under conditions of high gas flow channels (high porosity) in the SiC source powder. The determination coefficient (R2=0.9611) indicates that the trend line explains approximately 96.1% of the variation in damage width ( mm ) with respect to the powder porosity of the SiC source powder, highlighting a marked correlation between gas flow channel adjustments and the reduction of seed crystal damage. Based on the simulation results, crystal growth experiments were carried out by the PVT method using two configurations with different ramp rates and source powder porosities.

[picture]

Fig. 2 (a) Schematic diagram of the channel distributions for gas flow at low and high porosity of SiC source powder and (b) plot of the damage width (mm) as a function of the gas flow channel of the SiC source powder. R2 shows the result of quadratic curve-fitting.

Fig. 2. (a) Schematic diagram of the channel distributions for gas flow at low and high porosity of SiC source powder and (b) plot of the damage width (mm) as a function of the gas flow channel of the SiC source powder. R 2 shows the result of quadratic curve-fitting.

Figure 3 presents the numerical simulation results illustrating the effect of source material porosity on the internal thermal distribution and the resulting mass transport characteristics driven by the temperature gradient between the source and the seed. Porosity determines the resistance to gas-phase transport through the source material. Higher porosity generally increases the permeability, allowing for more efficient mass transport. The six measurement points in the graphite crucible are defined as follows: P 1 , center of the crystal; P 2 , edge of the crystal; P3−P4, surface of the source material; and P5-P6, bottom of source material. With increasing porosity ( 0.2 to 0.7 , ), an enhancement in vapor transport of SiC source species from the source is observed.

[picture]

Fig. 3 Numerical simulation of the effect of source material porosity on internal thermal gradients and mass-transport characteristics. The six measurement points in the graphite crucible are defined as follows: P 1 , center of the crystal; P 2 , edge of the crystal; P3−P4, surface of the source material; and P5-P6, bottom of source material.

Fig. 3. Numerical simulation of the effect of source material porosity on internal thermal gradients and mass-transport characteristics. The six measurement points in the graphite crucible are defined as follows: P 1 , center of the crystal; P 2 , edge of the crystal; P 3 − P 4 , surface of the source material; and P5-P6, bottom of source material.

Figure 4 presents the dependence of (a) mass source, (b) sublimation rate, (c) C/Si ratio, (d) SiC2 ratio, (e) Si2C ratio and (f) Si ratio on the porosity of the source material. These ratios (SiC2,Si2C,Si ratio, dimensionless quantity) represent the partial pressure share or mole fraction of each species within the total gas phase. Notably, at a porosity of 0.4 , the C/Si ratio in the seed surface region reached a stabilized state. This stabilization is attributed to the simultaneous increase in carbon-carrying species SiC2 and Si2C and a corresponding decrease in the Si ratio, suggesting that a porosity of 0.4 provides an optimal balance between thermal distribution and gas-phase stoichiometry for high-quality SiC growth. Figure 5 shows optical images (left half) and UVF images (right half) of SiC ingots grown under (a) non-optimal porosity and (b) optimal porosity conditions of the source powder.

Due to the minimized seed crystal loss, the SiC ingot grown at a porosity of 0.4 exhibited superior edge quality and was free of polycrystalline regions compared with ingots grown under other porosity conditions.

[picture]

Fig. 4 Dependence of (a) mass source, (b) sublimation rate, (c) C/Si ratio, (d) SiC2 ratio, (e) Si2C ratio and (f) Si ratio on the porosity of the source material. SiC2,Si2C, and Si ratios are dimensionless quantities.

Fig. 4. Dependence of (a) mass source, (b) sublimation rate, (c) C / S i ratio, (d) S i C 2 ratio, (e) S i 2 C ratio and (f) Si ratio on the porosity of the source material. S i C 2 , S i 2 C , and Si ratios are dimensionless quantities.

[picture]

Fig. 5 Optical images (left half) and UVF images (right half) of SiC ingots grown under non-optimal porosity (a) and optimal porosity (b) conditions of the source powder. The bluish regions at the upper and lower ends of the ingots represent optical illusions caused by interference.

Fig. 5. Optical images (left half) and UVF images (right half) of SiC ingots grown under non-optimal porosity (a) and optimal porosity (b) conditions of the source powder. The bluish regions at the upper and lower ends of the ingots represent optical illusions caused by interference.

Defect densities at the top (near the surface region) and bottom (near the seed region) of the SiC crystal grown under optimal porosity conditions (porosity: 0.4 ) were investigated after KOH etching and are summarized in Table 1. Both threading screw dislocation (TSD) and basal plane dislocation (BPD) densities were found to be below 500 cm−2 and 1,000 cm−2, respectively, indicating high crystalline quality. As shown in Fig. 6, growth under optimal porosity conditions resulted in low TSD and BPD densities, confirming the high crystal quality. Moreover, defect densities at the top and bottom of the wafer were comparable.

Table 1. Defect densities of the SiC crystal measured at the top (facet region) and bottom (near seed region) after KOH etching, under optimal porosity growth conditions.

Measurement positions | TSD (ea/cm²) | BPD (ea/cm²) | TED (ea/cm²) | EPD (ea/cm²)
Top | 450 | 1,000 | 2,100 | 3,550
Bottom | 480 | 920 | 2,300 | 3,700

*Threading Screw Dislocation (TSD), Basal Plane Dislocation (BPD), Threading Edge Dislocation (TED),
Etch Pit Density (EPD)

Fig. 6 Defect levels at the top (near surface) and bottom (near seed) of SiC crystals grown under optimal porosity conditions, measured using a Candela system (KLA-Tencor Corp.).

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

This study demonstrates that optimizing process parameters during the initial stage of SiC single crystal growth is crucial for minimizing damage caused by seed loss. Both simulations and experimental results confirm that heating ramp rates between 3 and 5∘C/min combined with higher porosity of the SiC source powder significantly reduce seed damage. SiC ingots grown under these optimized conditions exhibit superior edge quality, absence of polycrystalline regions, and low dislocation densities (TSD <500 cm−2,BPD<1,000 cm−2 ). These findings establish an effective process strategy for producing high-quality SiC single crystals and provide practical guidance for large-diameter crystal growth.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

This work was supported by Technology Innovation Program (Project Number: 00402234, Project Name: Development of highly flat, highly clean large area polished SiC single crystal wafers by utilizing advanced process technology for power semiconductor application) funded by the Ministry of Trade, Industry and Energy.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.59.pdf

J. R. Jenny, D. P. Malta, St G. Müller, A. R. Powell, V. F. Tsvetkov, H. McD Hobgood, R. C. Glass, C. H. Carter Jr., Journal of Electronic Materials, 32, 432-436 (2003).

M. V. S. Chandrashekhar, I. Chowdhury, P. Kaminski, R. Kozlowski, P. B. Klein and T. Sudarshan, Applied Physics express 5, 025502 (2012).

I. Manning, K. Moeggenborg, A. Soukhojak, J. Searson, M. Gave, G. Chung, E. Sanchez, Materials Science Forum, 1062, 54-58 (2022).

S. Zhang, G. Fu, H. Cai, J. Yang, G. Fan, Y. Chen, T. Li, L. Zhao, Materials, 16(2), 767 (2023).

J. Steiner, P. J. Wellmann, Materials, 15(5), 1897 (2022).

J. Pezoldt, V. Cimalla, Crystals, 10(6), 523 (2020).

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 65-70

doi: 10.4028/p-gZ2hnG

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-10

Accepted:
2026-02-23

Online:
2026-05-18

Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

Birgit Kallinger 1,a*, Christian Gobert 1, b, Maximilian Titl 1,c, Robin Karhu 1, d, Johannes Köhler 2,e and Jürgen Erlekampf 2,f

1 Fraunhofer IISB, Schottkystr. 10, 91058 Erlangen, Germany

2 AIXTRON SE, Schottkystr. 10, 91058 Erlangen, Germany

a*birgit.kallinger@iisb.fraunhofer.de,b christian.gobert@iisb.fraunhofer.de, c  maximilian.titl@iisb.fraunhofer.de, d  Robin.Karhu@iisb.fraunhofer.de, ej.koehler@aixtron.com,  fj.erlekampf@aixtron.com

Keywords: epitaxial growth, precursors, defects, isotopically enriched, quantum technology.

Abstract

This paper compares ethene and methane precursors for homoepitaxial 4H−SiC growth in planetary reactors with regards to their impact on growth rate and defectivity of the epilayers. Therefore, a comprehensive experimental study has been performed in AIXTRON G10-SiC and G5WW C planetary reactors using a standard process based on ethene and trichlorosilane precursors with conventional 150 mm n-type 4H-SiC substrates from 3 different international suppliers. Methane substituted ethene as precursor in many experiments. It was found that methane precursor can compete with ethene in terms of growth rate, epilayer thickness, and defectivity of the epilayers. By using isotopically enriched methane, Si12C epilayers with a 12C concentration of 99.96% have been grown which can be used for SiC-based quantum technology.

Introduction

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

Silicon Carbide (4H−SiC) has outstanding properties for applications in energy efficient power electronics and has been maturing with regards to material quality and device processing technology. Now, the SiC processing costs need to be reduced and the efficiency with regards to energy and resource consumption needs to be improved. For these reasons, we are testing alternative precursors such as methane (CH4) and tetrachlorosilane (SiCl4). These alternatives may enable higher growth rates, better material quality [1] and lower processing costs. Additionally, methane can act as an isotopically enriched precursor for growth of epilayers with a controlled 12C isotope concentration different from the natural isotope mixing ratio, which could be an enabler for SiC -based quantum technology due to the control of the nuclear spin bath concentration. SiC is a very promising candidate for quantum applications due to its silicon vacancy ( Vsisi , which acts as a color center [2] and its mature processing technology. Depending on the desired quantum application, specific isotope concentrations are required, such as a total concentration of 1.0 to 1.5% of 13C and 29Si for nuclear spin qubits addressable as quantum memories [3,4]. Hence, the 13C and 29Si concentrations need to be reduced by using isotopically enriched precursors during epitaxial growth. In the carbon case, methane (CH4) can be purchased with a nominal 12C concentration of 99.99%. This paper investigates the epitaxial growth using methane as a precursor and the characterization of the grown epilayers.

Experimental

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

For this study, conventional n-type 4H-SiC substrates with a diameter of 150 mm from three international vendors A,B, and C were used for epitaxial growth studies in AIXTRON planetary reactors G5WW C and G10-SiC, which are operated in our joint development lab in Erlangen, Germany. The standard growth process is based on ethene and trichlorosilane precursors and uses nitrogen doping for n-type epilayers with the Multi-Ject® technology. This process was adapted to utilize methane as carbon precursor, while trichlorosilane (TCS) was further used as (standard) silicon precursor. The ethene precursor was substituted by methane. Once a suitable methane-based epitaxial
growth process was developed, isotopically purified methane with 99.99%12C and ultra-low nitrogen concentration ( <3ppm ) was employed.

The epilayers grown in this study were characterized with regards to epilayer thickness, doping concentrations and defects by FTIR with a Semilab EIR 2300, capacitance-voltage (CV) measurements with mercury probers, and UV excited photoluminescence imaging (UVPL) in combination with differential interference contrast (DIC) microscopy with a Lasertec SICA 88. Minority carrier lifetime mappings were measured by microwave-detected photoconductivity decay ( μ-PCD) method [5] with a Semilab WT-2000. The 12C isotope concentration was determined by secondary ion mass spectroscopy (SIMS).

Results

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

Growth rate.

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

Many comprehensive growth experiments were conducted in both G5WW C and G10-SiC planetary reactors with ethene or methane precursor. Buffer layers with a thickness of 1μ m to 2μ m were grown as well as drift layers with a thickness up to 40μ m. The epilayer thickness is plotted as a function of the growth time in Fig. 1. The data points were linearly fitted and the slope of the fit yields the typical growth rate of 30μ m/h for both ethene- and methane-based growth processes. Further experiments will be done to increase the growth rate.

[picture]

Fig. 1. Epilayer thickness as a function of growth time for different planetary reactors with different C precursors ethene (standard C precursor) and methane (new C precursor). The slope of the linear fitting, displayed as black dotted line, gives a growth rate of 30 μm/h for these experiments.

Fig. 1. Epilayer thickness as a function of growth time for different planetary reactors with different C precursors ethene (standard C precursor) and methane (new C precursor). The slope of the linear fitting, displayed as black dotted line, gives a growth rate of 30 μ m / h for these experiments.

Defectivity of epilayers.

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

The defectivity of all epiwafers was measured by UVPL and DIC microscopy in a Lasertec SICA 88. Those epiwafers which comply with a 1,200 V epilayer specification (i.e. thickness: 10−14μ m, n-type doping concentration of ( 0.8−2 ) ×1016 cm−3 ) were further analyzed with regards to yield prediction assuming 5×5 mm2 die size and 3 mm edge exclusion. Stacking faults (SF), polytype inclusions, particle inclusions, PL stacking faults as well as PL propagated SF were considered for the yield prediction. Figure 2 shows the defect distribution (of mentioned defect classes) and the yield prediction for epilayers grown on substrates from vendor A,B (in G10−SiC reactor) and vendor C (in G5WW C reactor).

The killer defect density of such 1,200 V epilayers varied between 0.13 cm−2 and 0.94 cm−2 for different substrate vendors and reactor types. Accordingly, the device yield varied from 81.5% to 97.3%, which is comparable to results from conventional ethene based epigrowth processes.

[picture]

Fig. 2. Defect mappings and yield prediction for epilayers grown in different planetary reactors with methane precursor on substrates from different vendors.

Fig. 2. Defect mappings and yield prediction for epilayers grown in different planetary reactors with methane precursor on substrates from different vendors.

Carrier lifetime in epilayers.

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

The effective minority carrier lifetime in 1,200 V epiwafers was measured by μ−PCD method without any sample preparation. Effective lifetimes are depending on the minority carrier lifetime in the epilayer ("bulk lifetime"), on surface recombination at the epilayer surface, and the epilayer thickness or distance to the highly doped substrate. The epilayer thickness of about 10μ m of all investigated epilayers is comparable and the as-grown surfaces were untreated, the effective lifetimes are an indicator for the "bulk lifetime" in the epilayer. Figure 3 shows a comparison of lifetime maps from epilayers grown in ethene- and methane-based epitaxy processes.

[picture]

Fig. 3. Effective minority carrier lifetime mappings of 1,200 V epilayers grown with a methane based epigrowth process (a) and conventional ethene-based process (b) with the same color scale from 50 ns (red) to 230 ns (blue). Edge exclusion is 3 mm .

Fig. 3. Effective minority carrier lifetime mappings of 1 , 200 V epilayers grown with a methane based epigrowth process (a) and conventional ethene-based process (b) with the same color scale from 50 ns (red) to 230 ns (blue). Edge exclusion is 3 mm .

The effective carrier lifetime mappings show the typical radially symmetric lifetime distribution, which depends on the lateral thickness and doping concentration profiles of epilayers. No larger defects, like e.g. stacking faults, dislocation networks or defect clusters, are visible as "red spots" with shorter lifetimes. The mean effective minority carrier lifetime is 163 ns for the epilayer out of the methane-based process and 119 ns for the epilayer from ethene-based growth, i.e. the effective lifetime of the methane-based epilayer is slightly higher than that of the conventional epigrowth process. We measured more than 300 epiwafers with 1,200 V specification by μ-PCD and found that their mean effective lifetime is typically about 115 ns [6], which compares well to the calculated effective lifetime of 130 ns [6] for typical 1,200 V epilayers. We will further investigate if the methane based epigrowth can significantly increase the effective and bulk lifetime in the epilayer and the physical reasons. Point defect concentrations in the epilayers from different precursors and reactor types will be determined by deep level transient spectroscopy (DLTS).

IsoPureSi12Cepilayers.

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

After developing a methane-based growth process with good epilayer quality at 30μ m/h growth rate, isotopically enriched methane was used as precursor. Inserting methane with 99.99%12C into the reactor resulted in a 12C concentration of 99.96% in the epilayer as shown in Fig. 4. This result indicates clearly that almost no carbon exchange takes place between the precursor species in the gas phase and the growing epilayer on one hand side and the SiC deposition in the planetary reactor on the other side.

[picture]

Fig. 4. Isotope concentration (determined by SIMS) for epilayers grown with different methane precursor, i.e. conventional methane and isotopically enriched methane.

Fig. 4. Isotope concentration (determined by SIMS) for epilayers grown with different methane precursor, i.e. conventional methane and isotopically enriched methane.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

This work was funded by the German Federal Ministry for Economic Affairs and Climate Action (BMWK) as part of project 03EN4084B.

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

The conventional ethene precursor was substituted by methane precursor for comprehensive growth studies in AIXTRON planetary reactors G10-SiC and G5WW C on 150 mm SiC substrates. The growth rate, epilayer thickness and doping concentrations as well as the defectivity of epilayers was comparable for both methane- and ethene-based epigrowth processes. Furthermore, "IsoPure" epilayers with a 12C concentration of 99.96% were grown for use in quantum-based applications. The point defect content of epilayers will be further investigated by DLTS measurements to deepen the understanding of the effective minority carrier lifetime. Further experiments will be done to increase the growth rate to more than 30μ m/h.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.65.pdf

M. Ghezellou, J. Ul-Hassan, J.; Phys. Status Solidi B, 261: 2300535 (2024); https://doi.org/10.1002/pssb.202300535.

N. T. Son, C. P. Anderson, A. Bourassa, K. C. Miao, C. Babin, M. Widmann, M. Niethammer, J. Ul Hassan, N. Morioka, I. G. Ivanov, F. Kaiser, J. Wrachtrup, D. D. Awschalom; Appl. Phys. Lett. 116, 190501 (2020); .

Shravan K. Parthasarathy, B. Kallinger, F. Kaiser, P. Berwian, D.B.R. Dasari, J. Friedrich, R. Nagy, PHYSICAL REVIEW APPLIED 19, 034026 (2023).

Bourassa, A., Anderson, C.P., Miao, K.C. et al.; Nat. Mater. 19, 1319-1325 (2020). .

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C. Wißgott, B. Kallinger, M. Rommel; Minority charge carrier lifetime for evaluating 4H-SiC epitaxial growth by Microwave detected Photoconductivity Decay; Materials Science Forum (2026).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 71-77

doi: 10.4028/p-9UOfEY

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-10

Accepted:
2026-02-23

Online:
2026-05-18

Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways

The original version of this paper is available on https://www.scientific.net/SSP.393.71.pdf

Misagh Ghezellou 1,a*, Justinas Palisaitis 1, b, and Jawad UI-Hassan 1,c

Department of Physics, Chemistry, and Biology (IFM), Linköping University, SE-58 183, Sweden

ªMisagh.Ghezellou@liu.se, bJustinas.Palisaitis@liu.se, cJawad.UI-Hassan@liu.se

Keywords: Remote Epitaxy, CVD, Graphene

Abstract

Silicon carbide (SiC) is a promising wide-bandgap semiconductor for advanced quantum technologies. Yet, despite progress in bulk and epitaxial growth, a reliable SiC-on-insulator platform remains lacking. Remote epitaxy, mediated by a 2D interlayer, offers a potential pathway to transferable SiC thin films and substrate reuse. In this work, we examine remote epitaxial growth of SiC on epitaxial graphene. We first evaluate the stability of graphene under SiC growth conditions and find that it degrades significantly at the required high temperatures, primarily due to hydrogen and silane etching. With the conditions yielding the highest-quality SiC epitaxial layer; graphene migrates above the SiC rather than remaining at the interface, demonstrating that true remote epitaxy is not achieved. These results highlight the fundamental challenges of SiC remote epitaxy on graphene and point toward critical directions for future exploration.

Introduction

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Silicon carbide ( SiC ) is a wide band-gap semiconductor with exceptional properties, making it a key material for demanding applications in high-power electronics, optoelectronics, and quantum technologies. [1,2,3,4] In the quantum realm, SiC hosts optically addressable spin qubits, known as color centers, positioning it as a leading platform for integrated quantum photonics. [5, 6, 7] However, realizing this potential requires a scalable SiC-on-insulator platform. Traditional fabrication methods like mechanical polishing and etching struggle to produce the necessary ultra-thin layers at scale. A promising alternative is remote epitaxy, which uses a 2D intermediary layer to grow high-quality, transferable films, also allowing for the cost-saving reuse of expensive SiC substrates. [8, 9, 10]

The growth of an epitaxial film over a 2D intermediary can proceed through three distinct mechanisms. [11, 12, 13] In remote epitaxy, the substrate's electrostatic potential penetrates the 2D layer, guiding the formation of a single-crystalline film that copies the substrate's template. Conversely, quasi-van der Waals epitaxy relies on weak interactions with the 2D layer itself, where the substrate's potential is negligible. Finally, pinhole-based epitaxy occurs when defects in the 2D layer expose the underlying substrate, creating seeding points for direct growth and subsequent lateral overgrowth to form a continuous film. [9]

However, remote epitaxy of SiC faces a unique and critical challenge: polytype control. SiC exists in over 250 polytypes, and replicating a specific one during epitaxy requires step-flow growth on precisely off-cut substrates. [14] Consequently, the intermediary 2D layer must be compatible with this off-cut geometry. Graphene is an ideal candidate as it can be grown epitaxially on SiC . In contrast, materials like hBN, successful for III-V remote epitaxy, are unsuitable for SiC due to their polarity, which disrupts polytype replication. [15] This leads to a significant roadblock: while the epitaxial growth of graphene on SiC is a well-established process, it is typically optimized for on-axis substrates to achieve high uniformity. Research on producing high-quality epitaxial graphene on the required offaxis SiC substrates remains limited, hindering the advancement of SiC remote epitaxy. [16]

In this study, we address this central challenge by investigating the intricacies of SiC remote epitaxy. We explore the growth of epitaxial graphene on off-axis SiC substrates and develop process modifications to overcome the existing obstacles, thereby establishing a pathway for the subsequent remote epitaxial growth of SiC .

Table 1: Growth parameters of different samples grown under solely Ar ambient together with corresponding sample IDs.

Sample ID | Growth Temperature [°C] | SiH₄ flow [ml/min] | C/Si | Growth time [min]
A | 1660 | 11.5 | 1.2 | 10
B | 1660 | 3.5 | 1.2 | 10
C | 1590 | 5 | 1.2 | 1
D | 1590 | 5 | 1.2 | 10
E | 1590 | 5 | 1.2 | 30
F | 1540 | 5 | 1.2 | 30
G | 1590 | 5 | 1.6 | 30
H | 1590 | 5 | 2 | 30
I | 1610 | 2 | 2 | 30

Experimental

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All epitaxial layers in this study (graphene and SiC) were grown in a horizontal hot-wall chemical vapor deposition (CVD) reactor with induction heating. Standard highly doped n-type 4∘-off 4 H -SiC substrates ( Si - and C -face) were cut from the same commercial wafer and subjected to RCA cleaning prior to the growth. Carrier gases included Ar,H2, or their mixtures, with SiH4 and C3H8 serving as Si and C source gases, respectively. Unlike conventional graphite susceptor used for graphene growth, all epitaxial graphene layers were grown on a TaC-coated susceptor, identical to that used for SiC growth.

Graphene was synthesized by the sublimation method. Substrates underwent in-situ surface preparation at 1450∘C for 10 min in H2, followed by chamber evacuation and introduction of Ar at 200 mbar . The temperature was then raised to 1660∘C, and graphene growth proceeded for 30 min under Ar . To assess graphene preservation under SiC epitaxial growth condition, samples were subsequently exposed to H2,Ar+SiH4, and Ar+C3H8 ambient at various temperatures.

For SiC-on-graphene growth, Ar was selected as the carrier gas, and the temperature was varied between 1540∘C and 1660∘C. Growth runs were systematically performed with controlled parameter variations to examine their impact on SiC quality and graphene preservation. SiC deposition followed immediately after graphene growth by introducing source gases after pressure adjustment. Detailed parameters and sample IDs are provided in Table 1.

Surface morphology was examined by optical microscopy in differential interference contrast (DIC) mode. Raman spectroscopy was employed to verify graphene presence, assess its quality, and confirm SiC polytype replication. Transmission electron microscopy (TEM) was further used to confirm graphene retention and characterize the interfaces.

Results and Discussion

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On the Si-face, epitaxial graphene growth followed a layer-by-layer mode. Fig. 1(a,b) shows optical and Raman data from a 4∘-off Si-face substrate, with the Lorentzian fit of the 2D peak (FWHM =49 cm−1 ) confirming monolayer graphene above a buffer layer. [17, 18] Cross-sectional HRTEM (Fig. 1(c)) corroborates this structure.

The growth kinetics were examined by extending growth durations (Fig. 1(d)). Beyond 90 min, the 2D FWHM rapidly increased and saturated at ~80 cm−1, indicative of multilayer graphene. This saturation is likely influenced by the TaC-coated susceptor used for SiC growth, which contributes a positive Si partial pressure that suppresses further graphene sublimation.

In contrast, growth on the C-face produced highly non-uniform graphene coverage (Fig. 2). Optical and Raman analyses revealed bare regions without graphene (region A) and multilayer graphene

[picture]

Fig. 1: (a) Optical image showing the surface of a 4∘-off Si -face substrate after graphene growth. (b) Raman spectrum illustrating the 2D peak with Lorentzian fit, yielding a FWHM of 49 cm−1. (c) Cross-sectional HRTEM confirming the buffer layer and monolayer graphene. (d) Graph showing the evolution of the 2D peak FWHM with growth time on Si-face substrates.

Fig. 1. (a) Optical image showing the surface of a 4 ∘ -off Si -face substrate after graphene growth. (b) Raman spectrum illustrating the 2D peak with Lorentzian fit, yielding a FWHM of 49 c m − 1 . (c) Cross-sectional HRTEM confirming the buffer layer and monolayer graphene. (d) Graph showing the evolution of the 2D peak FWHM with growth time on Si-face substrates.

[picture]

Fig. 2: (a) Optical image showing epitaxial graphene grown on a C -face 4H−SiC substrate with randomly distributed graphene grains. (b) Raman spectra comparing two regions: one without graphene (A) and one with graphene (B).

Fig. 2. (a) Optical image showing epitaxial graphene grown on a C -face 4 H − S i C substrate with randomly distributed graphene grains. (b) Raman spectra comparing two regions: one without graphene (A) and one with graphene (B).

regions (region B,FWHM=53 cm−1 ). These observations agree with reports of turbostratic and uncontrolled graphene formation on the C-face, linked to its lower surface energy. [16]

The stability of epitaxial graphene under SiC growth conditions was tested in different ambient (Fig. 3). Graphene degraded in H2 above 1300∘C and was fully etched by introducing small flow of SiH4 in Ar ambient at 1590∘C, while repeating the experiment with C3H8 left graphene intact. These results establish SiH4 as the critical factor driving graphene loss during SiC growth.

SiC growth was next attempted on substrates with epitaxial graphene. At high precursor flow rates (samples A and B, Fig. 4(a,b)), parasitic graphitic deposits formed alongside preserved graphene in step-bunched regions. At reduced flow rates (Fig. 4(c,d)), deposits were suppressed but graphene was etched, indicating a delicate balance between precursor supply and graphene survival.

[picture]

Fig. 3: Optical images and Raman spectra showing graphene layers exposed to (a) H2 at 1300∘C, (b) Ar+SiH4 at 1590∘C, and (c) Ar+C3H8 at 1590∘C. Raman analysis indicates graphene removal in (a) and (b), while preservation is observed in (c).

Fig. 3. Optical images and Raman spectra showing graphene layers exposed to (a) H 2 at 1300 ∘ C , (b) A r + S i H 4 at 1590 ∘ C , and (c) A r + C 3 H 8 at 1590 ∘ C . Raman analysis indicates graphene removal in (a) and (b), while preservation is observed in (c).

[picture]

Fig. 4: (a) Optical image showing the surface of sample A, with inset providing higher magnification. (b) Raman spectra from two regions marked in (a). (c) Optical image of sample B. (d) Raman spectra from the region marked in (c).

Fig. 4. (a) Optical image showing the surface of sample A, with inset providing higher magnification. (b) Raman spectra from two regions marked in (a). (c) Optical image of sample B. (d) Raman spectra from the region marked in (c).

[picture]

Fig. 5: Optical images showing the surfaces of (a) sample C , (b) sample D , and (c) sample E after SiC growth for 1, 10, and 30 minutes, respectively. Surface pits linked to Si droplets are highlighted by yellow dashed circles.

Fig. 5. Optical images showing the surfaces of (a) sample C , (b) sample D , and (c) sample E after SiC growth for 1, 10, and 30 minutes, respectively. Surface pits linked to Si droplets are highlighted by yellow dashed circles.

Lowering the temperature to 1590∘C(C/Si=1.2) enabled SiC nucleation followed by epitaxial growth at a rate of ~1.3μ m/h, but Raman spectra showed no graphene peaks (Fig. 5). With increasing growth time, Si -droplet-related pits diminished and zigzag step structures characteristic of SiC emerged, yet graphene loss remained unavoidable.

To mitigate this, higher C/Si ratios ( 1.6 and 2.0) were explored (Fig. 6). Graphene-related peaks reappeared in Raman spectra, but surface quality degraded, with defective graphene or graphite features forming. Thus, higher C/Si ratios favor graphene preservation but compromise film morphology.

Optimized conditions were achieved in sample I, grown at 1610∘C,C/Si=2.0, and reduced SiH4 flow (2ml/min). No droplet pits were observed (Fig. 7(a)), triangular defects indicated SiC growth, and Raman spectra revealed 1−2 graphene monolayers (Fig. 7(b)). TEM confirmed 4H−SiC stacking (Fig. 7(c-f)). However, the graphene signal originated from the surface of the SiC film rather than the buried interface, ruling out true remote epitaxy.

[picture]

Fig. 6: (a, c) Optical images showing SiC grown on epitaxial graphene with different C/Si ratios: (a) sample G(C/Si=1.6) and (c) sample H(C/Si=2.0). (b, d) Raman spectra from the regions marked in (a) and (c), respectively.

Fig. 6. (a, c) Optical images showing SiC grown on epitaxial graphene with different C / S i ratios: (a) sample G ( C / S i = 1.6 ) and (c) sample H ( C / S i = 2.0 ) . (b, d) Raman spectra from the regions marked in (a) and (c), respectively.

[picture]

Fig. 7: (a) Optical image showing the surface of sample I with a triangular defect characteristic of SiC growth. (b) Raman spectrum indicating the presence of 1-2 graphene monolayers. (c) TEM image confirming the 4 H polytype of the epitaxial SiC layer. (d, e) TEM images showing step edges on the surface of sample I. (f) HRTEM image revealing a monolayer graphene above a buffer layer.

Fig. 7. (a) Optical image showing the surface of sample I with a triangular defect characteristic of SiC growth. (b) Raman spectrum indicating the presence of 1-2 graphene monolayers. (c) TEM image confirming the 4 H polytype of the epitaxial SiC layer. (d, e) TEM images showing step edges on the surface of sample I . (f) HRTEM image revealing a monolayer graphene above a buffer layer.

Two scenarios were considered: (i) graphene was etched during SiC growth and reformed upon cooling, or (ii) Si and C atoms penetrated beneath graphene to nucleate SiC, as reported for quasi2D GaN. [19] Additional experiments supported the first scenario. Suppressing graphene formation by raising chamber pressure after growth or introducing small H2 flows eliminated Raman graphene peaks, confirming that the observed graphene formed during cooldown rather than surviving growth.

Finally, the effect of H2 addition was examined. At very low H2/Ar(0.013), surfaces resembled step-bunched graphene (Fig. 8(a)), while higher H2/Ar(0.25) enabled SiC growth with smoother step edges (Fig. 8(b)). Yet in both cases, Raman showed no graphene, indicating that hydrogen promotes SiC growth but accelerates graphene loss.

[picture]

Fig. 8: Optical images showing sample surfaces after SiC growth with added H2 at H2/Ar ratios of (a) 0.013 and (b) 0.25 .

Fig. 8. Optical images showing sample surfaces after SiC growth with added H 2 at H 2 / A r ratios of (a) 0.013 and (b) 0.25 .

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.71.pdf

This study examined the feasibility of remote epitaxy of SiC using graphene as an intermediary layer. Preserving graphene during SiC growth proved highly challenging: it was consistently etched at high temperatures, low C/Si ratios, or in hydrogen- and silane-containing ambients. Even under conditions resulting in high quality SiC epitaxial layers, Raman and TEM analyses showed that graphene reformed only during cooldown, rather than surviving beneath the SiC epitaxial layer.

Overcoming these limitations will require lowering effective growth temperatures through improved precursor chemistry or ambient control, and exploring alternative substrate orientations that support island nucleation instead of step-flow growth. Addressing issues such as graphene-induced terrace widening, which promotes 3C-SiC nucleation, will also be critical.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/SSP.393.71.pdf

The Swedish Research Council (VR) grant No.2020-05444 and European Union's Horizon Europe research and innovation program grant for the project SPINUS (Grant No. 101135699) are acknowledged for financial support. Swedish Research Council and the Swedish Foundation for Strategic Research are acknowledged for access to ARTEMI, the Swedish National Infrastructure in Advanced Electron Microscopy (2021-00171 and RIF21-0026).

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The original version of this paper is available on https://www.scientific.net/SSP.393.71.pdf

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Solid State Phenomena, ISSN: 1662-9779, Vol. 393, pp 79-86

doi: 10.4028/p-fX8pPY

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2026-02-02

Accepted:
2026-02-23

Online:
2026-05-18

Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

The original version of this paper is available on https://www.scientific.net/SSP.393.79.pdf

Shota Tani a*, Masato Urakami b, Wataru Saito c, Shin-Ichi Nishizawa d

Kyushu University, Kasuga Koen 6-1, Kasuga, Fukuoka, Japan

a*tani.shota.587@s.kyushu-u.ac.jp, b  urakami_masato@riam.kyushu-u.ac.jp, c  wataru3.saito@riam.kyushu-u.ac.jp, d  s.nishizawa@riam.kyushu-u.ac.jp

Keywords: virtual reactor, numerical simulation, physical vapor transpor, recrystallization.

Abstract

In bulk SiC crystal growth using the PVT method, recrystallization within the source material leads to a decrease in growth rate and source utilization. In this study, numerical simulations were used to investigate the source temperature distribution and its effect on the growth rate and source utilization. Recrystallization in the upper and lower regions was considered separately. The results showed that reducing the source temperature gradient prevents recrystallization in the upper region, and a unidirectional gradient prevents recrystallization in the lower region, leading to higher growth rates and source utilization.

Introduction

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The Physical Vapor Transport (PVT) method is widely used for growing bulk SiC crystals. In this method, SiC powder is used as the source, and the sublimation and temperature distribution in the source directly affects the crystal quality and manufacturing cost of SiC . The evolution of SiC powder during crystal growth has been studied in previous work using in-situ X-ray techniques [1,2]. Generally, a moderate source temperature gradient enhances growth rate. However, when the temperature gradient is too high, a large amount of recrystallization occurs in the source [3, 4]. This problem reduces yield and growth rate, leading to high production costs. There have been many reports on studies of the SiC powder source in PVT growth [5,6,7,8]. However, few studies have focused on the optimization of source temperature distribution. This study uses numerical analysis with the STR software Virtual Reactor (VR) to examine the impact of recrystallization on growth rate and source utilization [9], and proposes an optimal source temperature distribution. In addition, the equilibrium vapor pressure dependent on temperature was used as a parameter to evaluate the source temperature distribution.

Optimal Source Temperature Distribution

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Case 1: Conventional RF coil model.

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In the PVT method, RF and resistance heating are employed as heating techniques for growing bulk SiC crystals. In Case1, the conventional RF coil model was used to examine the problem of recrystallization in the source. The modeling of the PVT furnace used is shown in Fig. 1. The model includes a graphite crucible, SiC powder, SiC seed, a seed holder, graphite felt insulation, and coils. Table 1 presents the physical properties of the materials used. A 4H polytype seed with a diameter of 120 mm was used. The growth was carried out under an Ar atmosphere at 1500 Pa , with the temperature controlled at 2250∘C at the center of the seed holder surface. The RF heating frequency was set to 10 kHz , and the heating power was calculated from the temperature and thermal properties of the structure. The growth time was set until the growth rate dropped below zero and the source was completely consumed, in order to calculate the source utilization. Growth steps were set at twohour intervals, and the total crystal growth was calculated from the obtained results. Initial particle size in the source was set to 500μ m with a porosity of 0.6 . Recrystallization is observed when the particle diameter exceeds this value. The utilization efficiency of the source was calculated as {[initial
source mass] - [residual source mass]} / [initial source mass]. The numerical modeling of the powder evolution is described in Reference [10].
In the high-temperature process of the PVT method, Lilov reported that the SiC reaction gas species are Si,Si2C, and SiC2. Below 2900 K,SiC2 is the dominant species controlling the growth rate [11]. Therefore, not only the temperature but also the equilibrium vapor pressure of SiC2 was considered for optimizing the source temperature distribution. The equilibrium vapor pressure values were calculated based on data traced from the graph published by Philippe Rocabois [12].

[picture]

Fig. 1. Casel model: Structure of the Conventional RF heating Furnace.

Fig. 1. Casel model: Structure of the Conventional RF heating Furnace.

Table 1. The physical parameters.

Components | Electric conductivity [S/m] | Thermal conductivity [W/(m×K)] | Density [kg/m³] | Heat capacity [J/(kg×K)] | Emissivity
SiC seed crystal | 1000 | 90 | 3220 | 920 | 0.9
SiC source Powder | 4 | 10 | 1600 | 920 | 0.8
Graphite Crucible | 1.6×10⁵ | 30 | 1840 | 1300 | 0.8
Graphite insulation side | 100 | 1.1 | 100 | 1000 | 0.8
Graphite insulation bottom | 200 | 1.4 | 180 | 1000 | 0.8

Fig. 2 shows the temperature distribution in the crucible and the particle size distribution after 24 hours of crystal growth. Fig. 3 shows the temperature and the corresponding equilibrium vapor pressure of SiC2 (Psic2) along the center axis ( 0 h ) [11]. The 24-hour average growth rate was 219 μm/h, with a total growth of 2.59 cm . From Fig. 2, it can be especially confirmed that recrystallization occurs in both the upper and lower regions of the source. It is also observed in the middle region. Recrystallization occurs when the sublimated gas becomes supersaturated in the source. Here, the transport direction and flux of the sublimated gas are determined by the value of the equilibrium vapor pressure gradient dP_SiC2/dy. Fig. 4 shows the equilibrium vapor pressure gradient, where negative values indicate gas flow toward the seed and positive values toward the bottom crucible. Differentiation was carried out using the finite difference method with Δ=2 mm. The source bottom is at y=15, and below the seed crystal is at y=165.

Recrystallization in the lower region occurs due to the temperature distribution created by RF coil heating, as the heat source is located at the crucible sidewall, leading to a gradual decrease in temperature toward the center. From Fig. 4, it can be seen that in the range of y=15−27, the vapor pressure gradient has positive values, causing gas transport toward the bottom crucible, resulting in supersaturation and recrystallization. Recrystallization in the upper region can be explained by the discontinuity of the equilibrium vapor pressure gradient at the source/gas interface. Fig. 4 shows that

[picture]

Fig. 2. Crucible temperature [ ∘C ] and particle size distribution [μm](24 h).

Fig. 2. Crucible temperature [ ∘ C ] and particle size distribution [ μ m ] ( 24 h ) .

[picture]

Fig. 3. Temperature [ ∘C ] and equilibrium vapor pressure of P−SiC2[ Pa] along the center axis (0h).

Fig. 3. Temperature [ ∘ C ] and equilibrium vapor pressure of P − S i C 2 [ P a ] along the center axis (0h).

at the source-gas interface (y=115), the vapor pressure gradient on the source side has a much larger negative value than that on the gas side. This gradient difference causes the sublimated gas to stagnate in the upper of the source, resulting in supersaturation and recrystallization. Similarly, recrystallization in the middle region occurs because, from y=27, the vapor pressure gradient in the lower region becomes more negative than that in the upper region. In contrast to the vapor pressure gradient, the temperature gradient increases gradually in the source. This finding indicates that vapor pressure distribution, rather than temperature distribution, is the key parameter in determining recrystallization.

These results suggest that recrystallization occurs when the vapor pressure gradient dP1SiC2/dy shifts from a large to a small negative value - in other words when the gradient of dP1SiC2/dy ( =d2P_SiC2/dy2 ) becomes positive causing stagnation of sublimated gas transport. Therefore, Fig. 5 presents d2P1SiC2/dy2 together with the SiC powder particle size growth rate [μm/h] at 0 h , indicating recrystallization in the source. This figure indicates that the particle size growth peaks at the sourcegas interface (y=115), where d2P−SiC2/dy2 reaches a maximum value of 0.032 at the gas-side interface. In Case 3, d2P_SiC2/dy2 at the source-gas interface was used as a parameter to study the effects of upper-region recrystallization on growth rate and source utilization. In Case 2, the lower temperature distribution was optimized.

[picture]

Fig. 4. Temperature gradient [∘C/cm] and equilibrium vapor pressure gradient dP_SiC2/dy [Pa/cm] along the center axis.

Fig. 4. Temperature gradient [ ∘ C / c m ] and equilibrium vapor pressure gradient dP_SiC2/dy [ P a / c m ] along the center axis.

[picture]

Fig. 5. Relationship between d2P_SiC2/dy2 and Particle radius growth rate [μm/h] along the center axis.

Fig. 5. Relationship between d 2 P _ S i C 2 / d y 2 and Particle radius growth rate [ μ m / h ] along the center axis.

Case 2: Optimaizing the temperature in the lower.

The original version of this paper is available on https://www.scientific.net/SSP.393.79.pdf

In Case 2, the material at the bottom of the crucible was replaced with one with higher thermal conductivity to improve the temperature distribution in the lower part of the source. The analysis model and physical parameters are shown in Fig. 6 and Table 2. This material has fictitious properties to create an ideal temperature distribution. All other analysis conditions were the same as those used in Case 1. The 24-hour average growth rate was 217μ m/h, the total growth was 3.17 cm . Compared with Case 1, the total growth increased by 0.58 cm , while the growth rate decreased by 2μ m/h. Fig. 7 shows a unidirectional temperature gradient in the lower region of the source and no recrystallization, leading to improved source utilization.

[picture]

Fig. 6. Case 2 model: Change of bottom material.

Fig. 6. Case 2 model: Change of bottom material.

[picture]

Fig. 7. Optimization of the lower source temperature distribution [∘C] and particle size distribution [μm].
(24 h).

Fig. 7. Optimization of the lower source temperature distribution [ ∘ C ] and particle size distribution [ μ m ] . ( 24 h ) .

Table 2. The physical parameters.

Parameter | Value
Electric conductivity | 1.6 × 10⁵ S/m
Thermal conductivity | 500 W/(m * K)
Density | 2200 kg/m
Heat capacity | 1900 kg/m³
Emissivity | 0.8

The slight difference in growth rate is due to the lower maximum temperature in Case 2 than in Case 1, with the sublimated gas generated in the lower region consumed by recrystallization in the upper region. In practical induction heating, designing the lower temperature distribution shown in Fig. 7 is challenging. Therefore, it is important to lower the heat source and design the crucible so that the lower part is heated uniformly.

Case 3: Optimaizing the temperature in the upper.

The original version of this paper is available on https://www.scientific.net/SSP.393.79.pdf

In Case 3, we analyzed the influence of the d2P_SiC2/dy2 at the source-gas interface on growth rate and source utilization by setting the source temperature difference in the range of ΔT source =4~50∘C. The analysis model is shown in Fig. 8. This model differs from those used in Cases 1 and 2, with the temperature set at the boundary condition to realize an ideal temperature distribution, without using coils._The source sidewall was given a linear temperature boundary condition, and bottom was given a constant one. The crucible diameter was also reduced to 60 mm , and a flat temperature distribution was created by minimizing the lateral temperature gradient. Fig. 9 shows the 0 h temperature and the 24 h particle size distribution, while Table 3 lists the temperatures and d2P_SiC2/dy2 at the gas/source interface. As shown in Fig. 9,

[picture]

Fig. 8. Case3 model: The temperature was set at the boundary conditions for the ideal temperature distribution (no coils).

Fig. 8. Case3 model: The temperature was set at the boundary conditions for the ideal temperature distribution (no coils).

Table 3. Analysis Results of Case 3 model.

ΔT source
[°C]
Tseed
[°C]
T source
top [°C]
T source
bottom
[°C]
Total
Growth
[cm]
d²Psic2
dy²
|y=Gas/
Source
Growth
Rate
[μm/h]
Utilization
e efficiency
[%]

4 | 2370 | 2386 | 2390 | 2.49 | 0.010 | 164.4 | 91
10 | 2370 | 2386 | 2396 | 2.68 | 0.012 | 172.5 | 90
20 | 2370 | 2386 | 2406 | 2.79 | 0.017 | 173.7 | 83
30 | 2370 | 2386 | 2416 | 2.58 | 0.021 | 171.3 | 73
40 | 2370 | 2386 | 2426 | 2.23 | 0.027 | 165.8 | 44
50 | 2370 | 2386 | 2436 | 1.63 | 0.030 | 171.1 | 28

Growth Rate [μ𝐦/𝐡 is the 24-hour average growth rate.; Total growth [cm] was calculated by summing the average growth rates until the source was fully consumed.; The pressure for all models was 1200 Pa .

[picture]

Fig. 9. Temperature distribution [∘C] ( 0 h ) and particle size distribution [μm] ( 24 h ) for the Case 3 model. Δ𝐓=Δ𝐓 source: Temperature difference of the source along the center axis. 𝐗𝐚~𝐟 : d2P_SiC2/dy2 at the source-gas interface.

Fig. 9. Temperature distribution [ ∘ C ] ( 0 h ) and particle size distribution [ μ m ] ( 24 h ) for the Case 3 model. Δ 𝐓 = Δ 𝐓 source: Temperature difference of the source along the center axis. 𝐗 𝐚 ~ 𝐟 : d 2 P _ S i C 2 / d y 2 at the source-gas interface.

a larger d2P_SiC2/dy2 at the gas/source interface leads to greater particle size growth in the upper region. In addition, starting from ΔT=30∘C where d2P_SiC2/dy2=0.21, it can be observed that the peak position of particle size gradually shifts toward the middle region, indicating that the sublimated gas is consumed before reaching the upper region. At ΔT source =4∘C, no recrystallization was observed in the source, and Fig. 10 shows the corresponding d2P_SiC2/dy2 and the powder particle size growth rate [μm/h]. The source bottom is at y=2, and below the seed crystal is at y=127. These results also confirm that no recrystallization occurred throughout the entire source. Fig. 11 shows the relationship between the d2P_SiC2/dy2 at the source-gas interface and the utilization efficiency and growth rate ( 24 h average). The growth rate reached their maximum at d2P−SiC2/dy2=0.017(Δ T source =20∘C ), with values of 173μ m/h. Thereafter, the growth rate showed a decreasing trend, which coincided with the timing when recrystallization began to shift downward to the middle region. At d2P_SiC2/dy2=0.030(Δ T source =50∘C), the growth rate temporarily increased but did not reach its maximum, and the utilization efficiency decreased to 28%. From these results, it was shown that the growth rate and source utilization efficiency can be maximized by setting d2P_SiC2/dy2 at the source-gas interface. In practice, it is difficult to suppress the source temperature difference to 4∘C or 10∘C while maintaining a unidirectional source temperature distribution. Therefore, in thermal design for the PVT process, minimizing the source temperature difference is important. This allows the maximum source temperature to be reduced, which in turn helps lower power consumption and suppress the degradation of the crucible and insulation materials. If the growth rate needs to be increased, it is effective to maintain a low source temperature difference while either raising the overall temperature or enlarging the temperature difference in the gas region, which also helps reduce production costs. A more detailed analysis would require further examination of the computational model and its accuracy.

[picture]

Fig. 10. Relationship between d2P_SiC2/dy2 and Particle radius growth rate [μm/h] along the center axis. ( ΔT source =4∘C).

Fig. 10. Relationship between d 2 P _ S i C 2 / d y 2 and Particle radius growth rate [ μ m / h ] along the center axis. ( Δ T source = 4 ∘ C ) .

[picture]

Fig. 11. Relationship between d2P_SiC2/dy2 at the source-gas interface and the utilization efficiency and growth rate ( 24 h average).

Fig. 11. Relationship between d 2 P _ S i C 2 / d y 2 at the source-gas interface and the utilization efficiency and growth rate ( 24 h average).

Summary

The original version of this paper is available on https://www.scientific.net/SSP.393.79.pdf

The results revealed that the optimal temperature distribution suppresses recrystallization by minimizing and making the source temperature gradient unidirectional within the source. These improvements lead to higher growth rates and source utilization, which contribute to the reduction of wafer production costs.

References

The original version of this paper is available on https://www.scientific.net/SSP.393.79.pdf

P.J. Wellmann, M. Bickermann, D. Hofmann, L. Kadinski, M. Selder, T.L. Straubinger, A. Winnacker, In situ visualization and analysis of silicon carbide physical vapor transport growth using digital X-ray imaging, J. Cryst. Growth 216 (2000) 263-272.

Z.G. Herro, P.J. Wellmann, R. Püsche, M. Hundhausen, L. Ley, M. Maier, P. Masri, A. Winnacker, Investigation of mass transport during PVT growth of SiC by 13C labeling of source material, J. Cryst. Growth 258 (2003) 261-267.

X. Liu, B. Chen, L.X. Song, E.W. Shi, Z.Z. Chen, The behavior of powder sublimation in the long-term PVT growth of SiC crystals, J. Cryst. Growth 312 (2010) 1486-1490.

H. Li, X.L. Chen, D.Q. Ni, X. Wu, Factors affecting the graphitization behavior of the powder source during seeded sublimation growth of SiC bulk crystal, J. Cryst. Growth 258 (2003) 100105.

D.S. Karpov, O.V. Bord, S.Yu. Karpov, A.I. Zhmakin, M.S. Ramm, Yu.N. Makarov, Mass transport and powder source evolution in sublimation growth of SiC bulk crystals, Mater. Sci. Forum 353-356 (2001) 37-40.

X. Wang, D. Cai, H. Zhang, Increase of SiC sublimation growth rate by optimizing of powder packaging, J. Cryst. Growth 305 (2007) 122-132.

H. Miao, G. Mi, Y. Liu, Effect of powder packing method on thermal field of SiC crystal grown by PVT method, Ferroelectrics 618 (2024) 2610-2621.

C. Zhou, Z. Lu, C. Li, Y. Lu, H. Li, L. Dong, S. Ke, S.Y. Tong, Optimization of SiC single crystal growth via numerical simulation: Enhanced mass transport with graphite ring and block design, J. Cryst. Growth 668 (2025) 128283.

M.V. Bogdanov, A.O. Galyukov, S.Yu. Karpov, A.V. Kulik, S.K. Kochuguev, . Ofengeim, A.V. Tsiryulnikov, M.S. Ramm, A.I. Zhmakin, Yu.N. Makarov, Virtual reactor as a new tool for modeling and optimization of SiC bulk crystal growth, J. Cryst. Growth 225 (2001) 307-311. [9] theoretical analysis of the mass transport in powder charge.

A.V. Kulik, M.V. Bogdanov, S.Yu. Karpov, Y. Makarov, Theoretical analysis of the mass transport in the powder charge in long-term bulk SiC growth, Mater. Sci. Forum 457-460 (2004) 67-70.

S.K. Lilov, Study of the equilibrium processes in the gas phase during silicon carbide sublimation, Mater. Sci. Eng. B 21 (1993) 65-69.

P. Rocabois, C. Chatillon, C. Bernard, F. Genet, Thermodynamics of the Si-C system II. Mass spectrometric determination of the enthalpies of formation of molecules in the gaseous phase, High Temp. High Press. 27-28 (1996) 25-39.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Chapter 2: Defects Evaluation

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 1-7

doi: 10.4028/p-Wfgrr2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-04

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-18

The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Jimmy Thörnberg 1,a* and Björn Magnusson 1, b

1 STMicroelectronics Silicon Carbide AB, Ramshällsvägen 15, 60238 Norrköping, Sweden

a*jimmy.thornberg@st.com, b  bjorn.magnusson@st.com

Abstract

Results from optical defect inspections, and X-ray topography, on wafers from entire 4HSiC ingots provide a clear visualization on the positional dependance of bulk inclusions in ingots with respect to growth stages, looking to both density and size. It is also clear while studying the superpositioning of Laue-Bragg interference densities that the different categories of said defectivity generate new crystallographic defects, dislocations. These in turn lead to significant reductions in usability of wafers, and the lack of tracing such defects, cause an increased difficulty to predict the final device yield, as is displayed by growing epitaxial layers on materials heavily affected by bulk inclusions.

Keywords: 4H−SiC,200 mm, bulk inclusions, defect inspection, XRT, dislocations.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Wide-bandgap semiconductor-based electronics are constantly being developed, with 4H-Silicon Carbide (4H−SiC) leading the way in next generation power devices. Within power electronics, SiC carries intrinsic advantages with higher thermal operation and lower switching losses compared to Silicon-based electronics [1-2]. The fundamental understanding of 4H−SiC crystal growth is also expanding in-line with an increasing commercialization of 4H−SiC wafers, with more key actors and larger facilities ramping up production and thus, increasing the global availability. When scaling up, and larger amount of data becomes available, you realize the outliers is a significant part of the distribution.

Herein, we investigate a defect seemingly overshadowed by more typical and apparent defects, for example micropipes and dislocation. Expanding the understanding of 4H−SiC defectivity with novel results on Bulk Inclusion (BI) tracing and sizing, and the consequences following its presence. We deep-dive into the consequences of such defects, showing how they can affect yield in thin 4H−SiC bonded layer technology. The mere presence of them close to the wafer surface, depending on their size, causes traceable decorations in grown epitaxial layers and directly impacts device yield. We show the ability to pin-point them in the wafer volume (3D) using commercial optical defectivity inspection tools, sizing and, classifying them with respect to their impact on consecutive product or device steps. In addition, many commercial systems used today also have an interaction-volume in orders of several um in the surface sensitive channels, easily mis-bin the presence of such defects as surface contaminations, possibly giving rise to misrepresented yield approximations, unnecessary wafer scrap and, wafers being graded too low. A better understanding of BI will assist in superior yield approximation and material allocation with respect to how sensitive a product is to different sizes of BIs.

Experimental Details

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

In this work, defectivity data from several thousand 200 mm4H−SiCN+ production and development grade wafers, produced in-house, have been used to create accurate theoretical models for defect and dislocation visualization, with their spatial and volumetric dependance as a function of crystal growth stages. The optical defectivity inspection tools used were KLA Candela 8520 and, to verify and align results, a Lasertec SICA88. Specially developed recipes on the former were used to,
not only localize, but also sub-categorize bulk inclusions in ranges of 60 nm to more than 1μ m. The results are compared with conventional recipes that are tailored to include standardized defects with sizing and classification of surface contamination calibrated towards reference wafers with polystyrene latex (PSL) particles on the surface. For dislocation data, a handful of wafers per ingot were scanned using a Rigaku XRTmicron and post-processed using in-house developed recipes using XRT Toolbox software. Epitaxial growth was done using an ASM LPE108 single-wafer CVD reactor. Processing of data was done with in-house made analytical software using primarily Python and R.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Generally, during data acquisition in commercial inspection tools, contrast images are generated based on some inherent normalization rules set in the software by either supplier or user. A system can contain several light sources, and several receiving signal detectors, at various angles. The acquired dataset is further processed by filtering noise from signals, using once again, pre-set rules to find contrast points that could be potential defects. The selected contrast point then goes through a hierarchy of different binning rules, looking to the data from one or more signal detectors, and if all criterias are fulfilled, it gets binned as a defect. If it fails to fulfill all pre-set defects in a binning hierarchy, it is considered noise and becomes undefined. More modern tools utilize machine learning to execute similar logic as mentioned above.

Experienced users can tailor the above logic to find the flaws in the material that do not necessarily fall under what is conventionally tracked in production environments, and this is exactly what is done in this work. We have used a finely tuned recipe, which utilizes several non-standard optical properties from different light sources and signal detectors, to find and sub-categorize volumetric defects in individual 4H−SiC wafers. Post-processing of the data using mathematical models can then construct a 3D visualization of the results of entire ingots. An example of this can be seen in Fig. 1, highlighting BIs of various sizes in an R&D ingot, grown under conditions favoring BIs formation, by combining data from all wafers belonging to it, here showing small (green), medium (blue) and large (red), BIs with approximate sizes of <300 nm,>300 nm and >1μ m, respectively.

In Fig. 1 there is a clear dependance on both the planar position and size of BIs as a function of the lateral position in the ingot, which corresponds to different stages during the crystal growth process. The detailed explanation for this is quite complex and not within the scope of this work, several factors can play a part. Examples of this could be the crystal growth rate, growth thickness,

[picture]

Fig. 1. 3D picture of entire R&D ingot used to produce 200 mm test wafers, showing real positions and distributions of a) smaller (green), b) medium (blue) and large (brown) Bulk Inclusions. Note that Z -axis is not to scale and exaggerated to ease interpretation.

Fig. 1. 3D picture of entire R&D ingot used to produce 200 mm test wafers, showing real positions and distributions of a) smaller (green), b) medium (blue) and large (brown) Bulk Inclusions. Note that Z -axis is not to scale and exaggerated to ease interpretation.

[picture]

Fig. 2. Gradient of small (light blue), medium (blue) and large (brown) bulk inclusions in two separate regions, a)-c) green segment closer to seed and d)-f) red segment closer to the dome, moving from g ) dome to seed position.

Fig. 2. Gradient of small (light blue), medium (blue) and large (brown) bulk inclusions in two separate regions, a)-c) green segment closer to seed and d)-f) red segment closer to the dome, moving from g ) dome to seed position.

stoichiometry of powder changing as a function of growth-time and rate, deterioration of graphite parts and their respective coatings, variation in the magnetic field strength, temperature gradients and so forth. All of which can give rise to circumstances where particles land on the growth front, briefly interrupting it, to evaporate or impinge, and eventually get overgrown to form voids or inclusions.

In Fig. 2, defectivity plots of BIs for individual wafers, belonging to the ingot shown in Fig. 1, can be seen. In Fig. 2 a)-c) the density of small and medium BIs increases and propagates outward as we move closer to the seed, while the segment closer to the end of the growth cycle, the dome, shown in Fig. 2 d)-f), shows less small and medium BIs but with the addition of large BIs, propagating outward as we move further away from the seed and close to the dome, the end of the crystal growth cycle. It is clear looking at the density and gradient of the defects that portions of these would be well within

[picture]

Fig. 3. Illustration of commercial defectivity on bare 4H−SiC substrates, including Bulk Inclusions, as seen a) cross-view of wafer volume with approximate interaction depths of KLA Candela 8520 and Lasertec SICA88 scattering normal and b) top-view showcasing which features would be registered as topographical defects using standardized recipes.

Fig. 3. Illustration of commercial defectivity on bare 4 H − S i C substrates, including Bulk Inclusions, as seen a) cross-view of wafer volume with approximate interaction depths of KLA Candela 8520 and Lasertec SICA88 scattering normal and b) top-view showcasing which features would be registered as topographical defects using standardized recipes.

[picture]

Fig. 4. A wafer severely affected by small and medium inclusions scanned with KLA Candela 8520, showing surface defectivity scan as seen a) using standard recipe calibrated with a PSL wafer and b) same scan but adding logic to improve distinction between surface and volumetric artifacts with c) and d) only showing the defects with high likelihood of affecting final yield.

Fig. 4. A wafer severely affected by small and medium inclusions scanned with KLA Candela 8520, showing surface defectivity scan as seen a) using standard recipe calibrated with a PSL wafer and b) same scan but adding logic to improve distinction between surface and volumetric artifacts with c) and d) only showing the defects with high likelihood of affecting final yield.

the first 5−30μ m of a wafer surface, the interaction volume for the surface sensitive channels in commercial defect inspection tools, where the final inspection would be done for final grading. Many of these would give the same contrast signature as surface contaminations, even though they are inside the substrate volume, potentially causing wrongful classifications. While the ingot presented in this paper belongs to the outliers in terms of BIs density, this defectivity has been found in all major 4 H SiC N+ substrate suppliers at the time of writing.

Due to BIs size and position in the volume, it is difficult to accurately classify them, and they can even be mistaken for other defects. While this heavily depends on refractive index of the material, wavelength and angle of incidence of light sources, an example could be made for 4H−SiCN+ material with the tools used in this work, KLA Candela 8520 and Lasertec SICA88, having an interaction volume of roughly ~30μ m and ~5μ m, respectively, in the surface sensitive channels, see illustrative example in Fig. 3. A very common mis-binning is surface related defectivity, impurity particles or smaller voids, seen in Fig. 3 a) showing common defects as seen from a cross-view of a wafer volume and in Fig. 3 b) how different systems could misinterpret signals from BIs looking to the scattering normal channel, the surface sensitive channel most commonly used for cleanliness and surface condition determination.

The difficulty of distinguishing between the classification of surface contaminations and close-tosurface inclusions are exemplified in Fig. 4, showing a wafer that is highly affected by small and medium BIs. The center-symmetrical pattern of the distribution suggests crystallographic origin and not cleanliness related. However, automated grading systems will have difficulties making that distinction of the feature unless there is a well-trained image recognition module. Another approach is utilizing gaussian-filters specific to the ingot to assist in smoothing out the inclusion trends by removing such noise on post-scan data to get the real surface contamination.

[picture]

Fig. 5. Large Bulk inclusions (brown) as seen in a) an ingot b) projected to a 2D-plane with c) associated TSD maps. The green, orange and red rings in a) is a positional correspondence of the c ) green, orange and red ring around the TSD maps.

Fig. 5. Large Bulk inclusions (brown) as seen in a) an ingot b) projected to a 2D-plane with c) associated TSD maps. The green, orange and red rings in a) is a positional correspondence of the c ) green, orange and red ring around the TSD maps.

Fig. 5 highlights another potential detrimental effect of BIs, specifically those categorized as slightly larger ( >1μ m ). In Fig. 5 a) we see an ingot volume highlighting the larger BIs along with three segments, green, orange and red, with corresponding TSD data collected with XRT in Fig. 5 c). The final segment, encircled by red dash line in c), has a TSD distribution that perfectly coincides with the 2D projection of all large BIs in the ingot, seen in b). It is clear by superpositioning the 2D projection of large BIs, as seen in b), with XRT data, that >95% of them generate their very own TSD. This TSD then continues to propagate from the point of the BIs, to the end of the dome. For medium and small BIs, the conversion-rate appears much lower.

Furthermore, it was hypothesized that an inclusion close to the wafer surface could affect the epitaxial growth due to local changes in thermodynamic driven surface diffusion. The local surface directly perpendicular to a void, close to the surface, could have a higher state of Gibbs free energy than the surrounding landscape due to changes in thermal conductance contributed by the void, its interface, and/or if the void is occupied by a different material, for example pure C . To verify this, a slightly thicker epitaxial layer, using standard 1200 V device conditions, was grown on two wafers, see Fig. 6, with slightly different localization of large BIs, wafer A and B, as seen in Fig. 6 a) and d), respectively. Superpositioning of the epitaxial defects, seen in Fig. 6 b) and e), with corresponding BI map, shows that large BIs close to the surface, at ~30μ m depth or less, tends to decorate the epitaxial layer with micropits at a very high conversion-rate. For small and medium BIs, the conversion is less likely to happen and requires the inclusion to be closer to the surface. Additional work needs to be done to fully understand the relationship between the latter two.

In Fig. 6 c) and f) the TSD maps of the wafers are also shown, pre-epitaxial growth, highlighting another example of how well TSD generation can be associated with BIs. TSD continues to propagate as TSD in epitaxial layers, a known phenomenon, and can increase the likelihood of leakage current in electronic devices [3, 4]. Micropits generated from sub-surface BIs can degrade most devices, showing that such sub-surface defectivity can be detrimental for device yields. The effect on longevity could also be a concern but requires further investigations.

Another significant consequence of larger voids and inclusions in the volume of 4H−SiC is holegeneration in thin 4H−SiC layers bonded on carrier substrates, i.e. polycrystalline 3C−SiC. If the layer thickness of the final bonded mono-SiC material is equal to or less than that of the diameter of an inclusion, a hole will be generated, creating a pathway directly down to the carrier substrate [5]. While the consequences of this depend on the nature of the carrier substrate, consecutive epitaxial growth and device yield are certain to be compromised as the defectivity generated will behave like that of a micropipe.

[picture]

Fig. 6. Defectivity and dislocation maps of two wafers heavily affected by Bulk Inclusions seen before epitaxial growth, a) and d), after epitaxial growth, b) and e), and corresponding Threading-Screw Dislocation maps, c) and f).

Fig. 6. Defectivity and dislocation maps of two wafers heavily affected by Bulk Inclusions seen before epitaxial growth, a) and d), after epitaxial growth, b) and e), and corresponding Threading-Screw Dislocation maps, c) and f).

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

Models based on empirical data pulled from thousand production and development grade wafers have been used to construct 3D visualization of BIs inside the volume. These aid in visualization of size, spatial and volumetric trends of BIs that can be directly linked to different crystal growth stages. The ability to pinpoint the defects sets the framework for which continuous studies can be done to understand the consequences on device yields. In this work it is already shown how BIs significantly affect dislocation generation, showing how all larger BIs ( >1μ m ) generate TSDs, and how BIs close to surface will decorate the epitaxial layers as micropits due to changes in the energy landscape on the surface above the BIs. The presence of BIs in commercial material is global, but the defect detection routines and procedures used today have not put emphasis on tracking this sort of defect yet. As the field progresses, pushes the limits of 4H−SiC crystal growth techniques, growth rates, thicknesses and, sizes, this type of defectivity will inevitably become more prominent.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

This study was conducted within the framework of the project ARCHIMEDES, receiving funding from the Key Digital Technologies Joint Undertaking (KDT JU) - the Public-Private Partnership for research, development, and innovation under Horizon Europe - and National Authorities under Grant Agreement No 101112295 funded by the European Union and Vinnova Sweden's Innovation Agency.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.1.pdf

X. She, A.Q. Huang, O. Lucia, B. Ozpineci, Review of silicon carbide power devices and their applications, IEEE Trans. Ind. Electron. 64, 10 (2017), pp. 8193-8205.

J. Guo, Y. Yang, B. Raghothamachar, T. Kim, M. Dudley, and J. Kim, Journal of Crystal Growth, 480 (2017) pp. 119-125.

L. Zhao, Nanotechnology and Precision Engineering, 3, 4 (2020), pp.229-234.

J. R. Huang, T.W. Chen, J.W. Lee, C.F. Huang, L.S Hong, A perspective on leakage current induced by threading dislocations in 4H-SiC Schottky barrier diodes, Materials Letters, 310 (2022) 131506.

E. Cela, W. Schwarzenbach, R. Shrestha, G. Bast, S. Shahidi, G. Simpson, DUV laser-based defect inspection of single-crystal 4H-SiC and SmartSiC engineered substrates for high volume manufacturing, ICSCRM 2024 conference, Session 10 (2024) Poster 2.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 9-14

doi: 10.4028/p-S58gNE

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

Weining Qian 1,2,a, Feihong Huang 2, b, Jinan Li2,c, Gan Feng 2, d, Yongqiang Sun 2,e, Jianhui Zhao 1,2,f and Junyong Kang 1,g*

¹College of Physical Science and Technology, Xiamen University, Xiamen, 361005, Fujian, China

2 Epiworld International Co., LTD, Xiamen 361101, Fujian, China

a  qianwn@epiworld.com.cn, b  huangfh@epiworld.com.cn, clija@epiworld.com.cn, d fengg@epiworld.com.cn, e sunyq@epiworld.com.cn, f zhaojh@epiworld.com.cn, g*jykang@xmu.edu.cn

Abstract

Surface pits in silicon carbide ( SiC ) epitaxial layers have a significant impact on various types of SiC devices, potentially causing electric field concentration and degrading device performance. The formation mechanism of surface pits remains unclear. In this work, the mechanism was investigated through the molten KOH etching experiments, and we confirmed that surface pits originate from dislocation defects in the substrate, particularly TSDs. The dislocations negatively impacted the step-flow growth of epitaxy, leading to pit formation. Further investigations into the effects of growth temperature, C/Si ratio, and epitaxial-layer thickness on pit formation revealed that low temperatures and silicon-rich conditions could effectively suppress pit formation. Both the density and size of surface pits increased significantly with the increase in epitaxial layer thickness. Therefore, this work proposes a model for the formation mechanism of surface pits, where the competition between step-flow growth and spiral growth is a key factor in controlling the size of surface pits.

Keywords: 150 mm4H−SiC, hot-wall reactor, surface pit.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

Compared to traditional silicon semiconductors, 4H−SiC offers revolutionary advantages in highvoltage and high-power applications, owing to its wide bandgap, high breakdown electric field, and high thermal conductivity [1]. With the accelerated popularization of new energy vehicles, the demand for 4H−SiC power devices in automotive applications has been increasing.

For the fabrication of 4H−SiC power devices, chemical vapor deposition (CVD) is one of the key technologies to conduct the homo-epitaxial growth. Nowadays, the defects in epitaxial layers remain a primary challenge in device fabrication, as epitaxial layer defects adversely affect the reliability of 4H−SiC power devices. With the continuous development of 4H−SiC epitaxial technology, killer defects (such as triangular defects and carrot defects) have been effectively controlled and significantly reduced [2,3]. However, the impact of non-killer defects (e.g., surface pits) on 4H−SiC devices has gradually become apparent, potentially increasing leakage current and causing long-term reliability issues [4,5]. Thus, understanding the formation mechanisms of surface pits and thus decreasing formation during the epitaxial process is crucial, which could effectively enhance device reliability.

In this work, we investigated the origin of surface pits and explored the influence of epitaxial process parameters on surface pit density during the growth of 4H−SiC epitaxial layers on 150 mm4∘ off-axis substrates using a hot-wall horizontal single-wafer reactor. By optimizing key process conditions (such as the carbon-to-silicon ( C/Si ) ratio and growth temperature), high-quality 4H−SiC epitaxial wafers with low surface pit defect density were successfully achieved, and the formation mechanism of surface pits was revealed. This research holds significant scientific and engineering value for advancing the large-scale application of 4H−SiC epitaxial materials in high-voltage and high-power devices, as well as for improving device reliability.

Experimental

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The epitaxial growth was conducted using a horizontal hot-wall reactor. Trichlorosilane (TCS) and ethylene (C2H4) served as the silicon and carbon precursors, respectively. Hydrogen (H2) was used as both carrier and dilution gas, while nitrogen ( N2 ) was employed for n-type doping. Homoepitaxial growth was performed on commercial 150 mm,4∘ off-axis n-type 4H-SiC substrates with an off-cut orientation towards <11-20>. Substrates from the same manufacturer, ingot, and with closely matched lot numbers were selected for comparative experiments to eliminate performance variations caused by substrate quality differences. The TSD density of all substrates used was controlled within the range of 200−400 cm−2. The epitaxial process temperature varies between 1550∘C and 1650∘C, and the chamber pressure was maintained at 100 mbar . The introduced C/Si ratio was varied by C2H4 gas flow rate, while keeping the TCS flow rate constant.

A SICA88 instrument was used to analyze the number and distribution of pit defects with a 3 mm edge exclusion. Thickness of 4H−SiC epitaxial layer was evaluated by Fourier-Transform Infrared spectroscopy (FTIR) with 5−mm edge exclusion. These measurements were performed along the radial direction because the thickness showed concentric distribution.

Results and Discussion

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Molten potassium hydroxide (KOH) treatments were performed on the epitaxial layer to investigate the origin of surface pits. Defect inspections were conducted at identical locations on the same substrate, the same epitaxial wafer, and the epitaxial wafer after KOH treatment. Using the synchronous positioning function of SICA88, differences in defects at the same positions were compared. The correlation between pit defects on the epitaxial wafer and defects on the substrate was investigated, as illustrated in Fig.1. When examining the same location on the substrate (Fig.1(a)), no microscopic defects were observed at the position where pit defects appeared on the epitaxial wafer surface (indicated by arrows in Fig.1(b)). However, after KOH treatment, dislocation defects in the substrate were exposed at precisely the same position on the epitaxial wafer (Fig. 1 (c)). This indicated that the pit defects did not originate from surface microscopic defects of the substrate, but rather from dislocation defects in the substrate. The dislocation defects likely propagated from the substrate to the epitaxial layer during the epitaxial process, and common dislocation defects in the substrate include threading edge dislocations (TEDs), threading screw dislocations (TSDs), and basal plane dislocations (BPDs) [6]. Based on the morphological characteristics of the etched pit, the dislocation defect shown in Fig.1(c) was likely TSDs or TEDs, rather than the BPD [7]. Based on the differences in the Burgers vectors of TSDs and TEDs, their etched pit morphologies vary significantly. The etched pits formed by TSDs showed a hexagonal structure and they were considerably larger than those formed by TEDs [8]. Therefore, as illustrated in Fig.1, the pit defects on the epitaxial wafer originated from the TSD defects in the substrate. The step-flow growth (along the <11−20> direction) dominated the epitaxial growth of 4H−SiC. If TSDs are present in the 4H−SiC substrate, spiral growth (non-<11-20> direction) would occur at the TSD sites, resulting in the formation of surface pits.

According to the identification of the correlation between surface pits and substrate dislocations, the effects of growth temperature, C/Si ratio, and epitaxial layer thickness on the formation of surface pits were investigated to reduce pits density. Under a fixed C/Si ratio of 0.8,4H−SiC epitaxial layers with a thickness of 10μ m were grown at temperatures of 1570∘C,1590∘C,1620∘C, and 1650∘C, respectively. This was to investigate the effect of growth temperature on surface pit defects. The results, as shown in Fig.2(a), indicated that the density of surface pits decreased significantly with decreasing growth temperature. This might be because the low temperatures suppress the spiral growth of dislocations, thereby reducing the formation of surface pits. Moreover, we explored the role of the surface C/ Si ratio in pit formation. The growth temperature was fixed at 1570∘C, while C/Si ratios of 0.8,0.9,1.0, and 1.1 were employed during epitaxial growth of a 10μ m-thick epitaxial layer. The results presented in Fig.2(b) demonstrated that the surface pit density decreased as the C/Si ratio was reduced. The underlying mechanism is that a lower surface C/Si ratio suppresses the spiral growth of dislocations [9], thereby effectively reducing the formation of pit defects.

Additionally, the evolution of pit size as the thickness increases was studied to investigate the formation of pit defects. Under the conditions of a C/Si ratio of 1.0 and a growth temperature of 1570∘C, 4H-SiC epitaxial layers with varying thicknesses ( 6μ m,12μ m,30μ m, and 60μ m ) were prepared to investigate the influence of epitaxial thickness on surface pit defects. As revealed in Figs.2(c) and 2(d), both the density and size of surface pits increased significantly as the epitaxial layer thickness increased. Based on the detection resolution of the SICA88 surface defect inspection system, the number of pits within different surface size ranges was compared across layers of different thicknesses (see Table 1). The results showed a gradual increase in the total number of detected pit defects and the number of large-sized pits, with increasing epitaxial layer thickness. This indicated that pit defects enlarged progressively during epitaxial growth until they reached the resolution limit of the inspection equipment and became detectable. Given that the pit defects originated from TSDs in the substrate, it could be concluded that the initial density of TSDs in the substrate were the fundamental factor determining the final number of pit defects in the epitaxial layer.

Finally, based on the origin of surface pits and the effects of growth parameters on these pits, we proposed a model of the formation mechanism of surface pits (Fig.3) [10]. The formation of surface pits essentially stemmed from the competition between step-flow growth of dislocations and spiral growth of dislocations. The dynamic balance between these two growth directly determined the size of surface pits. This mechanism underlying the interaction between step-flow growth and spiral growth is similar to that of micropipes formation [11]. The size of pits along non-<11-20> direction increased when spiral growth of dislocations dominates. For the step-flow growth prevails, spiral growth of dislocation was suppressed, leading to a significant reduction in the size of pits non-<1120> direction. The size of pits along the non-<11-20> direction primarily determined the overall size of the pits. The pits with a size over the detection resolution of the SICA88 inspection system could be detected. Under low-temperature or silicon-rich growth conditions, the spiral growth at TSD dislocations was suppressed, which reduced the average size of the pits, thereby decreasing the density of surface pits.

[picture]

Fig. 1. The surface morphology of (a) the substrate and (b) the epitaxial wafer, and (c) the epitaxial wafer after KOH treatment. All surface morphologies were taken from the same location by SICA88.

Fig. 1. The surface morphology of (a) the substrate and (b) the epitaxial wafer, and (c) the epitaxial wafer after KOH treatment. All surface morphologies were taken from the same location by SICA88.

[picture]

Fig. 2. Effect of different (a) growth temperature, (b) C/Si ratio and (c) growth thickness on the pit defect density; (d) Size of pit defects at different growth thicknesses.

Fig. 2. Effect of different (a) growth temperature, (b) C/Si ratio and (c) growth thickness on the pit defect density; (d) Size of pit defects at different growth thicknesses.

Table 1. The number of pits versus their size on epitaxial layers with different thicknesses (by SICA88).

Thickness | Total number of pits | Number of pits (<100 μm²) | Number of pits (100~250 μm²) | Number of pits (250~1000 μm²)
6 μm | 53 | 42 | 11 | 0
12 μm | 236 | 182 | 47 | 7
30 μm | 6504 | 6237 | 241 | 26
60 μm | 32477 | 24909 | 7505 | 63

[picture]

Fig. 3. Schematic illustration of the proposed model of the formation mechanism of surface pits.

Fig. 3. Schematic illustration of the proposed model of the formation mechanism of surface pits.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

This work systematically investigated the origin of surface pits in 4H−SiC epitaxial layers and their dependence on epitaxial growth parameters. Experimental results indicated that surface pits primarily originate from TSDs in the substrate. There was a spiral growth during the epitaxial process, leading to the formation of surface pits. By adjusting growth conditions (e.g., reducing temperature or the C/Si ratio), the formation and expansion of pits could be effectively suppressed. Furthermore, as the epitaxial layer thickness increased, both the density and size of the pits gradually increased, indicating that the pits undergo continuous evolution during growth. Based on these findings, a mechanistic model was proposed, showing the role of competition between step-flow growth and spiral growth of TSD in regulating pit morphology. This work provided a theoretical understanding and practical guidance for optimizing the SiC epitaxial processes, especially suppressing surface pits. It would offer a significant value for improving the performance of SiC devices.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.9.pdf

S. Ranbir, A. C. James, SiC power Schottky and PiN diodes, IEEE Trans. Electron Devices. 49 (2002) 665-672.

K. Tsunenobu, M. Nao, M. Hiroyuki, Performance limiting surface defects in SiC epitaxial pn junction diodes, IEEE Trans. Electron Devices. 46 (1999) 471-477.

S. A. El Hageali, G. Harvey, J. Stevenm, et al, Optoelectronic and structural characterization of trapezoidal defects in 4H-SiC epilayers and the effect on MOSFET reliability, J. Appl. Phys. 134 (2023) 075704.

H. Fujiwara, H. Naruoka, M. Konishi, et al, Impact of surface morphology above threading dislocations on leakage current in 4H-SiC diodes, Appl. Phys. Lett. 101 (2012) 42104.

T. Katsuno, Y. Watanabe, T. Ishikawa, et al, Surface morphology of leakage current sources of 4H-SiC Schottky barrier diodes by atomic force microscope, Trans. Tech. Publications. 375 (2012) 717-720.

P. C. Chen, W. C. Miao, T. Ahmed, et al, Defect inspection techniques in SiC, Nanoscale Res. Lett. 17 (2022) 1-17.

T. Ohno, H. Yamaguchi, S. Kuroda, et al, Direct observation of dislocations propagated from 4H-SiC substrate to epitaxial layer by X-ray topography, J. Cryst. Growth 260 (2004) 209-216.

T. Katsuno, Y. Watanabe, H. Fujiwara, et al, New separation method of threading dislocations in 4H-SiC epitaxial layer by molten KOH etching, Mater. Sci. Forum 679 (2011) 298-301.

S. I. Nakamura, T. Kimoto, H. Matsunami, et al, Effect of Si ratio on spiral growth on 6 H SiC (0001), Jpn. J. Appl. Phys. 42 (2003) 846-848.

R. Karhu, M. Ghezellou, J. UI Hassan.The origin and formation mechanism of an inclined linelike defect in 4H-SiC epilayers. Phys. Status Solidi B 259 (2022) 2100512.

I. Kamata, H. Tsuchida, T. Jikimoto, K. Izumi. Influence of 4H-SiC growth conditions on micropipe dissociation. Jpn. J. Appl. Phys. 41 (2002) L1137.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 15-19

doi: 10.4028/p-d2PrxR

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-15

Accepted:
2026-01-31

Online:
2026-05-18

Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

C. Wißgott 1,a*, B. Kallinger 1, b and M. Rommel 1,c

1 Fraunhofer IISB, Schottkystraße 10, 91058 Erlangen, Germany

a  christian.wissgott@iisb.fraunhofer.de, b  birgit.kallinger@iisb.fraunhofer.de, c  mathias.rommel@iisb.fraunhofer.de

Keywords: charge carrier lifetime, photoconductivity decay, defect, statistical process control.

Abstract

The quality of the epitaxial layer plays an important role in the performance of modern power electronic devices. Minority carrier lifetime is known to be sensitive to defects like dislocations, stacking faults, and points defects. Therefore, in this work lifetime measurements by microwave detected photoconductivity decay are used to evaluate the quality of the epitaxial layer on various 4H−SiC substrates from different vendors. The stability of the measurement technique is shown by a daily release measurement. This allows for a reliable analysis of almost 300 typical 1,200 V epilayer stacks. It has been shown that the effective lifetime of these samples can be separated into two different ranges. The lifetime values of about 120 ns fit to theoretical calculations. The cause for the increased lifetime of about 250 ns in the second range has yet to be determined in further research. Furthermore, the lifetime maps were used to locate defects in the surface near regions.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

For many modern power electronic devices epitaxial growth on top of a silicon carbide ( SiC ) substrates represents an important first step. The quality of the layer can strongly influence the quality of the subsequent process steps and, therefore, the performance of the whole device [1]. Defects like dislocations, stacking faults, and extrinsic point defects, which might be transferred from the substrate to the epitaxial layer or form in the layer itself can strongly restrict the possible device yield [1,2]. Minority carrier lifetime is known to be sensitive to the presence of such defects, as well as to doping and thickness variations and surface and interface recombination [3]. Hence, lifetime measurements potentially offer a nondestructive and contactless way of monitoring the quality of the grown layer.

Experimental

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Conventional 4H−SiC substrates with a diameter of 150 mm and a 4∘ off-axis orientation towards [112―0] from different vendors were used for epitaxy in multiwafer planetary reactors (AIXTRON G5 WW C and G10-SiC epitaxy reactors). The total thickness of the layers ranged between 10 and 14 μm, with a typical thickness deviation across individual wafers <4%σ/ mean. The layers featured an n-type doping concentration between 8×1015 and 2×1016 cm−3 and a lateral doping deviation <6.5%σ/ mean across the wafer area, which is common for typical 1,200 V epilayer stacks. A buffer layer of 1μ m thickness and doping concentration of 1×1018 cm−3 is included. The carrier lifetime of almost 300 epitaxial wafers has been determined by microwave detected photoconductivity decay ( μ-PCD) measurements in a SEMILAB WT-2000. A laser pulse at a wavelength of 349 nm for 4 ns with 120 μJ per pulse and a raster size of 1 mm was used. An edge exclusion of 3 mm was applied to exclude edge effects.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

Stability of the Measurement Technique.

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To verify the stability of the measurement technique and the tool itself a daily release measurement was performed on the same wafer each morning. After calibrating the laser, the same four points in
the sample center were being measured. The mean values of these four measurement points for each day are depicted in Figure 1. In this statistical process control (SPC) chart the measured values are controlled by an upper and lower specification limit as well as an upper and lower control limit. The former has been defined as ±8% to the mean value over all measurements. A deviation of the measured values outside of these limits can be used to explain irregularities in the measurement data that might occur on specific days. The control limits are defined as three times the standard deviation σ over and under the target value and represent the hard limitation for the usability of the tool.

[picture]

Fig. 1. Statistical process control (SPC) chart of daily μPCD measurements in the center of the same SiC sample with mean value, upper / lower spec limit (USL / LSL) and upper / lower control limit (UCL / LCL).

Fig. 1. Statistical process control (SPC) chart of daily μ P C D measurements in the center of the same SiC sample with mean value, upper / lower spec limit (USL / LSL) and upper / lower control limit (UCL / LCL).

As can be seen in the SPC chart, in over 90 measurement days the spec limits have only been passed on a small number of days, while the control limits have never been breached. This confirms the reliable usage of this measurement process.

Statistical Overview of Lifetime Measurements.

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

Almost 300 epiwafers with 1,200 V epilayers have been analyzed using the μPCD technique. In Figure 2a) exemplary lifetime maps with a raster size of 1 mm for two samples with different lifetimes are presented. Qualitatively, they show the same radial dependence with higher carrier lifetimes in the center of the sample and a decrease towards the edges. However, the maximum value and the decline of lifetime is more pronounced for the sample on the right. Additionally, for all epiwafers, the lifetime has been averaged over the entire wafer area, and the results are statistically evaluated in the histogram in Figure 2b). These average lifetimes are divided in two different ranges: most samples exhibit an average carrier lifetime between 75 ns and 150 ns , while there is also a smaller number of samples with lifetimes around 250 ns . Both groups roughly resemble a Gaussian distribution, which is to be expected.

[picture]

Fig. 2. a) Exemplary lifetime maps with 1 mm raster size from two samples with different lifetimes; b) Histogram of the average lifetimes on different SiC wafers, measured by μPCD.

Fig. 2. a) Exemplary lifetime maps with 1 mm raster size from two samples with different lifetimes; b) Histogram of the average lifetimes on different SiC wafers, measured by μ P C D .

According to Klein [3] effective carrier lifetimes in epilayers are dependent on four different recombination processes: Shockley-Read-Hall (SRH), radiative, Auger, and surface recombination, as seen in Equation (1):

1τmeas =1τSRH+1τRad +1τAuger +1τSurf (1)

For 4H−SiC at the given doping concentrations the radiative and Auger contributions can be neglected [3], leaving τSRH  in the bulk and τSurf  at the surface and the interface between epilayer and substrate. Kimoto et al. [4] showed that bulk lifetimes in epilayers dominated by SRH recombination can be estimated using the Z1/2 concentration NZ as following:

τSRH=2·1013 cm−3NZμS(2)

The surface contribution can be approximated using the epilayer thickness d , the carrier diffusion coefficient D , and the surface recombination velocity S , as reported by Klein [3]:

1τSurf =(d2π2D+d2S)−1(3)

This results in the following Equation (4) for the measured carrier lifetime τmeas  :

1τmeas =1τSRH+1τSurf=NZ2×1013 cm−3μ S+(d2π2D+d2S)−1(4)

Using the values for these parameters in Table 1, the measured carrier lifetime τmeas  can be approximated to 120.4 ns at an epilayer thickness of 10μ m. This matches the left lifetime range in the histogram in Figure 2b). However, the cause for samples with lifetimes in the higher range could not be determined yet. A comparison between the average lifetime of the samples and their corresponding epilayer thickness, doping concentration, substrate resistivity, or substrate vendor did not result in any distinct correlation.

In fact, for some samples originating from adjacent regions of the same SiC ingot, which were coated side by side in the same epitaxy process and measured consecutively using the lifetime measurement tool, lifetime values were obtained that could be divided into the two different lifetime ranges.

Table 1. Parameters used to approximate the effective carrier lifetime in the measured samples.

Z1/2 concentration NZ | 5×10¹² cm⁻³ [5]
Epilayer thickness d | 10 μm
Carrier diffusion coefficient D | 4.2 cm²/s [6]
Surface recombination velocity S | 5×10³ cm/s [3]

Lifetime and Defect Comparison.

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

The most probable cause for difference in the lifetime of different samples are defects in the epitaxial layer. In Figure 3 the lifetime maps of three different wafers are shown. Additionally, for each wafer a mapping of defects, recorded with a Lasertec SICA88, is included. It is noticeable that areas with higher density of defects have a strongly decreased carrier lifetime. Particularly stacking faults and polytype inclusions seem to have a strong influence. In the close ups of the Differential Interference Contrast (DIC) images, it is also recognizable that these areas with higher ratio of defects have a rougher surface compared to other areas of the wafers.

[picture]

Fig. 3. Comparison of lifetime and defect maps as well as Differential Interference Contrast (DIC) images (recorded with Lasertec SICA88); average lifetime for each map is given.

Fig. 3. Comparison of lifetime and defect maps as well as Differential Interference Contrast (DIC) images (recorded with Lasertec SICA88); average lifetime for each map is given.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

The μPCD measurement technique offers a fast and non-destructive way of determining the effective lifetime of minority charge carriers in the epitaxial layer of 4H−SiC epilayer stacks. This can be used to gain information about the quality of the epilayers as well as the location and density of defects in the layer. With the use of the daily measurements the stability of the measurement tool can be controlled. Additionally, the lifetime values around 120 nm could be verified by theoretical calculations. However, the occurrence of the second lifetime range is still not fully understood. In further research the different types of defects and their density in samples from the different groups will be compared, to gather further insight into their impact on the charge carrier lifetime.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.15.pdf

D. Baierhofer, B. Thomas, F. Staiger, B. Marchetti, C. Förster, and T. Erlbacher, "Defect reduction in SiC epilayers by different substrate cleaning methods," Mater. Sci. Semicond. Process., vol. 140, p. 106414, Mar. 2022, doi: 10.1016/j.mssp.2021.106414.

J. Erlekampf et al., "Lifetime limiting defects in 4H-SiC epitaxial layers: The influence of substrate originated defects," J. Cryst. Growth, vol. 560-561, p. 126033, Apr. 2021, doi: 10.1016/j.jcrysgro.2021.126033.

P. B. Klein, "Carrier lifetime measurement in n-4H-SiC epilayers," J. Appl. Phys., vol. 103, no. 3, Feb. 2008, doi: 10.1063/1.2837105.

T. Kimoto, T. Hiyoshi, T. Hayashi, and J. Suda, "Impacts of recombination at the surface and in the substrate on carrier lifetimes of n-type 4H-SiC epilayers," J. Appl. Phys., vol. 108, no. 8, Oct. 2010, doi: 10.1063/1.3498818.

D. Kaminzky, B. Kallinger, P. Berwian, M. Rommel, and J. Friedrich, "Modelling of Effective Minority Carrier Lifetime in 4H-SiC n-Type Epilayers," MSF, vol. 858, pp. 341-344, May 2016, doi: 10.4028/www.scientific.net/MSF.858.341.

P. Grivickas, J. Linnros, and V. Grivickas, "Carrier diffusion characterization in epitaxial 4HSiC," J. Mater. Res., vol. 16, no. 2, pp. 524-528, Feb. 2001, doi: 10.1557/JMR.2001.0075.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 21-26

doi: 10.4028/p-7MIvaq

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-21

Accepted:
2026-02-23

Online:
2026-05-18

DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Lan Luo 1,a, Yu Zhong 1,2, b*, Xiaoshuang Yang 1,c, Quanxin Zhao 1, d, Peng Cui 1,e, Yingxin Cui 1,f, Mingsheng Xu 1, g, Xiangang Xu 1, h and Jisheng Han 1,i*

1Institute of Novel Semiconductors, State Key Laboratory of Crystal Materials, Shandong University, Jinan, 250100, China

2 Shandong Research Institute of Industrial Technology, Jinan, 250100, China

alan.luo@mail.sdu.edu.cn, b  yu.zhong@sdu.edu.cn, c  202434109@mail.sdu.edu.cn, d  202414092@mail.sdu.edu.cn, e  pcui@sdu.edu, f  cuiyingxin@sdu.edu.cn, g xums@email.sdu.edu.cn, h xxu2002@163.com, j j.han@sdu.edu.cn

Keywords: 4 H -SiC, SBD, DLTS, Characterization, Deep Level Defects, Measurement Parameters.

Abstract

This paper investigates the effect of DLTS measurement parameters on characterizing deep level defects in 4H-SiC Schottky barrier diode (SBD). By adjusting parameters such as the time window ( tW ), pulse time ( tP ), reverse voltage ( UR ), and pulse voltage ( UP ), the underlying mechanisms influencing defect peak positions, signal amplitudes, and peak broadening are analyzed. Experimental results reveal three deep level defects identified in 4H−SiC SBD: majority carrier traps T1 ( EC− 0.66 eV ) and T2(EC−1.0eV), along with minority carrier trap T3(EV+1.1eV). Parameter settings not only influence defect characterization sensitivity and concentration calculations but also reveal the dynamics of carrier capture and emission. Through the thorough analysis of the DLTS signal and behavior under different DLTS measurement conditions, the electronic properties and concentration profiles of deep level defects in 4H-SiC epitaxial layers are determined.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

4H-Silicon carbide (4H−SiC) is one of the remarkable wide bandgap semiconductor materials due to its extraordinary properties, such as high breakdown electric field, high electron saturation drift velocity, and high thermal conductivity. Consequently, it is extensively utilized in high-power, hightemperature, and high-voltage applications [1,2]. However, deep level defects are key factors affecting the performance of 4H−SiC devices, significantly reducing carrier lifetime, mobility, and device reliability [3].

Deep level transient spectroscopy (DLTS) is a powerful technique widely used for studying deep level defects in semiconductors [4,5]. It can determine critical defect parameters, such as energy level position in the bandgap, capture cross-section, and defect concentration (NT). Still, the accuracy and resolution of DLTS measurements highly depend on the settings of the measurement parameters. This paper aims to systematically analyze the effects of key DLTS measurement parameters on the characterization results of deep level defects of 4H−SiC, including the time window ( tw ), pulse time (tP), reverse voltage ( UR ), and pulse voltage ( UP ). The findings aim to provide a crucial experimental and theoretical basis for the precise analysis of deep level defects in 4H-SiC with DLTS measurements.

Experimental

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The sample used in this study is 4H−SiC Schottky barrier diode (SBD), with its structural schematic shown in Fig. 1(a). The device, fabricated by Guangzhou Summit Power Semiconductor Co., Ltd., has an active area of 3.24 mm2. The current-voltage (I-V) characteristics of the device demonstrated good rectification, with an ideality factor of 1.05 and a Schottky barrier height of 1.2 eV . Furthermore, capacitance-voltage ( C−V ) curve analysis indicates a doping concentration of 8.6×1015 cm−3 for the n-type epitaxial layer, as shown in Fig. 1(b).

DLTS measurements are conducted over the temperature range from 100 K to 700 K using a PhysTech FT-1230 HERA-DLTS. DLTS spectra are acquired under various conditions by adjusting measurement parameters, including tw,tP,UR, and UP. A typical diagram of the DLTS measurement parameters and resulting transient capacitance is shown in Fig. 1(b). The measurement procedure is as follows: the sample is initially maintained under UR. The UP is then applied to fill the traps in the space charge region with carriers. At the end of UP, the bias voltage reverts to UR, initiating the carrier emission process. The subsequent capacitance transient is recorded over a specified tw. The influence of these DLTS parameters on the derived defect characteristics in SiC is systematically analyzed.

[picture]

Fig. 1. (a) Schematic diagram of 4H−SiCSBD structure. (b) C−V characteristic of 4H−SiCSBD. (c) Diagram of the DLTS measurement parameters and transient capacitance signals generated during carrier emission.

Fig. 1. (a) Schematic diagram of 4 H − S i C S B D structure. (b) C − V characteristic of 4 H − S i C S B D . (c) Diagram of the DLTS measurement parameters and transient capacitance signals generated during carrier emission.

Result and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Effect of Time Window on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

In DLTS signals, peaks can be observed when the trap emission rates ( eT ) match the tw. Changing tw results in peak positions to shift with temperature, allowing the eT to be measured through temperature scanning. As shown in Fig. 2(a), all peaks shift towards lower temperatures with increasing tw. This shift occurs because a longer tw corresponds to a slower eT. Since the eT of a trap follows an exponential dependence on the inverse temperature, a slower eT is matched at a lower temperature [4].

eT=Nc,vσvthexp(−ΔEkBT)(1)

Where σ is the trap capture cross-section, vth  is the thermal velocity of carriers, ΔE is the activation energy of the trap, and Nc,v is the effective density of states in the conduction band or valence band.

Fig. 2(a) shows the DLTS spectra of 4H−SiC SBD measured under different tw. Three signal peaks are observed: a positive peak appearing in the temperature range from 280 K to 330 K , labeled T1; a positive peak appearing in the range from 450 K to 550 K , labeled T 2 ; and a negative peak appearing in the range from 570 K to 620 K , labeled T3. As tw increases, the amplitude of T1 peak remains essentially unchanged, while the amplitudes of T2 and T3 peaks decrease obviously. The peak amplitude of the DLTS signal is proportional to the NT. Fig. 2(b) shows defect information derived from Arrhenius plot fitting under different tW, including σ and NT. As tW increases, the NT of T 2 and T3 decreases. Shorter tw is more sensitive to defects with faster eT, whereas a longer tw primarily detects defects with slower eT. Consequently, if tW does not match the eT of defects contributing to T2 and T3 peaks, the signal amplitudes of the peaks decrease.

The deep level trap T1 is identified as a majority carrier trap with the energy level located 0.66 eV below the bottom of the conduction band (EC). It exhibits a symmetric Gaussian-shaped peak and a single-exponential emission kinetics and these are characteristics of point defects. The measured ΔE and σ of T1 are consistent with the fingerprint of the Z1/2 center, an intrinsic defect complex in n-type 4H−SiC. The Z1/2 center, which is commonly attributed to a carbon vacancy (VC) or related complex,
can act as a lifetime-killing recombination center and is commonly observed in DLTS spectra of asgrown 4H-SiC epitaxial layers [6].

T 2 is a majority carrier trap with the activation energy of at EC−1.0eV. It exhibits broad and asymmetric DLTS peaks, which suggests T2 is not related to the discrete point defects. T2 may correspond to envelope peaks formed by multiple defects with close energy levels or the extended defect [7,8].

T3 is a minority carrier trap with the energy level located 1.1 eV below the valence band top (Ev +1.1 eV ). The 4H−SiCSBD is a unipolar device where minority carriers are typically absent under reverse bias. However, the presence of the P+ region can serve as a source of minority carrier injection under specific measurement conditions. This injection makes the detection of the minority carrier traps such as T3 possible [9, 10]. T3 exhibits a broad and asymmetric DLTS peak, which is characteristic of interface states at the metal/SiC interface or extended defects rather than point defects. Extended defects in 4H−SiC, such as stacking faults, dislocation clusters, or basal plane dislocations, can introduce broad distribution of energy levels within the bandgap due to strain fields and localized electronic states. These defects act as minority carrier trapping centers and can significantly affect carrier recombination and device reliability.

[picture]

Fig. 2. (a) DLTS spectra and (b) defect information of 4H−SiCSBD under different tw.

Fig. 2. (a) DLTS spectra and (b) defect information of 4 H − S i C S B D under different t w .

Effect of Pulse Time on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Fig. 3(a) illustrates the effect of tp on the DLTS spectrum. As tp increases, the position and shape of T1 peaks remain unchanged, indicating that its trap filling saturates rapidly even at the shortest tp. This result is consistent with the data in Fig. 3(b) that the amplitude of T1 peak does not exhibit significant variation with tp, which is characteristic of the capture kinetics of a point defect. In contrast, as tp increases, the T2 and T3 peaks shift to higher temperatures, gradually broaden, and their amplitude continues to increase over the entire test range in agreement with the trend in Fig. 3(b). This behavior strongly suggests the presence of a more complex capture mechanism involving defects with a continuous energy distribution. This feature of T2 peak is typically regarded as the fingerprint characteristic of spatially extended defects such as dislocations, stacking faults, or defect clusters [11, 12]. The capture process in such defects is governed by a combination of factors. These include potential barriers around the defect core, carrier re-emission during capture, or a distribution of capture rates. These factors lead to the observed slow, non-exponential filling behavior. As a minority carrier trap, T3 exhibits amplitude saturation when tp exceeds 100 ms . However, it also demonstrates significant increase before saturation, suggesting it possesses non-point defect kinetic properties. These characteristics are associated with defect clusters or interface states at the metal /SiO2 interface.

The defect parameters extracted from Arrhenius plots under different tp are summarized in Fig. 3(c). As tp increases, the σ of all three defects shows no obvious change. For NT, along with the increase of tp, the values for T2 and T3 exhibit an upward trend, while T1 remains almost unchanged.

Therefore, the tp used in this work can reveal the kinetic characteristics of T2 and T3 and confirm their non-point defect nature. It should be noted that accurate quantification of the total concentration of extended defects like T2 and T3 requires measurements at longer tp to ensure complete trap filling.

[picture]

Fig. 3. (a) DLTS spectra of 4 H -SiC SBD under different tp, (b) amplitudes of DLTS peaks as a function of the logarithm of the tp, and (c) defect information extracted from Arrhenius analyses.

Fig. 3. (a) DLTS spectra of 4 H -SiC SBD under different t p , (b) amplitudes of DLTS peaks as a function of the logarithm of the t p , and (c) defect information extracted from Arrhenius analyses.

Effect of Reverse Voltage on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Fig. 4 shows the DLTS spectra and the corresponding defect information under different UR. As the absolute value of UR decreases (|UR|), the NT of three defects reduces due to the narrowing of the detection depletion region width. The depth of the depletion region width can be tuned by applying different UR values and in this way defect profile information can be obtained. The signal amplitudes of T2 and T3 peaks exhibit non-monotonic and irregular fluctuations with changing UR. This behavior indicates an uneven distribution of these defects, further corroborating their association with extended defects. Such distribution characteristics are typically observed in defect clusters or extended structural defects.

[picture]

Fig. 4. (a) DLTS spectra and (b) defect information of 4H−SiCSBD under different UR.

Fig. 4. (a) DLTS spectra and (b) defect information of 4 H − S i C S B D under different U R .

Effect of Pulse Voltage on DLTS Spectra

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

Fig. 5 shows the DLTS spectra and the derived defect information under different Up. As Up increases, the depletion region width of the diode becomes narrower during UP period. This reduction allows more carriers to inject into the detection region, thereby filling more deep level traps, resulting in an enhanced DLTS signal. For varied UP, traps located at different depth scan be filled due to the corresponding changes in band bending. This capability enables the analysis of the spatial distribution of defects along with the depth. When utilized in combination with UR,UP can be effectively employed to distinguish between the deep level defects in bulk material and the interface states [13].

[picture]

Fig. 5. (a) DLTS spectra and (b) defect information of 4H−SiCSBD under different UP.

Fig. 5. (a) DLTS spectra and (b) defect information of 4 H − S i C S B D under different U P .

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

In conclusion, this study employs DLTS to measure three deep-level centers in 4H-SiC SBDs. The effects of different measurement conditions on the deep-level defects at different energy levels are compared. The result indicates that tw corresponds to the emission rate of specific traps; it can be used to distinguish between point defects and the extended defects. As tp increases, the amplitude of deep level trap peaks gradually saturates. Therefore, a higher tp is recommended for more precise detection of defects at specific energy levels. Furthermore, by precisely controlling the UR and UP, the concentrations and depth distributions of defects in the epitaxial layer can be quantitatively determined, enabling the distinction between the bulk traps and the interface traps. This paper offers crucial experimental evidence and theoretical basis for the precise characterization of deep level defects and the optimization of DLTS measurement protocols.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.21.pdf

F. La Via, D. Alquier, F. Giannazzo, T. Kimoto, P. Neudeck, H. Ou, A. Roncaglia, S.E. Saddow, S. Tudisco, Emerging SiC Applications beyond Power Electronic Devices. Micromachines. 14 (2023) 1200.

M. Buffolo, D. Favero, A. Marcuzzi, C. De Santi, G. Meneghesso, E. Zanoni, M. Meneghini, Review and Outlook on GaN and SiC Power Devices: Industrial State-of-the-Art, Applications, and Perspectives. IEEE Transactions on Electron Devices. 71 (2024) 1344-1355.

I. Capan, 4H-SiC Schottky Barrier Diodes as Radiation Detectors: A Review. Electronics. 11 (2022) 532.

D.V. Lang, Deep-level transient spectroscopy: A new method to characterize traps in semiconductors. J. Appl. Phys. 45 (1974) 3023-3032.

L. Luo, Yu. Zhong, K. Y. Cheong, R. Zhang, T. Wang, D. Yuan, H. Linewih, S. Li,, Y. Cui, M. Xu, X. Xu, J. Han, The Principles and Applications of Electrical Characterization Techniques for Electrically Active Defects in 4H-SiC Devices. J. Phys. status solidi A. 222 (2025) 2400840.

T. Kimoto; J. A. Cooper, Characterization Techniques and Defects in Silicon Carbide, in Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, Wiley, Singapore, 2014, pp.125-187.

Y. He, G. Yan, X. Liu, Z. Shen. W. Zhao, L. Wang, F. Zhang, G. Sun, Y. Zeng, Investigation of Defect Levels of Al/Ti 4H-SiC Schottky structures by Deep Level Transient Spectroscopy, 2019 16th China International Forum on Solid State Lighting & 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS), Shenzhen, China, 2019, pp. 7-10.

H. J. Kang, J. H. Moon, W. Bahng, S. Lee, H. Kim, S. -M. Koo, D. Lee, D. Lee, H. -Y. Cho, J. Heo, H. J. Kim, Oxygen- and photoresist-related interface states of 4H-SiC Schottky diode observed by deep-level transient spectroscopy. J. Appl. Phys. 122 (2017) 094504.

J. Weber, H. B. Weber, M. Krieger, On deep level transient spectroscopy of extended defects in n-Type 4H-SiC, in 2016 European Conference on Silicon Carbide & Related Materials (ECSCRM), Halkidiki, Greece, 2016, pp. 1-1.

X. Gao, X. Wang, Y. Li, Z. Yang, M. Gong, M. Huang, Y. Ma, Comparing the effect between room temperature and low temperature heavy ion irradiation by deep level transient spectroscopy. Nucl. Instrum. Methods Phys. Res., B. 550 (2024) 165319.

L. Gelczuk, G. Jozwiak, M. Dabrowska-Szata, D. Radziewicz, Dislocation in latticemismatched InGaAs/GaAs heterostructures as a factor of optoelectronic device degradation. Proceedings of 2005 International Students and Young Scientists Workshop Photonics and Microsystems, 2005., Dresden, Germany, 2005, pp. 33-36.

L. Gelczuk, M. Dąbrowska-szata, Z. Synowiec, Electrically active defects in SiC Schottky barrier diodes. Mater Sci-Pol. 29 (2011) 70.

A. V. P. Coelho, M. C. Adam, H. Boudinov, Distinguishing bulk traps and interface states in deep-level transient spectroscopy. J. Phys. D: Appl. Phys. 44 (2011) 305303.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 27-31

doi: 10.4028/p-QD8ybH

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-10

Accepted:
2026-02-23

Online:
2026-05-18

Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

Z. X. Fu 1,a, X. L. Yang 1, b*, X. F. Chen 1,c*, X. J. Xie 1, d, L. Sun 1,e, H. Y. Shao 1,f, W. H. Han 1, g, H. X. Wang 1, h, G. J. Yu 2,i, X. G. Xu 1,j

1 State Key Laboratory of Crystal Materials, Institute of Novel Semiconductors, Shandong University, Jinan, 250100, China

2 Guangzhou Summit Crystal Semiconductor Co., Ltd, Guangzhou, 511462, China

af  uzhenxing1122@126.com, b  yangxI2016@sdu.edu.cn, c  cxf@sdu.edu.cn, d  xiexj@sdu.edu.cn,

e sdusunli@sdu.edu.cn, f 202114048@mail.sdu.edu.cn, g hwh@mail.sdu.edu.cn,

h202434144 @mail.sdu.edu.cn, YuGuojian@summitcrystal.com, j xxu@sdu.edu.cn

Abstract

H-SiC single crystals were grown under different temperature fields and nitrogen doping conditions by physical vapor transport method. The distributions of basal plane dislocation (BPD) in 4H−SiC single crystals under different growth conditions were studied by molten KOH etching and X-ray Topography (XRT). The results indicate that the BPDs in the crystals grown under convex temperature field are distributed at the edge. In comparison, the BPD distributions in crystals grown under a concave temperature field are relatively closer to the center. Furthermore, the BPDs distributions in nitrogen-doped crystals exhibit quadratic symmetry caused by prismatic slip. In contrast, no prismatic slip-induced slip bands were observed in the undoped crystals, and the BPD distributions in the undoped crystals are consistent with the shear stress distribution caused by basal plane slip.

Keywords: 4H−SiC,8-inch, BPD distribution, dislocations slip.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

As a representative of the third-generation semiconductors, silicon carbide ( SiC ) exhibits excellent physical and chemical properties, offering a wide range of research and application scenarios [1,2]. Dislocation is one of the main factors limiting crystal quality, among which BPDs could lead to positive voltage drift during device operation. Due to the large size of 8 -inch 4H−SiC crystals, it is difficult to control the temperature field [3,4]. During the growth process of 8 -inch crystals under different temperature fields, the distribution of thermal stress varies, which leads to differences in the distribution of BPDs within the crystal. In addition, nitrogen doping, as a method to adjust the resistivity of SiC crystals to adapt to different needs, changes the physical properties of SiC by replacing carbon atoms with nitrogen atoms[5]. Since the diameter of nitrogen atoms is smaller than that of carbon atoms, the occupation of carbon sites by nitrogen atoms affects lattice matching[6]. Nitrogen doping is found to facilitate the nucleation of BPDs and decrease the shear stress required for the nucleation of BPDs [7].

In this work, we grown 4H−SiC single crystals under different temperature fields and nitrogen doping conditions using the physical vapor transport (PVT) method. The distribution characteristics of BPD in the crystals under different conditions were studied through molten KOH etching and XRT.

Experiments

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

8 -inch 4 H -SiC single crystals were grown on seeds with 4∘ off-angle using the PVT method. The growth temperature of the crystals was maintained at 2000~2200∘C, and the growth pressure was set at 1~10mbar. Other growth conditions are as shown in the Table 1, with the temperature field and whether nitrogen is doped as variables.

Table 1. Growth Conditions of Different Crystals.

Grown crystals | Temperature fields | Doping
Crystal A | Convex | N-doped
Crystal B | Concave | N-doped
Crystal C | Convex | undoped

Wafers from the early growth stage of these crystals were selected and etched by molten KOH solution at 500∘C for 30 minutes. These wafers were labeled as Wafer A1, B1, and C1, respectively. The dislocation morphology of the etched samples was observed using an optical microscope. Adjacent wafers to the etched ones were observed by XRT with the diffraction vector g=11−20, which were labeled as Wafer A2, B2, and C2.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

The BPD distributions of crystals grown in different temperature fields and nitrogen doping conditions are shown in Fig. 1. The BPDs in Wafer A1 are distributed at the edges, while the BPDs in Wafer B1 are away from the edges and more closely distributed towards the center. The reason is that the thermal stress generated during crystal growth under a convex temperature field is mainly distributed at the edges, whereas under a concave temperature field, the stress near the center of the crystal increases compared to the convex temperature field, leading to a distribution of BPDs closer to the center.

The BPD distribution of Wafer C1 is shown in Fig. 1(c). The BPDs in Wafer C1 are also distributed at the edges similar to that in Wafer A. The difference is that the positions with the highest BPD density in Wafer C1 are at the ends of a straight line parallel to the [1-100] direction and passing through the center of the wafer. However, the positions with the highest BPD density in Wafer A1 are four other areas, which is consistent with the report by Lu et al [8]. Although Crystal B was grown under a different temperature field, the distribution of BPDs in wafer B1 also exhibits the same fourfold symmetry as in Wafer A1. This result indicates that nitrogen doping affects the distribution of BPDs in 4H−SiC.

[picture]

Fig. 1. BPD density distribution map of (a) Wafer A1, (b) Wafer B1 and (c) Wafer C1.

Fig. 1. BPD density distribution map of (a) Wafer A1, (b) Wafer B1 and (c) Wafer C1.

After etching, 12 areas on Wafer A1 were observed, and the results are shown in Fig. 2(a). The BPD directions at different locations exhibit a certain pattern: in each area, the BPD etch pits mainly have two directions, both of which are two out of [11-20], [1-210] and [-2110]. The distribution characteristics of the BPD directions show a 12-fold symmetry, similar to the pattern discovered by Hu et al [9]. Additionally, among the four high dislocation density locations corresponding to Fig. 1(a), the number of BPDs along the [11-20] direction is significantly higher than that along other directions. This indicates that the reason for the fourfold symmetry in BPD density distribution is due to an increase in the number of BPDs in the [11-20] direction at specific locations.

Lu et al. [10] have pointed out that the primary dislocation slip mode during the growth of 8 -inch 4 H -SiC crystals is prism slip. By observing 12 areas on Wafer A2 using XRT, as shown in Fig. 2(b), a large number of dislocation lines caused by prism slip were found in the 12 areas of Wafer A2, and the direction of these dislocation lines is consistent with the direction of BPD etch pits at the same positions in Wafer A1. Furthermore, a greater number of prism dislocation lines [11] were observed in the four positions with the highest BPD density. This indicates that in N-doped 4H-SiC crystals grown under convex temperature fields, prism slip is the main cause of BPD generation.

[picture]

Fig. 2. (a) Morphology of BPD etch pitson Wafer A1, (b) Prismatic dislocations on Wafer A2.

Fig. 2. (a) Morphology of BPD etch pitson Wafer A1, (b) Prismatic dislocations on Wafer A2.

Fig. 3(a) shows the optical microscope images of BPD etch pits in 12 areas of Wafer B1, with the selected 12 positions being closer to the center of the wafer. The BPDs direction in Wafer B1 exhibit a 12-fold symmetric distribution, and the BPD quantities show a fourfold symmetric distribution, same as those in Wafer A1. Moreover, the number of BPDs in the [11-20] direction is higher than others. Fig. 3(b) presents the XRT image of Wafer B2, where the distribution of prism dislocations are highly consistent with those of BPD. This indicates that in N-doped 4H−SiC crystals grown under concave temperature fields, the main cause of BPD generation is still prism slip.

[picture]

Fig. 3. (a) Morphology of BPD etch pits on Wafer B1, (b) Prismatic dislocations on Wafer B2.

Fig. 3. (a) Morphology of BPD etch pits on Wafer B1, (b) Prismatic dislocations on Wafer B2.

Fig. 4(a) shows the BPD etch pit images in 12 areas of Wafer C1, with the selected 12 areas being the same as those in wafer A1. The characteristics of BPD in Wafer C1 are completely different from the patterns observed in wafers A 1 and B 1 . The directions of BPD etch pits in Wafer C1 are random. Fig. 4(b) presents the XRT image of 12 areas in Wafer C2, where no prism dislocation lines were observed. This indicates that in undoped 4H−SiC crystals grown under convex temperature fields, prism slip has no contribution to the generation of BPD. Moreover, the BPD distribution shown in Fig. 1(c) is consistent with the results of basal plane slip reported by Lu et al., suggesting that in undoped 4H−SiC crystals, basal plane slip is the main cause of BPD generation.

[picture]

Fig. 4. (a) Morphology of BPD etch pits on Wafer C1, (b) Prismatic dislocations on Wafer C2.

Fig. 4. (a) Morphology of BPD etch pits on Wafer C1, (b) Prismatic dislocations on Wafer C2.

Crystals A and C grow under the same temperature field, but the causes of BPD generation are different. Nitrogen doping is the reason for this phenomenon. It is well known that the {0001} face is the close-packed surface of 4H−SiC, so basal plane slip occurs more easily than prism slip. Therefore, in crystal C , basal plane slip plays a dominant role in the generation of BPD. After nitrogen doping, the critical shear stress of the crystal decreases, leading to the occurrence of prism slip in crystal A, which then dominates, resulting in new characteristics in the BPD distribution.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

Three crystals were grown under different temperature fields and nitrogen doping conditions, and the characteristics of BPD distribution were observed. In the convex temperature field, the BPD
is mainly distributed at the edge of the crystal; while in the concave temperature field, the BPD distribution is closer to the center of the crystal, which is related to the stress distribution under different temperature fields. The BPD distribution in nitrogen-doped crystals shows fourfold symmetry in quantity and twelvefold symmetry in direction, which is related to prism slip; the BPD distribution in undoped crystals shows axial symmetry in quantity and no regularity in direction, which is related to basal plane slip.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

This work was supported by the National Natural Science Foundation of China (Grant No. U23A20569), the Key R&D Program of Shandong Province (2022ZLGX02) and the Taishan Scholars Program.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.27.pdf

X. X. Xiong, X. L. Yang, X. F. Chen, X. M. Li, X. J. Xie, G. J. Hu, Y. Peng, G. J. Yu, X. B. Hu, Y. H. Wang, X. X. Xu, J. Inorg. Mater. 38 (2023) 1371.

Musolino M, Xu X, Wang H, Rengarajan V, Zwieback I, Ruland G, Crippa D, Mauceri M, Calabretta M and Messina, Mater. Sci. Semicond. Process. 135 (2021) 106088.

G. J. Hu, G. L. Zhong, X. X. Xiong, H. D. Li, H. Y. Shao, L. B. Zhao, X. M. Li, X. L. Yang, X. F. Chen, X. J. Xie, Y Peng, G. J. Yu , X. B. Hu, X. G. Xu, Vacuum 222 (2024) 112961.

S. T. Zhang, G. Q. Fu, H. D. Cai, J. Z. Yang, G. F. Fan, Y. Y. Chen, T. Li and L. L. Zhao, Materials 16 (2023) 767.

Y. X Cui, X. B. Hu, K. Yang, X. L. Yang, X. J. Xie, L. F. Xiao and X. G. Xu, Cryst. Growth Des. 15 (2015) 3131-3136.

H. D. Li, X. L. Yang, X. C. Jiang, H. Y. Shao, G. J. Hu, X. M. Li, Y. Peng, X. F. Chen, X. B. Hu, X. J. Xie, G. J. Yu and X.G. Xu. Phys. Scr. 99 (2024) 0959a6.

B. Kallinger, P. Berwian, J.Friedrich, G. Müller, A. D. Webe, E. Volz, G. Trachta, E. Spiecker, B. Thomas, J. CRYST. GROWTH. 349 (2012) 43-49.

X. S. Liu, R. Wang, J. R. Zhang, Y. H. Lu, Y. Q. Zhang, D. R. Yang and X. D. Pi, J. Phys. D: Appl. Phys. 55 (2022) 334002.

S. O Lu, B. J Xu, Y. Z. Wang, H. Y. Chen, W. Hang, R. Wang, J. L. Yuan, X. D. Pi, D. R. Yang and X. F. Han, CrystEngComm. 26 (2024) 2143.

S. S. Hu, S. Fang, Y. F. Liu, Q.Y. Cheng, H. Y. Peng, Z. Y. Chen, Y. H. Gao, C. Gao, B.Raghothamachar and M. Dudley, Mater. Sci. Forum, 1089 (2023) 45-50.

S. O. Lu, B. J. Xu, L. L. Xuan, X. D. Pi, D. Yang and X. F Han, CrystEngComm, 26 (2024) 6244.

J.Q. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quas and I. Manning, J, Electron. Mater. 46 (2017) 2040.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 33-38

doi: 10.4028/p-epPB1m

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2026-01-14

Accepted:
2026-02-23

Online:
2026-05-18

DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

Rosine Coq Germanicus 1,a* and Gabriel Ferro 2, b

¹Normandie Univ, Ensicaen, Unicaen, CNRS, CRISMAT UMR6508, 6 Bvd Marechal Juin, Caen, France

2 Laboratoire des Multimatériaux et Interfaces, CNRS UMR5615, Université Claude Bernard Lyon1, 6 rue Victor Grignard, 69622 Villeurbanne, France

a* rosine.germanicus@unicaen.fr, b gabriel.ferro@univ-lyon1.fr

Keywords: 4 H -SiC, surface structuring, macrostepped morphology, AFM, SSRM, sMIM.

Abstract

Local electrical properties of a 4 H -Silicon Carbide SiC(0001) 4∘ off macrostepped surface, obtained after liquid Si melting in a SiC/Si/SiC sandwich configuration, are investigated by Atomic Force Microscopy (AFM) in both DC and RF modes. On the same sample, macrosteps that are wide enough for allowing spatial resolution of the signal from terraces and step risers, but also some unreacted areas with standard flat surface (without macrosteps) are characterized. Scanning Spreading Resistance (SSRM, DC mode) reveals homogeneous conductivity on the wide terraces of the 4H−SiC(0001) macrosteps. On unreacted areas, which contain many step risers, the resistance is found higher than on the wide terrasses but it is also noisier. In addition, the AFM-RF scanning Microwave Impedance Microscopy (sMIM) mapping confirms the previous results by revealing lower conductivity on the unreacted areas than on the terraces of the macrosteps. Based on these results, some points defects located at the step risers which contribute negatively to the electrical properties of 4H−SiC(0001) surface are identified and electrically characterized.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

In 4H-SiC(0001) MOSFETs, the channel mobility can be limited by the electrically active defects at the SiO2/SiC interface [1]. Some experimental studies suggest that these defects tend to localize at the step edges of the step-and-terrace surface structure generated by the use of 4∘ off-axis crystals [24]. The separation between the effect of step risers and terrasses was possible thanks to the demonstration of macrostepping control of 4H−SiC(0001)4∘ off surface using liquid Si melting in a SiC/Si/SiC sandwich configuration [5, 6]. These results were obtained by using spatially resolved optical responses, not directly related to the electrical properties of the presence of defects at the step risers. In fact, the local electrical impact of these defects remains to be characterized, a crucial factor that can contribute to elucidating and understanding the origin of the low channel mobilities in 4 H SiC MOSFETs.

In this paper, electrical properties of a 4H−SiC(0001)4∘ off macrostepped surface are investigated by Atomic Force Microscopy (AFM) to reveal local electrical properties as a function of the surface morphology. Two complementary AFM electrical modes are applied to explore the surface properties: the widely used Scanning Spreading Resistance (SSRM) mode, which is a DC mode [7], and the more original scanning Microwave Impedance Microscopy (sMIM) mode, which is a RF AFM-mode [8].

AFM Electrical Modes and the Macrostepped SiC Sample

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

AFM measurements were conducted on a Bruker ICON Dimension AFM, with Scanning Spreading Resistance (SSRM) mode and scanning microwave impedance microscopy (sMIM). SSRM is based on the local electrical conduction of the current between a conductive AFM tip and the sample when a VDC bias is applied. In fact, during this electrical contact mode, a conductive AFM
tip contacts the surface, forming a nano-Schottky junction. A logarithmic amplifier records the current from the tip through the sample to the back contact under an applied DC bias (Fig. 1). Using ultra-hard tips (like doped diamond tip) prevents tip deformation and ensures reliable data.

The scanning Microwave Impedance Microscopy (sMIM) is an AFM-RF mode, based on the interaction of an incident 3 GHz microwave signal with the studied surface [6]. The sMIM mode uses this incident RF microwave interacting with the surface, requiring no electrical contact with the AFM chuck. This mode simultaneously maps the surface topography and local electrical properties of the probed materials, producing four channels: topography, deflection, sMIM-C and sMIM-R signals (Fig. 2). The two sMIM signals correspond to the real and imaginary parts of the tip-sample admittance changes.

[picture]

Fig. 1. Schematic of a Scanning Spreading Resistance (SSRM) mode based on an AFM.

Fig. 1. Schematic of a Scanning Spreading Resistance (SSRM) mode based on an AFM.

[picture]

Fig. 2. Schematic of a scanning Microwave Impedance Microscopy (sMIM) mode based on an AFM.

Fig. 2. Schematic of a scanning Microwave Impedance Microscopy (sMIM) mode based on an AFM.

The fabrication procedure for obtaining a macrostepped surface is described in details in ref [4-6]. The sample is obtained from a SiC (wafer)/ Si(30μ m)/SiC (wafer) sandwich stack treated at 1550∘C for 1 h . The vertical thermal gradient naturally forming inside the stack generates a carbon transport through the 30μ m thick liquid Si , from the bottom SiC wafer (hot) to the top SiC wafer (cold). This leads to the formation of parallel macrosteps on the dissolved (cold) surface (Fig. 3.a). Note that it may leave some so-called unreacted areas, denoted A in Fig. 3.b, which correspond to local zone
where the surface did not evolve yet to macrosteps despite being subjected also to dissolution. Though longer treatment times than 1 h allows eliminating these unreacted areas, we used here only 1 h treatment in order to take advantage of the presence of both types of areas (unreacted (A) and macrosteps (B)) in the same AFM scans for proper comparison of their local electrical properties.

[picture]

Fig. 3. SiC macrostepped surface a) SEM view of the SiC surface after thermal treatment and b) 3D view of the AFM topography.

Fig. 3. SiC macrostepped surface a) SEM view of the SiC surface after thermal treatment and b) 3D view of the AFM topography.

Results: Electrical AFM Mappings

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

The AFM height profile (Fig. 4.a) along one line allows easy identification of such unreacted area (A) when comparing to the adjacent macrosteps (B) displaying regular altitude increase and decrease. In order to probe local resistance of the SiC , a conductive diamond coating tip is used in contact with the SiC surface (Fig. 4.a). Prior to SSRM scanning, electrical AFM spectroscopy tests were carried out to determine the optimum VDC values for measuring the current flowing through the nanoSchottky contact between the conductive tip and the sample in passing mode. For this sample an optimum VDC was determined at -7 V applied to the sample. Using this optimum value of VDC, the recorded SSRM mapping is shown in Fig. 4.b. A measured resistance profile line is reported in the SSRM map. While resistance is homogeneous on the wide terraces of the macrosteps (location B), the electrical signal is noisier for the unreacted area (A). In addition, the average resistance looks higher in area A than in area B. The pixel histogram analysis of the measured resistances, reported in Fig. 4.d, for both areas confirms this trend. For the macrosteps (B), the mean resistance is log(R)=7.1Ω with a standard deviation of 0.2Ω, whereas for areas unreacted the distribution of resistances shows an average resistance about log(R)=7.4Ω with a standard deviation of 0.3Ω. Some pixels indicate resistances of up to log(R)=8.5Ω. Note that, since the SSRM mode is performed in contact mode and, due to the sharp geometry of the 4H−SiC(0001)4∘ off macrostepped surface, the systematic resistance increase at step riser can be attributed to the effective tip-sample contact, which becomes very weak at the extremity of the step. The SSRM measurements indicate that, when the probe is positioned on zone A, the current flow between the tip and the sample is significantly hindered. The measured resistance comprises the tip resistance (approximately 103Ω ) and the resistance of the back contact between the sample and the AFM chuck. For the entire scanned area, these two contributions remain constant; thus, any variation in the measured resistance reflects differences in the local electrical properties. To confirm these results, sMIM method is also used.

[picture]

Fig. 4. DC electrical conduction by AFM-SSRM, VDC=−7 V is applied to the sample: a) topography of the scanned surface 25μ m×25μ m,512×512 pixels, b) measured log(R) cartography by SSRM and c) pixel histograms of log(R) on the areas A and B.

Fig. 4. DC electrical conduction by AFM-SSRM, V D C = − 7 V is applied to the sample: a) topography of the scanned surface 25 μ m × 25 μ m , 512 × 512 pixels, b) measured log ( R ) cartography by SSRM and c) pixel histograms of log ( R ) on the areas A and B.

[picture]

Fig. 5. RF electrical conduction by AFM-sMIM, a) topography of the scanned surface 20μ m×20μm,512×512 pixels, b) measured sMIM-C cartography.

Fig. 5. RF electrical conduction by AFM-sMIM, a) topography of the scanned surface 20 μ m × 20 μ m , 512 × 512 pixels, b) measured sMIM-C cartography.

When sMIM mapping is performed on the 4H−SiC(0001) macrostepped surface, unreacted areas (A) and macrosteps (B) can be also identified (Fig. 5.a). Based on the interaction of the incident microwave signal with the surface and subsurface of the material, sMIM is sensitive to the RF conductivities of a nanoscale volume of material beneath the shielded tip. In Fig. 5.b, the sMIM-C signal (imaginary part of the complex impedance, measured after a calibration step) is related to the relative electrical capacitance of the material underneath the AFM nano-waveguide tip. sMIM results shows that the unreacted areas (A) are less conductive than the terraces of the macrosteps (B) which correlates well with the SSRM results.

Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

From the results obtained, a clear correlation between the local electrical conduction properties both in DC (SSRM) and in RF (sMIM) based on an AFM is demonstrated: unreacted areas present a higher and noisier local resistance than the macrosteps. As schematized in Fig 6, the main difference between unreacted areas and macrosteps is the density of step risers at the surface: it is much higher on unreacted areas. Then step risers can contains defects that negatively affect the electrical properties of 4H−SiC surface.

[picture]

Fig. 6. Cross sectional schematic view of the 4H−SiC(0001)4∘ off macrostepped sample surface showing after liquid Si melting i) an unreacted area (A) with a high density of step risers and ii) macrosteps (B) with ideally no step riser except at their extremity.

Fig. 6. Cross sectional schematic view of the 4 H − S i C ( 0001 ) 4 ∘ off macrostepped sample surface showing after liquid Si melting i) an unreacted area (A) with a high density of step risers and ii) macrosteps (B) with ideally no step riser except at their extremity.

Conclusion

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

Local electrical properties of a 4 H -Silicon Carbide SiC(0001) 4∘ off macrostepped surface, obtained by structuring using a SiC/Si/SiC sandwich with a liquid Si interlayer, are probed with two AFM based modes. The DC mode, SSRM, reveals that the local resistance of the unreacted areas is higher and noisier compared to the macrostepped areas. The RF mode, sMIM, confirms this trend with a lower conductivity for the unreacted area. These investigations demonstrate the correlation between surface morphology of the 4 H -Silicon Carbide SiC(0001)4∘ off macrostepped and electrical behavior, providing complementary insight into local transport mechanisms of the SiC at the nanoscale.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.33.pdf

P. Fiorenza et al., "Electron trapping at SiO2/4H−SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis," Nanotechnology, vol. 29, no. 39, p. 395702, Jul. 2018, doi: 10.1088/1361-6528/aad129.

J. Woerle et al., "Two-dimensional defect mapping of the interface," Phys. Rev. Mater., vol. 3, no. 8, p. 084602, Aug. 2019, doi: 10.1103/PhysRevMaterials.3.084602.

M. Camarda, J. Woerle, V. Souliere, G. Ferro, H. Sigg, U. Grossner, and J. Gobrecht, Analysis of 4HSiC MOS Capacitors on macro-stepped surfaces, Mater. Sci. Forum, 897, (2017), 107110, doi: 10.4028/www.scientific.net/MSF.897.107.

N. Alyabyeva et al., "Nanoscale Mapping of Sub-Gap Electroluminescence from StepBunched, Oxidized 4H-SiC Surfaces," physica status solidi (b), vol. 260, no. 5, p. 2200356, 2023, doi: 10.1002/pssb. 202200356.

Y. Jousseaume et al., "Controlled Macrostepping of Si-Face off over a Large Area via Liquid Si-Induced Reconstruction," Materials Science Forum, vol. 1089, pp. 9-14, 2023, doi: 10.4028/p-5p6o3j.

Y. Jousseaume, P. Kumar, M. E. Bathen, F. Cauwet, U. Grossner, and G. Ferro, "Surface Structuring of Patterned Surfaces Using a SiC/Si/SiC Sandwich Approach," Materials Science Forum, vol. 1124, pp. 7-12, 2024, doi: 10.4028/p-auZ0OI.

P. Fiorenza et al., "Complementary Two Dimensional Carrier Profiles of MOSFETs by Scanning Spreading Resistance Microscopy and Scanning Capacitance Microscopy," Solid State Phenomena, vol. 358, pp. 45-49, 2024, doi: 10.4028/p-9EfKbt.

R. C. Germanicus, T. Phulpin, K. Niskanen, A. Michez, and U. Lüders, "AFM-sMIM Characterization of the Recombination-Enhancing Buffer Layer for Bipolar Degradation Free SiC MOSFETs," Solid State Phenomena, vol. 361, pp. 85-91, 2024, doi: 10.4028/p-hUPMo0.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 39-44

doi: 10.4028/p-SZxKD4

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

N. Piluso 1,a*, C. Calabretta 1, b, F. Vento 1,c, R. Anzalone 1, d, C. Nania 1,e, D. Raciti 1,f, A. Rossitto 1, g, A. Lombardo 1, h, M. Coppola 1,i, A. Cannizzaro 1,j, A. Severino 1,k, G. Arena 1,l, M. M. Salamone 2, m, F. Giuffrida 2,n, L. Barbisan 2,o, P. Sharma 2,p, J. Per 2,q, M. K. Dayyala 2,r, P. Parisi 2, s

1 STMicroelectronics, Str. Primosole 50, 95121 Catania, ITALY

2 KLA Corporation, 1 Technology Dr, Milpitas, CA 95035, USA

a*nicolo.piluso@st.com, b cristiano.calabtretta01@st.com, c fabiana.vento@st.com, d ruggero.anzalone@st.com, e chiara.nania@st.com, f domenica.raciti@st.com, g antonio.rossitto@st.com, h alice.lombardo@st.com, i mario.coppola@st.com, jannalisa.cannizzaro@st.com, kandrea.severino@st.com,  'giuseppe-ctn.arena@st.com, m matteo.salamone@kla.com, n federico.giuffrida@kla.com, luca.barbisan@kla.com, p parikshit.sharma@kla.com, qj jeff.per@kla.com, r manojkumar.dayyala@kla.com, s  paolo.parisi@kla.com

Abstract

A new design approach for 4H−SiC material is ongoing to improve the electrical performance of devices. As seen in silicon devices, multi-epitaxial growth enhances performance by reducing on-resistance (Ron). However, devices built on SiC face several challenges due to very low dopant diffusion (e.g., phosphorus and aluminum) and defect evolution during epitaxial growth. Monitoring defects like prismatic faults, stacking faults, partial dislocations, and micropipes, especially after regrowth, is essential to assess their impact on device performance. Defects with a high killer ratio must be closely tracked to understand their evolution. In this work, we will show a method for early-stage process characterization and defect root-cause identification through sensitive inspections, effective reviews, and accurate defect classification to detect critical defects in 4H−SiC material when more than one epitaxial step is considered.

Keywords: 4H−SiC, defects, metrology, high power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

The global semiconductor market is expected to grow significantly. Considering the expansion to 8" wafer size and strong dedicated investments, the silicon carbide ( SiC ) power device market will reach $9 B by 2028 [1]. This growth is driven by rising demand for efficient power electronics in electric vehicles (EVs), renewable energy systems (smart grids), IT infrastructures (AI, data centers), and other applications, thanks to the significant benefits over traditional silicon-based semiconductors. To achieve market leadership, semiconductor companies must quickly transition to high-volume manufacturing (HVM) with Zero Defect standards [2], preventing productivity bottlenecks during fab ramp-up. Sensitive inspection, effective review, and reliable AI-based defect classification during R&D and maturity phases are critical solutions for early detection of process flaws and killer defects, determining yield and accelerating time to result (T2R).

Coupling high-quality 4H−SiC substrates with an efficient epitaxial growth process is a promising approach to enhance the performance of power electronic devices [3,4,5,6]. Optical microscopy is the most widely used method for detecting defects in this technology, and defects are classified based on size, shape, and intensity. Typical macroscopic defects on SiC material (Figure 1), easily detectable due to their size and contrast, are considered killers for devices. More challenging defects, especially those smaller than 1μ m, require advanced characterization techniques such as inline defect detection and AI-based classification.

In Table 1, defects of interest are reported along with their typical electrical behavior. Micropipes act as conductive paths, increasing leakage current and decreasing blocking voltage. The
characteristic hole that permeates the entire material, from the substrate to the epitaxy, causes a reduction in breakdown voltage and allows unexpected current to flow through the device during reverse bias. Typical hard failures are localized in active regions.

Threading Screw Dislocation (TSD) with pits generates inhomogeneities on the surface and on the gate oxide in MOSFET devices. They can cause a slight increase in leakage current and a local reduction in breakdown voltage. Additionally, oxide instability during electrical stress tests is detected. Such defects can expand under reverse bias stress, leading to hard failure of the device during standard operation.

Stacking Faults (SFs) are crystallographic defects without optical counterparts, detectable only by photoluminescence techniques. A recent and exhaustive classification is reported in [7]. Most SFs cause only a very slight increase in leakage current and are not directly connected with hard device failure. Nevertheless, if SF density exceeds a critical value, which strongly depends on the device considered, leakage current issues can become severe. In MOSFET devices, SF density should be kept below 0.5 cm−2. Additionally, Single Shockley SF ( 1 SSF ) can expand via ultraviolet irradiation [8] and/or current flow, potentially inducing bipolar degradation and hard device failure.

Morphological and extended defects are recognized as responsible for electrical hard failures. Due to their typical size and shape, they are easily detected with optical methods and screened during the Front-End process flow.

In Figure 2, the high-sensitivity inspection mode is shown, and the results reveal an improved capture rate of sub-micron defects while confirming the macroscopic defects normally tracked by standard process control solutions. Another key element is the ability to perform 100% defect sampling classification, allowing precise correlation between the results from the final electrical test and the defect typology. In Figure 3, DefectWise® high-purity and high-accuracy, fully integrated classification technology is presented.

[picture]

Fig. 1. Collection of morphological defects detected on SiC Epitaxial layer.

Fig. 1. Collection of morphological defects detected on SiC Epitaxial layer.

Table 1. SiC defects of interest.

Defect | Technique | Typical Size | Risk/Typical Failure
Micropipe | Optical microscope | ~1 μm | HIGH Electrical Destructive Failure
Threading Screw Dislocation (with superficial pit) | Scanning electron microscopy X-Ray Topography Optical Microscope + PL | < 1 μm | MID/LOW High Leakage Current and/or Oxide instability
Stacking Faults | Photoluminescence | > 1 μm | LOW High Leakage Current and/or Oxide instability
Morphological Extended Defects (Carrots, Triangles, Particles) | Optical microscope | >> 1 μm | HIGH Electrical Destructive Failure

[picture]

Fig. 2. Enhanced detection of sub −1μ m defects in next-generation PMOS devices utilizing KLA's Corp's 20x high-sensitivity inspection mode on the 8935 inspector.

Fig. 2. Enhanced detection of sub − 1 μ m defects in next-generation PMOS devices utilizing KLA's Corp's 20x high-sensitivity inspection mode on the 8935 inspector.

[picture]

Fig. 3. Example of classification of common defects in SiC by using KLA's AI-based solution (DefectWise ® ).

Fig. 3. Example of classification of common defects in SiC by using KLA's AI-based solution (DefectWise ® ).

Experimental

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

Multi-epitaxial growth is a strategy used to improve device performance, particularly in minimizing on-resistance (Ron) [9,10,11], thanks to superjunction-like drift layers. While this approach is common in silicon devices, SiC devices face challenges due to the low diffusion coefficients of dopants (e.g., phosphorus and aluminum) and the evolution of crystal defects during the multi-epitaxial process [12,13,14].

In Figure 4, a sketch of the epitaxial stack sent for inspection is shown. The first thick epitaxial layer, generally ranging from 5 to 10μ m, underwent ion implantation and was then epitaxially regrown with a thin layer ranging from 1 to 2μ m. Dedicated inspections were conducted to explore the interface quality between the epitaxial layers. The results (not presented here) showed a smooth interface free from defects generated by ion implantation.

[picture]

Fig. 4. Sketch of epitaxial stack underwent to highly sensitive mode inspection.

Fig. 4. Sketch of epitaxial stack underwent to highly sensitive mode inspection.

In Figure 5, the typical increase in defectivity, depicted here as Defect Die percentage within a 5×5 mm grid, is shown. This increase is mainly due to the expansion of defects already present on the surface of the first epitaxial layer, new defects caused by surface contamination, and, to a minimal extent, dislocations propagated along the first epitaxial layer (e.g., basal plane dislocations) that convert into extended defects during the second epitaxial layer step (typically stacking faults and carrots).

[picture]

Fig. 5. Typical Increasing of Defect Die percentage (average ~4% ) due to multi step epitaxial layer by considering three different substrate quality levels.

Fig. 5. Typical Increasing of Defect Die percentage (average ~ 4 % ) due to multi step epitaxial layer by considering three different substrate quality levels.

Figure 6 shows the evolution of defects from Epil to Epi2. To define the killer ratio (KR) of structured defects, it is necessary to detect and monitor defects after regrowth. Studies on prismatic defects and complex (carrots) stacking faults (Figure 6 A, C) provide insights into how defects propagate and the potential degradation of device performance. Additional partial dislocations after regrowth (Figure 6 B, D) must be detected, classified, and monitored to assess their impact on final electrical performance and process flow. Despite the limited size increase after the regrowth process, micropipes (Figure 6E,F ) are known to have a KR close to 100%, and their evolution is fundamental to identifying crystallographic changes and quantifying the portion of the surface impacted by their enlargement.

[picture]

Fig. 6. Evolution of defects from the epitaxial layer (A, C, E) to thin epitaxial regrowth (Fig. B, D, F). In detail: evolution of prismatic (A→B), complex Stacking Faults (C→D) and micropipe (E→F).

Fig. 6. Evolution of defects from the epitaxial layer (A, C, E) to thin epitaxial regrowth (Fig. B, D, F ) . In detail: evolution of prismatic ( A → B ) , complex Stacking Faults ( C → D ) and micropipe ( E → F ) .

The most relevant results were the efficient detection of submicron defects by optical means in highsensitivity mode, as shown in Figure 7. Among all the submicron defects detected, the Threading Screw Dislocation (TSD) stands out due to the importance of screening such defects. Literature works [15] confirm that pits or nano-pits on the epitaxial surface, caused by the propagation of dislocations such as TSD, negatively affect device performance.

Usually, high leakage current in diode devices corresponds exactly with the presence of pits. In the case of MOSFET devices, the failure is even more severe, resulting in gate oxide breakdown and device burnout.

[picture]

Fig. 7. Sub-micron defects detected by High Sensitivity mode inspection and related optical (Left) and SEM (right) review.

Fig. 7. Sub-micron defects detected by High Sensitivity mode inspection and related optical (Left) and SEM (right) review.

The KLA 8935 high-throughput, high-sensitivity, top-side inspection system is designed for 150300 mm bare and patterned wafers. It features a high-resolution, high-numerical-aperture optical microscope paired with an LED light source. A key capability of the system is its concurrent brightfield (BF) and darkfield (DF) inspection, which significantly expands its range of applicable use cases. The 8935 can be integrated with the DefectWise® deep-learning AI solution, enabling realtime 100% defect classification with high purity and accuracy.
The Micro-SR™ fully automated optical review system operates in synergy with the 8 Series inspection systems. It is designed for high-throughput, high-resolution, high-quality image acquisition of sub-micron defects, supporting efficient defect review and analysis.
The eDR7380™ electron-beam wafer defect review and classification system provides highresolution images of defects and uses a machine-learning automatic defect classifier to produce an accurate defect Pareto. The data generated by the eDR7380 enables faster defect sourcing in development, quicker excursion detection, and more accurate, actionable data during production. The defect information produced by the eDR7380 helps accelerate time to market for multiple bare substrate types (SiC, GaN, glass, sapphire, POI piezoelectric-on-insulator, etc.) and device types (power, LED, photonics, RF, MEMS, etc.). Built on a flexible, configurable platform, the eDR7380 reviews and classifies a wide range of defect sizes and types for multiple wafer sizes ( 150−300 mm ) and wafer thicknesses (180−1500μ m).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

A new multi-epitaxial stack has been presented, and each layer is fully characterized. The use of higher magnification (20x) inspection mode significantly enhances the detection of sub-micron defects, while AI-based classification improves the accuracy and consistency of defect identification. This strategy enables effective tracking of defect evolution throughout the process.
Improvement in defect detection is mandatory in multi-epi technology because new defects triggered by the second epitaxial layer step can exhibit atypical and challenging characteristics from a metrology point of view, mainly due to the very low thickness of the second grown layer, which leads to very small defect sizes. TSDs that do not generate pits on the surface of the first epitaxial layer can do so on the surface of the second epitaxial layer, with a relatively small size ( <1μ m ). SFs can be generated starting from BPDs that propagate through the first epitaxy up to the surface and appear very small in photoluminescence channels ( <10μ m ).

Correlation between electrical testing and defect mapping highlights the importance of identifying high-impact defects, such as micropipes, which exhibit a strong killer ratio. The combination of highresolution inspection, inline review, and precise classification supports the fine-tuning of nextgeneration power MOSFET development. Overall, this approach accelerates time-to-result while ensuring compliance with demanding industry standards.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.39.pdf

https://www.yolegroup.com/product/report/sic-transistor-comparison-2023/.

R. Raina et al., Achieving Zero-Defects for Automotive Applications, 2008 IEEE International Test Conference, (2008), doi: 10.1109/TEST.2008.5483611.

D. Raciti, R. Anzalone, M. Isacson, N. Piluso, A. Severino, Defect and Diffusion Forum, Vol 434, pp 117-121.

N. Piluso, et. al., IEEE International Reliability Physics Symposium (IRPS), pp 1-5 (2025).

N. Piluso et. al., Materials Science Forum, 963, pp 91-96 (2019).

T. Kimoto, H. Watanabe, Applied Physics Express 12, 120101 (2020).

M. Na. et al, Materials Science in Semiconductor Processing 175 (2024) 108247.

I. Yukari, et. al., Journal of Applied Physics 123(22):225101 (2018).

R. Ghandi et. al., Proceedings of the International Symposium on Power Semic. Devices & ICs, (2023).

C. Ma et al., Chao Ma et al 2024 J. Semicond. 45111301.

K. Ryoji et al., 31st International Symposium on Power Semiconductor Devices and ICs, ISPSD, IEEE, pp. 39-42, 2019.

RT. Leonard et al., Materials Science Forum, Trans Tech Publications Ltd, (2017).

C. Langpoklakpam et al., Crystals, Vol 12, n. 2, p. 245 (2022).

A. Severino et al., Materials Science Forum, 963, pp. 407-411 (2019).

T. Kimoto, Japanese Journal of Applied Physics 54, 040103 (2015).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 45-51

doi: 10.4028/p-xjp7QK

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-17

Accepted:
2026-02-23

Online:
2026-05-18

Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Zimo Yuan 1,a, Alex Metreveli 1, b, Lasse Vines 2,c, Orazio Samperi 2, d, Misagh Ghezellou 3,e, Jawad Ul-Hassan 3,f and Anders Hallén 1, g

1 KTH Royal Institute of Technology, SE 16440 Kista, Sweden

2 Centre for Material Science and Nanotechnologies, University of Oslo, 0373 Oslo, Norway

3 Department of Physics, Chemistry and Biology, Linköping University, SE 58183 Linköping, Sweden

a  willinf347@gmail.com, b  alexmet@kth.se, classe.vines@fys.uio.no, d  oraziosa@smn.uio.no, e  misagh.ghezellou@liu.se, jawad.ul-hassan@liu.se, g  ahallen@kth.se

Keywords: boron, deep levels, SRH recombination, thermodynamics.

Abstract

In this paper, the temperature dependence of charge carrier lifetimes in n-type 4H-SiC epitaxial layers is studied in a temperature range of 300−500 K. It is assumed that shallow (B) and deep (D) boron-related defects are the dominating lifetime killers in as-grown epitaxial layers. The thermodynamic behavior of these two types of defects is obtained from DLTS measurements, and implemented in the Shockley-Read-Hall (SRH) model to calculate lifetimes, using Gibbs free energies to describe the accurate temperature dependence for capture and emission processes of the defects. Calculation results show that the lifetimes controlled by shallow boron defects increase with increasing temperature, while D-defects give the opposite temperature dependence. The theoretical results are also compared to measured data from 10kV4H−SiC PiN-structures, showing that the temperature dependence of the effective lifetime can be changed by proton implantations, which gives rise to additional Z1/2 defects that have similar temperature effects on lifetimes as D-related defects.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Charge carrier lifetime is an important parameter for bipolar 4H−SiC devices, since it has a large impact on device losses and switching speed [1]. It was previously acknowledged that the point defects, especially the carbon vacancies ( Z1/2 centers), have a dominant effect on controlling lifetimes in 4H−SiC. Recent research, however, has found that the measured lifetimes are not proportional to the abundance of Z1/2 at low concentration levels, suggesting that other defects might affect the lifetimes [2]. Boron-related defects [3,4] in the lower half of the 4H−SiC bandgap have recently been suggested to control the carrier lifetimes at low Z1/2 levels from deep level transient spectroscopy (DLTS) analyses, namely the shallow (B) and deep boron (D), respectively. These defects originate from boron contamination incorporated during growth, and can sometimes have higher concentrations than Z1/2 [5].

One way to assess the lifetime is by calculations using the Shockley-Read-Hall (SRH) model, in which the bandgap energies, trap concentrations and capture rates of traps are obtained from DLTS measurements. This method also allows the temperature dependence of lifetimes to be determined, but it is also important to use the correct thermodynamic model for the capture and emission processes. This means that the Gibbs free energy, ΔG=ΔH−TΔS, should be used, where H is the enthalpy, T is the absolute temperature and S is the entropy relevant for the carrier transitions [6, 7]. The correct temperature dependence of the carrier lifetime is essential for device modelling, since the 4H−SiC devices operate within a wide temperature range. Although the lifetimes of 4H−SiC devices can be measured experimentally by, for instance, open voltage circuit decay (OCVD) and photoluminescence (PL), there is a need to derive the lifetimes from physical models based on the different recombination centers in the material.

In this work, we extend the SRH model to study the temperature dependence of lifetimes theoretically, assuming that the boron-related defects, the B- and D-defects, are the lifetime killers.

Thermodynamically based properties of these defects are collected from DLTS measurements [2,8], and are implemented into the SRH model. The results will also be compared to experimental forward IV data of 10 kV 4H-SiC PiN diodes, including also proton implanted devices adding high local concentration of carbon vacancies.

Models

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Based on statistics of carrier capture and emission from deep bandgap states, the SRH model is used to calculate the total, effective charge carrier lifetime, τ, summed up over γ different types of defects present in the material [9,10]:

τ−1=∑j=1γ(n0+p0+Δn)NTjcnjcpjcnj(n0+Δn+nj)+cpj(p0+Δn+pj)(1)

where n0 and p0 are carrier concentrations at thermal equilibrium, Δn is the excess carrier concentration (assuming charge neutrality, Δn=Δp ) and NTj is the concentration of the jth  type of defect.

Capture coefficients cn and cp can be calculated using the thermal velocity v and capture cross section σ for electrons and holes, respectively:

cn,p=σn,pvn,p(2)

where the thermal velocities are obtained from the absolute temperature T and the effective masses mn* and mp*. The Boltzmann constant is designated by k :

vn,p=3kTmn,p*(3)

Concentrations nj and pj represent the carrier concentrations when the Fermi level is aligned with the energy position of corresponding defects, calculated with Eq. 4 and Eq. 5.

nj=NCexp(−EC−ETjkT)pj=NVexp(−ETj−EVkT)

(4)(5)

where NC and NV are the effective density of states in the conduction band and valence band, and are both temperature dependent. It should also be noted nj and pj are now calculated with the traps bandgap positions given by the Gibbs free energies in order to describe the proper thermodynamic behavior of electronic transitions from trap to band edges defects [6,7]. The Gibbs free energy G includes both the enthalpy H and entropy S of the electronic transitions and is given by Eq. (6).

ΔG=ΔH−TΔS(6)

Concentrations nj and pj are therefore stated as:

nj=NCexp(−HC−HTjkT)exp(SC−STjk)pj=NVexp(−HTj−HVkT)exp(STj−SVk)

(7)(8)

DLTS measurements offer the possibility to obtain defect parameters that can be implemented into the SRH model to calculate temperature-dependent lifetimes. Following Peaker et al. [11], the activation energy Ea and the apparent capture cross section, σa, can be extracted and, through capture
rate measurements, the capture energy barrier Eσ and the true capture cross section σ∞ can also be obtained.

The enthalpy for the given defect ΔH is calculated by:

ΔH=Ea−Eσ(9)

The entropy ΔS is calculated by:

ΔS=klog(σaσ∞)(10)

Concentrations nj and pj calculated with Gibbs free energies are thus available using Eq. (6), Eq. (9) and Eq. (10).

Results and Discussion

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Figure 1 gives a simplified band diagram of 4H−SiC, with the energy positions of three significant traps that are active in the control of charge carrier lifetimes. The double acceptor trap, Z1/2, which has been proved to originate from carbon vacancies, is located about 0.67 eV [13] below the bottom of the conduction band. Two boron-related minority traps, shallow B and deep D -center, are closer to the valence band. It has been found that shallow boron, B , and the deep boron, D -center, are assigned to boron impurities occupying the silicon site and carbon site in the SiC lattice, respectively, which leads to completely different energy levels and thermodynamic properties. It should also be noted that associated DLTS peaks ( B1, B2,D1 and D2 ) from hexagonal and cubic sites [8,13] are both observed for these two traps, and they will be merged in this work. The energy positions of shallow B and D-centers summarized from the literature are also given in Fig. 1. Table 1 summarizes the recent measured trap parameters [8] that will be used in this work. Since the 4H−SiC lattice contains both hexagonal and cubic sites with slightly varying bandgap positions, and the two versions of the shallow boron, we have used the dominating level in these calculations. In this work, we mainly discuss B- and D-related defects, which correspond to the first and second type of defects in Eq. (1).

[picture]

Fig. 1. Three energy levels that are expected to compete for the control of the charge carrier lifetime in low doped 4H−SiC : the majority trap Z1/2 and the minority traps shallow B and D -centers. The energy positions of the dominating levels are given in the figure (not in scale).

Fig. 1. Three energy levels that are expected to compete for the control of the charge carrier lifetime in low doped 4 H − S i C : the majority trap Z 1 / 2 and the minority traps shallow B and D -centers. The energy positions of the dominating levels are given in the figure (not in scale).

Table 1. Thermodynamic parameters of shallow B and D-center.

Trap | Ea (eV) | Eσ (eV) | σa (cm²) | σ∞ (cm²)
B | 0.27 | 0.10 | 2.2×10⁻¹⁴ | 1.87×10⁻¹⁴
D | 0.57 | 0.05 | 3.93×10⁻¹⁴ | 1.04×10⁻¹⁶

A 10kV4H−SiC PiN diode is used as an example to study the lifetimes in the drift region. The diode has a 120μ m thick drift layer, with a doping concentration of 2×1014 cm−3. The SRH lifetimes for shallow B and D-center are computed under high and low injection, with an excess carrier concentration of 3×1016 and 1×1012 cm−3, respectively. The temperature range is from 298 to 498 K ,
covering a substantial part of the operation range of 4H−SiC devices. It should be noted that only the hole capture process of the minority traps has been measured, giving the hole capture cross section σp(σp=σa), enthalpy HTj−HV, and entropy STj−SV that can be used to calculate concentration pj, seen in Eq. (8). The electron transport to these defects has not been measured, and therefore we set σn=σp to estimate the electron cross section. The Gibbs free energy term in Eq. (7), GC−GTj, is assumed to be (GTj−GV)·(EC−ET)/(ET−EV). These assumptions do not affect the calculations, since the concentration nj for both B- and D-related defects are negligible within the previously mentioned temperature range.

To start with, we analyze the shallow B level. The term n1 is negligible due to large GC−GT1. The term p1 gives a concentration within the range of 1017 cm−3, far more than both Δn and n0. The approximate high-injection and low-injection SRH lifetime from shallow B, with concentration NT1, are therefore given by Eq. (11) and Eq. (12).

τB( high )≈1NT1cn1+cp1(1+p1Δn)cn1cp1τB( low )≈1n0NT1p1cn1

(11)(12)

Similarly, for the D-center as the second kind of defects with concentration NT2. With the parameters in Table 1, the term p2 is now about 10−20% of n0, meaning that p2 can also be neglected under a high injection. The corresponding approximate high-injection and low-injection lifetimes are given by Eq. (13) and Eq. (14).

τD( high )≈1NT2(1cn2+1cp2)τD( low )≈1n0NT2cn2n0+cp2p2cn2cp2

(13)(14)

Note that all the approximate lifetimes from Eq. (11) to Eq. (14) are separated to two terms, one constant term (including n0 and defect concentrations) and one temperature-dependent term. Figure 2 compares only the temperature-dependent terms for the shallow B and D-center. It can be seen that both the high-injection and low-injection term for shallow B are increasing with temperature, indicating that a higher temperature always increases the shallow B-related SRH lifetime, regardless of the injection level. Meanwhile, an opposite trend can be found for D-center.

[picture]

Fig. 2. The temperature dependent part of the SRH lifetimes of shallow B and D-center, at highinjection ( Δn=3×1016 cm−3 ) and low-injection ( Δn=1×1012 cm−3 ). (Note that the actual lifetime is not plotted, but just the temperature dependent part of equations 11-14, which also leads to different units for high and low injection levels.) Shallow B and D-center related defects have an opposite temperature dependence.

Fig. 2. The temperature dependent part of the SRH lifetimes of shallow B and D-center, at highinjection ( Δ n = 3 × 10 16 c m − 3 ) and low-injection ( Δ n = 1 × 10 12 c m − 3 ). (Note that the actual lifetime is not plotted, but just the temperature dependent part of equations 11-14, which also leads to different units for high and low injection levels.) Shallow B and D-center related defects have an opposite temperature dependence.

The effective SRH lifetime can now be calculated from Eq. (1). The temperature dependence of the effective lifetime is therefore strongly dependent on which type of trap dominates, i.e. the ratio of concentrations NT1 and NT2. Figure 3 shows the calculated high-injection effective lifetimes with different NT1/NT2, where NT2 is always set to a constant value ( 3×1012 cm−3 ). The concentration of Bdefects, NT1, has to be at least three times NT2 to counteract the temperature dependence of the Dcenter. A special trend is also observed when NT1 is equal to, or slightly higher than NT2, that the effective lifetime first increases and then decreases. The temperature when this happens is between 400 and 500 K .

[picture]

Fig. 3. Calculated effective SRH lifetimes with different concentrations of shallow B-related defects (NT1). The excess carrier concentration is 3×1016 cm−3. The effective lifetime decreases with increasing temperature when the D-defects have a higher concentration ( NT2 ) and increases with increasing temperature if B-defects dominate. When the ratio NT1/NT2 is between 1 and 2 (dotted lines), the effective lifetime will first increase and then slightly decrease as temperature increases.

Fig. 3. Calculated effective SRH lifetimes with different concentrations of shallow B-related defects ( N T 1 ) . The excess carrier concentration is 3 × 10 16 c m − 3 . The effective lifetime decreases with increasing temperature when the D-defects have a higher concentration ( N T 2 ) and increases with increasing temperature if B-defects dominate. When the ratio N T 1 / N T 2 is between 1 and 2 (dotted lines), the effective lifetime will first increase and then slightly decrease as temperature increases.

Figure 4 shows the lifetime as a function of injection level with the temperature as a parameter. The concentration of the B-defects is much higher ( 6.7 times) than D-defects, and the same trend described previously can be found when the injection level is higher than 1×1016 cm−3. On the lowinjection level side, the effective lifetime decreases from 298 to 398 K , and then increases. It can also be found that the low-injection effective lifetime is much higher than high-injection lifetime above 473 K , which is due to the large values of pj. From fitting measured forward bias IV characteristics with TCAD simulations, it is possible to estimate the change in lifetimes with temperature. The forward IV characteristics of 10 kV PiN diodes [14] used in this work are measured from 298 to 373 K , with a temperature step of 25 K . The diode is also modelled in Sentaurus TCAD.

Figure 5a shows the measured forward IV characteristics (solid lines) of a typical 10 kV diode. The characteristics are shifting to lower voltages, indicating an increase in lifetime with increasing temperature. This is partly due to a reduction of the bandgap at higher temperatures, but the charge carrier lifetimes are also adjusted in the simulations to fit the measured data (dotted lines). For this diode, the drift layer high-injection level lifetimes (the sum of the majority and minority lifetime) used in the simulations are 2.2,2.6,3 and 3.5μ s, corresponding to 298,323,348 and 373 K . This indicates that B -defect might be the dominant defect in the diode sample.

Figure 5b compares the measured IV characteristics of three samples, two of which have been irradiated with 2.5 MeV protons (dose: 1×109 and 1×1010 cm−2 ) to introduce the intrinsic defect Z1/2 in the drift layer with a local peak concentration around 40μ m into the drift layer.

[picture]

Fig. 4. Calculated effective SRH lifetimes with different temperatures and injection levels. The concentration of B- and D-defects are 2×1013 and 3×1012 cm−3, respectively. The low-injection effective lifetime rapidly increases when the temperature is over 448 K due to the rapid increase of p1/2.

Fig. 4. Calculated effective SRH lifetimes with different temperatures and injection levels. The concentration of B- and D-defects are 2 × 10 13 and 3 × 10 12 c m − 3 , respectively. The low-injection effective lifetime rapidly increases when the temperature is over 448 K due to the rapid increase of p 1 / 2 .

A similar trend of lifetimes as in Fig. 5a is found for the diode irradiated with lower dose, while increasing temperature does not seem to affect lifetimes very much for the sample irradiated with higher dose. A possible explanation for such different temperature effects is the compensation effect of majority traps Z1/2 introduced by proton implantation. The activation energy of Z1/2 is larger than that of D -center, yielding a similar temperature dependence as the D -center. Proton implantations create a considerable amount of Z1/2-related defects, and thus compensate the temperature effects from B-defects.

[picture]

Fig. 5. (a) Measured and simulated forward IV characteristics of the tested diode from 298 to 373 K . The simulations are used to estimate the lifetimes from the measured characteristics. Experimental results show that increasing temperature increases lifetimes. (b) The measured IV characteristics of diode samples with and without proton implantation (2.5MeV,1×109 and 1×1010cm−2 ), giving a strongly non-uniform distribution of defects in the drift layer with a Z1/2 peak concentration of 1×1014 cm−3[1]. The temperature effects are weaker for the samples treated with proton implantation, possibly due to local compensation of Z1/2.

Fig. 5. (a) Measured and simulated forward IV characteristics of the tested diode from 298 to 373 K . The simulations are used to estimate the lifetimes from the measured characteristics. Experimental results show that increasing temperature increases lifetimes. (b) The measured IV characteristics of diode samples with and without proton implantation ( 2.5 M e V , 1 × 10 9 and 1 × 10 10 c m − 2 ), giving a strongly non-uniform distribution of defects in the drift layer with a Z 1 / 2 peak concentration of 1 × 10 14 c m − 3 [ 1 ] . The temperature effects are weaker for the samples treated with proton implantation, possibly due to local compensation of Z 1 / 2 .

Conclusion

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In this work, we have tried to analyze the temperature dependence of charge carrier lifetimes in a lightly-doped n -type 4H−SiC epitaxial layer. It has been assumed that boron-related defects, i.e. shallow B and D -centers, are dominating the lifetimes rather than the Z1/2 centers in as-grown epilayers. The parameters of B- and D-related defects are obtained from recent DLTS measurements, and thermodynamic properties are implemented to the SRH model to calculate accurate lifetimes. The calculations show that the temperature dependence of lifetimes controlled by B- and D-related defects are opposite, and the temperature dependence of the total effective lifetime is determined by the defects with a dominant concentration. The results are also compared to measured IV characteristics of devices with varying content of Z1/2, and these measurements indicate that MeV proton implantation can counteract the intrinsic temperature dependence of lifetimes in the epitaxial layer by introducing a considerable amount of Z1/2 defects.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.45.pdf

Z. Yuan, et al. "Localized lifetime control of 10kV4H−SiC PiN diodes by MeV proton implantation." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

M. Ghezellou, et al. "The role of boron related defects in limiting charge carrier lifetime in 4HSiC epitaxial layers." APL Materials 11.3 (2023).

T. Knezevic, et al. "Boron-Related Defects in N-Type 4H-SiC Schottky Barrier Diodes." Materials 16.9 (2023): 3347.

V. J. B. Torres, I. Capan, and J. Coutinho. "Theory of shallow and deep boron defects in 4 HSiC." Physical Review B 106.22 (2022): 224112.

M. E. Bathen, et al. "Impact of carbon injection in 4H-SiC on defect formation and minority carrier lifetime." Materials Science in Semiconductor Processing 176 (2024): 108316.

O. Engström and A. Alm. "Thermodynamical analysis of optimal recombination centers in thyristors." Solid-State Electronics 21.11-12 (1978): 1571-1576.

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O. Samperi, L. Vines, A. Hallén and M. E. Fragalà, "Charge carrier capture by prominent defect centers in ." Diffusion and Defect Data, Solid State Data. Part A, Defect and Diffusion Forum, ISSN 1012-0386, E-ISSN 1662-9507, Vol. 434, s. 173-182 (2024).

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A.R. Peaker, V.P. Markevich, J. Coutinho, "Tutorial: Junction spectroscopy techniques and deep level defects in semiconductors", J. Appl. Phys. 123, 161559 (2018).

N.T. Son, X.T. Trinh, L.S. Lövlie, B.G. Svensson, K. Kawahara, J. Suda, T. Umeda, J. Isoya, T. Makino, T. Oshima, and E. Janzén, „Negative-U System of Carbon Vacancy in 4H-SiC“, Phys. Rev. Lett. 109, 187603 (2012).

M. E. Bathen, et al. "Dual configuration of shallow acceptor levels in 4H-SiC." Materials Science in Semiconductor Processing 177 (2024): 08360.

K. Tian, J. Xia, K. Elgammal, A. Schöner, W. Kaplan, R. Karhu, J. Ul-Hassan, A. Hallén", Modelling the static on-state current voltage characteristics for a PiN diode", Materials Science in Semiconductor Processing 115 (2020): 105097.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 53-57

doi: 10.4028/p-HPx5qU

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2026-01-13

Accepted:
2026-02-23

Online:
2026-05-18

Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

Li Sun 1,2,a Xuejian Xie 1,2, b*, Xiufang Chen 1,2,c*, Xianglong Yang 1,2, d, Yan Peng 1,2,e, Xiaobo Hu 1,2,f*, Xiangang Xu 1,2, g

1 State Key Lab of Crystal Materials, Shandong University, Jinan, 250100, PR China

2 Institute of Novel Semiconductors, Shandong University, Jinan, 250100, PR China

a sdusunli@sdu.edu.cn, b xiexj@sdu.edu.cn, c cxf@sdu.edu.cn, d yangx|2016@sdu.edu.cn, e pengyan@sdu.edu.cn, f xbhu@sdu.edu.cn, g xxu@sdu.edu.cn

Keywords: Micropipe, X-ray topography, defect characterization, SiC.

Abstract

Micropipe defects in silicon carbide (SiC) materials significantly degrade the performance of SiC materials and their applications in semiconductor devices. In this study, systematic methods were utilized to characterize different micropipes in 4H−SiC. X-ray topography was employed to investigate the morphology of micropipe defects in SiC substrates and quantify their associated lattice distortion fields. Meanwhile, white light interferometry mode microscopy and inner stain were utilized to thoroughly characterize their properties. It was found that micropipes were accompanied with different size and distortion areas in SiC substrate. This work will be served as a refined characterization of micropipes and give guidance for device application for SiC substrate.

Introduction

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Silicon carbide ( SiC ) has shown revolutionary potential in the field of power semiconductor devices due to its excellent properties. Micropipe defects in SiC materials are hollow tubular line defects formed during crystal growth, typically extending along the <0001> crystal growth direction. These defects significantly degrade the performance of SiC materials and their applications in semiconductor devices, leading to detrimental effects such as reduced breakdown voltage, increased leakage current, and diminished carrier mobility. [1-4] Consequently, controlling micropipe defects is critically important during the preparation of large-diameter SiC single crystals.
The influence of micropipe area in SiC crystals on device performance is comprehensive, Large-area micropipes significantly exacerbate device failure risks, particularly in high-voltage, hightemperature, and high-frequency applications. With the gradual optimization of the growth process, the current micropipe density has been greatly reduced, and the characterization of micropipes is facing the requirement of more refinement. Current characterization methods for micropipes primarily rely on various microscopy techniques: polarized transmission microscope reveals stress variations induced by micropipes, while white-light interferometry precisely identifies their hollow core positions.
In this paper, the micropipe was characterized by orthogonal polarizing microscope, white light interference microscope, X-ray topography and inner stress meter. On the premise of accurately obtaining the position of micropipe, the influence of micropipe on the distortion range of crystal was studied synchronously, which will be of great significance to further improve the quality of SiC single crystal.

Materials and Methods

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Sample fabrication: The samples were homemade 4H−SiC single crystal with an off-axis of 4∘, which were grown by physical vapor transfer method. The growth temperature was set at about 2000∘C~2200∘C, and nitrogen gas was introduced during the growth process to obtain nitrogen doped boule. The samples all went through chemical mechanical polish (CMP) processing to remove surface scratches and other processing defects.

Characterization: For X ray topography characterization, the images were taken by reflection geometry was performed on the Cu target (λ=1.54\AA) using diffraction vectors g→=0008, using the 1.2 kWCu/ Mo rotating anode target XRT system provided by Rigaku. White light interference images were taken by microscope fabricated by Sensofar. For inner strain, SV200 wafer stress detector was used by birefringence effect of polarized light.

Results and Discussion

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Fig. 1 presented an image of micropipes acquired using an orthogonal polarization microscope by transmission mode. The dark regions corresponded to areas free of micropipes on the substrate surface, while the bright areas arised from alterations in the optical path induced by the presence of micropipes. Fig. 1a and 1b depicted regions containing a single micropipe and double micropipes, respectively. Comparative analysis clearly reveals distinct imaging characteristics between these two configurations. In the single micropipe region, the micropipe exhibits an image with cubic symmetry, consisting of three bright and three dark zones arranged symmetrically around the micropipe center. In contrast, within the double micropipe region, the micropipe images displayed significant distortion due to mutual interaction. This observation indicated the presence of interaction between adjacent micropipes, leading to synchronous modification of the lattice distortion regions associated with their existence.

[picture]

Fig. 1. Comparison single micropipe and double micropipes in polarizing microscope.

Fig. 1. Comparison single micropipe and double micropipes in polarizing microscope.

X-ray topography (XRT) is an important means to characterize lattice defects, which can effectively characterize the influence range of defects on perfect lattice.[5-6] The Burgers vectors of micropipes (MPs) are expressed as b→MP=±nc(n=3~10), whereas those of threading screw dislocations (TSDs) in SiC substrates are b→TSD =±mc(m=1,2).[7] When identifying MPs in SiC substrate using XRT systems, both MPs and TSDs coexist. The distinction between MPs and TSDs in XRT imaging arised from the inequality ||b→MP|>|b→TSD|. Fig. 2 demonstrated the contrast between MPs and TSDs in SiC substrates under g→=0008 diffraction condition. The small black dots were TSD defects, the white hollow and relatively large black dots represented micropipes, and the white area in the middle was the atomic depletion area formed by the presence of micropipes, because it cannot be imaged in XRT. Fig. 2b showed the XRT image of the double micropipe position. Typically, the double micropipe was generally formed by micropipes with different spiral properties. Located at the upper and lower ends, the two MPs interacted and gave rise to an extensive distorted area in the center that cannot be imaged by XRT, corresponding to a region where the 4 H -SiC crystal structure was disrupted. Taking dark regions in XRT images as strain-affected areas, single and double micropipe were measured as 0.44 mm2 and 1.2 mm2, respectively.

[picture]

Fig. 2. Comparison single micropipe and double micropipes in XRT.

Fig. 2. Comparison single micropipe and double micropipes in XRT.

The white light interference mode of microscope is an effective means for micropipe recognition. The white light interference mode can effectively avoid the influence of the strain factory caused by the orthogonal polarization mode of transmission mode, and more directly reflect the intrinsic characteristics of micropipe. As illustrated in Fig. 3, micropipes exhibited diverse morphologies including elliptical and irregular configurations. By extracting major and minor axis dimensions from these morphological profiles, the corresponding micropipe areas were calculated, with results summarized in Table 1. The measurement range of micropipe dimensions in white light interference mode of microscope predominantly was within 5−10μ m. A synchronous statistical analysis of identical micropipes through XRT revealed that the central white spot areas corresponding to micropipes consistently approximate 10μ m. This comparative analysis demonstrates the feasibility of utilizing XRT as a direct characterization method for quantifying micropipe areas.

[picture]

Fig. 3. Micropipe image from White Light Interference Microscope.

Fig. 3. Micropipe image from White Light Interference Microscope.

Table 1. Comparison of micropipes size between White Light Interference Microscope and XRT.

Length/um |  | MP-1 | MP-2 | MP-3
Microscope | Major axes | 5.9389 | 11.0103 | 4.3960
Minor axes | 3.7758 | 11.5643 | 2.6325
XRT | Major axes | 18.4937 | 13.2033 | 18.2416
Minor axes | 10.6501 | 12.3507 | 17.2380

The distribution of micropipes in the same wafer was characterized by XRT and polarizing microscope. Fig.4a showed the XRT imaging of the 8-inch wafer. By adjusting the contrast, the distribution of micropipes in the picture can be clearly seen, as shown in the red box. It should be noted that there was a large bright color area in the lower right corner of the wafer, but according to the micropipe characteristics mentioned above, it can be determined that this position was not a micropipe, but should correspond to the rest of the defects, probably multi type defects. Similarly, in Fig. 4b obtained from transmission microscope , micropipe images appeared at the same position as in Fig. 4a. Comparatively, defects in the lower right corner was recognized as micropipes, which also proved that XRT was the most effective way to identify micropipes.

[picture]

Fig. 4. Micropipe distribution on whole wafer, (a)XRT and (b) transmission microscope.

Fig. 4. Micropipe distribution on whole wafer, (a)XRT and (b) transmission microscope.

To investigate the influence of micropipes on the overall stress distribution within the crystal, the wafer stress was mapped using an internal stress meter. Fig. 5a presented the resulting stress map, where the color intensity corresponded to the stress magnitude: darker shades indicate lower stress, while brighter regions signified higher stress. By comparing this stress map with the XRT image in Fig. 4a, it was evident that locations containing micropipes consistently exhibited significantly elevated stress levels.

[picture]

Fig. 5. Inner strain distribution on whole wafer.

Fig. 5. Inner strain distribution on whole wafer.

Summary

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In conclusion, this study presented a systematic investigation of micropipe defects in SiC crystals. By correlating XRT with white light interferometry, we directly revealed the lattice distortion caused by micropipes and demonstrate that the degree of distortion was correlated with the micropipe size. Consequently, the impact of micropipes on the crystal lattice varied significantly with their dimensions. In the characterization of the quality of SiC substrate, the size of micropipes also need to be considered apart from the distribution position of micropipes.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.53.pdf

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Fujie, F. et al. Synchrotron X-ray topographic image contrast variation of screw-type basal plane dislocations located at different depths below the crystal surface in . Acta Materialia 208(2021):116746.

Cheng, Q. et al. Analysis of dislocation configurations in SiC crystals through X-ray topography aided by ray tracing simulations. Materials Science in Semiconductor Processing 174(2024):108207.

Li, Jiajun, et al. Dislocations in 4H silicon carbide. Journal of Physics D: Applied Physics 55.46 (2022): 463001.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 59-64

doi: 10.4028/p-h1jN4u

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-19

Accepted:
2026-02-23

Online:
2026-05-18

High Quality P-Type 4H-SiC Growth by PVT Method

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

Shanshan Hu 1,a*, Haochi Wang 1, b, Zeyu Chen 1,c, Kaixuan Zhang 1, d, Yuzhuo Li1,e, Jianpei Zhang 1,f, Balaji Raghothamachar 1, g, Michael Dudley 1, h, Douglas Dukes 2,i and Victor Torres 2,j

1 Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794, USA

2 Pallidus, Inc., Albany, NY 12203, USA

a* shanshan.hu@stonybrook.com, b  haochi.wang@stonybrook.edu, c  zeyu.chen@stonybrook.edu, d  kaixuan.zhang@stonybrook.edu, e  yuzhuo.li@stonybrook.edu, f  jianpei.zhang@stonybrook.edu, 9balaji.raghothamachar@stonybrook.edu, h  michael.dudley@stonybrook.edu, i  douglas.dukes@pallidus.com, j  victor.torres@pallidus.com

Abstract

The fabrication of n -channel IGBTs is constrained by the low conductivity as well as poor quality of the p-type SiC substrate. This paper reports a 6-inch high quality p-type 4H−SiC wafer achieved by PVT method. The wafer was examined by synchrotron X-ray topography indicating average defect densities are on par or better than commercial 6-inch n-type wafers. Large areas of the wafer, especially the middle region of the wafer is characterized by very low density of BPDs. The extent of prismatic slip due to radial thermal gradients is also vastly reduced compared to typical ntype wafers.

Keywords: 4H−SiC,p-type, PVT growth.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

With outstanding electronic properties such as high breakdown field strength, high operating temperatures, high thermal conductivity, and high carrier saturation drift velocity, silicon carbide (SiC) is becoming the choice for fabrication of high-power electronic devices. Various device types such as diodes (JBS, SBD, PiN) and transistors (MOSFET, JFET, IGBT) have been developed chiefly on n -doped substrates. Among these, the SiC insulated gate bipolar transistors (IGBTs) have demonstrated great performance advantages and application prospects as high-voltage switches. Especially, n-channel IGBTs show superior performance than p-channel IGBTs due to higher mobility of electrons than holes but fabrication is preferable on p-doped substrates.

However, the fabrication of n -channel IGBTs is constrained by the low conductivity as well as poor quality of the p-type SiC substrate [1], which is essential for their device performance. Usually, p-type SiC is manufactured using an aluminum (Al)-containing compound placed in the SiC powder region as dopant. Since the vapor pressure of Al is significantly higher than that of the SiC gas species during crystal growth, the Al source is released excessively in the early stage of crystal growth and gets depleted for the later growth stage. As a result, it is hard to achieve stable and continuous p-type doping. In addition, the high concentration of Al at the seed/newly grown crystal interface affects the crystallization quality and leads to large defect nucleation. So far, Suo et al. [2] achieved 3-inch NAl co-doped p-type SiC crystals with regions having BPD etch pit density of 300 cm−2. 4-inch p-type 4H−SiC is obtained by Wang et al. [3] with dislocation etching pit density of 888.89 cm−2. Compared to actual BPD densities (total line length per unit volume), BPD etch pit densities (number per unit area) can be undercounted by a factor of 14 or greater for 4∘ offcut wafers[4]. Nevertheless, significant improvement in quality of p-type SiC wafers and further lowering of defect densities is necessary for development of devices such as n-channel IGBTs.

Synchrotron X-ray topography (XRT) is a powerful characterization technique widely applied in the semiconductor industry[5,6]. High-resolution images of the internal structure of a crystal can be generated through X-rays generated by a synchrotron radiation source non-destructively. Both synchrotron white beam X-ray topography (SWBXT) and synchrotron monochromatic beam X-ray
topography (SMBXT) are employed to obtain crystallographic defects and structural features. Transmission geometry and grazing incidence geometry are employed in SWBXT and SMBXT, respectively. Transmission geometry can expose the overall defect distribution, capturing defects throughout the crystal volume. Grazing incident geometry employs a very small incident angle (~2∘) and penetrates the sample only to a shallow depth below the surface.

In this study, 6-inch high quality p-type 4H-SiC wafers are achieved by PVT method. The wafers were examined by SWBXT in transmission geometries and SMBXT in grazing incidence geometries to map the defect content and distribution.

Experimental

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

4∘ off-axis 150 mm PVT-grown 4H-SiC commercial wafers were imaged by synchrotron white beam X-ray topography (SWBXT) in transmission geometry at beamline 27-ID (HEX), National Synchrotron Light Source II at Brookhaven National Laboratory. Synchrotron monochromatic X-ray topography (SMBXT) in grazing incidence geometry images for samples was obtained at beamline 1-BM, Advanced Photon Source at Argonne National Laboratory. The energy of ~9.1KeV is used for SMBXT. As shown in Fig .1, X-ray beam enters one surface of the sample and exits from another surface in transmission geometry while X-ray incidences and exits sample from the same surface with an incident angle of ~2∘ in grazing incidence geometry. Images were recorded on the Agfa Structurix D3-SC films with resolution of ~1μ m for both geometries.

[picture]

Fig. 1. Diagrams showing (a) transmission geometry, and (b) grazing incidence geometry for X-ray topography.

Fig. 1. Diagrams showing (a) transmission geometry, and (b) grazing incidence geometry for X-ray topography.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

As shown in Fig. 2, the optical image of the high-quality p-type wafer exhibits a uniform blue color. Although such uniform coloration cannot be regarded as definitive proof of doping uniformity, it does qualitatively suggest a consistent distribution of aluminum dopants. Si face of the wafer is placed up. Facet is observed on the right side of the wafer with a darker blue color as marked by red arrows.

[picture]

Fig. 2. Optical image of a high quality p-type wafer showing uniform blue color across the whole wafer. Facet is observed on the right side of the wafer and marked by red arrows.

Fig. 2. Optical image of a high quality p-type wafer showing uniform blue color across the whole wafer. Facet is observed on the right side of the wafer and marked by red arrows.

The high quality p -type wafer is calculated to have average basal plane dislocation (BPD) density of ~2.2*104 cm−2, threading screw dislocation (TSD) density of ~1331 cm−2, and threading edge dislocation (TED) density of ~2163 cm−2. Fig. 3 illustrates the procedure used to determine the dislocation densities across the entire wafer. As schematically shown by Fig. 3(a), 9 regions that are evenly distributed across the wafer are selected for density measurement. In each region, a grazing incidence image with 112―8 reflection as shown by Fig. 3(b) with size of 2.34 mm×1.75 mm is acquired. The dislocation densities calculated from these images are then averaged to represent the overall density of the wafer. As marked by Fig. 3(b), in grazing incidence images, BPDs show linear white and black contrast, TSDs show large circular white contrast, and TEDs show small circular white or black contrast. The TSDs/TEDs number and total length of BPDs in each image can be manually counted. The densities of TSDs and TEDs are determined by dividing the total number of observed TSDs/TEDs by the image area ( 2.34 mm×1.75 mm ) while the density of BPDs is calculated by measuring the total length of BPD and normalizing by the imaged volume. Since the penetration depth of X-rays for grazing incidence geometry with 112―8 reflection is ~17μ m. The volume where the BPDs are imaged is 2.34 mm×1.75 mm×17μ m.

[picture]

Fig. 3. (a) Schematic showing evenly distributed 9 regions across the wafer selected for dislocation density calculation. (b) Representative SMBXT grazing incidence image with 112―8 reflection acquired in each of the 9 regions for dislocation density evaluation.

Fig. 3. (a) Schematic showing evenly distributed 9 regions across the wafer selected for dislocation density calculation. (b) Representative SMBXT grazing incidence image with 11 2 ― 8 reflection acquired in each of the 9 regions for dislocation density evaluation.

In SWBXT transmission image, the low BPD density regions show whiter contrast compared to those with high BPD density regions. As marked by Fig. 4(a) in SWBXT transmission image for the whole p-type wafer, the middle ~12.6 cm diameter region is characterized by very low density of BPDs. Fig. 4(b)-4(d) shows the grazing incidence images that are obtained in the regions marked by box 1,2,3 in Fig. 4(a). The white horizontal linear contrasts in Fig. 4(b)-(d) are artifacts that are induced due to phase contrast effects from the beryllium window which serves as a vacuum barrier for the storage ring while permitting X-rays to pass into the beamline with minimal absorption. As indicated in Fig. 4(b), in addition to BPDs, TSDs, and TEDs, TSD pairs are observed as marked by red arrows suggesting nucleation in form of pairs is one source of TSDs for p-type wafers. BPD density for box 1,2,3 is low in the range of 581−1123 cm−2. In fact, the middle ~12.6 cm diameter region is characterized to have average BPD density of 598 cm−2, TSD density of 1447 cm−2, and TED density of 1592 cm−2, on par or better than commercial 6-inch n-type wafers.

[picture]

Fig. 4. (a) SWBXT image for the whole p-type wafer indicating the middle 12.6 cm region has low BPD density with whiter contrast, and (b)(c)(d) SMBXT grazing incidence geometry images with 112―8 reflection showing the low density dislocation regions in box 1,2,3 in (a).

Fig. 4. (a) SWBXT image for the whole p-type wafer indicating the middle 12.6 cm region has low BPD density with whiter contrast, and (b)(c)(d) SMBXT grazing incidence geometry images with 11 2 ― 8 reflection showing the low density dislocation regions in box 1 , 2 , 3 in (a).

The extent of prismatic slip for p-type wafer is vastly reduced compared to typical n-type wafers. Only the right periphery region of the wafer shows obvious prismatic slip dislocations contrast in SWBXT image. Other regions are free or have very low density of prismatic slip. As shown by Fig. 5. Prismatic slip dislocations have dark linear contrast along [ 211―0 ] and [ 12―10 ] directions in SWBXT transmission image as marked by yellow dashed line. Such orientations of the prismatic slip dislocations follow the predicted pattern by Guo et al[7,8].

[picture]

Fig. 5. SWBXT image with transmission geometry for the right periphery region of high quality p-type wafer showing distribution of prismatic slip. The orientation of prismatic slip dislocations follow the pattern predicted by Guo et al[7,8].

Fig. 5. SWBXT image with transmission geometry for the right periphery region of high quality p-type wafer showing distribution of prismatic slip. The orientation of prismatic slip dislocations follow the pattern predicted by Guo et al[7,8].

Fig. 6 schematically marks the ranges of prismatic slip dislocations for a high quality p-type wafer and a commercial n-type wafer. The prismatic slip is observed only at the right ~1 cm periphery region for p -type wafer while at the whole periphery region with ~4.7 cm range on the left and ~3.7 cm range on the right for n-type wafer. Note that such observation emphasize the high quality that can be achieved in p-type wafers and does not imply that p-type doping in general results in lower prismatic slip dislocation densities than n-type doping.

[picture]

Fig. 6. Schematics showing distribution of prismatic slip for (a) p-type wafer, and (b) n-type wafer. Shaded red lines mark the region where prismatic slip is observed.

Fig. 6. Schematics showing distribution of prismatic slip for (a) p-type wafer, and (b) n-type wafer. Shaded red lines mark the region where prismatic slip is observed.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

A 6-inch high quality p-type 4H-SiC wafer was achieved by PVT method with stable and uniform Al doping. Synchrotron X-ray topography images indicate on par or better quality than commercial 6-inch n-type wafers with BPD density ~2.2*104 cm−2, TSD density ~1331 cm−2, and TED density ~2163 cm−2. Especially, the middle 12.6 cm diameter region has even lower BPD density of 598 cm−2. Prismatic slip dislocations are only observed at right ~1.0 cm periphery region of the wafer, vastly reduced compared to typical n-type wafers.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

This work was supported by Pallidus, Inc.. This research used resources of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. This research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.59.pdf

L. Han, L. Liang, Y. Kang, Y. Qiu, A review of SiC IGBT: models, fabrications, characteristics, and applications, TPEL. 36 (2021) 2080-2093.

H. Suo, K. Eto, T. Ise, Y. Tokuda, H. Osawa, H. Tsuchida, T. Kato, H. Okumura, Crystal growth and evaluation of nitrogen and aluminum co-doped N-type 4H-SiC grown by physical vapor transport, J. Cryst. Growth. 498 (2018) 224-229.

G. Wang, D. Sheng, Y. Yang, Z. Zhang, W. Wang, H. Li, Wafer-scale p-Type SiC single crystals with high crystalline quality, Cryst. Growth Des. 24 (2024) 5686-5692.

H. Wang, S. Sun, M. Dudley, S. Byrappa, F. Wu, B. Raghothamachar, G. Chung, E. K. Sanchez, S. G. Mueller, D. Hansen, Quantitative comparison between dislocation densities in offcut 4HSiC wafers measured using synchrotron x-ray topography and molten KOH etching, J. Electron. Mater. 42 (2013) 794-798.

B. Raghothamachar, M. Dudley, G. Dhanaraj, X-ray topography techniques for defect characterization of crystals, in: G. Dhanaraj, K. Byrappa, V. Prasa, M. Dudley (Eds.), Springer Handbook of Crystal Growth, Springer, 2010, pp. 1425-1451.

B. K. Tanner, D. K. Bowen, Characterization of Crystal Growth Defects by X-ray Methods, Springer Science & Business Media, New York, 2013.

J. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quast, I. Manning, Prismatic slip in PVT-grown 4H-SiC crystals, J. Electron. Mater. 46 (2017) 20402044.

J. Guo, Y. Yang, O. Y. Goue, B. Raghothamachar, M. Dudley, Study on the role of thermal stress on prismatic slip of dislocations in 4H-SiC crystals grown by PVT method, ECST 75 (2016) 163-168.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 65-71

doi: 10.4028/p-zY1ER5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-19

Accepted:
2026-02-28

Online:
2026-05-18

Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

Hitesh Jayaprakash 1,3,4,a*, Manuel Belanche 2, b, Constantin Csato 3,c, Florian Krippendorf 3,d , Ulrike Grossner 2,e , Michael Rueb 3, 

1 Ernst-Abbe-Hochschule Jena, Carl-Zeiß-Promenade 2, 07745 Jena, Germany

2 Advanced Power Semiconductor Laboratory, ETH Zurich, Physikstrasse 3, 8092 Zurich, Switzerland

3 mi2-factory GmbH, Hans-Knöll-Straße 6, 07745 Jena, Germany

4 Friedrich Alexander Universität, Cauerstrasse 6, 91058 Erlangen, Germany

a* hitesh.jayaprakash@eah-jena.de b  belanche@aps.ee.ethz.ch, c  constantin.csato@mi2-factory.com, d  florian.krippendorf@mi2-factory.com, e ulrike.grossner@ethz.ch, f michael.rueb@mi2-factory.com

Keywords: 4 H -SiC, DLTS, MCTS, energy filtered ion implantation.

Abstract

The extensive study of point defects in 4H−SiC over the past two decades has led to a comprehensive understanding of their influence on device performance. Specifically, the dominant defects Z1/2 and EH6/7 have been well-quantified and are now formally assigned to specific states of the carbon vacancy. Building upon this foundational knowledge, our study investigates the defect landscape created by the novel process of Energy-Filtered Ion Implantation (EFII). Using DLTS and MCTS measurements conducted within the temperature range of 50−650 K, we analyzed the trap levels created by 19 MeV Nitrogen implantation in as-grown 4H−SiC epitaxial wafer. The majority carrier (electrons) trap with DLTS measurements reveal the presence of prominent peaks associated with carbon complexes, labeled as ON0a ( Ec−0.586eV ) and ON0b / Z1/2 at ( Ec− 0.681 eV ), along with smaller peaks in the shallow region and a broader peak identified as EH6/7 at ( Ec−1.53eV ) as the deepest peak. Notably, the close proximity of the ON0b peak to the wellknown Z1/2 peak poses a significant challenge, preventing the definitive assignment of a defect structure to the known carbon complexes. On the contrary, minority carrier (holes) trap detection with MCTS reveal B-center at ( EV+0.24eV ) and ( EV+0.33eV ) and a negligible shallow peak at (EV+0.22eV) assigned as X center. There was no indication of D-center formation in the EFII implanted samples.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

As an emerging power device technology, 4H−SiC has become a preferred material for high-power applications due to its robust physical properties. Although 4H−SiC is a widely used polytype, point defects are common in as-grown (CVD) material, with carbon vacancies typically observed and labeled as Z1/2 and EH6/7 [1]. These defects can also be generated by external processes such as ion implantation, which is a key step for creating carriers for current flow modulation. The presence of these point defects critically influences device performance, most notably through their direct impact on carrier lifetime [2]. Given that carrier lifetime dictates key device performance parameters like on-resistance ( Ron ) and switching speed in fabricated power devices such as diodes and MOS-FETs, addressing these defects would improve device performance. Carbon vacancies, in particular, are known to act as dominant recombination centers for electron-hole recombination [3]. Post ion im-plantation, a high-temperature annealing step, typically performed at 1700∘C to activate the dopants in an argon atmosphere, is effective at recovering the crystal lattice and removing most implantation-induced defects, a deeper understanding of the resulting defect structures is necessary, especially with the introduction of novel processing techniques.

Energy Filtered Ion Implantation (EFII) is a new technology that offers precision drift zone doping [4], making it a key enabler for a simplified approach for SiC Super-Junction devices by simply masking the implanted regions. However, the specific types of point defects generated by this novel technology remain unexplored. Therefore, this study aims to investigate the point defects and trap levels generated by 19 MeV Nitrogen implantation with this technique. EFII offers an implantation depth of approximately 8.5μ m in 4H−SiC for the afore-mentioned Nitrogen ion energy. The implanted samples were subsequently annealed at 1700∘C with carbon capping layer. Deep-Level Transient Spectroscopy (DLTS) and Minority Carrier Transient Spectroscopy (MCTS) measurements were per-formed on standard Schottky diodes fabricated on the implanted SiC samples to identify the peaks that correspond to trap levels existing between valance and conduction bands.

Experimental Approach

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The experimental approach involved the preparation and characterization of three 4H−SiC epitaxial wafers. A pristine wafer from Vendor A with a 10μ m as-grown epitaxial layer and a doping concentration of 5E15 cm-3 was used as a reference without additional processes before Schottky diode fabrication. Two additional wafers from Vendor B, which were unintentionally doped with nitrogen ( <5E14 cm−3 ) with 5μ m epitaxial layer thickness, were used for nitrogen ion implantation with EFII technology at an energy of 19 MeV . To implant different nitrogen concentrations, the wafers were divided into quadrants. The first wafer L was implanted with target concentrations of 1E14, 5 E 14 , and 1E15 cm−3, while the second wafer G was implanted with 1E15,5E15, and 1E16 cm−3 concentrations, with one quadrant on each wafer left un-implanted. Fig. 1a outlines the postimplantation process, all implanted samples were annealed at 1700∘C for 30 minutes in an argon ambient, where the surface was protected by a carbon capping layer formed by the pyrolysis of photo-resist. This layer was subsequently removed through O2 plasma ashing, followed by a sacrificial thermal oxidation at 1050∘C for 20 minutes to ensure complete carbon removal. The wafers were then cleaned with RCA and HF rinse. For the DLTS / MCTS measurements, Schottky diodes were fabricated by depositing a 100 nm nickel layer on the Si-face of the diced chips from each quadrant, with a semi-transparent contacts for MCTS measurements with optical excitation and a thicker central contact for DLTS measurements. The contact diameter for implanted wafer were 1 mm and for pristine (reference) sample was 1.5 mm .

[picture]

Fig. 1. Figure (a) illustrates post implant annealing steps for activation of dopants, and Figure (b) illustrates the calculated net-carrier density from the Tw vs UR=−1.5 plot measured for each sample to verify the implanted concentrations.

Fig. 1. Figure (a) illustrates post implant annealing steps for activation of dopants, and Figure (b) illustrates the calculated net-carrier density from the T w vs U R = − 1.5 plot measured for each sample to verify the implanted concentrations.

The measurement parameters were chosen to optimize the defect characterization and analysis of each sample. For the DLTS measurements, the period width, Up=0 V, ranged from 19.2 ms to 1.92 s , with an electrical pulse stepping from a reverse bias of tp=1 ms to -10 V up to a pulse voltage of UR=−1.5 V, with a pulse duration of 1/C2. In the case of MCTS measurements, the 365 nm LED
was pulsed for 300 ms while maintaining a reverse bias at V to -10 V , respectively for each sample. In order to capture the entire transient, the period width used ranged from 19.2 ms to 1.92 s .

Results and Discussions

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Fig. 1b shows the plots of 5E14 cm−3−1E16 cm−3 vs cm−3 of all implanted samples ranging from concentrations ND−NA. The highly linear nature of each plot shows the uniform doping concentration over depth, which is the intrinsic property of EFII implantation. The lowest implanted concentration 1E14 1700∘C,30 min and no implant regions were measured but the capacitance values were unrealistic due to very low doping levels. This linear slopes verifies the implanted Nitrogen concentrations to the net carrier density expected after activation annealing of the samples. The negligible variation of obtained net carrier concentration T6 value compared to the implanted Nitrogen concentration is due to the existing background doping and tolerances in dose measurement systems for each sample.

[picture]

Fig. 2. DLTS peak progression in (a) and (b) shows the influence of EFII implanted Nitrogen concentration, while MCTS peaks for wafers L and G are shown in (c) and (d), respectively.

Fig. 2. DLTS peak progression in (a) and (b) shows the influence of EFII implanted Nitrogen concentration, while MCTS peaks for wafers L and G are shown in (c) and (d), respectively.

Deep level Transient Spectroscopy.

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

Analysis of the DLTS spectra revealed a total of ten dis-tinct deep-level defect peaks labeled in Fig. 2a and 2b corresponding to implanted wafers L and G respectively. Their corresponding energy levels and densities detailed in the Table 1. The data for the un-implanted ( Ec−0.681eV ) sample serves as an important baseline for measurements specific to each wafer used. This sample shows minimal defect signals, especially compared to the implanted samples. This highlights that the hightemperature annealing effectively mitigates or eliminates native defects or those introduced during wafer processing. The prominent peaks in the implanted samples are therefore a direct consequence of the nitrogen implantation, and not the annealing process itself.

The dominant peaks, designated as 6.28E12 cm−3, has an activation energy of ( Z1/2 ) with a density of T5, and is assigned to either ON0b or the well-known Ec−0.586eV defect. A closely related peak, 1.06E13 cm−3, was observed at ( T4 ) with a density of Ec−0.40eV, and is assigned to the ON0a which is a carbon complex found in samples that were subjected to carbon injection experiments [5,6]. Hence ON0a is suggested to be stable defect with di-interstitial carbon.

Table 1. The list of peaks observed in the Deep Level Transient Spectroscopy (DLTS) measurements between 1/C2 temperature range.

Peaks | Energy (eV) | Energy SD (eV) | σ (×10⁻¹⁵ cm⁻²) | Nt (×10¹³ | Assignment cm⁻³)
T₁ | Ec - 0.133 | 0.009 | 0.151 | 0.207 | SD1 / Ti [2, 7]
T₂ | Ec - 0.213 | 0.015 | 0.899 | 0.186 | E0.22 [8]
T₃ | Ec - 0.39 | 0.02 | 2.34 | 0.127 | E0.38 [6, 9]
T₄ | Ec - 0.40 | 0.088 | 0.205 | 0.164 | S1 / EH1 [10, 11]
T₅ | Ec - 0.586 | 0.129 | 3.32 | 1.061 | ON0a [6]
T₆ | Ec - 0.681 | 0.042 | 6.36 | 0.628 | ON0b / Z1/2 [2, 3, 6, 10, 11]
T₇ | Ec - 0.729 | 0 | 0.083 | 0.0393 | EH3 / S2 [11–13]
T₈ | Ec - 1.183 | 0.156 | 6.59 | 0.167 | EH4/5 [14] / ON2b [2, 13, 15]
T₉' | Ec - 1.391 | 0.066 | 4.10 | 0.368 | SD2 [16] / EH6 [7, 12, 13]
T₉'' | Ec - 1.532 | 0.112 | 9.9 | 0.764 | EH6/7 [2, 3, 7, 8, 13, 16]

In addition to these prominent carbon-related complexes, peak S1/EH1 associated with activation energy ( VSi ), assigned to T7 which could be Ec−0.729eV due to implantation process involved, due to their overlapping nature, accurate assignment is not possible. and S2 at ( (Ci)(VSi) ), assigned to T1 related to Ec−0.133eV. Other defects detected include T2 at ( (Ec−0.22eV) ) related to Titanium, T3 at Ec−0.39eV cited in [8] are material or vendor specific defects and E0.38 at ( Ci ), the previously observed ( T8 ) is the metastable defect related to mono (Ec−1.183eV). The deepest traps are (EH4/5) at (CAV) are assigned to Ec−1.391eV relating to the carbon anti-site vacancy (SD2/EH6) pair or ON 2 b , T9' at ( EH6/7 ) assigned to T9′′ which could be a [Titanium - Nitrogen] interaction trap as mentioned in [16] and the well-documented Ec−1.532eV defect ( cm−3 ) at ( 1700∘C ) with a density of 7.64E12 P1,P2 was measured. The carbon interstitial complexes observed in this study are expected to be formed due to the Nitrogen implantation process where the Carbon is kicked out from its site creating a vacancy which is then occupied by nitrogen at P3 activation anneal. This is proved by the net carrier density value measured which is close to the implanted nitrogen concentrations.

Minority Carrier Transient Spectroscopy

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

A light pulse duration of 300 ms for hole trap filling was selected based on preliminary observations of the capacitance transients. This duration was empirically determined to ensure the charging process reached a steady state. Consequently, the combination of light intensity and pulse length employed in this experimental setup justifies the assumption of complete trap saturation within the probed volume. Furthermore, the use of semi-transparent contacts ensures that the photo-excited volume aligns closely with the volume electrically interrogated under reverse bias. Given these considerations, the calculated trap density provides a fair estimate of trap density for hole carriers. Beyond absolute quantification, this methodology facilitates a relative comparison across the samples, which remains a primary focus of this investigation. The MCTS measurements reveal three distinct peaks for the minority (hole) carriers as shown in Fig. 2c and 2d and listed in Table 2. Each peaks are labeled as, P1 and P2. Peak (Ev+0.259eV) at (Ev +0.171 eV ) which can be assigned to X relating to Al in the material was observed on all the samples, peak B′ at P3 assigned to the P3 defect, which is the shallow B -center on the shoulder of Peak Ev+0.294eV, and the dominant peak B′′ at [11,15,17] assigned to the 125 K−B′ defect is the deeper B-center which were resolved in both
experimental and theoretical studies B′′. Both boron peaks that overlap at Evv+0.881eV and Evv+0.893eV were separated based on hexagonal or pseudo cubic location of Boron in Silicon site. Influence of B" on Nitrogen implant concentration is witnessed in this study. An additional peak, P4, was observed in the pristine sample at ( 4H−SiC ) and ( 5E15 cm−3 ).

Table 2. The list of peaks observed in the Minority Carrier Transient Spectroscopy (MCTS) measure-ments between V temperature range.

Peaks | Energy (eV) | Energy SD (eV) | σ (×10⁻¹⁵ cm⁻²) | Nt (×10¹³ cm⁻³) | Assignment
P₁ | EV + 0.171 | 0.0211 | 1.226 | 0.154 | X [15]
P₂ | EV + 0.259 | 0 | 6.370 | 0.133 | B′ [11, 15, 17]
P₃ | EV + 0.294 | 0.0217 | 0.345 | 2.51 | B″ [11, 15, 17]
P₄ | EV + 0.881, EV + 0.893 | − | − | − | Found on Pristine Wafer only

Further, the pristine as-grown 50−650 K epitaxial layer with background doping of 1E16 cm−3 was subjected to identical DLTS and MCTS measurements. The deep level spectrum between EH4/5,EH6/7 are compared with the highest dose of Nitrogen implant with EFII of 50−200 K from another wafer. In Fig. 3a, it is evidently visible that the only difference in defect landscape being the Carbon complex (ON0a) peak at 250 K and the cm−3 at 520 K and 600 K respectively. The other shallow peaks between Z1/2 are material/vendor specific defects traps. The magnitude of DLTS signal indicates that the EFII process is not creating significant trap concentration at 1E16 1[15] Nitrogen concentrations and the signal value is in the same range of an operational SiC power devices. Sim-ilarly, in Fig. 3b, The MCTS signal show dominant peak of Deep Boron center (B’’) which is not a nitrogen related minority carrier trap. Notably, there are no other hole traps(D center) generated with nitrogen implantation using EFII process on all the EFII implanted samples. This indicates that the EFII process do not generate the lifetime killer D-center. The detected B centers could be due to the vendor specific Boron from reactors used for CVD growth. Overall, the estimated trap densities for the dominant peaks on implanted samples related to ON0a and carbon vacancy peak 3.4E12 cm−3 for pristine sample using the equation 1.8E12 cm−3 is NT=2·ND·(ΔC/Cref) and NT≪ND respectively. This indicates that the trap densities are in the standard operational range for power devices in 4H-SiC material.
4H−SiC when 50−650 K

[picture]

Fig. 3. (a) Comparision of DLTS peaks observed in the pristine crystal and the EH6/7 implanted Nitrogen. Similarly, (b) Comparision of MCTS peaks from same samples. Note: Wafers are from different vendors.

Fig. 3. (a) Comparision of DLTS peaks observed in the pristine crystal and the E H 6 / 7 implanted Nitrogen. Similarly, (b) Comparision of MCTS peaks from same samples. Note: Wafers are from different vendors.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

In this work we have detected and assigned the trap levels introduced in 200−300 K epitaxial grown material by performing Nitrogen implantation with Energy Filtered Ion Implantation technology, based on matching the defects activation energy and capture cross-section from earlier work, it is shown that there are no new defect signatures that were detected between 500−650 K in either DLTS or MCTS measurements. ON0a and 4H−SiC are the dominant electron traps detected in the DLTS spectra and Shallow B centers are the dominant hole traps detected in MCTS spectra. No D-center was found on any EFII implanted samples. The estimated trap densities of these defects are in the typical trap density range for SiC power device operation. However, further study on separating the overlapping signal peaks between the temperature range 4H−SiC and 4H−SiC can be performed to clearly understand the defect structure and create a foundation for further trap studies in ion implanted 4H−SiC samples.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

All Ion implantations were done at Ion Beam Center (IBC), Helmholtz-Zentrum DresdenRossendorfe.V. (HZDR) Dresden, Germany. The Activation anneal was performed at Fraunhofer Institut für In-tegrierte Systeme und Bauelemente technologie (IISB), Erlangen, Germany.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.65.pdf

Tsunenobu Kimoto. Fundamentals of Silicon Carbide Technology. Wiley-IEEE Press, (1st), November 2014.

J. Erlekampf, M. Rommel, K. Rosshirt-Lilla, B. Kallinger, P. Berwian, J. Friedrich, and T. Erlbacher. Lifetime limiting defects in epitaxial layers: The influence of substrate originated defects. Journal of Crystal Growth, 560-561:126033, April 2021.

Koutarou Kawahara, Giovanni Alfieri, and Tsunenobu Kimoto. Detection and depth analyses of deep levels generated by ion implantation in n - and p-type 4H-SiC. Journal of Applied Physics, 106(1):013719, July 2009.

Constantin Csato, Florian Krippendorf, Shavkat Akhmadaliev, Johannes Von Borany, Weiqi Han, Thomas Siefke, Andre Zowalla, and Michael Rüb. Energy filter for tailoring depth profiles in semiconductor doping application. Nuclear Instruments and Methods in Physics Research Sec-tion B: Beam Interactions with Materials and Atoms, 365:182-186, December 2015.

Marianne Etzelmüller Bathen, Margareta Linnarsson, Misagh Ghezellou, Jawad Ul Hassan, and Lasse Vines. Influence of Carbon Cap on Self-Diffusion in Silicon Carbide. Crystals, 10(9):752, August 2020.

Marianne Etzelmüller Bathen, Robert Karsthof, Augustinas Galeckas, Piyush Kumar, Andrej Yu. Kuznetsov, Ulrike Grossner, and Lasse Vines. Impact of carbon injection in on de-fect formation and minority carrier lifetime. Materials Science in Semiconductor Processing, 176:108316, June 2024.

Franziska C. Beyer. Deep Levels in SiC. Department of Physics, Chemistry and Biology, Linköping University, Linköping, 2011.

O. V. Feklisova, E. E. Yakimov, and E. B. Yakimov. Study of single-layer stacking faults in 4H-SiC by deep level transient spectroscopy. Applied Physics Letters, 116(17), April 2020.

Robert Karsthof, Marianne Etzelmüller Bathen, Augustinas Galeckas, and Lasse Vines. Conver-sion pathways of primary defects by annealing in proton-irradiated n -type . Physical Review B, 102(18):184111, November 2020.

M. E. Bathen, A. Galeckas, J. Müting, H. M. Ayedh, U. Grossner, J. Coutinho, Y. K. Frodason, and L. Vines. Electrical charge state identification and control for the silicon vacancy in 4H-SiC. npj Quantum Information, 5(1):111, December 2019.

Tihomir Knežević, Tomislav Brodar, Vladimir Radulović, Luka Snoj, Takahiro Makino, and Ivana Capan. Distinguishing the EH1 and S1 defects in n-type 4H-SiC by Laplace DLTS. Ap-plied Physics Express, 15(10):101002, September 2022.

J. Erlekampf, B. Kallinger, J. Weiße, M. Rommel, P. Berwian, J. Friedrich, and T. Erlbacher. Deeper insight into lifetime-engineering in 4H-SiC by ion implantation. Journal of Applied Physics, 126(4):045701, July 2019.

Takafumi Okuda, Giovanni Alfieri, Tsunenobu Kimoto, and Jun Suda. Oxidation-induced ma-jority and minority carrier traps in n - and p -type 4 H -SiC. Applied Physics Express, 8(11):111301, October 2015.

Marianne Etzelmüller Bathen, Robert Karsthof, Ulrike Grossner, and Lasse Vines. Stability, Evolution and Diffusion of Intrinsic Point Defects in 4H-SiC. Materials Science Forum, 1062:371-375, 2022.

Marianne Etzelmüller Bathen, Piyush Kumar, Misagh Ghezellou, Manuel Belanche, Lasse Vines, Jawad Ul-Hassan, and Ulrike Grossner. Dual configuration of shallow acceptor levels in 4H-SiC. Materials Science in Semiconductor Processing, 177:108360, July 2024.

A. A. Lebedev. Deep level centers in silicon carbide: A review. Semiconductors, 33(2):107130, February 1999.

Vitor J. B. Torres, Capan Ivana, and José Coutinho. Theory of shallow and deep boron defects in 4H-SiC. Physical Review B, 106(22), 2022.

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 73-78

doi: 10.4028/p-kRPYG5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2026-01-06

Accepted:
2026-01-31

Online:
2026-05-18

Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

Kaixuan Zhang 1,a*, Zeyu Chen 1, b, Shanshan Hu 1,c, Jianpei Zhang 1, d, Yuzhuo Li1,e, Donglin Wu 1,f, Haochi Wang 1, g, Balaji Raghothamachar 1, h, Michael Dudley 1,i and Andrey Soukhojak 2,j

¹Department of Materials Science and Engineering, Stony Brook University, Stony Brook, NY 11794, USA

2 SK siltron css, 1317 Straits Dr, Bay City, MI 48706, USA

a  kaixuan.zhang@stonybrook.edu, b  zeyu.chen@stonybrook.edu, c  shanshan.hu@stonybrook.edu, d  jianpei.zhang@stonybrook.edu, e  yuzhuo.li@stonybrook.edu, f  donglin.wu@stonybrook.edu, g  haochi.wang@stonybrook.edu, hbalaji.raghothamachar@stonybrook.edu, i michael.dudley@stonybrook.edu, j andrey.soukhojak@sksiltron.com

Keywords: 4 H -SiC, x-ray topography, defect characterization.

Abstract

Silicon carbide (SiC) is valued for high-power and high-frequency devices, but its performance is limited by crystalline defects. We report a newly observed defect arrangement, termed the "galaxy" defect, in wafers from a PVT-grown 6-inch 4∘ off-axis boule. Optical microscopy revealed dense clusters of micron-sized inclusions, while synchrotron X-ray topography (XRT) showed associated dislocation networks. Transmission synchrotron XRT indicated threading dislocation clusters, and grazing images revealed high densities of basal plane dislocations, deflected Frank partials, and threading-edge-dislocation low-angle grain boundaries (TED-LAGBs). The defect evolved as growth progressed, producing increasingly complex dislocation structures. Based on the observation, we proposed a mechanism for the evolution of the defect involving the generation, evolution, and interaction between the inclusions and dislocations.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

Silicon Carbide has gained great interest for its high thermal conductivity, high saturation velocity, and high breakdown voltage and, therefore, its suitability to fabricate high-frequency, high-power electronic devices [1, 2]. It has been applied in various fields, including transportation and communication. However, the longevity and performance of SiC devices are hindered by defects within the substrate and epitaxial material. The observation of defects and understanding of their formation mechanism is critical for the improvement of crystal quality and, therefore, better device performance and production yield [3, 4]. Synchrotron X-ray topography is a widely adopted tool for effectively characterizing the defects within single crystals, revealing the detailed structure of defects via diffraction imaging from a synchrotron X-ray light source. Synchrotron XRT can be performed either in the transmission geometry, where whitebeam X-ray is used and images is taken through the whole wafer thickness and provide an overview of the distribution of defects in the crystal. Grazing incidence geometry XRT, on the other hand, uses monochromatic X-ray to image the top few microns from the sample surface, creating a more detailed image of the intersection of defects with the sample surface.
In this study, we report the observation of a new arrangement of defects that we name the "galaxy" defect, which was observed on wafers from the same PVT-grown 6-inch 4∘ off-axis boule. Optical microscopy images show a region of a highly dense cluster of micrometer-level inclusions. The samples are investigated mainly with a combination of optical microscopy, synchrotron white beam X-ray topography, and grazing-incidence synchrotron X-ray topography. The structure of the "galaxy" defect is revealed, and a model is proposed based on the experimental results and observations.

Experimental

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

PVT-grown, 4∘ off-axis 4H−SiC substrate wafers are characterized by a combination of optical microscopy and synchrotron X-ray topography. XRT images were recorded in both transmission and grazing-incidence geometry. The transmission images were recorded using (11-20), (1-100), and (1-1 0 1) reflections using a whitebeam synchrotron source at Beamline 27-HEX at the NSLS-II at Brookhaven National Laboratory. The grazing incidence images were recorded from the Si -face using the (1 1-2 8) at an energy of 9.1 keV at beamline 1-BM of the Advanced Photon Source at Argonne National Laboratory.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

The "galaxy" defect was observed on a series of 150 mm PVT-grown 4∘-offcut 4H−SiC epitaxial wafers from the same boule from slice 13 to slice 25, as illustrated in Fig. 1(a). They are observed near the edge of the wafer as shown in Fig. 1(b) and Fig. 1(c). Optical microscopy as a cluster of inclusions with diameters of a few microns, as shown in Fig. 1(d).

[picture]

Fig. 1. Illustration of the optical observation of the "galaxy" defect, including the location and the wafer numbers and their relevant locations (a); the location of the defect on the boule (b); optical transmission image of the defect on slice 18 (c); and optical transmission microscopy images of the "galaxy defect".

Fig. 1. Illustration of the optical observation of the "galaxy" defect, including the location and the wafer numbers and their relevant locations (a); the location of the defect on the boule (b); optical transmission image of the defect on slice 18 (c); and optical transmission microscopy images of the "galaxy defect".

Fig. 2(a) shows the Transmission XRT, while Fig. 2(b) shows the transmission optical images from the "galaxy" defect region of selected wafers from the boule containing the defect. Transmission XRT images show a dark contrast within the region of the inclusion. Individual defects could not be identified due to the possible high defect density within this region. Also, no individual contrast from the optically observed inclusions could be identified in the topography images. The defect region can be observed to initiate further from the wafer edge and move towards the edge. The cluster can be observed to split into two parts from slice 15. The optical image from slice 49 shows no optical contrast for the defect, while the XRT image shows a large network of prismatic slip dislocations and LAGB as a residual from the defect.

[picture]

Fig. 2. Whitebeam transmission XRT images from ( 1 1 - 20 ) reflection (a) and optical transmission images (b) from slice 13, 15, 17, 22, 25, and 49 showing the evolution of the "galaxy" defect.

Fig. 2. Whitebeam transmission XRT images from ( 1 1 - 20 ) reflection (a) and optical transmission images (b) from slice 13, 15, 17, 22, 25, and 49 showing the evolution of the "galaxy" defect.

Further analysis can also be performed with g·b analysis, identifying the direction of the Burgers vectors of BPDs in this region. The defect region can be observed to be much darker on the (1 1-2 0) reflection images compared to the (1-1 00) reflection images. While exact quantitative measurements were difficult due to the high defect density in this region. Qualitatively, around a third of the BPDs in this region are parallel or antiparallel to the step flow direction. Grazing-incidence geometry XRT was performed on the wafer series in order to further identify the defect structure within this region. The results from slice 13, slice 18, slice 25, and slice 49 are selected as representative and shown in Fig. 3. Although the defect density is still too high to investigate the detailed interaction of defects, contrast corresponding to BPD, TED, and TMD can be identified from the grazing image of slice 13 . A similar arrangement is observed on the grazing images from slice 18. The density of deflected dislocations is found to be higher on slice 18 compared to slice 13. As the growth proceeds to slice 25, a large LAGB network can be observed to form, which corresponds with the observation from the transmission images. The density of deflected dislocations between the inclusion cluster and the wafer edge is also found to increase.

[picture]

Fig. 3. Grazing-incidence XRT images from (1 1 - 28 ) reflection from the Si-face of the "galaxy" defect region from slice 13 (a), slice 18 (b), slice 25 (c), and slice 49 (d).

Fig. 3. Grazing-incidence XRT images from (1 1 - 28 ) reflection from the Si-face of the "galaxy" defect region from slice 13 (a), slice 18 (b), slice 25 (c), and slice 49 (d).

Further SEM and Raman spectroscopy were used to investigate the composition and origin of the inclusions. However, neither SEM nor Raman spectroscopy was able to identify contrast on the sample surface. Reflective optical microscopy was also not able to resolve any inclusion on the sample surface. The interaction thickness of these characterization methods might have been too low to intersect with any of the inclusions. These inclusions could be due to the transportation of carbon or SiC particles from the source material to the growth interface by drag and thermophoretic forces [5]. However, the exact identity and the origin of the inclusions related to the "galaxy" defect are still under investigation with planned TEM studies.
Based on the observations and XRT images, a model can be proposed for the formation and inclusion of the "galaxy" defect, as illustrated in Fig. 4. Previous studies have shown that TSD/TMD pairs could originate from inclusions during epitaxial growth [6, 7]. A high density of inclusions was observed inside the "galaxy" defect region, which would cause the generation of TSD/TMD pairs and therefore the high density of TSD/TMDs observed on the grazing images. As the location of the "galaxy" defect is very close to the wafer edge, the surface curvature in this area would be comparably high, which would promote the formation of macrosteps during the epitaxial process [8, 9]. These macrosteps could then deflect the TSD/TMDs into frank partials and possible stacking faults, which could be the cause of the high density of deflected dislocations between the inclusion region and the wafer edge [10].
The high density of inclusions in this region could also be the origin of the high density of TEDs. While the generation of TEDs is also possible near inclusions, the prismatic slip dislocation network near the "galaxy" suggests that the slipping of prismatic slip dislocations could also be contributing factor to the TEDs in this region [8, 11, 12]. The inclusions in these regions could also serve as blockages of the slipping of prismatic slips dislocations, causing them to re-propagate as TED and pile up near the "galaxy" defect region. It is then possible for the high density of TEDs from the prismatic slips with the same orientation to align themselves along the most energetically favorable arrangement, which would explain the formation of TED-LAGB as growth progresses [13]. In the meantime, the inclusions can also serve as pinning points for the movement of BPDs. Both the inclusions and the highly dense TSD/TMDs within this region could serve as pinning points for the movements of BPDs. This pinning effect could cause the multiplication of BPDs in this region via the Frank-Read source, providing a possible explanation for the high BPD density in this region [14].

[picture]

Fig. 4. Illustration of the proposed model for the "galaxy" defect based on experimental results and observations.

Fig. 4. Illustration of the proposed model for the "galaxy" defect based on experimental results and observations.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

In this study, we investigated a new defect arrangement in PVT-grown 4H-SiC wafer named "galaxy" defect, which was initially observed as micron-level inclusions. The defect arrangements within the
defect are revealed through a combination of optical microscopy, whitebeam synchrotron X-ray topography, and grazing incidence synchrotron topography. A model for the evolution of the defect is proposed based on the experimental results, where the inclusions serve as the origin of TSD/TMDs while also piling up TEDs by blocking prismatic slips and eventually forming TED-LAGB. The inclusions and the TSD/TMDs could be the pinning points causing the multiplication of BPDs in this region. The identification and characterization of the "galaxy" defect provides insights into defect interactions in SiC , which is essential for the improvement of the PVT process in producing 4H−SiC wafers with better quality.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

This research was supported by SK siltron css. This research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence at the Advanced Photon Source. This research used beamline 27-HEX of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DESC0012704.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.73.pdf

Dhanaraj, G., B. Raghothamachar, and M. Dudley, Growth and Characterization of Silicon Carbide Crystals, in Springer Handbook of Crystal Growth, G. Dhanaraj, et al., Editors. 2010, Springer Berlin Heidelberg: Berlin, Heidelberg. p. 797-820.

Codreanu, C., et al., Comparison of 3c SiC, 6h SiC and 4H SiC MESFETs performances. Materials Science in Semiconductor Processing, 2000. 3: p. 137-142.

St. G. Müller et al., Defects in SiC substrates and epitaxial layers affecting semiconductor device performance, The European Physical Journal Applied Physics, vol. 27, no. 1-3, p.29-35.

Tsunenobu Kimoto and Heiji Watanabe, Defect engineering in SiC technology for high-voltage power devices. Applied Physics Express, 2020. 13: p. 120101-1-3.

Z. Wang, Z. Wu, M. Ge, H. Bao, Z. Ma, J. Wu, Study on Carbon Particle Inclusions during 4HSiC Growth by Using Physical Vapor Transport System, Materials Science Forum, 954 (2019), 46-50.

D. Hofmann, E. Schmitt, M. Bickermann, M. Kölbl, P.J. Wellmann, A. Winnacker, Analysis on defect generation during the SiC bulk growth process, Materials Science and Engineering: B, 61-62 (1999), 48-53.

M. Dudley, X. R. Huang, W. Huang, A. Powell, S. Wang, P. Neudeck, M. Skowronski; The mechanism of micropipe nucleation at inclusions in silicon carbide. Appl. Phys. Lett. 75 (1999) 784-786.

Shanshan Hu, Yafei Liu, Qianyu Cheng, Zeyu Chen, Xiao Tong, Balaji Raghothamachar, Michael Dudley, Investigation of defect formation at the early stage of PVT-grown 4H-SiC crystals, Journal of Crystal Growth, 628 (2024), 127542.

M. Dudley, F. Wu, H. Wang, S. Byrappa, B. Raghothamachar, G. Choi, S. Sun, E. K. Sanchez, D. Hansen, R. Drachev, S. G. Mueller, M. J. Loboda; Stacking faults created by the combined deflection of threading dislocations of Burgers vector c and during the physical vapor transport growth of 4H-SiC. Appl. Phys. Lett. 98 (2011), 232110.

S. Hu, B. Raghothamachar, Z. Chen, K. Kayang, D. Gersappe, M. Dudley, V. Torres, D. Dukes, D. Lang, A. Martin, H. Briccetti, S. Griswold, T. Kegg, and N. Griffin, New Insights into the Occurrence of Prismatic Slip during PVT Growth of SiC Crystals, Materials Science Forum, 1156 (2025), 57-64.

J. Guo, Y. Yang, B. Raghothamachar, J. Kim, M. Dudley, G. Chung, E. Sanchez, J. Quast, and I. Manning, Prismatic Slip in PVT-Grown 4H-SiC Crystal, Journal of Electronic Materials, 46 (2017), 2040-2044.

Q. Shao, W. Geng, S. Xu, P. Chen, X. Zhang, R. Shen, H. Tian, X. Pi, D. Yang, and R. Wang, Nucleation of Threading Dislocations in 4H-SiC at Early Physical-Vapor-Transportation Growth Stage, Crystal Growth and Design (2023), 5204-5210.

Q. Cheng, Z. Chen, S. Hu, B. Raghothamachar, M. Dudley, Analysis of Threading Edge Dislocation Low-Angle Grain Boundary Network Distributions in Wafers Through Synchrotron X-ray Topography and Ray-Tracing Simulation. J. Electron. Mater. 54 (2025), 5037-5050.

H. Wang, F. Wu, S. Byrappa, B. Raghothamachar, M. Dudley, P. Wu, I. Zwieback, A. Souzis, G. Ruland, T. Anderson, Synchrotron topography studies of the operation of double-ended Frank-Read partial dislocation sources in 4H-SiC, Journal of Crystal Growth, 401 (2014), 423430.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 79-85

doi: 10.4028/p-mYaQQ1

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-23

Accepted:
2026-02-23

Online:
2026-05-18

Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Y. Li 1,a, J. Zhang 1, b, Z. Chen 1,c, H. Wang 1, d, K. Zhang 1,e, S. Hu 1,f, Raghothamachar 1, g, A. A. Burk Jr 2, h, K. Singh 2,i, M. A. Johar 2,j, N. A. Mahadik 3,k, R. E. Stahlbush 3,I, M. Dudley 1, m

1 Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794 USA

2 Coherent, Inc., USA

3 U. S. Naval Research Laboratory, Washington DC, USA

a  yuzhuo.li@stonybrook.edu, b  jianpei.zhang@stonybrook.edu, c  zeyu.chen@stonybrook.edu, d  haochi.wang@stonybrook.edu, e  kaixuan.zhang@stonybrook.edu, f  shanshan.hu@stonybrook.edu, g  balaji.raghothamachar@stonybrook.edu, h  Albert.Burk@coherent.com, ikanwar.singh@coherent.com, jmuhammadali.johar@coherent.com, 

k  nadeem.mahadik@nrl.navy.mil, 'stahlbush@nrl.navy.mil, mmichael.dudley@stonybrook.edu

Keywords: Silicon Carbide, Thick Epitaxial Layer, X-ray Topography, 3C inclusions.

Abstract

Silicon carbide is a leading wide-bandgap semiconductor for high-voltage power electronics. For 6.5−10kV operation, thick epitaxial layers ( ≥60μ m ) are required to sustain depletion width and maintain uniform electric fields, placing a premium on low extended-defect densities in both substrate and epilayer. Thick epitaxial 4H-SiC layers of 60μ m and 110μ m were grown on 6inch substrates in a multi-wafer warm-wall reactor and evaluated by synchrotron X-ray topography in grazing-incidence (22-4 16) and transmission (11-20) geometries. Transmission imaging showed substrate dislocation content near the lower bound typically reported for 6-inch wafers. Notably, grazing-incidence topography (penetration depth >40μ m ) revealed no basal-plane dislocations propagating into the epilayers, consistent with efficient dislocation conversion at the substrateepilayer interface. The 3C-SiC inclusion density was ~30 per 6-inch wafer for 60μ m epilayers and ~60 per wafer for 110μ m epilayers; the average micropipes density varies from 0 to 5 for both 60 and 110 um epiwafers. Threading dislocation densities-screw, edge, and mixed-were on the order of 1.0−2.0×103 cm−2. These results establish thick 4H−SiC epilayers with suppressed basal-plane propagation and substantially reduced extended-defect content, providing a strong basis for reliable 6.5−10kV device fabrication.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Silicon carbide (4H−SiC) has emerged as a central wide-bandgap semiconductor for high-voltage power conversion because its large bandgap, high thermal conductivity, and high critical electric field enable compact drift regions that sustain high blocking voltages with low conduction loss. In the 6.510 kV class (e.g., planar MOSFETs and superjunction devices), thick and uniform drift layers (typically ≥60μ m ) are required to provide sufficient depletion width and a near-uniform electricfield distribution at breakdown, placing stringent demands on wafer-scale crystalline quality across both substrate and epitaxial layer [1,2].
Extended defects that are most consequential in this regime include basal-plane dislocations (BPDs), threading dislocations (screw/edge/mixed) (TSDs/TEDs/TMDs), micropipes, and 3C inclusions. For device reliability, a key objective in thick epitaxy is to suppress basal-plane-related degradation pathways, minimize threading dislocation densities to the low 103 cm−2 level across full 150 mm wafers, and eliminate high-leakage defects such as micropipes. [3-5]
Assessing these defect populations at the wafer scale with depth sensitivity is enabled by synchrotron X-ray topography (XRT). In off-axis 4H−SiC, grazing-incidence monochromatic topography
provides selective sensitivity to defects within the effective penetration depth near the surfaceparticularly for basal plane related defects and transmission geometries provide defect information primarily in the substrates.
In this work, thick epitaxial 4H-SiC layers of 60μ m and 110μ m were grown on 6-inch substrates using a multi-wafer warm-wall reactor and characterized by synchrotron XRT in complementary grazing-incidence ( g=22−416 ) and transmission ( g=11−20 ) geometries.

Experiment

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

4∘ off-axis PVT-grown 150 mm 4H-SiC wafers with 60 and 110μ m-thick CVD epilayers were characterized using synchrotron monochromatic beam X-ray topography (SMBXT) in grazingincidence geometry with the 22−416 reflection at 18 keV , performed at beamline 1−BM of the Advanced Photon Source (APS), Argonne National Laboratory (experimental setup in Fig. 1a; Images were recorded on high-resolution X-ray films (Agfa D3sc). High-resolution X-ray diffraction (HRXRD) double- and triple-axis rocking curves and reciprocal-space maps (RSMs) of (0008) were measured on a Bede D1 diffractometer using CuK1(λ=1.54 A). Figure 1(c) shows the double-axis geometry for rocking curve measurement. The laboratory source operated at 40kV/30 mA; the beam was conditioned by a MaxFlux multilayer mirror and a channel-cut symmetric Ge(004) monochromator. [6]

[picture]

Fig. 1. Schematic of experiment setup of (a) Synchrotron x-ray topography with transmission geometry, (b) Grazing incidence geometry, (c) High resolution x-ray diffraction with double-axis and triple-axis scanning of (0008) reflection.

Fig. 1. Schematic of experiment setup of (a) Synchrotron x-ray topography with transmission geometry, (b) Grazing incidence geometry, (c) High resolution x-ray diffraction with double-axis and triple-axis scanning of (0008) reflection.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Grazing-incidence synchrotron X-ray topographs using the g=224―16 reflection as an effective penetration depth of about 45μ m, imaging the 60μ m and 110μ m thickness epi layer 4H-SiC wafers. The HRXRD was used as an effective tool to reveal the general quality of the thick epi layer SiC wafers.
Overall wafer quality analysis. Fig. 2 shows transmission and grazing incidence topographs from 60um and 110um thick epiwafers. For 60 um epi layer wafers, the grazing topographs exhibit few broad contours and for 110 um epi layer wafers which show greater number and narrower contours, indicating a higher lattice distortion level than 60 um epi layer wafers. The double-axis rocking curve of these wafers given by HRXRD also confirm these observations withs: the average FWHM of 60 um epi layer wafers is 11arcsec while that of the 110 um epilayer wafers is 13arcsec, which correlates with the higher lattice distortion observed on the grazing incidence topographs. For these thick epilayer wafers, the number of 3C inclusion (except the edge of the wafer) incidence is of the order of tens per wafer ( 20 per 150 mm wafer for 60μ m;≈50 per wafer for 110μ m ). Few micropipes ( 1 or 2) were detected throughout the wafers, including in the 110μ m epilayers. The threading dislocation (TSD/TMD and TED) densities are relatively low for both thickness epi-wafers. The transmission topography ( g=11−20 ) indicates the dense BPDs from the substrate and relatively low TED densities (under 100 cm−2 ). In grazing-incidence (22-4 16, 18keV;≈40μ m effective depth), no

BPD is observed within the epilayers except for localized features surrounding the 3C inclusions and the average TED density in grazing topography is 400 cm−2 for 60μ m epi layer and 500 cm−2 for 110 μm epi layer).

[picture]

Fig. 2. Synchrotron X-ray topography of a 6-inch diameter 4H-SiC wafer with a 110μ m epitaxial layer: (a) Grazing-incidence topography ( g=22−416 ) of 60 um epi layer wafer and (c) 110 um epi layer wafer, highlighting surface and near-surface defect distributions and revealing 3C-SiC inclusions as distinct white contrast features; (b) Transmission topography ( g=11−20 ), providing comprehensive defect visualization of defects in substrate through the epitaxial layer depth, where 3C-SiC inclusions appear as characteristic black contrast features.

Fig. 2. Synchrotron X-ray topography of a 6-inch diameter 4H-SiC wafer with a 110 μ m epitaxial layer: (a) Grazing-incidence topography ( g = 22 − 416 ) of 60 um epi layer wafer and (c) 110 um epi layer wafer, highlighting surface and near-surface defect distributions and revealing 3C-SiC inclusions as distinct white contrast features; (b) Transmission topography ( g = 11 − 20 ), providing comprehensive defect visualization of defects in substrate through the epitaxial layer depth, where 3C-SiC inclusions appear as characteristic black contrast features.

3C Inclusions, HLA, and ID. Overall, the 3C inclusions are few and occur mainly near the wafer edge; the interiors are largely inclusion-free. The enlarged grazing topographs ( g=22−416 ) show the 3C inclusions with BPD loops generated. The BPD will propagate along <1−100> directions. The average width of 3C inclusions in 60μ m-thick epi layer wafers is about 860μ m. BPD loops and Interfacial dislocations are generated around the 3C inclusions. The average length of BPD propagation along <1−100> is 1000 um . The 3 C inclusions and associated BPDs covered is about 0.5% throughout the wafer. In 110μ m-thick epilayer wafers, the average width of 3C inclusions is approximately 1500μ m, with BPD loops and interfacial dislocations forming around them. The basalplane dislocations propagate along the <1−100> direction with the average length of about 1400μ m; the coverage of 3C inclusions and associated BPD loops over the wafer is 1.7%. Interfacial dislocations are observed in some 3C inclusions in both 60um and 110um epi layer wafers; the halfloop arrays, however, is not observed on these wafers.

[picture]

Fig. 3. Topographs of 3C inclusions from: (a) to (c) 40 um epi layer wafers; (d) to (f) 60 um epi layer wafers; (g) to (i) 110 um epi layer wafers.

Fig. 3. Topographs of 3C inclusions from: (a) to (c) 40 um epi layer wafers; (d) to (f) 60 um epi layer wafers; (g) to (i) 110 um epi layer wafers.

BPD Conversions. During the epitaxial growth of 4H−SiC on off-axis substrates, defects can be either replicated from the substrate into the grown epi layer or converted into other kinds of defects. One of the most important conversions is the BPD converting to TED. BPDs significantly affect SiC crystal quality and device reliability, leading to issues such as forward-voltage degradation in SiCp−n diodes under long-term operation [7] and increased leakage current. The BPD conversion in the epi layer growth, therefore, is critical to decrease the BPDs in the epi layer. BPDs originating in the substrate intersect the stepped growth surface. Because the surface advances in step-flow mode, the dislocations interact with terraces and macro-steps. As the BPD approaches the surface, it experiences an image force arising from the nearby free surface; this force becomes comparable to the critical resolved shear stress for prism-plane glide. To minimize line energy, the BPD bends upward and out of the basal plane within the first few microns of epilayer growth. Once bent, the dislocation reorients and propagates vertically as a TED. Consequently, BPD density drops sharply while TED density rises across the interface. [8] [9].

[picture]

Fig. 4. Schematic of different kinds of defect movements during the epitaxial growth.

Fig. 4. Schematic of different kinds of defect movements during the epitaxial growth.

[picture]

Fig. 5. Topographs with (22-4 16) under high magnitude optical microscopy of the thick epi layer wafers. The red arrows show the TEDs (white dot contrast) along with BPD (black line contrast), indicating the examples of BPD conversions during the epitaxial growth.

Fig. 5. Topographs with (22-4 16) under high magnitude optical microscopy of the thick epi layer wafers. The red arrows show the TEDs (white dot contrast) along with BPD (black line contrast), indicating the examples of BPD conversions during the epitaxial growth.

"Zebra" feature defects in 60μ𝐦 Epi-Layer. A prominent "zebra" band is observed in the 60μ m 4H-SiC epilayer wafer. Transmission synchrotron topography reveals a region of BPDs forming a large strain-contour loop, while grazing-incidence topography of the same region shows dense TEDs but no BPDs, confirming BPD to TED conversion within the epilayer. The persistence of the zebrashaped contrast indicates that although the defect character has changed, the associated long-range strain/tilt field from substrate defect clusters has been elastically transferred into the epilayer. Previously, Liao et al. [10] reported butterfly defects, which originate from tightly bundled, oppositely signed BPDs forming lobes of tilt. The zebra shape defect observed differs in geometry, presenting instead as a large, loop-like strain field, whereas in the zebra shape defect, the entire defect region in transmission images is filled with dense BPDs, producing a much broader strain loop. Moreover, no well-defined LAGB nucleation site is observed for the zebra feature. However, the butterfly-type distortion field may represent a contributing condition, influencing the elastic strain environment that shapes the zebra band. Ongoing work is directed at clarifying this mechanism, disentangling the roles of substrate-induced dislocation clusters, macro-step overgrowth, and possible butterfly-like strain fields in the formation of this unique defect structure.

[picture]

Fig. 6. Synchrotron X-ray topography of zebra feature defect of g=22−416 grazing image (left) and g=11−20 transmission image. The grazing image shows the black band contours with dense TEDs; the transmission image shows the dense BPD loop formed.

Fig. 6. Synchrotron X-ray topography of zebra feature defect of g = 22 − 416 grazing image (left) and g = 11 − 20 transmission image. The grazing image shows the black band contours with dense TEDs; the transmission image shows the dense BPD loop formed.

Scratches induced TED arrays. Scratch-induced TED arrays are observed in 40μ m and 110μ m thick epilayers, originating from residual scratches on the substrate surface that were not completely removed during polishing. Such scratches contain subsurface damage in the form of BPD half-loops, which act as dislocation sources during epitaxial growth. As growth proceeds, the intersections of these half-loops with the advancing surface replicate into the epilayer: intersections aligned in screw orientation propagate as screw-type BPDs, while those away from screw orientation propagate as TEDs. Because scratches usually extend laterally across the surface, many BPD loops intersect along the same trace, giving rise to rows of TEDs aligned with the scratch orientation. Synchrotron X-ray topographs show these arrays as closely spaced dislocations following the scratch line, often
appearing as opposite-signed pairs in accordance with Burgers vector conservation. With continued growth, these TED arrays can evolve in configuration, sometimes transforming into low-angle grain boundary-like structures further into the boule, though their density generally decreases with depth. [7,11]

[picture]

Fig. 7. Grazing incidence X-ray topography at high-magnification optical microscopy show scratches induced TED arrays in the 40μ m (left) epi layer wafer and in the 110μ m (right) epi layer wafer.

Fig. 7. Grazing incidence X-ray topography at high-magnification optical microscopy show scratches induced TED arrays in the 40 μ m (left) epi layer wafer and in the 110 μ m (right) epi layer wafer.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

Synchrotron X-ray topography and high-resolution X-ray diffraction confirm the excellent crystalline quality of the thick 4H−SiC epilayers studied. Nearly complete BPD → TED conversion was achieved, while zebra-shaped bands and scratch-induced TED arrays provide insight into dislocation evolution. Grazing-incidence imaging shows no detectable BPD propagation into the epilayers except at 3C inclusions; 3C-SiC inclusions number about 30 per 6 -inch wafer for 60−μm epilayers and ~50 for 110−μm epilayers. Only a few micropipes were observed, and threading dislocation densities were reduced to 200−400 cm−2. These results underscore the significant potential of these wafers for reliable, high-performance power electronic devices.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

This work has been funded, in part, by the Microelectronics Commons Program, a DOD initiative. The samples are provided by Coherent, Inc. This research used resources [or insert beamline if applicable] of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. This research used resources of the Advanced Photon Source, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.79.pdf

T. Kimoto, Material science and device physics in SiC technology for high-voltage power devices, Jpn. J. Appl. Phys. 54, 040103 (2015).

Y. Zhang, H. Peng, Z. Chen, and M. Dudley, Investigation of factors influencing the occurrence of 3C-inclusions for the thick growth of on-axis C-face 4H-SiC epitaxial layers, J. Cryst. Growth 512, 1 (2019).

K. Masumoto, K. Kojima, and H. Yamaguchi, Investigation of Factors Influencing the Occurrence of 3C-Inclusions for the Thick Growth of On-Axis C-Face 4H-SiC Epitaxial Layers, Materials 13, 4818 (2020).

M. Dudley, N. Zhang, Y. Zhang, B. Raghothamachar, S. Y. Byrapa, G. Choi, E. Sanchez, D. M. Hansen, R. Drachev, and M. J. Loboda, Characterization of 100 mm diameter 4H-silicon carbide crystals with extremely low basal plane dislocation density, Mater. Sci. Forum 645648, 291 (2010).

B. Raghothamachar, M. Dudley, Dislocations in 4H-SiC Substrates and Epilayers, in: P. Wellmann, N. Ohtani, R. Rupp (Eds.), Wide Bandgap Semiconductors for Power Electronics, Wiley VCH GmbH, Weinheim, 2022, pp. 169-198.

Z. Chen, Y. Liu, Q. Cheng, S. Hu, B. Raghothamachar, and M. Dudley, Analysis of strain in ion implanted by fringes observed in synchrotron X-ray topography, J. Cryst. Growth 627, 127535 (2024).

M. Dudley, N. Zhang, Y. Zhang, B. Raghothamachar, and E. K. Sanchez, Nucleation of c-axis screw dislocations at substrate surface damage during 4H-SiC homo-epitaxy, Mater. Sci. Forum 645-648, 295 (2010).

S. Ha, P. Mieszkowski, M. Skowronski, and L. B. Rowland, Dislocation conversion in 4H silicon carbide epitaxy, J. Cryst. Growth 244, 257 (2002).

H. Tsuchida, T. Miyanagi, I. Kamata, Y. Sugawara, et al., Investigation of basal plane dislocations in the 4 H -SiC epilayers grown on substrates, Mater. Sci. Forum 483-485, 97 (2005).

M.E. Liao, N. A. Mahadik, R. E. Stahlbush, A. Burk, U. Chakrabarti, I. Zwieback, X. Xu, and R. Rengarajan, Structural analysis of novel butterfly-shaped defects in 4H-SiC substrates, Proc. ICSCRM 2023 (2023).

Q. Cheng, H. Peng, B. Raghothamachar, and M. Dudley, Scratch-induced threading dislocations in thick 4H-SiC epilayers, Defect Diffus. Forum 434, 71 (2024).

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Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 87-91

doi: 10.4028/p-w9w53Z

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-29

Revised:
2025-12-20

Accepted:
2026-02-23

Online:
2026-05-18

Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

Dong Lee 1,a*, Kirby Schmidt 1,b, Muhammad Ali Johar 1,c, Shanthi Subramanian 1, d, Albert Burk 1,e and Andy Souzis 1,f

¹Coherent Corporation, 2251 Newlins Mill Road, Easton, PA 18045, USA

a* Dong.Lee@Coherent.com, b Kirby.Schmidt@Coherent.com, c muhammadali.johar@coherent.com, d Shanthi.Subramanian@Coherent.com, e Albert.Burk@coherent.com, f Andy.Souzis@coherent.com

Keywords: defects, dislocations, characterization, photoluminescence.

Abstract

The performance and reliability of silicon carbide ( SiC ) devices are critically dependent on the quality of epitaxial layers which in turn are influenced by substrate properties. The accurate classification of epitaxial defects coming from substrate crystal defects and surface defects is critical since these can adversely affect device performance. In this paper, two new methods of defect characterization in substrates and epitaxial layers are presented utilizing photoluminescence (PL) spectrum and carrier lifetime. These methods can be used to study the evolution of defects from substrates to epi and to better predict Epi yields.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

4 H polytype of silicon carbide (4H−SiC) is a semiconductor material finding increased use in power devices due to its wide bandgap, high breakdown voltage and high thermal conductivity [1]. The performance and reliability of silicon carbide ( SiC ) devices are critically dependent on the quality of epitaxial layers which in turn are influenced by substrate properties. The accurate classification of the device killer defects in epitaxial layers is critical for predictive capabilities [2]. In general, most epitaxial defects are inspected and classified by confocal differential interference contrast (DIC) microscopy technology. DIC scan images, combined with photoluminescence (PL) intensity, are used to classify defects into different defect bins for both substrates and epi. This study uses dynamic optical reflectance by pump-probe technology to identify dislocations in substrates and PL peak lambda and carrier lifetime based on band edge emission of each defect measured by Time Resolved PL (TRPL, 355 nm laser with 30 kHZ 600 ps pulse) to identify device killer defects in epi layers [3,4].

Experiments

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4H-SiC substrates were scanned initially by standard Lasertec SICA88 to identify crystal and surface defects. Conventional method for dislocation detection and classification in SiC uses KOH based etching chemistries followed by etch pit classification. This method is destructive and can show variability due to different chemistries and the need to control etching conditions carefully. Nondestructive methods of dislocation detection can avoid the disadvantages of etching and are more conducive to correlation with post-Epi defects. Previously, non-destructive detection and classification of dislocations have been studied using Lasertec SICA PL images [5]. In the present study, threading screw dislocations (TSD), threading edge dislocations (TED) and basal plane dislocations (BPD) are identified using a new dynamic optical reflectance technique that employs pump-probe technology (similar to photo-reflectance). Results from a beta version of this tool were correlated with the X-ray topography (XRT) measurements. A large dataset of wafers was used for this study and tool reproducibility, and repeatability was verified. The optical approach is also faster compared to XRT and can detect TEDs as well. XRT data was collected using Rigaku's XRT micron system. Fig. 1 (a) and (b) shows the correlation between the two different measurements for TSD and BPD. The R2 factors are close to 0.753 for TSD and 0.923 for BPD. The optical method shows higher values for TSD due to some TED and TMD being identified as TSD. XRT BPD measures a volume density which is converted to a surface density whereas the dynamical optical measurement measures
the BPD signal at the surface which can also lead to discrepancy between the two measurements. The exact number of BPD on the surface is also affected by the accuracy of BPD counting in areas where there are high density clusters.

[picture]

Fig. 1. Dynamic pump-probe optical measurement and XRT TSD (a) and BPD (b) measurements show linear correlation.

Fig. 1. Dynamic pump-probe optical measurement and XRT TSD (a) and BPD (b) measurements show linear correlation.

Fig. 2 (a) shows TSD, TED and BPD identification from the optical measurement scan image. Map images were processed using computer vision for improved classification and counts. Fig. 2 (b) is the optical measurement BPD map and Fig. 2 (c) shows the XRT BPD map on the same wafer. The BPD defect distribution on the wafer is similar between the two techniques.

[picture]

Fig. 2. The scan image of the dynamic pump-probe optical measurement for TSD, TED, and BPD (a), and BPD map distribution by the dynamic optical measurement (b) and the corresponding BPD map distribution of XRT scan on the same wafer (c). The two different measurements show similar trends

Fig. 2. The scan image of the dynamic pump-probe optical measurement for TSD, TED, and BPD (a), and BPD map distribution by the dynamic optical measurement (b) and the corresponding BPD map distribution of XRT scan on the same wafer (c). The two different measurements show similar trends

Epitaxial films were grown on these substrates using multi-wafer chemical vapor deposition (CVD). These wafers were scanned using Lasertec SICA again to identify epitaxial defects. The epitaxial wafers were also scanned and analyzed using EtaMax MiPLATO-SiC for PL spectrum and carrier lifetime of epitaxial defects. First, substrate defects and epitaxial defects were compared to correlate and detect propagation of defects from the substrate surface to epitaxial layers. However, it was found that SFs (stacking faults) were not easy to trace down to substrate defects. Most substrate BPD were converted into TEDs and could not be identified through standard characterization methods.
Lasertec SICA is the standard technique used to characterize epitaxial defects. Epi defects are mostly classified by DIC images, and the majority of defects are stacking faults based on DIC images and PL intensity. Some SF defects overlap in DIC and PL images. However, it is difficult to identify specific killer defects as shown in Fig. 3. Epi BPD counts are minimal and quite different from substrate BPD distribution (not shown here). Poly type inclusions are identified through DIC images.

[picture]

Fig. 3. Lasertec SICA scan on an epi wafer shows various defects and needs to filter out as needed.

Fig. 3. Lasertec SICA scan on an epi wafer shows various defects and needs to filter out as needed.

This wafer was scanned again using EtaMax MiPLATO. Figure 4 shows the scanned data with classified SFs and polytype inclusions, associated spectrum and carrier lifetime. Analysis of epi defects with a peak lambda of 540 nm in the PL spectrum can reveal additional 3C poly type inclusions, which do not appear in DIC images. Polytype and some SF defects show a peak at 540 nm . The ratio of polytype inclusion from DIC detection to 3C defect using the 540 nm peak lambda ranges from 95/109 to 90/122. This implies that DIC based classification may miss some 3C poly type defects. Thus, defect classification based on peak lambda can result in improved killer defects identification for correlation with device performance. In addition, the 424 nm peak lambda in the PL spectra reveals all 1SSF. Most poly type inclusions and major defects are relatively well matched between SICA and MiPLATO-SiC as shown in Fig. 3 and 4.

[picture]

Fig. 4. EtaMax MiPLATO-SiC scan on an epi wafer shows various defects and classification based on PL peak lambda.

Fig. 4. EtaMax MiPLATO-SiC scan on an epi wafer shows various defects and classification based on PL peak lambda.

Individual defects were analyzed using 5 um spatial resolution for TRPL carrier lifetime as shown in Fig. 5. The area surrounding the defects has abrupt changes in spectrum and carrier lifetime. The carrier lifetime of normal epi area is longer than 70 ns and the carrier lifetime of most SF defect areas is about 20−60 ns.3C polytype inclusion related defect spots have the shortest lifetime as 20−40 ns. The carrier lifetime of substrate defects is shorter than 15 ns . These different carrier lifetimes of defects and materials enable dynamic PL to be more efficient in filtering out crystal defects than static PL imaging. Depending on epi structure and growth mechanism, band-edge carrier lifetime has some
differences. Relatively thicker structure has usually longer lifetime. These initial results show the potential advantage of utilizing carrier lifetime measurement to gain further insight into substrate and epi defects.

[picture]

Fig. 5. Time resolved photo luminescence (TRPL) shows the carrier lifetimes on defect areas with different peak lambda as shorter than the carrier lifetime of the defect free area.

Fig. 5. Time resolved photo luminescence (TRPL) shows the carrier lifetimes on defect areas with different peak lambda as shorter than the carrier lifetime of the defect free area.

Discussion

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

Lasertech SICA reveals typical SiC substrate defects and most of the epi defects. While Epi killer defects can be identified, it is not easy to correlate these killer defects to substrate defects. New metrology using pump- probe technology (TimeTech Spectra) and XRT (Rigaku) provide nondestructive mapping characterization of TSD, TED, and BPD on substrates. Spectroscopic PL characterization by Horiba's MiPLATO-SiC identifies all epi killer defects on various epi wafers, which can be correlated relatively well with substrate defects from SICA defects, TSD, TED, and BPD .
XRT section topography can be employed for detailed analysis by dissecting epitaxial wafers and tracing the origin of killer defects back to the substrate, as shown in Fig. 6. While this approach provides valuable insight, it is limited in capturing all killer defects across the wafer. Therefore, it serves best as a complementary, non-destructive technique for analyzing selected defects identified through XRT mapping.

[picture]

Fig. 6. XRT section topography tracks the killer defect from the top of thick epi film to the origin of substrate defect. The first three images are from Epi film and the next three images from substrate (proportional to propagational depths). This propagation indicates this defect as IGSF (In-Grown Stacking Faults), which originated from substrate and formed in the buffer layer during epi growth.

Fig. 6. XRT section topography tracks the killer defect from the top of thick epi film to the origin of substrate defect. The first three images are from Epi film and the next three images from substrate (proportional to propagational depths). This propagation indicates this defect as IGSF (In-Grown Stacking Faults), which originated from substrate and formed in the buffer layer during epi growth.

A combination of multiple characterization techniques enables more accurate detection and classification of killer defects. Using TRPL, the carrier lifetime of substrate and epi will be evaluated to confirm the formation and evolution of killer defects, like single Shockley SF (1SSF) from BPD. The evolution of defects from substrate to Epi is challenging and a subject of continued study.

Summary

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

This study employs advanced metrology techniques for analyzing defects in both SiC substrates and epitaxial layers. We present results from a non-destructive optical method that accurately detects and classifies BPD, TSD, and TED in substrates. Additionally, PL spectroscopy and TRPL measurements demonstrate enhanced capability to distinguish among various types of epitaxial defects. Together, these techniques enable more effective correlation between substrate and epitaxial defects, supporting improvements in material quality and yield.

References

The original version of this paper is available on https://www.scientific.net/DDF.452.87.pdf

Tsunenobu Kimoto, Material science and device physics in SiC technology for high-voltage power devices, Jpn. J. Appl. Phys. 54, 040103 (2015).

Chihiro Kawahara, Jun Suda, and Tsunenobu Kimoto, Identification of dislocations in 4H-SiC epitaxial layers and substrates using photoluminescence imaging, Jpn. J. Appl. Phys. 53, 020304 (2014).

Moonkyong Na, Wook Bahng, Hyundon Jung, Chanhyoung Oh, Donghyun Jang, and Soon-Ku Hong, Revisiting stacking fault identification based on the characteristic photoluminescence emission wavelengths of silicon carbide epitaxial wafers, Materials Science in Semiconductor Processing 175, 108247 (2024).

Moonkyong Na, Wook Bahng, Hyundon Jung, Chanhyoung Oh, Donghyun Jang, and Soon-Ku Hong, Observation of broad triangular Frank-type stacking faults and characterization of stacking faults with emission wavelengths below 430 nm in epitaxial layers, Appl. Phys. Lett. 124, 152109 (2024).

R. Leonard, M. Conrad, E. Van Brunt, J. Giles, E. Hutchins, and E. Balkas, From Wafers to Bits and Back again: Using Deep Learning to Accelerate the Development and Characterization of SiC, Materials Science Forum Submitted 1004 (2024) 321-327.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Defect and Diffusion Forum, ISSN: 1662-9507, Vol. 452, pp 93-99

doi: 10.4028/p-uu09Dm

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-22

Accepted:
2026-03-21

Online:
2026-05-18

Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

C. Calabretta 1,a, N. Piluso 1, b, R. Anzalone 1,c, E. Fontana 1, d, G. Maira 1,e, G. Bellocchi 1,f, M. S. Alessandrino 1, g, F. Vento 1, h, C. Nania 1,i, S. Adamo 1,j, S. Zappalà 2,k, G. DˋArrigo 2,I, E. Vitanza 1, m, N. Bentivenga 1,n, A. Russo 1,o, G. Arena 1,p, A. Severino 1,q

1 STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy

2 CNR-IMM, VIII Strada 5, Z.I., 95121 Catania, Italy

a  cristiano.calabretta01@st.com, b  nicolo.piluso@st.com, c  ruggero.anzalone@st.com, denzo.fontana@st.com, e  giovanni.maira@st.com, f  gabriele.bellocchi@st.com, g santi.alessandrino@st.com, h fabiana.vento@st.com, i chiara.nania@st.com, j salvatore.adamo@st.com, k sonia.zappala@imm.cnr.it, 'giuseppe.darrigo@imm.cnr.it, m elisa.vitanza@st.com, n nella.bentivegna@st.com, o alfio-lip.russo@st.com, p  giuseppe-ctn.arena@st.com, q  andrea.severino@st.com

Keywords: altair, candela, defects, Em.Mi, EWS, HTRB, KOH, profilometr, SEM, TEM.

Abstract

The fabrication of high-quality 4H−SiC epitaxial layers for power semiconductor devices involves complex processes including bulk crystal growth, wafer slicing, polishing, and chemical vapor deposition (CVD) epitaxy with precise step-flow control on slightly off-cut Si-face substrates. Despite advances, intrinsic crystallographic defects such as threading dislocations, basal plane dislocations, and stacking faults remain significant challenges, propagating into epitaxial layers and degrading device performance and reliability. This study examines defect types and their impact on 4H-SiC wafers, emphasizing the transition from 150 mm to 200 mm substrates, which introduces increased defect densities and polytype inclusions. Comprehensive defect characterization using advanced microscopy, molten KOH etching, and electrical wafer sorting reveals strong correlations between physical defects-such as micropipes, carrot-like stacking faults, and triangular 3C−SiC inclusions-and device failures, particularly under reliability stress tests like High Temperature Reverse Bias (HTRB). The findings highlight the critical role of substrate quality, epitaxial growth conditions, and defect mapping in improving yield and device robustness. This work underscores the necessity of integrating multi-scale defect inspection and targeted reliability assessments to optimize 4H−SiC power device manufacturing and performance.

Introduction

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

The fabrication of standard 4H−SiC wafers typically involves multiple stages: initially growing a bulk SiC crystal, followed by slicing this crystal into individual wafers, polishing the wafer surfaces, and finally conducting epitaxial layer growth. At present, CVD remains the exclusive method for producing 4H−SiC epitaxial layers (epilayers) used in power semiconductor devices. Achieving highquality homoepitaxial layers that preserve the 4H−SiC polytype relies on a technique known as "stepflow control." This method uses substrates cut at a slight angle-generally a few degrees off the {0001} basal plane-allowing the atomic stacking sequence to replicate along the advancing atomic steps [1]. Currently, wafers with a silicon-terminated (Si-face) surface and a 4∘ off-cut are predominantly utilized in the manufacture of 4H−SiC Schottky barrier diodes (SBDs) and metal-oxide-semiconductor field-effect transistors (MOSFETs). The standard CVD process employs hydrogen ( H2 ) as the carrier gas, silane ( SiH4 ) as the silicon precursor, and propane ( C3H8 ) as the carbon source. Alternatively, chlorine-containing gas mixtures-either by supplementing the standard gases with hydrogen chloride ( HCl ) or by using chlorine-based precursors-are also employed to modify growth conditions [2-3-4-5]. To meet device design requirements, the epitaxial layers must exhibit tightly controlled thickness and doping profiles, with uniformity maintained both
across individual wafers and between different wafers. One of the current industrial challenges is to develop techniques capable of producing 200 mm diameter 4H-SiC epilayers that combine excellent uniformity with minimal defect densities. Additionally, increasing the epitaxial growth rate or shortening the overall production cycle is desirable to boost manufacturing throughput.

Despite improvements, commercially available 4H−SiC substrates still contain significant densities of crystallographic defects, including threading dislocations and basal plane dislocations (BPDs). Threading dislocations are classified by their Burgers vectors: threading screw dislocations (TSDs) have Burgers vectors of either c or c+a, while threading edge dislocations (TEDs) possess Burgers vectors of a/3. Basal plane dislocations share the Burgers vector a/3[6−7−8]. Those threading dislocations with a c+a Burgers vector are often termed threading mixed dislocations (TMDs). During epitaxial growth, these dislocations propagate into the epilayer, with some altering their orientation or transforming into partial dislocations that generate Shockley Stacking Faults (SFs) [9] induce Frank-type stacking faults, prismatic defects, or complex stacking fault structures (commonly referred to as carrot-like defects) within the epitaxial layer, all of which impair electrical characteristics [1011].

Historically, micropipe defects were a major concern in SiC wafers, but advances have reduced their density to below 0.1 cm−2. Consequently, the focus has shifted toward dislocations and epitaxial growth-related defects, which now represent the primary obstacles to device reliability. While industrial inspection techniques efficiently detect most defects, dislocations remain challenging to identify comprehensively. Therefore, understanding the formation, propagation, and impact of these defects is vital, particularly regarding their role in device degradation after reliability stress.

Results and Discussion

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The role of extended crystallographic defects as electrically active centers promoting leakage current, electric field crowding, and premature breakdown in 4H−SiC power devices is well established [12]. Threading dislocations, micropipes, basal plane dislocations, and stacking faults have been shown to directly trigger degradation and catastrophic failure under high-voltage and hightemperature stress conditions. In the following, we experimentally correlate specific defect types with device failure modes observed after electrical stress.

The ongoing transition from 150 mm to 200 mm diameter SiC substrates introduces new challenges. Unlike 150 mm wafers, 200 mm substrates exhibit slightly increased densities of propagated stacking faults (bar-shaped SFs) and polytype inclusions [13-14].

In typical 150 mm commercial substrates, the density of TSDs ranges from about 2×102 cm−2, TEDs <1.5×103 cm−2, and BPDs <3×102 cm−2, while micropipe are nearly eliminated. In 8 inches the density of TSD is <2.5×102 cm−2, TED <2.5×102 cm−2, BPD<6×102 cm−2 and micropipes <0.1 cm−2.

Monocrystalline SiC substrates have been employed to investigate defect impacts on device performance. Reliability evaluations are indispensable in semiconductor manufacturing, designed to assess device robustness and longevity under various stress conditions. These tests are tailored to specific device technologies and anticipated failure modes. Among the standard reliability tests are High Temperature Reverse Bias (HTRB), High Temperature Gate Bias (HTGB), Dynamic Reverse Bias (DRB), and Body Diode Stress (BDS). These tests collectively inform lifetime and durability models.

Beyond process-induced electrical failures such as threshold voltage instability caused by suboptimal MOS interfaces [15], it is crucial to assess the influence of epitaxial defects on MOSFET device reliability. Failure analysis of 650 V MOSFETs post-reliability testing employs Emission Microscopy (Em.Mi.) to localize failure sites. Following localization, device layers are chemically stripped to expose the SiC surface, which is then subjected to molten KOH etching to reveal underlying defects. The etching process is conducted at 500∘C for 10 minutes, followed by optical microscopy for defect classification and correlation with electrical failures. This approach, optimized for n-type epitaxial layers with doping levels near 1.6×1016 atoms /cm3, provides reliable defect identification [16-17]. SiC wafers undergo comprehensive defect inspection using specialized inline metrology tools to identify defect-affected areas. These defects may be intrinsic to the material (e.g.,
carrots, comets, pits) or induced during processing. While process-related defects are linked to fabrication steps and screened accordingly, intrinsic defects require detailed classification to establish their correlation with device failure, quantified by the killer ratio.

[picture]

Fig. 1. (a-d) Altair images showing, a)micropipes, b-c-d) triangles, e) carrot, f) particle. g) Comparison demonstrating the overlap between the defect map output from Altair and the EWS map.

Fig. 1. (a-d) Altair images showing, a)micropipes, b-c-d) triangles, e) carrot, f) particle. g) Comparison demonstrating the overlap between the defect map output from Altair and the EWS map.

Key metrics such as Defective Die Percentage (DDP) and Total Usable Area (TUA) are employed to evaluate manufacturing yield and efficiency. Tools like Candela and Altair (KLA) utilize optical microscopy and scatter light methods, respectively, tailored for SiC inspection. Despite methodological differences, these tools generally show good agreement in defect detection, especially for surface and epitaxial defects including particles and micropipes. However, many buried substrate defects such as TSDs and BPDs evade detection by conventional methods, necessitating advanced techniques like X-Ray Topography (XRT), which is gaining recognition as a reliable, non-destructive tool for dislocation density measurement.

Material quality assessment often involves mapping device-sized grids to quantify defect impact via DDP after epitaxial growth. This metric predicts the expected failure rate per wafer. Testing wafers outside specification limits helps determine killer ratios for specific defect types.

Figure 1 reports many typical epitaxial defects detected through Altair inspection. Micropipes (Figure 1a), characterized as hollow-core screw dislocations, originate during ingot growth and extend through the wafer thickness, severely compromising device performance. Their evolution during Physical Vapor Transport (PVT) growth is intricate and not fully controlled. Attempts to mitigate micropipes via buffer layer optimization during epitaxial growth have not yielded significant reductions in device failure rates, especially concerning MOSFET blocking voltages. Consequently, micropipes remain a critical substrate-level issue. Triangular defects (TD) appear in three main morphological forms: TD-I, which features grains at its apex (Fig. 1b); TD-II, distinguished by micropits (Fig. 1c); and TD-III (Fig. 1d), characterized by a washboard-like surface texture. These defects arise from various causes, including foreign particles, micropipes within the substrate, and threading edge dislocations, all of which interfere with the epitaxial growth process. Comprehensive investigations employing techniques such as laser confocal microscopy, molten KOH etching, microwave plasma etching, Raman and photoluminescence spectroscopy, as well as high-resolution transmission electron microscopy, have shown that these defects consist of 3C-SiC polytype inclusions or Frank-type stacking faults. The interfaces between the 3 C and 4 H polytypes display both coherent and periodic arrangements, with twinning phenomena notably present in TD-III [18]. The development of these triangular defects is strongly associated with substrate flaws and irregularities in growth conditions, resulting in localized changes in polytype and stacking sequences. [19-20]. Complex stacking fault formations, historically termed carrot defects (Fig. 1e), mainly result from TSD propagation, though single or paired BPDs can also initiate such defects. This is supported by observations of BPD signatures following KOH etching of carrot defects. Fig. 1f reports the case of a particle embedded in the crystal at the end of epitaxial growth.

Aligning the Optical Microscopy (OM) map with Electrical Wafer Sorting (EWS) bins involves matching physical defects detected on the wafer surface, such as micropipes, stacking faults, and contamination, with the electrical test results assigned to each die. The colors on the EWS wafer map correspond to the different EWS bins, visually representing the electrical classification of each die. By ensuring both datasets share the same coordinate system and overlaying the OM defect map onto the colored EWS bin map, it becomes possible to identify correlations between defect locations and electrical performance variations or failures. This alignment facilitates effective root cause analysis, process improvements, and yield enhancement by directly linking specific physical defects to their electrical impact, thereby improving the quality and reliability of 4H−SiC power devices [21].

Both Candela and Altair (KLA) maps reveal elevated concentrations of epitaxial defects such as stacking fault complexes, topographic irregularities, and surface triangles adjacent to polytype regions. These defect clusters correlate strongly with EWS maps, where they cause catastrophic device failures as underlined by the superposition reported in Fig. 1g.

[picture]

Fig. 2. a) SEM image displaying a V-shaped feature on the surface of the TSD. b) AFM image in the same region c) SEM image providing a detailed view of the pit formed by the TSD. d) Crosssectional TEM image revealing the presence of the threading dislocation at the surface.

Fig. 2. a) SEM image displaying a V-shaped feature on the surface of the TSD. b) AFM image in the same region c) SEM image providing a detailed view of the pit formed by the TSD. d) Crosssectional TEM image revealing the presence of the threading dislocation at the surface.

Reliability testing, particularly HTRB, is extensively used to probe failure mechanisms and improve device robustness. HTRB involves applying reverse bias near maximum rated voltages and currents under elevated temperatures to stress device junctions, following JEDEC standards for power devices. In this study, devices were subjected to 520 V reverse bias at 140∘C for 30 hours. Devices failing this test underwent detailed failure analysis. Em.Mi. images highlighting failure locations postHTRB, with emission spots indicating regions of high leakage current within various device areas depending on electrical configuration. Emissions detected in IDSS mode often correspond to epitaxial layer defects.

Following device delayering, surface morphology was examined via SEM and AFM (Fig. 2(a-b)). High magnification SEM images in Em.Mi. hot spots reveal the pit V-shape typical of TSDs arising from substrate [22]. AFM identifies surface pitting consistent with step flow irregularities caused by threading screw dislocations during growth. These shallow depressions evidenced by AFM analysis of about 20 nm depth vary with growth conditions and can cause localized electric field crowding, degrading device performance and potentially leading to failure. SEM analysis particularly elucidated the emergence of a cone shape formed by the TSD as large as 3μ m (Fig. 2c) and cross TEM analysis observations TSDs in 4H-SiC crystals reveal that TSDs propagate roughly along the c-axis but often exhibit non-straight, winding dislocation lines with occasional deflections generating confirming the presence of surface pit. KOH etching at the die level confirmed the association between device failure and TSDs (Fig. 2d).

[picture]

Fig. 3. a) shows a die with the burn location highlighted in red, as identified by Em.Mi analysis in b). The optical profilometer image (c) reveals the hexagonal shape of the burn spot after molten KOH etching. The blue and red profiles illustrate the burn's lateral extent and increasing depth toward the center (d). Optical microscopy (e) captures the defect at various focal planes, clearly indicating that the burn originates from a micropipe, evidenced by the defocus observed at −24μ m.

Fig. 3. a) shows a die with the burn location highlighted in red, as identified by Em.Mi analysis in b). The optical profilometer image (c) reveals the hexagonal shape of the burn spot after molten KOH etching. The blue and red profiles illustrate the burn's lateral extent and increasing depth toward the center (d). Optical microscopy (e) captures the defect at various focal planes, clearly indicating that the burn originates from a micropipe, evidenced by the defocus observed at − 24 μ m .

Molten KOH etching is a cost-effective, destructive method for dislocation density assessment. Conducted at 500∘C in a nickel crucible, etching times are adjusted based on doping levels, differing between substrate and epitaxial layers. This technique effectively reveals dislocations that critically influence device reliability.

The detection of defects such as micropipes reveals that micropipe etch pits are significantly larger than those associated with threading screw dislocations (TSDs), primarily due to the larger Burgers vector of micropipes. Fig. 3 illustrates a hard device failure caused by a crystallographic defect. Leakage currents measured between drain-gate and gate-source terminals reveal short circuits. Em.Mi. pinpoints the emission site (Fig 3b), and subsequent chemical delayering exposes a hexagonal hole at the defect location. Optical profilometry analysis (Fig. 3c) further confirmed that these defects exhibit a hexagonal symmetrical structure aligned with the crystallographic axes. Profiling along marked lines (Fig. 3d) showed that the micropipe etch pits extend approximately 180μ m in diameter, with edge depths ranging from 2 to 7μ m, gradually tapering toward the center. In Fig. 3e Bright-field optical microscopy provided additional confirmation by revealing a distinct hole characteristic of micropipes when the focal plane was adjusted approximately 24μ m below the sample surface. Together, the hexagonal etch morphology and the observed subsurface hole definitively identify the defect as a micropipe determining localized high current density and thermal damage.

Conclusion

The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

This comprehensive review underscores the critical importance of defect inspection in SiC wafer production, particularly focusing on the identification and characterization of killer defects that significantly impact device performance and yield. The article systematically categorizes the diverse crystallographic and surface defects inherent to SiC wafers, such as threading screw and edge dislocations, basal plane dislocations, micropipes, stacking faults, and polytype inclusions, detailing their origins, morphologies, and detrimental effects on various SiC power devices including MOSFETs, Schottky diodes, and p−n junctions. A broad spectrum of inspection techniques, ranging from destructive methods like KOH etching and transmission electron microscopy to advanced nondestructive optical and electron-based modalities such as photoluminescence, X-ray topography, Raman spectroscopy, and mirror projection electron microscopy are increasingly becoming essential in terms of their resolution, throughput, and applicability for in-line production environments. The review highlights the complementary nature of these methods and advocates for integrated inspection systems that combine high-resolution imaging with rapid scanning capabilities, enhanced by machine learning algorithms for automated defect classification and mapping.

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The original version of this paper is available on https://www.scientific.net/DDF.452.93.pdf

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Chapter 3: Stacking Faults

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 1-9

doi: 10.4028/p-besU1w

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-29

Accepted:
2026-02-28

Online:
2026-05-18

Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

Kazumi Takano 1,a*, Yasuyuki Igarashi 1, b, Yohsuke Matsushita 1,c and Takuya Morita 1, d

1 ITES, 1-60 Kuribayashi, Otsu, Shiga 520-2151, Japan

a*kazumi_takano@ites.co.jp, byiga@ites.co.jp, cyohsuke_matsushita@ites.co.jp

dtakuya_morita@ites.co.jp 

Keywords: proton implantation, shockley-type stacking fault (SSF), photoluminescence (PL), UV irradiation.

Abstract

Proton implantation has been reported as an effective approach for suppressing bipolar degradation in 4H−SiC; however, implantation inevitably introduces lattice damage and point defects. In this work, we investigate: (i) suppression of Shockley-type stacking fault (SSF) expansion in both the proton-implanted layer and the region beyond the implanted layer, and (ii) adverse effects associated with proton implantation. Half of an n -type 4H−SiC epitaxial wafer was implanted with protons ( 350keV,1×1013 cm−2 ) and annealed at 1600∘C for 30 min for dopant activation with carbon capping. SSF expansion was induced by UV laser irradiation, and photoluminescence (PL) imaging was used to quantify SSF width and observe cross sections. The proton-implanted region exhibited clearly reduced SSF expansion, with the expanded SSF width typically about 30μ m smaller than that in the non-implanted region; cross-sectional PL further confirmed that SSFs did not propagate into the near-surface implanted layer. Additional experiments with varied implantation depth and dose revealed a linear relationship between SSF width and active drift-layer thickness (defined as the driftlayer thickness minus the proton implantation depth), consistent with geometric expectations from the wafer off-cut. However, PL observations also showed anomalous SSF morphologies and evidence of dislocations, indicating that proton implantation can generate new SSF nucleation sites. Furthermore, the band-to-band PL peak intensity decreased after implantation and did not recover after the activation anneal, suggesting persistent lattice damage, including in proton-traversed regions. These results highlight a trade-off between SSF-suppression benefits and implantationinduced degradation.

Introduction

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Ion implantation has long been recognized as a key technology for forming semiconductor junctions. Around 1950, R. S. Ohl and W. Shockley at Bell Telephone Laboratories patented the concept of creating junction layers using ion implantation [1,2]. In SiC (silicon carbide), in particular, p−n junction formation by thermal diffusion is extremely difficult; consequently, ion implantation is indispensable for device fabrication. Beyond junction formation, proton implantation has also been proposed as an effective means of suppressing bipolar degradation in 4H−SiC devices. Kato et al. demonstrated that bipolar degradation can be mitigated by proton implantation at doses exceeding 1×1012 cm−2, using simple PiN diodes subjected to pulsed current stress of approximately 200 A/cm2 [3,4]. They initially attributed the suppression mechanism mainly to the pinning of partial dislocations (PDs) by hydrogen and implantation-induced point defects, and therefore targeted proton implantation near the epitaxial/substrate interface, where basal-plane-related defects are prevalent.

Subsequent studies expanded the scope of proton implantation designs and revealed both beneficial and potentially adverse effects. Amishiro et al. fabricated SiC MOSFETs incorporating a sandwich-structured proton-implanted layer within the drift region and applied current stress of 420 A/cm2. They reported that the width of Shockley-type stacking faults (SSFs) became slightly narrower in the region beneath the proton-implanted layer [5]. In contrast, Uchida et al. reported that proton implantation into the top 0.5μ m of the drift layer significantly increased the concentration of Z1/2
point defects, and that the carrier lifetime did not recover even after activation annealing [6]. These reports indicate that while proton implantation can suppress degradation-related defect evolution, it also introduces lattice damage that may persist after high-temperature annealing. Bipolar degradation in 4H−SiC is closely linked to the expansion of SSFs originating from basal plane dislocations (BPDs). Such expansion is known to proceed via recombination-enhanced dislocation glide (REDG), where the recombination energy of injected electron-hole pairs acts as the driving force for dislocation motion and SSF growth. Conventionally, SSF expansion has often been evaluated using PiN diodes under current conduction (Fig. 1), where electrons and holes are injected into the drift region. However, when the primary objective is to isolate and evaluate the effect of proton implantation itself, the expansion-visualization-contraction (EVC) method (Fig. 2) [7] provides a simpler and effective alternative: electron-hole pairs can be generated by ultraviolet irradiation without fabricating PiN structures on epitaxial substrates. A critical point in proton implantation is that lattice damage is not confined to the intended implanted layer. In the drift region, proton implantation induces defects such as Z1/2 in the implanted layer. Moreover, when protons are implanted from the surface side, the layers traversed by protons prior to reaching the projected range are also expected to experience lattice damage. Therefore, suppression of bipolar degradation may occur not only in the implanted layer but also in these proton-traversed regions (Fig. 3). In our previous studies, degradation suppression was observed immediately after implantation and remained even after activation annealing, suggesting that persistent implantation-induced lattice damage may play a role beyond simply suppressing SSF expansion.
In this study, we investigate, using the EVC method, suppression of SSF expansion in the width direction in both the proton-implanted layer and the proton-traversed layer, and we further examine adverse effects associated with proton implantation. By correlating SSF behavior with implantation conditions and defect-related optical signatures, we aim to clarify the trade-off between SSFsuppression benefits and implantation-induced degradation.

[picture]

Fig. 1. Accelerated pulsed-current stress.

Fig. 1. Accelerated pulsed-current stress.

[picture]

Fig. 3. Proton Implantation.

Fig. 3. Proton Implantation.

[picture]

Fig. 2. EVC Screening.

Fig. 2. EVC Screening.

[picture]

Fig. 4. Calculation result by SRIM 2013.

Fig. 4. Calculation result by SRIM 2013.

Experiment 1: Experimental Procedure

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(1) Epitaxial wafers and proton implantation

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Two commercial n-type 4H-SiC epitaxial wafers (off-cut angle: 4∘ ) were used in this study. Epitaxial wafer A was a 100−mm-diameter 4H−SiC epi-wafer consisting of a heavily nitrogen-doped buffer layer (thickness: 1μ m; ND=1×1018 cm−3 ) and a lightly doped drift layer (thickness: 10μ m; ND=8×1015 cm−3 ). Protons were implanted into one half of the wafer surface (implantation energy: 350 keV ; dose: 1×1013 cm−2 ). After implantation, activation annealing was performed at 1600∘C for 30 min with carbon capping. The proton depth distribution in SiC was simulated using SRIM. The simulation indicates that the peak proton concentration is located at a depth of 2.5μ m from the incident surface, and the detailed depth profile is shown in Fig. 4.

Epitaxial wafer B was a 150−mm-diameter 4H−SiC epi-wafer with a heavily nitrogen-doped buffer layer (thickness: 3μ m; ND=1×1018 cm−3 ) and a lightly doped drift layer (thickness: 19μ m; ND=4.5×1015 cm−3 ). To clarify the relationship between SSF width and proton implantation conditions, four implantation conditions were prepared by combining two doses ( 1×1012 and 1×1015 cm−2 ) and two target depths (5μ m and 15μ m). (The target depth was adjusted by decelerating protons as they passed through aluminum foil, but details remain undisclosed).

(2) UV laser irradiation for inducing SSF expansion (EVC method)

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To induce SSF expansion, UV laser irradiation was performed based on the EVC method. The UV laser was the third harmonic of a YAG laser (wavelength: 355 nm ; repetition rate: 50 kHz ; pulse width: 20 ns ). To adjust the irradiance, the beam diameter was set to 1 mm(1240 W/cm2) and 3 mm (100 W/cm2). The irradiation area was scanned using the following two protocols:

Protocol 1(10×10 mm area): A linear scan at 3 mm/s with 15μ m line spacing over a 10×10 mm area for 4 h . The scanned area was centered on the boundary between the proton-implanted and unimplanted regions so that both regions were included in the same irradiation field.

Protocol 2 (four 5×5 mm areas): A linear scan at 1 mm/s with 15μ m line spacing over four nonadjacent, independent 5×5 mm areas for 3 h .

(3) Photoluminescence (PL) imaging and SSF-width measurement

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

Expanded SSFs were evaluated by photoluminescence (PL) imaging. An ultra-high-pressure mercury lamp was used as the excitation source. The excitation light was passed through a cut-off filter to remove wavelengths below 350 nm . PL images were acquired at an observation wavelength of 420 nm using a 1 -megapixel cooled CMOS camera, providing a pixel resolution of approximately 1μ m. For the four regions irradiated under Protocol 2 (Section 2.2), the widths of ten SSFs in each region (i.e., 40 SSFs in total) were measured from the PL images to compare SSF expansion behavior among regions.

(4) Cross section sample preparation and cross-sectional PL observation

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

Cross section specimens were prepared from the 10×10 mm irradiation area used in Protocol 1 (Section 2.2). To investigate the depth-wise positions of the expanded SSFs, cross-sectional PL imaging was performed for two representative SSFs.

[picture]

Fig. 5. Expansion by UV laser irradiation.

Fig. 5. Expansion by UV laser irradiation.

Result 1: Surface and Cross-Sectional PL Imaging

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

Fig. 6 shows PL images of a 10×10 mm2 area with and without proton implantation. Fewer stripelike features were observed in the proton-implanted region, indicating suppressed expansion of barshaped Shockley-type stacking faults (SSFs) in the epitaxial layer. Consistently, the expanded SSF width in the proton-implanted region was approximately 30μ m smaller than that in the non-implanted region. Cross-sectional PL imaging (Fig. 7) further confirmed that SSFs did not propagate into the near-surface layer where protons were implanted.

For statistical evaluation, a two-sample t-test was performed using the widths of 10 SSFs measured within the same 5×5 mm2 area for each condition. As summarized in Table 1 and Fig. 8, a clear difference in SSF width was observed irrespective of the UV irradiance. The obtained p-values ( 1.03×10−17 and 2.56×10−16 ) indicate that the difference is statistically significant. These results demonstrate that proton implantation yields a consistent reduction in SSF expansion, regardless of the UV irradiation dose.

[picture]

Fig. 6. PL imaging after UV irradiation.

Fig. 6. PL imaging after UV irradiation.

[picture]

Fig. 7. Cross-section PL imaging.
Table 1. Test for the Difference of Means.

Fig. 7. Cross-section PL imaging. Table 1. Test for the Difference of Means.

[picture]

Fig. 8. PL image using BPF 420 nm .

Fig. 8. PL image using BPF 420 nm .

Experiments using epitaxial wafer B showed no measurable change in SSF width at an implantation dose of 1×1012 cm−2. At a higher dose of 1×1015 cm−2, the band-to-band PL emission was significantly weakened, which hindered observation of the buffer layer. Although previous results indicate that SSFs can also expand into the buffer layer, the present analysis focuses on SSF expansion within the drift layer.
Fig. 9 and Table 2 plot the relationship between the active drift-layer thickness (defined as the driftlayer thickness minus the proton implantation depth) and the SSF width for wafers A and B. A clear linear correlation is observed. The extracted slope was 13.7, which is close to the theoretical value of 14.2 calculated from the 4∘ off-cut angle using Eq. (1).
Width of SSF = Active drift-layer thickness / tan (Off-cut angle)

Table 2. Expansion Result.

| Drift layer | Proton Depth | Proton Density | Active layer | Width of SSF
wafer A | 10 | 0 | E12 | 10 | 149
2.5 | E12 | 7.5 | 107
wafer B | 19 | 5 | E15 | 14 | 200
15 | E15 | 4 | 44
| unit : μm |  | unit : cm⁻² |  |

[picture]

Fig. 9. Width of SSF.

Fig. 9. Width of SSF.

Experiment and Result 2: Adverse Effect

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

As summarized in Table 1, the expanded SSFs in the non-implanted region showed a nearly constant width of approximately 150μ m, suggesting that SSF expansion occurred across the entire epitaxial layer. The apparent initiation points of SSF expansion were located either at the epitaxial/substrate interface or at the surface, and no initiation was observed in the middle of the epitaxial layer under the present observation conditions.

In the proton-implanted region, the SSF width was approximately 120μ m, which is comparable to the expansion length from the epitaxial/substrate interface to the lower boundary of the implanted layer. This is consistent with the notion that the implanted layer suppresses surface-initiated SSF expansion. Based on this suppression behavior, we expected that SSF expansion would predominantly originate from the epitaxial/substrate interface as shown in Fig. 10(a). However, SSFs with atypical morphologies, as exemplified in Fig. 10(b), were also observed (Fig. 11(a) yellow arrow). The SSFs observed in Fig. 8 were classified, and the results are summarized in Table 3.

[picture]

Fig. 10. Schematic Diagram of SSF.

Fig. 10. Schematic Diagram of SSF.

[picture]

Fig. 11. PL image.

Fig. 11. PL image.

Table 3. SSF Classification.

Expansion from | Fig.8 (a) | Fig.8 (b) | Fig.8 (c) | Fig.8 (d)
Surface side | 13 | 10 | 9 | 10
Substrate side | 15 | 13 | 14 | 15

To further examine possible initiation sites for SSF expansion, dislocation lines were imaged at wavelengths ≥700 nm. Carbon-core dislocations, which have been reported as potential initiation sites for SSF expansion, were observed not only near the epitaxial/substrate interface but also near the lower boundary of the proton-implanted layer (Fig. 11(b)). Because prior PL observations did not show BPDs at this position, the presence of carbon-core dislocations at this depth suggests that proton implantation may have introduced or activated defect structures relevant to SSF nucleation. Although the mechanism remains unclear, these results indicate a potential adverse effect whereby implantation-induced damage could facilitate additional SSF nucleation pathways.

Discussion

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The band-to-band emission peak at 390 nm in the PL spectrum is often used as a qualitative indicator of crystal quality; therefore, lattice damage introduced by ion implantation may manifest as a decrease in this peak intensity. Fig. 12 shows the PL spectra of wafer B measured before implantation, after proton implantation, and after activation annealing. After proton implantation, the band-to-band peak intensity decreased, and samples with higher doping concentrations exhibited lower peak heights (Fig. 12(a)). Fig. 12(b) presents the spectra after activation annealing; the band-to-band peak height was comparable to that measured immediately after implantation. Under the present annealing conditions, these observations suggest limited recovery of implantation-induced damage, which may be consistent with the persistence of the SSF-expansion suppression effect observed in our experiments.
In addition, as shown in Fig. 12(c), even at the same doping concentration, deeper implantation conditions were associated with lower band-to-band peak intensities. This trend suggests that residual lattice damage may extend beyond the nominal implanted layer into regions along the proton trajectory. Further investigation will be needed to determine the dominant defects responsible for the observed PL degradation.

[picture]

Fig. 12. PL spectrum.

Fig. 12. PL spectrum.

In contrast, the adverse effect (the appearance of additional nucleation sites) was not clearly observed in proton-traversed regions, but was observed primarily in regions where protons are expected to stop (i.e., near the peak of the implanted proton distribution). This suggests that, within the present doping range (approximately 1012−1015 cm−2 ), the nature of implantation-related damage may differ between the traversed and stopping regions. In the stopping region, hydrogen can accumulate locally; if the local concentration exceeds the solubility limit, hydrogen-related voiding and/or crack-like mechanical damage (microcrack-like damage) may occur in addition to point defects. However, we did not directly confirm the presence of actual cracks in this study. Such cracklike damage can generate stress fields distinct from those associated with point defects and may
influence defect formation and SSF nucleation. Therefore, the atypical SSF morphologies and the inferred increase in nucleation sites observed in this study may reflect a combination of electronic effects from point defects and crack-like mechanical damage associated with proton stopping.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

Using a UV-irradiation-based EVC method and PL imaging, we demonstrated that proton implantation suppresses SSF expansion in 4H-SiC epilayers. The SSF width in implanted regions was reduced (e.g., from approximately 150μ m to 120μ m in typical areas), and cross-sectional PL imaging confirmed that SSFs did not propagate into the near-surface region corresponding to the implanted layer. Moreover, the SSF width exhibited an approximately linear dependence on the effective driftlayer thickness, with a slope close to that expected from the 4∘ off-cut geometry. These results support the interpretation that the implanted layer acts as a barrier that limits SSF propagation.

At the same time, our observations suggest important adverse effects. The presence of atypical SSF morphologies and dislocation-related signatures indicates that proton implantation may introduce additional SSF nucleation sites, rather than solely pinning pre-existing partial dislocations. PL spectroscopy further showed that the band-to-band emission peak intensity decreased after proton implantation and remained low after activation annealing, suggesting limited recovery of implantation-induced lattice damage. The dependence on implantation depth also implies that residual damage may extend into regions traversed by protons.

Overall, proton implantation provides measurable suppression of SSF expansion, but it can also introduce persistent damage and potentially new defect-generation pathways. Therefore, optimization of implantation dose and depth, together with evaluation of both suppression efficacy and implantation-induced degradation, is essential for reliable application of this approach in 4H-SiC devices.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

METI R&D Support Program for Growth Oriented Technology SMEs Grant Number JPJ005698.

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.1.pdf

W. Shockley, US Patent 2,666,814. (1949).

R.S. Ohl, US Patent 2,750,541. (1950).

Masashi Kato, Ohga Watanabe, Toshiki Mii, Hitoshi Sakane, Shunta Harada, Scientific Reports 12, 18790 (2022).

Shunta Harada, Toshiki Mii, Hitoshi Sakane, Masashi Kato, Scientific Reports 12, 13542 (2022).

Kazuya Ishibashi, Naoki Shikama, Hiroki Niwa, Takanori Tanaka, Hiroyuki Amishiro, Akifumi Imai, Katsutoshi Sugawara, Solid State Phenomena Vol. 376, pp. 33-40, (2025).

H. Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, Y. Higashi, H. Sezaki, S. Harada and K. Kojima Solid State Phenomena Vol. 375, pp. 21-27, (2025).

Yasuyuki Igarashi, Kazumi Takano, Yohsuke Matsushita, Chiyomi Shibata, Defect and Diffusion Forum Vol. 425, pp. 75-82, (2023).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 11-17

doi: 10.4028/p-yp6sOF

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-01-31

Online:
2026-05-18

Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

The original version of this paper is available on https://www.scientific.net/MSF.1190.11.pdf

Hiroki Niwa 1,a*, Takanori Tanaka 2,b, Kazuya Tojima 2,c, Hiroyuki Amishiro 1,d, Yasuhiro Kagawa 2,e, Katsutoshi Sugawara 1,f and Tatsuro Watahiki 1, g

1 Advanced Technology R&D Center, Mitsubishi Electric Corp., Tsukaguchi-Honmachi 8-1-1, Amagasaki, Hyogo, 661-8661, JAPAN

2 Power Device Works, Mitsubishi Electric Corp., Imajuku-Higashi 1-1-1, Nishi-ku, Fukuoka, 8190192, JAPAN

a*Niwa.Hiroki@dp.MitsubishiElectric.co.jp, b Tanaka.Takanori@cb.MitsubishiElectric.co.jp, c  Ishibashi.Kazuya@ak.MitsubishiElectric.co.jp, d Amishiro.Hiroyuki@cb.MitsubishiElectric.co.jp, èKagawa.Yasuhiro@cj.MitsubishiElectric.co.jp,  fSugawara.Katsutoshi@ea.MitsubishiElectric.co.jp, g  Watahiki.Tatsuro@dx.MitsubishiElectric.co.jp

Keywords: body diode, bipolar degradation, leakage current degradation, in-grown stacking fault, BPD, failure analysis, PL imaging.

Abstract

This study investigates the role of in-grown stacking faults (SF) in the bipolar degradation of 3.3 kV SiC-MOSFETs, emphasizing their significant contribution to both on-resistance ( VDSon  ) and leakage current ( IDSX  ) degradation. A high current stress was applied to over 1,500 chips, resulting in 72 degraded devices, with 45 exhibiting notable IDSX  degradation. A detailed analysis revealed that most IDSX  degraded chips contained bar-shaped in-grown SFs, suggesting a correlation between these defects and leakage current degradation. These findings indicate that peculiar basal plane dislocations associated with in-grown SFs may be critical contributors to IDSX degradation, indicating the need for further research to elucidate the mechanisms behind this degradation in SiC-MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.11.pdf

For many years, bipolar degradation has been one of the most important reliability issues in SiC MOSFETs [1-3]. In this phenomenon, Shockley-type stacking faults (SSFs) expand from basal plane dislocations (BPDs) during bipolar operation. For SiC-MOSFETs, this occurs during conduction through the body diode (BD), which leads to an increase in the on-resistance or forward voltage drop ( VDSon  of the MOSFET and VSDon  of the BD) and/or the leakage current during blocking mode ( IDSX  ) [4]. Most studies have focuses on VDSon  degradation, with very few addressing IDSX  degradation [47]. Idsx degradation does not always occur when SSFs expand, and its origin remains unclear.

Recently, expanded SSFs from BPDs gliding out from micropipes have been found to cause IDSX degradation after stressing more than 1,500 MOSFETs and analyzing degraded chips [8]. Indeed, all the IDSx degradations were attributed to SSFs originating from micropipes; they did not occur in SSFs from commonly observed BPDs within the substrate. A similar phenomenon has been observed in a few studies on IDSX degradation, which occurred in PiN diodes with half-loop arrays or BPDs owing to implantation damage [5, 6]. Therefore, IDSX degradation appears to occur in SSFs originating from some peculiar BPDs, such as interfacial dislocations or half-loop arrays, but not from SSFs expanding from BPDs inside the substrate.

Although peculiar BPDs may be the cause of IDSX degradation, the question remains as to whether other defects may cause it. In this study, we identify defects causing IDSX degradation in addition to known ones, such as micropipes. High-current stress was applied to the BD of 3.3 kV SiC-MOSFETs, and chips with bipolar degradation were identified. These degraded MOSFETs, especially the IDSx degraded MOSFETs, were analyzed in detail, and the crystal defects responsible for this degradation phenomenon were identified.

Experimental

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Figure 1 (a) shows the planar-type 3.3 kV SiC -MOSFET fabricated on an n+-type 4 H -SiC substrate prepared in this study. The size of the MOSFET was approximately 9×8 mm2. A different substrate vendor was used compared to the one in the previous study [8]. As the types and densities of crystal defects within the substrate differed by vendor, there is a higher possibility of obtaining new insights into the degradation phenomenon. During device fabrication, defect inspection using photoluminescence (PL) was performed after epitaxial growth and activation annealing. Figure 1 (b) illustrates the experimental flow of this study. After the device fabrication, an initial chip test was conducted to select "good" chips for the BD experiment. These "good" chips exhibited no abnormal I−V characteristics or signs of degradation. Subsequently, a high DC current stress of 300 A/cm2 at ~175∘C was applied to the BD of each chip. In the following chip test, chips with increased leakage current compared to the initial test were characterized as "IDSX degraded chips," while those showing only an increase in VDSon  (without IDSX  degradation) were characterized as " VDSon  degraded chips."

For the failure analysis of VDSon  degraded chips, PL imaging was performed after removing the electrodes and gate structures to analyze the expanded SSF. For IDSx degraded chips, the points of abnormal leakage were first identified using photoemission microscopy from the backside of the chip after removing the backside electrode. PL imaging was then performed after removing the frontside electrode and gate structures to analyze the expanded SSF. The results of photoemission microscopy and PL imaging were overlaid to identify the crystal defects causing abnormal leakage. For both types of degraded chips, the defect inspection results from the device fabrication process were reviewed, and the crystal defects responsible for the degradation were determined.

[picture]

Fig. 1. (a) Schematic cross-section of the planar-type 3.3 kV SiC-MOSFET investigated in this study. (b) Flow-chart of the experimental procedure. During failure analysis, photoemission microscopy and PL imaging were conducted to identify the crystal defects.

Fig. 1. (a) Schematic cross-section of the planar-type 3.3 kV SiC-MOSFET investigated in this study. (b) Flow-chart of the experimental procedure. During failure analysis, photoemission microscopy and PL imaging were conducted to identify the crystal defects.

Result of Body Diode Stress Test

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In this study, body diode stress was applied to more than 1,500 chips, and 72 were found to be degraded: 27 chips exhibited VDSon  degradation with no IDSX  degradation observed, and 45 chips exhibited IDSX degradation. Figure 2 shows the I−V characteristics of some of the IDSX degraded chips, where an abnormal leakage current can be observed. Failure analysis was conducted on these degraded chips to identify the origin of the degradation.

[picture]

Fig. 2. Leakage current characteristics of IDSX degraded chips. The compliance current in the measurement was set to 20μ A.

Fig. 2. Leakage current characteristics of IDSX degraded chips. The compliance current in the measurement was set to 20 μ A .

Analysis of Chips with Bipolar Degradation

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VDSonDegraded Chips.

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PL imaging was conducted on all VDSon  degraded chips, and the origin of the expanded SSFs was analyzed. Some of the PL images are presented in Fig. 3. Although most SSFs were caused by BPDs within the substrate (Fig. 3 (a)) or micropipes (Fig. 3 (b)), approximately 18% of the SSFs were attributed to in-grown stacking faults (SFs) (Fig. 3 (c)). In the PL image, the black SFs represent the in-grown SFs, while the white SFs represent the expanded SSFs. Such an expansion from an in-grown SF has been reported in recent years, where a BPD included in an in-grown SF became the nucleation source of SSFs [9]. The proportion of SSFs caused by in-grown SFs is significant and is a major contributor to VDSon  degradation.

[picture]

Fig. 3. PL images of VDSon  degraded chips with various origins of SSF. (a) SSF caused by BPDs within the substrate. (b) SSF caused by micropipe. (c) SSF caused by in-grown SF.

Fig. 3. PL images of V DSon degraded chips with various origins of SSF. (a) SSF caused by BPDs within the substrate. (b) SSF caused by micropipe. (c) SSF caused by in-grown SF.

I DSX Degraded Chips.

The original version of this paper is available on https://www.scientific.net/MSF.1190.11.pdf

Initially, the defect inspection results were reviewed to select chips for detailed analysis. Table 1 list the defect inspection results for each IDSX  degraded chip. Notably, most chips did not contain micropipes, as in a previous study [8], yet IDSX degradation still occurred. Upon closer examination, most chips were found to contain a bar-shaped in-grown SF, as shown in Fig. 4 (a). For those chips without bar-shaped in-grown SFs, triangular in-grown SFs were still present, as shown in Fig. 4 (b), suggesting in-grown SF has also caused the I DSX degradation. Therefore, some chips with bar-shaped in-grown SFs and all chips without bar-shaped in-grown SFs were selected for analysis to confirm it.

Table 1. Defect inspection results of IDSX  degraded chips.

With micropipe | 2 pcs
With bar-shaped in-grown SF | 38 pcs
Without micropipe | Without bar-shaped in-grown SF | 5 pcs

[picture]

Fig. 4. PL images of in-grown SF obtained by the defect inspection ( λ>660 nm ) during device fabrication. (a) Bar-shaped in-grown SF. (b) Triangular in-grown SF.

Fig. 4. PL images of in-grown SF obtained by the defect inspection ( λ > 660 n m ) during device fabrication. (a) Bar-shaped in-grown SF. (b) Triangular in-grown SF.

Figure 5 shows the failure analysis results of the IDSX  degraded chips. The IDSX  degraded chips were analyzed using photoemission microscopy and PL imaging to identify the source of abnormal leakage. In this chip, there was no micropipe, but a bar-shaped in-grown SF was present. After the BD stress, a white bar-shaped SF indicating the expanded SSFs was observed, having expanded from the bar-shaped in-grown SF. This indicates that bipolar degradation occurred because of the in-grown SF . Furthermore, the results of photoemission analysis revealed that abnormal leakage occurred along the black lines inside the bar-shaped SF, indicating that IDSX degradation also occurred because of the bar-shaped in-grown SF.

[picture]

Fig. 5. PL images and photoemission microscopy results of IDSX degraded chip with bar-shaped in-grown SF .

Fig. 5. PL images and photoemission microscopy results of I D S X degraded chip with bar-shaped in-grown SF .

Figure 6 shows the analysis results of the other IDsx degraded chips. As shown in Fig. 6 (a), there was a bar-shaped in-grown SF. However, after the BD stress, the long bar-shaped SSF expanding outside the in-grown SF was not observed, as shown in Fig. 5. Nevertheless, abnormal leakage occurred inside the in-grown SF. Although the bar-shaped SSF was not observed, SSFs other than the bar-shaped may have expanded inside the in-grown SF, causing the leakage current degradation for this chip. Because the expanded SSFs and in-grown SF may overlap, it was difficult to observe the SSFs. As shown in Fig. 6 (b), there was a triangular in-grown SF, but not a bar-shaped one. After the BD stress, a triangular SSF expanded outside the in-grown SF, and multiple emission points were observed inside the in-grown SF .

[picture]

Fig. 6. PL images and photoemission microscopy results of IDsx degraded chip. (a) Chip with bar-shaped in-grown SF, but without SSF expanding outside it. (b) Chip with triangular ingrown SF.

Fig. 6. PL images and photoemission microscopy results of I D s x degraded chip. (a) Chip with bar-shaped in-grown SF, but without SSF expanding outside it. (b) Chip with triangular ingrown SF.

A total of 10IDSX  degraded chips were analyzed. It was confirmed that all the abnormal leakage occurred from in-grown SFs in various ways, as shown in Figs. 5 and 6, regardless of the shape or expansion behaviors of the in-grown SFs and SSFs. All the chips without the bar-shaped in-grown SFs exhibited abnormal leakage from triangular in-grown SF. This indicates that most of the IDSX degradation observed in this study was also due to in-grown SFs, as most of the degraded chips contained a bar-shaped in-grown SFs inside the chip. Moreover, in this study, all chips containing bar-shaped in-grown SFs exhibited IDSx degradation after BD stress. By contrast, most triangular ingrown SFs did not induce IDSX  degradation. These results indicate that bar-shaped in-grown SFs are major contributors to IDSX  degradation.

Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.11.pdf

From the analysis of IDSx degraded chips in the previous section, it was found that in-grown SFs can cause IDSX  degradation. This raises the question of whether there are similarities with previous reports. In the case of IDSX degradation caused by micropipes, abnormal leakage occurred at the SF originating from BPDs gliding out of the micropipe [8], which were referred to as peculiar BPDs. Therefore, the defect inspection results of in-grown SFs causing IDSX  degradation were re-examined to confirm whether such BPDs existed in this study. Figure 7 shows an enlarged view of the barshaped in-grown SFs depicted in Fig. 5. White lines moved after activation annealing, indicating the gliding of BPDs. This suggests that peculiar BPDs, likely interfacial dislocations, were also observed inside in-grown SFs. In fact, all bar-shaped in-grown SFs of the IDSX degraded chips were reexamined, and it was found that most of them contained gliding BPDs inside the in-grown SF. Therefore, SSFs originating from peculiar BPDs accompanied by the in-grown SFs may have caused
the abnormal leakage, similar to the case of micropipes. In the case of chips with bar-shaped in-grown SFs without gliding BPDs, this may be because the gliding BPDs and some portion of the in-grown SFs have overlapped, making it difficult to observe them during defect inspection. However, these results further suggest that certain peculiar BPDs are responsible for IDSX degradation. More studies will be needed to identify the specific structure of these BPDs or SSFs that induced abnormal leakage to clarify the origin of the leakage current degradation.

[picture]

Fig. 7. Enlarged view of the bar-shaped in-grown SF causing IDSX  degradation shown in Fig. 5.

Fig. 7. Enlarged view of the bar-shaped in-grown SF causing I DSX degradation shown in Fig. 5.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1190.11.pdf

This study investigated the impact of in-grown SFs on bipolar degradation in 3.3 kV SiC-MOSFETs, identifying these as significant contributors to IDSX degradation. A comprehensive analysis of over 1,500 chips subjected to high-current stress revealed that 72 devices exhibited degradation, with 45 specifically exhibiting IDSX  degradation. A detailed failure analysis indicated that most IDSX  degraded chips contained bar-shaped in-grown SFs, suggesting a link between these defects and abnormal leakage currents. This study highlighted the potential role of peculiar BPDs associated with in-grown SFs in the degradation process. These findings underscore the necessity of further research to elucidate the mechanisms underlying the bipolar degradation in SiC-MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.11.pdf

A. Galeckas, J. Linnros, and P. Pirouz, Appl. Phys. Lett., vol. 81 (2002), p. 883.

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S. A. Mancini, S. Y. Jang, Z. Chen, D. Kim, J. Lynch, Y. Liu, B. Raghothamachar, M. Kang, A. Agarwal, N. Mahadik, R. Stahlbush, M. Dudley, and W. Sung, Proc. IRPS 2022, p. 62-1.

T. Ishigaki, T. Murata, K. Kinoshita, T. Morikawa, T. Oda, R. Fujita, K. Konishi, Y. Mori, and A. Shima, Proc. ISPSD 2019, p. 259.

H. Niwa, T. Tanaka, K. Ishibashi, H. Amishiro, A. Imai, Y. Kagawa, K. Sugawara, and T. Watahiki, Solid State Phenomena, vol. 375 (2025), p. 63.

E. Kodolitsch, A. Kabakow, V. Sodan, M. Krieger, H. Weber, and N. Tsavdaris, J. Phys. D: Appl. Phys., vol. 56 (2023) p. 315101.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 19-25

doi: 10.4028/p-2nuhGa

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-24

Accepted:
2026-02-23

Online:
2026-05-18

Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1190.19.pdf

N. Kölbel 1,a*, B. Kallinger 2,b, C. Kranert 2,c, St. G. Müller 2,d, A. Fuchs 2,e, T. Erlbacher 3,f, F. Faisal 3, g, J. Schulze 1,2, h

¹Friedrich-Alexander-Universität Erlangen-Nürnberg, Lehrstuhl für Elektronische Bauelemente, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer IISB, Schottkystraße 10, 91058 Erlangen, Germany

3 Nexperia Deutschland GmbH, Stresemannallee 101, 22529 Hamburg, Germany

a*nadja.koelbel@fau.de,b birgit.kallinger@iisb.fraunhofer.de, c christian.kranert@iisb.fraunhofer.de, 

d stephan.mueller@iisb.fraunhofer.de, e alesa.fuchs@iisb.fraunhofer.de,

Keywords: stacking faults, device failure, defect, ion implant, photoluminescence, yield.

Abstract

The yield of power electronic devices is influenced by many factors including crystal defects like stacking faults (SFs). There are different types of stacking faults but their influence on the finished device and its performance and the behavior of SF during processing is not fully understood yet. With our contribution, we shed light on the issue, showing four different optically characterized subtypes of SFs with different electrical behavior that can already be found after implantation and wafer annealing in photoluminescence (UVPL) imaging. This enables a distinction between different SF classes without the need for a finally processed device and the corresponding electrical characterization. The goal of this paper is to illustrate an alternative for subdividing SF types that would otherwise be detected as triangular defects without any distinction and to show the different effects those subclasses have on finished devices with non-destructive methods that can be used in between device manufacturing steps. These results will be used as basis for further studies to confirm the found classes and to compare them with research about the different crystal structures by spectral PL measurements. For better understanding of the effect on the finished device, the PL imaging data is correlated with I-V characteristics of trenched diodes and the defect types are evaluated on their effect on the I-V characteristic, identifying 3 defect types with detrimental influence on the reverse bias and blocking voltage while the forward bias characteristic and I-V characteristic of one type is not effected by the defects.

Introduction

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Stacking faults (SFs) are well-known to be a limiting factor for the device yield of power electronic devices fabricated on SiC. They occur on 4H-SiC substrates and epitaxial layers as Shockley and Frank type stacking faults, as single or multiple stacking faults and form complexes such as the carrot defect [1,2]. Previous studies have reported [3,4] that some SF types can affect device performance and cause failure of devices, however which specific SF types cause electrical failure remains insufficiently understood. For instance, Baierhofer et al. [5] indicated that only approximately 66% of the defects identified by UVPL imaging as SFs without polytype inclusion will kill a SiC MOSFET device. Further, these defects result in different failure mechanisms. This finding indicates the necessity for a more detailed subclassification in addition to the known SF types of these defects and the investigation of process steps like implantation on the SF. This requires repeated in-line defect characterization and subsequent correlation with electrical data for better understanding of SF progression during device processing and final device performance.

Experimental

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We prepared eleven 150 mm SiC Wafers for pin diode fabrication with a standard 1200 V epitaxial layer with 13μ m thickness and a doping concentration of 9E+15 cm−3. After epitaxy and trench formation, they received implantation steps. A patterned nitrogen contact ( n+ ) as well as aluminum FFR ( p+ ) and aluminum contact ( p+ ) implantations with 0∘ was used. However, two wafer received this implantation under 17∘ tilt. Subsequently implant annealing was performed at 1700∘ for 30 min . The diodes were investigated repeatedly with various imaging methods utilizing the PL channel of the Lasertec SICA88 tool at different steps of processing. PL images were recorded on the substrates, after epitaxy and again after ion implantation and annealing. The samples were illuminated with a Hg−Xe lamp at an excitation wavelength of 313 nm . A 650 nm longpass filter was applied in front of the detector. The finished devices were then electrically characterized using I-V mapping on four different wafers. Over 30 devices of different designs and with and without defects were compared to get insight on the effect of the different defect types on device performance.

Results

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PL Imaging of epilayers.

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In the as grown epilayer, the SFs appear as dark triangles in the UVPL images of the PL channel of the SICA. After implantation and anneal, we observed a change in the luminescence signal. Thus, we identified four different subgroups of SF according to the UVPL signal. One example of each defect types (A-D) after epitaxy and after implant anneal are shown in figure 1.

PL Imaging after implant and anneal.

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After ion implantation and annealing, type A SF can be seen as a bright triangle. Type B appears as dark triangles with a darker surrounding area. Type C defects can be described as dark triangles with partially bright luminescent segments. Group D defects appear as bright triangles with a dark surrounding field, pointing towards a combination of type A and B defects. Additionally, we were able to locate the exact position of the defects within the device which allows exclusion of these SF for electrical characterization which are not located within the active-area.

[picture]

Fig. 1. PL images from the Lasertec SICA for each defect type after epitaxy as well as after implant and anneal. Each defect type shows a different luminescence signal after the anneal while after epitaxy each defect appears as a dark triangle.

Fig. 1. PL images from the Lasertec SICA for each defect type after epitaxy as well as after implant and anneal. Each defect type shows a different luminescence signal after the anneal while after epitaxy each defect appears as a dark triangle.

To compare the quantity of each defect type on the wafers, defects were counted in the PL images and assigned to the suitable SF type based on the visual criteria that were described above. A key challenge in process-accompanying SF analysis is choosing an imaging method that allows the same SF to be consistently located at each step, even across a large defect population. Therefore, defects in the PL images taken after epitaxy were correlated to the images after implant and anneal based on the coordinates on the wafer. This was possible due to the high accuracy of the automatic wafer alignment without the need of further adjustment of the scans and data. While the total number and local distribution of defects differs from wafer to wafer, counting from 10 defects per wafer to over 100, overall, a total number of 396 defects were evaluated. The occurrence of each defect type per wafer in percent is displayed in the bar plot in figure 2. The least common defect type on all wafers is the bright triangle type A , followed by the dark defect with surrounding dark area type B and type C . On wafer 4, 5, and 7 defect type A could not be detected at all. Overall, the most common defect type is D across all wafers except wafers 6 and 8 . This finding is coincidental with the implantation angle of 17∘ that was only used for these two wafers.

[picture]

Fig. 2. Ratios of defect type A, B, C and D on eleven wafers in percent. The data was generated by counting each defect type. The absolute number of defects varied for each wafer between 10 and 100 defects per wafer.

Fig. 2. Ratios of defect type A, B, C and D on eleven wafers in percent. The data was generated by counting each defect type. The absolute number of defects varied for each wafer between 10 and 100 defects per wafer.

Dark triangles with bright segments dominate as defects on wafers 6 and 8, whereas number of type D SF on these wafers was comparably low. This indicates that the implantation angle may have an impact on the formation of this defect subtype. However, given the limited number of defects and wafers, this observation lacks statistical significance. Nevertheless, in our present dataset the correlation appears too clear to be ignored. In existing studies, to the influence of the implantation an angle of 17∘ degree is connected to the implantation along the [ 11―23 ] direction of the silicon carbide lattice resulting in channeling and higher implantation depths.[6] We therefore plan additional studies to improve the statistical foundation, but also to investigate other parameters like different implantation angles, temperature, ion energy and dose.

Electrical Characterization

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To investigate effects associated to the different SF types on the device performance we characterized electrically the wafers by measuring I-V characteristics of each device. We analyzed I-V curves for almost 100 devices with defects and compared them to defect free devices. The remaining defects were removed from the statistics because they were not located in active device area. Future analysis of more defects and devices will provide more statistical support for these results. In figure 3 the reverse bias characteristic is shown for all four defect types and four reference devices without any SF . Curves of the reference devices typically are within the range of the plotted characteristics of the three examples. For forward bias, the characteristics from devices with or without defects were similar and did not show any differences or noteworthy effect. Devices that contained a visible SF of type A, B and D in the PL images showed a much lower breakdown voltage compared to devices without SFs (black curves). Defectfree devices upheld up to a voltage of about 700 V , while those with a SF exhibit a break down below 100 V reverse bias. The most detrimental effect on the breakdown voltage was observed for devices with type D SFs with an almost instant breakdown under reverse bias. Type C SFs did not appear to influence the breakdown voltage, as the I-V characteristics of devices with and without this defect type overlapped.

[picture]

Fig. 3. I-V reverse bias characteristics for type A (a), type B (b), type C (c) and type D (d), each with reference measurements of devices without defects (black lines).

Fig. 3. I-V reverse bias characteristics for type A (a), type B (b), type C (c) and type D (d), each with reference measurements of devices without defects (black lines).

Based on these diagrams the breakdown voltage under reverse bias was determined and is seen in figure 4 . The boxplot shows that the breakdown voltages for defect types A, B, and D cluster within a narrow range at low reverse-bias voltages. In contrast, type C spans a broader voltage range and has a higher median than the other defect types. Type D, despite having the largest sample size n, exhibits the tightest distribution and the lowest breakdown voltage.

[picture]

Fig. 4. The boxplot shows the distribution of breakdown voltage under reverse bias for the different defect types. The mean value is marked by a small cross, and n denotes the number of defects per type.

Fig. 4. The boxplot shows the distribution of breakdown voltage under reverse bias for the different defect types. The mean value is marked by a small cross, and n denotes the number of defects per type.

Outlook: PL Device Characterization

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For more detailed investigation of the structure of SFs in devices, Trench-MOSFETs were reprocessed to the pre-metal and pre-oxide state to be examined with UVPL. Initial testing of one of the reprocessed devices with a SF and different illumination sources and filters can be seen in figure 5. The sample was uniformly illuminated with 305 nm and examined with three different detector filters. A 430 nm bandpass filter, a 550 nm short pass and a 650 nm long pass filter were applied to examine the SFs in different luminescence ranges. The SF is visible in all of the shown images, but the details and fine structure varies for each filter and illumination source combination. Additional to the signal from the stacking faults, we observed dark vertical lines, especially at the bottom of images b ) and c ). In panel a ) and b ) the SF appears as a dark triangle while a thick black line appears on the right side of the SF when illuminated with 305 nm and with the BP and the shortpass filter. Panel c) shows the SF as a bright triangular shaped form with the black line again on the right side of the triangle. The combination of illumination sources and different filters allows a more detailed investigation of the SF and energy states in the crystal surrounding the defect. The configuration in panel c) is similar to the SICA, so the SF is probably a type A or D defect as it appears as a dark triangle in the image. The different filters could possibly help to investigate the SF PL types further and understand the origin of the different effects the types have on the finished devices.
For as grown epitaxy layers different PL wavelengths can be used for subclassification of stacking fault types. [7,8] Since the implantation changes the contrast and brightness of the SF as can be seen in figure 1, the SF cannot be classified after this process step by evaluating the PL emission images in dependence on the excitation wavelength.
The black vertical lines that are visible especially in the images b) and c) all seem to originate in the edge termination of the device. A possible reason for this could be degradation by the electrical testing that was conducted before the reprocessing of the devices, through propagation of defects caused by electrical stress as reported by Hatta et al. [9] The appearance of these lines as well as SF behavior in stressed devices need further investigation.

[picture]

Fig. 5. UVPL Images of a reprocessed MOSFET device with stacking faults. With 305 nm excitation source, a 430 nm bandpass, a 550 nm shortpass and a 650 nm longpass filter were applied to show the luminescence signal in different wavelength ranges.

Fig. 5. UVPL Images of a reprocessed MOSFET device with stacking faults. With 305 nm excitation source, a 430 nm bandpass, a 550 nm shortpass and a 650 nm longpass filter were applied to show the luminescence signal in different wavelength ranges.

Summary

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This study indicates that SFs change the appearance of the PL signal during device processing, particularly related to implantation steps. From the PL signal after implant and anneal different subtypes can be classified with indications that the subtype may correlate with implant parameters. This will be examined in further studies and will be cross referenced with PL spectroscopy to confirm the SF types and classification and if necessary, lead to process optimization. Importantly, the subtypes exhibit different impacts on device performance: while Types A, B, and D significantly degrade the reverse blocking capability of diodes, Type C shows no measurable effect on breakdown voltage. PL imaging can also be used for characterization of finished devices after electrical testing and to investigate the SF in more detail by the application of a range of filters. In addition, with spectral PL, this method will be used in further investigation of the origin of the subtypes and SF induced degradation.

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.19.pdf

Tsuchida H, Kamata I, Nagano M (2008) Formation of basal plane Frank-type faults in 4H-SiC epitaxial growth. J Cryst Growth 310:757-765.

Zhao L (2020) Surface defects in 4H-SiC homoepitaxial layers. Nanotechnology and Precision Engineering 3:229-234.

Schoeck J, Schlichting H, Kallinger B, et al (2018) Influence of Triangular Defects on the Electrical Characteristics of 4H-SiC Devices. MSF 924:164-167. .

Das H, Justice J, Sunkari S, et al (2024) The Role of Defects on SiC Device Performance and Ways to Mitigate them. DDF 434:51-59.

Baierhofer D, Thomas B, Staiger F, et al (2023) Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices. DDF 426:11-16.

Belanche M, Yonezawa Y, Heller R, et al (2024) Aluminum channeling in 4H-SiC by highenergy implantation above 10 MeV . Material Science Semiconductor Processing 179:108461. .

Feng G, Suda J, Kimoto T (2008) Characterization of stacking faults in 4H-SiC epilayers by room-temperature microphotoluminescence mapping. Appl Phys Lett 92:221906. .

Odawara M, Kamei K, Miyasaka Y, et al (2014) Defects Grouping and Characterizations of PL-Imaging Methods for 4H-SiC Epitaxial Layers. MSF 778-780:382-385. .

Hatta N, Ishikawa S, Ozono K, et al (2023) Reduction of Forward Bias Degradation in 4H-SiC PiN Diodes Fabricated on 4H-SiC Bonded Substrates. Key Eng Mater 948:107-113. .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 27-35

doi: 10.4028/p-5mleKn

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-18

Accepted:
2026-03-21

Online:
2026-05-18

Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1190.27.pdf

Kazumi Takano 1,a*, Yasuyuki Igarashi 1,b, Yohsuke Matsushita 1,c and Takuya Morita 1, d

1 ITES, 1-60 Kuribayashi, Otsu, Shiga 520-2151, Japan

a* kazumi_takano@ites.co.jp, b yiga@ites.co.jp, c yohsuke_matsushita@ites.co.jp,  dtakuya_morita@ites.co.jp

Keywords: PL mapping, proton implantation, Shockley-type stacking fault (SSF), photoluminescence (PL), UV irradiation, basal plane dislocation (BPD).

Abstract

We have been developing the expansion-visualization-contraction (EVC) method as an inspection technique for 4H−SiC wafers, in which Shockley-type stacking faults (SSFs) are intentionally expanded by UV irradiation and subsequently visualized to identify converted dislocations that are not directly detectable by conventional PL inspection. In this study, we demonstrate a low-cost "operando" PL spectrum mapping approach for the EVC tool by using the 355−nm expansion laser as the PL excitation source and adding only a miniature spectrometer via an optical fiber, avoiding the need for an expensive hyperspectral camera. Two experiments were performed. In Experiment 1, proton-implanted and non-implanted regions on n-type 4H−SiC epilayers were compared using EVC screening and PL imaging. The proton-implanted regions exhibited narrower SSF widths, and a two-sample t-test yielded extremely small p-values, indicating a statistically significant suppression effect that remained after activation annealing. In Experiment 2, a thick epilayer wafer containing polytype inclusions was screened. PL spectrum mapping identified not only 1SSF-related emission ( ~420 nm ) but also Frank-type components ( ~488 nm ) and polytype-inclusion-related emission ( ~540 nm ), revealing composite stacking faults expanded from inclusions. The results suggest that operando PL spectrum mapping can help distinguish stacking-fault types during EVC screening and potentially prevent unnecessary expansion of thermally uncontractable faults, thereby reducing yield loss.

Introduction

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We have been developing the EVC (Expansion-Visualization-Contraction) method as an inspection technique for 4H-SiC wafers [1]. In industry, photoluminescence (PL) inspection is widely used as one of the standard methods for evaluating 4H−SiC wafers and epitaxial layers [2]. PL inspection is effective for detecting basal plane dislocations (BPDs) in epitaxial layers; however, it cannot directly detect BPDs that convert into threading edge dislocations (TEDs) at the substrate/epilayer interface (i.e., BPD-origin TEDs). Both through-going BPDs and converted BPDorigin TEDs can trigger the expansion of stacking faults during current-induced degradation [3], and therefore both types of defects can critically affect the reliability and yield of final products.

To address this limitation, we propose to inspect BPD-origin TEDs-undetectable by conventional PL inspection-using the EVC screening method. The EVC screening method consists of three steps: (i) an Expansion step, in which SSFs are intentionally expanded in the epilayer by ultraviolet (UV) irradiation; (ii) a Visualization step, in which the converted dislocation is not directly observed but is instead identified as the source of Shockley stacking faults (SSFs); and (iii) a Contraction step, in which the expanded SSFs are contracted to recover wafer quality [1].

[picture]

Fig. 1. EVC Screening method.

Fig. 1. EVC Screening method.

Operando approaches have been reported for studying current-induced degradation in SiC devices. Because a biased device generally emits electroluminescence (EL), in-situ EL observation is possible in principle; however, observation is often hindered by metal electrodes. To overcome this, a method using comb-shaped electrodes has been proposed so that EL can be observed through open windows [4]. In addition, combined schemes have been reported in which the current stress is temporarily stopped and PL imaging is performed in between stress intervals [5]. Current-stress-based SSF expansion has the advantage of applying stress in a structure close to the final product. Nevertheless, it requires electrode fabrication and other processing steps starting from a bare wafer, which increases both time and cost. Moreover, when the SSF expansion is driven by wafer-origin BPDs, performing operando characterization directly at the wafer stage may reduce disturbances introduced by electrodes and electrical circuitry. For example, series resistance in electrodes can reduce the injected current, decrease the EL intensity, and potentially lead to misclassification. In-situ PL observation, on the other hand, typically requires a dedicated excitation source, microscope optics, and a 2D camera, resulting in a more complex and costly instrumentation.

In the EVC tool, operando PL observation is, in principle, achievable by alternating the Expansion and Visualization steps. However, implementing a mechanical system that repeatedly moves the wafer while maintaining high positional accuracy significantly increases cost. In this study, we exploit the fact that the third harmonic of a YAG laser (e.g., 355 nm ) used in the Expansion step can also serve as a PL excitation source. We investigate the feasibility of low-cost operando PL spectrum mapping [6] by adding only a miniature spectrometer, without employing an expensive hyperspectral camera. The ability to acquire PL spectrum mapping data at low cost is particularly attractive under limited development budgets.

Furthermore, if SF types can be identified from PL spectra, unnecessary expansion of SFs that are difficult to contract thermally (e.g., Frank-type faults) could be avoided, thereby preventing reduction of usable wafer area.
This paper reports a trial implementation of operando PL spectrum mapping as a pathway to enhance the functionality of the EVC tool. Specifically, we demonstrate the influence of activation annealing on proton-implanted wafers prior to electrode formation, and present an example of detecting Franktype SSFs that are difficult to contract.

Experimental Preparation: Installation of a Mini-Spectrometer

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A quartz optical fiber for collecting PL emission was mounted near the UV-laser irradiation spot used for SSF expansion. The fiber was connected to a compact multichannel Si-CCD spectrometer (FLAME-S, Ocean Optics; wavelength range: 220−850 nm ) for PL spectral measurements (Fig. 2).

Experiment 1: EVC Screening and PL Spectroscopy

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Samples and proton implantation

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Three commercial n-type 4H-SiC epitaxial wafers with a 4∘ off-cut were used in this study. The epitaxial structures are summarized in Table 1. Proton implantation was carried out from the epilayer surface under the conditions listed in Table 1. The projected implantation depths for wafers A and B
were calculated using SRIM2013 [7], and the results are shown in Fig. 4. For wafer C, protons were accelerated to 2 MeV and then decelerated by passing through an aluminum foil, adjusting the effective energies to the equivalent of 1.25 MeV and 600 keV . Fig. 3 shows the damage events calculated using SRIM2013.

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Fig. 2. Expansion process.

Fig. 2. Expansion process.

Table 1. Wafers.

| Active | Buffer layer | Drift Layer | Proton Implantation
| Annealing | Thickness (μm) | ND (cm⁻³) | Thickness (μm) | ND (cm⁻³) | (keV) | ND (cm⁻²)
Wafer A | YES | 1 | 1.00E+18 | 10 | 8.00E+15 | 350 | 1.00E+13
Wafer B | NO | 0.5 | 1.00E+18 | 8 | 1.00E+16 | 600 | 1.40E+14
Wafer C | YES | 3 | 1.00E+18 | 19 | 4.00E+15 | 600, 1250 | 1.00E+12

Expansion step (UV-irradiation)

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As an expansion step, wafers A and B were irradiated by a scanned UV laser over a 10×10 mm2 area spanning both the proton-implanted and non-implanted regions in order to induce and expand Shockley-type stacking faults (SSFs) (Fig. 3).

[picture]

Fig. 3. UV irradiation.

Fig. 3. UV irradiation.

Visualization step (PL imaging and SSF-width analysis)

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As a visualization step, the expanded SSFs were evaluated by PL imaging. The SSF widths in the proton-implanted and non-implanted regions were measured, and a two-sample t-test was performed to assess the difference in mean SSF width between the two regions. By comparing wafers A and B, we examined whether the SSF-expansion suppression effect of proton implantation is maintained after activation annealing (i.e., not deactivated by the annealing process).

Contraction step and reproducibility check

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As a contraction step, wafer B was annealed at 800∘C for 3 h to contract the expanded SSFs. The expansion and visualization steps were then repeated to evaluate the reproducibility of SSF initiation locations. This procedure was conducted to confirm that the EVC screening method does not adversely affect wafer quality.

PL spectroscopy for wafer-quality evaluation

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Using wafer C, PL spectra were measured before proton implantation, after proton implantation, and after activation annealing in order to evaluate changes in wafer quality associated with each processing step.

Result 1: EVC Screening and PL Spectroscopy

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Simulations by SRIM2013 [7]

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SRIM2013 simulations suggested that implanted protons accumulate at a depth of approximately 2.4μ m in wafer A and approximately 5μ m in wafer B (Fig. 4). Fig. 5 shows the vacancy concentration estimated from SRIM2013 calculations for proton implantation.

[picture]

Fig. 4. Proton Distribution.

Fig. 4. Proton Distribution.

[picture]

Fig. 5. Vacancy Distribution.

Fig. 5. Vacancy Distribution.

[picture]

Fig. 6. PL Images of Wafer A.

Fig. 6. PL Images of Wafer A.

UV-PL imaging of expanded SSFs

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Fig. 6 shows UV-PL images of SSFs expanded by the EVC procedure for wafer A. The SSFs in the proton-implanted region exhibited a narrower band width than those in the non-implanted region, indicating that proton implantation suppresses SSF expansion.

Repeatability of SSF expansion after contraction

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Fig. 7 shows UV-PL images acquired using a 420−nm band-pass filter (BPF420). The white regions correspond to SSFs. The lower half of the image is the proton-implanted area, where SSFs were observed as gray features against a darker background. Panel (a) corresponds to the first expansion step. After the contraction step, the white SSF contrast disappeared (b). Panel (c) shows the second expansion step, in which SSFs expanded again at the same locations. The white square feature in the lower right region was not an SSF and was attributed to contamination.

[picture]

Fig. 7. PL Images of Wafer B.

Fig. 7. PL Images of Wafer B.

Statistical comparison of SSF widths

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Ten stripe-like SSFs were selected from each area, and their widths were measured. For both proton-implanted wafer A and wafer B, the SSF widths in the epilayer differed between the protonimplanted and non-implanted regions. A two-sample t-test yielded extremely small p-values (Table 2), indicating a statistically significant difference. These results suggest that the SSF-expansion suppression effect appears immediately after proton implantation and remains effective even after activation annealing.

Table 2. T-TEST.

Wafer | Proton | Average of SSF widcth (μm) | Standard deviation | Difference in means | P value | 95% CI diff (equal var)
A | NO | 150.3 | 1.52 | 28.2 | 1.03E-17 | 26.4, 30.0
YES | 122.1 | 2.17
B | NO | 120.6 | 2.58 | 72.8 | 2.07E-24 | 70.9, 74.7
YES | 47.8 | 1.29

Reproducibility of SSF initiation locations

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[picture]

Fig. 8. PL Images of Wafer B.

Fig. 8. PL Images of Wafer B.

Fig. 8(a) shows the UV-PL image obtained after the first expansion step, while Fig. 8(b) shows the UV-PL image obtained after the second expansion step following a contraction process. For comparison, the extracted contours from (b) were colored in purple and overlaid onto (a), as shown in Fig. 8(c). Sixteen SSFs were observed after the first expansion, and fifteen SSFs were observed after the second expansion at nearly the same locations. This reproducibility suggests that the EVC procedure does not measurably degrade wafer quality under the present conditions.

PL spectra

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The PL spectra in Fig. 9 are consistent with the above EVC-based evaluation of proton implantation. The emergence of the SSF-expansion suppression effect after proton implantation agrees with the reduced intensity of the band-to-band emission peak at 390 nm following implantation. In addition, the persistence of the suppression effect after activation annealing is consistent with the observation that the 390−nm peak intensity decreased slightly after annealing but remained largely stable overall.

[picture]

Fig. 9. PL spectrum of Wafer C.

Fig. 9. PL spectrum of Wafer C.

Experiment and Result 2: EVC Screening of Polytype-Inclusion-Related Stacking Faults and in situ PL Spectral Mapping

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An epitaxial wafer containing multiple polytype inclusions was purchased (Fig. 10). The wafer was an n-type 150−mm-diameter 4H−SiC epitaxial wafer with a 4∘ off-cut, consisting of a heavily nitrogen-doped buffer layer ( 2μ m,1×1018 cm−3 ) and a lightly doped drift layer ( 60μ m,9×1014 cm−3 ).

Focusing on regions containing triangular stacking faults (SFs), we evaluated the wafer using the EVC screening. After 355−nm laser irradiation as the expansion step, UV-PL imaging with a 420−nm band-pass filter (BPF420) was performed as the visualization step, and numerous bar-shaped SFs were observed. At this stage, as a simulated operando observation, PL spectral mapping was carried out within the yellow dashed region in Fig. 12 The measurement was performed with a 0.25−mm step while the laser irradiance was attenuated to approximately 1/100. Subsequently, a contraction step was conducted by annealing at 800∘C for 3 h .

Fig. 11(a) shows a bar-shaped 1SSF originating from a basal plane dislocation (BPD), whereas Fig. 11(b) shows a bar-shaped SF expanded from an inclusion containing SFs; its morphology was slightly different from that of the 1SSF in Fig. 11(a). After the contraction process, the 1SSF in Fig. 11(a) disappeared completely, whereas part of the SF in Fig. 11(b) remained uncontracted. No further change was observed even after an additional 6 h of annealing. The remaining SF is therefore considered to be different from a BPD-originated 1SSF.

Fig. 12(a) shows a PL image obtained with BPF420, and Fig. 12(b) shows the corresponding spectral mapping at 420 nm . Both images capture approximately two sets of bar-shaped stacking faults. Fig. 12(c) shows representative spectra; because both SSFs exhibit a peak at 420 nm , their dominant component was attributed to 1 SSF .

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Fig. 10. Polytype inclusion with triangle SF.

Fig. 10. Polytype inclusion with triangle SF.

[picture]

Fig. 11. PL image using BPF 420 nm .

Fig. 11. PL image using BPF 420 nm .

[picture]

Fig. 12. (a) PL-imaging (b) PL-Spectrum ( 420 nm ) mapping.

Fig. 12. (a) PL-imaging (b) PL-Spectrum ( 420 nm ) mapping.

Fig. 13(a) shows a PL image obtained with BPF420, and Fig. 13(b) shows spectral mapping at 488 nm . The 488−nm mapping revealed enhanced intensity at SF positions connected to polytype inclusions. The spectra in Fig. 13(c) exhibit a 420−nm peak attributed to 1SSF, a 488−nm peak attributed to Frank-type stacking faults [8], and a 540−nm peak attributed to polytype inclusions. These results indicate that stacking faults expanding from polytype inclusions are of a composite type, including not only 1SSF but also Frank-type stacking faults. If the uncontracted SFs are Frank-type faults with high thermal stability, their persistence after 800∘C annealing can be reasonably explained. These findings suggest that PL spectral mapping performed as an operando observation during EVC screening could enable early identification of SFs that do not contract (e.g., Frank-type components) and may allow their expansion to be halted at an early stage.
Because uncontractable SFs can render the affected wafer area unusable, minimizing their lateral extent is desirable from a cost perspective, and operando PL spectral mapping is therefore beneficial.

[picture]

Fig. 13. (a) PL-imaging (b) PL-Spectrum ( 488 nm ) mapping.

Fig. 13. (a) PL-imaging (b) PL-Spectrum ( 488 nm ) mapping.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1190.27.pdf

A miniature-spectrometer-based operando PL spectrum mapping scheme was implemented for the EVC inspection method by reusing the 355−nm expansion laser as the PL excitation source and collecting emission through an optical fiber. In proton-implanted epilayers, EVC/PL imaging showed a statistically significant reduction in SSF width, and the suppression effect persisted after activation annealing.

For a thick epilayer wafer containing polytype inclusions, PL spectrum mapping distinguished composite stacking faults expanded from inclusions, comprising 1SSF-related emission ( ~420 nm ) together with Frank-type ( ~488 nm ) and inclusion-related ( ~540 nm ) components. These findings
indicate that low-cost operando PL spectrum mapping can enhance EVC screening by enabling early fault-type identification and by supporting strategies to avoid unnecessary growth of thermally persistent faults that can reduce usable wafer area.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1190.27.pdf

METI R&D Support Program for Growth-oriented Technology SMEs Grant Number JPJ005698

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.27.pdf

Y. Igarashi, K. Takano, Y. Matsushita, C. Shibata, Defect and Diffusion Forum Vol. 425, pp. 75-82 (2023).

International Electrotechnical Commission Standard 63068-3 (2020).

A. Tanaka, H. Matsuhata, N. Kawabata, D. Mori, K. Inoue, M. Ryo, T.Fujimoto, T. Tawara, M. Miyazato, M. Miyajima, K. Fukuda, A. Ohtsuki, T. Kato, H. Tsuchida, Y. Yonezawa, T. Kimoto, J. Appl. Phys. Vol. 99, 011101 (2006).

C. Ota, J. Nishio, A. Okada, R. Iijima, 19th Conference on Defects, Vol.52, pp. 5109-5120 (2023).

K. Konishi, R. Fujita, A. Shima, J. Electron. Mater. Vol. 48, pp. 1704-1713 (2019).

G. Feng, J. Suda, T. Kimoto, Appl. Phys. Lett. Vol. 92, 221906 (2008).

Information on .

S. Hageali, H. Guthrey, S. Johnston, A.Norman, J. Soto, B. Odekirk, R. Stahlbush, N. Mahadik, B. Gorman, M. Al-Jassim, J. Appl. Phys. Vol. 134, 075704 (2023).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 37-42

doi: 10.4028/p-0xM8R1

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2026-01-18

Accepted:
2026-02-28

Online:
2026-05-18

Quantitative Analysis of Excess Minority Carrier Density and Critical Duration in UV Irradiation-Based Screening for Bipolar Degradation in 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

Yasuyuki Igarashi 1,a*, Kazumi Takano 1, b, Yohsuke Matsushita 1,c and Takuya Morita 1, d

1 ITES Co., Ltd., 1-60 Kuribayashi, Otsu, Shiga 520-2151, Japan

ª*yiga@ites.co.jp, bkazumi_takano@ites.co.jp, cyohsuke_matsushita@ites.co.jp,

dtakuya_morita@ites.co.jp

Abstract

Ultraviolet (UV) irradiation on 4H−SiC epitaxial wafers, conducted prior to metallized circuit formation, is widely used to reveal whether BPD (basal plane dislocation) induced nucleation and expansion of a single Shockley stacking fault (1SSF) occurs via recombination enhanced dislocation glide (REDG). However, the UV method has remained largely qualitative, and its quantitative relationship to forward bias current injection has not been established. Here, using the excess minority carrier density at the BPD-to-TED (threading edge dislocation) conversion point, we establish equivalence criteria between two stress modes (current density and UV irradiance) and introduce a previously overlooked requirement for pulsed UV laser sources: the minority carrier density must exceed a threshold and be sustained for a finite "critical duration," tcrit, defined as the minimum time required to initiate dislocation glide. Notably, tcrit shows only weak dependence on the bulk carrier lifetime ( τb ), offering a practical route to determine pulsed UV irradiation conditions that faithfully emulate forward bias stress, even when τb is unknown.

Keywords: 4H−SiC, bipolar degradation, basal plane dislocation, stacking fault, UV screening, recombination-enhanced dislocation glide, minority-carrier lifetime.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

Bipolar degradation, caused by the nucleation and expansion of 1SSF (single Shockley stacking fault) from BPD (basal plane dislocation) remains a key reliability concern for 4H−SiC bipolar power devices like PiN diodes and the body diode in MOSFETs. The conventional method for evaluating the impact of process modifications on bipolar degradation typically requires the fabrication of metallized active devices, followed by current injection testing. While highly reliable, this approach is costly and time intensive. As a simplified alternative, ultraviolet (UV) irradiation has been widely employed at the pre-circuit formation stage to verify the presence of defect expansion. UV irradiation is known to induce the nucleation and expansion of 1SSF from BPD through recombination enhanced dislocation glide (REDG) mechanism, similar to current injection. However, this method has been limited to qualitative assessments of 1SSF behavior and has not enabled quantitative equivalence, such as estimating the UV irradiation intensity corresponding to a specific current rating.

We have proposed a UV irradiation-based screening method (called E-V-C method) to detect latent BPD-related defects at an early stage by leveraging the SF expansion governed by REDG mechanism [1]. For practical deployment of the screening, however, it is essential to establish a quantitative equivalence between UV irradiation and forward bias current injection stress. We define UV irradiation conditions as equivalent to current injections if they allow identification of defect expansion with the same accuracy as current stress. Prior work [2], referencing Tawara et al. [3], reported that bar shaped 1SSF expansion occurs above a threshold current density, though device doping profiles influence the threshold value. Importantly, if we focus not on the current density but on the excess minority carrier density at the conversion point from BPD to TED (threading edge dislocation), where the stacking fault begins to expand, this density remains invariant to the device profile and is therefore defined as the critical minority carrier density. Based on this insight, we sought
to link the two stress modes, current injection and UV irradiation, via the critical minority carrier density generated under each condition.

A fundamental distinction, however, exists between the two stress modes. Constant current injection yields a steady state carrier distribution, whereas pulsed UV irradiation produces a transient carrier distribution that rises sharply post-pulse and decays exponentially. Therefore, in this study, we first independently determine, by experiment, the threshold conditions for SF expansion in each stress mode, namely, the threshold current density and the threshold UV irradiance. We then estimated the excess hole distributions using numerical calculations. By assuming equivalence of the hole density at the TED conversion point, we derived a correlation model. The analysis reveals that pulsed UV laser irradiation requires that the excess carrier density must not only exceed the threshold value for each pulse, but it must also persist above the value for a finite duration, herein termed "the critical duration" tcrit, a parameter absent under constant current injection case. This paper details the derivation of this equivalence condition for PiN diodes, incorporating the critical duration.

Experiments and Results

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

PiN diodes were fabricated on commercial n-type 100 mm,4H-SiC wafers ( 4∘ off-cut toward [1120] direction). The structure comprised a buffer layer ( 0.5μ m,1×1018 cm−3 ) and a drift layer ( 5.4μ m, 5×1015 cm−3 ), epitaxially grown on the substrate ( 350μ m,6×1018 cm−3 ). A 0.5μ mp+anode layer was formed by Al doping ( 4.1×1018 cm−3 ). Ni electrode was deposited on the backside, and Al combshaped electrodes ( 2 mm square chips) were patterned on half the wafer for accelerated current stress tests; the remaining half was reserved for UV stress experiments.

Accelerated current stress tests were conducted with pulsed currents of 250−400 A/cm2. 1SSF expansion was monitored using UV photoluminescence (UVPL, 420 nm band pass filter), tracking Si(g) dislocation glide velocities. In parallel, UV irradiation was applied using a 355 nm Nd:YAG pulsed laser ( 10 ns pulse, 20μ s period, duty 0.05%, max 211μ J/pulse,3 mm beam). Output was varied from 1−100% using an attenuator, and 1 SSF expansion was studied at 10%,25%,50%, and 100% power.

Under current stress, 329 bar shaped 1SSF sites from 43 chips were analyzed (Fig. 1(a)), while 11 sites were examined under UV stress (Fig. 1(b)). Measured glide velocities varied significantly at identical stress levels, presumably attributed to numerous factors in real devices that can impede the motion of the Si(g) dislocation (e.g., various crystallographic defects). Because the goal of this study is to evaluate the correlation between stress intensity and expansion, linear regression was applied to the maximum-velocity data points at each stress level (red markers in Fig. 1(a), and (b)), where the influence of impeding factors is presumed to be minimal. Threshold intensities, defined as the zerovelocity intercepts, were determined as 235 A/cm2 for current density and 36,650 W/cm2 for UV irradiance, indicating equivalence between the two [2].

[picture]

Fig. 1. Si(g) core glide velocity VS. stress intensity (current density (a) and irradiation power (b)).

Fig. 1. Si(g) core glide velocity VS. stress intensity (current density (a) and irradiation power (b)).

Numerical Analysis and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

The experimentally determined threshold current density of 235 A/cm2 and UV irradiance of 36,650 W/cm2 were used to estimate hole densities, assuming equivalence at the critical minority carrier density. The device structure was p+/n−/n+/n++(anode, drift, buffer, substrate), with particular emphasis on the buffer layer, where BPD-to-TED conversion predominates.

The excess hole density ΔpFB(x) under forward bias was calculated by solving the carrier transport equation, assuming quasi-Fermi potential continuity at interfaces (i.e., a continuous pn product). The computed values near the n+/n++interface aligned reasonably with literature ( 1.8−2.5×1016 cm−3 [3]), though slightly lower as shown in Fig. 2. Since the hole density depends on the bulk minority carrier lifetime τb in the n−layer, which is unknown, the calculation was carried out by varying τb from 50 ns to 2μ s. The minority carrier lifetimes in the buffer layer and the substrate are also unknown; therefore, with reference to previous studies [4-6], they were assumed to be τbuffer =30 ns and τsub =3 ns, respectively.

[picture]

Fig. 2. Depth profiles of hole density under forward bias stress for the current density of 235 A/cm2.

Fig. 2. Depth profiles of hole density under forward bias stress for the current density of 235 A / c m 2 .

In contrast, under UV irradiation stress the hole density generated by the laser pulses becomes a function of both time and space. The excess hole density ΔpUV(x,t) was obtained from diffusion equations with Robin-type boundary conditions for surface recombination, continuity of carrier density and flux at layer interfaces, and an initial distribution set by Lambert-Beer's law for optical absorption immediately after UV exposure. Although a Fourier-series analytical solution is possible, a large number of higher-order terms are required for convergence; therefore a one-dimensional backward Euler finite difference method was employed to reduce computational load. Simulations were run for τb=50 ns,200 ns, and 2μ s, as shown in Fig. 3(a), (b), (c), respectively. τbuffer  and τsub  were assumed to be the same as in forward bias case.

[picture]

Fig. 3. Depth profiles of hole density under UV irradiation stress for τb=50 ns,200 ns,2μ s for the UV irradiance of 36,650 W/cm2.

Fig. 3. Depth profiles of hole density under UV irradiation stress for τ b = 50 n s , 200 n s , 2 μ s for the UV irradiance of 36 , 650 W / c m 2 .

Since many BPD-to-TED conversion points are thought to distribute near the buffer/substrate and buffer/drift interfaces, the hole density at these locations was monitored over time. Figure 4 shows decay curves for τb=50 ns and 2μ s. Figure 5 overlays these curves with forward bias results (from Fig. 2). It is an enlarged view of Figure 4, highlighting the region that includes the point-within the range of τb=50 ns to 2μ s-at which the hole density under forward bias intersects with the decay curve of the hole density after UV pulse irradiation (i.e., the point where the two become identical). The vertical axis has been changed from a logarithmic scale to a linear scale.

Black triangles indicate the points where UV induced hole densities fall to the forward bias threshold level. This level can be interpreted as the minimum duration required for the initiation of 1SSF expansion. Specifically, it corresponds to the time needed for the leading edge of the Si(g) core dislocation to overcome the Peierls potential and initiate the local 4 H to 3 C transformation. This duration is defined as the critical time, tcrit. Notably, tcrit exhibits only a weak dependence on the bulk carrier lifetime in the drift layer, τ b. As shown in Figs. 2−4, the hole density in the buffer layer changes significantly with τb, but the direction of this change is the same under both forward bias and UV irradiation conditions. Consequently, terit itself is expected to vary little. By contrast, although not discussed in detail here, an increase in the minority carrier lifetime in the buffer layer or the substrate results in a longer tcrit -defined as the decay time required for the hole density after UV irradiation to converge to that under forward bias current injection-whereas a decrease leads to a shorter tcrit .

[picture]

Fig. 4. Decay curves of hole density.

Fig. 4. Decay curves of hole density.

[picture]

Fig. 5. The same hole density points
(Superimposed on Fig. 4 with Fig. 2).

Fig. 5. The same hole density points (Superimposed on Fig. 4 with Fig. 2).

As shown in Fig. 6, terit remained approximately constant ( ~50±5 ns ) across τb=50 ns to 2μ s, with negligible dependence on τ b. The same figure also shows (right y-axis) the τ b dependence of the hole density.

[picture]

Fig. 6. Critical duration ( tcrit  ) over the range of carrier lifetime from 50 ns to 2μ s.

Fig. 6. Critical duration ( t crit ) over the range of carrier lifetime from 50 ns to 2 μ s .

Therefore, a UV condition equivalent to a given forward bias condition can be defined by the following equation (1). At a conversion point x0 in the buffer

ΔpUV(x0,tcrit )=ΔpFB(x0).(1)

This provides a practical guideline for setting UV irradiation parameters for screening BPD-related defects. Moreover, the weak dependence of tcrit on carrier lifetime implies that even if τb is unknown, its impact on the equivalency is limited.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

We demonstrated that 1SSF nucleation/expansion under pulsed UV irradiation requires not only exceeding the threshold hole density but also sustaining it for the critical time tcrit. This duration represents the minimum time to overcome the Peierls barrier associated with the 4 H -to-3C transformation. Notably, torit is nearly independent of the bulk minority carrier lifetime τb in the n− layer. To replicate forward bias degradation via pulsed laser irradiation, conditions must yield hole densities matching those under forward bias, sustained for torit (Eq. (1)). The dependence of tcrit on the minority carrier lifetimes in the buffer layer and the substrate will be investigated in detail in future studies. While the equivalence estimation in this study relied on statistical analysis of multiple defects, future work will aim to directly validate Eq. (1) by examining the expansion behavior of identical defects. This will be pursued sequentially through UV stress, annealing-induced 1SSF contraction (300−600∘C), and subsequent current injection stress.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

This work was supported by the Ministry of Economy, Trade and Industry (METI) R&D Support Program for Growth-Oriented Technology SMEs (Grant No. JPJ005698). The authors gratefully acknowledge the technical guidance of Prof. Kato (Nagoya Institute of Technology) and Assoc. Prof. Harada (Nagoya University).

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.37.pdf

Y. Igarashi, K. Takano, Y. Matsushita, C. Shibata, Defect and Diffusion Forum, vol. 425, p. 75, 2023.

Y. Igarashi, K. Takano, Y. Matsushita, C. Shibata, Defect and Diffusion Forum, vol. 434, p. 23, 2024.

T. Tawara, S. Matsunaga, T. Fujimoto, M. Ryo, M. Miyazato, T. Miyazawa, K. Takenaka, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto, and H. Tsuchida, J. Appl. Phys., vol. 123, 025707, 2018.

T. Tawara, T. Miyazawa, M. Ryo, M. Miyazato, T. Fujimoto, K. Takenaka, S. Matsunaga, M. Miyajima, A. Otsuki, Y. Yonezawa, T. Kato, H. Okumura, T. Kimoto, H. Tsuchida, J. Appl. Phys. 120, 115101 (2016).

A. Y. Polyakov, Q. Li, S. Wook Huh, M. Skowronski, O. Lopatiuk, L. Chernyak, and E. Sanchez, J. Appl. Phys. 97, 0537032005.

W. A. Doolittle, A. Rohatghi, R. Ahrienkel, D. Levi, G. Augustine, and R. H. Hopkins, Mater. Res. Soc. Symp. Proc. 483, 1971998.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 43-48

doi: 10.4028/p-1DCRuh

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-21

Accepted:
2026-03-21

Online:
2026-05-18

Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

C. Calabretta 1,a*, C. Bottari 1,b, S. Adamo 1,c, B. Carbone 1,d, G. Maira 1,e, F. Vento 1,f, E. Fontana 1, g, N. Piluso 1, h, M. S. Alessandrino 1,i, A. Russo 1,j, P. Fiorenza 2,k, F. Roccaforte 2,l, A. Severino 1,m

1 STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy

2 CNR-IMM, Strada VIII n. 5 - Zona Industriale, 95121, Catania, Italy

a * cristiano.calabretta01@st.com, b ketty.bottari@st.com, c salvatore.adamo1@st.com,

d  beatrice.carbone@st.com, e  giovanni.maira@st.com, f  fabiana.vento@st.com, enzo.fontana@st.com, h  nicolo.piluso@st.com, i  santi.alessandrino@st.com, 

jalfio-lip.russo@st.com, k  patrick.fiorenza@imm.cnr.it, 'fabrizio.roccaforte@imm.cnr.it, mandrea.severino@st.com 

Keywords: 1SSF, ELFR, micro photoluminescence, burger vector, BPD, IDSS.

Abstract

Basal plane dislocations (BPDs) represent one of the most detrimental defects in 4H−SiC epitaxial wafers, causing forward voltage degradation in bipolar and power FET devices through the formation and expansion of Shockley-type stacking faults (SSFs). This expansion is driven by the recombination-enhanced dislocation glide (REDG) mechanism during forward bias operation. Despite efforts to mitigate BPD effects by converting them into threading edge dislocations (TEDs) via buffer layer engineering, throughout the epitaxial growth SSFs can still nucleate and propagate, particularly under high current injection. This work presents a comprehensive analysis combining electrical characterization, fault localization technique, Scanning Electron Microscopy (SEM) and micro-photoluminescence ( μ-PL) to investigate SSF formation, crystallographic features, and their impact on device performance. The results underscore the critical role of advanced diagnostics and epitaxial process optimization in controlling SSF-related degradation and improving the reliability of SiC power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

All BPDs are considered one of the most harmful defects in SiC epitaxial wafers. They cause forward degradation, which manifests as an increased forward voltage drop, in SiC bipolar devices and body diodes junction within power MOSFET when they occur in the active region. During forward bias in a SiC pn junction, BPDs can lead to SSFs due to the injection of minority carriers. This expansion of stacking faults is driven by the electron-hole REDG process [1-2]. This phenomenon was initially observed as causing degradation in the forward characteristics of highvoltage SiC pin diodes, with its primary source identified as stacking faults expanding within the voltage-blocking region. SSF expansion from BPDs occurs during forward bias operation in 4H−SiC, leading to forward voltage drift in minority carrier SiC devices [3]. Additionally, SSF expansion has been linked to reverse bias breakdown voltage degradation [4]. To reduce the impact of these SSFs in the active drift layer, a highly doped buffer layer was developed to convert most BPDs into threading edge dislocations (TEDs) [5]. It is seldom observed that nominal current density degradation is generally not impacted. However, at exceptionally high current levels, the increased density of minority charge carriers can penetrate deeper into the buffer region, potentially triggering stacking fault growth at deeply embedded crystal defects within the buffer or even the n+substrate. In the case of unipolar devices during each turn-off event of a SiC MOSFET, the body diode is subjected to forward bias, which may induce the propagation of stacking faults within the n-type drift layer. The expanded stacking fault introduces a potential barrier that contributes to an increase in the on-resistance of the device. An increase in the drain leakage current after the current stress is expected [6].

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

In this experiment, 4H-SiC planar MOSFETs, fabricated on an epitaxial layer of almost 13μ m thickness with a doping concentration of about 1×1016 cm−3, were used.
Sample prepation from backside was performed with MultiPrep TM  Precision Polishing System (Allied High Tech Products) aimed to remove package frame and to reach SiC substrate. PHEMOS1000 Emission microscopy (Em.Mi.) was used to identify the coordinates of point of failure induced by electrical stress. Focused ion dual beam (FIB) -Helios 5UC - was employed to mark the position and identify the region to investigate. LabRam Odyssey Raman spectrometer equipped with a λ=320 nm (74x objective) wavelength and 600gr/mm grating was adopted to perform the 1SSF PL map.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

Sample analyzed in this work didn't exhibit any indicators of impending failure, offering no warning of electrical issues at the Electrical Wafer Sorting test (EWS). After assembly process, sample was subjected to Early Life Failure Rate (ELFR) test flow, not exhibiting any anomalous current trend. Following ELFR, some electrical parameters have been additionally tested in order to confirm the goodness of the piece. As shown in Fig. 1, electrical test for this device revealed a slight increase in drain leakage current at high bias ( 850 nA at 1200 V ) (Fig.1a) if compared to other parts subjected to the same test cycle in which IDSS value is lower than 200 nA (Fig 1b).

[picture]

Fig. 1. Drain leakage current (IDSS) trends for sample analyzed in this work (left) and a device subjected to same trials (EWS + ELFR + Final test) (right). NOTE: vertical scale in the two graphs is different, current values at 1200 V are reported for easy of reference.

Fig. 1. Drain leakage current (IDSS) trends for sample analyzed in this work (left) and a device subjected to same trials (EWS + ELFR + Final test) (right). NOTE: vertical scale in the two graphs is different, current values at 1200 V are reported for easy of reference.

After the above described preparation, the device was subjected to fault localization analysis, Sample was appropiately powered in IDSS configuration to identify the region in which current leakage is concentrated, Emitted photons where clearly detected and shown in Fig. 2 as pink spots. These emissions are in correspondence to a defect, well visible as dark line with IR camera.

[picture]

Fig. 2. Fault Localization by photon emission from backside.

Fig. 2. Fault Localization by photon emission from backside.

To better investigate the defect region was identified from backside to. Decapping of the package and total delayering steps allowed the observation of the failure region at the epitaxial level under the SEM. As shown in Fig. 3, some depressions on epitaxy surface are well visible in correspondence of hot spot region, crossed by the dark line visible in Fig. 2.

[picture]

Fig. 3. SEM image perfomed with FIB Helios 5UC showing depression on epitaxial layer and responsible to IDSS leakage.

Fig. 3. SEM image perfomed with FIB Helios 5UC showing depression on epitaxial layer and responsible to IDSS leakage.

Following the Emission Microscopy investigation and spatial localization of the failure with SEM, μ−PL analysis was performed to examine stacking faults extended within the 4H−SiC epilayers.

Fig. 4a presents the map obtained by centering the acquisition on the spectral region corresponding to stacking fault emission, revealing a characteristic triangular morphology. The spectral data reported in Fig. 4b highlights two distinct regions: region 1 corresponding to the μ-PL acquisition within the stacking fault area, showing SF layer emission at λ=424 nm, thereby identifying it as a single stacking fault ( 1 SSF) and region 2 , exhibiting only band-to-band emission with a peak at λ=389 nm [7].

Considering the 4∘ off-axis angle and the 1SSF length of approximately 150μ m, it can be inferred that the stacking fault originates from a BPD located just above the BPD-to-TED conversion zone, likely formed during the initial stages of epitaxial growth and subsequently propagated during electrical testing. Indeed, Lendenmann et al. reported a voltage drop occurring during forward operation [8], attributing it to BPDs acting as sources of SSFs. Specifically, a BPD dissociates into two partial dislocations with SSF forming between them. The expansion of the SSF is driven by the glide of these partial dislocations through the REDG mechanism. When a sufficiently large amount of excess carriers are injected, the Si-core partial dislocation starts to glide, which leads to 1SSF expansion. Both bipolar and unipolar SiC devices exhibit forward degradation when a BPD propagates along the active direction. Various types of stacking faults have been identified using UVbased PL mapping, revealing over 15 distinct SSF shapes in the active regions of degraded SiC devices following electrical stress testing. These SSF shapes have been categorized into multiple forms, including rectangular, triangular, and rhombic geometries [9-10-11-12-13-14]. The expansion of SSFs primarily takes place in the n -type region and is confined between the p+−n−and n−−n+ junctions. Notably, Si-core partial dislocations are mobile, whereas C-core partial dislocations remain immobile. Stahlbush et al [15] suggested that the observed expansion patterns are closely linked to
the Burgers vector and direction of the BPDs. Ijima [16] elucidates the relationship between the morphologies of expanded SSFs and the configurations of BPD segments in 4H-SiC epilayers. It was demonstrated that, considering three types of Burgers vectors, 2 varieties of PD loops, and 12 line directions, there exist 72 distinct crystallographic BPD structures. The specific shapes of the expanded SSFs were predicted by analyzing the glide behavior of the PDs. Through g·b analysis, the predicted SSF shapes were confirmed to correspond well with experimental results and a total of 38 different expanded SSF shapes were identified. This established correlation enables the determination of the Burgers vectors and line directions of the original BPD segments based on the observed shapes of the expanded SSFs.

[picture]

Fig. 4. a) 1 SSF imaging through m−PL intensity map centred at λ=424 nm; b) PL spectra within (1) and outside (2) the 1SSF; c) BPD evolution modeling, with initial direction and burger vector at at the beginning of the expansion of 1SSF d) Vesta 1SSF lattice simulation reporting the lattice stacking in correspondence of the fault.

Fig. 4. a) 1 SSF imaging through m − P L intensity map centred at λ = 424 n m ; b) PL spectra within (1) and outside (2) the 1SSF; c) BPD evolution modeling, with initial direction and burger vector at at the beginning of the expansion of 1SSF d) Vesta 1SSF lattice simulation reporting the lattice stacking in correspondence of the fault.

The characteristic morphology of the SSFs provides insight into the nature of the dislocations that bound them. From the μ-PL analysis, it can be inferred that the dislocation direction is [10-10] with a Burgers vector of (1/3)[11-20] [16] as schematized in Fig. 4c where SSF starting shape is reported. A BPD can possess any of six possible Burgers vectors; however, due to the symmetry of the crystal, only three Burgers vectors (1/3)[11−20],(1/3)[1−210], and (1/3)[−2110] need to be considered when analyzing 1SSF expansion. The dislocation line itself typically aligns with one of the six ⟨11−20⟩ crystallographic directions. In this study after repeated laser irradiations, the SSF does not exhibit any further lateral enlargement. This behavior strongly suggests that the SSF is confined by C-core dislocations both above and below, effectively limiting its expansion. Furthermore, the intensity variations observed from left to right correspond to the defect's emergence toward the surface along the crystallographic direction [11-20]. This directional extension is governed by the presence of Sicore dislocations at the leading edge, which defines the expansion front of the stacking fault according to the PD loop model[17]. Using Zhdanov's notation, the stacking sequence of the SSF is expressed as (1,3), and that of perfect SiC is (2,2). In the reported stacking representation of the bond configuration near the edge of a SSF in SiC (Fig. 4d), the left and right sides correspond to the perfect SiC crystal structure and the SSF region, respectively. Four slip planes, designated as α,β,γ, and δ, are identified. SSFs may form along these dislocation slip planes. For the specific 1SSF defect shape considered, according to the basal plane dislocation loop model [16], the C -core partial dislocations oriented along the [-1-120] and [11-20] crystallographic directions, are consistently located on the right side of the SSF, as reported in [18]. Consequently, the dislocation loop forms when the slip occurs on either the α or β slip planes. The Fig. 4d exemplifies the structural evolution from the perfect crystal stacking sequence, transitioning from an A′C′AB stacking to an A′BCA configuration through slip along the β plane.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

This study highlights the critical role of BPDs and the associated formation of 1 SSF in 4H−SiC epitaxial wafers, which can influence device performance through forward degradation mechanisms. Advanced diagnostic techniques, particularly μ-PL mapping, provide detailed spatial and spectral insights into the morphology and crystallographic nature of 1SSF within the epitaxial layers. The μ PL analysis effectively identifies and characterizes stacking fault expansions originating from BPDs, enabling precise localization and understanding of defect propagation. These insights are essential to guide epitaxial growth optimization and process control strategies, including thermal and oxidation treatments, to mitigate SSF-related degradation and enhance the reliability of SiC power devices. The integration of electrical testing with μ-PL and complementary microscopy techniques forms a comprehensive approach for monitoring stacking fault dynamics and improving wafer screening procedures.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

The authors would like to thank:

STMicroelectronics group involved in electrical stress in people of S. Bevilacqua, A. Terracina, L. Anoldo, G. Tosto;

GQR Laboratory of STMicrolectronics for their efforts in sample preparation and fault localization analysis, especially of G. Almirante, R. Lucifora, S. De Nizza, C. Realmuto.

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.43.pdf

Feng, Gan, Jun Suda, and Tsunenobu Kimoto. Physica B: Condensed Matter 404, no. 23-24 :4745-4748, (2009).

Thierry-Jebali, N., C. Kawahara, T. Miyazawa, H. Tsuchida, and T. Kimoto. AIP Advances 5, no. 3 (2015).

Palanisamy, Shanmuganathan, et al. 2021 IEEE International Reliability Physics Symposium (IRPS). IEEE, (2021).

J Wang, Pin, et al. Materials Science in Semiconductor Processing .

Piluso, Nicolo, et al. "High Quality 4H-SiC Epitaxial Layer by Tuning CVD Process." Materials Science Forum. Vol. 963. Trans Tech Publications Ltd, 2019.

A. Agarwal, H. Fatima, S. Haney, and S. H. Ryu, IEEE Electron Device Lett. 28, 587 (2007).

Piluso, Nicolo, et al. " defects analysis by Micro Raman spectroscopy." Materials Science Forum. Vol. 821. Trans Tech Publications Ltd, 2015.

H. Lendenmann, F. Dahlquist, N. Johansson, R. Söderholm, P.Å. Nilsson, J.P. Bergman, and P. Skytt, Long term operation of 4.5 kV PiN and 2.5 kV JBS diodes, Mater. Sci. Forum 353356 (2001), pp. 727-730.

H. Jacobson, J. Birch, R. Yakimova, M. Syväjärvi, J.P. Bergman, A. Ellison, T. Tuomi, and E. Janzén, Dislocation evolution in 4H-SiC epitaxial layers, J. Appl. Phys. 91 (2002), pp. 63546360.

H. Jacobson, J.P. Bergman, C. Hallin, E. Janzén, T. Tuomi, and H. Lendenmann, Properties and origins of different stacking faults that cause degradation in SiC PiN diodes, J. Appl. Phys. 95 (2004), pp. 1485-1488.

S. Ha, M. Benamara, and M. Skowronski, Core structure and properties of partial dislocations in silicon carbide p-i-n diodes, Appl. Phys. Lett. 83 (2003), pp. 4957-4959.

S. Ha, M. Skowronski, and H. Lendenmann, Nucleation sites of recombination-enhanced stacking fault formation in silicon carbide p-i-n diodes, J. Appl. Phys. 96 (2004), pp. 393-398.

Calabretta, Cristiano, et al. "Impact of nitrogen on the selective closure of stacking faults in 3CSiC." Crystal Growth & Design 22.8 (2022): 4996-5003.

Calabretta, Cristiano, et al. "Exploring crystal recovery and dopant activation in coated laser annealing on ion implanted epitaxial layers." Materials Science in Semiconductor Processing 174 (2024): 108175.

Stahlbush, M.E. Twigg, J.J. Sumakeris, K.G. Irvine, and P.A. Losee, Mechanisms of stacking fault growth in SiC PiN diodes, Mater. Res. Soc. Symp. Proc. 815 (2004), p. 103.

Iijima, Akifumi, et al. Philosophical Magazine 97.30: (2017), 2736-2752.

Kimoto, Tsunenobu, and James A. Cooper. Fundamentals of silicon carbide technology: growth, characterization, devices and applications. John Wiley & Sons, 2014.

Matsuhata, Hirofumi, et al. "Contrast analysis of Shockley partial dislocations in 4H-SiC observed by synchrotron Berg-Barrett X-ray topography." Philosophical Magazine 94.15 (2014): 1674-1685.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 49-54

doi: 10.4028/p-kNQ0l1

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2026-01-06

Accepted:
2026-01-31

Online:
2026-05-18

Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

Takashi Yoda 1,a*, Masaki Sano 3, b, Jun Kojima 4,c, Shoichi Onda 4, d, Anton Myalitsin 1,e, Kuniyuki Kakushima 1,2,f, Takayuki Ohba 1, g, Atsushi Oshiyama 4,5,h and Kenji Shiraishi 3,5,i

1 WOW Alliance, 2 School of Engineering, Institute of Science Tokyo, 4259 Nagatsuta, Midori-ku, Yokohama, 226-8503, Japan

3 Graduate School of Engineering, 4 Institute of Materials and Systems for Sustainability, Nagoya University, Nagoya, Aichi 464-8603/8601, Japan

5 Center for Innovative Integrated Electronic Systems, Tohoku University,Sendai, 980-8572, Japan

a*yoda.t.efe9@m.isct.co.jp, b  sano.masaki.0328@outlook.jp, c  kojima.jun.t2@f.mail.nagoya-u.ac.jp, d  onda.shoichi.n9@f.mail.nagoya-u.ac.jp, e  anton@anvos-analytics.com,

f  kakushima.k.aa@m.titech.ac.jp, c  ohba.t.ac@m.titech.ac.jp, h  atsushi.oshiyama.b5@tohoku.ac.jp, ikenji.shiraishi.c2@tohoku.ac.jp

Abstract

Suppressing the expansion of Single Shockley-type stacking faults (1SSFs) is critical for the growing demand of high-performance power devices. However, the underlying suppression mechanism has not yet been fully elucidated. Through proton ion implantation studies, we have established a fundamental approach by modeling this phenomenon. Carbon vacancy ( Vc ) generated by high-energy proton implantation are found to play a significant role in suppressing the expansion of 1SSFs.

Keywords: silicon carbide (SiC), power devices, basal plane dislocations (BPDs), Single Shockleytype stacking faults (1SSFs), proton implantation, density functional theory (DFT), photoluminescence (PL), cathodoluminescence (CL), carbon vacancies ( Vc ).

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

Silicon carbide ( SiC ) power devices exhibit superior performance compared to conventional silicon-based counterparts, enabling operation at higher voltages and frequencies with enhanced power efficiency and reduced energy losses. However, during the epitaxial growth of SiC , basal plane dislocations (BPDs) propagate from the substrate into the epitaxial layer. Further complications arise from the fact that BPDs dissociate into pairs of partial dislocations (PDs) on the basal plane, accompanied by Single Shockley-type stacking faults (1SSFs), which expand when low-energy holes interact with the Si-core. The expansion of these 1SSFs leads to bipolar degradation [1]. Practical proposal to suppress the 1SSFs expansion have been actively developed and reported [2-11]. A standard solution is to design a recombination-enhancing buffer layer [12]. Proton implantation has also emerged as a promising technique for suppressing the formation of 1SSFs [13-16]. As alternative candidates, implantation techniques using helium and other ion species have been investigated [1719]. More recently hydrogen plasma treatment, which causes less damage to the device, has also been reported [20]. At the early stage of proton implantation development, various mechanisms for suppressing 1SSFs expansion, including hydrogen-related effects, were actively discussed. Nevertheless, as research on helium and other ion implantations has advanced, the role of vacancies has increasingly come into focus. In this study, we evaluate the impact of proton implantation on the suppression of the expansion of 1SSFs. Furthermore, we investigate the underlying suppression mechanisms by analyzing the atomic and electronic structures surrounding the 1SSFs.

Experimental and Modeling

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

The epitaxial films used in this study consisted of a 10−μm-thick drift layer grown on an n-type 4H−SiC substrate. Two types of 4H−SiC epitaxial films were subjected to proton implantation at depths of 5μ m and 10μ m from the epitaxial surface, respectively. The proton implantation conditions were 0.6 MeV for the 5−μm depth and 0.95 MeV for the 10−μm depth, with an identical dose of 1×1015cm−2. Following proton implantation, the samples were irradiated with ultraviolet (UV) light to promote the expansion of 1SSFs. The UV irradiation was carried out using a 355 nm Nd:YAG laser with an output power of 10 W and a spot size of 3 mm in diameter. Photoluminescence (PL) imaging through a 420−nm bandpass filter was employed to monitor the evolution of 1SSFs. Specimens for scanning transmission electron microscopy (STEM) were prepared using a focused ion beam (FIB) system (Helios 660, FEI). Cross-sectional STEM observations of 1SSF edges were performed with a JEM-ARM300F2 (JEOL) operated at an acceleration voltage of 300 kV . Cross-sectional cathodoluminescence (CL) measurements were conducted using a Schottky-emission scanning electron microscope (SEM, S4300SE). The accelerating voltage was set to 10 kV with a beam current of ~2nA. CL spectra were collected at low temperature ( 28 K ) using a Si-CCD detector. For modeling basal plane dislocations (BPDs), 1SSFs, and vacancy structures, structural optimization and electronic state calculations were performed using the Vienna Ab initio Simulation Package (VASP), based on density functional theory (DFT) [21].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

We first evaluated photoluminescence (PL) imaging of the 10−μm-thick drift layer of 4H−SiC following proton implantation at a depth of 5μ m from the epitaxial surface (Fig. 1). Figure 2 shows a bright-field STEM cross-sectional image corresponding to the region indicated by the red arrow in Fig. 1. The image clearly demonstrates that proton implantation effectively suppresses the expansion of 1SSFs. The expansion of 1SSFs was terminated by a partial dislocation (PD) located at 5.8μ m below the surface of the epitaxial layer, which is nearly identical to the targeted implantation depth of 5μ m. Subsequently, cross-sectional CL measurement s were performed for both the 5−μm and 10−μm proton-implanted epitaxial layers, as shown in Fig. 3 and 4. Three main features were identified in the spectra: near-bandedge emission ( 375−400 nm ), broad emission ( 430−700 nm ), and silicon vacancy ( Vssi )-related emission ( 852 nm and around 950 nm ). Figure 5 shows the CL spectra near 380−nm peak wavelength, comparing the results for proton implantation

[picture]

Fig. 1. PL-Imaging after proton implantation. Red arrow indicates STEM area.

Fig. 1. PL-Imaging after proton implantation. Red arrow indicates STEM area.

depths of 5μ m and 10μ m from the epitaxial film surface.

[picture]

Fig. 2. BF-STEM cross sectional image of SSF expansion suppressed by proton irradiation.

Fig. 2. BF-STEM cross sectional image of SSF expansion suppressed by proton irradiation.

[picture]

Fig. 3. CL spectra of 5μ m depth proton irradiated sample.

Fig. 3. CL spectra of 5 μ m depth proton irradiated sample.

[picture]

Fig. 4. CL spectra of 10μ m depth proton irradiated sample.

Fig. 4. CL spectra of 10 μ m depth proton irradiated sample.

[picture]

Fig. 5. Cross sectional CL spectra after proton implantation up to 5μ m and 10μ m from the epitaxial film surface.

Fig. 5. Cross sectional CL spectra after proton implantation up to 5 μ m and 10 μ m from the epitaxial film surface.

[picture]

Fig. 6. CL area intensity depth profile between 5μ m and 10μ m depth proton implantation sample.

Fig. 6. CL area intensity depth profile between 5 μ m and 10 μ m depth proton implantation sample.

This peak is generally attributed to near-band-edge emission arising from transitions between the conduction band minimum (CBM) to the valence band maximum (VBM). The cumulative intensity distribution in the 375−400 nm range is presented in Fig. 6. The data reveal that, up to the proton implantation depth, only weak emission signals are detected, suggesting the presence of non-emissive centers in the implanted region, most likely associated with vacancies. Vsi-related emission was also observed in Figs. 3 and 4. However, since the majority of intrinsic defects in 4H-SiC are carbon vacancies ( VC ) due to their lower formation energy, the dominant defects are expected to be VC rather than VSi. It should be noted that CL measurements can sometimes enhance Vsi-related emission because of the deep and stable energy levels of VSi. In this study, the specific vacancy type could not be conclusively identified. Vacancies generated by proton implantation are likely to include Vc, Vsi, and their complexes. However, considering the formation energies and experimental support from previous defect studies using deep level transient spectroscopy (DLTS) after proton implantation [16], in which a peak assigned to the Z1/2 center (origination from VC ) was observed, VC is the most favorable to form and thus represents the most plausible candidate. A Fundamental analysis of the dynamic behavior of defects during ion implantation has been reported in [22]. Building on these insights, we investigated the mechanism responsible for the suppression of 1SSF expansion induced by proton implantation. To this end, we incorporated carbon vacancies ( Vc ) near the expanded 1SSFs in our model and performed first-principles calculations. The employed model is illustrated in Fig. 7. The green ball in Fig. 7 denotes the nearest-neighbor Si atom, the brown dotted circle represents a carbon vacancy ( Vc ). According to our calculations, once a Vc is created, the nearest Si atoms form a pair to achieve stabilization. Analysis of the atomic distance after geometry optimization shows bond lengths of 2.71\AA and 2.77\AA, respectively. Compared with the typical Si−Si bond length in the Si -core (~2.4\AA), the Si-Si pair distance is slightly larger.

[picture]

Fig. 7. Side view of the 4H−SiC model with SSF and VC. Enlarged view of the model vicinity of the VC are also depicted.

Fig. 7. Side view of the 4 H − S i C model with SSF and V C . Enlarged view of the model vicinity of the V C are also depicted.

To clarify the influence of Vc on 1SSFs expansion, we carried out a Local density of states (LDOS) analysis. The results indicate that both the Si−Si bond beneath the Vc and the Si−Si bond in Si -core introduce electronic states within the bandgap. Notably, the Si−Si bond in the vicinity of the Vc is associated with deeper states within the bandgap. Based on these findings, we propose the following mechanism: when a Vc is located near a 1SSF, electrons associated with the Si−Si bond at Vc site may transfer to the Si−Si bond in the Si -core, which is responsible for hole trapping. Consequently, the occupied Si-core can no longer capture holes, thereby suppressing the expansion of 1SSFs (Fig. 8).

[picture]

Fig. 8. The energy levels and wavefunctions of Si−Si bond in Vc (green energy level) and Si−Si bond in Si -core (red energy level), respectively.

Fig. 8. The energy levels and wavefunctions of S i − S i bond in Vc (green energy level) and S i − S i bond in Si -core (red energy level), respectively.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

In this study, we investigated the suppression mechanism of 1SSF expansion by evaluating the impact of proton implantation, with particular focus on vacancy-related effects, using cross-sectional CL spectra. In addition, we performed LDOS analysis to clarify the atomic and electronic structures around carbon vacancies. The results suggest that when carbon vacancies are formed in the vicinity of 1SSFs, suppressions of their expansion arises from the inhibition of hole capture at the Si -core by these vacancies. This study provides new insights into the mechanism of 1SSF suppression and may offer valuable guidance for future process improvement.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

A part of this work was supported by MEXT as "Program for promoting research on the supercomputer Fugaku" (Quantum theory-based multiscale simulations toward development of nextgeneration energy saving semiconductor devices, Project No. JPMXP1020200205). The authors wish to thank Toray Research Center for analysis and advice.

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.49.pdf

T. Kimoto, Material science and device physics in SiC technology for high-voltage power devices, Jpn. J. Appl. Phys. 54, 0040103(2015).

E. Vuillermet, N. Bercu, F. Etienne and M. Lazar, Cathodoluminescence Characterization of Point Defects Generated through Ion Implantations in 4H-SiC, Coatings, 13, 992 (2023).

H. Tsuchida, K. Murata, T. Tawara et al., Suppression of Bipolar Degradation in 4H-SiC Power Devices by Carrier lifetime Control, IEDM (2019).

T. Tawara, S. Matsunaga, T. Fujimoto et al., Injected carrier concentration dependence of the expansion of single Shockley-type stacking faults in 4H-SiC PiN diodes, J. Appl. Phys. 123, 025707 (2018).

T. Tanaka, H. Shiomi, N. Kawabata et al., Expansion and contraction of single Shockley stacking faults in SiC epitaxial layer under ultraviolet irradiation, Appl. Phys. Express, 12, 041006 (2019).

A. Iijima and T, Kimoto, Estimation of the critical condition for expansion/contraction of single Shockley stacking faults in 4H-SiC PiN diodes, Appl. Phys. Lett. 116, 092105 (2020).

T. Kimoto and H. Watanabe, Defect engineering in SiC technology for high-voltage power devices, Appl. Phys. Express, 13,120101 (2020).

K. Maeda, K. Murata, I. Kamata and H. Tsuchida, Mechanical-stressing measurements of formation energy of single Shockley stacking faults in 4H-SiC, Appl. Phys. Express, 14, 044001 (2021).

A.T. Blumenau, C. J. Fall, R. Jones, S. Oberg, T. Frauenheim and P. R. Briddon, Structure and motion of basal dislocations in silicon carbide, Phys. Rev B 68, 174108 (2003).

A. Galeckas, J. Linnros, P. Pirouz, Recombination-Induced Stacking Faults: Evidence for a General Mechanism in Hexagonal SiC, Phys. Rev. Letters, 96, 025502 (2006).

A. Iijima and T. Kimoto, Electronic energy model for single Shockley stacking fault formation in 4H-SiC crystals, J. Appl. Phys. 126, 105703 (2019).

T. Tawara, T. Miyazawa, M. Ryo et al., Short minority carrier lifetimes in highly nitrogendoped 4HSiC epilayers for suppression of the stacking fault formation in PiN diodes, J. Appl. Phys. 120, 115101 (2016).

M. Kato, O. Watanabe, T. Mii, H. Sakane and S. Harada, Suppression of stacking-fault expansion in PiN diodes using proton implantation to solve bipolar degradation, Scientific Reports 12, 18790 (2022).

S. Harada, T. Mii, H. Sakane and M. Kato, Suppression of stacking fault expansion in a epitaxial layer by proton irradiation, Scientific Reports 12, 13542 (2022).

M. Kato, O. Watanabe, S. Harada and H. Sakane, Effects of proton implantation into 4H-SiC substrate: Stacking faults in epilayer on the substrate, Mater. Sci. Semicond. Process, 175, 108264 (2024).

M. Kato, T. Li, H. Sakane and S. Harada, Observation of point defect and carrier lifetime distributions in hydrogen or helium ion implanted SiC PiN diodes for suppression of bipolar degradation, Jpn. J. Appl. Phys. 64, 010901 (2025).

T. Li, H. Sakane, S. Harada and M. Kato, Suppression of stacking-fault expansion in 4H-SiC diodes by helium implantation, Appl. Phys. Express, 17, 086503 (2024).

B. Chen, H. Matsuhata, T. Sekiguchi et al., Pinning of recombination-enhanced dislocation motion in 4H-SiC: Role of Cu and complex, Appl. Phys. Lett. 96, 212110 (2010).

J. Nishio, C. Ota and R. Iijima, Comparison of single Shockley-type stacking fault expansion rates in under ultraviolet illumination after hydrogen or fluorine ion implantation, Jpn. J. Appl. Phys. 63, 101015 (2024).

T. Li, H. Sakane, S. Harada et al., Hydrogen and point defect introduction into by plasma treatment, Jpn. J. Appl. Phys. 64, 051003 (2025).

G. Kresse and D. Joubert, From ultrasoft pseudopotentials to the projector augmented-wave method, Phys. Rev. B 59, 1758 (1999).

X. Liu, F. F. Ren, Z. Wang et al., Dynamic reactions of defects in ion-implanted upon high temperature annealing, J. Phys. D: Appl. Phys. 56, 235102 (2023).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 55-62

doi: 10.4028/p-Jc6le5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-18

Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method

The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

Zeyu Chen 1,a, Jianpei Zhang 1, b, Shanshan Hu 1,c, Kaixuan Zhang 1, d, Yuzhuo Li1,e, Haochi Wang 1,f, Balaji Raghothamachar 1, g, Yafei Liu 2, h, Campbell Bouch 2,i, Ryan Philpott 2,j, Scott Turchetti 2,k, Pete Schunemann 2,l and Michael Dudley 1, m

1 Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY, 11794, USA

2 Onsemi, 55 Executive Drive, Hudson, NH, 03051, USA

a  zeyu.chen@stonybrook.edu, bjianpei.zhang@stonybrook.edu, c  shanshan.hu@stonybrook.edu, d  kaixuan.zhang@stonybrook.edu, e  yuzhuo.li@stonybrook.edu, f  haochi.wang@stonybrook.edu, g  balaji.raghothamachar@stonybrook.edu, h  yafei.liu@onsemi.com, iCampbell.Bouch@onsemi.com, jRyan.Philpott@onsemi.com, k  Scott.Turchetti@onsemi.com, 'Pete.Schunemann@onsemi.com,  mmichael.dudley@stonybrook.edu

Keywords: 4 H -SiC; Characterization; X-ray Topography; Defects

Abstract

Synchrotron monochromatic beam X-ray topography (SMBXT), synchrotron white beam X-ray topography (SWBXT) and high-resolution X-ray topography (HRXRT) were used to characterize a series of wafers sliced from two PVT-grown 4H−SiC boules under similar growth conditions. A unique spoke-shaped distribution of the threading screw/mixed dislocations (TSDs/TMDs) density map can be observed from wafers sliced from later stages of growth of both boules. Systematic sequential analysis of the SMBXT grazing incidence images and HRXRT reflection images of the wafers reveals the spoke patterns are formed due to continuous deflection process of TSDs/TMDs by thin layer of polytypes that propagate along step flow direction and expand vertically, leading to TSD density difference across the wafer. Regions with high TSD densities have higher growth rate, resulting in a ridge and valley structure. Generation of macrosteps in the valley regions due to regular step structure deflect more TSDs/TMDs that then form mixed type (Shockley+Frank) stacking faults.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

Silicon carbide ( SiC ) is a semiconductor with a wide bandgap and exceptional electronic and physical properties, including high saturation velocity, high breakdown field, and excellent thermal conductivity [1]. These attributes make SiC a highly promising material for demanding applications involving high voltage, high power, and high temperature environments. The development of largescale, high-quality single crystal SiC substrate wafers is crucial for enhancing device performance and broadening its application scope. Among the available growth techniques, physical vapor transport (PVT) [2] is the most widely used method, as it allows the production of large SiC substrates with controllable growth rates. However, the presence of various crystallographic defects, such as threading screw/mixed dislocations (TSDs/TMDs) and micropipes (MPs) can significantly impact device performance, limiting the full potential of SiC-based technologies [3,4]. Therefore, the generation and impact of such defects during PVT growth should be thoroughly investigated to improve the growth process and furnace design.

Besides replication from the seed, TSDs/TMDs pairs are usually generated at the seed interface if large stress is present or at the interface of inclusions [5-7]. Deflections of TSDs/TMDs onto the basal plane have been observed previously [8], where TSDs/TMDs get deflected by macrosteps formed at the later stage of the growth when the curvature of the growth interface becomes higher. In this study, series of 4H−SiC wafers sliced from two boules grown under similar conditions were analyzed by synchrotron white beam X-ray topography (SWBXT) in 1-100 and 1-101 reflections to map the
distribution of stacking faults. Mappings of TSDs/TMDs densities were conducted by high resolution X-ray topography (HRXRT) in 0008 reflection, where relatively high density of TSDs/TMDs are nucleated at the beginning of the growth, that then continuously get deflected as the growth proceeds. Such deflected TSDs/TMDs can possibly dissociate into partials dislocations bounding Frank type/mixed (Frank+Shockley) type stacking faults [9,10], which will lead to increase of forward voltage and leakage currents [11-14]. The nature and mechanism of such deflection process need to be analyzed carefully in order to improve the design of the furnace and refine the growth processing.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

Series of wafers sliced from two PVT-grown boules have been characterized and the position of the wafers with respect to the boules are shown in Fig. 1. Synchrotron Monochromatic Beam X-ray Topography (SMBXT) in grazing incidence geometry is an X-ray imaging technique capable of revealing the structural defects in the crystal up to a depth of 17μ m. Monochromatic beam (E=8.9KeV) is used in SMBXT and 11-28 grazing incident reflection is recorded on high resolution X-ray films. Synchrotron white beam X-ray topography (SWBXT) in transmission geometry are used to characterize stacking faults and 1-100 and 1-101 reflection via SWBXT were recorded. Experiments were carried out at Beamline 1-BM at the Advanced Photon Source (APS), Argonne National Laboratory. Ray-tracing simulation was conducted for inclusion contrast on topographs of 4H-SiC in 11-28 reflection through a Python algorithm based on orientation contrast model [15].

High-resolution x-ray topography (HRXRT) was performed using a Rigaku XRTMicron system. XRT image of TSDs/TMDs was acquired using g=[0008] in reflection geometry with CuKα radiation. TSD maps were generated by XRT Toolbox software, an automatic XRT data processing tool to generate defect analysis reports.

[picture]

Boule 1

Figure 1. Boule 1

[picture]

Boule 2

Figure 2. Boule 2

Fig. 1. Schematic diagram of PVT boules showing position of wafers sliced from the boules discussed in this study.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

Selected areas of HRXRT images in 0008 reflection of wafer1, 2, 4 and 5 of boule 1 are shown in Fig. 2(a), 2(b), 2(d), 2(e), 2(g) and 2(h), respectively with wafer1 closest to seed. Some of the line features observed on the topographs are highlighted by dashed red lines in images of wafer1 and wafer4, as shown in Fig. 2(a), 2(d) and 2(g). These features are observed to propagate and expand during growth as highlighted with orange dotted lines in images of wafer2 and wafer5, as shown in Fig. 2(b), 2(e) and 2(h). The stacked images, as shown in Fig. 2(c), 2(f) and 2(i), indicate that the line features propagate along the radial step flow direction and expand along [1-100] or [-1100] directions. To further investigate, SMBXTs in 11-28 reflection of wafer4 and wafer5 are shown in Fig. 3(a) and 3(b), where the line features are indicated by the red dotted line. Similar to the observation from HRXRT, the same line features can be detected from SMBXTs of wafer4 and wafer5, indicating that the line feature propagated in the boule on the basal plane during growth and deflected a bundle of TSDs/TMDs as indicated by the orange arrows. Ray tracing simulation was conducted to show contrast of a column of inclusion, where the result, as shown in Fig. 3(c), indicates white line contrast bounded by two dark lines, correlating with the line contrast observed from SMBXTs. Since the line
features have same contrast as a column of inclusions and they can propagate and expand on the basal plane, it strongly indicates that the line features are likely polytypes. Besides, since the width of the line feature in SMBXTs is around 40μ m comparable to the width of deflected TSDs/TMDs, the actual thickness of the polytype layers can be extremely small (tens of \AA ).

[picture]

Fig. 2. HRXRT images of (a) and (d) wafer 1 of boule 1; (b) and (e) wafer 2 of boule 1; (g) wafer 4 of boule 1 and (h) wafer 5 of boule 1. (c), (f) and (i) show stacked images of (a) and (b), (d) and (e), (g) and (h) respectively. Line features can be observed in individual images, and the stacked images indicate such line features propagate along step flow direction and expand along [1-100] or [-1100] direction.

Fig. 2. HRXRT images of (a) and (d) wafer 1 of boule 1; (b) and (e) wafer 2 of boule 1; (g) wafer 4 of boule 1 and (h) wafer 5 of boule 1. (c), (f) and (i) show stacked images of (a) and (b), (d) and (e), (g) and (h) respectively. Line features can be observed in individual images, and the stacked images indicate such line features propagate along step flow direction and expand along [1-100] or [-1100] direction.

[picture]

Fig. 3. 11-28 SMBXT of (a) wafer 4 and (b) wafer 5, showing that the line features deflect TSDs/TMDs. (c) shows ray tracing simulation of a column of inclusions.

Fig. 3. 11-28 SMBXT of (a) wafer 4 and (b) wafer 5, showing that the line features deflect TSDs/TMDs. (c) shows ray tracing simulation of a column of inclusions.

Deflection of TSDs/TMDs by polytype can be observed in Fig. 3(a) and 3(b). Fig. 4(a) depicts 3D schematic of nucleation of polytype, where 2D nucleation takes place on the flat terrace due to relatively fast growth, then the polytype will then expand with the step as shown in Fig. 4(b) and 4(c). The polytypes will deflect TSDs/TMDs, since the Burgers vectors of TSDs/TMDs in 4H are not
compatible with the polytype, and deflection onto the basal plane will be more energetically favorable. In addition, misfit stress between the polytype and the newly grown layer will also facilitate nucleation of new TSDs/TMDs as shown in Fig. 4(d).

[picture]

Fig. 4. Schematic of (a) nucleation of polytype, (b) and (c) deflection of TSDs/TMDs by polytype and (d) nucleation of TSDs/TMDs from polytype.

Fig. 4. Schematic of (a) nucleation of polytype, (b) and (c) deflection of TSDs/TMDs by polytype and (d) nucleation of TSDs/TMDs from polytype.

Fig. 5 shows the propagation and expansion of polytype at different parts of the wafer and with vertical step and curved step directions. At the beginning of the growth the step direction will be vertical near the central part of the wafer then slightly curved around the edge since the relatively flat growth front, as shown by T. Ailihumaer and coworkers [16]. Fig. 5(a) and 5(b) show propagation and expansion process of wafer 1 of boule 1 (stack image shown in Fig. 2(c) and 2(f)), and Fig. 5(c) and 5(d) show the process of wafer 4 of boule 1(stack image shown in Fig. 2(i)). As discussed above, the inner edge of the polytype will follow the step flow direction (perpendicular to step direction) and the other edge will expand along vertically, where faster growth takes place toward the edge of the wafer since C/Si ratio is higher at the position closer to the graphite crucible. Moreover, the polytypes expand quickly and occupy relatively large area of the wafer since the vertical step direction along [1-100] or [-1100] is the shortest distance to the edge of the wafer. Fig. 5(i) and 5(j) show comparison between polytype in wafer3 at early stage of growth and wafer7 at later stage of growth, where the size of the polytypes are slightly smaller in wafer7. When the growth proceeds to the later stage, the step direction will become curved as the curvature of the growth interface increases. Under such circumstances, the step direction will no longer be the shortest distance to the edge of the wafer, so the expansion will take place slightly slower, as indicated in Fig. 5(e) and 5(f). If the polytype is generated at the center of the wafer, both edges of the polytype will expand, since the gradient of C/Si ratio are similar for both sides.

Fig. 6(a) to 6(d) indicates TSDs/TMDs density map of wafer3, wafer6, wafer7 and wafer8, where red color means that TSDs/TMDs density is higher than manually set threshold value. Since deflections of TSDS/TMDs have been observed in HRXRT, the decrease of TSDs/TMDs density can be mainly attributed to deflections of TSDs/TMDs by the polytype layers. Even though deflection by polytype layers take place continuously starting from wafer1, such polytypes also nucleate new TSDs/TMDs as explained previously, so TSDs/TMDs density is relatively high at the early growth stage, as shown in Fig. 6(a). It should be noted that the remaining TSDs/TMDs formed a spoke-like pattern at the later stage of growth (Fig. 6(b) to 6(d). As the growth proceeds to wafer 6, the step direction becomes curved and the expansions of polytypes are slower. Fig. 6(e) depicts propagation and expansions of multiple polytypes, where one side of the polytypes at the inner region follow the step flow direction (dashed line) and the other side will expand (solid line), and polytype at the center will expand on both sides. It can be observed that the gaps between the polytypes, formed due to the difference between propagation and expansion direction, correlate with the spoke-like feature in Fig. 6(d), since fewer deflections will take place in the gap region.

Deflection process starts from the left side first (Fig. 6(b) and 6(c)) and the deflection on the right side of the wafer takes place at the later stage (Fig. 6(d)). As shown in Fig. 6(f), when the interface is slightly curved, the width of the terrace is longer on the left side, then as the curvature of the growth interface increase, the facet will migrate towards the center of the boule, shortening the terrace on the left side and terrace on the right side will become longer, where a longer width of the terrace will increase the probability of 2D nucleation of polytype.

[picture]

Fig. 5. Schematic of propagation and expansion of polytype with vertical step direction (a) and (b) near the edge; (c) and (d) near the center. Schematic of propagation and expansion of polytype with curved step direction (e) and (f) inner region of the wafer; (g) and (h) at the center of the curved step. HRXRD image of polytype of (i) wafer3 at early stage of the growth and (j) wafer7 at later stage of growth.

Fig. 5. Schematic of propagation and expansion of polytype with vertical step direction (a) and (b) near the edge; (c) and (d) near the center. Schematic of propagation and expansion of polytype with curved step direction (e) and (f) inner region of the wafer; (g) and (h) at the center of the curved step. HRXRD image of polytype of (i) wafer3 at early stage of the growth and (j) wafer7 at later stage of growth.

[picture]

Fig. 6. TSDs/TMDs density map from HRXRD of (a) wafer3, (b) wafer6, (c) wafer7 and (d) wafer8, where red color means that TSDs/TMDs density is higher than manually set threshold value. (e) shows propagation and expansion of polytypes on the left side of the wafer resulting in gaps between that correspond to the shape of the TSDs/TMDs density map in (d). (f) shows change of width of terrace as growth proceeds. where the terraces on the left side of the facet is narrower initially, then become longer as the growth proceeds.

Fig. 6. TSDs/TMDs density map from HRXRD of (a) wafer3, (b) wafer6, (c) wafer7 and (d) wafer8, where red color means that TSDs/TMDs density is higher than manually set threshold value. (e) shows propagation and expansion of polytypes on the left side of the wafer resulting in gaps between that correspond to the shape of the TSDs/TMDs density map in (d). (f) shows change of width of terrace as growth proceeds. where the terraces on the left side of the facet is narrower initially, then become longer as the growth proceeds.

[picture]

Fig. 7. SWBXT of wafer4 boule 2 in (a) 1−101 reflection and (b) 1−100 reflection, showing unique pattern of stacking faults where the spoke patterns are highlighted in dotted lines; (c) to (f): TSDs/TMDs density maps of wafers sliced from boule 2 at the position closer to the seed then further away from the seed.

Fig. 7. SWBXT of wafer4 boule 2 in (a) 1 − 101 reflection and (b) 1 − 100 reflection, showing unique pattern of stacking faults where the spoke patterns are highlighted in dotted lines; (c) to (f): TSDs/TMDs density maps of wafers sliced from boule 2 at the position closer to the seed then further away from the seed.

Wafer4 of boule 2 was analyzed by synchrotron white beam X-ray topography (SWBXT) in 1100 and 1-101 reflections. Mappings of TSDs/TMDs density for wafer1 to wafer4 sliced from boule 2 were conducted by HRXRD in 0008 reflection. As shown in Fig. 1, wafers sliced from boule 2 are from later stage of growth. Fig. 7(a) and 7(b) show the SWBXT in 1-100 and 1-101 reflections, where formation of stacking faults due to deflection of the TSDs/TMDs can be observed in the region between the spoke pattern which is highlighted by the dotted lines, where based on g.b analysis, majority of the stacking fault will be mixed type (Shockley+Frank), since 1-100 reflection shows stronger contrast of the faults [17]. Fig. 7(c) to 7(f) show density maps of TSDs/TMDs from the seed side (wafer1) to the dome side(wafer4), where higher density of TSDs/TMDs were observed near the facet region (Fig.7(c)) and the TSD/TMD density decreases as the wafer is closer to the dome side.

The pattern of wafer sliced from later stage of boule 2 show similarity to wafer8 of boule 1 (Fig. 6(d), indicating that deflections by polytypes exist in boule 2 as well. To further analyze the process, the TSDs/TMDs color maps are rescaled to see the difference on the spoke feature. Here, the spoke feature near the center of the wafer, highlighted by the red dotted box, will be specifically analyzed. Two areas with lower TSDs/TMDs density between the central spoke are highlighted by the white dashed line eclipse. Generally, TSDs/TMDs will have a faster growth rate than other parts of the crystal and form spiral steps during the growth [18], then when these steps merge, a growth island will be formed on the surface as shown in Fig. 8(a). When the growth proceeds, step bunching and polytypes will deflect TSDs/TMDs toward the step flow direction (Fig.8(b) and (c)). Since the density of TSDs/TMDs are lower on either side of the central spoke, as shown by the arrows of Fig.7(c), the growth rate along [000-1] will be slower in those regions, leading to ridge formation on the spoke positions, as shown in Fig.8(d). The ridge structure on the growth interface will be similar to star pattern observed from the facet [19]. Fig. 8(h) shows the top view of step structure of the ridge, where curved steps will form on the ridge (on the spoke position), while the valley will have normal steps conducive to forming a macrostep. Such step structure will suppress the formation of polytype on the ridge and the accumulated macrostep between the spoke can cause the deflection of TSDs/TMDs in
that region (Fig.8(e)), correlating with the decrease of TSDs/TMDs density between the spoke region in Fig. 7(d). Finally, as the growth interface becomes more convex, all the TSDs/TMDs will be deflected as shown in Fig. 8(f) and (g).

[picture]

Fig. 8. 3D schematic of (a) growth island formed due to faster growth rate at the region with higher TSDs/TMDs density, (b) and (c) deflection of TSDs/TMDs by step bunching and polytype, (d) ridge structure formation due to difference in TSDs/TMDs density, (e) deflection process between the spoke region, (f) and (g) defection of TSDs/TMDs by macrostep; (h) step structure on the ridge and valley.

Fig. 8. 3D schematic of (a) growth island formed due to faster growth rate at the region with higher TSDs/TMDs density, (b) and (c) deflection of TSDs/TMDs by step bunching and polytype, (d) ridge structure formation due to difference in TSDs/TMDs density, (e) deflection process between the spoke region, (f) and (g) defection of TSDs/TMDs by macrostep; (h) step structure on the ridge and valley.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

Synchrotron monochromatic beam X-ray topography, synchrotron white beam X-ray topography and high-resolution X-ray topography were used to characterize series of wafers sliced from two PVTgrown 4 H -SiC boules grown under similar conditions. Spoke pattern on TSDs/TMDs density map can be observed from wafer sliced from later stage of growth of both boules. Deflections of TSDs/TMDs by 2D nucleated thin polytype layers due to relatively fast growth rate have been observed, since Burgers vector of TSDs/TMDs in 4H structure is not compatible in polytype. The polytypes will propagate and expand, where one of the edges will follow the step flow direction and the other edge will expand along [1-100] and [-1100] directions. At the early stage of growth, the polytype will expand quickly due to vertical step structure, while it will slow down when the step structures become curved at the later stage of growth. The difference in direction between the propagation edge and the expansion edge facilitates the formation of the spoke pattern. Such pattern will give rise to faster growth rate along [000-1], leading to formation of ridge on the growth interface. The ridge structure will suppress the formation of polytype on the ridge and also accumulate macrosteps between the spokes that subsequently cause the deflection of TSDs/TMDs and formation of stacking faults. Processing parameters such as growth rate should be optimized to avoid formation of the polytypes and the deflections of TSDs/TMDs.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

Work supported by Onsemi. This research used resources of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. This research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence for access to Advanced Photon Source.

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The original version of this paper is available on https://www.scientific.net/MSF.1190.55.pdf

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Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 63-67

doi: 10.4028/p-3WKk3V

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-19

Accepted:
2026-02-23

Online:
2026-05-18

Micropipes in SiC die Observed by Molten KOH Etching

The original version of this paper is available on https://www.scientific.net/MSF.1190.63.pdf

1 STMicroelectronics, Stradale Primosole, 50, Catania 95100, Italy

afabiana.vento@st.com, b  nicolo.piluso@st.com, c  cristiano.calabretta01@st.com, d  chiara.nania@st.com, e  domenica.raciti@st.com, f  ruggero.anzalone@st.com, g  andrea.severino@st.com

Keywords: KOH etching, micropipes, defects, SiC die, wide-bandgap materials.

Abstract

The growing demand for wide-bandgap (WBG) materials in the microelectronics industry has led to increased investment in medium- and high-voltage power products based on SiC technology. SiC offers an excellent balance between high voltage blocking capability, high temperature operation and high switching frequencies [1]. One key step in preparing highperformance devices is improving the growth process of SiC ingot material by Physical Vapor Transport (PVT). Epitaxial growth occurs through the chemical vapor deposition (CVD) method [2]. However, this method is reported to generate extended defects such as Complex Stacking Faults (formerly referred to as carrots) and Polytype Inclusions (formerly referred to as triangles or comets) and propagate defects pre-existing in the bulk material, such as micropipes (MPs) and threading screw dislocations (TSDs), which have a very high killer ratio in SiC devices [3, 4]. In this work, the KOH molten etching method was used to investigate the nature of the defects that caused device failures; Raman spectroscopy was also employed to identify the spectroscopic correspondence of the peaks of interest.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.63.pdf

During the last decade the increasing demand for high-power devices has drawn attention to WideBandgap (WBG) semiconductors. WBG materials include silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN) [5]. Among these, SiC exhibits characteristics that make it suitable for high power and high efficiency applications. However, the excellent prospects for using this material depend on its crystallinity. Crystal growth occurs through chemical vapor deposition (CVD), which ensures high-quality and high-purity SiC layers. Since the stacking of crystallographic planes can assume three different positions, this gives rise to cubic, hexagonal, or rhombohedral lattice structures called polytypes. Each polytype has unique electrical properties; 4H−SiC is the polytype with attractive properties for power devices due to its very high electron mobility, high breakdown field, and high thermal conductivity [6, 7]. However, the high concentration of structural defects, both extended and point defects, formed during ingot growth may lead to deterioration in the performance and reliability of semiconductor devices [8].
The dislocations commonly found in 4H-SiC can be classified as Threading Screw Dislocations (TSDs), Threading Edge Dislocations (TEDs), Basal Plane Dislocations (BPDs), and Micropipes (MPs) [9]. Some of these defects, such as MPs or TSDs spreading in the epi layer, cause fatal damage. Their identification and classification are a priority for using SiC devices. To study these types of defects present in substrates or the epitaxial layer of SiC, selective chemical etching in KOH is extensively used [10]. In this work, considering defect-preferred corrosion using molten KOH , three different failed dies were selected and analyzed.
For clarity, other extended defects propagated from dislocations are classified as Complex Stacking Faults (formerly referred to as carrots) and Polytype Inclusions (formerly referred to as triangles and comets). The detection and study of these defects have been extensively addressed [11, 12], as they are the cause of early electrical failure (usually no electrical stress or reliability tests are needed).

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1190.63.pdf

Three different dies were selected from failed samples to analyze the defects that caused the burning. A nickel crucible filled with KOH pellets was used for etching the samples, and the temperature was set to 540∘C for 12 minutes. After etching, the dies were cooled to room temperature and then washed with deionized water and isopropyl alcohol. A confocal microscope and scanning electron microscope (SEM) were used to observe the morphology of the etch pits on the surface. Raman spectroscopy was employed to identify the spectroscopic correspondence of the peaks of interest.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.63.pdf

Three cases of failed dice were selected and treated with molten KOH .
In the first case (Fig.1a), the burn-in was revealed by optical inspection, showing that the failure seems to involve multiple defects. By zooming in on the region marked in red, it is possible to see one large defect (inside the green circle) accompanied by a small feature (inside the blue circle), connected to each other (orange circle). The FIB cuts (Fig.1b) performed in three different regions show the effect of the burn; however, they do not clarify the nature of the defect. Treating the sample with molten KOH (Fig.1c) reveals a micropipe (MP) on the surface, accompanied by another one highlighted by the green and orange traces. This phenomenon is due to the propagation of MPs generated in the substrate that evolve into the epitaxial layer, producing closed-core threading screw dislocations. Confirmation of the generation of closed-core threading screw dislocations is also provided by the presence of connections (orange circle) between the defects emerging on the surface. The two mechanisms involved during this propagation, which lead to the formation of closed-core screw dislocations, are reported in Fig. 2 [13].

[picture]

Fig. 1. In a) the electrical failure acquired with optical microscope with dissociation (orange circle) of the MP; in b) FIB cuts in three different regions (FIB 1, FIB 2, FIB 3) of the sample; in c) KOH etching of the die at temperature of 540∘C, and time of 12 min detected by x 20 and x 50 obj .

Fig. 1. In a) the electrical failure acquired with optical microscope with dissociation (orange circle) of the MP; in b) FIB cuts in three different regions (FIB 1, FIB 2, FIB 3) of the sample; in c) KOH etching of the die at temperature of 540 ∘ C , and time of 12 min detected by x 20 and x 50 obj .

[picture]

Fig. 2. Illustration of a micropipe evolution with no- dissociation and dissociation into several closed-core screw dislocations during epitaxial growth. In the case of VSpiral ≫VStepFlow (a) the MP does not experience dissociation. In case of VSpiral ≪VStepFlow (b) the MP undergoes dissociation [11].

Fig. 2. Illustration of a micropipe evolution with no- dissociation and dissociation into several closed-core screw dislocations during epitaxial growth. In the case of V Spiral ≫ V StepFlow ( a ) the MP does not experience dissociation. In case of V Spiral ≪ V StepFlow ( b ) the MP undergoes dissociation [11].

The second case reported in Fig. 3 shows a symmetrical burn whose crystallographic nature is not immediately visible with optical investigation (Fig. 3a). However, by treating the sample in molten KOH (Fig. 3b), the characteristic morphology around the hole attributable to a MP, where each fingerprint is at 60∘ to the next, is visible and confirmed by SEM analysis (Fig. 3c). In this case, the MP does not experience dissociation into closed-core threading screw dislocations because the device is characterized by only one burn on the surface.

[picture]

Fig. 3. In a) the electrical failure acquired with optical microscope; in b) KOH etching of the die at temperature of 540∘C, and time of 12 min ; in c) the comparison between the SEM acquisition and optical inspection of the MP.

Fig. 3. In a) the electrical failure acquired with optical microscope; in b) KOH etching of the die at temperature of 540 ∘ C , and time of 12 min ; in c) the comparison between the SEM acquisition and optical inspection of the MP.

In the third case shown in Fig. 4, the burn (Fig. 4a) detected through optical inspection does not show only a symmetric defect but also an additional feature (underlined in red). By subjecting the sample to KOH etching (Fig. 4b), a MP emerges from the inspected region, accompanied by additional features. To define the chemical nature of this feature, Raman analysis was conducted (Fig. 4c). The Raman spectrum of region 1, attributed to the micropipe, shows both the presence of 4H−SiC ( 777 cm−1 ) and the presence of polytype (it can be assumed be 15R−SiC ) due to the appearance of a pick between 780−790 cm−1. Focusing on Fig. 4c, region 2, the Raman analysis shows peaks that determine the only presence of 4H−SiC. This excludes the involving polytypes in the detected area. Usually, the polytype is detected at the edge of the features, resulting from the electrical burning.

[picture]

Fig. 4. In a) the electrical failure acquired with optical microscope; in b) KOH etching of the die at temperature of 540∘C, and time of 12 min ; in c) Raman inspection in regions 1 and 2 .

Fig. 4. In a) the electrical failure acquired with optical microscope; in b) KOH etching of the die at temperature of 540 ∘ C , and time of 12 min ; in c) Raman inspection in regions 1 and 2 .

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1190.63.pdf

The growth conditions of 4H−SiC bulk material present significant challenges, particularly due to the presence of various crystal defects such as MPs, TSDs, and basal plane dislocations (BPDs). Among these, it is well known that MPs affect semiconductor quality and device performance because they cause electrical failures. Results from molten KOH etching, combined with SEM and Raman analysis, contribute to the investigation of the formation and propagation of defects. Understanding the evolution of electrical failures helps clarify the mechanisms involved, with the aim of controlling and managing MP density to improve the electrical efficiency of devices.

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The original version of this paper is available on https://www.scientific.net/MSF.1190.63.pdf

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Ohtani, Noboru, et al., Journal of crystal growth 286.1 (2006): 55-60.

Wang, Rong, et al. "Impurities and defects in 4H silicon carbide." Applied Physics Letters 122.18 (2023).

Wang, Hejing, et al. "Micropipes in SiC single crystal observed by molten KOH etching." Materials 14.19 (2021): 5890.

P. Fiorenza, et. al., Materials Science in Semiconductor Processing 194, 109575 (2024).

Lei Xu, et. Al., Materials Science in Semiconductor Processing, Volume 195, (2025).

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology, Ieee, Wiley, (2014).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 69-77

doi: 10.4028/p-9ppZEB

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2026-01-07

Accepted:
2026-01-31

Online:
2026-05-18

Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

Jianpei Zhang 1,a, Zeyu Chen 1, b, Yuzhuo LI 1,c, Shanshan Hu 1, d, Balaji Raghothamachar 1,e, Yafei Liu 2,f, Campbell Bouch 2, g, Ryan Philpott 2, h, Scott Turchetti 2,i, Pete Schunemann 2,j and Michael Dudley 1,k,*

1 Department of Materials Science & Chemical Engineering, Stony Brook University, Stony Brook, NY 11794 USA

2 Onsemi, 55 Executive Drive, Hudson, NH 03051 USA

a  Jianpei.zhang@stonybrook.edu, b  Zeyu.cheni@stonybrook.edu, c  Yuzhou.Li@stonybrook.edu, d  Shanshan.hu@stonybrook.edu, e  Balaji.ragnothamachar@stonybrook.edu, fYafei.Liu@onsemi.com, 9  Campbell.Bouch@onsemi.com, h  Ryan.Philpott@onsemi.com, iScott.Turchetti@onsemi.com, jPete.Schunemann@onsemi.com,  kMichael.Dudley@stonybrook.edu,

Keywords: 4 H -Silicon carbide, physical vapor growth, low-angle grain boundary, synchrotron x-ray characterization.

Abstract

Synchrotron X-ray topography (XRT) combined with ray-tracing simulation was employed to examine the distribution and formation mechanisms of LAGBs in off-axis 4H−SiC wafers grown by PVT. TED-LAGB networks were observed adjacent to the facet, along with three TED-LAGBs emanating from micropipes on the left edge of the wafer. Ray-tracing simulations enabled the identification of TED Burgers vectors by correlating simulated and observed contrast configurations. The results suggest that large TED-LAGB networks near facets originate from misorientations between growth fronts of horseshoe-shaped steps incorporating prismatic slip dislocations, induced by radial temperature gradients. Similarly, LAGBs associated with micropipes arise from localized step-flow perturbations. These findings provide a revised mechanism for TEDLAGBs formation, establishing a link between their spatial distribution and growth dynamics, and offering new insights into their role in determining the quality of 4H−SiC substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

Silicon carbide ( SiC ) is a wide-bandgap semiconductor with high breakdown field and strong electrical and thermal conductivity[1]. These properties make it an important material for modern power and electronic systems, such as inverters, on-board chargers, and converters for electric vehicles[2], [3]. However, the presence of defects in PVT-grown SiC crystals negatively affect the reliability and performance of SiC devices. Among various types of defects in SiC crystals, low-angle grain boundaries (LAGBs) are a commonly observed planar defect that limit yield and prevent the implementation of large SiC devices[4]. LAGBs form through the aggregation of different types of dislocations, usually threading edge dislocations (TEDs) or edge type basal plane dislocations (BPDs) to accommodate the misorientation of lattice planes[5]. TED-LAGBs lead to tilt along prismatic planes often associated with radial temperature gradients and the coalescence of growth steps, forming network-like structures across the wafer and producing noticeable lattice tilt. BPD-LAGBs, on the other hand, result from the aggregation of basal plane dislocations (BPDs), particularly those of opposite signs driven together under stress, giving rise to tilt of the basal plane[5]. These boundaries are usually found near wafer edges or stress-concentrated regions and can sometimes combine with TED arrays to form composite grain boundary structures. They are more likely to evolve into Shockley stacking faults during device operation, severely impacting the performance
and reliability of power devices[6, 7]. Classical formation mechanisms of <11―00> orientation LAGBs are generally associated with threading screw dislocations (TSDs), which act as growth centers by generating spiral steps[8]. TED-LAGBs formed as TEDs align along the <11―00> direction to accommodate the c -axis rotation between the TSDs and surrounding regions when growth centers converge. Step flow based mechanism was proposed by Cheng et al[9] indicating that radial temperature gradients drive horseshoe-shaped step flow from the facet, where merging fronts incorporate prismatic slip dislocations to form TED-LAGBs.

In this study, an unique distribution patterns of LAGBs observed in physical vapor transport (PVT) grown off-axis 4H−SiC wafers is investigated. Synchrotron X-ray topography (XRT) in both transmission and grazing geometry reveal the presence of LAGBs networks next to the facet regions as well as associated with micropipes on the left edge of the wafer. A systematic analysis has been carried out to identify the dynamics of step flow and the associated mechanisms of LAGB formation induced by its motion.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

4H-SiC wafers grown by physical vapor transport (PVT) method with a 4∘ offcut were characterized by synchrotron x-ray topography (XRT)[10]. Both transmission and grazing-incidence geometries were employed, with topographs recorded under white-beam and monochromatic conditions, respectively. Synchrotron white beam x-ray topography (SWBXT) was recorded in a 112―0 reflection with the Si face as the beam exit surface. Synchrotron monochromatic beam x-ray topography (SMBXT) was recorded in 112―8 from the Si face of the wafer. Experiments were conducted at the Advanced Photon Source (APS) in the Argonne National Laboratory (ANL). Raytracing simulation was carried out based on the orientation contrast mechanism[11] for Burgers vector analysis of observed dislocations.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

TED-LAGB Network adjacent to the Facet. Schematic diagram shows the location of LAGB networks of the wafer indicated by the red lines (Fig. 1a). SMBXT recorded from the Si face of the wafer reveals this LAGB network consists of numerous black and white contrast TED-LAGB arrays each extending along the <11―00> directions which are marked with red lines. The optical image of the PVT-grown off-axis 4H−SiC wafer shows an unusual shape of the facet outlined with red line with three spikes along the <112―0> directions which are marked with green lines (Fig. 1c). In the facet regions, a star pattern that is also marked with green lines is observed with each line also following <112―0> directions, indicating that the spikes correspond to this star pattern (Fig. 1d). The SMBXT image recorded from the Si face of the wafer reveals a micropipe at the center of the star pattern marked with a red arrow in fig. 1e which is also crossing point of three spike. Similar pattern was reported by M. Sonoda et al[13], where the facet region showed hexagonal symmetry comprising six vicinal (0001―) C surfaces tilted toward <11―00> directions, indicating that these spikes originagte from the micropipe which act as the growth center during PVT growth.

To investigate the nature of dislocations comprising the LAGB network, ray-tracing-simulated TEDs with different Burgers vectors in the <112―8> reflection are compared with actual topographic observations. Simulation reveals distinct contrast configuration variation of TEDs with six different a-component Burgers vectors shown in Fig. 2 [12]. They appear as either dark contrast TEDs (Fig. 2a and b) or white contrast. TEDs with a distorted white center decorated by two dark arcs (Fig. 2cf). The Burgers vector of TEDs are perpendicular to the direction of each boundary.

[picture]

Fig. 1. (a) Schematic diagram shows the location of LAGB networks of the wafer indicated by red lines. (b) 112―8 SMBXT image recorded from the Si face showing the presence of a large TED-LAGB network noted with red lines. (c) Optical image of the wafer shows unusual shape of facet outlined with red line and three spikes coming from the facet indicated by green lines. (d) Optical image of the star pattern marked with green lines corresponding to these spikes.(e) Micropipe at the center of the star pattern noted with red arrow.

Fig. 1. (a) Schematic diagram shows the location of LAGB networks of the wafer indicated by red lines. (b) 11 2 ― 8 SMBXT image recorded from the Si face showing the presence of a large TED-LAGB network noted with red lines. (c) Optical image of the wafer shows unusual shape of facet outlined with red line and three spikes coming from the facet indicated by green lines. (d) Optical image of the star pattern marked with green lines corresponding to these spikes.(e) Micropipe at the center of the star pattern noted with red arrow.

[picture]

Fig. 2. Ray-tracing simulated 112―8 grazing-incidence x-ray topographs of TEDs with six different acomponent Burgers vectors [(a)-(f)] in 4H−SiC[12].

Fig. 2. Ray-tracing simulated 11 2 ― 8 grazing-incidence x-ray topographs of TEDs with six different acomponent Burgers vectors [(a)-(f)] in 4 H − S i C [ 12 ] .

[picture]

Fig. 3. Enlarged images of the TED-LAGB networks observed in 112―8SMBXT recorded from the Si face. Directions of TED arrays composing the LAGB network are highlighted by dotted lines. Contrasts of individual dislocations in each array marked with red boxes are enlarged showing that LAGBs along different <11―00> are composed of TEDs with different contrast and Burgers vectors in (a), (b), (c) and (d).

Fig. 3. Enlarged images of the TED-LAGB networks observed in 11 2 ― 8 S M B X T recorded from the Si face. Directions of TED arrays composing the LAGB network are highlighted by dotted lines. Contrasts of individual dislocations in each array marked with red boxes are enlarged showing that LAGBs along different < 1 1 ― 00 > are composed of TEDs with different contrast and Burgers vectors in (a), (b), (c) and (d).

Fig. 3 shows enlarged sections of these TED-LAGBs extending along all <11―00> directions. For the white TED boundary lying along [011―0], the enlarged image reveals that each TED with a white centered contrast has its top black contrast shifted more to the left and the bottom black contrast shifted more to the right. This configuration corresponds to the TED with Burgers vector b=1/3[211―0] (Fig. 3a). For the white TED boundary lying along [10-10], the enlarged image indicates that each white centered TED has its top black contrast shifted to the right and the bottom black contrast shifted to the left, which corresponds to a TED with Burgers vector b=1/3[12―10] (Fig. 3a). For the white TED boundary lying along [ 11―00 ], the enlarged image shows that each white centered TED has a larger top portion than bottom, top black contrast shifted to the left and the bottom black contrast shifted to the right, which corresponds to a TED with Burgers vector b=1/3[112―0] (Fig. 3b). For the black TED boundary lying along [10̄10], the enlarged image shows that each black centered TED has its top black arc shifted to the left side and bottom black arc shifts to the right side, which corresponds to a TED with Burgers vector b=1/3[1―21―0] (Fig. 3c). For the black TED boundary lying along [01 1―0], the enlarged image shows that each black centered TED has its top black arc shifted to the right side and bottom black arc shifted to the left side, which corresponds to a TED with Burgers vector b=1/3[2―110] (Fig. 3d).

Formation mechanism of TED LAGB Network adjacent to the Facet. A horseshoe-shaped growth step model to explain the TED LAGB network formation on PVT-grown 4H-SiC wafer was proposed by Cheng et al[9]: The crucible design of PVT growth has the heating induction coils encircling the growth cell, creating a radial temperature difference between the inner and outer region of the crystal, which temperature on the edge is higher than it on the center region. This causes diffusivity differences in adatoms deposited at various locations on the growth interface. Faster growth rate is expected at higher growth temperature[16]. Besides, higher growth temperatures
promote a smooth step morphology with smaller step heights, while lower temperatures increase step height and form large terraces, which introduce propagation speed variation during growth[17]. Observation of step morphology on initial grown 4H-SiC crystals reveals that steps originate from the growth facet position and propagate across the crystal radially[18]. Above all, step front near the crystal edge propagates faster than in the central region, a horseshoe-shaped growth step is formed.

The primary TED source of TED-LAGB networks is pre-existing prismatic slip dislocations in the adjacent regions [19]. Such dislocations are typically deformation-induced and arise from activation of the secondary slip system 1/3<112―0>{11―00}. The key factor enabling the activation of prismatic slip in 4H-SiC during PVT growth is thermal stress generated by the radial temperature gradients, which applies shear stress to all slip systems according to Schmid's law. Gliding of pre-existing TEDs on the secondary prismatic slip system will occur once the resolved shear stress exceeds the critical resolved shear stress (CRSS). This interpretation of having prismatic slip dislocations as the LAGB network dislocation source can be further verified by analyzing the prismatic slip dislocation distribution prediction model developed by Guo et al.[14]. in conjunction with ray-tracing simulation. Guo et al.'s study revealed screw-oriented prismatic slip dislocation segments as distinct straight linear contrast along one of the three [112―0] directions in synchrotron x-ray topographs near the periphery of 4H−SiC wafers[14]. Therefore, the horseshoe-shaped growth step incorporates prismatic slip dislocations to form LAGBs at its encountering location as the mobile TED segment glides behind the growth front and leaves a screw-oriented prismatic slip dislocation segment in its wake. Before the faces of the two growth fronts encounter each other, the original TED segment will escape the coalescing front, leaving a surface intersecting point of the screw-oriented prismatic slip dislocation segment. When the steps merge, in order to enable conservation of Burgers vector, the prismatic dislocations will be forced to redirect into TEDs exiting the top surface.

An analogous interpretation can be made for the LAGB network adjacent to the facet. Three spikes of facet emerging from the MP in the facet (Fig. 1(e)) extend along the [11̄20] directions (Fig. 4a). Due to the radial temperature gradient between the center and edge of the wafer, atoms deposited onto the terrace of the growth steps exhibit different diffusivities. Spikes closer to the edges of the boule propagate faster than the one between them, forming horseshoe shaped growth fronts on both sides. As growth continues, opposing spike fronts from each side converge first near the facet region, roughly along the horizontal direction (Fig. 4b-c). TED on the growth fronts will glide along [1 2―10 ] and [1―21―0] directions on the prismatic plane to form TED-LAGBs along [ 011―0 ] and [ 101―0 ] directions. The central spike will keep moving forward and it will encounter with other fronts on sides initially. As the central spike continues to advance, it will encounter the side fronts. To accommodate the misorientation introduced by the side front induced TED-LAGBs, the TED-LAGBs along the [1 1―00 ] direction will be formed(Fig. 4d). Each growth front undergoes this process, but due to changes in growth conditions process, the step flow pattern may slightly differ resulting in the formation of TED-LAGB networks in this region (Fig. 4e).

[picture]

Fig. 4. Schematic diagrams showing the formation mechanism of TED-LAGB networks coming from spikes based on the horse-shoe shape step flow mechanism.

Fig. 4. Schematic diagrams showing the formation mechanism of TED-LAGB networks coming from spikes based on the horse-shoe shape step flow mechanism.

TED-LAGB from Micropipes. Beyond the facet region, synchrotron XRT reveals LAGBs emanating from micropipes on the PVT-grown off-axis 4H−SiC wafer. Schematic diagram shows the location of LAGBs indicated by the blue lines(Fig. 5d). The SMBXT images (Fig.5a-c) reveals that these LAGBs noted with blue lines consisting very high density black or white contrast TED-LAGB arrays originates from contrasts associated with micropipes or micropipe arrays marked with green boxes. Optical images of MPs and MP arrays corresponding to those contrasts are observed indicated by green lines.

[picture]

Fig. 5. 112―8 Grazing-incidence synchrotron monochromatic beam x-ray topograph recorded from the Si face showing the presence of TED-LAGBs originating from micropipes marked with blue lines(a-c). The location of TED-LAGBs of the wafer indicated by the blue lines are shown on (d).

Fig. 5. 11 2 ― 8 Grazing-incidence synchrotron monochromatic beam x-ray topograph recorded from the Si face showing the presence of TED-LAGBs originating from micropipes marked with blue lines(a-c). The location of TED-LAGBs of the wafer indicated by the blue lines are shown on (d).

Formation mechanism of TED-LAGB from Micropipes. Based on these observations and horseshoe-shaped growth step model, we proposed a formation mechanism for LAGBs originating from MPs in the PVT-grown off-axis 4H-SiC boule in this study. Step flows merge together after the formation of TED-LAGBs near the facet and continue to propagate radially outward to other side of boule. When a MP is encountered, the step flow is pinned by the MP and the direction of the step flow changes to form a horseshoe-shaped growth step around the MP. When the two horse-shoe shaped growth fronts merge together, the pre-existing TEDs in this region will glide on the secondary
prismatic slip system to accommodate the misorientation between the fronts when the resolved shear stress exceeds the CRSS.When more growth steps accumulate during growth, each one undergoes this process repeatedly, but due to changes in growth conditions process, the step flow pattern may slightly differ from layer to layer resulting in the LAGB network adjacent to the MP cluster.

[picture]

Fig. 6. Schematic diagrams showing the formation mechanism of TED-LAGBs coming from micropipes based on the horse-shoe shape step flow mechanism.

Fig. 6. Schematic diagrams showing the formation mechanism of TED-LAGBs coming from micropipes based on the horse-shoe shape step flow mechanism.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

In this work, synchrotron X-ray topography and ray-tracing simulation are employed to investigate the distribution and formation mechanisms of LAGBs in PVT-grown 4H-SiC crystal. TED-LAGB networks next to the facet and three TED-LAGBs emanating from MPs are observed. Ray-tracing simulations enabled the identification of Burgers vectors of TEDs in these LAGBs from contrast configurations observed in synchrotron topographs. The results indicate that TED-LAGB networks next to the facet form to accommodate the misorientation between growth fronts of horseshoe-shaped steps, which incorporate prismatic slip dislocations originating from facet spikes under radial temperature gradients during growth. For TED-LAGBs emanating from micropipes, the MPs act as localized centers that also redirect step flows into horseshoe-shaped steps, thereby generating TEDLAGBs to accommodate the misorientation of those steps. Based on these observations, the role of step-flow dynamics and dislocation interactions in LAGB development is highlighted. These findings provide new insight into the origin of LAGBs in SiC crystals and their implications for substrate quality.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

Work was supported by Onsemi. Research used resources of the Advanced Photon Source (Beamline 1-BM), a U.S. DOE Office of Science User Facility operated for the DOE Office of Science by Argonne National Laboratory under Contract No. DE-AC02-06CH11357. This research used resources of the National Synchrotron Light Source II, a U.S. Department of Energy (DOE) Office of Science User Facility operated for the DOE Office of Science by Brookhaven National Laboratory under Contract No. DE-SC0012704. The Joint Photon Sciences Institute at SBU provided partial support for travel and subsistence at the Advanced Photon Source.

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The original version of this paper is available on https://www.scientific.net/MSF.1190.69.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 79-87

doi: 10.4028/p-k0dpCG

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-19

Accepted:
2026-02-23

Online:
2026-05-18

Polytype Transitions in Silicon Carbide: A Macroscopic View

The original version of this paper is available on https://www.scientific.net/MSF.1190.79.pdf

Jörg Pezoldt 1,a*, Vladislav Kurtash 1, b and Frank Neubert 2,c

1 FG Nanotechnologie, Institut für Mikro- und Nanoelektronik and Institut für Mikro- und Nanotechnologien MacroNano ® and Institut für Werkstofftechnik, Postfach 100565, 98684 Ilmenau, Germany

2 AMC - Analytik & Messtechnik GmbH Chemnitz, Heinrich-Lorentz-Str. 55, 09120 Chemnitz, Germany

ajoerg.pezoldt@tu-ilmenau.de, b  vladislav.kurtash@tu-ilmenau.de, c  FrankNeubert@gmx.net 

Keywords: polytype transition, polytype stability, defect formation, phase transition, thermodynamics, nonequilibriums state, device degradation, self-organization.

Abstract

Based on the analysis of the defect formation in silicon carbide polytypes in different semiconductor manufacturing processing steps, device operation and environmental-device interaction it is concluded that external material and energy fluxes are generally able to destabilize the polytype structure. The governing reason is the formation of stacking faults and instabilities of the partial dislocation associated with them. A new ansatz is proposed to describe the structural instabilities using none-equilibrium thermodynamics and entropy production. A criterial form for polyype transitions is proposed. The developed criterial form is applied to describe observed structural instabilities occurring under different external actions.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.79.pdf

Polytypism is a special one dimensional form of polymorphism and a universal property of a wide range of metals, elemental and compound semiconductors, insulators and superconductors [1-5]. Prominent polytypic crystals belong to the AnB8−n(SiC,ZnS),MX2(CdI2) and ABX3 (Perovskites) crystal structure families. One of the structural preconditions for the occurrence of this phenomenon is a relative low stacking fault energy of stacking faults formed in a glide plane (basal plane) [6-10]. Another, the location in the John-Bloch diagram at the border between two structural ground states, for AnB8−n the wurtzite (2H) and sphalerite (3C) modifications [11]. Additionally, the possibility to form different modes of stacking of two dimensional structural compatible units along a defined crystallographic direction is required [12].

Polytypic and polymorphic structural variants behave thermodynamically different. The polymorphic modifications represent well defined thermodynamic phases, with well specified stability ranges of temperature, composition and pressure. The transition from one polymorph to another is a firstorder phase transformation. On the contrary, except for very few short period polytype modifications, no such physical factors have been found to govern the formation of polytypes. This is originated by small differences of formation and total energies between different polytypes structures [13-17]. The small energetic differences of the different polytype structures as well as the low stacking fault energies are less than the energetic disturbance in semiconductor technological processing steps and below the thermal energy at room temperature. As a consequence, different polytype appear under identical conditions of temperature and pressure and display syntactic coalescence and intergrowth of polytypes [18-21]. Additionally, this cause a specific type of defect formation, i.e. polytype lamella (syntactic inclusions) associated with stacking fault formation and local or global polytype transitions, during semiconductor device processing steps, i.e. thermal treatment [22, 23], thermo-mechanical stress [24], impurity diffusion [25], ion implantation and annealing [26-28], sputtering [29], etching [30], oxidation [31], metallization [32], crystal [33] and epitaxial [18, 34, 35] growth. Furthermore, polytype transitions occur during the operation of semiconductor devices [36-39].

According to published data polytype transformations are related to partial dislocation (PD) and stacking fault (SF) formation in the initial structure, i.e. structural "disorder". It can be hypotesized that at the very early stage the transformation process is related to point defect formation and their
selective coagulation leading to dislocation and stacking fault formation. The transformation processes occurring at nonequilibrium conditions can be considered as nonequilibrium phase transitions. The local structural changes induced by the SFs are polytype inclusions, i.e. able to act as information centers for the nucleation and growth of extended regions with a different polytype structures. Collective and selective interactions between these defects result in a stability loss of the original structure. Reaching the critical state, nonequilibrium polytype phase transition occur which lead to the formation of a new polytype structure better adapted to the exterior conditions. Schematically, the nonequilibrium phase transitions can be described as: Order → point defect/dislocation generation → stacking fault generation → defined disorder → "catastrophe" → new order. In Fig. 1 a generalizing scheme of polytype phase transition in terms of thermodynamic quantities and defect interactions is given. Energy dissipation in the crystal originating from incoming fluxes of mass, energy, impulse and entropy lead to an information excess in the initial polytype structure as a precondition for structural changes.

[picture]

Fig. 1. Polytype transition as nonequilibrium phase transitions.

Fig. 1. Polytype transition as nonequilibrium phase transitions.

Theoretically, the stability of different polytype structures without point and extended defects was studied in the framework of total energy calculations using different simulation approaches [13-16, 40]. In [3,40] the role of entropy for the stabilization of the polytype structure was discussed. In case of crystal growth the nucleation theory was used to assess the stability of the formation of different polytypes in dependence on supersaturation, Si to C ratio and doping [41, 42]. Alternatively, kinetic Monte Carlo [43-46] and molecular dynamic [47-48] approaches were applied. Another class of modelling polytype formation and transitions rely on dislocation and stacking fault reactions and their transformations [1, 49-51]. All this theoretical modelling approaches address singular initial material property conditions and specific material processing steps with a limited generalization ability to describe polytype transitions occurring at other semiconductor processing steps or during device operation.

In this contribution an ansatz is proposed which might pave the way for generalized macroscopic description of the defect related polytype transitions at arbitrary physical and chemical treatments.

Nonequilibrium Thermodynamic Model

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As shown above polytype transformations are interconnected with defect formations and can be considered as a specific type of defect formation. The percolation of the defect subsystem at a critical point transforms the initial crystal structure i into a new polytype modification j independent on the
physical nature of the action in the semiconductor fabrication processing step or during device operation [50,51]. The structural origin is the evolution of existing "disorder" (information excess) or the generation of "disorder" in the initial polytype structure i.

Within the framework of nonequilibrium thermo-

[picture]

Fig. 2. Scheme of the energetic states between two different structures i and j under equilibrium and nonequilibrium conditions.

Fig. 2. Scheme of the energetic states between two different structures i and j under equilibrium and nonequilibrium conditions.

The excess entropy formed in polytype S is associated with the energy dissipation in the polytypic single crystalline matrix material i due to the action of thermodynamic forces and linked fluxes of energy, mass and impulse of the physical interaction process. Introducing an ordering time of the initial polytype matrix j Pi→j[50] necessary to annihilate or incorporate the defects into the lattice and to rearrange the lattice stacking into the structure of the polytypic matrix under the conditions of the technological process under consideration. i can be determined using the entropy production Δμexc,i of the process and Δμexc , i  :

ΔSexc , i 

with i, and with Δμ as the ordering time of the ordering process i=TΔSexc , I . In the linear approximation of nonequilibrium thermodynamics the general form of total entropy production with fluxes i and conjugated driving forces j is [52]:

i

with j as the entropy production per unit volume and i→j as the volume. Taking into account that forces ΔSexc , crit  are affecting the fluxes Δμexc ,i by ΔSexc ,i Eq. 2 takes the form:

iΔSexc ,i

From Eq. 1 and 3 it follows that i is composed by the action of all fluxes and forces interacting with the polytypic crystalline matrix i. In table 1 a summary of thermodynamic forces and fluxes are given for which degradation of the polytype structure or polytype transitions were observed.

[picture]

Fig. 3. Scheme of the excess entropy formation in the polytype matrix τord i due to disordering and ordering by a technological process.

Fig. 3. Scheme of the excess entropy formation in the polytype matrix τ ord i due to disordering and ordering by a technological process.

The generalized interaction scheme explains the interrelation between ΔSexc ,i and dS/dt is shown in Fig. 3. It demonstrates that entropy production and the excess entropy formed in the polytypic matrix τord ,i affects the ordering time

ΔSexc,i=(dS/dt)τord,i(1)

by a positive feedback loop leading to an increase of τord ,i=∑m=1nτm through an increased defect density of the matrix crystal. Consequently, entropy production as a state function of nonequilibrium thermodynamics allows to formulate a stability criterial form of the polytype matrix τm in an interaction process with an arbitrary environment. The polytype matrix is stable if the following inequality if fulfilled:

m

here Jk is the critical excess entropy causing the instability of the polytype matrix and the onset of polytype transition in form of Xk.

Table 1 Collection of fluxes and forces in their thermodynamic description able to contribute to polytype defects formation or polytype transitions

Process | Thermodynamic force, X | Thermodynamic Flux, J
Heat flow | Temperature Gradient ∇(T⁻¹) | Heat Flux q
Current flow | Electric field ET-l | Electrical Current I
Plastic Deformation | Stress σT-l | Plastic Strain εp
Diffusion | Chemical Potential ∇(μCT⁻¹) | Diffusion Flux JD
Deposition Vapour/Gas Phase | Chemical Potential ∇(μPT⁻¹) | Diffusion Flux JP
Chemical Reaction | Reaction Affinity ART-l | Reaction Rate Rc
Particle irradiation | Particle Flux Density ART-l | Target Atom Velocity vp
Polishing/Wear | Friction Force FT-l | Relative Velocity Vr

dS/dt=∫σSdV=∫(∑kJkXk)dV(2)

and σs are the chemical potential due to a specific concentration and partial pressure, respectively. The forces and fluxes for deposition from vapour or gas phases are given for the diffusion limited case without convective or turbulent contributions.

[picture]

Fig. 4. Critical excess entropy of polytype transition V in the dependence on the shortest translation period Xl of the initial polytype structure.

Fig. 4. Critical excess entropy of polytype transition V in the dependence on the shortest translation period X l of the initial polytype structure.

The critical excess entropy related with the polytype transition from polytype Jk to polytype Jk=∑lBklXl was determined using physical vapour transport experiments in a sublimation growth cell applying a special SiC vapour distributor allowing for supersaturation distributions over the crystal surface at constant substrate temperatures [18,57]. For the investigations the following polytypes were used:

dS/dt=∫(∑k∑lBklXlXk)dV(3)

. The polytpes are ordered with respect to the shortest translation period which is the period containing fundamental stacking sequence characteristic for the given polytype, for example (22) or (32) for 4 H and 15 R , respectively. The expression for critical excess entropy ΔSexc, i crit, i, for polytype transition i was derived using Eq. 1 and 3 for the conditions of physical vapour transport growth and has the form;

dS/dt,τord ,i

with ΔSexc ,i as universal gas constant, iΔSexs ,i as the number of unit cells per mole of polytype τord i as critical growth rate for transition τord i and i as the vaporization rate of polytype

ΔSexc i=dS/dtτord i<ΔSexs crit i,(4)

. The obtained results are summarized in Fig. 4. The main findings are as follows. The critical excess entropy ΔSexc crit, i for polytype transition i→j is independent on the polytype structure of the initial polytype μC and depends only on the final polytype of the polytype transition μP. The value of i→j is decreasing if the shortest translation period λi of the transformation product is increasing. Consequently, the entropy barrier for transitions into a polytype structure with higher i is lower. This means that the transformation into polytypes with larger j requires a lower "disorder" (information excess), i.e. the formation and rearrangement of a lower defect concentration compared to the transition into a polytype with higher crystal symmetry, for example 3C-SiC. This is supported by the defect permutations needed to transform different hexagonal or rhombohedral polytypes into other hexagonal or rhombohedral polytypes compared to a transformation into the 3 C or 2 H structures [1,3,58]. As a consequence polytype transitions into polytypes with larger 4H,15R,6H,21R,8H,27R,33R,39R,19R occur at lower critical growth rates as reported in [56, 59-61].

Assuming now a defective polytype matrix. Defects can be dopants, dislocations, stacking faults or inclusions. Then, these defects increase the excess entropy ΔScrexc  and chemical potential of the matrix to i→j. It follows that the vaporization rate i→j changes into the vaporization rate of the defective matrix

ΔSexc crit ,i→jcr=(R/Ni)ln(1+(vcr,i→j/voi)), (5)

;

R

Combining Eq. 6 with 4 it follows:

Ni

Therefore, defective or strained substrates exhibiting an enhanced evaporation rate have a reduced entropy barrier for polytype transitions due to decreased disorder needed for the transition. As a consequence the critical growth rate for structural changes at a given substrate temperature decreases. This was observed in [57], where a reduction of the critical growth rate for the polytype transitions i,vcr and i→j on 6 H modified by boron diffusion in dependence on the near surface boron concentration was observed. The increase of the boron concentration decreased the critical growth rate. The same effect was detected for nitrogen implanted 6 H -SiC substrates in dependence on the implantation dose and for surfaces treated by polishing [57].

Thermo-plastic deformation of silicon carbide at different temperature and deformation conditions was studied in [24, 62-67]. In this studies it was revealed that beside dislocation related mechanisms, structural transitions in form of polytypic transformations are possible in the brittle [65,67] and ductile deformation region [49, 62, 66]. The observed structural transformation series are formally similar to polytype transformation series observed in growth experiments. Generally, the shortest translation period of the transformation product is smaller than the initial one. In [67] the transition sequence voi was observed in milling experiments with increasing milling time. In [24, 64] the possibility of polytype transitions i and polytype ΔScrexc crit,i→j was found. The polytype transformation of an arbitrary polytype into 3C is the most common one observed in mechanical treatments of SiC polytypes [24, 49, 62, 63, 65, 66]. In Fig. 5 the experimental critical initial stress as a function of the shortest translation period i→j of the initial polytype is given. The critical stress values for the polytype transitions are decreasing with increasing i. This behavior resembles the dependence of the critical growth rate of the onset of the polytype growth transitions in dependence on j published in [56].

For thermo-plastic deformation the entropy production can be written as [68]:

ΔScr exc  crit ,i→j

with λj as the sheer flow stress, λj as the shear strain rate ( λj density of mobile dislocation segments, λj as average velocity of the mobile dislocations), ΔScrexc  as average dislocation energy per unit length, Δμdef  as the dislocation density. Using Eq. 8 and the defect interaction model developed in [50, 51] the critical initial shear stress was estimated. The results of the analysis are given in Fig. 5. They show a reasonable agreement with experimental data

[picture]

Fig. 5. Polytype phase transitions in dependence on the shortest translation period voi and the initial elastic sheer stress.

Fig. 5. Polytype phase transitions in dependence on the shortest translation period v o i and the initial elastic sheer stress.

Summary

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External mass, entropy and energy fluxes are generally able to destabilize the polytype structure. The governing reason is the formation of stacking faults and instabilities of partial dislocations associated
with them. A new ansatz is proposed to describe the structural instabilities using nonequilibrium thermodynamics and the entropy production. A criterial form for polytype transitions is proposed. The criterial form is applied to describe observed structural instabilities occurring under different external actions.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1190.79.pdf

V. Kurtash gratefully acknowledges funding from the Thüringer Landesgraduiertenförderung AkZ 0051050-7150000163. A part of the results was obtained in the framework of PE624/1-1 supported by the German Research Foundation.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1190, pp 89-94

doi: 10.4028/p-QUWd3K

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-10-09

Revised:
2025-12-22

Accepted:
2026-02-23

Online:
2026-05-18

Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

The original version of this paper is available on https://www.scientific.net/MSF.1190.89.pdf

Atsushi Shimbori 1,a*, Ryota Wada 2, b, Nobuhiro Tokoro 2,c, Takashi Kuroi 2, d, Hiu Yung Wong 3,e and Alex Q. Huang 1,f

1 J.J. Pickle Research Center, The University of Texas at Austin, 10100 Burnet Rd. Austin, TX 78758, USA

2 Nissin Ion Equipment Co, LTD, 75 Nishikujo Higashihieijo-cho, Minami-ku, Kyoto, Japan

3 San Jose State University, One Washington Square, San José, CA 95192, USA

a  ashimbo@utexas.edu, b  wada_ryota@nissin.co.jp, c  tokoro_nobuhiro@nissin-gr.com, d  kuroi_takashi@nissin.co.jp, ehiuyung.wong@sjsu.edu, f  aqhuang@utexas.edu

Keywords: SiC PiN Diode, Bipolar Degradation, Proton Implantation, Forward Voltage Drop, TCAD, Basal Plane Dislocation, Stacking Fault, Minority Carrier Lifetime, and Electroluminescence

Abstract

This work explores the role of implantation depth in suppressing bipolar degradation of 4H-SiC PiN diodes through proton implantation. Targeting depths aligned with active basal plane dislocations (BPDs) effectively reduces stacking-fault expansion, as confirmed by electroluminescence imaging [1,2]. From these observations, we quantified the effective range of suppression in both depth and safe operating current density. Room-temperature proton implantation ( 170keV,1×1016 cm−2 ) into the buffer reduced forward-voltage drift ΔF by 97% at 600 A/cm2. The implanted diode extended the safe operating current range to 1300 A/cm2,~200 A/cm2 higher than the reference, confirming effective suppression of bipolar degradation. Once the suppression barrier, defined as a critical excess hole density threshold, was exceeded, the proton-implanted diode exhibited explosive basal plane dislocation activity, leading to the formation of multiple bar-shaped stacking faults. These active BPDs are located deeper than the proton-implant tail, at a depth of around 11.4μ m; however, the threshold hole density required for their activation remains approximately the same (~4×1016 cm−3)[3].

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1190.89.pdf

[picture]

Fig. 1. Hole density distribution of the 4H−SiCPiN diode

Fig. 1. Hole density distribution of the 4 H − S i C P i N diode

One critical issue in the long-term reliability of 4H−SiC power MOSFETs is its body diode's VF (forward voltage drop) increase from the unique phenomenon of bipolar degradation. This is caused by the expansion of stacking faults (SFs) which originate from basal plane dislocations (BPDs) in the sublimation grown SiC substrate. Inserting a n+buffer layer with a short carrier lifetime is currently
the standard method in preventing electron-hole recombination from triggering SFs growth [4]. However, at higher current densities, the hole concentration can be substantial and reach the buffer/substrate interface where BPD-TED (threading edge dislocation) conversion points are present.

Fabrication

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An epitaxial layer, with a nitrogen doping concentration of 9×1015 cm−3 and a thickness of 10μ m, was grown by the CVD method with a high growth rate of 30μ m/hr. BPD density was further decreased by fast epitaxy and by adding a buffer layer with a thickness of 1μ m and a doping concentration of 2×1018 cm−3. Proton irradiation ( 1×1016 cm−2 at 170 keV , room temperature) was applied to the buffer layer prior to epitaxial growth to suppress stacking fault expansion with a non-implanted diode fabricated in parallel as a reference. To achieve high current density stress in the fabricated combshaped PiN diodes, surface doping at the anode was enhanced using a 30 nm Al capping layer. This approach shifted the first Al implantation peak closer to the surface, increasing the peak concentration near the metal-semiconductor interface to facilitate thin depletion tunneling (Fig. 2 (a)). As a result, a heavily doped p-type anode region with a peak concentration of 4×1020 cm−3 was formed through high-temperature Al implantation at 400∘C, followed by activation annealing at 1700∘C for 30 minutes. A low-temperature Ti-Pd based metallization stack ( Ti/Pd/Ti/Pt=2 nm/25 nm/40 nm/150 nm ), annealed at 700∘C for 1 min in Ar ambient, was employed for combshaped electrodes, achieving both precise pattern integrity and ultra-low specific contact resistance ( ρC=7.06×10−5Ω· cm2 ) required for EL emission analysis (Fig. 2(b)).

[picture]

Fig. 2. (a) Anode region SIMS profile and (b) Al vs Ti-Pd TLM contact evaluation comparison

Fig. 2. (a) Anode region SIMS profile and (b) Al vs Ti-Pd TLM contact evaluation comparison

Simulation and Numerical Analysis

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To accurately determine the threshold hole density at which bipolar degradation initiates in both reference and proton-implanted 4H−SiC PiN diodes, TCAD simulations were first calibrated against the I−V and C−V characteristics of simultaneously fabricated Ti-Pd-based circular diodes and subsequently extended to the comb-shaped electrode structure. During model validation, a slight deviation in the simulated I-V characteristics was observed, attributed to current-carrying limitations within the narrow electrode fingers of the comb-shaped layout rather than to contact resistance. EL analysis was then employed to identify the current density at which the initial onset of stacking fault (SF) expansion occurs, and to measure the maximum width W of a bar-shaped SSF. The high pulsed current required for this evaluation is limited primarily by the probe tip diameter rather than the anode contact resistance. To overcome this limitation, two probe tips were used on separate individual pads, each covering separate halves of the diode's conduction area.

[picture]

Fig. 3. TCAD simulation of hole density and H+profile at 1200−1400 A/cm2, showing delayed BPD activation beyond the implant tail edge

Fig. 3. TCAD simulation of hole density and H + profile at 1200 − 1400 A / c m 2 , showing delayed BPD activation beyond the implant tail edge

Fig. 3 shows the simulated hole density profiles superimposed against the hydrogen implant distribution under current stress levels of 1200 A/cm2 and 1400 A/cm2. In the reference diode (no proton implantation), basal plane dislocation (BPD) expansion begins when the hole density exceeds the threshold of approximately 4×1016 cm−3 near the buffer/substrate interface. In contrast, the H+implanted diode exhibits a delayed activation, with the BPD expansion point shifting deeper into the epilayer, just beyond the implantation tail edge (~11.4μ m). This delay arises because the protoninduced damage region locally reduces carrier lifetime (from 181 ns to 23.5 ns ) [5,6], creating a lower-injection zone that temporarily suppresses the minority-carrier density below the critical threshold.

Depth-Resolved Electroluminescence Analysis and Experimental Correlation with Implantation Profile

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[picture]

Fig. 4. EL images of (a) reference diode and (b) H+- implanted diode stressed at an equivalent current density of J=1200 A/cm2

Fig. 4. EL images of (a) reference diode and (b) H + - implanted diode stressed at an equivalent current density of J = 1200 A / c m 2

After the comb-shaped PiN diode had been fabricated, a bias stress of 400−μs−long8.5 V voltage pulse, equivalent to stress-current density of J=1200 A/cm2, was injected at a frequency of 3.33pulses/s for 20 min to observe the stacking fault expansion. Once the initially expanded dark region was observed, the bias stress was switched to DC to capture the time-evolution EL images at a current density of J=200 A/cm2 for an additional 20 min . For the reference diode (Fig. 4 (a)), both triangle-shaped and bar-shaped SSFs (Shockley-type stacking faults) were seen expanding along the [ [ 100 ] direction. To estimate the depth of the most active basal-plane dislocations (BPDs), the measured maximum width of a single stacking fault ( W ) was used in the geometric relation: d=W·tanθ, where d is depth of the expansion point and θ is the actual off-cut angle. From the EL image in Fig. 4(a), a maximum stacking-fault width of approximately 160μ m was observed. This corresponds to a depth of about 11.15μ m, calculated using the wafer off-cut angle of 4∘. The proton-implantation energy of 170 keV was therefore chosen so that the hydrogen peak would appear at this depth, matching the
location of the most active basal-plane dislocations near the buffer/substrate interface. As shown in the fabrication sequence below, the proton implantation step was introduced after the buffer layer growth and before the epitaxial growth, enabling a sufficiently high implantation dose and penetration depth to reach the targeted BPD-active region. The effectiveness of this approach is evident in Fig. 4(b), where the implanted diodes show no stacking-fault expansion even under the same current density conditions.

[picture]

Fig. 5. (a) SIMS hydrogen (H+)depth profile for 170keV,1×1015 cm−2 implantation showing a peak concentration at 11.15μ m within the buffer/substrate interface region. (b) Proton implantation step integrated into the 4H−SiC PiN diode fabrication sequence, illustrating the buffer layer position and subsequent process flow

Fig. 5. (a) SIMS hydrogen ( H + ) depth profile for 170 k e V , 1 × 10 15 c m − 2 implantation showing a peak concentration at 11.15 μ m within the buffer/substrate interface region. (b) Proton implantation step integrated into the 4 H − S i C PiN diode fabrication sequence, illustrating the buffer layer position and subsequent process flow

Finally, although the proton-implanted diodes initially showed no stacking-fault expansion under equivalent current densities, expansion was eventually observed at higher stress levels and longer operation times. This behavior defines the limit of the effective bipolar-degradation suppression range and highlights the need to further investigate the safe operating window of proton-implanted SiC diodes, where the devices do not exhibit bipolar degradation due to dislocation pinning [7,8] and carrier-lifetime reduction, thereby ensuring long-term reliability.

[picture]

Fig. 6. Time evolution of electroluminescence microscopy images under bias stress in the protonimplanted 4H−SiC PiN diode. Abrupt bar-shaped stacking faults (SFs) emerge at higher stress levels ( J=1400 A/cm2 ), indicating the upper limit of the bipolar-degradation suppression window

Fig. 6. Time evolution of electroluminescence microscopy images under bias stress in the protonimplanted 4 H − S i C PiN diode. Abrupt bar-shaped stacking faults (SFs) emerge at higher stress levels ( J = 1400 A / c m 2 ), indicating the upper limit of the bipolar-degradation suppression window

To correlate the simulated carrier-density threshold with the experimental onset of stacking-fault expansion, electroluminescence (EL) imaging was performed under incremental current stress. The observed width of 163μ m in the fully expanded bar-shaped SSF in Fig. 6, image (j) suggests that SF expansion initiates just below the proton implantation tail depth of 11.4μ m. This unpinning is triggered when minority carrier injection becomes sufficient to overcome the reduced-lifetime region
introduced by the implantation damage. This release occurs abruptly above ~1400 A/cm2 with barshaped SFs appearing more frequently than the reference diode, indicating an explosive activation of BPDs once the proton-induced barrier, defined by an excess hole density threshold, is overcome.

[picture]

Fig. 7. (a) I−V characteristics of reference and (b) H+-implanted diodes. Reference diode shows ΔVF drift under stress ( J=1300 A/cm2 ), while H+-implanted diode remains stable (c) Summary of VF shift in reference and H+-implanted PiN diodes under various current stress

Fig. 7. (a) I − V characteristics of reference and (b) H + -implanted diodes. Reference diode shows Δ V F drift under stress ( J = 1300 A / c m 2 ), while H + -implanted diode remains stable (c) Summary of V F shift in reference and H + -implanted PiN diodes under various current stress

As shown in Fig. 7, room-temperature proton implantation ( 1×1016 cm−2 ) into the buffer reduced forward-voltage drift ΔVF by 97% at 600 A/cm2. Proton-implanted diode demonstrated an extended safe operating current range, withstanding up to 1300 A/cm2, an increase of 200 A/cm2 compared to the non-implanted reference diode.
These observations, together with the TCAD-extracted threshold hole density of 4×1016 cm−3, support a consistent mechanism: proton-induced lifetime reduction within the buffer region pins BPDs and keeps the local minority-carrier density below the threshold near the buffer/substrate interface, thereby delaying SF activation until regions deeper than the proton-implant tail ( ~11.4μ m ) under elevated stress. As a result, the implanted diodes exhibit stable forward characteristics and no EL-visible SF expansion up to ~1300 A/cm2; beyond this level, the abrupt emergence of bar-shaped SFs indicates barrier overrun and defines the upper limit of the safe operating window.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1190.89.pdf

Proton implantation suppresses BPD-driven bipolar degradation in 4H−SiC diodes by reducing carrier lifetime and pinning dislocations within the implanted profile region, thereby shifting SF activation deeper beyond the implant tail. TCAD fitted with literature-calibrated lifetimes ( τ=181 ns for the reference, τ=23.5 ns for 1×1016 cm−2 at 170 keV implantation) indicates that, although the implanted diode exceeds the SF threshold at the buffer/substrate interface, proton-induced pinning prevents expansion, delaying activation until deeper beyond the implant tail. Implanted diodes remained stable up to 1300 A/cm2(~200 A/cm2 higher than reference), with no ΔVF drift and no bar-shaped SFs observed in EL imaging. These results confirm that lifetime engineering via proton implantation selectively into the buffer layer is an effective approach to extend the safe-operating current density of 4H−SiC PiN diodes without significantly reducing minority-carrier injection or conduction efficiency.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1190.89.pdf

The authors of this paper would like to thank Nissin Ion Equipment Co. Ltd for their support in the implantation process.

References

The original version of this paper is available on https://www.scientific.net/MSF.1190.89.pdf

M. Kato, O. Watanabe, T. Mii, H. Sakane, and S. Harada, "Suppression of stacking-fault expansion in 4H−SiC PiN diodes using proton implantation to solve bipolar degradation," Sci. Rep., vol. 12, art. no. 18790, 2022, doi: 10.1038/s41598-022-23691-y.

T. Li, H. Sakane, S. Harada, and M. Kato, "Suppression of stacking fault expansion by backside proton implantation into SiC substrates," Mater. Sci. Semicond. Process., vol. 203, art. no. 110262, 2026, doi: 10.1016/j.mssp.2025.110262.

A. Shimbori, R. Wada, N. Tokoro, T. Kuroi, H. Y. Wong, and A. Q. Huang, "Estimation of threshold hole density in single Shockley stacking fault expansion and its suppression through proton implantation in PiN diodes," 2025 Device Research Conference (DRC), Durham, NC, USA, 2025, pp. 1-2, doi: 10.1109/DRC66027.2025.11105740.

T. Kimoto et al., "Understanding and reduction of degradation phenomena in SiC power devices," 2017 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2017, pp. 2A-1.1-2A-1.7, doi: 10.1109/IRPS.2017.7936253

S. Harada, T. Mii, H. Sakane, and M. Kato, "Suppression of stacking-fault expansion in a 4HSiC epitaxial layer by proton irradiation," Sci. Rep., vol. 12, art. no. 13542, 2022, doi: 10.1038/s41598-022-17060-y.

T. Mii, H. Sakane, S. Harada, and M. Kato, "Analysis of carrier lifetime in a drift layer of 1.2kV -class 4 H -SiC devices toward complete suppression of bipolar degradation," Mater. Sci. Semicond. Process., vol. 153, art. no. 107126, 2023, doi: 10.1016/j.mssp.2022.107126.

M. Kato, S. Harada, and H. Sakane, "Effects of proton implantation for expansion of basal plane dislocations in SiC toward suppression of bipolar degradation: Review and perspective," Jpn. J. Appl. Phys., vol. 63, no. 2, art. no. 020804, Jan. 2024, doi: 10.35848/1347-4065/ad1779.

T. Li, H. Sakane, S. Harada, and M. Kato, "Suppression of stacking-fault expansion in 4H-SiC diodes by helium implantation," Appl. Phys. Express, vol. 17, no. 8, p. 086503, Aug. 2024, doi: 10.35848/1882-0786/ad6be5.

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Chapter 4: Material Characterisation and Devices Processing

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 1-6

doi: 10.4028/p-71tmVu

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-30

Revised:
2025-12-16

Accepted:
2026-03-21

Online:
2026-05-19

Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

A.A. Lebedev 1,a, K.S. Davydovskaya 1, b, V.V. Kozlovski 1,2,c, M.E. Levinstein 1,d, D.A. Malevsky 1,e, A.E. Nikolaev 1,f, A.V. Sakharov 1,g, N.S. Solonitsyn 1, h

¹A.F.Ioffe Institute Russian Academy of sciences, Polytechnic 26, 194021, St. Petersburg, Russian Federation

2 Peter the Great St. Petersburg State Polytechnical University, Polytechnic 29, St. Petersburg, 195251, Russian Federation

a shura.lebe@mail.ioffe.ru, b Davidovskaya.Klava@mail.ioffe.ru, c VKozlovski@spbstu.ru, d  melev@nimis.ioffe.rssi.ru, e  Dmalevsky@scell.ioffe.ru, f  aen@mail.ioffe.ru, 9  Val@beam.ioffe.ru, n  nikitasolonicyn@mail.ru

Keywords: GaN, SiC, radiation resistance, irradiation temperature, protons, resistance, C-V characteristics.

Abstract

In this paper, the radiation resistance of GaN and SiC is compared. The effect of the irradiation temperature on the carrier removal rate in both semiconductors during proton irradiation is considered. It was found that in GaN , as well as in SiC , the rate of carrier removal decreases with increasing irradiation temperature. The dependence of the GaN sample resistance on the radiation dose was also calculated based on a model previously proposed to describe a similar dependence for SiC. Based on the experimental data obtained, it is concluded that the processes of radiation compensation in GaN and SiC are similar.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

It is known that, like SiC , GaN is considered a promising material for manufacturing power semiconductor devices [1-3]. Compared with silicon carbide, gallium nitride has a larger forbidden gap, greater mobility, and a larger critical breakdown electric field. However, it has less structural perfection and worse thermal conductivity. From our point of view, it is also necessary to compare the radiation resistance of these two materials. While a large amount of work has already been done on this topic for SiC , many issues remain unclear for GaN . For example, the effect of irradiation temperature on the rate of carrier removal or the mechanism of radiation compensation. The purpose of this study was to partially fill the existing knowledge gap about GaN.

Samples and Research Methods

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

For the research, gallium nitride layers with a thickness of d=2 microns grown on sapphire substrates using the MOVPE method were used. The initial concentration of ( Nd−Na)0 at room temperature was 1.8×1017 cm−3. To carry out volt-farad measurements on the surface of the epitaxial layers, hightemperature Schottky diodes with a diameter of ~600 microns were formed using electron beam sputtering of Pt(50 nm)/Au(150 nm). Ohmic contacts were formed by spraying Ti/Al/Ti/Au metals (30 nm/150 nm/60 nm/150 nm) after surface treatment in argon plasma. The irradiation was carried out with protons with an energy of 15 MeV with a maximum dose of 1×1015 cm−2. The irradiation temperature is 200∘C. After each radiation dose, the volt-farad and volt-ampere characteristics were measured.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

Effect of irradiation temperature on the rate of carrier removal in GaN

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

The parameter carrier removal rate ηe is often used to assess radiation resistance.

ηe=[(Nd−Na)0−(Nd−Na)]ΔD,(1)

Where (Nd−Na)0 is the initial concentration of uncompensated donors in the semiconductor before irradiation, (Nd−Na) is the concentration of uncompensated donors after irradiation; 4D is the radiation dose. Based on the measurements of the capacitance-voltage characteristics (CVC) using formula (1), the values ( ηe ) for irradiation with protons under the specified experimental conditions were calculated. All obtained experimental data, as well as literature data for irradiation at room temperature and for SiC are presented in the table 1.

Table 1. Temperature dependence of the carrier removal rate for SiC and GaN .

T, K | 300 |  | 500 |
Material | SiC [4] | GaN [5] | SiC [4] | GaN, current work
ηc, cm⁻¹, protons | ~ 60 | 150 | 13 | ~ 70

As can be seen from the Table, the radiation resistance of GaN is some what inferior to the radiation resistance of SiC . At the same time, the nature of the temperature dependence of the carrier removal rate is similar for both semiconductors - heating to 2000C leads to a decrease in the values of ηe by about 3-4 times for SiC and 2-4 for GaN . Thus, the conducted studies have shown that in GaN , as well as in SiC, there is a significant decrease in the rate of carrier removal in the case of irradiation at elevated temperatures. This result is important for GaN as a promising material for creating hightemperature electronics devices.

Analysis of the temperature dependence of the GaN resistance on the radiation dose

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

Let us now consider the effect of the radiation dose on the resistance of the sample base. We will use the model that we previously developed for SiC analysis [6].

Table 2. Parameters and concentrations of DL arising in n-GaN after proton irradiation [7-10].

Energy level position | Fluence, cm⁻²
0 | 1.0 × 10¹² | 3.9 × 10¹² | 7.2 × 10¹² | 1.1 × 10¹³
Deep level concentration, cm⁻³
Ec – 0.13 eV | 0 | 2.9 × 10¹⁴ | 9.0 × 10¹⁴ | 1.7 × 10¹⁵ | 2.5 × 10¹⁵
Ec – 0.16 eV | 0 | 2.5 × 10¹⁴ | 1.0 × 10¹⁵ | 1.5 × 10¹⁵ | 3.0 × 10¹⁵
Ec – 0.25 eV | 1.7 × 10¹⁴ | 2.7 × 10¹⁴ | 5.4 × 10¹⁴ | 6.9 × 10¹⁴ | 1.3 × 10¹⁵
Ec – 0.6 eV | 2.8 × 10¹⁵ | 3.0 × 10¹⁵ | 3.7 × 10¹⁵ | 4.0 × 10¹⁵ | 3.6 × 10¹⁵
Ec – 0.72 eV | 6.2 × 10¹⁴ | 1.0 × 10¹⁵ | 2.3 × 10¹⁵ | 2.4 × 10¹⁵ | 3.9 × 10¹⁵
Ec – 1.25 eV | 3.9 × 10¹⁴ | 5.1 × 10¹⁴ | 5.9 × 10¹⁴ | 7.1 × 10¹⁴ | 7.7 × 10¹⁴

There are a number of studies where the parameters of the deep levels (DL) that occur when n-GaN is irradiated with protons have been determined. The results are presented in table 2.
Consider n-GaN, doped with Si, which is most often used to produce n-type conductivity in gallium nitride. Silicon donor levels have an activation energy of 15MeV[11]. We will assume that all
radiation defects formed after irradiation are acceptors. Then levels with an energy of 0.13−0.25 MeV will not affect the concentration of electrons in the base at room temperature, since all charge carriers captured by them will be ionized almost instantly into the conduction gap. The remaining GU levels can be conditionally divided into two groups, according to the ratio of the probability of capture and ionization of the carrier at this level.

Acceptor A 1 , which is an average of Ec−0.6eV and Ec−0.72eV levels. This level will capture electrons from the conduction zone, which will be partially ejected back into the zone.

Acceptor A2 with an activation energy equal to 1.25 eV . This level will only capture electrons, and there will be no reverse ionization from it at room temperature.
The schematic arrangement of these levels in the GaN forbidden gap is shown in Fig. 1. The parameters of deep acceptors A1 and A2 and the rate of their introduction are summarized in Table 3.

[picture]

Fig. 1. Diagram of the location of the main types of levels in the upper half of the GaN forbidden gap during proton irradiation.

Fig. 1. Diagram of the location of the main types of levels in the upper half of the GaN forbidden gap during proton irradiation.

Table 3. Parameters of deep levels in case of proton irradiation.

Level | Ionization energy, eV | Concentration before irradiation, cm⁻³ | Concentration after irradiation, cm⁻³ | Carrier removal rate, cm⁻¹
A1 | 0.66 | 3.42 · 10¹⁵ | 4 · 10¹⁵ | 580
A2 | 1.25 | 3.9 · 10¹⁴ | 5.1 · 10¹⁴ | 120

The total concentration of electrons in the conduction band will be considered as the sum of the contributions of levels D and A1. The calculation for each level was performed according to (2) [12]:

n=2(Nd−Na)1+gNaNc·eεd+[(1+gNaNc·eεd)2+4g(Nd−Na)eεdNc]1/2(2)

where Nc is the effective density of states in the conduction band, g=1 is the level degeneracy factor, Ed is the activation energy of the level, and εd is the reduced value of the activation energy calculated by formula (3):

εd=EdkT(3)

R=Le·n·μ·S(4)

where L is the length of the diode base, e is the electron charge, μ is the mobility of charge carriers, and S is the contact area.
As the radiation dose increases, electrons from the donor level D will move to the acceptor levels A 1 and A2. After full compensation of the donor level, the residual conductivity of the sample will be due to the electrons ionized from the A1 level. The dependence calculated by formulas (2) - (4), as well as experimental data from [13] are shown in Fig. 2.

[picture]

Fig. 2. Dependence of GaN resistance on the dose of proton irradiation at a temperature of T=300 K : experiment [13]: 1-Irradiation 0.6 MeV H; 2-Irradiation of 3 MeV 7Li; Calculated dependences 3 - without taking into account changes in mobility; 4 - taking into account changes in mobility.

Fig. 2. Dependence of GaN resistance on the dose of proton irradiation at a temperature of T = 300 K : experiment [13]: 1-Irradiation 0.6 MeV H; 2-Irradiation of 3 MeV 7Li; Calculated dependences 3 - without taking into account changes in mobility; 4 - taking into account changes in mobility.

When irradiated with protons with an energy of 0.6 MeV , the dependence practically coincides with the experiment, however, there are inconsistencies at intermediate radiation doses of ~1014 cm−2. The values of GaN resistance at low and high doses of proton irradiation practically coincide with the experiment.

A parameter that can affect the angle of inclination of the resistance curve depending on the radiation dose may be the mobility of charge carriers, which decreases with increasing radiation dose due to the introduction of defects in the crystal structure. There are no direct experimental data on this dependence, but in [14] the authors investigated the change in the mobility of gallium nitride charge carriers after irradiation during isochronous annealing. As the annealing temperature increased, the mobility of the irradiated gallium nitride sample increased, therefore, the mobility of charge carriers decreases during irradiation. Using the values of the mobility of the n -GaN sample carriers after irradiation, as well as after isochronous annealing, the curve of the resistance dependence on the dose of proton irradiation was calculated, taking into account the change in mobility.

The calculation results are also shown in Fig. 2.

Taking into account the change in carrier mobility, the coincidence with the course of experimental dependence becomes more satisfactory and has only small deviations at intermediate doses.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

The conducted studies have shown the similarity of radiation compensation processes in SiC and GaN. In both materials, a decrease in the rate of carrier removal is observed with an increase in the irradiation temperature. It was shown in SiC that this is due to an increase in the mobility of primary radiation defects with increasing temperature and an increase in the probability of their recombination. It can be assumed that a similar process takes place in GaN.

It was also shown that the dependence of GaN resistance on radiation dose is well described by the model developed for SiC. This model assumed that radiation compensation is caused by the transition of electrons to deep acceptor levels. Thus, it is obvious that such a compensation mechanism is also implemented for GaN.

Conflict of Interest

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

The authors declare that they have no conflict of interest.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.1.pdf

X. Liu, P. Zou, H. Wang, Yu. Lin, J. Wu, Z. Chen, X. Wang, Sh. Huang. Vertical GaN Schottky barrier diode with record high figure of merit ( 1.1GW/cm2 ) fully grown by hydride vapor phase epitaxy," IEEE Trans. Electron Dev. 70, (2023) 3748.

M. Matys, K. Kitagawa, T. Narita, T. Uesugi, J. Suda, T. Kachi. Mg-implanted vertical GaN junction barrier Schottky rectifiers with low on resistance, low turn-on voltage, and nearly ideal nondestructive breakdown voltage, Appl. Phys. Lett., 121, 203507 (2022).

D. Khachariya, Sh. Stein, W. Mecouch, M. Hayden Breckenridge, Sh. Rathkanthiwar, S. Mita, B. Moody1, P. Reddy, J. Tweedie, R. Kirste, K. Sierakowski, G. Kamler, M. Bockowski, E. Kohn, S. Pavlidis, R. Collazo, Z. Sitar. Appl. Phys. Express, Vertical GaN junction barrier Schottky diodes with near-ideal performance using Mg implantation activated by ultra-highpressure annealing, 15 (2022) 101004.

S.Y .Davydov, K.S. Davydovskaya, V.V. Kozlovski, A.A .Lebedev. Effect of proton and electron irradiation on the parameters of gallium nitride Schottky diodes, Semiconductors, 58, (1), 45-47, (2024).

V.V. Kozlovski, A.E. Vasil'ev, A.A. Lebedev, E.E. Zhurkin, M.E. Levinshtein, A.M. Strelchuk, D.A. Malevsky, A.V. Sakharov, and A. E. Nikolaev, Journal of Surface Investigation: X-ray, Synchrotron and Neutron Techniques, 18(6) (2024) 1577-1581.

A.A. Lebedev, V.V. Kozlovski, K.S. Davydovskaya, R.A. Kuzmin, M.E. Levinshtein, A.M. Strel'chuk, Features of the Carrier Concentration Determination during Irradiation of WideGap Semiconductors: The Case Study of Silicon Carbide, Materials 15 (2022) 8637.

S.A. Goodman et al. Electrical characterization of defects introduced in n-GaN during high energy proton and He-ion irradiation //MRS Online Proceedings Library (OPL). 537 (1998) G6. 12.

M. Hayes et al. Electrical defects introduced during high-temperature irradiation of GaN and AlGaN, Physica B: Condensed Matter, 340 (2003) 421-425.

Z. Zhang et al. Impact of proton irradiation on deep level states in n-GaN, Applied Physics Letters, 103 (2013) 042102.

Z. Zhang et al. Proton irradiation effects on deep level states in Mg-doped p-type GaN grown by ammonia-based molecular beam epitaxy, Applied Physics Letters, 106 (2015) 22104022104.5.

W Götz. et al. Activation energies of Si donors in GaN, Applied Physics Letters. V. 68, №. 22 (1996). 3144-3146.

K.V. Shalimova, Semiconductor Physics; Energoatom: Moscow, Russia, 1985.

A.I. Titov, P.A. Karaseov, S.O. Kucheev, Model for electrical isolation of GaN and ZnO by light-ion bombardment, Semiconductors, 38 (2004) 1215-1222.

S. O. Kucheyev et al. Effect of irradiation temperature and ion flux on electrical isolation of GaN. Journal of applied physics. 91 (2002) 4117-4120.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 7-14

doi: 10.4028/p-gydQM7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2026-01-26

Accepted:
2026-02-23

Online:
2026-05-19

Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Lin Dong 1,a*, Qiqi Wu 2, b and Stefan Nufer 1,c

1 Robert Bosch GmbH, Tübinger Straße 123, 72762 Reutlingen, Germany

2 Robert Bosch GmbH, 333 Fuquan (N.) Road, Shanghai 200335 P.R. China

a Lin.Dong2@de.bosch.com, b  Qiqi.WU@cn.bosch.com, c  Stefan.Nufer@de.bosch.com

Keywords: wafer warpage analysis, mechanical stress, photoelastic measurements, 200 mm SiC wafer technology.

Abstract

Controlling wafer warpage is critical for SiC power device fabrication on 200 mm substrates. Residual mechanical stress in bare SiC wafers is a major contributor to bow and warp. In this study, photoelastic measurements were employed to reveal distinct stress levels among wafers from different vendors, which reflect differences in crystal growth and wafering processes. By decomposing the stress into radial and tangential components, two dominant stress distribution modes-symmetric and asymmetric-were identified. The results demonstrate a clear correlation between residual mechanical stress and wafer warpage in 200 mm SiC substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Bosch is continuously expanding its semiconductor business in silicon carbide ( SiC ) chips by significantly expanding manufacturing facilities and scaling up 200 mm wafer production lines [1]. This growth is accompanied by the establishment of a diversified supplier portfolio, following a multi-sourcing and multi-location strategy. From a technical perspective, in addition to a deep understanding of substrate quality and supplier maturity, front-loaded requirements engineering is essential for ensuring the scalability of production.

In recent years, Bosch has focused on improving crystal defect characteristics; however, the large diameter wafer warpage control during the device manufacturing is now gaining increased attention. The overall shape of a substrate is typically defined by its bow and warp. As the wafer diameter increases from 150 mm to 200 mm , the influence of gravity on bow and warp values becomes more pronounced. According to SEMI standards for silicon wafers, which typically include diameters of 200 mm and 300 mm , the effects of gravity on bow and warp values can be estimated through experimental or mathematical methods [2-3]. However, for SiC wafers, particularly with the industry's initial adoption of 200 mm wafers, these topics have not been extensively explored.

The warpage of a wafer results from the overall mechanical stress state within the material, which can be induced during various manufacturing steps. Notably, the residual mechanical stress in the wafer due to SiC crystalline growth and wafering process can be a primary contributor to excessive bow and warp during device fabrication. Therefore, it is highly important to investigate residual mechanical stress in 200 mm SiC bare substrates and its impact on wafer warpage. We aim at establishing a monitoring method suitable for series production to control stress in incoming SiC wafers. Photoelastic measurement is a suitable method for assessing the stress levels in crystalline materials such as SiC and silicon wafers [4]. This paper focuses on Bosch's in-depth investigation of residual mechanical stress in SiC substrates and the stress-warpage correlation.

Experimental

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

We have investigated the warpage behavior and mechanical stress of multiple 200 mm n-type (0001) 4∘ off-cut 4H−SiC bare wafers produced from different vendors. The typical wafer thickness is 350±25μ m. To ensure that the surface stress due to the sub-surface damage does not influence the measurements, the Si-face of all samples underwent chemical-mechanical polishing (CMP), and
the C-face was treated either by CMP or fine lapping. The wafer bow and warp measurements were conducted using E+H and FRT metrology tools, which employ 2-rod and 3-point supports, respectively.

Photoelastic stress analysis was performed using the Raphael Optech SV200 and ilis StrainScope Stepper 200, both of which enable non-destructive visualization of internal stress distributions [5-6]. Figure 1(a) shows the schematic diagram of the optical path. Light emitted from the source S0 ( 630 nm for Raphael, 590 nm for ilis) first passes through a linear polarizer with a vibration direction along the y -axis. It then enters a quarter-wave plate Q(π/4,δ), whose fast axis is oriented at 45∘ to the polarizer, introducing a phase retardation δ to generate circularly polarized light. This light subsequently passes through the sample M(θ,ϕ), where θ denotes the optical axis orientation and ϕ represents the phase retardation induced by internal stress. Finally, the transmitted light reaches the polarization-sensitive camera Pi(β), which analyzes the polarization state at angle β(=0∘,45∘,90∘ and 135∘ ) and records the intensity distribution. As described in Fig. 1(b), prior to photoelastic stress measurements, the sample holder was adjusted to ensure that the light beam propagated along the wafer's c -axis direction by considering 4 H -SiC refractive index ( n=2.63 ) and off-cut angle to eliminate the natural birefringence phenomenon of 4H−SiC crystal. During the measurement, the whole sample area was scanned along a pre-determined path. The optical phase difference between ordinary and extraordinary light, along with the optical axis orientation ( θ ) was recorded. The stress was then calculated based on the stress-optic law below:

n1−n2=C(σ1−σ2).(1)

where n1 and n2 are the refractive index of fast and slow birefringence axis, respectively, and C is the photoelastic constant, which is −2.82×10−12 Pa−1 in this study [7]. σ1 and σ2 represent the principal stresses along the fast and slow axes. The fast axis corresponds to the direction of lower refractive index, while the slow axis corresponds to higher refractive index - thus n1<n2. Given C<0, this implies σ1>σ2.

[picture]

Fig. 1. (a) Schematic diagram of the instrument's optical path; (b) Schematic drawing of light beam alignment with the [0001] crystallographic orientation of 4H−SiC.

Fig. 1. (a) Schematic diagram of the instrument's optical path; (b) Schematic drawing of light beam alignment with the [0001] crystallographic orientation of 4 H − S i C .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Photoelastic Stress Analysis. We first compared wafer stress results obtained from the Raphael Optech SV200 and the ilis StrainScope Stepper 200. Table 1 presents the measured stress values for the same group of SiC samples using both instruments. The observed deviation between the two tools correlates with ingot and most likely due to different beam alignment at the two measurements. Therefore, the results are highly comparable, indicating good consistency between the two measurement systems. Additionally, we also compared the photoelastic stress distributions obtained from the two instruments and confirmed that all key stress features were consistently reproduced in both maps.

To assess the stress characteristics of incoming substrates from various vendors, Figure 2 presents photoelastic stress distributions across 200 mm4H−SiC wafers supplied by six different vendors. Although the investigation included a baseline of at least three wafers from three different ingots for
each supplier, with the sampling for two of the six suppliers being significantly more extensive, it was noted that wafers from a single source could still exhibit variations in stress patterns due to different growth runs or processing batches. Therefore, the wafers depicted in Fig. 2 are representative examples chosen to illustrate the most characteristic stress profile for each vendor. The stress levels vary significantly among vendors, both in terms of average stress values and spatial distribution. This variation reflects the influence of different crystal growth conditions, wafering techniques, and postprocessing treatments employed by each supplier. Some wafers exhibit relatively uniform stress distributions, while others show pronounced asymmetries or localized stress concentrations. To better understand these patterns, the stress maps were further analyzed and grouped based on their symmetry characteristics. Despite the differences in stress patterns, the wafers can be broadly classified into two distinct groups. Figure 3 shows two typical stress distributions of 200 mm SiC wafers. In first column of average stress mapping, the top wafer exhibits an axisymmetric stress profile with the central region predominantly dark blue (stress near 0 MPa ) transitioning to yellow and red at the wafer periphery (reaching approximately 20 MPa ), indicative of a uniform thermal gradient and controlled cooling process. The white arrows in the average stress maps, representing the direction of the fast birefringence axis and principal stress, are constantly aligned along radial or tangential orientations, suggesting a highly symmetric stress field probably resulting from optimized crystal growth parameters, such as a low thermal gradient. In contrast, the bottom wafer displays an asymmetric stress distribution, with significant stress concentrations across both central and edge regions, and white arrows indicating a non-axisymmetric stress field. This asymmetry, potentially arising from non-uniform temperature gradients during growth or cooling, may elevate the risk of defects such as basal plane dislocation (BPD) or even cracking.

Table 1. Comparison of wafer stress results from Raphael Optech SV200 and ilis StrainScope Stepper 200, showing near-identical measurements.

Sample | Average Stress (MPa) | Comparison Stress Ratio (ilis/Raphael)
Raphael Optech SV200 | ilis StrainScope Stepper 200
Ingot A / Wafer #08 | 2.90 | 2.91 | 1.00
Ingot A / Wafer #06 | 2.66 | 2.68 | 1.01
Ingot A / Wafer #03 | 2.46 | 2.50 | 1.01
Ingot B / Wafer #31 | 3.52 | 3.70 | 1.05
Ingot B / Wafer #29 | 3.38 | 3.54 | 1.05
Ingot C / Wafer #13 | 1.67 | 1.80 | 1.07

[picture]

Fig. 2. Photoelastic stress distributions of representative 200 mm4H−SiC wafers from six vendors (one wafer per vendor). Color scale indicates stress levels from 0 MPa (blue) to 10 MPa (red). Average values for each map are also indicated.

Fig. 2. Photoelastic stress distributions of representative 200 m m 4 H − S i C wafers from six vendors (one wafer per vendor). Color scale indicates stress levels from 0 MPa (blue) to 10 MPa (red). Average values for each map are also indicated.

In order to further understand the nature of the stress pattern variation, the stress is decomposed into radial and tangential components based on the optical axis orientation (shown in the white arrows in Fig. 3). It is well known that light propagating along the c -axis of a stress-free 4H−SiC crystal exhibits no birefringence, as the ordinary and extraordinary refractive indices are equal, resulting in isotropic optical behavior due to the crystal's axial symmetry [8]. However, when mechanical stress is applied to 4H−SiC, the crystal lattice becomes distorted, breaking its axial symmetry and inducing birefringence, as the refractive indices for ordinary and extraordinary rays diverge, leading to polarization-dependent optical behavior.

The stress components along the radial ( σr ) and tangential ( σt ) directions of the wafer are derived from the principal stresses (σ1,σ2) along the birefringence axes, using the angle θ between the fast birefringence axis and the radial direction, given by the following equations [9]:

σr=σ1cos2θ+σ2sin2θσt=σ1sin2θ+σ2cos2θτrt=(σ2−σ1)sinθcosθ

(2a)(2b)(2c)

Since photoelastic measurements can only determine the absolute difference between σ1 and σ2, we assume σ2≈0 to simplify the calculation. Since σ1>σ2 and σ2≈0, σ1 represents a tensile stress. Furthermore, as the measured θ values in our samples are close to 0∘ or 90∘, the equations can be approximated as:

σr≈σ1cosθσt≈σ1sinθτrt≈0

(3a)(3b)(3c)

The tangential tensile stress maps in Fig. 3 for both symmetric and asymmetric wafers exhibit a pronounced ring-like distribution at the wafer periphery (red, up to 20 MPa ), tapering to the center (dark blue, near 0 MPa ), suggesting that the tangential stress is not the primary factor for the asymmetry. It is speculated that during the cooling phase of crystal growth, a uniform peripheral contraction occurs that generates the tangential tensile stress to balance central expansion.

However, the radial tensile stress maps highlight the key difference: the symmetric pattern (top right figure) shows negligible radial stress throughout (near 0 MPa , average 0.416 MPa ). In contrast, the asymmetric pattern (bottom right figure) exhibits significant radial tensile stress in the central region (average 1.513 MPa ), reflecting anisotropic lattice bending or cooling irregularities that disrupt radial equilibrium and introduce non-uniform stress distribution. These contrasts underscore that the symmetric profile arises from optimized crystal growth with uniform thermal fields, while asymmetric profile, potentially stemming from uneven growth or cooling process or imperfect seed quality, manifests primarily through radial stress variations, elevating risks of multiplication of BPDs or cracking.

[picture]

Fig. 3. Comparison of stress mapping in 200 mm SiC wafers with symmetric (top row) and asymmetric (bottom row) stress patterns. From left to right: average stress, tangential tensile stress, and radial tensile stress. The arrows in the average stress maps represent the direction of the fast birefringence axis, which also corresponds to one of the principal stress directions. Average values for each map are also indicated.

Fig. 3. Comparison of stress mapping in 200 mm SiC wafers with symmetric (top row) and asymmetric (bottom row) stress patterns. From left to right: average stress, tangential tensile stress, and radial tensile stress. The arrows in the average stress maps represent the direction of the fast birefringence axis, which also corresponds to one of the principal stress directions. Average values for each map are also indicated.

Incoming Wafer Warpage Inspection and Stress Correlation. Figure 4 illustrates a comparison of bow and warp measurements for identical 200 mm SiC wafers using E+H metrology with 2-rod support and FRT metrology with 3-point support. The FRT results consistently show significantly higher bow and warp values, primarily due to increased gravitational deformation under the 3-point support configuration. This setup subjects the wafer to greater gravitational loading, resulting in more pronounced bending. Notably, all bow values recorded by FRT are negative, indicating a consistent downward curvature and underscoring the sensitivity of wafer geometry to support mechanics and measurement conditions. In contrast, the E+H metrology system provides more stable support, with its 2-rod configuration positioned closer to the wafer center, effectively lowering gravitational effects. As a result, bow values remain near zero and warp values are lower compared to those measured by FRT.

Finally, to establish a reliable monitoring method for incoming 200 mm4H−SiC wafers, we investigated the correlation between residual mechanical stress and various warpage parameters measured by either FRT metrology tool or E+H metrology tool. Interestingly, we found that only the warpage parameters significantly influenced by gravitational deformation, i.e., those measured using the FRT tool, showed a meaningful correlation with wafer stress. In contrast, bow and warp values obtained using the E+H tool with fewer gravitational effects, exhibited insufficient variation across wafers with different stress levels, making it difficult to establish a clear correlation.

The influence of gravity on wafer warpage measurements has been extensively discussed in the silicon industry [2-3, 10]. As an external force, gravity induces additional bending in the wafer, analogous to the mechanical deformation caused by process-induced stress during device fabrication. The effect of gravity also depends on the wafer's intrinsic curvature: it enhances bending in concave wafers and reduces it in convex wafers. To characterize this gravity-induced deformation, we reference the "z_gravity" concept described in SEMI standard MF1390-0218 for silicon wafers, introducing the term "sag value" in this paper [2].

The sag value is defined as the average of bow measurements taken with the wafer oriented both Si-face up and C-face up, using the FRT tool with 3-point support. Mathematically, it is expressed as:

 Sag = bow Si-up + bow C−up2,(4)

where bowsi-up and bowc-up refer to the three-point bow values taken with the Si -face and C -face facing upward, respectively. This method captures the full extent of gravitational influence on wafer warpage. Unlike single-side bow measurements (typically Si -face up), the sag value provides a more comprehensive representation of the wafer's bending behavior, accounting for both orientations. This dual-side approach enables more effective screening of wafers with different shapes and stress profiles.

[picture]

Fig. 4. Comparison of (a) bow and (b) warp measurements for identical 200 mm4H−SiC wafers using the FRT metrology tool with a 3-point holder and the E+H metrology tool with a 2-rod holder; (c) schematic illustration of the 3-point and 2-rod holder configurations.

Fig. 4. Comparison of (a) bow and (b) warp measurements for identical 200 m m 4 H − S i C wafers using the FRT metrology tool with a 3-point holder and the E+H metrology tool with a 2-rod holder; (c) schematic illustration of the 3-point and 2-rod holder configurations.

Figure 5(a)-(c) illustrates the correlation between absolute sag value and stress in 200 mm4H−SiC wafers. The dataset is divided into two groups based on the typical stress patterns identified in Fig. 3. Blue circles represent wafers with symmetric, ring-like stress patterns, while orange squares correspond to wafers exhibiting asymmetric stress distributions.

In Fig. 5(a), two distinct correlation trends are observed: for a given sag value, wafers with asymmetric stress patterns tend to exhibit higher average stress than those with symmetric patterns. As discussed previously, the stress components can be decomposed into radial and tangential tensile stresses. In wafers with symmetric stress patterns, the stress is primarily tangential and concentrated near the wafer periphery. In contrast, wafers with asymmetric stress patterns show significant radial tensile stress concentrated near the wafer center, which contributes comparably to the overall stress. This distinction explains why, in Fig. 5(b), a unified trend between sag value and tangential tensile stress is observed, regardless of stress pattern type. Conversely, Fig. 5(c) shows no significant correlation between sag value and radial tensile stress for either group, suggesting that radial stress has a limited influence on sag. While the underlying mechanism remains under investigation, we hypothesize that the spatial distribution of stress components-particularly a peripheral tangential field-governs gravity-induced bending by constraining basal-plane curvature. Accordingly, our future work will (i) develop a mechanics-based model that couples the measured stress components to the observed sag, and (ii) directly correlate the Fig. 5(b) metric (tangential tensile stress) with BPD distributions via molten KOH etching and/or X-ray topography on the same 200 mm wafers, to
establish quantitative stress-dislocation-warpage relationships. This is consistent with prior observations connecting residual stress, BPD distributions, and basal-plane bending in SiC growth [11].

[picture]

Fig. 5. Correlation between absolute sag value and stress in 200 mm SiC wafers. (a) Average stress vs. sag value; (b) Tangential tensile stress vs. sag value; (c) Radial tensile stress vs. sag value. Blue circles represent wafers with symmetric ring-like stress patterns, while orange squares indicate asymmetric stress patterns.

Fig. 5. Correlation between absolute sag value and stress in 200 mm SiC wafers. (a) Average stress vs. sag value; (b) Tangential tensile stress vs. sag value; (c) Radial tensile stress vs. sag value. Blue circles represent wafers with symmetric ring-like stress patterns, while orange squares indicate asymmetric stress patterns.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

In this study, we investigated the mechanical stress and warpage behavior of 200 mm bare 4H−SiC wafers. Photoelastic measurements were employed to quantify residual stress, revealing significant variation among wafers from different vendors-an indication of differing levels of process maturity in crystal growth and wafering. The stress distributions were classified into two dominant types: symmetric and asymmetric. By decomposing the stress into tangential and radial components based on the optical axis orientation, we attributed these patterns to distinct stress mechanisms. In the analysis of wafer warpage, we demonstrated that the metrology setup-particularly the support method-plays a critical role in the measured bow and warp values due to gravitational deformation. To better capture this effect and correlate it with residual stress, we introduced the sag value as a representative metric for gravity-induced wafer bending. Our results show a clear correlation between sag value and average stress, with distinct trends for symmetric and asymmetric stress patterns. Interestingly, tangential tensile stress exhibited a unified correlation with sag value, independent of stress pattern type, while radial tensile stress showed no significant correlation. These findings suggest that warpage measurements influenced by gravity, such as those captured by the sag value, can serve as an effective and non-destructive method for monitoring the mechanical properties of incoming SiC wafers.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

We gratefully acknowledge Dr. Christian Kranert and M. Sc. Paul Wimmer from Fraunhofer IISB Germany for the insightful discussions that inspired this work. The results are part of IPCEI ME/CT project which is supported by the Federal Ministry for Economic Affairs and Energy on the basis of a decision by the German Parliament, by the Ministry for Economic Affairs, Labor and Tourism of Baden-Württemberg based on a decision of the State Parliament of Baden-Württemberg, the Free State of Saxony on the basis of the budget adopted by the Saxon State Parliament, the Bavarian State Ministry for Economic Affairs, Regional Development and Energy and financed by the European Union - NextGenerationEU.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.7.pdf

Information on https://www.bosch-semiconductors.com/stories/silicon-carbide-chip-production-preparing-for-the-future/.

SEMI MF1390-0218, Semiconductor Equipment and Materials International (2023).

SEMI 3D12-1020, Semiconductor Equipment and Materials International (2015).

E. Gamarts, P. Dobromyslov, V. Krylov, S. Prisenko, E. Jakushenko, V. I. Safarov, Characterization of stress in semiconductor wafers using birefringence measurements, J. Phys. III 3 (1993) 1033.

Information on .

Information on .

M. Herms, G. Irmer, S. Spira, M. Wagner, The photoelastic constant of (0001) 4H silicon carbide determined by scanning infrared polariscopy, Phys. Status Solidi A 218 (2021) 2100198.

M. Fukuzawa, K. Kanamoto, Photoelastic characterization of residual strain distribution in commercial off-axis SiC substrates, J. Electron. Mater. 49 (2020) 5161-5166.

J.M. Gere, B.J. Goodno, Mechanics of materials, 7th ed., Cengage Learning, 2009, pp.538-566.

H. Liu, X. Zhu, R. Kang, Z. Dong, X. Chen, Three-point-support method based on position determination of supports and wafers to eliminate gravity-induced deflection of wafers, Precision Eng. 46 (2016) 339-348.

T. Ailihumaer, H. Peng, B. Raghothamachar, M. Dudley, G. Chung, I. Manning, E. Sanchez, Relationship between basal plane dislocation distribution and local basal plane bending in PVTgrown 4H-SiC crystals, J. Electron. Mater. 49 (2020) 3455-3464.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 15-20

doi: 10.4028/p-CYfCa5

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-19

Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

László Makai 1,a*, Julien Körfer 2, b, Zsombor Pap 1,c, Bálint Fodor 1, d, Mathias Rommel 2,e

1 Semilab Co. Ltd., Prielle K. u. 2, 1117 Budapest, Hungary

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystr. 10, 91058 Erlangen, Germany

a  aszlo.makai@semilab.hu, b  julien.koerfer@iisb.fraunhofer.de, c  zsombor.pap@semilab.hu, d  balint.fodor@semilab.hu, e  mathias.rommel@iisb.fraunhofer.de

Keywords: spectroscopic ellipsometry, thin oxide layer measurements, backside reflection, brewster's angle.

Abstract

The measurement of thin silicon dioxide ( SiO2 ) layers on silicon carbide ( SiC ) substrates is crucial because these layers serve a variety of critical functions in electronic and optoelectronic devices. Silicon carbide's superior electrical and thermal properties make it a preferred material for high-power, high-frequency, and high-temperature applications. When deposited on SiC , thin SiO2 films act as preconditioning layers, and as gate oxides, precise measurement of these oxide layers is important to ensure both optimal functionality and extended device longevity. This paper presents the essential considerations that should be addressed when Silicon-Oxide layers on SiC substrate are measured by spectroscopic ellipsometry to avoid backside artifact and enhance sensitivity in their thickness measurements. The methodology demonstrated enables reliable detection of layer thicknesses down to less than 1 nm , with a discrimination of less than ±0.5 nm. During ellipsometry data evaluation, parametric models are applied to describe the anisotropic backside reflections. Incorporating additional parameters, such as the substrate thickness, can yield deeper insights into the sample. However, this added complexity can render the modeling approach impractical for routine industrial applications, even though it remains scientifically valuable. Overall, this study emphasizes the combined importance of using a microspot system and optimizing the incidence angle to overcome the inherent challenges of measuring thin SiO2 films on 4H−SiC.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

The accurate characterization of ultrathin silicon dioxide ( SiO2 ) layers on silicon carbide ( SiC ) substrates is essential due to their pivotal role in the performance and reliability of electronic and optoelectronic devices. Owing to its outstanding electrical and thermal characteristics, SiC is widely used in high-power, high-frequency, and high-temperature applications [1]. When thin SiO2 films are formed on SiC , they function as gate dielectrics or surface conditioning layers, making precise thickness measurement a key factor in ensuring device efficiency and long-term stability.
Previous studies [2] have shown that spectroscopic reflectometry often lacks the necessary sensitivity to accurately measure SiO2 layers thinner than 50 nm , and especially those below 10 nm . In addition, monitoring the efficiency of SiO2 hard mask etching is key to checking if the oxide has been totally removed or if there is any (very) thin oxide left because this could hinder a subsequent process step. In contrast, spectroscopic ellipsometry (SE) is a highly sensitive, absolute measurement technique that analyzes changes in the polarization state of light upon reflection from a sample surface. In this study, SE measurements were carried out using the Semilab SE-2000 system [3], and data analysis was performed with the Semilab SEA software.
This study presents the practical consideration to successfully apply Spectroscopic Ellipsometry sensitivity on the measurement of the ultrathin SiO2 layers on 4H−SiC substrates.

Measurement Principles and Sensitivity Optimization

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

The results of spectroscopic ellipsometry are typically presented as a pair of spectra: Ψ, which represents the amplitude ratio of the Fresnel reflection coefficients for p - and s-polarized light, and Δ, which denotes the phase difference between these two polarization components.
The Brewster's angle of a bulk material sample is defined as the angle of incidence at which the reflected and refracted light beams are perpendicular to each other. This angle depends on the refractive index of the material and plays a critical role in optical measurements.
When the angle of incidence (AOI) approaches the Brewster's angle of the 4H−SiC substrate, spectroscopic ellipsometry (SE) achieves high sensitivity. At this angle, the p-polarized component of the reflected light is significantly reduced, and ideally, a sharp 180∘ phase shift ( Δ ) occurs when the layer thickness is 0 nm . As the layer thickness increases, the slope of the phase change ( Δ ) gradually flattens (see Fig. 1), enabling precise detection of ultrathin layers. Therefore, selecting an incidence angle close to the Brewster's angle is essential for accurate thin-film thickness measurements.

[picture]

Fig. 1. D sensitivity for SiO2 layer thickness around Brewster's angle: a. for SiC at 70∘AOI, b. for Si at 75∘AOI.

Fig. 1. D sensitivity for S i O 2 layer thickness around Brewster's angle: a. for SiC at 70 ∘ A O I , b. for Si at 75 ∘ A O I .

Measuring thin SiO2 films on SiC surfaces becomes more complex due to the anisotropic properties of the substrate [4]. These properties can introduce backside reflections that appear as interference fringes in the spectroscopic data. As an example, a measurement on a 2.9 nmSiO2 layer on a 4H−SiC substrate measured at 75∘ angle of incidence is presented. In this case the angle of incidence is not ideal for the measurement as it is further away from the Brewster's angle of 4H−SiC, which is 70∘ for the refractive index 2.747.

Backside Reflection and Anisotropy Correction

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

In practice, the spectral interference pattern depends on the difference between the ordinary and extraordinary refractive indices and the thickness of the substrate. As shown in Fig. 2 there are spectral ranges where the interference pattern vanishes due to the peaks in the extinction coefficient (k) spectra which is responsible for light absorption.

The modeling of the ellipsometry spectra affected by anisotropic backside reflection requires the backside reflection correction feature of the SEA software. The optical dispersion for the anisotropic substrate is obtained from the literature [4]. The modeled ellipsometric spectra of anisotropic samples were calculated using the 4×4 Berreman matrix method [5, 6]. Accurate modeling of ellipsometric spectra in the presence of anisotropic backside reflections requires careful consideration of the optical
behavior of the substrate. To account for the complex behavior of light within the substrate, including multiple internal reflections and wave interference, advanced modeling techniques are employed. These approaches ensure that both coherent and incoherent contributions to the reflected signal are properly represented, enabling a more precise interpretation of the measured spectra.

[picture]

Fig. 2. Y spectrum of a 2.9 nmSiO2 on SiC structure with model fit. The inset shows the ordinary and extraordinary refractive index of 4H−SiC.

Fig. 2. Y spectrum of a 2.9 n m S i O 2 on SiC structure with model fit. The inset shows the ordinary and extraordinary refractive index of 4 H − S i C .

Although accounting for anisotropic backside reflection yields scientifically meaningful results for modeling such samples, it is not practical from an industrial perspective. Implementing this correction necessitates incorporating the substrate thickness into the model and fitting it during lateral mapping. This approach not only increases analysis time but may also reduce sensitivity to thin layer thickness due to parameter correlation. Excluding the backside-reflected light from the measured intensity would enable a more robust model with enhanced sensitivity to thin oxide layers.

Microspot System and Instrumental Enhancements

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

To effectively address this issue, a precisely configured microspot system is essential for reducing or eliminating backside reflections, thereby minimizing spectral interference. The microspot system of the Semilab SE-2000 achieves this by employing the so-called knife-edge method.
The principle of this method is based on the optical separation of frontside, and backside reflected light, ensuring that the backside reflection does not reach the detector. In specific configurations, the system can be adjusted so that only the backside reflected light is detected, while the frontside reflection is excluded.
The implementation of the knife-edge method is based on the SE-2000 microspot system which reduces the measurement spot size by projecting the light source onto the sample, achieving a minification. Using the identical optical configuration in the reverse way at the detection side, it magnifies not only the measurement spot, but also the distance between the frontside reflected light and the virtual position of the backside reflected light. (Fig. 3).

[picture]

Fig. 3. Schematic drawing shows how the SE-2000 microspot system helps exclude the backside reflection. The layer and substrate thicknesses are not to scale.

Fig. 3. Schematic drawing shows how the SE-2000 microspot system helps exclude the backside reflection. The layer and substrate thicknesses are not to scale.

The effect of the microspot system on the backside reflection removal could be improved if we further reduce the spot size. In a projection-based system, it could be accomplished either by decreasing the focal length ratio of the focusing objective and the collimation optic or by minimizing the object size. The object size could be reduced by introducing a pinhole in front of the lamp which reduces the area from which the light of the source is used.

Experimental Results and Sensitivity Demonstration

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

The investigated sample in this study was a native oxide layer on 4H−SiC. The instrument used was an SE-2000 spectroscopic ellipsometer equipped with an automatic goniometer and an Ultra Microspot option. In practice, the Ultra Microspot employs a pinhole in front of the light source to further decrease the measurement spot size and mitigate unwanted reflections.
Fig. 4. shows measurement and fitted spectra of a 1.2 nm thick SiO2 layer on 4H−SiC along with two simulated spectra using the same model but varying the layer thickness by ±0.5 nm. The measurement in this case applies both the above-mentioned methods for improving the measurement quality. The 70∘ incidence angle provides sensitivity for even small thickness changes and the microspot system, along with the ultra-microspot pinhole, effectively reduces the backside effect to the noise level.

[picture]

Fig. 4. Measured native oxide layer on 4H−SiC surface with fitted thickness of d=1.201 nm and simulated curves for layers with d±0.5 nm. The dashed and dotted curves apparently present the sensitivity of the Brewster's angle conditions for small changes in thickness

Fig. 4. Measured native oxide layer on 4 H − S i C surface with fitted thickness of d = 1.201 n m and simulated curves for layers with d ± 0.5 n m . The dashed and dotted curves apparently present the sensitivity of the Brewster's angle conditions for small changes in thickness

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

This study demonstrates that spectroscopic ellipsometry enables highly sensitive measurement of ultrathin oxide layers on 4H−SiC substrates. However, due to the material's high transparency, elevated refractive index, and the limited thickness of the substrate, specific methodological enhancements are required to ensure measurement robustness. These include the suppression of anisotropic backside reflections and the optimization of measurement geometry-particularly by aligning the incidence angle near the Brewster's angle of the sample. With these improvements, spectroscopic ellipsometry holds strong potential to become a standard process control technique for wide-bandgap materials, even in applications where precise monitoring of thin oxide layers is critical.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.15.pdf

T. Kimoto "Material science and device physics in SiC technology for high-voltage power devices" 2015 Jpn. J. Appl. Phys. 54040103.

J. Koerfer, M. Rommel, A. Fuchs, O. Rusch. "Improvement of Reflectance Spectroscopy for Oxide Layers on 4H-SiC". SSP;358:109-14.

L. Makai, T. Lehto, B. Fodor, P. King; "Breakthrough instruments and products: Investigation of atomic layer deposited layer by spectroscopic ellipsometry from the deep-UV to the mid-IR in one instrument." Rev. Sci. Instrum. 92 (11): 119501.

R. Ahuja et al "Optical properties of 4H-SiC". J. Appl. Phys. 91: 2099-2103.

D. W. Berreman, "Optics in Stratified and Anisotropic Media: -Matrix Formulation," J. Opt. Soc. Am. 62, 502-510 (1972).

H. Fujiwara, Spectroscopic Ellipsometry: Principles and Applications, (Wiley, 2007).

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 21-28

doi: 10.4028/p-apC4NR

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-29

Accepted:
2026-02-23

Online:
2026-05-19

A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

Christian Stefan Gruber 1,2,a*, Gregor Pobegen 1,b and Jürgen Smoliner 2,c

1 Kompetenzzentrum für Automobil- und Industrieelektronik GmbH, Europastraße 8, 9524 Villach, Austria

2 Technische Universität Wien, Institute of Solid State Electronics, Gußhausstraße 25-25a, 1040 Wien, Austria

a* christianstefan.gruber@k-ai.at, b gregor.pobegen@k-ai.at, cjuergen.smoliner@tuwien.ac.at

Keywords: recombination lifetime, minority charge carrier lifetime, effective lifetime, scanning electron microscope, electron beam induced current, time-resolved EBIC.

Abstract

We present a new method to potentially map the effective minority charge carrier lifetime by means of a chopped electron beam induced current in a scanning electron microscope using a digital lock-in amplifier. While previous authors have been mainly interested in measuring the diffusion length and some even the minority charge carrier lifetime using line-scans, we show that this method could be extended to measure the lifetime locally in the cross section of a given device. In our case, we use a simple SiC pn-junction. The decrease of current with increasing chopping frequency of the electron beam makes a direct measurement of the effective lifetime possible. Inspired by optical beam induced current (OBIC), this novel approach has great potential to measure the minority charge carrier lifetime locally and is going to help device and process engineers to develop the next generation of SiC power devices.

Introduction

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The effective minority charge carrier lifetime is a crucial parameter that influences a plethora of device characteristics, most notably reverse recovery and in consequence, the switching speed of a power device. For future optimization in both device and process engineering, this raises the question and the need to accurately measure the effective lifetime not only of an entire device, which may be seen as an integrated measurement of all local lifetimes combined, but locally. Existing optical methods include time-resolved photoluminescence [1], time-resolved photoconductance [2] measurements but none of these methods reach sub-micron resolution. A scanning electron microscope (SEM) outperforms optical excitation setups by orders of magnitude in terms of spot size. Thus, a scanning electron microscope can be used in order to obtain the effective minority charge carrier lifetime with great spatial resolution.
The phenomenological process of recombination may be split up into the following physical processes: Shockley-Read-Hall, radiative, Auger-Meissner and surface recombination [3].
These recombination effects can also be written in terms of their corresponding lifetime: Shockley-Read-Hall (SRH) τAug ,radiative τrad  and Auger-Meissner τAug  lifetime. Surface recombination τsur  also needs to be considered:

1τeff=1τSRH+1τrad+1τAug+1τsur(1)

In terms of their physics, SRH describes the recombination of electron-hole pairs through deep level impurities or traps. The energy that is set free during the process is mediated by phonons. Radiative recombination describes a direct band-to-band transition, whose energy is set free by a photon. For intrinsic SiC (without doping), radiative recombination however is unlikely due to its indirect band gap. Radiation may however be emitted through optical transitions of point defects in the crystal. Auger-Meissner recombination is a three-particle process. When an eh-pair recombines, the transition
energy is given off to an outer shell electron, resulting in the ionization of the atom. Surface recombination is a phenomenon that occurs at semiconductor interfaces to other media (such as air or other dielectrics). The crystal lattice is abruptly disturbed. Dangling bonds at this interface become traps for eh-pairs [3] and lead to rapid recombination and short lifetimes near the surface.
Accounting for all recombination processes separately needs labor-intensive measurements, while usually the effective carrier lifetime τeff  is sufficient in most cases to optimizate the device according to the need of the device engineer and subsequently the application.

Theory

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In our effective lifetime measurements, we use the well-known technique called electron beam induced current (EBIC). An incident electron beam on a semiconductor sample creates electron hole pairs. If an electric field is present (like the electric field of a depletion region), the eh-pairs are separated efficiently and can be measured in an external electrical circuit (see Fig. 2). EBIC is used in many applied fields such as failure analysis or defect characterization. Theoretically, it can best be described by the diffusion equation [4] for minority carriers in a n -doped material (same considerations apply for a p-doped material):

Dp∂(pn−pn0)∂x2−pn−pn0τp=∂pn−pn0∂t(2)

Here, Dp is the diffusion coefficient, pn−pn0 the excess carrier concentration and τp the effective carrier lifetime. Steady-state EBIC is by far the most common technique. Therefore, in steady-state, the right-hand side of Eq. 2 is 0 and we get the well-known solution IEBIC∝exp(−xLp), where Lp=Dpτp is the diffusion length. Since in the following analysis, we are concerned with a frequency-dependent approach, the excess carrier concentration oscillates with a given frequency, thus making a time-dependent approach necessary [4]:

u(x)=(pn−pn0)eiωt(3)

u(x) is the general solution to the diffusion Eq. 2 may now be rewritten:

d2udx2−1Lp(1+iωτp)u(x)=0(4)

This differential equation may be solved, yielding the following general solution (using ω=2πf )

u(x)=Aexp(xLp(β+iγ))+Bexp(−xLp(β+iγ))(5)

with

β,γ=12±1+1+(2πfτp)2(6)

The coefficient A is zero, because far away from the junction, EBIC should be null. The phase γ has a minus sign, such that the phase becomes zero in steady-state ( f=0 ). This short mathematical derivation already gives some interesting theoretical insights into the semiconductor material and the EBIC signal and its corresponding phase. This relationship between EBIC, phase and distance are plotted in Fig. 1. With an increase of the beam blanking (chopping) frequency of the electron beam, the EBIC signal is expected to decrease, while the phase becomes more negative. From this decrease in EBIC, the effective carrier lifetime τp may be determined. The same information can be obtained from the phase γ.

[picture]

Fig. 1. Theoretical EBIC signal prediction of a carrier lifetime of 1μs for increasing distance x from the depletion region scaled by the diffusion length L . Solid lines denote the current, dashed lines are the phase prediction for different frequencies. The higher the chopping frequency, the smaller the EBIC signal response with increasing distance (left scale), following Eq. 5. Simultaneously, the phase (right hand scale, dotted straight lines) becomes more negative with increasing frequency.

Fig. 1. Theoretical EBIC signal prediction of a carrier lifetime of 1 μ s for increasing distance x from the depletion region scaled by the diffusion length L . Solid lines denote the current, dashed lines are the phase prediction for different frequencies. The higher the chopping frequency, the smaller the EBIC signal response with increasing distance (left scale), following Eq. 5. Simultaneously, the phase (right hand scale, dotted straight lines) becomes more negative with increasing frequency.

Plotting the EBIC response in the frequency domain is another method to determine the effective lifetime, as is depicted in Fig. 1. Fig. 1 neglects the surface contribution to the EBIC signal. In a real experiment, the EBIC signal is affected by surface recombination, altering the minority charge carrier lifetime. This surface effect can however be accounted for quantitatively, using the technique of Pang et. al. [5]. This method may be altered to use different acceleration voltages for the electron beam (probing depths) as interpolation points to determine the diffusion coefficient and the surface recombination velocity locally.

Another well-known method is time-resolved cathodoluminescence (same principle as time-resolved photoluminescence), which is however limited to measure the radiative carrier lifetime only.

Method

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While the previous analysis has been performed by numerous authors [6, 7, 8] using time-resolved EBIC in the 1980s and very recently by Vasco et. al. [9], local measurement and comparison near the depletion region of minority charge carrier lifetime using the frequency-EBIC method on device level has not been done to our knowledge. After background subtraction at a particular position x, we compare the normalized data of a low and high frequency domain EBIC to deduce the local effective lifetime anywhere in the device:

r=log(I500kHz)log(I20kHz)=−x1Lp2±1+1+(2πf500kHzτp)2−x1Lp2±1+1+(2πf20kHzτp)2(7)

We expect τp to be in a range of roughly 10−7−10−6 s far away from the depletion region, such that the product f20kHzτp is negligible (the error being around 0.2% for a lifetime of 1μs ), such that we can write:

r=121+1+(2πf500kHzτp)2(8)

One could potentially measure the steady state EBIC with a regular DC-EBIC amplifier instead. However, using two different measurement instruments can yield erroneous results in the magnitude (such as offsets and differences in the amplification factor). From an application standpoint, low frequencies also require long averaging times, since lower frequencies have longer periods. To average over the same number of periods thus requires more time. In consequence, the beam needs to dwell at point (xi,yi) until the lock-in amplifier has successfully done its averaging and returned the signal into the SEM before the beam may move to position ( xi+1,yi ). Otherwise, the lock-in signal becomes a mix of EBIC at ( xi,yi ) and ( xi+1,yi ) which is generally undesired.

Eq. 8 can easily be rewritten in terms of τp :

τp=(2r2−1)2−12πf500kHz(9)

This derivation has one flaw: The diffusion length Lp as well as the lifetime τp are considered constants with respect to x in the analytical solution made by McKelvey. Here, first the diffusion Eq. 2 is solved with constant Lp and τp, but we then change our view and assume it to be dependent on x.

Experimental Setup

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In our experiment, a Thermo Fisher Apreo 2 with a Zurich Instruments HFLI Lock-In Amplifier was used. The blanking capability of the Thermo Fischer Apreo 2 SEM is limited by a 20 ns rise/fall time, which gives a highest usable frequency of 100 MHz . The usable frequency range is much lower due to parasitic capacitances in the cables and measurement electronics. The setup is depicted in Fig. 2: A reference signal of the lock-in amplifier was fed into the beam blanking electronics of the SEM. The beam is thus blanked at a desired frequency f. The chopped beam hits the sample and creates eh pairs which diffuse towards the nanoprobing needle or chuck on the back of the sample. This EBIC shown in (c) is then measured in the lock-in amplifier. Meanwhile, it is always possible to obtain a secondary electron image such as from the separated Everhardt-Thornley detector (ETD) as depicted in (b).
As shown in Fig. 2 (d), one could potentially sweep all available frequencies to obtain the entire lowpass filter behavior of a certain position. Since this procedure is quite laborious, it is sufficient to pick two suitable EBIC images taken at two different carefully chosen frequencies (ideally one low frequency and one large one without neglecting the limitations of the SEM, cables and lock-in amplifier).

Results

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Our sample is a high bandgap SiC diode. The most important physical properties are summarized in Table 1. The depletion layer thickness and electric field were calculated from the available doping concentrations and voltage drop.

Table 1. Physical properties of the investigated SiC pn-junction.

p-region doping concentration (cm⁻³) | 10¹⁸ (Al)
p-region thickness (nm) | 400
epitaxial layer doping concentration (cm⁻³) | 10¹⁶ (N)
epitaxial layer thickness (nm) | 5000
Voltage drop (V) | 2.93

Within the depletion region, speaking of a minority charge carrier lifetime originating from a diffusion current is misleading. In the depletion region, this process is not dominated by diffusion but by a drift current. When an eh-pair is generated in the depletion region, the electric field and not a diffusion current accelerates the electrons and holes towards their respective oppositely charged junction boundaries (much like in a plate capacitor). In this analysis, we talk of this time as the transit time t from the generation of a charged carrier to the border of the depletion region and not as the minority carrier lifetime.
Using the mobilities μp,n of electrons and holes in SiC ( 900 and 100 cm2Vs respectively), the transit time through the depletion region can be computed easily. The velocity v=μE [10] can also be rewritten in terms of v=w/t, w being the depletion width. We computed a transit time in the range of picoseconds. Even though these calculations are at best approximate, one can deduce that these transit times are much smaller than the effective minority carrier lifetimes measured in the following analysis. It can thus be assumed that when an eh-pair is generated in the depletion region, it is first swept across the depletion region before it can be measured as current in the external circuit, as majority carriers. The effective minority charge carrier lifetime of generated minority charge carriers on their path towards the depletion region is what we can measure in this analysis, not when carriers are generated within the depletion region. A possible subject for further investigation is bias dependence of EBIC: One could apply a small forward bias (not greater than the built-in voltage) or reverse bias to the junction, such that the depletion region shrinks or expands. That way, the minority charge carrier lifetime closer or further away from the abrupt pn-junction could be analyzed, bearing in mind that the voltage drop only occurs at the depletion region boundary. These experiments have however not been performed yet and will be investigated in the future.

[picture]

Fig. 2. Schematic of the experimental setup: a) The beam is blanked by the reference signal of the lock-in amplifier. If the eh-pairs are generated close enough to the depletion region, they can diffuse to the respective contact pads/back metallization respectively, and be recorded by the lock-in amplifier. Simultaneous measurements (b) of secondary electrons (SE) in the Everhardt-Thornley Detector (ETD) and (c) EBIC is common to yield secondary electron and EBIC images from the scanning of the electron beam over a region of interest. d) Frequency dependence of the EBIC current at position X1. As stated, we refrain from performing an entire sweep of frequencies, but rather compare a low and high frequency EBIC image, which is sufficient to create effective lifetime maps.
By stacking two EBIC images on top of each other, the ratio r and subsequently τp can be obtained from Eq. 9, as depicted in Fig. 3. While strictly only two frequency-dependent EBIC (fEBIC) images are necessary to obtain the minority charge carrier lifetime, some line scans were obtained to show the characteristic decrease of EBIC with increasing frequencies.

Fig. 2. Schematic of the experimental setup: a) The beam is blanked by the reference signal of the lock-in amplifier. If the eh-pairs are generated close enough to the depletion region, they can diffuse to the respective contact pads/back metallization respectively, and be recorded by the lock-in amplifier. Simultaneous measurements (b) of secondary electrons (SE) in the Everhardt-Thornley Detector (ETD) and (c) EBIC is common to yield secondary electron and EBIC images from the scanning of the electron beam over a region of interest. d) Frequency dependence of the EBIC current at position X1. As stated, we refrain from performing an entire sweep of frequencies, but rather compare a low and high frequency EBIC image, which is sufficient to create effective lifetime maps. By stacking two EBIC images on top of each other, the ratio r and subsequently τ p can be obtained from Eq. 9, as depicted in Fig. 3. While strictly only two frequency-dependent EBIC (fEBIC) images are necessary to obtain the minority charge carrier lifetime, some line scans were obtained to show the characteristic decrease of EBIC with increasing frequencies.

[picture]

Fig. 3. Frequency-dependent normalized EBIC current (at 10kHz,20kHz,100kHz and 500 kHz ) and the respective minority charge carrier lifetime (in red) of line-scans using Eq. 9. The bump in lifetime close to zero is a result of computing a value close to log(1)=0.

Fig. 3. Frequency-dependent normalized EBIC current (at 10 k H z , 20 k H z , 100 k H z and 500 kHz ) and the respective minority charge carrier lifetime (in red) of line-scans using Eq. 9. The bump in lifetime close to zero is a result of computing a value close to log ( 1 ) = 0 .

Summary and Outlook

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We have shown that the effective minority charge carrier lifetime can be computed locally in the cross section of a device which may provide valuable information of recombination characteristics. Here, we only use line-scans to measure the lifetime locally, however this technique can be extended to measure the lifetime anywhere in a device, since this technique does not require the knowledge of x or L. While this novel technique has great potential to be used in future failure analysis and device optimization techniques, there are still some unsolved challenges to overcome until this method is ready to be fully automated. Once this method runs smoothly everywhere in the cross section, we will be using different accelerating voltages to compute both the diffusion coefficient and the surface recombination velocity locally.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

This work was funded by the Austrian Research Promotion Agency (FFG, Project No. 914019).

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.21.pdf

Li, Z., Liu, A., Basnet, R., Black, L. E., Macdonald, D., & Nguyen, H. T. (2025). Applications of time-resolved photoluminescence for characterizing silicon photovoltaic materials. Semiconductor Science and Technology, 40(4), 045015.

Sanders, A., & Kunst, M. (1991). Characterization of silicon wafers by transient microwave photoconductivity measurements. Solid-state electronics, 34(9), 1007-1015.

D. K. Schroder, Semiconductor Material and Device Characterization, third ed., John Wiley & Sons, Hoboken, 2006.

J. P. McKelvey, Solid state and semiconductor physics, Robert E. Krieger Publishing Company, Malabar, 1966.

S. Pang, A. Rohatgi, A new methodology for separating Shockley-Read-Hall lifetime and Auger recombination coefficients from the photoconductivity decay technique, Journal of applied physics, 74 (1993) 5554-5560.

T. Fuyuki, H. Matsunami, Determination of lifetime and diffusion constant of minority carriers by a phase-shift technique using an electron-beam-induced current, Journal of Applied Physics, 52 (1981) 3428-3432.

J. Pietzsch, Measurement of minority carrier lifetime in GaAs and with an intensity-modulated electron beam, Solid-State Electronics, 25 (1982) 295-304.

N. Honma, C. Munakata, H. Itoh, T. Warabisako, Nondestructive Measurement of Minority Carrier Lifetimes in Si Wafers Using Frequency Dependence of ac Photovoltages, Japanese Journal of Applied Physics, 25 (1986).

S. Bustillos-Vasco, N. Baier, C. Lobre, C. Cervera, N. Péré-Laperne, A. Evirgen, O. Gravrand, Use of Electron Beam-Induced Current Technique to Characterize Transport Properties of Narrow-Gap-Energy Materials for IR Detection, Journal of Electronic Materials, 53 (2024) 5850-5857.

S. M. Sze, Y. Li and K. K. Ng, Physics of Semiconductor Devices, third ed., John Wiley & Sons, Hoboken, 2007.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 29-35

doi: 10.4028/p-iPd033

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-20

Accepted:
2026-02-23

Online:
2026-05-19

Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1191.29.pdf

Robin Karhu 1,a*, Volker Häublein 1, b, Marshall Wilson 2,c, Mathias Rommel 1, d and Birgit Kallinger 1,e

1 Fraunhofer IISB, Schottkystrasse 10, 91058 Erlangen, Germany

2 Onto Innovation, 12415 Telecom Dr., Tampa, FL 33637, USA

a* robin.karhu@iisb.fraunhofer.de, b volker.haeublein@iisb.fraunhofer.de, c  marshall.wilson@semilabsdi.com, d  mathias.rommel@iisb.fraunhofer.de, ebirgit.kallinger@iisb.fraunhofer.de 

Keywords: oxide, CV measurement, LPCVD TEOS, thermal oxide.

Abstract

An area of increasing interest for SiC device processing is the processing and qualification of silicon oxides. In this article a contactless corona CV (CnCV) measurement procedure is evaluated as a way to gain more knowledge about the different processes related to oxides. A 21-point measurement pattern is used to gain information about uniformity of oxide properties. Two different types of oxides have been considered, low pressure chemical vapor deposited (CVD) oxides using tetraethylorthosilicate (TEOS) and thermally grown oxides. The two different groups have received different combinations of pre- and post-processing steps prior to measurements. As expected, low pressure CVD (LPCVD) and thermally grown SiO2 without any post oxidation annealing (POA) showed significantly different electrical characteristics compared to the wafers that did get a POA. This difference could clearly be distinguished by CnCV , meaning that individual process steps can be analyzed without the fabrication of any test structures on the wafers. As the individual process steps can be analyzed, the uniformity of the individual steps can be accessed. Using a 21-point pattern it was possible to show that there is a non-uniformity in the LPCVD process used prior to the POA. This makes the CnCV technique suitable for in-line characterization and process monitoring.

Introduction

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As silicon carbide technology continues to mature, higher demands are put on each of the processing steps. One area where increased monitoring is desired is that of different oxide layer formation steps that take place during device fabrication. This is due to the wide variety of different oxides that are used. This could be chemical vapor deposition (CVD) oxide to be used as hard mask [1], a thermal oxide to be used as a gate oxide for SiC MOS devices [2], or an atomic layer deposited (ALD) oxide for special applications [3]. What further complicates oxide qualification is that additional processing might affect the properties of the final oxide. The gate oxide quality of a MOS transistor is, e.g., also dependent on the surface quality of the substrate, implying that gate oxide optimization also depends upon the activation anneal after the ion implantation. So, if certain oxide properties are desired, a good understanding of the processing steps and their effect on the oxide is required. Hence, inline control measurements for oxide properties are needed which are quick and do not require any test structure. This study aims to investigate the influence of different processing steps on oxide characteristics using a contactless corona-based capacitance voltage ( CnCV ) technique to characterize the oxides [4]. The CnCV technique uses a corona spot charging device and a Kelvin probe to perform a CV measurement of the oxidized wafers. From these measurements it is possible to extract the equivalent oxide thickness (EOT), total dielectric charge ( Qtot ), flatband voltage ( VFB ), and the distribution ofinterface trap densities ( Dit  ) which can be calculated up to about 0.8 eV from the band edge. The CnCV technique can be used on bare oxides and does not require any test structures. This makes CnCV a strong candidate for inline process monitoring as the contactless nature enables fast measurements without the need of manufactured test structures and the wafers can be returned into the processing line afterwards. The CnCV technique is explained in detail in reference [4].

Experimental

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Six 150 mm4H−SiC homoepitaxial wafers with epitaxial layer thickness between 10.8−12.3μ m have been considered in this work. The epitaxial layers are doped using nitrogen to a net doping concentration of 8.4-8.9 ·1015 cm−3. The wafers received one of two types of oxides, either a silicon oxide realized by a low-pressure chemical vapor deposition (LPCVD) process using TEOS followed by a densification step in inert atmosphere at 900∘C or a thermally grown dry oxide. The LPCVD TEOS deposition took place at a temperature of about 700∘C and the thermal dry oxides were grown at about 1300∘C. The wafers received different combinations of pre- and post-oxide treatments. The pretreatment was a time coupled HF dip where the wafer is dipped in HF immediately prior to loading into the LPCVD reactor or furnace. The post process was a post oxidation anneal (POA) at 1300∘C in a nitrogen monoxide (NO) atmosphere. All processes generated oxides with a thickness between 50−60 nm. The wafer processing is summarized in Table 1.

Table 1. Summary of the wafer processing used in this work. The first column is the wafer "Wafer" identification number. The second column "Time coupled HF dip" indicates whether the wafer got the time coupled HF dip pre-oxide treatment or not. The third column "Oxide" indicates what type of oxide the wafer received. The fourth column "Post oxidation anneal" indicates whether the wafer received the post oxidation anneal in NO atmosphere or not.

Wafer | Time coupled HF dip | Oxide | Post oxidation anneal
1 | Yes | LPCVD TEOS | No
2 | Yes | LPCVD TEOS | Yes
3 | No | LPCVD TEOS | Yes
4 | Yes | Thermal dry oxide | No
5 | Yes | Thermal dry oxide | Yes
6 | No | Thermal dry oxide | Yes

Reproducibility of Measurements

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The wafer used in this study on reproducibility is a wafer that got the same oxide processing steps as wafer 4 in Table 1. The initial voltage ( Vinit  ) measurement by the Kelvin probe depends on the potential of the surface. Vinit  is obtained without applying any charge to the wafer. Thus, it is possible to map Vinit  without affecting later measurements that involve charging the wafer. Vinit  can change drastically depending on what the wafer has been exposed to prior to the measurement, such as charge left on the surface from a previous CnCV measurement or surface absorbed contaminants from water or isopropyl alcohol. The lack of control of the surface absorbed contaminants makes it difficult to reproduce a surface condition. This causes variations in the measured Vinit.  In the following section a demonstration of the reproducibility is shown without perfect restoration of the wafer surface between measurements. To fairly assess the reproducibility of the measurements, the wafer was partially dipped in deionized water and then dried on a hotplate at 95∘C for 10 minutes before each consecutive measurement. In Figure 1 an example is shown; the lower part of the wafer has been dipped in deionized water and the measurement point is marked. A ten-time repeat of the measurement is presented in Table 2. From Table 2 Vinit  was measured between 0.13−0.29 V. This uncertainty adds to the uncertainty of Qtot  as Qtot  is the amount of charge required to reach VFB from Vinit.  To compare Qtot  between the different measurements the Qtot  values have been corrected to the Vinit  of the first
measurement. These are the Qtot  values that we will consider in this paper. Qit  differs from the more widely used Dit in that Dit is evaluated at a specific position in the bandgap, in this case at an energy level of 0.3 eV below the Fermi level ( EF ) (see Figure 2). Qit is obtained by integrating the Dit spectrum between 0.05−0.3eV and for the evaluation of the reproducibility of the measurements Qit  has been considered instead of the more widely used Dit . In Figure 2 the Dit  spectra for each consecutive measurement overlap almost perfectly. Notice that the Dit  spectra in Figure 2 has been translated to represent the energy below the conduction band, the Dit at EF−0.3eV values in Table 2 can be found at about 0.49eV(0.3eV+EF) below the conduction band in Figure 2. In Table 2 the sigma/mean values for the different properties can be seen. For VFB sigma/mean value is 1.56%, for Qit 2.18%, and for EOT it gives 0.15%. Later in this paper it will be shown that these sigma/mean results are sufficient to resolve most of the processes considered.

[picture]

Fig. 1. A map showing the distribution of Vinit  of the wafer used in the reproducibility test.

Fig. 1. A map showing the distribution of V init of the wafer used in the reproducibility test.

Table 2. Summary of the ten consecutive measurements done to test the reproducibility.

Measurements: | Vinit [V] | Vfb [V] | Dit at Ef-0.3eV [10¹¹cm⁻²eV⁻¹] | Qit [10¹¹ q/cm²] | Qtot [10¹¹q/cm²] | Qtot corr. to same Vinit [10¹¹q/cm²] | EOT [Å] | Nd [10¹⁵ cm⁻³]
1 | 0.18 | 2.13 | 3.01 | 1.99 | -6.18 | -6.18 | 540 | 9.93
2 | 0.24 | 2.16 | 3.42 | 2.08 | -6.23 | -6.26 | 537 | 10.1
3 | 0.21 | 2.14 | 3.13 | 1.99 | -6.22 | -6.21 | 540 | 10.1
4 | 0.17 | 2.15 | 3.12 | 2.01 | -6.29 | -6.23 | 540 | 9.88
5 | 0.25 | 2.11 | 3.24 | 2.02 | -6.04 | -6.18 | 539 | 10.0
6 | 0.16 | 2.19 | 3.39 | 2.14 | -6.47 | -6.28 | 539 | 10.0
7 | 0.22 | 2.10 | 3.27 | 2.07 | -5.99 | -6.17 | 540 | 9.87
8 | 0.29 | 2.22 | 3.33 | 2.05 | -6.09 | -6.22 | 539 | 9.83
9 | 0.14 | 2.15 | 3.18 | 2.01 | -6.31 | -6.19 | 539 | 9.96
10 | 0.13 | 2.18 | 3.00 | 2.00 | -6.56 | -6.32 | 539 | 9.92
Average: | 0.20 | 2.15 | 3.21 | 2.04 | -6.24 | -6.22 | 539 | 9.96
Standard deviation: | 0.05 24.6 | 0.03 1.56 | 0.141 | 0.0444 | 0.172 | 0.0470 | 0.79 0.15 | 0.0785
1σ/Mean: | 1% | % | 4.40% | 2.18% | 2.76% | 0.76% | % | 0.79%

[picture]

Fig. 2. Dit  spectra for all of the consecutive measurements numbered #1−#10. The measurements have been made at the site marked in Figure 1.

Fig. 2. D it spectra for all of the consecutive measurements numbered # 1 − # 10 . The measurements have been made at the site marked in Figure 1.

Measurements

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The measurements of the six wafers have been performed in a 21-point pattern as shown in Figure 3. This allows for analysis of the uniformity of oxide properties across the wafers. In Figure 4 the VFB values for each wafer have been plotted for each measurement point. One of the LPCVD TEOS and one of the thermal oxide wafers exhibit significantly higher VFB values than the other four wafers. These are the two wafers that did not get the POA, i.e., wafers 1 and 4. Among the other four wafers it can be seen in the insert that the LPCVD TEOS group together, wafer 2 and 3, and the thermal oxide wafers group together, wafers 5 and 6 . But no significant systematic difference is detected between wafers 2 and 3, and wafers 5 and 6. In Figure 4 b) an outlier can be seen at the center of wafer 6 . This comes from accidental charge left at this measurement spot during the experimental setup.

[picture]

Fig. 3. Explanation of the measurement pattern used for all measurements.

Fig. 3. Explanation of the measurement pattern used for all measurements.

[picture]

Fig. 4. The flatband voltage, VFB, of all six wafers. a) measurements along the x -axis, b) measurements along the y -axis.

Fig. 4. The flatband voltage, V F B , of all six wafers. a) measurements along the x -axis, b) measurements along the y -axis.

In Figure 5 the EOT data is presented, exhibiting several similarities with the results presented in Figure 4, namely, that the two outlier wafers are wafer 1 and 4, the two wafers that did not receive the POA. This increase in EOT for the other wafers is expected as the POA is performed in a NO atmosphere that slightly adds to the EOT thickness. Another similarity between Figure 4 and 5 is that the two LPCVD TEOS wafers 2 and 3 group together and the two thermal oxide wafers 4 and 5 also group up together. One interesting observation is that the LPCVD TEOS process used resulted in concave thickness profiles, both along the x - and y -axis. This is different from the thermally grown oxides that resulted in convex thickness profiles. The shape of the oxide thickness profiles was not changed significantly with the processing steps considered in this work.

[picture]

Fig. 5. EOT of all six wafers, a) along the x-axis, b) along the y-axis.

Fig. 5. EOT of all six wafers, a) along the x -axis, b) along the y -axis.

Figure 6 contains the Qit  results across the wafers. The trends are much the same as in Figure 4 and 5, the two outlier wafers are wafer 1 and 4, the two wafers that did not receive the POA. This is in line with current understanding of POA in NO atmosphere, as it is densifying the oxide and reducing the density of interface traps [5]. Once again, the other two LPCVD TEOS wafers, 2 and 3, do not have any systematic difference from each other. The same is true for the two remaining thermally oxidized wafers, 4 and 5.

[picture]

Fig. 6. Qit of all the six wafers, a ) along the x -axis, b ) along the y -axis.

Fig. 6. Q i t of all the six wafers, a ) along the x -axis, b ) along the y -axis.

Figure 7 shows a collection of Dit  spectra from wafers 1 and 5 . Every color used is a separate Dit  spectrum for each measurement site in Figure 3. All the spectra overlap very well and indicate that the interface traps are very uniformly distributed across the wafers.

[picture]

Fig. 7. Dit  spectra of all the 21 measurement points plotted in the same graph. Every color corresponds to a different measurement site. a) wafer 1, b ) wafer 5 .

Fig. 7. D it spectra of all the 21 measurement points plotted in the same graph. Every color corresponds to a different measurement site. a) wafer 1 , b ) wafer 5 .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.29.pdf

Six 150 mm homoepitaxial SiC wafers received silicon oxide layers through different combinations of processing steps. These wafers were measured at 21 points using the CnCV measurement technique. The resulting profiles for VFB, EOT and Qit  were discussed and although there are a lot of similarities, significant differences became evident. Outlying wafers are always the two wafers that did not receive the POA. This is expected as the POA is supposed to have a large impact on the enhancement of oxide properties. The LPCVD TEOS and the thermal oxides show differences that can be resolved in these measurements. An example is the behavior of the EOT values across the wafers in Figure 5, where the LPCVD TEOS oxides show a concave shape and the thermal oxides show a convex shape even with the pre- and post- processing steps considered in this work. When looking at the wafers that differ only on whether they received the time coupled HF dip or not (wafers 2 and 3 for the LPCVD TEOS case and wafers 5 and 6 for the thermally grown oxides), these wafers could not be systematically distinguished from each other. This could mean that the time coupling between the HF dip and the oxidation is less strict than previously expected, or that the oxide processes considered in this work are not very sensitive to any natural oxide formed prior to the oxide process. A big benefit of the large number of measurement sites, i.e., 21points, is that a lot of
information about uniformity is gained. Looking at the LPCVD TEOS oxides in Figure 4 for example, the VFB of wafer 1 has a weak concave profile along the x -axis, while VFB is lowest closest to the wafer flat and highest at the opposite side of the wafer along the y -axis. As the measurement method is contactless, this enables the wafers to be returned to production after measurement. In the future more processing steps should be considered to see if this method is suitable to either monitor oxide processing or process development.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.29.pdf

Y-H Tseng, B-Y Tsui, J. Vac. Sci. Technol. A 1 November 2016; 34 (6): 061305.

Dev Alok, P. K. McLarty, B. J. Baliga, Appl. Phys. Lett. 23 May 1994; 64 (21): 2845-2846.

C. Kim, J. H. Moon, J. H. Yim, D.H. Lee, J.H. Lee, H. H. Lee, H. J. Kim, Appl. Phys. Lett. 20 February 2012; 100 (8): 082112.

M. Wilson, A. Findlay, A. Savtchouk, J. D'Amico, R. Hillard, F. Horikiri, J. Lagowski, ECS Journal of Solid State Science and Technology, 6 (11) S3129-S3140 (2017).

H. Li, S. Dimitrijev, H. B. Harrison, D. Sweatman, Appl. Phys. Lett. 14 April 1997; 70 (15): 2028-2030.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 37-42

doi: 10.4028/p-lyf5Sy

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-29

Revised:
2025-12-24

Accepted:
2026-02-23

Online:
2026-05-19

Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

S. De Luca 1,a*, A. S. Mancuso 1,2,b, A. Muoio 1,c, E. Sangregorio 1,d and F. La Via 1,e

1 CNR-IMM, sede di Catania Strada VIII 5 - Zona Industriale I-95121 Catania, Italy

2 Università degli Studi di Catania, Via S. Sofia n. 64, 95123 Catania, Italy

a saverio.deluca@cnr.it, b alfio.mancuso@phd.unict.it, c annamaria.muoio@cnr.it, d  Enrico.Sangregorio@imm.cnr.it, e  francesco.lavia@cnr.it

Keywords: 4 H -SiC detectors, OBIC (Optical Beam Induced Current) technique, electric field characterization, Synopsis TCAD simulations.

Abstract

Silicon carbide ( SiC ) is a wide-bandgap semiconductor that has attracted considerable attention for the development of advanced electronic and sensing devices. Thanks to its combination of high breakdown field, excellent thermal conductivity, and chemical stability, SiC enables operation in conditions where conventional semiconductors fail. In this study, the Optical Beam Induced Current (OBIC) technique will be employed to analyze the electric field distribution within the structure of SiC bipolar diodes featuring varying epitaxial layer thicknesses. To create OBIC signal we have used ultraviolet laser beam. We have tested bipolar diodes with both 10μ m and 100μ m epilayer thicknesses. We have obtained several OBIC signals by re-scanning the same location at different reverse voltages applied to the same SiC diode. Also, Synopsis TCAD simulations of the electric field are reported for both diodes. In these simulations it is possible to observe the increase of the electric field at the edge of the devices that are observed by the OBIC measurements. In conclusion, OBIC technique aids in optimizing device design and improving overall performance.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

Silicon carbide ( SiC ) is a wide-bandgap semiconductor known for its outstanding characteristics, making it especially suitable for high-voltage and harsh-environment applications [1-3]. Compared to conventional silicon (Si)-based power devices, SiC consistently demonstrates superior performance [4]. For this reason, 4H-SiC-based devices are increasingly considered as a promising solution to meet the rising demand for high blocking voltages, with requirements ranging from about 3 kV for train electronics to more than 10 kV for electrical distribution networks. In this context, a new generation of 4H−SiC power devices has been developed at CNR-IMM in collaboration with ASM company, aiming to meet the needs of next-generation high-voltage applications. The new-designed devices were tested using the Optical Beam Induced Current (OBIC) technique, a characterization technique that relies on the current generated by an ultraviolet laser ( 325 nm ) to study the electric field in the device at different voltages. The results were compared to numerical simulations performed using the Synopsys Sentaurus TCAD simulation toolkit [5].

Tested Devices

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

The devices investigated in this work are 4H−SiC bipolar diodes developed by CNR-IMM with the support of ASM company. Two types of diodes were fabricated, primarily differing in the thickness and doping concentration of the epitaxial layer to optimize their performance for different blocking voltage ranges. The device designed to operate at 3 kV was grown on n-type 4H−SiC substrates with an epitaxial layer of 10μ m thickness and a doping concentration of 1015 cm−3, while the device designed to operate at 10 kV was fabricated on the same substrate material but featured a thicker
epitaxial layer of 10μ m with a lower doping concentration of 1014 cm−3. In both cases, the P+/N junction was established by epitaxially grown a P+layer on top of the N−epitaxial layer, with a doping concentration of 1018 cm−3. A large active area of 2,25 cm2 was designed for both devices, allowing them to sustain currents on the order of several amperes. To ensure stable operation at high voltages, special edge termination structures were implemented to shape the electric field at the device periphery, preventing premature breakdown. Specifically, a P−Junction Termination Extension (JTE) and a N+Field Stop guard ring was realized through ion implantation to close the field lines and so confine the electric field inside the active area of detectors. The design of the devices, including the active region and the edge termination, is illustrated in Fig. 1, which shows a schematic lateral cross-section of the 4H−SiC bipolar diodes.

[picture]

Fig. 1. Lateral cross-section of the 4H−SiC diode, illustrating the active region (on the left) and the edge termination structure (on the right), including the P−JTE and the N+Field Stop Guard Ring.

Fig. 1. Lateral cross-section of the 4 H − S i C diode, illustrating the active region (on the left) and the edge termination structure (on the right), including the P − JTE and the N + Field Stop Guard Ring.

Experimental Setup and OBIC Technique

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

To create electron-hole pairs inside the semiconductor, a 325 nm UV laser beam was used, as shown in Fig. 2 (a), where the structure of the used bipolar diode with a Junction Termination Extension (JTE) has been reported. The laser beam has been focused by 10 x and 40 x objectives, and the resulting spot diameters size were of the order of 10−5 mm respectively. The focused laser beam was moved on the surface of the device with steps of 2 microns. Both 10 and 100μ m bipolar diodes were tested under revers bias conditions, with voltages in the range of 10−200 V. The voltage was provided and measured by a Keithley 2450 and 2470 SMU (Source Measurement Unit). The OBIC signals were then mapped in 2-directions ( X and Y ) or along one line using a dedicated LabSpec6 software. Fig. 2 (b) shows the OBIC signal generated during a linear laser scan of the device. Four distinct regions can be identified, arising from the different interactions between the laser and the various layers of the material.

[picture]

Fig. 2. (a) Schematic representation of experimental set-up and UV laser used to generate carriers (electron-hole pairs). (b) OBIC signal obtained along a straight line of the entire device.

Fig. 2. (a) Schematic representation of experimental set-up and UV laser used to generate carriers (electron-hole pairs). (b) OBIC signal obtained along a straight line of the entire device.

Results and Discussions

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

The intensity of the photo-generated current is linked to the intensity of the average electric field and therefore to the reverse voltage applied to the detector under test. In Fig. 3. (a) the four different regions can be better observed. Until 50μ m the OBIC is about zero because the laser is outside the active region of the device (Region 1), this signal represents the background current of the detector. Starting from 50μ m an increase of the OBIC signal is observed, as the laser is irradiating the edge structure of the device (Region 2). Close to 200μ m a large decrease of the current is observed as the laser beam reaches the Al metallization layer (Region 3). Then, starting from about 230μ m, a large flat region is visible in correspondence of the anode of the device (Region 4). In this case, the intensity of OBIC is lower with respect to the edge of the device (Region 2) because the thin silicide layer on the top of the P+epitaxial layer produces a reduction of the laser intensity that arrives in the depleted layer, due to its high reflectivity. The same behavior has been observed on the other side of the detector, as shown in Fig. 2 (b).
OBIC signals were acquired at different reverse biases (up to 200 V ) by re-scanning the same location with the laser. The increased electric field caused by an increase in reverse voltage results in an increase of the OBIC signal at the same location, as observed in Region 2 of Fig. 3 (a). Here, using a 10 V reverse bias, the induced current obtained by the laser scan decreases towards the edge of the device (going throws Region 1). This result is linked to a low electric field induced by the reverse polarization. As the reverse bias increases to 50 V , a box-like OBIC signal suggests a uniform electric field in this region. By increasing even more the reverse bias, a small peak of the OBIC current is observed close to the edge of Region 2, suggesting a higher value of the field in this region. The same behavior is observed in the thicker diode (Fig. 3. b), where the OBIC peak is visible already at 50 V . By the amplitude of the OBIC signal in Region 2, the lateral depletion width was calculated at different tensions, the results are reported in Fig. 4 (b).

[picture]

Fig. 3. (a) Photo-current produced by UV laser in 10μ m (a) and 100μ m (b) epilayer thickness SiC detectors along the four regions close to the device edge at different reverse biases. The different amplitude of induced currents depends on the different filters used for the two detectors.

Fig. 3. (a) Photo-current produced by UV laser in 10 μ m (a) and 100 μ m (b) epilayer thickness SiC detectors along the four regions close to the device edge at different reverse biases. The different amplitude of induced currents depends on the different filters used for the two detectors.

o connect experimental data with the structures of the new detectors, several simulations were carried out using Synopsys Sentaurus TCAD for both 10 and 100μ m epitaxial layer devices. Fig. 4 (a) shows the electric field distribution of the 100μ m epitaxial layer device at 500 V . Under these conditions, the simulation reveals a high-intensity electric field point (marked by a red circle) at the boundary between Region 2 and Region 1, responsible for the induced current peak observed experimentally.
Fig. 4 (b) compares the experimental and simulated lateral depletion widths of the boundary region for both devices as a function of the square root of the applied reverse bias. In both cases, experimental and simulated data follow a linear trend up to ~170μ m, where saturation of the lateral depletion occurs. The simulated depletion width of the 10μ m device shows a better agreement with the corresponding experimental data compared to the 100μ m device. This discrepancy may be related to the different objectives used during the characterization of the two devices.

[picture]

Fig. 4. (a) Simulated electric field distribution of the 100μ m epitaxial layer device at 500 V , showing the peak close to the edge of Region 2 (red circle) and the lateral depletion region. (b) Comparison between simulated and experimental lateral depletion widths for the 10μ m and 100μ m epitaxial layers devices as a function of the square root of the applied reverse bias.

Fig. 4. (a) Simulated electric field distribution of the 100 μ m epitaxial layer device at 500 V , showing the peak close to the edge of Region 2 (red circle) and the lateral depletion region. (b) Comparison between simulated and experimental lateral depletion widths for the 10 μ m and 100 μ m epitaxial layers devices as a function of the square root of the applied reverse bias.

Finally, to highlight the correlation between the OBIC signal and the electric field within the device, the mean electric field and the induced current at different reverse bias were evaluated at specific x positions. Fig. 5 reports the simulated mean electric field (averaged along the y direction) and the corresponding experimental induced current measured at different reverse biases for the 100μ m epitaxial layer device at x=150μ m. The electric field was averaged over the first 20μ m from the surface, corresponding to the laser interaction volume. As the reverse bias increases, the induced current rises, reflecting the increase in the mean electric field, which enhances carrier drift velocity and reduces recombination losses. Once a 100% charge collection efficiency (CCE) is reached, further increases in the applied bias, and thus in the internal electric field, do not result in a higher induced current, since all generated carriers are already collected. This behavior explains the exponential correlation observed in Fig. 5.

[picture]

Fig. 5. Simulated mean electric field vs induced current obtained in the plateau area in Region 2 (position x=150μ m ) at different reverse bias for 100μ m epitaxial layer device. The electric field was averaged along y line for the first 20 microns of depth from the surface. This is the penetration thickness of the used UV-laser.

Fig. 5. Simulated mean electric field vs induced current obtained in the plateau area in Region 2 (position x = 150 μ m ) at different reverse bias for 100 μ m epitaxial layer device. The electric field was averaged along y line for the first 20 microns of depth from the surface. This is the penetration thickness of the used UV-laser.

Conclusions

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

Several measurements and simulations were performed on a new generation of 4H−SiC devices. The electric field distribution within SiC bipolar diodes under reverse bias was characterized using the Optical Beam Induced Current (OBIC) technique with a spatial resolution of 5−10μ m. This approach enabled the investigation of the edge structure of high-voltage P+/N diodes through the analysis of OBIC signals. The experimental results were compared with TCAD simulations, and optimization of the simulation parameters is in progress to reduce the mismatch with the experimental data at low bias for both devices. Future work will focus on the characterization of the 100μ m epitaxial layer device using a 349 nm UV laser, in order to gain deeper insight into the electric field distribution within the thick epitaxial region.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.37.pdf

K. Shenai et al., IEEE Trans. Electron. Dev. 36 (9) (1989) 1811-1823.

C. Raynaud et al., Diam. Relat. Mater. 19 (2010) 1-6.

T. Mizushima et al., Proc. Int. Symp. Power Semicond. Dev. IC's (2014) 277-280, 10.10.1109/ ISPSD.2014.6856030. WBGS Young, ICSCRM Michael, J. Appl. Phys. 00, 5050 (2021).

S. Tudisco et al., Sensors 18.7 (2018): 2289.

Synopsys Sentaurus TCAD Ver. J-2014.09, Synopsys, Inc., Mountain View, CA, USA. (2014). Available online: .

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 43-47

doi: 10.4028/p-3U7wdg

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-14

Accepted:
2026-03-08

Online:
2026-05-19

A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Han-Wei Chen 1,a*, Chiao-Yang Cheng 2, b, Wei-Liang Lai 3,c, Yew-Chung Sermon Wu 3, d, Bing-Yue Tsui 1,e*

1 Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C

2 The Academy of Innovative Semiconductor and Sustainable Manufacturing, National Cheng Kung University, Tainan, Taiwan, R.O.C

3 Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan, R.O.C

a  weich.ee12@nycu.edu.tw, b 11408019 @gs.NCKU.edu.tw, c  a2289063@gmail.com,

d  sermonwu@nycu.edu.tw, e  bytsui@nycu.edu.tw

Keywords: Super-junction, Schottky barrier diode, Epitaxial growth, DLTS, SIMS, AFM, Molten KOH.

Abstract

The impact on doping profile, surface roughness and defect production of each process step for a suggested Multiple epitaxy and implantation (MEI) process for Super-junction has been investigated through Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. Results show that the suggested process can possibly reduce the cost of the original fabrication and speed up the process.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Super-junction (SJ) is known to alleviate the tradeoff between breakdown voltage and specific on-resistance by applying the concept of charge balance [1]. However, the most common fabrication method of SJ structure, Multiple Epitaxy and Implantation (MEI), is time-consuming and costly due to the process complexity [2−3]. On the other hand, hydrogen pretreatment is applied before epitaxial growth, in which the surface is etched and implanted atoms (usually aluminum) may precipitate into the epitaxial chamber. In this work, we examine each step of the MEI process and propose suggestions to simplify the process.

Device Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Fig. 1 shows the main process steps of the experiment, representing one cycle of the MEI process. First, two 4H−SiCn-type epi-wafers with a 11−μm-thick-epi-layer and nitrogen doping concentration of 8.0×1015 cm−3 were prepared. Al ion implantation with energy up to 2.5 MeV was carried out with high energy implanter on half of the wafers, with the expectation that no Al atoms would be distributed within the surface layer of 0.3μ m. Next, one wafer was coated with photoresist and baked to form a carbon cap (C-cap) on the SiC surface. Afterwards, the wafer underwent a 1700∘C postimplantation annealing (PIA) process for 30 minutes, followed by sacrificial oxidation (to a thickness of 35 nm ) after C-cap removal. Surface etching of approximately 0.2μ m by H2 treatment was performed and the subsequent n-type epi-layer with thickness of 2.5μ m and the same doping concentration was grown on both wafers. Table. 1 lists the sample IDs and split conditions. The quality of the regrown epi-layer was analyzed by Secondary Ion Mass Spectrometer (SIMS), Atomic Force Microscope (AFM), Deep Level Transient Spectroscope (DLTS) and Molten KOH etching. For DLTS analysis, the samples underwent further process. After a 400−nm-thick PECVD SiO 2 layer was deposited as field oxide, active areas were defined by photo lithography and wet etching processes. Next, Ti/TiN/Al stack were sputtered and patterned, with backside metal deposited in the following step. Finally, the samples were annealed at 500∘C for 5 minutes in vacuum and SBD were fabricated.

Table I. Samples ID and process conditions.

Sample | Al implantation | Annealing
I-A | Yes | Yes
NI-A | No | Yes
I-NA | Yes | No
NI-NA | No | No

[picture]

Fig. 1. Process steps, schematic wafer structure and the cross section of Schottky barrier diode (SBD).

Fig. 1. Process steps, schematic wafer structure and the cross section of Schottky barrier diode (SBD).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

Fig. 2 shows the depth profile of the I-NA and I-A samples obtained by SIMS. The results are also compared to TCAD simulations. Through the figure, it can be seen that whether or not PIA was performed, the regrown epi-layer did not affect the Al distribution. No Al in the regrown epi-layer was detected, indicating that after neglecting the low-energy ion implantation step, no Al atoms escape into the epitaxial chamber. Fig. 3 shows the surface roughness ( Rq ) of the four samples measured by AFM. It is expected that implantation without annealing and sacrificial oxidation would increase Rq, which could influence the subsequent epitaxial growth. However, the results show that the Rq values of the four samples are similar, indicating that skipping the annealing and sacrificial processes does not make a significant difference from this perspective.

[picture]

Fig. 2. Secondary Ion Mass Spectrometry (SIMS) depth profiles of Al in the I-NA and I-A samples.

Fig. 2. Secondary Ion Mass Spectrometry (SIMS) depth profiles of Al in the I-NA and I-A samples.

[picture]

Fig. 3. Atomic Force Microscopy (AFM) surface morphology of the four samples.

Fig. 3. Atomic Force Microscopy (AFM) surface morphology of the four samples.

The results of DLTS measurements for the samples are shown in Fig. 4. All samples exhibit a similar and weak Z1/2 signal, and the defect concentration is approximately 6.85×1012 cm−3. The NINA sample shows another signal at 400 K , which is assumed to be RD1/2 with defect density of 3.28×1013 cm−3 and may have been generated during epitaxial growth process [4-5]. To verify this assumption, additional samples with epitaxial layers grown using the same equipment were also fabricated into SBDs and examined by DLTS (Fig. 5). It was found that samples exhibited the RD1/2 signal did show a defect density of 1.2×1012~3.8×1012 cm−3. The following epitaxial might have increased the defect density in the second growth step. On the other hand, the I-NA sample shows a strong signal at 440~460 K. Since the samples underwent Al implantation, we assume the signal originates from ON1 and ON2a[6]. Last, the I-A sample shows an abnormal signal peaked at 500 K . Compared with the previous sample, we suppose that annealing and sacrificial oxidation may have converted the defect into new ones due to the high-temperature process, resulting in a signal combining ON2a and ON2 b [7-9]. Since the defect concentrations in some samples of I-A and I-NA are similar, if PIA is skipped and the MEI cycle is continued, the overall defect concentration will not be affected, although the defect type may be altered [10].

[picture]

Fig. 4. Deep Level Transient Spectroscopy (DLTS) spectra of the NI-NA, I-NA, and I-A samples.

Fig. 4. Deep Level Transient Spectroscopy (DLTS) spectra of the NI-NA, I-NA, and I-A samples.

[picture]

Fig. 5. Deep Level Transient Spectroscopy (DLTS) spectra of other samples with epitaxial growth from the same equipment.

Fig. 5. Deep Level Transient Spectroscopy (DLTS) spectra of other samples with epitaxial growth from the same equipment.

Fig. 6 shows the optical images of the molten KOH -etched surfaces. For I-NA sample, the densities of threading edge dislocations (TEDs) and threading screw dislocations (TSDs) are 1153 cm−2 and 192 cm−2, respectively; on the other hand, for I-A sample, the density of TEDs and TSDs are 1077 cm−2 and 153 cm−2. These values are comparable to that of typical SiC epitaxial wafers. There is no significant difference in the densities of TEDs between the two samples, indicating that the dislocations are nearly independent of the annealing process in the MEI cycle. However, there is a noticeable difference in the densities of TSDs. The difference can be attributed to the variations in substrate quality. The most influential step affecting the quality of the epitaxial layer is still the regrowth process.

[picture]

Fig. 6. Image of SiC surface after molten KOH etching of (a) I-NA sample and (b) I-A sample.

Fig. 6. Image of SiC surface after molten KOH etching of (a) I-NA sample and (b) I-A sample.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

In this work, we examined the impact of each process step of the MEI process on the quality of the subsequent epi-layer. From SIMS analysis, skipping the low-energy implantation prevents Al escape into the epitaxial chamber during growth of the subsequent n-epi layer, thereby avoiding contamination and the following maintenance of the chamber. Moreover, surface roughness and the dislocation density in the subsequent epi-layer are independent of whether PIA is performed. Through DLTS, results indicate that PIA may induce defect transformation, but the slightly increased deeplevel defects can be mitigated by the subsequent epitaxial process. The influence of these defects on the electrical characteristics on devices should be further investigated. Nevertheless, if p-pillar ion implantation and subsequent epitaxy can be performed sequentially, the cost and process complexity could be significantly reduced.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

This work was supported by the National Science and Technology Council, Taiwan, R.O.C. under the contract No. NSTC 113-2218-E-A49-018. Experimental processes were helped by Diodes Inc. and Nano Facility Center of National Yang Ming Chiao Tung University.

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The original version of this paper is available on https://www.scientific.net/MSF.1191.43.pdf

T. Fujihira, Jpn. J. Appl. Phys. 36 6254, (1997).

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T. Okuda et al, Appl. Phys. Express 8 111301, (2015).

H F Xiong et al, J. Semicond. 45 072502, (2024).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 49-53

doi: 10.4028/p-4zjeaP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-09

Accepted:
2026-02-26

Online:
2026-05-19

Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

Nicola Rinaldi 1,a*, Luigi Di Benedetto 1, b, Mathias Rommel 2,c, Alexander May 2, d, Leander Baier 2,e, Rosalba Liguori 1,f, Alfredo Rubino 1, g and Gian Domenico Licciardo 1,h

¹Department of Industrial Engineering, University of Salerno, Via Giovanni Paolo II, 132, Fisciano, Italy

2 Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystraße 10, Erlangen, Germany

a  nrinaldi@unisa.it, b  Idibenedetto@unisa.it, c  mathias.rommel@iisb.fraunhofer.de, d alexander.may@iisb.fraunhofer.de, e leander.baier@iisb.fraunhofer.de, f rliguori@unisa.it, g arubino@unisa.it, h gdlicciardo@unisa.it

Abstract

The effects of 673 K temperature anneal on a 4H−SiC CMOS NOT logic gate have been investigated. After an annealing at 673 K for 30 minutes in ambient atmosphere, a shift of threshold logic voltage, VM, towards higher input voltage by 6.67%, and a hysteresis reduction are observed. Both effects can be related to MOSFETs electrical behavior after the same thermal annealing. The threshold voltage of NMOSFET, VTH, N, increases by 6.67%, whereas PMOSFET one reduces by 11.15%, allowing the VM increase. NMOSFET shows a reduction of its trans-characteristic hysteresis, △VH, by −33.3%, as well as PMOSFET one, that is by −20.4%, explaining the hysteresis reduction of NOT gate. Moreover, a more reproducible NOT transfer characteristics is obtained after the 673 K annealing.

Keywords: 673 K annealing, NOT logic gate, 4H−SiC lateral MOSFETs, 4H−SiC CMOS technology.

Introduction

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Wide band-gap semiconductors are suitable for harsh environment thanks to their intrinsic physical properties [1]. Among them, 4 H polytype of Silicon Carbide, 4H−SiC, has emerged, with the development of lateral devices and integrated circuits, ICs [2]. JFET and BJT based technologies have been demonstrated for high temperature applications with several integrated circuits [3,4]. However, the process easiness allows the CMOS technology to emerge. This one has proven promising with complex ICs able also to operate up to 773 K [5-7], with the integration of novel devices [8] or conventional lateral temperature sensors [9,10].
Although demonstration of circuits and devices up to very high temperature, i.e. 773 K , have been already done, there is still a lack of knowledge about the reliability of circuit performance, like the repeatability of the results after different temperature anneals.
In this paper, we investigate the static room temperature performances of a 4H−SiC CMOS NOT logic gate after several temperature anneals, which have been heated in ambient atmosphere environment at 673 K for 30 minutes. In addition, we relate the NOT gate electrical behavior after thermal annealing to MOSFET one.

Device Structure and Experimental Set-Up

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NOT logic gate has been fabricated in 4H−SiC CMOS Fraunhofer IISB's Technology [7]. The process starts with the epitaxial grow of a 1015 cm−3 n-type layer on a 4 H -SiC n-type 350μ m4∘ offaxis (0001) substrate. Aluminum and Nitrogen ion implantation, followed by 1973 K,30 minutes, thermal annealing is performed for n -type and p -type doped regions. A doping concentration of 1017cm−3 and 1016 cm−3 is obtained for p -well and n -well regions, respectively. Whereas a doping concentration of 5·1019 cm−3 is for high doped p+and n+regions. A 55 nm thick gate oxide is thermally grown at 1300∘C and a post-oxidation annealing is performed at 1300∘C in NO
environment to reduce the SiO2/4H−SiC interface state density. All these process steps result in gate oxide capacitance, Cox=62.8nF/cm2. Gate electrode is made by depositing a 500 nm thick n-type PolySilicon. NiAl and Ti/Al are used for n-type and p-type contact respectively, whereas a Ti/Pt metal layer stack is used for the two lines of metal interconnections. More detailed information regarding process steps is in [7].
The NOT logic gate is made by a NMOSFET with channel width, WN=6μ m, and a PMOSFET with channel width, WP=44μ m, both with channel length, L=6μ m.
Measurements have been made at room temperature, i.e. T=298 K, with a Keithley SCS-4200, a SUSS PM5 probe station and with Signatone Corporation manipulators. Each temperature anneals consists of heating the devices in ambient atmosphere at 673 K for 30 minutes with a 630 W G.Maier Elektrotechnick GmbH hotplate.

Results and Discussion

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NOT logic gate Characteristics.

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The NOT logic gate is supplied by VDD=20 V and transfer characteristics at T=298 K after multiple 673 K temperature anneals are reported in Fig.1.a). It can be observed that after first 673 K temperature anneal, a shift of threshold logic voltage, Vm, of +6.67% and a reduction of hysteresis voltage, from ΔVH=0.2 V to ΔVH=0.15 V, are observed, as shown in Fig.1.a)-b). Moreover, a reduction of High Noise Margin, NMH, of −6.74% and an increase of Low Noise Margin, NMl, of +6.95%, can be calculated (see Fig.1.c)). Whereas, after the second 673 K temperature anneal, almost the same values of Vm and NML are reached, with a variation of 0.94% and 1% with respect to the first 673 K anneal, and the same value of NMH is observed in Fig.1.c).
Then, a 673 K thermal annealing shows an improvement of NOT performances and a more stable and repeatable transfer characteristic.

[picture]

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T=298 K and VDD=20 V. b) Threshold logic voltage and c) Noise Margins variations.

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T = 298 K and V D D = 20 V . b) Threshold logic voltage and c) Noise Margins variations.

[picture]

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T=298 K and VDD=20 V. b) Threshold logic voltage and c) Noise Margins variations.

Fig. 1. a) NOT logic gate transfer characteristic before and after 673 K temperature annealing, at T = 298 K and V D D = 20 V . b) Threshold logic voltage and c) Noise Margins variations.

The effects of the thermal annealing on NOT gate, i.e. shift of its transfer characteristics towards higher voltage and its hysteresis reduction, are related to electrical behaviors of individual devices. Indeed, we analyzed the transfer characteristics in linear region of a NMOSFET and a PMOSFET.

MOSFETs Characteristics.

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Trans-characteristics, at ∣ Vds ∣=0.1 V, of NMOSFET and PMOSFET, both with W=18μ m and L=6μ m, before and after the first 673 K temperature anneal are in Fig.2.a) and in Fig.3.a), respectively. After the thermal annealing, we observe an increase of NMOSFET threshold voltage, Vth, n , extracted according to the extrapolation in linear region method [11], by 6.93% and a reduction of PMOSFET threshold voltage, Vth, p , by −11.15%. This phenomenon can be related to the release of fixed oxide charge, allowing a shift of the flat band voltage towards higher values. Moreover, a reduction of the hysteresis of NMOSFET and PMOSFET characteristics by - 33.3% and −20.4%, respectively, can be observed, which agrees with the reduction of the NOT gate hysteresis. In this case, thermal energy supplied by 673 K annealing could reduce the density of acceptor like slow border traps [12], leading to the hysteresis reduction.
Subthreshold Slope, SS, is obtained from the slope of Ids - Vgs curves, under subthreshold conditions at VDS=0.1 V [13] and same SS is observed for NMOSFET, (see Fig.2.c).
Finally, field effect channel mobility is extracted from trans-characteristics in Fig.2.a) and Fig.3.a) according to [14]:

μCH=dIDSdVGS|VDS=0.1VLVDSCoxW(1)

and, also in this case, same maximum channel mobility, μCH, N peak =19.4 cm2/Vs, was observed (see Fig.2.d). In contrast, the PMOSFET shows a SS reduction of −23.8% and an increase of the channel mobility maximum, μCH,P peak of 4.1% (see Fig. 3.c and d)), which can be related to a reduction of SiO2/4H−SiC interface defects density [15] and, therefore, to a decrease of the associated scattering [16].
Moreover, substituting extracted NMOSFET threshold voltage values before and after thermal annealing, see Fig. 2.b) and Fig.3.b), and the channel mobility peaks, see Fig.2.d) and Fig.3.d), in the following equation of Vm [17]:

VM=VTH,N+r(VDD−|VTH,P|)1+r(2)

where:

r=μCH, P peak COXWPLμCH, N peak COXWN, we obtain a △VM=0.84 V, almost near to the experimental one of 0.6 V,

Fig.1.b), allowing to explain the Vm shift towards higher value.

Fig. 2. a) Trans-characteristic of NMOSFET before and after 673 K temperature anneal. b) The inset shows the extracted Vth,n. In c) Subthreshold Slope and d) field-effect channel mobility.

[picture]

Fig. 3. a) Trans-characteristic of PMOSFET before and after 673 K temperature anneal. b) The inset shows the extracted Vth,p. In c) Subthreshold Slope and in d) field-effect channel mobility.

Fig. 3. a) Trans-characteristic of PMOSFET before and after 673 K temperature anneal. b) The inset shows the extracted Vth,p. In c) Subthreshold Slope and in d) field-effect channel mobility.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

Analysis of NOT logic gate transfer characteristics after multiple 673 K temperature anneals have been done and its electrical behavior linked to single lateral MOSFETs ones. In particular, the Vm shift towards a higher input voltage value is due to the Vth,n increase by 6.93% and Vth,p decrease by 11.15%. Whereas the NOT transfer characteristics hysteresis reduction can be related to both MOSFETs' hysteresis reduction after the thermal annealing. Then, a 30 minutes 673 K thermalannealing seems to improve the overall devices and circuits performances, improving, also, the repeatability of NOT gate characteristics after multiple temperature anneals.

Author Contributions

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

Conceptualization, N.R and L.D.B; methodology N.R.; validation N.R., L.D.B, L.B and A.M; formal analysis N.R. and L.D.B; investigation N.R., L.D.B, M.R, and L.B; data curation N.R. and L.B.; writing-original draft N.R, L.D.B.; M.R., R.L., and G.D.L; writing-review and editing, N.R, L.D.B., M.R., R.L, and G.D.L; project administration A.R. and M.R.; funding acquisition A.R. All authors have read and agreed to the published version of the manuscript.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.49.pdf

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J. Romijn, S. Vollebregt, L. M. Middelburg, B. El Mansouri, H. W. van Zeijl, M. Alexander, T. Erlbacher, G. Zhang, and P. M. Sarro, Integrated digital and analog circuit blocks in a scalable silicon carbide cmos technology, IEEE Transactions on Electron Devices, 69 (2021) 1, 4-10.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 55-60

doi: 10.4028/p-4kesV3

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-23

Accepted:
2026-03-16

Online:
2026-05-19

Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

Mohamed Torky 1,a*, Justin Lynch 1,b, Nick Yun 1,c, Stephen Mancini 1,d, Miguel Hinojosa 2,e, Aivars Lelis 2,f and Woongje Sung 1, g

¹Department of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203, U.S.A

2 U.S. Army Research Laboratory (ARL), Adelphi, MD 20783 U.S.A

a*mtorky@albany.edu, b  jmlynch@albany.edu, c  nyun@albany.edu, d  smancini@albany.edu, e miguel.hinojosa4.civ@army.mil, f aivars.j.lelis.civ@mail.mil, 9 wsung@albany.edu

Keywords: ultra-high-voltage, ion implantation, lateral straggle, TCAD simulation, edge termination techniques.

Abstract

Achieving reliable breakdown in ultra-high-voltage ( >10kV ) SiC devices is limited by edge termination design, where low epitaxial doping ( ~4×1014 cm−3 ) results in lateral straggle to be more prominent, therefore necessitating wider spacing between Aluminum implants in conventional floating field rings (FFRs). This study introduces a background doping modulation (BDM) scheme, incorporating a moderately doped N-type confinement region within P+ rings, enabling tighter spacing without added process complexity for high-voltage MOSFETs. Fabricated BDM-FFRs achieved >13kV breakdown ( 30% higher than conventional FFRs), with leakage current <10nA at 10 kV , while reducing termination area by 18.6%. Therefore, the BDM-FFR demonstrates a scalable, and high-performance edge termination approach for next-generation ultra-high-voltage SiC devices.

Introduction

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Wide bandgap semiconductors such as silicon carbide ( 4H−SiC ) have emerged as the most promising candidates for next-generation high-voltage and high-efficiency power devices. The materials' superior material properties, wide bandgap, high critical electric field, and excellent thermal conductivity enable devices capable of blocking voltages beyond 10 kV while operating with reduced conduction and switching losses. Such performance is critical for high-voltage direct current (HVDC) transmission, traction inverters, grid integration of renewable energy, and pulsed power systems [1]. Despite significant progress in device fabrication, the realization of reliable and reproducible breakdown voltages (BV) in ultra-high-voltage ( >10kV ) devices remains challenging. A major limitation is the design of edge termination structures, which must suppress electric field crowding at the active area to achieve close-to-theoretical breakdown performance [2]. Conventional termination schemes-including floating field rings [3], junction termination extension (JTE) [4], and a hybrid combination of both designs [5] are widely adopted. In ultra-high-voltage SiC devices, the drift layer is typically thick ( >100μ m ) and lightly doped ( ~4×1014 cm−3 ), which strongly impacts edge termination design. The low doping makes the lateral dopant straggle more prominent, degrading electric field control in conventional FFR structures and requiring wider ring spacing. To accommodate lateral and vertical depletion, the termination width must generally exceed five times the epi thickness, making it a dominant factor in total chip size. A proposed background doping modulation (BDM) ensures a reduced edge termination design that can significantly minimize the lateral straggle, reducing the chip size and hence the chip cost, through improving the blocking characteristics with small spacings.

Edge Termination Theory and Background

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The ideal breakdown voltage of a one-dimensional p-n junction is determined by the peak electric field within the device, influenced by drift layer thickness and doping. Once the peak electric field
reaches the critical electric field of SiC , avalanche breakdown occurs. However, in real devices, field crowding at the active area limits the actual breakdown to ~70−80% of the theoretical value. To mitigate this, edge termination structures are implemented to spread the depletion region laterally and smooth out the electric field distribution. Among various approaches, floating field rings (FFRs) are particularly attractive for high-voltage applications due to their simplicity, scalability, and compatibility with both diode and MOSFET structures. They consist of multiple concentric P+ implanted rings surrounding the active region. The rings gradually drop the potential from the active junction edge to the device periphery, thereby reducing the peak field. However, the effectiveness of FFRs depends critically on ring spacing and dopant profiles, which are strongly influenced by the low doped background.

In 4H-SiC with very low background doping, implanted dopants undergo significant lateral diffusion and straggle [6]. This smearing of ring edges compromises the field distribution and requires increased spacing between rings ( ≥1μ m ). For devices with a hundred rings, this can cause the termination width to extend to nearly 1 mm , which is prohibitive for compact high-current devices. Furthermore, too-small spacing can lead to premature breakdown due to field crowding at ring corners, while too-large spacing results in incomplete field modulation and premature breakdown due to field crowding at the cylindrical junction in the active area [2].

In 10 kV -class SiC devices, edge terminations can occupy ~80% of chip area for a 1 A -rated device and ~50% for a 10 A-rated device, as shown in Fig. 1, reducing current density, increasing cost per ampere, and limiting scalability. To address these issues, this work proposes a novel approach by adding N-type doping within the FFR structure, resulting in background doping modulation (BDM-FFR). By intentionally pre-doping a moderately N-type region before the implantation of the floating field rings, the lateral straggle is suppressed, enabling tighter ring spacing without field crowding [7]. This results in more compact termination, higher breakdown voltage, and reduced leakage current compared to conventional FFR designs.

[picture]

Fig. 1. Edge termination percentage as a function of breakdown voltage for different current ratings.

Fig. 1. Edge termination percentage as a function of breakdown voltage for different current ratings.

Fig. 2 and 3 show the structural differences between the conventional and proposed FFRs. It should be noted that the proposed BDM-FFRs do not require high energy implantation as the primary goal is to accomplish narrow spacing design between P+ concentric rings without increasing the electric field at their corners. Notably, this additional N-type implantation can coincide with the JFET region in standard MOSFET process flows, allowing seamless integration of the proposed structure without adding process complexity. In the case of Schottky or JBS diodes, however, an additional implantation step would be required.

[picture]

Fig. 2. (a) Top and (b) cross-sectional views of conventional FFRs.

Fig. 2. (a) Top and (b) cross-sectional views of conventional FFRs.

[picture]

Fig. 3. (a) Top and (b) cross-sectional views of the proposed BDM-FFRs.

Fig. 3. (a) Top and (b) cross-sectional views of the proposed BDM-FFRs.

Edge Termination Fabrication

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PiN diodes with three different edge terminations designs were fabricated on a 6-inch wafer with a drift layer thickness of 125μ m and N-type doping concentration of 4×1014 cm−3 enabling >10kV blocking capabilities. Nitrogen implantation was used for implanting the background doping modulation (BDM) layer, while high temperature aluminum and nitrogen implantation was used for the P+ rings and the channel stop as shown in Fig. 2 and 3. After implantation, dopants are activated thermally at 1605∘C for 10 min . with a carbon cap. Three different edge termination designs were fabricated; one PiN diode has BDM-FFR with a ring width of 5μ m and a spacing of 0.8μ m. The other two PiN diodes have a conventional FFR design with a ring width of 3μ m and a spacing of 1 μm and 1.5μ m respectively to account for the lateral straggle due to the low doped background.

Table 1. Structural parameters for BDM-FFR, FFR1 and FFR2 devices.

Structural Parameters | BDM-FFR | FFR 1 | FFR 2
BDM | Yes | No | No
W [μm] | 5 | 3 | 3
S₀ [μm] | 0.8 | 1 | 1.5
Si [μm] | 0.03 | 0.1 | 0.05
n | 100 | 100 | 120
L [μm] | 728.5 | 895 | 897

Table 1 illustrates the structural parameters for BDM-FFR and the two conventional FFRs. The nth  spacing between rings as a function of ring number is given by,

Sn=S0+(n+1)Si(1)

where S0 is the initial spacing, n is the number of rings and Si is the spacing increment. Fig. 4 illustrates the simulated doping profiles of both the BDM ( N -type) and P+ rings where the BDM doping is a 2×1016 cm−3 box profile.

[picture]

Fig. 4. BDM (N-type) and P+ implantation profiles used in our study from Sentaurus TCAD simulation.

Fig. 4. BDM (N-type) and P+ implantation profiles used in our study from Sentaurus TCAD simulation.

Results and Discussion

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As shown in Fig. 5 (a) and (b), cross-sectional imaging using Focused Ion Beam (FIB) and SEM confirmed the effectiveness of BDM with a minimal lateral straggle. BDM-FFR rings exhibit sharp boundaries with negligible lateral straggle even at increased depth, while conventional FFRs suffer from substantial smearing and overlap between adjacent rings. Conventional FFRs suffer from lateral straggle with 43% increase in the P+ width, which has been validated by TCAD simulation as shown in Fig. 6. Consequently, we designed the spacings of the conventional FFRs as illustrated in Table 1 to account for the lateral straggle at the expense of the edge termination width.

[picture]

Fig. 5. SEM FIB cross-sectional view for (a) BDM-FFR and (b) conventional FFRs. Numbers inside parentheses denote the designed spacings.

Fig. 5. SEM FIB cross-sectional view for (a) BDM-FFR and (b) conventional FFRs. Numbers inside parentheses denote the designed spacings.

[picture]

Fig. 6. Sentaurus simulation cross-sectional schematic showing the lateral straggle between (a) BDM-FFR and (b) conventional FFRs.

Fig. 6. Sentaurus simulation cross-sectional schematic showing the lateral straggle between (a) BDM-FFR and (b) conventional FFRs.

Wafer-level electrical characterization was performed using Keithley high-voltage probe stations. The breakdown voltage was defined at a leakage current of 100μ A, and leakage characteristics were measured up to 10 kV . Fig. 7 shows the blocking characteristics of FFR1, FFR2, and BDM-FFR. The BDM-FFR achieved a blocking voltage of 12.5 kV , approximately 24% higher than conventional FFR devices, which have a breakdown voltage of 10 and 10.7 kV , respectively. These results demonstrate the improved field control and reduced corner crowding afforded by the BDM-FFR technology, as it has wider rings and controlled spacings between rings due to the minimized lateral straggle. At 10 kV , BDM-FFR exhibited leakage currents of only 2 nA , three orders of magnitude lower than FFR1, which has a leakage current of 8μ A, and a 91% lower leakage in the case of FFR2, which has a leakage of 23 nA . The high leakage in FFR1 is attributed to insufficient ring separation (1μ m), leading to premature conduction and leakage paths. Although the P+ ring width of the BDMFFR is 5μ m compared to conventional FFRs, the termination length (L) of BDM-FFR is only 728.5 μm, compared to ~895μ m for conventional FFRs, an 18.6% total area reduction. This reduction in total area is crucial for scaling to high-current devices where chip area directly impacts cost and manufacturability. The confinement layer limits lateral dopant struggle, thereby stabilizing potential distribution across the rings. This enables narrow ring spacing without excessive electric field concentration at ring corners, leading to higher BV and lower leakage. Table 2 shows the blocking characteristics for the three devices.

[picture]

Fig. 7. Blocking characteristics of BDM−FFR, FFR 1 and FFR 2.

Fig. 7. Blocking characteristics of B D M − F F R , FFR 1 and FFR 2.

Table 2. Blocking voltage and leakage current for BDM-FFR, FFR1 and FFR2.

Blocking Performance | BDM-FFR (S₀ = 0.8 μm) | FFR 1 (S₀ = 1.0 μm) | FFR 2 (S₀ = 1.5 μm)
BV @ IAK = 10⁻⁵ A [V] | 12.5 | 10 | 10.7
IDSS @ VDS = 10 kV [A] | 2×10⁻⁹ | 8.1×10⁻⁶ | 2.3×10⁻⁸

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

This work demonstrates a novel background doping modulation (BDM) edge termination for ultra-high-voltage ( >10kV ) 4H-SiC power devices. By introducing a confinement layer beneath P+ floating field rings, lateral straggle is suppressed, enabling tighter designs with tight ring spacing. Compared to conventional FFRs, BDM-FFR achieved a breakdown voltage of 12.5kV(24% improvement), leakage currents <10nA at 10 kV , and termination width reduction of ~18.6%. These results provide clear evidence that BDM offers a scalable, manufacturable, and high-performance solution for edge termination in next generation SiC power devices. Future work will extend this approach to devices beyond 15 kV and explore integration in power modules for high-current applications.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

The authors would like to thank ADI for fabricating the devices. We also would like to thank Alexander Bialy and Cobert Johnson from NY CREATES for helping in taking FIB and SEM images in Fig. 5.

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The original version of this paper is available on https://www.scientific.net/MSF.1191.55.pdf

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W. Sung, E. V. Brunt, B. J. Baliga, A. Q. Huang, A New Edge Termination Technique for High-Voltage Devices in 4H-SiC-Multiple-Floating-Zone Junction Termination Extension, IEEE Transaction on Electron Devices, 32 (7) (2011) 880-882.

W. Sung, B. J. Baliga, A Near Ideal Edge Termination Technique for 4500V 4H-SiC Devices: the Hybrid Junction Termination Extension (Hybrid-JTE), IEEE Transaction on Electron Devices, 37 (12) (2016) 1609-1612.

J. Lynch, N. Yun, W. Sung, Design Considerations for High Voltage SiC Power Devices: An Experimental Investigation into Channel Pinching of 10 kV SiC Junction Barrier Schottky (JBS) Diodes, 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China, (2019) 223-226.

N. Yun, D. Kim, J. Lynch, A. J. Morgan, W. Sung, M. Kang, A. Agarwal, R. Green, A. Lelis, Developing 13-kV 4H-SiC MOSFETs: Significance of Implant Straggle, Channel Design, and MOS Process on Static Performance, IEEE Transaction on Electron Devices, 67 (10) (2020) 4346-4353.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 61-67

doi: 10.4028/p-S3kheK

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-19

Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Minori Matsuoka 1,a*, Daiki Soda 1, b, Kosuke Miyazaki 1,c, Toshikazu Tanioka 1, d, Kazuya Tojima 1,e, Akira Kiyoi 2,f, Yasuhiro Kagawa 1, g and Tetsuya Nitta 1, h

1 Power Device Works, Mitsubishi Electric Corporation,1-1-1 Imajuku-higashi, Nishi-ku, Fukuoka-shi, Fukuoka, 819-0192, Japan

2 Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki-shi, Hyogo, 661-8661, Japan

a* Matsuoka.Minori@db.mitsubishielectric.co.jp, b Soda.Daiki@dc.MitsubishiElectric.co.jp, c Miyazaki.Kosuke@dw.MitsubishiElectric.co.jp, d Tanioka.Toshikazu@eb.MitsubishiElectric.co.jp,

e Ishibashi.Kazuya@ak.MitsubishiElectric.co.jp, f Kiyoi.Akira@ay.MitsubishiElectric.co.jp,

9  Kagawa.Yasuhiro@cj.mitsubishielectric.co.jp, h  Nitta.Tetsuya@ea.MitsubishiElectric.co.jp

Keywords: MOSFET, body diode, activation annealing, carbon vacancy, reverse recovery charge, electrical characteristics.

Abstract

A body diode is commonly employed as a free-wheeling diode to reduce costs of SiC components instead of an external Schottky barrier diode. However, one of the key issues is higher reverse recovery loss due to bipolar charge contribution to reverse recovery charge. In this study, we investigated the impact of high-temperature annealing on the characteristics of MOSFETs as a costeffective approach to introduce minority carrier lifetime killers. The trap densities of Z1/2 center and EH6/7 center can be controlled by activation annealing temperature. Qrr of 1900∘C measured at 150∘C was significantly decrease by 67% compared to that of 1750∘C attributed to the 89% suppression of Qbip . However, reverse leakage current increased adversely with the activation annealing temperature. Ron  and Vth  increased with the activation annealing temperature. The trade-off of the annealing temperature worsened slightly compared to that of the doping concentration. It is still possible that high-temperature annealing represents a cost-effective approach to improve the reverse recovery characteristics of the body diode.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Silicon carbide ( SiC ) is a suitable material for power devices due to its superior properties such as wide bandgap, high critical electric field, and high thermal conductivity. A body diode is a parasitic p-n diode within a MOSFET structure. In typical switching applications, a body diode is commonly employed as a free-wheeling diode to reduce costs of SiC components instead of an external Schottky barrier diode. The use of the body diode can contribute to cost reduction in SiC components and system miniaturization. However, there are several issues related to the use of the body diode. One of the key issues is a higher reverse recovery loss due to the contribution of bipolar charge ( QBIP ) to the reverse recovery charge ( Qrr ). The recovery current when using the body diode is larger than that when using an external Schottky barrier diode. This is attributed to the fact that QBIP is significantly large due to the body diode being a bipolar device. One measure to reduce the reverse recovery loss is introducing minority carrier lifetime killers. It is known that Z1/2 center is the most representative carrier lifetime killer in n-type 4H−SiC[1]. Z1/2 center and EH6/7 center [2] are identified as traps caused by carbon vacancies [3]. Methods for generating carbon vacancies include electron irradiation [4,5], proton irradiation [6,7], and high-temperature annealing [8]. Electron irradiation and Proton irradiation need additional processes and equipment, while high-temperature activation annealing can potentially introduce carrier lifetime killers without additional processes or equipment, making it cost-effective. This is because the activation of the ion implantation layers needs annealing at temperatures above 1600∘C, allowing for the simultaneous introduction of lifetime killers [9]. Few
studies have reported on the reverse recovery loss of the body diode related to high-temperature activation annealing. Therefore, we investigated the effect of the activation annealing temperature on electrical characteristics of SiC-MOSFETs.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Figure 1 shows the cross-sectional schematics of fabricated SiC planar MOSFETs with 1.7 kV rating on n-type 4H−SiC(0001) wafer. The off-cut angle of the wafer is 4∘. Figure 2 illustrates the MOSFETs fabrication processing flow. After the ion implantation process, these MOSFETs were annealed in Ar atmosphere with a carbon cap. The processing temperatures were set at 1750∘C, 1800∘C and 1900∘C, respectively. The duration at the set temperature was the same. Subsequently, the gate oxidation and the metallization were carried out. The fabricated MOSFETs were evaluated for the trap density of Z1/2 center and EH6/7 center around the PN junction measured by deep level transient spectroscopy (DLTS). Afterwards, we measured the reverse recovery characteristics, reverse leakage current characteristics, and on-state characteristics of the MOSFETs. Typical data were plotted for each activation annealing temperature in the following Figs. 3-8 ,10.

[picture]

Fig. 1. Cross-sectional schematic diagram of the planar SiC-MOSFET.

Fig. 1. Cross-sectional schematic diagram of the planar SiC-MOSFET.

[picture]

Fig. 2. The MOSFETs fabrication processing flow. The activation annealing temperatures were set at 1750∘C,1800∘C and 1900∘C, respectively.

Fig. 2. The MOSFETs fabrication processing flow. The activation annealing temperatures were set at 1750 ∘ C , 1800 ∘ C and 1900 ∘ C , respectively.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

Figure 3 shows the trap densities of Z1/2 center and EH6/7 center calculated from DLTS spectra. DLTS measurement conditions are as follows: reverse bias of -30 V , pulse bias of -15 V and a rate window of 192 ms , with G-S shorted. The DLTS spectrum has two peaks at positions of 300 K and 678 K , which are related to the Z1/2 center and EH6/7 center. The defect densities at 1900∘C are significantly increased compared to 1750∘C and 1800∘C. Figures 4 shows the dependence of trap densities on the activation annealing temperature. The trap densities of both Z1/2 center and EH6/7 center increase exponentially with the activation annealing temperature, reaching approximately 1014/cm3 at 1900∘C. These results suggest that the trap densities of Z1/2 center and EH6/7 center can be efficiently controlled by adjusting annealing temperature.

[picture]

Fig. 3. Trap density calculated from DLTS spectrum.

Fig. 3. Trap density calculated from DLTS spectrum.

[picture]

Fig. 4. Dependency of activation annealing temperature on trap density.

Fig. 4. Dependency of activation annealing temperature on trap density.

Figures 5(a) and 5(b) show the typical reverse recovery waveforms at 25∘C and 150∘C. The reverse recovery characteristics were measured with the double pulse testing method, and the supply voltage and switching drain-source current are 900 V and 265 A/cm2, respectively. The gate voltages of the upper arm and the lower arm are -7 V and −7/+15 V, respectively. At 25∘C, there is almost no difference among the three waveforms, and the reverse recovery currents are independent of the activation annealing temperatures. On the other hand, at 150∘C, the reverse recovery current decreases dramatically from 176 A/cm2 to 131 A/cm2 between 1750∘C and 1900∘C. The reverse recovery charge ( Qrr ) is defined in accordance with JEP201 published by JEDEC as follows,

Qrr=QBIP+QOSSQrr=−∫t0t1Jbddt

(1)(2)

where t0 is defined as the moment when the current density reaches zero, and t1 is defined as the point when the drain voltage reaches 98%. The reverse recovery charge ( Qrr ) was then calculated from the current density between these two time points.

[picture]

Fig. 5. Typical reverse recovery waveforms of the body diode current Jbd  (a) at 25∘C and (b) at 150∘C.

Fig. 5. Typical reverse recovery waveforms of the body diode current J bd (a) at 25 ∘ C and (b) at 150 ∘ C .

Figures 6(a) and 6(b) show the composition of Qrr for each annealing temperature (a) at 25∘C and (b) at 150∘C. The capacitive charge ( Q oss) is independent of the activation annealing temperature. At 25∘C,Qrr and QBIP of 1900∘C is reduced by 13% and 51% compared to that of 1750∘C, respectively. At 150∘C,QBIP  is reduced significantly with the activation annealing temperature. Qrr  of 1900∘C is reduced by 67% compared to 1750∘C attributed to the 89% suppression of Qbip . This suggests that the carrier lifetime of 1900∘C is significantly decreased at 150∘C. Therefore, high-temperature annealing represents an effective method to improve the reverse recovery characteristics of the body diode.

[picture]

Fig. 6. Composition of Qrr for each annealing temperature (a) at 25∘C and (b) at 150∘C.

Fig. 6. Composition of Q r r for each annealing temperature (a) at 25 ∘ C and (b) at 150 ∘ C .

Figures 7(a) and 7(b) show the typical reverse leakage waveforms at 25∘C and 150∘C. A sourcegate voltage ( VGS ) of -7 V is applied. The reverse leakage current increases adversely with the activation annealing temperature both at 25∘C and 150∘C. The reverse leakage current characteristics are nearly the same at 1750∘C and 1800∘C, while the reverse leakage current at 1700 V increases by an order of magnitude at 1900∘C.

[picture]

Fig. 7. Typical reverse leakage characteristics for the SiC -MOSFETs with various activation annealing temperature of VGS=−7 V (a) at 25∘C and (b) at 150∘C.

Fig. 7. Typical reverse leakage characteristics for the SiC -MOSFETs with various activation annealing temperature of V G S = − 7 V (a) at 25 ∘ C and (b) at 150 ∘ C .

To confirm the impact of the Z1/2 center and EH6/7 center on the reverse recovery characteristics, TCAD simulations were conducted in three different cases. Figure 8(a)-(c) show simulation results of reverse recovery waveform at 150∘C (a) with only Z1/2 center, (b) with only EH6/7 center and (c) with both Z1/2 center and EH6/7 center. The trap density, energy and cross-section obtained from DLTS are utilized to simulation parameters as shown in Table 1. In the simulation utilizing with only Z1/2 center (Fig. 8(a)), both the reverse recovery current and the reverse recovery time decrease with increasing the activation annealing temperature. The reverse recovery current and the recovery time in the simulation utilizing only EH6/7 center (Fig. 8(b)) show no significant dependence on the activation annealing temperature. In the simulation utilizing Z1/2 center and EH6/7 center (Fig. 8(c)), the reverse recovery waveforms exhibited a trend similar to those obtained with the Z1/2 center. This trend is also consistent with the measured reverse recovery characteristics. Therefore, we speculate that reverse recovery current is strongly dependent on the density of Z1/2 center.

Table 1. Simulation parameters obtained by DLTS.

trap | Energy [eV] | σe [cm²]
Z1/2 | EC-0.63 | 1.66e-15
EH6/7 | EC-1.44 | 3.39e-16

[picture]

Fig. 8. Simulation results of reverse recovery waveform at 150∘C (a) with Z1/2 center, (b) with EH6/7 center and (c) with Z1/2 center and EH6/7 center.

Fig. 8. Simulation results of reverse recovery waveform at 150 ∘ C (a) with Z 1 / 2 center, (b) with E H 6 / 7 center and (c) with Z 1 / 2 center and E H 6 / 7 center.

Figure 9(a)-(c) show the simulation results of the reverse recovery waveform at 150∘C (a) with Z1/2 center, (b) with only EH6/7 center and (c) with both of Z1/2 center and EH6/7 center. In the simulation utilizing only Z1/2 center (Fig. 9(a)), the reverse leakage current shows slightly dependence on the activation annealing temperature. The reverse leakage current in the simulation utilizing only EH6/7 center (Fig. 9(b)) increases with activation annealing temperature. In the simulation utilizing Z1/2 center and EH6/7 center (Fig.9(c)), the reverse leakage current exhibit a trend like those obtained with the EH6/7 center alone. This trend is also consistent with the measured reverse leakage current characteristics. Therefore, we speculate that the reverse leakage current is strongly dependent on the density of EH6/7 center.

[picture]

Fig. 9. Simulation of off-state I-V characteristics at 150∘C (a) with Z1/2 center, (b) with EH6/7 center and (c) with Z1/2 center and EH6/7 center.

Fig. 9. Simulation of off-state I-V characteristics at 150 ∘ C (a) with Z 1 / 2 center, (b) with E H 6 / 7 center and (c) with Z 1 / 2 center and E H 6 / 7 center.

Figure 10(a) and (b) shows trade-off between on-resistance Ron  and threshold voltage Vth  of 25∘C (a) at 25∘C and (b) 150∘C. Ron  and Vth  increase with high-temperature annealing because the net accepter concentration increases. However, there is a slight difference between the trade-off of the activation annealing temperature and that of doping concentration. It suggests that there are other factors that contribute to the increase in on-resistance.

[picture]

Fig. 10. Trade-off of activation annealing temperature and doping concentration between threshold voltage Vth  at 25∘C and on-resistance Ron  (a) at 25∘C and (b) at 150∘C.

Fig. 10. Trade-off of activation annealing temperature and doping concentration between threshold voltage V th at 25 ∘ C and on-resistance R on (a) at 25 ∘ C and (b) at 150 ∘ C .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

We investigated the impact of high-temperature annealing on the characteristics of MOSFETs as a cost-effective approach to introduce carrier lifetime killers for reverse recovery suppression. The trap densities of Z1/2 center and EH6/7 center were controlled up to approximately 1014/cm3 through the activation annealing temperature. Qrr of 1900∘C was reduced compared to that of 1750∘C, attributed to the significant suppression of QBIP . However, the reverse leakage current increased adversely with the activation annealing temperature. The trade-off between Ron  and Vth  of annealing temperature worsened slightly compared to that of doping concentration.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.61.pdf

K. Danno, T. Hori and T. Kimoto, Impacts of growth parameters on deep levels in n-type 4HSiC, J. Appl. Phys. 101, 053709 (2007).

N. T. Son, X. T. Trinh, L. S. Løvlie, B. G. Svensson, K. Kawahara, J. Suda, T. Kimoto, T. Umeda, J. Isoya, T. Makino, T. Ohshima, and E. Janze, Negative- System of Carbon Vacancy in -SiC, Phys. Rev. Lett. 109, 187603 (2012).

G. Alfieri and T. Kimoto, Resolving the level in 4H-SiC by Laplace-transform deep level transient spectroscopy, Appl. Phys. Lett. 102, 152108 (2013).

P. Dong, Y. Qin, X. Yu, X. Xu, Z. Chen and L. Li, Electron Radiation Effects on the PiN Diodes Characteristics: An Insight from Point Defects to Electrical Degradation, IEEE Access. 7, 170385 (2019).

T. Kimoto and K. Danno, Lifetime-killing defects in epilayers and lifetime control by low-energy electron irradiation, phys. stat. sol. (b) 245, 1213 (2008).

A Castaldini, A Cavallini and L Rigutti Assessment of the intrinsic nature of deep level by compensation effects in proton-irradiated 4H-SiC, Semicond. Sci. Technol. 21 (2006) 724728.

P. Hazdra and S. Popelka, Optimization of SiC Power p-i-n Diode Parameters by Proton Irradiation, IEEE Access. 65, 4483 (2018).

E. Saito, J. Suda and T. Kimoto, Control of carrier lifetime of thick n-type 4H-SiC epilayers by high-temperature Ar annealing, Appl. Phys. Exp. 9, 061303 (2016).

M. Spera, D. Corso, S. Di Franco, G. Greco, A. Severino, P. Fiorenza, F. Giannazzo and F. Roccaforte, Effect of high temperature annealing ( ) on the morphological and electrical properties of p-type implanted 4H-SiC layers, . Mater. Sci. Semicond. Proc. 93 (2019) 274-279.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 69-73

doi: 10.4028/p-5ozE8T

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-15

Revised:
2025-12-23

Accepted:
2026-02-26

Online:
2026-05-19

4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

Virginia Boldrini 1,a, Marica Canino 1, b*, Marco Pieruccini 1,c,Vincenzo Carrano 2, d, Heinz C. Neitzert 2,4,e, Luigi Di Benedetto 2,f, Claudio Santonastaso 3,4,5,g, Raffaele Buompane 3,4,h, Maria Lucia Mitsou 3,4,i, Nicola Casali 6,j, Ravi Prakash Yadav 6,k, Matthias Laubenstein 7,I, Cristian Degli Esposti Boschi 1, m, Alfredo Rubino 2,n, Alba Formicola 6,o, Lucio Gialanella 3,4,p

1 CNR - ISMN Bologna Section, Via P. Gobetti 101, 40129 Bologna, Italy

2 Dip. Ingegneria Industriale Università degli Studi di Salerno - Salerno, Italy

3 Dip. Matematica e Fisica, Univ. della Campania "L. Vanvitelli" - Caserta, Italy

4 Istituto Nazionale di Fisica Nucleare, Sezione di Napoli - Napoli, Italy

5 RIKEN Nishina Center, Wako, Saitama, Japan

6 INFN - Dip. di Fisica "G. Marconi" Piazzale Aldo Moro 2, 00185, Roma, Italy

7 INFN - Lab. Naz. del Gran Sasso, Via G. Acitelli 20, Assergi - L'Aquila, Italy

a  virginia.boldrini@cnr.it, b  mariaconcetta.canino@cnr.it, c  marco.pieruccini@cnr.it,

d vcarrano@unisa.it, e neitzert@unisa.it, f Idibenedetto@unisa.it, g claudio.santonastaso@riken.jp, h raffaele.buompane@unicampania.it, imarialucia.mitsou@unicampania.it,

j  nicola.casali@roma1.infn.it, k  raviprakash.yadav@roma1.infn.it, 'matthias.laubenstein@Ings.infn.it,

m cristian.degliespostiboschi@cnr.it, n arubino@unisa.it, a alba.formicola@roma1.infn.it, plucio.gialanella@unicampania.it

Abstract

This study presents the design, fabrication, and electrical characterization of 4H−SiCp+/n diodes employed to provide a high electric field able to induce Stark effect in 7Be atoms implanted in the space charge region. Indeed, a variation in the half-life of the 7Be radioactive decay is expected to be achieved by applying an electric field of the order of 106 V/cm, which can be produced by reverse-biasing 4H−SiC diodes close to the breakdown voltage. A set of diodes of area ranging between 2.12×10−3 cm2 and 9.88×10−3 cm2 was designed and fabricated to reach breakdown voltages up to 1000 V . When tested under reverse current limitation set equal to 300 nA , over 50% out of 24 devices could withstand reverse bias exceeding 800 V . This work reports on the characteristics of one diode of 9.88×10−3 cm2 area, implanted with 7Be and subject to continuous reverse-bias at 750 V for 107 days. Electrical characterization conducted before, during, and after long-term polarization highlighted an increase in the reverse current generation due to implantation-related defects, which however does not affect the breakdown voltage. These considerations lead to the conclusion that the electric field acting on the implanted 7Be remains stable over time, confirming the suitability of 4H−SiC diodes for both induction and measurement of 7Be lifetime variations.

Keywords: 4H−SiC,p+/n diodes, high voltage reverse current, Be ion implantation, radioactive decay.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

This work focuses on a novel application of 4H−SiC diodes, i.e. their use to provide the electric field required to demonstrate the Stark effect in the radioactive decay of 7Be atoms implanted in the depletion region of a p/n junction. Indeed, a precise measurement of the 7Be half-life in 4H−SiC resulted in ( 53.284±0.016 ) days at zero bias [1]; this value can vary by applying a high reverse bias resulting in an electric field of the order of 106 V/cm[2].4H-SiC represents the material of choice to
conduct such experiment thanks to its high critical electric field and to its tolerance to ion implantation processes. Electrical characterizations, performed by current-voltage (I-V) and capacitance-voltage (C-V) at different fabrication stages, as well as after a high number of radioactive decay events, allow to demonstrate the suitability of 4H−SiC diodes as environment to host ion implanted 7Be atoms while maintaining their blocking capabilities under prolonged high reverse bias operation. Furthermore, identifying the mechanisms of reverse current conduction enables the assessment of electric field stability and sets the basis for result interpretation.

Experimental

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p+/n diodes were realized starting from a 4H−SiC wafer purchased from II-VI, with a 6μ m thick, 1×1016 cm−3 n-type doped epitaxial layer and 2μ m buffer layer. The epitaxial layer thickness and doping were determined by Synopsys TCAD Sentaurus simulations to obtain the required electric field in the 7Be implanted region of around 1MV/cm at -750 V . Al ion implantation followed by 1950∘C30 min annealing led to the formation of the anode and JTE regions extending 350 nm below the sample surface with 5×1019 cm−3 and 1.25×1017 cm−3Al concentration respectively. The front side ohmic contact was made by thin Ti,Al, and Ni layers alloyed in vacuum at 1100∘C for 5 min . A first round of characterization by I-V and C-V was performed in the as-made diodes to select the diode exhibiting the lowest current at 900 V reverse bias, but it is not reported in this work. The chosen device had an anode area equal to 9.88×10−3 cm2.
High energy 7Be ion implantation was performed at the Tandem Accelerator Laboratory, DMF, University of Campania. The beam energy during the implantation was modulated to obtain a boxshaped depth profile with 1×1016 cm−37Be concentration extending between 2.8μ m and 4μ m below the sample surface. A double AZ10XT photoresist layer was used as mask to selectively implant 7Be in the inner region of the diode in a circular area of 960μ m diameter. At 750 V reverse bias the electric field value in the region comprising 7Be is expected to be (1.3±0.2)MV/cm. The diode layout is shown in Fig. 1.

[picture]

Fig. 1. Layout of the epitaxial layer. The horizontal axis scale is in micron, while the vertical axis is not in scale. The grey area represents the 7Be implanted region.

Fig. 1. Layout of the epitaxial layer. The horizontal axis scale is in micron, while the vertical axis is not in scale. The grey area represents the 7 B e implanted region.

750 V reverse bias was applied for 107 days at Gran Sasso National Laboratories (LNGS, Italy) on the wire-bonded device to measure the 7Be decay time in a high electric field. The current flowing through the diode was continuously monitored throughout the progress of the experiment. Finally, IV and C−V curves were acquired after the experiment.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

The high-voltage I-V curves measured in the as-made diodes (called first round measurements) and at the end of the experiment (final measurements), i.e. after 7Be ion implantation and 107 days of reverse bias operation, are shown in Figure 2. Figure 3 shows the corresponding C-V curves at 100 kHz (a) together with the ND vs W plot (b). The final forward I-V characteristics (Fig. 2a) shows a
single exponential slope over more than 6 decades even if with an increase of recombination current, while the reverse bias, though experiencing an increase following the 7Be implantation and the longterm reverse bias, maintains its blocking behaviour. After 107 days a current reduction is observed. For 4H−SiC PiN diodes it has been demonstrated that displacement damage caused by irradiation (thus likely also by ion implantation), can induce an increase in carrier recombination due to lifetimekiller defects (affecting forward I-V characteristic), an increase in generation current (causing reverse leakage), the compensation of n-type region due to acceptor centers and a decrease in carrier mobility caused by scattering [3,4]. After Be implantation the observed increase in reverse current can be ascribed to charge generation at centers within the bandgap induced by defects, but a fairly preserved blocking capability.

[picture]

Fig. 2. Forward (a) and reverse (b) current flowing in the as-made diodes (first round, black circles) and after 7Be ion implantation and 107-days continuous polarization at -750 V (final, red squares); high voltage reverse current density in as-made diodes, after 7Be ion implantation (blue triangles) and after long-term bias.

Fig. 2. Forward (a) and reverse (b) current flowing in the as-made diodes (first round, black circles) and after 7 B e ion implantation and 107-days continuous polarization at -750 V (final, red squares); high voltage reverse current density in as-made diodes, after 7 B e ion implantation (blue triangles) and after long-term bias.

[picture]

Fig. 3. C-V curves measured (a) in the as-made diodes (first round, black open circles), after 7Be ion implantation (*different device and different implantation sequence, blue triangles), and 107 days continuous polarization at -750 V (final, red squares); calculated doping concentration in the depletion layer width (b).

Fig. 3. C-V curves measured (a) in the as-made diodes (first round, black open circles), after 7 B e ion implantation (*different device and different implantation sequence, blue triangles), and 107 days continuous polarization at -750 V (final, red squares); calculated doping concentration in the depletion layer width (b).

Fig. 3a shows the C-V curves of the diode under study in the final round (black open circles) and at the final stage of the experiment (red circles), together with the C−V curve of a p+/n diode with the same geometry in the as-implanted stage (blue triangles); the latter underwent a different 7Be ion
implantation sequence, achieving a higher 7Be concentration (i.e. 4×1016 cm−3 ), so that the C−V curves of the implanted diodes are not directly comparable. Nevertheless, it is apparent that the capacitance undergoes a decrease after the 7Be ion implantation process. Fig 3b shows the doping profile in the depletion region calculated from the C−V curves. The region probed by the measurement is expected to correspond to a depth comprised between 1.5μ m and 3.5μ m below the sample surface, under the hypothesis of an Al implant tail as long as 1μ m. The first round of measurements yields doping values in the as-grown diodes close to the nominal concentration. The apparent donor profile at the final stage shows a decrease close to the junction, that tends to approach the nominal value while probing deeper inside the space-charge region. It is worth to remark that the quantitative analysis of the C-V curve of the as-implanted diodes was carried out by considering the whole diode area, whereas the 7Be ion implantation is restricted to a selected portion of the diode area. Consequently, the reported concentration has only a qualitative validity. Since the location featuring dopant deactivation is shallower than the 7Be projected range, the observed capacitance decrease is not related either with ion implantation damage induced by nuclear scattering at the 7Be projected range, nor to compensation by 7Be. More likely, it can be attributed to the deactivation occurring close to the junction, where the Al implant tail results in lighter net doping. In this region, even a small amount of irradiation defects can induce a non-negligible capacitance decrease. Indeed, this phenomenon was observed in particle- [5, 6] and light-ion [7] irradiated 4H-SiC detectors.

These considerations show that the actual electric field acting on 7Be remains stable and close to its expected value, as i) the capacitance variation occurs after 7Be ion implantation; ii) the calculated epitaxial layer doping levels in the 7 Be region do not show any dramatic change between the first round of measurements and the final stage.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

We reported the design, fabrication, and electrical characterization of 4H−SiCp+/n diodes suitable to provide a high electric field that can induce Stark effect in 7Be atoms implanted in the space charge region. One diode with the best rectifying behaviour at 900 V reverse bias was chosen for the final experiment. I-V measurements showed a single slope forward current with low recombination and a low reverse leakage with a principle of breakdown at 900 V with a current of 3 nA . Such behaviour ensured the possibility of polarizing the device at 750 V thus achieving an electric field of about (1.3±0.2)MV/cm in the region were 7Be will be implanted. After 7Be ion-implantation and a continuous reverse bias at 750 V for 107 days, the repeated I-V and C-V measurements showed that the electrical properties of the device weren't changed substantially. A slight increase in carrier recombination was seen under forward bias, while under reverse bias we observed a higher generation current due to defects left by 7Be ion-implantation. The breakdown voltage didn't visibly lower and since C−V measurements demonstrated a drop in the doping concentration close to the junction but reducing while entering deeper in the space-charge region, it can be affirmed that the actual electric field acting on 7Be remains close to its expected value. This proofs the suitability of 4H−SiC diodes as host material to probe the Stark effect possibly affecting 7Be.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

This work was supported by the Italian Ministry of Research under the PRIN ASBeST Contract No. 2020WN3PBE_003. The authors are grateful to the personnel of ISMN clean room for assistance in process design and execution: Michele Bellettato, Filippo Bonafè, Fabrizio Tamarri, Michele Sanmartin.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.69.pdf

C. Santonastaso et al., Precise measurement of the 7Be electron capture decay half-life in silicon carbide, J. Phys. G: Nucl. Part. Phys. 52 (2025) 035101. DOI: 10.1088/13616471/ad98ac.

J. T. Emery, Perturbation of Nuclear Decay Rates, Annu. Rev. Nucl. Part. Sci. 22 (1972) 165202. DOI: 10.1146/annurev.ns.22.120172.001121.

P. Hazdra, J. Vobecký, Radiation Defects Created in n-Type 4H-SiC by Electron Irradiation in the Energy Range of , Phys Stat. Solidi A 216 (2019) 1900312. DOI: pssa. 201900312.

P. Hazdra; P. Smrkovský; J. Vobecký; A. Mihaila, Radiation Resistance of High-Voltage Silicon and 4H-SiC Power p-i-n Diodes, IEEE TED 68 (2021) 202-207. DOI: 10.1109/TED.2020.3038713.

J.M. Rafí, G. Pellegrini, P. Godignon, S. Otero Ugobono, G. Rius, I. Tsunoda, M. Yoneoka, K. Takakura, G. Kramberger, M. Moll, Electron, Neutron, and Proton Irradiation Effects on SiC Radiation Detectors, IEEE TRANSACTIONS ON NUCLEAR SCIENCE 67 (2020) 2481. DOI: 10.1109/TNS.2020.3029730.

R.L. Gao, X. Du, W.Y. Ma, B. Sun, J.L. Ruan, X. Ouyang, H. Li, L. Chen, L.Y. Liu, X.P. Ouyang, Radiation tolerance analysis of PIN diode detectors for neutron Irradiation, Sensors and Actuators A 333 (2022) 113241. DOI: 10.1016/j.sna.2021.113241.

D. Pellegrino, L. Calcagno, M. Zimbone, S. Di Franco, A. Sciuto, Correlation between Defects and Electrical Performances of Ion-Irradiated 4H-SiC p-n Junctions, Materials 14 (2021) 1966. DOI: .

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Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 75-79

doi: 10.4028/p-9L9dhm

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-22

Accepted:
2026-02-26

Online:
2026-05-19

Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

Shuiyou Zheng 1,a, Xingjun Luo 2, b and Huaxing Jiang 1,c,*

1 School of Microelectronics, South China University of Technology, Guangzhou, China

2 South China Normal University, Guangzhou, China

a  miwater_friend@mail.scut.edu.cn, b  luoxingjun@m.scnu.edu.cn, c hxjiang@scut.edu.cn;

*corresponding author

Keywords: SiC, Junction Termination Extension, Channeling Implantation, Breakdown Voltage, Process Window.

Abstract

This work reports enhanced high-voltage blocking capability and an enlarged process window for junction termination extension (JTE) in SiC power devices using a hybrid random and channeling implantation for p-type doping (Al), compared with conventional random-only implantation. A three-step hybrid implantation process has been developed to replace a nine-step random implantation, achieving a similar doping profile and equivalent breakdown voltage in the JTE while significantly increasing fabrication productivity and reducing cost. Moreover, TCAD studies reveal that when using the same number of steps and ion energies as the conventional random implantation method, the JTE realized by the channeling-incorporated hybrid approach enables an increased breakdown voltage and a widened dose window in SiC devices. This is attributed to a deeper Al distribution with a lower average concentration, which effectively alleviates electric field crowding.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

The JTE structure is widely employed in SiC power devices to enhance off-state performance and reliability, but its effectiveness critically depends on implantation dose and depth [1,2]. To avoid sharp peaks in the electric field at both the main junction and the edge of the JTE, a deep and uniform dopant profile with a relatively low doping concentration is preferred for the JTE design. However, achieving this with conventional random-only implantation requires costly and time-consuming highenergy multi-step processes. While channeling implantation has offered great potential for creating a deep doping profile in SiC [3,4], its specific application to JTE structures has been underexplored. In this work, combining experimental investigation with TCAD simulation, we propose a hybrid random and channeling implantation technique for JTE formation. Compared with multi-energy random implantation, this hybrid approach achieves a significantly enhanced breakdown voltage and an enlarged process window.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

All samples in this study were fabricated on 4∘ off-axis 6-inch 4H-SiC substrates. A cross-sectional schematic of the fabricated PiN diode with a single-zone JTE design is illustrated in Fig. 1. The epitaxial layer has a thickness of 12μ m and a doping concentration of 1×1016 cm−3. The key fabrication steps are as follows: The P+anode and JTE region were formed via ion implantation. Specifically, random implantation was performed at an elevated temperature, while channeling implantation was conducted at room temperature. After implantation, all samples underwent hightemperature annealing for dopant activation. Subsequent steps included inter-layer dielectric (ILD) deposition, ohmic contact formation, pad metallization, silicon nitride (SiN) passivation, and polyimide coating.

Three groups of devices were fabricated: the first group (Reference sample, denoted as Ref.) employed a nine-step random implantation process with different energies for each step for the JTE; the second (denoted as Condition A) and third (denoted as Condition B) groups utilized a hybrid scheme consisting of two random implantation steps and one channeling implantation step for the JTE formation. The implantation energy for all groups ranged from 120 keV to 2300 keV . For both Conditions A and B , the energies of the two random implantations were 120 keV and 2300 keV , respectively, while the channeling implantation employed an intermediate energy. The total implantation doses were designed to satisfy Condition A < Ref. < Condition B. The electrical characterization of all fabricated devices was subsequently performed using a Keysight B1505A power device analyzer.

[picture]

Fig. 1. Cross-sectional schematic of the fabricated SiC diodes with JTE in this work.

Fig. 1. Cross-sectional schematic of the fabricated SiC diodes with JTE in this work.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

The aluminum (Al) distribution in the JTE implantation regions of the three samples was characterized using secondary ion mass spectrometry (SIMS). As shown in Fig. 2, the depth profiles of Al under all three implantation conditions exhibit nearly consistent dopant concentration distributions.

[picture]

Fig. 2. Comparison of Al depth profiles of SIMS measurement in the JTE structures using random and hybrid implantation.

Fig. 2. Comparison of Al depth profiles of SIMS measurement in the JTE structures using random and hybrid implantation.

Notably, electrical characterization results (Fig. 3(a)) demonstrate that diodes with the JTE structure fabricated using the hybrid implantation scheme exhibit competitive breakdown voltages and
comparable leakage currents to those of the reference. The average breakdown voltages for Conditions A and B, calculated from 18 devices per group, are 1643 V and 1717 V , respectively, both surpassing the reference value of 1630 V (Fig. 3(b)). These results confirm that the incorporation of channeling implantation significantly simplifies the JTE fabrication process without compromising the electrical performance.

[picture]

Fig. 3. (a) Measured reverse I-V characteristics for SiC diodes with different JTE implantation conditions; (b) Breakdown voltage distribution of SiC diodes ( 18 devices per group). Hollow squares denote the mean values, labeled with their respective average voltages of 1630 V,1643 V, and 1717 V .

Fig. 3. (a) Measured reverse I-V characteristics for SiC diodes with different JTE implantation conditions; (b) Breakdown voltage distribution of SiC diodes ( 18 devices per group). Hollow squares denote the mean values, labeled with their respective average voltages of 1630 V , 1643 V , and 1717 V .

Channeling implantation can produce a deep and uniform box-like profile [5], which aligns well with the deep and homogeneous doping distribution required for an effective JTE structure. To further investigate the potential of channeling implantation in optimizing JTE performance, a comparative TCAD simulation study was performed using the device structure shown in Fig. 1. Both implantation schemes maintain the same total dose and implantation energy, with detailed parameters summarized in the table inserted in Fig. 4. In the hybrid scheme, channeling implantation was applied at 370 keV , while random implantation was used at other energies. As illustrated in Fig. 4, despite the same total dose and implantation energy, the hybrid implantation scheme results in a much deeper profile with a lower Al concentration compared to the random implantation approach.

[picture]

Fig. 4. Comparison of simulated Al doping profiles under random-only and hybrid implantation conditions with the same number of implantation steps, energy values, and total dose, along with a detailed summary of the implantation schemes.

Fig. 4. Comparison of simulated Al doping profiles under random-only and hybrid implantation conditions with the same number of implantation steps, energy values, and total dose, along with a detailed summary of the implantation schemes.

Fig. 5 presents the simulated reverse breakdown voltage characteristics of the diodes with JTE using the aforementioned two implantation schemes. The hybrid implantation scheme achieves a much higher breakdown voltage in the device along with a wider dose window for the JTE. This improvement can be attributed to its distinctive dopant distribution characteristics: on the one hand, the deeper implantation profile effectively mitigates electric field crowding at the main junction edge (shown in Fig. 6(a)), thereby increasing the breakdown voltage and extending the lower end of the dose window; on the other hand, under the same total dose, the hybrid scheme yields a lower peak Al concentration, which helps suppress the electric field at the JTE periphery-as validated by the twodimensional electric field distribution shown in Fig. 6(b). As the dose increases, the random implantation scheme suffers from a rapid decrease in breakdown voltage due to a sharp rise in the JTE peripheral electric field. In contrast, the hybrid implantation maintains superior breakdown performance owing to its improved field distribution, thereby extending the upper end of the dose window. In summary, the hybrid implantation scheme facilitates enhanced breakdown voltage and broader process tolerance by producing a deeper and uniform dopant distribution with a low peak concentration.

[picture]

Fig. 5. Simulated results of breakdown voltage as a function of JTE dose in SiC p-n diodes with random and hybrid implantation.

Fig. 5. Simulated results of breakdown voltage as a function of JTE dose in SiC p-n diodes with random and hybrid implantation.

[picture]

Fig. 6. Simulated electric field distributions at 1.2 kV reverse bias in diodes with JTE formed by random-only and hybrid implantation: (a) near the main junction edge, and (b) near the JTE edge.

Fig. 6. Simulated electric field distributions at 1.2 kV reverse bias in diodes with JTE formed by random-only and hybrid implantation: (a) near the main junction edge, and (b) near the JTE edge.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

This study systematically investigates the impact of hybrid implantation technology on the reverse blocking capability of the junction termination extension in 4H−SiC power devices. The proposed approach was thoroughly validated through experimental measurements and TCAD simulations. The results demonstrate that, compared to conventional random-only implantation, the hybrid implantation scheme offers two key advantages: first, with the same maximum implantation energy, it achieves a higher breakdown voltage and a wider dose window; second, in deep JTE applications, the hybrid scheme significantly simplifies the implantation process without degrading the breakdown voltage, thereby effectively reducing manufacturing costs. These findings confirm the potential of hybrid implantation technology to enhance both the electrical performance and cost effectiveness of SiC power devices, providing a reliable and efficient approach for the design of high-performance JTE structures.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

This work was financially supported in part by Guangzhou Municipal Science and Technology Bureau, China under grant 2025A04J5383 and in part by Guangdong Basic and Applied Basic Research Foundation, China under grant 2023A1515011054.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.75.pdf

N. Yun and W. Sung, "Detailed analysis on determining effective dose for various JTE-based edge terminations utilized on 4H−SiC power devices", IEEE Transactions on Electron Devices. 69, 3826 (2022).

B.J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

R. Wada, T. Nagayama, N. Tokoro, T. Kuroi, H. Das, S. Sunkari, and J. Justice, "The exceptional advantages of channeling implantation into to make abrupt deep profiles", Japanese Journal of Applied Physics, 61, SC1033 (2022).

D. Kim, S. de Boer, J. Lynch, S. Jang, A. Morgan, and W. Sung, "Enhancing 1.2 kV 4H-SiC MOSFET Performance and Ruggedness Through Deep P-Well Technology", IEEE International Electron Devices Meeting, p. 1-4 (2024).

Scholze, A. V. Suvorov, D. J. Lichtenwalner, S. Rogers, H. Dixit, and S. H. Ryu, "Calibration of Aluminum Ion Implantation Monte-Carlo Model for TCAD Simulations in ", Solid State Phenomena, 359, 47-51 (2024).

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1191, pp 81-88

doi: 10.4028/p-9BUJBo

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-15

Accepted:
2026-02-26

Online:
2026-05-19

Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

Dinuth C. Y. B. Yapa Mudiyanselage 1,a*, Skylar deBoer 1, b, Stephen A. Mancini 1,c, Justin Lynch 2, d, Seung Yup Jang 2,e, Adam J. Morgan 2,f, Woongje Sung 1,g

¹College of Nanotechnology, Science, and Engineering, University at Albany, State University of New York, Albany, New York, USA

2 NoMIS Power Corporation, Albany, New York, USA

a* dyapamudiyanselage@albany.edu, b sdeboer@albany.edu, c smancini@albany.edu, djustin.lynch@nomispower.com, e  seungyup.jang@nomispower.com, f adam.morgan@nomispower.com, 9 wsung@albany.edu

Keywords: 4 H -SiC MOSFET, N+ source, ion implantation depth, contact resistance, and lateral ion straggle.

Abstract

The heavily doped N+ source region in 4H−SiC MOSFETs is a critical design parameter, as its depth and the profile strongly influence contact resistivity and conduction efficiency. This work investigates the impact of varying N+ implantation depth on the electrical performances of 1.2 kV MOSFETs in both Nominal (linear cell) and Hexagonal (HEXFET) architectures. By varying implantation energy at a fixed dose, three junction depths were obtained: 0.22μ m (shallow), 0.24μ m (moderate), and 0.27μ m (deep). Transfer Length Method (TLM) measurements revealed a significant reduction in source contact resistivity with increasing depth, from 3.91×10−5Ω· cm2 (shallow) to 1.22×10−6Ω· cm2 (deep). For Nominal MOSFET design, electrical measurements confirmed a corresponding decrease in specific on-resistance ( Ron,sp ), from 3.05 to 2.89 mΩ· cm2. However, deeper implants introduced greater lateral straggle, shortening the effective channel length and reducing the threshold voltage ( Vth  ) from 2.25 V to 1.96 V . The channel barrier potential lowering associated with lateral straggle increased leakage current in the blocking mode, resulting in reduced breakdown voltage (BV). For Nominal MOSFETs, BV decreased from 1610 V in the shallow split to 1470 V in the deep split, while HEXFETs exhibited sharper BV degradation due to their higher channel density. To address this limitation, optimized JFET doping was introduced, restoring the BV of the deep split to 1560 V in the Nominal architecture. These results demonstrate that although increased N+ depth improves conduction by lowering contact resistance, careful co-optimization with P-well and JFET design is necessary to suppress high leakage current during blocking mode.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

4H-SiC has emerged as the leading wide bandgap semiconductor for advanced power electronics, offering a wide bandgap of 3.26 eV , a high critical electric field of approximately 3 MV/cm, and excellent thermal conductivity. These material advantages enable MOSFETs with significantly lower conduction and switching losses compared to silicon, while also supporting high temperature and high frequency operation. Today, 4 H -SiC MOSFETs are used in a broad range of automotive, industrial, and renewable energy applications, with 1.2 kV devices serving as a key voltage class for converters, motor drives, and charging systems [1-3]. To further develop these applications toward higher efficiency, it is essential to pursue an optimal and area efficient design. A primary strategy involves reducing conduction losses within a given area, commonly expressed as the specific on-resistance ( Ron,sp ). The Ron,sp of a MOSFET originates from several components, including channel resistance, JFET region resistance, drift layer resistance, and contact resistance. While each constituent can be individually optimized to lower Ron,sp, careful consideration is necessary since these parameters are interdependent and often governed by trade-off relationships [4].

The heavily doped N+ source region plays an important role in forming a low resistance ohmic contact to the source electrode. Prior studies have shown that optimizing the implantation profile and dimensions of the N+ source can reduce the overall resistance in 4H−SiC power devices [5,6]. The depth of the N+ source can be considered as an important design parameter. From a fundamental standpoint, electrical resistance is inversely proportional to the effective cross-sectional area available for current flow. Extending the N+ junction deeper into the semiconductor increases the effective current carrying cross-section beneath the source contact, which mitigates current crowding near the surface and lowers the overall contact resistance. Consequently, a deeper N+ source enhances carrier injection by widening the conduction path, thereby directly contributing to the reduction of Ron,sp. To create a deeper N+ profile, a higher ion implantation energy is used. However, by employing a higher implantation energy, the lateral straggle of the implanted region increases [7]. Although this has been shown for other implantations, the effects on the N+ source region have yet to be studied in sufficient detail. Therefore, this study undertakes a comprehensive evaluation of N+ implantation depth and its implications on electrical performance of 1.2 kV 4 H -SiC MOSFETs.

In this study, 1.2kV4H−SiC MOSFETs were fabricated with three distinct N+ junction depths by varying the nitrogen ion implantation energy. Electrical characterization included Transfer Length Method (TLM) measurements to extract contact resistivity, as well as static characteristics measurements to assess conduction and blocking behaviors. Complementary TCAD simulations and SEM cross-sectional imaging were employed to validate the physical junction depths and to analyze the influence of lateral straggle on channel potential. Strategies such as JFET optimization are further explored with deep N+ split as a means of reducing the leakage current during the blocking mode.

Design and Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

Three 4H−SiC wafers were employed for this study, incorporating both linear (Nominal) and hexagonal (HEXFET) device layouts, as shown in Fig. 1(a) and Fig. 1(b). The fabrication sequence included ion implantations to form the JFET, P-well, N+ source, P+ body, and Junction Termination Extension (JTE) regions, followed by a high-temperature activation anneal to electrically activate dopants and repair implantation induced lattice damage. All implantation parameters and subsequent process steps were kept identical across the wafers, with the only variation being the N+ source implantation depth, adjusted by implant energy to achieve shallow, moderate, and deep N+ junction profiles. Here, Fig. 2(a) shows the TCAD simulated cross section of the device structures with three N+ source depths, while Fig. 2(b) depicts the corresponding SEM cross sections from the fabricated devices with N+ split.

[picture]

Fig. 1. Top-view of the cell layout for (a) Nominal MOSFET and (b) HEXFET device.

Fig. 1. Top-view of the cell layout for (a) Nominal MOSFET and (b) HEXFET device.

[picture]

Fig. 2. (a) TCAD simulated, and (b) SEM cross-sections of shallow, moderate and deep N+ configurations. Depths: Shallow - 0.22μ m, Moderate −0.24μ m, and Deep - 0.27μ m.

Fig. 2. (a) TCAD simulated, and (b) SEM cross-sections of shallow, moderate and deep N+ configurations. Depths: Shallow - 0.22 μ m , Moderate − 0.24 μ m , and Deep - 0.27 μ m .

Lower implant energies yielded shallower N+ junction depths, whereas higher energies yielded progressively deeper profiles. The N+ Implant doses remained the same for all 3 wafers. Following the thermally grown gate oxide, polysilicon was deposited and patterned, after which an interlayer dielectric (ILD) was deposited. Contact etching was then performed. Nickel was subsequently deposited and annealed to form low resistance ohmic contacts through nickel silicidation. This was followed by metal deposition for interconnection, and finally a passivation layer was deposited and patterned to complete the device fabrication. The same set of photomasks was used for all three wafers, as the only variation in this study was the N+ implantation energy. The fabrication process was conducted at Clas-SiC wafer fab in United Kingdom.
Fig. 3 (a) shows the TCAD simulated vertical doping profiles extracted along the A-B cutline indicated in Fig. 2(a). The junction depths were approximately 0.22μ m,0.24μ m, and 0.27μ m for the shallow, moderate, and deep implants, respectively. The lateral doping distribution across the channel region (C-D cutline) is shown in Fig. 3(b).

[picture]

Fig. 3. (a) Vertical doping profile (across A-B cutline), and (b) Lateral doping profile (across C-D cutline) of shallow, moderate, and deep N+ source conditions.

Fig. 3. (a) Vertical doping profile (across A-B cutline), and (b) Lateral doping profile (across C-D cutline) of shallow, moderate, and deep N+ source conditions.

[picture]

Fig. 4. Resistance versus pad spacing extracted from TLM structures for shallow, moderate, and deep N+ implant splits.

Fig. 4. Resistance versus pad spacing extracted from TLM structures for shallow, moderate, and deep N+ implant splits.

As the implantation energy (or depth) increases, the lateral spread of the doped region becomes more pronounced, resulting in the N+ junction extending further into the channel region. This progressive extension is clearly observed when comparing the shallow, moderate, and deep implant splits. This will be discussed in detail in the next section.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

TLM measurements were carried out to evaluate the source contact resistivity for each N+ depth condition. Fig. 4 shows the resistance versus pad spacing plots for the shallow, moderate, and deep implant splits. A clear trend is observed, where the extracted contact resistivity decreases significantly with increasing N+ source depth. Specifically, values of 3.91×10−5Ω· cm2,2.40×10−6Ω· cm2, and 1.22×10−6Ω· cm2 were obtained for the shallow, moderate, and deep splits, respectively. The observed improvement is consistent with the expectation that higher implantation energy increases the crosssectional area with the depth, creating a more effective current carrying cross-section beneath the contact. This enhancement ultimately contributes to the reduction of the overall device resistance.

Figure 5(a) shows the trade-off relationship between Ron,sp  and Vth  for Nominal and HEXFET architectures under different N+ depths. Here, Ron,sp was extracted at drain to source current (Ids)=15 A and gate to source voltage (Vgs)=20 V. For Nominal devices, Ron,sp decreased from 3.05 mΩ· cm2 (shallow) to 2.96 mΩ· cm2 (moderate) and further to 2.89 mΩ· cm2 (deep), corresponding to reductions of 3.0% and 5.3% relative to the shallow condition. For HEXFET devices, Ron,sp decreases from 2.71 mΩ·cm2 (shallow) to 2.63 mΩ· cm2 (moderate) and 2.52 mΩ· cm2 (deep), representing 3.0% and 7.0% reductions, respectively. The greater improvement in HEXFETs reflects their higher channel density compared to that of the nominal design. These results clearly demonstrate that greater N+ junction depth plays a decisive role in lowering Ron,sp.

Similarly, a consistent downward trend in threshold voltage is observed with increasing depth. Here, Vth  was extracted at drain to source current (Ids)=10 mA while sweeping Vgs=Vds. For Nominal devices, Vth  decreases from 2.25 V (shallow) to 2.10 V (moderate) and 1.96 V (deep), representing reductions of 6.7% and 12.9%, respectively. For HEXFET devices, Vth  shifts from 2.20 V (shallow) to 2.03 V (moderate) and 1.88 V (deep), corresponding to reductions of 7.7% and 14.5%. This behavior is attributed to the extension of the N+ junction toward the channel region with increasing depth, which effectively shortens the channel and reduces the required gate bias to initiate conduction through the channel. The extension of N+ happens due to a phenomenon called lateral straggle. Lateral straggle in ion implantation refers to the sideways spread of implanted ions as they penetrate
into the semiconductor. During implantation, ions undergo multiple collisions with lattice atoms, which causes their trajectories to deviate from the vertical direction. As a result, the dopant distribution extends laterally in addition to its intended vertical depth profile. In this case, the phenomenon causes the N+ source region to extend toward the channel as implant energy increases, as shown in Fig. 3(b). This lateral extension shortens the effective channel length and lowers the effective acceptor concentration near the N+ end of the channel region, which reduces the Vth .

Figure 5(b) shows the relationship between breakdown voltage (BV) and threshold voltage ( Vth  ) for the N+ depth splits. A clear reduction in BV is observed as the N+ junction depth increases. Here, BV was extracted at Ids=100μ A and Vgs=0 V. For Nominal devices, BV decreased from 1610 V in the shallow split to 1470 V in the deep split. In HEXFET devices, the degradation is more pronounced, with BV dropping from 1560 V to 1015 V . Here in both the device types, the BV was dictated by the increased leakage current rather than avalanche breakdown. This behavior is strongly correlated with the reduction in Vth  discussed in the previous section, as both parameters are influenced by the lateral straggle. The underlying mechanism is further illustrated in the simulated channel potential distributions shown in Fig. 6.

[picture]

Fig. 5. Trade-off relationship between (a) Ron,spvs.Vth(b)BV vs. Vth of N+ depth split. The cross marks denote the average value of each population. The Ron,sp and BV decrease with N+ depth.

Fig. 5. Trade-off relationship between (a) R o n , s p v s . V t h ( b ) B V vs. V t h of N + depth split. The cross marks denote the average value of each population. The R o n , s p and BV decrease with N+ depth.

[picture]

Fig. 6. Channel potential distribution at Vds=1200 V of the N+ Split. The leakage current increases with barrier lowering in the channel region.

Fig. 6. Channel potential distribution at V d s = 1200 V of the N + Split. The leakage current increases with barrier lowering in the channel region.

[picture]

Fig. 7. TCAD simulated leakage current density during blocking mode operation (at Vds=1200 V ).

Fig. 7. TCAD simulated leakage current density during blocking mode operation (at V d s = 1200 V ).

With deeper implants, the N+ region extends closer to the channel, which reduces the channel potential depth (from 0.89 V to 0.76 V ). This lowering of the channel potential barrier promotes increased leakage current in the off state, thereby limiting the BV of the device. The results highlight the inherent trade-off between conduction and blocking characteristics that arise when employing deeper N+ source implants. Fig. 7 shows TCAD simulated leakage current density during the blocking mode operation (at Vds=1200 V ). Increased leakage with deep N+ can be clearly seen here.

To mitigate the high leakage current observed with the deep N+ condition, another wafer was fabricated with same N+ depth however, the JFET region doping was reduced this time. In this case, the shallowest JFET implant dose was reduced by 55% compared to the baseline condition. All other process parameters were identical between initial deep N+ and the new deep N+ with optimized JFET wafers. Figure 8 compares the deep N+ split before and after this adjustment. For Nominal devices, BV improves from 1470 V to 1560 V , while Vth  increases from 1.96 V to 2.16 V . A slight increase in Ron,sp  is also observed. Average values of each wafer employed in this study are summarized in table 1.The recovery mechanism is as follows: lowering the JFET doping reduces the net donor concentration including at the surface, thereby increasing the net acceptor concentration in the channel region. This shift raises the local channel potential and restores the channel barrier, which suppresses off-state leakage and supports a higher blocking voltage. Further, co-optimization of both p-well and JFET is required to bring the Ron,sp  down to the original value or further down while maintaining the same blocking performance.

[picture]

Fig. 8. Deep N+: BV vs. V th comparison with optimized JFET. V th and BV increase with the reduced JFET doping compared to the original deep N+ condition. Cross denotes the average of the population.

Fig. 8. Deep N+: BV vs. V th comparison with optimized JFET. V th and BV increase with the reduced JFET doping compared to the original deep N+ condition. Cross denotes the average of the population.

Table I. Average electrical characteristics of Nominal MOSFET and HEXFET devices.

Conclusion

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The impact of N+ source implantation depth on the performance of 1.2kV4H−SiC MOSFETs was systematically investigated through a combination of electrical measurements, TCAD simulations, and SEM cross-section validation. TLM structures confirmed that deeper N+ junctions reduce contact resistivity by nearly two orders of magnitude, which directly lowered the source contact contribution to the total device resistance. This reduction translated into measurable improvements in Ron,sp  with Nominal and HEXFET devices exhibiting decreases of approximately 5% and 7%, respectively, when comparing shallow and deep splits. The improvement is attributed to enhanced current spreading beneath the source electrode and a larger effective conduction cross-section provided by deeper implantation. In parallel, threshold voltage exhibited a reduction with increasing implant depth, decreasing from 2.25 V to 1.96 V in Nominal devices. TCAD profiles reveal that the shift originates from the extension of the N+ junction into the channel region, due to lateral straggle which shortens the effective channel length and reduces the effective acceptor concentration near the channel. BV was strongly influenced by deeper N+, decreasing from 1610 V to 1470 V in Nominal devices and from 1560 V to 1015 V in HEXFETs as the junction depth increased. Channel potential distributions confirmed that the extension of the N+ region lowers the channel barrier, which promotes higher leakage and limits blocking capability. To counteract this degradation, the JFET doping was reduced in deep N+ devices, which increased the effective P -well influence in the channel region and restored the channel barrier. This process modification successfully improved BV from 1470 V to 1560 V in Nominal devices, with only a minor increase in Ron,sp and a modest upward shift in Vth. Overall, the results demonstrate that deeper N+ implants are highly effective in reducing contact resistance and Ron,sp, but they introduce fundamental trade-offs in Vth and BV due to dopant redistribution into the channel region. These findings highlight the importance of co-optimizing N+ source depth with Pwell and JFET engineering to balance conduction efficiency with robust blocking capability. Such design strategies are essential for advancing 1.2 kV 4H-SiC MOSFET technology toward higher performance and reliability in next generation power electronic systems.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

This work was supported in part by the Air Force Research Lab (AFRL), U.S. Department of Defense, Wright-Patterson Air Force Base under Contract FA2391-23-C-CB001. The authors gratefully acknowledge Alexander Bialy, Senior SEM Technician at the College of Nanotechnology, Science and Engineering, University at Albany (SUNY), for providing the SEM cross-sections used in this study.

References

The original version of this paper is available on https://www.scientific.net/MSF.1191.81.pdf

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications. Hoboken, NJ, USA: Wiley, 2014.

P. Godignon, J. Biscarrat, M. Tranchesset, R. Lavieville, D. Tournier, P. Brosselard, and J. Montserrat, "Breakdown voltage capability of vertical 4H-SiC power devices," Mater. Sci. Semicond. Process., vol. 178, no. 108347, Apr. 2024.

T. Kimoto, "High-voltage SiC power devices for improved energy efficiency," Proc. Jpn. Acad., Ser. B, vol. 98, no. 4, pp. 161-184, 2022.

D. Kim, N. yun, S. Y. Jang, A. J. Morgan and W. Sung, "An Inclusive Structural Analysis on the Design of 1.2 kV 4 H -SiC Planar MOSFETs," in IEEE Journal of the Electron Devices Society, vol. 9, pp. 804-812, 2021, doi: 10.1109/JEDS.2021.3109605.

N. Yanagida, K. Ishibashi, S. Uchiumi, and T. Inada, "Characterization of n-type layers formed in (11-20) by phosphorus ion implantation," Nuclear Instruments and Methods in Physics Research Section B Beam Interactions With Materials and Atoms, vol. 257, no. 1-2, pp. 203-207, Feb. 2007.

A. Agarwal and B. J. Baliga, "Optimization of linear cell 4H-SiC power JBSFETs: Impact of N+ source contact resistance," Power Electronic Devices and Components, vol. 2, p. 100008, 2022.

J. Müting, V. Bobal, T. N. Sky, L. Vines, and U. Grossner, "Lateral straggling of implanted aluminum in 4H-SiC," Applied Physics Letters, vol. 116, no. 1, art. no. 012101, Jan. 2020, doi: 10.1063/1.5132616.

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Chapter 5: Wafer Processing

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 1-7

doi: 10.4028/p-Xc7FbW

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-20

Accepted:
2026-02-26

Online:
2026-05-21

Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Bixue Li 1,a, Xing Zhang 1, b, Qiu Chen 1,c, Linlin Che 1, d, Jianfei Zhang 1,e, Haoyu Fan 1,f, Xiangang Xu 1, g, Rongkun Wang 1, h*, Xiufang Chen 1,i*

1 State Key Laboratory of Crystal Materials, Institute of Novel Semiconductors, Shandong University, Jinan 250100, China

alibx@mail.sdu.edu.cn, b17731872242 @163.com, c chenqiu0629@sdu.edu.cn, d 202214075@ mail.sdu.edu.cn, e  zjf2531@163.com, f  fanhaoyu2001@163.com, g  xxu@sdu.edu.cn, h wrk@sdu.edu.cn, i cxf@sdu.edu.cn

Keywords: laser slicing, nanoindentation, precision grinding, silicon carbide.

Abstract

With the growing application of wide-bandgap semiconductors such as SiC in power electronics, efficient and low-damage machining of large-diameter, high-quality 4H−SiC wafers has become a critical research priority. This study systematically compares the grinding behavior of the C - and Si-faces of laser-sliced 4H−SiC wafers and reveals the effect of crystallographic anisotropy on tool wear. In the experiments, a picosecond laser was used to induce internal crystal modification, and multiple pairs of 12-inch high-purity semi-insulating crystals and wafers were obtained through ultrasonic separation. These wafers were subsequently ground using #800/#8000 resin-bonded diamond wheels. Material removal and wheel wear were recorded in real time, and the wheel wear ratio (W/M) was adopted as the key evaluation metric. Nanoindentation and white-light interferometry were further employed to characterize the mechanical properties and surface morphology of the two crystal faces. Results show that in both rough and fine grinding, the C-face demonstrates superior material removal performance despite its higher hardness, whereas the Si-face is more prone to wheel degradation. For thin wafers, residual laser focus near the surface further aggravates wheel wear. These findings establish a link between crystallographic anisotropy, laser-modified layer position, and wheel wear behavior, providing an experimental foundation for clarifying the underlying mechanisms and developing face-specific grinding strategies for high-quality SiC wafer fabrication.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

With the rapid development of next-generation power electronics, wide-bandgap semiconductors such as silicon carbide (SiC) have become essential materials for high-performance devices, enabling applications in electric vehicles, renewable energy systems, 5G communications, and aerospace electronics. Among them, 4H−SiC stands out due to its wide bandgap, high critical electric field, superior thermal conductivity, and excellent chemical stability. These properties offer significant advantages under high-power, high-frequency, and high-temperature conditions, positioning 4H−SiC as a promising alternative to conventional silicon-based devices. Consequently, the demand for high-quality, large-diameter SiC wafers has grown rapidly, highlighting the need for efficient and low-damage processing technologies.

Although diamond wire sawing is widely used for SiC wafer preparation, it suffers from excessive kerf loss and low processing efficiency, which increase costs and limit wafer quality [1]. In contrast, laser-induced modification and slicing technologies enable high-precision wafer separation by inducing localized modifications within the crystal through nonlinear absorption [2−7]. Nevertheless, laser-sliced wafers often exhibit kerf marks and heat-affected zones, necessitating subsequent precision grinding. By integrating these two processes, laser slicing not only significantly reduces material loss but also enables low-damage wafer preparation while maintaining high processing efficiency.

However, grinding, as a necessary process for removing the surface damage layer after laser slicing, still faces challenges. The anisotropy of 4H−SiC leads to significant differences in
mechanical responses under different crystallographic orientations. The carbon end ( C -face) and the silicon end (Si-face) differ in hardness, elastic modulus and fracture toughness, which directly affect crack initiation, plastic deformation, dislocation structures and material removal mechanisms. In recent years, several scholars have investigated the material removal mechanisms of 4H−SiC with different orientations [8−10]. Other studies have also reported that crystal orientation influences the wear and micro-chipping of diamond tools. However, these studies have mostly focused on nanoscale or small-scale simulations, and lacks systematic investigations of wafer-scale grinding behavior after laser slicing. At the same time, some studies have primarily focused on surface quality indicators such as roughness and subsurface damage [11], while insufficient attention has been given to the quantitative correlation between grinding wheel wear and crystal orientation. This gap constrains the development of differentiated grinding strategies.

Therefore, a comparative investigation of the grinding behavior between the C -face and Si -face of laser-sliced 4H−SiC wafers is of great importance. Such a study not only enhances the understanding of how crystallographic anisotropy influences tool wear and material removal mechanisms, but also provides an experimental foundation for optimizing face-specific grinding parameters, thereby reducing wheel wear, improving machining efficiency, and extending tool life. In this work, C -face and Si -face wafers prepared by laser slicing are systematically compared in terms of material removal thickness, grinding wheel wear ratio, and surface morphology. The objective is to elucidate face-dependent grinding mechanisms and to offer guidance for the optimized manufacturing of high-quality 4H−SiC wafers.

Experimental Methods

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Sample Preparation.

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A 12 -inch high-purity 4H−SiC single crystal was sliced using a picosecond laser operated at a wavelength of 1030 nm , a pulse width of 15 ps , and a maximum output power of 40 W . During slicing, the crystal was fixed on a five-axis precision motion platform with a ceramic vacuum chuck to ensure stability and positioning accuracy. Laser scanning was performed along a predefined trajectory perpendicular to the (112―0) crystal plane, with a scanning pitch of 200μ m. The target wafer thickness was 700±20μ m. After laser modification, ultrasonic-assisted separation was employed to detach the wafers near the incident surface from the parent crystal, yielding complete thin-sheet structures.

Grinding Experiments.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

The separated crystal-wafer pairs were ground using a grinding machine developed by the China Electronics Technology Group Corporation (CETC). Resin-bonded diamond grinding wheels (ZZSM) with grit sizes of #800 and #8000 were employed for rough and fine grinding, respectively. The overall process flow is illustrated in Figure 1. For grinding wheels of the same grit size, identical procedures were applied, with precise control of grinding depth to remove the laser-modified layer and residual slicing marks. Simultaneously, the material removal thickness and grinding wheel wear were recorded in real time, enabling direct comparison between the C-face and Si-face. To quantitatively evaluate tool degradation, the wheel wear ratio (W/M) was adopted as the primary metric, defined as the ratio of wheel wear to material removal. Both wafer removal thickness and wheel wear were automatically measured by the thinning machine with an accuracy of ±1μ m.

[picture]

Fig. 1. Schematic of laser slicing and subsequent grinding applied to 4H−SiC wafers.

Fig. 1. Schematic of laser slicing and subsequent grinding applied to 4 H − S i C wafers.

Characterization.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

To evaluate the mechanical responses and machining quality of the C -face and Si -face, a KLA nanoindentation system was employed to measure the mechanical properties of polished 4H−SiC samples ( Ra<5 nm ). A three-sided pyramidal Berkovich indenter was used in continuous stiffness measurement mode, and hardness (H) was extracted from the load-displacement curves. Surface topography and morphology were further characterized using a white-light interferometer (Sneox 090, Sensofar).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Nanoindentation Testing.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Multi-point nanoindentation tests were conducted on the C -face and Si -face of a high-purity 4H−SiC sample. The corresponding hardness-displacement into surface curves are presented in Figure 2. As shown, the hardness exhibits a rapid increase during the initial loading stage ( 0−50 nm ), primarily due to surface roughness and residual surface stress [12]. With further indentation (approximately 100−200 nm ), the curves gradually stabilize and enter a plateau region. Statistical analysis within the stable range ( 300−350 nm ) indicates that the average hardness of the C -face is approximately 44.21±0.68GPa, whereas that of the Si-face is approximately 41.34±0.91GPa. These values are consistent with the theoretical hardness of 4H−SiC reported in the literature [13]. A direct comparison confirms that the C -face exhibits higher hardness than the Si -face.

[picture]

Fig. 2. Hardness measurement results: (a) Hardness of the C-face; (b) Hardness of the Si-face.

Fig. 2. Hardness measurement results: (a) Hardness of the C-face; (b) Hardness of the Si-face.

Effect of Crystal Plane Orientation on Wheel Wear Ratio.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

During the rough grinding stage, distinct laser modification marks were observed on both the Cand Si-faces. After rough grinding, both faces gradually transitioned to flat regions, and by the completion of fine grinding, they exhibited uniform and smooth morphologies. Figure 3 presents the surface morphology evolution of the Si -face of a 4H−SiC wafer at different processing stages. Given the similar morphological evolution trends observed on both crystal faces, the Si-face is selected as a representative example to illustrate the typical surface morphology changes of laser-sliced wafers during rough and fine grinding.

As shown in Figure 4, under grinding wheels with different grit sizes, the wheel wear ratio of the C-face was consistently lower than that of the Si-face in both the rough and fine grinding stages, indicating that the Si-face is more susceptible to wheel degradation during grinding. Previous studies have also reported that although the C-face exhibits higher hardness and lower fracture toughness, its higher dislocation density facilitates stress release, thereby resulting in more favorable material removal behavior. In contrast, although the Si-face exhibits a slightly lower hardness than the C-face, its crystallographic orientation may to some extent restrict dislocation activity and weaken stress relaxation through dislocation slip during grinding, thereby promoting local stress accumulation and intermittent brittle removal events [10]. This relatively single-dominant removal mechanism lacks the buffering effect of cooperative deformation modes, causing diamond abrasives and the bond to be continuously subjected to high local mechanical loading and frictional work. As a result, grit micro-crack propagation and bond degradation are accelerated, ultimately leading to an increased wheel wear ratio.

A further comparison between the rough and fine grinding stages reveals that the difference in wear ratio between the two faces is much greater during rough grinding than during fine grinding. This phenomenon arises not only from differences in crystal surface hardness but is also closely
related to the focal position in the laser slicing process. For laser sliced wafers, the laser focus typically resides near the upper wafer surface (Figure 5), making the Si-face more susceptible to grinding-induced wheel wear in subsequent processes, and consequently leading to a significant increase in its wear ratio.

[picture]

Fig. 3. Surface morphologies of the Si -face of 4H−SiC wafers: (a) as-received surface; (b) after grinding with #800 diamond wheel; (c) after fine grinding with #8000 diamond wheel.

Fig. 3. Surface morphologies of the Si -face of 4 H − S i C wafers: (a) as-received surface; (b) after grinding with #800 diamond wheel; (c) after fine grinding with #8000 diamond wheel.

[picture]

Fig. 4. Comparison of grinding performance between the C -face and Si -face:
(a) material removal thickness, wheel wear, and wheel wear ratio during #800 rough grinding;
(b) material removal thickness, wheel wear, and wheel wear ratio during #8000 fine grinding.
The triangular symbols ( A ) and error bars represent the wheel wear ratio (W/M), defined as the ratio of wheel wear to material removal.

Fig. 4. Comparison of grinding performance between the C -face and Si -face: (a) material removal thickness, wheel wear, and wheel wear ratio during #800 rough grinding; (b) material removal thickness, wheel wear, and wheel wear ratio during #8000 fine grinding. The triangular symbols ( A ) and error bars represent the wheel wear ratio (W/M), defined as the ratio of wheel wear to material removal.

[picture]

Fig. 5. Cross-sectional morphology of the 4H−SiC wafer after laser modification.

Fig. 5. Cross-sectional morphology of the 4 H − S i C wafer after laser modification.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

This study systematically compares the grinding behavior of the C - and Si -faces in laser-sliced 4H−SiC wafers. The results reveal pronounced differences in material removal and wheel wear. Under identical grinding conditions, the Si-face exhibits a higher wheel wear ratio. This behavior is closely related to the intrinsic anisotropy of 4H−SiC : the C -face possesses higher hardness and distinct fracture characteristics, while its higher dislocation density facilitates stress release, thereby reducing tool wear. In contrast, the Si-face displays a relatively single-dominant removal mechanism, which leads to increased wheel wear. Moreover, for thin wafers obtained by laser slicing, the focal position of the laser strongly influences subsequent grinding performance. When the focus remains near the wafer surface, the wear ratio of the Si-face increases significantly.

These findings provide valuable insights for optimizing SiC wafer grinding processes. Future work will integrate nanoindentation experiments with micro-cutting simulations to further elucidate the differences in mechanical response and crack evolution between crystal planes. In addition, the coupling between the laser-modified layer and subsequent grinding will be investigated to better elucidate the removal mechanisms of different crystallographic orientations, ultimately guiding the development of efficient processes for fabricating large-diameter, high-quality 4H−SiC wafers.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

This work was supported by the National Natural Science Foundation of China (Grant No. U23A20569), the National Natural Science Foundation of China (62305189), the Key R&D Program of Shandong Province, China (2022ZLGX02) and Shandong Provincial Natural Science Foundation, China (ZR2022QF129).

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

M. Zou, F. Dou, Review of silicon carbide wafer cutting methods, Superhard Mater. Eng. 34 (2022) 35-41. (in Chinese).

E. Kim, Y. Shimotsuma, M. Sakakura, et al., Ultrashort pulse laser slicing of semiconductor crystal, Proc. Pac. Rim Laser Damage 2016: Opt. Mater. High-Power Lasers 9983 (2016) 4045.

E. Kim, Y. Shimotsuma, M. Sakakura, et al., 4H-SiC wafer slicing by using femtosecond laser double-pulses, Opt. Mater. Express 7 (2017) 2450-2460.

K. Hirata, New laser slicing technology named KABRA process enables high speed and high efficiency SiC slicing, Laser-Based Micro-and Nanoprocessing XII 10520 (2018) 1052003.

M. Swoboda, R. Rieske, C. Beyer, et al., Cold split kerf-free wafering results for doped 4H-SiC boules, Mater. Sci. Forum 963 (2019) 10-13.

Y. Yao, Q. Chen, B. Li, et al., Influence of crystal orientation and incident plane on n-type 4H-SiC wafer slicing by using picosecond laser, Opt. Laser Technol. 182 (2025) 112174.

Q. Chen, Y. Yao, J. Zhang, et al., Effect of nitrogen doping concentration on 4H-SiC laser slicing, J. Am. Ceram. Soc. (2025) e20555.

Z. Tian, X. Chen, X. Xu, Molecular dynamics simulation of material removal mechanism during scratching of 4H-SiC and 6H-SiC, Extreme Manuf. 2 (2020) 045104. (in Chinese).

K. Tang, W. Ou, C. Mao, et al., Material removal characteristics of single-crystal 4H-SiC based on varied-load nanoscratch tests, Chin. J. Mech. Eng. 36 (2023) 111.

H. Wang, Z. Dong, R. Kang, et al., Surface characteristics and material removal mechanisms during nanogrinding on C -face and Si -face of 4 H -SiC crystals: Experimental and molecular dynamics insights, Appl. Surf. Sci. 665 (2024) 160293.

J. Xia, Q. Yan, J. Pan, et al., Mechanism analysis and process optimization of nanogrinding single-crystal SiC, Mater. Sci. Semicond. Process. 175 (2024) 108218.

J. Cui, X. Yang, Y. Li, et al., Study on ultraprecision cutting characteristics of single-crystal silicon based on nanoindentation and nanoscratch experiments, J. Synth. Cryst. 52 (2023). (in Chinese).

K.E. Prasad, K.T. Ramesh, Hardness and mechanical anisotropy of hexagonal SiC single crystal polytypes, J. Alloys Compd. 770 (2019) 158-165.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 9-17

doi: 10.4028/p-OGH9rS

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-22

Accepted:
2026-02-26

Online:
2026-05-21

Effects of Processing Passes on Laser-Sliced SiC

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Jianfei Zhang 1,a, Bixue Li1, b, Qiu Chen 1,c, Linlin Che 1, d, Xing Zhang 1,e, Haoyu Fan 1,f, Yangyang Jia 1, g, Jiawei Wang 1, h, Yufeng Xue 1,i, Rongkun Wang 1,j*, Xiufang Chen 1,k*

1 State Key Laboratory of Crystal Materials, Institute of Novel Semiconductors, Shandong University, Jinan 250100, China

Keywords: Laser slicing; Crack propagation; Kerf loss.

Abstract

Silicon carbide (SiC), a representative of next-generation wide-bandgap semiconductors, exhibits enormous application potential in fields such as new energy vehicles, aerospace, and photovoltaic power generation. Conventional cutting methods based on diamond wire sawing suffer from high material loss and are prone to causing fractures. In contrast, laser slicing, as a kerf-free processing technology, enables the acquisition of high-quality wafers with minimal material removal. This study systematically investigates the effect of processing cycles on crack propagation and delamination strength during laser slicing of SiC. The experimental results demonstrate that under optimized parameters, an appropriate number of processing cycles can achieve successful wafer separation while maintaining surface integrity, reducing material loss, and lowering delamination strength. The established processing window provides practical guidance for improving SiC slicing quality and holds significant implications for advancing innovative wafer manufacturing technologies in power electronics applications.

a zjf2531@163.com, blibx@mail.sdu.edu.cn, c 724717776@qq.com, d 202214075@ mail.sdu.edu.cn, e17731872242@163.com,f fanhaoyu2001@163.com, g202534175@mail.sdu.edu.cn,h15634035763@163.com, i2904562783@qq.com, j wrk @ sdu.edu.cn, k cxf@sdu.edu.cn

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Silicon carbide ( SiC ), as one of the core representatives of third-generation wide-bandgap semiconductor materials, has become a critical supporting material in strategically emerging fields such as rail transit traction converters, 5G base station radio frequency devices, aerospace extreme environment sensors, and new energy vehicle power modules, thanks to its excellent hightemperature stability, high breakdown electric field strength, high-frequency signal response capability, and high-power bearing characteristics [1,2]. In the manufacturing process of SiC power chips, it is first necessary to grow high-quality single-crystal ingots via techniques such as Physical Vapor Transport (PVT). Subsequently, precision processing procedures including slicing, grinding, and polishing are performed to produce substrates that meet epitaxial requirements. Finally, device fabrication steps such as epitaxial growth, photolithographic patterning, ion implantation, and annealing activation are sequentially completed [3,4]. Throughout the entire process mentioned above, the processing accuracy and quality control of the crystal slicing step are particularly critical-the thickness uniformity, surface roughness, and subsurface damage layer depth of the substrate after slicing directly determine the crystalline quality and interface integrity of the subsequent epitaxial layer, thereby exerting a significant impact on the on-resistance, breakdown voltage, and long-term reliability of the final power device. However, the extremely high hardness (Mohs hardness of 9.29.5 ) and brittle nature of single-crystal SiC pose challenges such as difficult material removal and easy accumulation of processing damage during precision slicing, making it difficult for traditional processing technologies to balance efficiency and quality [5,6]. Currently, the mainstream SiC slicing technologies in industry and academia are mainly divided into two categories: laser slicing and wire saw slicing. Among them, laser slicing, based on the principle of non-contact processing, has significant advantages including high processing efficiency, low kerf loss, high dimensional accuracy, and strong damage controllability, and has become an important development direction for slicing
large-size SiC ingots. The core principle of this technology is as follows: a pulsed laser with a specific wavelength is focused to a preset depth inside the SiC ingot, so that the energy density in the focused area reaches the material damage threshold and a modified layer (e.g., amorphized region, microcrack region) is generated; by designing a high-precision laser scanning path, adjacent modified regions are connected to form a continuous separation surface, weakening the internal bonding force of the ingot; finally, with the assistance of ultrasonic vibration-assisted peeling, mechanical tensile separation, or electrochemical etching, efficient separation of the wafer from the ingot is achieved [7,8].

Continuous technological iterations and mechanism research have driven the rapid development of the field of SiC laser slicing. Kim et al. [9,10] took the lead in focusing ultrafast pulsed lasers with a dual-pulse structure into 4H−SiC crystals, realizing the precise separation of thin wafers; through Raman spectroscopy and high-resolution microscopic characterization, they found that significant structural transformation occurred in the laser-affected region, specifically manifested as the amorphization of 4H−SiC crystals and their decomposition into amorphous silicon and amorphous carbon phases; mechanical tests further confirmed that the tensile force required for wafer separation under the dual-pulse processing method was significantly lower than that under single-pulse processing. Han et al. [11] used a 1064 nm picosecond laser to induce multiphoton-induced microexplosions in 4H−SiC; these micro-explosions confined the micro-explosion layer to the vicinity of the laser beam focus, and due to the generated instantaneous high temperature, 4H−SiC decomposed into amorphous silicon and carbon, and two 4H−SiC wafers with a thickness of 250μ m were successfully prepared. Geng et al. [12] proposed a composite slicing technology combining femtosecond laser irradiation and bandgap-selective photoelectrochemical (PEC) peeling, achieving high-yield (yield >95% ) separation of 4H−SiC wafers. Characterization and analysis via optical absorption spectroscopy, micro-Raman, and photoluminescence (PL) showed that the damage layer induced by femtosecond lasers inside 4H−SiC was mainly composed of amorphous silicon (a-Si) and amorphous carbon (a-C), with its bandgap width reduced to 0.4 eV , which was significantly different from that of intact 4H-SiC (bandgap of 3.26 eV ); using this characteristic, the damage layer could be selectively removed from the intact region of 4H−SiC via bandgap-selective PEC etching, avoiding secondary damage to the wafer surface caused by mechanical separation. Jiang et al. [13] proposed a continuous laser-assisted SiC wafer splitting method based on a picosecond laser-modified layer, showing that the modified layer prepared by picosecond lasers in SiC samples significantly improved laser absorption rate, and the absorption coefficient of the modified SiC samples at 1064 nm was increased by 2720 times. Lv et al. [14] designed orthogonal experiments on ultrasonic-assisted peeling for laser-modified 4H−SiC single crystals, systematically investigating the influence of ultrasonic frequency, vibration time, and ultrasonic power on the bonding force of the modified layer. The results showed that ultrasonic vibration could promote the propagation of microcracks inside the modified layer through cavitation effect, reducing the bonding force between the modified layer and the matrix by 25%−60%. Wang et al. [15] conducted laser cutting experiments on 4H−SiC samples with different surface roughness. The study found that good surface quality could reduce damage to the wafer surface during laser cutting, decrease the occurrence of cleavage, and improve the flatness and uniformity of the modified layer. Chen et al. [16] combined experiments with two-temperature model analysis to explore the influence of different doping concentrations on the laser cutting of n-type 4HSiC; the results showed that an increase in nitrogen doping concentration led to a decrease in resistivity and an increase in laser absorption rate, which in turn affected the crack propagation length and modified line width. By optimizing processing parameters, high-quality laser cutting of SiC wafers with five gradient doping concentrations was successfully achieved. Finally, an 8-inch N-type 4H−SiC wafer was successfully sliced.

Although existing studies on laser slicing of 4H−SiC wafers have achieved breakthroughs in multiple aspects, there is a lack of systematic research on the key variable of laser repeated processing cycles. In actual industrial production, to achieve efficient slicing of large-size 4H−SiC ingots (e.g., 6-8 inches), multiple laser scans are often required to enhance the continuity of the modified layer, thereby reducing the difficulty of subsequent separation; however, the cumulative effect of energy during repeated processing may lead to excessive expansion of the modified layer, causing problems
such as an increase in the depth of longitudinal microcracks and an expansion of the subsurface damage range, which in turn affect the material removal efficiency of subsequent grinding processes and the final quality of the substrate.

Based on this, this study takes semi-insulating 4H-SiC single crystals as the research object. On the basis of fixing the core laser parameters (wavelength of 1030 nm , pulse width of 10 ps ) and optimizing process conditions (C-face incidence, scanning along the [11―00] orientation), experimental groups with 1-9 laser repeated processing cycles were designed. Optical microscopy was used to analyze the influence of processing cycles on crack morphology, and an electronic universal testing machine was employed to measure the change in tensile force required for wafer separation. The study aims to clarify the quantitative relationship between the number of laser repeated processing cycles and the slicing quality of 4H−SiC, reveal the cumulative mechanism of longitudinal damage caused by multiple processing cycles, and avoid discontinuous modified layers and excessively high separation tensile force due to insufficient processing cycles, or excessive damage diffusion caused by excessive processing cycles. Based on the comprehensive evaluation of crack propagation uniformity, separation tensile force stability, and damage controllability, the optimal number of laser repeated processing cycles and supporting process parameters are determined, providing a quantitative basis for reducing longitudinal damage and improving slicing efficiency. The results of this study can not only fill the research gap in the optimization of processing cycles in existing laser slicing technologies but also provide technical guidance with both theoretical value and engineering practicality for the precision processing and advanced manufacturing of 4H−SiC wafers.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

The experimental material used in this study was a 6-inch SiC wafer, which was laboratoryfabricated with a thickness of 700μ m and a surface roughness (Ra) of approximately 1 nm . This wafer was then cut into rectangular cuboids with dimensions of 20 mm×20 mm×700μ m. A schematic diagram of the laser slicing system used in the experiment is shown in Fig.1. The laser cutting parameters were as follows: wavelength λ=1030 nm, pulse width τ=10ps, pulse repetition frequency (PRF) of 100−1000kHz, and scanning speed of 100−400 mm/s. A Liquid Crystal Spatial Light Modulator (LCSLM) was used to accurately compensate and correct the spherical aberration caused by the difference in refractive index between air and 4H−SiC, realizing distortion correction of the laser-focused spot. Under the conditions of a power of 1 W and a step distance of 200μ m, the samples were subjected to complete laser modification with different numbers of cycles ( 1 to 9 cycles). An industrial microscope was used to observe the connection of crack propagation in the top and side views. To further quantify the laser modification effect and slicing feasibility, a mechanical peeling experiment was conducted on the modified samples using an electronic universal testing machine. Both ends of the samples were fixed to the fixtures with high-strength epoxy adhesive, a tensile force was applied at a constant speed, and the peeling force was recorded simultaneously. The cutting quality was evaluated based on the changes in crack propagation and peeling force.

[picture]

Fig. 1. Schematic of laser-slicing system.

Fig. 1. Schematic of laser-slicing system.

Results and Discussion

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Top-View Observation of Crack Propagation.

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The integrity, continuity, and morphological regularity of crack propagation are core indicators for evaluating laser slicing quality, as they directly determine the feasibility of subsequent wafer separation and the flatness of the separation surface. In this study, an industrial inspection microscope was used to conduct top-view observations of 4H−SiC samples after 1−9 laser processing cycles, and the crack propagation morphologies under different processing cycles were obtained; the results are shown in Fig. 2 (a-i). From Fig. 2 (a) (1 processing cycle), clear laser scanning traces can be observed on the sample surface, with an interval of approximately 200μ m between adjacent traces. This interval completely matches the preset scanning step parameter in the experiment, verifying the accuracy of the laser scanning path. Measurements of typical regions in this group of samples revealed that the width of the laser traces was approximately 19.8μ m, and the total crack propagation length was about 65.6μ m. Notably, the cracks between adjacent traces did not form effective connections. This phenomenon is attributed to the limited energy input of a single laser processing cycle, which only generates a local modified layer (mainly composed of amorphized regions and microcracks) near the scanning path. A continuous separation surface is not established between adjacent modified layers, resulting in a relatively high internal bonding force of the wafer and significant difficulty in subsequent separation.

[picture]

Fig. 2. (a)-(i) Top-view optical micrographs corresponding to 1−9 processing passes.

Fig. 2. (a)-(i) Top-view optical micrographs corresponding to 1 − 9 processing passes.

When the number of processing cycles increased to 2−3 (Fig. 2( b−c) ), the cracks induced by adjacent laser traces began to connect with each other, forming a preliminary continuous separation path. However, the crack morphology exhibited partial irregular feather-like branches. This is because during the second and third laser scans, the laser energy caused a stress concentration effect at the tips of the already formed microcracks; while this effect promotes the lateral propagation of cracks, it also triggers local irregular branching. As the number of processing cycles further increased to 4− 6 (Fig. 2 (d-f)), the cumulative effect of laser energy became increasingly prominent. On one hand, multiple scans increased the width of the laser traces and further expanded the range of crack propagation; on the other hand, obvious ablation marks appeared in local areas of the samples. When the number of processing cycles reached 7−9 (Fig. 2 (g-i)), the surface ablation marks deepened further, and significant height differences emerged in some regions. This is because excessive laser energy input not only intensifies crack propagation but also causes stress accumulation inside the modified layer, leading to tiny bulges or depressions in local areas and damaging the surface flatness. To meet the substrate requirements, a thicker damaged layer must be removed through subsequent grinding processes, which increases processing costs and material loss.

Side-View Observation of Cracks and Peeling Force.

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

To further investigate the effect of laser processing cycles on the longitudinal damage of 4 H SiC samples, side-view observations were conducted on the samples after side polishing to analyze the propagation depth of transverse cracks and the distribution of longitudinal damage. Meanwhile, an electronic universal testing machine was used to measure the peeling force of the laser-modified samples, establishing a correlation among "processing cycles-crack morphology-peeling force". As shown in Fig.3, different numbers of processing cycles exhibit a significant regulatory effect on the transverse propagation of cracks and longitudinal damage. When processed only once (Fig. 3 (a)), crack propagation is limited and the cracks are disconnected; the typical spacing between cracks induced by adjacent laser traces is approximately 30.6μ m, and no continuous damage layer is formed.

This result mutually confirms the "disconnected cracks" observation from the top-view analysis. When processed twice (Fig. 3 (b)), the cracks extend further and begin to transition toward a continuous state, though local disconnected regions still exist. When processed 3-4 times (Fig.3 (cd)), the transverse cracks are completely connected, accompanied by slight longitudinal delamination damage. This phenomenon occurs because multiple laser scans increase the thickness of the modified layer; while transverse cracks are connecting, the accumulation of longitudinal stress triggers local delamination. When the number of processing cycles increases to 5−9 (Fig.3 (e-i)), the transverse cracks are already fully and stably connected, but the longitudinal damage intensifies significantly. The core reason for this phenomenon is that under a large number of processing cycles, the modified layer formed by previous laser scans alters the energy absorption and focusing state of subsequent lasers (the refractive index of the modified layer differs from that of intact SiC , leading to the deviation of the laser focus point). This causes excessive energy accumulation in the longitudinal direction, triggering damage diffusion along the depth. Such diffusion not only increases the amount of material to be removed in subsequent grinding but may also reduce the thickness uniformity of the substrate.

[picture]

Fig. 3. (a-i) Cross-sectional crack morphology images corresponding to 1−9 processing passes.

Fig. 3. (a-i) Cross-sectional crack morphology images corresponding to 1 − 9 processing passes.

The variation trend of tensile strength shows a strong correlation with the crack propagation effect (as shown in Fig.4). When processed only once, due to disconnected cracks and high internal bonding force of the wafer, the peeling force required for sample separation is as high as 3.01 MPa . With the increase in processing cycles, the transverse cracks gradually connect, the bonding force weakens progressively, and the peeling force decreases accordingly. When the number of processing cycles reaches 5, the peeling force drops to 0.68 MPa and then stabilizes. This indicates that an appropriate number of processing cycles can not only reduce longitudinal damage but also lower the peeling force during the cutting process.

[picture]

Fig. 4. Trend chart of tensile strength versus number of processing passes.

Fig. 4. Trend chart of tensile strength versus number of processing passes.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

This study systematically investigates the regulatory law of laser processing cycles on the slicing quality of 4H−SiC wafers, with a focus on analyzing the evolutionary characteristics of crack propagation morphology and peeling force. The key findings are as follows: When processed only once, limited by the constraints of energy input, the generated cracks are limited in scope and disconnected from each other. In this case, the internal bonding force of the wafer is not effectively weakened, resulting in a relatively large peeling force. For 2−4 processing cycles, the cumulative effect of laser energy promotes the transverse propagation of cracks and enables their connection; however, there is a risk of longitudinal delamination. When the number of processing cycles reaches 5-9, although the transverse cracks are already fully connected, the longitudinal damage intensifies significantly, which increases cutting loss. The test results of peeling force show a strong correlation with the crack propagation morphology: the peeling force decreases with the increase in processing cycles, and stabilizes when the number of processing cycles reaches 5 . This indicates that an optimal balance is achieved between crack connectivity and damage minimization at this point. An appropriate number of laser processing cycles can reduce longitudinal damage and peeling force during the cutting process, providing practical references for improving the quality of SiC laser slicing and advancing the development of wafer manufacturing technology.

Authorship Contribution Statement

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Jianfei Zhang: Writing - review & editing, Writing - original draft, Validation, Investigation, Conceptualization. Bixue Li: Writing original draft, Validation, Data curation, Conceptualization. Qiu Chen: Data curation, Formal analysis. Linlin Che: Conceptualization, Validation. Xing Zhang: Writing - review & editing, Supervision. Haoyu Fan: Visualization, Formal analysis. Yangyang Jia: Visualization, Formal analysis. Jiawei Wang: Visualization, Formal analysis. Yufeng Xue: Visualization, Formal analysis. Rongkun Wang: Project administration, Methodology. Xiufang Chen:

Writing review & editing, Supervision, Resources, Project administration, Funding acquisition, Conceptualization.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

This work was supported by the National Natural Science Foundation of China (Grant No. U23A20569), the Key R&D Program of Shandong Province, China (2022ZLGX02).

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Zhao J, Ji P, Li Y, et al. Ultrahigh-mobility semiconducting epitaxial graphene on silicon carbide[J]. Nature, 2024, 625(7993): 60-65.

Nakamura D, Gunjishima I, Yamaguchi S, et al. Ultrahigh-quality silicon carbide single crystals[J]. Nature, 2004, 430(7003): 1009-1012.

Eddy C R, Gaskill D K. Silicon Carbide as a Platform for Power Electronics[J]. Science, 2009, 324(5933): 1398-1400.

Chen X, Yang X, Xie X, et al. Research progress of large size SiC single crystal materials and devices[J]. Light: Science & Applications, 2023, 12(1): 28.

Wang G, Sheng D, Yang Y, et al. High-Quality and Wafer-Scale Cubic Silicon Carbide Single Crystals[J]. ENERGY & ENVIRONMENTAL MATERIALS, n/a(n/a): e12678.

Li Y, Zhang Z, Song Q, et al. Surface micromorphology and nanostructures evolution in hybrid laser processes of slicing and polishing single crystal 4H-SiC[J]. Journal of Materials Science & Technology, 2024, 184: 235-244.

Peng Y, Zeng J, Xie X, et al. Laser machining of silicon carbide: current status, applications and challenges[J]. Optics & Laser Technology, 2025, 191: 113376.

Jiang K, Zhang P, Song S, et al. A review of ultra-short pulse laser micromachining of wide bandgap semiconductor materials: SiC and GaN[J]. Materials Science in Semiconductor Processing, 2024, 180: 108559.

Kim E, Shimotsuma Y, Sakakura M, et al. Ultrashort pulse laser slicing of semiconductor crystal[C]//Jitsuno T, Shao J, Rudolph W. Pacific Rim Laser Damage 2016: Optical Materials for High Power Lasers. Yokohama, Japan, 2016: 99831B.

Kim E, Shimotsuma Y, Sakakura M, et al. 4H-SiC wafer slicing by using femtosecond laser double-pulses[J]. Optical Materials Express, 2017, 7(7): 2450.

Shifei Han, Haijuan Yu, Chaojian He, et al. Laser slicing of wafers based on picosecond laser-induced micro-explosion via multiphoton processes[J]. Optics & Laser Technology, 2022, 154: 108323.

Geng W, Shao Q, Pei Y, et al. Slicing of 4H-SiC Wafers Combining Ultrafast Laser Irradiation and Bandgap-Selective Photo-Electrochemical Exfoliation[J]. Advanced Materials Interfaces, 2023, 10(21): 2300200.

Lu Jiang, Zhao S, Han S, et al. CW laser-assisted splitting of SiC wafer based on modified layer by picosecond laser[J]. Optics & Laser Technology, 2024, 174: 110700.

Lv B, Ye L, Zhu X, et al. Ultrasonic-assisted stripping of single-crystal SiC after laser modification[J]. Ceramics International, 2024: S0272884224042081.

Hanwen Wang, Chen Q, Yao Y, et al. Influence of Surface Preprocessing on 4H-SiC Wafer Slicing by Using Ultrafast Laser[J]. Crystals, 2023, 13(1): 15.

Chen Q, Yao Y, Zhang J, et al. Effect of nitrogen doping concentration on laser slicing[J]. Journal of the American Ceramic Society, n/a(n/a): e20555.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 19-24

doi: 10.4028/p-jAm4lU

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-27

Online:
2026-05-21

Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

Takanori Tanaka 1,a*, Kyohei Akiyoshi 1, b, Kazumasa Iwanaga 1,c, Shunta Takahashi 2, d, Hiroshi Watanabe 2,e, Kenichi Hamano 1,f and Akihiko Furukawa 1, g

1 Power Device Works, Mitsubishi Electric Corporation, 1-1-1, Imajyukuhigashi, Nishi-ku, Fukuoka 819-0192, Japan

2 Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki, Hyogo 661-8661, Japan

a Tanaka.Takanori@cb.MitsubishiElectric.co.jp, b Akiyoshi.Kyohei@ea.MitsubishiElectric.co.jp, c  Iwanaga.Kazumasa@aj.MitsubishiElectric.co.jp, d  Takahashi.Shunta@bp.MitsubishiElectric.co.jp,

eWatanabe.Hiroshi@dh.mitsubishielectric.co.jp, f  hamano.kenichi@df.mitsubishielectric.co.jp, g  Furukawa.Akihiko@df.MitsubishiElectric.co.jp

Keywords: SiC wafer, reutilization process, recycling wafer, laser split, bonding technique.

Abstract

We propose a novel SiC wafer recycling process that employs the laser splitting and wafer bonding techniques. The process allows us to attain the recycled SiC wafers suitable for conventional device processes, leading to the reduction of SiC device costs and environmental burdens. Preliminary evaluations were conducted on the key technologies of the process: surface activated bonding and laser splitting for SiC wafers. The bonding interface was confirmed to withstand the stresses encountered during device manufacturing thanks to the recrystallization of the interface layer. The electrical characteristics of MOSFETs thinned using laser splitting showed no significant difference compared to those thinned by conventional grinding. These results demonstrate that the proposed process is a feasible technique that offers a cost-effective and ecofriendly solution for SiC power device production.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

The high cost of SiC wafers is one of the major issues in further promoting the adoption of SiC devices. SiC wafers are frequently thinned through grinding to reduce on-resistance and mitigate thermal stress caused by differences in thermal expansion coefficients within power modules. Reducing the amount of discarded SiC material and, ideally, reusing it in device fabrication is highly desirable. This approach not only helps reduce costs but also minimizes environmental impact. Several potential technologies for reducing wafer costs have been reported [1, 2], but there are still challenges to tackle from both technical and cost perspectives.

We propose a novel SiC wafer reutilization process that employs laser splitting and bonding techniques. The laser splitting technology is progressing markedly today and well-suited for this process. Preliminary experiments have been conducted on wafer bonding and laser splitting, which are key technologies for the proposed wafer reutilization process. In this paper we present the findings and examine the feasibility of the proposed approach.

Proposal of Novel SiC Wafer Reutilization Process

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

A novel SiC wafer reutilization process for device fabrication is proposed. Fig. 1 illustrates the rough sequence of the SiC wafer reutilization process. In this process, a wafer is split into two wafers at a certain thickness after fabricating device structures on its top surface. The wafer with the device structures undergoes usually used wafer processing. Meanwhile, the surface of the split wafer without device structures is polished, cleaned, and then bonded with another split wafer. This results in a recycled wafer with a thickness suitable for device fabrication. After forming device structures on the

[picture]

Fig. 1. Schematic of Novel SiC Wafer Reutilization Process using laser splitting and bonding techniques.

Fig. 1. Schematic of Novel SiC Wafer Reutilization Process using laser splitting and bonding techniques.

bonded wafer, it is split again into two wafers: one with devices and one without devices. The split wafer without devices then repeats the above-mentioned process, and thereby the recycled wafer is fabricated again.

The proposed process is expected to attain several advantages. Firstly, it leads to reduction in costs and material loss, which is crucial for SiC device manufacturing. Specifically, this process increases the chip yield (in this case referring to the number of chips) per initial wafer, thereby drastically reducing the chip cost. Secondly, it eliminates the need for externally procured heterogeneous support wafers, such as poly-SiC wafers, and the recycled wafers are formed entirely from 4H−SiC material. This not only reduces costs but also enhances compatibility with conventional device production processes. Furthermore, it is possible for the sprit wafer with devices to exclude the junction interface, ensuring that there are no negative effects on device characteristics resulting from including the bonding interface such as increase in resistance.

The wafer bonding technique and the laser splitting technique are key technologies in this wafer reutilization process. To verify the feasibility of this wafer reutilization process, preliminary experiments were conducted on these two techniques.

Investigation of Wafer Bonding Technique

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

We investigated the bonding technique for split SiC wafers and the feasibility to split the bonded wafer at a designed thickness. The SiC wafer bonding method is schematically shown in Fig. 2. Two 6-inch 4∘ off 4H-SiC wafers were thinned to 150μ m by grinding, and their surfaces for bonding (both C - and Si -face) were flattened using a CMP method. Subsequently, the two wafers were bonded at room temperature using the surface activated bonding method [3].

The bonded wafer fabricated using above method were implanted with Al ions at a doping concentration of 2×1015 cm−2 across the entire wafer surface and subsequently annealed at 1750∘C to electrically activate the Al. Additionally, another bonded wafer was divided again by the laser

[picture]

Fig. 2. Fabrication method of bonded wafers.

Fig. 2. Fabrication method of bonded wafers.

splitting technique after epitaxial growth. The evaluation was conducted through optical microscope observation, warpage measurement, and cross-sectional TEM analysis.

Fig. 3(a) shows appearance of the wafer immediately after wafer bonding. No significant differences in appearance between the bonded and normal wafers are noted except for a few small voids ( 1−5 mm in diameter) caused by particles at the bonding interface. Photos of the whole wafers after the Al implantation and the thermal annealing are shown in Fig. 3(b) and (c), respectively. Change of color due to Al implantation is observed in Fig. 3(b), but the color returns to the original color of as-bonded wafers after the thermal annealing. No cracks, chips or peelings originating from voids or wafer edges are observed after the bonding and subsequent Al implantation and the annealing processes. Despite the strong stress imposed on the wafer by high dose ion implantation and high temperature annealing, the bonded wafer shows no fatal changes.

The bonding interfaces immediately after bonding and after the annealing were observed in detail using the cross-sectional TEM. Corresponding TEM images are shown in Fig. 4(a) and (b), respectively. In the TEM image of the as-bonded wafer (Fig. 4(a)), an interface layer is clearly observed between the upper and lower wafers, and it is confirmed from the magnified image that this layer exhibits an amorphous structure. In contrast, at the bonding interface after the thermal annealing, the distinct amorphous layer disappears, indicating that solid phase reaction has occurred and yielded polycrystals at the interface during the high temperature annealing process. Since the polycrystals are strongly bonded to each other, the bonded wafers do not break or peel and are expected to withstand harsh wafer processes.

We investigated warpage of the bonded wafer. Fig. 5 shows the relationship between the SORI and the wafer thickness for the bonded and standard wafers. SORI of both types of wafers decreases with increasing the wafer thickness. It is found that they are on the curve calculated using Stoney's equation. Additionally, it has been confirmed that the SORI does not change significantly even after implantation and annealing. This indicates that we need no special care to handle the bonded wafers.

[picture]

Fig. 3. Appearances of the wafer (a) after bonding, (b) Al implantation at a doping concentration of 2×1015 cm−2, and (c) thermal annealing at 1750∘C.

Fig. 3. Appearances of the wafer (a) after bonding, (b) Al implantation at a doping concentration of 2 × 10 15 c m − 2 , and (c) thermal annealing at 1750 ∘ C .

[picture]

Fig. 4. Cross-sectional TEM images of the bonding interface (a) immediately after bonding, and (b) after thermal annealing.

Fig. 4. Cross-sectional TEM images of the bonding interface (a) immediately after bonding, and (b) after thermal annealing.

[picture]

Fig. 5. Wafer thickness dependence of SORI for standard wafers and bonded wafers.

Fig. 5. Wafer thickness dependence of SORI for standard wafers and bonded wafers.

[picture]

Fig. 6. Cross-sectional structure and splitting position of bonded wafers.

Fig. 6. Cross-sectional structure and splitting position of bonded wafers.

[picture]

Fig. 7. Images of the bonded wafer (a) before laser splitting, and (b) the top side without bonding interface and (c) the bottom side with bonding interface after laser splitting.

Fig. 7. Images of the bonded wafer (a) before laser splitting, and (b) the top side without bonding interface and (c) the bottom side with bonding interface after laser splitting.

Next, feasibility of re-splitting the bonded wafer using laser splitting technique [4, 5] was investigated. Cross-sectional structure and splitting position of the bonded wafer is illustrated in Fig.
6. After SiC epitaxial growth on top side of the bonded wafer, a protective tape was put onto it. The splitting was set at the position between the bonding interface and the epitaxial layer. Since the laser beam scan is performed from the backside of the wafer, the laser light focuses beyond the bonding interface.

Fig. 7 shows surface images of bonded wafer before laser splitting (a) and after laser splitting (b, c). The bonding interface exists in the bottom side wafer. No noticeable cracks or chips are observed in the wafer after splitting, indicating that the bonding interface does not negatively affect the laser splitting. This result shows that the bonded wafer can be re-split with the designed thickness irrespective of the position of bonding interface.

Influence of Laser Splitting Process on MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

The influences of laser splitting on characteristics of SiC power devices has been investigated to verify the feasibility of applying the laser splitting technique to device fabrication. SiC MOSFETs were fabricated using the laser splitting technique for the thinning process.

The fabrication procedure for the SiC MOSFETs is illustrated in Fig. 8. An epitaxial layer was grown on a standard 6 -inch 4H−SiC substrate with a 4∘ off-cut angle, and 1200 V SiC MOSFET structures were subsequently fabricated on this epitaxial layer. This wafer was then divided at a depth of 180μ m from the top surface by precisely controlling the laser focus during the laser splitting

[picture]

Fig. 8. Fabrication procedure.

Fig. 8. Fabrication procedure.

[picture]

Fig. 10. Comparison of main electrical characteristics ((a) Igss, (b) Vth, (c) Idss, and (d) Vds(ON)) of MOSFETs fabricated using laser splitting and conventional grinding process.

Fig. 10. Comparison of main electrical characteristics ((a) Igss, (b) Vth, (c) Idss, and (d) Vds(ON)) of MOSFETs fabricated using laser splitting and conventional grinding process.

process. The rough splitting surfaces were subsequently ground to achieve a final thickness of 100 μm. Finally, a backside metal electrode was formed, and the wafer was diced into chips. Image of the wafers observed from the top side after laser splitting are shown in Fig. 9. No damage is visible in the image.

The main electrical characteristics of MOSFETs, including gate leakage current (Igss), threshold voltage ( Vth  ), drain leakage current (Idss) and on-voltage (Vds(on)), were measured.

Fig. 10 shows the characteristics of the MOSFETs. In the figure, the values of the MOSFETs thinned by the laser splitting process are compared to those of MOSFETs thinned by the conventional grinding process. The Igss remains very low for the MOSFETs with the laser process (as shown in Fig. 10(a)), and the Vth shows no change compared to MOSFETs with conventional thinning process (as shown in Fig. 10(b)), meaning that the gate oxide film was not subjected to significant damage from the laser irradiation. No significant changes in mean values and deviations were observed for the Idss and the Vds(On) (as shown in Fig. 10(c) and (d)), indicating that the laser splitting process does not damage the drift layer or electrodes. So far, we have obtained no results that show the laser process negatively impacts the MOSFET electrical characteristics.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

We proposed a novel SiC wafer reutilization process that integrates laser splitting and wafer bonding techniques. This approach aims to drastically reduce costs and material loss in SiC power device manufacturing by enabling the recycling of the wafers.

Our preliminary investigations have demonstrated the technical feasibility of this proposed process. Through comprehensive experiments on SiC wafer bonding, we confirmed that strong and stable bonds can be achieved using the SAB technique. The bonded wafers withstand processes such as high-temperature annealing and high-dose ion implantation without significant changes or delamination. Detailed cross-sectional TEM analysis revealed the formation of robust polycrystalline bonds at the interface due to solid phase reactions during thermal annealing, confirming their suitability for subsequent device processing.

The influence of the laser splitting process on device characteristics was evaluated using SiC MOSFETs. The electrical characteristics of the devices thinned by laser splitting showed no significant degradation compared to those thinned by conventional grinding. This confirms that the laser splitting process does not induce damage to the gate oxide film, drift layer, or electrodes.

These results demonstrate the technical feasibility of the proposed approach, which offers a costeffective and eco-friendly solution for SiC power device production. It will be necessary to conduct evaluations of thermal stress accumulation after multiple cycles of splitting and bonding, as well as reliability assessments of the MOSFET after laser splitting in the future.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

S. Rouchier, G. Gaudin, J. Widiez, F. Allibert, E. Rolland, K. Vladimirova, G. Gélineau, N. Troutot, C. Navone, G. Berre, D. Bosch, Y.L. Leow, A. Duboust, A. Drouin, J-M. Bethoux, R. Boulet, A. Chapelle, E. Cela, G. Lavaitte, A. Bouville-Lallart, L. Viravaux, F. Servant, S. Bhargava, S. Thomas, I. Radu, C. Maleville and W. Schwarzenbach, Materials Science Forum 1062, 131 (2022).

H.Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, S. Kurihara, S. Harada and K. Kojima, Defect and Diffusion Forum 434, 39 (2024).

T. Suga, F. Mu, M. Fujino, Y. Takahashi, H. Nakazawa and K. Iguchi, Jpn. J. Appl. Phys., 54, 030214 (2015).

K. Hirata, Proc. of SPIE, 10520, 1052003 (2018).

K. Akiyoshi, T. Tanaka, S. Takahashi, K. Iwanaga, K. Hamano and A. Furukawa, "Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics", Proc. of ICSCRM 2025 (in press).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 25-32

doi: 10.4028/p-lQ20LA

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-21

Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Kyohei Akiyoshi 1,a*, Takanori Tanaka 1, b, Shunta Takahashi 2,c, Kazumasa Iwanaga 1, d, Kenichi Hamano 1,e and Akihiko Furukawa 1,f

¹Power Device Works, Mitsubishi Electric Corporation, 1-1-1 Imajuku-higashi, Nishi-ku, Fukuoka, Fukuoka, 819-0192, Japan

2 Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki, Hyogo, 661-8661, Japan

a* Akiyoshi.Kyohei@ea.MitsubishiElectric.co.jp, b Tanaka.Takanori@cb.MitsubishiElectric.co.jp, c Takahashi.Shunta@bp.MitsubishiElectric.co.jp, d Iwanaga.Kazumasa@aj.MitsubishiElectric.co.jp, èhamano.kenichi@df.mitsubishielectric.co.jp, f  Furukawa.Akihiko@df.MitsubishiElectric.co.jp 

Keywords: SiC wafer, reutilization process, recycling wafer, laser slice, JBS diode, MOSFET.

Abstract

A laser slicing technique is an attractive alternative to grinding for thinning SiC wafers. This method has the potential to enable the reutilization of SiC wafers and reduce the waste generated during the grinding process. This paper comprehensively investigates the technical feasibility of laser slicing for the fabrication of SiC power devices. SiC JBS samples fabricated with laser irradiation revealed that by selecting the appropriate laser conditions, we can employ the technique without adversely affecting the JBS leakage current characteristics. Additionally, we fabricated SiC MOSFETs through wafer thinning using the laser slicing technique. The key electrical characteristics of the MOSFETs, including IGSS, IDSS,Vth  and VDS(on), showed no differences compared to those fabricated using conventional grinding. These results indicate that laser slicing is a highly promising thinning technique for the fabrication of SiC power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Silicon carbide (SiC) power devices offer superior characteristics, including high breakdown voltage, low on-resistance, low switching loss, and high-temperature operation. In their application to high-power systems, significantly improved performance is expected compared to their Si counterparts [1].

However, the manufacturing costs of SiC power devices remain high due to the high costs of SiC wafers. The high costs of SiC wafers are attributed not only to the costly sublimation bulk growth process but also to wafering processes such as slicing and grinding, which are challenging due to the inherent hardness and brittleness of SiC [2, 3]. Additionally, in the fabrication of SiC power devices, SiC wafers are thinned to enhance their performance. The conventional thinning process used today employs mechanical grinding, which removes valuable SiC material as sludge, creating a significant environmental burden.

Recently, the laser slicing technique has attracted significant attention as a method for slicing wafers from ingots [4]. Laser slicing can substantially reduce material loss (kerf loss) while maintaining high throughput [5]. In light of these advantages, the use of laser slicing for wafer thinning has been proposed as a replacement for conventional grinding. The sequence of wafer thinning process is illustrated in Fig. 1 [6]. This method enables device re-manufacturing on the wafer left after laser slicing. By applying this method to SiC power devices, it is expected to reduce manufacturing costs and decrease the environmental impact associated with SiC sludge.
A primary concern regarding the application of laser slicing for SiC wafer thinning is its potential adverse impacts on the characteristics of SiC power devices. This paper comprehensively evaluates the impacts of the laser slicing technology on device characteristics. First, we systematically

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Fig. 1. An example of a wafer reutilization process applying laser slicing technology for wafer thinning.

Fig. 1. An example of a wafer reutilization process applying laser slicing technology for wafer thinning.

investigate the effects of focused laser irradiation on Junction Barrier Schottky (JBS) electrodes, which are sensitive to heat. Second, we apply the laser slicing technique to the thinning process of SiC MOSFETs and present their electrical characteristics in comparison to those fabricated using conventional grinding process, demonstrating that the laser slicing is a promising technique to replace grinding.

Impacts of Laser Irradiation on JBS Electrodes

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Sample Chip Preparation and Evaluation Procedure.

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

1200 V SiC JBS diodes were fabricated to examine the impacts of laser slicing. The schematic top view and 3D cross-sectional view of the sample JBS diode, along with the fabrication and evaluation flow of the JBS diodes, are shown in Fig. 2 and 3. An epitaxial layer was grown on the Si-face of a 6 -inch N -type 4H−SiC substrate with a 4∘ off-cut angle, and a JBS structure was formed on this epitaxial layer. Using a laser slicing apparatus, the laser beam was irradiated to the SiC wafer from the backside ( C -face), focusing it at the desired depth from the JBS electrodes. The focused laser beam was scanned along a line depicted in Fig. 2, generating a modified layer and line-shaped cracks within the wafers. The laser power was set at 2.5 W,5.0 W, and 7.5 W , and the distance between the laser focal point and the surface electrode was varied from 20μ m to 160μ m in 20μ m increments. Finally, a backside metal electrode was formed on the C -face, and the wafer was diced into sample JBS chips.

We measured the reverse characteristics (leakage current) of the sample JBS diodes as an indicator sensitive to the heat generated by laser irradiation. For samples exhibiting increased leakage current, emission microscopy (EMS) was employed from the backside of the samples. Using EMS, we can detect light emissions from current leakage points, allowing us to pinpoint the defective locations. After removing the anode and Schottky barrier electrodes (Ti), scanning electron microscopy (SEM) observation was performed to assess the surface morphology, followed by energy-dispersive X-ray spectroscopy (EDX) conducted at the leakage points.

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Fig. 2. (a) Top view and (b) 3D cross-sectional view of the fabricated 1200 V JBS diode.

Fig. 2. (a) Top view and (b) 3D cross-sectional view of the fabricated 1200 V JBS diode.

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Fig. 3. Fabrication and evaluation process flow of 1200 V JBS diodes.

Fig. 3. Fabrication and evaluation process flow of 1200 V JBS diodes.

Leakage Current Measurement and Analysis.

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

The reverse characteristics of the fabricated JBS diodes under laser power of 2.5 W,5.0 W and 7.5 W are shown in Fig. 4(a), (b) and (c), respectively. At 2.5 W , all the chips exhibited I-V curves almost identical to that without laser irradiation. At 5.0 W and 7.5 W , the chips with the focal point distances ranging from 60μ m to 140μ m also exhibited I-V curves comparable to that without laser irradiation. In contrast, increase in leakage current was observed for the samples with shorter focal point distances and higher laser power.

To clarify the relationship between the increase in leakage current and laser irradiation to the JBS diodes, EMS analysis was performed on the defective chips with leakage current. The light emission was clearly observed from the backside when the leakage current flew over around 10μ A. Optical and EMS images and the I-V curve taken during EMS analysis of the sample are shown in Fig. 5(a), (b), and (c). The laser irradiation conditions for this sample are a laser power of 5.0 W and a focal point distance of 40μ m. In Fig. 5(b), the dark line indicates the modified layer with internal cracks generated by the laser irradiation. At the center of the line (just above the laser focus scanning line),

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Fig. 4. Reverse characteristics of 1200 V JBS diodes with irradiated laser power at (a) 2.5 W , (b) 5.0 W , and (c) 7.5 W .

Fig. 4. Reverse characteristics of 1200 V JBS diodes with irradiated laser power at (a) 2.5 W , (b) 5.0 W , and (c) 7.5 W .

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Fig. 5. (a) Optical + EMS image of JBS with leakage current, (b) an enlarged view of the emission point in (a), and (c) I-V characteristics during the EMS analysis. Laser slicing for the sample was performed under a laser power of 5.0 W and a focal point distance of 40μ m.

Fig. 5. (a) Optical + EMS image of JBS with leakage current, (b) an enlarged view of the emission point in (a), and (c) I-V characteristics during the EMS analysis. Laser slicing for the sample was performed under a laser power of 5.0 W and a focal point distance of 40 μ m .

an emission is clearly visible when the leakage current flows. This result suggests that the laser irradiation is the direct cause for the pinpoint leakage current. To reveal the mechanism by which leakage current occurred, we examined JBS surfaces after etching electrodes. Fig. 6(a) shows an optical image of the JBS diode surface that is subjected to laser irradiation at a power of 7.5 W and a laser focal point distance from the surface of 20μ m. Cracks are visible inside the wafer along the line where the laser beam was scanned. Fig. 6(b) and (c) show SEM images of the chip edge and JBS area of the sample, respectively. It should be noted that there is no Ti deposition in the chip peripheral area shown in Fig. 6(b). Although no laser-induced melting marks are observed in Fig. 6(b), small melting marks are observed just on the laser irradiated point in Fig. 6(c). EDX spectra at the points, melting marks (i) and non-melting marks (ii), in Fig. 6(c) are shown in Fig. 7. EDX analysis revealed that detectable Ti exists exclusively at the melting marks after removal of the Ti electrode. This indicates that the melting marks are alloys including Ti , and that the presence of the Ti is a key factor to the formation of these melting traces, which generate leakage current paths.
To investigate the parameter range where melting traces, specifically current leakage points, are created, we systematically examined the sample surfaces after stripping the electrodes. The surface

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Fig. 6. (a) An optical image of the sample JBS chip after the removal of electrodes. Inner cracks are visible along the laser-irradiated line. (b) A SEM image of the chip edge including the laser-irradiated line. No melting marks are present in the area. (c) A SEM image of the surface in JBS area. Melting marks are visible on the laser-irradiated line. A laser power and a focal point distance from the Ti electrode are 7.5 W and 20μ m.

Fig. 6. (a) An optical image of the sample JBS chip after the removal of electrodes. Inner cracks are visible along the laser-irradiated line. (b) A SEM image of the chip edge including the laser-irradiated line. No melting marks are present in the area. (c) A SEM image of the surface in JBS area. Melting marks are visible on the laser-irradiated line. A laser power and a focal point distance from the Ti electrode are 7.5 W and 20 μ m .

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Fig. 7. EDX spectrum at the points indicated in Fig. 6(c): (a) melting marks (i) and (b) nonmelting marks (ii).

Fig. 7. EDX spectrum at the points indicated in Fig. 6(c): (a) melting marks (i) and (b) nonmelting marks (ii).

images of the JBS diodes observed by SEM are shown in Fig. 8. Melting traces were observed on the SiC surface directly above the laser irradiation line. It was found that the higher the laser power and the shorter the distance from the electrodes the larger the area of the melting trace tended to be.

Based on these results, we take the discussion a step further. When the Ti electrode does not exist, no trace was observed (Fig. 6(b)). This means that Ti electrodes absorb the laser light effectively, and it is converted to heat. As indicated in Fig. 7, Ti is detected in and around the melting traces. It is known that SiC and Ti can react to form silicide and the silicide formation can occur at relatively low temperatures (below 1100∘C [7]) compared to Ti melting point of 1668∘C, suggesting that the formation of alloy makes it easier to form melting marks. Fig. 9 schematically illustrates how melting marks are formed above laser focal points.

From Fig. 4, it is evident that no significant impact on electrical characteristics was detected when the focal point distance from the electrode exceeded 60μ m. Considering that the typical final wafer thickness for power devices is more than around 100μ m, it is possible to establish the laser irradiation conditions for laser slicing that does not affect device characteristics.

Application of Laser Slicing to SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Laser slicing was applied to the thinning of 1200 V SiC MOSFETs. The fabrication process flow for SiC MOSFETs is shown in Fig. 10. An epitaxial layer was grown on the Si-face of a 6-inch Ntype 4H−SiC substrate with a 4∘ off-cut angle, and a MOSFET structure was fabricated on it. Using a laser slicing apparatus, the laser beam was irradiated and focused inside the SiC wafer from the backside (C-face) at a depth of 140μ m from the MOSFET surface. The laser beam was scanned over the entire wafer, forming a modified layer and cracks inside the wafer. Then the wafer was split into two pieces. Images of the wafers observed from the top side before and after laser slicing are shown in Fig. 11(a), (b) and (c). No middle or large size defects such as cracks or chippings are visible on the laser-sliced wafers. The detached surfaces were subsequently ground to achieve a final thickness of 100μ m. Finally, a backside metal electrode was formed, and the wafer was diced into chips.

The main electrical characteristics of the MOSFETs, including the gate leakage current (IGSS), the threshold voltage ( Vth  ), the drain leakage current at 1200 V(IDSS), and the on-voltage ( VDS(ON) ), were measured. The results are shown in Fig. 12(a), (b), (c), and (d). The electrical characteristics of the MOSFETs thinned by the laser slicing process are compared to those thinned by the conventional grinding process. The IGSS remains very low for the laser-processed MOSFETs and the threshold voltage Vth  shows no significant change compared to MOSFETs thinned by conventional grinding, indicating that the gate oxide film was not damaged by the laser irradiation. Furthermore, no significant changes, including standard deviation, are observed for the IDSS. The VDS(ON) also shows no significant change, suggesting that the laser slicing process does not damage the drift layer or electrode. Overall, we observe no adverse impacts on MOSFET characteristics due to the laser slicing.

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Fig. 8. SEM images of the JBS sample surface on the laser-irradiated line with various laser conditions ((a)-(o)) after the removal of anode electrodes and Schottky barrier electrodes (Ti).

Fig. 8. SEM images of the JBS sample surface on the laser-irradiated line with various laser conditions ((a)-(o)) after the removal of anode electrodes and Schottky barrier electrodes (Ti).

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Fig. 9. Illustrative diagram depicting the impact on electrodes due to laser light irradiation during laser slicing.

Fig. 9. Illustrative diagram depicting the impact on electrodes due to laser light irradiation during laser slicing.

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Fig. 10. 1200 V MOSFET fabrication process flow.

Fig. 10. 1200 V MOSFET fabrication process flow.

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Fig. 11. Top surface images of wafers: (a) before laser slicing, (b) with device structures after laser slicing, and (c) without device structures after laser slicing.

Fig. 11. Top surface images of wafers: (a) before laser slicing, (b) with device structures after laser slicing, and (c) without device structures after laser slicing.

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Fig. 12. Comparison of the main electrical characteristics ((a) IGSS, (b) Vth , (c) IDSS, and (d) VDS(ON) ) of the MOSFETs thinned by laser slicing and grinding only. Error bars represent ±1σ.

Fig. 12. Comparison of the main electrical characteristics ((a) I G S S , (b) V th , (c) I D S S , and (d) V D S ( O N ) ) of the MOSFETs thinned by laser slicing and grinding only. Error bars represent ± 1 σ .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

We investigated the laser slicing technique as an alternative to grinding for thinning SiC wafers. The impacts of focused laser light onto the SiC wafers were examined using test devices with JBS electrodes, whose characteristics are sensitive to heat. Measurements of leakage current revealed that higher laser power and shorter distances between the laser focus and JBS electrodes (below 60μ m ) increased leakage current. SEM observation and EMS analysis revealed that the heat from the laser beam creates melting traces on the SiC surface, generating leakage current paths. However, these results suggest that by selecting the appropriate laser irradiating parameters, laser slicing can be applied to the fabrication of SiC power devices. Based on our findings, SiC MOSFETs were experimentally fabricated utilizing the laser slicing technique. The performance of the MOSFETs exhibited no significant differences when compared to those fabricated using the conventional grinding technique. These results demonstrate that the laser slicing is a promising SiC wafer thinning technique replacing grinding.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

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T. Ishida, T. Ushijima, S. Nakabayashi, K. Kato, T. Koyama, Y. Nagasato, J. Ohara, S. Hoshi, M. Nagaya, K. Hara, T. Kanemura, M. Taki, T. Yui, K. Hara, D. Kawaguchi, K. Kuno, T. Osajima, J. Kojima, T. Uesugi, A. Tanaka, C. Sasaoka, S. Onda, and J. Suda, Appl. Phys. Express, 17, 026501 (2024).

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 33-40

doi: 10.4028/p-uAfni2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-31

Accepted:
2026-02-23

Online:
2026-05-21

A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

The original version of this paper is available on https://www.scientific.net/MSF.1193.33.pdf

Myung-Beom Park 1,a*, Jungwon Kim 1,b, Yigil Cho 1,c, Yun Ho Kim 1,d, Sam-Jong Choi 1,e

1 Samsung Electronics Co., Ltd., 1, Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do, 18448, South Korea

a* m.b.park@samsung.com, b  jwon88.kim@samsung.com, c  yigil.cho@samsung.com, d  yunho17.kim@samsung.com, e  wafer@samsung.com

Keywords: SiC powders, Si-based materials, synthesis of Si and SiC, recycling of by-products.

Abstract

This study delves into the synthesis of high-purity SiC powders utilizing two distinct silicon (Si) sources of recycled Si wafers and back-grind wastewater-both of which are abundant byproducts in semiconductor manufacturing processes. The synthesis involved the high-temperature reaction of these Si sources with ultra-high-purity graphite ( >6 N ) at temperatures exceeding 2100∘C. The resulting α-phase SiC powders derived from previously used Si wafers demonstrated unparalleled quality, achieving a purity level surpassing 99.9999% and exhibiting particle sizes exceeding 500 μm. These characteristics render them highly suitable for the fabrication of SiC wafers, a cornerstone of advanced semiconductor applications. This research underscores the potential of leveraging industrial by-products as sustainable Si sources for SiC synthesis, highlighting the superiority of α phase SiC produced from recycled Si wafers in high-purity applications.

1. Introduction

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Silicon carbide ( SiC ) has cemented its position as a cornerstone material in modern power electronics, owing to its unparalleled electrical and thermal properties [1]. These attributes, including its wide bandgap, high thermal conductivity, and superior mechanical strength, make SiC an ideal candidate for high-performance power semiconductor devices, such as Schottky diodes, MOSFETs, and IGBTs[2, 3]. However, the success of SiC-based devices is intricately linked to the quality and consistency of SiC wafers, which are directly dependent on the purity and physical properties of the precursor materials used in their fabrication [4-7]. Achieving a stable supply chain for these precursors is critical to meeting the growing demand for SiC technology in electric vehicles (EVs), renewable energy systems, and other power electronics applications [8].

The quality of SiC wafers is fundamentally determined by the characteristics of the precursor materials, particularly the SiC powders used as the foundational raw material [4]. High-purity SiC powders with consistent particle sizes and controlled crystalline phases are essential for producing wafers with the desired electrical conductivity, thermal stability, and mechanical integrity [9,10]. Any impurities or deviations in the powder properties can lead to defects in the SiC lattice structure, compromising the performance and reliability of the final semiconductor devices [9]. Therefore, the development of high-quality SiC powders is a cornerstone of advancing SiC wafer manufacturing and ensuring the long-term success of power semiconductor technologies.

The rapid increase in silicon sludge generated is a significant trend accompanying in from silicon solar cell manufacturing [11,12]. This by-product, rich in silicon content, presents a valuable opportunity for recovery and utilization across various industries, including semiconductors, where high-purity silicon is essential for wafer fabrication and device manufacturing. Additionally, silicon sludge can be processed into fine powders, which serve as a sustainable source of silicon for the production of silicon carbide (SiC) powders-a critical material in power electronics and semiconductor devices. By integrating these by-products into the silicon supply chain, industries can reduce reliance on virgin raw materials, enhance process efficiency, and contribute to environmental sustainability. Cutting is achieved by abrasive slurry, which consists of suspension silicon carbide
particles. During the process of wafer cutting almost 50% of silicon is lost in the sludge [13]. Several attempts were made to recycle the silicon sludge retrieved from the wire saw machines. However, there are no high successful results reported so far.

In the semiconductor industry, silicon is extracted from used wafers and back-grind wastewater, offering a reliable and sustainable source for SiC synthesis. These advancements in material recovery and processing not only optimize resource utilization but also align with the growing demand for high-performance materials in applications such as power electronics, electric vehicles (EVs), and renewable energy systems. By leveraging silicon sludge and other by-products, industries can achieve a more circular and efficient supply chain, supporting both economic and environmental objectives.

To address the challenges of obtaining high-quality SiC powders while ensuring a stable supply chain, this study explored the potential of utilizing semiconductor process by-products as sustainable raw materials for SiC wafer fabrication. Silicon by-products such as used Si wafers and back-grind wastewater, are readily available in semiconductor manufacturing facilities and offer a promising source of high-purity Si. These by-products can be processed into silicon powders, which can then be synthesized into SiC powders for SiC wafer production. By capitalizing on these readily available materials, manufacturers can reduce reliance on virgin raw materials, minimize waste generation, and enhance the environmental sustainability of SiC production processes. In detail, this research investigated the preparation and characterization of SiC powders derived from two distinct Si sources: used Si wafers and back-grind wastewater. Used Si wafers, which are inherently high-purity and large-particle materials, were crushed to produce fine Si powders, while back-grind wastewater, a byproduct of wafer back-grinding, was processed to extract Si through solvent evaporation and milling. The resulting Si powders were then synthesized into SiC powders under carefully controlled conditions, with the aim of evaluating their suitability for SiC wafer manufacturing.

This study underscores the critical importance of optimizing precursor materials and supply chain management in the advancement of SiC wafer fabrication and power semiconductor technology. By leveraging semiconductor process by-products as sustainable raw materials, manufacturers can significantly enhance the efficiency, cost-effectiveness, and environmental sustainability of SiC production processes.

2. Experimental

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In order to recycle these generated silicon in semiconductors and other industries, it is important to find a best methods for the solidified powder form Si solution. Two powders prepared from different methods is various, as shown in Fig.1. Si powder was prepared by crushing from the used Si wafer, as shown in Fig. 1(a). On the other hand, as for the method of recycling silicon wastewater, as shown in Fig. 1.(b), typical method of making solid silicon from various silicon byproducts is a method of solidifying a Si solution by forming a solid phase using a filter press with a silicon solution as shown in Figure 2. Specifically, a method of forming a silicon cake by extracting deionized water

Processed Wafer

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Fig. 1. (a) Cleaned wafer and back-grinding process and in semiconductor processes.

Fig. 1. (a) Cleaned wafer and back-grinding process and in semiconductor processes.

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Fig. 2. Methods of Si powders prepared from the Si solution.

Fig. 2. Methods of Si powders prepared from the Si solution.

from a silicon solution is typical, and silicon cake can be dried to finally produce silicon powder. This study focuses on the synthesis and evaluation of silicon carbide ( SiC ) powders derived from two distinct silicon (Si) sources (used Si wafers and back-grind wastewater) for SiC wafer. Two different SiC powders were prepared by reaction of both Si powders with pure graphite (purity >6 N ) at over 2100∘C. Key objectives include analyzing the purity, particle size, and crystalline phases of the resultant SiC powders, as well as exploring their applications in semiconductor SiC devices manufacturing. Advanced analytical techniques, including energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM), were employed to investigate the composition and structural properties of the Si and SiC materials.

3. Results & Discussion

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3.1 Characterization of Si Powders and Optimization of SiC Powder Synthesis for Semiconductor Applications

Si powders derived from back-grind wastewater yielded larger particle sizes (around 1μ m ), which SiC powders are less suitable for advanced SiC wafer applications. The primary constituents of silicon (Si) powders derived from back-grind wastewater were confirmed through energy-dispersive X-ray spectroscopy (EDX) to be Si,O, and C , as illustrated in Figure 3(a). X-ray photoelectron spectroscopy (XPS) further revealed the presence of SiOx phases, indicative of an amorphous structure, as shown in Figure 3(b). These findings suggest that the surface of the Si powders interacted with ambient oxygen forming SiOx layers that significantly influenced their reactivity and applicability, as depicted in Figure 3(c).

In contrast, Si powders were successfully synthesized from used Si wafers with small oxidation

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Fig. 3. Chemical composition results of Si powders: (a) EDX results, (b) and XPS results. And then, a schematic diagram of Si powders coated oxidized and carbonized Si as shown in (c).

Fig. 3. Chemical composition results of Si powders: (a) EDX results, (b) and XPS results. And then, a schematic diagram of Si powders coated oxidized and carbonized Si as shown in (c).

Table I. Characteristics of Si Powders Prepared Using Various Methods.

under 0.1%, characterized by particle sizes around 100μ m, as shown in Table I. These attributes make them highly suitable for SiC wafer fabrication, aligning with the stringent requirements of power semiconductor manufacturing.

The quality of SiC powders, which are critical raw materials for SiC wafer manufacturing in power semiconductors, is determined by several key factors, including metal impurities and physical properties. High-quality Si powders are essential for achieving the purity and structural integrity required for SiC wafers. As such, the quality of Si powders and their supply chain management (SCM) are paramount for the success of SiC power semiconductor manufacturing. Obtaining Si powders from semiconductor processes, particularly through Si wafer back-grinding, is a promising approach to ensure the quality and consistency of SiC powders.
To evaluate the feasibility of Si powder synthesis from Si by-products, this study prepared Si powders using Si generated within a semiconductor company. In order to compare the quality of the synthesized Si powder, Si prepared for each raw material was analyzed, as shown in Table I. The results demonstrated that the Si powders prepared from used Si wafer exhibited superior quality, exceeding the performance of conventional raw materials. The size of Si powder over 80 um prepared from the used Si wafer, as shown in Table I with under 0.1% oxidation. These powders were further assessed at a SiC powder mass production facility, and their suitability for SiC wafer fabrication was confirmed. From used Si wafers, high-purity Si powders were successfully synthesized.

This research highlights the potential of leveraging silicon by-products from semiconductor processes as sustainable raw materials for SiC powder synthesis. By securing high-quality SiC powders from used Si wafers, manufacturers can improve the efficiency and scalability of SiC wafer production, ultimately enhancing the performance of power semiconductor devices.

3.2. High-Purity α-Phase SiC Powders and Their Role in SiC Wafer Fabrication and Semiconductor Device Enhancement

The intrinsic properties of SiC powders are pivotal in determining their suitability for SiC wafer fabrication and the subsequent performance of semiconductor devices. High-purity α-phase SiC powders, specifically those derived from crushed Si wafers, exhibit a remarkable combination of characteristics that make them exceptionally well-suited for SiC wafer production, as shown in Fig.4. These powders possess particle sizes exceeding 500μ m, which not only enhance the structural integrity of the wafers but also facilitate efficient processing during manufacturing in Table II. Furthermore, their purity levels exceeding 99.9999% ensure minimal impurity incorporation, which is critical for achieving high-quality SiC wafers with superior electrical and thermal properties, as

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Fig. 4. XRD of two Size distribution of two different SiC powders prepared from different methods of filtered powder from back-grinding Si and crushed powders from process wafer in semiconductor industries.

Fig. 4. XRD of two Size distribution of two different SiC powders prepared from different methods of filtered powder from back-grinding Si and crushed powders from process wafer in semiconductor industries.

shown in Table II. These attributes align seamlessly with current manufacturing workflows, enabling manufacturers to integrate SiC powders into existing production processes without significant modifications. This compatibility ensures a smooth transition to scalable SiC -based power device production, which is essential to meet the growing demands of the electric vehicle (EV) and renewable energy sectors. The large particle sizes of the α-phase SiC powders also contribute to reducing processing times and material waste, further enhancing the economic viability of SiC wafer fabrication.

Conversely, Si powder obtained from backgrind wastewater showed oxidation ratio ( 16% ) of 1.7 μm in size, causing the problem of producing β-phase SiC , which is essential for SiC wafer applications, as shown in Fig. 4. The study highlights the critical role of SiC powder quality in determining the performance of SiC -based devices. Si powders from back-grind wastewater, though viable for certain applications, were found to be less effective for SiC wafer production. Si powders derived from back-grind wastewater present notable challenges for SiC wafer applications. These powders typically exhibit smaller particle sizes (~1.7μ m), which can lead to increased aggregation and poor sinterability, resulting in lower-quality wafers. Additionally, their higher oxidation ratios ( 16% ) introduce oxygen impurities that can adversely affect the electrical properties of the final SiC devices. These characteristics render them less suitable for high-performance SiC wafer fabrication, though they may still find utility in applications where material cost and processing efficiency are prioritized over ultimate device performance.

In the realm of SiC wafer fabrication, high-purity α-phase SiC powders derived from polished Si wafers stand out as a highly promising material for SiC wafer production [9,10]. These powders, with their exceptional purity levels exceeding 99.9999% and particle sizes exceeding 500μ m, offer distinct advantages that align with modern manufacturing requirements for SiC -based power devices. Their superior quality ensures compatibility with existing production workflows, enabling manufacturers to seamlessly integrate advanced materials into current processes without the need for significant modifications. This characteristic is particularly valuable in the context of scalability, as it allows for the efficient and cost-effective production of high-performance SiC wafers, which are increasingly in demand for applications in electric vehicles (EVs), renewable energy systems, and other power electronics sectors. The use of α-phase SiC powders derived from polished Si wafers also enhances the intrinsic properties of the resulting SiC wafers, such as electrical conductivity, thermal stability, and mechanical strength. These improvements directly contribute to the performance of power semiconductor devices manufactured using these wafers, such as Schottky diodes, MOSFETs, and IGBTs. By leveraging the high purity and large particle sizes of these powders

Table II. Characteristics of SiC Powders.

manufacturers can achieve wafers with minimal impurities, which is critical for maintaining the integrity of the lattice structure and ensuring optimal device characteristics. Furthermore, the scalability of SiC-based power devices is significantly enhanced, as these wafers can be processed using established manufacturing techniques, thereby reducing the time and cost associated with process development and implementation.

Si powders derived from back-grind wastewater, despite their potential as sustainable raw materials, fall short of meeting the stringent requirements for SiC wafer fabrication. These powders typically exhibit smaller particle sizes ( ~1.7μ m ) and higher oxidation ratios ( 16% ), which lead to challenges in achieving the desired purity and structural integrity for high-performance SiC wafers. The increased particle aggregation and poor sinterability associated with these powders result in wafers that are less suitable for applications requiring exceptional electrical and thermal properties.

However, these Si powders still offer viable alternatives for applications where material cost and processing scalability are prioritized over ultimate device performance. For instance, they can be utilized in lower-cost SiC devices or as part of hybrid manufacturing processes that combine different SiC powder sources to optimize material utilization and cost-effectiveness. Therefore, high-purity α phase SiC powders derived from polished Si wafers represent a transformative solution for SiC wafer fabrication, offering superior quality, compatibility with existing workflows, and scalability for SiCbased power devices. These materials not only enhance the performance of the final devices but also align with the sustainability goals of the semiconductor industry by leveraging by-products from existing fabrication processes. While Si powders from back-grind wastewater may have limitations for high-performance SiC wafer applications, they provide valuable alternatives for specific use cases, demonstrating the diverse potential of Si -based materials in advancing semiconductor technology.

As you know, general Si wafer were doped with n-type or p-type dopant I used this doped wafer for preparation of SiC powder. The doping depth is very shallow and very low concentration, compared to that bulk wafer thickness and Si bulk atomic concentration. I did not any action for removing this doping amount for pure SiC powders. I checked the main doping amount. I do not observe remarkable impurities depending on doping amount in Table II.

3.3. Properties of SiC Powders and Their Impact on SiC Wafer Fabrication and Device Performance

The intrinsic properties of SiC powders are pivotal in determining their suitability for SiC wafer fabrication and the subsequent performance of semiconductor devices. High-purity α-phase SiC powders, specifically those derived from crushed Si wafers, exhibit a remarkable combination of characteristics that make them exceptionally well-suited for SiC wafer production. These powders possess particle sizes exceeding 500μ m, which not only enhance the structural integrity of the wafers but also facilitate efficient processing during manufacturing.

Conversely, Si powders derived from back-grind wastewater present notable challenges for SiC wafer applications. These powders typically exhibit smaller particle sizes (~1.7μ m), which can lead to increased aggregation and poor sinterability, resulting in lower-quality wafers. Additionally, their higher oxidation ratios ( 16% ) introduce oxygen impurities that can adversely affect the electrical properties of the final SiC devices. These characteristics render them less suitable for highperformance SiC wafer fabrication, though they may still find utility in applications where material cost and processing efficiency are prioritized over ultimate device performance.

4. Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1193.33.pdf

Silicon carbide (SiC) has emerged as a pivotal material in modern power electronics due to its exceptional electrical and thermal properties, making it essential for high-performance semiconductor devices. However, the production of SiC wafers relies heavily on the quality and purity of precursor materials, which directly impact the performance of the final products. This study explores the synthesis and characterization of SiC powders derived from two distinct silicon (Si) sources: used Si wafers and back-grind wastewater. These by-products, readily available in semiconductor manufacturing, were selected as potential raw materials for SiC wafer fabrication. The research focuses on optimizing the production process to maximize the quality of SiC powders. High-purity α-phase SiC powders were successfully synthesized from used Si wafers, exhibiting exceptional purity ( >99.9999% ) and large particle sizes ( >500μ m ), making them highly suitable for SiC wafer manufacturing. Conversely, Si powders obtained from back-grind wastewater, while similar in size of 1.7μ m, showed higher oxidation ratios ( 16% ) and were less effective in producing α-phase SiC, which is essential for SiC wafer applications. The study highlights the critical role of SiC powder quality in determining the performance of SiC-based devices. High-purity α-phase SiC powders derived from used Si wafers demonstrated outstanding compatibility with existing manufacturing workflows, supporting the scalability of SiC-based power electronics. By controlling the characteristics of SiC powders from Si raw materials to SiC devices, this study contributes to advancing Si-based material technology and enhancing the performance of power semiconductor devices. The findings provide valuable insights for optimizing SiC wafer fabrication processes, ensuring a stable supply chain, and meeting the growing demand for high-performance SiC materials in power electronics.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.33.pdf

P.J. Wellmann, Semicond Sci Technol, 33, 103001 (2018).

G. Grant, S. Villastefan, Nature Electronics, 6(2), 64-73 (2023).

Y. H. Park, C. H. Byeon, J. H. Kim, Journal of Electronic Materials, 51, 2684 (2022).

S. Zhang, Y. Ren, X. Yang, W. Ma, H. Chen, et. al., J. Mat. Res. & Tech., 34, 2593 (2025).

J. M. Fernández, A. Muñoz, A.R. de A. López, et. al., Acta Mater, 51, 3259 (2003).

J. Lamon, Comprehensive Nuclear Materials, 2, 323 (2012).

H. Sakidin, M.A.H. M. Sohor, et al., UTP-UMP Sympos. Ener. Sys., 131, 04003 (2017).

Chopra, S. and Meindl, P. Supply Chain Management: Strategy, Planning, and Operation. Prentice-Hall, Upper Saddle River, NJ. (2001).

J. G. Kim, E. J. Jung, Y. Kim, Y. Makarov, D. J. Choi, Ceramics Inter., 40, 3953 (2014).

E. Jung, M. H. Lee, Y. J. Kwon, et al., J. Kor. Cryst. Growth & Cryst. Tech., 27, 57 (2017).

W. T. Kwon, S. R. Kim, Y. H. Kim, Y. J. Lee, E. J Jung, W.-K. Park, S. C. Oh, Mat. Sci. For. 724.49 (2012).

Y.H. Kim, E.B. Kim, S.R. Kim, M.H. Suh, D.J. Choi, W.T. Kwon Adv. Mater. Res. 26-28, 271 (2007).

R.A. Andrievski, Rev. Adv. Mater. Sci. 22, 1 (2009).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 41-45

doi: 10.4028/p-BAyAw0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-23

Accepted:
2026-03-16

Online:
2026-05-21

Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Yuken Matsumura 1,a*, Shunto Iden 1, b, Daisetsu Toh 1,c, Jumpei Yamada 1, d and Yasuhisa Sano 1,e

1 Department of Precision Engineering, Graduate School of Engineering, The University of Osaka, Osaka, Japan

a*y.matsumura@up.prec.eng.osaka-u.ac.jp, b  iden@up.prec.eng.osaka-u.ac.jp, ctoh@prec.eng.osaka-u.ac.jp, d  yamada@prec.eng.osaka-u.ac.jp, e  sano@prec.eng.osaka-u.ac.jp

Abstract

Plasma chemical vaporization machining (PCVM) is a high-rate etching method that uses atmospheric-pressure plasma. Its application to the plasma dicing of SiC wafers is anticipated. However, since the reaction is mainly driven by neutral radicals, it is difficult to maintain anisotropy, and issues such as side etching are of concern. In this study, PCVM processing was performed using SF6 gas with a Ni mask to investigate vertical and lateral etching behaviors. We achieved vertical etching of 100μ m within approximately 35 minutes, and lateral side etching of about 50μ m. The lateral etch rate remained nearly constant, whereas the vertical etch rate was initially high but decreased as the etching progressed, approaching the lateral rate. Finite element-based electrostatic field analysis revealed that, as the etching depth increased, electric field shielding by the mask weakened the field at the bottom of the trench, leading to a transition toward neutral radicaldominated reactions.

Keywords: plasma chemical vaporization machining, atmospheric-pressure plasma, etching, dicing, SF6, damage-free, time dependance.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

In semiconductor device manufacturing, wafer dicing is an indispensable process. SiC has attracted significant attention as a material for power devices; however, due to its high hardness and brittleness, conventional mechanical dicing using diamond blades often introduces defects and cracks, leading to reduced chip strength and yield. Laser-based dicing techniques, such as laser thermal dicing and stealth dicing, have also been explored as non-contact alternatives; however, they involve localized thermal modification or internal damage layers, which may induce residual stress and microcracks, thereby limiting the mechanical reliability of SiC chips. In contrast, plasma dicing-non-contact and damage-free processing using plasma-has already been put into practical use for silicon. Nevertheless, when applied to SiC , the removal rate is too slow for practical implementation. To address this issue, we propose the application of plasma chemical vaporization machining (PCVM) [1,2]-a high-pressure plasma process operating in the kPa -to-atmospheric-pressure range-to SiC dicing. PCVM removes material through chemical reactions using high-density radicals generated in atmospheric-pressure plasma. Owing to its non-contact nature, it suppresses cracks and chipping while enabling high-rate processing. It has previously been reported that a high etching rate of approximately 15μ m/min can be achieved on 2-inch SiC wafers [2]. In our previous work, we conducted etching experiments with varying metal mask widths and demonstrated that the etch rate decreases with narrower mask openings and deeper trenches. However, due to the limited durability of the masks, the etching depth was restricted to about 40μ m, which prevented sufficient evaluation of the time dependence of side etching or detailed electrostatic field analysis [3]. In this study, we applied PCVM to SiC wafers covered with a thick, durable Ni mask prepared by electroplating. By systematically measuring the trench depth and lateral progression as a function of processing time, we evaluated the development of side etching and the evolution of anisotropy. In
addition, finite element analysis was employed to examine the electrostatic field distribution, and the observed decrease in the electric field at the trench bottom was interpreted as being attributable to mask-induced field shielding. Through this approach, we clarified the side etching behavior in SiC plasma dicing and provided a fundamental investigation toward its practical application.

Experimental Procedure

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Figure 1 shows a schematic of the PCVM processing system. The sample was prepared by cutting a commercially available n-type 4H-SiC wafer into pieces of 10×20 mm2; the ( 0001― ) surface, corresponding to the back side of devices, was used as the processing surface. As the mask, a 100 nm-thick Ni metal layer was first deposited via vacuum evaporation, followed by electroplated Ni growth to a thickness of approximately 0.7μ m. To confine the plasma irradiation region, the mask was patterned with a cross-shaped slit opening about 50μ m wide. To prevent arc discharge during processing, the aluminum sample stage was coated with yttria via thermal spraying, to provide surface insulation and serve as a protective coating. The electrode was a water-cooled aluminum alloy plate with a diameter of approximately 2 inches in which numerous micro holes for gas injection were distributed on the surface facing the sample. A 13.56−MHz RF power supply was employed for plasma generation. The process gas was pure SF6, supplied at a flow rate of 250 sccm . The chamber pressure was maintained at 2.5 kPa , with an electrode-to-sample distance of 1.7 mm and an applied RF power of 1200 W .

The experimental procedure was as follows: The chamber was first evacuated with a dry pump down to approximately 30 kPa , after which SF6 was introduced to reach 2.5 kPa . The pressure was then kept at 2.5 kPa by adjusting the exhaust valve opening. RF voltage was applied between the plasma-generating electrode and the sample to ignite the plasma, and etching was carried out. Processing times were set to 5 or 10 minutes, and etching followed by evaluation was repeated multiple times. For post-process evaluation, the vertical etch depth was measured using a confocal laser scanning microscope (LEXT3000, Olympus). The lateral etch amount was determined using a scanning electron microscope (S-4800, Hitachi) to observe the cross-shaped mask opening from an oblique angle, as shown in Fig 2. To aid in the interpretation of the results, electrostatic field simulations were performed using the two-dimensional finite element analysis software E-STAT (Field Precision LLC) [4].

[picture]

Fig. 1. PCVM experimental apparatus.

Fig. 1. PCVM experimental apparatus.

[picture]

Fig. 2. Method for measuring side etching.

Fig. 2. Method for measuring side etching.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Removal rate.

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Figures 3 and 4 show the time evolution of etch depth and etch rate. In this experiment, vertical etching to a depth of 100μ m-comparable to the thickness of thinned wafers after backside thinning-was successfully achieved within approximately 35 minutes. As for the amount of side etching accompanying the vertical etch, cross-sectional SEM images (Fig. 5) revealed that, after 35 minutes, lateral etching beneath the mask reached up to approximately 50μ m. Focusing on the time dependence of the etch rates, the lateral etch rate remained almost constant regardless of etching duration, whereas the vertical etch rate exhibited a pronounced time variation. Specifically, the vertical etch rate was initially very high, but gradually decreased as etching proceeded, eventually converging to a value comparable to that of the lateral etch rate.

[picture]

Fig. 3. Time evolution of removal amount (red: lateral, blue: vertical).

Fig. 3. Time evolution of removal amount (red: lateral, blue: vertical).

[picture]

Fig. 4. Time evolution of removal rate (red: lateral, blue: vertical).

Fig. 4. Time evolution of removal rate (red: lateral, blue: vertical).

[picture]

Fig. 5. Cross-sectional SEM image of the processed sample ( 600× magnification).

Fig. 5. Cross-sectional SEM image of the processed sample ( 600 × magnification).

Electrostatic field analysis.

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

To elucidate the physical factors underlying this behavior, two-dimensional finite elementbased electrostatic field analyses were performed to calculate the field distribution within the etched trench. Fig. 6 shows an example of the calculated distribution at a trench depth of 100μ m. The trench depth varied from 0 to 100μ m, in 10−μm increments, and the electric field intensity at the trench bottom was extracted; the results are summarized in Fig. 7, illustrating the quantitative relationship between trench depth and bottom field intensity. At the early stage of etching, the high vertical etch rate can be attributed to the strong electric field formed between the electrode and the sample when the trench was shallow and close to the surface. In this region, ions were slightly accelerated by the near-surface electric field and bombarded the sample surface, thereby promoting material removal reactions and resulting in rapid vertical etching. It has been reported elsewhere that, in SiC , even slightly accelerated ions can enhance the etching reaction [5]. In our experiment, the estimated ion energy, derived from the field strength and mean free path, was below 2 eV , suggesting that physical damage to the sample was negligible. As the etching progressed and the trench deepened, however, the electric field intensity at the trench bottom was found to decrease, due to the shielding effect of the mask structure. Consequently, ions were less able to reach and be accelerated at the bottom, and the dominant reactive species gradually shifted to neutral radicals. Unlike ions, neutral radicals are unaffected by electric fields; therefore, the etching proceeded isotopically. This explains the observed trend in which the vertical etch rate approached the lateral etch rate over time. From these results, we could demonstrate that, in the plasma etching of SiC using the PCVM method, the strong electric field present in the initial stage plays a crucial role in achieving high vertical etch rates. As etching proceeds and the bottom field intensity diminishes, the etching mechanism transitions to radicaldominated isotropic etching. Future studies should focus on optimizing processing conditions to maintain higher anisotropy while achieving fast and precise SiC dicing.

[picture]

Fig. 6. Electrostatic field analysis example (trench depth: 100μ m ).

Fig. 6. Electrostatic field analysis example (trench depth: 100 μ m ).

[picture]

Fig. 7. Electric field distribution at each etch depth.

Fig. 7. Electric field distribution at each etch depth.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

In this study, PCVM was applied to SiC wafers with patterned mask openings, and damagefree dicing with a vertical etch depth of 100μ m was successfully demonstrated within approximately 35 minutes. We observed a decrease in the vertical etch rate accompanied by an increasing depth. which was mainly attributable to the reduction of ion contributions caused by electric field attenuation. Future work will systematically investigate the effects of plasma generation conditions - such as pressure, electrode configuration, and RF power - on both vertical and lateral etch rates, with the aim of optimizing dicing conditions to achieve greater anisotropy in SiC etching.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Y. Mori, K. Yamauchi, K. Yamamura, and Y. Sano. Rev. Sci. Instrum. 71, 4627-4632 (2000).

Y. Sano et al. ECS J. Solid State Sci. Technol. 10, 014005 (2021).

Y. Sano et al. Mater. Sci. Forum 1124, 51-55 (2024).

E-Stat: Electric Field Distribution Simulation Tool, Field Precision LLC. [Online]. Available: .

S. Iden, Y. Matsumura, J. Yamada, D. Toh, K. Yamauchi, and Y. Sano. "Basic study of plasma dicing for SiC wafer using high-pressure plasma," presented at the 20th International Conference on Precision Engineering (ICPE2024), Oral, GS17-05, Tohoku University Aobayama Campus, Miyagi, Japan, Oct. 23-26, 2024.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 47-54

doi: 10.4028/p-3CfRaK

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-06

Accepted:
2026-03-21

Online:
2026-05-21

Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

David M. Lynch 1,a*, Gregory L. Keaton 1,b, Christopher A. Lee 2,c and Alexander T. Bean 3,d

1 Halo Industries, 3270 Scott Blvd., Santa Clara, CA 95054, USA

2 Corning Incorporated, 60 O'Connor Rd., Fairport, NY 14450, USA

3 Landmark Measurement Solutions Inc., 9990 Coconut Rd., Estero, FL 34135, USA

a* david.lynch@halo-industries.com, b  greg@halo-industries.com, c  leeca@corning.com, dalex@landmarkmeasurement.com

Keywords: total thickness variation (TTV), frequency scanning interferometry, refractive index homogeneity.

Abstract

Accurate total thickness variation (TTV) measurement is essential for silicon carbide (SiC) wafer manufacturing and process control. This work evaluates the accuracy of interferometric TTV measurements using the Corning Tropel FlatMaster MSP system, benchmarked against a dual-source chromatic white light (CWL) profilometer. We investigate the influence of spatial refractive index variation on interferometric accuracy by comparing MSP and CWL results. The analysis reveals high MSP repeatability with small deviations linked to index variation. These trends provide a framework for interpreting interferometric TTV data and improving metrology practices for SiC substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

The rapid growth of power and optoelectronic devices has positioned silicon carbide ( SiC ) as a critical semiconductor valued for its wide bandgap, high thermal conductivity, and high breakdown field strength. As demand accelerates, particularly for larger-diameter substrates, efficient and scalable manufacturing becomes essential.

SiC wafer production faces persistent challenges. Mechanical wire sawing introduces kerf loss, residual stress, and geometric distortions such as bow, warp, and total thickness variation (TTV). Post-processing steps like grinding and chemical mechanical polishing (CMP) can mitigate these effects but add material loss. Emerging laser-based wafering methods aim to minimize kerf loss and stress-induced deformation; such approaches are under development by Halo Industries and others.

Accurate wafer geometry measurement is crucial for process control and device yield. Chromatic white light (CWL) profilometry provides direct thickness mapping by measuring both wafer surfaces, but its scanning nature limits speed and spatial resolution. Interferometric systems, such as the Corning Tropel FlatMaster MSP, enable rapid, full-field measurements with high sampling density [1,2].

However, interferometry depends on the substrate's refractive index to convert optical path distance into physical thickness. Variations in index arising from doping or other local inhomogeneities introduce systematic errors. While these effects are recognized, existing studies of these dependencies are sparse and often restricted to single-wavelength data [3].

This work evaluates interferometric TTV measurements of 4H−SiC wafers on the MSP, benchmarked against a dual-source CWL profilometer. We quantify refractive index effects across both intentional doping levels (semi-insulating to heavily doped) and unintentional material variations (e.g., near basal facet regions). Results demonstrate high MSP repeatability and systematic deviations linked to index variation, offering more robust TTV metrology in SiC manufacturing.

Experimental Plan

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Samples.

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We analyzed the thickness and optical properties of 4H−SiC wafers fabricated by Halo Industries' laser-based wafering method. Most samples were 150 mm device-grade n-type wafers ( N -doped, 1924 mΩ· cm ) with a 4∘ miscut toward [ 1120 ]; five were 200 mm optical-grade, undoped, and without miscut.

Measurement Methods.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Interferometric thickness was measured by frequency-scanning interferometry on a Corning Tropel FlatMaster MSP 300 with an 830 nm laser. Results were benchmarked against physical thickness measured using a Camtek FRT Microprof MHU, equipped with dual chromatic white light (CWL) sensors for simultaneous mapping of the top and bottom surfaces.

The MSP collects 128 interferograms while stepping the laser from 825−835 nm. A Fourier transform yields spectra with peaks from different surface pairs [Fig.1(a)]. The location of each peak in Fourier space gives the optical path difference (OPD) between the two surfaces, where the OPD is defined as:

OPD=ng·t(1)

where ng is the group index and t is the distance between surfaces. Therefore, the Fourier spectrum can be used to calculate the thickness of the sample if the group index is known. Since illumination is nearly parallel to the crystallographic c-axis, the ordinary group index is appropriate for MSP thickness calculations [5, 6]. For initial calculations, we assumed an ng of 2.690 , and any residual index error was corrected by calibration against CWL thickness measurements:

[picture]

Fig. 1. (a) Schematic of the MSP measurement [4]. Fourier spectrum of the interference patterns shows peaks from different surface pairs. (b) MSP stack with an optical flat, enabling independent measurement of wafer thickness and group index via additional surface pairs.

Fig. 1. (a) Schematic of the MSP measurement [4]. Fourier spectrum of the interference patterns shows peaks from different surface pairs. (b) MSP stack with an optical flat, enabling independent measurement of wafer thickness and group index via additional surface pairs.

Refractive Index Verification.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Refractive index verification was performed using two independent methods. Phase index was measured at 632.8 nm with a Metricon prism-coupler (TE-polarized HeNe laser). Group index at 950 nm was measured on a custom MSP with a 950 nm laser and optical flat [Fig. 1(b)], enabling independent determination of thickness and index.

Optical Retardance.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Optical retardance maps were collected with an Ilis StrainScope Stepper 200. For doped wafers with a 4∘ tilt, samples were physically tilted ~12∘ toward [1120] to align with the optic axis and suppress intrinsic birefringence. The measured retardance therefore primarily reflects stress-induced birefringence.

MSP vs. CWL Thickness Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Measurement Overview.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Fig. 2(a) shows an MSP thickness map of a CMP-processed 150 mm doped wafer measured in ~30 s ( 340μ m average thickness, 170μ m pixel size, ~600k points). This combination of speed and dense sampling highlights the strength of interferometry for full-wafer metrology.

Nanotopography maps can be generated directly from MSP data by removing low-order Zernike terms and applying a Gaussian filter [Fig. 2(b)]. This reveals sub-micron features ( ± 200 nm here) that are otherwise obscured in the raw map, such as radial patterns from residual grinding damage and concentric CMP artifacts. The ability to extract these details rapidly from high-resolution wafer-level maps is a key advantage of the MSP approach.

By contrast, CWL profilometry achieves direct physical thickness mapping without index assumptions but at the cost of throughput. Fig. 2(c) shows a CWL map of comparable resolution ( 341 μm average thickness, 100μ m pitch), which required ~90 minutes per wafer. To reduce acquisition time to ~10 minutes, the measurement pitch must be coarsened to 1.5 mm ( ~8k points), as in Fig. 2(d), but this sacrifices spatial detail.

These examples illustrate a fundamental trade-off: CWL provides direct thickness but only with slow, step-and-scan measurements, while MSP delivers fast, high-resolution maps suitable for waferlevel process control. This contrast is expected to become even more pronounced at larger wafer diameters, underscoring the scalability advantage of interferometric metrology.

[picture]

Fig. 2. Example thickness maps for a 150 mm wafer: (a) MSP thickness map, (b) MSP nanotopography map (Gaussian-filtered with cutoff wavelength of 20 mm ), (c) high-resolution CWL map, and (d) low-resolution CWL map.

Fig. 2. Example thickness maps for a 150 mm wafer: (a) MSP thickness map, (b) MSP nanotopography map (Gaussian-filtered with cutoff wavelength of 20 mm ), (c) high-resolution CWL map, and (d) low-resolution CWL map.

Refractive Index Calibration.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

MSP thickness relies on the assumed refractive index. At a given OPD measurement,

t=OPDng(3)

so a small index error Δng produces a thickness error

Δt=−tngΔng(4)

Thus, thickness error scales with wafer thickness and the fractional index error. Table 1 shows that a 1/1000 index error yields ~100−200 nm thickness error. While modest, larger index deviations can quickly become significant.

Table 1. Estimated thickness error from a 1/1000 error in assumed group index, evaluated for nominal wafer thicknesses at ng=2.690.

Wafer

Thickness mathematical formula

2.690 | 350 | 130
500 | 186

A simple calibration method is to compare MSP average thickness with physical thickness from CWL. Fig. 3 shows this relationship for doped wafers, with a fit slope giving

tMSPtCWL=ncalnused=1.00066(5)

indicating a ~0.07% overestimation and suggesting a true index of 2.692 (vs. 2.690).

[picture]

Fig. 3. MSP vs. CWL average thickness for doped wafers, with proportional fit showing a ~0.07% overestimation of MSP thickness with a chosen index of 2.690.

Fig. 3. MSP vs. CWL average thickness for doped wafers, with proportional fit showing a ~ 0.07 % overestimation of MSP thickness with a chosen index of 2.690.

While global averages provide a quick calibration, they can be skewed by outliers or macroscopic distortions (e.g., dimples, residual grind marks). To mitigate these effects, we instead compared full wafer maps by subtracting CWL and MSP thickness data after alignment and pixel matching [Fig. 4]. Although this approach can still be influenced by misalignment, edge exclusion differences, and CWL artifacts, the average value of the resulting difference maps offers a more robust estimate of index miscalibration.

[picture]

Fig. 4. Difference maps (CWL - MSP) for two wafers: (a) 279-4, variation mainly from map misalignment; (b) 104-3, variation dominated by basal facet region.

Fig. 4. Difference maps (CWL - MSP) for two wafers: (a) 279-4, variation mainly from map misalignment; (b) 104-3, variation dominated by basal facet region.

Table 2 summarizes mean difference map values by material type and source. Doped wafers showed consistent offsets of -210 to -250 nm across three suppliers, corresponding to calibrated indices of 2.691-2.692. Optical-grade wafers showed +310 nm average difference, corresponding to 2.688. These values imply ~0.04−0.07% systematic error in calculated thickness.

Table 2. Mean values of difference map averages by material source and type, with corresponding calibrated group index.

Material Source | Material Type | Difference Average [μm] | ncal
A | Doped | -0.2476 | 2.692
B | Doped | -0.2169 | 2.691
C | Doped | -0.2351 | 2.692
D | Optical | 0.3064 | 2.688

Refractive Index Uniformity.

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Difference maps also reveal the spatial uniformity of the group index. While average offsets support global calibration, the standard deviation and range of the maps quantify local variation within each wafer [Fig. 5].

[picture]

Fig. 5. Variation in wafer difference maps, shown as range (top) and standard deviation (bottom). Data are grouped by source (A-C: doped; D: optical), ingot ID, and wafer ID. Wafers from Fig. 4 are highlighted.

Fig. 5. Variation in wafer difference maps, shown as range (top) and standard deviation (bottom). Data are grouped by source (A-C: doped; D: optical), ingot ID, and wafer ID. Wafers from Fig. 4 are highlighted.

Across all wafers, the variation shows a noise floor of ~70−80 nm in standard deviation and 0.5−0.7μ m in range. This baseline largely reflects scan artifacts (e.g., the horizontal feature in Fig. 4(b)) and residual misalignment between MSP and CWL maps. Wafer 279-4 [Fig. 4(a)] illustrates this baseline: its minimal within-wafer variation demonstrates the agreement achievable between MSP and CWL thickness in the absence of material inhomogeneities.

Excursions above this floor point to spatially varying optical effects not explained by measurement artifacts. These deviations are typically linked to microstructural features that alter the index. For wafer 104-3 [Fig. 4(b)], the basal facet region appears 100−200 nm thicker than the wafer bulk. Nanotopography maps [Fig. 6] confirm this is not true thickness variation: the facet appears in the thickness map but not in the Si-face topography. This indicates an optical artifact caused by index variation, corresponding to a local index ~0.001 lower than the bulk value.

[picture]

Fig. 6. Wafer 104-3 (a) thickness nanotopography and (b) Si face Nanotopography maps. The basal facet appears in (a) but not in (b), indicating an optical artifact rather than a true thickness variation.

Fig. 6. Wafer 104-3 (a) thickness nanotopography and (b) Si face Nanotopography maps. The basal facet appears in (a) but not in (b), indicating an optical artifact rather than a true thickness variation.

Index Validation Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Prism Coupling.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

To independently assess the bulk index observed with MSP measurements, we performed prismcoupling measurements on selected wafers using TE-polarized light at 632.8 nm . This provides the ordinary phase index, the most relevant parameter since MSP primarily probes this direction under normal incidence. Results for doped and optical-grade wafers, including basal facet regions where available, are shown in Fig. 7 and summarized in Table 3. Measured indices agree with literature values [5] to within 0.04%.

[picture]

Fig. 7. In-plane refractive index measured by prism-coupling refractometry at 632.8 nm for select wafers at multiple radial positions. The first nine samples are doped wafers (with basal facet measurements labeled "Dark Region"); the final two are optical-grade wafers.

Fig. 7. In-plane refractive index measured by prism-coupling refractometry at 632.8 nm for select wafers at multiple radial positions. The first nine samples are doped wafers (with basal facet measurements labeled "Dark Region"); the final two are optical-grade wafers.

Table 3. Literature and measured ordinary refractive index at 632.8 nm [5].

Measured | Literature Phase Index (o-ray) | 2.634
Doped Bulk | 2.633
Doped Basal | 2.632
Optical Bulk | 2.634

Measured index showed excellent uniformity across wafers, with typical within-wafer variations of ±0.0001, corresponding to ±20 nm effective thickness error in interferometric measurements. Localized deviations were observed in basal facet regions, where the index was reduced by ~0.001 : an order of magnitude larger than bulk variation. This corresponds to a thickness error of ~130 nm, consistent with estimates from wafer 104-3 [Fig. 4]. These results confirm that basal facets introduce small but measurable refractive index shifts, which can impact MSP-derived TTV.

Interferometry.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Difference maps provide useful insight, but they are limited by CWL resolution and scan/alignment artifacts. These limitations can be avoided by measuring index-independent thickness directly on the

MSP using the configuration shown in Fig. 1(b). Inserting an optical flat introduces additional surface pairs in the measurement stack, allowing both OPD and thickness to be independently measured. From these, an index map can be calculated across the wafer. Examples are shown in Fig. 8 for a doped wafer with a basal facet and for an optical-grade wafer.

[picture]

Fig. 8. Group index maps measured with an MSP at 950 nm using the configuration in Fig. 1(b). (a) Doped wafer 104-4, showing a large basal facet region with lower index than the wafer bulk. (b) Optical-grade wafer with highly uniform index.

Fig. 8. Group index maps measured with an MSP at 950 nm using the configuration in Fig. 1(b). (a) Doped wafer 104-4, showing a large basal facet region with lower index than the wafer bulk. (b) Optical-grade wafer with highly uniform index.

The doped wafer [Fig. 8(a)] exhibits a bimodal index distribution: 2.665 in the basal facet region and 2.666 in the wafer bulk (Table 4). These measurements, performed at 950 nm , differ slightly from earlier 830 nm data. The lower basal index is consistent with preferential dopant incorporation on basal facets during growth; n-type SiC index decreases with nitrogen concentration [7]. Using a single global index would introduce a ~130 nm thickness error, consistent with prism-coupling estimates.

Table 4. Literature and measured group index from the difference map method ( 830 nm ) and optical flat method (950 nm) [5].

| Wavelength
| 830 nm | 950 nm
Literature Group Index (o-ray) | 2.692 | 2.661
Measured | Doped Bulk | 2.692 | 2.666
Doped Basal | 2.688 | 2.665
Optical Bulk | 2.688 | 2.663

In contrast, the optical-grade wafer [Fig. 8(b)] shows high uniformity, with an average index of 2.663 and standard deviation of 0.0001 . This corresponds to a ±20 nm thickness error, indicating that a single calibrated global index can yield accurate thickness for high-quality optical wafers.

Optical Retardance.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Intrinsic stress in the SiC crystal manifests as stress-induced birefringence, which can be quantified and visualized [8, 9]. Optical retardance maps for the wafers in Fig. 8 (rotated 90∘ ) highlight stressinduced birefringence. For the doped wafer, a 12∘ tilt was applied to suppress intrinsic birefringence, isolating stress contributions. The map reveals a radial stress field: the center is nearly stress-free, while edges show stronger radial alignment. The maximum retardance ( ~12 nm ) corresponds to a birefringence of 3×10−5 for a 350μ m wafer: an order of magnitude smaller than the index variations measured with the MSP. The optical-grade wafer shows a similar maximum birefringence ( 2×10−5 for 500μ m wafer), but with improved uniformity, as most of the wafer remains at ~4×10−6.

This contrast indicates that stress in doped material is more localized and directional, whereas optical-grade material remains low, homogeneous stress. Although these stress signatures are small compared to index variation, they may reflect wafer thermal or mechanical history. Radial patterns could originate from growth gradients, while reduced stress in optical-grade material suggests improved processing. Further correlation of retardance with growth conditions and yield could clarify their significance.

[picture]

Fig. 9. Optical retardance maps of wafers from Fig. 8 shown as vector maps and heat maps (retardance in nm ). (a) Doped wafer with a radial stress field and higher edge retardance. (b) Optical-grade wafer with improved retardance uniformity (central data missing in stitched map).

Fig. 9. Optical retardance maps of wafers from Fig. 8 shown as vector maps and heat maps (retardance in nm ). (a) Doped wafer with a radial stress field and higher edge retardance. (b) Optical-grade wafer with improved retardance uniformity (central data missing in stitched map).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

The MSP provides rapid, high-resolution wafer measurements with excellent repeatability, far exceeding CWL throughput. Bulk refractive index uniformity was stable, introducing only ±20 nm thickness error when a single global index is applied, and localized deviations near basal facets produced errors ~100−200 nm. Though small relative to wafer thickness, these effects show that local inhomogeneities can bias results if overlooked. MSP offers a robust, scalable approach for SiC wafer metrology if index calibration and awareness of local variations are maintained.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

J. Wang et al., Optical characterization of high refractive index glass wafers for augmented reality wearables, Optical Interference Coatings Conference (2019).

T. Dunn, C. Lee, M. Tronolone, and A. Shorey, Characterization of wafer thickness uniformity during 3D-IC processing, IEEE 62nd Electronic Components and Technology Conference (2012).

G. Lim, T. Manzur, and A. Kar, Improved optical properties and defectivity of an uncooled silicon carbide mid-wave infrared optical detector with increased dopant concentration, J. Opt. 14, (2012) 105601.

FlatMaster MSP for augmented reality waveguides, Corning Tropel Applications (2019).

S. Wang et al., 4H-SiC: A new nonlinear material for infrared lasers, Laser Photonics Rev. 7 (2013) 831-838.

"Effective index", Sellmeier coefficients, and glass thickness measurements on FM-MSP, Corning Tropel Applications (2024).

T. Bosma et al., Broadband single-mode planar waveguides in monolithic 4H-SiC, J. Appl. Phys. 131(2) (2022) 025703.

K. Gomi et al., Residual stress estimation in SiC wafer using IR polariscope, 2008 International Conference on Electronic Materials and Packaging (2008).

V. Ganapati et al., Infrared birefringence imaging of residual stress and bulk defects in multicrystalline silicon, J. Appl. Phys. 108 (2010) 063528.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 55-61

doi: 10.4028/p-np1tSH

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-28

Accepted:
2026-02-26

Online:
2026-05-21

Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

Tamara Fidler 1,a* and Patrick Schmid 1, b

1 Centrotherm International AG, Württemberger Str. 31, 89143 Blaubeuren, Germany

a*tamara.fidler@centrotherm.de, b  patrick.schmid@centrotherm.de

*corresponding author

Keywords: high temperature SiC oxidation, oxide thickness distribution, vertical oxidation furnace, cover wafer effect.

Abstract

H}-\mathrm{SiC}) wafers were processed in thermal oxidation furnace and impact of oxidation temperature up to 1500∘C, processing pressure and different gaseous ambient on oxide thickness distribution was investigated. Beside the impact of thermal distribution within oxidation furnace, an additional effect on oxide thickness distribution has been observed, due to promotion of oxidation rate in the center of the wafer. Within this work, we have examined which influence processing parameters have on described effect, specific for SiC oxidation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

Vertical furnaces are essential tools for implant anneal as well as thermal oxidation processes in high-performance mass production SiC device manufacturing lines. The thermal distribution in these tools is thoroughly studied by different temperature measuring methods and simulations and specified by manufacturer [1]. Likewise, due to vital role of thermal oxidation and oxide quality in SiC device production, thermal oxidation kinetics and mechanism have been a topic of numerous experimental and theoretical studies [2-4]. However, until now there is no comprehensive study of impact of different ambient and cover wafer conditions on oxide thickness distribution on SiC substrate in thermal oxidation production furnaces.

The design of the furnace for thermal oxidation is the determining factor for oxide thickness distribution. Specifically, the thermal distribution is defined by furnace configuration (the number, dimensions and location of heaters and insulation parts) and its temperature measurement and control system. Also supply and ventilation systems that have impact on ambient distributions inside the process chamber are of importance. The oxidation furnaces used in this work are state-of-the-art production tools. The temperature measurement and control are executed by pyrometers, which are profiled with thermocouple up to the highest oxidation temperature of 1500∘C. The power monitoring ensures processing stability over long time periods. There are different possibilities how temperature distribution inside of a furnace can be determined. Apart from pyrometrical measurements on the surface of the chamber and measurements with thermocouples inside of the processing chamber, one of the conventional methods to determine the thermal distribution of oxidation furnace can be measurement of oxide uniformity on the processed wafer. With known temperature sensitivity, oxide thickness distribution can be converted to temperature distribution. Within this study, another influence on oxide thickness has been observed for thermal SiC oxidation process in conjunction with covered or stacked wafers, which neither matches the thermal distribution pattern nor can it be explained by the consumption or depletion of oxygen and expectations based on published SiC oxidation mechanism [2-4]. Furthermore, influence of different ambient parameters on observed center accentuated distribution has been investigated.

Experimental

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Oxides were grown on n-type 150 mm or 200 mm SiC wafers with Si-face front surface and Cface rear surface orientation, with 4∘ miscut angle, using centrotherm's vertical production furnace c.OXIDATOR 150 or c.OXIDATOR 200. After tube evacuation, a process pressure in a range between 100 to 890 mbar is set with defined gas flow of diluted oxidation gas mixture. In this study oxygen, nitrogen monoxide or carbon dioxide were used as oxidation agents. Nitrogen or argon were used for dilution. The wafers were heated to target oxidation temperature. In described experiments temperature range from 1150∘C−1500∘C was investigated. The ramp rate to target temperature was 10 K/min. At targeted temperature, gas flow was set to tested pure gas or mixture and temperature was maintained for a defined time. Oxidation time was chosen to reach desired oxide thickness in a range up to 60 nm . At the end of the oxidation step, the heating was turned off and the tube was evacuated and refilled with nitrogen. Afterwards wafers were cooled down to 350∘C in free fall cooling.

The oxide thickness on Si wafers was determined with laser ellipsometry measurements on a Plasmos SD4000 laser ellipsometer at wavelength of 633 nm . The oxide thickness on SiC wafers was determined with spectral ellipsometry measurements on a Sentech SE800 spectral ellipsometer in a wavelength range of 280−370 nm. The angel of incidence was 70∘. A two-layer structure was assumed as the analysis model, consisting of SiC/SiO2.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

According to the thermal distribution of the furnace, wafer loading position inside of furnace will impact the oxide distribution. During the ramp, steady state and cooldown, the thermal distribution inside of the furnace will change. How much the change of thermal distribution in furnace during one processing run will impact the final oxide thickness distribution, depends on oxide growth rate in each of these stages. For observation of oxide thickness distribution across the wafer and easier comparison which influence various parameters have on the distribution, we have chosen center-toedge oxide thickness ratio (C/E), described in Eq. 1.
CE=SiO2 thickness wafer center SiO2 thickness wafer edge .

By observing C/E ratio, we can easily distinguish if we have center-accentuated e.g. hill distribution ( C/E>1 ) or edge-accentuated e.g. bowl oxide distribution ( C/E<1 ) on the wafer.

In figure 1. silicon and silicon carbide oxide distributions processed in different positions inside of the process are presented as illustrated by center-to-edge ( C/E ) oxide thickness ratios. The tested oxidation condition in this example is 1350∘C processing temperature, in pure oxygen atmosphere with 18 minutes steady state time is identical for silicon and silicon carbide wafers. The oxidation rates of silicon and C -face SiC is faster than the oxidation rate of Si -face SiC . This processing condition grows approximately 50 nm oxide on Si -face SiC e.g. 170 nm on Si or 110 nm on C -face SiC, due to different oxidation rates of these substrates.

[picture]

Fig. 1. Ratio of oxide thickness in the center vs. edge of the wafer ( C/E ) for Si and 4H−SiC substrates.

Fig. 1. Ratio of oxide thickness in the center vs. edge of the wafer ( C / E ) for Si and 4 H − S i C substrates.

On silicon wafer, oxide distribution is mostly flat ( C/E close to 1 ), with slight bowl distribution at bottom positions of the boat and slight hill distribution in upper boat positions. C/E ratio of oxide on C -face follows the same trend and is mainly influenced by thermal distribution inside of the chamber. C/E ratio of oxide grown on Si -face is significantly different to C/E ratio from other two substrates. There is an obvious additional impact that promotes oxide growth in the center of the wafer more than on the edge, which is not in direct correlation with temperature distribution across the wafer nor within the expected ambient distribution in the chamber. We would like to point out that the oxide thickness measurements from Si -face and C -face oxide layers are determined on the same wafer and therefore confirm that temperature distribution is not origin of center-accentuated oxide distribution on Si -face SiC . The gas inlet and outlet are located at the opposite side of the process chamber, and liner tube directs the flow from the bottom towards top of the chamber, with main flow path between liner wall and wafers. Consequently, the gas exchange between wafers is mainly driven by the diffusion and relatively low. Limited ambient exchange could lead to depletion of oxidant species in the center area between wafers. This would result in lower thickness in the middle of the wafer and therefore C/R ratio below 1 , because oxidation rate scales with the square root of the oxygen partial pressure [5]. Also, it would be expected that accumulation of carbon monoxide as byproduct of SiC oxidation, would also further dilute the oxygen ambient leading to lower oxidation rate in the wafer center, which is clearly not the case here.

Further evidence that the observed oxide thickness pattern on Si-face is not temperature distribution related is depicted in figure 2, showing the impact of distance between processed wafers in the chamber and the covering wafer material type.

[picture]

Fig. 2. C/E ratio for 4H−SiC substrates with different wafer coverage.

Fig. 2. C / E ratio for 4 H − S i C substrates with different wafer coverage.

In conventional production, the wafers are processed in vertical furnace with Si-face pointing up. In this case each Si -face is pointing towards C -face of 4H−SiC wafer. For test in figure 2. (left) two runs were executed with 18 minutes steady state at 1350∘C oxidation temperature. In first run two wafers were placed in the same area of the processing chamber face-to-back and in the second run face-to-face so that Si -face is turned towards Si -face of the adjacent wafer. C/E ratio of the uncovered wafer is additionally shown for comparison. Since the wafers in both runs were processed in a same way with the same number of wafers, loaded in the same boat positions and therefore with thermal mass remaining equal in both runs, the thermal distribution across the wafer is in these two runs is identical and flow pattern of incoming pure oxygen gas is matching as well. Unexpectedly, the thickness in the center is significantly higher, if the processed SiC wafer is covered with C -face, with respect to covering of processed wafer with Si -face SiC . Since there is a clear relation to occurrence of the elevated oxidation rate and covering of the wafer, we can postulate that the observed cover wafer effect is most probably ambient related. In another test, shown in Fig. 2 (right) same processing condition was performed but Si-face of SiC wafer was placed below silicon wafer, which still had slight influence on the oxide thickness in the center of the wafer. Uncovered wafer situation is a reference value for each example, depending on thermal distribution in respective loading position in the processing chamber e.g. boat slot and therefore different in (left) and (right) example.

In the next experiment, shown in figure 3, very big influence of oxidation temperature on cover wafer effect can be observed. Remarkably, if we compare C/R ratio of Si -face 4H−SiC substrate processed at 1150∘C to substrate processed at 1350∘C in pure oxygen, the cover wafer effect is substantially bigger at lower temperature. The experiment with diluted oxygen mixture in figure 3. (right) demonstrates same temperature behavior. Oxidation times for experiments is figure 3. were chosen to grow approx. 50 nm oxide on Si -face of 4H−SiC, therefore oxidation time at lower temperature was longer.

[picture]

Fig. 3. C/E for Si -face 4H−SiC substrates covered with C -face 4H−SiC or uncovered at different temperatures for pure (left) and diluted oxygen (right).

Fig. 3. C / E for Si -face 4 H − S i C substrates covered with C -face 4 H − S i C or uncovered at different temperatures for pure (left) and diluted oxygen (right).

It must be considered that oxide is partially grown during ramp-up period and with higher oxidation temperature more oxide grows during ramp-up. During ramp-up the wafer edge in a stack of wafers is expected to be colder at the edge of the wafer. Also, in this case we can use uncovered wafer situation as a reference value, which relates better to thermal distribution of different processes to distinguish thermal from ambient related effects, to conclude that effect on higher oxidation rate in the wafer center is clearly higher at lower temperature but not due to thermal distribution.

The strong dependency of elevated oxidation rates in the middle of the wafer to temperature as well as strong effect from covering of wafer with C-face lead to assumption that might be explained by the higher amount of generated oxidation byproducts, due to much higher oxidation rate of C -face in relation to Si -face at 1150∘C [5, 6], are causing observed effect. It's unclear if presence of COx
byproduct of C -face SiC oxidation is catalyzing SiC oxidation on Si -face of neighboring wafer or if elevated oxidation rates are caused by improved diffusion of oxidant through oxide. In both cases, concentration of oxidation byproducts is center accentuated under tested pressure and flow conditions and contributes to observed center to edge thickness distribution.

Change of the oxide thickness across the wafer length is exemplary illustrated for 1200∘C oxidation temperature for covered and uncovered sample in figure 4. As has been explained above, at 1200∘C covering effect is more pronounced, hence it is convenient for observation of oxidation time and thickness influence on spatial distribution. Oxide thickness distribution across the uncovered wafer (full symbols) is similar for different wafer thicknesses and is mainly impacted by temperature distribution during steady state at 1200∘C and placement in the central position of the boat. On the contrary, oxide distribution across the covered wafer (empty symbols) is center accentuated and is getting more pronounced with higher thickness.

[picture]

Fig. 4. Spatial oxide thickness distribution across the covered (empty symbols) vs. uncovered wafer (full symbols) for different oxidation times of Si-face 4H−SiC oxidation at 1200∘C in pure oxygen illustrated as oxide thickness at measured position on the wafer relative to mean oxide thickness of covered wafer.

Fig. 4. Spatial oxide thickness distribution across the covered (empty symbols) vs. uncovered wafer (full symbols) for different oxidation times of Si-face 4 H − S i C oxidation at 1200 ∘ C in pure oxygen illustrated as oxide thickness at measured position on the wafer relative to mean oxide thickness of covered wafer.

The oxide thickness growth of uncovered Si -face wafers as well as covered and uncovered C -face 4H−SiC at 1200∘C fits well with the model for SiC oxidation based on Deal-Grove model with Massoud's empirical corrections for thin oxides, implemented in the process simulator Sentaurus Process [5], as shown in figure 5. Oxidation rate of covered Si -face 4H−SiC wafers is higher than values predicted by the model in examined thickness range.

[picture]

Fig. 5. Oxide thickness as a function of time for Si -face (left) and C -face (right) 4H−SiC oxidation at 1200∘C in pure oxygen. Experimental data for covered and uncovered substrates, indicated by symbols, are compared to data obtained by SiC oxidation process model published by Zechner et al. [5], indicated by full line.

Fig. 5. Oxide thickness as a function of time for Si -face (left) and C -face (right) 4 H − S i C oxidation at 1200 ∘ C in pure oxygen. Experimental data for covered and uncovered substrates, indicated by symbols, are compared to data obtained by SiC oxidation process model published by Zechner et al. [5], indicated by full line.

Furthermore, we have investigated influence of different gaseous ambient, on described enhanced growth in the center of the wafer, as demonstrated in figure 6. On the left side we see example of oxide distribution in different ambientes for thin oxides around 5 nm , which are thinner in the middle of the wafer and example for growing 50 nm thick oxide in carbon dioxide on the right side. With change of ambient due to altered oxidation mechanism [7, 8] and absence of species essential for oxidation rate enhancement, we have influenced the growth in the middle of the wafer.

[picture]

Fig. 6. C/E ratio comparison for covered and uncovered wafers processed in different gaseous ambient at 1400∘C for oxide thickness around 5 nm (left). C/E ratio comparison for wafer covered and uncovered wafers processed in pure carbon dioxide at 1450∘C for oxide thickness around 50 nm (right).

Fig. 6. C/E ratio comparison for covered and uncovered wafers processed in different gaseous ambient at 1400 ∘ C for oxide thickness around 5 nm (left). C/E ratio comparison for wafer covered and uncovered wafers processed in pure carbon dioxide at 1450 ∘ C for oxide thickness around 50 nm (right).

Since changing oxidation parameters (temperature, pressure, oxidant species or concentration) may impact quality of oxide and increasing space between wafers would impact the throughput of the tool, another approach is recommended to improve oxide uniformity in SiC oxidation process. Diminishing COx byproduct concentration with preventing or reducing oxidation rate on C -face by protective layer is a viable approach in a case when higher oxidation temperature or ambient change are not possible. Deposition of silicon nitride, silicon dioxide or poly silicon can be considered as possible options.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

In conclusion, we have presented empirical oxide thickness data for crucial ambient parameters that have to be considered for optimization of oxide uniformity of thermal oxidation furnace for SiC substrates. We have reported unexpected, elevated oxidation rates, which are in contradiction with low oxidant concentration between wafers expected for described flow pattern in the furnace. Based on observed temperature dependence and wafer coverage dependence we have proposed explanation for observed behavior as well as preventing measures against it.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

P. Schmid, ECSCRM 2020-2021, Industrial Session: c.ACTIVATOR 200 & c.OXIDATOR 200 (2021).

V. Šimonka, A. Hössinger, J. Weinbub, S. Selberherr, J. Appl. Phys. 120 (2016) 135705.

D. Goto, Y. Hijikata, J. Phys. D: Appl. Phys. 49 (2016) 225103.

N. S. Jacobson, D. L. Myers, Oxid. Met. 75 (2011) 1.

C. Zechner, A. Johnsson, T. Fidler, P. Schmid, Phys. Status Solidi A 217 (2024) 2400234.

D. Goto, Y. Hijikata, S. Yagi, H. Yaguchi, J. Appl. Phys. 117 (2015) 095306.

R. Deguchi, T. Hosoi, ICSCRM 2023, Thermal oxidation of surface in a pure ambient (2023).

S. A. Corrêa, C. Radtke, G. V. Soares, L. Miotti, I. J. R. Baumvol, S. Dimitrije, J. Han, L. Hold, F. Kong, F. C. Stedile, Appl. Phys. Lett. 94 (2009) 251909.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 63-68

doi: 10.4028/p-92Xjcg

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-19

Accepted:
2026-02-23

Online:
2026-05-21

Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

1 Rena Technologies GmbH, Hoehenweg 1, D-78148, Guetenbach, Germany

2 School of Engineering, University of Warwick, Coventry, CV47AL, UK

a  norbert.bay@rena.com, b  Athul.Rathnakar@warwick.ac.uk, c  Xavier.gay@rena.com, d wyatt.engler@rena.com, e rahim.hamid@rena.com, f franck.delahaye@rena.com, g  Oliver.Whear@rena.com, h  vishal.shah@warwick.ac.uk, 'holger.kuehnlein@rena.com

*Corresponding author: franck.delahaye@rena.com

Keywords: SiC, silicon carbide, wet etching, strain relief, wet processing, substrate engineering.

Abstract

Strain relief etching is a critical wet process technique use in high volume manufacturing of semiconductor substrates and device wafers. The goal of a strain relief etch is application dependent but can generally be considered for removal of warp/bow or improving mechanical strength by removing sub-surface damage thereby optimizing yields. Silicon Carbide (SiC) has a high chemical resistance which has blocked SiC wafer manufacturers from using strain relief etching to date. In this work, we demonstrate strain relief etching using an Advanced Chemical Etching (ACE) process of the full wafer surface on commercial grade 4H−SiC wafers and poly- SiC wafers at high etch rates ( μ m's/hr) which enable ACE as a production technique. The data shows a 4 times improvement of breakage strength, from 13 to 55 N , in laser split wafers. Bow and warp of ground wafers is reduced from 70/250μ m to −5/25μ m approx. respectively, matching Chemical Mechanical Polished (CMP) wafers which is the industrial method for preparing wafers. Thus showing the potential of stronger, flatter wafers being available for chemical mechanical polishing.

Norbert Bay1,a, Athul Rathnakar2,b, Xavier Gay1,c, Wyatt Engler1,d, Rahim Hamid1,e, Franck Delahaye1,f⋆, Oliver Whear1,g, Vishal A. Shah2,h, Holger Kuehnlein1,i

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

1 Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

Wet chemical etching is a well-established process in the semiconductor industry, particularly for silicon-based wafer manufacturing. It plays a key role in device fabrication, substrate preparation, and surface conditioning due to its scalability, controllability, and compatibility with high-volume manufacturing. However, extending this technique to wide bandgap semiconductors such as silicon carbide ( SiC ) has proven challenging due to SiC 's exceptional chemical inertness. As a result, SiC substrates typically undergo aggressive mechanical processes-such as grinding and polishing-to achieve the desired thickness and surface flatness. These techniques can introduce significant subsurface damage, residual stress, and wafer bow or warp, especially early in the manufacturing line when wafers are thin and fragile[2,3]. Use of extensive mechanical techniques is also expensive and difficult to perform at volume where wafers are fragile early in the substrate manufacturing line. Research has explored mechanisms of wet etching for creating microstructures on 4H−SiC[4] and trenches in 6H−SiC [5].
ACE performs wet etching of 4H−SiC in an innovative approach. The ACE technology allows controlled material removal in a single-sided processing set-up with no edge exclusion with material removal rates between 15 and 20μ m/h.
We also postulate that one of the primary applications of ACE on SiC wafers is strain relief etching, where the removal of damaged and strained surface layers leads to reductions in bow and warp, and a marked improvement in mechanical strength. This is particularly beneficial prior to downstream steps such as chemical mechanical polishing (CMP), where wafer flatness and stress state directly impact process yield and wafer survival.
In this study, we investigate the effects of ACE strain relief etching on commercial-grade n+ type SiC wafers. The focus is on providing evidence of the strain-relieving properties of the ACE and
quantifying any improvements in mechanical strength and wafer shape (bow/warp) achieved through ACE processing. A combination of metrology techniques is used to characterize the impact of the process.

2 Methodology

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

Sample Description

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Samples were obtained from SiC wafer manufacturers, which have undergone wafer cutting with wire-sawing or laser-splitting and coarse grinding. Wafers were 150 mm in diameter, nominally (0001) orientated with a 4 deg offcut, 350μ m thick and doped with Nitrogen so that the resistivity was 10−20mOhm.cm. In addition, wafers after laser-splitting were processed as well. Finally, 4 H monocrystalline wafers as well as poly-SiC substrates both thinned with backside-grinding were obtained from another commercial supplier.

Characterization Techniques Used

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

To assess the strain relief and damage removal capabilities of ACE on 4H−SiC wafers.
Stress/Strain was compared using:

Laser scatterometry (Onto Primascan) for visualization of grinding-induced surface damage.

X-ray topography (XRT) using the Rigaku Micron 3-300 in reflection mode to assess subsurface strain. Instead of typical plan view images, cross sectional images were obtained to demonstrate the surface effect.
Thickness of removed material was measured by weighing the wafers before and after the etching with a laboratory scale. Wafer breakage strength was measured on a 3-point bending set-up.

3 Results and Discussion

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Here we characterise ACE etching on three important components of SiC technology: 1) standard processing of monocrystalline wafers, 2 ) new laser split monocrystalline wafers and 3 ) device wafers which are thinned as the final step on both monocrystalline and polycrystalline wafers.

Impact of ACE on Strain in Ground Monocrystalline 4H-SiC Wafers

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In this section we show the comparison of laser scatterometry images and XRT images captured in reflection mode before and after the 3μ m ACE etch on commercial coarse ground 4H−SiC wafers

Laser Scatterometry

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Prior to etching [Fig. 1a], the typical wafer surface displays a dense pattern of radial grinding marks, typical of mechanical thinning processes and indicative of residual surface stress and microcracking. After etching [Fig. 1c], these features are significantly reduced or eliminated, suggesting effective removal of the mechanically damaged surface layer. This result implies a more uniform surface stress profile and is consistent with strain relief from the etching process.

Subsurface Strain Mapping with XRT

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The pre-etch wafer [Fig. 1b] exhibits a dark linear feature near the surface-this line corresponds to a region of high strain effects introduced by coarse grinding. After the 3μmACE etch [Fig. 1d], this feature is completely absent, suggesting that the strained layer has been removed and the near-surface lattice has relaxed. This behaviour is additionally underlined by the XRT cross section scan [Fig. 1e]: while the scan of the ground wafer exhibits large strain peaks close the the wafer surface, these are reduced almost down to bulk level in the etched wafer.

[picture]

Fig. 1. Laser scatterometry images of 6′′SiC wafers (a) before and (c) after 3μ m ACE etching. Grinding marks are largely diminished post-etch, indicating reduced surface strain and damage. Cross-sectional XRT images (b) before and (d) after 3μ m ACE etching. The high-strain layer present in the unetched wafer is fully relieved post-etch. Large peaks witnessing the high amount of subsurface strain after grinding in the XRT cross-section scan (e) almost completely disappear after etching.

Fig. 1. Laser scatterometry images of 6 ′ ′ S i C wafers (a) before and (c) after 3 μ m ACE etching. Grinding marks are largely diminished post-etch, indicating reduced surface strain and damage. Cross-sectional XRT images (b) before and (d) after 3 μ m ACE etching. The high-strain layer present in the unetched wafer is fully relieved post-etch. Large peaks witnessing the high amount of subsurface strain after grinding in the XRT cross-section scan (e) almost completely disappear after etching.

Enhancement of Mechanical Strength on Laser Split Monocrystalline 4H-SiC Wafers

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To evaluate the mechanical benefits of ACE following laser splitting, a batch of 6-inch 4H-SiC wafers was subjected to ACE etching with a removal depth of 5μ m. The mechanical robustness of the as split and etched wafers was assessed via 3-point bend breakage testing. For comparison, a control group of wafers underwent coarse backside grinding instead of ACE etching.
Figure 2 presents the break force results across the three conditions: post-laser split (no treatment), post-coarse grind, and post-ACE etch. The as-split wafers exhibit low break strength, with values around 13 N. Following ACE etching, the breakage force increases by a factor of four, reaching values above those achieved by coarse grinding ( ~40 N vs. ~50−60 N ). This substantial improvement indicates that ACE etching effectively strengthens the wafer against mechanical failure, likely by smoothing out the sharp surface features of the post-laser-split surfaces.
This indicates that integrating a 5μ m ACE etch immediately after laser splitting can significantly improve wafer robustness and reduce breakage rates in subsequent handling or grinding operations.

3-pt Bend Break Force vs Process Step

Fig. 2. 3-point bend break force measurements for SiC wafers after laser splitting, after coarse grinding, and after 5μ m ACE etching. ACE-treated wafers show the highest mechanical strength.

Reduction of Bow and Warp Through ACE Etching After Grinding

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To assess the impact of ACE on wafer shape distortion, 25 6-inch SiC wafers were first subjected to frontside (Si face) grinding. The wafers were then split into two groups: Group A ( 20 wafers) underwent ACE etching with a removal depth of 5μ m, while Group B ( 5 wafers) was processed through chemical mechanical polishing (CMP) as a control.
Figure 3 illustrates the evolution of bow and warp through the sequence of process steps. After grinding, wafers show significant shape distortion, with bow values exceeding 100μ m and warp values reaching ~250μ m. However, after ACE etching, both bow and warp are reduced to levels comparable to those achieved with CMP.
This significant reduction in mechanical distortion confirms that ACE etching effectively removes the stressed and damaged surface layer introduced by grinding. By eliminating this strain, ACE restores flatness and dimensional stability to the wafers and this way provides a better starting point for the following CMP processing.

[picture]

Fig. 3. Bow and warp measurements of 6′′SiC wafers after grinding, ACE etching (Group A), and CMP (Group B). ACE etching reduces both parameters to the level of the CMP control group.

Fig. 3. Bow and warp measurements of 6 ′ ′ S i C wafers after grinding, ACE etching (Group A), and CMP (Group B). ACE etching reduces both parameters to the level of the CMP control group.

Implementation of ACE on Wafers after Backside Thinning

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Warp and Bow reduction

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To evaluate the effectiveness of ACE etching wafers after backside grinding, two types of 6-inch SiC substrates - 4H−SiC monocrystalline and poly-SiC - were processed. The monocrystalline wafer carried front-side devices, the poly wafer was still blank on both sides. Both were subjected to backside grinding to thin the substrate. Subsequently, a backside ACE etch was performed, removing residual damage.
Figure 4 shows the resulting bow and warp values before and after ACE etching.

On the 4H−SiC wafer, warp was slightly reduced from 399μ m to 317μ m. However, bow changed significantly - from −202μ m to +315μ m. This suggests that the compressive stress introduced by grinding was effectively removed from the backside, leaving the tensile stress from the front-side device layers dominant. This implies that partial etching, leaving some compressive stress on the backside, might yield a flatter wafer overall.

On the poly-SiC wafer, both warp and bow were significantly reduced - warp dropped from 886μ m to 85μ m, and bow from −260μ m to +34μ m. This indicates effective stress relaxation and damage removal on this wafer type through ACE.
These results highlight the importance of stress balancing in post-thinning processes and demonstrate the potential of ACE to improve wafer flatness on complex device wafers.

[picture]

Fig. 4. Effect of ACE etching on warp and bow for 4H−SiC device wafer and poly- SiC substrate after backside grinding. ACE etching leads to significant improvements in flatness, especially on poly-SiC material.

Fig. 4. Effect of ACE etching on warp and bow for 4 H − S i C device wafer and poly- SiC substrate after backside grinding. ACE etching leads to significant improvements in flatness, especially on poly-SiC material.

4 Conclusion

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ACE technology enables effective strain relief in SiC wafers through wet etching. It significantly improves wafer strength after laser splitting, flattens ground wafers to levels comparable to CMP, and reduces strain-induced distortion in device wafers. Optical and structural characterization confirms the removal of sub-surface damage and residual stress. These findings highlight the potential of ACE for enabling more robust, cost-effective, and high-yield SiC wafer processing. While these findings are encouraging, further work is needed to evaluate long-term device performance and the integration of ACE into high-volume manufacturing environments.
The results demonstrate that ACE etching enables production-scale wet processing of SiC, opening new pathways for cost-effective, high-throughput manufacturing of SiC substrates and devices.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

Yole Développement, Wafer Starts for More Than Moore Applications report, April 2023.

Moeggenborg K, Kegg T, Parfeniuk C, Stoney T, Quast J. Effect of Surface Damage on SiC Wafer Shape. MSF 2015; 821-823: 545-8. https: -doi-org.pugwash.lib.warwick.ac.uk/10.4028/www.scientific.net/msf.821-823.545.

Yang et al Journal of Manufacturing Processes, Volume 70, , October 2021, Pages 350-360.

Yang et al. ACS Appl. Mater. Interfaces. 2018 DOI: 10.1021/acsami.8b19557.

Chang et al. JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 15, NO. 3, JUNE 200.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 69-76

doi: 10.4028/p-onsJ9i

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-23

Revised:
2025-12-28

Accepted:
2026-02-23

Online:
2026-05-21

CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

The original version of this paper is available on https://www.scientific.net/MSF.1193.69.pdf

Georg Pfusterschmied 1,2,a*, Michael Kusolitsch 1,2, b and Christopher Zellner 1,2,c, Marco Perazzi 1,2, d, Tingqiang Yang 1,2,e, Ulrich Schmid 1,f

1 Institute of Sensor and Actuator Systems, TU Wien, Gusshausstrasse 27-29, 1040, Vienna, Austria

2 Christian Doppler Laboratory for Sustainable Silicon Carbide Technology, Gusshausstrasse 27-29, 1040 Vienna, Austria

a* georg.pfusterschmied@tuwien.ac.at, b michael.kusolitsch@tuwien.ac.at, c  christopher.zellner@tuwien.ac.at, d  marco.perazzi@tuwien.ac.at, et  ingqiang.yang@tuwien.ac.at, fulrich.e366.schmid@tuwien.ac.at

Keywords: electrochemical etching, pore nucleation, reactive ion etching.

Abstract

Electrochemical etching (ECE) of silicon carbide is a powerful route to porous 4H−SiC. Yet, reliable pore initiation on the Si-face typically requires additional sophisticated pre-conditioning (e.g. masked KOH etching, metal-assisted photochemical etching (MAPCE), focused ion beam (FIB) milling), limiting industrial adoption. We demonstrate a simple, CMOS-compatible pre-conditioning based on short reactive-ion-etching (RIE) steps ( 10−30 s,SF6/O2 ) that reproducibly nucleate pores on the Si-face of highly doped 4H−SiC (resistivity <0.02Ω· cm ) and enable homogeneous ECE in HF/ethanol without UV illumination. Surface roughness increases modestly with RIE time ( Ra≈1.3 nm to 4.0 nm ), while subsequent ECE does not significantly degrade topography. SEM cross-sections reveal continuous porous layers; image-based quantification shows enhanced vertical pore alignment with longer RIE duration. A stepwise voltage program ( 11.5 V→8.5 V→11.5 V ) yields stable current transients during etching. Eliminating noble metals and lithography reduces contamination risk. It improves process compatibility with front-end manufacturing while remaining synergistic with our previously established ECE process flows and high-temperature reorganisation of thin, porous SiC layers.

Introduction

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Porous semiconductors are essential for several processes in today's semiconductor industry, due to their unique properties as well as cost aspects. In silicon, electrochemical porosification followed by bonding, annealing, or selective dissolution is used at scale to implement ELTRAN® layer transfer for SOI [1] and to form sacrificial or architected layers in MEMS [2]. Extending the same strategy to silicon carbide would offer clear advantages for device operation at high temperature, or chemically aggressive media. Even more, the integration into process flows for power electronics would open up new possibilities [3], [4]. However, progress has been limited because the electrochemistry of SiC compared to silicon is more demanding, and the etching kinetics depend strongly on the exposed crystal face. Early work established that n-type 4H-SiC forms porous layers by photoelectrochemical etching (PECE) in HF electrolytes, with the Si- and C-terminated faces exhibiting substantially different oxidation as well as etching behaviours (e.g., C-face typically faster and yielding more columnar morphologies) [5], [6], [7].
To enable application-relevant morphologies and stacking, our group previously combined metalassisted photochemical etching (MAPCE) with PECE to tailor porosity depth profiles and avoid cap or skin layers [8]. We used this approach to demonstrate that single-crystalline, porous 4H−SiC foils can be released from the mother substrate and later be compactified by high-temperature annealing while preserving crystallinity. This is an analogue to silicon "reorganisation" used in ELTRAN® and related processes [9]. Notably, we scaled PECE foil release to 2-inch diameter areas. We verified single crystallinity by TEM after He-annealing up to 1600∘C, highlighting a viable path toward
substrate re-use and advanced SiC substrate concepts [10]. In parallel, we demonstrated controlled spalling of SiC using a Ni stressor layer anchored in MAPCE-generated surface porosity. This is another wafer-economical route that benefits from predictable, uniform near-surface microstructures [11]. But, all These developments point to porous-SiC-enabled integration strategies analogous to mature silicon technologies such as ELTRAN®, which rely on porous layers for bonding and controlled splitting. However, a persistent bottleneck in SiC is reliable, lithography-free pore nucleation on the Si-face in a manner compatible with CMOS contamination control. Common preconditioners include patterned KOH pits (silicon) [12], noble-metal seeding (MAPCE) [8], or FIB nanocavities [13]; in SiC, these either add topography, introduce metals, or lack throughput.
In this work, a reactive-ion-etching (RIE) pre-treatment is explored as a noble-metal-free approach for preparing the Si-face of 4 H -SiC prior to electrochemical etching. Short SF6/O2 RIE steps are applied before ECE, resulting in a controlled modification of the near-surface region. Fluorine-based plasmas are known to induce subtle nanoscale roughness, micro-masking effects, and chemical surface modifications, which can influence surface energy, wettability, and local electric fields [14], [15]. The following sections investigate how such an RIE pre-conditioning affects pore initiation behaviour during subsequent electrochemical etching, including its influence on current transients, pore morphology, and pore orientation. The study focuses on evaluating the suitability of this approach as a CMOS-compatible pre-treatment for Si-face porosification.
Finally, we want to place this approach in the broader context of porous-SiC manufacturing. Beyond layer transfer and substrate engineering, recent works have revisited ECE of SiC for optical mirrors [16] and MEMS membranes [17], while other groups explore architected 3D microstructures by combined dry/wet routes. These directions reinforce the need for pre-conditioning methods that are selective, scalable, and fab-compatible-requirements our RIE-assisted ECE approach directly addresses [18], [19].

Experimental Details

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Samples ( 2.5×2.5 cm2 ) were diced from 4 -inch, N -doped 4 H -SiC wafers ( 4∘ off-axis, Si-face roughness <0.1 nm, resistivity 0.02Ω· cm ) from SiCrystal. After an HF dip, they received reactive-ion-etching (RIE) in a parallel-plate plasma (STS) at 300 W with 25sccmO2 and 5sccmSF6 for 10, 20, or 30 s. ECE was performed in a tabletop AMMT cell (see Fig. 1) with the SiC piece acting as the separator between anodic and cathodic compartments; pore formation occurred at the side facing the cathode, in an aqueous solution of HF and ethanol ( 5.52 mol L−1HF,1.7 mol L−1 ethanol). No UV illumination was required due to the high electrical conductivity of the samples. A step-programmed bias was applied (first minute 11.5 V , then 8.5 V for 2 min , followed by 11.5 V for 1 min ) to manage nucleation and growth transients (see the current-time trace analogous to Fig. 2). More information about the ECE mechanism and setup is presented in Ref. [8]. Surface roughness was measured with a stylus profilometry (Bruker Dektak) and AFM (Bruker Dimension Edge). SEM (Hitachi SU8030) was used for plan-view and cross-section imaging. A custom Python/OpenCV workflow quantified pore alignment: pore cross-sections were segmented and clustered into orientation kernels, fitted by ellipses to extract principal axes, and visualised as polar histograms (see Fig. 5).

[picture]

Fig. 1. a) Optical photograph of the tabletop etching cell from AMMT, and b) illustration of the applied voltage profile during electrochemical etching.

Fig. 1. a) Optical photograph of the tabletop etching cell from AMMT, and b) illustration of the applied voltage profile during electrochemical etching.

Current-Time Curves for Different RIE Durations

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[picture]

Fig. 2. Typical current response during electrochemical etching of RIE pre-treated samples. The applied voltage in the first minute was 11.5 V , followed by 8.5 V for two minutes and again 11.5 V for one minute.

Fig. 2. Typical current response during electrochemical etching of RIE pre-treated samples. The applied voltage in the first minute was 11.5 V , followed by 8.5 V for two minutes and again 11.5 V for one minute.

Results

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When analysing samples exposed to 10 , 20 , and 30 s RIE steps, the arithmetic mean roughness increased from Ra≈1.3 nm(10 s) and 1.4 nm(20 s) to 4.0 nm(30 s) as listed in Table 1. After ECE, Ra values were 1.3, 1.5, and 5.2 nm , respectively. The corresponding Rq values followed the same trend, thus the ECE step did not measurably degrade surface quality beyond the RIE-imposed baseline. Fig. 3 illustrates the surface after 20 seconds of RIE treatment prior to ECE. The currenttime response exhibited characteristic plateaus/decays at each voltage level (11.5 V→8.5 V→11.5 V ), indicating controlled transitions from nucleation-dominated to growth-dominated regimes (Fig. 2). The final 11.5 V step restored a stable current consistent with sustained pore propagation.

Table 1. Roughness results gained from surface profilometry.

Surface roughness [nm] | Before ECE | After ECE
| Ra | Rq | Ra | Rq
10 s RIE | 1.3 | 1.9 | 1.3 | 1.6
20 s RIE | 1.4 | 1.7 | 1.5 | 1.8
30 s RIE | 4.0 | 6.2 | 5.2 | 5.9

[picture]

Fig. 3. Results from AFM analysis of a sample with 20 s RIE treatment before ECE.

Fig. 3. Results from AFM analysis of a sample with 20 s RIE treatment before ECE.

SEM plan-views before and after ECE (Fig. 4a-f) show the RIE-textured Si-face surface. The corresponding cross-sectional views are shown in Fig. 4 g -i, revealing continuous porosity across the processed depth. Residual flakes seen in plan-view originate from dicing tape and are not morphological features of the RIE process nor from the porosified SiC using ECE. Image analysis of cross-sectional SEMs showed a progressive narrowing of the angular distribution of pore axes with increasing RIE time (polar histograms in Fig. 5), i.e., longer RIE pretreatments yielded a higher fraction of pores aligned closer to the surface normal.

Discussion

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It is known from literature, that the Si -face is less reactive than the C -face. This demonstrated in multiple studies which show faster oxidation and higher etch rates under comparable conditions, which correlate with the prevalence of columnar pores on the C-face in PECE [5], [7]. Recent mechanistic analyses of SiC oxidation further indicate that the C -face develops thicker oxides within a given time frame and higher reaction currents than the Si -face, consistent with kinetically easier formation and/or removal of carbon-containing by-products on the C-face [20].

[picture]

Fig. 4. SEM micrographs of the sample surface and cross-sections before and after RIE pre-treatment with different etching durations: 10 s (left column), 20 s (middle column), and 30 s (right column). The top row (a-c) shows the surface morphology before electrochemical etching (ECE), the middle row ( d−f ) shows the surface after ECE, and the bottom row ( g−i ) presents the cross-sectional views after ECE. The flake-like structures shown in the top-view micrographs are residuals from the dicing tape.

Fig. 4. SEM micrographs of the sample surface and cross-sections before and after RIE pre-treatment with different etching durations: 10 s (left column), 20 s (middle column), and 30 s (right column). The top row (a-c) shows the surface morphology before electrochemical etching (ECE), the middle row ( d − f ) shows the surface after ECE, and the bottom row ( g − i ) presents the cross-sectional views after ECE. The flake-like structures shown in the top-view micrographs are residuals from the dicing tape.

Our data suggest that brief SF6/O2 RIE steps compensate this kinetic disadvantage of the Si-face by (i) introducing sub-nanometric roughness and micro-defect sites that act as local field concentrators and oxidation nuclei, (ii) modifying surface chemistry (fluorination/oxygenation) to lower the barrier for initial SiC oxidation in HF electrolytes, and (iii) improving electrolyte wetting and transport into nascent cavities, which is enhanced by ethanol in the electrolyte [14], [15], [21]. The outcome is a reproducible pore nucleation density that enables homogeneous ECE at moderate voltages, without UV. The observed current transients under the 11.5→8.5→11.5 V program are consistent with an initial field-assisted nucleation burst followed by growth stabilisation and a re-acceleration step to sustain front propagation. This control principle mirrors our prior MAPCE/PECE approach, where time-programmed potentials were used to engineer porosity gradients and avoid cap layer formation [8]. In highly doped n-type SiC, band-bending at the semiconductor/electrolyte interface already confines holes at the surface under forward bias, enabling UV-free ECE when contact/transport conditions are favourable. The sharpening of the pore-axis angular distribution with longer RIE (Fig. 5) implies a transition from lateral/branched to preferentially vertical growth as the density and uniformity of initiation sites increase. We ascribe this to a combination of (i) more uniform initial pit geometry and (ii) reduction of local lateral field inhomogeneities once a dense array of nearly equally spaced pits forms, leading to self-screening of lateral growth paths. This interpretation is consistent with prior observations that controlled initiation influences pore directionality and that facedependent kinetics reinforce vertical growth once nucleation is spatially homogeneous [8].

[picture]

Fig. 5. Binarised SEM cross-section images (a-c) and corresponding polar histograms (d-f) of porous structures after electrochemical etching of samples pretreated by RIE for 10 s(a and d),20 s( b and e ), and 30 s (c and f). The pore orientation was analysed using Python and OpenCV: pores were segmented and clustered into orientation-specific kernels, then approximated by ellipses to extract the main axis direction. The resulting angle distribution was visualised in polar histograms, revealing increasing pore alignment with longer RIE duration.

Fig. 5. Binarised SEM cross-section images (a-c) and corresponding polar histograms (d-f) of porous structures after electrochemical etching of samples pretreated by RIE for 10 s ( a and d ) , 20 s ( b and e ), and 30 s (c and f). The pore orientation was analysed using Python and OpenCV: pores were segmented and clustered into orientation-specific kernels, then approximated by ellipses to extract the main axis direction. The resulting angle distribution was visualised in polar histograms, revealing increasing pore alignment with longer RIE duration.

Compared with MAPCE pore nucleation, the RIE pre-treatment removes a significant contamination possibility (Pt/Au residues) and avoids lithography or FIB. It uses standard precursor gas chemistry ( SF6/O2 ) and short recipes compatible with front-end cleanliness protocols. In integration terms, the present method is complementary to our ECE-based foil release and high-temperature compactification: RIE-assisted ECE can pre-define homogeneous porous layers on the Si-face, after which ECE and post-annealing can yield homogeneously compactified, crystalline surfaces suitable for bonding to alternative carriers, similar to the ELTRAN® approach in silicon [10] [2]. The tradeoff between nucleation reliability and surface roughness is evident: 30 s RIE provides the best alignment but increases Ra to ~5 nm after ECE. We hypothesise that the benefit from RIE derives from two coupled factors: (i) nanoscale topography that locally concentrates the interfacial field and (ii) a modified near-surface chemistry/defect state that lowers the barrier for pore nucleation.

Summary

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We demonstrate a CMOS-compatible route to reliably initiate homogeneous pore formation on the Si -face of 4 H - SiC without noble metals or added lithography. A short O2/SF6 reactive-ion etch ( 10−30 s,300 W) raises the surface roughness from ~1.3 nm to ~4.0 nm, which is sufficient to seed uniform electrochemical etching in HF/ethanol (no UV required for highly conductive wafers). The increased roughness on the nanoscale correlates with (i) suppression of the initial current spike in the ECE transient, (ii) higher pore nucleation density with smaller pore diameter, and (iii) tighter poreorientation distributions, yielding laterally uniform porosification across cm-scale areas. AFM/SEM and cross-sectional image analysis confirm a progression from sparse, misoriented pores ( 10 s RIE) to dense, aligned morphologies ( 30 s RIE). Compared with MAPCE-based preconditioning, the proposed RIE step is simpler, contamination-resilient, and backend-compatible. It can be combined with established ECE processes to engineer porosity profiles for applications such as photonics, power electronics, or MEMS. Overall, controlled nano scaled roughness ( ~4 nmRMS ) is identified as a practical initiator for robust, homogeneous porosification even of the Si -face of 4H−SiC samples.

Further investigations will focus on the structural and chemical analysis using AFM, TEM, XPS and ToF-SIMS to identify the driving mechanisms of pore nucleation. Future investigations will be performed in a 3-electrode ECE setup to improve the validity of the current response.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1193.69.pdf

The financial support by the Austrian Federal Ministry for Labour and Economy and the National Foundation for Research, Technology and Development and the Christian DopplerResearch Association is gratefully acknowledged.

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The original version of this paper is available on https://www.scientific.net/MSF.1193.69.pdf

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M. Mokhtarzadeh, M. Carulla, R. Kozak, and C. David, 'Optimization of etching processes for the fabrication of smooth silicon carbide membranes for applications in quantum technology', Micro and Nano Engineering, vol. 16, p. 100155, Aug. 2022, doi: 10.1016/j.mne.2022.100155.

A. Hochreiter, F. Groß, M.-N. Möller, M. Krieger, and H. B. Weber, 'Electrochemical etching strategy for shaping monolithic 3D structures from 4H-SiC wafers', Sci Rep, vol. 13, no. 1, p. 19086, Nov. 2023, doi: 10.1038/s41598-023-46110-2.

G. Lee et al., 'Oxidation differences on Si - versus C -terminated surfaces of SiC during planarization in the fabrication of high-power, high-frequency semiconductor device', Sci Rep, vol. 13, p. 22847, Dec. 2023, doi: 10.1038/s41598-023-49622-z.

M. Ohmukai, M. Honda, Y. Kodama, H. Tsunekuni, and Y. Tsutsumi, 'The effect of chemical treatment on porous silicon: the role of alcohol', MRS Online Proceedings Library, vol. 737, no. 1, p. 39, Dec. 2002, doi: 10.1557/PROC-737-F3.9

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 77-82

doi: 10.4028/p-XZ6YqE

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-16

Accepted:
2026-01-31

Online:
2026-05-21

BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

Shunya Hirano 1,a*, Hyuk Kim 1,b, Satoru Takahashi 2,c, Shuzo Masui 2,d, Noboru Ohtani 3,e, Kozo Abe 3,f

¹Makino Milling Machine Co., Ltd., Engineering Development Group of LASER Business Division, 2-10-4 Nakane, Meguro-ku, Tokyo, 152-8578, Japan

2 The University of Tokyo, Dept. of Precision Engineering, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

3 Kwansei Gakuin University, School of Engineering, 1 Gakuen Uegahara, Sanda, Hyogo 669-1330, Japan

a*h iranosh@makino.co.jp, b kimh@makino.co.jp, c takahashi@nanolab.t.u-tokyo.ac.jp, d  masui.s@nanolab.t.u-tokyo.ac.jp, e  ohtani.noboru@kwansei.ac.jp, f  abekzw@outlook.jp

*corresponding author

Keywords: wafer dicing, water jet guided laser, laser ablation, basal plane dislocations.

Abstract

Silicon carbide (SiC) wafers are essential for next-generation power devices; however, conventional dicing methods often induce cracks and Basal Plane Dislocations (BPDs), reducing device reliability. This study demonstrates BPD-free dicing of epitaxial SiC wafers using Water jet Guided Laser (WGL) processing. Full-thickness cutting was performed on 350μ m-thick wafers with a 10μ m-thick epitaxial layer using a YAG laser ( 532 nm wavelength, 200 ns pulse width, 10 kHz repetition rate, 30−80 W output) on an LB300 system. BPD evaluation was carried out by X-ray topography (XRT) with the −1−128 reflection before and after cutting. The results showed no generation or propagation of new BPDs, and pre-existing BPDs did not glide, confirming that WGL processing enables BPD-free machining. These results are attributed to the ablation-based nature of WGL with water assistance, which avoids mechanical stress on epitaxial SiC wafers.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

Silicon carbide ( SiC ) wafers are increasingly used in next-generation power devices due to their superior power handling and efficiency characteristics. In SiC power devices, the epitaxial layer is particularly important because it is closely related to the active region where device operation occurs. Therefore, defects introduced into or propagated near the epitaxial layer during dicing may directly affect device performance and long-term reliability. For this reason, it is necessary to evaluate not only the macroscopic cutting quality, such as kerf width and chipping, but also the crystallographic quality of epitaxial SiC wafers after dicing [1]. Various dicing and separation methods, including ultrasonic-assisted wafer sawing and laser-based separation techniques, have been investigated for hard and brittle SiC wafers [2-4]. Although these methods are effective for chip separation, processinduced mechanical loading and thermal effects must be carefully considered in SiC device manufacturing. Therefore, achieving defect-free, particularly BPD-free, dicing remains a significant challenge. This study aims to demonstrate a BPD-free dicing technique for epitaxial SiC wafers using Water jet guided laser (WGL) processing. As illustrated in Fig. 1, WGL utilizes a high-pressure, micron-scale water jet as an optical waveguide for a pulsed laser beam, facilitating precise material ablation and simultaneous cooling [5]. The water jet confines and guides the laser beam due to total internal reflection within the jet, allowing the laser to maintain a tight focus over a longer working distance. This guidance effect reduces beam divergence and enables highly accurate, narrow kerf cutting. In addition, the water jet removes debris from the cutting area, preventing redeposition and thermal damage to surrounding material. The combination of optical guidance and cooling allows WGL to perform defect-free machining even on brittle or hard materials. Moreover, by adjusting the water pressure and jet diameter, the energy density of the laser at the workpiece can be precisely controlled, optimizing the ablation efficiency. While previous studies have shown that WGL did not
generate BPDs in bulk SiC, its applicability for dicing epitaxial layers has not yet been confirmed. In addition, the damage-free nature of WGL dicing was evaluated by analyzing XRT images of grooved SiC wafers from two directions and by performing EDX analysis on the cleaved surfaces. Although previous studies have evaluated WGL-grooved SiC wafers using XRT and EDX analysis [6-7], the effect of WGL full-thickness cutting on the BPD distribution of epitaxial SiC wafers has not been sufficiently investigated. Since XRT is effective for observing crystallographic defects such as BPDs in SiC wafers [8], the same area was examined before and after cutting in this study. This approach enables evaluation of whether detectable BPDs were newly generated or whether pre-existing BPDs propagated during WGL full-thickness cutting. In this study, WGL-based dicing is applied to epitaxial SiC wafers, and the resulting crystal quality is evaluated by X-ray topography (XRT).

[picture]

Fig. 1. Schematic illustration of WGL.

Fig. 1. Schematic illustration of WGL.

Method

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

A schematic view of WGL dicing is shown in Fig. 1, and the experimental flow for BPD evaluation is shown in Fig. 2. To evaluate whether WGL processing induced detectable new BPDs or caused the propagation of pre-existing BPDs, XRT observations were performed at the same position before and after cutting. In step (a), alignment markings were processed to enable positional correlation between the pre- and post-processing XRT images. In step (b), XRT observation was performed near the alignment markings before WGL cutting. In step (c), the SiC wafer was fully cut by WGL inside the marked region. In step (d), XRT observation was performed again at the same position after WGL dicing. The alignment markings were used as reference features to identify the same observation area before and after WGL cutting. The WGL cutting path was set inside the marked region so that the area surrounding the cut could be included in the XRT observation field. This arrangement allowed the BPD distribution near the full-thickness cutting region to be compared directly before and after processing. The XRT observation area was selected to include both the cutting region and the surrounding wafer area. Therefore, changes in BPD-related line contrasts could be evaluated with respect to the initial defect distribution of the wafer.

The wafer was mounted using dicing tape, and the working distance between the nozzle and the wafer surface was set to 10 mm . Full-thickness cutting was performed on a 350μ m-thick SiC wafer with a 10μ m-thick epitaxial layer using an LB300 system. The main WGL processing conditions are summarized in Table 1. BPD evaluation was conducted before and after WGL cutting at the same position using XRT with the −1−128 reflection. The XRT evaluation conditions are summarized in Table 2.

[picture]

Fig. 2. Process flow for BPD evaluation at the same position using XRT observation.

Fig. 2. Process flow for BPD evaluation at the same position using XRT observation.

(a) Alignment markings for position identification.
(b) XRT observation before WGL cutting.
(c) WGL full-thickness cutting inside the marked region.
(d) XRT observation at the same position after WGL cutting. The BPD distributions before and after processing were compared in the XRT observation area.

Table 1. WGL processing conditions used for full-thickness cutting of the epitaxial SiC wafer.

Item | Condition
Workpiece | Epitaxial SiC wafer
Wafer thickness | 350 μm
Epitaxial layer thickness | 10 μm
Machine | LB300, Makino Milling Machine Co., Ltd.
Laser source | YAG laser
Wavelength | 532 nm
Pulse width | Approximately 200 ns
Repetition rate | 10 kHz
Output power | 30–80 W

Table 2. XRT evaluation conditions used for comparing BPD distributions before and after WGL cutting.

Item | Condition
Evaluation method | X-ray topography
XRT system | XRTmicron, Rigaku Holdings Corporation
Reflection | -1-128
Exposure area | 8.0 mm × 6.0 mm
Pixel size | 2.3 μm

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

As shown in Fig. 3, XRT images were acquired before and after WGL full-thickness cutting to evaluate changes in the BPD distribution. The overview XRT images in Fig. 3(a) and (b) show the same observation area before and after processing. The overall distribution of line contrasts attributed to pre-existing BPDs was maintained after processing, and no significant change in the defect contrast was observed around the cutting region. This result indicates that no detectable generation or propagation of BPDs occurred within the XRT observation area. This stability of the BPD distribution was confirmed not only in a single observation area but also in multiple regions of the wafer. In addition, similar tendencies were observed for cutting directions rotated by 90 degrees, indicating that the absence of detectable BPD generation was reproducible under the present experimental conditions. These observations suggest that WGL processing can maintain the initial BPD distribution of epitaxial SiC wafers during full-thickness cutting. Specifically, Fig. 3(c)-(h) shows magnified XRT images of selected areas before and after processing, where no emergence or growth of BPDs was observed. The contrast in images (c)-(h) was adjusted to improve BPD visibility. In particular, images (c) and (d) confirm that no new BPDs were generated in areas initially free of BPDs, while images (e)-(h) demonstrate that even pre-existing BPDs ( δ,ε ) did not glide during processing. The absence of detectable BPD generation and propagation is considered to be related to the non-contact and water-assisted nature of WGL processing. Unlike blade dicing, WGL removes material mainly by laser ablation without direct mechanical contact with the wafer. In addition, the water jet assists cooling during processing. These characteristics can reduce process-induced mechanical loading and suppress excessive thermal influence around the cutting region, which is consistent with the stable BPD distribution observed by XRT.

[picture]

Fig. 3. XRT images of full-thickness cutting.

Fig. 3. XRT images of full-thickness cutting.

(a), (b) XRT images before and after processing.
(c), (e), (g) magnified XRT images of selected areas before processing.
(d), (f), (h) magnified XRT images of selected areas after processing. α−η indicate pre-existing BPDs. (Contrast was adjusted in (c)-(h) to enhance the visibility of BPDs.).

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

In this study, Water jet Guided Laser (WGL) processing was applied to full-thickness cutting of epitaxial SiC wafers. XRT evaluation before and after processing confirmed that no new Basal Plane Dislocations (BPDs) were generated and that pre-existing BPDs did not propagate or glide. These results confirm that WGL processing enables BPD-free machining by an ablation-based technique with water assistance that does not impart mechanical stress to epitaxial SiC wafers. Future studies will be directed toward optimizing the processing parameters and validating the technique under mass-production conditions for practical application in SiC power device fabrication.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

M. Skowronski et al., J. Appl. Phys. 99, 011101 (2006).

Y.H. Wang et al., Proceedings of CSS MANTECH (Denver, Colorado, USA, 2014), 271-274.

E. Ohmura et al., J. Achiev. Mater. Manuf. Eng., 17, 381-384 (2006).

A. Bauer, H. Ryssel, Mater. Sci. Forum, 821-823, 528-532 (2014).

B. Richerzhagen, U.S. Patent No. 5,902,499, May 11, 1999.

S. Kadoya et al., "Proposal of Damage-Free SiC Wafer Dicing Using Water Jet Guided Laser," Materials Science Forum, Vol. 1124, pp. 85-89, 2024.

S. Masui et al., "Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser," ICSCRM2024, pp. 666-668, Raleigh, NC, USA, 2024.

K. Omote et al., Rigaku Journal, Vol. 29, No. 1, pp. 1-8, 2013.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 83-88

doi: 10.4028/p-eyjUb3

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-02-27

Online:
2026-05-21

Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

Chen-Hang Wu 1,a, Chao-Jun Zhang 1,b, Shao-Yuan Huang 1,c and Chao-Chang A. Chen 1, d*

1 National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Rd., Taipei, 10607, Taiwan

ªM11103241@mail.ntust.edu.tw, bM11203203@mail.ntust.edu.tw, c M11303241@mail.ntust.edu.tw, d*artchen@mail.ntust.edu.tw

Keywords: fixed-abrasive lapping, electrochemical passivation, polarization curve, silicon carbide, wafer thinning.

Abstract

This study aims to develop an electrochemical assisted fixed-abrasive lapping (ECAL) process for thinning 4H−SiC wafers ( C -face). Process with 20wt%NaNO3 electrolyte to generate a softened passivation layer has been formed and simultaneously removed by a fixed diamond lap wheel. Electrochemical tests using a potentiostat have verified 20 V as the selected experimental potential, and a significant reduction in hardness has been confirmed by nanoindentation. Under these conditions, the 4-inch wafer has achieved a material removal rate (MRR) of 3.181μ m/h with wafer quality (Bow −7.80μ m, Warp 48.50μ m, TTV 7.70μ m ). When the same conditions have been applied to 6-inch wafers, an MRR of 2.457μ m/h and wafer quality (Bow −5.00μ m, Warp 36.70μ m, TTV 6.60μ m) have been obtained. These results have demonstrated the scalability of ECAL for larger SiC substrates, offering potential for next-generation device manufacturing.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

Monocrystalline silicon carbide ( SiC ) is a key material for high-power applications such as electric vehicles, renewable energy systems, and 5G communication technologies due to its wide bandgap, high thermal conductivity, and excellent breakdown field. To meet the packaging and reliability demands, wafer thinning becomes an essential process for improving heat dissipation capability and ensuring reliable device operation. However, conventional thinning processes often introduce subsurface damage (SSD) and residual stress, which have been identified as having negative impact on wafer quality and device performance. Therefore, an electrochemical assisted fixed-abrasive lapping (ECAL) process has been developed in this study, combining electrochemical reaction with mechanical removal of material, with the aim of reducing surface damage while improving process efficiency.

Research and Experimental Conditions

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

An electrochemical assisted fixed-abrasive lapping (ECAL) process has been developed for 4-inch and 6 -inch 4 H -SiC wafers, in which the wafer has been connected as the anode and the diamond lapping plate as the cathode. The process schematic and setup are shown in Fig. 1. A direct current has been applied through the electrolyte to form a passivation layer on the wafer surface, which has been simultaneously removed by the lapping plate during processing. Electrochemical characterization has been first carried out using a potentiostat to determine the potential and electrolyte conditions used in the subsequent ECAL experiments. Potentiodynamic polarization curves obtained in 20wt%NaNO3 at 70∘C have revealed a distinct passivation region, from which an applied potential of 20 V has been selected as shown in Fig. 2. Potentiostatic polarization tests further have indicated that at 20 V , the current density has the highest initial value and has rapidly decayed, resulting in a stable level within 60 s as shown in Fig. 3.
To investigate the mechanical effect of passivation, nanoindentation hardness tests have been conducted on untreated wafers and wafers after 20 V anodic polarization. For the untreated SiC wafer,
the hardness has been measured as 24.59 GPa and the Young's modulus has been measured as 271.56 GPa . Under the condition of 20 V , the hardness has decreased significantly to 1.50 GPa and the Young's modulus to 64.60 GPa , confirming the formation of a softened passivation layer as shown in Fig. 4. Although tests at 15 V and 25 V have also been performed, the 20 V condition has been selected for subsequent experiments, as it has revealed stable passivation behavior.

[picture]

Fig. 1. Schematic and experimental setup of ECAL process [2].

Fig. 1. Schematic and experimental setup of ECAL process [2].

[picture]

Fig. 2. Potentiodynamic polarization of SiC in 20wt%NaNO3 at 70∘C [2].

Fig. 2. Potentiodynamic polarization of SiC in 20 w t % N a N O 3 at 70 ∘ C [2].

[picture]

Fig. 3. Potentiostatic polarization of SiC at 20 V for 60 s [2].

Fig. 3. Potentiostatic polarization of SiC at 20 V for 60 s [2].

[picture]

Fig. 4. Nanoindentation load and displacement curve under 20 V [2].

Fig. 4. Nanoindentation load and displacement curve under 20 V [2].

The ECAL process for 4 -inch SiC wafers has been performed with a NaNO3 electrolyte concentration of 20wt%, an applied potential of 20 V , a head/platen rotation speed of 50/60rpm, and a down pressure of 3 psi , ensuring uniform and stable contact between the SiC wafer and the diamond lap wheel. To verify the scalability of the process, the same electrochemical and mechanical parameters have been applied to 6-inch wafers. The electrochemical mechanism is illustrated in Fig. 5.

[picture]

Fig. 5. Electrochemical reaction mechanism.

Fig. 5. Electrochemical reaction mechanism.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

Based on the electrochemical reaction studies of 4 H -monocrystalline silicon carbide ( 4H−SiC ), the electrolyte parameters have been determined to be 70∘C and 20wt%NaNO3 from potentiodynamic polarization experiments. Potentiostatic tests further have indicated that 20 V provides the highest and distinct passivation layer growth rate. Under these conditions, electrochemical assisted fixedabrasive lapping (ECAL) experiments have been carried out on 4 -inch SiC wafers using a #800 diamond lapping plate. The effects of down pressure and rotational speed on MRR and surface quality have been evaluated, as summarized in Table 1.

Table 1. 4-inch SiC wafer (C-face) ECAL parameters [2].

4-inch SiC wafer lapping parameters
Process | ECAL
Diamond Plate | #800
Down Pressure | 1 psi / 3 psi
Electrolyte Type | NaNO₃ 20 wt%
Temperature | 70°C
Flow Rate | 0.5 L/min
Head/Platen Rotation Speed | 30/40 rpm, 50/60 rpm
Process Time | 1 h

In this section, the results of the ECAL process for 4-inch monocrystalline silicon carbide (SiC) wafers under different experimental parameters are summarized. The discussion focuses on the effects of varying down pressure and rotational speed on wafer surface quality and MRR. At 1 psi and 30/40rpm,MRRH has been measured as 1.770μ m/h and Sa0.4394μ m. At the same pressure with 50/60rpm,MRRH has increased to 1.938μ m/h and Sa0.4888μ m. For 3 psi and 30/40rpm, MRRH has reached 2.213μ m/h and Sa0.5085μ m. The highest efficiency has been obtained at 3 psi and 50/60rpm, with MRRH3.180μ m/h and Sa0.6538μ m.
The 4-inch 4H-SiC wafer after ECAL processing under the 3 psi and 50/60 rpm as shown in Fig. 6. According to the experimental results, higher pressure and speed have enhanced the MRR but have slightly degraded the surface quality. The corresponding wafer quality results are summarized in Table 2. Although the Warp value has been slightly higher, the overall wafer has maintained good flatness and can be further improved by subsequent CMP processes.

[picture]

Fig. 6. 4-inch 4H−SiC after ECAL processing [2].
Table 2. Measurement results of Bow, Warp, TTV for 4-inch 4H-SiC [2].

Fig. 6. 4-inch 4 H − S i C after ECAL processing [2]. Table 2. Measurement results of Bow, Warp, TTV for 4-inch 4H-SiC [2].

To evaluate the scalability of the ECAL process, the same conditions have been applied to 6 -inch monocrystalline SiC wafers. The resulting MRR is lower than that of the 4 -inch wafers, with an MRRH of 2.457μ m/h and Sa of 0.457μ m. This reduction has been attributed to the reduced current density on the larger surface area, while the surface roughness has remained comparable and relatively stable.
The wafer quality after ECAL has been summarized in Table 3. For the 6-inch wafers, Bow, Warp, TTV have been measured as −5.00μ m,36.70μ m, and 6.60μ m, respectively. The 6-inch wafer has maintained overall flatness and surface condition after ECAL processing, with the Bow/Warp/TTV measurement map shown in Fig. 7(a) and the wafer photograph after processing in Fig. 7(b).

Table 3. 6-inch SiC Wafer (C-face) ECAL parameters [2].

6-inch SiC wafer lapping parameters
Process | ECAL
Diamond Plate | #800
Down Pressure | 3 psi
Electrolyte Type | NaNO₃ 20 wt%
Temperature | 70°C
Flow Rate | 0.5 L/min
Head/Platen Rotation Speed | 50/60 rpm
Process Time | 1 h

[picture]

Fig. 7. (a) 6 -inch 4H−SiC Bow/Warp/TTV measurement (b) 6 -inch 4 H -SiC after ECAL processing [2].

Fig. 7. (a) 6 -inch 4 H − S i C Bow/Warp/TTV measurement (b) 6 -inch 4 H -SiC after ECAL processing [2].

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

In this study, the electrochemical assisted fixed-abrasive lapping (ECAL) process has been demonstrated on 4 -inch and extended to 6 -inch 4 H - SiC wafers. Electrochemical analyses have confirmed that 20 V has provided stable passivation, enabling effective wafer thinning. The applied process parameters have resulted in high removal efficiency while maintaining wafer flatness. The successful demonstration on 6 -inch wafers has emphasized the scalability of ECAL for nextgeneration SiC substrates. Future work can focus on further optimizing electrochemical conditions and integrating ECAL with CMP to improve overall wafer quality. These findings have demonstrated that ECAL has strong potential for integration into large-scale SiC wafer manufacturing, contributing to improved device performance in power electronics and communication applications.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

P. Wu, et al., Effect of voltage on electrochemical mechanical polishing (ECMP) of 4H-SiC with fixed abrasives, Journal of Materials Research and Technology (2025).

C.-H. Wu, Research on electrochemical-assisted fixed abrasive lapping process for monocrystalline silicon carbide wafer, M.S. Thesis, National Taiwan University of Science and Technology, Taipei, Taiwan (2024).

T.-C. Wu, Research on electrochemical-assisted fixed abrasive lapping process for monocrystalline silicon wafer thinning, M.S. Thesis, National Taiwan University of Science and Technology, Taipei, Taiwan (2023).

X. Yang, et al., Selective electrochemical mechanical polishing of surface employing porous material impregnated with electrolyte, Ceramics International 49 (22) (2023) 3456934581.

X. Yang, et al., Charge utilization efficiency and side reactions in the electrochemical mechanical polishing of 4H-SiC (0001), Journal of the Electrochemical Society 169 (2) (2022) 023501.

Z. Chen, Y. Zhao, Investigation into electrochemical oxidation behavior of with varying anodizing conditions, Electrochemistry Communications 109 (2019) 106608.

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Chapter 6: Interface, Dielectrics and Ohmic Contact in SiC Power Devices

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 1-7

doi: 10.4028/p-BBnM7g

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-17

Revised:
2025-12-09

Accepted:
2026-03-08

Online:
2026-05-20

Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

Chia-Lung Hung 1,a*, Patrick Rabinzohn 2,b, Andrii Vozny 2,c, Tatiana Ivanova 2,d, Mikko Söderlund 2,e, Yi-Kai Hsiao 1,f and Hao-Chung Kuo 1, g

1 Semiconductor Research Center, Hon Hai Research Institute, Taiwan, R.O.C.

2 BENEQ Oy, Olarinluoma 9, 02200 Espoo, Finland

a  kevin.cl.hung@foxconn.com, b  patrick.rabinzohn@beneq.com, c  andrii.voznyi@beneq.com, d  tatiana.ivanova@beneq.com, e  Mikko.Soderlund@beneq.com, f  jason.yk.hsiao@foxconn.com, ghao-chung.kuo@foxconn.com

Keywords: 4 H -SiC, Atomic Layer Deposition, Density of interface states, Embedded CMOS, SiO2, Specific on-state resistance, Trench UMOSFET

Abstract

This paper presents process integration of atomic layer deposition (ALD) SiO2 as gate dielectric in the 1.7 kV SiC trench UMOSFET. This integration provides a solution for embedding complementary metal oxide semiconductor (CMOS) circuits into the UMOSFET power device, enabling the realization of smart power management integrated circuit (IC) functions in the future. 4H-SiC power MOSFETs have gained increased attention in medium to high power applications recently due to their wide bandgap, high breakdown electric field, and excellent thermal conductivity. The electric vehicle (EV) is one example of an application where the Tesla Model 3 utilizes SiC 650V VDMOSFETs as driving components in its inverter design. Trench MOSFETs are key to achieving these requirements to further scale down power devices while decreasing the specific on-state resistance ( Ron,sp ). This is challenging with thermal gate oxide on SiC trench MOSFETs due to the anisotropic thermal oxide growth rate on the sidewalls and the bottom of trench or mesa region. Therefore, we propose a novel fabrication process by integrating ALD SiO2 gate oxide into trench UMOSFET. The Ron,sp of the fabricated device can be reduced to 2.3 mΩ−cm2, accompanied by a very low density of interface states ( Dit  ) of approximately 5.36×1010eV−1 cm−2. Another feature of this ALD SiO2 solution for gate oxide is the monolithic integration of the CMOS circuit with the UMOSFET, enabling the realization of smart power IC management.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

SiC power MOSFET are replacing Si devices in the blocking voltage range from 600 to 6500 V with substantial energy saving in various electric systems courtesy to their low on-resistance and fast switching. This trend is now often supported by trench UMOSFET. In particular significant attention has been paid to monolithic SiC power IC [1] due to its fast-switching capabilities and suitability for harsh environment applications. However, a major challenge remains in achieving a conformal gate oxide thickness on both the UMOSFET and CMOSFET. The strong crystal face dependence of the oxidation rate [2] must be carefully considered in device fabrication. The industry trend has shifted from thermal oxidation to deposition techniques, with ALD offering best quality, superior conformality and precise control of thickness at low temperatures, while also enabling interface engineering using plasma-based processes.

Nobel Fabrication Process for Embedded CMOS and UMOSFET

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

In this paper, we propose a novel fabrication process for embedding the low voltage (LV) CMOS circuit and high voltage (HV) trench UMOSFET simultaneously on a SiC substrate as presented in Figure 1. Began with the RCA clean process with a nitrogen-doped ( 5×1015 cm−3 ), 4-degree tilted epitaxial layer (15μ m) grown on a heavily doped SiC substrate. A multiple ion implantation process

[picture]

Fig. 1. Cross-sectional scheme for LV and HV device integration

Fig. 1. Cross-sectional scheme for LV and HV device integration

was executed in a high-temperature ( 500∘C ) implanter, including the p -bottom shielding (PBS), p plus ( p+), guard ring (GR), n-plus ( n+), p-well (PW), and side-wall protection (SP) implantations. Among the implantation steps, the PBS and SP processes further utilized the spacer on hard mask sidewall (SHMS) technique to precisely control the lateral doping profile, ensuring a balance between Ron,sp  and breakdown voltage (BV). An implantation hard mask was patterned for the PBS and SP layers, a side wall spacer was then formed on the lateral side wall of the hard mask. High energy ion implantation was executed to the desired junction depth to form the bottom and side wall protection structures for the PBS and SP, respectively. The implanted dopants were activated by 1750∘C thermal annealing with carbon cap. Trench formation was achieved by first patterning a hard mask on SiC, followed by reactive ion etching (RIE) to create the desired depth and profile, resulting in trenches with a width of 1μ m and a depth of 1.5μ m. The sacrificial oxidation followed by the deep trench etching was conducted to repair the side wall damage region induced by the trench etching. A raised CVD field oxide layer of 0.2μ m was subsequently patterned to create the isolation region within the CMOS circuit area. Gate dielectrics were formed under three different conditions for comparison: LPCVD SiO2 deposition followed by nitrogen ( N2 ) annealing at 1000∘C, ALD SiO2 deposition with TDMAS and O3 as precursors followed by nitric oxide (NO) annealing at 1250∘C, and dry thermal oxidation followed by NO annealing at 1250∘C. The ALD SiO2 dielectric stack includes in-situ plasma preclean and a 5 nm interfacial layer deposited by advanced PEALD Atomic Layer Annealing (ALA) [3] prior a thick high-quality SiO2 thermal ALD layer thus tailoring the SiC/ dielectric interface, enhancing leakage current, breakdown voltage, and overall quality of the SiC/SiO2 interface.

[picture]

Fig. 2. TOF-ERDA composition analysis of the ALDSiO2 stack [33.7+/−0.5%Si,66.2+/−0.5%O,<1%C,H<0.3%, N<BDL ]

Fig. 2. TOF-ERDA composition analysis of the A L D S i O 2 stack [ 33.7 + / − 0.5 % S i , 66.2 + / − 0.5 % O , < 1 % C , H < 0.3 % , N < B D L ]

[picture]

Fig. 3. Current density-electric field and Capacitance-voltage Plot

Fig. 3. Current density-electric field and Capacitance-voltage Plot

[picture]

Fig. 5. SEM cross section of trench UMOSFET with (a) PBS implantation (b) without PBS implantation

Fig. 5. SEM cross section of trench UMOSFET with (a) PBS implantation (b) without PBS implantation

Fig. 4. (a) Simulated trench UMOSFET with PBS implantation and (b) without PBS implantation

High purity of the ALDSiO2 dielectric stack was confirmed after NO annealing on Figure 2. Current density-electric field and Capacitance-voltage characteristics of MOS test capacitors using the ALD SiO2 dielectric stack are shown on Figure 3. These characteristics are accompanied by a nearly ideal VFB of - 0.69 V , a 0.1 V hysteresis and −6.6×1010 cm−2 charge trapping at the SiO2/SiC interface. Heavily phosphorus-doped polysilicon with a thickness of 1μ m was formed using the deposition-etching-deposition (DED) technique to ensure effective gap filling and conductivity in both the trench UMOSFET and CMOS devices. An inter-metal dielectric (IMD) layer was deposited and subsequently patterned to define the source and gate contact regions, facilitating device interconnections. Nickel silicide ( NiSi ) and titanium/titanium nitride ( Ti/TiN ) was employed for the metal contact in the source and gate contact region, respectively. Pure aluminum (Al) was deposited and subsequently patterned to establish top metal region. Finally, a passivation layer consisting of 0.2 μm of oxide and 0.7μ m of nitride was deposited using PECVD tool. Additionally, a 10μ m polyimide layer was applied to protect the entire chip area, except for the opening region on the electrical pad for probing the power device. This completes the fabrication of the SiC trench UMOSFETs and CMOS circuits on the wafer. The simulated and fabricated UMOSFET are shown in Figures 4 and 5, respectively.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

Figure 6 presents the SEM cross-sectional image of trench UMOSFETs utilizing LPCVD SiO2, ALD SiO2, and thermal SiO2 as gate dielectrics. The gate oxide thickness on the trench sidewall is thinnest for LPCVD SiO2, attributed to its poor step coverage. In contrast, the thickness at the trench

[picture]

Fig. 6. SEM cross section of trench UMOSFET with (a) LPCVD SiO2 (b) ALD SiO2 (c) Thermal SiO2

Fig. 6. SEM cross section of trench UMOSFET with (a) LPCVD S i O 2 (b) ALD S i O 2 (c) Thermal S i O 2

Table 1. Gate Oxide Thickness Comparison

Gate Oxide Condition | LPCVD SiO₂ | ALD SiO₂ | Thermal SiO₂
Post Oxide Annealing | N₂ 1000°C | NO 1250°C | NO 1250°C
Oxide Thickness@ Trench Side Wall | 28.35 nm [SEM] | 45.3 nm [SEM] | 48.8 nm [SEM]
Oxide Thickness@ Trench Bottom | 25 nm [SEM] | 43.7 nm [SEM] | 11.1 nm [SEM]
Oxide Thickness@ Trench Mesa | 48 nm [CV] | 41 nm [CV] | 15 nm [CV]
Mesa Normalized to Side Wall | 169 % | 91 % | 31 %

[picture]

Fig. 7. CV characteristics of MOSCAP with different gate oxide and annealing

Fig. 7. CV characteristics of MOSCAP with different gate oxide and annealing

Fig. 8. Density of interface states versus energy distribution with different gate oxide and annealing
bottom reveals that thermal SiO2 exhibits only 10 nm compared to the other two deposition methods due to the lower anisotropic thermal oxidation rate at the trench bottom. Table 1 summarizes the gate oxide thickness across three different regions surrounding the trench for the three gate oxide formation methods. ALD SiO2 demonstrates the best step coverage and conformality among the options, indicating a high potential for integrating CMOS circuits into trench UMOSFET power chips. Figure 7 illustrates the CV characteristics of the planar MOS capacitor built on the mesa region under various gate oxide and annealing conditions. The ALD SiO2 exhibits behavior similar to that of the thicker thermal SiO2. In contrast, the LPCVDSiO2 reveals a larger flat band shift and distortion, attributed to accumulated Dit  at the interface. Additionally, the thinner thermal SiO2 raises significant concerns regarding leakage and reliability issues. The Hi−LoCV method was conducted to extract the Dit  in this work. The Dit  at 0.2 eV from the conduction band edge is measured to be 5.36×1010eV−1· cm−2 for ALD SiO2, 6.30×1010eV−1· cm−2 for thermal SiO2, and 6.80×1012eV−1· cm−2 for LPCVD SiO2, as shown in Figure 8. As expected in-situ plasma preclean and deposition of the ALA SiO2 interfacial layer strongly improved Dit  of the Si -face on SiC . Figure 9 presents the transfer characteristics of the planar NMOSFET and PMOSFET utilizing ALD SiO2 as the gate oxide. The extracted threshold voltages ( Vth  ) are found to be 2 V for the NMOSFET and 5.3 V for the PMOSFET. The subthreshold swing (S.S) are 203 and 287mV/ Dec for the NMOSFET and PMOSFET, respectively. The output characteristics of the NMOSFET and PMOSFET exhibit typical linear and saturation behavior as demonstrated in Figure 10. To demonstrate the integration of the CMOS
circuits with power trench UMOSFET by utilizing the ALD SiO2 as the gate dielectric, we also fabricate an inverter circuit composed of both NMOSFET and PMOSFET in this work. Figure 11 presents the transfer characteristics of the fabricated inverter circuit, showing a high noise margin (NMH) of 6.3 V and a low noise margin (NML) of 10.5 V . The observed asymmetry between NMH and NML is attributed to the Vth  mismatch between the NMOSFET and PMOSFET, as previously discussed. The PBS implantation was introduced to the thermal SiO2 wafer to provide protection for the ultra-thin oxide at the trench bottom and corners. Figure 12 illustrates the transfer characteristics of the trench UMOSFET, with the Vth  determined at a gate voltage (VG) corresponding to a current

[picture]

Fig. 9. Transfer characteristics of NMOSFET and PMOSFET with ALD SiO2 as gate dielectric

Fig. 9. Transfer characteristics of NMOSFET and PMOSFET with ALD S i O 2 as gate dielectric

[picture]

Fig. 10. Output characteristics of NMOSFET and PMOSFET with ALD SiO2 as gate dielectric

Fig. 10. Output characteristics of NMOSFET and PMOSFET with ALD S i O 2 as gate dielectric

[picture]

Fig. 11. Transfer characteristics of CMOS inverter with ALDSiO2 as gate dielectric

Fig. 11. Transfer characteristics of CMOS inverter with A L D S i O 2 as gate dielectric

[picture]

Fig. 12. Transfer characteristics of UMOSFET with different gate oxide and annealing

Fig. 12. Transfer characteristics of UMOSFET with different gate oxide and annealing

of 1 mA . The Vth  values are found to be 2 V for ALDSiO2 and 4.8 V for thermal SiO2. In contrast, the LPCVD SiO2 exhibits an abnormally high Vth , attributed to the elevated Dit  accumulated at the SiO2/SiC interface. In addition to the varying effects of the gate oxide, the higher Vth  observed in the trench UMOSFET with thermal SiO2 is also influenced by the PBS implantation effect. The merged PBS implant profile with the p -well on the left side wall of the trench, resulting from an alignment error as depicted in Figure 5(a), contributes to the higher Vth and the lower conduction observed current. Figure 13 shows the output characteristics of the trench UMOSFET with ALD SiO2 as the gate dielectric. Finally, the benchmark comparison of our work with other studies [4~6] is presented in Figure 14, highlighting a Ron,sp of 2.3~2.7 mΩ· cm2 and a BV of 1755~2349 V achieved in this study. Figure 15 presents the BV characteristics of the fabricated UMOSFET and floating GR. The
wider BV range was attributed to the leakage current originating in the UMOSFET cell region, which likely stemmed from the corner and bottom of the trench structure being inadequately protected by the SP and PBS.

[picture]

Fig. 13. Output characteristics of UMOSFET with ALD SiO2 as gate dielectric

Fig. 13. Output characteristics of UMOSFET with ALD S i O 2 as gate dielectric

[picture]

Fig. 14. Benchmark comparison of other studies with this work

Fig. 14. Benchmark comparison of other studies with this work

[picture]

Fig. 15. BV characteristics of the fabricated UMOSFET and GR in this work

Fig. 15. BV characteristics of the fabricated UMOSFET and GR in this work

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

We have successfully demonstrated the monolithic integration of CMOS circuits with power trench UMOSFETs by utilizing ALD SiO2 as the gate dielectric, owing to its superior step coverage and conformality. In-situ plasma preclean of the SiC surface and deposition of a 5 nmALASiO2 interfacial layer strongly improve Dit.  The Dit  of the ALDSiO2 can reach 5.36×1010eV−1· cm−2, which is comparable to or even better than that of thermal SiO2 observed so far. The NMH and NML of the fabricated inverter circuit are 6.3 V and 10.5 V , respectively. The asymmetry between NMH and NML can be further improved through Vth  adjustment or optimization of the channel width design in future work. The Vth  of the ALDSiO2 trench gate oxide UMOSFET is 2 V , and the Ron,sp can be reduced to 2.3 mΩ· cm2 due to the ultra-lower Dit  at the SiO2/SiC interface. The BV of the fabricated ALD SiO2 trench MOSFET and the guard ring is within 1755~2349 V, which is good enough for the 1700 V application. The enabling capability of ALD for the monolithic integration versus thermal oxide and LPCVD, which are just not capable due to conformality across the mesa and trench regions. Future work will require the optimization of the ALDSiO2 process, as well as the SP and PBS implantation processes.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

The authors would like to express their gratitude to Kosuke San from SAMCO for providing support with the SiC trench process, and to Professor Bing Yue Tsui from NYCU for supplying the measurement instruments.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.1.pdf

M. Okamoto, et al., First Demonstration of a Monolithic SiC Power IC Integrating a Vertical MOSFET with a CMOS Gate Buffer, ISPSD 2021.

T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, 2nd ed. (Wiley-IEEE Press, 2014) p. 214.

A. Voznyi et al., ALD deposited dielectric stack with engineered interface using in-situ Atomic Layer Annealing for high-performance SiC MOSFET, ICSCRM 2024.

C. L. Hung, et al., Enhancing Characteristics of SiC VDMOSFETs: Strategic Integration of Cell Design and Process Optimization, IEEE Trans. Electron Devices, 71, 6228, 2024.

N. J. Yeop, et al., A Novel 1700V 4H-SiC Double Trench MOSFET Structure for Low Switching Loss, J. IKEEE, 25, 15, 2021.

A. T. Hajjiah, et al., Novel SiC-trench-MOSFET with reduced oxide electric field, IEEE. ICSICT, 2004.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 9-13

doi: 10.4028/p-rMav12

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-08

Revised:
2025-12-09

Accepted:
2026-03-16

Online:
2026-05-20

Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

Bongmook Lee 1,a* and Veena Misra 2, b

¹College of Engineering, SUNY Polytechnic Institute, Utica, NY 13502, USA

2 Department of Electrical Engineering, North Carolina State University, Raleigh, NC

aleeb1@sunypoly.edu, b  vmisra@ncsu.edu

Abstract

This study investigates the electric dipole effect at Al2O3/SiO2 interfaces deposited by Atomic Layer Deposition (ALD) on 4H-silicon carbide (SiC) substrates for threshold voltage ( VT ) modulation. By incorporating an ultrathin 3 nmAl2O3 layer onto ALD-deposited 30 nmSiO2, they created an electric dipole that produces a 0.65±0.15 V positive shift in threshold voltage after N2O post-deposition annealing. The dipole-induced voltage shift was validated through both MOS capacitor measurements and lateral MOSFET characterization. Importantly, the threshold voltage enhancement occurred without degradation in field-effect mobility, demonstrating that the dipole effect does not introduce additional scattering centers. This technique offers an effective approach for threshold voltage tuning in alternative semiconductor devices where thermal SiO2 growth is not feasible, addressing critical challenges in SiC power electronics that require high threshold voltages (>3 V) for reliable operation.

Keywords: atomic Layer deposition, 4H−SiC power device, dipole effect, VT modulation, VFB modulation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

Electric dipole effects at high-permittivity dielectric (high-k)/ SiO2 interfaces have been reported for various dielectrics, including HfO2,Al2O3,LaOx, and Y2O3 on Silicon as well as Silicon Carbide substrates [1-4]. For example, a dipole-induced voltage shift of up to 0.57 V has been observed for Al2O3 on thermally grown SiO2 on Si [2]. Such dipole effects can lead to either positive or negative flatband or threshold voltage shifts, depending on the properties of the high-k dielectric within the stack. Consequently, dipole engineering provides a means to modulate the threshold voltage of metal-oxide-semiconductor field-effect transistors (MOSFETs) [2]. Traditionally, dipole effects of high-k dielectrics have been investigated on thermally grown SiO2 on silicon. However, it is particularly interesting to explore these effects on alternative substrates where threshold voltage control remains challenging, such as in silicon carbide (SiC) MOSFETs. In SiC devices, enhancing channel mobility via nitrogen-based post-oxidation annealing often forces a trade-off between mobility and threshold voltage. For reliable power electronics applications, a sufficiently high threshold voltage ( >3 V ) is typically required. In this work, we report a Vt enhancement method based on the dipole effect of Al2O3/SiO2 stacks deposited by atomic layer deposition (ALD) on 4H−SiC. ALD dielectrics are particularly attractive as gate dielectrics due to their excellent film quality, uniformity, precise thickness control, and low-temperature processing [5]. Here, we demonstrate for the first time the dipole effect in Al2O3/SiO2 stacks deposited entirely by ALD on 4H−SiC.

The origin of the dipole effect is generally attributed to energy band bending at the high- k/SiO2 interface. This effect can arise from either (i) the electronegativity difference between the cations in the two oxides or (ii) differences in oxygen areal density across the interface [3,4]. As a result, the threshold voltage/flatband voltage ( VT/VFB ) shift induced by the dipole effect does not introduce additional interface states or Fermi-level pinning [3,4]. Importantly, unlike charge-induced Vt/VFB shifts, the dipole-induced shift does not generate new scattering centers, and its magnitude is independent of both the SiO2 and high-k dielectric thicknesses. Thus, the dipole effect can be modeled as an intrinsic band bending at the high-k/SiO2 interface, which produces a constant flatband shift for a given dielectric stack. Accordingly, the expression for the MOS capacitor flatband voltage must be
modified under the assumption that any anomalous VT/VFB shift is caused by the dipole effect. The general expression for the flatband voltage of a MOS capacitor is given as:

VFB=Φms−qεox∫0EOTxρ(x)dx+ dipole (1)

In this framework, Φms represents the work function difference between the gate and the substrate, εox is the relative permittivity of SiO2,x denotes the distance from the gate, EOT is the effective oxide thickness of the dielectric stack, and ρ(x) corresponds to the fixed charge density within the dielectric layers or at the interfaces [6]. In the calculation, only fixed charges are considered; these may be located at the SiO2/SiC interface, within the bulk of the SiO2, at the high-k /SiO2 interface, within the bulk of the high-k dielectric, or at the gate/high-k interface. For high-quality SiO2, the bulk charge density can typically be neglected. Any charge or dipole at the dielectric/gate interface can be accounted for by using an experimentally determined effective gate work function. Therefore, in all subsequent equations, Φms should be regarded as the effective work function difference between the gate and the substrate. For a Al2O3/SiO2 dual-layer stack, the flatband voltage equation can be modified as follows:

VFB=Φms−qεox(QSiO2EOT+QAl2O3EOTAl2O3+ρAl2O3EOTAl2O32)+ dipole (2)

Here, QSiO2 and QAl2O3 represent the fixed charge densities at the SiO2/SiC interface and the Al2O3/SiO2 interface, respectively. In the derivation, the bulk charge density within the high-k layer is assumed to be uniform. From Equation (2), it follows that, in the absence of any bulk charge, the flatband voltage should exhibit a linear dependence on EOT. Our experimental results indicate that high- kAl2O3 contains a negligible amount of bulk charge; therefore, the bulk charge term in Equation (2) can be ignored in the following discussion. To verify the presence of a dipole effect, the charge densities QSiO2 and QAl2O3 must be extracted. When the Al2O3 thickness is fixed, Equation (2) can be simplified and written as:

VFB=Φms−qεox(QSiO2EOT+QAl2O3EOTAl2O3)+ dipole (3)

With Equation (3), the fixed charge density at the ALDSiO2/SiC2 interface can be extracted by varying SiO2 thickness while the Al2O3 thickness is fixed.

VFB=Φms−qεox(QSiO2+QAl2O3)EOT+qεoxQAl2O3EOTSiO2+ dipole (4)

Similarly, using another set of capacitors with varying Al2O3 thickness, the fixed charge density at the ALDAl2O3/SiO2 interface can be extracted using Equation (4).

Experiments

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

MOS capacitors were fabricated on n-type, Si-face ( 0001 ) 4H-SiC substrates with a nitrogen doping concentration of ND=6×1015/cm3. Following surface cleaning in solvents and diluted hydrofluoric (HF) acid, the samples were immediately transferred to an ALD system for SiO2 deposition at 150∘C. Variation in SiO2 thickness across the MOS capacitors was achieved by wet etching in diluted HF . For the dual-layer capacitors, an ALDAl2O3 layer was subsequently deposited at 200∘C after the SiO2 etching step. Post-deposition annealing (PDA) was carried out in a rapid thermal anneal (RTA) system at 900∘C in pure N2O ambient. The gate electrode was formed by RF sputtering of tantalum nitride (TaN) capped with tungsten (W). A post-metallization anneal (PMA) in N2 ambient was then performed to mitigate sputter-induced damage. The capacitance-voltage ( C−V ) characteristics were measured using an HP 4284A precision LCR meter. Flatband voltage and effective oxide thickness (EOT) were extracted from the 1MHzC−V curves with the CVC program, using 4H−SiC material parameters [7]. Lateral MOSFETs were fabricated on Al-doped ( NA=5×1015 cm3 Si-face (0001) 4H-SiC substrates. Source and drain regions were formed by phosphorus
implantation followed by activation annealing. After field oxide deposition and patterning, the samples underwent the same surface cleaning, ALD dielectric deposition, PDA, and TaN/W gate electrode deposition and patterning steps used for the capacitors. Contact holes were etched in HF solution prior to the N2O PDA. The source/drain ohmic contacts were formed by nickel silicide after the gate stack fabrication. Finally, MOSFET characteristics were measured using a Keithley 4200 semiconductor parameter analyzer.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

The C−V characteristics of MOS with ALDSiO2 and Al2O3/SiO2 dielectrics are shown in Fig. 1 (a). The C-V curves measured at different frequencies exhibit minimal frequency dispersion. The flatband voltage and effective oxide thickness of the MOS capacitors were extracted to evaluate the dependence of VFB on oxide thickness. The effective work function of TaN gate electrode on Al2O3 and SiO2 dielectrics was individually extracted from measured capacitor C−V data of MOS capacitors with single-layer Al2O3 and SiO2. The effective work function of TaN on ALD SiO2 and ALD Al2O3 is 4.47±0.01eV and 4.56±0.04eV, respectively. As shown in Fig. 1 (b), VFB values of capacitors with only ALDSiO2 and those with dual-layer stacks both show a linear dependence on oxide thickness, indicating a negligible amount of bulk fixed charge in the oxide. The linear fitting line of the dual-layer devices shows a significantly higher y-intercept than that of the ALD SiO2 samples, suggesting the existence of a dipole. The positive slopes of the linear fits indicate negative effective fixed charges, consistent with prior observations in ALDSiO2 dielectrics [8]. Table 1 summarizes the extracted charge density and interface state density. Based on calculations, the dipole-induced VFB shift is estimated to be 0.65±0.15 V. The addition of Al2O3 reduces the gate leakage due to the incorporation of a high-k layer in the oxide stack.

[picture]

Fig. 1. (a) C-V characteristics of MOS Capacitors and (b) Flatband voltage vs. oxide thickness of MOS Capacitors with 30 nm ALD SiO2 and ALD Al2O3/SiO2 after 900∘CN2O PDA. Both sets of samples contain ALD SiO2 with various thicknesses.

Fig. 1. (a) C-V characteristics of MOS Capacitors and (b) Flatband voltage vs. oxide thickness of MOS Capacitors with 30 nm ALD S i O 2 and ALD A l 2 O 3 / S i O 2 after 900 ∘ C N 2 O PDA. Both sets of samples contain ALD S i O 2 with various thicknesses.

Figure 2 (a) shows the average flatband voltage for ALDSiO2 and Al2O3/SiO2 dielectrics after postdeposition annealing (PDA) at 900∘C and 1000∘C. The Al2O3/SiO2 stack maintains a higher flatband voltage compared to SiO2 indicating the persistence of the interface dipole between Al2O3 and SiO2. Figure 2 (b) presents the gate leakage characteristics, where the incorporation of an Al2O3 layer effectively suppresses gate leakage in the low- and moderate-field regions. These results confirm that the Al2O3/SiO2 dielectric stack provides superior electrical performance, offering both enhanced flatband voltage stability and reduced leakage current relative to a single SiO2 dielectric.

Table I. Extracted parameters from MOS capacitor with ALD SiO2 and Al2O3/SiO2 after 900∘C PDA.

Dielectric | Parameters
Charge Density superscript number | D mathematical formula at mathematical formula - superscript number

[picture]

Fig. 2. (a) Average flatband voltage after two different PDA temperatures and (b) Gate leakage characteristics of MOS capacitors with single SiO2 and dual Al2O3/SiO2 dielectrics.

Fig. 2. (a) Average flatband voltage after two different PDA temperatures and (b) Gate leakage characteristics of MOS capacitors with single S i O 2 and dual A l 2 O 3 / S i O 2 dielectrics.

[picture]

Fig. 3. Ids-Vgs curves and mobility of MOSFETs with ALD SiO2 and Al2O3/SiO2.

Fig. 3. Ids-Vgs curves and mobility of MOSFETs with ALD S i O 2 and A l 2 O 3 / S i O 2 .

Lateral MOSFETs were fabricated to validate the MOS capacitor results. As shown in Fig. 3, the lateral MOSFET with an ALDAl2O3/SiO2 dual-layer gate dielectric exhibits a threshold voltage that is 1.24 V higher than that of the device without Al2O3, accompanied by an increase of 1.5 nm in effective oxide thickness (EOT) due to the additional Al2O3 layer. Considering the effect of the negative fixed charge, the increase in EOT from the Al2O3 layer accounts for approximately 0.6 V of the observed VT shift. The remaining increase in VT is therefore attributed to the dipole effect.

Importantly, no degradation in field-effect mobility or subthreshold swing was observed. These results demonstrate that the ALDAl2O3/SiO2 dual-layer stack is an effective approach to increase the threshold voltage of SiO2-based devices without compromising device performance. Furthermore, the findings confirm that the dipole does not introduce additional scattering centers at the SiC/dielectric interface compared to devices with only ALD SiO2. In addition, the ALD-deposited dual-layer stack can be extended to other alternative semiconductor substrates to induce a positive threshold voltage shift.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

We have demonstrated the existence of an electric dipole at the Al2O3/SiO2 dual-layer stack deposited by ALD on 4H−SiC substrates. After N2O post-deposition annealing, the dual-layer stack exhibits a dipole-induced voltage of 0.65±0.15 V. Lateral MOSFET results further confirm that the incorporation of Al2O3 induces a positive threshold voltage shift of 1.24 V , accompanied by suppressed gate leakage and without degradation in mobility or subthreshold swing. These results highlight that Al2O3/SiO2 stacks not only enable threshold voltage tuning but also improve dielectric properties. This approach provides an effective pathway to achieve a positive threshold voltage in 4H-SiC MOSFETs and can be extended to other wide bandgap semiconductor devices where thermal oxidation of SiO2 is not feasible.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.9.pdf

T. -H Kil, M. Noguchi, H. Watanabe, and K. Kita, "Impact of Al2O3/SiO2 interface dipole layer formation on the electrical characteristics of 4H-SiC MOSFET," IEEE Electron Device Letters, 43 (1), 2022.

P. D. Kirsch et al, "Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning," Appl. Phys. Lett., vol. 92, no. 9, pp. 092 901, Mar. 2008.

K. Kita and A. Toriumi, "Origin of electric dipoles formed at high-k/ interface," Appl. Phy. Lett., vol. 94, no. 13, pp. 132 902, April. 2009.

B. Lee, S. Novak, D. Lichtenwalner, X. Yang, and V. Misra, "Investigation of the origin of modulation by capping layer approaches for NMOS application: Role of La diffusion, Effect of host high-k layer, and interface properties," IEEE Transactions on Electron Devices, Vol. 58, no. 9, pp. 3106-3115, 2011.

S. M. George, "Atomic layer deposition: An overview," Chem. Rev., vol. 110, no. 1, pp. 111131, Jan. 2010.

R. Jha, J. Gurganos, Y. H. Kim, R. Choi, J. Lee, and V. Misra, "A capacitance-based methodology for work function extraction of metals on high- ," IEEE Electron Device Lett., vol. 25, pp. 4202004.

J. R. Hauser and K. Ahmed, "Characterization of ultra-thin oxides using electrical C-V and IV measurements," in Proc. AIP Conf., 1998, pp. 235-239.

X. Yang, B. Lee, and V. Misra, "Electrical characteristics of deposited by Atomic Layer Deposition on 4H-SiC after nitrous oxide anneal," IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2826-2830, 2016.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 15-20

doi: 10.4028/p-48Kf9g

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-23

Accepted:
2026-02-26

Online:
2026-05-20

Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

Wei-Chen Yu 1,a*, Chia-Lung Hung 1,b, Wei-Cheng Lin 2,c, Wei-Ting Lin 1,d, Tejender Singh Rawat 1,e, Yi-Kai Hsiao 1,f, Tian-Li Wu 2, g and Hao-Chung Kuo 1,2,h

1 Hon Hai Research Institute, Hsinchu city, Taiwan, R.O.C.

2 National Yang Ming Chiao Tung University, Hsinchu city, Taiwan, R.O.C.

a* wayne.wc.yu@foxconn.com, b kevin.cl.hung@foxconn.com, c wclin.st11@nycu.edu.tw, d  bruce.wt.lin@foxconn.com, ètejender.s.r@foxconn.com,  9tlwu@nycu.edu.tw, hao-chung.kuo@foxconn.com

Keywords: SiC MOSFETs, gate oxide, ALD, hysteresis, CV characteristics, NO annealing.

Abstract

This work investigates the impact of different gate oxide fabrication schemes on the electrical characteristics of 4H−SiC planar MOSFETs. Three processes with a target thickness of 50 nm were implemented: (1) thermal oxidation with NO annealing at 1350∘C (actual thickness: 52 nm ), (2) ALD-grown oxide with NO annealing at 1250∘C (actual thickness: 43 nm ), and (3) a stacked 20 nm thermal/ 30 nm ALD oxide structure with NO annealing at 1250∘C (actual thickness: 47 nm ). Electrical characterization included IdVg,CV, and IgEox measurements. Results show that Condition 1 exhibits the lowest leakage and best uniformity, and demonstrates strong oxide integrity without soft breakdown events. In contrast, Condition 2 and 3 show increased leakage, higher variability, and evidence of soft breakdown, suggesting greater interfacial weakness likely due to incomplete passivation of ALD-related defects at the lower annealing temperature. However, a surprising trend was observed in the CV analysis: Condition 2's flat band voltage ( VFB ) is closest to the ideal 0 V , indicating a lower fixed charge density than Condition 1[1], which has the most negative VFB(≈−2 V). The hysteresis results further highlight differences, with Condition 3 showing the largest hysteresis window ( ΔVth =0.13 V ). These findings suggest that while the ALD process coupled with a lower-temperature NO anneal (Condition 2) can effectively reduce fixed charges, it does not fully eliminate interfacial defects responsible for increased leakage and soft breakdown. Our results underscore the complex trade-offs in different fabrication schemes, emphasizing that careful interface engineering beyond conventional NO annealing is required to ensure reliable performance in SiC MOSFETs.

Introduction

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Wide bandgap semiconductors such as 4H−SiC have enabled significant progress in high-power and high-temperature electronics, offering advantages in efficiency and miniaturization compared to traditional Si devices [2]. However, the performance and reliability of SiC MOSFETs remain constrained by the quality of the gate oxide and the SiC/SiO2 interface. Unlike Si MOSFETs, where decades of process optimization have led to highly controlled interface states, the SiC/oxide system still suffers from high interface trap density ( Dit ), charge trapping, and threshold voltage instability. While thermal oxidation followed by nitric oxide (NO) annealing remains the industrial standard [3], alternative approaches such as atomic layer deposition (ALD) or composite dielectric stacks are actively investigated [4]. These three specific schemes, thermal, ALD, and stacked oxides were selected in this study to compare the trade-offs between the superior interface quality of hightemperature thermal oxides, the low-temperature deposition benefits of ALD, and the potential synergistic effects of a combined stack. Each oxide scheme affects key device parameters such as threshold voltage ( Vth  ), leakage current, channel mobility, and long-term reliability. Therefore, systematic evaluation of different oxide processes is critical for advancing SiC MOSFET performance.

This work investigates three gate oxide formation schemes applied to lateral n -channel 4H−SiC planar MOSFETs. Both capacitance voltage (CV) and current voltage ( IdVg ) characteristics were measured to capture interface-related effects such as hysteresis and trap activity, in addition to standard parametric testing of leakage and breakdown reliability.

Experimental

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The baseline process flow for lateral n -channel 4 H -SiC MOSFETs is shown in Figure 1. Only the gate oxide formation step differs among the three experimental conditions:

Condition 1: 50 nm thermal oxidation +NO annealing at 1350∘C for 1 hr (actual thickness: 52 nm ).

Condition 2: HF surface clean +50 nm thermal ALD +NO annealing at 1250∘C for 1 hr (actual thickness: 43 nm ).

Condition 3: 20 nm thermal oxidation +30 nmALD+NO annealing at 1250∘C for 1 hr (actual thickness: 47 nm ).

[picture]

Fig. 1. Baseline thermal oxidation process flow after implantation and activation.

Fig. 1. Baseline thermal oxidation process flow after implantation and activation.

Electrical characterization:

CP testing: threshold voltage (Vth), leakage (IDSS), and body diode forward drop (VSD). Good die rate was defined as the % of dies falling within median ±3σ.

IdVg sweeps: measured with Vd fixed at a small bias, gate bias swept forward/reverse. Vth extracted at Id=1×10−5 A. Hysteresis window defined as ΔV th between sweeps.

CV sweeps: small-signal AC capacitance measurement across accumulation and inversion, forward/reverse bias. Frequency dispersion and stretch-out analyzed for trap effects.

IgEOX test: oxide integrity verified by gate leakage breakdown measurement.

Results and Discussion

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Electrical Properties

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Tables 1 and 2 summarize statistical results.

Condition 1 shows the highest Vth (2.49 V), lowest leakage (I DSS: 6.1E-5 A), and best uniformity.

Condition 2 and 3 demonstrate comparable VSD but increased leakage and higher σ, suggesting greater variability.
These differences indicate that ALD-based oxide processes may introduce additional interfacial issues not fully addressed by conventional NO annealing. Furthermore, the variations in Vth and leakage across these schemes are expected to influence the carrier mobility and channel resistance. While not directly measured here, the increased variability in Condition 2 and 3 potentially stems from a higher density of near-interface traps ( Nit ) which can enhance Coulomb scattering, thereby impacting the overall MOSFET conduction performance.

Table 1. Gate oxide thickness and error for Each Gate Oxide Process Condition.

Experiment | Condition 1 | Condition 2 | Condition 3
Ideal = 50 nm | Measure | Error | Measure | Error | Measure | Error
Thickness (nm) | 52 | 4.0% | 43 | 14.0% | 47 | 6.0%

Table 2. Summary of Electrical Performance and Yield for Each Gate Oxide Process Condition.

Experiment | Condition 1 | Condition 2 | Condition 3
Item | Median | RateGood die STDEV | Median | RateGood die STDEV | Median | RateGood die STDEV
Vth (V) | 2.49 | 100.0% 0.06 | 2.13 | 100.0% 0.06 | 2.28 | 97.2% 0.10
IDSS (A) | 6.1E-05 | 100.0% 6.00E-05 | 1.0E-04 | 88.9% 1.10E-03 | 2.9E-04 | 83.3% 1.70E-03
VSD (V) | 3.42 | 100.0% 0.04 | 3.24 | 100.0% 0.04 | 3.24 | 100.0% 0.04

𝐈𝐝𝐕𝐠Characteristics and Hysteresis

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Representative IdVg curves for the three conditions, measured at a drain bias of VDS=0.1 V, are shown in Figure 2. All devices exhibit complete channel switching behavior. Extracted hysteresis windows are:

Condition 1: ΔV th =0.10 V

Condition 2: ΔV th =0.11 V

Condition 3: ΔV th =0.13 V

Although all shifts are relatively small, the trend clearly indicates that Condition 3 has more active trap states, consistent with its stacked oxide scheme [4]. This increased hysteresis in the stacked structure may be attributed to a higher density of near-interface traps ( Nit ) and border traps, which are often formed at the transition interface between the thermal and ALD layers. Condition 1, with hightemperature NO passivation, shows the most stable switching characteristics, indicating effective reduction of shallow traps at the SiC/SiO2 interface.

[picture]

Fig. 2. (a) Forward and reverse IdVg curves for three conditions. (b) Curves for Condition 1. (c) Curves for Condition 2. (d) Curves for Condition 3.

Fig. 2. (a) Forward and reverse I d V g curves for three conditions. (b) Curves for Condition 1. (c) Curves for Condition 2. (d) Curves for Condition 3.

CV Characteristics

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Figure 3 shows the CV results measured on dedicated MOS capacitor structures, which reveals distinct electrical characteristics, directly correlated with the oxide layer properties.

[picture]

Fig. 3. CV Curves for 3 Conditions.

Fig. 3. CV Curves for 3 Conditions.

The accumulation capacitance ( Cox ), measured at positive gate bias, inversely correlates with the oxide thickness. Our results show that Condition 2, with a measured thickness of 43 nm , exhibits the highest capacitance ( 8.5×10−8 F/cm2 ). In contrast, Condition 1, at 52 nm , has the lowest capacitance ( 7.1×10−8 F/cm2 ), and Condition 3, at 47 nm , falls in between ( 7.8×10−8 F/cm2 ). This data confirms the expected relationship between oxide thickness and capacitance [5].
The flat band voltage ( VFB ), a key indicator of fixed charge density, shows a surprising trend. The CV curve for Condition 2 is positioned closest to the ideal 0 V( VFB≈−1 V), suggesting it has the lowest positive fixed charge density among the three. Condition 1's curve is the most negatively shifted ( VFB≈−2 V ), indicating a higher concentration of positive fixed charges, despite being a thermal oxidation process. Condition 3's VFB is intermediate ( VFB≈−1.5 V ). This suggests that the NO annealing process at 1250∘C for the ALD film (Condition 2) is more effective at reducing fixed charges than the 1350∘CNO annealing for the thermal oxide (Condition 1). The lower fixed charge in Condition 2 may be attributed to reduced thermal-induced stress compared to the 1350∘C process. In conclusion, while Condition 2 demonstrates the lowest fixed charge density and highest capacitance due to its thinner film, its interface quality is not optimal [6]. This is evidenced by the increased frequency dispersion and stretch-out observed in the CV characteristics, pointing to a higher
density of interface traps ( Dit ) in the ALD-based samples. Conversely, Condition 1 and Condition 3 show better interface quality but suffer from higher fixed charge densities. These results highlight the complex trade-offs between different fabrication processes in achieving optimal electrical properties for MOS devices.

Oxide Reliability (IgEox)

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Figure 4 compares the gate leakage and breakdown characteristics of the three process conditions.

Fig. 4. IgEox Curves for 3 Conditions.

An examination of the initial leakage current reveals a distinct difference. At low electric fields, Condition 2 exhibits a slightly higher initial leakage current compared to Conditions 1 and 3. This observation strongly suggests that defects are present not only within the bulk of the pure ALD film but, more importantly, at the direct interface between the ALD layer and the SiC substrate. Such an interface, formed without an intervening thermal oxidation layer, may contain a higher density of dangling bonds and defects that act as easy pathways for current, even under low-stress conditions [7]. Specifically, the interface chemistry of ALD films on SiC often suffers from residual carbon clusters or sub-oxides (e.g., SiOx ) formed during the initial deposition stages, which are not effectively removed by the 1250∘C NO anneal.
The breakdown behavior also highlights the critical role of the interface. Condition 3, which combines a thermal oxide layer with an ALD layer, shows the weakest performance, experiencing a hard breakdown at a relatively low electric field of approximately 10MV/cm. This premature failure can be attributed to the combined effects of defects from both processes, creating a vulnerable interface at the junction of the thermal oxide and ALD layers, leading to an early breakdown.
In contrast, while the pure thermal oxide in Condition 1 and the pure ALD film in Condition 2 ultimately fail at a higher electric field, their breakdown characteristics differ. Condition 2's curve is notably smooth and free of significant steps, indicating a high-quality, uniform dielectric with superior integrity. Condition 1, however, shows several soft breakdown events sudden increases in leakage current before its final hard breakdown. Despite these soft breakdown events, the ultimate hard breakdown voltage for both Condition 1 and 2 is remarkably close, both occurring around 11.5 to 12MV/cm. The soft breakdown events in Condition 1 and the increased leakage in Conditions 2 and 3 likely stem from localized defect-assisted tunneling. In the ALD-based samples, this is intensified by the high density of near-interface traps ( Nit ) that facilitate trap-assisted tunneling (TAT) at lower fields, acting as precursors to breakdown.

Summary

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This study systematically compared three gate oxide schemes in 4H-SiC planar MOSFETs, revealing nuanced trade-offs in their electrical performance.

Condition 1 (thermal + high-temp NO): This scheme demonstrates the best overall device uniformity and lowest leakage current. The IgEox curve confirms its superior dielectric integrity, showing no soft breakdown events. However, its CV curve is the most negatively shifted, indicating the highest concentration of positive fixed charges among the three.

Condition 2 (ALD + low-temp NO): While this process results in the highest capacitance and the most ideal flat band voltage ( VFB closest to 0 V ), it exhibits slightly higher initial leakage and shows evidence of increased trap activity. This suggests that while the low-temperature NO anneal effectively passivates fixed charges by reducing thermal stress, it is not sufficient to fully mitigate the near-interface traps ( Nit ) and carbon-related defects responsible for gate leakage and soft breakdown.

Condition 3 (stacked thermal/ALD + low-temp NO): This stacked structure demonstrates the weakest oxide reliability, with the earliest hard breakdown and the largest hysteresis window ( ΔVth  ), pointing to the highest trap activity likely at the stacked oxide interface.
In conclusion, our results highlight that no single process provides a clear advantage across all electrical metrics. While ALD-based approaches offer flexibility for future scaling, achieving stable and reliable performance requires dedicated interface engineering to address both fixed charges and trap-assisted conduction mechanisms. Future work should explore optimized pre-cleaning, alternative passivation chemistries, or modified stack architectures to improve the reliability of ALD-based gate oxides.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.15.pdf

C. Kim, et al., Appl. Phys. Lett. 100, 082104 (2012).

M. Östling, R. Ghandi, and C.-M. Zetterling, in Proceedings of the 23rd International Symposium on Power Semiconductor Devices and ICs (ISPSD) (IEEE, 2011), pp. 10-17.

P. Jamet, S. Dimitrijev, and P. Tanner, J. Appl. Phys. 90, 5058 (2001).

S. Li, J. Luo, and T. Ye, ECS J. Solid State Sci. Technol. 12, 053006 (2023).

S.K. Sinha and S. Chaudhury, IEEE Trans. Nanotechnol. 12, 958 (2013).

A.B. Renz, et al., Mater. Sci. Semicond. Process. 122, 105527 (2021).

P. Deák, et al., J. Phys. D: Appl. Phys. 40, 6242 (2007).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 21-28

doi: 10.4028/p-0EmUTi

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-05

Accepted:
2026-03-16

Online:
2026-05-20

Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

Harsha Vardhan Manchineni 1,2,a*, Andre Wachowiak 2, b and Thomas Mikolajick 1,2,c

¹NaMLab gGmbH, Nöthnitzer Str. 64a, Dresden, Saxony, 01187, Germany

2 Chair of Nanoelectronics, TU Dresden, Dresden, Saxony, 01187, Germany

a*Harsha.Manchineni@namlab.com, b Andre.Wachowiak@namlab.com, c  Thomas.Mikolajick@namlab.com

Abstract

The increased demand for SiC power MOSFETs requires gate dielectrics with low defect densities and high reliability under high electric field and temperature conditions. In this work, we examine how oxidant chemistry and deposition temperature affect the electrical properties of Al2O3/SiO2 bilayer dielectrics formed in n-type 4H−SiC MOS capacitors. These structures consist of a thin SiO2 interfacial layer, over which Al2O3 is deposited via ALD using three different oxidants at a temperature of 150−350∘C. Electrical characterization shows that the choice of oxidant influences the flat band voltage shift and leakage current density, with a process-dependent trade-off between optimizing each parameter. These findings highlight that precise control of oxidant chemistry during ALD is essential for balancing flat band voltage stability with leakage suppression, and that multilayer-specific conduction models are critical for accurately predicting high electric field leakage characteristics in advanced SiC gate stacks.

Keywords: 4H−SiC MOS capacitors, MOSFET, bilayer gate dielectric, Al2O3/SiO2 stacks, atomic layer deposition (ALD), oxidant chemistry, flat band voltage shift, conduction mechanisms, interface trap density, dielectric strength, high electric field barrier suppression.

Introduction

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Silicon carbide (SiC) has emerged as a leading wide-bandgap semiconductor for high-voltage and high-power electronic devices due to its large critical electric field ( ~3MV/cm ), high electron saturation velocity ( ~2×107 cm/s ), and superior thermal conductivity ( ~3.7 W/cm·K ) [1, 2]. These intrinsic material properties enable the fabrication of compact devices with reduced specific onresistance and enhanced efficiency compared to silicon-based power devices [3]. A unique advantage of SiC compared to other wide band gap materials is its ability to form a silicon dioxide (SiO2) through thermal oxidation, enabling the development of SiC MOSFETs with a well-established dielectric system [4]. Thermally grown SiO2/SiC interfaces currently exhibit the lowest interface state density (Dit ) among alternative dielectrics on SiC[5]. However, the Dit  at the SiO2/SiC interface remains one order of magnitude higher than that of conventional SiO2/Si interfaces, leading to mobility degradation, threshold voltage instabilities, and long-term reliability concerns [6-7, 15].
Furthermore, the reliance on SiO2 as a gate dielectric in SiC -based devices constitutes a fundamental limitation that hinders the full exploitation of SiC's superior intrinsic properties. Due to the relatively low dielectric constant of SiO2(κ≈3.9), nearly 2.5 times smaller than that of 4H−SiC(κ≈9.7), a significant portion of the applied bias drops across the oxide rather than the semiconductor, resulting in elevated electric fields within the dielectric [5, 15]. To address this imbalance, high- κ dielectrics have been widely investigated. High-k dielectrics offer several advantages: their higher dielectric constant reduces the equivalent oxide thickness (EOT) while lowering the electric field in the dielectric for a given applied voltage [8, 15]. The significant advantages of using aluminum oxide (Al2O3) are its large bandgap, the large band offsets to SiC, and the high breakdown electric field compared to other high-k dielectrics. [8]. Nevertheless, the direct deposition of high-k dielectrics on SiC surfaces typically introduces higher defect densities than thermal SiO2, mainly due to dangling bonds, oxygen vacancies, and interface reaction products formed during deposition [9, 16]. These
interfacial traps cause charge trapping/detrapping dynamics, manifesting as detrimental threshold voltage shifts in MOSFETs.
A promising strategy to mitigate these challenges uses hybrid gate stacks, where a thin interfacial SiO2 layer (1−2 nm) is thermally grown on SiC , followed by deposition of a thicker high-k dielectric such as Al2O3 by atomic layer deposition (ALD) [6, 9]. This stack architecture leverages the superior interface quality of SiO2 with the enhanced dielectric properties of Al2O3. However, introducing an additional SiO2/ high-k interface creates another potential defect plane, and its structural and electrical properties are strongly influenced by ALD process conditions such as oxidant chemistry, precursor reactivity, and deposition temperature. For instance, oxidants can significantly alter the defect density and chemical bonding at the interface, while deposition temperature dictates the film's density, hydroxyl incorporation, and stoichiometry [10-12]. In addition to interface quality, understanding the conduction mechanisms governing leakage currents is critical for assessing dielectric robustness. Several leakage pathways are typically observed in SiC MOS capacitors with high-k or hybrid dielectrics, including Schottky emission (SE), Poole-Frenkel emission (PFE), trap-assisted tunneling (TAT), and Fowler-Nordheim (FN) tunneling [13, 14]. The dominant leakage mechanism can be extracted by analyzing temperature-dependent leakage current measurements and fitting the respective conduction mechanism models, providing insights into trap distributions and dielectric reliability.
In this work, we systematically study the influence of different ALD oxidants (like O2-plasma, water, Ozone) and deposition temperatures on the dielectric properties of Al2O3/SiO2/SiC stacks, and examine the conduction mechanisms responsible for the observed leakage currents. The breakdown electric field, leakage current density, and conduction mechanisms are analyzed to assess capacitors.

Experimental Methods

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Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated on n-type 4H-SiC substrates with a 2 nmSiO2 interfacial layer. A 20 nmAl2O3 film was deposited by ALD using trimethylaluminum (TMA) as the aluminum precursor and three different oxidants (A, B, C), with deposition temperatures between 150∘C and 350∘C. Following dielectric deposition, a 10 nm TiN layer was deposited by reactive sputtering under ultra-high vacuum to serve as the gate electrode. Then, post-deposition annealing at 480∘C for 1 min in an argon ambient was performed, which kept the Al2O3 film in an amorphous state. The electron-beam evaporation of 10 nmTi/30 nmPt circular pads (diameter varying from 100 to 200μ m ) achieved final contact metallization through a precision shadow mask. Device isolation was performed via dry etching to define the active capacitor regions. A schematic of the test structure is shown in Fig. 1.

Fig. 1. Cross-section schematic of the fabricated MOS capacitor on n-type 4H−SiC with a 2 nmSiO2 interlayer, 20 nm ALD-deposited Al2O3, TiN gate, and Ti/ Pt contacts used for electrical characterization.

Electrical characterization employed a Keithley 4200A-SCS parameter analyzer. Capacitance Voltage ( C−V ) measurements were conducted in dual-sweep mode (from depletion to accumulation and vice versa) to assess the flat band voltage shifts ( ΔVfb ), using an AC modulation frequency of 100 kHz with an amplitude of 25 mV . Current-voltage (I-V) measurements were carried out over a bias range extending into accumulation until dielectric breakdown, with additional temperaturedependent I-V measurements performed from 25∘C to 150∘C to elucidate charge transport
mechanisms and thermal activation effects. The reported leakage current density (AVG J throughout the paper) and ΔVfb represent the average value of five MOSCAP devices.

Results and Discussions

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When MOSCAPs on n-type 4H−SiC are biased in accumulation (at gate voltages higher than the flat band voltage (Vfb) ), electrons from the SiC conduction band can be captured by interface traps or near-interface oxide traps at the SiO2/SiC interface. In addition, carriers may tunnel through the gate dielectric and get trapped in bulk oxide traps within the dielectric layer [4, 17-19]. The capture of these negative charges perturbs the electric field distribution across the MOS structure, producing a positive ΔVfb, resulting in a shift of C−V characteristics. Such trapping is a critical reliability concern, as it can directly translate into threshold voltage instability in MOSFETs and degrade long-term device performance [8]. This trapped charge is often quasi-permanent due to a lack of minority charge carriers: the emission time constants of the responsible traps are much longer than the measurement timescale, strongly preventing detrapping during standard C−V sweeps [18,20]. For thermally grown SiO2 on 4H−SiC, the ΔVfb magnitude is typically small ( ΔVfb≈0.8 V in our measurements). Nevertheless, still quasi-permanent, as evidenced by subsequent sweeps reproducing the initial sweep's reverse branch (see Fig. 2). This behavior is consistent with deep electron traps possessing long emission time constants, e.g., with high emission activation energies, leading to incomplete detrapping within the experimental time window [17,19,21].

[picture]

Fig. 2. Normalized capacitance-voltage characteristics of a 15 nm thick pure SiO2 dielectric on 4 H SiC with a TiN top electrode, showing a 0.8 V positive ΔVfb after three successive measurements. Arrows represent the direction of the sweep. Inset: schematic of the fabricated MOS capacitor test structure.

Fig. 2. Normalized capacitance-voltage characteristics of a 15 nm thick pure S i O 2 dielectric on 4 H SiC with a TiN top electrode, showing a 0.8 V positive Δ V f b after three successive measurements. Arrows represent the direction of the sweep. Inset: schematic of the fabricated MOS capacitor test structure.

Incorporating a high-k dielectric such as Al2O3 can increase the observed ΔVfb compared to pure SiO2. The oxidant chemistry during ALD determines Vfb stability among the other process parameters [10]. Our measurements for a fixed deposition temperature (Fig. 3) reveal that the leakage current density and the ΔVfb vary significantly with the used oxidant. The Vfb of the ideal MOSCAP is expected to be ~1 V due to the work function difference between the TiN electrode and the n-type 4H-SiC [22]. The difference in Vfb observed during the initial upsweep between the MOSCAPs for different oxidants compared to the ideal expectation most likely arises from different amounts of fixed charges located at the interfaces or within the bulk of the Al2O3 layer [8, 14] (Fig. 3A). Oxidant C might act more aggressively on the interface since it causes the highest initial shift in the MOSCAPs. Furthermore, an additional offset in Vfb can also stem from dipole formation at the high- k/SiO2 interface, irrespective of the electrode material, as reported by Iwamoto et al. [22].
Furthermore, a much smaller ΔVfb is observed in our MOSCAPs when oxidant A(ΔVfb~0.4 V) is used compared to oxidants B and C(ΔVfb>2 V) (Fig. 3A). The reduced ΔVfb for oxidant A can be attributed to electron detrapping from bulk or near-interface traps and escaping to the top electrode during the measurement, reducing ΔVfb. This interpretation is based on observed higher leakage current characteristics for oxidant A compared to oxidants B and C (Fig. 3B), which indicate
enhanced pathways facilitating charge carrier transport in the Al2O3 film deposited using oxidant A . While no compromise seems evident for obtaining low ΔVfb and low leakage current, a trade-off emerges: lowering the ΔVfb can often lead to higher leakage current, and vice versa, solely by altering the oxidant chemistry [10]. For oxidants B and C , the influence of deposition temperature on the electrical performance of MOSCAPs is low (Fig. 4). In contrast, by using oxidant A, the MOSCAP exhibited a pronounced improvement in leakage characteristics and dielectric strength within the 200−250∘C window, suggesting optimal film quality and reduced defect density in this regime. However, this temperature range did not coincide with the minimal ΔVfb  observed near 300∘C (Fig. 4).

[picture]

Fig. 3. A. Normalized capacitance-voltage characteristics of MOSCAPs with Al2O3, deposited with different oxidants ( A,B,C ). Numbers indicate the average ΔVfb measured in the initial dual sweep (arrows indicate the sweep direction). B. Average leakage current density for Al2O3 films deposited with different oxidants (A, B, C) as a function of applied electric field. Stars and numbers denote the corresponding dielectric breakdown electric field strength ( EBD ) of Al2O3 films for different oxidants.

Fig. 3. A. Normalized capacitance-voltage characteristics of MOSCAPs with A l 2 O 3 , deposited with different oxidants ( A , B , C ). Numbers indicate the average Δ V f b measured in the initial dual sweep (arrows indicate the sweep direction). B. Average leakage current density for A l 2 O 3 films deposited with different oxidants (A, B, C) as a function of applied electric field. Stars and numbers denote the corresponding dielectric breakdown electric field strength ( E B D ) of A l 2 O 3 films for different oxidants.

[picture]

Fig. 4. A. Flat band voltage shift ( ΔVfb ), B. Average leakage current density at 4MV/cm, and C . Breakdown electric field for Al2O3 films deposited using oxidants A,B, and C as a function of the deposition temperature in Al2O3 ALD deposition.

Fig. 4. A. Flat band voltage shift ( Δ V f b ), B. Average leakage current density at 4 M V / c m , and C . Breakdown electric field for A l 2 O 3 films deposited using oxidants A , B , and C as a function of the deposition temperature in A l 2 O 3 ALD deposition.

To further evaluate leakage behavior, temperature-dependent I-V measurements were performed on Al2O3 films deposited at 300∘C using different oxidants (Fig. 5). Among the three, Al2O3 films deposited with oxidant A exhibited the highest leakage with minimal temperature dependence. In contrast, pronounced temperature sensitivity was observed when oxidants B and C were used, particularly beyond 5MV/cm, where leakage current increased by nearly an order of magnitude between 25∘C and 150∘C. Simultaneously, the dielectric breakdown electric field decreased by approximately 3MV/cm over the same temperature range. At low electric fields ( <2MV/cm ), the leakage current density approached the resolution limit of the parameter analyzer, preventing quantitative comparison. Notably, this low-leakage regime terminated at different electric field strengths for each oxidant, likely due to the initial Vfb differences between the oxidants discussed previously. For example, in the case of oxidant C , the leakage onset occurred near 3MV/cm (Fig. 5).

In the moderate electric field regime ( 2−5MV/cm ), leakage current exhibited a rather low temperature dependence. This suggests that thermally activated processes are less dominant in this range.

[picture]

Fig. 5. Average leakage current density as a function of electric field for Al2O3 films deposited at 300∘C using oxidants A,B, and C in ALD and measured at 25∘C to 150∘C.

Fig. 5. Average leakage current density as a function of electric field for A l 2 O 3 films deposited at 300 ∘ C using oxidants A , B , and C in ALD and measured at 25 ∘ C to 150 ∘ C .

To gain deeper insight into the underlying charge transport mechanism. We fitted the measured current using established conduction models with some free parameters to evaluate the conduction mechanism responsible for the observed leakage [13, 14, 23, 24]. The methodology for this calculation is detailed in [13]. This fitting procedure enabled the extraction of free model parameters. In the moderate electric field regime, the calculated current from the TAT model (analytical expression is mentioned in [23]) closely matched experimental data (see Fig. 6), confirming that TAT is the primary conduction mechanism under these conditions with the following argumentation. Since FN tunneling becomes significant only at high electric fields and PFE is highly temperature dependent, both mechanisms can be discounted as a major contributor. Electrode-limited SE can be ruled out as a major contributor due to the large conduction band offset between the SiO2 interlayer and SiC. Moreover, since the electrode was the same in our experiments and using different oxidants during the deposition of Al2O3 produced distinct leakage current levels, SE can also be excluded as the primary mechanism in this electric field range [13,24]. As a result, we attribute the leakage current in the moderate electric field regime mainly to TAT, which aligns with previous studies on high-k and Al2O3 gate stacks with SiO2 interlayer [13, 14]. The extracted model parameters and calculated results for all three oxidants are shown in Fig. 6, offering quantitative insights into trap characteristics and how they depend on oxidant chemistry. According to the calculation results, the high leakage level for oxidant A is governed by the highest TAT trap density ( Nt ) for traps having an energy of 0.8 eV below the conduction band of the dielectric (Fig. 6A). The absolute Nt values from our calculations might be underestimated by several orders of magnitude, as evidenced in the literature [23]. However, they indicate how the Nt can vary by changing the oxidant chemistry during the ALD deposition.
At high electric fields exceeding 5MV/cm, our MOSCAPs exhibit a pronounced increase in leakage current beyond a certain threshold at a given temperature when oxidants B and C are used, ultimately leading to dielectric breakdown as mentioned earlier. In this regime, none of the conventional conduction models in our simulations yielded physically reasonable parameter values across all tested mechanisms (SE, PFE, FN, TAT). Consequently, the applied models cannot meaningfully reproduce the leakage characteristics with their significant measurement temperature dependence. One plausible explanation is that most analytical formulations of conduction mechanisms are derived for singlelayer dielectric systems. However, the gate stack in our experiments comprises a bilayer (SiO2/Al2O3), where each dielectric has a different band offset relative to 4H−SiC. This structural complexity can significantly alter carrier transport, as carriers may experience sequential barriers and/or mixed conduction pathways not captured by single-layer models.

[picture]

Fig. 7. Simulated energy-band diagrams of the Al2O3/SiO2 bilayer dielectric stack on n-type 4H−SiC under zero external electric field and close-up at average electric fields of 2.5 and 5.0MV/cm.

Fig. 7. Simulated energy-band diagrams of the A l 2 O 3 / S i O 2 bilayer dielectric stack on n-type 4 H − S i C under zero external electric field and close-up at average electric fields of 2.5 and 5.0 M V / c m .

It is therefore plausible that the observed leakage might arise from a combination of bulk-limited and electrode-limited conduction processes, potentially involving multi-step tunneling or hopping conduction through defect states distributed across both layers [25]. Our band-diagram simulations (Fig. 7) show that at high electric fields (above ~5MV/cm ), the electric field-induced band bending becomes so pronounced that the Al2O3 barrier is almost completely suppressed, enabling enhanced carrier injection by direct tunneling through the 2 nmSiO2 layer. This could explain the increase in leakage after 5MV/cm for oxidants B and C. However, our calculation approach was hindered by the lack of a simple analytical expression for direct tunneling through a trapezoidal barrier with a changing electric field. Furthermore, the observed significant temperature dependence of the leakage characteristic in the high electric field region for oxidants B and C may also indicate charge carrier transport through a combination of carrier injection and a bulk trap-related conduction mechanism with thermally activated processes.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

This study investigates how oxidant chemistry and deposition temperature affect the electrical performance and leakage characteristics of Al2O3/SiO2 bilayer gate stacks on n-type 4H−SiC MOS capacitors. Electrical tests with C−V and temperature-dependent I−V measurements show that oxidant chemistry greatly influences the ΔVfb and leakage current density, with a trade-off between these factors. The impact of the deposition temperature was minimal. Trap-assisted tunneling is identified as the primary conduction process in the moderate electric field range, while PooleFrenkel, Schottky emission, and Fowler-Nordheim tunneling are ruled out. At higher electric fields, simple single-layer dielectric models do not fully explain the leakage behavior, likely due to the complex band alignment of the bilayer system. Band diagram simulations reveal significantly high electric field barrier suppression in Al2O3, suggesting a combination of bulk- and electrode-limited conduction with thermally activated processes. These results emphasize the important role of oxidant chemistry in improving device reliability and highlight the need for modeling methods that consider multilayer dielectric stacks in SiC power electronics.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1192.21.pdf

This work was co-financed by the European Union and from tax revenues on the basis of the budget adopted by the Saxon State Parliament in Project: LeistungsSchaltEr, no 100687609.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 29-37

doi: 10.4028/p-C8ENIb

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-20

Accepted:
2026-02-26

Online:
2026-05-20

Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

The original version of this paper is available on https://www.scientific.net/MSF.1192.29.pdf

M. Szabo 1,a*, T. Becker 1, b, M. Jank 1,c and T. Erlbacher 2, d

1 Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Schottkystraße 10, 91058, Erlangen, Germany

2 Nexperia Germany GmbH, Stresemannallee 101, 22529 Hamburg, Germany

a* maximilian.szabo@iisb.fraunhofer.de, b  tom.becker@iisb.fraunhofer.de, c michael.jank@iisb.fraunhofer.de, d Tobias.Erlbacher@nexperia.com

Keywords: 4H-SiC, capacitors, metal-oxide-semiconductor (MOS), trench, trench sidewall capacitance, linear component separation.

Abstract

This work proposes a linear, area-based component separation method to extract an effective trench sidewall capacitance from C−V measurements of 4H−SiC UMOS capacitors. Devices were fabricated with two gate-oxide schemes LPCVD TEOS and low-temperature oxidation of LPCVD polysilicon and characterized by I-V and C-V measurements. Planar capacitors show breakdown strength above 9MV/cm. Least-squares decomposition of layout-dependent capacitances enabled the separation of mesa, sidewall and bottom contributions. Additionally, this applying this approach revealed trench-pitch dependent depletion and larger wafer-level thickness variation for the polysilicon-oxidation flow. Reconstruction errors up to 20% indicate that spacing-dependent depletion, corner curvature, fringe and field-oxide capacitances exceed the simple parallel-capacitor model.

Introduction

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Reducing the on-state resistance ( RDS(on) ) of silicon carbide ( SiC ) metal-oxide-semiconductor fieldeffect transistors (MOSFETs) remains a major driver for research and development. State-of-the-art SiC trench MOSFETs (UMOSFETs) reduce RDS( on ) by increasing the channel width per unit area and lowering internal series resistance. Consequently, channel resistance becomes more dominant, and low channel mobility remains as a limiting factor for these devices. High channel resistance is mainly caused by the high density of interface traps ( Dit ) present at the SiO2/SiC interface. Sophisticated optimization processes have been developed to reduce these interface traps. These include preoxidation etching in hydrogen atmosphere [1], high temperature oxidation, post-oxidation annealing in N2 and NO[2,3], as well as the use of chemical vapor deposition (CVD) [1,2], low- pressure chemical vapor deposition (LPCVD) [3], and low-temperature oxidation of polycrystalline silicon [2]. Most of the processes have only been evaluated on planar MOS capacitors (MOSCaps) as the measurement and evaluation of Dit  for the UMOS relevant trench sidewall is a challenge. Results from planar devices do not transfer to trench devices one-to-one due to different crystal orientations and the possibility of etch-induced interface modifications. In this work, we investigate the behavior of Trench MOSCaps (UMOSCaps) with gate oxides fabricated by LPCVD and low-temperature oxidation of undoped LPCVD polysilicon. We propose a method to extract an effective sidewall capacitance and an effective Dit, enabling qualitative comparison between gate-oxide fabrication methods. We also investigate the breakdown behavior of the gate oxides.

Device Fabrication

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The MOSCap fabrication process Fig 1 (a) follows the processing of a SiC-UMOS closely [4]. The structure of the UMOSCaps is depicted in Fig. 1 b. To fabricate both samples an n-type epitaxy layer with a thickness of 12.79±0.34μ m and a nitrogen concentration of 9.55*1015±0.34*1014 cm−3 suitable for 1.2 kV class UMOSFETs, was grown on commercial six inch 4H-SiC substrates. A 1.5μ m thick CVDSiO2 hard mask was deposited and patterned by stepper lithography and structured
by dry etching. Subsequently, SiC trenches with a target depth of 1.3μ m were etched using an ICP dry etching process described by Rusch et al. [5]. The trench depth was measured by structured illumination microscopy over the full wafer and was 1.23±0.01μ m for sample 1 and 1.21±0.01μ m for sample 2 (Fig. 1 (d)). A high-temperature H2 reshape was applied to round the trench top and bottom corners, mitigating field crowding and premature gate-oxide breakdown [4]. Trench geometry was confirmed by focused-ion-beam (FIB) cross-section SEM measurement (Fig. 1 (c)). The measurement of 1.27μ m indicated that structured illumination microscopy underestimated the trench depth by approximately 50 nm . This difference between FIB-SEM and microscopy must be considered when using the optical measurement for further wafer level evaluation.

[picture]

Fig. 1. a) Process flow for UMOSCaps. b) Schematic of fabricated devices. c) FIB-SEM cross-section of a 1μ m wide trench on sample 1 after trench reshape process. d) Wafer map of trench depth measured by structured illumination microscopy on sample 1. e) FIB-SEM cross-section of a final device on sample 1 (LPCVD TEOS oxide). f) FIB-SEM cross-section on a final device on sample 2 (oxidized LPCVD polysilicon).

Fig. 1. a) Process flow for UMOSCaps. b) Schematic of fabricated devices. c) FIB-SEM cross-section of a 1 μ m wide trench on sample 1 after trench reshape process. d) Wafer map of trench depth measured by structured illumination microscopy on sample 1. e) FIB-SEM cross-section of a final device on sample 1 (LPCVD TEOS oxide). f) FIB-SEM cross-section on a final device on sample 2 (oxidized LPCVD polysilicon).

Two approaches to form the gate oxide were used. For sample 1 a sacrificial oxide was grown after the trench reshape process and removed in buffered oxide etch. SiO2 was then deposited by low pressure CVD at a temperature of 710∘C and a pressure of 0.133 mbar using TEOS as a precursor which was subsequently densified at 900∘C to form a layer with 87.7±0.4 nm thickness [3]. For sample 2, undoped polysilicon with a thickness of 32.5±0.4 nm was deposited and oxidized at 850∘C for 8 h in O2 atmosphere. This process was based on a work reported by [2]. Both wafers underwent NO annealing at 1300∘C for 1 h ; post-anneal oxide thicknesses were 94.5±0.6 nm (sample 1 Fig. 1 (e)) and 66.6±0.8 nm (sample 2 Fig. 1 (f)) measured by ellipsometry. In situ phosphorus-doped polysilicon was deposited by LPCVD as the gate electrode and patterned by dry etching to form pads of 1.0 mm2,0.5 mm2, and 0.316 mm2. A 600 nm TEOS oxide was deposited as a field oxide and contact windows were opened by dry etching. Frontside metallization consisted of 100 nm Ti and 3μmAl sputtered onto the frontside and patterned. On the backside, a NiAl contact was sputtered and laser-annealed to form an ohmic contact to the SiC substrate, followed by Al backside metallization [6].

Results and Discussion

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Breakdown Evaluation.

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To evaluate the gate oxides, current voltage measurements (I-V) were done on 40 devices per design. The applied voltage was ramped from 0 V to 100 V and the measurement was stopped at a current compliance of 10 mA . Fig 2 (a) shows the averaged curves of the measurements. Because of the different gate oxide thicknesses of the two gate oxide processes and the variance in the oxide thickness on the trench sidewall, bottom and mesa (Fig. 1 (e) (f)) the current is plotted over the electric field on the trench mesa. To calculate this field the average oxide thickness on the wafer after NO annealing measured via ellipsometry is used (Sample 194.5 nm and Sample 266.6 nm ). The planar designs show a high breakdown field of above 9MV/cm for both gate oxides. Sample 2 shows an earlier onset of Fowler-Nordheim tunneling which might suggest a reduced oxide quality or additional thickness variation in the planar devices.

[picture]

Fig. 2. Leakage current of planar and trenched devices at room temperature and for trenched devices at 175∘C. The electric field is calculated for a) the planar mesa top and b) for the planar devices in the mesa top and for the trenched devices in the smallest oxide thickness.

Fig. 2. Leakage current of planar and trenched devices at room temperature and for trenched devices at 175 ∘ C . The electric field is calculated for a) the planar mesa top and b) for the planar devices in the mesa top and for the trenched devices in the smallest oxide thickness.

For the trench devices the breakdown electric field is significantly lower than for the planar devices. This is mainly caused by the difference in oxide thickness at the trench bottom and trench corners that can be observed for both sample 1 and sample 2. The electric field for the trench capacitors becomes closer to that of the planar devices when calculating with the lowest oxide thickness measured via FIB-SEM. For sample 1 this is the trench bottom with 58.7 nm and for sample 2 the top corner with 54.1 nm . However, the breakdown fields using this approach are slightly larger than for the planar devices which is not expected. This overestimation occurs because the simple calculation does not include field crowding effects that occur on the corners of the trench. Here, only one representative trench was measured by FIB-SEM meaning so it is also possible that even lower oxide thickness is present in the device. Moreover, for a given current value, the current density in the UMOSCap is lower than the current density in the planar MOSCap with identical metallization area.

Capacitance-Voltage measurements.

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Full-wafer high-frequency capacitance measurements ( C−V ) at 100 kHz were performed at room temperature. Depicted in Fig. 3 (a) are the forward and backward capacitance curves for 40 devices on both samples for planar MOSCaps (Table 1, design 1) and UMOSCaps (Table 1, design 3), normalized with respect to the accumulation capacitance. No hysteresis can be observed regardless of design and oxide process. When comparing the absolute values of planar MOSCaps on sample 1 and sample 2, an increased spread of Cox can be observed for the polysilicon oxidation process. Most likely this scheme yields a higher variation in layer thickness over the wafer than the TEOS process. For the planar devices the difference in flat-band voltage can be attributed to the different oxide thickness of both samples as well as different interface properties. For the trench devices, several
distinct slopes can be observed in depletion and weak inversion. This is particularly apparent for the devices on sample 2. The steeper slopes at approx. -6.2 V and -2.9 V are attributed to the different oxide thickness that occurs on the trench mesa, bottom and sidewall.

[picture]

Fig. 3. a) Normalized capacitance-voltage measurements at 100 kHz for trenched and planar designs with 40 devices respectively and the two different gate oxide processes. b) Capacitance-voltage measurements at 100 kHz for all 12 different designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide).

Fig. 3. a) Normalized capacitance-voltage measurements at 100 kHz for trenched and planar designs with 40 devices respectively and the two different gate oxide processes. b) Capacitance-voltage measurements at 100 kHz for all 12 different designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide).

However, the steeper slopes at approx. -10.8 V (sample 2) and -7.7 V (sample 1) are caused by the extension of the space charge region into the trench sidewalls until the trench area is fully depleted and the space charge region starts to extend beyond the trench structure into the semiconductor [7]. This causes a change in effective capacitor surface area leading to in an abrupt reduction in capacitance. This effect is commonly used as the shielding effect in double UMOS transistors and is sensitive to the distance between two trenches [4]. Fig. 3 b) shows representative CV curves of the designs listed in table 1 on one stepper field in the center of sample 1.

Linear Component Separation.

The original version of this paper is available on https://www.scientific.net/MSF.1192.29.pdf

In this work we expand on work reported by Lim [4], Banzhaf [7] and Guo et al. [8] which all investigated SiC UMOSCaps. The capacitance of a trench MOS capacitor is simplified to consist of three parallel capacitors: the capacitance on the top of the trench Cm, the trench sidewall Cs and the trench bottom Cb. The total capacitance C is the sum of these three contributions:

C(V)=AmCm(V)+AsCs(V)+AbCb(V).(1)

Here, Am,As and Ab, represent the effective areas of the trench top, sidewall, and bottom, respectively. The knowledge about the effective areas allows for determination of the different capacitances by solving a linear system of equations. It is possible to extend this model by adding additional terms in case of significant corner rounding at the trench top and bottom, which has not been done in the scope of this work. A variation of the trench depth might be necessary to increase the accuracy of the method when trying to extract the influence of trench rounding. When no trench depth variation is included in the evaluated devices the influence of the rounding cannot be isolated from the trench sidewall because the area of the rounding is correlated to the trench sidewall area. It should also be mentioned that the behavior of a curved MOSCap is not equivalent to a planar structure and additional considerations to deal with the electrostatics (e.g. field crowding) of such a component must be considered when adding this to the model [9]. In addition to this, the real devices also include a fourth capacitance component which is caused by the field oxide depicted in Fig. 1 (b). Because of the low contribution to the overall capacitance ( <4 %) and insufficient variation of this parameter from design to design, this component is neglected in the investigation. Table 1 lists the different designs that are evaluated. Three different types of designs are used. Planar designs where no trench is etched, recess designs where one large continuous trench is etched, and trench designs were several trench stripes
with the same trench width and spacing (mesa width) are etched. The analytical calculation of the corresponding areas for the designs is described in literature [4,7]. For this calculation, the device areas are taken from the mask layout as drawn, the trench width is confirmed by focused-ion-beam (FIB) cross-section SEM measurements (Fig. 1 (c)), and wafer-level trench depth is measured by structured illumination microscopy (Fig. 1 (d)) which is verified by focused-ion-beam cross-section SEM measurements (Fig. 1 (c)). The area calculation is corrected by the top and bottom corner rounding measured by FIB-SEM. As described earlier, there is some measurement error for the wafer level measurements. For the following investigations, the trench depth measured by FIB-SEM on a device in the wafer center is used and it is assumed that the trench depth does not change from device to device as they are close together on the wafer. For future wafer level measurements, the accuracy of the optical trench depth measurement must be improved and a method to accurately determine the trench depth of each device such as optical critical dimension scatterometry should be considered to increase the accuracy of the method.

Table 1. Sizing of fabricated devices.

Design | Type | Area [mm²] | Trench width [μm] | Mesa width [μm] | Effective area [10³ μm²]
|  |  |  |  | Sidewall | Mesa | Bottom
1 | Planar | 1 | 0 | 1000 | 0 | 100 | 0
2 | Recess | 1 | 996 | 2 | 0.36 | 0.72 | 99.12
3 | Trench | 1 | 1 | 1 | 133.83 | 20.71 | 19.81
4 | Trench | 1 | 1 | 2 | 79.24 | 49.39 | 15.39
5 | Planar | 0.5 | 0 | 707 | 0 | 50 | 0
6 | Recess | 0.5 | 703 | 2 | 0.25 | 0.51 | 49.38
7 | Trench | 0.5 | 1 | 1 | 66.47 | 10.62 | 9.84
8 | Trench | 0.5 | 1 | 2 | 39.34 | 24.88 | 7.64
9 | Planar | 0.316 | 0 | 562 | 0 | 31.6 | 0
10 | Recess | 0.316 | 558 | 2 | 0.20 | 0.40 | 31.11
11 | Trench | 0.316 | 1 | 1 | 42.04 | 6.72 | 6.20
12 | Trench | 0.316 | 1 | 2 | 24.91 | 15.72 | 4.81

With the effective areas shown in Table 1 and equation 1 an overdetermined system of linear equations is formed which is then solved pointwise for every applied voltage. At least three different trench MOSCap designs with different area ratios are needed to solve the system of linear equations. Because of process variation, it is beneficial to increase the accuracy of the estimation by forming an overdetermined system of equations which is then solved by fitting a least-squares solution to the linear matrix equation. This yields an effective per-area capacitance for the trench mesa, trench sidewall, and trench, as bottom depicted in Fig. 4 for both, sample 1 and sample 2.

[picture]

Fig. 4. Capacitance per area over voltage for trench mesa, bottom and sidewall calculated by linear component separation for the two different gate oxides.

Fig. 4. Capacitance per area over voltage for trench mesa, bottom and sidewall calculated by linear component separation for the two different gate oxides.

For sample 1, the area-related oxide capacitance of the trench sidewall is larger than both the mesa and bottom capacitances. This suggests that the oxide thickness of the trench sidewall is lower than the oxide thickness of both the mesa and the bottom. As can be seen in Fig. 1 (e) this clearly is not the case. Sample 2 shows a similar effect even though here the oxide thickness of the sidewall is significantly larger than at the mesa and bottom. Some of this behavior can likely be attributed to the combination of trench sidewall and corner rounding to one capacitance. Previously, we suggested that the different slopes in the C-V curves are caused by the different oxide thicknesses. In the simple component separation, however, all curves show these different slopes. The curve for the mesa should not show this effect as no thickness variation caused by the trench geometries occurs. This leads to the conclusion that the three different components are not sufficiently separated. To verify the accuracy of the method the theoretical C-V curves for different designs are calculated using Eq. 1 (Fig. 5 (a) dashed lines) by multiplying the corresponding areas for sidewall, mesa and bottom listed in Table 1 with the calculated effective per area capacitance depicted in Fig. 4. When comparing them to the actual measurements (Fig. 5 (a) solid lines), good alignment can only be seen for the fully trench recessed devices (designs 2, 6 and 10). Fig. 5 (b) shows the relative error between the measurements and modelled capacitance of all 12 designs. It can be observed that the different design types (planar, recess, 1μ m trench /1μ m mesa and 1μ m trench /2μ m mesa) show characteristic error curves.

[picture]

Fig. 5. a) Measured capacitance-voltage characteristics at 100 kHz (solid lines) for all 12 designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide), compared with the corresponding curves reconstructed from the linearly separated mesa, sidewall, and bottom capacitances (dashed lines, using Eq. (1) and the areas in Table 1). b) Relative error between reconstructed and measured capacitances as a function of gate voltage for all designs, illustrating the systematic, design-dependent deviation of the simple parallel-capacitor model.

Fig. 5. a) Measured capacitance-voltage characteristics at 100 kHz (solid lines) for all 12 designs on one stepper field in the center of sample 1 (LPCVD TEOS oxide), compared with the corresponding curves reconstructed from the linearly separated mesa, sidewall, and bottom capacitances (dashed lines, using Eq. (1) and the areas in Table 1). b) Relative error between reconstructed and measured capacitances as a function of gate voltage for all designs, illustrating the systematic, design-dependent deviation of the simple parallel-capacitor model.

The largest error is observed for the devices with 1μ m trench and 2μ m mesa widths at -7.2 V where the curve calculated via linear component separation underestimates the actual capacitance of the devices by up to 20%. Close to the voltage the error curves of the designs with 1μ m trench width and 1μ m mesa width show a minimum. This leads to the conclusion that there is another effect which the linear component separation assigns to the trench sidewall but is caused by the difference in mesa width. This effect is the previously described extension of the space charge region into the trench sidewalls. Because this effect does not only depend on the area of the different capacitance components but on the spacing of the trenches the simple linear combination of parallel capacitors cannot model this behavior and therefore ascribes the corresponding capacitance to the trench sidewall. A more refined compact model could represent the lateral extension of the depletion region between neighboring trenches by an additional series capacitance that depends on trench pitch and doping, while keeping the oxide-related contributions as parallel capacitors. Corner and field-oxide effects could likewise be represented by separate capacitance elements. However, introducing these additional components would substantially increase the number of unknown parameters. A calibrated TCAD simulations model might allow for a robust extraction of the depletion capacitance. In addition to this the influence of the corner rounding could also be more accurately be described through TCAD simulations.

Density of interface states.

The original version of this paper is available on https://www.scientific.net/MSF.1192.29.pdf

For the evaluation of the density of interface states manual high and low frequency measurements (quasistatic and 1 MHz ) and manual measurements at 100 kHz for the Terman Dit  determination method equivalent to the full wafer C-V measurements on four devices per wafer were done. Fig. 6 (a) shows the density of interface states for design 1 (planar) and design 3 ( 1μ m trench/ 1μ m mesa) on sample 1. The measured values are in good agreement with previously reported results for planar MOSCaps using LPCVD TEOS oxides annealed in NO [3]. The differences between the high-low method and the Terman method are well reported [9]. However, because of measurement time and setup requirements of the low frequency measurement for the high-low method, it is not suitable for wafer level measurements. When applying the high low-method to the trench devices and assuming a constant surface potential and no variation of the oxide thickness the difference between the planar structures and the trench devices is not too large [10]. The Terman method shows an increased deviation between the trench and planar designs.

[picture]

Fig. 6. a) Average interface state density determined by the high-low and Terman methods for four devices per design for planar and trench MOSCaps on sample 1. b) Calculated effective Dit  for the trench sidewall, mesa and bottom with the Terman method.

Fig. 6. a) Average interface state density determined by the high-low and Terman methods for four devices per design for planar and trench MOSCaps on sample 1. b) Calculated effective D it for the trench sidewall, mesa and bottom with the Terman method.

An effective Dit  for the three calculated capacitance components for design 3 is evaluated for sample 1 and sample 2. Overall, these values are not quantitatively accurate as many influences that were previously described are not included in this model. The extracted quantities should therefore be regarded as effective Dit  values, which also contain these parasitic effects. The behavior of the mesa top and trench bottom follows the Terman evaluation for the planar devices, while the trench sidewall follows the trenched devices. Sample 1 shows a lower effective Dit  for the trench sidewall leading to the conclusion that between the two compared oxide processes the LPCVD TEOS oxide is better suited for fabricating UMOSFETs. However, because of the different SiO2 thickness distributions and the model errors of up to 20%, this apparent difference cannot be interpreted as a rigorous quantitative statement about the physical Dit  at the trench sidewall.

Summary and Outlook

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In this work, we demonstrate a linear component separation approach to extract effective sidewall capacitances from 4H-SiC UMOSCaps fabricated with LPCVD TEOS and polysilicon oxidation. While planar MOSCaps exhibit good breakdown performance trench devices show reduced breakdown strength attributed to non-uniform oxide thickness and corner field crowding.

It was possible to separate the capacitance-voltage measurement with the proposed linear component separation. However, significant systematic deviations between measured and reconstructed capacitances indicate that the simple parallel capacitor model inadequately captures the complex electrostatic behavior of trench structures. The observed errors correlate with design geometry, suggesting that mesa spacing-dependent depletion, field oxide contributions, and trench corner effects cannot be neglected. Future improvements should incorporate physics-based models for lateral depletion behavior and an expansion from point wise solving the linear matrix equation to form a linear system of functions and solving for these functions. Integration with TCAD simulations could provide deeper insights into the underlying physics and enable development of more accurate analytical models.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.29.pdf

T. Keita et al., Formation of high-quality SiC(0001)/SiO2 structures by excluding oxidation process with H2 etching before SiO2 deposition and high-temperature N2 annealing, Appl. Phys. Express. 13 (2020) 121002.

T. Kobayashi et al., Design and formation of interfaces via Si deposition followed by low temperature oxidation and high-temperature nitridation, Appl. Phys. Express 13 (2020) 091003.

M. Lim et al., Pre-Deposition Interfacial Oxidation and Post-Deposition Interface Nitridation of LPCVD TEOS Used as Gate Dielectric on 4H-SiC, MSF. 1004 (2020) 535-40.

M. Lim, Modeling and Verification of Trench MOS Integration using Trench-FirstTechnology, Ph.D. dissertation, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2023.

O. Rusch et al., Increasing 4H-SiC Trench Depth by Improving the Dry Etch Selectivity towards the Oxide Hard Mask, SSP 359 (2024) 193-200.

C. Hellinger et al., Low-Ohmic Nickel Contacts on N-Type 4H-SiC by Surface Roughness Dependent Laser Annealing Energy Density Optimization, SSP 359 (2024) 113-118.

C. Banzhaf, Entwicklung und Charakterisierung von Trench-Gate-Strukturen für 4H-SiC Leistungs-MOSFETs, Shaker Verlag, Aachen, 2016.

Z. Guo et al., Extraction of the Trench Sidewall Capacitances in an n-Type 4H-SiC Trench Metal- Oxide-Semiconductor Structure, IEEE Trans. Electron Devices vol. 68, no. 6 (2021) 2879-2885.

N. Yoshida et al., Extraction of interface state density at interfaces based on impedance measurements with different temperatures, Thin Solid Films 557 (2014) 237-240.

C. Banzhaf et. al., Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures. MSF, 740-742. (2013) 691-694.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 39-45

doi: 10.4028/p-Am6ufR

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-14

Revised:
2025-12-24

Accepted:
2026-02-26

Online:
2026-05-20

Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

Masao Sakuraba 1,2,a*, Tatsunori Oki 2,5,b, Satoshi Watanabe 1,6,c, Shigeo Sato 1,2, d, Iori Morita 1,e, Tetsuya Ueno 2,f, Seima Sato 2, g, Hiroyuki Nagasawa 3, h, Yukimune Watanabe 4,i and Maki Suemitsu 3,j

1 Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, 2-1-1 Katahira, Aoba-ku, Sendai 980-8577, Japan

2 Graduate School of Engineering, Tohoku University, 6-6 Aramaki Aza Aoba, Aoba-ku, Sendai 980-8579, Japan

3 CUSIC Inc., 2-2-10 Chuo, Aoba, Sendai, Miyagi, 980-0021, Japan

4 SiCure, 3−4−10 Meieki, Nakamura-ku, Nagoya, 450-0002, Japan

5 Tokyo Electron Miyagi Ltd., 1-1 Techno-Hills, Taiwa-cho, Kurokawa-gun, Miyagi 981-3629, Japan

6 CIES, Tohoku Univ., 468-1 Aramaki Aza Aoba, Aoba-ku, Sendai 980-8572, Japan

a*  sakuraba.masao@myad.jp, b  tatunori32@gmail.com, c  satoshi.watanabe.e2@tohoku.ac.jp,

d shigeo@tohoku.ac.jp, e iori.morita.c6@tohoku.ac.jp, f ueno.tetsuya.t2@dc.tohoku.ac.jp,

s  sato.seima.q2@dc.tohoku.ac.jp, h  nags@cusic.co.jp, 'y.watanabe@sicure.jp, j  suemitsu@cusic.co.jp

Abstract

C}-\mathrm{SiC}) with a moderate band gap and a large electron affinity is expected to have superior long-term stability against performance degradation. We have fabricated Al-gate MOS diodes in 3C-on- 4H−SiC and 4H−SiC regions on a simultaneous lateral epitaxy (SLE) wafer. Here, evaluation results of their high-frequency differential capacitance-voltage (C-V) characteristics are reported and, from suggested band diagrams, carrier transport involved in the phenomena are considered. In the case of n−-type 3C-on-4H-SiC MOS diode, increase in capacitance due to fast modulation in the inversion layer charge (hole) concentration can be confirmed in the negative bias below -5 V. 2dimensional hole gas ( 2 DHG ) is considered at the Si -face 3C/4H heterointerface negatively charged by spontaneous polarization and is expected to be an effective supply source of holes. Especially in the case of p-type 3C-on-4H-SiC MOS diode, it is considered that injection of holes from neutral p type region into the heterointerface induces compensation of the fixed charges and lowering of the electron barrier at conduction band, and then, electron injection through the barrier causes the fast response of inversion-layer modulation. Appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as "a deep acceptor level" and "2DHG confined by fixed charges". These findings are believed to contribute to building new production platforms of high-performance power semiconductor devices utilizing the polytype heterostructure of SiC .

Keywords: 3C−SiC,4H−SiC, polytype heterostructure, heterointerface, spontaneous polarization, 2 dimensional hole gas (2DHG), metal-oxide-semiconductor (MOS) capacitor, carrier transport.

Introduction

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Metal-oxide-semiconductor (MOS) transistors using 3C-SiC, which have moderate band gap ( 2.4 eV ) and large electron affinity compared to that of 4H−SiC, are expected to have superior long-term stability against performance degradation due to leakage current in the gate insulator in addition to high blocking voltage, low interface trap density and higher n-channel mobility than 300 cm2/(V−s)

[picture]

Fig. 1. Optical micrographs of (a) n−-type and (b) p-type Al-gate MOS diodes using the SLE wafer, (c) schematic cross-sections for a stripe between periodically arranged trenches. SLE trench interval, widths for 3C-SiC stripe, 4H-SiC stripe and length of Al gate square are 150μ m,70μ m, 80μ m and 50μ m, respectively.

Fig. 1. Optical micrographs of (a) n − -type and (b) p -type Al-gate MOS diodes using the SLE wafer, (c) schematic cross-sections for a stripe between periodically arranged trenches. SLE trench interval, widths for 3C-SiC stripe, 4H-SiC stripe and length of Al gate square are 150 μ m , 70 μ m , 80 μ m and 50 μ m , respectively.

at 25∘C [1-3]. Recently, a simultaneous lateral epitaxy (SLE) method has been developed in which 3C−SiC and 4H−SiC are simultaneously epitaxially grown along the basal plane and produced 3 C -on4H polytype heterostructure SiC wafers (SLE wafers) [4-6]. In this presentation, we will report on the fabrication of Al-gate MOS diodes in 3 C -on- 4H−SiC and 4H−SiC regions on a single SLE wafer (Fig. 1) and the evaluation results of their high-frequency differential capacitance-voltage (C-V) characteristics.

Experimental

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One piece cut out from a SLE wafer produced from Si -face 4H−SiC(0001) wafer with off angle of 4∘ along [11 2―0 ] (Fig. 1) was used as an n-type SLE wafer (carrier concentration of about 1016 cm−3 ),  and the other was used as an SLE wafer with a pn junction after high-temperature ion implantation ( 500∘C,Al ions) and heat treatment ( 1700∘C,5 min, Ar atmosphere) to make a 500 nm -thick surface p-type layer (carrier concentration of about 2×1017 cm−3 ). Here, a 24−30 nm-thick thermal oxide ( SiO2 ) film was formed by H2−O2 pyrogenic wet oxidation (1050∘C,4 h). Subsequently, about 100 nm -thick Al film was deposited on the surface, and resist patterns were formed on each area of 3C−SiC and 4H−SiC by photolithography using direct laser drawing exposure method, and Al gate electrodes were formed by wet etching. Finally, about 100 nm -thick Al film was deposited on the back surface and H2 sintering was performed at 400∘C ( 95% N2+5%H2, atmospheric pressure). C−V characteristics of the MOS diodes were measured at room temperature and 50−400kHz for the small amplitude signal superimposed on the gate voltage sweep.

Results and Discussion

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The evaluation results of their C-V characteristics are shown in Fig. 2 and, from suggested band diagrams shown in Figs. 3-6, carrier transport involved in the phenomena are considered. Here, following the advanced research on 3C/4H−SiC polytype heterostructure with spontaneous polarization [7-11], discontinuity at conduction band and negative fixed charges at the 3C/4H heterointerface have been included in the band diagrams. In Figs. 4-6, we are assuming situations in which a depletion layer exists inside far away from the MOS interface in relation to heterointerface and/or the pn junction, and stretching/shrinking of the width of the depletion layer are causing charging/discharging of the depletion layer capacitance ( CD ). Therefore, we added CD in the inset pictures of equivalent circuit.

n−-type 4H-SiC Region.

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In the case of n−-type 4 H -SiC MOS diode (Fig. 2 (a)), the C -V curve indicates that free electrons accumulate at the SiO2/4H−SiC interface in the positive bias (Fig. 3 (b)),

[picture]

Fig. 2. C-V characteristics of the MOS diodes at room temperature and 50−400kHz for the small amplitude signal superimposed on the gate voltage.

Fig. 2. C-V characteristics of the MOS diodes at room temperature and 50 − 400 k H z for the small amplitude signal superimposed on the gate voltage.

while the capacitance decreases monotonically in the negative bias, suggesting the expansion of the depletion layer (Fig. 3 (a)). Here, the depletion is observed near 0 volts, and the flat band voltage is estimated to be about +3 V .

n−-type 3C-on-4H-SiC Region.

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

In the case of n−-type 3C-on-4H-SiC MOS diode (Fig. 2 (b)), free electrons accumulate at the SiO2/3C−SiC interface at around 0 V and in the positive bias, while increase in the capacitance due to fast change in the inversion layer charge (hole) concentration can be confirmed in the negative bias below -5 V . The latter indicates a fast response of minority carrier (hole) concentration at the SiO2/3C−SiC interface, although 3C−SiC has a sufficiently wide band gap to suppress carrier generation at room temperature. It has been reported that 2 -dimensional hole gas ( 2 DHG ) is formed at the Si -face 3C/4H heterointerface negatively charged by a spontaneous polarization [7-8] (Fig. 4). Therefore, it is considered that 2DHG can act as an effective supply source of holes. In contrast, on the C -face 3C/4H-SiC heterointerface, formation of a 2 -dimensional electron gas (2DEG) with channel mobility as high as 780 cm2/(V−s) has been observed [9-11].

p-type4H𝐇-SiC Region.

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

In the case of p-type 4H-SiC MOS diode (Fig. 2 (c)), holes are considered to accumulate at the SiO2/4H−SiC interface in the negative bias (Fig. 5 (a)), while a monotonic decrease in the capacitance can be confirmed in the positive bias, suggesting the expansion of the depletion layer (Fig. 5 (b)). In
addition, since no increase in capacitance is observed in the positive bias, it is believed that conversion from n−-type to p-type by Al ion implantation is successful, and a high-quality pn junction ( pn isolation structure) is formed.

p-type 3C-SiC Region.

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In the case of p-type 3C-SiC MOS diode (Fig. 2 (d)), a drastic increase in the capacitance in the positive bias is clearly observed, indicating not only fast response of the minority carrier (free electron) concentration at the SiO2/3C−SiC interface but also the drastic change of band alignment. From the suggested band diagram shown in Fig. 6 (b), it is considered that (1) holes are injected from the p-type 3C-SiC, (2) the injected holes neutralize the fixed negative charges at the Si-face 3C/4H heterointerface [7-8] and causes (3) barrier lowering to enhance free electron transport from the n−type 4H−SiC (similarly to "parasitic bipolar effect"). When we assume that most of holes in the ptype 3C-SiC layer are injected into the 2DHG, the sheet density is estimated as high as about 1×1013cm−2 from the implanted p-type dopant dose. Additionally, reported sheet hole density of 2DHG induced by spontaneous polarization ( 9.7×1012 cm−2[7] ) is almost the same order. Therefore, neutralization by compensation can be considered to occur effectively at the heterointerface. Here, it can be suggested that a structure of n−-type 4H−SiC/2DHG/n−-type 3C−SiC acts as an npn heterojunction bipolar transistor with high current gain due to a wider-gap emitter and a narrower-

[picture]

Fig. 3. Suggested band diagram of the MOS diode on n−-type 4H−SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 3. Suggested band diagram of the MOS diode on n − -type 4 H − S i C region of SLE wafer under (a) negative and (b) positive bias.

[picture]

Fig. 4. Suggested band diagram of the MOS diode on n−-type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 4. Suggested band diagram of the MOS diode on n − -type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

gap base, in which holes are supplied from p-type 3C-SiC through the depleted n−-type 3C-SiC to 2DHG. On the other hand, in a negative bias of -5 V or less, holes accumulate at the SiO2/3C−SiC interface as shown in Fig. 6 (a), and the flat band voltage is estimated to be about -7 V . It is considered that the conversion from n−-type to p-type by ion implantation is successful in 3C−SiC as well as 4 H SiC . For example, the holes in 2DHG below the gate electrode are considered to move away out of the electrode area ( 50μ m2 ) due to horizontal electric field caused by applying positive gate voltage. Based on such phenomenology, the holes in 2DHG should move because the band bending changes. Here, we assume that "slow modulation of 2DHG" (shown in Figs. 4 and 6) includes two phenomena such as "wide-range horizontal movement of holes during entering/exiting the electrode area along the 2DHG" and "capture/release in the deeply-confined state at the 2DHG". Because the phenomena seemed to be not so quick due to wide range and deepness, it is considered that the modulation might be slow and induce the frequency dependence.

[picture]

Fig. 5. Suggested band diagram of the MOS diode on p-type 4H−SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 5. Suggested band diagram of the MOS diode on p -type 4 H − S i C region of SLE wafer under (a) negative and (b) positive bias.

[picture]

Fig. 6. Suggested band diagram of the MOS diode on p-type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

Fig. 6. Suggested band diagram of the MOS diode on p -type 3C-SiC region of SLE wafer under (a) negative and (b) positive bias.

Frequency Dependence of Capacitance

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

From overview of all the C-V curves, frequency dependence of capacitance is found especially in Fig. 2 (b-d). As such frequence dependence can be seen generally in trap and release process of carrier at specific state, it can be imagined that the larger activation energy results in the slower response. In our case, acceptor level of Al atom doped in 4H−SiC and 3C−SiC is reported to have relatively large
activation energy such as 0.25−0.26eV [12-13], while donor level of N atom doped in 4H−SiC and 3C-SiC has as low activation energy as 0.0653 eV and 0.124 eV in 4H−SiC and 0.018−0.047eV in 3C-SiC [14-15]. Therefore, appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as "a deep acceptor level" and "2DHG confined by fixed charges". Here, during modulation of depletion layer thickness by small-amplitude signal at high frequency for capacitance measurement, holes in the trap and release process at deep acceptor level especially at edge of the depletion layer will contribute to frequency dependence. Additionally, because similar relation can be also imagined between holes and the negative fixed charges at Si-face 3C/4H heterointerface, "2DHG confined by fixed charges" will also contribute to frequency dependence in supplying/receiving holes (Figs. 4 and 6). In another typical case of n−-type 4H-SiC region (Fig. 2. (a)), due to shallow donor level without heterointerface, frequency dependence is considered to become small. Thus, it is suggested that frequency dispersion of capacitance is large in Fig. 2 (b-d) and significant especially at negative bias in Fig. 2 (d) with coexisting effect of the Al doped region and 3C/4H heterointerface. For the detailed contribution of each process, further research is needed. Additionally, it should also be noted that frequency dependence in both the accumulation and inversion capacitance of C−V characteristics can be observed if the series resistance is high [16]. Therefore, concerning the actual effect of series resistance as well as contribution of interface traps at the SiO2/SiC, further investigations are necessary.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

By fabrication of Al -gate MOS diodes in 3 C -on- 4H−SiC and 4H−SiC regions on an SLE wafer, evaluation results of their high-frequency C-V characteristics are reported and, from suggested band diagrams, carrier transport involved in the phenomena are considered. In the case of n−-type 3C-on-4H-SiC MOS diode, increase in capacitance due to fast modulation in the inversion layer charge (hole) concentration can be confirmed in the negative bias below -5 V. 2-dimensional hole gas ( 2 DHG ) is considered at the Si -face 3C/4H heterointerface negatively charged by spontaneous polarization and is expected to be an effective supply source of holes. Especially in the case of p-type 3C-on-4H-SiC MOS diode, it is considered that injection of holes from neutral p-type region into the heterointerface induces compensation of the fixed charges and lowering of the electron barrier at conduction band, and then, electron injection through the barrier causes the fast response of inversionlayer modulation. Appearance of the larger frequency dependence can be understood by inclusion of the larger-activation-energy phenomena, such as "a deep acceptor level" and "2DHG confined by fixed charges". These phenomena can be useful sometimes, but they can also be a hindrance if they are used improperly. Strategy of elimination or utilization for such phenomena will be important for breakthroughs in the novel semiconductor device development. These findings are believed to contribute to building new production platforms of high-performance power semiconductor devices utilizing the polytype heterostructure of SiC.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

This work was partly supported by Grant-in-Aid for Scientific Research(C) (No. 24K08267) from the JSPS in Japan and the Cooperative Research Project Program of the Research Institute of Electrical Communication, Tohoku University.

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The original version of this paper is available on https://www.scientific.net/MSF.1192.39.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 47-52

doi: 10.4028/p-8XxBpT

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-16

Revised:
2025-12-16

Accepted:
2026-02-26

Online:
2026-05-20

Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

Koushik Ramadoss 1,a*, Joshua Holt 2, b, Lucien Date 3,c, Safdar Muhammad 4, d, Jesse Kalliomaki 4,e, Fernanda Albrechtvechietti 4,f, William Charles 5, g, Athena Pang 2,h, Shubhendra Jain 5,i, Benjamin Briggs 5,j, Ludovico Megalini 2,k, Michael Chudzik 2,I, Dallas Morisette 1, m and James Cooper 1,n

1 School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA

2 Applied Materials, 3325 Scott BIdv., Santa Clara, CA 95054, USA

3 Applied Materials, Kapeldreef 75, Leuven, BEL 3001, Belgium

4Applied Materials, Masalantie 365, 02430, Masala, Finland

5 Applied Materials, 1 Broadway, Cambridge, MA 02142, USA

a*kramado@purdue.edu, b Joshua_Holt@amat.com, c lucien_date@amat.com,

d  safdar_muhammad@amat.com, e  jesse_kalliomaki@amat.com,

f fernanda_albrechtvechietti@amat.com, g william_charles@amat.com, h Athena_Pang@amat.com,

iShubhendra_Jain@amat.com, jbenjamin_briggs@amat.com, kludovico_megalini@amat.com, 

I  michael_chudzik@amat.com, m  morisett@purdue.edu, ncooperj@purdue.edu 

Abstract

In this work, we demonstrate a novel oxidation-free gate oxide process consisting of a twostep surface preparation treatment, followed by atomic layer deposition of SiO2 and a post-deposition anneal in nitrogen. The surface treatment includes a 1300∘C anneal in hydrogen and dilute silane, followed by decoupled plasma nitridation (DPN). Long channel MOSFETs fabricated with this process show a 1.5 X improvement in peak field effect mobility compared with devices utilizing a standard thermal oxide and NO anneal. The MOSFETs had a positive threshold voltage, low gate leakage, and a breakdown field above 8MV/cm.

Keywords: atomic layer deposition, decoupled plasma nitridation, MOSFET, H2 etching.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

Silicon carbide (SiC) is a wide gap semiconductor that is being rapidly adopted in power electronic applications due to its high critical electric field, high thermal conductivity, the availability of highquality large area substrates, and maturing fabrication technology. However, SiC MOSFETs exhibit poor performance due to a high density of interface states, leading to low channel mobility ( <5% of bulk mobility). To mitigate this, various studies have been conducted using deposited gate oxide processes to avoid thermal decomposition of the substrate. These processes include atomic layer deposition (ALD) [1], plasma enhanced CVD [2] [3], and a process we call "poly-ox", wherein a thin film of Si is deposited by chemical vapor deposition (CVD), followed by oxidation of the Si film at a sufficiently low temperature to avoid oxidation of the underlying SiC [4] [5]. Alternatively, other nitridation techniques including nitrogen plasma [6] [7] [8], N2O [9] and high temperature nitrogen anneals [4] have been explored as an alternative to the NO anneal to maximize the nitrogen coverage and improve interface properties. But these methods have negative side-effects such as the incorporation of nitrogen throughout the bulk of the oxide [4], or lead to only marginal improvements in interface properties. In this study, we use an Applied Materials TM  Centura TM  DPN (decoupled plasma nitridation) process in conjunction with an Applied Materials TM  Picosun TM  P300B ALD tool to form an oxidation-free SiO2 gate oxide. Decoupled plasma nitridation is a remote plasma process, capable of directly nitriding the SiC surface within a few tens of seconds, and is therefore particularly suitable for high-volume manufacturing [10] [11] [12] [13] [14]. Optimization of the DPN parameters allows the introduction of a tunable concentration of nitrogen as high as ~1.5×1021/cm3 in a sharply
defined peak at the SiC/SiO2 interface, making the traditionally hours-long and expensive NO or N2O post-deposition nitridation process unnecessary. When combined with a hydrogen + dilute silane surface pretreatment process as described previously [5] [2] [15], MOSFETs formed by this process show a 1.5 X enhancement in peak channel mobility compared to standard MOSFETs prepared by thermal oxidation and NO annealing, as well as a positive threshold voltage, low gate leakage, and a breakdown field greater than 8MV/cm.

Device Fabrication

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

Our oxidation-free gate dielectric process was demonstrated using long-channel MOSFET templates consisting of an n-type 4H−SiC substrate with a 9.0×1015 cm−3n-type epilayer and ion implanted p -body regions having a surface aluminum concentration of 1.6×1016 cm−3, confirmed by SIMS analysis. The source and drain regions consist of highly doped n+regions implanted with nitrogen. The DPN-based process flow used to form the gate oxide is shown in Fig. 1. Before forming the gate oxide, the substrates were first RCA cleaned and subjected to H2 etching in a hot walled CVD furnace (1300∘C,900mbar,10slmH2) for 6 min . During the final 3 minutes of this anneal, a 5%SiH4/H2 mixture was added at a flow rate of 100 sccm , for a silane concentration of 0.05%. This last silane step is critical to minimize and passivate interface defects [5] [2] [15]. Subsequently the samples were subjected to the DPN process with a remote plasma to incorporate nitrogen into the SiC surface, similar to that formed by a post-deposition anneal in NO. A 48 nm thin film of silicon dioxide was then deposited using an Applied Materials Picosun P300B ALD system, and densified by annealing in a N2 ambient at 1200∘C for 30 min . The final MOSFETs were formed with n-type polysilicon gates doped by 800∘C,60 s diffusion from a Filmtronics P509 spin-on phosphorus source, Ni source and drain ohmic contacts formed by rapid thermal annealing at 800∘C for 120 s , and Al top metal pads were deposited and patterned for electrical contacts. The gate poly was also encapsulated by a 300 nm thick PECVD SiO2 prior to the formation of ohmic contacts. The channel length and width are 140μ m and 110μ m respectively. In our experiments, a control sample was prepared by thermal oxidation of SiC in dry O2 followed by NO annealing at 1175∘C for 2 hrs . to give about 50 nm of SiO2 for comparison.

[picture]

Fig. 1. Process flow diagram for DPN based gate oxide process.

Fig. 1. Process flow diagram for DPN based gate oxide process.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

The transfer characteristics of a typical MOSFET fabricated in this manner are shown in Fig 2a.

[picture]

Fig. 2. Transfer characteristics (a) and field-effect mobility (b) as a function of gate voltage for MOSFETs formed by the DPN process in comparison with a standard thermal + NO process.

Fig. 2. Transfer characteristics (a) and field-effect mobility (b) as a function of gate voltage for MOSFETs formed by the DPN process in comparison with a standard thermal + NO process.

The device shows a sharper increase in drain current with a positive but somewhat reduced threshold voltage ( Vth ~1 V ) in comparison to the control sample with a 50 nm thick thermally grown gate oxide and NO anneal. The field effect mobility (Fig. 2b) of a DPN treated device shows a significant 1.5 X improvement ( ~38 cm2/Vs ) as compared to the control sample ( ~25 cm2/Vs ). This increased mobility, reduced threshold voltage, and a sharper turn-on characteristic are all consistent with a significant reduction in the interface state density. It is important to note that these measurements were done on an ion implanted channel with NA=1.6×1016 cm−3. While this p-type doping concentration may be insufficient for practical power devices, it still allows a direct comparison of parameters for the MOSFETs fabricated with the two different gate oxide methods.

[picture]

Fig. 3. a) Normalized CV characteristics of DPN treated circular MOSCAP device (diameter =225μm) compared with Thermal + NO control. b) Comparison of leakage current and oxide breakdown fields for DPN treated device and Thermal + NO control.

Fig. 3. a) Normalized CV characteristics of DPN treated circular MOSCAP device (diameter = 225 μ m ) compared with Thermal + NO control. b) Comparison of leakage current and oxide breakdown fields for DPN treated device and Thermal + NO control.

The high frequency CV characteristics (at 100 kHz in dark conditions) are shown for the DPN treated MOSCAPs (Fig 3a). The normalized CV data shows minimal hysteresis, and a -0.8 V shift in the CV curve compared to the control sample. This shift is consistent with that of a reduction in negative interface charges (interface + fixed charge) of q*3.45×1011C/cm2 and is also consistent with the higher mobility shown in Fig 2b. The DPN treated MOSCAPs also exhibit low leakage current and a high breakdown field ( >8MV/cm ) (Fig. 3b), although somewhat lower breakdown field than the thermal+NO control sample. While nearly ideal breakdown fields have been observed in ALD deposited SiO2 films [16], it is not uncommon for such films to have somewhat lower
breakdown fields than thermal oxides. Further optimization of our process is required to achieve an oxide breakdown field comparable to traditional thermal+NO oxides. Fig. 4 shows a transmission electron microscopy (TEM) cross-section image and electron energy loss spectroscopy (EELS) map across the interface. The image indicates that the N2 is preferentially incorporated at the interface during the DPN treatment with small distribution into the oxide bulk.

[picture]

Fig. 4. TEM micrograph of DPN treated device showing SiO2 thickness of 48 nm . The EELS map of various elements (Nitrogen, Silicon, Oxygen, Carbon) across the device cross section is also shown.

Fig. 4. TEM micrograph of DPN treated device showing S i O 2 thickness of 48 nm . The EELS map of various elements (Nitrogen, Silicon, Oxygen, Carbon) across the device cross section is also shown.

[picture]

Fig. 5. Depth profiles of nitrogen atom concentration near SiC−SiO2 interface and in the bulk SiO2. The peak concentration at the interface is slightly higher than Thermal + NO control.

Fig. 5. Depth profiles of nitrogen atom concentration near S i C − S i O 2 interface and in the bulk S i O 2 . The peak concentration at the interface is slightly higher than Thermal + NO control.

To quantify the concentration of N2 near the interface and in the bulk oxide, depth profiling was performed using SIMS as shown in Fig. 5. The results indicate high concentration of N2 near the interface for DPN treated samples with small amount of N2 present in the bulk of the oxide as well. Further experiments are required to optimize the conditions of DPN treatment and post ALD deposition anneal to further improve the device performance.

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

In summary, we have demonstrated a gate oxide process that reduces the interface defect density to yield a 1.5 X improvement in peak channel mobility while maintaining a small positive threshold voltage. The effectiveness of the DPN process in nitriding the SiC surface in a very short time enables a high-throughput fabrication process and is therefore particularly suitable for high-volume manufacturing of SiC devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

The authors would like to thank the support from the Margot A. and Carl J. Johnson Foundation for financial support. This work was done in part at the Birck Nanotechnology Center, Purdue University. We also acknowledge the assistance from Clas-SiC Wafer Fab.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.47.pdf

R. P. Ramamurthy, D. T. Morisette, V. Amarasinghe and L. C. Feldman, "Thermal-oxidationfree dielectrics for SiC power devices," in 2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2017.

K. Tachiki, M. Kaneko and a. T. Kimoto, "Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of H 2 etching, SiO 2 deposition, and interface nitridation," Applied Physics Express, vol. 14, p. 031001, 2021.

M. Yakut, A. Roy, F. Arith, A. Whitworth, A. Alexander, J. Gryglewicz, J. Sheriff, S. Olsen, K. Vasilevskiy and a. A. O'Neill, "Increasing Mobility in 4H-SiC MOSFETs with Deposited Oxide by In-Situ Nitridation of SiC Surface," Solid State Phenomena, vol. 359, pp. 157-162, 2024.

T. Kobayashi, T. Okuda, K. Tachiki, K. Ito, Y.-i. Matsushita and a. T. Kimoto, "Design and formation of SiC (0001)/SiO2 interfaces via Si deposition followed by low-temperature oxidation and high-temperature nitridation," Applied Physics Express, vol. 13, p. 091003, 2020.

K. Ramadoss, A. Samal, D. T. Morisette and a. J. A. Cooper, "High Mobility SiC MOSFETs Using an Oxidation-Minimizing Process," in Poster presented at 21st International Conference on Silicon Carbide and Related Materials, 2024.

X. Zhu, A. C. Ahyi, M. Li, Z. Chen, J. Rozen, L. C. Feldman and a. J. R. Williams, "The effect of nitrogen plasma anneals on interface trap density and channel mobility for MOS devices," Solid-State Electronics, vol. 57, no. 1, pp. 76-79, 2011.

Modic, Y. Sharma, Y. Xu, G. Liu, A. Ahyi, J. Williams, L. Feldman and a. S. Dhar, "Nitrogen Plasma Processing of SiO2/4H-SiC Interfaces," Journal of Electronic Materials, vol. 43, p. 857-862, 2014.

D.-K. Kim, Y.-S. Kang, K.-S. Jeong, H.-K. Kang, S. W. Cho, K.-B. Chung, H. Kim and a. M.H. Cho, "Effects of spontaneous nitrogen incorporation by a surface caused by plasma nitridation," Journal of Materials Chemistry C, vol. 3, pp. 5078-5088, 2015.

T. Kimoto, H. Kawano, M. Noborio, J. Suda and a. H. Matsunami, "Improved Dielectric and Interface Properties of MOS Structures Processed by Oxide Deposition and N 2 O Annealing," Materials Science Forum, Vols. 527-529, pp. 987-990, 2006.

H. N. Al-Shareef, A. Karamcheti, T. Y. Luo, G. Bersuker, G. A. Brown, R. W. Murto, M. D. Jackson, H. R. Huff, P. Kraus, D. Lopes, C. Olsen and G. Miner, "Device performance of in situ steam generated gate dielectric nitrided by remote plasma nitridation," Applied Physics Letters, vol. 78, pp. 3875-3877, 2001.

Materials, "TSMC Qualifies Applied Materials' Gate Stack System for Its Leading-Edge 65nm Transistor Processes," Applied Materials, Inc, 5 May 2005. [Online]. Available: .

S. W. Lim, T.-Y. Luo and a. J. Jiang, "Mechanism of Silicon Dioxide Decoupled Plasma Nitridation," Japanese Journal of Applied Physics, vol. 45, p. L413, 2006.

M. Tian, K. Chen, C. Wang, T. Guan, Q. Sun and a. D. W. Zhang, "Decoupled Plasma Nitridation (DPN) and Postnitridation Annealing (PNA) Treatment for Metal Boundary Effect Reduction," IEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 2233-2237, 2024.

P. Fiorenza, G. Lorito, L. Vigo, L. Date, J. Holt, M. Vivona, G. Cautiero, A. Cockburn, L. Megalini, M. Chudzik and a. F. Roccaforte, "Decoupled Plasma Nitridation of SiC surface for Interface States Density reduction in MOS Capacitors," in Poster presented at 22nd International Conference on Silicon Carbide and Related Materials, 2025.

T. Kimoto, T. Kobayashi and a. K. Tachiki, "SiC semiconductor device manufacturing method and SiC semiconductor device". United States Patent Application No. 2023/0307503 A1, 28 Sep 2023.

X. Yang, B. Lee and V. Misra, "Electrical Characteristics of SiO2 Deposited by Atomic Layer Deposition on 4H-SiC After Nitrous Oxide Anneal," IEEE Transactions on Electron Devices, vol. 63, p. 2826, 2016.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 53-57

doi: 10.4028/p-2GRnYr

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-01-31

Online:
2026-05-20

Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

Heng Wang 1,a, Yangming Du 1, b, Ji Shu 1,c, Pengwei Zhou 1, d, Yingchen Yang 1,e and Kevin. J. Chen 1,f*

1 The Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong, China

a  hwangfz@connect.ust.hk, b  eeyangmingdu@ust.hk, c  eejayshu@ust.hk, d  pzhouan@connect.ust.hk, e  yyangfx @connect.ust.hk, f  eekjchen@ust.hk

Abstract

In this work, we present a process flow to optimize the SiC/SiO2 gate interface quality for SiC power MOSFETs. The process incorporates high-temperature N2/H2 pretreatment, followed by LPCVD SiO2 deposition and NO post-deposition annealing (PDA). By tailoring the pretreatment conditions, a substantially improved SiC/SiO2 interface with reduced interface trap density ( Dit  ) can be achieved. Furthermore, the gate oxide quality is also characterized by measuring the leakage current and time-dependent dielectric breakdown (TDDB). The results indicate a noticeable improvement in the average breakdown field ( Eox ), thanks to the enhanced SiC surface condition achieved by the N2/H2 pretreatment.

Keywords: 4H−SiC MOS capacitor, SiC/SiO2 interface, high temperature pretreatment, interface trap density, gate leakage current.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

Despite the on-going commercialization, the 4H−SiC power MOSFET still suffers from the traprich SiC/SiO2 MOS gate interface, which affects the field-effect MOS channel mobility, threshold voltage stability, and device lifetime. Attempts to improve the SiC/SiO2 MOS gate interface should continue for improved device performance and reliability. Carbon-related defects (i.e., the carbon clusters) generated during the thermal oxidation process of SiC are identified as a predominant contributor to the high Dit  level [1].

Preventing the thermal oxidation of SiC surface during which the high oxidation temperature (~1,200∘C) could lead to carbon accumulation at the interface, e.g., replacing thermal oxide with deposited oxide (at lower temperature), has been experimented to eliminate the carbon-related defects, thereby improving the quality of SiC/SiO2 interface [2-3]. Nevertheless, carbon-related defects can still form during sacrificial oxidation process. Therefore, an appropriate pretreatment prior to the gate oxide deposition is needed to remove the existing carbon-related defects, thereby obtaining a highquality SiC surface for the subsequent gate oxide deposition process.

In this work, we present a process flow that integrates high temperature N2/H2 pretreatment, LPCVD SiO2 deposition, and NO post deposition annealing (PDA) to optimize the quality of SiC/SiO2 interface. The hydrogen-containing pretreatment enables effective removal of the carbonrelated defects through a layer-by-layer etching process of the defective layers at the SiC surface, preparing a high-quality SiC surface [4]. The LPCVD deposition at 420∘C effectively avoids the thermal oxidation of SiC and the associated carbon clusters, and the subsequent NO PDA further passivates the interface states, pursuing a high-quality SiC/SiO2 gate interface for improved device performance.

Experiment

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SiC/SiO2 MOS capacitors were fabricated on an n-type 4H−SiC(0001) epilayer (donor density: 1×1016 cm−3 ) grown on a n-type substrate [Fig. 1]. The fabrication process starts with a surface pretreatment in a furnace under a gas atmosphere of 95% N2 and 5%H2 at atmospheric pressure. Compared with the pretreatment etching by pure H2[2−3], such N2/H2 gas composition is compatible with standard industrial furnace with high level of safety. Subsequently, a gate oxide layer of ~55 nm was deposited by LPCVD at 420∘C. Afterwards, NO PDA was performed at 1250∘C for 70 min for interface passivation. Finally, circular Al front electrode (diameter: 400μ m ) and Al back contact were deposited and sintered. Following device fabrication, electrical measurements ( C−V and I−V ) and material characterization were performed to evaluate the impact of the proposed process and gain insights into the underlying physical mechanisms.

[picture]

Fig. 1. Procedure and schematic of the proposed fabrication process of MOS capacitors.

Fig. 1. Procedure and schematic of the proposed fabrication process of MOS capacitors.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

To evaluate the quality of SiC/SiO2 interface, Dit  near the conduction band edge ( Ec ) is extracted from the C-V results by using high ( 100 kHz )-low (quasi-static) method. Fig. 2 (a) shows the Dit  distribution profiles of samples pretreated in N2/H2 mixture gas at 1350∘C for different treatment time duration. The lowest Dit  level is obtained in the 30 -min sample. Further prolonging the pretreatment time to 40 min leads to a noticeable increase of Dit , especially in shallow levels close to Ec. The results could be attributed to the layer-by-layer etching process of the SiC defective surface layers by H2. With 30 -min pretreatment, a clean Si -rich layer is exposed with the lowest level of Dit, but further extending the pretreatment time to 40 min exposes the underlying C -rich layer that inherently leads to higher density of Dit . In addition, two Nitrogen-based treatments, i.e., the N2/H2 pretreatment and the NO PDA, could both introduce Nitrogen atoms to passivate the SiC/SiO2 interface and improve its quality. The XPS C 1s spectra of samples without pretreatment and with a 30− min pretreatment were analyzed and compared. The C-C/C-Si ratio decreases from 0.038 to 0.026 after pretreatment, indicating an effective reduction of carbon clusters on the SiC surface due to the N2/H2 pretreatment.

The temperature dependence of the Dit  level during the 30−minN2/H2 pretreatment is also investigated [Fig. 2 (b)]. Samples pretreated at 1350∘C exhibits the lowest Dit  level. At higher temperature ( 1350∘C ), the accelerated etching and passivation reactions outweigh the trap generation from Si−C bond breaking, so the trap removal and passivation process dominants.

[picture]

Fig. 2. Energy distribution of Dit  extracted from samples with different pretreatment (a) time duration and (b) temperature.

Fig. 2. Energy distribution of D it extracted from samples with different pretreatment (a) time duration and (b) temperature.

The layer-by-layer etching process of H2 is verified by the AFM image of the SiC surface selective region pretreatment experiment [Fig. 3]. A layer of SiO2 is deposited and patterned to expose a selected SiC surface region to the N2/H2 pretreatment. After the 30−minN2/H2 pretreatment at 1350∘C, a Si−C bilayer of ~0.5 nm is removed from the SiC surface, exposing the Si-rich surface to improve the quality of SiC/SiO2 interface.

[picture]

Fig. 3. AFM image after selective region N2/H2 pretreatment.

Fig. 3. AFM image after selective region N 2 / H 2 pretreatment.

Any performance benefit introduced by optimizing the fabrication process should come without a penalty in the gate oxide reliability. Most reliability-relevant characteristics including the leakage current and time-dependent dielectric breakdown of the gate oxide from samples with and without the pretreatment ( 1350∘C for 30 min ) were compared. Both the leakage current and the breakdown electric field indicate the N2/H2 pretreatment does not negatively affect the gate oxide quality [Fig. 4 (a)]. Based on the statistical distribution of oxide breakdown electric field in Fig. 4 (b), the devices with N2/H2 pretreatment show a noticeable increase in the average Eox, indicating a better SiC surface was prepared for gate oxide deposition. The relatively large dispersion in the Eox distribution under both conditions is primarily attributed to intrinsic process-induced variations in oxide quality.

[picture]

Fig. 4. (a) Insulating properties of MOS capacitors with and without the pretreatment. (b) Statistical chart of Eox for the two samples.

Fig. 4. (a) Insulating properties of MOS capacitors with and without the pretreatment. (b) Statistical chart of E o x for the two samples.

TDDB test was further performed at room temperature to evaluate the reliability of the gate oxide pretreated at 1350∘C for 30 min [Fig. 5 (a)]. The stress electric field is 8MV/cm,8.25MV/cm, and 8.5MV/cm, with the corresponding Weibull slope (β) value of 0.98,1.16, and 0.94 . This value is relatively low in comparison to that of thermal oxide [5], which is attributed to the compromised quality of the LTO. To project the lifetime of the fabricated MOS capacitors, t63% is plotted against the applied gate electric field, as shown in Fig. 5 (b). From the projection, the lifetime of these devices can reach 10 years at room temperature with a maximum operating electric field of 6.74MV/cm.

[picture]

Fig. 5. (a) Weibull distributions of devices failures at various electric fields; (b) Ten-year lifetime predictions by choosing 63% failure rate.

Fig. 5. (a) Weibull distributions of devices failures at various electric fields; (b) Ten-year lifetime predictions by choosing 63 % failure rate.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

To conclude, the discussed process that integrates N2/H2 pretreatment, gate oxide deposition, and NO post deposition annealing demonstrated effective improvement of the SiC/SiO2 interface by removing the thermal-oxidation-related carbon clusters and the associated Dit.  Meanwhile, the quality of the gate oxide is not compromised by the pretreatment process, which could be further improved by optimizing the deposition method and conditions.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

This work is supported by Hong Kong RGC Strategic Topics Grant under STG3/E-602/23-N.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.53.pdf

Z. Wang, Z. Zhang, S. Liu, C. Shao, J. Robertson, and Y. Guo, Impact of carbon-carbon defects at the SiO2/4H−SiC(0001) interface: a first-principles calculation, Journal of Physics D: Applied Physics 55.2 (2021): 025109.

K. Tachiki, M. Kaneko, and T. Kimoto, Mobility improvement of 4H-SiC (0001) MOSFETs by a three-step process of etching, deposition, and interface nitridation, Applied physics express 14.3 (2021): 031001.

K. Tachiki, M. Kaneko, T. Kobayashi, and T. Kimoto, Formation of high-quality SiC structures by excluding oxidation process with etching before deposition and high-temperature annealing, Applied physics express 13.12 (2020): 121002.

S. Glass, F. Reis, M. Bauernfeind, J. Aulbach, M. R. Scholz, F. Adler, L. Dudy, G. Li, R. Claessen, and J. Schäfer, Atomic-Scale Mapping of Layer-by-Layer Hydrogen Etching and Passivation of SiC (0001) Substrates, The Journal of Physical Chemistry C 120.19 (2016): 10361-10367.

B. Tsui, Y. Huang, T. Wu, and C. Chien, Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes, Microelectronics Reliability 123 (2021): 114186.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 59-65

doi: 10.4028/p-UxdeG4

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-20

Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

The original version of this paper is available on https://www.scientific.net/MSF.1192.59.pdf

X. Tian 1,a*, A. B. Renz 1, b, K. Melnyk 1,c, M. A. Yildirm 1, d, M. Boccarossa 2,e, L. Maresca 2,f, A. Irace 2, g, J. A. Gott 3, h, N. S. Agbo 4,i, P. Taylor 4,j, M. Antoniou 1,k, P. A. Mawby 1,1, P. M. Gammon 1,m

1 School of Engineering, University of Warwick, Coventry, United Kingdom

2 University of Naples Federico II, Naples, Italy

3 Warwick Manufacturing Group, University of Warwick, Coventry, UK

4 Dynex Semiconductor Ltd., Lincoln, UK

a* Xinkai.Tian@warwick.ac.uk, b Arne.Renz@warwick.ac.uk, c Kyrylo.Melnyk.1@warwick.ac.uk, d Mustafa.Yildirim@warwick.ac.uk, e marco.boccarossa@unina.it, f luca.maresca@unina.it, g  andirace@unina.it, hJ.Gott@warwick.ac.uk, iNereus.Agbo@dynexsemi.com, jPaul.Taylor@dynexsemi.com, kMarina.Antoniou@warwick.ac.uk, IP.A.Mawby@warwick.ac.uk, mP.M.Gammon@warwick.ac.uk.

Abstract

We investigate the physical and electrical characteristics of the Al-doped or undoped HfO2/SiO2 gate stacks on 4H−SiC by testing MOSCAP chips fabricated in house. A clear reduction in accumulation capacitance ( Cox ) with increasing chuck temperature from room temperature up to 523 K is observed, with Al-doping playing a key role and aligning with temperature-dependent Landau ferroelectric theory. Chips annealed at 1100∘C in N2 ambient show the highest Cox decrease rates while maintaining functional MOS interfaces with acceptable flatband voltage, hysteresis, and Dit profiles. TCAD simulations on a double trench MOSFET model, based on the extracted data indicate improved electro-thermal performance, demonstrating that Al -doped HfO2/SiO2 gate stacks are a promising approach for enhancing 4H−SiC power devices.

Keywords: Al-doped HfO2, ferroelectricity, paraelectricity, high-k dielectrics, crystallisation, accumulation capacitance, temperature-dependence, Dit  profile, short-circuit ruggedness.

Introduction

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Silicon Carbide ( SiC ) has several material advantages over silicon ( Si ) in power electronics applications, such as its wider bandgap, higher breakdown voltage, and higher operating temperatures of SiC devices. Hence, they could be used for making more efficient power-dense 4H−SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) with lower on-resistances (Ron). Problems surrounding reliability under harsh conditions are still a challenge in 4H−SiC technology in this field. Short-circuit (SC) withstand time has been one of the challenges extensively researched, as the withstand times in 1.2kV4H−SiC MOSFETs have been low compared to their lower-rated 650 V counterparts [1]. Through Landau's theory of the temperature dependence of the dielectric constant and accumulation capacitance ( Cox ) in ferroelectric materials [2], the solution proposed was the integration of a ferroelectric hafnium oxide (HfO2)/ silicon dioxide (SiO2) gate-stack as the gate dielectric, which led to decreased peak current leakage and peak device temperature, resulting in improved electro-thermal behaviour of the device [3, 4]. This is based on the ferroelectric/paraelectric capacitance model from Landau's theory, where the dielectric permittivity increases up to when the operation temperature ( T ) reaches the Curie-Weiss temperature ( TCw ), but then decreases when T is above the TCw [2]. Research in ferroelectricity of HfO2 has shown that doping the HfO2 layer with different dopants, such as Si or aluminium (Al) could enhance the ferroelectric property of HfO2 [5, 6]. Therefore, the investigation will involve doped- HfO2/SiO2/4H−SiC MOS capacitor (MOSCAPs) chips.

In this study, the electrical performance and structural properties of the atomic layer deposited (ALD) Al-doped HfO2/SiO2/4H−SiC will be investigated. The focus will be on the Cox  change rate at increasing chuck temperatures against room temperature (RT) for the validity of Landau's theory. Flatband voltage ( VFB ), hysteresis and density interface traps ( Dit ) at RT are also investigated for studying the electrical reliability and integrity of the MOS interface.

Methodology

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For the fabrication of the MOSCAP chips in this investigation, seven 1 cm×1 cm chips have been cleaved from a 10μ m thick wafer consisting of an epitaxially grown light nitrogen-doped ( 1×1016cm−3 ) drift layer on top of a heavy nitrogen-doped ( >1×1020 cm−3 ) 4H-SiC substrate. The cleaved chips then underwent standard RCA cleaning with an: HF(10%)/RCA1/HF(10%)/RCA2/HF(10%), cleaning cycle. For the deposition of the HfO2/SiO2 gate-stack, 6 nm of SiO2 was deposited followed by 30 nm of doped/undoped HfO2 on top. Oxygen plasma is the oxidant of choice along with bis(diethylamido)silane (BDEAS) and tetrakis(dimethylamido)hafnium (TDMAHf) as Si and Hf precursors. This is all done by plasma-enhanced ALD (PE-ALD) at 200∘C with the Ultratech Fiji G2 PE-ALD system. For Al -doped HfO2 layers ALD cycles ratios of 1:19 and 1:29 of the Al2O3:HfO2 have been used to produce the Al−HfO2/SiO2/4H−SiC MOSCAP chips. Post deposition annealing (PDA) was done on the chips in nitrogen ( N2 ) ambient for one hour leading to a following list of MOSCAP chips produced:

Undoped HfO2/SiO2/4H−SiC MOSCAP chips annealed in a quartz furnace at 900∘C, 1000∘C, or 1100∘C.

Al-doped: HfO2/SiO2/4H−SiC MOSCAP chips annealed at 900∘C,1000∘C, or 1100∘C.

500 nm thick aluminium contacts were deposited on the top and bottom of the chips by means of metal sputtering to complete the fabrication of the devices. The top contacts were circular with a surface area of 1.26×10−3 cm2. The bottom surface of the chip was dry etched for the formation of the ohmic contact, before the bottom contact was deposited.

High-low frequency variant ±10 V capacitance-voltage (C-V) sweeps were conducted on at least 15 MOSCAP devices on each chip, with the average VFB, hysteresis and Dit  were extracted at room temperature (RT) (293 K). Dit  profiles of each MOSCAP device are extracted by the high-low frequency method with 100 Hz being the lowest frequency and 1 MHz being the highest frequency, using an Agilent E4980A LCR meter. High frequency C-V sweeps at varying probe station chuck temperature points (between 293 K - lowest and 523 K - highest) were performed on the MOSCAP chips; VFB, hysteresis and Cox(at+10 V) measurements were obtained at those various temperature points. A previously characterised ALD−SiO2/4H−SiC MOSCAP served as a reference for comparative electrical benchmarking. Grazing-incidence X-ray diffraction (GIXRD) measurements are conducted on the HfO2 surface for determining the crystal phase of the HfO2 film after a PDA; further structural analysis and the layer thicknesses have been verified by scanning transmission electron microscopy (STEM).

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Fig. 1. A TEM scan verifying the thickness of (a) deposited stacked dielectric as well the (b) element composition.

Fig. 1. A TEM scan verifying the thickness of (a) deposited stacked dielectric as well the (b) element composition.

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Fig. 2. SEM images of a unannealed (left) and N21100∘C annealed (right) MOS structure.

Fig. 2. SEM images of a unannealed (left) and N 21100 ∘ C annealed (right) MOS structure.

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Fig. 3. GIXRD measurements of the undoped/doped HfO2 films on SiO2/4H−SiC.

Fig. 3. GIXRD measurements of the undoped/doped H f O 2 films on S i O 2 / 4 H − S i C .

Physical Characterisation

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The STEM analysis of the N21100∘C annealed gate-stack MOS interface cross-section, shown in fig. 1, has confirmed the thicknesses of each insulator in the gate stack. Some crystallinity could be observed in the HfO2 layer from the STEM analysis. This detected crystallinity is like the crystallinity detected on HfO2 layers annealed on Si [9]. Comparative SEM conducted on an as-deposited layer of
HfO2 and then a N21100∘C annealed (both on separate chips of SiO2/4H−SiC ), have been done as shown in fig. 2. Fig. 2 depicts the grains of the annealed HfO2 to be greater than that of the asdeposited HfO2. Similar trends have also been seen on as-deposited or 700∘C annealed 500 nm thick HfO2 films on Si , where the method of deposition was by electron beam evaporation [10]. GIXRD results of fig. 3, show that for all the chips that underwent a high temperature PDA, a monoclinic crystal phase has been detected on the HfO2 film, which is synonymous with paraelectric properties of HfO2 [5]. Thus, links with the paraelectric phase of the ferroelectric theory could be established, especially the Cox decrease at higher chuck temperatures.

Electrical Results

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Fig. 4 shows normalised high-frequency C-V sweep results of a MOSCAP device taken from a 1:19 Al-doped HfO2/SiO2/4H-SiC chip annealed at 1100∘C in N2 at varying chuck temperatures. All recorded capacitance values have been referenced to the Cox  at RT. A Cox  (at +10 V ) decreased by 15%

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Fig. 4. Normalised Capacitance-Voltage sweep of a device on an Al2O3:HfO2 1:19 Aldoped MOSCAP chip.

Fig. 4. Normalised Capacitance-Voltage sweep of a device on an A l 2 O 3 : H f O 2 1:19 Aldoped MOSCAP chip.

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Fig. 5. Cox change vs chuck temperature results for all the PDA Al-doped HfO2/SiO2 gate-stack and SiO2 benchmark MOSCAP chips.

Fig. 5. C o x change vs chuck temperature results for all the PDA Al-doped H f O 2 / S i O 2 gate-stack and S i O 2 benchmark MOSCAP chips.

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Fig. 6. Cox change vs Chuck Temperature on retested MOSCAP devices.

Fig. 6. C o x change vs Chuck Temperature on retested MOSCAP devices.

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Fig. 7. (a) Hysteresis and (b) VFB results at varying chuck temperatures.

Fig. 7. (a) Hysteresis and (b) V F B results at varying chuck temperatures.

has been recorded as the chuck temperature rose from RT to 523 K . This result partially supports Landau's theory of temperature dependence on Cox in ferroelectric materials, especially in the paraelectric phase [2]. Fig. 5 shows the average Cox  change rate for all Al-doped gate stack MOSCAP chips in comparison to the ALD−SiO2 benchmark chip [7] at rising chuck temperatures (in 50 K increments). These results show that, regardless of the deposition cycles for the Al-doped HfO2, the PDA temperature of 1100∘C leads to the most favourable trends in Cox reduction rate with rising chuck temperatures; Hence, the doped MOSCAP chips annealed at 1100∘C have been taken further for further study. Cox change rate for the benchmark MOSCAP chip has been close to zero regardless of chuck temperature level. Moreover, high-frequency C-V sweeps, even with smaller chuck temperature increments of 25 K , have been conducted on a new set of MOSCAP devices on chips annealed at 1100∘C (fig. 6), further confirming the decreasing Cox trend (Fig. 5). This experimentally confirms a similar trend, also observed in silicon-on-insulator MOSFET devices [8].

Fig. 7a and 7b show the average hysteresis and VFB results at varying chuck temperature points for the MOSCAP chips. At all chuck temperature levels, the VFB is shown to be closer to the ideal VFB of ΦMS than that of the ALD-SiO2 2 benchmark. The hysteresis for the MOS interfaces is calculated using Eq. (1); therefore, a positive value indicates that negative charge is trapped in the MOS interface, but a negative value indicates that positive charge is trapped. Fig. 4b shows that positive
charges are trapped in the interface for the Al-doped gate stacks at all chuck temperature points, whereas negative charges are trapped for the ALD- SiO2 benchmark interface.

 Hysteresis =VFB( Acc. → Inv. )−VFB( Inv. → Acc. )(1)

Fig. 8 shows the RT Dit profile results of the Al-doped/undoped gate stacks and the ALD- SiO2 benchmark. The Dit  profile results are lower than 1012eV−1 cm−2 even when at 0.2 eV . Such results confirm that Al-doped gate-stacks can also make functional 4H−MOS interfaces.

TCAD Simulations Based on Experimental Results

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SC TCAD simulations have been conducted on a double trench MOSFET [11] employing similar methods for temperature-dependent dielectric constant ( ε ) curve fitting of the N2,1100∘C annealed 1:19 (Al2O3:HfO2)/SiO2 gate-stack and SC testing parameters, as of [3]. Fig. 9 shows the curve results of the curve fitting for the ε vs chuck temperature based on the electrical characterisation results. Given that no changes have been made on the design dimensions of the double trench MOSFET device, except for the gate insulator, it shows that there is improved electro-thermal performance when the temperature-dependent gate-stack has been adopted over the SiO2 gate insulator. Fig. 10 shows the responses of the MOSFET drain current ( ID ) and the maximum lattice temperature ( Tmax ) when under SC stress. Besides the lower peak Id and TMAX for the MOSFET that adopted the temperature-dependent ε gate-stack, the SC withstand time (SCWT) also increased by 2μ s.

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Fig. 8. Dit  profile results of the MOS interfaces of different gate insulator options.

Fig. 8. D it profile results of the MOS interfaces of different gate insulator options.

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Fig. 9. Dielectric constant ( ε ) vs Chuck temperature curve fit.

Fig. 9. Dielectric constant ( ε ) vs Chuck temperature curve fit.

A comparative Tmax  in the TCAD MOSFET lattice model switching from the SiO2 (fig. 11a) to the doped gate-stack (fig. 11b) have recorded a decrease in lattice temperature from 1286 K to 1229 K .

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Fig. 10. Simulated SC Id and Tmax for the DT MOSFET with constant SiO2 (red) and temperature dependent HfO2/SiO2 gate-stack gate insulator (blue).

Fig. 10. Simulated SC Id and Tmax for the DT MOSFET with constant S i O 2 (red) and temperature dependent H f O 2 / S i O 2 gate-stack gate insulator (blue).

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Fig. 11. Lattice temperature distribution in the simulated TCAD double trench MOSFET model with (a) constant SiO2 or (b) temperature dependent HfO2/SiO2 gate stack.

Fig. 11. Lattice temperature distribution in the simulated TCAD double trench MOSFET model with (a) constant S i O 2 or (b) temperature dependent H f O 2 / S i O 2 gate stack.

Conclusion

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Ferroelectric/Paraelectric properties of HfO2 on SiO2/4H−SiC have been investigated for the first time both physically and electrically on various materials/electrical characterisation methods. The physical characterisation through GIXRD and SEM reveals that the doped/undoped HfO2 layers that underwent a high-temperature PDA all exhibit a monoclinic (P21/c) crystal phase, which may justify the Cox  decrease against the rising chuck temperature. Chips that underwent a PDA of 1100∘C in N2 ambient led to the highest rates of Cox decreases between −13% and −18% from RT to 523 K . Furthermore, the VFB/ hysteresis vs chuck temperature, and RT Dit  profile results, all show that the gate-stack could still lead to functional and efficient MOS interfaces for 4H−SiC power MOS devices. Simulation results on a TCAD double trench MOSFET model, based on experimental data of this study, show improved electro-thermal performance when utilising the gate-stack as an alternative.

This study demonstrated that Al -doped HfO2/SiO2 gate-stacks could be a viable gate insulator option in SiC power devices. Further investigations into the stability of pure-ferroelectric property of HfO2 should be conducted in the future, with some changes to be made to the HfO2 doping ratios and the PDA process step thermal budget during the fabrication process of future gate-stack MOSCAP chips. The suitability of those gate stacks for MOSFET device integration will also encompass Dit (for channel mobility) and voltage breakdown (for gate leakage) parameters, as the polycrystalline nature of high temperature PDA HfO2 could sometimes lead to current leakage through the HfO2 layer [12].

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.59.pdf

G. Kampitsis, S. Papathanassiou, S. Manias, "Comparative evaluation of the short-circuit withstand capability of 1.2 kV silicon carbide (SiC) power transistors in real life applications", Microelectronics Reliability, Volume 55, Issue 12, Part B, (2015), pp. 2640-2646, ISSN 00262714, https://doi.org/10.1016/j.microrel.2015.09.012.

G.A. Salvatore et al., "Modeling the Temperature Dependence of Fe-FET Static Characteristics Based on Landau's Theory," in IEEE TED, vol. 58, no. 9, pp. 3162-3169, Sept. 2011.

M. Boccarossa et al., "The Ferro-Power MOSFET: Enhancing Short-Circuit Robustness in Power Switches With a Ferroelectric Gate Stack," in IEEE Access, vol. 13, pp. 59264-59274, 2025, doi: 10.1109/ACCESS.2025.3555931.

M. Boccarossa et al., "Substantial Improvement of the Short-circuit Capability of a 1.2 kV SiC MOSFET by a HfO2/SiO2 Ferroelectric Gate Stack," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 88-91, doi: 10.1109/ISPSD59661.2024.10579678.

Mueller, S., Mueller, J., Singh, A., Riedel, S., Sundqvist, J., Schroeder, U. and Mikolajick, T. (2012), Incipient Ferroelectricity in Al-Doped Thin Films. Adv. Funct. Mater., 22: 24122417. .

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X. Tian et al., "The Impact of Varying the High-Temperature Post-Deposition Anneal Time or Temperature Ramp Rates on ALD-SiO2/4H-SiC Interfaces," 2024 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe), Cardiff, United Kingdom, 2024, pp. 1-5, doi: 10.1109/WiPDAEurope62087.2024.10797374.

Jiseok Kim, Siddarth A. Krishnan, Sudarshan Narayanan, Michael P. Chudzik, Massimo V. Fischetti, "Thickness and temperature dependence of the leakage current in hafnium-based Si SOI MOSFETs", Microelectronics Reliability, vol. 52, Issue 12, 2012, pp. 2907-2913, ISSN 0026-2714, .

Zhang, XY., Hsu, CH., Lien, SY. et al. Temperature-Dependent HfO2/Si Interface Structural Evolution and its Mechanism. Nanoscale Res Lett 14, 83 (2019). .

Kant, S., Kumar, V.S.R.S.P., Kumar, M. et al. Surface wettability, morphology and optical characteristics of HfO2 films grown systematically by electron beam evaporation. Appl. Phys. A 129, 172 (2023). .

K. Melnyk et al., "Analysis and Performance Trade-Offs of State-of-the-Art 4H-SiC Trench MOSFET Technology," 2024 IEEE ECCE, Phoenix, AZ, USA, 2024, pp. 6764-6770.

M.A. Yildirim et al., "Investigation of Interface and Reliability of 3C- and 4H-SiC MOS Structures through Gate Dielectric Stacking and Post-Deposition Annealing," MSF, vol. 1158, pp. 67-74, Sept. 2025, doi: 10.4028/p-q2iyst. Available: .

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 67-74

doi: 10.4028/p-1Pi4j8

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-21

Accepted:
2026-01-31

Online:
2026-05-20

High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

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Johannes Ziegler 1,4a*, Dick Scholten 2,b, Holger Bartolf 1,c and Jörg Schulze 3,4,d

1 Robert Bosch GmbH, Mobility Electronics, 72762 Reutlingen, Germany

2 Robert Bosch GmbH, Corporate Research, 71272 Renningen, Germany

3 Fraunhofer IISB, 91508 Erlangen, Germany

4 Chair of Electron Devices (LEB), FAU Erlangen-Nürnberg, 91508 Erlangen, Germany

ajohannes.ziegler2@de.bosch.com, b  dick.scholten@de.bosch.com, c  holger.bartolf@de.bosch.com,  djoerg.schulze@iisb.fraunhofer.de

Abstract

In this paper, we study high-temperature H2, N2, and H2/N2 surface conditioning processes prior to the SiO2 deposition as a promising approach for SiO2/4H−SiC interface preparation in metal-oxide-semiconductor field-effect transistors (MOSFET). A thorough electrical analysis is presented, consisting of temperature-dependent transfer characteristics as well as reliability studies regarding bias temperature instabilities (BTI) and dielectric breakdown behavior. Especially N2-containing surface pretreatments were found to greatly suppress electron traps, whereas hole trapping is enhanced. Finally, X-ray photoelectron spectroscopy (XPS) was utilized to elucidate the elemental surface composition after the different annealing procedures. The obtained results are in good agreement with the electrical characterization and complement already published results regarding the formation of surface reconstructions on 4H−SiC through H2 and H2/N2 annealings.

Keywords: SiO2/4H−SiC, MOSFET, Surface Conditioning, Transfer Characteristics, Channel Mobility, Threshold Voltage, PBTI, NBTI, TZDB, TDDB, XPS, Surface Reconstruction.

Introduction

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Within the recent years, the SiC power MOSFET market has been massively grown. The wide bandgap of the 4H−SiC material comes along with a high breakdown field strength, offering the possibility of shrinking the drift zone thickness and ultimately its resistance contribution. Together with other superior physical properties like a high thermal conductivity, 4H−SiC is expected to continuously replace Si -based devices in high-voltage, energy-efficient power electronics application. A fundamental building block of every MOSFET device is the oxide-semiconductor interface. Despite the ongoing efforts to improve the SiO2/4H−SiC interfacial quality, the resulting channel mobility remains below expectation. Hence, metal-oxide-semiconductor (MOS) channel engineering is still a highly interesting matter of applied research.

With progressing scientific achievements in the field of SiO2/4H−SiC interface improvement, it is nowadays common knowledge, that thermal oxidation of 4H−SiC creates various defect states, located at different energetic levels. Exchanging a thermally grown by a deposited SiO2 gate oxide, however, turned out to yield a more abrupt material transition, if combined with an appropriate post-deposition annealing (PDA) process [1]. Hence, low pressure chemical vapor deposition (LPCVD) became the method of choice for high-quality gate oxide formation in 4H−SiC MOSFETs. Along with the transition to deposited gate oxides, the investigation of appropriate surface pretreatment processes prior to the dielectric deposition gained growing scientific interest. In this regard, especially H2-based, high-temperature surface conditioning in combination with a deposited SiO2 gate oxide was recently shown to offer a substantial increase in the channel mobility [2,3]. Even if the physical origin of the remarkable performance improvement is not yet fully understood, it is speculated, that mobilitylimiting defects are heavily reduced by H2 conditioning together with avoiding substrate oxidation.

The surface configuration of H2-annealed Si -face ( 0001 ) 4H−SiC is a matter of scientific interest since decades. Within the published studies, several hints to explain the recently shown mobility improvement can be found. Typically, upon H2 annealing, highly ordered silicate adlayers have been
observed, which provide an atomically sharp, epitaxial material transition to the underlying 4H−SiC [4]. Such silicate layers are expected to provide a well-suited seed layer for subsequent SiO2 deposition. However, it was found out, that the resulting surface reconstruction leaves behind an unsaturated bond per unit cell, which forms a mid-gap interface state. In this regard, researchers discovered an even more promising surface structure by adding a N2 annealing subsequent to the H2 treatment [5]. Such a combined H2/N2 surface treatment was proven to form an epitaxial silicon oxynitride ( SiON ) adlayer in a self-limiting manner, which potentially serves as an ideal insulator/ 4 H SiC transition due to the absence of dangling bonds. Even if first attempts to transfer those theoretical predictions to simple MOS capacitor devices have been published by Rozen et al. [6], to the best of our knowledge, there exists no successful demonstration on 4H−SiC MOSFET devices. In this work, we close this gap by investigating the effect of high-temperature H2, N2 and H2/N2 surface conditioning processes on the electrical performance of lateral 4H−SiC MOSFETs. Besides a thorough evaluation of the resulting transfer characteristics, reliability aspects of the processed gate oxides are discussed. Finally, the electrical results are correlated with XPS analysis.

Experimental

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To study the effect of different high-temperature surface conditioning processes, we fabricated lateral, long channel MOSFET devices on epitaxial n-type layers, grown on conventional 4∘-off axis ( 0001 ) 4H−SiC6′′ substrates. A schematic cross section of the MOSFET devices is shown in Fig. 1 together with the detailed process chain of the investigated gate formation procedures. To prepare the wafers for the variation in high-temperature surface conditioning, three subsequent ion implantation steps were conducted. In a first step, Al was implanted as a p-type dopant to create the channel region. Subsequently, a surrounding p-type border was implanted with a higher Al dose, which later serves as ohmic contact, connecting the channel region to ground potential during electrical characterization. Finally, highly doped n -type source and drain regions were formed by implanting ionized N atoms. Except the ion implantation steps, device fabrication took place in the corporate research cleanroom of the Robert Bosch GmbH. Following the implantation block, dopant activation was conducted by the state-of-the-art process of high-temperature annealing with the wafer surface being covered by a C capping.

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Fig. 1. Schematic cross section of the fabricated long channel MOSFET devices. Process chain and details regarding the gate stack formation including the surface conditioning procedures are given on the right side together with the respective sample nomenclature.

Fig. 1. Schematic cross section of the fabricated long channel MOSFET devices. Process chain and details regarding the gate stack formation including the surface conditioning procedures are given on the right side together with the respective sample nomenclature.

Prior to the surface conditioning processes, the wafers were cleaned to subsequently grow a sacrificial oxide layer, which is removed in a wet buffered oxide etch (BOE) solution. Right after, the wafers were processed according to the fabrication scheme, shown in Fig. 1. As a baseline for comparing the electrical results, a reference sample without additional surface treatment, denoted as " SiO2 ", was fabricated. All other samples underwent a dedicated high-temperature surface conditioning process, namely H2, N2 and a combination thereof. The respective processing conditions in terms of temperature profile over time and gas ambient are schematically provided in Fig. 1. All pretreatment processes were performed ex-situ to the subsequent LPCVD SiO2 formation. However,
the anticipated surface passivation layers upon H2 and H2/N2 annealing are published to be very stable against air exposure [4,5]. After the surface conditioning processes, all wafers were put together and processed nominally the same. SiO2 gate dielectrics were deposited by means of LPCVD and annealed in NO ambient at moderate temperatures to avoid reoxidation of interfacial layers. An insitu P doped LPCVD poly-Si layer was subsequently deposited as gate electrode material. Following a dry etching step to structure the poly- Si , a thick SiO2 insulation layer was formed to encapsulate the MOS stack, again via a LPCVD process. Afterwards, electrical contacts to the source, drain, gate and bulk regions had to be defined. Starting with the ohmic contacts to the 4H−SiC, the insulation layer was selectively etched in dedicated areas, followed by NiSi formation via sputtering and rapid thermal annealing (RTA) at elevated temperatures. Finally, to ensure a reliable needle contact to the MOSFET terminals during electrical characterization, thick Al contact pads were formed.

The fabricated MOSFET devices were electrically characterized in a Cascade Microtech probe station. A Keithley 2636 sourcemeter was connected to the probe station to record transfer characteristics and perform BTI, time-zero dielectric breakdown (TZDB) and constant voltage timedependent dielectric breakdown (TDDB) analysis. For analyzing the atomic surface configuration, XPS characterization was carried out in a PHI Quantera II equipment. Si2p, C1s, O1s and N1s core level spectra were acquired by using a monochromatic AlKαx-ray source with a take-off angle of 45∘. The resulting diameter of the analyzed area is roughly 200μ m.

Results and Discussion

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Fig. 2 a)-c) present the transfer characteristics of our devices. In Fig. 2 a), the linear drain current ID curve traces of one exemplary device per wafer are shown. The gate voltage VG was swept in 0.1 V steps from -5 V to +25 V and vice versa. The drain voltage VD was set to 0.3 V . To better compare the turn-on characteristics of the differently processed MOSFETs, a logarithmic illustration of ID in the voltage range 0 V<VG<4 V is given in Fig. 2 b ). Out of the results in Fig. 2 a ) and b), the peak field-effect mobility μFE, threshold voltage Vth  and sub-threshold hysteresis ΔVsub-th  are extracted and shown as box plots in Fig. 2 c) for a statistics of 16 devices per wafer.

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Fig. 2. a) Linear transfer characteristics of one exemplary MOSFET device per wafer with a channel length L=20μ m and width W=300μ m. The measurements were done at room temperature. An extrapolation in the linear curve regime is sketched by dashed lines to indicate the Vth  extraction. The ID−VG turn-on behavior is shown in b ) in logarithmic scale. The current level to extract ΔVsub-th  between up- and down-sweep direction is illustrated by the dashed line. The characteristic MOSFET parameters μFE,Vth  and ΔVsub-th  are derived for 16 devices per sample and shown as box plots in c). The dashed lines indicate the reference level of the SiO2 wafer.

Fig. 2. a) Linear transfer characteristics of one exemplary MOSFET device per wafer with a channel length L = 20 μ m and width W = 300 μ m . The measurements were done at room temperature. An extrapolation in the linear curve regime is sketched by dashed lines to indicate the V th extraction. The I D − V G turn-on behavior is shown in b ) in logarithmic scale. The current level to extract Δ V sub-th between up- and down-sweep direction is illustrated by the dashed line. The characteristic MOSFET parameters μ F E , V th and Δ V sub-th are derived for 16 devices per sample and shown as box plots in c). The dashed lines indicate the reference level of the S i O 2 wafer.

Comparing all wafers, a substantial μFE improvement of up to 2.2 times the reference value as well as a reduced ΔVsub-th  value is observed for both wafers, which have been processed with N2-containing surface conditioning. Furthermore, the N2−SiO2 and H2/N2−SiO2 devices turn on with a significantly steeper ID−VG slope, as shown in Fig. 2 b). Those aspects clearly reveal a superior SiO2/4H−SiC
interface quality after N2-containing surface pretreatment. Comparing the N2−SiO2 to the H2/N2−SiO2 sample, the N2-alone process seems to be even more effective to boost the MOSFET's performance. Interestingly, in contrast to the published results [2,3], the H2 surface conditioning process just marginally improves μFE, while energetically deeper interface states are even slightly increased, as ΔVsub-th  is enlarged and the onset of ID increase is delayed, as compared to the SiO2 reference wafer.

To get further insights regarding the SiO2/4H−SiC interface quality upon the investigated pretreatment processes, the temperature dependence of Vth  and μFE was evaluated by measuring the transfer curves between 25∘C and 175∘C in 25∘C steps. The corresponding results are elucidated in Fig. 3 a) and b), respectively.

[picture]

Fig. 3. a) Temperature-dependent Vth  for one exemplary device per sample. b) The corresponding μFE values show a different TC, which can be explained by considering the temperature dependence of μC,μSR and μOP. A qualitative drawing of the scattering contributions is given in c). While μSR and μOP are assumed to be comparable between the wafers, especially μC strongly depends on the interface preparation and is therefore significantly improved for the N2−SiO2 sample.

Fig. 3. a) Temperature-dependent V th for one exemplary device per sample. b) The corresponding μ F E values show a different TC, which can be explained by considering the temperature dependence of μ C , μ S R and μ O P . A qualitative drawing of the scattering contributions is given in c ) . While μ S R and μ O P are assumed to be comparable between the wafers, especially μ C strongly depends on the interface preparation and is therefore significantly improved for the N 2 − S i O 2 sample.

Regarding Vth , a distinct difference between the devices with N2-containing pretreatment and the SiO2 sample is observed in Fig. 3 a). Already at room temperature, the N2−SiO2 and H2/N2−SiO2 samples show a lower Vth  value, which can be explained by the steeper ID−VG turn-on behavior as a result of a reduced interface trap density around the conduction band edge. The Vth  gap, however, decreases with increasing temperature. The more stable Vth  temperature behavior of the N2−SiO2 and H2/N2−SiO2 samples is another indication for the improved interface characteristics. The superior interfacial quality additionally shows up in the μFE trend in Fig. 3 b). Whereas the samples with lower μFE exhibit a positive temperature coefficient (TC) of μFE, the behavior clearly reverses for the wafers, which were processed with N2-containing surface conditioning. A qualitative explanation for this observation is given in Fig. 3 c ), where the temperature dependence of the dominant scattering mechanisms, namely Coulomb scattering μC, surface roughness scattering μSR and optical phonon scattering μOP, is sketched [7]. The bulk mobility μC is omitted as it is known to be significantly larger than the other contributions. According to Matthiessen's rule, the lowest value dominates the overall μFE behavior. In the case of the SiO2 and H2−SiO2 sample, Coulomb scattering, which has a positive TC, limits μFE . As the interface quality gets remarkably improved by N2-containing pretreatment, the contribution of μC decreases, such that the overall μFE takes over the negative TC from μOP. Similar behavior is typically only reported on non-polar surfaces like (11-20) or (0-33-8), where the SiO2/4H SiC interface quality is inherently much better [3,8].

During long-term operation of a MOSFET, the stability of important parameters like Vth  is crucial. To compare the devices' Vth  stability with differently processed gate oxides, high-temperature gate bias (HTGB) analysis was performed at 175∘C and a gate bias of +20 V and -11 V , respectively. Prior to each Vth  readout, a preconditioning pulse according to Fig. 4 a) was applied to reduce the contribution of fully reversible trap charging/discharging on the shift in Vth . The resulting ΔVth  drift signal is shown in Fig. 4 b) and c) for positive BTI (PBTI) and negative BTI (NBTI) stress. For each
sample and stress bias, six devices were analyzed. The respective measurement data is given together with the averaged values per sample and accumulated stress time t.

[picture]

Fig. 4. a) Schematic explanation of the HTGB measurement procedure. Prior to every Vth  readout, a preconditioning pulse is applied to reduce the ΔVth  drift contribution of fully reversible trap charging/discharging. Note that even if the preconditioning pulse plateau phases are short (~0.1 s), they can add up a parasitic BTI stress. ΔVth  drift signals are shown in b) for PBTI and c) for NBTI stress at 175∘C. The measurement data points of six devices per wafer and stress bias are shown together with the averaged values.

Fig. 4. a) Schematic explanation of the HTGB measurement procedure. Prior to every V th readout, a preconditioning pulse is applied to reduce the Δ V th drift contribution of fully reversible trap charging/discharging. Note that even if the preconditioning pulse plateau phases are short ( ~ 0.1 s ) , they can add up a parasitic BTI stress. Δ V th drift signals are shown in b) for PBTI and c) for NBTI stress at 175 ∘ C . The measurement data points of six devices per wafer and stress bias are shown together with the averaged values.

In terms of PBTI in Fig. 4 b), a significantly lower ΔVth  drift is observed for the samples with N2− containing pretreatment. Hence, we speculate, that at least a part of the mobility-limiting interface traps, which are remarkably reduced for the N2−SiO2 and H2/N2−SiO2 samples, can also trap electrons (quasi-) permanently. In contrast, however, interface nitridation prior to the gate oxide deposition seems to contribute to enhanced hole trapping during NBTI stress, as shown in Fig. 4 c ). Such behavior is similarly observed for heavily nitrided SiO2/4H−SiC interfaces upon prolonged NO PDA at high temperatures [9]. The SiO2 as well as the H2−SiO2 sample, on the other hand, show negligible ΔVth  drift during NBTI stress. Even a small positive ΔVth  is observed until t≈103 s, which is assumed to be caused by the parasitic PBTI stress contribution originating from the preconditioning pulse.

Besides the stability of Vth , securing a reliable gate oxide operation over lifetime is indispensable. First evaluations in this regard were done by means of TZDB and constant voltage TDDB analysis. The corresponding results are shown in Fig. 5 a)-c). In Fig. 5 a) the gate leakage current normalized to the device area was recorded by increasing VG with a constant ramp of 0.5 V/s until dielectric breakdown occurred. Per Wafer, ten MOS capacitor devices, built on the n-type doped epi surface, are shown together with a fitted curve, assuming an ideal Fowler-Nordheim (FN) gate leakage behavior. For the calculation of the electric field E, the resulting oxide thicknesses after device processing were considered by performing capacitance-voltage ( C−V ) measurements. The oxide's dielectric constant was assumed to be εr=3.9 for all samples. Compared to the SiO2 reference sample, all pretreatment processes contribute to a narrower distribution of the breakdown field strength EBD. The highest EBD around 11MV/cm is reached for the H2−SiO2 sample, while especially the N2−SiO2 and H2/N2−SiO2 samples show a distinct shift of the gate leakage curves, attributed to a lower energetic FN tunneling barrier ΦB. The shown ΦB values were calculated by considering an effective electron mass of m*=0.42m0[10]. Similar lowering of ΦB was already reported for prolonged interface nitridation via NO PDA [10]. Additionally, at high gate oxide fields, a more pronounced deviation from the ideal FN curve shape is observed for both samples with N2-containing surface conditioning. While at moderate E-fields in the oxide, the leakage current is predominantly governed by FN tunneling, at higher fields, electrons have sufficient energy to generate holes by anode hole injection from the poly-Si electrode and/or impact ionization in the oxide near the anode. The generated holes drift towards the SiO2/4H−SiC interface, get trapped and hence, enhance the electric field, which further reduces the FN tunneling barrier for electrons [11]. In logical consequence, electron and hole injection amplify each other, leading to a deviation from the ideal FN current
behavior in the high E-field regime. The gap between the measured and fitted current is more pronounced for the N2−SiO2 and H2/N2−SiO2 samples. As the bulk SiO2 is assumed to have comparable quality for all samples, the current enhancement at higher fields is expected to originate from increased hole trapping near the SiO2/4H−SiC interface. This conclusion is supported by the observations from NBTI stress analysis, where N2-containing pretreatment was shown to create interfacial defect states, that capture holes during NBTI as well as high-field TZDB characterization.

To investigate a potential impact of the differences in ΦB and hole trap density on the TDDB characteristics, MOS capacitor devices from the SiO2 and N2−SiO2 samples were stressed at three different E-fields at a temperature of 140∘C. For each stress field and sample, eight devices were analyzed. Fig. 5 b) shows the respective leakage current evolution over time, while c) illustrates the time-to-breakdown tBD data together with the t63% values, which we extracted by assuming a Weibull distribution. Interestingly, at least in the investigated E-field range, the resulting tBD values are nearly the same for both samples, even if the initial gate leakage current is significantly higher for the N2 SiO2 devices due to lower ΦB and stronger leakage current enhancement. However, as can be seen by the humps in Fig. 5 b), the chosen E-field values are still in a range, where significant hole injection occurs, which can lead to an overestimation of the gate oxide lifetime. Hence, additional TDDB analysis at lower stress fields would need to be performed to reliably exclude a detrimental effect of N2 pretreatment on the gate oxide lifetime at typical operation conditions.

[picture]

Fig. 5. a) TZDB measurements of ten MOS capacitor devices per sample at room temperature. At moderate E-fields, the measurement curves are reproduced by assuming FN-governed electron tunneling through the SiO2. The calculated ΦB values, extracted from the fit, are given. b) Constant voltage TDDB measurements of eight MOS capacitor devices per sample and stress field at 140∘C. The stress time tBD, when dielectric breakdown occurs, is detected and plotted in c) over the E-field. The t63% values are calculated by assuming a Weibull distribution.

Fig. 5. a) TZDB measurements of ten MOS capacitor devices per sample at room temperature. At moderate E -fields, the measurement curves are reproduced by assuming FN-governed electron tunneling through the S i O 2 . The calculated Φ B values, extracted from the fit, are given. b) Constant voltage TDDB measurements of eight MOS capacitor devices per sample and stress field at 140 ∘ C . The stress time t B D , when dielectric breakdown occurs, is detected and plotted in c) over the E -field. The t 63 % values are calculated by assuming a Weibull distribution.

In the attempt to correlate the electrical results with compositional surface characterization, we performed XPS analysis. Additional samples were prepared by annealing epitaxial n-type wafers with the same H2, N2 and H2/N2 processes as utilized for the electrical MOSFET devices. A bare 4H−SiC epi wafer was added as reference. The XPS core level spectra were acquired ex-situ to the annealing processes. The corresponding results are presented in Fig. 6 a)-f). In Fig. 6 a), the elemental surface composition is evaluated by weighting the integrated signal intensity of the Si 2 p , C1s, O1s and N1s core level peaks. For all elemental components, three different measurement spots were analyzed. Even if this simple integration method contains some uncertainties regarding the exact compositional values, Fig. 6 a) clearly reveals the formation of O- and N-containing adlayers after all hightemperature surface treatments. While the O-content in the Ref. sample stems from a thin, native oxide layer as well as potential adsorbates from air exposure, the fraction of O and N atoms at the surface remarkably increases for all annealed surfaces by substituting C atoms in the uppermost atomic layers. Regarding the interfacial N coverage, it is often reported, that a higher N amount enhances the μFE of a MOSFET, while especially the device's reliability has to be taken with caution [9]. Interestingly, in terms of μFE and PBTI drift, the N2−SiO2 sample reveals the best electrical
performance, even if its interfacial N density seems to be reduced, compared to the H2/N2−SiO2 sample. Note that the elemental surface composition could be also affected by further MOS stack and device fabrication and might be slightly different in a fully processed MOSFET device. However, also the N binding configuration might have an impact on the defect passivation. As aforementioned in the introductory section, especially for H2[4] and H2/N2[5] treatment of 4 H -SiC surfaces, the formation of epitaxial surface reconstructions is reported. The published structures are shown in Fig. 6 e) and f) for H2 and H2/N2, respectively. Both structures consist of an uppermost SiO layer, which is either directly bonded to the 4H−SiC surface or connected via a bridging SiN interlayer. In case of the H2 treatment, one dangling bond per unit cell is left behind, while the H2/N2 treatment ideally passivates the surface.

[picture]

Fig. 6. a) Elemental surface composition for the investigated samples was calculated by weighting the integrated Si2p, C1s, O1s and N1s signal intensities. The corresponding core level spectra are shown in b) for Si2p, c) for O1s and d) for N1s for three measurement spots per sample. Energetic positions of the peaks are indicated by dashed lines. The published surface configurations after e) H2 [4] and f) H2/N2 [5] treatments of 4H−SiC are schematically drawn.

Fig. 6. a) Elemental surface composition for the investigated samples was calculated by weighting the integrated Si2p, C1s, O1s and N1s signal intensities. The corresponding core level spectra are shown in b) for Si2p, c) for O1s and d) for N1s for three measurement spots per sample. Energetic positions of the peaks are indicated by dashed lines. The published surface configurations after e) H 2 [4] and f) H 2 / N 2 [5] treatments of 4 H − S i C are schematically drawn.

To discuss the potential formation of such surface reconstructions in our experiments, the detailed XPS core level spectra of Si2p, O1s and N1s are given in Fig. 6 b)-d). All spectra were corrected to the theoretical binding energy of the Si 2 p peak in an ideal 4H−SiC crystal. As compared to the reference sample, Fig. 6 b) shows a pronounced shoulder of different shape for the samples with hightemperature surface conditioning. SiO surface components are typically observed towards higher binding energies, whereas SiN bonds are known to energetically lie between the SiO and SiC component [5]. Those considerations are in line with our measurements, where an increased intensity in the SiN region is observed especially for the N2 and H2/N2 surface treatment. Interestingly, the intensity increase of the Si2p spectra for the H2 and H2/N2 sample towards higher binding energy nearly perfectly overlap. This observation is in agreement to the energetical position of the O1s peak in Fig. 6 c), which is identical for both samples. Hence, it is speculated, that the O atoms are similarly bound in both configurations. The H2/N2 sample, however, contains an additional, N-related contribution in Fig. 6 b). Those observations promote the hypothesis, that similar surface adlayers, as shown in Fig. 6 e) and f), are created by the H2 and H2/N2 annealings in our experiment. In contrast, the N2 treatment seems to form a slightly different adlayer, as compared to the H2/N2 treatment. The O1s peak for the N2 sample is slightly shifted, pointing towards a different Si -O binding configuration. The N1s peak, however, seems to have a similar binding energy.

Summarizing the XPS analysis, our observations are in good agreement with published considerations and our electrical data. The N2-containg pretreatments were shown to efficiently suppress mobility-limiting traps by passivating the surface. H2 treatment, in contrast, leaves behind one dangling bond per unit cell, which could be a potential explanation for the less pronounced μFE improvement after this annealing. However, the reliability of SiO2 gate dielectrics upon N2-containing surface conditioning has to be taken with caution, as the resulting surface configurations, even if they slightly differ from each other, were shown to be prone to hole trapping.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

In this work, we investigated the impact of high-temperature H2, N2, and H2/N2 surface conditioning processes on the electrical performance of lateral SiO2/4H−SiC MOSFETs and correlated the results with compositional XPS surface analysis. Especially N2-containing surface treatments were shown to greatly suppress electron trapping states around the conduction band edge, leading to a remarkably improved conductivity of the gate-controlled 4H−SiC/SiO2 interface. However, similarly to heavily NO-nitrided SiO2/4H−SiC interfaces, hole traps arise, which could have a detrimental effect on the device's reliability during long-term operation. In contrast to recently published results regarding H2 treatments, its beneficial effect on μFE could not be reproduced to the same extent.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

This work has received funding from the IPCEI ME/CT project. The IPCEI ME/CT project itself is supported by the Federal Ministry for Economic Affairs and Energy on the basis of a decision by the German Parliament, by the Ministry for Economic Affairs, Labor and Tourism of BadenWürttemberg based on a decision of the State Parliament of Baden-Württemberg, the Free State of Saxony on the basis of the budget adopted by the Saxon State Parliament, the Bavarian State Ministry for Economic Affairs, Regional Development and Energy and financed by the European Union NextGenerationEU.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.67.pdf

P. Fiorenza et al., "Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4 H -SiC MOSFETs subjected to different nitridations", Applied Surface Science, vol. 557, pp. 149752 (2021).

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K. Mikami et al., "Insight Into Mobility Improvement by the Oxidation-Minimizing Process in SiC MOSFETs," IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 931-934 (2024).

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H. Tochihara et al., "The epitaxial crystalline silicon-oxynitride layer on : Formation of an ideal SiC-insulator interface", Progress in Surface Science, vol. 86, no. 11, pp. 295-327 (2011).

J. Rozen et al., "Enhancing interface quality by gate dielectric deposition on a nitrogenconditioned 4H-SiC surface", Journal of Materials Research, vol. 28, no. 1, pp. 28-32 (2013).

K. Kutsuki et al., "Experimental investigation and modeling of inversion carrier effective mobility in 4H-SiC trench MOSFETs", Solid-State Electronics, vol. 157, pp. 12-19 (2019).

T. Hiyoshi et al., "Improvement of interface state and channel mobility using 4H-SiC (0-33-8) face", Materials Science Forum, vol. 740, pp. 506-509 (2013).

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H. Watanabe et al., "Comprehensive research on nitrided interfaces by hightemperature nitric oxide annealing formed on basal and non-basal planes", Japanese Journal of Applied Physics, vol. 64, no. 1, pp. 010801 (2009).

T. Liu et al., "Time-Dependent Dielectric Breakdown of Commercial Power MOSFETs," IEEE Journal of the Electron Devices Society, vol. 9, pp. 633-639 (2021).

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 75-80

doi: 10.4028/p-0waUsG

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-20

Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

Marilena Vivona 1,a*, Salvatore Ethan Panasci 1, b, Marco Zignale 1,c, Valerio Votadoro 1, d, Salvatore Di Franco 1,e, Emanuela Schilirò 1,f, Giuseppe Greco 1, g, Raffaella Lo Nigro 1, h, Patrick Fiorenza 1,i, Filippo Giannazzo 1,j, Fabrizio Roccaforte 1,k

1 CNR-IMM, Strada VIII n.5, Zona Industriale, I-95121, Catania, Italy

Abstract

In this work, the electrical properties of Mo2C/4H−SiC Schottky contacts were studied at different annealing temperatures. In particular, the Schottky barrier height was derived by currentvoltage measurements on as-deposited and 400∘C and 700∘C-annealed contacts. The Schottky barrier height was comparable for the as-deposited and 400∘C-annealed Mo2C/4H-SiC contact (0.94 and 0.96 eV , respectively), while it increased ( 1.07 eV ) for the 700∘C-annealed Mo2C/4H−SiC one. For the sample annealed at 700∘C, the electrical characterization of the diodes was combined with the study of the surface and interface electrical properties, by Kelvin-probe force microscopy (KPFM) and frequency dependent capacitance-voltage measurements ( C−f−V ) and discussed assuming a Mo/4H−SiC Schottky contact ( ΦB=1.39eV ) as a reference. The KPFM measurements revealed a similar value of the surface potential, thus suggesting that the work function of the metal is the same in both cases. On the other hand, a higher density of interface state was obtained by C−f−V for the Mo2C/4H-SiC system. This latter can explain the reduction of the Schottky barrier height observed for this system.

a* marilena.vivona@imm.cnr.it, b salvatoreethan.panasci@imm.cnr.it, c marco.zignale@imm.cnr.it, d valerio.votadoro@cnr.it, e salvatore.difranco@imm.cnr.it, f emanuela.schilirò@imm.cnr.it,
jilippo.giannazzo@imm.cnr.it, kfabrizio.roccaforte
*corresponding author

Keywords: Mo2C/4H-SiC interface, Schottky contact, electrical characterization.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

The Schottky-barrier diode (SBD) on 4H-SiC is a well-established technology, currently employed in several power electronics applications within the medium-to-high voltage range [1]. Although the advantages (namely fast switching, low forward voltage drop, high temperature operations) of using 4H-SiC-SBD are undoubted, further technological optimizations are still necessary to fully exploit the potential of 4H−SiC [2]. To this end, various approaches have been explored to improve the properties of the metal /4H−SiC interface, which underpins the performance of the SBDs, with particular attention to the metal choice and its interaction with 4H−SiC during thermal annealing for the Schottky contact formation [3]. In recent years, molybdenum (Mo) has attracted interest due to its good thermal stability and ability to form contacts with low Schottky barrier height, which is beneficial for minimizing the conduction power losses [4]. However, a wide variability in the Schottky barrier height has been observed in Mo/4H−SiC Schottky contacts, depending on several factors, such as surface passivation treatments [5], temperature of the metal deposition [6] and metal stack composition [7], with the ΦB varying between 1.0 and 1.5 eV . Recently, we investigated Mo/4H−SiC Schottky contact subjected to annealing treatments up to 950∘C, observing a reduction of the ΦB from 1.42 eV to 1.29 eV upon annealing at 950∘C, without any evidence of interface reaction between metal and semiconductor [8]. In that case, the reduction of ΦB was associated with
the enlargement and preferential orientation of the metal grains, as demonstrated by X-Ray Diffraction (XRD) and Transmission Electron Microscopy (TEM) [8]. Nevertheless, based on the ternary phase diagram of the Mo-Si-C system, solid-state reactions can occur between Mo and both silicon ( Si ) and carbon ( C ), leading to the formation of carbides and silicides. This tendency opens the possibility to further explore and tune the Schottky barrier properties to 4H−SiC, potentially broadening the range of achievable ΦB values. As an example, Mo-based contacts containing C have been recently investigated, either deposited in laminated layers or obtained from Mo-C alloyed targets [7,9], demonstrating stable electrical characteristics even at high annealing temperature. However, the origin of this electrical behavior is not fully clear yet.
In this paper, the behavior of the Schottky barrier height ΦB in Mo-carbide /4H−SiC contacts was investigated, as a function of the annealing temperature. The electrical characterization of the diodes was combined with the study of the surface and interface electrical properties, by Kelvin-probe force microscopy (KPFM) and frequency dependent capacitance-voltage (C-V-f) measurements, to get information on the surface potential and the energy of interface state density (Nss). While similar values of surface potential were found for the Mo2C and Mo/4H−SiC contacts, the higher level of Nss in the Mo2C/4H−SiC can explain the reduction of the Schottky barrier in this contact compared to a Mo/4H−SiC one.

Experimental Details

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

The starting material for this study consisted in a 4H−SiC epitaxial layer with a n-type doping concentration of 1.5×1016 cm−3 grown onto a n+-doped substrate. Schottky diodes were fabricated starting from the deposition of a large-area back-side Ohmic contact by sputtering 100 nm-thick Ni layer, followed by a rapid thermal annealing (RTA) treatment in a furnace at 950∘C in N2 for 60 s [10]. Then, for the front-side Schottky contact, 100 nm -thick film was sputtered from a Mo2C target. The contact pads were defined by optical photolithography and lift-off processing steps. Rapid thermal annealing (RTA) treatments were carried out in a furnace for 10 min in N2 atmosphere at temperatures of 400∘C and 700∘C. For comparison, 80 nm -thick Mo/4H-SiC contacts were fabricated in the same manner. The electrical characteristics of a set of contacts were investigated by means of current-voltage (I-V) and capacitance-frequency-voltage (C-f-V) measurements in a KarlSuss MicroTec probe station equipped with a parameter analyzer. Kelvin Probe Force Microscopy (KPFM) measurements were carried out in PeakForce Tapping Mode Amplitude Modulation (AM)KPFM with a Dimension Icon system by Bruker. Silicon tips with a triangular geometry (nominal radius of 5 nm ) were employed to evaluate the variation of the surface potential of the contact.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

Firstly, we investigated the electrical characteristics under forward bias for a set of as-deposited, 400∘C and 700∘C annealed Mo2C/4H−SiC contacts. The related current density-voltage (J-V) curves are reported in Figs.1a, 1b and 1c, respectively.

[picture]

Fig. 1. Forward J−V curves of the a) as-deposited, b) 400∘C and c) 700∘C-annealed Mo2C/4H−SiC Schottky contacts.

Fig. 1. Forward J − V curves of the a) as-deposited, b) 400 ∘ C and c) 700 ∘ C -annealed M o 2 C / 4 H − S i C Schottky contacts.

The J-V characteristics exhibited good reproducibility, with the 700∘C-annealed sample showing a more extended linear region. The Schottky barrier height values, extrapolated from a fit of the linear part of the J-V curves, according to the thermionic emission (TE) model [11], are reported in Fig.2. As one can see, the as-deposited and 400∘C-annealed Mo2C/4H-SiC contact showed similar barrier height, with ΦB=0.94±0.02eV and ΦB=0.96±0.04eV, respectively. After thermal treatment at 700∘C, the barrier increased up to 1.07±0.04eV.

To understand the origin of the barrier reduction, we investigated the surface potential, which is linked to the work-function of the contact material. The surface potential mapping was performed by KPFM, carried out on both the Mo (reference) and Mo2C contacts. Specifically, 4H−SiC was employed as a reference to evaluate the variation on the surface potential of the contact material with respect to the semiconductor. Figs. 3a and 3b show the histograms of surface potential values extracted from the KPFM maps.

[picture]

Fig. 2. Schottky barrier height ( ΦB ) for the as-deposited and annealed Mo2C/4H−SiC contacts.

Fig. 2. Schottky barrier height ( Φ B ) for the as-deposited and annealed M o 2 C / 4 H − S i C contacts.

[picture]

Fig. 3. Histograms of the KPFM surface potential values associated to the maps for a) Mo/4H−SiC and b) Mo2C/4H−SiC contacts. 4H−SiC was taken as reference.

Fig. 3. Histograms of the KPFM surface potential values associated to the maps for a) M o / 4 H − S i C and b) M o 2 C / 4 H − S i C contacts. 4 H − S i C was taken as reference.

These surface potential distributions were fitted by Gaussian functions to derive the peak corresponding to the average surface potential values. Noteworthy, a surface potential variation of 0.16 eV was observed for Mo and 4H−SiC while is of 0.19 eV for Mo2C and 4H−SiC one. This corresponds to very similar surface potential values for Mo and Mo2C, differing by only ~0.03eV. Such a small variation alone cannot account for the difference observed in the Schottky barrier height between the two contacts. Hence, we extended the investigation to the interface electrical properties by a C-f-V study [12]. This technique enables the evaluation of the density of interface states (Nss) in Schottky diodes from capacitance measurements as function of the frequency (f) and forward bias (V). In fact, at low frequencies, the measured capacitance contains contributions from both the spacecharge region (Csc) and the interface states (Css), whereas at high frequencies only the space-charge capacitance contributes [13]. This can be expressed according to the following eqs. 1 and 2, where the total capacitance is given by a parallel of Csc and Css at low frequencies whereas the total capacitance can be approximated to only Csc at high frequencies [14]:

Clf=CSC+CSS( at low frequency )Chf≈CsC( at high frequency )

(1)(2)

From the difference between the two cases, CSS is derived. This term is proportional to the NSS, as given in eq. 3 [15]:

CSS=qANSSarctan(ωτ)ωτ(3)

with ω=2πf (f varying between 1 kHz and 1 MHz ), q the elementary charge, A the device area, and τ a time parameter depending on the thermal velocity of carriers, the cross-section of interface states and the doping concentration.

The NSS derived according to eq.3, results of 2.2×1010eV−1 cm−2 for Mo/4H−SiC contact and of 9.5×1013eV−1 cm−2 for Mo2C/4H−SiC. This high difference in the density of interface state can be at the base of the reduction of the Schottky barrier occurred in Mo2C contacts.

[picture]

Fig. 4. C−f−V characteristics for 700∘C annealed Mo and Mo2C/4H−SiC contacts.

Fig. 4. C − f − V characteristics for 700 ∘ C annealed Mo and M o 2 C / 4 H − S i C contacts.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

The electrical characterization of Mo2C/4H−SiC Schottky contacts demonstrated a Schottky barrier height around 0.95 eV for the as-deposited and 400∘C-annealed contact and of 1.07 eV for the 700∘C-annealed contact, the latter exhibiting a more extended linear region. The Mo2C/4H−SiC contact properties were compared with those of a reference Mo/4H−SiC contact, fabricated under same processing conditions, with surface and interface electrical properties investigated by Kelvinprobe force microscopy and capacitance-frequency-voltage study, respectively. The study indicated comparable surface potential values (derived by Kelvin-probe force microscopy) for the two systems, whereas a higher density of interface state was extracted for the Mo2C/4H−SiC contact. This latter finding accounts for the reduction in Schottky barrier height observed in the Mo2C/4H−Si contact.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

This work was carried out in the framework of the MicroTech_for_Green project, funded by Ministero delle Imprese e del Made in Italy (MIMIT) under IPCEI Microelettronica 2, using the facilities of the Italian Infrastructure Beyond-Nano. The authors S.E.P. and V.V, would like to thank the European Union (NextGeneration EU), through the MUR-PNRR project infrastructure for Energy Transition and Circular Economy @ EuroNanoLab iENTRANCE@ENL (IR00000027) for financial support.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.75.pdf

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R. Rupp, R. Elpelt, R. Gerlach, R. Schomer, M. Draghici A new SiC diode with significantly reduced threshold voltage. In Proceedings of the 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 28 May-1 June 2017; pp. 355-358.

A. B. Renz, V. A. Shah, O. J. Vavasour, Y. Bonyadi, F. Li, T. Dai, G.W.C. Baker, S. Hindmarsh, Y. Han, M. Walker, Y. Sharma, Y. Liu, B. Raghothamachar, M. Dudley, P. A. Mawby, P. M. Gammon, The improvement of -SiC Schottky diodes via a surface passivation treatment. J. Appl. Phys. 127 (2020) 025704.

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M. Vivona, I. Streicher, L. Kirste, A.M. Mio, G. Nicotra, P. Fiorenza, F. Giannazzo, F. Roccaforte, Thermal annealing effects on the electrical and structural properties of Mo Schottky contacts to n-type 4H-SiC, Mater. Sci. Semicond. Process. 198 (2025) 109786.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 81-87

doi: 10.4028/p-LlTen7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-15

Revised:
2025-12-22

Accepted:
2026-02-26

Online:
2026-05-20

NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

Paolo Badalà 1,a*, Corrado Bongiorno 2, b, Salvatore Sanzaro 1,c, Anna Bassi 1, d, Simone Rascunà 1,e, Gabriele Bellocchi 1,f, Massimo Boscaglia 1, g, Antonino La Magna 2, h and Alessandra Alberti 2,i

1 STMicroelectronics, Zona Industriale Stradale Primosole, 50-95121 Catania, Italy

2 CNR-IMM, Zona Industriale Strada VIII, 5-95121 Catania, Italy

a * paolo.badala@st.com, b  corrado.bongiorno@imm.cnr.it, c  salvatore.sanzaro@st.com, d  anna.bassi@st.com, e  simone.rascuna@st.com, f  gabriele.bellocchi@st.com, ¹  massimo.boscaglia@st.com, h  antonino.lamagna@imm.cnr.it, ialessandra.alberti@imm.cnr.it 

Keywords: laser annealing, ohmic contact, silicide, 4H-SiC.

Abstract

Laser annealing is considered an enabling process for a new generation of SiC power devices, since it allows the formation of ohmic contacts on very thin wafers, significantly reducing their total ON resistance. Ni silicide and Ti silicide ohmic contacts have been widely investigated and reported in literature, exploring in detail the role of laser features, metal thickness and thinning process. Nevertheless, adding a small amount of Si to the contact layer could represent an opportunity to increase process options. In this work, a NiSi alloy has been used as a contact metal to study the role of the addition of Si to Ni in the reaction process under UV laser irradiation. Morphological and structural properties of the reacted layers have been investigated by means of Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD) analyses. The electrical characterization of reacted contacts has been performed by measuring their Sheet Resistance ( Rs ) by Four Point Probe (FPP) method and, at device level, by measuring the forward voltage drop ( Vf ) of Schottky Barrier Diodes (SBDs) fabricated on 150 mm -diameter 4H−SiC wafers. Furthermore, a comparison has been made between Ni and NiSi alloy under the same irradiation conditions. It has been found that adding Si to Ni in the contact metal layer moves the silicide reaction forward, driving the strong relationship observed between structural, morphological and electrical properties of the reacted contacts.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

Silicon carbide has attracted increasing attention in recent years for power electronics and detectors applications, thanks to its excellent physical properties, which allow for obtaining higher breakdown voltage, higher switching frequency, lower resistance, higher heat dissipation, and smaller devices [1-6]. Laser annealing process has been widely adopted in silicon carbide device fabrication, for dopant activation [7,8] and ohmic contact formation [9, 10]. In particular, among the alternative processes to Rapid Thermal Annealing (RTA) for silicide formation [11-13], laser annealing, thanks to its limited heat diffusion, is the most suitable one for the formation of ohmic contact on thin wafers, therefore allowing to significantly reduce the total ON resistance of SiC power devices [14]. Ohmic contacts on SiC based on Ti silicide [15, 16] and Ni silicide [17-28] have been already deeply investigated, and the reaction process has been also studied in detail from a theoretical point of view [29-31]. Nevertheless, the behavior of a NiSi alloy as a contact material under laser irradiation has not completely described and understood so far. In this work, the role played by the addition of a small amount of Si to Ni of the contact layer, in the ohmic contact formation by means of excimer UV laser annealing, has been investigated. A comparison between Ni and NiSi alloy under the same irradiation conditions is reported.

Experimental Setup

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Schottky Barrier Diode (SBD) devices have been fabricated on 150 mm -diameter 4H-SiC wafers, thinned at 180μ m. A 100 nm NiSi alloy layer has been deposited by sputtering in Ar ambient, at a base pressure of 1×10−3mbar, on the ground face of the wafers. Wafers have then been irradiated on the backside by using an excimer UV laser, with pulse duration of 160 ns and wavelength of 308 nm . Structural properties of the reacted layers have been characterized by means of X-Ray Diffraction (XRD) analyses, using a Bruker AXS D8 DISCOVER diffractometer, working with a Cu−Kα source and a thin film attachment. Morphology of reacted layers has been investigated by means of Transmission Electron Microscopy (TEM) analyses, using a JEOL-JEM microscope working at 200 keV . The electrical characterization of reacted contacts has been performed by measuring their Sheet Resistance ( Rs ) by Four Point Probe (FPP) method and, at device level, by measuring the forward voltage drop ( Vf ) at nominal current of Schottky Barrier Diodes (SBDs), by using a semiconductor device parameter analyzer (Agilent B1500A) and a high-power curve tracer (Sony Tektronix 371A).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

It has been reported [17] that the typical Rs curve, as a function of laser fluence, shows an increase of Rs values for low laser fluences, due to the initial intermixing between metal layer and Si , and then a rapid drop of Rs to a final plateau, above a threshold fluence. In particular, the value of threshold fluence depends on contact material and its thickness, number of laser pulses, and SiC roughness.

[picture]

Fig. 1. Comparison between threshold fluence for the Rs drop of Ni and NiSi alloy, as a function of number of laser pulses. Fixed the laser conditions, the threshold fluence of NiSi alloy is lower than that of Ni .

Fig. 1. Comparison between threshold fluence for the R s drop of Ni and NiSi alloy, as a function of number of laser pulses. Fixed the laser conditions, the threshold fluence of NiSi alloy is lower than that of Ni .

As shown in Fig. 1, the threshold fluence at which the Rs drop is observed decreases with the increasing number of laser pulses, both for Ni and NiSi alloy, but the threshold fluence of NiSi alloy is lower than that of Ni , at the same number of laser pulses. This could mean that, fixed the laser annealing conditions, the addition of Si to Ni moves the reaction forward.

[picture]

Fig. 2. Forward voltage drop ( Vf ) at nominal current ( I0 ) of Schottky Barrier diodes annealed at 3.8 J/cm2 with two pulses. As a reference, the Vf of diodes treated with RTA is reported.

Fig. 2. Forward voltage drop ( V f ) at nominal current ( I 0 ) of Schottky Barrier diodes annealed at 3.8 J / c m 2 with two pulses. As a reference, the V f of diodes treated with RTA is reported.

This hypothesis is confirmed by the measurement of Vf of SB diodes. As reported in Fig. 2, in fact, NiSi sample annealed at 3.8 J/cm2 with two pulses shows a Vf significantly lower than the Ni sample annealed at the same conditions, and even lower than that of a Ni sample treated by Rapid Thermal Annealing (RTA), reported as a reference.

[picture]

Fig. 3. XRD pattern, acquired in grazing incidence configuration, of NiSi alloy sample after laser annealing at 3.8 J/cm2, two pulses, and corresponding deconvoluted component peaks.

Fig. 3. XRD pattern, acquired in grazing incidence configuration, of NiSi alloy sample after laser annealing at 3.8 J / c m 2 , two pulses, and corresponding deconvoluted component peaks.

Structural properties of Ni and NiSi alloy samples, annealed at 3.8 J/cm2 with two pulses, have been characterized by XRD, performed in grazing incidence configuration. Fig. 3 shows the XRD pattern of the annealed NiSi sample and the deconvoluted contributions of the main peaks. The extracted quantitative fractions reveal the predominant presence of Ni3Si2 and NiSi phases, with lower contribution of Ni2Si and NiSi2.

Fig. 4. Comparison between XRD patterns, acquired in grazing incidence configuration, of Ni and NiSi alloy samples annealed at 3.8 J/cm2, two pulses.

The same approach has been adopted to characterize the annealed Ni sample, revealing the presence of Ni3Si,Ni31Si12,Ni2Si and Ni3Si2 phases. The comparison between NiSi alloy and Ni annealed samples, reported in Fig. 4, shows the presence of Si-rich phases in NiSi alloy sample, confirming that adding Si to Ni moves the reaction ahead, fixed the laser annealing process parameters. In fact, the Ni−Si reaction starts at the interface between Ni and SiC and moves from Ni− rich phases towards Si-rich ones. As the silicide reaction moves forward, the electrical behaviour of ohmic contact improves, as shown by Sheet Resistance and Forward Voltage measurements reported in Fig. 1 and Fig. 2.

[picture]

Fig. 5. Cross sectional TEM analysis of NiSi alloy sample annealed at 3.8 J/cm2, two pulses. The reacted material shows an interfacial layer, a Ni -Si network region, and a graphite layer on top (a). HR-TEM micrographs show the presence of NiSi2 regions and C -clusters in the Ni -Si network area (b), and the presence of stacking faults in the interfacial layer with 4H−SiC (c).

Fig. 5. Cross sectional TEM analysis of NiSi alloy sample annealed at 3.8 J / c m 2 , two pulses. The reacted material shows an interfacial layer, a Ni -Si network region, and a graphite layer on top (a). HR-TEM micrographs show the presence of N i S i 2 regions and C -clusters in the Ni -Si network area (b), and the presence of stacking faults in the interfacial layer with 4 H − S i C (c).

The morphology of NiSi alloy sample annealed at 3.8 J/cm2 with two pulses has been investigated by cross-sectional TEM analyses (Fig. 5). As visible in Fig. 5a, the reacted material shows an interfacial layer, a Ni-Si network region, and a graphite layer on top. NiSi2 regions and C -clusters are included in the Ni-Si network area, as shown by cross-sectional High-Resolution TEM micrograph reported in Fig. 5b. The presence of stacking faults in the interfacial layer with 4H−SiC has been revealed by HR-TEM (Fig. 5c).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

The silicide reaction between a NiSi alloy and 4H−SiC under excimer UV laser annealing has been investigated, with the aim of finding an alternative to Ni and Ti for the ohmic contact formation on thin SiC wafers, enlarging the range of process options. It has been found that, fixed the laser annealing conditions, the addition of Si to Ni in the contact metal layer moves the silicide reaction forward. Moreover, a strong relationship has been observed between the electrical behavior of the annealed contacts and the structural and morphological properties of the reacted layers. Exploring the role of Si content in the NiSi alloy, by changing the composition of starting material, could shed additional light on the reaction process. NiSi alloy could represent a valuable opportunity for the formation of ohmic contacts on SiC by laser annealing.

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The original version of this paper is available on https://www.scientific.net/MSF.1192.81.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 89-96

doi: 10.4028/p-U2bkIl

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-23

Revised:
2026-01-07

Accepted:
2026-01-31

Online:
2026-05-20

Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

The original version of this paper is available on https://www.scientific.net/MSF.1192.89.pdf

Maximilian Ley 1,a*, Julian Kauth 1,b, Mathias Rommel 1,c, Björn Fischer 2,d, Alexander May 1,e, and Jörg Schulze 1,3,f

1 Fraunhofer Institute for Integrated Systems and Device Technology (IISB), Schottkystraße 10, 91058 Erlangen, Germany

2 Infineon Technologies AG, Am Campeon 1-15, 85579 Neubiberg, Germany

3 Chair of Electron Devices, Friedrich-Alexander-Universität Erlangen-Nürnberg, Cauerstraße 6, 91058 Erlangen, Germany

a  maximilian.ley@iisb.fraunhofer.de, b  julian.kauth@iisb.fraunhofer.de, c  mathias.rommel@iisb.fraunhofer.de, d  bjoern.fischer@infineon.com, e  alexander.may@iisb.fraunhofer.de, f  joerg.schulze@fau.de

Keywords: TLM Test Structure, Contact Length, TCAD, 4H-SiC, Contact end Resistance, Sheet Resistance, Specific Contact Resistivity, Transfer Length, Simulation Analysis, Ohmic Contact

Abstract

Accurate characterization of low-resistance ohmic contacts on 4H−SiC is crucial for device development, but is complicated by the limitations of the standard Transfer Length Method (TLM). TLM test structures are widely used for extracting the specific contact resistivity ( ρC ) between metal and semiconductor layers, as well as the sheet resistance of doped layers. The contact formation process itself, particularly the annealing step, modifies the SiC layer under the contact. This results in a sheet resistance below the contact ( RSK ) that deviates from the sheet resistance of interest between the contacts ( RSH ), which invalidates a key assumption of the standard TLM evaluation of a constant RSH throughout the whole TLM test structure. This study uses 2D TCAD simulation of TLM test structures to investigate the influence of the contact length L, while using an advanced evaluation method for extracting ρC with the help of a third contact. Consequently, it is necessary to measure the contact end resistance RCE, which is derived from the potential at the end of the TLM contact. The findings provide a deeper understanding of the TLM technique's robustness and offer valuable guidelines for optimizing TLM test structures to ensure accurate characterization of ohmic contacts on 4H−SiC.

Introduction

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In recent years, 4 H -Silicon Carbide (4H−SiC) has emerged as a leading semiconductor material for high-power, high-frequency, and high-temperature electronic devices, owing to its superior material properties, including a wide bandgap, high critical electric field, and excellent thermal conductivity [1]. The overall performance and energy efficiency of these devices are critically dependent on the quality of the metal-semiconductor interface, specifically the formation of low-resistance ohmic contacts. However, achieving such contacts on 4H−SiC is challenging compared to silicon, primarily due to three factors: Its wide bandgap creates a large Schottky barrier, its chemical inertness complicates surface preparation, and there is a lack of metals with suitable work functions [2]. To characterize and optimize ohmic contacts, the Transfer Length Method (TLM) has become an industry-standard technique [2]. The standard TLM evaluation allows for the extraction of the specific contact resistivity (ρC) and the sheet resistance ( RSH ) of the semiconductor layer between the contacts [3]. The accuracy of these extracted parameters is highly dependent on the design of the TLM test structure and the assumptions made during the analysis [4,2].
This work presents a systematic simulation-based study using TCAD Sentaurus [5] to investigate and quantify the impact of the contact length L on the extraction of contact front resistance RCF and contact end resistance RCE in 4H-SiC TLM test structures. Scenarios where RSK and RSH differ are analyzed, exploring the conditions where the regular TLM analysis comes to its limits.

Standard TLM Evaluation and Parameter Extraction

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According to the standard TLM evaluation, the total resistance RT measured between two adjacent ohmic contacts is linearly dependent on the spacing di between them, as described by the following equation [4]:

RT=(RSH/Z)d+2RCF(1)

Here, RCF is the contact resistance, RSH is the sheet resistance of the doped semiconductor layer, and Z is the contact width of the TLM test structure. The standard model relies on the assumption of a uniform sheet resistance ( RSH=RSK ) [6, 7]. In this work, ideal material properties and interfaces are assumed in the simulation, resulting in a linear relationship between RT and di (i.e., with a coefficient of determination R2=1 ), this criterion is not always matched in real measurements. The analytical procedure begins by determining RT from simulated current-voltage (I-V) characteristics for a range of different contact spacings di. The resistance values are then plotted as a function of d, as shown in Fig. 1. A linear regression applied to this data allows for the extraction of key parameters: The slope of the fit yields RSH/Z, the y -axis intercept corresponds to 2RCF, and the x -axis intercept corresponds to −2LT.LT is the distance after which the potential under the contact drops to 1/e, i.e., it describes

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Fig. 1: Graphical representation of the standard TLM evaluation. The total resistance RT is plotted against the contact spacing d. The sheet resistance RSH is extracted from the slope of the linear fit, while the contact resistance RCF and transfer length LT are determined from the y - and x -axis intercepts, respectively.

Fig. 1. Graphical representation of the standard TLM evaluation. The total resistance R T is plotted against the contact spacing d . The sheet resistance R S H is extracted from the slope of the linear fit, while the contact resistance R C F and transfer length L T are determined from the y - and x -axis intercepts, respectively.

the length of the contact that mainly contributes to the current flow and is calculated by the following equation:

LT=RCF·Z/RSH(2)

The specific contact resistivity ρC, which is a measure of the contact quality independent on geometry, can be calculated either through the coth, which considers the potential distribution under the contact, or by an approximation, which is only valid for long contacts (L≫LT) [4]:

ρC=RCF·LT·Z/coth(L/LT)ρC=RSH·LT2(3)

TLM Evaluation with Contact End Resistance

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To account for the discrepancy between RSK and RSH, the evaluation can be extended by additionally measuring the contact end resistance RCE[8].RCE describes the resistance at the trailing edge of the

TLM contact. The contact front resistance RCF and the contact end resistance RCE can be derived as [4]:

RCF=V(x=0)I(x=0)=RSKρCZcoth(L/LTk)=ρCLTkZcoth(L/LTk)RCE=V(x=L)I(x=0)=VCEI=RSKρCZ1sinh(L/LTk)=ρCLTkZ1sinh(L/LTk)

(4)(5)

Here, L is the contact length, and LTk is the transfer length defined as LTk=ρcRSK. Note that LTk is the true transfer length under the contact, which may differ from the apparent transfer length LT extracted from the standard TLM plot, as LT is derived assuming RSK=RSH. The ratio of RCE to RCF depends only on L relative to LTk :

RCERCF=1cosh(L/LTk)(6)

This relationship, in combination with Eq. 4 and 5, allows the determination of LTk,ρC, and RSK.LTk can be calculated by rearranging the resistance ratio equation:

LTk=Larcosh(RCF/RCE)(7)

With LTk known, ρC is calculated without the implicit assumption of RSK=RSH, which does not account for a differing RSK :

ρc=LTk·Z·RCEsinh(L/LTk)(8)

Finally, RSK is determined using the definition of LTk :

RSK=ρCLTk2(9)

The advanced analysis with RCE enables a more accurate determination of ρC and an insight into the impact of the contact fabrication on the underlying semiconductor layer.

Simulation Methodology

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A three-contact TLM test structure is investigated in 2D using Synopsys TCAD Sentaurus, using standard physics models for 4H−SiC, including models for doping-dependent mobility and incomplete ionization of dopants. The simulated structure, depicted in Fig. 2, consists of a p-type doped layer on a lightly doped n -type epitaxial layer with a background concentration of 1×1015 cm−3. The doping of the p-type implanted layer is fixed to a concentration of 1×1019 cm−3. The specific contact resistivity is set to ρC=0.5 mΩ cm2. To investigate the impact of the contact processing, the sheet resistance directly under the contacts RSK  was independently controlled by varying the net active doping concentration within the top 100 nm of this implanted layer. This setup allows for a systematic study of the effects of a non-uniform sheet resistance ( RSK≠RSH ). RCE is determined by measuring the potential at contact C 3 . This potential is identical to the potential of the trailing edge ( x=L ) of the currentcarrying contact C2 relative to the leading edge ( x=0 ) of C2, where the current injection takes place. Contact C3 is modeled as a floating voltage probe by constraining its current to zero. The resistance value of RCE is independent on the spacing di between the contacts, but strongly dependent on L and the sheet resistance of the layers under the contact. Current-Voltage (I-V) characteristics (Fig. 3) are simulated across a range of contact lengths L and contact spacings di by sweeping the voltage and measuring the current between the contacts C 1 and C 2 . This approach addresses a significant limitation of the standard TLM evaluation: The assumption of a uniform sheet resistance ( RSH=RSK ), which is often invalid in practice. For instance, forming nickel silicide ( NixSiy ) contacts to n -type SiC

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Fig. 2: Cross-section and top view schematic of the simulated device for a TLM test structure with a third contact, which serves as a voltage probe.

Fig. 2. Cross-section and top view schematic of the simulated device for a TLM test structure with a third contact, which serves as a voltage probe.

[picture]

Fig. 3: I-V characteristic for two different di and L for determining the resistance values for the standard TLM evaluation (left) and RCE  (right).

Fig. 3. I-V characteristic for two different d i and L for determining the resistance values for the standard TLM evaluation (left) and R CE (right).

selectively consumes silicon [9], while forming TiAl-based contacts to p-type SiC consumes SiC to form TixSiCy[10]. Both processes alter the stoichiometry and doping profile, leading to a discrepancy ( RSK≠RSH ) that can cause errors in the extracted ρC.
The measurement of RCE enables the separation of the sheet resistances RSK from RSH, leading to a more accurate determination of ρC[11]. However, the ability to accurately measure RCE depends on the geometric design. The contact length L must be carefully chosen relative to the contact length [3] as shown in the simulation data presented in the following sections. The simulation results are normalized to a standard device width of Z=1μ m, which corresponds to the contact width. RSK is controlled independently of RSH  by defining a separate net doping concentration in that region. This idealized approach allows for a direct investigation of the impact of the RSK/RSH ratio on the extracted parameters, decoupled from the complex and process-specific physics of contact formation.
The simulation procedure is designed to extract RCF and RCE. To determine RCF, the total resistance RT between adjacent contacts is simulated for several structures with systematically varied contact
spacings di.RCF is then extracted from the y -intercept of a linear fit of RT versus d and RSH from the slope of the same plot, consistent with the standard TLM analysis:

RT=VCF(d)/I(d)(10)

To determine RCE, the current I between C 1 and C 2 is measured, and the potential difference between the current-carrying contact C 2 and the floating contact C 3 is recorded. RCE is then calculated by:

RCE=VCE/I(11)

The entire procedure is repeated for different L and RSK/RSH to analyze their combined influence on the extracted parameters.

Discussion of Simulation Results

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Fig. 4 compares the ideal case ( RSK=RSH ) with a uniform sheet resistance across the TLM test structure with a more realistic scenario where the sheet resistance under the contact is higher ( RSK>RSH ). The specific contact resistivity ρC and sheet resistance values extracted from these linear fits show

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Fig. 4: Standard TLM evaluation plot: R is shown in dependence on di for different contact lengths L, for L=5μ m also the case of RSK>RSH is shown.

Fig. 4. Standard TLM evaluation plot: R is shown in dependence on d i for different contact lengths L , for L = 5 μ m also the case of R S K > R S H is shown.

good agreement with the input parameters of the simulation for the ideal case, confirming the validity of the model and the extraction methodology.
When RSK>RSH, the total measured resistance increases, resulting in a significantly larger yintercept. A standard TLM analysis would erroneously attribute this entire increase to a higher RCF, leading to an inaccurate calculation of the specific contact resistivity ρC. These simulations underscore the necessity of measuring RCE to correctly separate the different resistance contributions. As seen in Fig. 4, using a contact length L shorter than LT results in a higher extracted RCF. Meanwhile, increasing L reduces the contact resistance only up to a certain limit, with similar y -axis intercepts observed for L=5μ m and L=20μ m in Fig. 4).

Impact of contact length L on extracted resistances. L has a significant effect on the extracted values of RCE. This relationship is illustrated in Fig. 5, which shows the simulated resistances as a function of L. The data reveals a design trade-off for accurate parameter extraction. While RCF remains largely independent of the contact length for L>LT,RCE shows a strong dependence.

For short contacts ( L≈LT ), RCE is easily measurable, but becomes sensitive to manufacturing variations in L. In contrast, for long contacts (L≫LT),RCE diminishes exponentially and approaches zero. Thus, a correct extraction of RCE is not possible due to measurement limitations. The observed trend

[picture]

Fig. 5: Dependence of RCF and RCE on the contact length L shown for different RSH and RSK.RCE is approaching zero and thus not measurable for large L. Meanwhile, RCF  shows an asymptotic approach to a fixed value for large L. The distance between contact C2 and C3 is equal to the one between C1 and C2 in this simulation, the value of RCE is independent of the spacing di.

Fig. 5. Dependence of R C F and R C E on the contact length L shown for different R S H and R S K . R C E is approaching zero and thus not measurable for large L . Meanwhile, R CF shows an asymptotic approach to a fixed value for large L . The distance between contact C2 and C3 is equal to the one between C1 and C2 in this simulation, the value of R C E is independent of the spacing d i .

in Fig. 5 reveals a fundamental trade-off. For L≫LT the current transfer is essentially completed well before the physical end of the contact. Consequently, VCE (and thus RCE ) becomes vanishingly small. In an experimental setting, this small voltage would be lost in the measurement noise, making an accurate extraction of RCE  impossible. Without a reliable RCE  value, the separation of RSK  from RSH  is not possible. For short contacts, small absolute variations represent large percentual variation in L, making the extracted values of RCE highly susceptible to manufacturing tolerances, leading to poor statistical reproducibility across a wafer. Consequently, an effective design requires a L comparable to the contact's specific LT. This is a critical consideration for 4H−SiC, where LT can vary significantly (e.g., LT≈0.5μ m for contacts to n-type SiC vs. LT≈4μ m for contacts to p-type SiC - this data was extracted by using the standard TLM evaluation) [12].
Comparison between ρC values from both analyses. To quantify the error introduced by the standard TLM evaluation, we compared ρC obtained from the two different sets of equations explained in the previous section: For the standard analysis, ρC is calculated using the standard TLM evaluation with and without the approximation for the coth according to Eq. 3, which assumes a uniform sheet resistance ( RSK=RSH ). In contrast, for the TLM analysis with RCE,ρC is calculated using the more comprehensive model that incorporates the measured RCE, as described in Eq. 8.
The results are plotted in Fig. 6. For the more realistic scenario with RSK>RSH, the standard analysis significantly overestimates the true ρC (grey dotted line). In contrast, the TLM analysis with RCE, which accounts for the non-uniformity, extracts ρC more accurately. This result confirms that the RCE measurement is essential for the accurate characterization of real ohmic contacts. For the case of RSK=RSH, both methods yield similar results as expected.

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Fig. 6: ρC determination with different evaluation routines are shown. The ρC determination with RCE is more accurate for RSK>RSH, while there is no significant difference for the ideal case of RSK=RSH.

Fig. 6. ρ C determination with different evaluation routines are shown. The ρ C determination with R C E is more accurate for R S K > R S H , while there is no significant difference for the ideal case of R S K = R S H .

Conclusion

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Through 2D TCAD simulations, this work has quantitatively demonstrated that the contact length L is a critical design parameter for the accurate characterization of 4H−SiC ohmic contacts using RCE, i.e., the determination of ρC and the decoupling of RSK and RSH. This implies that TLM test structures must be carefully designed: L must be within the range of the transfer length. This makes L a critical design parameter, as LT is not a fixed value. Contacts to n - and p -type 4 H -SiC require different L, as their respective processing conditions and contact schemes yield significantly different transfer lengths LT. LT strongly depends on the contact material and the semiconductor doping. Therefore, an optimized TLM design for different contacts and materials is required. Measuring RCE  is essential for correctly determining the specific contact resistivity ( ρC ) in realistic scenarios where the sheet resistance is nonuniform ( RSK≠RSH ). Adopting these guidelines will enable the design of more accurate TLM test structures.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.89.pdf

T. Kimoto, Fundamentals of silicon carbide technology. John Wiley & Sons Singapore Pte. Ltd, 2014.

K. Zekentes and K. Vasilevskiy, Advancing Silicon Carbide Electronics Technology I, vol. 37. Materials Research Forum LLC, 2018.

G. K. Reeves and H. B. Harrison, "Obtaining the specific contact resistance from transmission line model measurements," vol. 3, no. 5, pp. 111-113, 1982.

D. K. Schroder, Semiconductor material and device characterization. IEEE Press and Wiley, 3rd ed. ed., 2006.

Synopsys, "Sentaurus device user guide."

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H.-J. Ueng, D. B. Janes, and K. J. Webb, "Error analysis leading to design criteria for transmission line model characterization of ohmic contacts," vol. 48, no. 4, pp. 758-766, 2001.

G. K. Reeves and B. Harrison, "An analytical model for alloyed ohmic contacts using a trilayer transmission line model," vol. 42, no. 8, pp. 1536-1547, 1995.

S. Y. Han, K. H. Kim, J. K. Kim, H. W. Jang, K. H. Lee, N.-K. Kim, E. D. Kim, and J.-L. Lee, "Ohmic contact formation mechanism of ni on n-type 4h-sic," vol. 79, no. 12, pp. 1816-1818, 2001.

S. Tsukimoto, K. Ito, Z. Wang, M. Saito, Y. Ikuhara, and M. Murakami, "Growth and microstructure of epitaxial contact layers on sic," vol. 50, no. 5, pp. 1071-1075, 2009.

W. M. Loh, S. E. Swirhun, T. A. Schreyer, R. M. Swanson, and K. C. Saraswat, "Modeling and measurement of contact resistances," vol. 34, no. 3, pp. 512-524, 1987.

M. Rommel, A. May, L. Baier, J. Kauth, N. Bottcher, and M. Jank, "Investigation of ohmic contacts and resistances of a 4h-sic cmos technology up to 550 degrees c," vol. 21, no. 4, 2024.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1192, pp 97-103

doi: 10.4028/p-t0ptSI

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-26

Accepted:
2026-02-26

Online:
2026-05-20

Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

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M. Kobayashi 1,a*, S. Ishikawa 2,b, Y. Higashi 2,c, H. Sezaki 3,d, M. Okamoto 2,e, S. Harada 2,f and K. Kojima 2, g

1 Sumitomo Metal Mining Co., Ltd., 5-11-3, Shimbashi, Minato-ku, Tokyo 105-0004, Japan

2 Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Ibaraki 305-8568, Japan

3 PHENITEC SEMICONDUCTOR Corp., 6833, Kinoko-cho, Ibara, Okayama 715-8602, Japan

a*motoki.kobayashi.x2@smm-g.com, b  ishikawa-seiji@aist.go.jp, chigashi-phenitec@aist.go.jp, d  hiroshi-sezaki@phenitec.co.jp, e  mitsuo-okamoto@aist.go.jp, f  s-harada@aist.go.jp, 9kazu-kojima@aist.go.jp

Keywords: bonded substrate, low-resistivity polycrystalline layer, backside contact resistance, SIMS, hall measurement, circular TLM, threshold resistivity.

Abstract

In this study, 4H−SiC bonded substrates (bonded- SiC ) with an average resistivity of 2.431.5 mΩ· cm were prepared, and attention has been directed toward the relationship between the resistivity of bonded- SiC and the contact resistance at the backside where metal Ti/Ni was applied. A circular transmission line model (cTLM) was used to accurately measure the backside contact resistance. A linear correlation was found between ρC and the resistivity of bonded-SiCs at room temperature (RT). This result indicates the existence of a threshold resistivity at which the specific contact resistance ( ρC ) in the range of 2.2×10−6 to 1.5×10−5Ω· cm2 can be achieved without contact annealing; it also indicates that the temperature dependence of ρC between 17.4 and 34.4 mΩ· cm of the resistivity on bonded-SiCs is eliminated. This phenomenon can occur because ρC is dominated by tunneling current above the nitrogen concentration at the threshold resistivity, which is driven by the high nitrogen concentration and sufficient carrier activation in the polycrystalline portion (polycrystalline layer) of bonded-SiCs. These are important properties resulting from a polycrystalline layer with a 3C structure in bonded-SiC.

Introduction

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The 4H−SiC bonded- SiC ( SiCkrestTM ) consists of a thin monocrystalline 4H−SiC layer with a thickness of less than 1μ m, which is bonded to an n-type low-resistivity polycrystalline 3C-SiC substrate via surface-activated bonding. Fig. 1 shows (a) the photogram and (b) the schematic structure of SiCkrest TM. Some features of this substrate, for example, no unstable interlayer at bonded interface, which is shown in this cross-sectional transmission electron microscope (TEM) image, enables to apply various high temperature process of SiC . And the polycrystalline layer exhibits a low resistivity of under 10 mΩ· cm, which is significantly lower than that of the 4H−SiC monocrystalline substrate. This hybrid structure can be applied to the same epitaxial growth and device processes as conventional 4H−SiC bulk substrates [1,4]. In addition, compared with traditional 4H-SiC bulk substrates, it has reduced on-state resistance [1] and suppressed forward bias degradation in PiN diodes [2, 3] and a significant decrease in switching loss within the body-diode of MOSFETs [4].

In a previous study, this low-resistivity bonded-SiC not only reduced the on-resistance of SBD but also provided a low-resistance backside contact without the need for contact annealing and reduced temperature dependence [5]. However, the effect of resistivity on the necessity for contact annealing and the temperature dependence of ρC remains unclear because the resistivity of the bonded- SiCs tested in our previous research was only 10 mΩ· cm. In this study, bonded-SiCs with an average resistivity ranging from 2.4 to 31.5 mΩ· cm were prepared, and attention has been directed toward the relationship between the resistivity of the bonded- SiC and the contact resistance at the grinded
backside where metal Ti/Ni was applied. A cTLM was used to accurately measure the contact resistance. The relationship between the resistivity of the bonded- SiC and the backside contact resistance was clarified, and the mechanism underlying such a relationship was investigated.

[picture]

Fig. 1. (a) the photogram and (b) the schematic structure of SiCkrest TM and TEM image of bonded interface.

Fig. 1. (a) the photogram and (b) the schematic structure of SiCkrest T M and TEM image of bonded interface.

Experimental

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Fig. 2 presents the resistivity of the bonded-SiCs prepared in this study, which possessed an average resistivity ranging from 2.4 to 31.5 mΩ· cm compared with 10 mΩ· cm of the previous study. The polycrystalline layer of the bonded-SiCs with different resistivities was prepared by changing the nitrogen concentration through chemical vapor deposition. he resistivity of the bonded-SiCs was evaluated by using Eddy current measurements, whereas the nitrogen concentration in the polycrystalline layer was analyzed by using secondary-ion mass spectrometry (SIMS), and the carrier concentration was determined through Hall measurements, as shown in Fig. 3 (a). Fig. 3 (b) shows the measurement position within a substrate of the resistivity, nitrogen concentration, and carrier concentration. Resistivity and ρC were measured at 37 points across the entire surface and five points, respectively. Other analyses were performed at the same position (see Fig. 3 (b)) within the substrate for accurate comparison.

[picture]

Fig. 2. Resistivity of the bonded-SiCs prepared in this study.

Fig. 2. Resistivity of the bonded-SiCs prepared in this study.

[picture]

Fig. 3. (a) Evaluation items and methods for bonded- SiCs and polycrystalline layers.
(b) Measurement position within a substrate in this study.

Fig. 3. (a) Evaluation items and methods for bonded- SiCs and polycrystalline layers. (b) Measurement position within a substrate in this study.

cTLM was used to accurately measure the ρC [6, 7]. Fig. 4 illustrates (a) the process flow, (b) schematic structure, and (c) a split table of the cTLM samples. Three types of samples were tested in this study: (1) 4H−SiC monocrystalline substrate (mono- SiC ) with contact annealing, (2) bonded- SiCs with contact annealing, and (3) bonded-SiCs without contact annealing. I-V measurements were conducted using an Agilent 4156C, with the temperature controlled at RT, 75∘C,125∘C, and 175∘C using a hot plate.

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Fig. 4. (a) Process flow, (b) schematic image of the cTLM structure, and (c) split table for cTLM samples in this study.

Fig. 4. (a) Process flow, (b) schematic image of the cTLM structure, and (c) split table for cTLM samples in this study.

Results and Discussion

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Relationship between the resistivity of the bonded substrate and theρ𝐂

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Fig. 5 illustrates the relationship between the resistivity of bonded- SiCs and ρC at RT. Both measurements were conducted at the same locations on the substrate (center and four peripheral positions) to accurately investigate the correlation between resistivity and ρC. This result indicates a linear correlation between the resistivity of bonded-SiCs and ρC when the resistivity is 17.4 mΩ· cm or lower at RT. Even without contact annealing, at the lowest resistivity point in the substrate, the resistivity of the bonded-SiC is 1.9 mΩ· cm, whereas ρC is approximately 2.2×10−6Ω· cm2 at RT, which is equivalent to an ohmic contact to a mono-SiC using n+doping and high-temperature annealing [6]. Furthermore, as indicated by the symbols ■ and • for ρC without and with annealing, respectively, no difference in ρC between the two was observed for any resistivity values of
17.4 mΩ· cm or less. However, for resistivity values exceeding 17.4 mΩ· cm,ρC increased and varied across the substrate without contact annealing.

Fig. 6 shows the distribution of ρC within a substrate (Fig. 5 (a) and (b)). Bonded-SiCs with resistivities of approximately 17 and 34 mΩ· cm showed minimal variations in ρC with annealing. By contrast, bonded-SiCs with a resistivity near 34 mΩ· cm without annealing exhibited a significant variation in ρC similar to mono- SiC because of unstable silicide formation with a backside metal.

[picture]

Fig. 5. Relationship between the resistivity of bonded-SiCs and ρC at RT. The symbols ■ and • indicate ρ𝐂 without and with annealing, respectively.

Fig. 5. Relationship between the resistivity of bonded-SiCs and ρ C at RT. The symbols ■ and • indicate ρ 𝐂 without and with annealing, respectively.

Fig. 6. Distribution within a substrate of ρ𝐂 : (a) bonded-SiCs with a resistivity near 17 mΩ· cm, as plotted in Fig. 5 (a); (b) bonded-SiCs with a resistivity near 34 mΩ· cm, as plotted on Fig. 4 (b); and (c) mono-SiC.

Fig. 7 (a) shows the temperature dependence of ρC for mono- SiC with annealing and bonded- SiCs without annealing, as well as for bonded- SiCs as a function of resistivity. Mono- SiC showed a strong temperature dependence in the previous study [5], whereas bonded-SiCs exhibited no temperature dependence at 17.4 mΩ· cm or less and a weak negative temperature dependence at 34.4 mΩ· cm. Fig. 7 (b) presents the relationship between the resistivity of bonded-SiCs and ρC at RT,175∘C, and the difference ( ΔρC ) between RT and 175∘C. In mono- SiC and bonded- SiCs with a resistivity of 34.4 mΩ· cm or more, ΔρC indicates a negative value (negative temperature characteristic).

These results indicate the existence of a threshold resistivity at which the ρC in the range of 2.2×10−6 to 1.5×10−5Ω· cm2 can be achieved without contact annealing; it also indicates that the temperature dependence of ρC between 17.4 and 34.4 mΩ· cm is eliminated.

[picture]

Fig. 7. (a) Temperature dependence of ρ𝐂 of bonded- SiCs(𝐦) and mono- SiC(•). Resistivity varies from 2.6 to 34.4 mΩ· cm for the bonded-SiCs. (b) Relationship between the resistivity of bondedSiCs and ρC at RT, 175∘C, and the difference ( ΔρC ) between RT and 175∘C.

Fig. 7. (a) Temperature dependence of ρ 𝐂 of bonded- S i C s ( 𝐦 ) and mono- S i C ( • ) . Resistivity varies from 2.6 to 34.4 m Ω · c m for the bonded-SiCs. (b) Relationship between the resistivity of bondedSiCs and ρ C at RT, 175 ∘ C , and the difference ( Δ ρ C ) between RT and 175 ∘ C .

Analysis of a polycrystalline layer of a bonded substrate

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Fig. 8 presents the results of SIMS and Hall measurements, illustrating (a) the relationship between the resistivity of bonded-SiCs and nitrogen concentration and (b) the relationship between nitrogen concentration and carrier concentration, as compared with mono-SiC. The nitrogen concentration in bonded-SiCs correlates with the resistivity of the polycrystalline layer and is one order of magnitude higher than that in mono-SiC with similar resistivity (see Fig. 8 (a)). This is due to the low carrier mobility in the polycrystalline layer; however, it is easy to increase the nitrogen concentration by an order of magnitude in the polycrystalline layer. Furthermore, the nitrogen and carrier concentrations in the polycrystalline layer of bonded-SiCs were nearly identical, indicating that the nitrogen in the polycrystalline layer was nearly 100% activated (see Fig. 8 (b)). Yu et al. have presented the relationship between ρC and donor concentration (ND) [8], and it is known that ρC depends on carrier concentration. Below, we discuss the effect of high carrier concentration in polycrystalline bonded SiC on ρC.

[picture]

Fig. 8. Relationship between (a) the resistivity of bonded- SiCs and nitrogen concentration and between (b) nitrogen concentration and carrier concentration in the polycrystalline layer of bondedSiCs as compared with mono-SiC.

Fig. 8. Relationship between (a) the resistivity of bonded- SiCs and nitrogen concentration and between (b) nitrogen concentration and carrier concentration in the polycrystalline layer of bondedSiCs as compared with mono-SiC.

Fig. 9 (a) presents the band diagram for the ohmic contact of mono- SiC as reported [6, 9]. For mono-SiC, n+doping with a concentration exceeding 1×1019 cm−3, combined with high-temperature annealing, can provide low-resistance ohmic contact to 4 H mono-SiC. n+doping increases the Fermi level ( EF ) of the mono-SiC above its conduction band energy ( EC ), resulting in a thin Schottky barrier. Considering that the conduction between mono-SiC and a metal is dominated by tunneling current, extremely low-resistance ohmic contact can be achieved. In this case, the carrier transport mechanism is known as field emission.

Fig. 9 (b) illustrates the band diagram for a polycrystalline layer of bonded-SiC with ohmic contact, as predicted based on results in this study. As shown in Fig. 7, the ρC of the polycrystalline layer on bonded-SiC exhibited no temperature dependence below the threshold resistivity, indicating that tunneling current is the dominant conduction mechanism between the polycrystalline layer and the backside metal. By contrast, the ρC on mono-SiC shows temperature dependence, indicating that thermally excited current and tunneling current contribute to the conduction. In this case, the mechanism underlying current transport through the barrier is known as thermionic field emission. Similarly, above the threshold resistivity, ρC of the polycrystalline layer on bonded-SiC exhibits temperature dependence, indicating that thermally excited current becomes dominant alongside tunneling current in the conduction between the polycrystalline layer and the backside metal.

Furthermore, a linear correlation exists between the resistivity of bonded- SiCs and ρC below the threshold resistivity (Fig. 5). Similar to the mechanism underlying the ohmic contact of mono-SiC
(Fig. 9 (a)), a high nitrogen concentration in the polycrystalline layer leads to a thinner barrier width and increased tunneling current. Thus, ρC is primarily determined by the resistivity of the polycrystalline layer of bonded-SiC. Considering that ρC is primarily governed by ND and barrier height (ϕB)[8], when tunneling current dominates the ohmic contact, the current depends on ND. In addition, the polycrystalline layer has a high nitrogen concentration (Fig. 8), with nearly 100% activation, resulting in a carrier concentration of 1.5×1020 cm−3 (at a resistivity of 2.6 mΩ· cm ). This value is an order of magnitude higher than the n+doping concentration required for mono-SiC tunnel ohmic contacts ( ≥1×1019 cm−3 ). Therefore, the EF value of the polycrystalline layer can be close to or above Ec , which is similar to the band structure of n+doped mono-SiC ohmic contact [6]. Under these conditions, a large number of electrons exist above the conduction band, which could be a key factor that increases tunneling current. These results also support that, above the nitrogen concentration at the threshold resistivity, tunneling current is the dominant conduction mechanism between the polycrystalline layer and the backside metal.

As shown in Fig. 9, by simplifying the equation presented by Yu et al. [8], ρC is proportional to exp(ϕB/N). In order to analytically model a linear relationship between ρC and resistivity of the polycrystalline layer of bonded-SiC, it is necessary to clarify the relationship between carrier concentration and resistivity; however, this has not yet been achieved. Additionally, the formation of Ti/Ni silicide in the backside contact affects both the ϕB at the silicide interface and the thickness of the natural oxide layer (tunneling distance) at the interface. However, since the contact between the polycrystalline layer and Ti/Ni is ohmic, it is difficult to measure the barrier height, and thus the influence of ϕB has not been separated. These remain issues to be addressed in future work.

[picture]

Fig. 9. Band diagrams of the (a) tunnel ohmic contact of 4H−SiC using n+doping and the hightemperature annealing [6] and (b) ohmic contact of 3C-SiC polycrystalline with a backside metal.

Fig. 9. Band diagrams of the (a) tunnel ohmic contact of 4 H − S i C using n + doping and the hightemperature annealing [6] and (b) ohmic contact of 3C-SiC polycrystalline with a backside metal.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1192.97.pdf

In this study, bonded-SiCs (SiCkrest TM ) with an average resistivity of 2.4−31.5 mΩ· cm were prepared. The relationship between the resistivity of the bonded-SiCs and the backside contact resistance was clarified, and the mechanism underlying such a relationship was investigated.

In the polycrystalline layer of bonded-SiC, the correlation between the resistivity of bonded-SiCs and ρC indicates the existence of a threshold resistivity at which low ρC can be achieved without contact annealing; it also indicates that the temperature dependence of ρC is eliminated. This phenomenon is attributed to the dominance of tunneling current above the nitrogen concentration at the threshold resistivity, which is driven by a high nitrogen concentration and sufficient carrier activation in the polycrystalline layer of bonded-SiCs. These are important properties resulting from a polycrystalline layer with a 3C structure in bonded-SiC.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/MSF.1192.97.pdf

This paper was produced as part of a joint research project of Tsukuba Power Electronics Constellations. The co-authors, S. Ishikawa and Y. Higashi, are affiliated with PHENITEC Semiconductor Corp.

References

The original version of this paper is available on https://www.scientific.net/MSF.1192.97.pdf

T. Shimono, H. Uchida, A. Onogi and H. Fujiwara, presented at the 7th  Meeting on Advanced Power Semiconductors, Japan (2020).

N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, K. Yagi, M. Kobayashi, S. Kurihara, S. Harada and K. Kojima, Key Engineering Materials 948, p. 107 (2023).

H. Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, S. Kurihara, S. Harada and K. Kojima, Abstract of 20th ICSCRM, p. 209 (2023).

Y. Higashi, S. Ishikawa, K. Ozono, M. Kobayashi, H. Uchida, M. Okamoto, S. Harada, K. Kojima, T. Kato and Y. Tanaka, Scientific Books of Abstracts, 8, 12-13, 2024.

M. Kobayashi, H. Uchida, N. Hatta, S. Ishikawa, Y. Higashi, H. Sezaki, S. Harada and K. Kojima, Scientific Books of Abstracts, 8, 396-398, 2024.

F. Roccaforte, F. La Via and V. Raineri, International Journal of High Speed Electronics and Systems, 15, 77-116, 2006.

G.K. Reeves, Solid-State Electron, 23, 487-490, 1980.

Y. Liu, S. P. Singh, L. M. Kyaw, M. K. Bera, Y. J. Ngoo, H. R. Tan, S. Tripathy, G. Q. Lo, and E. F. Chora, ECS Journal of Solid State Science and Technology, 4, 30-35, 2015.

K. Maeda, K. Kuwahara, M. Hara, M. Kaneko and T. Kimoto, Scientific Books of Abstracts, 8, 402-404, 2024.

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Chapter 7: Performance Analysis of SiC Power Devices

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 1-5

doi: 10.4028/p-AOAv5u

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-28

Revised:
2025-12-08

Accepted:
2026-03-08

Online:
2026-05-21

Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Suman Das 1,a, Daniel J. Lichtenwalner 1, b*, Shane R. Stein 1,c and Sei-Hyung Ryu 1,d

1 Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

a  suman.das@wolfspeed.com, b  daniel.lichtenwalner@wolfspeed.com, c  shane.stein@wolfspeed.com, d  sei-hyung.ryu@wolfspeed.com

Keywords: gated Hall, Hall mobility, interface traps, Coulomb scattering, surface phonon, surface roughness, mobility modeling.

Abstract

Gated Hall measurements of lateral MOSFET devices can be used to directly measure the inversion layer free carrier density and carrier Hall mobility. From this measurement the total number of charged interface traps ( NIT ) can be extracted. This provides useful insight into the degree of Coulomb scattering expected. By obtaining gated Hall data from 4∘ off-axis Si-face ( 0001 ) 4H−SiC MOSFETs with varied p -well doping levels, mobility limiting components can also be estimated. For these samples it is observed that interface trapped charge is almost half of the total inversion charge, and thus Coulomb scattering dominates at low Vgs or low transverse (or normal) effective field; while phonon scattering may dominate at moderate effective field, and surface roughness only limits mobility at gate fields higher than the rated usage, or at doping levels much higher than 2×1018 cm−3.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Although the oxide reliability and threshold stability of Si-face (0001) 4H−SiC MOSFETs is relatively good using the established thermal oxidation and NO anneal process [1], it is known that improvements in channel mobility are possible [2], and better measurements of channel properties can be helpful to fully understand the limits of performance. Gated Hall measurements have been found to be a useful way to extract not only carrier mobility (Hall mobility), but also the free carrier density (carriers/ cm2 ) and total trapped charge ( NIT  ) [3-7]. When performing gated Hall measurements on samples with varied p-well doping levels, the mobility limiting components can more accurately be extracted. This enables a more complete understanding of the interface properties, regarding the limiting factors controlling the inversion-layer channel mobility.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Figure 1(a) shows a top view and Fig. 1(b) shows a schematic cross-section of the fabricated MOS gated Hall bar. The Hall bar is fabricated on a Si-face (0001) 4∘ off-axis 4H−SiC n-type wafer with low doped n -type epilayers, on uniform Al-doped implanted p -well layers ( 1 um in depth) with doping values of 2×1017,4×1017,1×1018 and 3×1018 cm−3. This is a long channel ( Lch=1 mm, Wch=200um ) lateral MOSFET with Hall voltage contacts, designed to minimize errors due to geometric effects [8]. The gate oxide is a typical thermal oxide passivated with a NO anneal. All samples have the same P+ and N+ doped regions, the same activation anneal, and the same gate oxidation process. The only difference between samples is the implanted Al p -well concentrations.

DC Hall measurements are performed at room temperature using a Lakeshore FastHall system with a gate bias option and a 1 Tesla permanent magnet. The Vgs is stepped from the threshold ( VT ) value to a Vgs above device use fields to cover a wide range of data for each of the samples measured. As the VT increases for higher doped samples, a narrower data range is obtained as doping increases. The Vgs has been converted to effective normal field as described by Noguchi [5], using η=1/3, and a Hall scattering factor of unity used for mobility and free carrier calculations from the Hall data.

[picture]

Fig. 1(a). Top-view schematic of a gated Hall MOSFET. Lchan =1 mm, and Wchan =200 um.

Fig. 1. (a). Top-view schematic of a gated Hall MOSFET. L chan = 1 m m , and W chan = 200 um.

[picture]

Fig. 1(b). Schematic cross section of a gated Hall MOSFET along the channel length. In gated Hall only inversion charge (dotted line) is measured as a function of Vgs.

Fig. 1. (b). Schematic cross section of a gated Hall MOSFET along the channel length. In gated Hall only inversion charge (dotted line) is measured as a function of Vgs.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Figure 2 shows the measured (a) field-effect ( μFE ) and (b) Hall mobility ( μHall  ) for different pwell doping concentrations at room temperature. The difference between μFE and μHall  occurs due to the high density of interface traps, and the assumption in the field-effect calculation that the carrier concentration is determined only by oxide thickness and dielectric constant (disregarding trapped charge). Gated Hall allows the free charge (Ns or nfree ,cm−2 ) to be measured as a function of Vgs. The interface trapped charge ( NIT  or ntrap ,cm−2 ) is then determined by subtracting the measured free charge from the total inversion charge. The total charge at the interface is obtained using a split C−V measurement between G to S−D keeping the B contact grounded. A typical split C−V measurement at 5 kHz is shown in Fig. 3, from which integration shows the total channel charge on the right y -axis (after subtracting gate to N+ overlap capacitance). The total charge density ( ntotal  ) measured is consistent with the value calculated from the measured Tox and Cox. The occupied trapped charge density ( ntrap  ) for all samples is plotted in Fig. 4, obtained from the gated Hall measured value of nfree  (data points) subtracted from the measured total charge (ntotal ). In order to show the data together more clearly, the Vgs is scaled by the Vt. It appears that a slight increase in ntrap  is observed as doping increases. This could be a result of the fermi level change with doping, resulting in more filled traps at a given Vgs - Vt. Of note is that the charged interface trap density is similar to that of the free carriers, and even up to the rated Vgs use conditions nearly half of all inversion layer carriers are trapped.

To observe the overall effect of all scattering mechanisms at the channel, the Hall mobility can be modeled from the individual mobility limiting components, namely the bulk mobility limiting factors (μBulk), Coulomb limited mobility ( μC ), surface phonon limited mobility ( μPh ), and surface roughness limited mobility ( μSR ). The Coulomb limited mobility can then be calculated from the measured Hall mobility using Mattheissen's rule:

1μC=1μHall −1μBulk +1μPh+1μSR(1)

The field ( Eeff  ) dependence of μPh and μSR are taken from previous observations in literature [3,5,9,10]. Values for the bulk mobility are chosen based on the doping levels, and the surface phonon limiting term is taken as being close to that of other reports [4,5] using the ideal exponent ( Eeff−0.33 ). The surface roughness limiting term was chosen such that it corresponds closely to the ideal functional form ( Eeff−2 ). All prefactors are adjusted such that the data for all doping levels is fit well, and the extracted coulomb scattering term follows a power law relationship to Ns or nfree [5].

In Fig. 5 the Hall mobility versus effective normal field (Eeff) is plotted for the sample with 2×1017 cm−3p-well doping. The red dotted line is the fit to the data considering all the scattering components.

[picture]

Fig. 2. Comparison of (a) the field-effect mobility measured from Id-Vgs curves, and (b) the Hall mobility. The field-effect mobility will be lower when there is trapped charge, due to the way that the field-effect mobility is calculated.

Fig. 2. Comparison of (a) the field-effect mobility measured from Id-Vgs curves, and (b) the Hall mobility. The field-effect mobility will be lower when there is trapped charge, due to the way that the field-effect mobility is calculated.

The Coulomb limiting values have been extracted as discussed above, shown by green dots and fit empirically using a logarithmic function of Eeff  (maintaining a power law function of Ns). The data can be fit nicely using almost the same surface phonon scattering term as used by others [4,5], with a slightly lessened effect of surface roughness, which is process-dependent. For each sample, the Coulomb scattering term is obtained as described above, and is different for each p-well doping.

Figure 6 shows the effect of these scattering mechanisms on the samples with different doping concentrations. The values of μPh and μSR used are identical for all samples; however, the values of μBulk  and μC change due to doping. We observe that the μC drops with increasing p-well concentration. This holds for a fixed temperature; all data shown is at room temperature. The data overall indicates that for these samples, at low Vgs near Vt and above, Coulomb scattering effects limit the channel mobility. This is not surprising due to the high NIT  measured directly from these gated Hall devices. At higher Vgs values surface phonon effects dominate for samples with doping <2×1018 cm−3. Only at Vgs or Eeff  values above typical use values, or for samples with doping much higher than 2×1018 cm−3, do surface roughness effects come into play for these samples.

[picture]

Fig. 3. Split C-V from G to S-D with Base grounded. Frequency is low ( 5 kHz ) to measure most of the interface charge.

Fig. 3. Split C-V from G to S-D with Base grounded. Frequency is low ( 5 kHz ) to measure most of the interface charge.

[picture]

Fig. 4. Calculated trap levels ntrap  from the measured Hall free carriers and ideal charge ntotal . Doping has only a small effect on ntrap  levels.

Fig. 4. Calculated trap levels n trap from the measured Hall free carriers and ideal charge n total . Doping has only a small effect on n trap levels.

[picture]

Fig. 5. Graph showing how the Coulomb scattering effects ( μC ) can be obtained from the measured Hall mobility, fixing the terms for bulk, surface phonon, and surface roughness.

Fig. 5. Graph showing how the Coulomb scattering effects ( μ C ) can be obtained from the measured Hall mobility, fixing the terms for bulk, surface phonon, and surface roughness.

[picture]

Fig. 6. Graph showing how the mobility limiting terms affect all doping levels, and how the mobility limiting effects are Eeff  dependent.

Fig. 6. Graph showing how the mobility limiting terms affect all doping levels, and how the mobility limiting effects are E eff dependent.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

Gated Hall measurements of Si -face 4H−SiC MOSFETs with NO -annealed thermal gate oxide show clearly that Coulomb and surface phonon effects dominate in limiting the channel mobility at low and medium Vgs or Eeff values. Surface roughness effects are minimal in these samples and are only observed to limit the channel mobility at very high Vgs or Eeff  values, or for samples with doping levels much higher than 2×1018 cm−3. The high interface trap density is the main mobility limiting effect (Coulomb effects) that could be improved if the interface passivation were improved or near interface oxide traps were reduced.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.1.pdf

G.Y. Chung, C.C. Tin, J.R. Williams, K. McDonald, R.K. Chanana, R.A. Weller, S.T. Pantelides, L.C. Feldman, O.W. Holland, M.K. Das, J.W. Palmour, IEEE Elec. Dev. Lett. 22 (2001) pp. 176-178.

D.J. Lichtenwalner, S. Ryu, B. Hull, S. Allen, and J.W. Palmour, Materials Science Forum Vol. 1090 (2022) pp 93-100.

H. Naik and T.P. Chow, Materials Science Forum Vols. 679-680 (2011) pp 633-636.

T. Ohashi, Y. Nakabayashi, and R. Iijima, IEEE Trans. Elec. Dev. Vol. 65 (2018) pp. 27072713.

M. Noguchi, T. Iwamatsu, H. Amishiro, H. Watanabe, N. Miura, K. Kita, and S. Yamakawa, Jpn. J. Appl. Phys. Vol. 58, 031004 (2019).

S. Das, Y. Zheng, A. Ahyi, M.A. Kuroda and S. Dhar, MDPI Materials, Vol. 15 (2022) pp.19-25.

S. Das, D.J. Lichtenwalner, S.R. Stein and S. Ryu, ICSCRM 2024 Raleigh NC (in press).

J. Lindemuth, Hall Effect Measurement Handbook, Lakeshore Cryotronics, Inc. ISBN 978-1-73470-780-9, ed. B. Dodrill (2020).

S. Takagi et al., IEEE Trans. Electron Dev. 41 (1994) pp. 2357-2362.

S. Potbhare, N. Goldsman, G. Pennington, A. Lelis, and J.M. McGarrity, J. Appl. Phys. 100, 044515 (2006).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 7-12

doi: 10.4028/p-h2cCpq

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-29

Revised:
2025-12-08

Accepted:
2026-01-31

Online:
2026-05-21

Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

Andrei Konstantinov 1,a, Shagufta Naureen 1, b, Sergey Reshanov 1,c and Jang-Kwon Lim 2, d*

1 II-VI Kista AB, Electrum-207, 16440 Kista, Sweden

2 RISE AB, Electrum-236, 16440 Kista, Sweden

a Andrei.Konstantinov@cohetent.com, b Shagufta.Naureen@coherent.com, c  Sergey.Reshanov@cohenent.com, d* * Jang-Kwon.Lim@ri.se

*corresponding author

Abstract

Visible light emission was observed for negative-bias gate stress of n -channel power MOSFETs in 4H−SiC. The emission intensity is approximately proportional to the current through the gate oxide; and its pattern follows the configuration of active MOSFET channels. We relate the emission to recombination of the electrons injected from the gate into the oxide with valence-band holes from SiC at the surface states at the SiC -to-oxide interface. The gate leakage imaging technique may be helpful for locating different types of gate oxide current crowding, which crowding might cause enhanced wear-out of the gates and early device failure.

Keywords: 4H−SiC,SiC−MOSFET, gate stress, gate leakage.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

Reliability of gate oxides in silicon carbide power MOSFETs has significantly improved in recent years. However, it might take further effort to reach the same reliability level as that offered by silicon power devices. A significant roadblock comes from limited set of available efficient tools. Reliability-related device development techniques are often based on statistical analysis of failures under lengthy stress. An option for direct imaging the gate leakage could enhance development of reliable SiC MOSFETs. In this work we demonstrate a prospective approach based on imaging visible light emission from the gate oxide interface to SiC under negative bias gate stress conditions.

Visible light emission from the interface of gate oxide to SiC was first reported for lateral SiC MOSFETs by Macfarlane and Stahlbush from the NRL [1,2], who employed pulsed gate biasing to form an inversion channel with subsequent release of the interface-trapped electron charge. This excitation technique is similar to well-known charge pumping. Depending on the voltages of high and low gate-bias levels, visible light emission spectra correspond to either bulk recombination in SiC or to recombination at the oxide interface states. A recent series of spectral and imaging studies applied the Macfarlane-Stahlbush technique to SiC power MOSFETs; which summary can be found in [3].

In this study we report visible light emission upon negative and positive gate bias stress; we discuss emission mechanisms and potential practical applications of gate current imaging.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

Power MOSFET wafers were processed at a foundry with a target rated voltage of 1200 V . The MOS-channels were formed by thermal oxidation, which was followed by a nitridation anneal and by a deposition of polysilicon gates. Imaging analysis was done after removing the backside contact to observe the emission through the SiC crystal using an inverted microscope with a cooled panchromatic CCD camera from Hamamatsu. Negative gate-to-source bias was applied to maintain a gate current of 100μ A. Low-magnification ( 2× objective) emission image of a power MOSFET displayed in Fig. 1(a) shows a fairly uniform gate current density. No emission comes from the gate
pad or from the gate runner. The CCD readouts were proportional to the gate current for the same exposure time. High-magnification ( 40× objective) image shown in Fig. 1(b) reveals certain details of the active structure of the device.

[picture]

Fig. 1. Backside-imaged power MOSFET emission for negative-bias gate stress at a gate current of 100μ A at low (a) and high magnification (b).

Fig. 1. Backside-imaged power MOSFET emission for negative-bias gate stress at a gate current of 100 μ A at low (a) and high magnification (b).

In order to locate the regions of peak light emission, reflected-light micrograph was taken through the wafer backside. Backside reflected light image of Fig. 2(a) is complemented by two aligned inserts, showing the polysilicon gate outline and the gate emission. The peak light intensity follows the outline of the p-wells, although some emission also comes from the regions above vertical n-JFETs. Those regions are shown on a schematic cross-section in Fig. 2(b). Certain nonuniformity of emission is observed at microscopic-scale, which origin is yet unclear; it might come from step bunching of the SiC surface, or from process-related fluctuations of the p-well width.

[picture]

Fig. 2. Backside-imaged reflection micrograph with aligned insets for gate polysilicon configuration and for emission (a) and the cross-section of MOSFET unit cell (b); and positive gatebias emission image for gate current of 200μ A (c).

Fig. 2. Backside-imaged reflection micrograph with aligned insets for gate polysilicon configuration and for emission (a) and the cross-section of MOSFET unit cell (b); and positive gatebias emission image for gate current of 200 μ A (c).

Light emission was also observed for a positive gate bias, however, its intensity was much weaker than for the negative gate polarity. Shown in Fig. 2(c) is a medium-magnification ( 10× objective) image for a positive-bias at gate current of 200μ A. The CCD readout for a negative gate bias at 100μ A were 25 times higher with the same objective, implying a 50× higher emission yield per charge carrier passed through the gate oxide. At high magnification ( 40× objective) the image quality was very poor due to too low light intensity.

We made a comparison of the stress-induced emission with that due to the charge-pumping using the conditions reported by Macfarlane and Stahlbush [1]. A square-wave gate-to-source bias with high and low levels of +8 V and -8 V respectively was applied to the MOSFET gate with the source grounded. Alternating gate polarity results in a recombination of free carriers of the gateinduced channel with the opposite-polarity charge trapped at the surface states during the preceding half-period. Light emission could be recorded even with a relatively low pulse frequency of 100 kHz . Negative-bias stress was done after the charge pumping to compare the pattern of light emission between the two techniques. High negative DC bias was applied to the gate of a test MOSFET to drive the same current density as that used for imaging a large area power MOSFET.

[picture]

Fig. 3. Emission of a small-area test MOSFET under charge pumping (a), under negative-bias stress (b), and partial overlay of the two emission images (c).

Fig. 3. Emission of a small-area test MOSFET under charge pumping (a), under negative-bias stress (b), and partial overlay of the two emission images (c).

Emission images of a small-area test MOSFET are shown in Fig. 3. The active region of the test MOSFET followed the same design rules as the high-power MOSFET. Fig. 3(a) corresponds to the charge pumping mode, and emission is assigned red color. Emission image for the negative-bias stress is shown in Fig. 3(b). A partial overlay of the two emission images is shown in Fig. 3(c), in which portions of emission in Figs. 3(a) and 3(b) were electronically removed to leave an overlay in the central area only. The charge pumping yields more uniform emission with no enhancement in the p-well regions. It is also not as grainy as that from DC stress. Overall configuration is identical; both types of emission come from the MOSFET p-wells and from the vertical JFETs.

We will now discuss the light emission mechanism. Shown in Fig. 4(a) is the band alignment of the MOSFET under the conditions of negative-bias gate stress. High-field carrier transport in silicon dioxide is governed by conduction-band electrons, which are driven by electric field from the gate to towards the interface to SiC . The holes of the SiC valence band are driven to the same interface, at which point they recombine with the electrons. Recombination results in light emission from the same interface traps as that for the charge-pumping studied in [1-3].

[picture]

Fig. 4. Electron band diagram for negative-bias gate stress (a), gate-to-source electrical characteristics (b).

Fig. 4. Electron band diagram for negative-bias gate stress (a), gate-to-source electrical characteristics (b).

The dependence of gate current on absolute value of gate-to-source bias is plotted in Fig. 4(b) for positive and negative gate bias conditions. High negative gate bias results in a very strong charging of the oxide interface, as is seen in Fig. 4(b): prolonged negative bias results in a voltage shift of 10-20 Volt. Such interface charging is quite typical for the negative-bias SiC MOSFET stress as was reported in multiple publications [4,5]. The positive charge captured at or next to the interface can often be neutralized by positive gate bias, however high and/or prolonged negative gate bias may result in a permanent shift of the threshold voltage of the MOSFET.

[picture]

Fig. 5. Electron band diagram for positive-bias gate stress (a), and the fraction of holes in total oxide current for silicon and SiC for positive-bias gate stress (b).

Fig. 5. Electron band diagram for positive-bias gate stress (a), and the fraction of holes in total oxide current for silicon and SiC for positive-bias gate stress (b).

For positive gate polarity the charge trapping is not as pronounced. Electrical characteristics are in this case governed by electron tunneling from the surface accumulation or inversion layer in SiC to the oxide. The carriers that tunneled though the barrier travel over the oxide to the gate, and this process should not cause any light emission unless some holes are generated on the path. Such generation of holes is well-known for silicon MOSFETs at very high electric fields in the oxide. Its dominant mechanism is related to impact ionization by hot electrons in the oxide at the anode [6], as shown schematically in Fig. 5(a).

In silicon MOSFET technology, holes generated in the gate oxide are often measured using a charge separation experiment, which utilizes a lateral n-channel MOSFET on a p-type substrate. Weineberg et al. [7] detected the generation of holes in the oxide by measuring the p-substrate current of a planar n-MOSFET at positive bias at the gate. The substrate current is zero if no ionization events occur in the oxide or next to the anode. The substrate current shows up as the gate-to source bias is increased to cause ionization. Plotted in Fig. 5(b) are the data of Weinberg et al. [7] for hole generation in silicon MOSFETs as a function of the gate current density and oxide thickness. A similar charge separation experiment was reported for 4H−SiC by Sometani et al. [8], the data of which are also plotted in the figure. The power MOSFET is not suitable for charge separation because the p-bodies are shorted to the source. It is nevertheless possible to roughly estimate the hole current fraction from the ratio of emission efficiency for positive and negative gate bias conditions, which number is around 0.02 , as discussed above. This data point shown in Fig. 5(b) is in reasonable agreement with published results of charge separation experiments for silicon and for SiC .

Early gate leakage of a power MOSFET represents a significant reliability issue, especially if the gate current is highly localized. Gate-oxide current flow in a power MOSFET may result in wear-out of the oxide, which wear-out rate is governed by the current density. Inspection of MOSFET electroluminescence due to gate stress might therefore be a useful means of detecting crowding of the gate current, which may cause early failure. An example image from examination of a problematic design using this technique is shown in Fig. 6. The MOSFET sample under study was obtained from an external vendor. Fig. 6(a) shows a low-magnification emission image under negative gate-to-source bias for a portion of high-power MOSFET. No emission occurs from the gate pad, which is physically in the bottom part of the image. Regions of very strong emission are observed around the periphery of the active region. High-magnification emission image of the left bottom corner is shown in the insert to Fig. 6(a).

The ledged region of bright emission in the chip corner coincides with a pattern, observed through the substrate in reflected light, Fig. 5(b). Marked with a dashed line is the edge of the gate poly that yields a lighter tone due to reflection. The small dark squares are the locations of Ohmic
contacts. The gate intersects a ledged pattern, which appears to be an imprint of the mask used for subcontact p+ implant. Heavy p -type doping of this ledged region is confirmed by SEM inspection that was done after removing all metals and dielectrics from the top side of the SiC MOSFET chip. The potential-contrast SEM image in Fig. 6(c) indeed shows high p-type doping in the ledged region, which brighter tone corresponds to high p -type doping. Similar gate overlaps with p+ were found next to the gate pad and to the gate runner in the middle part of the device, Fig. 6(a).

[picture]

Fig. 6. Images of a MOSFET from external vendor in electroluminescence (a), in backside-reflected light (b), and in potential-contrast SEM (c).

Fig. 6. Images of a MOSFET from external vendor in electroluminescence (a), in backside-reflected light (b), and in potential-contrast SEM (c).

Crowding of the gate current in the power MOSFET shown in Fig. 6 therefore occurs due to overlapping of the gate oxide with a heavily doped p-type region. Heavily doped p-type SiC has a lower barrier to hole injection into the oxide than the p-well or the n-type JFET. Deterioration of oxide quality due to heavy p-type doping might also contribute to gate current crowding.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

To summarize, we demonstrated the feasibility of imaging the gate leakage pattern in a vertical 4H-SiC power MOSFET using a negative-bias gate stress. For devices having nearly uniform flow of the gate current, the emission occurs from the p-wells and from the vertical JFETs of the MOSFET structure. The emission mechanism is believed to be similar to the light emission due to charge pumping [1-3]; it is related to recombination of electrons and holes at the traps at oxide-SiC interface. Electrons passing though the oxide recombine with valence-band holes from SiC at the interface states. The new imaging technique provides a straightforward means of detecting weak spots of the gate oxide having high density of leakage current, which weak spots may compromise device reliability.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.7.pdf

P. J. Macfarlane, and R. E. Stahlbush, "Characterization of light emission from 4H and 6H SiC MOSFETs," MRS Online Proceedings Library 640, 49 (2000).

R. E. Stahlbush, P. J. Macfarlane, J. R. Williams, G. Y. Chung, L. C. Feldman, K. McDonald, "Light emission from 4H SiC MOSFETs with and without NO passivation," Microelectronic engineering, 59 (2001), pp. 393-398.

M. W. Feil, H. Reisinger, A. Kabakow, et al., "Electrically stimulated optical spectroscopy of interface defects in wide-bandgap field-effect transistors," Communications Engineering 2, 5 (2023).

L. Anoldo, E. Zanetti, W. Coco, A. Russo, P. Fiorenza, and F. Roccaforte, "4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses". Materials, 17(8), 1908 (2024).

T. Liu, S. Zhu, S. Yu, et al., "Gate Leakage Current and Time-Dependent Dielectric Breakdown Measurements of Commercial 1.2 kV 4H-SiC Power MOSFETs," 2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Raleigh, NC, USA, 2019, pp. 195-199.

D. J. DiMaria, E. Cartier, D. A. Buchanan, "Anode hole injection and trapping in silicon dioxide," Journal of Applied Physics, 80 (1996), pp. 304-317.

Z. A. Weinberg, M. V. Fischetti, "Investigation of the -induced substrate current in silicon field-effect transistors," Journal of Applied Physics, 57 (1985), pp. 443-452.

M. Sometani, D. Okamoto, S. Harada, et al., "Temperature-dependent analysis of conduction mechanism of leakage current in thermally grown oxide on ," Journal of Applied Physics, 117, 024505 (2015).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 13-17

doi: 10.4028/p-0rgVLc

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-05

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-21

Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

Yang Liu 1,a*, Lei Yuan 1, b*, Xuesong Liu 2,c, Tongxiao Hou 2, d, Bo Peng 1,e, Renxu Jia 1,f and Yuming Zhang 1, g

1 Faculty of Integrated Circuit, Xidian University, Xi'an 710071, China

2 Beijing BJAST Holdings Co., Ltd., Beijing, China

a*23111110095@stu.xidian.edu.cn, b  yuanlei@xidian.edu.cn, c  xs6721@126.com,

d  644988605@qq.com, eboopeng@xidian.edu.cn, f  rxjia@mail.xidian.edu.cn, ²  zhangym@xidian.edu.cn

Keywords: bipolar phototransistor, ultraviolet, far-UVC detection.

Abstract

The far-UVC band ( 200−240 nm ) is highly attractive for germicidal and solar-blind detection. To address limited surface carrier collection in epitaxial SiC phototransistors, we designed fully ion-implanted lateral phototransistors by combining transistor physics with CMOS-compatible processing. The lateral base width was systematically varied from 1 to 8μ m to investigate its influence on carrier transport and gain. A narrower base significantly enhanced photocurrent amplification, with the 1μ m device reaching 100.7 A/W at 200 nm and 60.0 A/W at 240 nm , while maintaining amplification up to the ~380 nm cutoff. Moreover, dark currents remained as low as 10−11 A, confirming the advantage of structural engineering for high-performance far-UVC SiC phototransistors.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

Applications such as astronomical detection, biomedical imaging, and solar-blind communication demand highly efficient ultraviolet detectors operating in the Far-UVC band [1-3]. Silicon carbide (SiC), owing to its wide bandgap, inherently possesses wavelength selectivity for ultraviolet detection. Moreover, its low intrinsic carrier concentration enables photodetectors fabricated from this material to exhibit exceptionally low dark current levels. Beyond these advantages, highperformance UV detectors are also expected to demonstrate excellent responsivity, that is, the capability to amplify weak optical signals. In this respect, bipolar phototransistors (BPTs) and avalanche photodiodes (APDs) offer significant benefits over conventional photodiodes, metal-semiconductor-metal (MSM) detectors, and other similar device architectures. While APDs are particularly suited for ultra-high-sensitivity detection, phototransistors present advantages in terms of compatibility with integrated design and operation under low bias voltages.

SiC epitaxial technology is comparatively mature and cost-effective, making it a long-standing preferred choice for fabricating not only photodetectors but also power and compact electronic devices. Numerous research groups have successfully demonstrated SiC-based bipolar phototransistors employing multiple epitaxial growth steps. However, from the perspective of quantum efficiency, these devices still struggle to achieve effective optical signal amplification [46]. With the advancement of SiC device technology, ion implantation has been increasingly adopted in device fabrication, gradually narrowing the gap between ion-implanted photodetectors and their epitaxial counterparts [7].

In this work, we report for the first time the design and implementation of several ion-implanted phototransistor architectures realized through CMOS-compatible processes. We provide a comprehensive evaluation of their optoelectronic performance, including dark current density, responsivity, quantum efficiency, and detectivity, and further elucidate how device structure influences these parameters.

This class of detectors effectively overcomes the long-standing limitation of SiC phototransistors in achieving practical optical signal amplification, while simultaneously revealing a set of effective design guidelines for the structural optimization of SiC-based phototransistors.

Device Structure and Process Design Based on Phototransistor Operation

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

The operating principle of a bipolar phototransistor relies on the separation of photon-generated electron-hole pairs by the reverse-biased base-collector (BC) junction. Under the influence of the electric field, holes drift into the base region. The accumulation of holes raises the base potential at the base-emitter (BE) junction, driving it into forward bias. This, in turn, facilitates electron injection from the emitter into the base, thereby realizing bipolar amplification. Consequently, the BC junction must sustain a stable photocurrent to ensure effective forward biasing of the BE junction. Once the concentration of separated holes is insufficient to maintain this condition, the device can no longer operate in the amplification mode.

In epitaxially grown structures, this limitation is often observed due to the exponential attenuation of photons within semiconductors, with the penetration depth strongly dependent on wavelength. For materials such as silicon operating in the infrared regime, the photon penetration depth can extend to several hundred micrometers. Hence, in Si-based infrared detectors, strategies such as stacking multiple epitaxial layers and extending the space-charge region are commonly employed to maximize photon absorption and collection [8]. In contrast, the design logic for ultraviolet detection is fundamentally different. For instance, at a wavelength of 244 nm , the penetration depth in SiC is only about 0.7μ m [9]. As a result, when the depth of the epitaxially formed space-charge region approaches or falls below this value, only a negligible fraction of photons can reach the reverse-biased depletion region. The correspondingly scarce hole population generated in this case is insufficient to maintain forward amplification in the phototransistor.

However, phototransistor structures formed by ion implantation can effectively address this issue. In this case, photons can directly reach the surface depletion region without significant attenuation, thereby substantially increasing the photocurrent generated at the base-collector (BC) junction and making it easier for the phototransistor to enter the amplification regime. Although this concept holds clear advantages in principle, several process-related considerations require special attention.

[picture]

Fig. 1. (a) Top-view optical micrograph; (b) Schematic diagram of the device structure (half unit); (c) The relationship between incident optical power density and wavelength used during the testing process.

Fig. 1. (a) Top-view optical micrograph; (b) Schematic diagram of the device structure (half unit); (c) The relationship between incident optical power density and wavelength used during the testing process.

First, in a conventional ion-implanted BJT structure, the BC buried junction is typically located relatively deep inside the substrate. To mitigate this, we attempt to utilize the N-type region within the P-well as the collector, while designating the epitaxial layer as the emitter. Second, because the near-surface BC junction generates a large photocurrent, amplification must also be achieved through a surface BJT configuration. Consequently, the design focus shifts from realizing a vertically thinbase BJT via implantation energy to constructing a laterally narrow-base BJT. On this basis, we fabricated four types of phototransistors with lateral base widths of 1,2,4, and 8μ m, respectively. Third, the surface oxide inevitably contains a certain amount of fixed charges, which may influence
surface recombination and leakage current [10,11]. To minimize such effects, we employed the highest-quality oxide deposition process available to us, avoiding wet oxidation techniques that are prone to introducing large densities of interface charges. In summary, the actual device structure of our designed phototransistor is illustrated in Fig. 1.

Test Methods and the Impact of Lateral Base Width Variation on Device Performance

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

The electrical characteristics of the devices were measured using a Keysight B1500A semiconductor parameter analyzer. Optical excitation was provided by an EQ-77 white light source driven by a laser, with the output wavelength selected through a monochromator. The optical power incident on the device was controlled by adjusting the distance ( d1−d4 ) between the optical fiber and the sample, as illustrated in Fig. 1c. The corresponding optical power density was calibrated using a commercial Si-based photodetector (Zolix OPE-B3-UV), which had been previously calibrated by the National Institute of Metrology, China, to ensure measurement accuracy.

The dark current characteristics and the comparison of dark current density are shown in Fig. 2. It can be observed that the four devices exhibit generally consistent trends, with slight variations in the absolute magnitude of the dark current. Specifically, when the applied bias is below 4 V , the dark current remains relatively low, but increases significantly once the bias exceeds this threshold. This behavior can be attributed to base punch-through: under reverse bias of the BC junction, the collector is a heavily doped region. As the applied bias increases, the depletion region extends deeply into the base and rapidly connects with the depletion region of the BE junction, resulting in a sharp increase in current. This phenomenon is a direct consequence of swapping the emitter and collector roles in the device design. Within the bias range below 4 V , the dark current densities of the four devices show minimal differences, all close to the measurement limit ( 10−10−10−11 A ). The slightly higher dark current in the device with a 1μ m lateral spacing is mainly attributed to the enhanced tunneling current caused by the abrupt doping gradient across the short distance [12], whereas increasing the spacing to 2μ m effectively suppresses this effect.

[picture]

Fig. 2. Dark current characteristics for different CE spacings and bias.

Fig. 2. Dark current characteristics for different CE spacings and bias.

The responsivity comparison and variation trends are illustrated in Fig. 3. First, under identical optical power density and excitation wavelength, the responsivity increases as the lateral base width decreases. In particular, devices with 2−8μ m base widths exhibit a significant reduction in responsivity compared to the 1μ m device. This can be explained by the fact that a narrower base width in the surface BJT enables more effective amplification. It can be anticipated that base widths around 1μ m or even smaller could deliver stronger amplification; however, such scaling introduces a trade-off with the punch-through effect under operating bias, as discussed previously. Moreover,
the difference in responsivity is more pronounced at 200 nm compared to 280 nm excitation (Fig. 3b and 3c).

Second, for the same device under identical wavelength excitation but varying optical power densities, it is clearly observed that responsivity increases as the optical power density decreases ( d 1 to d4). This result indicates that the near-surface BJT structure is more favorable for weak light detection.

Third, under constant optical power density but different excitation wavelengths, the responsivity at 200 nm is generally higher than at longer wavelengths. This suggests that the device is particularly well-suited for short-wavelength detection in the far-UVC region, as the shallower penetration depth of shorter-wavelength photons allows them to be more effectively absorbed and utilized by the surface BJT structure.

[picture]

Fig. 3. (a) Spectral response under varying collector-emitter (CE) spacings. (b-d): Responsivity comparison of different UV light excitation.

Fig. 3. (a) Spectral response under varying collector-emitter (CE) spacings. (b-d): Responsivity comparison of different UV light excitation.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

The key performance metrics of the devices under 200 nm illumination are summarized in Table 1. It can be seen that under low-light conditions, the device with a collector-emitter spacing ( dce ) of 1μ m achieves a detectivity ( D* ) of 33.4×1013 Jones, whereas under high illumination intensities, the device with dce=2μ m exhibits better detectivity. The responsivity of the 1μ m device reaches 100.7 A/W at 200 nm and 60.0 A/W at 240 nm , and photocurrent amplification is maintained across the entire spectral range up to the cutoff wavelength of approximately 380 nm .

Table I. Comparison of Key Parameters of Different PTs under 200 nm UV Illumination.

These results collectively demonstrate that careful optimization of the device structure, particularly the lateral base width, plays a critical role in balancing responsivity, dark current, and detectivity in ion-implanted SiC phototransistors. Our study provides important insights for the future design of high-performance photodetectors targeting the far-UVC spectral region.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.13.pdf

Li, Jiaqi, Zhou, Yue, Yi, Xiangyu, et al., Current Optics and Photonics 1, 196-202 (2017).

G. Wang, K. Wang, C. Gong, et al., IEEE Photonics J. 10, 1-13 (2018).

D. Guo, Y. Su, H. Shi, et al., ACS Nano 12, 12827-12835 (2018).

Y. Wang, W. Li, W. Xu, et al., IEEE Electron Device Lett. 45, 617-620 (2024).

Y. Wang, W. Li, D. Zhou, et al., IEEE Trans. Electron Devices 1-8 (2022).

C. Sun, H. Guo, L. Yuan, et al., IEEE Trans. Electron Devices 70, 2342-2346 (2023).

C. D. Matthus, T. Erlbacher, A. J. Bauer, et al., "Comparative Study of UV-Sensors with Ion Implanted and Epitaxially Grown p-Emitter," in 2018 22nd International Conference on Ion Implantation Technology (IIT) (IEEE, 2018), pp. 110-113.

R. Cariou, J. Benick, F. Feldmann, et al., Nat Energy 3, 326-333 (2018).

T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications, 1st ed. (Wiley, 2014).

S. Asada, T. Kimoto, and J. Suda, IEEE Trans. Electron Devices 64, 3016-3018 (2017).

S. Asada, J. Suda, and T. Kimoto, IEEE Trans. Electron Devices 65, 4786-4791 (2018).

G. P. Li, E. Hackbarth, and T.-C. Chen, IEEE Trans. Electron Devices 35, 89-95 (1988).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 19-27

doi: 10.4028/p-6BmS4C

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-15

Accepted:
2026-03-21

Online:
2026-05-21

1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Tommaso Stecconi i1,a*, Roger Stark 1, b, Paula Reigosa 1c, Nick Schneider 1, d, Coris Li2,e, Leon Liang 2,f and Lars Knoll 1, g

1 SwissSEM Technologies AG

Dammweg 23, 5600, Lenzburg, Switzerland

2 Sun.King Pacific Semiconductors Technology(Zhejiang) Co., Ltd

NO. 56 Jinji Road, Huimin Street, Jiashan County, Jiaxing City, Zhejiang Province, 314100, China

a*tommaso.stecconi@swiss-sem.com, broger.stark@swiss-sem.com, c  paula.reigosa@swiss-sem.com, d  nick.schneider@swiss-sem.com, e  coris.li@swiss-sem.com,

Keywords: SiN, high-k, dynamic losses.

Abstract

This paper presents a comprehensive electrical evaluation of a 1.2 kV SiC vertical MOSFET incorporating a novel SiN gate dielectric. Compared to a reference device with thermally grown SiO2, the proposed MOSFET achieves superior static performance and lower dynamic losses. Notably, the reduced losses stem from a lower gate-drain capacitance (CGD). Furthermore, the novel MOSFET demonstrates superior thermal and electrical stability of the threshold voltage. All these findings underscore the potential of higher-k dielectrics to simultaneously optimize both static and dynamic performances in SiC power MOSFETs, paving the way for more efficient high-voltage power switches.

I. Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Crystalline SiC MOSFETs, with their higher thermal conductivity and wider bandgap, deliver superior electrical performance at high frequencies compared to Si-based power switches [1]. However, integrating crystalline SiC as the transistor bulk material introduces notable processing challenges. Specifically, the growth of a SiO2 layer on SiC substrates generates interface and oxide traps, which degrade the device's electrical performance [2]. To mitigate these issues, high-k dielectrics offer a promising alternative by potentially reducing interface trap concentration [3] and improving threshold voltage stability [4]. However, these static-performance gains may come at the cost of degraded gate leakage [5] and lower threshold voltage [6]. Moreover, the impact of the high-k gate dielectric on dynamic performances is not yet fully explored. In this work, we present a novel SiC MOSFET with a SiN gate dielectric that outperforms a reference device with SiO2 gate oxide in both static and dynamic performances.

II. Electrostatic Properties

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Two vertical MOSFET devices, sharing the same process flow, except for the gate-dielectric fabrication, are compared. The first split, labeled as " SiO2 ", features a thermally grown gate-oxide layer in mixed O2 and N2 environment. The second split, labeled as " SiN ", incorporates a SiN gate dielectric layer deposited by Low Pressure Chemical Vapor Deposition (LPCVD). The SiN film is made 62.5% thicker than the SiO2 layer to reduce gate leakage. Fig. 1 shows the input capacitance (Ciss ) vs. gate-source voltage ( VGS ) graph. At VGS=15 V,Ciss  saturates to a value approximately equal to the gate-dielectric capacitance (Cox). We can express Cox as:

Cox=Akε0tox(1)

Where A is the gate area, k is the dielectric constant, ε0 is the permittivity of free space, and tox is the gate dielectric thickness. After taking the ratio of (1), we obtain:

kSiN=1.84·kSiO2,(2)

which aligns well with reported values in literature for Si3 N4 [7].

[picture]

Fig. 1. Area normalized input capacitance ( Ciss,sp  ) of the SiO2 (blue) and SiN (orange) MOSFETs measured as VGs ranges from -3 to 15 V .

Fig. 1. Area normalized input capacitance ( C iss,sp ) of the S i O 2 (blue) and SiN (orange) MOSFETs measured as V G s ranges from -3 to 15 V .

The higher dielectric constant determines a higher Ciss  and hence superior control of the channel carrier density with VGs. This can be observed in Fig. 2 (a), where we plot the subthreshold drain current ( ID ) vs. VGS, under a low drain-source bias (VDS) of 20 mV . We calculate the average inverse subthreshold slope (STS−1) up to VGS=6 V, showing STS −1SiN=660mV/ dec , compared to STS −1SiO2=750mV/ dec. To calculate the threshold voltage ( Vth  ), the Id vs. VGS measurement is repeated on planar MOSFET structures. We extract the transconductance (gm), defined as:

gm=ΔIDSΔVGS(3)

and we trace the x -axis intercept of the ID/(gm)1/2 curves, as outlined by the method [8].

[picture]

Fig. 2. (a) Subthreshold Id-VGS characteristics of the SiO2 (blue) and the SiN (orange) MOSFETs, measured at VDS=20mV. The average inverse subthreshold slope (STS−1) values are displayed in the graph. (b) Transconductance ( gm ) of both devices, measured at VDS=10 V while sweeping VGS from 0 to 15 V .

Fig. 2. (a) Subthreshold Id-VGS characteristics of the S i O 2 (blue) and the SiN (orange) MOSFETs, measured at V D S = 20 m V . The average inverse subthreshold slope ( S T S − 1 ) values are displayed in the graph. (b) Transconductance ( g m ) of both devices, measured at V D S = 10 V while sweeping VGS from 0 to 15 V .

We obtain Vth SiN=6.9 V and Vth SiO2=6.7 V, demonstrating a higher- k MOSFET with higher threshold voltage than the SiO2 reference. In Fig. 2 (b), the gm of the vertical MOSFETs is compared in the highpower regime under VDS=10 V, with VGS swept from 0 to 15 V . The SiN MOSFET exhibits an 11% higher peak gm value, determined by the higher CoxSiN.
In Fig. 3, the voltage hysteresis ( ΔVhyst  ) of the two splits is compared using bidirectional VGS sweeps at VDS=20mV. The SiO2 and SiN splits exhibit ΔVhyst =31 and ΔVhyst =17mV, respectively, indicating improved turn-on/turn-off switching stability with the novel SiN gate dielectric.
Fig. 4 benchmarks the static performance of our SiC devices, including our baseline product "m23", against three competing 13 mΩ,1.2kV-rated SiC MOSFETs. The x-axis represents the Vas values measured by forcing a 10 mA current under the VGD=0 V condition (Vth ,10 mA). The y -axis shows the on-state resistance values extracted at VGS=18 V for ID, on =100 A ( RDS, on  ).

[picture]

Fig. 3. Voltage hysteresis ( ΔVhyst  ) measured by bidirectional Id-VGs sweeps for currents up to Id,compliance =100 mA, performed at 10 V/s of sweep rate.

Fig. 3. Voltage hysteresis ( Δ V hyst ) measured by bidirectional Id-VGs sweeps for currents up to Id,compliance = 100 m A , performed at 10 V / s of sweep rate.

[picture]

Fig. 4. Y -axis: On-state resistance ( RDS,on ) measured at VGS=18 V and ID,on=100 A. X -axis: Threshold voltage ( Vth ,10 mA ), defined as VGS measured while forcing a 10 mA current with VGD=0 V. The compared splits include our SiO2 (blue), our SiN (orange), our m23 product (green), and three other 1.2 kV -rated, 13 mΩ - commercial MOSFETs (grey). Transparent colors represent cold ( 25∘C ) data, while opaque colors correspond to hot (175∘C) measurements.

Fig. 4. Y -axis: On-state resistance ( R D S , o n ) measured at V G S = 18 V and I D , o n = 100 A . X -axis: Threshold voltage ( V th , 10 m A ), defined as V G S measured while forcing a 10 mA current with V G D = 0 V . The compared splits include our S i O 2 (blue), our SiN (orange), our m 23 product (green), and three other 1.2 kV -rated, 13 m Ω - commercial MOSFETs (grey). Transparent colors represent cold ( 25 ∘ C ) data, while opaque colors correspond to hot ( 175 ∘ C ) measurements.

The results are compelling:

Our vertical MOSFETs achieve the best RDS, on 175∘C, ranging between 21 and 26 mΩ.

Our SiN vertical MOSFET demonstrates superior thermal stability of the threshold voltage ( Vth ,10 mA ), with only a 500 mV shift from 25∘C to 175∘C (all the other samples exhibit approximately a 1 V reduction). The high Vth,10 mA is beneficial for short-circuit-safe-operating-area (SCSOA) capability.

Table I. Summary of the static properties of the SiO2 and the SiN vertical MOSFETs, including blocking performance and gate leakage (IG,leak). The breakdown voltage (BVDS) is defined at ID=250μA with VGS=0 V, while the gate leakage current ( IG, leak  ) is measured at VGS=15 V.

Table I.

III. Dynamic Properties

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

In the MOSFET turn-on and turn-off processes, a large fraction of the switching losses is dissipated during the Miller Plateau phase [9]. At this stage, the speed of the output voltage (VDS) transition is governed by the gate-drain component of the gate capacitance ( CGD ) [9,10].
Fig. 5 shows a simplified model of the MOSFET gate capacitance, highlighting the CGd component in red. Under an applied drain voltage (VD), a depletion region of width wdep forms in the drift region, with:

[picture]

Fig. 5. Gate capacitance model of the vertical MOSFET, highlighting the gate-drain component ( CGD ) in red, which is given by the series combination of Cox,dep  and Cdep. Cox, dep  is determined by the coupling between gate and oxide/semiconductor interface. Cdep  arises from the charge modulation in the JFET and drift region. For increasing Vd voltages, the width of the depleted region (wdep) increases.

Fig. 5. Gate capacitance model of the vertical MOSFET, highlighting the gate-drain component ( C G D ) in red, which is given by the series combination of C ox,dep and C dep. C ox, dep is determined by the coupling between gate and oxide/semiconductor interface. C dep arises from the charge modulation in the JFET and drift region. For increasing V d voltages, the width of the depleted region (wdep) increases.

Cdep=εSiwdep(VD,Cox)[9].(4)

For sufficiently high Vd such that:

VD≫qεSiND2Cox2 [9], (5)

where q is the elementary charge, εSi is the silicon permittivity and ND is the doping concentration, the depletion region width ( wdep ) can be approximated by:

[picture]

Fig. 6. (a) wdep  and (b) Cdep  simulated qualitative trends as functions of VD and gate oxide capacitance, from a nominal Cox value up to ten times higher (10·Cox). Both x - and y -axis are represented in log scale, to highlight the square root dependence to VD. These trends assume sufficiently high VD, as per Eq. (5).

Fig. 6. (a) w dep and (b) C dep simulated qualitative trends as functions of V D and gate oxide capacitance, from a nominal C o x value up to ten times higher ( 10 · C o x ) . Both x - and y -axis are represented in log scale, to highlight the square root dependence to VD. These trends assume sufficiently high V D , as per Eq. (5).

wdep≈2εSiVDqND−εSiCox(6)

From (6), wdep  is proportional to VD, with a correction term equal to −εSiCox.
Fig. 6 (a) illustrates the qualitative trend of the depletion width ( wdep  ) as a function of increasing Vd, under the high VD approximation of Eq. (5). The trends are shown for different gate oxide capacitances, from a nominal Cox value up to ten times nominal ( 10·Cox ). The effect of a higher oxide capacitance is to induce a wider wdep , especially at lower VD voltages. Since the depletion capacitance ( Cdep  ) is inversely proportional to wdep  (Eq. (4)), a higher oxide capacitance results in lower Cdep  values, as depicted in Fig. 6 (b).
Finally, CGd is the series combination of Cox,dep and Cdep , with Cox,dep independent from Vd [9]. Fig. 7 presents the CGD values experimentally measured for a drain-to-gate voltage ( VDG ) swept from 10 to 800 V , for both the SiO2 and the SiN MOSFETs. For Vdg>50 V, CGd shows the same log-log trend as Cdep  from Fig. 6 (b), so, in this range, CGD is mainly determined by the Cdep  term. The SiN split exhibits a 5% lower CGD value on average in the VDG range between 10 to 800 V .
The SiO2 and SiN vertical MOSFETs were assembled on DBC substrates in the half-bridge configuration, comprising of one MOSFET on the high-side and one on the low-side, and measured according to the double-pulse testing (DPT) sequence, as described in [9].

[picture]

Fig. 7. CGD of the SiO2 (blue) and SiN (orange) MOSFETs measured by sweeping the gate-to-drain voltage (VDG) from 10 to 800 V .

Fig. 7. C G D of the S i O 2 (blue) and SiN (orange) MOSFETs measured by sweeping the gate-to-drain voltage (VDG) from 10 to 800 V .

Fig. 8 (top), (center) and (bottom) show the turn-on waveforms at 125∘C of the gate-source voltage (VGS), drain-source voltage (Vds) and drain current (Id), respectively, at a stray inductance (Ls) of 50 nH,RG=40Ω, and 800 V of DC link voltage. Before the Miller Plateau is reached, the SiO2 MOSFET shows a slower dID/dt rate, due to the higher Ciss  value. When the Miller Plateau is reached, the SiN MOSFET shows a faster dVDS/dt rate, due to the lower average CGD from 800 V to few V.
By reducing the RG values, a faster turn-on process is achieved and, consequently, lower dynamic losses. Fig. 9 presents the turn-on switching losses ( Eon ) measured for RG=10,20 and 40Ω. The SiN MOSFET exhibits comparable losses at lower di/dt rates, demonstrating a superior turn-on performance.
Fig. 10 (top), (center) and (bottom) show the turn-off waveforms at 125∘C of the gate-source voltage (VGS), drain-source voltage (VDS) and drain current (Id), respectively, at a stray inductance (Ls) of 50nH,RG=40Ω, and 800 V of DC link voltage. The lower CGD of the SiN MOSFET determines a faster Vds voltage ramp up, which in turns enables an earlier fall of the drain current Id, yielding lower energy losses. For RG=10Ω, large oscillations exceeding 20 V build up at the gate

[picture]

A. Center: VDS turn-on waveform. Bottom: Id turn-on waveform.

Figure 9. A. Center: VDS turn-on waveform. Bottom: Id turn-on waveform.

[picture]

Fig.9. Turn-on dID/dt and switching losses (Eon) for RG=10,20 and 40Ω.

Fig.9. Turn-on d I D / d t and switching losses ( E o n ) for R G = 10 , 20 and 40 Ω .

node (not shown). The peak amplitude of the VGS oscillations ( ΔVGSpeak  ) was measured and plotted in Fig. 11 against the turn-off losses ( Eoff  ), for RG=10,20 and 40Ω. The SiN MOSFET exhibits lower ΔVGSpeak  at lower Eoff, proving a superior turn-off performance. The voltage oscillations observed at the drain node with RG=10Ω are comparable in the two splits: VDS,peak SiO2=995 V and VdS,peak SiN= 1007 V (not shown).

IV. Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

We have presented a 1.2 kV rated vertical SiC MOSFET incorporating a SiN gate dielectric that outperforms a reference device with SiO2 gate oxide in both static and dynamic performances. Notably, the SiN split demonstrates superior STS −1, gm,ΔVhyst ,ΔVth 25→175∘C, while also delivering lower Eon and Eoff losses at comparable switching conditions. The reduced dynamic losses are attributed to the lower gate-drain capacitance ( CGD ) observed with the SiN gate dielectric.

[picture]

Fig. 10. Top: VGS turn-off waveform, from +15 to -5 V , at T=125∘C, using Rg=40Ω and ID,on= 150 A . Center: Vds turn-off waveform. Bottom: Id turn-off waveform.

Fig. 10. Top: V G S turn-off waveform, from +15 to -5 V , at T = 125 ∘ C , using R g = 40 Ω and I D , o n = 150 A . Center: Vds turn-off waveform. Bottom: Id turn-off waveform.

[picture]

Fig. 11. Turn-off oscillations peak amplitude vs. losses ( Eoff  ) for RG=10,20 and 40Ω.

Fig. 11. Turn-off oscillations peak amplitude vs. losses ( E off ) for R G = 10 , 20 and 40 Ω .

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.19.pdf

Baliga, B. Jayant. "Silicon carbide power devices: Progress and future outlook." IEEE Journal of Emerging and Selected Topics in Power Electronics 11.3 (2023): 2400-2411.

Pantelides, Sokrates T., et al. "Si/SiO2 and SiC/SiO2 interfaces for MOSFETs-challenges and advances." Materials science forum. Vol. 527. Trans Tech Publications Ltd, 2006.

Wirths, Stephan, et al. "Vertical power SiC MOSFETs with high-k gate dielectrics and superior threshold voltage stability." 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2020.

Hosoi, Takuji, et al. "Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics." 2012 International Electron Devices Meeting. IEEE, 2012.

T. Hatayama, S. Hino, N. Miura, T. Oomori and E. Tokumitsu, "Remarkable Increase in the Channel Mobility of SiC-MOSFETs by Controlling the Interfacial SiO2 Layer Between Al2O3 and SiC," in IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2041-2045, Aug. 2008, doi: 10.1109/TED.2008.926647.

Arith, F., et al. "Increased mobility in enhancement mode 4 H -SiC MOSFET using a thin SiO 2/Al 2 O 3 gate stack." IEEE Electron Device Letters 39.4 (2018): 564-567.

Lorenz, H., et al. "Characterization of low temperature SiO2 and Si3N4 films deposited by plasma enhanced evaporation." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena 9.2 (1991): 208-214.

Ghibaudo, Gérard. "New method for the extraction of MOSFET parameters." Electronics letters 24.9 (1988): 543-545.

Baliga, B. Jayant. Fundamentals of power semiconductor devices. Springer Science & Business Media, 2010

Stark, Roger, et al. "Accuracy of three interterminal capacitance models for SiC power MOSFETs under fast switching." IEEE Transactions on Power Electronics 36.8 (2021): 93989410.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 29-34

doi: 10.4028/p-IkqQM7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-23

Accepted:
2026-03-08

Online:
2026-05-21

Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

llaria Matacena 1,a*, Luca Maresca 1, b, Alessandro Borghese 1,c, Michele Riccio 1, d, Andrea Irace 1,e, Giovanni Breglio 1,f and Santolo Daliento 1, g

1 Department of Electrical Engineering and Information Technology, University of Naples Federico II, Naples, Italy

ailaria.matacena@unina.it, bluca.maresca@unina.it, calessandro.borghese@unina.it, d michele.riccio@unina.it, e a.irace@unina.it, f breglio@unina.it, g daliento@unina.it

Keywords: capacitance measurements, capacitance peak, transconductance, gate capacitance.

Abstract

SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

SiC MOSFETs are gradually replacing their Si counterparts in various applications, thanks to their higher performance. Besides being a wide bandgap material, SiC also exhibits a higher thermal conductivity [1], supplanting Si in power industry. Although SiC technology has experienced huge progress in last decades, there are some open challenges that have to be addressed. Among them the high defect density at SiC/SiO2 interface is a crucial feature that has to be investigated since it can negatively influence important parameters, such as threshold voltage instability [2], channel mobility [3] and leakage current, affecting the performance of the overall device. Interface traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. Due to the importance of SiC/SiO2 interface defect density [4], several techniques have been investigated to characterize such interface. Among these, the most used methods are based on the measurement of impedance, and more in detail capacitance varying with voltage. These techniques are extensively employed across a wide spectrum of applications, including semiconductor devices and solar cells [5]-[13], as well as batteries [14]. The method is non-destructive and it enables a rapid characterization process. In the literature, most investigations on power devices have focused on MOS structures, where the low-high frequency capacitance technique can be applied [15]-[19]. In such structures, the capacitance response strongly depends on the applied frequency [20], and this dependence provides valuable insight into the nature of defects and traps within the device under test. Specifically, the inversion charge can follow the applied excitation only at sufficiently low frequencies, due to the limited thermal generation of carriers in the depletion region. Consequently, in the inversion regime, the capacitance behavior is primarily governed by the inability of the inversion charge to respond to high-frequency signals. However, this condition is strictly valid for MOS capacitors.

In MOSFETs, the situation differs because, in the inversion region, the channel is replenished with carriers from the Source and Drain. As a result, the capacitance in inversion does not exhibit significant variation between low and high frequency, rendering the low-high frequency method unsuitable for these devices [21]. Therefore, it becomes essential to conduct a precise analysis of the capacitance associated with MOSFETs. This can be achieved using numerical frameworks capable of characterizing the SiC/SiO2 interface properties [22]-[26]. Capacitance measurements are typically
performed at the Gate terminal, with the Drain connected and the Source terminal tied to reference [27]-[29].

In our previous works [25], [30]-[33], we explored non-standard C−V measurement approaches on commercially available planar SiC MOSFETs. In those studies, experimental data were obtained by applying a small-signal AC excitation at the Gate while maintaining a fixed DC bias at the Drain, with the Source grounded. The resulting capacitance revealed an anomalous peak in the inversion region, attributable to both the interface properties and the channel region.

In this work, we investigate the correlation between the capacitance peak observed in the nonclassical C-V characteristics and the transconductance behavior of SiC MOSFETs. To this end, the C−V curves are analyzed under the described measurement configuration, while the derivative of the Id D -V GS  characteristics is evaluated to extract the device transconductance. The experimental findings are confirmed by numerical results obtained using the Sentaurus TCAD environment. The remainder of the paper is organized as follows: the experimental setup is described in the next section, while the TCAD numerical setup is discussed in a separate section. Finally, the main conclusions are summarized in the last section.

Experimental Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

Experimental results are obtained on two different 1.2 kV planar SiC MOSFETs commercially available using the setup shown in Fig. 1i. The presented curves are obtained by measuring the capacitance arising between Gate and Source terminals, while a DC bias is applied to Drain terminal, VDS. The excitation consisted of a DC sweep from -10 V to +10 V with a superimposed small-signal AC component (Fig. 1ii) applied to the Gate of the device under test. A fixed DC bias (Fig. 1iii) was applied to the Drain, while the Source was grounded. The measured Gate capacitance with the Drain biased at fixed positive values is reported as a red line in Fig. 2 for the first device considered. The capacitance exhibits the classical behavior in accumulation and depletion. Conversely, in the inversion region, when Vds ≠0 V, a sharp peak emerges. Capacitance obtained on the other device under test is reported in Fig. 3 in red. In this plot, there a several capacitance curves obtained with increasing Vds. These curves exhibit the same behavior found in Fig. 2. In the inversion region, capacitance shows an unexpected peak whose amplitude increases with higher Vds. In previous studies, the peak profile was attributed to traps located in the channel region beneath the SiC/SiO2 interface [22]. Since interface traps in the channel affect this region physical properties, they have considerable impact on ID−VGS characteristics. Hence for the devices under test, we also measured the transfer characteristics, with the aim of investigating the relation between the capacitance peak and the transconductance behavior. The derivative of the ID−VGS characteristics, i.e. the transconductance, for both the device under tests are reported in Fig. 2 and Fig. 3 as blue curves. Experiments show that the derivative of ID−VGS characteristics, obtained for the same VDS imposed in the C−V measurements, shows a maximum at the same voltage where the capacitance peak occurs, for both studied devices.

[picture]

Fig. 1. i) Experimental setup; ii) applied Gate voltage; iii) applied Drain voltage.

Fig. 1. i) Experimental setup; ii) applied Gate voltage; iii) applied Drain voltage.

[picture]

Fig. 2. Experimental C-V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red line, left y-axis) and corresponding transconductance (blue line, right y -axis).

Fig. 2. Experimental C-V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red line, left y-axis) and corresponding transconductance (blue line, right y -axis).

[picture]

Fig. 3. Experimental C−V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red lines, left y-axis) and corresponding transconductance (blue lines, right y -axis).

Fig. 3. Experimental C − V curves obtained from a commercial device, 1.2 kV SiC MOSFET, with positive Vds (red lines, left y-axis) and corresponding transconductance (blue lines, right y -axis).

Numerical Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

The consistency of the experimental findings was further investigated through numerical simulations carried out within the Synopsys Sentaurus TCAD framework. The simulated device structure is depicted in Fig. 4, where the geometrical layout and material parameters were carefully defined to reproduce the actual device under test. In particular, the channel region was modeled by incorporating reduced carrier mobility and defect-related effects, thus reflecting the physical non-idealities typically observed in this region. To investigate the capacitive response, an AC small-signal analysis was performed under various biasing conditions, with a DC potential applied to the Drain terminal while the Gate voltage was swept across the operating range. This approach enabled the extraction of capacitance characteristics, which are strongly influenced by the transport properties of the channel. The resulting C-V curves are reported in Fig. 5 as red traces for different channel doping values. The numerical current-voltage curves were also obtained in the same circumstances. The obtained derivative of the numerical Id-VGS characteristics is also shown in Fig. 5 in blue. Observing curves in Fig. 5, it is possible to see that the capacitance and transconductance peaks occur at the same voltage. These results demonstrate excellent agreement with the experimental measurements. In particular, the capacitance peak (blue traces), obtained for different sets of channel parameters, appears at the same bias voltage at which the corresponding transconductance (red traces) exhibits its maximum value. Simulation findings indicate that the Cgs peak coincides with the gm maximum in terms of both peak value and corresponding voltage, revealing a strong relation of both parameters in accordance with [34].

[picture]

Fig. 4. Sketch of the TCAD structure. The structure is not to scale.

Fig. 4. Sketch of the TCAD structure. The structure is not to scale.

[picture]

Fig. 5. Numerical C-V curves obtained with a positive VDS (red curves, left y -axis) and corresponding transconductance (blue lines, right y-axis) from structure of Fig. 4.

Fig. 5. Numerical C-V curves obtained with a positive V D S (red curves, left y -axis) and corresponding transconductance (blue lines, right y-axis) from structure of Fig. 4.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

In this work, we performed non-classical C−V measurements on commercially available planar SiC MOSFETs. Experimental results were obtained by measuring the capacitance arising between Gate and Source terminals, while a fixed DC bias is applied to Drain terminal. The capacitance measured in this configuration showed a non-negligible peak. The arising peak appeared more prominent as the applied Drain voltage increases and its shape is related to the traps in the channel region under the SiC/SiO2 interface. Since interface traps in the channel affect this region physical properties, they have considerable impact on ID−VGS characteristics. Hence for the devices under test, transfer characteristics were also measured, with the aim of investigating the relation between the capacitance peak and the transconductance behavior. Experiments showed that the derivative of ID−VGS characteristics, obtained for the same VDS imposed in the C−V measurements, exhibits a maximum at the same voltage where the capacitance peak occurs, for both studied devices. In order to better understand experimental outcomes, a numerical analysis was performed in Sentaurus TCAD environment. Numerical curves presented exhibited the same experimental behavior: the capacitance peak obtained for different channel properties occurs at the same voltage where the transconductance reaches its maximum. This correlation highlights the direct link between the channel transport properties and the observed capacitance behavior, confirming that the adopted characterization technique is directly related to transconductance and it could be able to give information about channel properties.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.29.pdf

B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

C. Raynaud, et al., Comparison of trapping-detrapping properties of mobile charge in alkali contaminated metal-oxide-silicon carbide structures, Applied physics letters 66, no. 18: 23402342, (1995).

D. Peters et al., Investigation of threshold voltage stability of SiC MOSFETs, ISPSD, (2018).

V. V. Afanasev, et al., Intrinsic interface states, physica status solidi (a) 162, no. 1: 321-337, (1997).

Lancellotti, L., Lisi, N., Veneri, P. D., Bobeico, E., Matacena, I., & Guerriero, P. (2019, July). Graphene-on-Silicon solar cells with graphite contacts. In 2019 International Conference on Clean Electrical Power (ICCEP) (pp. 199-203). IEEE.

Gobbo, C., Di Palma, V., Trifiletti, V., Malerba, C., Valentini, M., Matacena, I., ... & Tseberlidis, G. (2023). Effect of the interface on the charge extraction in Cd -free kesterite solar cells. Energies, 16(10), 4137.

Sonnet, A. M., Hinkle, C. L., Heh, D., Bersuker, G., & Vogel, E. M. (2010). Impact of semiconductor and interface-state capacitance on metal/high-k/GaAs capacitance-voltage characteristics. IEEE transactions on electron devices, 57(10), 2599-2606.

Lancellotti, L., Bobeico, E., Della Noce, M., Veneri, P. D., & Matacena, I. (2018, June). Work function determination of transparent contact for a: -Si heterojunction solar cells. In 2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC/I&CPS Europe) (pp. 1-5). IEEE.

Matacena, I., Guerriero, P., Lancellotti, L., Alfano, B., De Maria, A., La Ferrara, V., ... & Daliento, S. (2023). Impedance spectroscopy analysis of perovskite solar cell stability. Energies, 16(13), 4951.

Westerhoff, U., Kurbach, K., Lienesch, F., & Kurrat, M. (2016). Analysis of lithium-ion battery models based on electrochemical impedance spectroscopy. Energy Technology, 4(12), 16201630.

Matacena, I., Lancellotti, L., Daliento, S., Alfano, B., De Maria, A., La Ferrara, V., ... & Guerriero, P. (2023). Impedance Spectroscopy of Perovskite Solar Cells With SnO 2 Embedding Graphene Nanoplatelets. IEEE Journal of Photovoltaics.

Turut, A. (2020). On current-voltage and capacitance-voltage characteristics of metalsemiconductor contacts. Turkish Journal of Physics, 44(4), 302-347.

Matacena, I., et al. "Capacitance-Voltage Investigation of Encapsulated Graphene/Silicon Solar Cells." IEEE Transactions on Electron Devices (2023).

Gaberšček, M. (2022). Impedance spectroscopy of battery cells: Theory versus experiment. Current Opinion in Electrochemistry, 32, 100917.

Chang, Yao-Wen, et al. "Charge-based capacitance measurement for bias-dependent capacitance." IEEE Electron Device Letters 27.5 (2006): 390-392.

Almora, Osbel, et al. "On Mott-Schottky analysis interpretation of capacitance measurements in organometal perovskite solar cells." Applied Physics Letters 109.17 (2016).

Gobbo, Carla, et al. "Effect of the interface on the charge extraction in Cd -free kesterite solar cells." Energies 16.10 (2023): 4137.

Matacena, Ilaria, et al. "Forward bias capacitance investigation as a powerful tool to monitor graphene/silicon interfaces." Solar Energy 226 (2021): 1-8.

Heerens, W-C. "Application of capacitance techniques in sensor design." Journal of physics E: Scientific instruments 19.11 (1986): 897.

Schroder, D.K. Semiconductor Material and Device Characterization, 3rd ed.; Wiley: Hoboken, NJ, USA, 2006.

Hu, Chenming Calvin. "Modern Semiconductor Devices for Integrated Circuits." Part I: Electrons and holes in a semiconductor (2011).

I. Matacena, L. Maresca, M. Riccio, A. Irace, G. Breglio, S. Daliento, & A. Castellazzi, (2022). SiC MOSFET CV Characteristics with Positive Biased Drain. In Materials Science Forum (Vol. 1062, pp. 653-657). Trans Tech Publications Ltd.

L. Maresca et al. Influence of the MOSFET Interface Traps Distribution on C V Measurements Evaluated by TCAD Simulations. IEEE Journal of Emerging and Selected Topics in Power Electronics 9.2 (2019): 2171-2179.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2022, June). Experimental Analysis of CV and IV Curves Hysteresis in SiC MOSFETs. In Materials Science Forum (Vol. 1062, pp. 669-675). Trans Tech Publications Ltd.

Matacena, Ilaria, et al. "SiC MOSFET CV Curves Analysis with Floating Drain Configuration." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022.

Matacena, Ilaria, et al. "Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Wei, Jiaxing, et al. "Interfacial damage extraction method for SiC power MOSFETs based on CV characteristics." 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). IEEE, 2017.

Tsuji, Katsuhiro, et al. "Measurement of MOSFET CV curve variation using CBCM method." 2009 IEEE International Conference on Microelectronic Test Structures. IEEE, 2009.

Jouha, Wadia, et al. "Physical study of SiC power MOSFETs towards HTRB stress based on CV characteristics." IEEE Transactions on Device and Materials Reliability 20.3 (2020): 506511.

Matacena, Ilaria, et al. "SiC MOSFETs Capacitance study." e-Prime-Advances in Electrical Engineering, Electronics and Energy (2023): 100251.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2023, July). SiC MOSFETs Biased CV Curves: A Temperature Investigation. In Materials Science Forum (Vol. 1091, pp. 31-36). Trans Tech Publications Ltd.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., & Daliento, S. (2024). Frequency Investigation of SiC MOSFETs CV Curves with Biased Drain. Solid State Phenomena, 360, 145-149.

Matacena, I., Maresca, L., Riccio, M., Irace, A., Breglio, G., Castellazzi, A., & Daliento, S. (2022, July). SiC/SiO 2 interface traps effect on SiC MOSFETs Gate capacitance with biased Drain. In 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (pp. 1-5). IEEE.

I. Matacena, A. Irace, S. Daliento and L. Maresca, "Investigation on Gate Capacitance Peak in SiC MOSFETs With Biased Drain," in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2025.3638294.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 35-41

doi: 10.4028/p-JdLnD2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-18

Accepted:
2026-01-31

Online:
2026-05-21

Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

Shane R. Stein 1,a*, Suman Das 1, b, Daniel J. Lichtenwalner 1,c and Sei-Hyung Ryu 1,d

1 Wolfspeed, Inc., 4600 Silicon Drive, Durham, NC 27703, USA

a* shane.stein@wolfspeed.com, b suman.das@wolfspeed.com, c  daniel.lichtenwalner@wolfspeed.com, d  sei-hyung.ryu@wolfspeed.com

Keywords: bias temperature instability, threshold voltage, hysteresis, charge pumping, triple sense method, interface traps, border traps.

Abstract

Bias-temperature instability (BTI) is one of the primary sources of parameter drift in silicon and SiC MOSFETs and consequently can determine device lifetime. Most studies of BTI in SiC MOSFETs have characterized the threshold voltage ( VT ) but not the interface trap density ( Nit ), leaving uncertainty about the relative contributions of carrier capture and trap creation to the VT shift. In this study, to lend insight into the physical mechanisms responsible for BTI in SiC MOSFETs, we measure Nit during positive bias-temperature stress (BTS) using the charge pumping (CP) technique. We also characterize the shift in VT and hysteresis using the triple-sense method [1], [2] for comparison with the Nit changes to evaluate whether the changes in Nit are responsible for the VT and/or hysteresis changes, and demonstrate the utility of the technique for reliable characterization of VT and hysteresis in SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

In SiC MOSFETs, the VT shift with an applied gate bias consists of two components: (i) a fast, reversible hysteresis wherein VT rapidly shifts back or forth by a finite amount in response to a negative or positive gate bias, and (ii) a quasi-permanent shift of the hysteresis envelope itself with prolonged gate bias [3], [4]. The hysteresis is believed to result from the capture of electrons or holes in interface and border traps. When a sufficiently positive voltage is applied to the gate to form an inversion channel, electrons which accumulate at the interface are captured by these traps and the negative trapped charge shifts VT positively. Conversely, when a sufficiently negative voltage is applied to the gate to accumulate holes at the oxide-semiconductor interface, the positively charged holes become trapped and shift VT negatively. For interface traps, the capture rate during inversion and accumulation is very fast compared to emission, so VT responds rapidly to the change in gate bias, resulting in the observed hysteresis. On the other hand, the physical mechanism responsible for the quasi-permanent VT shift component is less clear. Generally, the candidate mechanisms are either carrier capture (particularly in border traps), or the creation of new interface traps which can then become charged and contribute to the VT shift [5]. Many studies have been published which carefully characterize and model the VT shift according to one mechanism or the other [6], but there is a lack of reports directly measuring the trap density to help confirm or rule out the role of interface trap generation in the VT shift.

Charge pumping (CP) has been demonstrated to be an effective and versatile technique for measuring Nit for both silicon [7] and SiC [8], [9] MOSFETs. Advantages of this technique are that it can be used on a fully fabricated MOSFET (as long as the source and body contact are separated) undergoing the same process conditions as a production MOSFET and containing a p-type body, and it measures Nit across most of the semiconductor bandgap, including both donor and acceptor traps on each side of the bandgap, and only excluding traps very close to the band edges. This makes the technique especially useful for measuring the density of traps that affect VT, which are located deeper than the Fermi level position when the gate is biased near VT.

[picture]

Fig. 1. (a) Bias sequence of the triple-sense method. (b) ID−VGS curves corresponding to the three VGS of the triple-sense method after a cumulative stress time of 1000 s .

Fig. 1. (a) Bias sequence of the triple-sense method. (b) I D − V G S curves corresponding to the three V G S of the triple-sense method after a cumulative stress time of 1000 s .

For the purpose of this study, it is also necessary to compare the Nit measured by CP with the VT and the hysteresis as a function of BTS duration. Since the VT shift for SiC MOSFETs consists of the two components mentioned above, it is critical to have a proper VT measurement technique to capture the full VT behavior during BTS, or at least a conditioning step to establish a repeatable MOS interface charge state after each BTS interval. The triple-sense method has been demonstrated to be an optimal method for this purpose [1], [2]. As the name implies, the method uses three gate voltage ( VGS ) sweeps after each bias stress interval to obtain three VT sense measurements. A diagram of the bias sequence and the corresponding ID−VGS curves for the triple-sense method are shown in Fig. 1. In the case of a positive gate bias stress, the first sweep is a down-sweep starting from inversion with minimal delay time after the stress interval to minimize VT relaxation due to electron emission from the interface/border traps, the second sweep is an up-sweep starting from accumulation in order to rapidly charge the interface positively by hole capture, and the third sweep is final down-sweep starting from inversion to negatively charge the interface again. VT,1 obtained from the first sweep thus represents the combined effects of the negative trapped charge that exists during channel inversion and any additional time-dependent electron trapping during the bias stress interval preceding the first sweep, and VT,2 and VT,3 represent the lower and upper ends of the quasi-permanent hysteresis envelope, respectively, after resetting the interface charge condition with the accumulation bias at the beginning of the second VGS sweep. Therefore, by using three VGS sweeps and corresponding VT measurements, the triple-sense method can capture all aspects of VT shift during BTS.

The purpose of this study is to provide insight into the physical mechanisms responsible for the quasi-permanent VT shift in SiC MOSFETs during BTS. Specifically, the goal is to clarify whether interface traps are generated during BTS and, if so, whether they are responsible for the observed VT shift. To accomplish this, CP is used to measure Nit, and the triple sense method is used to characterize the quasi-permanent VT shift and hysteresis, after each BTS interval. Finally the magnitudes of the VT and hysteresis shifts are compared with the Nit changes to evaluate whether they are caused by the Nit changes.

Experimental Details

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The devices studied are lateral test MOSFETs fabricated on 4∘ off-axis 4H−SiC epitaxial wafers, with an implanted acceptor concentration of 2×1017 cm−3 in the channel, a thermal gate oxide formed on the Si face followed by NO annealing, and a channel length and width of 2μ m and 200 μm, respectively. For the BTS, the device temperature was set to 175∘C, and a gate voltage well beyond the recommended operating voltage was applied in order to accelerate the VT shift, which corresponds to an oxide electric field of 7.3MV/cm. At the same time, this bias is low enough to avoid the onset of additional degradation mechanisms such as impact ionization in the oxide which occur at even higher electric fields [9], [10]. For the triple-sense sequence, VGS was swept down from

15 V to 0 V for the first and third sweep, and swept up from -8 V to 4 V for the second sweep. After each triple-sense sequence the CP sweep is performed using the constant-amplitude method, with a gate pulse amplitude of 15 V , a rise/fall time of 1μ s, and a high/low time of 10μ s.

Results and Discussion

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Fig. 2 shows the ID−VGS characteristics resulting from the triple-sense measurements throughout the BTS experiment. The ID−VGS curve shifts toward more positive voltages with increasing gate stress time ( tstress  ), and this is accompanied by an increase in the hysteresis between sweep #2 and sweep #3. The increase in hysteresis suggests that an increase in interface and/or border trap density is taking place during the BTS.
By choosing a reference current level to define VT, each VT from the triple-sense method can be plotted versus tstress  to evaluate the VT shift and calculate the hysteresis. Fig. 3(a) shows each VT and the calculated hysteresis (Vhyst ) versus tstress  using a reference current of 10 nA . From this plot the full

[picture]

Fig. 2. (a) Triple-sense sweep #3 for each BTS interval from 0 s to 1000 s of cumulative stress time. (b) Sweep #2 and #3 before and after the entire BTS duration, from which both the quasi-permanent VT and hysteresis can be seen to have increased.

Fig. 2. (a) Triple-sense sweep # 3 for each BTS interval from 0 s to 1000 s of cumulative stress time. (b) Sweep #2 and #3 before and after the entire BTS duration, from which both the quasi-permanent V T and hysteresis can be seen to have increased.

[picture]

Fig. 3. (a) Each VT of the triple-sense method versus stress time using a reference current of 10 nA , and the calculated hysteresis from the difference of VT,2 and VT,3. (b) The quasipermanent VT and hysteresis shifts (referred to the initial values before stress) as a function of stress time. The shifts can be fit to a power law, as is routinely done for BTI measurements.

Fig. 3. (a) Each V T of the triple-sense method versus stress time using a reference current of 10 nA , and the calculated hysteresis from the difference of V T , 2 and V T , 3 . (b) The quasipermanent V T and hysteresis shifts (referred to the initial values before stress) as a function of stress time. The shifts can be fit to a power law, as is routinely done for BTI measurements.

VT behavior can be seen as it evolves during the BTS. VT,1 is highest value as it contains the maximum contribution of electron trapping effects on VT with minimal relaxation after each stress interval. VT,2 is the lowest value since it results from the up-sweep starting in accumulation which conditions the interface to a positive charge state. VT,3 lies between VT,1 and VT,2 since it results from a down-sweep from inversion which conditions the interface to a negative charge state but comes after the accumulation conditioning of the up-sweep which effectively resets the interface condition after the preceding stress interval. The difference between VT,1 and VT,3 can then be attributed to any charge trapping occurring during the bias stress interval which responds quickly enough to be eliminated during the accumulation conditioning of the up-sweep; i.e., by recombination during hole capture. VT,2 and VT,3 together then form the hysteresis envelope, and the shift that each experiences in common can be attributed to the charge trapping or trap generation occurring during the bias stress interval which is too slow to respond or be eliminated during the accumulation conditioning. For this reason, this shift is labelled "quasi-permanent," and it is the VT shift that is most relevant during typical MOSFET operation in switching applications.

Fig. 3(b) shows the quasi-permanent shift of VT,2 and VT,3 over time, as well as the change in hysteresis. Most of the shift is common between VT,2 and VT,3, but there is also a small increase in the hysteresis as the two VT values slowly diverge with time. Since the triple-sense sweep and timing parameters are constant along the BTS duration, any change in hysteresis should be related to a change in trap density. This is where CP measurements can provide additional insight by characterizing Nit during BTS as well.

The change in Nit as a function of tstress  measured by CP is shown in Fig. 4 . The CP measurements confirm that additional interface traps are indeed generated during the BTS, which is consistent with the observed increase in hysteresis from the triple-sense measurements. The Nit change is quite small compared to the typical values measured for SiC MOS devices [8], [9], [11], which is also consistent with the fact that the hysteresis change is small relative to the quasi-permanent VT shift.

To characterize the change in Nit further, the rise and fall times of the charge pumping gate pulse were varied in order to modulate the upper and lower bounds of the energy window of interface traps measured within the SiC bandgap and thus extract the interface trap density energy distribution ( Dit ) close to the valence band edge ( EV ) and close to the conduction band edge ( EC ) [9]. Since this procedure is more time intensive, it was performed once before the BTS experiment and once after the total 1000 s duration, to compare the Dit profile before and after stress. Furthermore, to extend the energy range of the Dit distribution that could be extracted, the procedure was repeated at two measurement temperatures: 25∘C and 125∘C.

The resulting Dit profile on each side of the bandgap before and after the BTS is shown in Fig. 5. The baseline Dit distribution is consistent with previous observations for Si-face SiC MOSFETs [12], [13], [14], with a uniform and relatively low Dit near EV, and an exponential increase near EC. After

[picture]

Fig. 4. The change in interface trap density as a function of bias stress time, which also follows a power law similar to the VT shift.

Fig. 4. The change in interface trap density as a function of bias stress time, which also follows a power law similar to the V T shift.

[picture]

Fig. 5. The extracted Dit profile before and after 1000 s of positive bias-temperature stress (a) in the lower half of the bandgap near the valence band edge and (b) in the upper half of the bandgap near the conduction band edge, obtained by modulating the rise and fall times of the gate voltage pulse during charge pumping.

Fig. 5. The extracted D i t profile before and after 1000 s of positive bias-temperature stress (a) in the lower half of the bandgap near the valence band edge and (b) in the upper half of the bandgap near the conduction band edge, obtained by modulating the rise and fall times of the gate voltage pulse during charge pumping.

the BTS, Dit increases a small amount evenly on both sides of the bandgap, which means both acceptor and donor interface traps are generated during the BTS.

With both VT and Nit having been measured as a function of stress time, it is now of interest to compare these quantities to evaluate their correlation. To make a quantitative comparison, the quantity Vit=qNit/Cox was calculated, where q is the elementary charge and Cox is the specific oxide capacitance of the MOSFET. This quantity represents the total expected gate voltage shift between accumulation and inversion due to the interface trap density measured by CP. In other words, it is the expected hysteresis based on the measured Nit value.

Fig. 6(a) shows the change in VT,3 and the change in Vit plotted together versus tstress  for comparison. In the plot, ΔVT,3 is plotted for four different choices of reference current used to extract VT, which is seen to have minimal impact on the extracted ΔVT,3. The magnitude of ΔVT,3 is about 3× greater than ΔVit, indicating that the VT shift is caused primarily by factors other than the creation of interface traps, such as electron capture in border traps within the oxide.

[picture]

Fig. 6. The change in Vit plotted versus stress time alongside (a) the change in VT,2 and (b) the change in hysteresis, for comparison of the interface trap density changes measured by CP with the quasi-permanent VT and hysteresis changes measured with the triple-sense method. ΔVT,2 and ΔVhyst  are each plotted for four different choices of reference current used to extract VT.

Fig. 6. The change in V i t plotted versus stress time alongside (a) the change in V T , 2 and (b) the change in hysteresis, for comparison of the interface trap density changes measured by CP with the quasi-permanent V T and hysteresis changes measured with the triple-sense method. Δ V T , 2 and Δ V hyst are each plotted for four different choices of reference current used to extract V T .

In Fig. 6(b), the change in hysteresis and the change in Vit are plotted together versus tstress  for comparison. The choice of reference current used to measure VT is seen to have a significant impact on the ΔVhyst  extracted. This can be interpreted as a result of the different amounts of band bending which occur depending on the current level used, which changes the energy range of the interface trap distribution causing the hysteresis. For the lower current levels, ΔVit and ΔVhyst  converge with increasing time, indicating that the generated interface traps measured by CP are responsible for the increase in hysteresis during the BTS.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

In summary, using CP measurements and the triple-sense method, we have been able to deduce certain facts about the physical mechanisms responsible for BTI in SiC MOSFETs. First, CP measurements revealed that interface traps are generated during positive BTS. Second, the quasipermanent VT shift during sBTS was significantly greater than the voltage shift caused by the generated Nit, which allows us to conclude that the VT shift is not primarily caused by interface trap creation, but by other effects such as charge capture by border traps. Lastly, the hysteresis envelope widened during the BTS, and the magnitude of the change was equal to the voltage shift due to the generated Nit, from which we can conclude that the generated interface traps are responsible for the increase in hysteresis. These insights into the physical mechanisms responsible for BTI are valuable for enabling the modeling and prediction of BTI related degradation and parameter shifts in SiC MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.35.pdf

D. J. Lichtenwalner, "Demonstration of the Benefits of Measuring SiC MOSFET BTI using a Triple Sense Method," in 2025 IEEE International Reliability Physics Symposium (IRPS), Mar. 2025, pp. 1-5. doi: 10.1109/IRPS48204.2025.10983888.

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T. Aichinger, G. Rescher, and G. Pobegen, "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs," Microelectronics Reliability, vol. 80, pp. 68-78, Jan. 2018, doi: 10.1016/j.microrel.2017.11.020.

J. H. Stathis, S. Mahapatra, and T. Grasser, "Controversial issues in negative bias temperature instability," Microelectronics Reliability, vol. 81, pp. 244-251, Feb. 2018, doi: 10.1016/j.microrel.2017.12.035.

T. Grasser et al., "The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction-Diffusion to Switching Oxide Traps," IEEE Trans. Electron Devices, vol. 58, no. 11, Art. no. 11, Nov. 2011, doi: 10.1109/TED.2011.2164543.

G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, "A reliable approach to charge-pumping measurements in MOS transistors," IEEE Trans. Electron Devices, vol. 31, no. 1, Art. no. 1, Jan. 1984, doi: 10.1109/T-ED.1984.21472.

A. Salinaro et al., "Charge Pumping Measurements on Differently Passivated Lateral 4H-SiC MOSFETs," IEEE Trans. Electron Devices, vol. 62, no. 1, Art. no. 1, Jan. 2015, doi: 10.1109/TED.2014.2372874.

S. R. Stein, J. Kim, S. Das, D. J. Lichtenwalner, and S. Ryu, "Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress," in 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA: IEEE, Apr. 2024, pp. 1-5. doi: 10.1109/IRPS48228.2024.10529394.

F. Masin et al., "Non-monotonic threshold voltage variation in metal-oxidesemiconductor field-effect transistor: Investigation and modeling," Journal of Applied Physics, vol. 130, no. 14, p. 145702, Oct. 2021, doi: 10.1063/5.0057285.

T. Hatakeyama et al., "Impact of crystal faces of in structures on interface trap densities and mobilities," Appl. Phys. Express, vol. 12, no. 2, Art. no. 2, Feb. 2019, doi: 10.7567/1882-0786/aaf283.

H. Yoshioka, T. Nakamura, and T. Kimoto, "Accurate evaluation of interface state density in SiC metal-oxide-semiconductor structures using surface potential based on depletion capacitance," Journal of Applied Physics, vol. 111, no. 1, Art. no. 1, Jan. 2012, doi: 10.1063/1.3673572.

G. Rescher, G. Pobegen, T. Aichinger, and T. Grasser, "On the subthreshold drain current sweep hysteresis of 4H-SiC nMOSFETs," in 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA: IEEE, Dec. 2016, p. 10.8.1-10.8.4. doi: 10.1109/IEDM.2016.7838392.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 43-47

doi: 10.4028/p-3xeuTP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-09

Accepted:
2026-03-16

Online:
2026-05-21

Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

The original version of this paper is available on https://www.scientific.net/KEM.1057.43.pdf

Luigi Di Benedetto 1,a*, Nicola Rinaldi 1, b, Mathias Rommel 2,c, Alexander May 2, d, Leander Baier 2,e, Rosalba Liguori 1,f, Alfredo Rubino 1, g and Gian Domenico Licciardo 1, h

¹Department of Industrial Engineering, University of Salerno, Via Giovanni Paolo II, 132, Fisciano, Italy

2 Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystraße 10, Erlangen, Germany

a  Idibenedetto@unisa.it, b  nrinaldi@unisa.it, c  mathias.rommel@iisb.fraunhofer.de,

d alexander.may@iisb.fraunhofer, e leander.baier@iisb.fraunhofer.de, f rliguori@unisa.it, g arubino@unisa.it, h gdlicciardo@unisa.it

Keywords: cryogenic temperatures, NOT logic gate, 4H-SiC lateral CMOS technology.

Abstract

In this paper, the electrical characterizations of a 4H−SiC CMOS NOT logic gate are performed in the temperature range from 300 K down to 100 K and the results are analyzed. The integrated circuit is fabricated with the Fraunhofer IISB 4H-SiC 2μ m CMOS technology and the lateral NMOSFET and PMOSFET have channel form factor of 6/6 and 44/6, respectively. The circuit is supplied with a 20 V . The curves show a reduction of the threshold voltage from 8.96 V to 6.85 V reducing the temperature from 300 K to 100 K and an ever-widening region in the High side (NMOSFET in saturation and PMOSFET in triode regime) compared to the Low side (NMOSFET in triode and PMOSFET in saturation regime). However, the noise margins are still wide enough for practical applications, making the circuit still useful. The behavior can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. Finally, analysis also focuses on the power dissipation during the transition of the output voltage from high (low) to low (high).

Introduction

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Nowadays, 4H-Silicon Carbide semiconductor devices are largely used in power electronics or for high-temperatures applications [1]. Its widespread availability permitted the fabrication of highquality substrates together with the improvements of the oxidation and of the ion implantation processes provided the basis for the development of new technologies, like 4H−SiC Complementary Metal Oxide Semiconductor, CMOS [2]. Indeed, 4H-SiC CMOS Integrated Circuits have been demonstrated to operate up to 873 K [3] or to allow integration of other devices, like diodes [3] or UV [4] sensors, opening new application fields. On the other hand, electronics for space explorations needs good radiation hardness, reducing the shielded package, and capability to operate at temperatures lower than 150 K . Moreover, the possibility of a single device to operate from 800 K down to 100 K with such huge temperature range is interesting both for scientific and for industrial purposes. Actually, only a few papers showed the operability of 4H−SiC devices at cryogenic temperatures from single vertical diodes [5] to power MOSFETs [6] as well as about lateral 4H−SiC MOSFETs [7-8]. However, there are lacks of information about the understanding of 4H−SiC device performances at low temperatures, like the effects of the incomplete ionization of Aluminum or of the interface trap density [9], and experimental results needs for an in-depth analysis.

In this context, our paper shows the electrical performance of a 4 H -SiC CMOS NOT logic gate, which is the core circuit for digital electronics. It has been measured in the temperature range from 300 K down to 100 K with the aim to analyze and understand the limits of 4H−SiCCMOS technology at cryogenic temperatures.

Fabrication Process and Experimental Set-Up

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The Fraunhofer IISB 4H−SiC2μ m CMOS technology [2] is used to fabricate the NOT logic gate, where the channel width of the NMOSFET, MN, and PMOSFET, MP, are 6μ m and 44μ m, respectively, whereas the channel length is even to 6μ m for both devices. In Fig. 1 a simplified crosssection of the device structures is reported. On a 4H−SiC n-type 350μ m4∘ off-axis (0001) substrate, a n-type epitaxial layer is grown with doping concentration of 1015 cm−3 and thickness of 10μ m. Selective doping regions are made through ion implantations of Aluminum and Nitrogen dopant atoms, respectively, for p-type and n -type regions and doping concentrations of 5·1019 cm−35,1017cm−3,1016 cm−3 are for high doping regions, p-type and n-type wells. After ion implantation, thermal activation annealing at 1973 K for 30 minutes is made. Then, thermal gate oxide of 55 nm -thick is grown and post-annealed at 1573 K in NO ambient and covered with n-type high doped poly-silicon. The resulting gate capacitance, Cox, is equal to 62.8nF/cm2. Silicide of Ti/Al and NiAl are formed on p+and n+-regions, respectively, and Ti/Pt is used as metal stack layers.

Measurement set-up consists of a HP 4145A for the electrical characterization and of a closed cycle cryo-system attoDRY800xs [10] and the temperature is monitored with a Cernox RTDs temperature sensor [11]. The samples are bonded on special PCB and positioned on the sample holder in order to cool down from 300 K to 100 K with a temperature step of 25 K .

[picture]

Fig. 1. A cross-section view of the 4H−SiC CMOS device structures.

Fig. 1. A cross-section view of the 4 H − S i C CMOS device structures.

Experimental Measurements and Discussion of the Analysis

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In Fig. 2 VIN -Vout characteristics are shown with a supply voltage, VDD, of 20 V and by varying the temperature from 100 K to 300 K with a step of 25 K . At 300 K the CMOS NOT has a threshold voltage, VM, of 8.96 V and, hence, is not fully complementary, i.e., VM≠VDD/2, because NMOSFET is more conductive than PMOSFET.

Observing the curves, the reduction of the temperature modifies the transfer-characteristics both shifting toward lower VIN  and decreasing the gain in the transition region. Indeed, in Fig. 3 we report VM as function of the temperature and it changes from 8.96 V at r.t. to 8.53 V at 200 K and to 6.85 V at 100 K , which is a reduction of −23.55% respect to r.t. It is worth to note that at 100 K the value of VM is still valid as NOT logic gate. Further, the high output voltage, Voh , is 19.98 V from 300 K to 150 K , but decreases to 19.95 V at 125 K and to 19.64 V at 100 K , whereas the low output voltage, VOL, is nearly 0 V . On the other hand, the variations of the VM and of the gain cause a significative reduction of VIL and VIH values: from 300 K to 100 K , VIH decreases from 9.89 V to 7.17 V and VIL from 8.18 V to 5.5 V . In Tab. 1 the main parameters of the NOT logic gate are reported for different temperatures.

[picture]

Fig. 2. VIN −VOut  characteristics from 100 K to 300 K with a T-step of 25 K . The inset shows Voltage Transfer Characteristics for the estimation of the Noise Margin and the NOT logic gate

Fig. 2. V IN − V Out characteristics from 100 K to 300 K with a T-step of 25 K . The inset shows Voltage Transfer Characteristics for the estimation of the Noise Margin and the NOT logic gate

[picture]

Fig. 3. Threshold voltage, VM, and High and Low Noise Margin, NMH and NML, as function of the temperature measured at VDD=20 V.

Fig. 3. Threshold voltage, V M , and High and Low Noise Margin, N M H and N M L , as function of the temperature measured at V D D = 20 V .

Table 1. Parameter of the Voltage-Transfer Characteristic of the 4H−SiC CMOS NOT logic gate as function of the temperature at VDD=20 V.

T [K] | VIL [V] | VIH [V] | VOL [V] | VOH [V] | VM [V] | NML [V] | NMH [V]
100 | 5.5 | 7.17 | ~0 | 19.64 | 6.85 | 5.5 | 12.47
150 | 7.11 | 8.54 | ~0 | 19.96 | 8.02 | 7.11 | 11.44
200 | 7.75 | 9.21 | ~0 | 19.98 | 8.53 | 7.75 | 10.77
250 | 8.06 | 9.62 | ~0 | 19.98 | 8.81 | 8.06 | 10.22
300 | 8.18 | 9.89 | ~0 | 19.98 | 8.96 | 8.18 | 10.09

Moreover, in the inset of Fig. 2 the area related to the High Noise Margin, NMH, increases compared to that of Low Noise Margin, NML, and in Fig. 3 their values are reported. They are defined as NMH=VOH−−VIH and NML=VIL−VOL. At 300 KNMH and NML are worth, respectively, 10.09 V and 8.18 V and, then, they have different behaviour with the reduction of the temperature: indeed, NMH increases to 10.77 V at 200 K and to 12.47 V at 100 K , whereas NML reduces to 7.75 V at 200 K and to 5.5 V at 100 K . In Tab. 1 detailed results are also reported. In both cases, their values make still useful the circuit for practical applications.

The temperature behavior of the Voltage-Transfer characteristic of NOT logic gate can be ascribed to the reduction of the conductivity of the PMOSFET and to the still valid operation of the NMOSFET down to 100 K . Indeed, in [7] 4H-SiC lateral PMOSFET diode-connect temperature sensors vary their characteristics around 175 K due to a significative reduction of the field-effect channel mobility, μCH,P : at a current of 1μ A,μCH,P is equal to 5.59 cm2/V/s at T=300 K and decreases to 0.2 cm2/V/s at 150 K , and to 0.07 cm2/V/s at T=100 K. Being μCH,P proportional to free/trapped carrier ratio, such reduction of μCH,P is related to the reduction of the free/trapped carriers ratio with the temperature, because the Fermi level moves toward the valence band [12]. On the other hand, NMOSFET field-effect channel mobility, μCH,N, decreases from 4.25 cm2/V/s at 300 K to 2.9 cm2/V/s at 150 K , but then increases to 3.38 cm2/V/s at 100 K at a current of 1μ A [8].

Finally, Static power dissipation is analyzed through the supply current, IDD, that is normalized with that at r.t., IDD,300 K, and it is reported as function of VIN  in Fig. 4. IDD reduces with the temperature and at 200 K is one order lower than 300 K until to have more than two orders of magnitude at 100 K . This advantageous reduction of the power dissipation is expected when electronic circuits operate at cryogenic temperatures [13].

[picture]

Fig. 4. Normalized supply currents, IDD/IDD,300 K, respect to 300 K as function of the input voltage for temperatures from 100 K to 275 K with a T-step of 25 K and measured at VDD=20 V.

Fig. 4. Normalized supply currents, I D D / I D D , 300 K , respect to 300 K as function of the input voltage for temperatures from 100 K to 275 K with a T-step of 25 K and measured at V D D = 20 V .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.43.pdf

In this paper the voltage transfer characteristics of 4H−SiC CMOS NOT logic gates are measured from r.t. down to 100 K showing the operability of the circuit in cryogenic temperature range. Indeed, although a reduction of the threshold voltage and of the low noise margin is evident, the values are still valid for its functionality as logic gate. Also, the expected reduction of the supply current during the transition from high (low) to low (high) output values is confirmed. The worsening of the static characteristic is mainly ascribed to the reduction of the field-effect channel mobility of PMOSFET. To have a complete understanding of the 4H−SiC CMOS NOT logic gate, dynamic characterizations are necessary as well as a long-term performance need to be addressed.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.43.pdf

P. G. Neudeck, D. J. Spry, L. Chen, N. F. Prokop, and M. J. Krasowski, Demonstration of 4hsic digital integrated circuits above 800∘C, IEEE Electron Device Letters, 38 (2017) 8, 10821085.

"Fraunhofer Institute for Integrated Systems and Device Technology (IISB)," .

J. Mo, J. Li, Y. Zhang, J. Romijn, A. May, T. Erlbacher, and S. Vollebregt, A highly linear temperature sensor operating up to in a 4 H -SiC CMOS technology. IEEE Electron Device Letters, 44 (2023) 6, 995-998.

L. Di Benedetto, G.D. Licciardo, T. Erlbacher, A.J. Bauer, and A. Rubino, A 4H-SiC UV phototransistor with excellent optical gain based on controlled potential barrier, IEEE Transactions on Electron Devices, 67 (2019) 1, 154-159.

C. D. Matthus, L. Di Benedetto, M. Kocher, A. J. Bauer, G. D. Licciardo, A. Rubino, and T. Erlbacher, Feasibility of p-i-n Diode for Sensitive Temperature Measurements Between 20.5 K and 802 K, IEEE Sensors Journal 19 (2019) 8, 2871-2878.

Y. Wei, M.M. Hossain, and H. A. Mantooth. Comparisons and evaluations of silicon and wide band gap devices at cryogenic temperature, IEEE Transactions on Industry Applications 59 (2022) 2, 1982-1994.

N. Rinaldi, M. Rommel, A. May, R. Liguori, A. Rubino, G.D. Licciardo, and L. Di Benedetto, Analysis of a lateral PMOSFET temperature sensor between . IEEE Sensors Letters, 9 (2025) 3, 2501504.

N. Rinaldi, M. Rommel, A. May, R. Liguori, A. Rubino, G. D. Licciardo, L. Di Benedetto, A 4H-SiC NMOSFET-based temperature sensor operating between 14 K and 481 K , IEEE Electron Device Letters, 45 (2024) 11.

L. Di Benedetto, N. Rinaldi, G.D. Licciardo, R. Liguori, A. Rubino, A. May, and M. Rommel, Performance and Understanding of 4H-SiC Electron Devices at Low Temperature Range. 2024 IEEE International Semiconductor Conference (2023) 23-28.

Information on .

Information on .

X. Chi, K. Tachiki, K. Mikami, M. Kaneko, and T. Kimoto, Different temperature dependence of mobility in n-and p-channel 4H-SiC MOSFETs. Japanese Journal of Applied Physics, 62 (2023), 110906.

R. M. Fox, and R.C. JAEGER, MOSFET behavior and circuit considerations for analog applications at 77 K . IEEE Transactions on electron Devices, 34 (1987) 1, 114-123.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 49-54

doi: 10.4028/p-5MC2iz

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-18

Accepted:
2026-01-31

Online:
2026-05-21

Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

Nicola Rinaldi 1,a*, Luigi Di Benedetto 1, b, Mathias Rommel 2,c,

Alexander May 2, d, Leander Baier 2,e, Rosalba Liguori 1,f, Alfredo Rubino 1, g and Gian Domenico Licciardo 1, h

¹Department of Industrial Engineering, University of Salerno, Via Giovanni Paolo II, 132, Fisciano, Italy

2 Fraunhofer Institute for Integrated Systems and Device Technology, IISB, Schottkystraße 10, Erlangen, Germany

a* nrinaldi@unisa.it, b Idibenedetto@unisa.it, c mathias.rommel@iisb.fraunhofer.de, d  alexander.may@iisb.fraunhofer.de, eleander.baier@iisb.fraunhofer.de, f  rliguori@unisa.it, g  arubino@unisa.it, h  gdlicciardo@unisa.it

Abstract

Experimental analysis of 4H−SiC lateral MOSFETs characteristics up to 773 K is shown. The reduction of threshold voltage, VTH, and the increase of the field effect channel mobility, μCH, with temperature cause an increase of MOSFET current up to 623 K . However, when scattering with lattice vibration starts to be predominant, μCH decreases with an abrupt drop at 773 K , reducing MOSFET current. Channel resistance, RCH, decreases with the temperature up to the range between 523 K and 573 K , implying possible thermal instability effects. However, when the temperature increases over this range, the thermal scattering predominates and RCH again increases, ensuring thermal stability of MOSFETs.

Keywords: high temperature, 4H−SiC lateral MOSFETs, 4H−SiC CMOS technology.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

Electron devices capable of operating at high temperature condition are required for harsh environment applications. To this aim, wide band-gap semiconductors are the most suitable [1]. 4HSiC CMOS technology is emerging among others, such as JFET [2, 3] and BJT ones [4], thanks to the ease of manufacturing and the possibility of easily achieving complementarity, necessary requirement for integrated circuits, ICs, design. However, there is still a lack of knowledge about electrical behaviour of single lateral NMOSFETs and PMOSFETs under high temperature operation, which is a starting point to understand and to improve technology performances and applications. Experimental characteristics of 4 H -SiC lateral MOSFETs have been shown up to 773 K [5, 6], however they are limited to devices with wide channel width, i.e. W=100μ m and W=150μ m, which are unusual for ICs design. Also, sensors based on diode connected MOSFETs have been shown up to 873 K [7], but the analysis is not supported by key physical parameters, like threshold voltage, VTH, and channel mobility, μCH. Moreover, in [8] experimental characteristics of 4H-SiC lateral MOSFETs have been analyzed in a limited temperature range, i.e. up to 573 K , and the effects of interface state defects are evaluated through numerical simulation tools. However, in [5-8] no considerations regarding thermal stability of devices through the extracted channel resistance have been provided. In this paper, we experimentally investigate the I-V characteristics of 4H−SiC lateral MOSFETs up to 773 K , through the extraction of physical parameters like VTH and μCH. Moreover, thermal stability analysis has been done through the extracted channel resistance.

Device Structure and Experimental Set-Up

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

Lateral MOSFETs have been fabricated in 4H-SiC CMOS Fraunhofer IISB's Technology [9]. A 1015 cm−3 Nitrogen doped epitaxial layer is grown on a SiC n-type 350μ m4∘ off-axis ( 0001 ) substrate. Aluminum and Nitrogen ion implantation, followed by a 1973 K,30 min, thermal annealing in Argon environment is performed for p -type and n -type doped regions. Resulting in a p -well with a doping
concentration of 1017 cm−3 and in a n -well with 1016 cm−3, whereas source and drain regions have a 5·1019 cm−3 doping concentration. The gate oxide is thermally grown at 1300∘C and a post-oxidation annealing in NO environment is performed at 1300∘C to reduce the interface state density. It results in a 55 nmSiO2 thick gate oxide with an oxide capacitance, Cox, of 62.8nF/cm2. A 500 nm n-type PolySilicon is deposited for the gate electrode, and a further 400 nm -thick oxide is deposited to gate electrode isolation. NiAl and Ti/Al are used for n-type and p-type contact materials. SiO2/Si3 N4/SiO2 stack is deposited by plasma enhanced chemical vapor deposition (PECVD) to isolate metals layers. These are made by Ti/Pt to allow high temperature operation [10]. Fabricated NMOSFET and PMOSFET have both channel width, W=24μ m, and channel length, L=6μ m.
Measurements have been performed in ambient atmosphere by heating the devices with a 630W G.Maier Elektrotechnick GmbH hotplate and measuring with a Keithley SCS-4200, a SUSS PM5 probe station and with Signatone Corporation manipulators equipped with Tungsten high temperature probe tips.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

High Temperature Characteristics.

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

I-V-T characteristics have been performed in T∈[298;773] with a ΔT=50K. The output characteristics, at |VGS|=20 V, of lateral NMOSFET and PMOSFET are shown in Fig.1.a)-b), respectively, whereas trans-characteristics, at |VDS|=0.1 V, are in Fig. 1.c)-d), both devices have W=24μ m and L=6μ m.

[picture]

Fig. 1. Output characteristics, |VGS|=20 V, of a) NMOSFET and b) PMOSFET, and trans-characteristics, |VDS|=0.1 V of c) NMOSFET and d) PMOSFET. Both with L=6μ m and W=24μ m, VBS=0 V, and T∈[298;773] with ΔT=50 K.

Fig. 1. Output characteristics, | V G S | = 20 V , of a) NMOSFET and b) PMOSFET, and trans-characteristics, | V D S | = 0.1 V of c) NMOSFET and d) PMOSFET. Both with L = 6 μ m and W = 24 μ m , V B S = 0 V , and T ∈ [ 298 ; 773 ] with Δ T = 50 K .

NMOSFET current increases with temperature by 100% up to 573 K and for VGS=VDS=20 V. Then, it increases by only 3.6% in T∈[623;723]K (see Fig.1.a)) and at T=773 K it decreases, as can be also observed in IDS−VGS characteristics of Fig. 1.c). Similarly, as shown in Fig.1.b), PMOSFET current increases up to T=573 K by 125% at VSG=VSD=20 V, then it reduces at T=773 K by −2.67%.

To explain MOSFET electrical behavior, key physical parameters, like threshold voltage and channel mobility have been extracted and their temperature behavior linked to MOSFET ones.

Threshold Voltage.

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

VTH has been extracted, for both NMOSFET and PMOSFET, from the trans-characteristics of Fig.1.c)-d) with the extrapolation in linear region method [11]. Both MOSFETs show a non-linear reduction with temperature increase, as shown in Fig. 2. The non-linearity can be explained through VTH  equation [12]:

VTH=φms+2ψB+4εSiCqNAψBCox+qQfCox+qDit(T)Cox(1)

where φms is the work function difference between the n -type Polysilicon and SiC, ψB the difference between the Fermi potential with respect to the midgap, εSiC the 4H−SiC dielectric permittivity, q the elementary charge, NAp-well doping concentration, Qf the fixed charge, and Dit(T) the temperature dependent interface defects. The high density of SiO2/4H−SiC interface defects and their temperature dependence introduce non-linearity [13-15], being directly linked to VTH through Eq.1.

[picture]

Fig. 2. VTH−T dependence for NMOSFET and PMOSFET in T∈ [298;773] with ΔT=50 K.

Fig. 2. V T H − T dependence for NMOSFET and PMOSFET in T ∈ [298;773] with Δ T = 50 K .

Channel Mobility

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

μCH has been extracted from trans-characteristics of Fig.1.c)-d) according to:

μCH=dIDSdVGS|VDS=0.1VLVDSCoxW(2)

Both NMOSFET and PMOSFET show an increase of field effect channel mobility peak up to T=523 K, then it starts to decrease (see Fig.3). Indeed, it increases up to μCH,N peak =21.75 cm2/Vs and μCH,P peak =8.25 cm2/Vs for NMOSFET and PMOSFET, respectively, whereas a minimum value is observed at T=773 K, with μCH,N peak =14.28 cm2/Vs and μCH,P peak =6.78 cm2/Vs. This behaviour can be explained in this way: the reduction of interface trapped charge with temperature causes a reduction of Coulomb scattering, allowing the channel mobility increase [16], but when the thermal scattering starts to be dominant the channel mobility decreases [12].

[picture]

Fig. 3. Extracted channel mobility for a) NMOSFET and b) PMOSFET, at |VDS|=0.1 V in Tϵ[298;773]K.

Fig. 3. Extracted channel mobility for a) NMOSFET and b) PMOSFET, at | V D S | = 0.1 V in T ϵ [ 298 ; 773 ] K .

The combined effect of VTH-reduction and μCH-increase with temperature causes a MOSFETs current increase up to T=623 K. However, when the reduction of channel mobility, due to thermal scattering starts to dominate, |IDS| reduces, as can be seen at T=773 K of Fig.1.c)-d).

Channel Resistance.

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

The current thermal behaviour explains channel resistance, RCH, temperature behaviour, which is shown in Fig.4. RCH has been extracted for both NMOSFET and PMOSFET from the output characteristics of Fig.1.a)-b) at |VDS|=0.1 V, by subtracting parasitic series resistance contribution, due to the implanted regions and contact resistance [17]. n-Channel resistance reaches a minimum at T=573 K of 11.5kΩ, whereas p-Channel resistance minimum of 36kΩ is at T=523 K. such reduction implies an increase of the current with temperature, in those applications where a bias voltage is applied, and therefore a possible self-heating effect can induce a thermal instability of the devices. However, the further increase of resistance at higher temperatures, as shown in Fig.4, reduces the thermal-run-away of the current, allowing a thermally stable device.

[picture]

Fig. 4. RCH−T of a) NMOSFET and b) PMOSFET in Tϵ[298;773]K, at |VGS|=20 V and |VDS|=0.1 V.

Fig. 4. R C H − T of a) NMOSFET and b) PMOSFET in T ϵ [ 298 ; 773 ] K , at | V G S | = 20 V and | V D S | = 0.1 V .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

Experimental analysis of 4H−SiC lateral MOSFET is shown between 298 K and 773 K . The MOSFET current temperature behavior can be related to the VTH and μCH temperature dependence. The current increases up to T=623 K and it stays almost constant in T∈[623;723]K. However, |IDS| starts to abruptly decrease when scattering carriers with lattice vibration becomes predominant on channel mobility, which abruptly decreases. Analysis of RCH−T behavior shows that possible self-heating problems could be due to decrease of RCH with temperature. However, the RCH increase at higher temperature guarantees the thermal stability of MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.49.pdf

[1] P. G. Neudeck, R.S. Okojie, L.Y. Chenl. High-temperature electronics-a role for wide bandgap semiconductors?. Proceedings of the IEEE 90.6 (2002): 1065-1076.

Spry, D. J., Neudeck, P. G., Chen, L., Lukco, D., Chang, C. W., & Beheim, G. M. (2016). Prolonged demonstration of 4 H -SiC JFET ICs with two-level interconnect. IEEE Electron Device Letters, 37(5), 625-628.

M. Kaneko, M. Nakajima, Q. Jin, T.Kimoto, SiC complementary junction field-effect transistor logic gate operation at 623 K . IEEE Electron Device Letters 43.7 (2022): 997-1000.

L. Lanni, B.G. Malm, M. Östling, C.M. Zetterling, Lateral pnp transistors and complementary SiC bipolar technology. IEEE electron device letters 35.4 (2014): 428-430.

Z. Dong, Y. Bai, C. Yang, Y. Tang, J. Hao, X. Li, X. Tian, X. Liu, Impact of Temperature on Digital Integrated Circuits in a CMOS Technology. IEEE Transactions on Electron Devices (2024).

J. Mo, Y. Niu, A. May, M. Rommel, C. Rossi, J. Romijn, G. Zhang, S. Vollebregt, An analog to digital converter in a SiC CMOS technology for high-temperature applications. Applied Physics Letters 124.15 (2024).

J. Mo, , A.May, M.Rommel, S. Vollebregt, G. Zhang, Temperature Sensing Elements for Harsh Environments in a CMOS Technology. IEEE Transactions on Electron Devices (2024).

H. Wang, P. Lai, A. Abbasi, M.M. Hossain, A. Faruque, H.A. Mantooth, Z. Chen. Characterization of Silicon Carbide Low-Voltage -Channel MOSFETs at High Temperatures. IEEE Journal of the Electron Devices Society (2024).

N. Rinaldi, M. Rommel, A. May, R. Liguori, A.Rubino, G.D. Licciardo, L. Di Benedetto, A 4H-SiC NMOSFET-based temperature sensor operating between 14 K and 481 K ." IEEE Electron Device Letters (2024).

R.M. Tiggelaar, R.G.P Sanders, A.W. Groenland, J.G.E. Gardeniers, Stability of thin platinum films implemented in high temperature microdevices, Sensors and Actuators A: Physical 152.1 (2009): 39-47.

A. Ortiz-Conde, F.J.G. Sanchez, J.J. Liou, A. Cerdeira, M. Estrada, Y.Yue, A review of recent MOSFET threshold voltage extraction methods. Microelectronics reliability 42.4-5 (2002): 583-596.

S.M. Sze, K.K. Ng, Physics of semiconductor devices. John wiley & sons, 2007.

G.D. Licciardo, L. Di Benedetto, S. Bellone, Modeling of the interface-trapped charge as a function of the surface potential in vertical-DMOSFET. IEEE Transactions on Electron Devices 63.4 (2016): 1783-1787.

S. L. Rumyantsevet, M.S. Shur, M.E. Levinshtein, P.A. Ivanov, J.W. Palmour, A.K. Agarwal, B.A. Hull, S.H. Ryu. Channel mobility and on-resistance of vertical double implanted 4H-SiC MOSFETs at elevated temperatures. Semiconductor science and technology 24.7 (2009): 075011.

S. Harada, R. Kosugi, J.Senzaki, S. Suzuki, W.J. Cho, K. Fukuda, K. Arai. Temperature dependences of channel mobility and threshold voltage in 4 H -and 6 H -SiC MOSFETs. MRS Online Proceedings Library 640.1 (2000): 37.

V. Uhnevionak, A. Burenkov, C. Strenger, G. Ortiz, E. Badel-Pereira, V.Mortet, F. Cristiano, A.J. Bauer, P.Pichler. Comprehensive study of electron scattering mechanisms in MOSFETs, IEEE Transactions on Electron Devices 62.8 (2015): 2562-2570.

M. Rommel, A. May, L. Baier, N.Böttcher, M. Jank, Investigation of Ohmic Contacts and Resistances of a 4 H -SiC CMOS Technology up to 550 Degrees C. Journal of Microelectronics and Electronic Packaging 21.4 (2024): 73-79.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 55-62

doi: 10.4028/p-HeV6Em

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-28

Accepted:
2026-02-26

Online:
2026-05-21

Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Jenny Damcevska 1,2,a*, Sima Dimitrijev 1,2,b, Daniel Haasmann 1,2,c, Philip Tanner 1, d, Fanpeng Zeng 3,e, Lan Luo 3,f, Yingxin Cui 3, g, Yu Zhong 3, h and Jisheng Han 1,3,i

¹Queensland Quantum and Advanced Technologies Research Institute, Griffith University, Nathan, Brisbane, QLD, 4111, Australia

2 School of Engineering and Built Environment, Griffith University, Nathan, Brisbane, QLD, 4111, Australia

3 Institute of Novel Semiconductors, 27 Shanda Nan Lu, Central Campus, Shandong University, Jinan, Shandong 250100, China

a* jenny.damcevska@griffithuni.edu.au, b s.dimitrijev@griffith.edu.au, c d.haasmann@griffith.edu.au, d  p.tanner@griffith.edu.au, e  202420644@mail.sdu.edu.cn, f  lan.luo@mail.sdu.edu.cn, g  cuiyingxin@sdu.edu.cn, h  yu.zhong@sdu.edu.au, j  j.han@sdu.edu.cn

Keywords: merged PN Schottky diode, non-repetitive surge current, repetitive surge current, Schottky barrier diode, silicon carbide, surge current.

Abstract

The repetitive peak forward surge current ( IF,RM ) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the nonrepetitive peak forward surge current value ( IF,SM ) in datasheets, which is generally determined from derated measured peak currents that cause diode failures. Consequently, it is assumed that IF,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine IF,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature does not exceed the maximum device rating, which is 175∘C for the commercially available devices analysed in this study.

Introduction

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Silicon carbide Schottky diodes have become indispensable in modern power electronics due to their superior material properties compared to conventional silicon devices. Their wide energy gap, high critical electric field, and excellent thermal conductivity enable fast switching, low reverse recovery charge, and high efficiency operation at elevated voltages and temperatures [1,2]. These characteristics make SiC Schottky diodes particularly attractive for applications in renewable energy systems, electric vehicles, and high-frequency power conversion, where energy efficiency, reliability, and compact form factors are paramount. A practically important parameter for ensuring the reliability of SiC Schottky diodes in such demanding applications is the repetitive peak forward surge current, IF,RM. This parameter governs how devices perform under repeated surge or inrush conditions, such as those encountered during startup transients, short-circuit events, or highly dynamic load changes. However, despite its importance for robust circuit designs, no standardized method or criterion currently exists for specifying this imperative parameter. Manufacturers predominantly present the non-repetitive peak forward surge current, IF,SM, in datasheets. When IF,RM values are provided by manufacturers, details regarding the criterion or method used to establish its value are not specified. As a result, variations in datasheet specifications among vendors make it difficult to meaningfully compare device robustness or to design circuits with reliable surge performance. Therefore, datasheet IF,RM values cannot be assumed to represent thermally safe repetitive operation,
as they are not derived using a disclosed or standardized physical criterion. At present, the only standardized procedures for surge-current rating are defined by JEDEC for silicon rectifier diodes [3], and no equivalent standardized method exists for specifying repetitive surge current capability in SiC Schottky diodes.
To address this gap, a consistent criterion for determining IF,RM is required. Therefore, in this study, we perform a comparative analysis based on a recently proposed method and criterion for IF,RM in SiC Schottky diodes that ensures that the maximum junction temperature rating of 175∘C is not exceeded [4]. In this way, the surge current capability is directly referenced to a fundamental thermal reliability limit. This was achieved using a comprehensive dataset comprising both TO-220 and TO-247 devices with blocking voltages of 650 V,1200 V, and 1700 V , and encompassing two structural types: merged PN Schottky (MPS) diodes and homogeneous-current Schottky barrier diodes (SBDs). By systematically evaluating repetitive surge currents in commercially available SiC Schottky diodes, this work demonstrates both the applicability and the necessity of the proposed method and criterion for determining IF,RM. The analysis further highlights variations in vendor datasheet practices and establishes a standardized framework for assessing repetitive surge current capability in SiC Schottky diodes. As a result, this study provides researchers and circuit designers with a practical and reliable tool for benchmarking device performance and ensuring robust, thermally safe power-electronic designs.

Surge Current Ratings and Reliability Considerations in SiC Schottky Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

In 4H-SiC Schottky diodes, the surge current capability constitutes a key parameter in assessing the robustness and long-term reliability in practical power electronic applications, which is specified in terms of both IF,SM and IF,RM. The IF,SM parameter represents the maximum current a diode can withstand during a single short-duration high-current pulse, arising from fault conditions or inrush currents, such as charging of bulk capacitors and inductive load energization. By contrast, IF,RM specifies the maximum current permissible during repetitive, short-duration high-current pulses, which are typically encountered in electronic circuits during normal operation, such as switching transients or recurring fault conditions.
The IF,SM parameter is evaluated in the literature by progressively increasing the peak of a single surge-current pulse until device failure or a defined degradation criterion indicative of surge limit is reached, which is then derated to assure consistent functionality under specified conditions [5-9]. The evaluation is typically performed using a half-sine wave pulse of either 10 ms duration at 50 Hz or 8.3 ms at 60 Hz . The IF,RM parameter is evaluated under identical half-sine wave conditions; however, to ensure reliable operation and prevent cumulative thermal overstress, a peak surge current level below the destructive threshold defined by IF,SM is selected and applied repetitively with sufficient cooling intervals [10-13]. An important consideration for repetitive surge current events is their reliance on the time-dependent transient thermal impedance, which determines the cumulative junction-temperature rise when cooling between pulses is insufficient, ultimately becoming the dominant reliability constraint. However, under standardized test conditions with sufficient cooling intervals, the cumulative thermal effect is effectively mitigated.
Together, the IF,SM and IF,RM ratings provide critical benchmarks for the safe design and reliable operation of SiC Schottky diodes, as they define the operating limits and tolerance for both singleevent and repetitive surge current conditions. While IF,SM sets the destructive single-event limit, IF,RM is practically important and serves as a critical parameter for circuit designers in preventing premature failure and ensuring long-term operation in practical applications. This practical importance is highlighted by experimental studies demonstrating that repetitive surge current stress can induce forward-voltage drift and progressive degradation in SiC Schottky-based devices, including JBS and MPS diodes, even when the applied current remains below the single-surge destructive limit. Reported mechanisms include stacking-fault-mediated bipolar degradation associated with minoritycarrier injection in JBS/MPS structures [11], as well as aluminum metallization melting and electromigration driven by repeated high-current thermal stress [11, 13]. Therefore, these parameters are indispensable for ensuring device robustness in practical applications such as power converters,
motor drives, and automotive systems, where surge currents frequently occur during switching, inrush, or fault conditions. Accordingly, it is essential that both IF,SM and IF,RM are clearly defined and supported by an appropriate method and criterion for SiC Schottky diodes, as each plays a critical role in device reliability.

Criterion for Repetitive Peak Forward Surge Current

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Given the critical importance of the IF,RM parameter, the analysis within this paper is based on a recently proposed method and criterion for repetitive peak surge current [4]. The foundation of the proposed criterion is defined by the condition that the surge current pulse does not exceed the isothermal I−V characteristic measured at the device's maximum rated junction temperature, which is 175∘C for commercially available devices [14-17]. This ensures that the junction temperature ( Tj ) of the packaged device remains within its specified thermal limit under repetitive surge current conditions. Figure 1 illustrates the method used in [4] by mapping the surge current measurements (loops) to the isothermal I−V characteristics measured at 175∘C.

[picture]

Fig. 1. Mapping of surge-current loops to isothermal I−V′s at 175∘C for vendor C (a) and vendor A (b).

Fig. 1. Mapping of surge-current loops to isothermal I − V ′ s at 175 ∘ C for vendor C (a) and vendor A (b).

Experimental Scope and Device Dataset

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A comparative analysis was conducted across four commercial vendors (Vendors A-D) for both TO220 and TO-247 packaging with the maximum temperature rating of 175∘C. The devices include two structural types-merged PN Schottky (MPS) diodes, represented by Vendors A-C, and homogeneous-current Schottky barrier diodes (SBDs), represented by Vendor D-with TO-220 devices rated at 650 V and 1200 V and TO-247 devices rated at 650 V,1200 V, and 1700 V . This selection of vendors, package types, and voltage ratings establishes a representative dataset, allowing the proposed criterion to be systematically applied and the results benchmarked against the corresponding datasheet specifications.

Criterion-Based Analysis of Repetitive Surge Current Capability: TO-220 SiC Schottky Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Assessment of Datasheet-Based Surge Current Specifications

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Tables I and II summarize the surge-current data for the TO-220 SiC Schottky diodes from three commercial vendors (Vendors A-C), along with the corresponding comparative analysis. A key limitation in relying on commercial datasheets to assess the surge current capability of SiC Schottky diodes is that the IF,RM parameter is not always specified, as demonstrated by Vendor B in Table I. In such cases, it is common practice to approximate the repetitive surge current as 70% of the specified IF,SM value ( 0.7IF,SM in Table I). However, the derated IF,SM values show poor correlation with the stated IF,RM values, signifying that IF,SM is not an adequate and reliable indication of IF,RM when it is not provided in datasheets. For Vendor A, the 650 V devices exhibit an IF,RM/IF,SM ratio of
0.66 ; however, at 1200 V this ratio decreases significantly to 0.45 , indicating a pronounced reduction in repetitive surge current capability with increasing blocking voltage. The devices from Vendor C show a wider range of IF,RM/IF,SM ratios at 1200 V , ranging from 0.57 to 0.70 . Thus, at 650 V the only available determination is 0.66 (as Vendor B does not specify the IF,RM parameter), whereas at 1200 V the ratios vary considerably between 0.45 and 0.70 across vendors. Therefore, in the absence of a standardized method for extracting IF,RM, these variations illustrate the lack of consistency in the IF,SM derating criterion used to define the IF,RM parameter. Consequently, for vendors that do not report IF,RM values (e.g., Vendor B), reliance on datasheet specifications alone is problematic due to the inconsistencies observed across manufacturers. At 1200 V , Vendor A specifies an IF,RM/IF,SM ratio of 0.45, whereas Vendor C reports ratios between 0.57 and 0.70 for devices with the same blocking voltage. This up to 55% variation in repetitive surge current capability across vendors demonstrates that datasheet IF,RM values are not based on a consistent criterion. Therefore, the absence of standardization and the observed variability further demonstrate that repetitive surge current capability cannot be reliably estimated by simply applying a universal de-rating of IF,SM.

Table I. Comparison of surge-current data for TO-220 SiC Schottky diodes from three different vendors.

Criterion-Based Determination of Repetitive Surge Current Capability

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

To illustrate the importance of the recently proposed criterion for specifying repetitive surge current, the peak surge current ( Ipeak  in Table II) was measured at Tj=175∘C and Tc=25∘C following the same surge current measurement method in [4]. To establish a tolerance margin, Ipeak  is derated to 90% so that the repetitive surge current is defined as IF,RM(175∘C)=0.9Ipeak . In Table II, these values for the repetitive surge current are benchmarked against the available IF,RM specifications in datasheets. The comparison shows that using 0.9Ipeak  yields IF,RM values in good agreement with most IF,RM specifications reported in manufacturer datasheets. Nonetheless, in the case of Vendor A, the datasheet IF,RM value for one 1200 V diode is slightly overrated, whereas the datasheet values for all three 650 V diodes are consistently underrated. This trend is further illustrated in Fig. 1, which maps surge-current loops to isothermal I−V characteristics at 175∘C for representative 1200 V/5 A devices from Vendor C (Fig. 1a) and Vendor A (Fig. 1b). For Vendor C (Fig. 1a), the datasheet IF,RM of 26A lies below the measured peak surge current (Ipeak =29 A), while the criterion-based estimate (0.9Ipeak =26 A) aligns exactly with the datasheet value, indicating an accurate specification. In contrast, for Vendor A (Fig. 1b), the datasheet IF,RM of 31.8A exceeds both the measured peak surge current ( Ipeak =28 A ) and the criterion-based estimate ( 0.9Ipeak =25 A ), indicating an overrated specification. For the Vendor A 1200 V/5 A TO-220 diode, the datasheet IF,RM of 31.8 A exceeds the
criterion-based value of 25 A derived from measurements at Tj=175∘C. This indicates that the datasheet permits repetitive surge operation beyond the thermally defined limit of the device. In this case, the commonly assumed approximation IF,RM≈0.7IF,SM would yield 49A, nearly double the thermally constrained value, illustrating that IF,SM-based derating can significantly overestimate safe repetitive operation.
The ratio IF,RM(175∘C)/IF,SM in Table II shows that the repetitive surge current typically lies between 60−90% of the non-repetitive surge current, reflecting how much of the single-event surge capability can be safely sustained under repetitive conditions at the maximum junction temperature of 175∘C. This approach also captures vendor- and voltage-dependent variations, with certain high-voltage devices exhibiting reduced margins ( 0.36−0.41 ). This variability among vendors and devices illustrates that device-specific behavior must be accounted for, and that a simple universal derating of IF,SM is insufficient for reliably determining IF,RM. Therefore, even in the presence of variation among vendors and devices, the proposed method provides a consistent framework for determining IF,RM with a safety margin that ensures adherence to the device's maximum thermal limits.

Table II. Repetitive peak surge current, IF,RM(175∘C), based on a recently proposed criterion for TO-220 SiC Schottky diodes for three different vendors.

Criterion-Based Analysis of Repetitive Surge Current Capability: TO-247 SiC Schottky Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

Assessment of Datasheet-Based Surge Current Specifications

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

The comparative analysis was extended to TO-247 SiC Schottky diodes, which are widely used in high-power, high-temperature applications owing to their superior thermal and current-carrying capabilities, thereby providing an important benchmark for evaluating surge current behavior across different vendors. Tables III and IV summarize the surge-current data for the TO-247 SiC Schottky diodes for three commercial vendors (Vendors A, B, and D), along with the corresponding comparative analysis.
The comparison in Table III highlights distinct vendor-dependent practices for specifying IF,RM, demonstrating a lack of consistency in how manufacturers define the repetitive surge current capability, as reflected by the wide variation in IF,RM/IF,SM ratios (0.42-0.90) across vendors and voltage classes. Moreover, the commonly assumed derating of IF,SM by 0.7 does not align with datasheet values for IF,RM, leading in some cases to overestimation (e.g., Vendor A, 1700V) and in others to underestimation (e.g., Vendor D, 1200 V ). For 1200 V/20 A TO- 247 devices, Vendor B specifies an IF,RM/IF,SM ratio of 0.42 , while Vendor D reports a ratio of 0.90 , highlighting more than
a twofold discrepancy in repetitive surge current capability for devices with identical ratings. These discrepancies, as observed in the TO-220 analysis, demonstrate that a simple universal derating of IF,SM is insufficient for reliably determining IF,RM, since in some cases this approach can be misleading and may result in operation beyond the device's thermal limits.

Table III. Comparison of surge-current data for TO-247 SiC Schottky diodes from three different vendors.

Criterion-Based Determination of Repetitive Surge Current Capability

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

The comparison illustrated in Table IV reinforces the vendor-dependent variability in repetitive surge current specification. As in the previous case, the peak surge current ( Ipeak  ) was measured at Tj=175∘C and Tc=25∘C, and then derated to 0.9Ipeak  to specify the repetitive peak surge current, IF,RM(175∘C). These values were then benchmarked against the datasheet specifications where available. Overall, Table IV confirms the same trends identified for the TO-220 packaged devices: vendor- and voltage-dependent variations exist, and datasheet specifications may either underrate or overrate actual surge current device performance. For example, Vendor A specifies an IF,RM value for its 1700 V/25 A diode that is greater than the measured Ipeak , even though the latter was obtained at the device's maximum junction temperature. For Vendor A's 1700 V/25 A TO- 247 diode, the datasheet IF,RM of 117A exceeds the criterion-based value of 104A obtained at Tj=175∘C. Similarly, for Vendor D's 650 V/20 A diode, the datasheet IF,RM(128 A) exceeds the measured peak surge current at 175∘C (99A), again indicating disagreement with a thermally constrained definition of IF,RM. This implies that the device could repeatedly sustain surges beyond its rated thermal limit. A similar issue is observed for Vendor D's 650 V/20 A diode, where the datasheet IF,RM likewise exceeds the measured Ipeak , again suggesting repetitive operation beyond safe thermal limit. By contrast, applying the proposed method-first determining the maximum surge current that can be handled within the 175∘C junction temperature limit, and then derating this value by 10%-ensures that IF,RM remains below the destructive threshold and maximum device ratings. Furthermore, the observed variation in the IF,RM(175∘C)/IF,SM ratio highlights the device-specific thermal behavior arising from structural design, blocking voltage, and current ratings. In this case, the results confirm the need for a standardized method and criterion to ensure that repetitive surge current capability is defined within the thermal limits of the device.

Table IV. Repetitive peak surge current, IF,RM(175∘C), based on a recently proposed criterion for TO-247 SiC Schottky diodes for three different vendors.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

The repetitive peak forward surge current ( IF,RM ) is a critical reliability parameter for SiC Schottky diodes, as it defines safe operation under repeated surge events and ensures robust circuit designs. Despite its importance, no standardized method or criterion currently exists, and manufacturers typically report only the non-repetitive peak forward surge current ( IF,SM ), which is based on destructive single-pulse measurements and provides limited guidance for repetitive operation. In this study, we perform a comparative analysis based on a recently proposed criterion for determining IF,RM, where the measured peak surge current at Tj=175∘C and Tc=25∘C ( Ipeak  ) is derated by 10% ( 0.9Ipeak  ) to maintain operation within the device's maximum thermal limit of 175∘C. Analysis across multiple vendors and voltage classes shows that this approach yields IF,RM values that are largely consistent with datasheet specifications, while avoiding the inconsistencies associated with unstandardized reporting or reliance on a universal derating of IF,SM. The results demonstrate that the proposed criterion provides a reliable and broadly applicable specification for IF,RM, enabling meaningful benchmarking across vendors, ensuring compliance with maximum thermal ratings, and supporting robust, thermally safe circuit designs. These findings highlight the lack of standardization in current datasheet practices and establish the importance of adopting a unified measurement method for repetitive surge current capability in commercial SiC Schottky diodes.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.55.pdf

T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, Wiley-IEEE Press, Singapore, 2014.

B.J. Baliga, Wide Bandgap Semiconductor Power Devices: Materials, Physics, Design and Applications, Woodhead Publishing, Cambridge, 2019.

JEDEC Standard Silicon Rectifier Diodes JESD282B.02, JEDEC Solid State Tech. Assoc, Arlington, VA, USA, 2023, pp. 1-162.

J. Damcevska, S. Dimitrijev, D. Haasmann, and P. Tanner, IEEE Access. 13 (2025) 153987 153992.

J. Wu, N. Ren, K. Sheng, Design and experimental study of 1.2 kV 4H-SiC merged PiN Schottky diode, Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), Shanghai, China, (2019) 203-206.

V. Banu, M. Berthou, J. Montserrat, X. Jordá, P. Godignon, Surge current robustness improvement of SiC junction barrier Schottky diodes by layout design, Romanian J. Inf. Sci. Technol. 20 (2017) 369-384.

V. Banu, X. Jordá, J. Montserrat, P. Godignon, J. Millan, P. Brosselard, Accelerated test for reliability analysis of SiC diodes, Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), Barcelona, Spain, (2009) 267-270.

R. Radhakrishnan, N. Cueva, T. Witt, R.L. Woodin, Analysis of forward surge performance of SiC Schottky diodes, Mater. Sci. Forum. 924 (2018) 621-624.

B. Zhang, et al., The surge current failure and thermal analysis of Schottky barrier diode, IEEE Trans. Electron Devices. 71 (2024) 1-6.

J. Wu, N. Ren, H. Wang, K. Sheng, 4H-SiC merged PiN Schottky diode with improved surge current capability, IEEE J. Emerg. Sel. Top. Power Electron. 7 (2019) 1496-1504.

X. Huang, G. Wang, M.C. Lee, A.Q. Huang, Reliability of SBD/JBS diodes under repetitive surge current stress, Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Raleigh, NC, USA, (2012) 2245-2248.

J. León, et al., Temperature effects on the ruggedness of SiC Schottky diodes under surge current, Microelectron. Reliab. 54 (2014) 2207-2212.

S. Palanisamy, J. Kowalsky, J. Lutz, T. Basler, R. Rupp, J. Moazzami-Fallah, Repetitive surge current test of SiC MPS diode with load in bipolar regime, Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), Chicago, IL, USA, (2018) 367-370.

D. Bisewski, M. Myśliwiec, K. Górecki, R. Kisiel, J. Zarębski, Examinations of selected thermal properties of packages of SiC Schottky diodes, Metrol. Meas. Syst. 23 (2016) 451-459.

Wolfspeed Inc., C3D Series Silicon Carbide Schottky Diodes, Datasheet, Wolfspeed Inc., Durham, NC, USA, 2022.

Infineon Technologies AG, CoolSiC Schottky Diode 1200 V Series, Datasheet, Infineon Technologies AG, Neubiberg, Germany, 2023.

GeneSiC Semiconductor Inc., GD20MPS12H 1200 V 20 A SiC Schottky MP Diode, Datasheet, GeneSiC Semiconductor Inc., Dulles, VA, USA, 2022.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 63-68

doi: 10.4028/p-a2X5vs

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-19

Accepted:
2026-03-16

Online:
2026-05-21

Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

Pei-Chun Liao 1,a, Kung-Yen Lee 1,2, b*, Ruei-Ci Wu 3,c, Yan-Yu Wen 1, d, Po-Yu Cheng 2,e and Wei-Xiang Wang 2,f

1 Graduate School of Advanced Technology, National Taiwan University, Taiwan

2 Department of Engineering Science and Ocean Engineering, National Taiwan University, Taiwan

3 SiCEV Electronics Co., Ltd., Taiwan

a  d13k44005@ntu.edu.tw, b*kylee@ntu.edu.tw, cricky_wu@sicev.com.tw, df10525134@ntu.edu.tw, er13525108@ntu.edu.tw, fr13525037@ntu.edu.tw

Keywords: silicon carbide (SiC), split-gate MOSFET (SG-MOSFET), short-circuit reliability, draininduced barrier lowering (DIBL), gate oxide field crowding.

Abstract

This work investigates the short-circuit (SC) reliability of Split-Gate (SG) versus planar 4H-SiC MOSFETs through TCAD simulations. While SG-MOSFETs effectively reduce gate-drain capacitance and improve switching performance, SG-MOSFETs exhibit enhanced short-circuit failure effects. Structural optimization-such as thicker drift regions, extended gate lengths, and narrowed JFET widths-can improve SC withstand time (SCWT). However, SG-MOSFETs suffer from intensified electric field crowding and enhanced drain-induced barrier lowering (DIBL), leading to greater post-SC leakage and thermal instability. Results suggest SG-MOSFETs require careful field and oxide engineering to ensure reliability under fault conditions.

Introduction

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Silicon carbide (SiC) MOSFETs are widely adopted for high-power and high-frequency applications due to their superior thermal conductivity, breakdown voltage, and switching efficiency [1,2]. However, their robustness under short-circuit (SC) conditions remains a critical reliability concern. [3-6] has gained particular attention. During SC events, the device must withstand large current surges under high drain bias without undergoing catastrophic failure. The short-circuit withstand time (SCWT) is a standard metric for assessing device survival under fault scenarios. Planar SiC VDMOSFETs are mature and reliable, but recent efforts have focused on Split-Gate (SG) MOSFETs [7], which reduce parasitic gate-drain capacitance ( Cgd ) and gate charge ( Qgd ) , thus lowering switching loss.

Although prior studies report similar SCWT for SG and planar structures [8, 9], the impact of SGinduced electric field redistribution, especially at oxide corners-has not been fully characterized. Additionally, physical factors such as gate length and JFET width may affect both conduction loss and SC robustness. This study uses TCAD to compare SG and planar 4H-SiC MOSFETs under SC conditions, focusing on how design parameters impact SCWT, peak current, and failure mechanisms. The analysis reveals SG-specific vulnerabilities, particularly in oxide stress and DIBL-induced leakage, highlighting the need for structural and electrostatic optimization.

Methodology

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

To assess the short-circuit behavior of SG and planar 4H-SiC MOSFETs, two-dimensional TCAD simulations were conducted using Synopsys Sentaurus. A half-bridge circuit was modeled, in which one MOSFET was pulsed to create SC conditions while the other remained off. Gate voltage ranged from 0 to 15 V , and drain voltage was set at 600 V or 1000 V .

Key physical models included drift-diffusion transport, Shockley-Read-Hall and Auger recombination, and avalanche generation to accurately simulate high-field, high-temperature effects. It should be noted that the TCAD 2D electrothermal simulations employed in this study provide a
qualitative indication of the temperature increase within the device. While they effectively capture relative trends and mechanisms, they may not fully represent the complex 3D thermal dissipation paths present in a packaged device.

Both SG and planar device structures were constructed with variable parameters: drift layer thickness, gate length, and JFET width. The drift region was uniformly doped at 5×1015 cm−3. Shortcircuit performance was evaluated by extracting transient peak drain current, maximum lattice temperature, and SC withstand time (SCWT). Gate charge curves were analyzed to calculate Qgd, and the high-frequency figure of merit (HF-FOM) [10] was used to assess switching efficiency. Electric field and conduction band profiles under SC stress were also examined to assess field crowding and DIBL-induced reliability concerns.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

The simulated SC responses of planar and SG-MOSFETs reveal how structural differences influence device robustness. Emphasis was placed on the interaction between parasitic capacitances, conduction paths, and electrothermal effects that define SCWT. Fig. 1 presents the schematic crosssections of both device types. The planar VDMOSFET employs a continuous polysilicon gate overlapping the JFET region, which inherently results in higher Cgd and Qgd. In contrast, the SGMOSFET introduces a split-gate structure that reduces the gate-to-drain overlap, thereby lowering Cgd and improving switching performance.

[picture]

Fig. 1. Cross-sections of (a) planar VDMOSFET and (b) SG-MOSFET.

Fig. 1. Cross-sections of (a) planar VDMOSFET and (b) SG-MOSFET.

As shown in Fig. 2, increasing the drift region thickness significantly affects SC behavior. A thicker drift layer introduces greater series resistance, which limits the peak drain current during SC and delays thermal buildup. This extends SCWT by reducing the rate of self-heating. For instance, devices with a 15μ m drift layer show lower current peaks and slower temperature rise compared to those with 10μ m, resulting in several microseconds of additional SCWT. However, this improvement comes with increased Ron,sp , highlighting a trade-off between fault tolerance and conduction loss. Designers must therefore balance SC reliability against efficiency requirements when adjusting drift thickness.

[picture]

Fig. 2. Simulated SC drain current and maximum lattice temperature versus time for different epitaxial thicknesses.

Fig. 2. Simulated SC drain current and maximum lattice temperature versus time for different epitaxial thicknesses.

Fig. 3 explores how gate length impacts Ron,sp and HF-FOM in SG-MOSFETs. Shorter gates reduce Cgd and Qgd, improving switching speed and lowering HF-FOM. However, they also weaken carrier accumulation in the JFET region, increasing Ron,sp and degrading conduction efficiency.

[picture]

Fig. 3. Simulated Ron,sp and HF-FOM relationship for different extended gate lengths.

Fig. 3. Simulated R o n , s p and HF-FOM relationship for different extended gate lengths.

Fig. 4 shows that narrowing the JFET width effectively reduces peak drain current during SC events, resulting in extended SCWT. For example, reducing the JFET width from 2.2μ m to 1.4μ m nearly doubles the SCWT, as the narrower current path limits surge current and delays thermal failure. However, excessive narrowing increases Ron,sp and can degrade overall conduction performance. Moreover, tighter current confinement enhances electric field stress near the oxide interface, raising concerns about long-term reliability. These results indicate that while reducing JFET width is a viable strategy for improving SC tolerance, it must be balanced against static and dynamic performance penalties.

As shown in Fig. 5, reducing JFET width below 1.4μ m causes a sharp rise in Ron,sp due to severe conduction constriction. While this improves SCWT, the gain is offset by degraded conduction efficiency. These findings emphasize that JFET scaling must avoid extremes, moderate narrowing is beneficial, but excessive reduction compromises both electrical and thermal stability.

[picture]

Fig. 4. Simulated SC drain current versus time with different JFET widths of SG-MOSFET. ( Vds= 1000 V ).

Fig. 4. Simulated SC drain current versus time with different JFET widths of SG-MOSFET. ( V d s = 1000 V ).

[picture]

Fig. 5. Simulated relationship between JFET width, Ron,sp, and reverse oxide electric field.

Fig. 5. Simulated relationship between JFET width, R o n , s p , and reverse oxide electric field.

Fig. 6 compares the SC current waveforms of SG and planar MOSFETs under identical bias conditions. Both exhibit similar SCWT, confirming that the split-gate structure does not compromise baseline SC survivability. However, post-SC behavior reveals critical differences. The SG-MOSFET demonstrates a more abrupt thermal runaway once failure initiates. This is attributed to its altered field distribution and lower Qgd, which while beneficial for switching, result in faster energy accumulation and less thermal buffering during SC events. These results suggest that while SCWT remains comparable, the failure of SG-MOSFETs are more abrupt and thermally aggressive than the planar MOSFET.

[picture]

Fig. 6. Simulated SC drain current versus time comparison between planar VDMOSFET and SGMOSFET. (a) Vds=600 V (b) Vds=1000 V.

Fig. 6. Simulated SC drain current versus time comparison between planar VDMOSFET and SGMOSFET. (a) V d s = 600 V (b) V d s = 1000 V .

Fig. 7 presents the electric field distribution under SC conditions at 1000 V . The planar MOSFET shows a relatively uniform field profile, with peak intensity near the drain junction. In contrast, the SG-MOSFET exhibits strong field crowding at oxide corners adjacent to the split gate. This localized enhancement raises the maximum oxide field ( Eox,max ), increasing the likelihood of oxide degradation and triggering early failure mechanisms. The elevated field also intensifies susceptibility to DIBL, further contributing to leakage current growth and thermal instability. These results explain the more rapid failure escalation observed in SG-MOSFETs post-SCWT.

[picture]

Fig. 7. Simulated electric field distributions under SC conditions ( Vds=1000 V ).

Fig. 7. Simulated electric field distributions under SC conditions ( V d s = 1000 V ).

Fig. 8 shows conduction band profiles under SC stress. In the planar MOSFET, the conduction band maintains a stable barrier between source and drain, which helps limit leakage current even at high drain bias. In contrast, the SG-MOSFET exhibits a more pronounced band lowering near the JFET region-indicative of stronger DIBL effects. This band lowering accelerates leakage current growth beyond the SCWT threshold, compounding thermal stress and promoting rapid thermal runaway. While the split-gate design improves switching performance, it inherently compromises electrostatic control, making SG-MOSFETs more vulnerable under extreme SC conditions.

[picture]

Fig. 8. Simulated conduction band energy profiles ( Vds=1000 V ).

Fig. 8. Simulated conduction band energy profiles ( V d s = 1000 V ).

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

This study presents a comparative TCAD analysis of SG- and planar 4H−SiC MOSFETs under short-circuit stress. While both achieve similar SCWT, SG-MOSFETs are more prone to post-SC degradation due to intensified oxide field and DIBL. Structural tuning-such as increased drift thickness, optimized gate length, and moderately narrowed JFET width—can effectively reduce Qgd, limit peak SC current, and improve HF-FOM. However, these benefits must be balanced against increased electric field stress and conduction losses. Future design strategies should prioritize field control near oxide corners to enhance SG-MOSFET reliability in high-stress environments.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.63.pdf

P. Samanta and K. C. Mandal, "Hole injection and dielectric breakdown in 6H-SiC and 4HSiC metal-oxide-semiconductor structures during substrate electron injection via FowlerNordheim tunneling," Solid-State Electronics, vol. 114, pp. 60-68, 2015.

S. Singh, T. Chaudhary, and G. Khanna, "Recent advancements in wide band semiconductors (SiC and GaN) technology for future devices," Silicon, vol. 14, no. 11, pp. 5793-5800, 2022.

T.-T. Nguyen, A. Ahmed, T. Thang, and J.-H. Park, "Gate oxide reliability issues of SiC MOSFETs under short-circuit operation," IEEE Transactions on Power Electronics, vol. 30, no. 5, pp. 2445-2455, 2014.

M. Okawa et al., "First demonstration of short-circuit capability for a 1.2 kV SiC SWITCHMOS," IEEE Journal of the Electron Devices Society, vol. 7, pp. 613-620, 2019.

G. Romano et al., "Short-circuit failure mechanism of SiC power MOSFETs," in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015: IEEE, pp. 345-348.

G. Romano et al., "A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 4, no. 3, pp. 978-987, 2016.

A. Agarwal, K. Han, and B. J. Baliga, " 2.3 kV 4H-SiC accumulation-channel split-gate planar power MOSFETs with reduced gate charge," IEEE Journal of the Electron Devices Society, vol. 8, pp. 499-504, 2020.

H. Liu, J. Wei, Z. Wei, S. Liu, and L. Shi, "Experimental comparison of a new 1.2 kV 4H-SiC split-gate MOSFET with conventional SiC MOSFETs in terms of reliability robustness," Electronics, vol. 12, no. 11, p. 2551, 2023.

K. Shin, D. Kim, M. Kim, J. Park, and C. Han, "Enhanced Short-Circuit Robustness of 1.2 kV Split Gate Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors for HighFrequency Applications," Electronics, vol. 14, no. 1, p. 163, 2025.

B. J. Baliga, Advanced power MOSFET concepts. Springer Science & Business Media, 2010.z

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 69-74

doi: 10.4028/p-Ncz2vl

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-17

Accepted:
2026-02-26

Online:
2026-05-21

Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

Hojung Lee 1,a*, Justin Lynch 1,b, Stephen A. Mancini 1,c, Skylar deBoer 1,d, Miguel Hinojosa 2,e, Aivars Lelis 2,f and Woongje Sung 1, g

¹College of Nanotechnology Science and Engineering, University at Albany, Albany NY, 12203, USA

2 U.S. Army Research Laboratory (ARL), Adelphi, MD 20783 U.S.A.

a*hlee36@albany.edu, b  jmlynch@albany.edu, c  smancini@albany.edu, d  sdeboer@albany.edu, e  miguel.hinojosa4.civ@army.mil, f  aivars.j.lelis.civ@army.mil, 9  wsung@albany.edu

Abstract

This study investigates the influence of active cell geometry on the static performance of 10−kV 4H-Silicon Carbide (SiC) Junction Barrier Schottky (JBS) diodes. Two types of diodes were fabricated and characterized, one with a hexagonal cell and the other with a stripe cell. While forward conduction characteristics were comparable, the reverse leakage current of the hexagonal cell was more than two orders of magnitude lower than that of the stripe cell at 8 kV . 3D TCAD simulations revealed that this discrepancy stems from strong electric field concentrations both at the bottom corners of the P+junctions and at the center of the Schottky contact in the stripe structure. These localized fields reduce the Schottky barrier height and enhance electron injection. In contrast, the hexagonal cell exhibited a more uniform electric field distribution in both regions, effectively suppressing leakage current. These findings underscore the critical role of active cell geometry in achieving robust reverse blocking performance in ultra-high-voltage SiC JBS diodes by clarifying the physical mechanisms contributing to leakage current behavior.

Keywords: 4 H -silicon carbide (SiC), 10−kV 4H-SiC junction barrier schottky (JBS) diodes, 3D TCAD simulations, cell geometry, reverse leakage, electric field.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

Silicon carbide ( SiC ) has emerged as a leading material platform for next-generation high-voltage power semiconductor devices, owing to its outstanding material properties such as wide bandgap, high critical electric field, high thermal conductivity, and excellent radiation hardness [1]. These attributes allow SiC devices to operate with significantly lower conduction and switching losses compared to their silicon counterparts, making them highly suitable for demanding applications that require compactness, efficiency, and reliability [2]. In particular, SiC is widely adopted in power conversion systems for electric grids, renewable energy infrastructure, and defense systems where voltage ratings often exceed the limits of conventional silicon-based technology [3]. For applications operating at voltages beyond 10 kV , it becomes especially important to minimize reverse leakage current and maintain robust blocking capability to ensure reliable and long-term operation.

Key design parameters that influence the reverse blocking performance of SiC devices include epitaxial layer doping and thickness, edge termination structures such as JTE or floating field rings, and the geometry of the active cell layout [4-7]. Among these, the active cell geometry is a particularly critical factor, as it affects both forward and reverse behavior by shaping the electric field distribution and carrier injection dynamics under bias. Therefore, a well-optimized cell structure is essential for achieving low leakage current without degrading forward conduction characteristics.

In this study, we investigate the effect of active cell layout on the static performance of 10−kV4H SiC junction barrier Schottky (JBS) diodes. Devices were designed and fabricated with two different active cell structures, one with a hexagonal pattern, which exhibits an enclosed geometry, and the other with a stripe pattern. Their forward and reverse characteristics were experimentally evaluated, and 3D TCAD simulations (Synopsys Sentaurus) were performed to analyze the electric field distribution in each structure.

The results demonstrate that the hexagonal layout effectively reduces field concentration and suppresses reverse leakage current while maintaining comparable forward conduction behavior.

Device Design and Simulation

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

To investigate the impact of active cell geometry on the static performance of ultra-high-voltage SiC JBS (Junction Barrier Schottky) diodes, two types of devices were designed and fabricated, one employing a hexagonal cell layout and the other a stripe cell layout. Both structures were configured with identical design parameters for a fair comparison, specifically setting the P+region width ( Lpp ) to 2.0μ m and the Schottky contact width ( Lsch  ) to 3.0μ m. Fig. 1 illustrates the top and cross-sectional views of each design, extracted directly from the GDS layout.

[picture]

Fig. 1. Schematic top and cross-sectional views of 10−kVSiCJBSdiodeswithtwodifferentactive cell geometries, (a) hexagonal and (b) stripe layouts. Both designs share identical cell dimensions, with the P+region width (Lpp) set to 2.0μ m and the Schottky region width (Lsch) set to 3.0μ m.

Fig. 1. Schematic top and cross-sectional views of 10 − k V S i C J B S d i o d e s w i t h t w o d i f f e r e n t a c t i v e cell geometries, (a) hexagonal and (b) stripe layouts. Both designs share identical cell dimensions, with the P + region width ( L p p ) set to 2.0 μ m and the Schottky region width ( L s c h ) set to 3.0 μ m .

The devices were fabricated on a 6-inch, n-type 4H-SiC wafer with an epitaxial drift layer engineered for 10 kV blocking capability. A Surface region was first formed through nitrogen ion implantation at room temperature. This step was performed prior to the P+region formation to locally increase the carrier concentration beneath the Schottky contact for improved current spreading, and to suppress excessive lateral straggle of the subsequent P+implantation, thereby enabling precise definition of the Schottky contact width ( Lsch  ). The P+regions were then formed via high-temperature aluminum ion implantation, followed by high-temperature activation annealing. A Ni metal layer was deposited on both the front and back sides of the wafer, and Rapid Thermal Process (RTP) was carried out to simultaneously form a P+ohmic contact on the front side and an N+ohmic contact on the back side. Subsequently, Ti was deposited on the front side as part of the top metal stack, forming a Schottky contact with the n-type drift layer in regions not implanted with aluminum ions. Finally, metal layers were deposited on both the front and back sides to complete the device fabrication.

To analyze the underlying physical mechanisms responsible for differences in device behavior, 3D TCAD simulations were performed using Synopsys Sentaurus. Both the hexagonal and stripe designs were modeled with full 3D structures incorporating the same design dimensions used in the fabricated devices. Fig. 2 shows the simulated geometries of the hexagonal and stripe designs, while Fig. 3 presents the doping profile used for the P+junction regions. The implantation model used in the simulation was pre-calibrated using actual SIMS (Secondary Ion Mass Spectrometry) data obtained from fabricated devices, in order to closely replicate the realistic junction depth and dopant concentration profile of the P+implantation. The simulations were configured to evaluate forward and reverse characteristics, with particular focus on electric field distribution and current conduction paths under reverse bias conditions.

[picture]

Fig. 2. Simulated geometries of 10−kVSiCJBSdiodeswith(a)hexagonaland(b)stripeactivecell designs. Each set shows the 3D isometric view (left), top view (top right), and cross-sectional view (bottom right) of the modeled structure used in the TCAD simulation.

Fig. 2. Simulated geometries of 10 − k V S i C J B S d i o d e s w i t h ( a ) h e x a g o n a l a n d ( b ) s t r i p e a c t i v e c e l l designs. Each set shows the 3D isometric view (left), top view (top right), and cross-sectional view (bottom right) of the modeled structure used in the TCAD simulation.

[picture]

Fig. 3. Simulated Surface N and P+ion doping profile used in the TCAD simulation.

Fig. 3. Simulated Surface N and P + ion doping profile used in the TCAD simulation.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

The electrical characteristics of the fabricated 10−kV SiC JBS diodes with hexagonal and stripe active cell designs were experimentally evaluated under both forward and reverse bias conditions. Fig. 4 shows the forward I-V characteristics, which represent the average response of approximately 20 devices for each structure. At a forward current of 0.5 A , the forward voltage drop was measured to be 3.70 V for the hexagonal cell and 3.48 V for the stripe cell, corresponding to a difference of 0.22 V . While this indicates a slight increase in conduction loss for the hexagonal design, both structures still maintain comparable forward behavior within typical operating margins for 10 kV class SiC diodes. This result confirms that the impact of active cell geometry on forward conduction behavior was effectively minimized within the tested current range.

In contrast, a significant difference was observed in reverse leakage characteristics, as illustrated in Fig. 5. Due to limited reverse yield, representative single-device measurements are shown. Under a reverse bias of 8 kV , the leakage current was measured to be 4.0×10−8 A for the hexagonal cell and 1.0×10−5 A for the stripe cell. This demonstrates that the hexagonal design achieves more than two orders of magnitude reduction in leakage current compared to the stripe layout, highlighting the importance of cell geometry in optimizing reverse blocking performance for ultra-high-voltage applications.

[picture]

Fig. 4. Statistical comparison of forward voltage drop for hexagonal and stripe active cells. Box plots reflect approximately 20 wafer-level measurements per structure, with median voltage drop values of 3.70 V for the hexagonal design and 3.48 V for the stripe design.

Fig. 4. Statistical comparison of forward voltage drop for hexagonal and stripe active cells. Box plots reflect approximately 20 wafer-level measurements per structure, with median voltage drop values of 3.70 V for the hexagonal design and 3.48 V for the stripe design.

[picture]

Fig. 5. Representative reverse I-V characteristics of 10−kV SiC JBS diodes based on single-device measurements. At a reverse bias of 8 kV , the leakage current was 4.0×10−8 A for the hexagonal design and 1.0×10−5 A for the stripe design, showing a difference of more than two orders of magnitude.

Fig. 5. Representative reverse I-V characteristics of 10 − k V SiC JBS diodes based on single-device measurements. At a reverse bias of 8 kV , the leakage current was 4.0 × 10 − 8 A for the hexagonal design and 1.0 × 10 − 5 A for the stripe design, showing a difference of more than two orders of magnitude.

To investigate the physical mechanisms behind this discrepancy, 3D TCAD simulations were carried out for both designs. Fig. 6 shows the electric field distributions under reverse bias conditions. The left-hand side presents isometric views of the electric field distribution, while the top and bottom images on the right provide surface plots of the electric field at critical locations, the bottom of the P+ junction ( ABCD plane) and the surface center of the Schottky region ( A′B′C′D′ plane), respectively. The simulation results clearly reveal that the electric field is more uniformly distributed in the hexagonal design, while strong field crowding is observed at the P+junction corners and Schottky surface in the stripe structure.

[picture]

Fig. 6. Simulated electric field distributions under reverse bias conditions for 10−kVSiC JBS diodes (a) Hexagonal active cell design and (b) Stripe active cell design. Each subfigure shows a 3D isometric view (left), an electric field surface plot at the bottom of the P+junction (ABCD plane, top right), and a surface field plot near the surface region ( A′B′C′D′ plane, bottom right).

Fig. 6. Simulated electric field distributions under reverse bias conditions for 10 − k V S i C JBS diodes (a) Hexagonal active cell design and (b) Stripe active cell design. Each subfigure shows a 3D isometric view (left), an electric field surface plot at the bottom of the P + junction (ABCD plane, top right), and a surface field plot near the surface region ( A ′ B ′ C ′ D ′ plane, bottom right).

Quantitative analysis of the electric field profiles is provided in Fig. 7, which compares the 1D vertical electric field distribution along the drift depth at representative high electric field locations. The peak electric field at the P+junction bottom corner was 2.02MV/cm for the hexagonal cell and 2.25MV/cm for the stripe cell. Similarly, at the surface center of the Schottky region, the local electric field was 1.13MV/cm for the hexagonal design and 1.43MV/cm for the stripe. These results indicate that the stripe geometry induces stronger electric field peaks at both the P+junction corner and the Schottky surface center. This increased field concentration may lead to enhanced electron tunneling or field-assisted thermionic emission, effectively narrowing the barrier width.

[picture]

Fig. 7. Simulated 1D vertical electric field distributions along the drift depth for the hexagonal and stripe JBS diode structures under reverse bias. (a) Electric field at the P+junction bottom corner and (b) Electric field at the surface center of the Schottky region. The hexagonal design exhibits lower peak electric field values at both locations compared to the stripe design.

Fig. 7. Simulated 1D vertical electric field distributions along the drift depth for the hexagonal and stripe JBS diode structures under reverse bias. (a) Electric field at the P + junction bottom corner and (b) Electric field at the surface center of the Schottky region. The hexagonal design exhibits lower peak electric field values at both locations compared to the stripe design.

These field-enhanced mechanisms are likely to facilitate increased electron injection from the Schottky contact into the drift layer through tunneling or field-assisted thermionic emission, which aligns with the elevated leakage current observed in the stripe device. In contrast, the hexagonal cell structure results in a more uniform electric field distribution and inherently provides better shielding of the Schottky surface by the surrounding P+regions due to its enclosed layout [8]. This shielding effect reduces the electric field intensity at the Schottky interface, thereby suppressing Schottky barrier lowering and limiting unwanted carrier injection. As a result, the hexagonal design achieves significantly lower reverse leakage current with minimal impact on forward conduction performance. A summary of the key simulation and measurement results is presented in Table 1, clearly illustrating the relationship between active cell geometry, electric field behavior, and reverse leakage characteristics.

Table 1. Summary of measured electrical characteristics and simulated peak electric fields for hexagonal and stripe JBS diode designs.

Active Cell

Forward Voltage

Drop [V,

measured]

Reverse Leakage

Current [A,

measured]

Peak Electric

Field at mathematical formula

junction bottom

corner [MV/cm]

Peak Electric

Field at Schottky

surface [MV/cm]

Hexagonal | 3.70 | superscript number | 2.02 | 1.13
Stripe | 3.48 | superscript number | 2.25 | 1.43

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

This study investigated the effect of active cell geometry on the electrical performance of 10−kV4H−SiC junction barrier Schottky (JBS) diodes by comparing hexagonal and stripe cell layouts. Both structures were designed with identical process parameters and fabricated on 6 -inch 4H−SiC wafers. Experimental measurements revealed that while forward characteristics were similar between the two designs, the hexagonal cell exhibited significantly reduced reverse leakage current, over two orders of magnitude lower than that of the stripe cell at 8 kV reverse bias. To understand this improvement, 3D TCAD simulations were conducted, showing that the hexagonal design suppresses peak electric field intensity both at the P+junction corner and Schottky surface center. This reduction in electric field mitigates Schottky barrier lowering and minimizes electron injection under reverse bias. These results suggest that the hexagonal active cell layout is a promising design choice for enhancing the reverse blocking performance of ultra-high-voltage SiC JBS diodes without compromising forward conduction efficiency.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.69.pdf

T. Kimoto and J. A. Cooper, Fundamentals of silicon carbide technology: growth, characterization, devices and applications., John Wiley & Sons, 2014.

S. Y. Jang, J. Kim, H. Lee and K. S. Kim, "Improved on-state resistance with reliable reverse characteristics in 1.2 kV 4H-SiC MOSFET by selective nitrogen implantation assisted current spreading layer", Japanese Journal of Applied Physics, vol. 59, no. 4, May 2022.

R. J. Callanan, A. Agarwal, A. Burk, M. Das, B. Hull, F. Husna, A. Powell, J. Richmond, S. Ryu and Q. Zhang, "Recent Progress in SiC DMOSFETs and JBS Diodes at Cree", in Proc. IEEE Annu. Conf. Ind. Electron., pp. 2885-2890, 2008.

A. Mihaila, R. A. Minamisawa, L. Knoll, V. K. Sundaramoorthy, E. Bianda, H. Bartolf, G. Alfieri, M. Rahimo, "On the Influence of Active Area Design on the Performance of SiC JBS Diodes", Mater. Sci. Forum, vols. 897, pp. 471-474, May 2017.

L. Liu, J. Wu, H. Xu, Z. Zhu, N. Ren, J. Zhang, K. Sheng, "The Impact of the Hexagonal and Circular Cell Designs on the Characteristics and Ruggedness for 4H-SiC MPS Diodes", IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1226-1232, Mar 2022.

B. Asllani, H. Morel, L.V. Phung, D. Planson, " 10 kV Silicon Carbide PiN Diodes-From Design to Packaged Component Characterization", Energies 12(23), 4566, 2019.

J. Lynch, N. Yun and W. Sung, "Design Considerations for High Voltage SiC Power Devices: An Experimental Investigation into Channel Pinching of 10 kV SiC Junction Barrier Schottky (JBS) Diodes", in Proc. 31st Int. Symp. Power Semiconductor Devices ICs (ISPSD), pp. 223226, May 2019.

S. A. Mancini, S. Y. Jang, D. Kim and W. Sung, "Increased 3rd Quadrant Current Handling Capability of 1.2 kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances", in Proc. IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), pp. 101-106, 2021.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 75-80

doi: 10.4028/p-ux3mDr

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-17

Revised:
2025-12-08

Accepted:
2026-01-31

Online:
2026-05-21

Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

D. Scholten 1,a*, J. Ziegler 2,b, W. Feiler 2,b

1 Advanced Technologies and Micro Systems, Robert Bosch GmbH, Germany,

2 Mobility Electronics, Robert Bosch GmbH, Germany

a  dick.scholten@de.bosch.com, b  johannes.ziegler2@de.bosch.com, c wolfgang.feiler@de.bosch.com

Keywords: 4 H -SiC MOSFET, Fowler-Nordheim current, gate leakage.

Abstract

We show that various commercially available silicon carbide MOSFETs exhibit significant gate leakage current at gate voltages below - 20 V . With prolonged negative bias stress, this leakage current reduces by several orders of magnitude. Literature [ 1−4 ] suggests that this current is due to hole current from the silicon carbide and explain the current reduction by the discharge of neutral electron traps at the SiC/SiO2-interface. However, measurements on n+-doped SiC -MOSCAPs, where we avoid hole current, exhibit similar gate leakage behavior, indicating that there might be an alternative explanation. Further measurements show that the threshold voltage is not significantly impacted by the negative gate bias stress, indicating that the channel region is not involved in the gate leakage current and its reduction due to trapping effects. Devices with a floating source do not show leakage, and we therefore conclude that the origin of the gate leakage is in the source region. An analytical calculation is used to show that field enhancement at the edges of the polysilicon gate electrode, assuming a corner radius below 10 nm , may explain the onset voltage of the gate leakage current at negative bias. Alternatively, gate oxide damage from the polysilicon etching process may also explain the leakage current. The reduction of the onset voltage of the gate leakage with prolonged negative voltage gate stress, may be explained by significant electron trapping due to the high local current density at the poly-silicon gate electrode corner.

Introduction

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The minimum rated gate voltage of commercial SiC MOSFETs typically ranges between -15 V and -4 V . Lower gate voltages may be employed for accelerated testing, such as in time-dependent dielectric breakdown (TDDB) with negative gate voltage, threshold voltage drift under negative gate bias, or bipolar dynamic gate switching stress. However, at very low gate voltages, typically below -15 V , several studies report significant gate leakage currents that decrease with continued negative gate voltage stress [ 1−4 ]. To evaluate the impact of the gate leakage on the accelerated reliability tests, a comprehensive understanding of its root cause is necessary. The prevailing hypothesis in these studies suggests that this current is a hole current from the silicon carbide towards the gate electrode. The reduction of hole current with continuing negative bias stress is explained by neutral near-interface traps that discharge electrons, thereby increasing the barrier height for holes.

In this paper, we investigate the location of the gate leakage and focus on the corners of the polysilicon gate electrode. Fig. 1 shows a schematic cross section of a typical planar and a typical trench MOSFET, where the edges of the poly-silicon gate electrode are indicated by the dashed circles.

We will show the gate leakage for negative gate voltage from different commercially available devices and compare that with results measured from SiC MOSCAP testing structures. To estimate the impact of the gate electrode geometry, we will present a calculation method to estimate the field enhancement factor from the radius of curvature of the poly-silicon edges.

[picture]

Fig. 1. Schematic cross sections of different typical SiC MOSFET cell concepts. Dashed circles indicate poly-silicon corners at the gate electrode opposite the source region. Plum and blue colored arrows indicate leakage current paths as proposed in literature and in this work. a) planar cell concept. b) trench cell concept.

Fig. 1. Schematic cross sections of different typical SiC MOSFET cell concepts. Dashed circles indicate poly-silicon corners at the gate electrode opposite the source region. Plum and blue colored arrows indicate leakage current paths as proposed in literature and in this work. a) planar cell concept. b) trench cell concept.

Gate Voltage Ramp Measurements

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We utilized commercially available SiC MOSFETs from four different vendors and applied bidirectional gate voltage ramps with varying maximum voltage values, as illustrated in Fig. 2, where the ramp order is indicated by the legend. All measurements were performed at room temperature. The onset of gate leakage with positive gate voltage ramp was significantly higher for Vendor C. Assuming that this is due to higher gate oxide thickness and desiring to have similar oxide electric fields for all vendors, we extended the voltage ramps for vendors C by 5 V .

We started by ramping up and down to a positive maximum gate voltage twice. The figure shows that the FN-current for positive gate bias is stable for all devices. The leakage current for all subsequent voltage ramps with negative gate bias shows clear reduction of current for each further gate bias ramp.

[picture]

Fig. 2. Absolute value of gate leakage current during different subsequent voltage ramps measured on devices from 4 different vendors. Note that for vendor C , we used 5 V higher values for the maximum gate voltage.

Fig. 2. Absolute value of gate leakage current during different subsequent voltage ramps measured on devices from 4 different vendors. Note that for vendor C , we used 5 V higher values for the maximum gate voltage.

The gate leakage current under negative bias appears to converge to a curve similar to the forward Fowler-Nordheim (FN) curve, but with opposite polarity, as negative voltage stress continues. We therefore propose that the gate leakage current under negative bias is an FN current characterized by an initially low barrier or a high local electric field at the barrier. Continued negative gate voltage stress shifts the onset of the current to significantly lower voltages, either by increasing the barrier or reducing the local electric field. Before and after each gate voltage ramp, we measured the threshold voltage, as shown in Fig. 3. The change in threshold voltage was significantly smaller than the shift in the onset of gate leakage. Compare for example, the shift in gate leakage onset ΔVonset  for the device from Vendor C of about - 13 V in Fig 2 with the change in threshold voltage of <50mV, as shown in Fig. 3. This indicates that the charging or discharging of near-interface traps in the channel region cannot account for the shift in the onset of gate leakage at negative bias.

[picture]

Fig. 3. Threshold voltage before and after each voltage ramp shown in Fig. 2.

Fig. 3. Threshold voltage before and after each voltage ramp shown in Fig. 2.

Gate Leakage of a Planar MOSCAP on an𝐧+-Doped SiC Epilayer

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

To test if hole current causes leakage at moderate negative bias, we measured the leakage current in an n+-doped SiC MOSCAP. The gate oxide thickness was 80 nm , and the substrate contained a uniform doping profile with a depth of 200 nm and an aluminum doping concentration of 8×1018 cm−3. We ramped the voltage of the top electrode from 0 V to +70 V to -50 V to 0 V and observed similar gate leakage behavior to that in commercial SiC MOSFETs, as shown in Fig. 4. We see an onset of gate leakage beyond -25 V and corresponding hysteresis, while at positive bias, we do not see significant hysteresis. At moderate negative gate bias in the range of this onset, we do not expect significant hole current from the n+-doped silicon carbide, as we do not expect inversion. Without hole current we can rule out the hypothesis from literature described above.

[picture]

Fig. 4. Gate leakage of a planar MOSCAP on an n+-doped SiC epilayer. a) Schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to +70 V to -50 V and back to 0 V .

Fig. 4. Gate leakage of a planar MOSCAP on an n + -doped SiC epilayer. a) Schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to +70 V to -50 V and back to 0 V .

Gate Leakage of a MOSFET with Either the Source or the Drain Terminal Floating

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

We measured the leakage current at negative gate bias for a device from Vendor A with either the source electrode or the drain electrode floating, as shown in Fig. 5b, demonstrating that the leakage current does not originate from the drain.

[picture]

Fig. 5. Gate leakage of a MOSFET with either the source or the drain terminal floating. a) schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to -40 V and back to 0 V of a device from vendor A with either drain or source electrode floating.

Fig. 5. Gate leakage of a MOSFET with either the source or the drain terminal floating. a) schematic cross section of the device. b) Absolute value of gate leakage current during a voltage ramp from 0 V to -40 V and back to 0 V of a device from vendor A with either drain or source electrode floating.

Analytical Calculation of the Field Enhancement Factor at the Poly-Silicon Corner

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Fig. 6a, shows calculated equipotential lines for a square edge close to an infinite surface. By associating the infinite surface with the SiC/SiO2-interface and one of the equipotential lines with the edge of the poly-silicon gate electrode, we estimate the field enhancement at a rounded corner of a SiC MOSFET gate electrode. The electric field was calculated using conformal mapping with a complex function

f(z)=f(x+iy)=u+iv.(1)

We use the Schwarz-Christoffel Transformation,

f(z)=ez+1+12log[ez+1−1ez+1+1](2)

adapted from [5], to map the equipotential lines of the electric field of an infinite parallel plate capacitor in two dimensions to a similar capacitor that has a 90∘ bend in the top plate away from the bottom plate, as depicted in Fig. 6a by the black line inside the superimposed poly-silicon area.

The field line roughly corresponding to the minimum radius of curvature of all the equipotential lines, is indicated in the figure by the line exiting from the poly-silicon corner. We calculated the radius of curvature of this field line by the following formula.

R=|(1+(dvdu)2)32d2vdu2|(3)

Fig. 6b displays the radius of curvature of the field line from Fig. 6a versus the field enhancement factor, defined as the field at the corner relative to the field between parallel plates far from the corner. Note that at large radii of curvature, the field enhancement factor decreases below 1 due to the increased distance between the corner and the plane compared to the region distant from the corner.

Based on the presented data, we propose the following hypothesis: With a corner radius of approximately 3 nm , the onset of FN current is expected to occur roughly twice as early as in the case of parallel plates. Typical polysilicon etching or reoxidation processes can cause corner radii well below 10 nm , which aligns with our simplified model explaining the early onset. Although some manufacturers seem to use polysilicon reoxidation to increase the distance between the SiC -interface and the poly-silicon corner by up to 50%, a corner radius well below 10 nm would still cause significant gate leakage as indicated by the steep slope of the field enhancement factor below 10 nm radius shown in Fig. 6b.

[picture]

Fig. 6. a) Edge of poly-silicon electrode in a planar SiC-MOSFET superimposed with calculated equipotential lines using conformal mapping with the Schwarz-Christoffel Transformation. b) Calculated field enhancement factor at the corner of the poly-silicon against the radius of curvature.

Fig. 6. a) Edge of poly-silicon electrode in a planar SiC-MOSFET superimposed with calculated equipotential lines using conformal mapping with the Schwarz-Christoffel Transformation. b) Calculated field enhancement factor at the corner of the poly-silicon against the radius of curvature.

Oxide Damage at the Edge of the Polysilicon Electrode

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

Etching polysilicon to define the extent of the electrode might cause damage to the oxide surface not masked by the polysilicon [6]. Oxide damage at the corner of the polysilicon might lower the barrier for electron emission from the gate electrode and thus explain the leakage current at negative gate bias, possibly in combination with geometric field enhancement.

Leakage Current Reduction with Prolonged Gate Bias Stress

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Due to the anticipated high electron current density at the poly-silicon corners, we also assume that local electron trapping is significantly enhanced, leading to a reduction of the electric field at the corners and consequently a decrease in FN current with continued electron current stress. The leakage current is therefore self-limiting. The trapping rate might also be enhanced due to the oxide damage at the edge of the polysilicon as explained in the previous section.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.75.pdf

Fiorenza, Patrick, Antonino La Magna, Marilena Vivona, and Fabrizio Roccaforte. "Near Interface Traps in SiO2/4H−SiC Metal-Oxide-Semiconductor Field Effect Transistors Monitored by Temperature Dependent Gate Current Transient Measurements." Applied Physics Letters 109, no. 1 (July 4, 2016): 012102. https://doi.org/10.1063/1.4955465.

Anoldo, Laura, Edoardo Zanetti, Walter Coco, Alfio Russo, Patrick Fiorenza, and Fabrizio Roccaforte. "4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed HighTemperature Reverse Bias and Negative Gate Bias Stresses." Materials 17, no. 8 (April 20, 2024): 1908. .

Shi, Limeng, Jiashu Qian, Michael Jin, Monikuntala Bhattacharya, Shiva Houshmand, Hengyu Yu, Atsushi Shimbori, Marvin H. White, and Anant K. Agarwal. "Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-Oxide-Semiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress." Electronics 13, no. 22 (November 18, 2024): 4516. .

Hiroki Nemoto, Dai Okamoto, Xufang Zhang, Mitsuru Sometani, Mitsuo Okamoto, Tetsuo Hatakeyama, Shinsuke Harada, Noriyuki Iwamuro and Hiroshi Yano. "Conduction mechanisms of oxide leakage current in p-channel 4H-SiC MOSFETs" Japanese Journal of Applied Physics, volume 59, number 4 (March 30, 2020): 044003. .

See .

Ohmori, T., and T. Makabe. "In Situ Measurement of Plasma Charging on SiO2 Hole Bottoms and Reduction by Negative Charge Injection during Etching." Applied Surface Science 254, no. 12 (April 2008): 3696-3709. .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 81-87

doi: 10.4028/p-Q9p090

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-22

Revised:
2025-12-21

Accepted:
2026-02-26

Online:
2026-05-21

Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

Takeshi Tawara 1,a*, Kensuke Takenaka 1, b, Syunki Narita 2,c and Shinsuke Harada 1, d

1 National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba West, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan

2 Fuji Electric Co., Ltd., 4-18-1 Tsukama, Matsumoto, Nagano 390-0821, Japan

a*tawara-takeshi@aist.go.jp, btakenaka-kensuke@aist.go.jp, ,narita-syunki@fujielectric.com, d  s-harada@aist.go.jp

Keywords: superjunction, MeV implantation, body diode, reverse recovery.

Abstract

MeV-SJ-MOSFET with short tapered SJ columns was developed by high-energy (MeV) Al ion implantation and was evaluated for the reverse recovery characteristics and the body diode reliability compared to those of Multiepi-SJ. MeV-SJ alleviated the increase in on-resistance at elevated temperatures regardless of short SJ columns and exhibited soft reverse recovery characteristics due to the short tapered SJ shape. MeV-SJ also suppressed the body diode degradation more than Multiepi-SJ. It was considered that the carrier lifetime of drift layer of MeV-SJ may be decreased by non-radiative defects.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

A 1.2 kV SiC semi-SJ-MOSFET formed by multi-epi process (repetition of epitaxial growth and ion implantation of medium-energy ( keV )) has advantages of a low specific on-resistance ( RonA ), soft reverse recovery and suppression of bipolar degradation of the body diode even at a high temperature [1-3]. However, due to the low diffusion coefficients of dopant atoms, the cost of Multiepi process is relatively high because of a large repetition number [4]. Recently MeV ion implantation process (deep ion implantation at MeV energies) was proposed to address the cost issue [5,6], but there are no detailed studies. In this study, we investigated the reverse recovery and bipolar degradation of the body diode of SJ-MOSFET formed by the MeV ion implantation process.

Experiment

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N-type epitaxial layers were grown on a 4H−SiC commercial substrate, followed by Al ion implantation at room temperature (R.T.) up to 8.0 MeV to form the SJ structure. A trench-MOSFET with 2.5μ m depth short tapered p-columns ( MeV -SJ) was fabricated. The tapered shape was employed to enhance the soft reverse recovery. For comparison, a trench-MOSFET (UMOS) and a trench-MOSFET with 5.2μ m depth SJ columns formed by multiepi method (Multiepi-SJ) were also fabricated. MeV-SJ and Multiepi-SJ have an identical design of the drift epitaxial layers. Crosssectional schematics and SEM micrographs of devices are illustrated in Figs. 1 and 2, respectively. The fabricated devices were mounted in TO-247 PKG, and their static and dynamic characteristics were evaluated. Reverse recovery characteristics were evaluated using a double pulse test method, where the same type of devices were used for the MOSFET and the body diode. The load inductance was 1 mH , the gate resistance was 75Ω and the junction temperature was 175∘C. Then we evaluated bipolar degradation of the body diode under a maximum current stress of 1500 A/cm2 for 5 min at 175∘C. Finally, implantation defects were investigated by cathodoluminescence (CL) at 28 K [7].

Results & Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

1. Static characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

Typical static characteristics at R.T. and 175∘C are summarized in Table. 1. Blocking waveforms are displayed in Fig. 3. MeV-SJ has a lower breakdown voltage for the shorter SJ columns than Multiepi-SJ, but shows a stable avalanche breakdown. Temperature dependences of specific onresistance ( RonA ) are presented in Fig. 4. Multiepi-SJ and MeV -SJ show lower RonA and weaker temperature dependence than UMOS, which originates from the high doping density of their drift layers.

[picture]

Fig. 1. Cross-sectional schematics of devices.

Fig. 1. Cross-sectional schematics of devices.

[picture]

Fig. 2. Cross-sectional SEM micrographs of devices.

Fig. 2. Cross-sectional SEM micrographs of devices.

Table I. Typical static characteristics.

[picture]

Fig. 3. Blocking waveforms.

Fig. 3. Blocking waveforms.

[picture]

Fig. 4. Temperature dependences of Specific on-resistance.

Fig. 4. Temperature dependences of Specific on-resistance.

2. Reverse recovery characteristics

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

First, we investigated the effect of the shape of SJ columns on the reverse recovery characteristics. The reverse recovery waveforms of 1.2 kV class SJ-MOS were simulated by Sentaurus TCAD simulation for the two SJ column shapes (SJ-straight and SJ-taper) and UMOS in the chopper circuit where the same type of devices were used in MOS and body diode. The results are depicted in Fig. 5. SJ-straight show large dV/dt and dir/dt values, while SJ-taper shows smaller values. In SJ devices, the dir/dt drastically changes when the output capacitance ( Coss  ) rapidly decreases due to the full
depletion of SJ columns [8,9]. The tapered shape of SJ columns alleviates the abrupt change of Coss  caused by the pinch-off of SJ columns, resulting in the soft recovery waveform.

[picture]

Fig. 5. Simulated reverse recovery waveforms of devices with different SJ column shapes.

Fig. 5. Simulated reverse recovery waveforms of devices with different SJ column shapes.

Second, we present the measured reverse recovery waveforms in Fig 6. MeV-SJ presents soft recovery waveforms by the short tapered columns. Then the current dependences of reverse recovery charge ( Qrr ) are shown in Fig. 7. The dependence for MeV -SJ is very weak, indicating that the carrier injection is suppressed at elevated temperatures similar to Multiepi-SJ. The smaller Qrr value of MeV SJ arises from the small junction capacitance for short SJ columns. The measured Coss−Vds characteristics are presented in Fig. 8 (a). MeV-SJ exhibits small Coss  without second sharp decline caused by the pinch-off of SJ columns. The simulated Coss −Vds curves in Fig. 8 (b) are in good agreement with the measured Coss −Vds curves. The depletion layer at Vds of 20,50 and 120 V are depicted in Fig. 8 (c). The depletion layer of Multiepi-SJ is expanding laterally and pinched off causing the drastic change of Coss  at around 100 V while that of MeV -SJ is expanding vertically, which leads to the gradual change of Coss.

Then the turn-on and turn-off waveforms of each device are presented in Fig. 9 and 10, respectively. The dV/dt of MeV-SJ is also smaller that that of Multiepi-SJ and there are no clear differences in Turn-off waveforms.

[picture]

Fig. 6. Reverse recovery waveforms at 175∘C.

Fig. 6. Reverse recovery waveforms at 175 ∘ C .

[picture]

Fig. 7. Qrr dependencies on load current.

Fig. 7. Q r r dependencies on load current.

[picture]

Fig. 8. (a) Measured and (b) simulated Output capacitance characteristics and (c) the depletion layer of each device.

Fig. 8. (a) Measured and (b) simulated Output capacitance characteristics and (c) the depletion layer of each device.

[picture]

Fig. 9. Turn-on waveforms.

Fig. 9. Turn-on waveforms.

[picture]

Fig. 10. Turn-off waveforms.

Fig. 10. Turn-off waveforms.

3. Body diode reliability

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Body diode reliability was evaluated with the current stress test up to 1500 A/cm2 at 175∘C. The Vf variations after each current stress are presented in Fig. 11. MeV-SJ shows higher durability than Multiepi-SJ. We observed the PL image with a wavelength of 420 nm after the 1500 A/cm2 stress test. Most devices show the bar-shaped single Shockley Stacking Faults (bar-shaped SFs) in chips. The typical width of bar-shaped SFs is 60μ m in Multiepi-SJ and 30μ m in MeV-SJ. Those values equivalent to the depth of 4μ m and 2μ m considering the substrate off-angle of 4∘. Bar-shaped SFs of MeV−SJ are assumed to stop expanding in the buffer layer.

[picture]

Fig. 11. (Upper) ΔVf dependences on current stress and (Lower) PL images ( λ=420±5 nm ) after the current stress of 1500 A/cm2.

Fig. 11. (Upper) Δ V f dependences on current stress and (Lower) PL images ( λ = 420 ± 5 n m ) after the current stress of 1500 A / c m 2 .

The simulated hole density profile of MeV -SJ under the current stress of 1500 A/cm2 at 175∘C is presented in Fig. 12 where the carrier lifetime of both drift layer consisting of SJ columns and buffer layer is changed from 1 ns to 100 ns . As described in Ref. 7, the Al implantation to form SJ columns decreases a carrier lifetime in the drift layer. In Fig. 12, the dotted line indicates the expansion threshold of bar-shaped SFs at the buffer/substrate interface as reported in Ref. 10, which is 1e16 cm−3. If the hole density exceeds the threshold, bar-shaped SF would expand from epi/substrate interface. In the case of the lifetime of 1ns, there is no region of hole density over the threshold near the epi/substrate interface and no bar-shaped SFs would expand. On the other hand, for the lifetime of 100 ns , the hole density exceeds the threshold in the whole drift layer and a bar-shaped SF would expand to the surface. However, in the case of the lifetime of 5 and 7.5 ns , there is a local region of hole density under the threshold. A bar-shaped SF expanding from epi/substrate interface would stop at the region and become narrow as reported in Ref. 11. The region of high hole density near the epi/substrate interface is supported by the excess electron injection into the buffer region from the substrate side and extends with increasing the drift layer lifetime. From these results, the lifetime in drift region of MeV-SJ would be smaller than that of Multiepi-SJ.

[picture]

Fig. 12. Simulated hole density profile of devices with different lifetimes of drift layer.

Fig. 12. Simulated hole density profile of devices with different lifetimes of drift layer.

Finally, we investigated ion implantation defects using CL imaging. First the typical CL spectra are presented in Fig. 13(a). CL spectrum of Multiepi-SJ and MeV-SJ have different intensities but similar peaks in each device region. The cross-sectional images of the Ll line which is a well-known implantation defect, are shown in Fig. 13 (b). The intensity is standardized by the near the band edge intensity. The L1 intensity of Multiepi-SJ is stronger than that of MeV-SJ in SJ and buffer region.

This would be caused by the extensive thermal history of Multiepi-SJ where the epitaxial growth is repeated. The L1 line intensity is reported to increase under high-temperature annealing [12]. On the other hand, these results cannot explain the higher body diode reliability of MeV -SJ. The nonradiative defects that are not detected in CL may affect the suppression of bipolar degradation.

[picture]

Fig. 13. (a) CL spectra of devices. (b) Cross-sectional SEM micrographs and CL images of normalized L1 line luminescence and those line profiles.

Fig. 13. (a) CL spectra of devices. (b) Cross-sectional SEM micrographs and CL images of normalized L 1 line luminescence and those line profiles.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

Even short SJ columns of 2.5μ m can mitigate the increase of on-resistance at high temperatures because of high doping concentration of the drift layer. Short tapered SJ columns soften the reverse recovery waveform by mitigating the abrupt change of Coss.  MeV-SJ suppresses the body diode degradation more than Multiepi-SJ due to the short carrier lifetime of the drift region. MeV-SJ with short tapered SJ columns has the advantage of high reliability of the body diode and soft reverse recovery compared with Multiepi-SJ.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

This study was implemented under a joint research project of Tsukuba Power Electronics Constellations (TPEC). Specifically, T. Tawara and K. Takenaka were assigned from Fuji Electric Co., Ltd. Authors specially thanks to Mr. T. Morimoto of AIST and Mr. K. Oozono of PHENITEC SEMICONDUCTOR Corp. for prototyping and helpful discussions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.81.pdf

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 89-94

doi: 10.4028/p-V4pYXX

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-21

Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Boglárka Dikó 1,a, Oleg Rusch 2,b, Julien Körfer 2,c, Zsófia Kiss 1,d, Attila Sütő 1,e and Emeric Balogh 1, f *

1 Semilab Semiconductor Physics Lab. Co. Ltd., Hungary

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Germany

a  boglarka.diko@semilab.hu, b  oleg.rusch@iisb.fraunhofer.de, c  julien.koerfer@iisb.fraunhofer.de,

d zsofia.kiss@semilab.hu, e attila.suto@semilab.hu, f emeric.balogh@semilab.hu

Keywords: trench MOSFET, OCD, critical dimension metrology, ellipsometry, reflectometry.

Abstract

Silicon carbide (SiC) MOSFETs are widely utilized in power device applications for their numerous advantages, and the device's properties can be further optimized through the implementation of trench structures. The formation of the trench structure is a multi-step process, in which it is important to monitor the result of each step and ensure that the structure meets the desired requirements. OCD (optical critical dimension) metrology can provide a fast, non-destructive solution for this purpose. In this article, an OCD analysis of structures at two different process steps is presented and compared with the results from the electron microscopy images. OCD results show high sensitivity to the geometrical dimensions of the structure and produce a good correlation with the electron microscopy images. This metrology can provide a means to detect subtle structural differences without causing any damage to the sample.

1 Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Silicon Carbide (SiC) MOSFETs are extensively researched and widespread in power device applications owing to their many advantages, and trench structures can further improve their properties. The vertical channel in trench MOSFETs increases integration density, heat dissipation and channel mobility, simultaneously reducing on-resistance, enabling the production of more efficient devices with lower power consumption [1,2].

Trench structures are fabricated in a multi-step process, involving different etching steps [3]. Trench formation in SiC is usually carried out using dry etching processes. During the process, SiO2 serves as a masking material, and the shape of the hard mask (HM) has a significant influence on the shape of the final SiC trench [1]. A certain sidewall angle (~90∘) is required for trenches to obtain high charge carrier mobility, to minimize the interface states between the SiC sidewall and the gate oxide, and to avoid cavities during the subsequent polysilicon filling. In addition to the shape, the depth of the trenches is also a critical parameter for obtaining the length of the channel that allows the desired properties to be achieved [1,2]. There are many process steps in which it is important to monitor whether the structure meets the requirements for an optimal trench MOSFET device.

Optical critical dimension metrology (OCD) offers a fast, non-destructive, non-contact method for investigating the geometrical parameters of the structure (sidewall angle (SWA), depth, critical dimension (CD) parameters, etc.). We present the advantages and results of OCD evaluation of two types of structures (hard mask trench on SiC substrate and SiC trench with a hard mask on top). The investigated structures are analyzed by scanning electron microscopy (SEM) as well, which allows us to compare the parameter values obtained by the two methods and to validate the OCD analysis results. It is important to highlight that OCD measures average results within the measurement spot (50μ m), and therefore, local variation in trench geometry can make direct SEM comparison challenging.

2 Methods

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2.1 Evaluation method

OCD metrology, also known as Model-Based Dimension (MBD) metrology or scatterometry, allows the geometric parameters and shape of the investigated structure to be characterized rapidly and non-destructively [4]. Measurements used by OCD, such as reflectometry and ellipsometry, can be sensitive to buried structures as well, which are traditionally not measurable by non-destructive techniques. This is an indirect, model-based method; thus, an accurate theoretical model of the trench structure has to be built for accurate evaluation. This requires some prior knowledge of the structure, including the shape and nominal dimensions of the trench structure and the optical constants of constituent materials. Furthermore, a successful OCD evaluation requires the measurement spot to cover a periodically repeating structure with a sufficient number of periods [5]. Evaluation is done by modelling the light-matter interaction of the measurement beam with the sample structure. Most commonly, the Rigorous Coupled-Wave Analysis (RCWA) [6] method is applied for this purpose, and it was also used in this study. The geometrical parameters are extracted by an algorithm which finds the trench parameters that produce the best match between simulated and measured spectra. With an optimized evaluation algorithm, this allows fast full-wafer mapping and tight process control in many steps of the process. To accurately model SiC, the optical anisotropy of the material has to be considered in RCWA [7]. To further increase accuracy, the instrumentation properties (like detector resolution and focusing optics properties) were taken into account [8].

In this study, Spectroscopic Polarized Reflectometry measurements were performed on the wafers to characterize the trenches. The sample under investigation is illuminated with light of two polarizations: parallel to the plane of incidence ( p -polarization) and perpendicular to it ( s polarization) and reflectance is measured independently for both polarizations. Extraction of the geometrical dimensions of the trenches is then done with a dedicated software which performs the simulation of the measurement and parameter fitting. With an optimized evaluation recipe, the evaluation can be done in seconds, allowing the characterization of the trench dimensions to be performed on each die on the wafer, or even at multiple sites within a single device.

2.2 Investigated structures and SEM measurements

Several samples were fabricated according to the process described in Rusch et al. [1]. In the first example (Fig. 1.), the wafer has already gone through the HM etching process and the characterization of the dimensions of the oxide mask is performed. The HM defines the shape and width of the final trench; therefore, this process step is critical to monitor.

The second example (Fig. 2.) is a case of SiC trench etch monitoring right before hard mask removal. The presented optical method allows the monitoring of both the SiC trench etch depth and the remaining HM thickness; therefore, in this step, it is possible to contain the etch process.

The samples were prepared for SEM measurements by FIB milling to reveal the cross-section of the trenches. SEM images were taken at 10k,50k and 100 k magnifications, aligned at a 52∘ angle to the surface normal. This angle was accounted for in the measurements and the SEM images shown are scaled accordingly for visual comparison with OCD evaluation.

[picture]

Fig. 1. SEM image of SiO 2 hard mask trench on SiC .

Fig. 1. SEM image of SiO 2 hard mask trench on SiC .

[picture]

Fig. 2. SEM image of SiC trench with a SiO2 mask on top.

Fig. 2. SEM image of SiC trench with a S i O 2 mask on top.

3 Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

3.1 OCD analysis of hard mask etched SiC samples

The comparison of the SEM and OCD analysis results was performed at three different points on the wafer. For one of the sites, Fig. 3. shows the measured and fitted reflectance spectra derived from RCWA simulation based on the modelled structure. For the same site, the SEM image and the OCD model for the SiO2 hard mask trench are shown in Fig. 4. The trench is modelled with a trapezoidal shape in the OCD model. The results show very good agreement with the structure observed in the electron microscopy image. The agreement of the results, and the good match between the measured and modelled spectra for both polarizations show the accuracy of the theoretical model and reliability of the evaluation algorithm. It is important to note here as well that the OCD evaluation represents an average over the entire measurement spot, rather than the parameters of a single trench as in the SEM measurement. Therefore, the comparison should be interpreted accordingly.

[picture]

Fig. 3. Measured and fitted reflectance spectra of HM trench.

Fig. 3. Measured and fitted reflectance spectra of HM trench.

[picture]

Fig. 4. SEM image and trench structure resulting from the OCD evaluation −SiO2 hard mask trench on SiC .

Fig. 4. SEM image and trench structure resulting from the OCD evaluation − S i O 2 hard mask trench on SiC .

Considering the results of the three sites on the wafer, a strong correlation can be observed between the extracted and SEM parameter values. Fig. 5. shows the relation between these values for the trench bottom CD (BCD), top CD (TCD), and SiO2 wall sidewall angle (SWA) parameters. The diagrams confirm that accurate structural modelling allows the extraction of reliable structural parameters by OCD analysis, in a fast and non-destructive way.

The HM sidewall angle, for example, is a key parameter, as it significantly influences the shape of the final SiC trench. Knowing this value allows us to be aware of whether the desired structure has been achieved and whether it is worthwhile to proceed with the SiC trench formation process.

[picture]

Fig. 5. Trench BCD, TCD, and Wall SWA - relationship between SEM and OCD analysis results.

Fig. 5. Trench BCD, TCD, and Wall SWA - relationship between SEM and OCD analysis results.

3.2 OCD analysis of SiC trench samples with an oxide mask on top

In this case as well, the comparison was performed at three different points on the wafer. The measured and simulated spectra at one measurement points are shown in Fig. 6. This OCD model is built from a total of 6 trapezoids to describe the shape of the SiC trench wall and that of the remaining HM oxide on top and redeposited on the wall. Similar to the HM trench, very good agreement was observed between the structure obtained from the OCD analysis and that derived from the SEM images (Fig. 8.). The shape of the trench also closely follows the form observed in the electron microscopy image (Fig. 7.).

[picture]

Fig. 6. Measured and fitted reflectance spectra of SiC trench with an oxide mask on top.

Fig. 6. Measured and fitted reflectance spectra of SiC trench with an oxide mask on top.

[picture]

Fig. 7. SEM image and trench structure resulting from the OCD evaluation -SiC trench with an oxide mask on top.

Fig. 7. SEM image and trench structure resulting from the OCD evaluation -SiC trench with an oxide mask on top.

[picture]

Fig. 8. Trench BCD , TCD , and oxide mask TCD - relationship between SEM and OCD analysis results.

Fig. 8. Trench BCD , TCD , and oxide mask TCD - relationship between SEM and OCD analysis results.

3.3 Full wafer and micro-mapping of trench dimensions

OCD analysis enables fast evaluation of the structural parameters across the wafer at multiple measurement points. Fig. 9 shows the measured SWA, trench TCD, and height maps of the HM trench across the entire wafer. These maps provide insight into how the structure changes and where the desired trench shape has been successfully achieved.

[picture]

Fig. 9. Wall SWA, trench TCD, and HM height maps across the wafer −SiO2 hard mask trench on SiC.

Fig. 9. Wall SWA, trench TCD, and HM height maps across the wafer − S i O 2 hard mask trench on SiC.

In addition to the wafer-scale maps, it is also possible to scan specific regions of the wafer at a smaller scale, providing insight into structural variations at the microscale. Fig. 10. presents maps of the parameters shown in the wafer-scale maps but measured over a selected 3.4×2.4 mm region of the wafer using a 200μ m step size. This represents the active area of a single trench MOSFET device. Even within such a small region, the distribution of the parameters can be characterized, providing feedback for process control and verification.

[picture]

Fig. 10. Wall SWA, trench TCD, HM height maps with a 200μ m step −SiO2 hard mask trench on SiC.

Fig. 10. Wall SWA, trench TCD, HM height maps with a 200 μ m step − S i O 2 hard mask trench on SiC.

In a similar manner, the SiC trench wafer was also characterized using these approaches. The parameter distributions of trench TCD and height are shown at macro (Fig. 11) and micro (Fig. 12) scales in the following figures. The thickness of the residual oxide mask was roughly uniform on a millimeter scale, so only the full wafer map is presented for this parameter.

[picture]

Fig. 11. Trench TCD, trench height, and HM height maps across the wafer −SiO2 hard mask trench on SiC .

Fig. 11. Trench TCD, trench height, and HM height maps across the wafer − S i O 2 hard mask trench on SiC .

[picture]

Fig. 12. Trench TCD and trench height maps with a 200μ m step −SiO2 hard mask trench on SiC .

Fig. 12. Trench TCD and trench height maps with a 200 μ m step − S i O 2 hard mask trench on SiC .

4 Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Silicon carbide trench devices are fabricated in a multi-step process during which it is essential to monitor whether the structure is indeed forming according to the requirements.

We presented the evaluation of the structural parameters of two types of structures (hard mask trench on SiC substrate and SiC trench with a hard mask on top) using a non-contact, non-destructive and fast method. The results obtained from the OCD analysis for three sites were compared with electron microscope images taken at the same sites on the wafer.

OCD shows high sensitivity to structure details and the results show good correlation with the SEM parameter values proving the reliability of the OCD measurement. We presented wafer maps evaluated by OCD analysis to show the variation of parameters across the wafer, and we also investigated the parameter changes on the scale of a single device.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.89.pdf

Oleg Rusch, Kevin Brueckner and Tobias Erlbacher, Solid State Phenomena, 359, 193-200 (2024).

Xiaoyu Tan, Guoming Lin, Ankuan Ji and Yuanwei Lin, Materials Science in Semiconductor Processing, 188, 109172 (2025).

Tsunenobu Kimoto and James A. Cooper, Fundamentals of Silicon Carbide Technology (2014).

Morten Hannibal Madsen and Poul-Erik Hansen, Surf. Topogr.: Metrol. Prop., 4, 023003 (2016).

Richard Silver et al., Metrology, Inspection, and Process Control for Microlithography XXI, 6518, 65180U, (2007).

M. G. Moharam and Thomas K. Gaylord, J. Opt. Soc. Am., 71, 811-818 (1981).

John M. Jarem, Proc. SPIE 4467, Complex Mediums II: Beyond Linear Isotropic Dielectrics, (9 July 2001).

Thomas A. Germer and Heather J. Patrick, Proc. SPIE 7638, Metrology, Inspection, and Process Control for Microlithography XXIV, 76381F (2010).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 95-101

doi: 10.4028/p-4rcL7P

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-20

Accepted:
2026-03-08

Online:
2026-05-21

Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1057.95.pdf

Kyrylo Melnyk 1,a*, Arne Benjamin Renz 1,b, M. A. Yildirim 1,c, N. Iosifidis 1,d, Q. Cao 1,e, J. Ortiz Gonzalez 1,f, V. A. Shah 1, g, J. A. Gott 2, h, P. M. Gammon 1,i and Marina Antoniou 1,j

1 University of Warwick, Coventry, United Kingdom

2 Warwick Manufacturing Group, Coventry, United Kingdom

a*Kyrylo.Melnyk@warwick.ac.uk, b Arne.Renz@warwick.ac.uk, c Mustafa.Yildirim@warwick.ac.uk, d Nikos.losifidis@warwick.ac.uk, e Q.Cao.2@warwick.ac.uk, f J.A.Ortiz-Gonzalez@warwick.ac.uk, 9 Vishal.Shah@warwick.ac.uk, h J.Gott@warwick.ac.uk, iP.M.Gammon@warwick.ac.uk, j  Marina.Antoniou@warwick.ac.uk

Keywords: superjunction, semi-superjunction, planar MOSFET, body diode, reverse recovery.

Abstract

This study investigates static and dynamic behavior of a 3.3 kV semi-Superjunction (SJ) MOSFET, compared with a conventional planar MOSFET. The semi-SJ was designed using a costeffective trench side-wall implantation and SiO2 refill fabrication method and evaluated through TCAD simulations. The optimized semi-SJ MOSFET designs, reduces Ron by 19% and increases BV by 500 V compared with the planar MOSFET, while maintaining a comparable reverse recovery charge ( QRR ). The proposed semi-SJ design demonstrated the best RON×QRR figure of merit (17.8 mΩ·μC), outperforming the conventional planar MOSFET design ( 19.7 mΩ·μC ).

Introduction

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The 4H−SiC MOSFETs are widely adopted in industrial and automotive applications due to their superior efficiency and performance compared with Si IGBTs [1]. In the 3.3 kV voltage class, further improvements in device performance can be achieved through Superjunction (SJ) technology, which lowers on-state resistance (Ron) while enabling higher breakdown voltage (BV) [2]. However, the introduction of alternating n - and p -pillars increases output capacitance [3-5], make it essential to assess SJ devices not only in terms of static performance but also dynamic behaviour such as reverse recovery.
In inverter and converter systems, the intrinsic body diode of the MOSFET can replace an external freewheeling diode, offering system-level cost benefits [6,7]. A drawback, however, is that thirdquadrant operation of the body diode may induce bipolar degradation, such as stacking fault expansion driven by electron-hole recombination [8]. While recent advances in 1.2 kV and 3.3 kV devices have helped mitigate this concern [6], reverse recovery remains an important performance factor. Schottky diodes have been shown to suppress reverse recovery effectively, with reductions in turn-on losses of up to 45% reported for the 3.3 kV class [7], but this improvement comes at the expense of an additional device component. Moreover, experimental studies on trench MOSFETs with full and semi-SJ structures, fabricated through multi-epitaxy and p-implantation, indicate that SJ concepts can increase reverse recovery charge ( QRR ) compared to conventional non-SJ devices [4,5].
This work investigates the body diode and reverse recovery behavior of a 3.3 kV semi-SJ MOSFET compared with a conventional planar MOSFET using TCAD. The proposed device is designed using a cost-effective trench etching and side-wall implantation method, without requiring multiple epitaxy steps and with only two additional implantation schedules compared with the planar process [2,9].

Design Description

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[picture]

Fig. 1. Schematic of the (a) planar and (b) semi-SJ designs; (c) SEM image of the fabricated planar MOSFET active area.

Fig. 1. Schematic of the (a) planar and (b) semi-SJ designs; (c) SEM image of the fabricated planar MOSFET active area.

The proposed semi-SJ design (Fig. 1 (b)) is based on the fabricated 3.3 kV planar MOSFET, with dimensions and SEM of the active area shown in Fig. 1 (a) and (c). The planar MOSFET features a 32.5μ m epitaxial layer doped at 3×1015 cm−3 and a simulated 1.5μ m JFET region at 8×1015 cm−3. All structures feature a 6.6μ m cell pitch, 50 nm gate-oxide, and 0.7μ m channel length (Lch). The JFET width (Wsfet) is 1.8μ m in the planar device and adjusted to 1.4μ m in both semi-SJ designs. Additionally, the deep trench opening and depth are 2.8μ m and 6.9μ m, incorporating 0.25μ m sidewall and 0.5μ m bottom p-implants. The trench dimensions are based on the process developed in [9] with the tilt angle ( θ) of 6∘. The semi-SJ also includes an n-type charge-balance layer ( NCB ), varied between 2×1016 cm−3 and 3×1016 cm−3 as an optimization parameter.

On-State and Off-State Performance

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[picture]

Fig. 2. (a) Measured and simulated on-state characteristics of the conventional planar MOSFET; simulated planar and semi-SJ MOSFET: (b) on-state comparison and (c) transfer comparison.

Fig. 2. (a) Measured and simulated on-state characteristics of the conventional planar MOSFET; simulated planar and semi-SJ MOSFET: (b) on-state comparison and (c) transfer comparison.

The room-temperature on-state characteristics of the conventional 3.3 kV planar MOSFET are shown in Fig. 2 (a) for VGS =18 V and 15 V , with the simulated TCAD results. The conventional planar device achieves Ron of 64 mΩ (measured) and 57 mΩ (simulated). Compared to the simulated planar MOSFET, the semi-SJ designs achieve Ron of 46 mΩ(−19%) and 44 mΩ(−23%) for NCB=2×1016 cm−3 and 3×1016 cm−3, respectively, as shown in Fig. 2 (b). All simulated designs were calibrated to a

[picture]

Fig. 3. (a) Side-wall p-type doping concentration versus BV; EF distribution at 3.3 kV : (b) planar, (c) semi-SJ ( NCB=2×1016 cm−3,5×1017 cm−3 side-wall), (d) semi-SJ ( NCB=3×1016 cm−3, 7×1017 cm−3 side-wall).

Fig. 3. (a) Side-wall p-type doping concentration versus BV; EF distribution at 3.3 kV : (b) planar, (c) semi-SJ ( N C B = 2 × 10 16 c m − 3 , 5 × 10 17 c m − 3 side-wall), (d) semi-SJ ( N C B = 3 × 10 16 c m − 3 , 7 × 10 17 c m − 3 side-wall).

measured threshold voltage ( VTH ) of 3 V at 9 mA , with transfer characteristics shown in Fig. 2 (c). The side-wall implantation doping concentration as a function of breakdown voltage (BV) for the semi-SJ designs is shown in Fig. 3 (a). The simulated off-state performance of the conventional planar MOSFET is 4 kV , which is denoted as the dashed line in Fig. 3 (a). In comparison, the semi-SJ design with the NCB=2×1016 cm−3 achieves BV of 4.5 kV when the side-wall doping concentration is 5×1017 cm−3, while the design with NCB=3×1016 cm−3 achieves BV of 4.4 kV when the side-wall doping concentration is 7×1017 cm−3. Additionally, the semi-SJ MOSFET with NCB=2×1016 cm−3 maintains BV above 4 kV over a wider implantation range ( 4×1017−7×1017 cm−3 ), while the NCB=3×1016 cm−3 design has a slightly narrower implantation window ( 6×1017−8×1017 cm−3 ).
The electric field (EF) distributions of planar and semi-SJ designs are shown in Fig. 3(b)-(d). The trench angle required for side-wall implantation in semi-SJ designs introduces a charge imbalance above and below the trench midpoint [2,10]. Therefore, as illustrated in Fig. 3 (c) and (d), the n-type layer becomes charge overcompensated below the trench midpoint, shifting the maximum EF toward the trench-bottom p-type implant, with the effect becoming stronger at higher n-top doping concentrations ( NCB=3×1016 cm−3 ).

Third-Quadrant Performance

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The measured reverse conduction of the fabricated 3.3 kV planar MOSFET is shown in Fig. 4 (a) for Vgs values between -5 V and 0 V . As reported in [1,11], third-quadrant conduction below Vth is a combination of the MOS channel, the body diode, and the parasitic BJT current components. At Vds =−3 V and VGS=0 V, the lower conduction voltage drop indicates that current is primarily unipolar, enabled by the body effect and positive fixed charge ( QF ) at the SiC/SiO2 interface. This is confirmed by the current distribution in Fig. 4 (b) and (d) simulated with the QF=7×1011 cm−2, which shows high electron density conduction through the channel. At VDS=−3 V and VGS=−5 V, the simulated electron and hole distribution in Fig. 4 (c) and (e) shows that electron current through the parasitic npn BJT dominates, while a smaller hole component is injected at the body diode junction to provide the base drive (see Fig. 4 (c)) [11].
The simulated reverse conduction at VGS=0 V and -5 V for the semi-SJ structures, compared with the planar benchmark, are shown in Fig. 5 (a) and (b). At VGS=−5 V, the semi-SJ device exhibits

[picture]

Fig. 4. (a) Measured body diode reverse conduction characteristics; hole current density (VDS=−3 V) : (b) VGS=−5 V and (c) VGS=0 V; electron current density (VDS=−3 V) : (d)VGS=−5 V and (e) VGS=0 V.

Fig. 4. (a) Measured body diode reverse conduction characteristics; hole current density ( V D S = − 3 V ) : (b) V G S = − 5 V and (c) V G S = 0 V ; electron current density ( V D S = − 3 V ) : ( d ) V G S = − 5 V and (e) V G S = 0 V .

[picture]

Fig. 5. Simulated third-quadrant characteristics at VGS : (a) 0 V , (b) -5 V ; Hole density distribution at VDS=−4 V and VGS=−5 V : (c) planar, (d) semi-SJ ( NCB=2×1016 cm−3 ), (e) semi-SJ (NCB=3×1016 cm−3).

Fig. 5. Simulated third-quadrant characteristics at V G S : (a) 0 V , (b) -5 V ; Hole density distribution at V D S = − 4 V and V G S = − 5 V : (c) planar, (d) semi-SJ ( N C B = 2 × 10 16 c m − 3 ), (e) semi-SJ ( N C B = 3 × 10 16 c m − 3 ) .

the highest forward voltage (VF) drop, reaching 4.3 V at 50 A , compared with 3.7 V for the planar device. A similar trend is observed at higher current densities when VGS=0 V. The reduced conductivity modulation in the semi-SJ design is confirmed by the simulated hole current density distributions in Fig. 5 (c-e), where significantly fewer holes are injected into the drift region compared to the planar MOSFET. Reducing the NCB to 2×1016 cm−3 improves reverse conduction, lowering the VF to 4.1 V at 50 A and potentially improved reverse recovery performance.
Body Diode Reverse Recovery Performance

To evaluate the dynamic performance of the

[picture]

Fig. 6. Simulated output capacitance (Coss) of planar, semi-SJ and full-SJ designs.

Fig. 6. Simulated output capacitance (Coss) of planar, semi-SJ and full-SJ designs.

behavior.
The body diode performance was simulated using a double-pulse test at 1.7 kV and the load inductance of VDS=400 V, with results shown in Fig. 7 (a) and (b). Note, that parasitic source and drain inductances were set as 5 nH and 10 nH , respectively. The high-side switch was biased at p−n and the gate resistance of the low-side switch ( VDs=50 V ) was set to NCB=2×1016 cm−3 and 3×1016 cm−3. The simulated diode forward current ( 68μH ) was fixed at 27 A .

[picture]

Fig. 7. Simulated planar and semi-SJ MOSFET reverse recovery current at: (a) VGS=−5 V, RG 5 V and (b) 15Ω.

Fig. 7. Simulated planar and semi-SJ MOSFET reverse recovery current at: (a) V G S = − 5 V , R G 5 V and (b) 15 Ω .

Table 1. Reverse recovery characteristic of planar and semi-SJ designs.

Parameter: | Planar | Semi-SJ (NCB=2×10¹⁶ cm⁻³) | Semi-SJ (NCB=3×10¹⁶ cm⁻³)
| RG=15Ω | RG=5Ω | RG=15Ω | RG=5Ω | RG=15Ω | RG=5Ω
tRR (ns) | 63 | 37.3 | 42 | 31.4 | 42 | 32.7
QRR (nC) | 357 | 346 | 417 | 386 | 507 | 463
IRRM (A) | 9.6 | 13.8 | 16.1 | 19.6 | 20.2 | 23.3
dIRR/dt (kA/μs) | 0.25 | 1.1 | 1.1 | 2.6 | 1.8 | 3.5
ESW (μJ) | 512 | 437 | 577 | 523 | 730 | 648

The summary and comparison of switching characteristics can be seen in Table 1, where the SemiSJ shows a comparable reverse recovery charge ( 5Ω ) compared to a conventional planar MOSFET. For IF, the planar device results in the RG=15Ω of 346 nC , while the semi-SJ with the VGS= shows the RG=5Ω, VGS=−5 V of 386 nC , corresponding to a QRR increase. Increasing the RG=5Ω concentration to QRR in the Semi-SJ structure leads to a NCB=2×1016cm−3 increase in QRR compared to the planar device.
Additionally, the semi-SJ designs show higher peak reverse current and steeper dIRR/dt during recovery, due to increased stored charge and capacitance. These results are consistent with previous reports on SiC SJ MOSFETs [4,5], where the increased pn-junction area increases Coss (see Fig. 6) and increases the reverse recovery losses.
Based on the 10% figure of merit with NCB switching results, the semi-SJ with 3×1016 cm−3 offers a balanced trade-off 30%, outperforming the planar MOSFET design QRR(463nC) and offering lower fabrication cost compared to other SJ technologies. The comparison between static and dynamic performance of all investigated devices is summarized in Table 2.

Table 2. Static and dynamic performance comparison between conventional and semi-SJ designs.

Parameter: | Planar | Semi-SJ (NCB=2×10¹⁶ cm⁻³) | Semi-SJ (NCB=3×10¹⁶ cm⁻³)
RON (mΩ) | 57 | 46 [- 19 %] | 44 [- 23 %]
BV (kV) | 4 | 4.5 [+ 12.5 %] | 4.4 [+ 10 %]
Implantation window (cm⁻³) | - | 4-7×10¹⁷ | 6-8×10¹⁷
RON× QRR (mΩ.μC) | 19.7 | 17.8 | 20.3

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.95.pdf

This work investigated the third-quadrant conduction and reverse recovery behavior of a 3.3 kV semiSJ design, with static characteristics benchmarked against a fabricated planar MOSFET. The optimized semi-SJ device achieved a balanced trade-off between conduction and switching performance. With an n-top ( RON×QRR ) doping concentration of RG=5Ω, the optimized semi-SJ reduced Ron by NCB=2×1016cm−3 and increased the maximum BV by 500 V compared with the planar MOSFET. This design also achieved the best (17.8 mΩ·μC) figure of merit at (19.7 mΩ·μC), outperforming the planar device with the Ron NCB of 2×1016 cm−3. These results demonstrate that semi-SJ devices, designed with a cost-effective side-wall implantation fabrication method, provide a promising solution for high-voltage SiC MOSFETs with competitive static and body diode reverse recovery characteristics.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.95.pdf

R. Zhang et al., "Third Quadrant Conduction Loss of 19% SiC MOSFETs: Impact of Gate Bias Control," in IEEE Transactions on Power Electronics, vol. 36, no. 2, pp. 2033-2043, Feb. 2021.

M. Boccarossa et al., "A 3.3 kV SiC Semi-Superjunction MOSFET with Trench Sidewall Implantations," Micromachines, vol. 16, no. 2, p. 188, 2025.

G. W. C. Baker et al., "Optimization of 1700-V 4H-SiC Semi-Superjunction Schottky Rectifiers With Implanted P-Pillars for Practical Realization," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1924-1930, April 2022.

S. Harada et al., "First Demonstration of Dynamic Characteristics for SiC Superjunction MOSFET Realized using Multi-epitaxial Growth Method," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2018, pp. 8.2.1-8.2.4.

M. Baba et al., "Ultra-Low Specific on-Resistance Achieved in 3.3 kV -Class SiC Superjunction MOSFET," 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Nagoya, Japan, 2021, pp. 83-86.

J. Qian et al., "An investigation of body diode reliability in commercial 1.2 kV SiC power MOSFETs with planar and trench structures,"Micromachines, vol. 15, no. 2, p. 177, 2024.

M. A. Karout et al., "Impact of Diode Technology on the Switching Performance of 3.3 kV SiC MOSFETs," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 108-111.

W. Cao et al., "SiC superjunction MOSFET with Schottky diode for improving short-circuit and reverse recovery ruggedness," Micro and Nanostructures, vol. 191, p. 207847, 2024.

Q. Z. Cao et al., "Device fabrication of SiC superjunction trench MOSFETs with Schottky diode using ICP and RIE processes," Materials Science Forum, vol. 1159, pp. 21-29, Sep. 2025.

K. Melnyk et al., " 3.3 kV 4H-SiC Trench Semi-Superjunction Schottky Diode With Improved ON-State Resistance," in IEEE Transactions on Electron Devices, vol. 71, no. 9, pp. 55735580, Sept. 2024.

Y. Chen et al., "Novel Cell-Level Insights into Third Quadrant Current Paths of Power SiC MOSFET," 2024 IEEE Energy Conversion Congress and Exposition (ECCE), Phoenix, AZ, USA, 2024, pp. 6754-6758.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 103-110

doi: 10.4028/p-bGig86

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-08

Accepted:
2026-01-31

Online:
2026-05-21

An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

Giorgian Borca-Tasciuc 1,a* and T. Paul Chow 1, b

¹Rensselaer Polytechnic Institute, Troy, New York 12180, U.S.A.

a*borcag2@rpi.edu, b chowt@rpi.edu

Keywords: analytical modeling, reverse recovery, P-i-N diodes.

Abstract

We generalize a recent Si P-i-N reverse-recovery (RR) model to more accurately capture 4H-SiC diode behavior by adding deep-acceptor-limited anode injection, strong recombination (due to >100 x shorter optimized high-level lifetimes compared to Si ), and improved modeling of the depletion layer dynamics. Closed-form expressions for the growth of the depletion layer are derived, enabling analytical estimates for QRR, tRR, and JPR. The model is validated against Sentaurus RR simulations of optimized 4H-SiC P-i-N diodes spanning BV =6−17kV and di /dt=10 A/μs−10kA/μs, achieving an average reduction in error of >90% for estimations of key switching performance parameters (QRR,tRR,JPR). By correctly capturing the dependence of QRR on di/dt, the model enables better estimates for the high-level lifetime ( τHL ) directly from the RR waveforms. The differential form enables straightforward utilization of the model to analyze non-idealized RR waveforms. Overall, the generalized model reveals a more favorable QRR−VF trade-off than implied by the unmodified Si model and improves first-order device optimization prior to full design.

Introduction

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Bipolar P-i-N junction diodes have a distinct BV-VF trade-off compared to unipolar Schottky diodes due to conductivity modulation, in which the concentration of mobile carriers in the drift region can be increased well beyond the background doping. 4H-SiC P-i-N diodes are expected to have a lower VF than 4H-SiC Schottky barrier diodes past 10 kV . Recent advancements in reducing the lifetimekilling Z1/2 defect and in suppressing the bipolar degradation phenomenon have eliminated some of the major impediments to realizing optimized 4H−SiCP−i−N diodes [1,2]. However, bipolar devices have a trade-off between the static and dynamic performance, as the on-state losses can be reduced at the expense of increasing the switching losses through an increase in QRR by increasing the degree of conductivity modulation. The total loss is minimized by trading off between the two losses. An analytical model allows a good first-order optimization of this trade-off before further refinement.
In [3], an analytical model is recently proposed to model the dynamics of SiP−i−N diode reverse recovery (RR) and estimate key switching performance parameters such as QRR, the snappiness factor tB/tA, and the reverse recovery time tRr. However, several material aspects of SiC limit the applicability of this model: (1) the necessity of using deep acceptors reduces the injection efficiency of the anode, and (2) carrier recombination significantly reduces QRR due to the >100x reduction in the optimized high-level lifetime compared to Si . We thus generalize the model in [3] in order to increase its applicability to include SiC. We have evaluated the improvement in our model by performing simulations and evaluating the reduction in error obtained by the new model compared to the model in [3], and obtained substantial improvements in accuracy. The model indicates (and simulations confirm) that 4H−SiCP−i−N diodes have an improved BV−VF trade-off than implied by the previous model. Our new model is expected to have applicability in enabling the design of competitive SiC P-i-N diodes and in improving the estimation of material parameters from the RR waveform.

Methodology

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On-State.

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Due to Aluminum being a deep-acceptor in 4H−SiC,<10% of electrically active acceptors are ionized at room temperature (RT). The space-charge neutrality equation can be used to determine the free hole concentration:

p+ND+−n−NA−=0

where:

p=NVexp−EF−EVkT,n=NCexp−EC−EFkT,NA−=NA1+gAexpEA−EFkT,ND+=ND1+gDexpEF−EDkT

An acceptable approximation of the solution to this transcendental equation for the hole-density in anode is given by:

p0P+=Nζ2(1+4NANζ−1)

where:

Nζ=NVexpEA−EVkT

Equivalent expressions can be obtained for the free electron concentration n0N+ in the cathode, with EA−EV replaced by EC−ED, and NA replaced by ND which will give satisfactory approximations if 100% donor activation cannot be assumed. Bandgap narrowing is modeled by assuming that:

EA−EV=ΔEA0−αNA13

The parameter of interest is average carrier concentration na in the drift region. Using [3], this can be written as:

JF=JSP+n(−d)2+2qnadτHL+JSN+n(+d)2JSP+=qDnP+p0P+LnP+tanh(WP+LnP+)JSN+=qDpN+n0N+LpN+tanh(WN+LpN+)

DnP+,DpN+ are the diffusion coefficients in the anode and cathode; LnP+,LpN+ are the diffusion lengths in the anode and cathode; and WP,WN are the thicknesses of the anode and cathode, respectively. The thickness and high-level lifetime of the drift region is given as t=2d and τHL. n(−d) and n(+d) are the plasma concentration at the anode and cathode, and are given by the catenary carrier distribution:

n(x)=τHL2qLa(cosh(xLa)sinh(dLa)−Bsinh(xLa)cosh(dLa))

Where La=DaτHL is the ambipolar diffusion length in the drift region, and B=μn−μpμn+μp.

Thus, given the forward current density and the structural and material parameters of the P−i−N diode, the plasma carrier concentration na can be derived.

[picture]

Fig. 1. Effect of aluminum acceptor level on (a) hole concentration and (b) anode injection efficiency.

Fig. 1. Effect of aluminum acceptor level on (a) hole concentration and (b) anode injection efficiency.

[picture]

Fig. 2. Schematic representation of the drift region and modeled parameters during reverse recovery.

Fig. 2. Schematic representation of the drift region and modeled parameters during reverse recovery.

Dynamic Switching.

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Figure 2 gives a schematic overview of the parameters solved by the dynamic switching equations. During the RR, holes are extracted at the anode and electrons are extracted at the cathode. The growth of the depletion region at the P+side is due to electrons in the plasma moving towards the cathode, leaving behind a depletion layer in which the holes are extracted towards the anode at saturation velocity. Given the small nature of dn(x)dx in the plasma, it can be assumed that electrons in the plasma are driven towards the cathode by drift. As the total current is given by:

J=JF−at=q(μn+μp)n(x,t)E

We can approximate the electric field by assuming n(x,t)≈na(t) where na(t) is the average carrier density of the plasma at time t and thus derive:

E=JF−atqna(t)(μn+μp)

Thus, the electron current component, Jn=qμnnE becomes:

Jn=μnμn+μp(JF−at)n(x,t)na(t)

Again, assuming n(x,t)≈na(t), this simplifies to:

Jn=μnμn+μp(JF−at)

We now apply a charge control approach to derive dxndt. During an infinitesimal time step, the charge extracted at the boundary of the P+/n - depletion region with the plasma is:

Qn=Jndt=μnμn+μp(JF−at)dt

During this infinitesimal time step, the depletion region grew dxn. Thus, the charge removed, assuming n(x,t)≈na(t) is:

Qn=dxpqna(t)

This yields, for dxp/dt :

dxpdt=−μnμn+μpJF−atqna(t)

An acceptable approximation for na(t), the average plasma concentration within the region that remains conductivity-modulated, can be made by assuming that na(t) only changes through recombination. Thus, na(t)=nae−tτHL, where na is simply the static value of the average carrier concentration of the plasma in the on-state. This yields the final formula for the growth of the depletion region at the P+/n−region:

dxpdt=−μnμn+μpJF−atqnae−tτHL

Similar arguments made for the N+/n−depletion region yield:

dxndt=−μpμn+μpJF−atqnae−tτHL

[picture]

Fig. 3. Simulated depletion layer formation with μn/μp=2.5 along with model predictions.

Fig. 3. Simulated depletion layer formation with μ n / μ p = 2.5 along with model predictions.

An interesting observation is that this model predicts that the ratio of the depletion region widths xp/xn asymptotically approaches μn/μp, regardless of whether the diode is a P+−n−N+diode or a P+-p−N+diode. This effect can be seen in Figure 3, where RR was simulated with an exaggerated μn/μp to demonstrate the two-sided depletion formation.
The above-derived differential equations have the solution:

xp(t)=CpτHL[(JF+aτHL)(exp(t1,pτHL)−exp(tτHL))−a(t1,pexp(t1,pτHL)−texptτHL)],t>t1,pxn(t)=CnτHL[(JF+aτHL)(exp(t1,nτHL)−exp(tτHL))−a(t1,nexp(t1,nτHL)−texptτHL)],t>t1,n

Where Cp=μn(μn+μp)qna and Cn=μp(μn+μp)qna. The variables t1,p and t1,n denote when the depletion regions start growing at the P+/n−side and the N+/n−side, respectively. At t=t1,p, there is no voltage across the P+/n−junction, and equivalently for t=t1,n. Electric-field dependent mobilities, μn(E) and μp(E) can be used in the differential equations if the carriers in the plasma begin approaching their saturation velocity during the switching.

We now find the time t1,p and t1,n when the depletion region begins growing on each side. At time t1,p, the carrier concentration at the anode/drift-region boundary is 0 . Let b be the distance from the anode where the on-state equilibrium carrier concentration remains undisturbed. Then, at time t1,p current right at the anode is driven purely by diffusion. Using these assumptions and the previous derivations result in the following equations for the hole current exiting the anode at time t1,p, where γ=dndx|x=−d :

Jp(t1,p)=μpμn+μp(JF−at1,p)=qDPdndx≈qDpn(−d)−γbb

The total charge removed, utilizing the current zero-crossing t0=JFa and approximating the removed charge using a triangle, is:

Q1,P=∫t0t1,p(JF−at)dt=12bqn(−d)

Thus, two equations are derived for two unknowns, t1,p and b. Combining the two equations yield a rather unwieldly cubic polynomial, whose positive real root is the time the voltage across the P+/n− junction is equal to zero. Equivalent arguments yield t1,n. We utilize t1=min(t1,p,t1,n), as the moment the depletion layer begins growing on one side, the voltage will promptly cross zero.
We now have all the terms to derive a straightforward expression for the voltage supported across the P−i−N diode during the RR:

VAK(t)=VP(t)+VN(t)

Where VP(t) is the voltage supported across the P+/n−junction and VN(t) is the voltage supported across the N+/n−junction. Using Poisson's equation, VP(t) and VN(t) can be straightforwardly derived from xn(t) and xp(t) :

VP(t)=12ϵs(at−JFvsat,p+qND)xp(t)2VN(t)=12ϵs(at−JFvsat,n+qND)xn(t)2

The peak reverse current is obtained by solving for VAK(t2)=VS. To model the final phase of the RR , consider the charge remaining in the drift region once JPR is reached:

Qr≈qnaexp(−tτHL)(2d−xn(t2)−xp(t2)−hn−hp)

Here, hp and hn are the slopes of the carrier profile at the boundary of the P+/n−depletion region of the plasma, and at the boundary of the N+/n−depletion region and the plasma, respectively. The expression for these are derived from the diffusion current at the boundary of the plasma at time t2 :

Jn=μnμn+μpJPR=qDndndx≈qDnnaexp−tτHLhn

The expression for hp is equivalent. At this point, we assume that recombination is negligible in extracting the remaining charge. This is a justifiable assumption as once the large peak reverse current is reached, it becomes more efficient at removing charge than recombination. Our simulations confirm this assumption. A tail-like decay is still seen in the final phase of inductive switching, but this is due to the decay of the diffusion gradient as carriers exit the conductivity-modulated region, not due to carrier recombination. With this assumption in hand, we can write:

12JPRtb=Qr

And thus, the total reverse recovery charge, QRR can be written as:

QRR=12(t2+tb−t0)JPR

The expression for tb assumes a linear decay of the current from JPR to 0 . A satisfactory waveform for the current decay can be derived by assuming for t>t2 :

J(t)=JPRexp(−t−t2τb),t>t2

The current-decay time constant τb, capturing the effects of the decay of the gradients driving diffusion, can be defined using:

∫t2∞J(t)=Qr

[picture]

Fig. 4. Errors in model predictions for (a) QRR, (b) JPR, (c) tRR, and (d) t1. Error displayed in logscale.

Fig. 4. Errors in model predictions for (a) Q R R , (b) J P R , (c) t R R , and (d) t 1 . Error displayed in logscale.

Model Verification

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

TCAD Sentaurus is used to perform simulations in order to verify the model. Optimized 4H−SiC p-i-n diodes are designed with differing mid-region thicknesses varying from 50μ m to 150μ m by 25μ m increments, yielding breakdown voltages (BV) between 6 kV and 17 kV . Inductive-load RR simulations are performed on the optimized diodes, varying the ramp rate between 10 A/μs and 10kA/μs and the reverse voltage from 1/8 to 1/2 the BV. The key switching parameters ( QRR,sp,JPR, tRR,t1 ) are extracted and quantitatively compared with the model predictions using the prediction error (xtrue −xpredicted xtrue ). The mean absolute percentage error (MAPE) is used to aggregate the errors across the different switching reverse voltage. The model described in [3] is used as a baseline.
As is visible in Figure 3, the model makes substantial improvements over the Si RR model. Both JPR and QRR are accurate always accurate within 20% across the 60 tested scenarios and are almost always within 10%. The average errors are 8.8% for QRR ( 94% reduction), 3.7% for JPR ( 93% reduction), 9.2% for tRR ( 84% reduction), and 5.3% for t1 ( 90% reduction). This testifies to the degree of relative as well as absolute accuracy of the new model. Figure 4 provides a qualitative comparison of the new model, the simulation results, and the model described in [3].
The increase in the error of tRR with increasing ramp rate arises from the increased role of recombination in removing the remaining charge ( Qr ) in the final phase.

[picture]

Fi.
mulated waveforms vs model predictions.

Figure 5. Fi. mulated waveforms vs model predictions.

The new model can be used to make accurate QRR−VF curves, as is seen in Figure 6(a). Usage of the model in [3] provides an excessively pessimistic Qrr. Thus, the performance of the 4H−SiCP−i−N diode is significantly better than predicted by [3]. Figure 7(b) demonstrates that the model can also reproduce the dependence of QRR  on di/dt. The same τHL extracted in [4] using the slope of the IF−QRR  curve also gives a reasonable fit for the QRR−di/dt curve. As current waveforms during switching often deviate from the idealized form assumed for modeling, the differential forms can be used with J(t) substituting for JF−at when using the model for device characterization.

(a)

(b)

Table 1. Important parameters utilized in RR simulations.

EA0 | α | NA | ND | EC-ED | μn,max | μp,max
0.265eV[5] | 3.6E-8eV/cm | 1E19cm⁻³ | 1E19cm⁻³ | 0.1eV | 950cm²/V-s | 125cm²/V-s

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

We generalized the classical Si reverse-recovery framework presented in [3] by including reduced anode injection efficiency due to utilization of deep acceptors, recombination during RR, and twosided depletion growth. We utilize the model to predict RR in optimized 4H−SiCP−i−N diodes, deriving closed-form relations for depletion growth and analytical estimates of QRR, tRR, and JPR that match Sentaurus RR across BV=6−17kV and di/dt=10 A/μs−10kA/μs, reducing errors by >90% versus the unmodified Si model. The model predicts an improved Qrr−VF trade-off than the previous model, extending the regions in which 4H−SiCP−i−N diodes become competitive. The model reproduces the dependence of QRR on di/dt seen in empirical RR measurements. The differential form of the model enables utilization of the model with a measured (non-idealized) RR current waveform to analyze the stored charge in the drift region. Thus, the model expands the viable design space for SiC P-i-N diodes by guiding τHL and drift-layer sizing against VF−QRR and can be utilized to obtain additional insight into measured RR waveforms, accelerating device design and characterization.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.103.pdf

M. Kato, O. Watanabe, T. Mii, H. Sakane, S. Harada, "Suppression of stacking-fault expansion in 4H−SiC PiN diodes using proton implantation to solve bipolar degradation," Sci. Rep. 12 (2022) 18790.

T. Okuda, G. Alfieri, T. Kimoto, J. Suda, "Oxidation-induced majority and minority carrier traps in n- and p-type 4H-SiC," Appl. Phys. Express 8 (2015) 111301.

B.J. Baliga, Fundamentals of Power Semiconductor Devices, 2nd ed., Springer, Cham, 2019.

K. Nakayama, S. Ogata, T. Hayashi, T. Hemmi, A. Tanaka, T. Izumi, K. Asano, D. Okamoto, Y. Tanaka, T. Mizushima, M. Yoshikawa, H. Fujisawa, K. Takenaka, M. Takei, Y. Yonezawa, K. Fukuda, H. Okumura, "High voltage and fast switching reverse recovery characteristics of 4H-SiC PiN diode," Mater. Sci. Forum 778-780 (2014) 841-844.

A. Koizumi, J. Suda, T. Kimoto, "Temperature and doping dependencies of electrical properties in Al-doped 4H-SiC epitaxial layers," J. Appl. Phys. 106 (2009) 013716.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 111-118

doi: 10.4028/p-Xxkc5I

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-08

Accepted:
2026-02-26

Online:
2026-05-21

Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

Giorgian Borca-Tasciuc 1,a*, Reza Ghandi 2, b, Collin W. Hitchcock 2,c and Tat-Sing Paul Chow 1, d

¹Rensselaer Polytechnic Institute, Troy, New York 12180, U.S.A

2 GE Aerospace Research, Niskayuna, New York 12309, U.S.A.

ab  borcag2@rpi.edu, b  ghandi@ge.com, c  collin.hitchcock@ge.com, d  chowt@rpi.edu

Keywords: Reverse Recovery, Dynamic Breakdown, Charge-Balance, Superjunction

Abstract

We report an anomalous reverse-recovery (RR) of the body diode in a 3.3kV4H−SiC superjunction (SJ) DMOSFET: at 77 K , QRR,sp increases by 1.4×−3.5× versus room temperature and 5× versus 195 K , and JPR increases by >2×, while trRR changes by only <30 ns. A clear dependence of QRR,sp on the ramp rate at 77 K indicates the QRR,sp is not due to additional depletion charge. Currentcontrolled negative resistance (CCNR) is also observed solely for the SJ body diode at 77 K . The voltage waveforms strongly suggest the additional QRR,sp is due to dynamic breakdown of the SJ due to transient charge imbalance of the pillars caused by delayed hole emissions of the deep acceptors. The anomalous behavior is qualitatively reproduced in simulation. We also benchmark a 3.3 kV Charge Balance (CB) 4H-SiC DMOSFET along with the SJ device from 77-423 K using an inductive double-pulse test. For T>77 K the switching for both devices is dominated by the depletion capacitance (weak QRR,sp dependence on the ramp rate): the SJ device turns off faster ( tRR=0.3−0.8× CB ), is snappier ( tB/tA=0.23−0.56×CB ), and shows larger JPR(1.8−2.8×CB) while recovering less charge ( QRR,sp=0.4−0.8×CB ). The CB device shows the expected increase of QRR,sp with temperature and only modest tRR temperature variation. Overall, the CB device provides softer, predictable RR without a cryogenic anomaly, whereas SJ delivers the shortest trRR above 77 K but exhibits the 77 K anomalous increase and is consistently snappier.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

The 4H−SiC power DMOSFET has emerged as a competitive alternative to Si equivalents due to the wide bandgap of 4H−SiC enabling thinner drift regions and higher doping for the same breakdown voltage, leading to a dramatic reduction in Ron,sp. While a wide bandgap enables the large critical electric field that makes 4H−SiC competitive for unipolar devices, it also leads to a higher on-state voltage for bipolar devices, including the 4H−SiC DMOSFET integral body diode. Additionally, the 4H-SiC DMOSFET body diode exhibits certain undesirable switching characteristics. While demonstrating a much-faster reverse recovery (RR) than Si body diodes, they tend to exhibit increased snappiness which can lead to large voltage overshoots and increased power loss [1]. Thus, the antiparallel body diode inherently present in all DMOSFETs is often shorted by a Schottky diode in switching applications of the 4H−SiC DMOSFET, increasing costs.
Charge balance (CB) and superjunction (SJ) drift layers improve the on-state performance of the 4 H SiC DMOSFET by improving the trade-off between BV and Ron,sp [2,3]. However, the improved onstate performance enabled by the CB and SJ drift-layer can be counteracted by degraded RR performance, as observed in the Si SJ integral diode, where excessive oscillations are caused by rapid changes of the SJ capacitance with voltage [4]. Knowledge of the RR characteristics is therefore required in order to evaluate the trade-offs of different power MOSFETs in circuit applications.
This study evaluates and compares the RR performance of the body diodes of GE (General Electric) 3.3kV4H−SiCCB and SJ DMOSFETS, from liquid nitrogen temperatures up to 423 K . The static performance of the DMOSFETs have previously been characterized in [5]. An anomalous RR is consistently observed for the SJ DMOSFET at 77 K . A mechanism for the observed anomalous RR is hypothesized and simulated.
Methodology

[picture]

Fig. 1. Full-Cell Cross-Section of CB and SJ Vertical DMOSFETs

Fig. 1. Full-Cell Cross-Section of CB and SJ Vertical DMOSFETs

Devices and structures. Inductive RR measurements are performed on GE 3.3kV4H−SiC chargebalance (CB) and superjunction (SJ) DMOSFETs packaged in TO-247. Full-cell cross-sections for the conventional (Conv), CB, and SJ vertical DMOSFETs are shown in Figure 1. The CB architecture is implemented through intermittent shallow Al implants interleaved with the growth of a 12μ mn type epitaxial layer ( 1×1016 cm−3 ) to form buried charge-balance regions that act as electric-field dividers, enabling higher drift-layer doping at a fixed breakdown voltage. Intermittent vertical P-type "bus" pillars ( 12μ m depth) are realized via high-energy Al implantation ( >20MeV ) to tie the buried CB layers to the P+source/anode for hole supply. The SJ device employs alternating vertical P- and N-type pillars ( 5μ m pillar width) formed with the same high-energy implantation approach; pillar dopings are 1×1016 cm−3. Both CB and SJ stacks are scalable to higher voltage ratings. For the 3.3 kV DMOSFETs studied here, the drift region thickness is 24μ m.

[picture]

Fig. 2. Schematic reverse recovery switching waveforms and the associated performance parameters [6]

Fig. 2. Schematic reverse recovery switching waveforms and the associated performance parameters [6]

Temperature control. Cryogenic data are taken in liquid nitrogen ( 77 K ) and in a dry-ice/isopropanol bath ( 195 K ). High-temperature (HT) measurements use a temperature-controlled hot plate at 423 K (150∘C). Devices are soaked at the setpoint prior to testing to ensure thermal equilibrium.

Inductive reverse-recovery setup. RR of the body diode is characterized with a standard inductive double-pulse circuit. An 18 mH inductor is used as the load. The gate and source of the 4H−SiCSJ or CB DMOSFET are shorted and the body diode is used as the freewheeling diode. The RR waveform is measured at the start of the second pulse. Duty cycles of <1% are used to minimize device selfheating. Given the differing device areas, a current density ( JF=50 A/cm2 ) is targeted. The pulse width is set in order to achieve the target JF. The ramping rate ( di/dt ) is varied by varying the external gate resistance between 0Ω,50Ω, and 100Ω of the bottom transistor. Lead lengths are minimized in order to minimize parasitic inductance. Switching parameters are extracted according to Figure 2.

Experiments and Results

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

[picture]

Fig. 3. Sample RR Current Waveforms for 4H−SiCSJ(a) and CB (b) body diodes.

Fig. 3. Sample RR Current Waveforms for 4 H − S i C S J ( a ) and CB (b) body diodes.

Switching Characteristics. Excluding the SJ cryogenic anomaly at 77 K , both CB and SJ body diodes exhibit capacitance-dominated reverse recovery over 77 K−423 K and VR=0.5−1kV at JF=50Acm−2.QRR,sp has only a weak dependence on dJ/dt (Figure 4a), consistent with conventional 4HSiC body diodes where an implantation-damage "tail" near the junction limits the lifetime and causes minority carriers to recombine before they can be extracted, leaving the depletion charge extraction to dominate the RR waveform [1,7]. In this regime the 4H-SiC SJ body diode does not exhibit the excessive oscillations reported for the Si SJ body diode [4]. The fast minority carrier recombination in the damage layer of the implanted pillars suppresses the pre-depletion current build-up that produces the oscillations due to a large di/dt once the pillars pinch off. This is clearly seen in Figure 10 as the SJ begins supporting significant voltage only 10−20 ns after the current-zero crossing, indicating the current almost immediately consists of extracted depletion charge. Consistent with increasing minority carrier lifetime with temperature, Figure 4 b shows that the CB diode demonstrates the expected increasing QRR,sp with temperature, whereas the temperature trend of the SJ diode remains relatively flat, indicating that the switching remains capacitance dominated even at higher temperatures. A minority carrier charge extraction component begins to be detectable for the CB diode at 423 K , as indicated by the slight positive slope of QRR,sp vs dJ/dt at 423 K . Finally, the best snappiness characteristics for both diodes is seen at room temperature (Figure 7).

Comparison. Above 77 K , the SJ device generally exhibits faster turn-off, with the SJ exhibiting a tRR0.3x−0.8x that of the CB (Figure 9). The larger tRR of the CB device is expected due to increased resistance from the P -bus tying the charge sheet layers together introducing a larger RC time constant. As expected, the SJ is consistently snappier than the CB device, with a tB/tA of about 0.23x−0.56x that of the CB device. This is expected as the pillars must fully pinch-off before significant voltage can be supported, leading to a large drop in capacitance. The same mechanism drives the larger JPR(1.8x− 2.8 x ) of the SJ devices. Despite the larger JPR, the SJ exhibits a smaller QRR,sp than the CB, approximately 0.4x−0.8x that of the CB due to the smaller tRR. Interestingly, unlike the SJ , the CB
shows only minimal variation of switching time with temperature. These comparisons hold across the differing dJ/dt values caused by varying the external gate resistance of the bottom MOSFET in the DPT set-up.

[picture]

Fig. 4. QRR,sp dependence on dJ/dt (a) and temperature (b) for 4H−SiCCB and SJ Body Diode

Fig. 4. Q R R , s p dependence on d J / d t (a) and temperature (b) for 4 H − S i C C B and SJ Body Diode

Anomalous Cryogenic RR. At 77 K , the SJ body diode exhibits an anomalous increase in QRR,sp of 3.5 x compared to room temperature (RT) and 5 x relative 195 K . This behavior remains across multiple tested SJ devices. This is the opposite trend than what is expected from the well-documented trend of the minority carrier lifetime increasing with temperature. Thus, QRR,sp for the SJ becomes 1.9x-3.0x then that of the CB under matched conditions. The RR is no longer junction-capacitance dominated as QRR,sp has a clear dependence on the ramp rate in Figure 4. A larger slope of QRR,spvs reverse voltage at 77 K was also observed, indicating additional extracted charge besides the depletion charge. The increased QRR,sp remains clear even when JF is reduced to 20 A/cm2. In contrast, the SJ at 195 K shows an almost pure junction-capacitance dominated waveform, with QRR,sp remaining within 1% across the three different ramp rates. In Figure 8, a shallow voltage dip is consistently seen around ~200−300 V for the SJ at 77 K which is absent in the voltage waveforms taken at other temperatures.

[picture]

Fig. 5. Static I-V Characteristics for the 4H−SiCCB and SJ Body Diodes at various temperatures.

Fig. 5. Static I-V Characteristics for the 4 H − S i C C B and SJ Body Diodes at various temperatures.

CCNR Behavior in SJ. In the process of investigating the origin of the anomalous RR behavior of the SJ diode at 77 K , static I-V characterization was performed and are shown in Figure 5. A short pulse width ( 80μ s, for a duty cycle of 1.9% ) was used to minimize device self-heating. The turn-on knee increases at lower temperatures due to an increase in the junction barrier height as the Fermi level moves towards the band edges. Decreased acceptor ionization also induces a large series resistance in the diode. CCNR behavior is observed solely for the SJ device triggered at JF=50Acm−2. The current decay tail at the end of the second pulse is investigated to determine the operating point of the SJ device during switching and is shown in Figure 6a. No CCNR behavior is observed in the transient I-V of the SJ diode.

[picture]

Fig. 6. (a) The current decay curve through the 4H−SiCSJ body diode at the end of the second pulse (b) Extracted J-V characteristics from the current decay pulse.

Fig. 6. (a) The current decay curve through the 4 H − S i C S J body diode at the end of the second pulse (b) Extracted J-V characteristics from the current decay pulse.

Analysis and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

Switching Characteristics. The CB body diode addresses several shortcomings of the conventional 4H-SiC DMOSFET body diode while preserving the core advantage over Si. Turn-off remains capacitance-dominated and fast across the tested conditions ( tRR=~100−350 ns ), yet the recovery is markedly softer: at room temperature tB/tA can exceed 10 and, aside from 77 K , was greater than 1.4 in 9/9 RT scenarios tested and in 8/9 HT scenarios tested. The softer recovery reduces voltage overshoot and loss without sacrificing speed. Coupled with the CB drift region's improved Ron,spBV trade-off, this yields a device that combines better on-state performance with more benign reverse recovery, diminishing the need to short the CB body diode with a Schottky diode. Outside 77 K , the SJ body diode retains the same advantages of the conventional 4H−SiC body diode over Si diodes (fast turn-off and comparatively low JPR due to the capacitance-dominated switching) while still retaining the principal drawback of increased snappiness ( tB/tA>1.4 in only 9/15 RT scenarios tested and in 0/15HT scenarios tested). This snappiness limitation, however, is intrinsic to the SJ structure as it is due to the requirement of pillar pinch-off prior to significant voltage being supported. However, the 4H−SiC SJ does not suffer from excessive oscillations typical of Si SJ structures because the switching is depletion-capacitance dominated.
Comparison. The results favor the CB body diode for RR performance as it preserves fast, capacitance-dominated switching while remaining substantially less snappy than the SJ due to the lack of the pillar pinch-off constraint. It has a predictable temperature dependence, with QRR,sp increasing with temperature from 77 K−423 K, and almost no variation in switching time with temperature at matching conditions.

[picture]

Fig. 7. Dependence of snappiness on dJ/dt at various temperatures for the 4H−SiCCB and SJ Body Diodes.

Fig. 7. Dependence of snappiness on d J / d t at various temperatures for the 4 H − S i C C B and SJ Body Diodes.

[picture]

(b)

Figure 8. (b)

Fig. 8. Voltage waveforms during RR for 4H−SiC SJ Body Diode.

Anomalous Cryogenic RR. There are two possible sources for the additional QRR,sp observed in the SJ RR at 77 K . The additional extracted charge is either present before the RR is initiated (in the onstate) or is generated during the RR. The expected trend of decreasing lifetime with decreasing temperature predicts a reduction in stored minority carriers in the on-state (before initiation of RR) at 77 K compared to RT. The voltage zero-crossing temperature dependence (Figure 10) rules out a large increase in the stored minority carrier charge in the on-state, as such an increase would also increase t1 compared to RT. The measured decrease in t1 at 77 K compared to RT correlates with an expected lower lifetime at 77 K . Observing Figure 8, a consistent negative differential resistance (NDR) is observed around −VAK=200 V−300 V. NDR during RR has been previously observed in [8] and was attributed to dynamic breakdown. The breakdown voltage of the SJ rapidly decreases with the degree of charge imbalance [9]. While in [8], dynamic breakdown was caused by large transient current densities significantly modifying the background doping, the current densities in this case cause only a <0.01% modification in pillar doping. Rather, [9] reveals a plausible mechanism. For the SJ to support voltage, both the p -pillar and the n -pillar need to deplete. Depletion of the p -pillar is driven by hole emission of the acceptors. Due to the deepness of the Al acceptor level in 4H−SiC, the hole emission time at 77 K can exceed the switching time scale. For optimally designed SJ pillars, the lateral electric field at pillar pinch-off (when significant voltage begins to be supported) is equal to the critical electric field. If the p -pillars remain undepleted due to the large hole emission time at 77 K , the local electric field can exceed the critical field, causing avalanching. Since the avalanching happens at a high-voltage and large current, it is accompanied with significant local self-heating. The local self-heating decreases the hole emission time and locally depletes the p-pillar, compensating the n -pillar and reducing the electric field below the critical field. The large local electric field also decreases hole emission time through the Poole-Frenkel effect. Thus, destructive breakdown is avoided through negative feedback as the large electric fields leading to avalanching also create the condition to deplete the p -pillar and reduce the local electric field by compensating the donors in the n-pillar.

[picture]

Fig. 9. Dependence of the reverse recovery time ( tRR ) on dJ/dt at various temperatures for the 4 H SiC CB and SJ body diode.

Fig. 9. Dependence of the reverse recovery time ( t R R ) on d J / d t at various temperatures for the 4 H SiC CB and SJ body diode.

Simulations. We investigate our hypothesis by performing RR simulations of the 4H−SiC SJ DMOSFET using TCAD Sentaurus. Figure 11a shows the RR simulation of the SJ at 300 K as a baseline. In Figure 11b, a large ( >100x ) increase is seen in IPR when modeling the acceptors as traps located 0.2 eV above the valence band with σn=σp=1E−15 cm−2 and using the default Sentaurus PooleFrenkel model. Figure 11c reproduces the NDR characteristic seen in the SJ RR at 77 K , but the diode is no longer capable of turning off. When self-heating effects are also included (Figure 12), all observed characteristics are reproduced: (1) a large increase in QRR,sp compared to room temperature, and (2) an NDR dip during the RR. The simulations are only a qualitative reproduction, as IRP exceeds 100 A in the simulation. However, doping significantly reduces the thermal conductivity of 4H−SiC [10], especially at low temperature where the undoped thermal conductivity reaches a peak, and this effect was not modeled. A reduced thermal conductivity enhances self-heating and reduces the switching time and IRP of the simulated SJ body diode.

[picture]

Fig. 10. Temperature Dependence of the voltage zero-crossing time ( t1 ) at various reverse voltages.

Fig. 10. Temperature Dependence of the voltage zero-crossing time ( t 1 ) at various reverse voltages.

[picture]

Fig. 11. Simulated RR of 4H−SiC SJ Body Diode. (a) 300 K RR (b) 77 K RR, including temperature and electric-field hole emission time of acceptors (c) Same as (b), but including avalanche generation.

Fig. 11. Simulated RR of 4 H − S i C SJ Body Diode. (a) 300 K RR (b) 77 K RR, including temperature and electric-field hole emission time of acceptors (c) Same as (b), but including avalanche generation.

[picture]

Fig. 12. Simulated RR characteristics of 4H−SiC SJ Body Diode including self-heating effects and electric-field and temperature-dependent hole emission time for acceptors. (a) RR waveform, (b) Maximum temperature inside device during RR.

Fig. 12. Simulated RR characteristics of 4 H − S i C SJ Body Diode including self-heating effects and electric-field and temperature-dependent hole emission time for acceptors. (a) RR waveform, (b) Maximum temperature inside device during RR.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

RR is characterized for 3.3kV4H−SiC SJ charge-balance CB DMOSFET body diodes from 77−423 K using an inductive double-pulse. For T>77 K, both are capacitance-dominated: SJ turns off faster ( tRR=0.3−0.8×CB ), is snappier ( tB/tA=0.23−0.56×CB ), and shows larger JPR ( 1.8−2.8× CB ) while recovering less charge ( QRRsp=0.4−0.8×CB ). CB remains fast ( tRR≈100−350 ns ), has softer recovery ( tB/tA>1.4 in essentially all non-cryogenic cases), and follows a predictable temperature trend ( Qrr,sp increases with T with modest trrr variation). At 77 K the SJ shows an anomalous RR: QRR,sp increases by 1.4×−3.5× vs room temperature and 5× vs 19 K , JPR increases by >2×, and tRR changes by <30 ns; QRR,sp also regains sensitivity to ramp rate and VR and persists at JF=20 A/cm∧2 (vanishing by 7.5 A/cm2 ). Static I-V shows current-controlled negative resistance (CCNR) only for the SJ at 77 K , but transient decay during RR does not; we therefore have no evidence that CCNR directly causes the anomalous QRR,sp. TCAD including deep-acceptor emission and field/temperature-assisted effects qualitatively reproduces the cryogenic trends. Overall, CB is the safer default across temperature (fast, soft, predictable; no cryogenic anomaly), while SJ offers the shortest tRR above 77 K at the cost of higher snappiness and a 77 K charge increase.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.111.pdf

Z. Wang, J. Zhang, X. Wu, K. Sheng, Evaluation of reverse recovery characteristic of silicon carbide MOSFET intrinsic diode, IET Power Electron. 9 (2016) 969-976.

R. Ghandi, et al., Deep Implanted SiC Super-Junction Technology, presented at ICSCRM 2024, Raleigh, NC, USA, Sept. 29-Oct. 4, 2024.

R. Ghandi, et al., 4.5 kV SiC charge-balanced MOSFETs with ultra-low on-resistance, in: Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), 2020, pp. 126-129.

P. Xue, G. Fu, Analysis of the reverse recovery oscillation of superjunction MOSFET body diode, Solid-State Electron. 129 (2017) 81-87.

Z. He, C.W. Hitchcock, R. Ghandi, S. Kennerly, T.P. Chow, Comparative performance evaluation and analysis of high-voltage superjunction, charge-balanced and conventional 4 H SiC DMOSFETs at cryogenic and high temperatures, in: Proc. Int. Symp. Power Semicond. Devices ICs (ISPSD), 2025.

B.J. Baliga, Fundamentals of Power Semiconductor Devices, second ed., Springer, Cham, 2019, pp. 249-255.

S. Chowdhury, C.W. Hitchcock, R. Dahal, I. Bhat, T.P. Chow, Current-controlled negative resistance in high-voltage p-i-n rectifiers, IEEE Trans. Electron Devices 64 (2017) 897900.

M. Domeij, Transient breakdown in 4H-SiC p-i-n diodes, Solid-State Electron. 44 (2000).

N. Donato, F. Udrea, Static and dynamic effects of the incomplete ionization in superjunction devices, IEEE Trans. Electron Devices 65 (2018) 4469-4475.

R. Wei, S. Song, K. Yang, et al., Thermal conductivity of 4H-SiC single crystals, J. Appl. Phys. 113 (2013) 053503.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 119-124

doi: 10.4028/p-wV3ZEX

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-21

Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

Marvin Gloth a*, Drinas Kelmendi b, Hamed Azimi c, Benjamin Weigt d and Tobias Erlbacher e 

Nexperia, Stresemannallee 101, 22529 Hamburg, Germany

a  Marvin.Gloth@nexperia.com, b  Drinas.Kelmendi@nexperia.com, c  Hamed.Azimi@nexperia.com, d Benjamin.Weigt@nexperia.com, e Tobias.Erlbacher@nexperia.com

Keywords: Silicon Carbide, Deep Oxide Traps, Tunneling, Body Diode, Dynamic Conduction, Sub-Threshold Regime, Flat-Band Voltage Shift

Abstract

This paper investigates the dynamic conduction behavior of silicon carbide (SiC) MOSFETs in the sub-threshold regime. We demonstrate that controlled gate bias preconditioning, combined with time-resolved electrical measurements in thermal equilibrium, reveals a notable drift in the source-drain voltage Vsd. The direction of this drift depends on the polarity of gate preconditioning and is directly related to variations in the channel conduction. These effects are shown to be attributed to charge release from deep oxide traps, leading to a gradual shift in the flatband voltage ( Vfb ) over time. Experimental results reveal that these dynamic effects are most prominent in the depletion and weak inversion regimes. Our findings highlight the influence of oxide trap dynamics on the body diode forward voltage ( Vf ) and its significance for the reliability of SiC devices, specifically in its role as the temperature-sensitive parameter.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

Despite their revolutionary characteristics, SiC MOS-FETs exhibit unique challenges, particularly related to sub-threshold conduction, as well as their correlation to Vf. Previous studies have shown that Vf, as a temperature-sensitive electrical parameter (TSEP), exhibits pronounced time dependence [1,2] and is further affected by the applied gate bias [3]. This dynamic Vf may lead to inaccuracies in junction temperature estimation, causing over- or under-stress conditions during reliability tests. To illustrate this effect, Fig. 1 shows an example where the cooling curve of the body diode in a discrete SiC-MOSFET was measured at different Vgs after being subjected to identical heating conditions through the active channel. The results reveal that the temperature response during cooling significantly differs between measurements, demonstrating that the influence of gate bias cannot be neglected. Huerner et al. [4] investigated the influence of gate voltage on the forward conduction properties of the body diode. The study showed that the current path through the channel remained significant even for gate voltages below the threshold voltage, creating an additional conduction path in parallel to the body diode. Their simulations further demonstrated that once the MOSFET enters depletion, the current through the channel becomes negligible and primarily flows through the body diode. However, the sub-threshold conduction and its correlation to the body-diode characteristics remain largely unexplored.

[picture]

Fig. 1. Junction temperature cooling curve at different Vgs for a chiller temperature of Tc=25∘C

Fig. 1. Junction temperature cooling curve at different V g s for a chiller temperature of T c = 25 ∘ C

Experimental Setup and Findings

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

To systematically analyze the dynamic conduction behavior, a Keysight B 1505 parameter analyzer with the circuit configuration shown in Fig. 2 was used. A set of tests as shown in Tab. 1 was defined for these investigation. In Phase 1 (Pre-Conditioning), the SiC MOSFETs were subjected to controlled gate bias Vgs,pre, to reach either strong inversion or strong accu-mulation. After Phase 1, the gate bias was switched to different Vgs, meas  values, each initiating a voltage

[picture]

Fig. 2. Measurement circuit for measuring the dynamic conduction behavior

Fig. 2. Measurement circuit for measuring the dynamic conduction behavior

monitoring phase (Phase 2). During this phase, a measurement current of 10 mA is continuously applied from source to drain to measure Vsd. This measurement current was chosen sufficiently small to make self-heating negligible. Multiple products from different manufacturers and different design technologies, including planar MOSFETs, trench MOSFETs with PN junctions, and planar MOSFETs incorporating embedded Schottky junctions (MPS), were used for these investigations. For represen-tation comparison, two device types - a planar MOSFET with a PN junction and a planar MOSFET with an MPS structure- were selected.

Table 1. Test Plan for measuring the dynamic conduction behavior

Phase 1: Pre-Conditioning | Phase 2: Voltage-Monitoring | Measurement Current
mode | Vgs,pre | time | Vgs,meas | time | Im
strong Inversion | +15 V | 60 s | -10 V...+10 V | 1000 s | 10 mA
strong Accumulation | -15 V | 60 s | -10 V...+10 V | 1000 s | 10 mA

Fig. 3a shows the response measured at Vgs, meas =−3 V for the two preconditioning modes outlined in Tab. 1. These graphs reveal several key observations: First, Vsd is clearly time-dependent, with the largest shift in ΔVsd occurring at the transition from Phase 1 to Phase 2. Then the signal gradually converges to a steady-state value, exhibiting time constants of up to τ≈160s.

[picture]

Fig. 3. (a) Dynamic reverse-conduction response after different gate-preconditioning voltages at -3 Vgs, meas  (b) ΔVsd after different gate preconditioning at various gate voltages.

Fig. 3. (a) Dynamic reverse-conduction response after different gate-preconditioning voltages at -3 V g s , meas (b) Δ V s d after different gate preconditioning at various gate voltages.

Interestingly, the preconditioning bias defines the drift direction, which exhibits an inverse settling behavior. However, the conduction levels ultimately converge to a common steady-state value, independent of the initial conditions. Comparing ΔVsd with Cgs within the defined Vgs, meas  range from the Tab. 1 reveal a direct correlation to the channel conduction regimes, as shown in Fig. 3b. The dynamic effects are most pronounced during channel depletion and weak inversion, while they are considerably less significant under strong inversion and accumulation, as indicated by the Cgs curves. Furthermore, the direction of the voltage sweep in the capacitance measurement introduces a hystere-sis effect. Similarly, another hysteresis is evident in the ΔVsd measurements, depending on the applied preconditioning. The amplitude of ΔVsd is lower when the device is preconditioned in inversion com-pared to preconditioning in accumulation.

These findings indicate that the underlying mechanism in the dynamic Vsd cannot be explained solely by the body diode and is somehow linked to the MOS capacitor behavior. Therefore, mechanisms like self-heating and deep-level bulk crystal defects, can be excluded based on our measurements. Thus the behavior is related to an additional current path through the channel [4].

Flat-band voltageVsdShift

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Fig. 4 illustrates a simplified representation model of the parallel conduction paths through the body diode and the channel. In this configuration, the channel conduc-tion is determined by the charges controlled through the MOS-capacitor and its electrostatics. Therefore, the flat-band voltage ( Vfb ) at the SiC/SiO2 interface must now be taken into account. Eq. (1) defines the relation between Vfb and the built-in potential ( Vbi ) as a function of the metal/polysilicon work function ( Φm ), the semiconductor work function ( Φs ), and the trapped charges within the oxide ( −Qox ,t/Cox  ). Any shift in Vfb directly influences the threshold voltage and, consequently, the degree of channel conduction.

[picture]

Fig. 4. Simplified representation model

Fig. 4. Simplified representation model

Vfb=−Vbi=Φm−Φs−Qox,tCox(1)

According to Kang et al.[5] the trap charge related flat-band voltage shift can be expressed as ΔVfb by Eq. (2).

ΔVfb=−Qox,tCox=−1Cox∫0toxxttoxρ(x)dx→ΔVfb(t)∝Q(0)Coxe−tτ(2)

Based on this relation, the shift in ΔVfb settles exponentially. This shift induces a corresponding variation in threshold voltage ( ΔVth  ), which reflects a change in channel resistance ( ΔRch ), and thus influences the source-drain voltage (ΔVsd). To quantify the average variation of Vfb as a function of ΔVsd, Figure 5 compares Vsd at t=0 s and t=6 s for various gate-source voltages ( Vgs ). For simplicity, it is assumed that Vsd has reached steady state after 6 s , such that the vertical difference at a given Vgs corresponds to ΔVsd.

[picture]

Fig. 5. Sub-threshold behavior at the beginning and end of the Vds(Vgs) measurement at Im=10 mA. It shows rendering trap dynamics due to Vth  and PN-conduction properties. Zoom shows the average sub-threshold shift due to hole release and the resulting Vfb shift.

Fig. 5. Sub-threshold behavior at the beginning and end of the V d s ( V g s ) measurement at I m = 10 m A . It shows rendering trap dynamics due to V th and PN-conduction properties. Zoom shows the average sub-threshold shift due to hole release and the resulting V f b shift.

At the same time, at a fixed Vsd, the horizontal gap represents a ΔVgs. This ΔVgs shift is timedependent and reflects the dynamics of the MOS capacitor, which are governed by trap dynamics expressed as ΔVfb. The magnitude of the shift allows for an estimation of the amount of trap charges participating in the dynamic response, providing a visual representation of Eq. (2). Furthermore, the slope of the curves provides insight into sensitivity of the channel to charge changes at the gateoxide. This behavior demonstrates the proportional correlation between gate charge and channel conductance in this regime.

Another observation indicates that for gate voltages exceeding the Vth , the channel enters strong inversion, thereby reducing the sensitivity of conduction to shifts in Vfb. Once Vsd reaches the forward voltage of the PN/MPS junction, variations in the flat-band voltage become less pronounced, as the measurement current flows primarily through the body diode. The impedance of the body diode is dominating the depleted channel. This effect may occur even before accumulation of the channel and is particularly pronounced in MOSFETs with an integrated MPS junction.

Trap Dynamics Mechanics

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As discussed in the previous section, the observed behavior of Vsd is driven by trap dynamics that affect the channel conduction. Kang et al. [5] attributed this trap dynamics to the presence of deep ox-ide traps exhibiting long tunneling time constants. The time constants are governed by the tunneling probability, which is, in turn, strongly dependent on the spatial position of the trap within
the oxide. Traps located deeper in the oxide, i.e., farther from the SiC/SiO2 interface, exhibit significantly longer time constants than those near the interface, rendering them more difficult to detect during transient or fast measurements. Thicker oxides further exacerbate this effect, as the reduced tunneling probability for deeply embedded trap states results in more pronounced charge release over prolonged times. The following Eq. (3) provides a quantitative description of this phenomenon [6]. ΦB,h―,Ec,Et,mox* and ms* represent the discontinuity between semiconductor and oxide, reduced Planck constant, conduc-tion band edge, trap energy level, effective electron masses in the oxide and in the semiconductor, respectively.

τ(x)=mox*22x(1+12η1x)2π2η2h¯2Dite2η1x with η12=2mox*(ΦB+Ec−Et)h¯2,η22=2ms*(Ec−Et)h¯2(3)

The analysis of trap dynamics indicates that the observed signal at Fig. 3a cannot be adequately represented by a single time constant. A deconvolution-based approach, applied across the temperature range, did not result in conclusive and reliable estimations of the activation energies associated with the participating trap states. Nevertheless, the extracted mean time constant of τ≈160 s suggests that the tunneling probability of deep traps appears to dominate the overall time constant of the observed dynamic effect.

After a positive preconditioning, the oxide gradually releases holes, leading to a decreased channel depletion. Conversely, after a negative preconditioning, negative charges are released, increasing the channel depletion. Fig. 3a illustrates the dynamic reverse conduction behavior response and the presence of both deep positive and negative oxide traps at −3 Vgs, meas  for positive (+15 V) and negative (−15 V) preconditioning respectively. The switching trap behavior dependence on the preconditioning voltage shows similar signatures attributed to dipole oxygen vacancies (e.g., Eγ4t centers) [7].

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

This work investigates the dynamic conduction of SiC MOSFETs in the sub-threshold regime under conditions of low reverse current and thermal equilibrium. Gate-bias preconditioning is shown to induce inverted drifts in Vsd(t), which converge toward a common steady state. The effect is most pronounced during channel depletion and weak inversion, consistent with the observed correlation between Vsd(t) and Cgs(VGs). The behavior is attributed to time-dependent flat-band shifts (Vfb(t)) arising from trap dynamics in the oxide. A characteristic time constant of τ≈160 s was extracted, indicating tunneling from traps located deep within the oxide. In regimes of strong inversion or strong depletion, the sensitivity to Vfb shifts diminishes, rendering the drift negligible. Alternative explanations such as self-heating or deep bulk crystal defects were systematically excluded. These findings carry practical implications for reliability assessment and for temperature sensing based on the diode forward voltage ( Vf ) as a TSEP: preconditioning and relaxation times must be carefully controlled or compensated to avoid bias in junction-temperature estimation. Future work will focus on the quantitative extraction of trap energy and depth distributions through extended temperature sweeps and complementary techniques (e.g., charge pumping, DLTS, scanning capacitance), as well as on assessing process and oxide-thickness dependencies to mitigate the observed drift.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.119.pdf

M. Noah, et al. "Dynamic calibration: How to properly estimate junction temperature in SiC MOSFETs subject to body diode voltage shift. "Proceedings of the 14th Int. Conference on Inte-grated Power Electronics Systems (CIPS), Düsseldorf 2024.

J. Breuer, et al. "Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling - a Dynamic Approach. "Proceedings of the 14th Int. Conference on Integrated Power Electronics Systems (CIPS), Düsseldorf 2024.

F. Kato, S. Sato, K. Koui, H. Tanisawa, H. Hozoji and H. Yamaguchi, "Study of Gate Bias Volt-age for Preventing Threshold Shift of SiC-MOSFET Body Diode during Transient Temperature Measurements," 2019 International Conference on Electronics Packaging (ICEP), Niigata, Japan, 2019, pp. 88-91

A. Huerner, et al. "Analytical model for the influence of the gate-voltage on the forward conduction properties of the body-diode in SiC-MOSFETs. "Proceedings of the International Con-ference on Silicon Carbide and Related Materials, ICSCRM 2017 Trans Tech Publications Ltd, 2018. 901-904

C. J. Kang, et al. "Charge trap dynamics in a SiO 2 layer on Si by scanning capacitance microscopy, Appl. Phys. Lett. 74, 1999. 1815-1817

R. E. Paulsen, R. R. Siergiej, M. L. French and M. H. White, "Observation of near-interface oxide traps with the charge-pumping technique," in IEEE Electron Device Letters, vol. 13, no. 12, pp. 627-629, Dec. 1992

C. J. Nicklaw, et al. "The Structure, Properties, and Dynamics of Oxygen Vacancies in Amorphous SiO2", IEEE Transactions on Nuclear Science, vol. 49, no. 6, Dec. 2002.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1057, pp 125-130

doi: 10.4028/p-m0gjDq

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-02-26

Online:
2026-05-21

Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1057.125.pdf

Ruei-Ci Wu 1,a, Kung-Yen Lee 2,3,b*, Pei-Chi Liao 2,c, Pei-Chun Liao 2,d, Jui-Chi Chu 2,e

1 SiCEV Electronics Co., Ltd, Taiwan

2 Graduate School of Advanced Technology, National Taiwan University, Taiwan

3 Department of Engineering Science and Ocean Engineering, National Taiwan University, Taiwan

a  ricky_wu@sicev.com.tw, b  kylee@ntu.edu.tw, cr13k  43003@ntu.edu.tw, d  d13k44005@ntu.edu.tw, er13k43039@ntu.edu.tw

Abstract

This study demonstrates that the output capacitance ( Coss  ) of a 4H−SiC MOSFET is proportional to the length of JFET ( LJFET  ) at a low Vds , since under this condition, the gate-to-drain capacitance ( Cgd ) may account for nearly half of Coss . Furthermore, when Vds is low, the Coss  of MOSFETs with square and hexagonal cell topologies is approximately 20% and 25% higher than that of MOSFETs with the strip cell topology, respectively, due to larger JFET areas. However, when Vds is higher, the Coss  of MOSFETs with square and hexagonal cell topologies is lower because of the lower drain-to-source capacitance ( Cds ) resulting from smaller Pwell areas. The split-gate MOSFET can reduce Cgd, but the smaller poly-gate area decreases the depletion capability, resulting in a higher Cds. As Ljfet of the MOSFET decreases, Cgd becomes lower, which may shorten the switching time, but due to the increased area of Pwell ( LPW ), the reverse recovery current ( IIr ) increases. This study proposes partially increasing the gate oxide thickness. Although this may slightly increase Cds, the shorter switching time results in a 5% reduction in the turn-on switching loss (Eon ).

Keywords: Cell topology, Split-gate MOSFET, Output capacitance ( Coss  ), Abrupt drop phenomenon, Switching losses

Introduction

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Coss  has a significant impact on the switching time and reverse recovery characteristics of MOSFETs [1], [2], [3]. Coss  consists of Cgd and Cds, and Cds consists of the sidewall and bottom capacitances of the Pwell ( CSw and CB ) [4], [5], as illustrated in Fig. 1. Therefore, the structure and topology of both the JFET and Pwell significantly influence Coss  [6], [7]. However, their correlation and mechanisms have not yet been sufficiently studied. When Vds is low, Coss  is dominated by Cgd and Csw. . At high Vds, the JFET is fully depleted, Cgd and Csw is saturated, and Coss  is then dominated by CBt [5], [8], [9]. Therefore, the area of the JFET and the sidewall of the P-well affect Coss  more significantly at low Vds, whereas the area of the bottom of P -well affects Coss  at high Vds. This study investigated the influences of the variation of LJFET  and LPW , as well as the split-gate structure on Coss . Accordingly, the Coss  of MOSFETs with strip, square, and hexagonal cell topologies was compared. Furthermore, turn-on time ( ton ), reverse recovery current ( Irr ), and turn-on energy loss ( Eon ) of the MOSFETs with different LJFET  and LPW  were obtained by the double pulse test (DPT) in this study.

[picture]

Fig. 1. Schematic and parasitic capacitances of the 4H−SiC MOSFETs in this study.

Fig. 1. Schematic and parasitic capacitances of the 4 H − S i C MOSFETs in this study.

Experimental

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The MOSFETs with strip, square, and hexagonal cell topologies were fabricated in this study, as shown in Fig. 2. The LJFET  and LPW  of the MOSFETs are listed in Table I. The concentrations of epitaxy and Pwell of the MOSFETs are approximately 8×1015 cm−3 and 2×1018 cm−3, respectively. For comparison, the split-gate MOSFET was also fabricated, with the spacing between adjacent poly gates being 1.0μ m. The forward and reverse Ids−Vds curves and capacitances of MOSFETs were measured by Keysight B1505A, whereas the DPT was simulated using TCAD software, Sentaurus.

[picture]

Fig. 2. The capacitances of MOSFETs with different cell structures and topologies. All the MOSFETs were fabricated in this study.

Fig. 2. The capacitances of MOSFETs with different cell structures and topologies. All the MOSFETs were fabricated in this study.

Table I. The structural parameters of MOSFETs fabricated in this study.

Topologies | Strip | Strip | Strip | Strip | Split-gate | Square | Hexagonal
mathematical formula | 2.4 | 2.2 | 2.0 | 2.2 | 2.2 | 2.4 | 2.4
mathematical formula | 6.5 | 6.5 | 6.5 | 5.0 | 5.0 | 6.5 | 6.5

Results and Discussions

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Fig. 3 shows that the on-resistance ( Ron ) of the hexagonal-cell and square-cell MOSFETs is approximately 21% and 10% lower than that of the conventional strip-cell MOSFET, respectively, because of the larger channel areas. Additionally, Fig. 4 shows that their breakdown voltages ( BV ) are nearly the same. According to Fig. 5, when Vds is low (less than 10 V ), Cgd represents approximately half of Coss  in the conventional strip-cell MOSFET, as indicated by the blue dashed and red dotted lines. In addition, since the abrupt drop occurs at a Vds of 10 V , this implies that the JFET is fully depleted at this point. Therefore, when Vds exceeds 10 V , both Cgd and CSw become saturated, and Coss  is dominated by CBt, as illustrated in Fig. 1.

As shown in Fig. 6, when Vds is low, Coss  decreases as LJFET  is shortened from 2.4μ m to 2.0μ m, due to a reduction in Cgd. When LJFET is shortened by 0.2μ m,Coss  decreases by 2%. However, as Vds increases, the difference between Coss  of the various MOSFETs becomes small. This is because Cgd decreases more rapidly than Cds, making its influence on Coss  less significant. After the abrupt drop, the Coss  of different MOSFETs are more consistent, because CBT  of each MOSFETs is similar.

[picture]

Fig. 3. The measured forward Ids−Vds curves of the MOSFETs with different cell topologies.

Fig. 3. The measured forward I d s − V d s curves of the MOSFETs with different cell topologies.

[picture]

Fig. 4. The measured reverse Ids−Vds curves of the MOSFETs with different cell topologies.

Fig. 4. The measured reverse I d s − V d s curves of the MOSFETs with different cell topologies.

[picture]

Fig. 5. The measured Ciss, Coss, and Crss (Cgd) of the conventional strip-cell MOSFET.

Fig. 5. The measured Ciss, Coss, and Crss (Cgd) of the conventional strip-cell MOSFET.

[picture]

Fig. 6. The measured Coss of the conventional strip-cell MOSFETs with different LJFET and LPW.

Fig. 6. The measured Coss of the conventional strip-cell MOSFETs with different L J F E T and L P W .

From Fig. 7, at a low Vds, the Coss of the square and hexagonal-cell MOSFETs are 20% and 25% higher than that of the strip-cell MOSFET, respectively, because of the higher Cgd resulting from the larger JFET area and higher CSw resulting from more sidewalls of Pwells. Nevertheless, after the abrupt drop, the Coss  of the square and hexagonal-cell MOSFETs becomes slightly lower than that of the strip-cell MOSFET, owing to their smaller P-well areas. Even though the difference in Coss  is relatively small, high-voltage switching can still cause considerable variations in space charge and significantly affect Irr . Additionally, it can be inferred that when Coss  is higher at low Vds , it may be lower at high Vds when the chip area of the MOSFET is fixed.

As shown in Fig. 8, Cgd can be reduced not only by shortening LJFET or decreasing the JFET area, but also by reducing the poly-gate area. Therefore, a split-gate MOSFET with the poly-gate length reduced by 1.0μ m exhibits a 28% reduction in Coss  at low Vds . However, a smaller poly gate reduces the depletion capability of the MOSFET, leading to a higher Cds. As a result, after Cgd saturates, the Coss  of the split-gate MOSFET may become higher than that of the conventional MOSFET, and the abrupt drop occurs later since the JFET should be fully depleted at a higher Vds.

According to Fig. 9, when LJFET  decreases, Cgd  is reduced, allowing the MOSFET to turn on more quickly. Therefore, the turn-on time ( ton ) is shortened. However, Irr may increase due to the larger Pwell area, which leads to a higher Cds. Hence, it can be concluded that there is a trade-off between ton and Irr. In addition, it is found that the MOSFET with LJFET and LPW of 2.2μ m and 6.5μ m, respectively, achieves an Eon  of about 8% and 6% lower than those of the other two MOSFETs with LJFET and LPW of 2.0μ m and 6.5μ m, and 2.4μ m and 6.5μ m, respectively, as shown in Fig. 9 .

[picture]

Fig. 7. The measured Coss of the MOSFETs with different cell topologies.

Fig. 7. The measured Coss of the MOSFETs with different cell topologies.

[picture]

Fig. 8. The measured Coss of the conventional and split-gate MOSFETs.

Fig. 8. The measured Coss of the conventional and split-gate MOSFETs.

[picture]

Fig. 9. The simulated turn-on waveforms of the MOSFETs with different structures during DPT.

Fig. 9. The simulated turn-on waveforms of the MOSFETs with different structures during DPT.

In this study, a novel MOSFET with partially thickened gate oxide is proposed, as shown in Fig. 10. This design lowers Cgd by reducing the gate oxide capacitance, yet it does not significantly affect Cds, since the depletion width of the P−N junction is maintained. As a result, the ton of the novel MOSFET is slightly shorter than that of the conventional MOSFET, whereas the Irr of both MOSFETs remains nearly the same, as shown in Fig. 11. Consequently, the Eon  of the novel MOSFET is reduced by 5% compared with that of the conventional MOSFET.

[picture]

Fig. 10. Schematic of the novel MOSFET with a partially thickened gate oxide.

Fig. 10. Schematic of the novel MOSFET with a partially thickened gate oxide.

[picture]

Fig. 11. The simulated turn-on waveforms of the conventional and novel MOSFETs during DPT.

Fig. 11. The simulated turn-on waveforms of the conventional and novel MOSFETs during DPT.

Summary

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Before the abrupt drop, Coss  is dominated by Cgd and Cds, whereas after the abrupt drop, it is dominated only by Cds because JFET is fully depleted. Hence, at low Vds, MOSFETs with a longer LJFET  or a larger JFET area, such as hexagonal-cell and square-cell MOSFETs, exhibit higher Coss . At higher Vds,Coss increases with the Pwell area. In addition, although the split-gate MOSFET can reduce Cgd , its inferior depletion capability not only delays the occurrence of the abrupt drop but may also lead to an increase in Cds.
Cgd and Cds depend on the areas of the JFET and P-well, respectively. Thus, a higher Cgd may correspond to a lower Cds. Furthermore, ton and Irr depend on Cgd and Cds, respectively. Consequently, a shorter ton results in a higher Irr. This indicates a trade-off between ton and Irr.

This study proposes a novel MOSFET with a partially thickened gate oxide, which shortens ton but ensures that Irr does not increase excessively. According to the simulation results, the Eon  of the novel MOSFET is 5% lower than that of the conventional MOSFET.

References

The original version of this paper is available on https://www.scientific.net/KEM.1057.125.pdf

H. Jiang, J. Wei, X. Dai, C. Zheng, M. Ke, X. Deng, Y. Sharma, I. Deviny and P. Mawby, "SiC MOSFET with Built-in SBD for Reduction of Reverse Recovery Charge and Switching Loss in 10-kV Applications," 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 2017, pp. 49-52, doi: 10.23919/ISPSD.2017.7988890.

J. Wei, M. Zhang, H. Jiang, X. Zhou, B. Li and K. J. Chen, "Superjunction MOSFET with Dual Built-In Schottky Diodes for Fast Reverse Recovery: A Numerical Simulation Study," in IEEE Electron Device Letters, vol. 40, no. 7, pp. 1155-1158, July 2019, doi: 10.1109/ LED.2019.2917556.

S. Jahdi, O. Alatise, R. Bonyadi, P. Alexakis, C. A. Fisher, J. A. Ortiz Gonzalez, L. Ran and P. Mawby, "An Analysis of the Switching Performance and Robustness of Power MOSFETs Body Diodes: A Technology Evaluation," in IEEE Transactions on Power Electronics, vol. 30, no. 5, pp. 2383-2394, May 2015, doi: 10.1109/TPEL.2014.2338792.

R. C. Wu, K. Y. Lee and P. C. Liao, "Adjustment of Abrupt Drops in the C-V Curves of Various 4H-SiC MOSFETs and JBS Diodes," IEEE Electron Device Letters, vol. 46, no. 2, pp. 135-138, 2025, doi: 10.1109/LED.2024.3522278.

R. C. Wu, K. Y. Lee, Y. Y. Wen and P. C. Liao, "The Correlation of the Drain-source Capacitance Variation and the P-pillar Structures in a Quasi Super Junction MOSFET," Materials Science in Semiconductor Processing, vol. 178, 108413, 2024, doi: 10.1016/j.mssp.2024.108413.

A. Agarwal, K. Han, and B. J. Baliga, "Impact of Cell Topology on Characteristics of 600 V 4HSiC Planar MOSFETs," IEEE Electron Device Letters, vol. 40, no. 5, pp. 773-776, 2019, doi: 10.1109/LED.2019.2908078.

H. Wu, H. Luo, J. Zhang, B. Zheng, R. Wang, and X. Chen, "Comparison and Analysis on Static and Dynamic Performance of SiC Planar MOSFETs with Different Cell Topologies," Materials Science in Semiconductor Processing, vol. 184, 108849, 2024, doi: 10.1016/j.mssp.2024.108849.

Z. Y. Ye, L. Liu, Y. Yao, M. Z. Lin and P. F. Wang, "Fabrication of a 650V Superjunction MOSFET with Built-in MOS-Channel Diode for Fast Reverse Recovery," in IEEE Electron Device Letters, vol. 40, no. 7, pp. 1159-1162, July 2019, doi: 10.1109/LED.2019.2915008.

S. Roy, A. Bhattacharyya, C. Peterson, S. Krishnamoorthy, " Lateral High-Permittivity Dielectric Superjunction Schottky Barrier Diode with Power Figure of Merit," IEEE Electron Device Letters, 43(12), 2037-2040, 2022, doi: 10.1109/LED.2022.3216302.

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Chapter 8: Design of SiC Power Devices

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 1-6

doi: 10.4028/p-9dcWT2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-15

Revised:
2026-01-21

Accepted:
2026-01-31

Online:
2026-05-19

Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

Marco Zignale 1,2,a, Patrick Fiorenza 1,b*, Lucia Calcagno 2,c, Marina Antoniou 3,d, Filippo Giannazzo 1,e, Fabrizio Roccaforte 1,f

1 CNR-IMM, Strada Ottava 5, 95121 Catania, Italy

2 Dipartimento di Fisica ed Astronomia, Università degli Studi di Catania, via Santa Sofia 64, 95121 Catania, Italy

3 School of Engineering, University of Warwick, Coventry, UK

a  marco.zignale@imm.cnr.it, b  patrick.fiorenza@imm.cnr.it, clucia.calcagno@ct.infn.it, d  marina.antoniou@warwick.ac.uk, efilippo.giannazzo@imm.cnr.it,  fabrizio.roccaforte@imm.cnr.it

Abstract

Silicon carbide ( SiC ) has emerged as a leading material for high-power applications. However, the high density of interface states (Dit) at the SiO2/SiC interface still constrains the performance and reliability of MOSFET devices. In this work, lateral 4 H -SiC MOSFETs subjected to post-deposition annealing (PDA) in nitric oxide (NO) of different durations were investigated through capacitance-voltage measurements, supported by an analytical model and an iterative MATLAB-based Dit  extraction algorithm. The results demonstrate that NO PDA effectively reduces Dit  not only near the conduction band edge but also towards the valence band, yielding improved channel mobility ( μFE ) and enhanced threshold voltage stability.

Keywords: silicon carbide, SiC, MOSFET, interface states, Dit.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

Silicon carbide has emerged as the reference material for high-power and high-voltage applications thanks to its superior physical properties. In 4H−SiC MOSFETs, these properties allow for enhanced voltage and current ratings as a consequence of the high critical electric field combined with intrinsically lower conduction resistance. A major challenge, however, arises from the relatively high density of interface states ( Dit ) at the oxide/semiconductor interface, which remains significantly larger with respect to Si . Interface states have been widely recognised as a critical factor that degrades fundamental device parameters, including the field-effect channel mobility ( μFE ) and the onresistance (RON)[1,2]. The impact of Dit  on conduction is strongly dependent on the processing of the SiO2/4H−SiC interface [3] and can be mitigated by post-oxidation annealing (POA) or post-deposition annealing (PDA) in NO ambient [4]. However, introducing nitrogen during PDA can create trapping states at the SiO2/4H−SiC interface, potentially negatively affecting the stability of the threshold voltage ( Vth  ) [5,6].

In this context, it is crucial to investigate the evolution of the Dit  not only near the 4H−SiC conduction band but also those close the valence band, as well as the near-interface oxide traps (NIOTs) that may form during prolonged PDAs in NO.

In this work, experimental and simulated capacitance-voltage ( C−V ) measurements were carried out on lateral MOSFETs subjected to PDAs of different duration in NO ambient [7], in order to investigate the electrical evolution of Dit  across the entire wide bandgap of the SiO2/4H−SiC system. Unlike MOS capacitors, which do not allow a complete evaluation of Dit  over the entire semiconductor band gap, lateral MOSFETs enable direct access to the full 4H−SiC band gap.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

This study is focused on lateral n -channel MOSFETs with the p -type body obtained by Al ion implantation into an n-type epitaxial layer with a doping concentration of approximately ND=9·1015 cm−3. The implantation process was optimised by adjusting both fluence and ion energy
to achieve a uniform doping profile within the body, resulting in a final concentration in the range of NA=2−3·1017 cm−3. The oxide layer was subsequently deposited by Low Pressure Chemical Vapour Deposition (LPCVD), with process parameters controlled to obtain an average thickness of about 55 nm , as confirmed by capacitance measurements of MOSFETs in the accumulation regime [7]. Postdeposition annealing (PDA) was then performed for different durations, specifically 10, 20, 50 and 120 minutes, with the aim of identifying an optimal processing window that maximises the passivation effect of the treatment while avoiding secondary effects, such as defect formation induced by prolonged exposure to high temperatures in a NO ambient.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

The MOSFETs were characterised by measuring capacitance-voltage ( C−V ) curves using a CASCADE Microtech probe station equipped with a Keysight B1505A parameter analyser. Figure 1 reports the C-V characteristics acquired at 1 kHz and room temperature, with the gate voltage swept from -20 V to +10 V , i.e. from accumulation to inversion.

[picture]

Fig. 1. C-Vs measured on the different MOSFETs subjected to different PDAs in NO.

Fig. 1. C-Vs measured on the different MOSFETs subjected to different PDAs in NO.

As shown in Figure 1, increasing the duration of NO annealing modifies the slope of the C−V curves. Although the overall shape of the experimental curves remains similar, differences emerge in the positive gate voltage region, where a progressive increase in the slope can be observed as the annealing time extends from 10 to 120 minutes. This behaviour indicates the effectiveness of postdeposition annealing in reducing the density of interface states near the conduction band. A corresponding shift of the minimum point of the C−V curves towards more negative gate voltages is also observed with increasing annealing duration. In addition, for gate voltages below -5 V , a slight variation in the slope can be observed, which may be attributed to changes in the interface states located close to the valence band. Taken together, these features suggest the evolution of the Dit  profile as a function of annealing in NO ambient.

Following the electrical characterisation of the MOSFETs, the density and distribution of interface states were evaluated using an analytical model. For this purpose, an in-house MATLAB algorithm was developed to extract the Dit  profile in MOSFET structures through an iterative procedure. The model, derived from the ideal C-V response of a MOS structure without interface states, accounts for their contribution as a function of energy level and density, thereby generating a modified C−V profile that reproduces the experimental data acquired. In particular, the model iterates on a set of pre-defined level with specific energy dispersion (exponential, Gaussian etc.) in order to achieve the best fit of the experimental C−V curves.

In order to simplify the analysis, the incorporation of traps was represented using analytical mathematical profiles such as Gaussian, exponential, or linear functions, which ensure mathematical continuity for any energy value within the bandgap and allow the construction of a trap density profile across the semiconductor band gap. As a reference for this modelling, discrete energy levels reported in the literature were incorporated, including bulk defects such as carbon clusters and silicon or carbon vacancies [8], as well as interface defects associated with the incorporation of NO molecules [9], as shown in Figure 2.

[picture]

Fig. 2. Discrete levels used to calculate the Dit profile in the whole SiO2 band gap.

Fig. 2. Discrete levels used to calculate the Dit profile in the whole S i O 2 band gap.

These assumptions came from the hypothesis that the bulk semiconductor levels can be mirrored at the interface with the Dit  insulating layer.

To provide a detailed description of the adopted approach, Table 1 summarises the main characteristics of the interface states considered in the iterative simulation. Both the trap type (donor or acceptor) and the mathematical distribution used for their representation (Gaussian, uniform, or exponential) are reported, together with their corresponding energy position within the bandgap and their relative weight. These centres were then combined to construct the overall 4H−SiC profile, which was subsequently used to evaluate the modifications induced by PDA across the 4H−SiC band gap.

Table 1. Mathematical functions associated to each discrete level for the fitting of the 4H−SiC curves.

Trap Type | Distribution Shape | Energy Position (from EV) [eV] | Length [a.u.]
Donor | Gaussian | 0.2 | 0.1
Donor | Uniform | 0.3 | 0.3
Donor | Uniform | 0.6 | 0.6
Donor | Uniform | 1.1 | 0.4
Donor | Uniform | 1.5 | 0.4
Acceptor | Uniform | 2.4 | 1.8
Acceptor | Exponential | 3.26 | 0.19
Acceptor | Exponential | 3.26 | 0.03

The constructed trap profiles were incorporated into the ideal C-V response of MOSFETs, allowing close agreement with the experimental measurements. As a representative case, Figure 3
presents the fitting of the C-V curve measured after 120 minutes of PDA, obtained through the MATLAB iterative loop simulation with a trap profile specifically developed for this condition. The good agreement between experiment and simulation highlights the capability of the adopted model to capture the contribution of interface states across the C−V bandgap.

[picture]

Fig. 3. Example of an experimental Dit  curve ( 120 min of PDA ) fitted by the iterative MATLAB loop.

Fig. 3. Example of an experimental D it curve ( 120 min of PDA ) fitted by the iterative MATLAB loop.

In particular, the use of an exponential trap profile near the conduction band of the semiconductor has a significant impact on the charge accumulated in these interface states and, consequently, on the total capacitance of the device. At high trap densities, the charge stored in the trap energy levels becomes non-negligible, leading to an increase in capacitance at fixed gate bias values and resulting in a modification of the final C-V curve. Similarly, donor-like traps introduced near the valence band induce variations in the 4H−SiC characteristics, especially for gate bias values below -5 V .

By extending the analysis to all NO PDA durations, the variations induced by the different annealing times could be identified as is shown in Figure 4. The results show that increasing the annealing time in NO reduces the exponential tail of the μFE profile near the Vth  conduction band edge, while also decreasing the states located below the mid-gap and close to the valence band edge.

[picture]

Fig. 4. Dit profiles obtained on the different MOSFETs subjected to different PDAs in NO.

Fig. 4. Dit profiles obtained on the different MOSFETs subjected to different PDAs in NO.

These combined experimental and simulated findings are consistent with an enhancement of the field-effect channel mobility ( 4H−SiC ) and a reduction of μFE instability when the PDA is sufficiently long, as previously reported [10].

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

The results presented in this work demonstrate that NO PDA treatments induce a progressive reduction of interface states not only close to the Vth  conduction band edge but also near the valence band. This finding contrasts with earlier studies that reported a detrimental effect near the valence bandgap edge [11]. The combined experimental and simulated analyses further confirm that sufficiently long PDA durations lead to an enhancement of the 4H−SiC and a reduction of SiO2/4H−SiC instability. Nonetheless, achieving a reliable improvement in interfacial transport properties requires a fine control of the PDA conditions in order to maximise the beneficial passivation effect while avoiding the onset of secondary mechanisms that could reintroduce defects or compromise threshold voltage stability.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

This work is supported by Horizon EU Advances in Cost-Effective HV SiC Power Devices for Europe's Medium Voltage Grids (AdvanSiC) Project Grant number 101075709. Some authors acknowledge the project iENTRANCE@ENL funded by the European Union - NextGenerationEU.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.1.pdf

Cabello, M., Soler, V., Rius, G., Montserrat, J., Rebollo, J., & Godignon, P. (2018). Advanced processing for mobility improvement in 4H-SiC MOSFETs: A review. Materials Science in Semiconductor Processing, 78, 22-31.

Fiorenza, P., Giannazzo, F., Frazzetto, A., & Roccaforte, F. (2012). Influence of the surface morphology on the channel mobility of lateral implanted ( 0001 ) metal-oxidesemiconductor field-effect transistors. Journal of Applied Physics, 112(8).

Roccaforte, F., Fiorenza, P., Greco, G., Nigro, R. L., Giannazzo, F., Iucolano, F., & Saggio, M. (2018). Emerging trends in wide band gap semiconductors ( SiC and GaN ) technology for power devices. Microelectronic Engineering, 187, 66-77.

Fiorenza, P., Giannazzo, F., Cascino, S., Saggio, M., & Roccaforte, F. (2020). Identification of two trapping mechanisms responsible of the threshold voltage variation in MOSFETs. Applied Physics Letters, 117(10).

Yano, H., Kanafuji, N., Osawa, A., Hatayama, T., & Fuyuki, T. (2014). Threshold voltage instability in 4 H -SiC MOSFETs with phosphorus-doped and nitrided gate oxides. IEEE Transactions on electron devices, 62(2), 324-332.

Lelis, A. J., Green, R., Habersat, D. B., & El, M. (2014). Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs. IEEE Transactions on Electron Devices, 62(2), 316-323.

Fiorenza, P., Bongiorno, C., Giannazzo, F., Alessandrino, M. S., Messina, A., Saggio, M., & Roccaforte, F. (2021). Interfacial electrical and chemical properties of deposited SiO2 layers in lateral implanted 4 H -SiC MOSFETs subjected to different nitridations. Applied Surface Science, 557, 149752.

Kimoto, T., & Cooper, J. A. (2014). Fundamentals of silicon carbide technology: growth, characterization, devices and applications. John Wiley & Sons.

Shimizu, T., Akiyama, T., Nakamura, K., Ito, T., Kageshima, H., Uematsu, M., & Shiraishi, K. (2021). Reaction of NO molecule at interface: An ab initio study for the effect of NO annealing after dry oxidation. Japanese Journal of Applied Physics, 60(SB), SBBD10.

Fiorenza, P., Zignale, M., Camalleri, M., Scalia, L., Zanetti, E., Saggio, M., ... & Roccaforte, F. (2024). Impact of the NO annealing duration on the interface properties in lateral MOSFETs: The energetic profile of the near-interface-oxide traps. Materials Science in Semiconductor Processing, 169, 107866.

Chung, G. Y., Tin, C. C., Williams, J. R., McDonald, K., Di Ventra, M., Pantelides, S. T., ... & Weller, R. A. (2000). Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4 H polytype of silicon carbide. Applied Physics Letters, 76(13), 1713-1715.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 7-14

doi: 10.4028/p-jgTu1m

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-29

Accepted:
2026-01-31

Online:
2026-05-19

The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

Jan Frederik Dick 1,a*, Jannik Schwarberg 1, b, Mathias Rommel 2,c and Jörg Schulze 1,2,d

1 Friedrich-Alexander-Universität Erlangen-Nürnberg, Chair of Electron Devices, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystraße 10, 91058 Erlangen, Germany

a*jan.dick@fau.de, b  jannik.schwarberg@fau.de, cmathias.rommel@iisb.fraunhofer.de,  djoerg.schulze@iisb.fraunhofer.de

Keywords: power semiconductor device concept, tunneling transistor, TFET, Power-TFET, high-frequency power electronics.

Abstract

With ever-increasing power conversion densities in electric power converters, the volume of the converter must shrink for a certain power rating, which in turn demands the reduction in size of the energy-storing passive component. Constant power rating of those systems and the reduction of size of passive components leads to a higher switching frequency of the semiconductor power switches. At high switching frequencies, dynamic losses in the power semiconductor device dominate the overall power losses. Consequently, novel device concepts that address dynamic power losses may be superior to conventional power devices, even though they might have a higher static on-state loss. In this paper, the concept of the power tunneling field-effect transistor (Power-TFET) employing tunneling between a highly p-type doped source region and a n-type accumulation channel is proposed and compared to an equivalent LDMOS in terms of static and dynamic losses. Devices fabricated in a 2μ m4H−SiC technology are measured and compared to evaluate the viability of the Power-TFET device concept. The fabricated Power-TFET shows high-voltage blocking capability and has a switchable tunneling junction with on- and off-state, despite showing high on-state resistance due to the tunneling through the wide bandgap of 4H−SiC. The alternative of tunneling through a switchable Schottky barrier is simulatively explored to solve the high on-state resistance of the pn-junction based Power-TFET.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

Many of the disciplines in semiconductor engineering have shown exponential development in their fields over the years. The most prominent example of such exponential growth is the integration density of integrated circuits and the scaling of the individual semiconductor devices in logic circuits, which was first described by Gordon Moore [1]. Analogous to Moore's law, there is also an exponential increase in the power conversion density over time in the field of power electronics [2]. The power conversion density describes the amount of electrical power transferred and converted in a set converter volume. To further increase the power conversion density, it is therefore mandatory to reduce the converter volume for a set power throughput. A reduction of the converter volume can mainly be achieved by two means. First, the energy storage components that need the most space in typical converter applications must shrink, which mandates higher frequency switching since the same power must be transferred through the smaller energy storage components [3] and second, smaller cooling solutions are required, which mandates lower power losses of the semiconductor devices at the same power throughput. In essence, semiconductor power devices need to become more efficient at higher switching frequencies for future applications. Every power device technology for a certain blocking voltage has a fundamental limit in terms of the efficiency that it can reach in a converter [4]. The efficiency is set by the static conduction losses during on-state and the dynamic losses that arise from switching. Consequently, the overall converter efficiency decreases with
increasing switching frequency [4]. In many power electronic applications that use metal oxide semiconductor field-effect transistors (MOSFET) or high electron mobility transistors (HEMT), the dynamic losses surpass the static losses already in the frequency range between 20 kHz and 100 kHz , which makes it impractical to surpass the 1 MHz mark without significant drawbacks in terms of dynamic power losses and therefore more complex and bulkier cooling [4].
A sensible solution for the shortcomings of the existing technologies is to search for device concepts that enable lower power consumption during hard switching processes. In this paper, the possibility of a tunneling field-effect transistor (TFET) for power applications (Power-TFET) is explored. The concept of the TFET has been developed over the past two decades [5] to find a steep-slope concept to replace the conventional MOSFET. The goal is to achieve higher efficiency of those integrated circuits by reducing the supply voltage necessary for reliable switching. Since the load at the output node of a complementary MOS (CMOS) logic gate is typically the input capacitance of the following CMOS logic gate, static losses are of smaller interest, and the dynamic losses are dominant. Bohr and Young have shown in their work that TFETs need less energy for switching and have a lower delay at the output node [6]. Considering this, the TFET may as well be a viable concept for a fast-switching power device.

The Tunneling Field-Effect Transistor as a Power Device Concept

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A TFET, in its most basic form, is a pin-diode with a MOS gate adjacent to its intrinsic region. The MOS electrode controls the potential at the semiconductor interface such that carriers can tunnel from the source region into the now formed channel [7]. This works for n - and p -channel TFETs in the exact same way due to the ambipolar device behavior. A basic schematic of such a TFET is given in Fig. 1 a). For a power electronic device, such a TFET is not yet useful since only n-channel behavior is of interest due to the higher mobility of electrons. Additionally, a drift region must be added to contain the electric field at high blocking voltages. Therefore, the device structure shown in Fig. 1 b) is proposed. In comparison to the conventional TFET in Fig. 1 a), the gate is shortened to only cover the source-side junction of the central region to suppress the ambipolarity and prevent drain-side breakdown of the gate at high blocking voltages. The central intrinsic region is extended on the drainside to accommodate higher fields and lightly n-type doped for better conduction in on-state. A similar device structure was already proposed in a patent by Vandenderghe and Verhulst in [8], although not for power semiconductor device applications but for CMOS applications, where ambipolarity is suppressed.

[picture]

Fig. 1. Comparison of the a) TFET and d) MOSFET for logic applications with their power device counterparts in b) and e). Their respective internal resistances are shown, representing the static loss of each device. The channel is marked in grey in both cases. In c) and f) the input capacitances of Power-TFET and LDMOS are compared, representing the dynamic losses.

Fig. 1. Comparison of the a) TFET and d) MOSFET for logic applications with their power device counterparts in b) and e). Their respective internal resistances are shown, representing the static loss of each device. The channel is marked in grey in both cases. In c) and f) the input capacitances of Power-TFET and LDMOS are compared, representing the dynamic losses.

In Fig. 1 b), the static loss of the Power-TFET is compared with the static loss in on-state of an equivalent lateral power MOSFET shown in e). From the device structure it is apparent that the commonalities between the shown MOSFET and Power-TFET are mostly given by the resistances of the drift region Rdrift , source region RS, and drain region RD. However, the total channel resistance differs greatly. The channel of the MOSFET can be separated in two sections: First, the inversion channel resistance Rch  within the p-type doped body and second, the resistance of the accumulation channel RA at the overlap of the gate with the drift region. The channel of the Power-TFET can also be separated in two parts: First, a non-linear tunneling resistance at the junction RT and second, the accumulation channel resistance RA at the gate overlap with the drift region. Assuming the drift region overlap of the gate electrode is equal for the MOSFET and the Power-TFET than the accumulation channel resistance RA are also equivalent. We can therefore directly compare the MOSFETs inversion channel resistance with the tunneling resistance in the Power-TFET to evaluate the relative static losses. The inversion channel resistance Rch in a MOSFET at small drain-source voltage VDS is given in [9, p. 327] as follows:

Rch=LchwchμnCox( VG−Vth)(1)

Lch describes the channel length, wch the channel width, μn the inversion layer mobility of the electrons, Cox the specific oxide capacitance and VG−Vth  is the difference between the applied gate voltage and the threshold voltage.
The tunneling resistance in a TFET is non-linear, which is apparent by the non-linearity of the tunneling current in p+−n+junction. The inter-band tunneling current density JT in a p+−n+junction is given in [10] as:

JT( VT)=2 m*q3ε VT4π2ℏ2Egexp(−42 m*Eg323qϵℏ)=2 m*q3(Eg/q+VT)VT4π2ℏ2λEgexp(−4λ2 m*Eg323q(Eg/q+VT)ℏ)(2)

In this equation, m* is the effective mass, q the elementary charge, ℰ the electric field within the junction, VT is the externally applied voltage bias across the tunneling junction and Eg is the bandgap energy. A central assumption behind (2) is that the potential barrier is triangular and therefore the electric field is constant with the value ε≈(E g/q+VT)/λ, where λ is the width of the tunneling barrier. Since the electric field ε contained in (2) is also a function of VT, it appears quadratically in the leading factor of JT and it appears reciprocally in the exponent. While the channel resistance Rch of a MOSFET is constant with respect to the applied drain-source voltage in its on-state with small forward voltage drop, in the Power-TFET the on-current is non-linear and therefore at low voltage the differential on-resistance is high and drops at higher drain-source voltage bias. In fact, small current flow will already result in a sizable voltage drop across a Power-TFET. Depending on the material parameters contained in (2), it is possible that a Power-TFET can match the static current carrying capability of an equivalent MOSFET and therefore its static losses, but only within a high current density regime at operation points with low differential on-resistance.
The Power-TFET has benefits with respect to its dynamic losses. Dynamic losses arise especially from the charging and discharging of the input capacitance of the respective power device [9, p. 432]. Fig. 1 c ) and f) depict the capacitive parts of the gated region of c) a Power-TFET and f) a MOSFET, respectively. The total input capacitance for the Power-TFET can be written as follows:

Cin, Power-TFET =CGS+CGD(3)

CGS is the source-side overlap capacitance and CGD is the drain side accumulation capacitance overlapping the drift-region. For the equivalent MOSFET given here, the total input capacitance is given as follows:

Cin,MOSFET=CGS+CGB+CGD(4)

CGB is the body capacitance containing the inversion channel. Comparing the input capacitances from (3) and (4), we can see that the overlap capacitances of the source region and the drift region are equal for equivalent MOSFET and Power-TFET devices. The MOSFET has the additional channel capacitance, which is responsible for the establishment of the inversion channel. The reduced input capacitance of the Power-TFET does improve the dynamic power loss compared to those of the MOSFET, which makes it an interesting device concept for reduced dynamic loss.

The Lateral Homo-Junction 4H-SiC Power-TFET

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Device Geometry and Fabrication. To evaluate the device concept of the Power-TFET, lateral devices were implemented alongside laterally diffused MOSFETs (LDMOS) for reference on the 2μ m high-temperature CMOS platform by Fraunhofer IISB [11]. Schematic cross-sections of the two fabricated devices are shown in Fig. 1 b) and e). As substrates n-type 4H−SiC wafers are used with a 12μ m thick epitaxial layer, which is n-type doped with a concentration of 1015 cm−3. Further doping wells and contact regions were implanted. The n+and p+doped contact regions are doped with 5·1019 cm−3 respectively and the p-well forming the body of the LDMOS is doped with a concentration of 1017 cm−3. The gate MOS electrode consists of a 55 nm thick thermally grown SiO2 and a n+doped polycrystalline silicon electrode. The channel length of the LDMOS is 2μ m and the drift zone of both devices have a length of 12μ m. The gate-source and gate-drain overlap are each 1μ m respectively.
Static Electrical Characteristics. In Fig. 2 the transfer characteristics are shown at a drain-source bias of VDS=1 V. The LDMOS device shows the typical exponential subthreshold behavior with a distinct off-state at VGS=0 V and a distinct on-state at VGS=20 V spanning eleven orders of magnitude in current between off- and on-state. The Power-TFET in contrast shows the same low leakage current in off-state, but does only span six orders of magnitude if the gate is biased up to VGS=40 V. Furthermore, the Power-TFET shows a shallow and rounded transfer characteristic. The onset of the tunneling current is also shifted towards higher voltages compared to the LDMOS. Fig. 3 shows the comparison of the measured output characteristics of the Power-TFET and the reference LDMOS. The characteristics are plotted on separate current axis due to the significant difference in on-state current, such that the qualitative shape of the characteristics can be compared. Compared to the linear behavior of the LDMOS at small VDS, the Power-TFET exhibits the non-linear tunneling current with an immediate onset of the tunneling current above VDS=0 V. Both devices show a saturation behavior at high VDS .

[picture]

Fig. 2. Transfer characteristics of the 4H−SiC LDMOS and the 4H−SiC Power-TFET normalized on gate width.

Fig. 2. Transfer characteristics of the 4 H − S i C LDMOS and the 4 H − S i C Power-TFET normalized on gate width.

[picture]

Fig. 3. Scaled output characteristics normalized on gate width of the 4H−SiC LDMOS and the 4H− SiC Power-TFET for comparison of the characteristics' shape.

Fig. 3. Scaled output characteristics normalized on gate width of the 4 H − S i C LDMOS and the 4 H − SiC Power-TFET for comparison of the characteristics' shape.

The devices were also characterized with regard to their breakdown behavior, which is shown in Fig. 4. Since the devices discussed here are lateral devices that do not implement any doping structures to reduce surface electric field, the devices fail typically at the semiconductor-oxide interface and do not exploit the total breakdown capability of 4H−SiC. This also explains the variance in breakdown voltage shown in the inset in Fig. 4. Nevertheless, the devices show high-voltage capability with some Power-TFETs reaching a breakdown voltage of 600 V , beyond the capability of the LDMOS.

[picture]

Fig. 4. Comparison of the breakdown behavior of the devices in off-state. The inset shows the distribution of breakdown voltages of LDMOS and Power-TFET.

Fig. 4. Comparison of the breakdown behavior of the devices in off-state. The inset shows the distribution of breakdown voltages of LDMOS and Power-TFET.

Overall, the built devices show for the first time tunneling field-effect transistor behavior in 4H−SiC with a switched homo-junction with distinct off- and on-state and high blocking capability. Nevertheless, the on-current is too low for practical use and therefore the tunneling resistance and consequently the tunneling barrier must be optimized for the application.

Tunneling Barrier Design for Low Static Loss

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

Design Considerations. The output and transfer characteristics illustrate well that the tunneling resistance is eight orders of magnitude larger than the channel resistance of the equivalent LDMOS at VGS=20 V and VDS=1 V and limits the on-current to values not appropriate for the application as power device. The large tunneling resistance results almost entirely from the large bandgap energy of 4H−SiC, which the carriers must tunnel through. Equation (2) illustrates this since the bandgap energy is in the denominator of the pre-factor of the tunneling current density and in the numerator of the negative exponent of the exponential function, both leading to a lowering of the tunneling current density. Consequently, the barrier height is the parameter to optimize. In literature, TFETs for logic applications on other material systems are shown that employ heterojunctions using materials with smaller bandgap energy directly at the tunneling junction for increased current and steeper subthreshold behavior [12, 13]. In 4H-SiC heteroepitaxy is not a viable method [14] because the materials available still have large bandgaps limiting the tunneling current [15, 16]. The alternative is to use a Schottky-barrier for tunneling in the tunneling transistor [17-19]. Here the metalsemiconductor combination yields the barrier height and can be chosen quite freely and is in most cases easily manufacturable by evaporation or sputtering with optional annealing steps for alloying thereafter. Consequently, a low barrier height yields the highest tunneling current density in on-state and the lowest tunneling resistance. Low barrier height of a Schottky barrier does also introduce a lot of leakage in blocking mode through thermionic emission and Fowler-Nordheim tunneling, worsening the efficiency of the device in blocking mode and therefore increasing static loss in offstate. This leakage current has also been observed in power Schottky rectifier diodes and has been suppressed by additional structures such as in junction barrier Schottky (JBS) diodes, which
implement additional p-implanted structures underneath the Schottky contact depleting it in thermodynamic equilibrium and therefore suppressing the leakage from the Schottky barrier [20]. Implementing both, the JBS diode structure for the depletion of the Schottky barrier and a MOS gate contact adjacent to the Schottky barrier, making it switchable, keeps the low leakage in off-state while achieving a high on-current in the on-state.
Simulative Evaluation of the Switchable JBS Diode. To confirm the function of the concept a technology computer aided design (TCAD) simulation using Synopsys Sentaurus [21] was performed. The geometry of the simulated device is chosen analogous to the lateral homo-junction Power-TFET described above and 4H−SiC is chosen as semiconductor material. A schematic crosssection is shown in the inset of Fig. 5. The p+doped region underneath the Schottky contact is used to deplete the Schottky junction, such that the leakage is minimal. The gate is attached to the metal semiconductor junction with a distance of 1μ m from the p+doped region. The semiconductor is recessed at the boundary of the Schottky-junction for 100 nm , such that the electric field control of the gate on the semiconductor directly underneath the metal is optimal. For the simulation a multitude of models are used given in Tab. 1.

Table 1. Models used for the TCAD simulation of the Schottky Power-TFET and the reference LDMOS [21].

Recombination: | Shockley-Read-Hall
| Auger
| Non-local tunneling model with non-local mesh
Mobility: | Doping dependence (Massetti)
| Field dependence normal to carrier movement (Lombardi)
| High field saturation (Caughey Thomas)
Incomplete Ionization: | 50% split of the shallow and deep nitrogen donor level in 4H-SiC
Material anisotropy: | Mobility
| Poisson
Interface Traps: | 5·10¹² cm⁻² at the semiconductor-oxide interface

[picture]

Fig. 5. Comparison of a simulated 4H−SiC LDMOS and a simulated 4H−SiC Schottky PowerTFET (cross-section shown in the inset). The channel established in the n-layer is shown in gray, which directly contacts the metal source contact. The contact potential at the Schottky junction is set to ϕm−HL=0.6 V.

Fig. 5. Comparison of a simulated 4 H − S i C LDMOS and a simulated 4 H − S i C Schottky PowerTFET (cross-section shown in the inset). The channel established in the n-layer is shown in gray, which directly contacts the metal source contact. The contact potential at the Schottky junction is set to ϕ m − H L = 0.6 V .

For the Schottky barrier height between the n -layer and the metal source contact, a value of ϕM−HL=0.6eV is chosen. The transfer characteristic of the device is shown in Fig. 5 and compared to a simulative representation of the abovementioned LDMOS simulated with the same models and parameters. The reference LDMOS in Fig. 2 shows overall a very similar behavior as the simulated LDMOS in Fig. 5. The values for the on-current and the onset of the subthreshold behavior fit well between simulation and measurement, hinting that the simulative results are reliable. The simulation shows the same leakage for both Schottky Power-TFET and LDMOS in off-state and at a gate bias of 20 V the Schottky Power-TFET achieves an on-current comparable to the on-current of the LDMOS. The transfer characteristic of the Schottky Power-TFET shows two distinct regions. First, a steep rise of current, which is the gate's influence on the depletion of the Schottky barrier by increasing the carrier concentration in the accumulation channel and thereby increasing the leakage at the Schottky barrier. Second, the Schottky barrier is getting thin and a significant tunneling current occurs due to the rising carrier concentration in the channel. This yields the rounded behavior of the second increase.

Conclusion

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The Power-TFET promises lower dynamic loss by reduction of the input capacitance since it does not implement a gate-body capacitance compared to an equivalent MOSFET. This benefit is only useful, if the static loss of the Power-TFET is comparable to those of a MOSFET. The direct comparison of a fabricated lateral MOSFET and a Power-TFET has shown that the Power-TFET lacks eight orders of magnitude in terms of on-current due to the tunneling barrier being the bandgap of 4H−SiC. It is simulatively shown that swapping the homo-junction for a JBS diode structure, where the gate switches a Schottky barrier with low barrier height can achieve both low leakage in off-state and the required on-current.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.7.pdf

G. E. Moore, "Cramming More Components Onto Integrated Circuits," Proc. IEEE, vol. 86, no. 1, pp. 82-85, 1998, doi: 10.1109/jproc.1998.658762.

H. Ohashi, "Power electronics innovation with next generation advanced power devices," Proceedings of the 25th International Telecommunications Energy - INTELEC '03, pp. 9-13, 2003. [Online]. Available: 1252084

J. Zou, N. C. Brooks, S. Coday, N. M. Ellis, and R. C. Pilawa-Podgurski, "On the Size and Weight of Passive Components: Scaling Trends for High-Density Power Converter Designs," in 2022 IEEE 23rd Workshop on Control and Modeling for Power Electronics (COMPEL 2022): Tel-Aviv, Israel, June 20-23, 2022, Tel Aviv, Israel, 2022, pp. 1-7.

T. Heckel, C. Rettner, and M. Marz, "Fundamental efficiency limits in power electronic systems," in 2015 IEEE International Telecommunications Energy Conference (INTELEC), Osaka, Japan, 2015, pp. 1-6.

W. Hansch, C. Fink, J. Schulze, and I. Eisele, "A vertical MOS-gated Esaki tunneling transistor in silicon," Thin Solid Films, vol. 369, 1-2, pp. 387-389, 2000, doi: 10.1016/S0040-6090(00)00896-8.

M. T. Bohr and I. A. Young, "CMOS Scaling Trends and Beyond," IEEE Micro, vol. 37, no. 6, pp. 20-29, 2017, doi: 10.1109/MM.2017.4241347.

A. C. Seabaugh and Q. Zhang, "Low-Voltage Tunnel Transistors for Beyond CMOS Logic," Proc. IEEE, vol. 98, no. 12, pp. 2095-2110, 2010, doi: 10.1109/JPROC.2010.2070470.

W. Vandenberghe and A. Verhulst, "Tunnel field-effect transistor with gated tunnel barrier," USA US8120115B2, Feb 21, 2012.

B. J. Baliga, Fundamentals of power semiconductor devices. Cham, Switzerland: Springer, 2019.

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ, USA: John Wiley & Sons, Inc, 2006. [Online]. Available: 10.1002/0470068329

A. May et al., "A 4H-SiC CMOS Technology enabling Smart Sensor Integration and Circuit Operation above ," in 2024 Smart Systems Integration Conference and Exhibition (SSI): 16-18 April 2024: conference location: Hamburg, Germany, Hamburg, Germany, 2024, pp.15.

D. Haehnel, I. A. Fischer, A. Hornung, A.-C. Koellner, and J. Schulze, "Tuning the Ge(Sn) Tunneling FET: Influence of Drain Doping, Short Channel, and Sn Content," IEEE Trans. Electron Devices, vol. 62, no. 1, pp. 36-43, 2015, doi: 10.1109/TED.2014.2371065.

K. K. Bhuwalka, J. Schulze, and I. Eisele, "A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 15411547, 2005, doi: 10.1109/TED.2005.850618.

P. G. Neudeck, J. A. Powell, A. J. Trunek, and D. J. Spry, "Step Free Surface Heteroepitaxy of 3C-SiC Layers on Patterned 4H/6H-SiC Mesas and Cantilevers," MSF, 457-460, pp. 169-174, 2004, doi: 10.4028/www.scientific.net/MSF.457-460.169.

S. Chen et al., "High-quality heteroepitaxy of -Ga 2 O 3 films on 4 H -SiC substrates grown via MOCVD," CrystEngComm, vol. 26, no. 25, pp. 3363-3369, 2024, doi: 10.1039/D4CE00283K.

M. Hu et al., "Heteroepitaxy of N-polar AlN on C-face 4H-SiC: Structural and optical properties," APL Materials, vol. 11, no. 12, 2023, doi: 10.1063/5.0168970.

F. Lanois, "Vertical controlled Schottky diode for use in forward type rectifier, has driver surrounded by insulator that extends in thin layer according to direction, and interdependent control electrode secured to conducting material," FR2975531 (A1), FR FR20110054215 20110516, Nov 23, 2012.

M. Schwarz et al., "The Schottky barrier transistor in emerging electronic devices," Nanotechnology, vol. 34, no. 35, 2023, doi: 10.1088/1361-6528/acd05f.

L. Knoll and R. Minamisawa, "VERTICAL POWER SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING SUCH A DEVICE," EP3255676 (A1), EP EP20160173688 20160609, Dec 13, 2017.

B. J. Baliga, "The pinch rectifier: A low-forward-drop high-speed power diode," IEEE Electron Device Lett., vol. 5, no. 6, pp. 194-196, 1984, doi: 10.1109/EDL.1984.25884.

Synopsys, Inc., "Sentaurus Device User Guide: Version Q-2019.12," Synopsys, Inc., Dec. 2019.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 15-20

doi: 10.4028/p-1PUxT1

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-16

Accepted:
2026-03-08

Online:
2026-05-19

Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

Jeff Joohyung Kim 1,a*, Jae-Hyung Park 1,b, Shane Stein 1,c, Daniel Lichtenwalner 1, d, Sei-Hyung Ryu 1,e

Abstract

We have introduced a new 1200 V4H−SiC MOSFET as Wolfspeed's Gen4 MOSFET, which offers compatible Rds,on, improved dynamic switching energy losses, reduced Qrr, and enhanced short circuit withstand time performance. In this study, we examine the P-body effect resulting from multi-step ion implantation and its significant impact on both the static and dynamic characteristics of SiC MOSFETs, specifically focusing on body-diode reverse recovery, short circuit withstand time (Tscwt), and observed switching energy losses in the 1.2 kV 4H-SiC power MOSFETs within this Gen4 series. Our findings are expected to contribute valuable insights into optimizing the design and operation of SiC MOSFETs, ultimately supporting the needs of modern power electronic systems that demand greater performance and efficiency.

Wolfspeed, 4600 Silicon Drive, Durham, NC 27703, USAa  Jeff.Kim@wolfspeed.com, b  Jae-Hyung.Park@wolfspeed.com, c  Shane.Stein@wolfspeed.com, d  daniel.lichtenwalner@wolfspeed.com, e  sei-hyung.ryu@wolfspeed.com

Keywords: 4H−SiC MOSFET, Short Circuit Withstand Time, Double Pulse Test, Switching energy losses, Reverse recovery, Qrr.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) are recognized as advanced power semiconductor devices that enable a wide array of highly efficient, high-power electronic applications. This remarkable capability primarily arises from their wide bandgap characteristics, which enhance performance in demanding operational environments [ 1,2 ]. As the demand for higher efficiency and reliability in power electronic systems continues to grow, recent advancements in this field focus on minimizing the on-resistance (Rds,on) of these devices to significantly reduce conduction losses. However, achieving this goal often requires careful consideration of trade-offs between key design parameters, as elaborated in our previous reports [3, 4,5]. Based on our thorough analysis of these trade-off relationships, we have successfully launched a new 1200 V 4H-SiC MOSFET as Wolfspeed's Gen4 MOSFET. This device offers competitive Rds,on, improved switching energy losses, reduced Qrr, and notably enhanced short circuit withstand time performance. Such improvements are vital for applications in sectors such as renewable energy, electric vehicles, and industrial power systems, where performance and reliability are paramount [2 - 6]. This paper aims to explore the P-body effect resulting from the multi-step ion implantation process, which significantly impacts not only the static characteristics of SiC MOSFETs but also a range of dynamic characteristics. Among these are performance metrics related to body-diode reverse recovery, short circuit withstand time ( Tscwt  ), and the switching energy losses observed in the 1.2 kV 4H−SiC power MOSFETs that are part of Wolfspeed's Gen4 series. By understanding these effects, we can further optimize device performance and contribute to the next generation of high-efficiency power electronics.
1.2 kV 4 H SiC MOSFET structure and Experiment

[picture]

Fig. 1. Schematic cross-sectional view of 1.2kV4H−SiC Power MOSFETs.

Fig. 1. Schematic cross-sectional view of 1.2 k V 4 H − S i C Power MOSFETs.

Figure 1 illustrates a simplified cross-sectional view of a 1.2 kV SiC power MOSFET, clearly depicting the structural elements integral to its function. It highlights critical design parameters such as the width of the JFET ( WJFET  ), gate-drain capacitance ( Cgd ), gate-source capacitance ( Cgs ), and the influence of the n -drift region. These parameters play a crucial role in determining the overall performance of the device, impacting factors like switching speed and efficiency. In our experiments, we varied the P -well doping concentration at two distinct levels to comprehensively investigate the impact of P-well doping on the P-body effect. Specifically, we denote these configurations as High PW and Low PW, which differ in their implantation dose levels. This variation enables us to analyze how different doping concentrations influence device characteristics, such as on-resistance, switching behavior, and reliability. Furthermore, understanding these effects will provide valuable insights into optimizing the design of SiC MOSFETs for high-power applications. The outcomes of our study will contribute to enhancing the performance and efficiency of next-generation power semiconductor solutions.

Electrical Results

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

[picture]

Fig. 2. (a) Id and Mobility comparison for two P-wells in lateral MOSFETs, (b) Nit between two P -wells for charge pumping test.

Fig. 2. (a) Id and Mobility comparison for two P-wells in lateral MOSFETs, (b) Nit between two P -wells for charge pumping test.

The experimental results, presented in Figures 2(a) and (b), depict the relationships between drain current ( Id ) and both the calculated field-effect mobility ( μFE ) and trap density (Nit). These were meticulously measured using the charge pumping (CP) method [5], applied specifically to lateral SiC

MOSFETs. These results expose the significant impact of P -well doping on the channel properties of the MOSFET. Notably, the High PW configuration exhibits a threshold voltage ( Vth  ) that is 80 mV higher than that of the Low PW configuration. In contrast, the field-effect mobility μFE is approximately 10% lower in the High PW samples. Additionally, the trap density Nit is found to be about 22% greater in samples with higher P -well doping. These findings suggest that the doping concentration of the P -well can significantly influence the channel properties through gate oxide surface effects, which extend beyond merely adjusting the channel Vth  due to a greater implantation dose of the P-well. The interplay between doping levels and channel characteristics is critical, as it governs the overall efficiency and performance of the MOSFET. Moreover, the increased trap density associated with higher doping concentrations may lead to greater charge trapping effects, potentially impacting the reliability of the device under high-frequency and high-temperature conditions. Understanding these interactions will not only aid in optimizing device design but also provide insights into the long-term stability and efficiency of SiC MOSFETs in various applications.

[picture]

Fig. 3. Static characteristic for two P -wells at 25 and 175∘C. (a) Normalized Rds, on versus Vth (b) BVdss versus Normalized Rds,on.

Fig. 3. Static characteristic for two P -wells at 25 and 175 ∘ C . (a) Normalized Rds, on versus Vth (b) BVdss versus Normalized Rds,on.

Figure 3 presents the static characteristics of the 1.2kV4H−SiC Power MOSFET at two temperatures: 25∘C and 175∘C. Within this figure, 3 (a) and (b) depict the normalized Rds ,on as a function of Vth, alongside the breakdown voltage (BVdss) versus Rds,on, respectively. As shown in Figure 3, the High PW configuration exhibits Rds, on values that are 9.32% and 13.24% greater than those of the Low PW configuration at 25∘C and 175∘C, respectively. Additionally, High PW also shows Vth values that are 5.4% and 1.8% higher than Low PW at 25∘C and 175∘C. Furthermore, High PW demonstrates around 115 V greater BVdss compared to Low PW at both temperature points, primarily as a result of JFET pinching influenced by the heavy doping of the P-well. The results clearly indicate that the High PW configuration exhibits higher values for Vth , Rds,on, and BVdss in comparison to the Low PW configuration, which is consistent with the findings presented in Figure 2. The trends observed suggest that higher P-well doping concentrations lead to enhanced threshold voltage and on-resistance characteristics. Moreover, the rate of increase in Rds, on at 175∘C, is noted to be less pronounced compared to the behavior exhibited at 25∘C when P -well doping increases. This behavior underscores that the variation in the doping profile of the P -well is more dominant in shaping the channel property characteristics, particularly at elevated temperatures. These findings have important implications for the operation and reliability of the device under varying temperature conditions. By gaining insight into these relationships, we can better optimize design parameters to enhance performance and mitigate potential thermal degradation in high-temperature applications. Ultimately, understanding the influence of P-well doping on these key characteristics will provide a pathway to developing more efficient and reliable SiC MOSFETs for demanding applications in the power electronics landscape.

In Figure 4, the measured normalized parasitic capacitance plots ( Ciss ,Coss , and Crss  ) for both doping configurations are presented. The results indicate that for the High PW configuration, Ciss  is approximately 5.5% higher compared to the Low PW configuration, while Crss is around 33% lower. These differences can be attributed to the higher levels of P -well doping, which positively influence the device characteristics. Additionally, the changes in these capacitances also account for the increased breakdown voltage (BVdss) observed in Figure 3(b).

[picture]

Fig. 4. C-V characteristics ( Ciss ,Coss ,Crss  ) for two P-wells at 25∘C.

Fig. 4. C-V characteristics ( C iss , C oss , C rss ) for two P-wells at 25 ∘ C .

[picture]

Fig. 5. Double Pulse Test (DPT) waveforms for two P-wells at 175∘C. (a) Turn on (b) Turn off.

Fig. 5. Double Pulse Test (DPT) waveforms for two P-wells at 175 ∘ C . (a) Turn on (b) Turn off.

[picture]

Fig. 6. Reverse recovery ( Qrr ) waveforms for two P -wells at 175∘C.

Fig. 6. Reverse recovery ( Q r r ) waveforms for two P -wells at 175 ∘ C .

Table 1. Normalized DPT and reverse recovery characteristics based on Fig. 5 and 6.

|  | Low PW | High PW
DPT | dI/dt on | 1 | 0.862
Eon | 1 | 1.055
di/dt off | 1 | 1.103
Eoff | 1 | 0.708
Reverse Recovery | dI/dt | 1 | 0.978
dIr/dt | 1 | 0.789
Irr | 1 | 0.969
Qrr | 1 | 1.203

Furthermore, Figure 5 illustrates the switching waveforms obtained from the double pulse test (DPT), which are essential for comparing the switching characteristics of MOSFETs with the High PW and Low PW doping levels during the Turn On process (Figure 5(a)) and the Turn Off process (Figure 5(b)). Additionally, Figure 6 presents the reverse recovery characteristics, providing a comparative analysis of the body diode performance for both doping samples. The normalized switching parameters, including dI/dt, switching energy losses ( Eon  and Eoff  ), and dIr/dt, are meticulously summarized in Table 1. The High PW configuration exhibits a lower dI/dt during the Turn On phase, accompanied by a higher Eon compared to the Low PW configuration. Conversely, during the Turn Off phase, the High PW configuration demonstrates a higher dI/dt while maintaining a lower Eoff  value. These observed behaviors can be attributed to the reduced channel mobility that arises from the increased levels of P -well doping. In terms of reverse recovery characteristics, the High PW configuration displays a lower dIr/dt and reverse recovery current ( Irr ), while also exhibiting a greater reverse recovery charge ( Qrr ) compared to the Low PW configuration. The heavily doped P-well influences the performance, contributing to a lower softness factor in the body diode, albeit at the cost of an increased Qrr value. Furthermore, it is noteworthy that the High PW configuration demonstrates a higher forward voltage drop ( Vsd ) across the body diode when the gate is fully turned off, although plots illustrating this aspect are not included here. These insights into the switching and recovery characteristics underscore the complex trade-offs associated with varying doping levels in MOSFET designs. Understanding these relationships is essential for optimizing device performance in specific applications, particularly where fast switching and efficient energy management are critical. The findings provide a solid foundation for future studies aimed at refining doping strategies and enhancing overall MOSFET performance in high-power and high-frequency applications.
Σ

Fig. 7. TscWT waveform ( Vds=800 V ) comparison at 175∘C for two P -wells.

In Figure 7, a comparison of short-circuit current waveforms is presented at a drain-source voltage (Vds) of 800 V . The findings indicate that the High PW configuration exhibited a peak drain current reduction of 10.5% during these events. This decrease in peak drain current during short-circuit incidents is associated with a remarkable improvement in the short-circuit withstand time ( Tscwt  ), which is observed to be 25% longer with the heavily doped P -well configuration. These results substantiate the notion that channel mobility, combined with the straggle effects associated with Pwell implantation due to elevated doping levels, plays a vital role in enhancing Tscwt  in these devices. The improved Tscwt  is critical for ensuring the reliability and robustness of the MOSFETs in demanding applications. Additionally, the reduction in peak drain current not only contributes to better thermal management during faults but also reduces the stress on the device, potentially prolonging its operational life. Overall, the relationship between P-well doping and short-circuit performance highlights the importance of optimizing doping strategies to achieve superior device reliability and performance under extreme conditions.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

This study explores the influence of P -well doping levels on the performance of 4H−SiC Power MOSFETs, revealing critical insights into operational efficiency and reliability. The results indicate notable differences between High PW and Low PW configurations in terms of threshold voltage ( Vth  ), field-effect mobility ( μFE ), and trap density (Nit). Specifically, the High PW configuration exhibits a higher Vth  and trap density, which corresponds to a reduction in μFE. These findings highlight the need for optimizing P -well doping concentrations to enhance device performance while managing associated effects. The static characteristics show that the High PW configuration has increased onresistance (Rds,on) and breakdown voltage (BVdss) compared to Low PW, with less sensitivity to temperature changes in Rds,on. Such insights are vital for ensuring stable performance in hightemperature applications. Additionally, our analysis of switching characteristics indicates that higher P-well doping results in trade-offs in dynamic performance. The High PW configuration experiences reduced peak drain current during short-circuit events, contributing to a significant improvement in short-circuit withstand time ( Tscwt  ). This enhancement is crucial for device reliability in demanding environments.

In conclusion, this research underscores the complex relationship between P -well doping and key MOSFET performance parameters. A deeper understanding of these interactions enables better optimization of device design and doping strategies, leading to more efficient and reliable SiC MOSFETs suitable for high-power and high-frequency applications. Future studies should continue refining doping techniques to further enhance device performance under diverse operational conditions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.15.pdf

J. W. Palmour et. al., IEEE ISPSD, 2014, 79-82.

P. Leteinturier et. al., 32nd ISPSD, 2020, pp. 5-9.

https: .

J. Kim et. al., Solid State Phenomena, 2024, Vol. 360, pp 189-193.

J. Kim et. al., ISPSD, 2024, pp. 148-151.

S. R. Stein et. Al., 2024 IEEE International Reliability Physics Symposium (IRPS), pp. 1-5.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 21-27

doi: 10.4028/p-6iQUYo

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-22

Accepted:
2026-01-31

Online:
2026-05-19

High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

Shariare Hossain Rabbi 1,a*, Justin Lynch 1, b, Stephen A. Mancini 1,c and Woongje Sung 1,d

¹College of Nanotechnology Science and Engineering, University at Albany, Albany, NY, 12203, USA

a  srabbi@albany.edu, b  jmlynch@albany.edu, c  smancini@albany.edu, d  wsung@albany.edu

Abstract

This paper reports on the comparative analysis of several 6.5 kV -rated 4H-SiC Junction Barrier Schottky integrated MOSFETs (JBSFETs) and 4H-SiC MOSFET to assess their forward conduction, 3rd  quadrant behavior, and blocking characteristics. Among different JBSFET architectures, the Island P+ JBSFET achieved nearly identical specific on-resistance ( Ron,sp ) to the nominal MOSFET while delivering superior 3rd  quadrant conduction and maintaining a high breakdown voltage. Further optimization of Schottky width demonstrated a trade-off between leakage suppression and 3rd  quadrant conduction efficiency that underscores the Island P+JBSFET 's potential as a reliable high-voltage SiC power device for next-generation applications.

Keywords: 4H−SiC, JBSFET, MOSFET, High Voltage, Power Devices, 3rd  Quadrant Conduction.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

4H−SiC has become a leading material for next-generation high-voltage power electronics owing to its wide bandgap and high critical electric field. These properties enable thinner and more heavily doped drift layers compared to traditional silicon devices, while still maintaining the same voltage blocking capability. Consequently, 4H−SiC power devices can achieve significantly lower onresistance at voltage ratings above 600 V , making them highly attractive for high-efficiency and highpower applications [1]. However, the approximately three times higher built-in potential across PN junctions in 4H-SiC results in a larger forward voltage drop in the intrinsic body diode of MOSFETs during 3rd  quadrant conduction. To mitigate this, external Junction Barrier Schottky (JBS) diodes are often co-packaged as a freewheeling diode [2,3]. While effective, the use of external diodes increases package area.

In high-voltage SiC power devices, the use of thick epitaxial drift layers leads to an increase in basal plane dislocation (BPD) density, thereby worsening bipolar degradation. As drift resistance ( Rdrift ) dominates in high-voltage devices, a relatively large JBS diode is required to effectively prevent body diode conduction. This is crucial, as bipolar current not only slows switching speed but also accelerates the growth of BPDs into stacking faults (SFs), which degrade the MOSFET's static characteristics [4]. To improve conduction efficiency, reliability, and area efficiency, the integration of the JBS diode directly into the MOSFET structure has been proposed, resulting in Junction Barrier Schottky integrated MOSFETs (JBSFETs) [5]. This architecture combines unipolar conduction with improved third-quadrant performance, greatly reducing dependency on the body diode and enhancing device robustness under high-stress conditions [6]. Moreover, this introduced Schottky path mitigates the BPD-induced degradation, which poses a critical reliability concern for SiC devices [7].

While JBSFETs may exhibit higher specific on-resistance ( Ron,sp ) due to increased cell pitch, structural innovations with efficiently integrated JBS diode enhance the forward conduction, achieving performance comparable to that of MOSFET [8]. Although such performance has been demonstrated in low-voltage devices, replicating this in high-voltage architectures remains challenging. Building on prior work where Stripe JBSFET showed reduced 3rd  quadrant forward voltage drop ( VF ) compared to nominal MOSFET [6], this study extends the technique to enhance the 3rd  quadrant conduction, while offering the same Ron,sp  for high voltage devices. A comparative analysis of JBSFET structures and MOSFET is presented, focusing on structural evolution, trade-offs
in Ron,sp,VF, and the role of Schottky width in reducing leakage current for enhanced high-voltage device reliability.

Device Design and Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

Fig. 1 illustrates the structural differences between the Stripe JBSFET, Island P+ JBSFET, and the Nominal MOSFET. The Nominal MOSFET, where a P+ source is placed in the orthogonal direction, within the linear topology of the unit cell [9], has a reduced cell pitch compared to the conventional stripe MOSFET approach, with a cell pitch of 6μ m. The Stripe JBSFET features a wide cell pitch of 11μ m to accommodate the integration of the linear Schottky region. The Schottky area is allocated in the x-direction along with the MOSFET cell by interrupting the p-well. The nature of the linear stripe pattern of the JBSFET structure creates long linear Schottky regions along with the MOSFET cell in the y-direction. In the Island P+ JBSFET, the Schottky opening is placed in the orthogonal direction, similarly to the MOSFET layout, and is shielded solely by the P -well in the X-direction [8]. As a result, a cell pitch of 6.8μ m was achieved for the Island P+ JBSFET. The structural parameters of each device design are summarized in Table 1.

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Fig. 1. Top layout views of the Nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET structures analyzed in this study.

Fig. 1. Top layout views of the Nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET structures analyzed in this study.

Table 1. Structural parameter summary of each device studied.

Device Type | Cell Pitch (μm) | Active Area [mm²] | Half JFET Width [μm] | Schottky Open in X-axis [μm] | Shielding in X-axis
Nominal MOSFET | 6 | 1.70 | 0.8 | N/A | N/A
Stripe JBSFET | 11 | 1.70 | 0.8 | 2 | P+
Island P+ JBSFET | 6.8 | 1.70 | 0.8 | 1.6 | P-well
5.2 | 0.32 | 0.4 | 0.8 | P-well

[picture]

Fig. 2. Top layout and cross-sectional views of the Schottky contact regions are presented for the Stripe JBSFET (left) and the Island P+ JBSFET (right), featuring Schottky widths ( WS ) of 2μ m and 1.6μ m, respectively, as indicated by the green arrows.

Fig. 2. Top layout and cross-sectional views of the Schottky contact regions are presented for the Stripe JBSFET (left) and the Island P+ JBSFET (right), featuring Schottky widths ( W S ) of 2 μ m and 1.6 μ m , respectively, as indicated by the green arrows.

Fig. 2 illustrates the Schottky region in the Stripe and Island P+ JBSFET featuring a Schottky width ( Ws ) of 2μ m and 1.6μ m, respectively. Cross-sectional views along the X-direction ( A−B and E-F) illustrate how the Schottky region is effectively shielded by the P+ region in the Stripe JBSFET and by the P -well region of the MOSFET in the Island P+ JBSFET. The exclusion of the P+region in the X-direction leads to a significant reduction in cell pitch, resulting in a compacted JBSFET design, which is slightly larger than that of the nominal MOSFET [8]. In the Y-direction (G-H), the Schottky region in the Island P+JBSFET is shielded by the P+ region. To ensure a fair comparison, all devices were fabricated with the same active area, JFET width, and channel length of 1.70 mm2,1.6μ m, and 0.5μ m, respectively. An additional Island P+ JBSFET was evaluated to investigate the impact of a reduced Schottky width (0.8μ m) and a corresponding cell pitch of 5.2μ m on device performance.

A 60μ m thick, 1×1015 cm−3 doped n-type epi-layer on a 4-inch, N+4H-SiC substrate was used to fabricate the JBSFETs, and the Nominal MOSFET. Aluminum ions were implanted to make the Pwell and P+, where the Nitrogen ions were implanted to make the N+ source, respectively. Implantation steps were followed by a 1650∘C10 min activation anneal with a carbon cap. A 50 nm thick gate oxide was formed, followed by a POA in nitric oxide ambient. An interlayer dielectric was deposited and etched using the reactive ion etch process by using the gate pad opening mask to open the ohmic and Schottky regions to avoid an additional mask layer. Ni was deposited on the frontside and patterned, followed by 2−min RTA at 1000∘C. Back-side metal contact was also formed by Ni deposition and the same RTA process. A Ti/Al stack was then deposited to form the Schottky contacts on the N-epitaxial drift layer and also as a top metal for the source metal and gate pad. Front-side was passivated by nitride and polyimide. Finally, a solderable metal stack was deposited on the backside.

Results and Discussion

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Fig. 3 shows the forward conduction of the Nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET. The specific on-resistance ( Ron,sp ), extracted at Ids=0.15 A and Vgs=20 V, is 42.9 mΩ· cm2 for the Stripe JBSFET, 39.9 mΩ· cm2 for the Island P+ JBSFET, and 39.7 mΩ· cm2 for the nominal MOSFET. Due to the reduced cell pitch of the Island P+ JBSFET, a specific on-resistance ( Ron,sp ) comparable to the MOSFET was able to be achieved while also reducing the Ron,sp by 7.5% when compared to the Stripe type JBSFET. Therefore, the adoption of the Island P+ cell architecture is successfully able to improve the JBSFET output characteristics for higher voltage applications,
similar to their lower voltage rating counterparts. Even though the ohmic region is reduced, the specific on-resistance ( Ron,sp ) of Island P+ JBSFET greatly improved due to the utilization of the entire channel region as a conduction path [8].

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Fig. 3. Representative output characteristics of the Nominal MOSFET, Stripe JBSFET, and Island P+JBSFE were plotted at gate biases of Vgs=0 V,10 V, and 20 V .

Fig. 3. Representative output characteristics of the Nominal MOSFET, Stripe JBSFET, and Island P + J B S F E were plotted at gate biases of V g s = 0 V , 10 V , and 20 V .

Fig. 4 shows the 3rd  quadrant characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFET, measured at a gate bias of Vgs=0 V and -5 V . With a Vgs=0 V, the forward voltage drops (VF), extracted at Ids=0.5 A, are 6.60 V for the nominal MOSFET, 2.55 V for the Stripe JBSFET, and 2.25 V for the Island P+JBSFET. A gate bias of Vgs=−5 V is applied to suppress channel conduction and isolate the body-diode and Schottky paths. Notably, despite the discontinuity of the Schottky region in the Island P+ JBSFET, the aggressive cell pitch design increases Schottky density,

[picture]

Fig. 4. The 3rd  quadrant characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFET structures were plotted at a gate bias of Vgs=0 V and -5 V .

Fig. 4. The 3 rd quadrant characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFET structures were plotted at a gate bias of V g s = 0 V and -5 V .

resulting in highly efficient unipolar current conduction and a substantial reduction in VF. These results confirm that Island P+ JBSFET exhibits a lower VF than the Stripe JBSFET and outperforms the MOSFET during the 3rd  quadrant operation.

Fig. 5 shows the forward blocking output characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFETs, measured at a gate bias of Vgs=−5 V to minimize any leakage through the channel. The Stripe JBSFET exhibits the highest leakage current due to the strong electric field beneath its large Schottky region [8], which leads to a soft breakdown. In contrast, the Island P+ JBSFET demonstrated significantly lower Leakage current, largely attributed to the fully surrounded Schottky contact, effectively shielding the contact during the blocking mode of operation [10]. However, the Island P+ JBSFET still demonstrated an increased leakage when compared to the nominal MOSFET. Both the nominal MOSFET and the Island P+ JBSFET exhibited avalanche breakdown at approximately 8.3 kV , confirming the superior blocking capability of the Island P+ design compared to the Stripe JBSFET.

[picture]

Fig. 5. Forward blocking output characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFETs were measured at a gate bias of Vgs=−5 V to minimize any leakage through the channel.

Fig. 5. Forward blocking output characteristics of the Nominal MOSFET, Stripe, and Island P+ JBSFETs were measured at a gate bias of V g s = − 5 V to minimize any leakage through the channel.

Due to the larger leakage current observed within the Island P+ JBSFET, further designs were investigated with the goal of suppressing the overall leakage current during the blocking mode of operation. For this, an alternative Island P+ design with a reduced Schottky width of 0.8μ m was investigated. The resulting forward blocking and 3rd  quadrant output characteristics for the Island P+ JBSFETs with Schottky widths ( Ws ) of 1.6μ m and 0.8μ m are compared in Fig. 6. By reducing the

[picture]

Fig. 6. The 3rd  quadrant (left) and the forward blocking (right) characteristics of the Island P+ JBSFET structure with WS=1.6μ m and 0.8μ m.

Fig. 6. The 3 rd quadrant (left) and the forward blocking (right) characteristics of the Island P + JBSFET structure with W S = 1.6 μ m and 0.8 μ m .

Schottky width to 0.8μ m, a significant decrease in the leakage current was observed, due to the increased shielding over the Schottky contact. However, this reduction also impacts 3rd  quadrant conduction and requires further optimization of Schottky width and process conditions to balance leakage performance with conduction efficiency.

[picture]

Fig. 7. The trade-off between specific on-resistance ( Ron,sp ) and forward voltage drop ( VF ) was analyzed for the Nominal MOSFET, Stripe, and Island P+ JBSFETs, with forward voltage drop extracted at Vgs=0 V and Ids=0.5 A.

Fig. 7. The trade-off between specific on-resistance ( R o n , s p ) and forward voltage drop ( V F ) was analyzed for the Nominal MOSFET, Stripe, and Island P+ JBSFETs, with forward voltage drop extracted at V g s = 0 V and I d s = 0.5 A .

Fig. 7 summarizes the trade-off between specific on-resistance ( Ron,sp ) and forward voltage drop (VF) for the nominal MOSFET, Stripe JBSFET, and Island P+ JBSFET. The Stripe JBSFET structure demonstrates improved 3rd  quadrant performance but suffers from the highest Ron,sp , and leakage current. In contrast, the Island P+ design achieves the lower Ron,sp than the Stripe structure, which offers almost the same Ron,sp as the nominal MOSFET. The superior 3rd quadrant performance of the Island P+ structure is due to the design innovation that achieves a smaller cell pitch. Despite a slightly larger cell pitch than the MOSFET, the Island P+JBSFET demonstrates well-balanced performance in forward conduction, 3rd quadrant behavior, and leakage current, underscoring its strong potential as a next-generation high-voltage, reliable power device.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

This work compared 6.5 kV -rated 4H-SiC JBSFET architectures with a nominal MOSFET in terms of forward conduction, third-quadrant behavior, and blocking capability. The Stripe JBSFET improved third-quadrant conduction but suffered from the highest Ron,sp, leakage current, and cell pitch. In contrast, the Island P+ JBSFET achieved nearly identical Ron,sp to the MOSFET, superior third-quadrant performance, and a high breakdown voltage of 8.3 kV . Reducing Schottky width to 0.8μ m further suppressed leakage, though at the expense of third-quadrant conduction, emphasizing the need for design trade-offs. Overall, the Island P+ JBSFET offers the best balance of conduction efficiency, leakage suppression, and blocking robustness, highlighting its promise as a reliable highvoltage 4H−SiC power device. Future work will focus on optimizing Schottky width and process conditions, scaling to higher voltage ratings, and validating long-term reliability under dynamic switching stress.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.21.pdf

B Jayant Baliga, Fundamentals of power semiconductor devices. New York, NY: Springer, 2008, Chap.3, pp. 91-155.

R. Callanan, J. Rice, and J. Palmour, "Third quadrant behavior of SiC MOSFETs," in Proc. 28th Annu. IEEE Appl. Power Electron. Conf., Mar. 2013, pp. 1250-1253.

W. Sung and B. J. Baliga, "Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme," in IEEE Electron Device Letters, vol. 37, no. 12, pp. 1605-1608, Dec. 2016, doi: 10.1109/LED.2016.2618720.

A. Agarwal, H. Fatima, S. Haney, and S.-H. Ryu, "A New Degradation Mechanism in HighVoltage SiC Power MOSFETs," IEEE Electron Device Letters, vol. 28, no. 7, pp. 587-589, July. 2007. doi: 10.1109/LED.2007.897861

W. Sung and B. J. Baliga, "On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)," in IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 8206-8212, Oct. 2017, doi: 10.1109/TIE.2017.2696515.

N. Yun et al., "Comparative Study of 6.5 kV 4H-SiC Discrete Packaged MOSFET, JBSFET, and Co-Pack (MOSFET and JBS Diode)," 2022 IEEE 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vancouver, BC, Canada, 2022, pp. 249-252, doi: 10.1109/ISPSD49238.2022.9813639

R. E. Stahlbush, K. N. A. Mahakik, A. J. Lelis, and R. Green, "Effects of Basal Plane Dislocations on SiC Power Device Reliability," 2018 IEEE International Electron Devices Meeting (IEDM), Dec. 2018, doi: 10.1109/iedm.2018.8614623.

S. A. Mancini, S. Yup Jang, D. Kim and W. Sung, "Exploring Optimum Designs for 1.2 kV 4HSiC JBS Diode Integrated MOSFETs (JBSFETs)," 2022 IEEE 9th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), Redondo Beach, CA, USA, 2022, pp. 11-16, doi: 10.1109/WiPDA56483.2022.9955290.

A. Saha and J. A. Cooper, "A 4H-SiC Power DMOSFET Optimized for Low onResistance," in IEEE Transactions on Electron Devices, vol. 54, no. 10, pp. 2786-2791, Oct. 2007, doi: 10.1109/TED.2007.904577.

S. A. Mancini, S. Y. Jang, D. Kim and W. Sung, "Increased 3rd Quadrant Current Handling Capability of 1.2 kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances," 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Redondo Beach, CA, USA, 2021, pp. 101-106, doi: 10.1109/WiPDA49284.2021.9645152.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 29-36

doi: 10.4028/p-JFK9oG

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-25

Revised:
2025-12-28

Accepted:
2026-01-31

Online:
2026-05-19

Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

Zhaowen He a*, Giorgian Borca-Tasciuc b and T. Paul Chow c

Rensselaer Polytechnical Institute, Troy, New York 12180, U.S.A

a  hez5@rpi.edu, b  borcag2@rpi.edu, c  chowt@rpi.edu

Keywords: High Voltage, 4H-SiC, Power MOSFET, Bidirectional, Cryogenic.

Abstract

We have demonstrated an integrated 3.3 kV 4H-SiC vertical planar bidirectional (BD) conventional (Conv) power DMOSFET in common-drain (CD) configuration using two commercially available power DMOSFET dies and study its operation down to 77 K(−196∘C) to evaluate its cryogenic static and switching performance. The BD conduction and blocking are achieved down to 77 K . The measured specific on-resistance ( RON,sp ) of the BD MOSFET at room temperature (RT) is 26 mΩ - cm2, approximately twice that of the unidirectional device. It increases by 54% when cooled to 77 K due to a substantial increase in channel and possibly JFET on-resistance components. In addition, the extracted specific switching losses ( EON,sp and EOFF,sp ) increases by 33%(13%) at 195 K(−77∘C) and by 83%(88%) at 77 K , relative to their RT values. These increases are primarily attributed to the substantial rise in RON,sp at 77 K . As a result, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance under cryogenic operation, driven mainly by the significant increase in channel and JFET resistance components.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

Cryogenic-capable bidirectional (BD) AC-to-AC power switches are essential for extraterrestrial space missions as well as for superconducting and quantum computing applications. Also, these power switches enable more compact systems and improved integrations, critical for applications where mass, volume, and thermal management constraints are stringent. Compared to the Si counterparts, 4 H -SiC BD power DMOSFETs may be a good candidate for such applications owing to the wide bandgap of 3.26 eV , high critical electric field, and superior thermal conductivity.

[picture]

Fig. 1. Half-cell schematic cross-sections of vertical BD Conv DMOSFETs in (a) Commondrain (CD) configuration. (b) Common-source (CS) configurations.

Fig. 1. Half-cell schematic cross-sections of vertical BD Conv DMOSFETs in (a) Commondrain (CD) configuration. (b) Common-source (CS) configurations.

However, several studies have reported anomalous temperature dependence [1-3] of the specific onresistance (Ron,sp) in unidirectional (UD) commercial 4H-SiC DMOSFETs at cryogenic temperatures, potentially degrading on-state performance. In addition, switching performance degradation at low temperatures has also been documented in the literature [4,5]. These findings highlight the need to investigate and evaluate the cryogenic performance of high-voltage 4H−SiCBD conventional (Conv) DMOSFETs. In this paper, an integrated 3.3kV4H−SiCBD conventional (Conv) DMOSFET is demonstrated and studied down to 77 K(−196∘C) to evaluate its cryogenic static and switching performance.

Device Structure and Integration

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

The vertical BD power DMOSFET can be realized in either common-drain (CD) or commonsource (CS) configurations, as illustrated in Fig. 1. In the CD configuration, the drains of the two planar DMOSFETs are tied together, while the gate of the high-side transistor is biased with a floating power supply to keep the channel on. In the CS configuration, the sources and gates of both devices are connected. The CD configuration simplifies packaging for discrete unidirectional (UD) power transistors but requires separate gate drivers, whereas the CS configuration reduces driver count to one at the expense of more packaging complexity.

Traditional BD functionality is often achieved through hybrid package implementations (Fig. 2) using discrete devices [6]. For example, an anti-series connection of two MOSFETs is used to achieve this, which doubles the on-resistance (Ron) compared to a single device. To mitigate this increase, two identical anti-series pairs can be placed in parallel, but this quadruples the total chip area.

In addition, integrated BD DMOSFETs can be realized using a die-bonded approach (Fig. 2). In this method, two power device dies are bonded back-to-back in a BD package with a metallic interposer. As demonstrated in [7], two 1.2−kV 4H-SiC Conv DMOSFETs in a CD configuration achieve the same chip area as a UD device. This die-bonded approach retains the simplicity of hybrid packaging while enabling a more compact footprint for power module integration.

Monolithic implementations, often in CD configurations, further reduce device count and bondwire connections. In a true monolithic BD Conv DMOSFET, a shared drift region with dual gates enables bidirectional blocking, cutting RON roughly in half for high-voltage ( >3kV ) applications where drift resistance dominates. In 4H−SiC, this implementation was demonstrated in [8] with the BiDFET device (Fig. 2), which achieves a blocking voltage of ±1200 V. The BiDFET consists of two 1.2−kV vertical Conv DMOSFETs in a common-drain configuration, each integrated with a JBS diode. Two drift regions are employed-one for each blocking direction-connected through an N+ substrate and backside drain metallization. While this design benefits from full on-chip integration, it incurs penalties of doubled chip area and doubled specific on-resistance due to the dual drift regions.

[picture]

Fig. 2. Three approaches for implementing vertical BD Conv DMOSFETs in CD configurations.

Fig. 2. Three approaches for implementing vertical BD Conv DMOSFETs in CD configurations.

On the other hand, Chowdhury et al. [9] demonstrated a compact, vertical implementation of monolithic BD 4H-SiC IGBT with shared drift region via the double-sided lithography processes on a free-standing 4H-SiC substrate [10]. The initial prototype devices experimentally achieved blocking voltages of up to 7 kV . This work presents a promising approach for the vertical monolithic integration of 4H−SiCBD DMOSFETs. However, such implementation requires double-sided processes, which increases complexity and cost in fabrication and chip manufacturing.

In this work, the 3.3 kV 4H-SiC BD Conv DMOSFET prototype is vertically implemented in the CD configuration via integrated die-bonded approach using two commercially available Wolfspeed (CPM3-3300-R050A) SiC Gen3 MOSFET dies, as schematically shown in Fig. 3(a). Fig. 3(b) shows the BD DMOSFET chip in a customed BD package. This BD chip is fabricated by joining the drain metal contacts of the two dies using a commercially available nanoparticle silver paste, followed by a 200∘C sintering process. The custom package is constructed by sandwiching the BD die between two through-hole G10 substrates, sealed with silicone for mechanical and environmental protection. A 30μ m Parylene layer and hard baked photoresist layer are used to passivate the exposed die sides, surfaces, and bonding wires.

[picture]

Fig. 3. (a) Circuit schematics and schematic cross-section of the implemented 3.3kV4H−SiC Conv BD DMOSFET in Common-drain configuration. (b) Photo and cross-section of the custom BD DMOSFET package.

Fig. 3. (a) Circuit schematics and schematic cross-section of the implemented 3.3 k V 4 H − S i C Conv BD DMOSFET in Common-drain configuration. (b) Photo and cross-section of the custom BD DMOSFET package.

[picture]

Fig. 4. Temperature-dependent on-state characteristics. (a) Output I-V curves measured at 77, 195, and 300 K for VGS =0,8, and 18 V . (b) Transfer characteristics at VDS =0.1 V over the same temperature range. (c) Estimated specific on-resistance (Ron,sp) components-drift, channel, substrate, and others-extracted at 77,195,300, and 423 K . (d) Threshold voltage ( VT ) as a function of temperature, exhibiting a linear dependence with a temperature coefficient of −12mV/K.

Fig. 4. Temperature-dependent on-state characteristics. (a) Output I-V curves measured at 77, 195, and 300 K for VGS = 0 , 8 , and 18 V . (b) Transfer characteristics at VDS = 0.1 V over the same temperature range. (c) Estimated specific on-resistance (Ron,sp) components-drift, channel, substrate, and others-extracted at 77 , 195 , 300 , and 423 K . (d) Threshold voltage ( V T ) as a function of temperature, exhibiting a linear dependence with a temperature coefficient of − 12 m V / K .

Results and Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

On-state characteristics were measured using a Tektronix 370A curve tracer. An Agilent B1505A power device analyzer equipped with an N1268A ultra-high-voltage expander was used to characterize BVDSS. 

Inductive load switching is performed using a customized inductive load ( 12 mH ) double pulse test (DPT) setup (Fig.6) at 200 V and 5 A with a 100Ω gate resistance ( RG ). A 1.2−kV Rohm SiC commercial Schottky diode (SCS120KGC) was used as the flyback diode to suppress reverse recovery effects. The power supply was set to 200 V , and the gate pulse width was adjusted to achieve a switching current of 5 A . Because the CD configuration requires independent gate drivers, only one device was actively switched, while the other device's gate was held at 18 V .

Fig.4(a) shows the output I-V characteristics of our prototype BD MOSFET at 77(−196∘C),195(−77∘C), and 300 K(27∘C). The output I-Vs show symmetric BD conduction at all three testing temperatures. Extracted RON,sp of the BD device ( VGS=18 V ) at room temperature (RT) is 26 mΩ cm2, which is doubled of the RON,sp of the UD device ( 13 mΩ−cm2 ). Measured RON,sp increased by 54% at 77 K and decreased by 23% at 195 K , showing a "bathtub-shaped" temperature dependence. This is consistent with trends previously reported for UD commercial conventional 4H−SiC DMOSFETs [1,2]. Estimated major resistance components at 77,195,300, and 423 K(150∘C) are plotted in Fig. 4(c). The drift-region resistance component increases monotonically with temperature. Although significant carrier freeze-out occurs at 77 K , the drift resistance still decreases markedly to
21% of its room-temperature value, owing to approximately 20 times increase in bulk electron mobility, as estimated using the temperature-dependent model reported in [16]. On the other hand, estimated channel resistance component exhibits a well-known negative temperature coefficient due to mobility degradation from high interface trapping and increase in threshold voltage at cryogenic temperatures. Interestingly, estimated other lumped resistance components show a non-linear temperature dependence from 77 to 423 K . This non-linear temperature dependence could originate from non-linearity of JFET resistance component from the DMOS structure. According to a reported study of 4H−SiC JFET performance at cryogenic and high temperature [17], the JFET resistance increases with temperature above 200 K , primarily due to the temperature dependence of bulk mobility. Under cryogenic conditions, both [3] and [17] have shown that a shift in the JFET threshold voltage from channel pinch-off, along with carrier freeze-out in the quasi-neutral region, are responsible for the substantial rise in JFET resistance. Due to such reasons, this increase in JFET resistance is predicted to be more pronounced for smaller pitch planar DMOSFETs at 77 K [3]. Therefore, channel and JFET resistance components are likely to dominate in this device at cryogenic temperatures.

The transfer I-V characteristics at VDS=0.1 V are shown in Fig.4(b). Extracted threshold voltages are 7.2,6, and 4.1 V at 77,195 , and 300 K , respectively, exhibiting a monotonic decrease with temperature. To assess the temperature dependence, threshold voltages were extracted up to 423 K . A linear fit across the 77−423 K range yields a negative slope of −12mV/K, consistent with previously reported trends [2]. The ideal threshold voltages from 77 to 423 K , shown as the red curve in Fig. 4(d), were calculated assuming a fixed oxide charge density of 2e12 cm−2, yielding a slope of −2.5mV/K. The deviation between measured and ideal values becomes more pronounced at lower temperatures, suggesting that the discrepancy could originate from increased filled interface charge (Qit) at SiO2/SiC interface at lower temperatures.

[picture]

Fig. 5. (a) Blocking IVs at 77 and 300 K . (b) RoN,sp vs. BV trade-off comparison of the implemented 3.3−kV4H−SiC BD Conv DMOSFET at room temperature (RT) and 77 K . For reference, the authors' prior works on high-voltage 4H−SiC BD superjunction (SJ) [13] and charge-balanced (CB) [14] devices are included, demonstrating improved trade-offs compared to the Conv BD device reported in this work. Commercial high-voltage 4H−SiC UD DMOSFETs are also shown for benchmarking.

Fig. 5. (a) Blocking IVs at 77 and 300 K . (b) RoN,sp vs. BV trade-off comparison of the implemented 3.3 − k V 4 H − S i C BD Conv DMOSFET at room temperature (RT) and 77 K . For reference, the authors' prior works on high-voltage 4 H − S i C BD superjunction (SJ) [13] and charge-balanced (CB) [14] devices are included, demonstrating improved trade-offs compared to the Conv BD device reported in this work. Commercial high-voltage 4 H − S i C UD DMOSFETs are also shown for benchmarking.

[picture]

Fig. 6. Customized inductive load double pulse test (DPT) setup for switching characterization.

Fig. 6. Customized inductive load double pulse test (DPT) setup for switching characterization.

[picture]

Fig. 7. Switching waveforms at 77, 195, and 300 K of the implemented 3.3 kV BD Conv DMOSFET (a) Turn-on waveforms. (b) Turn-off waveforms.

Fig. 7. Switching waveforms at 77, 195, and 300 K of the implemented 3.3 kV BD Conv DMOSFET (a) Turn-on waveforms. (b) Turn-off waveforms.

The blocking I-V characteristics at RT and 77 K are shown in Fig. 5(a). Over 3.4 kV and 3.8 kV BD blocking is achieved at RT and 77 K , respectively. An anomalous increase in BV DSS is observed at 77 K . In both the literature [11] and our prior work [12] on commercial packaged UD 4H-SiC DMOSFETs, the BV DSS has consistently shown a positive temperature coefficient, as expected when breakdown is limited by the intrinsic avalanche mechanism. This behavior arises from the reduced ionization path length at elevated temperatures. Hence, better termination performance could be one of the possible explanations for this anomalous increase in BVDSS  at 77 K .

At 77 K , RON,sp increases by 54% while BVDSS improves by only ~10%, resulting in a degraded RON,sp  vs. BVDSS  trade-off for this device (Fig. 5(b)). Consequently, static performance of the testing device is expected to deteriorate under cryogenic operation.

Fig. 7 compares the switching performance of the implemented 3.3 kV BD Conv DMOSFET at 77, 195, and 300K. During turn-on (Fig.7(a)), the specific energy loss (EON,sp) increases from 0.6 mJ/cm2 at 300 K to 1.1 mJ/cm2 at 77 K , showing an 83% increase in turn-on losses at cryogenic temperatures. In addition, the turn-off waveforms (Fig. 7(b)) also show an increase in energy loss, with Eoff,sp rising from 0.8 mJ/cm2 at 300 K to 1.5 mJ/cm2 at 77 K , exhibiting an 88% increase. This increase in both turn-on and turn-off switching energy is attributed to significant increase of RON,sp at 77 K . Hence, VDS waveforms at 77 K during turn-on and turn-off exhibiting a noticeable slow tail and head while IDS is still high. Overall, the results demonstrate that while BD Conv DMOSFETs maintain functional
switching operation across the full temperature range, both turn-on and turn-off losses increase significantly at cryogenic temperatures, leading to a degradation in dynamic performance.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

An integrated 3.3 kV 4H-SiC vertical BD Conv DMOSFET is successfully demonstrated to maintain bidirectional conduction and blocking capability down to cryogenic temperatures. At 77 K , the channel resistance and possibly JFET resistance from DMOS structure becomes the dominant component, primarily due to inversion electron mobility degradation caused by increased Coulombic scattering. Consistent with UD 4H-SiC DMOSFETs, the implemented BD Conv DMOSFET exhibits degradation in both on-state and switching performance at 77 K , primarily due to the significant increase in channel and JFET on-resistance components.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

The authors would like to thank Wolfspeed, Inc. for providing the 3.3kV4H−SiC commercial Conv power DMOSFET dies used in the bidirectional implementation of this work.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.29.pdf

K. Hong et al., "Experimental investigations into temperature and current dependent on-state resistance behaviors of 1.2 kV SiC MOSFETs", IEEE Journal of the Electron Devices Society, no.7, pp. 925-930, 2019.

S. Chen et al., "Cryogenic and high-temperature performance of power MOSFETs ", 28th Annual IEEE APEC, 2013, pp. 1277-1283.

S. Chowdhury et al., "Comparative evaluation of commercial 1200 V SiC power MOSFETs using diagnostic IV characterization at cryogenic temperatures", Mat. Sci. Forum, vol 897, pp. 545-548, 2017.

Y. Wei et al., "Cryogenic performances comparisons among Si MOSFET, SiC MOSFET, cascode GaN, and GaN devices," IOP Conference Series: Materials Science and Engineering, vol. 1241, pp. 012042, 2022.

K. Tian et al., "Comprehensive characterization of the planar and trench gate MOSFETs from cryogenic to high temperature," IEEE Transactions on Electron Devices, vol. 66, no. 10, pp. 4279-4286, Oct. 2019.

J. Huber and J. W. Kolar, "Monolithic bidirectional power transistors," IEEE Power Electronics Magazine, vol. 10, no. 1, pp. 28-38, Mar. 2023.

C. Hitchcock and T. P. Chow, "Common-drain bidirectional 1200 V SiC MOSFETs," Materials Science Forum, vol. 1004, pp. 882-888, 2020.

K. Han et al., "Monolithic 4-terminal bi-directional field effect transistor (BiDFET) with integrated JBS diodes," Proc. 32nd Int. Symp. Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, Sept. 2020, pp. 242-245.

S. Chowdhury et al., "Operating principles, design considerations, and experimental characteristics of high-voltage bidirectional IGBTs," IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 888-896, Mar. 2017.

S. Chowdhury et al., "Characteristics of 4H-SiC P-i-N diodes on lightly doped free-standing substrates," Proc. 27th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), May 2015, pp. 353-356.

P. Steinmann et al., "Temperature dependence of avalanche breakdown in devices," Journal of Applied Physics, vol. 133, no. 23, pp. 235705, 2023.

Z. He et al., "Comparative performance evaluation and analysis of high voltage superjunction, charge-balanced, and conventional 4H-SiC DMOSFETs at cryogenic and high temperatures," Proc. 37th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), 2025.

Z. He et al., "Experimental demonstration and analysis of 4.5 kV bidirectional superjunction power DMOSFETs in 4H-SiC," Proc. 37th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), 2025.

Z. He et al., "Experimental comparative demonstrations and analysis of common-drain and common-source bidirectional charge-balanced power DMOSFETs switching," Proc. 36th Int. Symp. Power Semiconductor Devices and ICs (ISPSD), 2024, pp. 140-143.

R. Ghandi et al., "Scalable ultrahigh voltage SiC superjunction device technologies for power electronics applications," Proc. IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 9-1.

S. Kagamihara et al., "Parameters required to simulate electric characteristics of SiC devices for n-type 4H-SiC," J. Appl. Phys., vol. 96, no. 23, pp. 5601-5606, 2004.

Cheng et al., "Cryogenic and high temperature performance of vertical junction field effect transistors (VJFETs) for space applications," Proc. Int. Symp. Power Semiconductor Devices and ICs (ISPSD), Santa Barbara, CA, USA, 2005, pp. 231-234.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 37-44

doi: 10.4028/p-2newLP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-17

Accepted:
2026-01-31

Online:
2026-05-19

Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

Stephen A. Mancini 11,a*, Daixin Chen 2,b, Seung Yup Jang 1,4,c, Andrew Binder 3,d, Richard Floyd 3,e, Robert Kaplar 3,f, Jack Flicker 3, g, Adam Morgan 4, h, Xiaoqing Song 2,i, Woongje Sung 1,j

1Department of Nanotechnology Science and Engineering, University at Albany, Albany, NY, 12203, USA

2 Department of Electrical Engineering and Computer Science, University of Arkansas, Fayetteville, AR, 72703, USA

3 Sandia National Laboratories, Albuquerque, NM, USA

4 NoMIS Power Corporation, Albany, NY, USA

a  smancini@albany.edu, b  daixinc@uark.edu, c  sjang3@albany.edu, d  abinder@sandia.gov, e rsfloyd@sandia.gov, f rjkapla@sandia.gov, g satcitt@sandia.gov,

h  adam.morgan@nomispower.com, i  songx@uark.edu, j  wsung@albany.edu

Keywords: 4H-silicon carbide (SiC), bi-directional switch, bi-directional MOSFET, common drain, monolithic integration, design approach.

Abstract

Several 1.2 kV 4H-SiC Bi-Directional MOSFETs (BiD-MOS) design approaches were successfully fabricated and evaluated based on their electrical characteristics. Both monolithic integration design approaches exhibited negligible differences in conduction, blocking, and switching characteristics when compared to their 2-Chip counterpart. However, during the short-circuit withstand time testing, severe gate oscillations were observed in the 2-Chip design, which was not an issue present in either monolithic configuration. As a result of its robust electrical behavior, monolithic integration emerges as a promising design approach for developing efficient and reliable Bi-Directional Switches.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

With the global shift toward electrification, the demand for highly efficient AC-AC and AC-DC converters capable of conducting current and blocking voltage in both forward and reverse directions is rapidly increasing. Conventional power conversion systems (PCS) that employ Bi-Directional switches typically rely on multiple MOSFETs and diode components, which introduce substantial switching losses and increase overall system complexity [1]. Therefore, implementing a single BiDirectional switch offers the potential to simplify the system architecture, reduce the total number of components, and improve both switching efficiency and overall device performance, making it an attractive solution for modern power electronics applications. In line with this approach, several demonstrations of 4H−SiC Bi-Directional Field Effect Transistors (BiDFETs) as monolithically integrated, single-chip devices have been reported [2,3]. However, when using vertical MOSFET technology, the larger chip area required for monolithic integration raises concerns about yield loss and manufacturing efficiency, motivating the exploration of more area-efficient alternatives [4]. While these designs offer promising reductions in chip area even when considering yield losses due to chip size [5], their electrical performance remains insufficiently characterized, leaving questions about trade-offs between integration, efficiency, and reliability. This study investigates the electrical performance of various Bi-Directional MOSFET (BiD-MOS) designs, providing a comprehensive assessment of the feasibility and advantages of monolithic integration for high-performance BiDirectional switching applications.

Device Design and Fabrication

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

Fig. 1 shows the top and cross-sectional views of three BiD-MOS design approaches evaluated in this study. These include: (1) a 2-Chip solution using two discrete MOSFETs, (2) a monolithic design with two MOSFETs side-by-side on a single chip and matching the area of the 2-Chip solution, and (3) a monolithic design featuring a shared channel stop integrated within the edge termination to reduce die area [4,5]. These designs are referred to as the 2-Chip, Mono, and Mono SN+ BiD-MOS, respectively. The monolithic designs, fabricated as single chips on the wafer, are inherently restricted to the Common-Drain configuration. In contrast, the 2-Chip solution, being composed of separate device components, can be implemented in either Common-Source or Common-Drain form. To ensure a consistent basis for comparison, the 2-Chip solution was also evaluated in the CommonDrain configuration for this study.

[picture]

Fig. 1. Top layout and simplified cross-sectional views of the three Bi-Directional MOSFET (BiDMOS) design approaches examined within this study. The 2-Chip BiD-MOS approach utilizes two individual MOSFET components, whereas the Monolithically integrated BiD-MOS designs employ a single chip solution.

Fig. 1. Top layout and simplified cross-sectional views of the three Bi-Directional MOSFET (BiDMOS) design approaches examined within this study. The 2-Chip BiD-MOS approach utilizes two individual MOSFET components, whereas the Monolithically integrated BiD-MOS designs employ a single chip solution.

In addition to all devices adopting the Common-Drain configuration, the individual MOSFETs used in the monolithic BiD-MOS and the discrete MOSFET components shared the same design and layout. To maximize device performance, 2D electrical simulations were conducted to optimize both the active and edge termination regions. For the active area cell design, the channel length and JFET width were set to 0.5μ m and 1μ m, respectively. The subsequent active area of each MOSFET component was designed to be 0.44 mm2 to achieve the desired current rating. To achieve the 1.2 kV voltage rating, a Hybrid-JTE edge termination was employed to ensure reliable blocking behavior and low leakage current for all devices [6]. In the Mono SN+ design, the channel stop at the end of the termination was shared by both MOSFETs along their common side, thereby reducing die area by enabling the individual MOSFET components to be placed closer together.

The MOSFETs used in the 2-Chip design, along with all monolithic BiD-MOS designs, were fabricated on the same wafer at X-FAB, USA, under identical process conditions. To achieve the targeted 1.2 kV voltage rating, a 10μ m-thick N -type epitaxial drift layer with a doping concentration of 8×1015 cm−3 was grown on top of a heavily doped, N+4H−SiC substrate. Nitrogen and aluminum ion implantation were employed to form the JFET/ N+and P-Well/P +/JTE regions, respectively, followed by a 10 -minute activation anneal at 1650∘C. After the implantation steps, a 50 nm -thick gate oxide was then grown, followed by the deposition of polysilicon. Both layers were then patterned and etched to form the gate regions. This was followed by deposition and patterning of an interlayer dielectric (ILD), enabling the sequential formation of ohmic and gate contacts. A Ti/TiN/AlCu metal stack was subsequently deposited to establish ohmic contacts with the 4H−SiC substrate and the polysilicon gate. The metal stack was then patterned to form the gate and source pads within each device.

To complete the fabrication process, a thick SiN and polyimide layer was deposited and patterned to provide surface passivation. After fabrication, both the 2-Chip and monolithic BiD-MOS designs were packaged in a SOT-227 module for evaluation, as shown in Fig. 2.

[picture]

Fig. 2. Top views of the 2-Chip and Monolithic BiD-MOS design approaches (Top and bottom left, respectively) with the key device regions labeled. Due to the shared substrate limitations of the monolithic designs, both approaches utilize a common-drain configuration and are packaged inside a SOT-227 package (right) with the assistance of NoMIS Power.

Fig. 2. Top views of the 2-Chip and Monolithic BiD-MOS design approaches (Top and bottom left, respectively) with the key device regions labeled. Due to the shared substrate limitations of the monolithic designs, both approaches utilize a common-drain configuration and are packaged inside a SOT-227 package (right) with the assistance of NoMIS Power.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

The measured output of each BiD-MOS design approach in both the forward ( S2→ S1 ) and reverse (S2← S1) directions are shown in Fig. 3. For these measurements, the high-side gate (VG2−S2 for the forward direction and VG1−S1 for the reverse direction) was set to either 20 V or -5 V , while the opposite gate was gradually increased to allow current conduction either through both channel regions or through the body diode of the first MOSFET and the channel region of the second MOSFET. Regardless of the BiD-MOS conduction mode, each design approach exhibited nearly identical output characteristics. When both MOSFET channels were in the on-state ( VG2−S2=VG1−S1=20 V ), the average Ron  values were 169.8 mΩ,169.1 mΩ, and 166.1 mΩ for the 2-Chip, Mono, and Mono SN+ design approaches, respectively. Although minimal, it is important to note that the Mono design, and to a larger extent the Mono SN+ design, resulted in a slightly lower Ron  when compared to the 2-Chip solution counterpart.

[picture]

Fig. 3. Measured output characteristics for each BiD-MOS design approach in both the forward (S2→ S1) and reverse directions (S2← S1), with a gate bias of VG2−S2=20 V and VG1−S1=20 V applied for the forward and reverse directions, respectively (a), and with a gate bias of VG2−S2=−5 Vand VG1−s1=−5 V applied for the forward and reverse directions, respectively (b). Minimal differences between each BiD-MOS design are observed for each conduction mode of operation.

Fig. 3. Measured output characteristics for each BiD-MOS design approach in both the forward ( S 2 → S 1 ) and reverse directions ( S 2 ← S 1 ) , with a gate bias of V G 2 − S 2 = 20 V and V G 1 − S 1 = 20 V applied for the forward and reverse directions, respectively (a), and with a gate bias of V G 2 − S 2 = − 5 V and V G 1 − s 1 = − 5 V applied for the forward and reverse directions, respectively (b). Minimal differences between each BiD-MOS design are observed for each conduction mode of operation.

[picture]

Fig. 4. Simulated current density of the 2-Chip, Mono, and Mono SN+ BiD-MOS design approaches. Both monolithic designs demonstrate conduction through the common epitaxial drift and substrate layers, subsequently increasing the overall current flow.

Fig. 4. Simulated current density of the 2-Chip, Mono, and Mono SN+ BiD-MOS design approaches. Both monolithic designs demonstrate conduction through the common epitaxial drift and substrate layers, subsequently increasing the overall current flow.

To further examine the conduction behavior of the various BiD-MOS design approaches, simplified 2D electrical simulations were performed to highlight potential trends between the structures, as shown in Fig. 4. These simulations reveal that current conduction occurs primarily through the common drain of each BiD-MOS. However, for the Mono design, and more prominently for the Mono SN+ design, current conduction also occurs through the common epitaxial drift and substrate layers. Specifically, the current conduction through the epitaxial drift layer, substrate, and common drain is 0.74%,9.15%, and 90.11% for the Mono BiD-MOS, and 3.66%,32.22%, and 64.12% for the Mono SN+BiD-MOS, respectively, for these simulations. In contrast, due to the layout of the 2-Chip design, current conduction is restricted exclusively to the common drain. The presence of additional conduction pathways in the monolithic designs helps reduce current crowding and slightly improve conduction behavior, resulting in a 1.6% improvement between the Mono and 2-Chip designs. Furthermore, by bringing the MOSFET components closer together in the Mono SN+ design, the conduction pathway is shortened, and overall resistance is reduced, leading to a 7.8% improvement over the 2-Chip design.

The measured blocking characteristics of each BiD-MOS design in both the forward ( S2→ S1 ) and reverse ( S2← S1 ) directions are shown in Fig. 5. For these measurements, both the high- and lowside gates of the BiD-MOS were set to 0 V . All three BiD-MOS designs exhibited similar blocking behavior, with a breakdown voltage of approximately 1620 V and a leakage current below 1 nA at VS2−S1=1200 V. As illustrated in Fig. 6, the blocking capability of each BiD-MOS is determined by the edge termination structure of the low-side device, as this MOSFET operates in its forwardblocking mode. In contrast, the high-side device has no impact on blocking performance. Since all BiD-MOS designs employ the same edge termination, their blocking performance is nearly identical.

[picture]

Fig. 5. Typical measured blocking characteristics of each BiD-MOS design approach in both the forward ( S2→ S1 ) and reverse directions ( S2← S1 ) (a), along with the leakage current in the forward direction (b). Minimal differences between each BiD-MOS design approach are observed.

Fig. 5. Typical measured blocking characteristics of each BiD-MOS design approach in both the forward ( S 2 → S 1 ) and reverse directions ( S 2 ← S 1 ) (a), along with the leakage current in the forward direction (b). Minimal differences between each BiD-MOS design approach are observed.

[picture]

Fig. 6. Simulated electric field and electrostatic potential of the 2-Chip and Monolithic BiD-MOS design approaches during the blocking mode. In both cases, the blocking characteristics are governed by the edge termination of the low-side device, resulting in comparable blocking performance.

Fig. 6. Simulated electric field and electrostatic potential of the 2-Chip and Monolithic BiD-MOS design approaches during the blocking mode. In both cases, the blocking characteristics are governed by the edge termination of the low-side device, resulting in comparable blocking performance.

The switching characteristics of the various BiD-MOS designs were evaluated using a double-pulse test (DPT) setup, with the turn-on and turn-off waveforms shown in Fig. 7. For this analysis, the highside gate (VG2−S2 for the forward direction and VG1−S1 for the reverse direction) was set to 20 V , and switching was performed on the low-side component. Similar to the conduction and blocking measurements, only minimal differences were observed among the design approaches, with the resulting turn-on, turn-off, and total switching losses measuring approximately 0.81 mJ,0.69 mJ, and 1.50 mJ , respectively, for each design.

[picture]

Fig. 7. Measured turn-on (a) and turn-off (b) switching waveforms for each BiD-MOS design approach using a double-pulse test (DPT) setup. During the measurements, VG2−S2=20 V was applied, with the following parameters: gate resistance =10Ω, on-state gate voltage VG1−S1=20 V, off-state gate voltage VG1−S1=−5 V, switching current IS2−S1=50 A, and blocking voltage VS2−S1=800 V.

Fig. 7. Measured turn-on (a) and turn-off (b) switching waveforms for each BiD-MOS design approach using a double-pulse test (DPT) setup. During the measurements, V G 2 − S 2 = 20 V was applied, with the following parameters: gate resistance = 10 Ω , on-state gate voltage V G 1 − S 1 = 20 V , off-state gate voltage V G 1 − S 1 = − 5 V , switching current I S 2 − S 1 = 50 A , and blocking voltage V S 2 − S 1 = 800 V .

To further the evaluation of the various BiD-MOS design approaches, several Short Circuit Withstand Time (SCWT) tests were conducted. Unlike the previous analysis, a noticeable difference can be observed between the 2-Chip and monolithic design approaches, as seen in Fig. 8. Under modified test conditions of VS2−S1=100 V, with a 2μ s pulse, the 2-Chip BiD-MOS exhibited significant oscillations in the gate turn-off waveforms, which were absent in both monolithic configurations. These oscillations were consistent for all 7 measured 2-Chip BiD-MOS samples. Since the gate could not be properly turned off, the resulting SCWT for the 2-Chip approach was unable to be fully determined. However, under typical SCWT evaluation conditions (i.e. VD2−S1=800 V), the Mono and Mono SN+ designs demonstrated comparable SCWTs of 3.82μ s and 3.67μ s, respectively.

[picture]

Fig. 8. VG1−S1 waveforms during the SCWT test in which VS2−S1=100 V, SWCT pulse =2μ s, and VG2−S2=20 V were used (a), and typical SCWT test (i.e. VS2−S1=800 V, and VG2−S2=20 V ) for both monolithic BiD-MOS designs (b). Large oscillations are seen within the VG1−S1 turn-off waveform for the 2-Chip approach that is not present in either of the monolithic designs.

Fig. 8. V G 1 − S 1 waveforms during the SCWT test in which V S 2 − S 1 = 100 V , SWCT pulse = 2 μ s , and V G 2 − S 2 = 20 V were used (a), and typical SCWT test (i.e. V S 2 − S 1 = 800 V , and V G 2 − S 2 = 20 V ) for both monolithic BiD-MOS designs (b). Large oscillations are seen within the V G 1 − S 1 turn-off waveform for the 2-Chip approach that is not present in either of the monolithic designs.

The results of all measurements conducted for each BiD-MOS design are summarized in Table 1. In terms of conduction, blocking, and switching characteristics, the different approaches exhibited nearly identical performance. Under SCWT testing, however, the 2-Chip BiD-MOS showed pronounced gate oscillations that were not observed in the monolithic counterpart. This difference is hypothesized to arise from variations in parasitic inductance between the 2-Chip and monolithic designs, as parasitic inductance has been shown to negatively affect device SCWT [7,8]. However, further analysis is needed to confirm the root cause of these oscillations in the 2-Chip design.

Table 1. Summary of measurement results for the various BiD-MOS design approaches.

BiD-MOS Design Approach | Ron [mΩ] | Breakdown Voltage [V] | Leakage Current @1.2kV [nA] | Turn-On Loss [mJ] | Turn-Off Loss [mJ] | Total Switching Loss [mJ] | SCWT [μs]
2-Chip | 169.8 | 1640 | 0.73 | 0.81 | 0.67 | 1.48 | < 2*
Monolithic | 169.1 | 1620 | 0.52 | 0.83 | 0.71 | 1.54 | 3.82
Mono SN+ | 166.1 | 1640 | 0.46 | 0.79 | 0.69 | 1.48 | 3.67

*Due to high gate oscillations, the actual SCWT of the 2-Chip approach could not be determined.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

Several Common-Drain BiD-MOS design approaches were successfully fabricated and evaluated in terms of electrical performance. The static and switching characteristics were found to be nearly identical across the different designs. However, under the SCWT test, the 2-Chip approach exhibited reliability issues that were not observed in either monolithic counterpart. Given the unhindered electrical performance, monolithic integration emerges as a promising design approach for achieving an efficient and reliable Bi-Directional Switch.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-NA0003525.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.37.pdf

W. Wheeler, J. Rodriguez, J. C. Clare, L. Empringham, and A. Weinstein, "Matrix converters: a technology review," IEEE Transactions on Industrial Electronics, vol. 49, no. 2, pp. 276-288, 2002.

K. Han et al., "Monolithic 4-Terminal A 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Integrated JBS Diodes," 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, 2020, pp. 242-245, doi: 10.1109/ISPSD46842.2020.9170064.

S. Y. Jang, S. B. Isukapati, J. Lynch, and W. Sung, "Demonstration of Cell-to-Cell Integrated 4H-SiC Lateral Bi-Directional Junction Field Effect Transistor (LBiDJFET)," IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA), pp. 400-404, 2021.

S. A. Mancini et al., "Monolithically Integrated , 20A 4H-SiC BiDFET Utilizing an Accumulation Mode Channel for Improved Output Characteristics," 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Bremen, Germany, 2024, pp. 339-342, doi: 10.1109/ISPSD59661.2024.10579613.

S. A. Mancini et al., "Investigation on Design Approaches for Bi-Directional Field Effect Transistors (BiDFETs)," 2024 IEEE 11th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), Dayton, OH, USA, 2024, pp. 1-5, doi: 10.1109/WiPDA62103.2024.10773119.

W. Sung and B. J. Baliga, "A Near Ideal Edge Termination Technique for 4500 V 4H-SiC Devices: The Hybrid Junction Termination Extension," IEEE Electron Device Letters, vol. 37, no. 12, pp. 1609-1612, Dec. 2016, doi: 10.1109/led.2016.2623423.

G. Kampitsis, E. Batzelis, E. Gati, S. Papathanassiou and S. Manias, "Electro-thermal characterization of 1.2 kV normally-on SiC JFETs under hard switch fault," 2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe), Geneva, Switzerland, 2015, pp. 1-9, doi: 10.1109/EPE.2015.7309054.

B. Kakarla, T. Ziemann, R. Stark, P. Natzke and U. Grossner, "Short Circuit Ruggedness of New Generation 1.2 kV SiC MOSFETs," 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Atlanta, GA, USA, 2018, pp. 118-124, doi: 10.1109/WiPDA.2018.8569077.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 45-50

doi: 10.4028/p-CFg0Cb

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-21

Accepted:
2026-03-16

Online:
2026-05-19

Characteristics of High Current 4H-SiC Schottky Barrier Diodes

The original version of this paper is available on https://www.scientific.net/KEM.1055.45.pdf

Lan Luo 1,a, Yu Zhong 1,b*, Peng Cui 1,c*, Ziang Zhao 1,d, Lei Ge 1,e, Yingxin Cui 1,f, Mingsheng Xu1,g, Xiangang Xu1,h, Jisheng Han 1,d,i* and Yaohao Wang 2,j

1 Institute of Novel Semiconductors, State Key Laboratory of Crystal Materials, Shandong University, Jinan, 250100, China

2 Summit Power Semiconductor Co., Ltd., Guangzhou, 511400, China

a  lan.luo@mail.sdu.edu.cn, b  yu.zhong@sdu.edu.cn, c  pcui@sdu.edu, d  202334091@mail.sdu.edu.cn, eleige@sdu.edu.cn, f  cuiyingxin@sdu.edu.cn, g  xums@email.sdu.edu.cn, i  j.han@sdu.edu.cn, j wangyaohao@summitpower.com

Keywords: 4 H -SiC, SBD, High Current, Large-area, Temperature.

Abstract

Silicon carbide (SiC) Schottky barrier diodes (SBDs) have become critical components in power electronics due to their excellent high-voltage, high-temperature tolerance, and fast switching capability. However, increasing the device area to improve current-carrying capability increases the total number of defects, which leads to an increase in reverse leakage current and a reduction in wafer yield. To improve current distribution uniformity within SiC module packaging, reduce system size and weight, and enhance the current-carrying capacity and high-temperature stability of a single SBD, this paper develops 750 V/100 A and 1200 V/100 A SiC SBDs on 6-inch wafers. For the 750 V/100 A device, the corresponding forward voltage drop (VF) at forward current (IF) of 100 A is 1.68 V . For the 1200 V/100 A device, the corresponding VF is 1.75 V . Calculation based on the current voltage characteristics shows that the ideal factors of 750 V/100 A and 1200 V/100 A devices are 1.01 and 1.04 , respectively, which are very close to 1 . It demonstrates excellent Schottky contact and a high-quality interface. The devices exhibit high-temperature stability, meeting the demands of high-temperature applications.

Introduction

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In industrial power applications, there is a demand for 4H−SiC SBDs with the capability for a high current [1,2]. These devices have a great potential in fields such as new energy vehicles, switching power supplies, and industrial motor drives [3-5]. Considering the usage scenarios of these applications, enhancing power density is a key issue that assists in improving the system's efficiency. In a high-current module, using the high-current SiC SBDs contributes to the reduced number of chips, and it can increase the uniformity of the current distribution within the module packaging [6]. However, a challenge for high-current SiC SBDs is that increasing the active area to maintain high currents increases the likelihood of encountering material defects. This leads to an increase in reverse leakage current ( IR ) and ultimately reduces wafer yield [7, 8]. Therefore, this paper investigates the fabrication of two high-current SiC SBDs with specifications ( 750 V/100 A and 1200 V/100 A ).

In contrast to conventional ion implantation techniques, this paper proposes a design that employs an epitaxial etching process to fabricate the terminal P+ region. This method not only achieves excellent junction terminal protection but also significantly reduces manufacturing costs[9]. Consequently, the device ensures enhanced reverse blocking voltage capability and reduced IR. Static characteristic tests of 750 V/100 A and 1200 V/100 A SiC SBDs on 6-inch SiC wafers were conducted in the temperature range from room temperature to 240∘C. The devices present superior properties, including high current, low IR, and favorable capacitance characteristics. They maintain stable operation even under high-temperature conditions, thereby meeting the urgent demand for highperformance SiC power diodes in high-temperature and high-frequency power modules.

Experimental

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The schematic diagram of the 4H−SiCSBDs is shown in Fig. 1(a). The devices in this study were fabricated on 6 -inch n-type 4H−SiC single-crystal epitaxial wafers of high quality. The p-type terminal region was patterned by photolithography and inductively coupled plasma (ICP) etching, with its cross-sectional view shown in Fig. 1(b). The terminal protection was accomplished by employing polyimide/silicon nitride (SiN). A nickel (Ni) metal layer was deposited on the rear side of the wafer, followed by high-temperature annealing to form an ohmic contact with the SiC substrate. The titanium (Ti) and aluminum (Al) metal layers were deposited on the n-type SiC epilayer to establish the Schottky contact. Based on the aforementioned process, two large-area single-chip SiC SBDs with different specifications were successfully fabricated. The active region areas were 21.5 mm2 and 38.9 mm2 for the 750 V/100 A and 1200 V/100 A devices, respectively. Photographs of the fabricated samples are shown in Fig. 1(c) and 1(d). The yield of the 750 V/100 A and 1200 V/100 A SiC SBD is 85.4% and 76.4%.

[picture]

Fig. 1. (a) The schematic cross-section of the 4H−SiC SBD structure. (b) The cross-sectional view of the epitaxial etching termination area. (c) 750 V/100 A SiC SBD and (d) 1200 V/100 A SiC SBD fabricated in the 6 -inch SiC wafers.

Fig. 1. (a) The schematic cross-section of the 4 H − S i C SBD structure. (b) The cross-sectional view of the epitaxial etching termination area. (c) 750 V / 100 A SiC SBD and (d) 1200 V / 100 A SiC SBD fabricated in the 6 -inch SiC wafers.

Result and Discussion

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Forward characteristics at different temperatures

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The static characteristics and temperature stability of the devices are evaluated at various temperatures from 30∘C to 240∘C. The forward characteristic curves of the 750 V/100 A and 1200 V/100 A devices at low current are shown in Fig. 2(a) and 3(a), respectively. Test results indicate that under lower forward current (IF), the forward voltage (VF) of the device decreases with increasing temperature, exhibiting a negative temperature coefficient. This behavior is primarily attributed to the thermionic emission mechanism of the Schottky barrier, where electrons at higher temperatures possess greater energy and can more easily overcome the Schottky barrier. At low forward current, the current-voltage (I-V) characteristics of the SBD typically follow thermionic emission theory. Thus, the forward I-V characteristics can be used to derive the key parameters of SBDs. Calculations show that the Schottky barrier heights (SBH) of 1.31 eV and 1.14 eV for the 750 V/100 A and 1200 V/100 A devices, respectively, with ideal factors (n) of 1.01 and 1.04 , respectively, both very close to 1 . This indicates that current conduction in both devices is almost entirely dominated by thermionic emission, with the effects of interface states or tunneling effects being negligible, confirming the excellent quality of the Schottky contacts and interfaces.

[picture]

Fig. 2. Forward characteristic curves of 750 V/100 A SiC SBD at (a) low forward current, and (b) high forward current.

Fig. 2. Forward characteristic curves of 750 V / 100 A SiC SBD at (a) low forward current, and (b) high forward current.

The forward characteristic curves of the 750 V/100 A and 1200 V/100 A devices at high current are shown in Fig. 2(b) and 3(b), respectively. When VF=1.7 V, the forward current density of the 750 V/100 A SBD decreases from 476 A/cm2 at 30∘C to 259 A/cm2 at 240∘C. The forward current density of the 1200 V/100 ASBD decreases from 240 A/cm2 at 30∘C to 111 A/cm2 at 240∘C. Meanwhile, under the same IF,VF shows significant positive temperature coefficients, rising to 2.54 V(Δ VF=0.86 V) for the 750 V/100 A device and 3.19 V(Δ VF=1.44 V) for the 1200 V/100 A device at 240∘C. This phenomenon is primarily attributed to the increase in the intrinsic resistance of the SiC material and the significant decrease in carrier mobility with rising temperature. Calculation results indicate that at 30∘C, the 750 V/100 A SiC SBD exhibits a specific on-resistance ( Ron-sp  ) of 1.6 mΩ· cm2, while the Ron-sp  of the 1200 V/100 A SiC SBD is 3.3 mΩ· cm2. However, as the temperature increases from 30∘C to 240∘C, the Ron-sp  of the 750 V/100 A device significantly increases to 4.1 mΩ· cm2, while the Ron-sp  of the 1200 V/100 A device increases to 10.4 mΩ· cm2.

[picture]

Fig. 3. Forward characteristic curves of 1200 V/100 ASiCSBD at (a) low forward current, and (b) high forward current.

Fig. 3. Forward characteristic curves of 1200 V / 100 A S i C S B D at (a) low forward current, and (b) high forward current.

Reverse characteristics at different temperatures

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Fig. 4(a) and 4(b) show the reverse characteristics of 750 V/100 A and 1200 V/100 A SiC SBD devices at different temperatures. Test results indicate that the IR of devices is positively related to temperature. Under a reverse voltage ( VR ) of 750 V and room temperature, the IR of the 750 V/100 A device is 13.5μ A. As the temperature increases to 240∘C, the IR of the 750 V/100 A device increases to 1.3 mA . For the 1200 V/100 A device, IR is 14.8μ A at VR=1200 V and 30∘C; after the temperature rose to 240∘C, the IR increased to 1.8 mA . The increase in IR at high temperatures is primarily influenced by the combined effects of thermionic emission current, barrier height lowering, and tunneling current.

[picture]

Fig. 4. Reverse characteristic curves at different temperatures of (a) 750 V/100 ASiCSBD and (b) 1200 V/100 A SiC SBD.

Fig. 4. Reverse characteristic curves at different temperatures of (a) 750 V / 100 A S i C S B D and (b) 1200 V / 100 A SiC SBD.

Capacitance characteristics

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One of the main advantages of SiC SBDs is their ultra-fast switching speed and extremely low switching losses. This study conducted a detailed analysis of their capacitance characteristic. This characteristic is crucial for calculating and predicting the switching losses of the device in actual circuits. Capacitance characteristics are measured at a frequency of 1 MHz , and the results are shown in Fig. 5(a).

Capacitive charge (QC) and capacitance stored energy (EC) are core electrical parameters of SiC SBDs. Qc quantifies the total charge stored under reverse bias in SiC SBDs, which directly determines reverse recovery losses and dynamic turn-on response speed. EC quantifies the magnitude of energy stored through capacitive effects. It is used to evaluate capacitive discharge losses during switching cycles and the risks of circuit surge. Based on the integration results of the capacitance-voltage characteristics, Fig.5(b) and 5(c) show the characteristic curves of QC and EC versus voltage for the
750 V/100 A and 1200 V/100 A devices, respectively. The corresponding QC and EC values for specific VR are summarized in Table 1.

[picture]

Fig. 5. (a) Capacitance-voltage characteristics; (b) Capacitive charge curve; (c) Capacitance stored energy curve.

Fig. 5. (a) Capacitance-voltage characteristics; (b) Capacitive charge curve; (c) Capacitance stored energy curve.

Table 1. Capacitance, QC, and EC at specific voltages of 750 V/100 A and 1200 V/100 A devices.

Devices | Capacitance [pF] | QC [nC] | EC [μJ]
750V/100A (@VR = 400 V) | 347 | 220 | 29
1200V/100A ((@VR = 800 V) | 374 | 423 | 105

Summary

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This study successfully produces high-current SiC SBD devices rated at 750 V/100 A and 1200 V/100 A. Their electrical characteristics are analyzed in the temperature range of 30∘C to 240∘C. Test results indicate that the fabricated 4H-SiC SBDs exhibit excellent static characteristics, with an ideal factor approaching 1, demonstrating superior interface quality. They maintain good thermal stability even at elevated temperatures. Consequently, these SiC SBDs show significant application potential in high-voltage, high-power, high-temperature, and high-frequency fields.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.45.pdf

L. Jiang, W. Zou, Q. Zhang, Y. Chen, X. Yan, Y. Wang, S. Wang, Large-area vertical Schottky barrier diodes based on 4H-SiC epilayers: Temperature-dependent electrical characteristics, J. Nucl. Instrum. Methods Phys. Res., A. 1048 (2023) 167917.

I. -H. Ji, A. Mathew, J.-H. Park. N. Oldham, M. McCain, S. Sabri, E. Van Brunt, B. Hull, D.J. Lichtenwalner, D.A. Gajewski, J.W. Palmour, High Temperature and High Humidity Reliability Evaluation of Large-Area 1200 V and 1700 V SiC Diodes, 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023, pp. 1-4.

A. Battiston, L. Kefsi, M. Milosavljevic and A. Sabrie, High-Power / High-Voltage ( 250 kW / 750 V ) SiC-Based Inverter for Electric Vehicles Applications, 2021 23rd European Conference on Power Electronics and Applications (EPE'21 ECCE Europe), Ghent, Belgium, 2021, pp.111.

Y. Nomura, T. Funaki, T. Hanada and T. Nakamura, Power Conversion Efficiency Improvement of High Voltage Power Supply With SiC SBD Module, 2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe), Coventry, United Kingdom, 2022, pp. 1-6.

T. Kimoto, J. A. Cooper, Applications of Silicon Carbide Devices in Power Systems, in Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, John Wiley & Sons, Singapore, 2014, pp. 445-486.

G. Liu, Y. Wu, K. Li, Y. Wang, ChengZhan Li, Development of high power SiC devices for rail traction power systems, J. Cryst. Growth, 507 (2019) 442-452.

H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, T. Endo, Impact of surface morphology above threading dislocations on leakage current in 4HSiC diodes, J. Appl. Phys. Lett. 101(4) (2012) 042104.

T. Nakamura, T. Miyanagi, I. Kamata, H. Tsuchida, Comparison of Electrical Characteristics of 4H-SiC(0001) and (000-1) Schottky Barrier Diodes, J. Mater. Sci. Forum. 527-529 (2006) 927-930.

S. Dimitrijev and J. Han, U.S. Patent 10,971,580 B2. (2017).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 51-56

doi: 10.4028/p-t04lTi

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-23

Accepted:
2026-02-26

Online:
2026-05-19

Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

Seung Yup Jang 1,a*, Skylar deBoer 1, b and Woongje Sung 1,c

¹College of Nanotechnology Science and Engineering, University at Albany, Albany NY, 12203, USA

a*  sjang3@albany.edu, b  sdeboer@albany.edu, c  wsung@albany.edu

Keywords: 4H-silicon carbide (SiC), lateral, bi-directional, MOSFET, 3D TCAD simulation.

Abstract

This paper presents the fabrication and characterization of a cell-to-cell integrated SiC lateral bi-directional MOSFET (L-BiD-MOSFET), with blocking performance analyzed through correlation of experimental results and 3D TCAD simulations. The fabricated devices exhibit a breakdown voltage of 600 V , notably lower than the 900 V predicted by 2D simulations. To address this discrepancy, 3D TCAD simulations were performed, which identified electric field crowding at the finger edges as the dominant factor limiting the breakdown voltage. To mitigate this effect, an extended P-top edge design was introduced, which increases the simulated breakdown voltage by more than 10%. Experimental results on devices incorporating the proposed design confirm improved breakdown capability, demonstrating good agreement with simulations. These results highlight the importance of accurate 3D simulation for edge effects in lateral structures. Overall, the proposed design strategy provides valuable guidance for the development of high-performance lateral bi-directional SiC power devices.

Introduction

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Bi-directional power devices, capable of conducting and blocking current in both forward and reverse directions, are essential building blocks for emerging applications such as current source inverters (CSIs) and matrix converters. Various approaches to implementing bi-directional power devices have been reported, including package-level integration and monolithic two-chip integration [1-3]. Recently, our research group successfully demonstrated a cell-to-cell integrated SiC lateral bi-directional power MOSFET (L-BiD-MOSFET) [4, 5]. Cell-to-cell integration not only enables exploration of novel device architectures but also provides considerable area savings by sharing the central drift region. Compared with vertical device structures, lateral structures offer a distinct advantage for cell-to-cell integration, as they can be realized through layout design without requiring complex backside processing.

However, lateral power device structures in wide-bandgap materials require careful electric-field management during high-bias blocking operation. Because these materials exhibit high critical electric fields, achieving a uniform field distribution within relatively small dimensions is essential. This challenge is further pronounced in lateral devices, which contain corner and edge regions where field crowding is more likely to occur. Without proper structural optimization, local field crowding can become severe, ultimately resulting in premature breakdown. In our previous study, the measured breakdown voltage of fabricated devices was lower than simulated predictions, highlighting the need for improved design strategies. To enhance the blocking performance of cell-to-cell integrated lateral bi-directional devices, it is therefore essential to examine layout designs using 3D TCAD simulations to capture electric field concentrations accurately [6, 7].

In this work, we correlate the measurement results of fabricated L-BiD-MOSFETs with 3D TCAD simulations. The 3D analysis reveals significant electric field crowding at finger edges, and we propose an extended P-top design to mitigate these effects, thereby improving breakdown voltage. Simulation results are compared with measured device performance, demonstrating the effectiveness of the proposed design and providing insights for further optimization of high-performance SiC lateral bi-directional devices.

Device Design and Fabrication

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Fig. 1(a) illustrates the schematic structure and symbol of the SiC L-BiD-MOSFET device. It features a common-drain configuration, in which two back-to-back connected MOSFET unit cells share the central n -drift region without a dedicated drain terminal. The sources and gates of the MOSFETs are labeled as Source1 (S1), Source2 (S2) and Gate1 (G1), Gate2 (G2), respectively. The interdigitated S1 and S2 fingers are shown in Fig. 1(b). It should be noted that finger edges are present for each S1 and S2 finger unless alternative isolation techniques, such as mesa etching, are employed.

[picture]

Fig. 1. (a) Cell structure of the common-drain SiC lateral bi-directional MOSFET (L-BiDMOSFET), with the 4-terminal symbol included. (b) Top-view layout showing the designed interdigitated finger structure of the device.

Fig. 1. (a) Cell structure of the common-drain SiC lateral bi-directional MOSFET (L-BiDMOSFET), with the 4-terminal symbol included. (b) Top-view layout showing the designed interdigitated finger structure of the device.

The L-BiD-MOSFET devices were successfully fabricated at Clas-SiC Wafer Foundry, UK. A 10 μm thick drift layer with N - type doping concentration of 1×1016 cm−3 on an N+4H-SiC substrate was used. Aluminum and Nitrogen ion implants were used to form the P-well / P+ source / P-top, and JFET / N+ source, respectively. At the conclusion of all the implantation steps, an activation anneal with a carbon cap was conducted. A 50 nm thick gate oxide was formed, followed by a post-oxidation annealing (POA). An N-type polysilicon was deposited and patterned for the formation of the gate. After, an interlayer dielectric (ILD) was deposited, patterned and etched to make ohmic contact regions. After the formation of ohmic contacts, the source and gate metal, based on Aluminum, were

[picture]

Fig. 2. Cross-sectional SEM images of the fabricated L-BiD-MOSFET. (a) Two interdigitated fingers (S1 and S2). (b) Enlarged view of the S1 finger.

Fig. 2. Cross-sectional SEM images of the fabricated L-BiD-MOSFET. (a) Two interdigitated fingers (S1 and S2). (b) Enlarged view of the S1 finger.

[picture]

Fig. 3. Measured and simulated output and blocking characteristics of the fabricated L-BiDMOSFET. The black curves correspond to the both-gates-on state (bi-directional conducting), while the red curves represent the both-gates-off state (bi-directional blocking). Simulations were performed using a 2D cross-sectional device structure.

Fig. 3. Measured and simulated output and blocking characteristics of the fabricated L-BiDMOSFET. The black curves correspond to the both-gates-on state (bi-directional conducting), while the red curves represent the both-gates-off state (bi-directional blocking). Simulations were performed using a 2D cross-sectional device structure.

deposited, patterned, and etched. For the passivation, Silicon Nitride was deposited, patterned, and etched.

Fig. 2 shows cross-sectional SEM images of the fabricated L-BiD-MOSFET devices. The symmetric finger structures are well defined and consistent with the design. It should be noted that the device was fabricated entirely using the foundry's baseline SiC planar MOSFET process.

The measured and simulated output and blocking characteristics are presented in Fig. 3. The curves correspond to two operating conditions: both gates on (VG1=VG2=20 V) and both gates off (VG1=VG2=0 V ). These results clearly demonstrate the bi-directional and symmetric conducting and blocking behavior of the device. The measured on-state characteristics show good agreement with the simulation results; however, the fabricated devices exhibit a breakdown voltage (BV) of approximately 600 V , which is lower than the 900 V predicted by the 2D TCAD simulations.

3D TCAD Simulation

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To investigate the discrepancy between the 2D simulation and the experimental results, we performed 3D TCAD simulations using Synopsys Sentaurus, focusing on the finger-edge structures that cannot be accurately captured in a 2D environment. Two edge designs were modeled (Fig. 4): (a) a conventional finger-edge structure, in which the P -top width is consistent with that of the finger

[picture]

Fig. 4. Top-view diagrams showing (a) the conventional and (b) the proposed finger-edge designs generated using 3D TCAD simulations.

Fig. 4. Top-view diagrams showing (a) the conventional and (b) the proposed finger-edge designs generated using 3D TCAD simulations.

body, and (b) a proposed structure, where the P -top is widened by 5μ m at the finger edge to mitigate electric field crowding under reverse bias. Identical implantation and process conditions were applied in SProcess [8] to generate 3D doping profiles for both structures.

Accurate device simulation required careful meshing optimization. While fine box meshing was initially applied near the interface to resolve implantation profiles, this approach led to convergence issues in SDevice simulations. To address this, we adopted an adaptive meshing strategy that preserved fine resolution in the critical interface region while gradually coarsening the mesh deeper into the MOSFET structure, enabling stable and reliable device simulations.

Results and Discussion

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As summarized in Table I, the 3D simulation of the conventional finger-edge structure under VS2 sweep conditions (outside high bias) yields a BV of 740 V -significantly lower than both the 2D simulation result and the BV obtained under the opposite bias condition (inside high bias). This confirms that the finger edge is the weak point with respect to electric field crowding in the outside high bias case, thereby preventing the BV from reaching the ideal 2D value.

The proposed finger-edge design achieves a notably improved BV of 818 V (about 10% increase), demonstrating that the extended P -top region effectively suppresses electric field concentration at the edge and consequently enhances the BV. The corresponding electric field distributions are shown in Fig. 5. As expected, the finger edge exhibits a stronger electric field during blocking mode; however, the proposed structure significantly mitigates this crowding. A slightly elevated-though reducedfield remains at the edge compared to the finger body, which likely accounts for the residual gap between the 3D and 2D simulated BVs.

Table 1. Simulated breakdown voltages for each structure and condition.

Bias Conditions | 2D Structure | 3D Conventional | 3D Proposed
VS1 Sweep | 903 V | 888 V | 883 V
VS2 Sweep | 901 V | 740 V | 818 V

[picture]

Fig. 5. Electric field distribution at a depth of 0.6μ m from the surface for (a)-(c) the conventional and (d)-(f) the proposed finger-edge designs. Bias conditions are VS1=700 V and VS2=0 V for (a) and (d), and VS1=0 V and VS2=700 V for (b), (c), (e), and (e). (c) and (f) show surface plots of the electric field at the 0.6μ m depth.

Fig. 5. Electric field distribution at a depth of 0.6 μ m from the surface for (a)-(c) the conventional and (d)-(f) the proposed finger-edge designs. Bias conditions are V S 1 = 700 V and V S 2 = 0 V for (a) and (d), and V S 1 = 0 V and V S 2 = 700 V for (b), (c), (e), and (e). (c) and (f) show surface plots of the electric field at the 0.6 μ m depth.

[picture]

Fig. 6. Measured blocking characteristics of the fabricated devices with conventional and proposed finger-edge designs. Simulated breakdown voltages for each structure are shown as dashed lines for comparison.

Fig. 6. Measured blocking characteristics of the fabricated devices with conventional and proposed finger-edge designs. Simulated breakdown voltages for each structure are shown as dashed lines for comparison.

Measurement results for the fabricated devices with the conventional and proposed finger-edge structures are presented in Fig. 6. The improvements observed experimentally show good correlation with the 3D simulation results, although a gap between the measured and simulated values still remains. This discrepancy appears to be common to both structures, suggesting a mismatch between the simulated and the actual fabricated devices.

Several possible causes can be considered. The most likely contributors are variations in the net P-top dose and width. Because the present design employs a P-top structure analogous to a singlezone junction termination extension (JTE), the BV is highly sensitive to these parameters [9]. Although the simulations reproduce the process flow and account for factors such as implant profiles and SiC consumption, discrepancies in the actual P+/P-top dimensions or in SiC surface consumption could lead to deviations between simulation and experiment. To address this, calibration through a series of split experiments varying dose and width will be required, and future designs should aim to be less sensitive to such variations. Additional factors may also play a role, including the influence of SiC/oxide interface states and structural differences in the implanted regions near corners.

Note that GaN lateral bi-directional power devices at the 600 V class have been demonstrated for nearly two decades and recently commercialized by several vendors [10,11]. Compared with GaNbased solutions, SiC L-BiD-MOSFETs can offer complementary advantages in applications where robust avalanche characteristics and high-temperature operation are emphasized. The use of a thermally grown SiO2 gate dielectric further supports stable MOS-gated device operation within SiC processing platforms. In addition, lateral SiC device structures can be oriented toward future integration with SiC CMOS technologies, enabling increased functionality at the chip level.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

In this work, we investigated and improved the blocking performance of a cell-to-cell integrated SiC lateral bi-directional MOSFET (L-BiD-MOSFET) through combined experimental characterization and 3D TCAD simulation. The fabricated devices exhibited a breakdown voltage of 600 V , notably lower than the 900 V predicted by 2D simulations, due to electric field crowding at finger edges. To address this limitation, an extended P -top edge design was proposed, which reduced field concentration and improved the simulated breakdown voltage by more than 10%. Experimental measurements of devices with the proposed design confirmed enhanced blocking capability, in good agreement with the 3D simulation results. The remaining gap between the measured and simulated breakdown voltages may be attributed to process and structural mismatches between the simulated and fabricated devices-particularly variations in the P-top dose and width, as well as differences in
the SiC /oxide interface states. These findings highlight the importance of accurate 3D TCAD analysis to capture edge effects that cannot be represented in 2D simulations. Overall, the proposed edgeengineering approach provides effective design guidance for advancing high-performance lateral bidirectional SiC power devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

The authors would like to thank Clas-SiC Wafer Foundry for the fabrication of the devices and Alexander Bialy at NY CREATES for providing the SEM image presented.

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The original version of this paper is available on https://www.scientific.net/KEM.1055.51.pdf

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A. Shimbori, A. Q. Huang, "Design Optimization and Surge Current Capability of Lateral Deep P JBS Diode on Thin RESURF Layer," IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA), pp 17-21 (2022)

Synopsys Inc., SentaurusTM Process User Guide, ver. T-2022.03, March 2022.

W. Sung, B. J. Baliga, "A near ideal edge termination technique for devices: The hybrid junction termination extension," IEEE Electron Device Letters, vol. 37 (12), pp 1609-1612 (2016).

.

.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 57-61

doi: 10.4028/p-F5Vgsj

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-17

Accepted:
2026-02-26

Online:
2026-05-19

Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

D. Dansako a*, T. Abe b , K. Miyazaki c , T. Tanioka d , Y. Kagawa e  and T. Nitta f 

Power Device Works, Mitsubishi Electric Corporation,1-1-1, Imajuku-higashi, Nishi-ku, Fukuokashi, Fukuoka, 819-0192, Japan

a  Dansako.Daichi@dh.mitsubishielectric.co.jp, b  abe.tetsuya@dc.mitsubishielectric.co.jp, c  miyazaki.kosuke@dw.mitsubishielectric.co.jp, d  tanioka.toshikazu@eb.mitsubishielectric.co.jp, e  kagawa.yasuhiro@cj.mitsubishielectric.co.jp, f  nitta.tetsuya@ea.mitsubishielectric.co.jp

Keywords: edge termination, field limiting rings (FLRs), SBD embedded MOSFET, HV-H³TRB.

Abstract

In high-voltage class SiC devices, maintaining sufficient robustness against humidity and fabrication processes has become a major concern when minimizing the edge termination size. Previous research has shown that suppressing the maximum electric field on the SiC surface in the termination region improves durability in HV-H 3 TRB tests for 3.3 kV SBDs. In this study, we investigated the impact of the FLR design on the electric field distribution in the termination region. Simulation results showed that the termination length can be reduced without changing the maximum electric field on the SiC surface and the breakdown voltage. Furthermore, the fabricated 4.5 kV SiC SBD-embedded MOSFETs exhibited good reverse leakage characteristics, which were consistent with the simulation results.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Silicon carbide ( SiC ) is a promising material for power devices owing to its excellent properties such as a wide bandgap, a high critical electric field, and high thermal conductivity. Thus, 3.3 kV class SiC power devices are currently applied to railways [1], and 4.5 kV -class and higher devices are expected for HVDC and power grids [2-3]. However, as the power class becomes higher, the edge termination size increases, leading to larger chip sizes and higher manufacturing costs.

Previous research indicated that field limiting rings (FLRs) exhibit high robustness against Al implantation dose variations [4-5]. Furthermore, another study showed that reducing the maximum electric field on the SiC surface ( Esurface max  ) in the termination region improves durability in high voltage high humidity high temperature reverse bias (HV-H 3 TRB) test for 3.3 kV Schottky Barrier Diodes (SBDs) [6].

In this paper, we investigated the impact of the FLR design on the electric field distribution in the termination region using TCAD simulation and evaluated the fabricated 4.5 kV SiC SBD -embedded MOSFETs.

Simulation Setup

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Figure 1 shows a cross-sectional schematic of the simulated FLR region. The substrate and drift layer are n-type 4H−SiC(0001). The p-doped layer has a simulated Al implantation profile. Each FLR pitch ( PFLR  ) is uniform, and the ring spacing of the FLRs is designed to increase as it moves outward according to the outermost ring spacing (WN). Positions (x) and (y) indicate the innermost and outermost FLR positions, respectively.

[picture]

Fig. 1. Cross-sectional schematic of the simulated FLR region.

Fig. 1. Cross-sectional schematic of the simulated FLR region.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Figure 2 (a)-(c) show the simulated 2-D electric field distributions in the termination region. PFLR  is fixed at 9.0μ m.WN values are set to (a) 7.2μ m, (b) 4.5μ m, and (c) 1.8μ m. The applied DrainSource voltage is 3.6 kV , corresponding to typical HV-H 3 TRB test conditions. As WN decreases, the depletion layer extends further outward, causing the position of the maximum electric field to shift outward as well. The electric field distributions on the SiC surface and at the PN junction were investigated in detail. Figure 3 shows the extracted distributions. When WN is 4.5μ m,Esurface max  and the maximum electric field at PN junction ( EPN max  ) reach their minimum values of approximately 1.3 MV/cm and 2.3MV/cm, respectively. The position of the Esurface max  is further outward than that of EPN max , which is located at the center of the FLR. It is found that Esurface max  should be located slightly outward from the center of the FLR structure to suppress its value.

Figure 4 compares the light emission positions and the simulated EPN max  positions of PN diode TEGs with WN values of (a) 7.2μ m, (b) 4.5μ m, and (c) 1.8μ m when avalanche breakdown occurred. As WN decreases, the emission position shifted outward, and all emission positions correspond closely to the simulated EPN max  positions.

[picture]

Fig. 2. Simulated 2-D electric field distributions for termination region.

Fig. 2. Simulated 2-D electric field distributions for termination region.

[picture]

Fig. 3. Relation between electric field distribution and WN on (a) SiC surface (b) PN junction.

Fig. 3. Relation between electric field distribution and W N on (a) SiC surface (b) PN junction.

[picture]

Fig. 4. Comparison between light emission and simulated EPNmax position of PN diode TEGs.

Fig. 4. Comparison between light emission and simulated E P N max position of PN diode TEGs.

We investigated the WN at which Esurface max  is minimized when varying the PFLR  values. Figure 5 shows the relationship among WN,Esurface max  and BV . The optimal WN values vary according to PFLR, with values of 3.5,4.2, and 4.5μ m corresponding to PFLR  values of 5.0,7.0, and 9.0μ m, respectively. At these values, BV doesn't decrease and there is sufficient margin for variations in WN.

Furthermore, we investigated the dependence of Esurface max  and BV when varying FLR length with the optimal WN values. As shown in Fig. 6, by reducing PFLR  with the optimized WN values, the FLR length can be shortened while maintaining a low Esurface max  and an equivalent BV .

[picture]

Fig. 5. Relation among WN,Esurface max  and BV .

Fig. 5. Relation among W N , E surface max and BV .

[picture]

Fig. 6. Dependence of Esurface max  and BV when varying FLR length using the optimal WN values.

Fig. 6. Dependence of E surface max and BV when varying FLR length using the optimal W N values.

Figure 7 shows the relationship among Al dose, BV , and Esurface max  for the three termination designs (A-C), which have equivalent Esurface max  but different termination lengths. The parameters of terminations (A-C) are presented in Table 1. Even with a short FLRs length of 155μ m, a wide margin of Al dose ranging from 1.5 to 2.5×1013 cm−2 was confirmed. When the Al dose exceeds 2.5×1013cm−2, Esurface max  significantly increases. This increase is attributed to the electric field concentration at the outermost FLR.

We fabricated SBD-embedded MOSFETs with the three simulated terminations (A-C). Figure 8 shows typical reverse leakage current characteristics at 25∘C with Gate-Source voltage of -7 V . The experimental BV and reverse leakage characteristics exhibited no significant differences among the three termination designs. The experimental BV matched the simulated values of approximately 5.4 kV well.

[picture]

Fig. 7. Dependence of BV and Esurface max  on Al dose.

Fig. 7. Dependence of BV and E surface max on Al dose.

[picture]

Fig. 8. Reverse leakage current characteristics of fabricated SBDembedded MOSFET.

Fig. 8. Reverse leakage current characteristics of fabricated SBDembedded MOSFET.

Table 1. Parameters of selected three termination structures.

Termination structure | FLR length [μm] | PFLR [μm] | WN [μm]
A | 155 | 5 | 3.5
B | 205 | 5 | 3.5
C | 287 | 7 | 4.2

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

We investigated termination designs for 4.5 kV SiC devices from the points of cost-effectiveness, humidity-tolerance and process-robustness using simulation and fabricated 4.5 kV SiC SBDembedded MOSFETs. By optimizing WN, the electric field peak on the SiC surface shifts slightly outward from the center of the FLRs and Esurface max  reached its minimum value. By reducing the PFLR  with the optimized WN, the FLR length can be shortened while maintaining Esurface max  low and an equivalent BV . Even with a short FLR length of 155μ m, a wide margin of Al dose ranging from 1.5 to 2.5×1013 cm−2 was confirmed. Furthermore, the fabricated devices exhibited almost the same BV as the simulation and showed no difference in leakage characteristics.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.57.pdf

Information on http://www.mitsubishielectric.com/news/2013/1225.html.

A. Q. Huang, Power Semiconductor Devices for Smart Grid and Renewable Energy Systems, Proceedings of the IEEE. 105 (2017) 2019-2047.

S. Sen, J. Tong, Z, Guo and A. Q. Huang, A Bottom Charge-Modulated Field Limiting Rings Termination With N-P-N Sandwich Epitaxial Wafers for 4H-SiC Devices, in Proc. APEC 2022, 957-961.

K. Ebihara, K. Kawahara, S. Hino, K. Sadamatsu, A. Nagae, Y. Nakao, H. Watanabe and S. Yamakawa, Investigation of the Robust Edge Termination Applied to 6.5 kV SiC MOSFET, Materials Science Forum, 924 (2018) 778-781.

J. Zhang, H.Luo, H.Wu, Z. Wang, B. Zheng and X. Chen, Design and optimization of cell and field limiting ring termination for 1200 V 4H-SiC Junction Barrier Schottky (JBS) Diodes, in Proc. ICEPT 2022, 1-5.

K. Ebihara, H. Niwa, T. Murakami, K. Fujiyoshi, Y. Nakata, S. Okimoto, K. Hatori and K. Nishikawa. Durable Edge Termination Design of SiC SBD against Humidity, in Proc. ISPSD 2024, pp.510-513.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 63-68

doi: 10.4028/p-Rd95Vt

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-04

Revised:
2025-12-12

Accepted:
2026-03-16

Online:
2026-05-19

JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Zihan Zhang 1,a, Lei Yuan 1,4, b*, Kaiyu Chen 2,c, Xiaowen Wang 2, d, Xuesong Liu 3,e, Tongxiao Hou 3,f, Bo Peng 1, g, Guibao Wang 4, h, Miao Yu 4,i, Renxu Jia 1,4,j and Yuming Zhang 1,k

1 Faculty of Integrated Circuit, Xidian University, Xi'an 710071, China

2 Alkaidsemi Electronic Technology Ltd., Shanghai, China

3 Beijing BJAST Holdings Co., Ltd., Beijing, China

4 Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, China

a 24251111422 @stu.xidian.edu.cn, b*yuanlei@xidian.edu.cn, cgary_chen@alkaidsemi.com, d  xiaowen_wang@alkaidsemi.com, e  xs6721@126.com, f  644988605@qq.com,

bboopeng @xidian.edu.cn,h  wangguibao@xidian.edu.cn, i  yumiao@xidian.edu.cn,  jrxjia@mail.xidian.edu.cn, k zhangym@xidian.edu.cn

Keywords: edge termination, silicon carbide (SiC), superjunction (SJ), junction termination extension (JTE), process robustness, charge-imbalance.

Abstract

A charge-imbalanced P-pillar distribution termination (D3) is proposed for 1500 V -class 4H−SiC superjunction (SJ) devices. By combining a junction termination extension (JTE)-based termination with gradually widened P-pillar spacing, the design effectively suppresses edge electric field crowding and enhances device reliability. TCAD simulations show that D3 achieves comparable blocking capability while exhibiting significantly improved robustness against charge imbalance, oxide charge density, and JTE dose deviations, demonstrating superior process margin and reliability. With relaxed process sensitivity and an efficient structure, D3 presents a promising approach for highvoltage 4H−SiC SJ device fabrication.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

With the evolution of electric vehicle voltage platforms from 400 V to 800 V and even 1000 V , the demand for higher-voltage power devices continues to grow [1, 2]. Among them, 1500 V silicon carbide ( SiC ) metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted increasing attention, since 1200 V devices provide insufficient voltage margin at the 1000 V platform, while 1700 V devices result in unnecessary cost and overdesign [1]. Nevertheless, the intrinsic tradeoff between breakdown voltage (BV) and specific on-resistance ( Ron,sp ) remains a major challenge in developing 1500 V SiC MOSFETs with high voltage capability, high current density, fast switching, and low power loss [3]. By employing charge compensation effect, superjunction (SJ) technology breaks the conventional BV~Ron,sp  trade-off, allowing for higher drift doping concentrations under high breakdown conditions and thus offering significant potential for low-loss, high-voltage device operation [4]. However, the charge balance in SJ devices, realized by periodically alternating heavily doped N-pillars and P-pillars, demands highly precise process control, significantly increasing fabrication complexity, especially in the termination region [5-8]. Notably, studies on SiC SJ terminations remain limited, and most using uniform P-pillar distributions, with few analyzing the impact of P -pillar distribution on termination performance [2,9,10].

In this work, we propose a novel charge-imbalanced P-pillar distribution structure for JTE-based 4H-SiC SJ terminations (D3) for 1500 V 4H-SiC SJ-MOSFETs. The design more effectively suppresses edge electric fields by gradually widening the P -pillar spacing, and achieves more efficient lateral depletion of the superjunction by JTE structure. We evaluate the impact of P -pillar distribution on the performance and process robustness of JTE-based 4H-SiC SJ terminations.

Design and Simulation

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Figures 1(c)-1(e) show three termination designs with different P-pillar distributions: D1 with uniform spacing (N/P balanced), D2 with a non-uniform distribution (N-rich center, P-rich edges), and D3 transitioning from P-rich to N-rich. It is worth noting that in JTE-based SJ terminations, the JTE region sustains the surface electric field while the SJ pillars support the bulk field, and their combined action provides effective protection for the MOSFET cell region. The top-view layout is shown in Figure 1(a). The corresponding breakdown voltages, shown in Fig. 1(b), all exceed 1700 V , satisfying the 1500 V voltage device requirement. The electric field distribution at 1500 V is shown in Fig. 2. D1 exhibits higher P-pillar utilization efficiency, with the P-pillars near complete depletion at the edge of the termination due to the relatively small uniform spacing.

[picture]

Fig. 1. SJ termination structures including (a) top-view layout, (b) reverse blocking performance, and (c) N/P balanced, (d) N-rich center with P-rich edges, and (e) P-rich to N-rich transition designs.

Fig. 1. SJ termination structures including (a) top-view layout, (b) reverse blocking performance, and (c) N/P balanced, (d) N-rich center with P-rich edges, and (e) P-rich to N-rich transition designs.

[picture]

Fig. 2. Electric field distributions of D1-D3 under 1500 V blocking voltage, showing higher termination efficiency for D1.

Fig. 2. Electric field distributions of D1-D3 under 1500 V blocking voltage, showing higher termination efficiency for D1.

Fig. 3 further analyzes the electric field distribution along different cutlines ( C1~C3 ) at a blocking voltage of 1500 V . Significant electric field peaks appear near the terminal surface at C 1 and C 2 in D1, exceeding the bulk field level, while a sharp field drop is observed at the edge (C3). Such insufficient redistribution of the bulk field induces edge field crowding, potentially threatening longterm reliability despite meeting the 1500 V blocking requirement. In D 2 , the electric field peak at C 1 and C2 degrade device reliability, even though their peaks are below the bulk field level. By comparison, D3 demonstrates a highly uniform field profile, indicating improved prospects for longterm device stability. In the D3 structure, the lateral charge-compensation gradient transitions gradually from a P -rich region near the source to an N -rich region toward the edge. This graded profile enables a smoother lateral depletion process, allowing the electric field to spread across a wider effective termination width rather than concentrating near the gate-oxide surface.

[picture]

Fig. 3. Electric field distributions along (a) C1, (b) C2, and (c) C3 cutlines under 1500 V drain bias for different termination designs.

Fig. 3. Electric field distributions along (a) C1, (b) C2, and (c) C3 cutlines under 1500 V drain bias for different termination designs.

Process Robustness Evaluation

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Breakdown Voltage Dependence on charge imbalance.

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

The reliance of SJ structures on precise charge balance makes them highly sensitive to process variation, posing a major challenge to device fabrication. Fig. 4(a) shows the impact of P-pillar dose errors on termination performance. It is observed that D3 maintains 1500 V blocking capability with an error window exceeding ±8%, showing a clear advantage, especially under P-rich conditions. The improved robustness is attributed to the widened P -pillar spacing at the edge, which reduces the effect of charge imbalance on termination performance.

Breakdown Voltage Dependence on oxide charge density.

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

The impact of oxide charge located at the SiO2/SiC cannot be ignored in the manufacturing of SiC devices [11]. The sensitivity of the termination blocking capability to the oxide charge density (Nox) is illustrated in Fig. 4(b), with the calculation range of Nox selected according to representative values
previously reported in the literature [12, 13]. Both positive and negative interface charges affect the BV, with higher densities markedly degrading the terminal blocking capability. For positive oxide charge, all three structures exhibit nearly identical blocking performance, while D3 shows a broader blocking range under negative oxide charge. With a tolerance window of 1.1×1013 cm−2 at 1500 V blocking, D3 achieves a 51% improvement compared with D1. The breakdown current distribution at a negative Nox of 5×1012 cm−2 is shown in Fig. 5. The breakdown location of D3 shifts inward compared to D1 and D2, indicating its potential to withstand higher negative oxide charge density.

Breakdown Voltage Dependence on JTE dose error.

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

The impact of JTE concentration variation on termination blocking capability was investigated in Fig. 4(c), considering the dose sensitivity of JTE structures. The blocking capability of D1 degrades markedly once the JTE dose exceeds the optimum. By contrast, D2 and D3 exhibit low sensitivity within a ±15% dose variation, thereby relaxing implantation accuracy requirements and resulting in a significantly wider tolerance window. Fig. 4(d) shows that under a 5% JTE dose deviation with a termination length of 140μ m, D1 suffers from pronounced edge field crowding, whereas D3 reduces the edge electric field by 92% along cutline C2, even though both designs exhibit comparable blocking capability.

[picture]

Fig. 4. Impact of (a) charge imbalance, (b) oxide charge density, and (c) JTE dose error on breakdown voltage for D1, D2, and D3, and (d) electric field distributions under a 5% JTE dose deviation.

Fig. 4. Impact of (a) charge imbalance, (b) oxide charge density, and (c) JTE dose error on breakdown voltage for D1, D2, and D3, and (d) electric field distributions under a 5 % JTE dose deviation.

[picture]

Fig. 5. Breakdown current density distribution of D1-D3 at Nox =−5×1012 cm−2, with D3 showing breakdown closer to the active region, indicating a higher tolerance to negative charge density.

Fig. 5. Breakdown current density distribution of D1-D3 at Nox = − 5 × 10 12 c m − 2 , with D3 showing breakdown closer to the active region, indicating a higher tolerance to negative charge density.

The enhanced robustness of D3 originates from the lateral P-rich to N-rich pillar arrangement, which promotes smoother lateral depletion and suppresses edge field concentration, thereby reducing the impact of charge imbalance, oxide charges, and JTE-dose variations.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

In this work, the impact of P-pillar distribution on JTE-based terminations for 4H-SiC SJ MOSFETs was systematically investigated. TCAD simulations of three representative designs (D1D3) demonstrated that the D3 structure with a non-uniform P-pillar distribution provides the most uniform electric field profile and superior robustness against process-induced variations, including superjunction charge imbalance, interfacial oxide charges, and JTE dose deviations. These results indicate that the D3 termination is a promising solution for high-voltage SiC SJ devices, offering both enhanced breakdown capability and improved process tolerance.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.63.pdf

Information on https://www.componentbuy.com/newsroom/byd-unveils-1500v-sic-module-on-super-e-platform.

Information on .

B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer, New York, 2010.

T. Masuda, T. Hatayama, S. Harada, and Y. Saitou, Edge termination design with strong process robustness for 1.2 kV -class 4 H -SiC super junction V-groove MOSFETs, C. International Symposium on Power Semiconductor Devices & ICs (ISPSD). (2020) 166-169.

R. Ghandi, C. Hitchcock, T. Saha, E. Delgado, S. Kennerley, 5-kV SiC Deep-Implanted Superjunction MOSFETs, J. IEEE Electron Device Lett. 46 (2025) 533-555.

M. Okada, S. Kyogoku, T. Kumazawa, J. Saito, T. Morimoto, M. Takei, S. Harada, Superior short-circuit performance of SiC superjunction MOSFET, C. International Symposium on Power Semiconductor Devices & ICs (ISPSD). (2020) 70-73.

Tawara, Takeshi, Kensuke Takenaka, Syunki Narita, Mitsuru Sometani, Kunihide Oozono, Shiyang Ji, Tadao Morimoto, Shinsuke Harada, Effect of the column design and fabrication method on the reverse recovery characteristics of 1.2 kV SiC-superjunction-MOSFETs, J. Materials Science in Semiconductor Processing. 176 (2020).

Y. Kobayashi, S. Kyogoku, T. Morimoto, T. Kumazawa, Y. Yamashiro, M. Takei, S. Harada, High-temperature performance of 1.2 kV -class SiC superjunction MOSFET, C. International Symposium on Power Semiconductor Devices & ICs (ISPSD). (2019) 31-34.

Wang R, Qiao M, Wang Y, Li Z, Zhang B, Novel high-tolerance termination with resistive field plate for 600 V super-junction vertical double-diffused MOSFET, J. IEEE Electron Device Letters. 43 (2022) 1093-1096.

Kang H, Du F, Yuan H, Bai B, Zhou Y, Li J, Han C, Tang X, Song Q, Zhang Y, Analysis and fabrication of a SiC super-junction termination structure in a state of charge imbalance, J. Science China Information Sciences. 68 (2025).

Feng, Gan, Jun Suda, Tsunenobu Kimoto, Space-modulated junction termination extension for ultrahigh-voltage pin diodes in 4H-SiC, J. IEEE transactions on electron devices. 59.2 (2011) 414-418.

D. Okamoto, H. Yano, K. Hirata, T. Hatayama, T. Fuyuki, Improved Inversion Channel Mobility in 4H-SiC MOSFETs on Si Face Utilizing Phosphorus-Doped Gate Oxide, J. IEEE Electron Device Letters. 31 (2010).

Dhar S, Feldman LC, Wang S, Isaacs-Smith T, Williams JR, Interface trap passivation for /(000̄̄) C-terminated 4H-SiC, J. Journal of Applied Physics. 98 (2005).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 69-74

doi: 10.4028/p-q19NrM

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-26

Revised:
2026-01-29

Accepted:
2026-03-08

Online:
2026-05-19

2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Yuniarto Widjaja 1,a*, Valerii Nebesnyi 1, b, Oleksandr Maistriuk 1,c, Asen Asenov 1,2, d, Nikolas Xeni 2,e, Tapas Dutta 2,f, Djamel Bensouiah 2, g, Servin Rathi 3,h, Leo Laborie 3,i, Robert Young 3,j, Yunyi Qi 3,k and David T. Clark 3,1

1 Volta Semiconductor, Inc., Cupertino, CA, USA

2 Semiwise Ltd., Glasgow, UK

3 Clas-SiC Wafer Fab Ltd., Lochgelly, UK

a*ywidjaja@voltasemi.com, b vn@voltasemi.com, c om@voltasemi.com, dasen.asenov@semiwise.uk, enikolas.xeni@semiwise.uk, t  tapas.dutta@semiwise.uk, g  djamel.bensouiah@semiwise.uk, h  servin.rathi@clas-sic.com, ileo.laborie@clas-sic.com, j  robert.young@clas-sic.com, k  kelly.qi@clas-sic.com, 'david.clark@clas-sic.com 

Keywords: 3300 V , silicon carbide, low specific on-resistance, on-current improvement, p-well bias.

Abstract

We experimentally demonstrated a ~2x on-current enhancement in VDMOSFET fabricated in a standard 3300 V -rated 4H−SiC process. The on-current improvement is achieved by applying a positive bias to the p-well region when the VDMOSFET is in the on-state. A 5×103−104 ratio between the on-current gain and the p-well current gain is shown. TCAD simulations are performed to study the underlying mechanisms of the on-current gain.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC), have been increasingly utilized in high-voltage, high-power applications due to advantages in electrical and thermal properties over silicon. Low conduction losses is one of the requirements of power semiconductor applications and therefore there are many efforts to improve the on-current and specific on-resistance of SiC devices, for example through process improvements [1-3], cell topologies [4], and charge modulations [5]. Previously, we demonstrated a >2.5 x on-current improvement in 1200 V-rated 4HSiC based MOSFET through the application of p-well voltage [6]. 3300 V -rated devices have received significant interest for solid-state transformers, industrial and traction applications. In this work, we demonstrated a ~2x on-current enhancement resulting from p-well voltage biasing in 3300 V-rated 4H−SiC based VDMOSFET.

Fig. 1(a) illustrates a schematic cross-sectional view of our VDMOSFET device, which is fabricated in a standard 3.3kV4H−SiC process on 150 mm wafers. The details of the fabrication process are described in [7] and a breakdown voltage of 3950 V is achieved (Fig. 1(b)).

[picture]

Fig. 1. (a) Cross-sectional view of device structure, (b) Breakdown characteristic of a typical 3300 V device.

Fig. 1. (a) Cross-sectional view of device structure, (b) Breakdown characteristic of a typical 3300 V device.

Separate contacts are formed for the p-well and source regions, allowing for independent biasing of both regions (p-well contact is not shown in Fig. 1(a)). A positive bias is applied to the p-well region when the VDMOSFET is in the on-state and removed when it is in the off-state. In a conventional VDMOSFET, the p-well and source regions are shorted and typically connected to a common ground.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Fig. 2(a) shows the Id-Vg curves measured from a test structure having a JFET width of 15μ m for different Vp and drain voltage (Vd). The ratio of the drain current with Vp=2.2 V and Vp=0 V for a range of gate voltage ( Vg ) is shown in Fig. 2(b), demonstrating ~2x on-current when Vp=2.2 V is applied compared to conventional VDMOSFET (with Vp=0 V ). The ratio of the on-current as a function of applied Vp bias is also shown in Fig. 2(c), indicating that the current flow across the VDMOSFET can be controlled by both Vg and Vp. When the VDMOSFET is turned off, the positive Vp bias is removed and the off-state characteristics return to those with Vp=0V applied. In addition, the application of Vp bias has been shown to reduce both the variability of the threshold voltage and the time-dependent threshold voltage drift [8, 9].

[picture]

Fig. 2. (a) Id-Vg characteristics of VDMOSFET for Vd=1 V and 2 V with Vp=0 V (solid) and Vp=2.2 V (dashed), (b) Ratio of drain current with Vp=2.2 V and Vp=0 V applied, (c) Ratio of drain current at different applied Vp and Vp=0 V for Vd=2 V.

Fig. 2. (a) Id-Vg characteristics of VDMOSFET for V d = 1 V and 2 V with V p = 0 V (solid) and V p = 2.2 V (dashed), (b) Ratio of drain current with V p = 2.2 V and V p = 0 V applied, (c) Ratio of drain current at different applied Vp and V p = 0 V for V d = 2 V .

Kimoto and Watanabe have previously shown that the drift resistance accounts for ~80% of the on-resistance of 3300 V SiC power MOSFET [10]. The p-well current is measured to study whether the significant on-current gain can be attributed to the vertical BJT device. Fig. 3(a) provides the ratio of the on-current gain to the p -well current (i.e. the BJT gain). A high ratio of 5×103−104 is observed, demonstrating that the large current gain does not require a large p -well current. The improvement in the channel resistance is investigated by measuring the transconductance (gm). Fig. 3(b) shows a ~30% higher peak gm with Vp=2.2 V. The Id-Vg and gm show that threshold voltage (Vt) shift and gm contribute to the on-current gain.

[picture]

Fig. 3. (a) Ratio of current gain (the difference between drain current with Vp=2.2 V and 0 V ) and p well current for Vd=1 V and 2 V , (b) Transconductance (gm) for Vd=2 V with Vp=2.2 V and 0 V .

Fig. 3. (a) Ratio of current gain (the difference between drain current with V p = 2.2 V and 0 V ) and p well current for V d = 1 V and 2 V , (b) Transconductance ( g m ) for V d = 2 V with V p = 2.2 V and 0 V .

TCAD simulations are performed to further study the underlying mechanisms of the drain oncurrent gain. The TCAD simulations have been calibrated using the experimental results from the 1.2 kV4H−SiC process and adjusted to account for the differences between the 3.3 kV and 1.2 kV processes. Fig. 4 illustrates a comparison of the Id-Vg characteristics of the 3.3 kV device under Vp=0 V and Vp=2.2 V bias conditions. As shown in Fig. 4, TCAD simulations also show a ~2x oncurrent, consistent with the experimental results.

[picture]

Fig. 4. (a). TCAD simulation Id-Vg characteristics of VDMOSFET for Vd=1 V and 2 V with Vp=0 V (solid) and Vp=2.2 V (dashed), (b) TCAD optimization results showing drain current gain (left axis) and the ratio of current gain to p-well current (right axis).

Fig. 4. (a). TCAD simulation Id-Vg characteristics of VDMOSFET for V d = 1 V and 2 V with V p = 0 V (solid) and V p = 2.2 V (dashed), (b) TCAD optimization results showing drain current gain (left axis) and the ratio of current gain to p-well current (right axis).

Fig. 5(a) illustrates a cross section of the energy band diagram along the source/ p -well/drift region junctions with Vp=0 V and Vp=2.2 V bias applied. Applying a positive Vp bias lowers the energy barrier between the source and the p-well regions, increasing current flow through the p-well region. A comparison of the current density plots shows that a higher current density is observed throughout the source junction region and is not limited to only the area near the surface channel when a positive bias is applied to the p-well. Electron flow in the region away from the surface area is not limited by the poor channel mobility of SiC , and as a result, a higher effective mobility, μ eff is obtained, as observed by the higher transconductance shown in Fig. 3(b). This is similar to the effect of onresistance improvement through the formation of current spreading layer (CSL) or deep JFET layer shown by Jang et al. [11] and Kim et al. [12], respectively.

[picture]

Fig. 5. TCAD simulation results showing (a) the energy band diagram across the region indicated by the dashed line, and total current density in the VDMOSFET region enclosed by the box for (b) Vp=0 V and (c) Vp=2.2 V.

Fig. 5. TCAD simulation results showing (a) the energy band diagram across the region indicated by the dashed line, and total current density in the VDMOSFET region enclosed by the box for (b) V p = 0 V and (c) V p = 2.2 V .

TCAD simulations are also used to further optimize the 3.3 kV device. As shown in Fig. 4(b), a higher on-current can be achieved through further device structure optimizations, while maintaining 5×103−104 ratio between on-current gain and the p-well current. This is accomplished by further increasing the conduction area to encompass a larger portion of the source area.

The specific on-resistance is shown in Fig. 6 alongside selected 3.3 kV results [13-15] and our previous 1.2 kV results [6], demonstrating that the p-well biasing results approach the SiC limit [16].

[picture]

Fig. 6. Specific on-resistance vs. breakdown voltage, showing p-well boosting approaches the SiC limit.

Fig. 6. Specific on-resistance vs. breakdown voltage, showing p-well boosting approaches the SiC limit.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

A ~2x improvement in the on-current of 3300 V -rated 4H−SiC VDMOSFETs has been demonstrated. The current gain is achieved through the application of a positive bias to the p -well region. The application of the p -well bias does not result in significant increase in the p -well current, where a ratio of 5×103−104 between the on-current gain and the p-well current is observed. The specific on-resistance demonstrates that the p -well biasing yield results approaching the SiC limit. TCAD simulations are performed to understand the current boosting mechanism and to investigate further optimizations.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

The authors would like to thank Ian Widjaja for contributions to TCAD simulations, as well as Christopher Norwood, Kuk-Hwan Kim, and Valentin Abramzon for insightful discussions.

Author Contribution

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

YW: conceptualization (equal), writing - original draft (lead), formal analysis (lead), writing - review and editing (equal).

VN: conceptualization (equal), formal analysis, writing - review and editing (equal).
OM: formal analysis, writing - review and editing (equal).
AA: conceptualization (equal), formal analysis, writing - review and editing (equal).
NX: data curation (equal), investigation - simulation (equal), writing - review and editing (equal).
TD: data curation (equal), investigation - simulation (equal), writing - review and editing (equal).
DB: data curation (equal), investigation - simulation (equal), writing - review and editing (equal).

SR: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).
LL: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).

RY: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).
YQ: data curation (equal), investigation - device layout, process, test (equal), writing - review and editing (equal).

DTC: data curation (equal), formal analysis, investigation - device layout, process, test (equal), writing - review and editing (equal).

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.69.pdf

Uchida, Kosuke, et al. "The optimised design and characterization of 1200 V/2.0 mΩ cm24H SiC V-groove trench MOSFETs." 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2015.

Kim, Dongyoung, et al. "The effect of deep JFET and P-well implant of MOSFETs." IEEE Journal of the Electron Devices Society 10 (2022): 989-995.

Kim, Jeff Joohyung, et al. "Investigation into Relationship of the Switching Performance and Short-Circuit Withstand Time on 1.2 kV 4H-SiC Power MOSFETs." 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD). IEEE, 2024.

Han, Kijeong, and B. J. Baliga. "Comparison of four cell topologies for accumulationand inversion-channel MOSFETs: Analysis and experimental results." IEEE Transactions on Electron Devices 66.5 (2019): 2321-2326.

Masuda, Takeyoshi, et al. "Challenges in Extremely Low Specific On-Resistance with SiC SJVMOSFETs." Materials Science Forum. Vol. 1004. Trans Tech Publications Ltd, 2020.

Widjaja, Yuniarto, et al. "1200 V 4H-SiC VDMOSFET Having> 2.5x On-Current Improvement." International Conference on Silicon Carbide and Related Materials (2024): 530531.

S. Rathi, D. Macdonald, A. Murphy, M. Bell, R. Young, and D. Clark, "Influence of Channel Length and Gate Oxide Thickness Variations in 3300 V 4H-SiC VDMOSFET." International Conference on Silicon Carbide and Related Materials (2023).

Franco, Jacopo, et al. "Reduction of the BTI time-dependent variability in nanoscaled MOSFETs by body bias." 2013 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2013.

Waltl, Michael, et al. "Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors." Microelectronics Reliability 168 (2025): 115693.

Kimoto, Tsunenobu, and Heiji Watanabe. "Defect engineering in SiC technology for highvoltage power devices." Applied Physics Express 13.12 (2020): 120101.

Jang, Seung Yup, et al. "Improved on-state resistance with reliable reverse characteristics in 1.2 kV 4H-SiC MOSFET by selective nitrogen implantation assisted current spreading layer." Japanese Journal of Applied Physics 59.4 (2020): 046501.

Kim, Dongyoung, et al. "The effect of deep JFET and P-well implant of MOSFETs." IEEE Journal of the Electron Devices Society 10 (2022): 989-995.

Palmour, John W., et al. "Silicon carbide power MOSFETs: Breakthrough performance from 900 V up to 15 kV ." 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014.

Zhang, Luyang, et al. "Comparison of a 3.3 kV SiC Hybrid-Channel Trench MOSFET and a Planar MOSFET." 2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe). IEEE, 2022.

Chen, Ximing, et al. "Different JFET designs on conduction and short-circuit capability for 3.3 kV planar-gate silicon carbide MOSFETs." IEEE Journal of the Electron Devices Society 8 (2020): 841-845.

Baliga, B. Jayant. "Fundamentals of Power Semiconductor Devices." Springer, Berlin (2008).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 75-83

doi: 10.4028/p-e0IRdP

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-15

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-19

Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Haizhao Zhi 1,a*, Sirui Feng 1,b, Xiaoping Wang 1,c, Xinpeng Lin 1,d, Yitian Jiang 1,e, Haolin Hu 1,f and Yuxi Wan 1, g*

1 Shenzhen Pinghu Laboratory, No. 93, Xinxia Avenue, Pinghu Subdistrict, Longgang District Shenzhen, China

a  zhihaizhao@phlab.com.cn, b  fengsirui@phlab.com.cn, c  wangxiaoping@phlab.com.cn, dlinxinpeng@phlab.com.cn, ejiangyitian@phlab.com.cn, 'huhaolin@phlab.com.cn g  wanyuxi@phlab.com.cn

Keywords: SiC trench MOSFET, clamped PMOS, trench refill, single event burn-out.

Abstract

This study proposes a refilled PMOS SiC trench MOSFET (RPTMOS) design with integrated parasitic PMOS clamping transistors to mitigate single-event burnout (SEB) susceptibility. The configuration of the core epi-refill process to realize the proposed RPTMOS is also demonstrated. Through systematic TCAD simulations, we analyze the transient lattice temperature, electric field distribution, and current density dynamics under heavy-ion irradiation (LET =19.0MeV·cm2/mg, Drain DC Bias VD=500 V ). The optimized structure features a grounded parasitic PMOS clamp formed by the P-connect, P-bottom, and N-drift regions, which enables efficient hole extraction and suppresses electric field crowding at the gate oxide corner. Comparative simulations reveal that the proposed design reduces peak lattice temperatures and elevates the SEB withstand voltage by ~20%. Parametric studies further demonstrate that increasing the P-connect thickness ( 200\AA→400\AA ) significantly enhance radiation hardness, proves the pivotal contribution from the parasitic PMOS. The findings offering a viable pathway for radiation-hardened SiC power devices in aerospace and high-energy applications.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

SiC MOSFET are very attractive for irradiated power electronics applications[1]. One of the biggest threat to the SiC MOSFET operated under irradiation is the single-event-burnout (SEB) effect, which can cause permanent damage due to the incidence of high-energy particles. These particles generate electron and hole pairs along the incident path leading to local electrical field spike and serious thermal effect. Since the generated electrons could be drifted by the high drain bias, pumping out the holes in time become the critical reinforcement strategy to avoid SEB.

Many technologies have been developed to improve the anti-SEB capability. For instance, the N+N− junction within the deep P+ well of CoolSiC trench MOSFET to assist the hole extraction[2], adoption of semi-Superjunction[3], multi-buffer and multi-shield below p-well[4,5,6].

In this work, we proposed a refilled PMOS SiC trench MOSFET (RPTMOS), which protects the gate oxide[7] and help to pump out the irradiation-generated holes by the parasitic PMOS. The parasitic PMOSs are formed by a epi-refill process, which controls the flow rate of hydrogen chloride (HCl) gas during the trench re-fill process and grow a thin p -type region ( p -connect) on the side walls of trench. TCAD characterization reveals that the lateral thickness of the p-connect region should be maintained below 400\AA to achieve lower MOSFET on-resistance (Rds,on)[7]. We characterized the lattice temperature, electric field and current density etc. under heavy-ion strike with certain values of particle linear energy transfer (LET) and discovered that the parasitic PMOS plays a pivotal role during the SEB process.

Device Structure and Process

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Fabrication of the device follows our prior work [7], with key steps shown in Fig.1. Fig. 1 shows the main steps of realizing the RPTMOS.

As shown in Fig.1(a), from bottom to top, the epi-structure contains n+ substrate, n -buffer, n -epi (drift) layer, p-well layer, n+ source layer. The trench orientation in Fig.1(b), directed towards the reader, is aligned to the [11-20] crystal direction, with a deviation smaller than 0.2∘.

[picture]

Fig. 1. The fabrication process of the RPTMOS.

Fig. 1. The fabrication process of the RPTMOS.

The p-type epilayer is refilled in SiC trench, which can achieve a very thin layer ( <0.1μ m ) above the sidewalls of n-type trench[8] as shown in Fig.1(c), The addition of hydrogen chloride is to have a certain etching effect on the trench sidewall [9,10,11]. The final structure of the device is as shown in Fig.1(f) [7,11], the parasitic PMOS is labeled within the red rectangle.

SEB TCAD Simulation RESULT

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TCAD simulation was carried out to investigate the RPTMOS's performance under high-energy particle irradiation. For trench-gate devices, the region adjacent to the gate oxide represents the most vulnerable area in trench-gate MOSFET[4]. The conditions depicted in Fig. 2 correspond to vertical heavy-ion irradiation at x=5.0μ m of the trench-gate device, where x=5.0μ m marks the boundary layer between the SiC P -connect region and the gate oxide. The standardized SEB irradiation parameters: B.DENSITY (electron-hole pair generation density) =1×1020 cm−3 and radius =0.05μ m. This yields a linear energy transfer (LET) value of 0.126pC/μm, which equates to 19.0MeV·cm2/mg [2]. Our study adopts this LET value ( 19.0MeV·cm2/mg ) for TCAD simulations of SEB. The SEB LET threshold for 1200 V SiC MOSFETs is approximately 10MeV·cm2/mg [12], thereby justifying the selection of 19.0MeV·cm2/mg here as a conservative yet representative value for SEB.

About the RPTMOS, during reverse blocking operation, the parasitic PMOS inherently clamps the electrical potential of the p -bottom region. Under reverse blocking conditions, the P-bottom, N-drift, and P -well regions collectively form an equivalent PMOS clamping transistor. With the polysilicon gate grounded, the elevated potential in the N-drift region beneath the P-well activates the PMOS clamp, with the p -connect region as a hole provider. The parasitic PMOS act as an accumulationmode PMOS[7].

[picture]

Fig. 2. The vertical distribution of the lattice temperature of the RPTMOS along x=4.99μ m under heavy-ion irradiation at x=5.0μ m at different transient time steps T1 - T7. The arrows point to the lattice temperature distribution within the RPTMOS.

Fig. 2. The vertical distribution of the lattice temperature of the RPTMOS along x = 4.99 μ m under heavy-ion irradiation at x = 5.0 μ m at different transient time steps T 1 - T 7 . The arrows point to the lattice temperature distribution within the RPTMOS.

The vertical axis of Lattice Temperature in Fig. 2 illustrates the transient lattice temperature distribution along the vertical y -axis at x=4.99μ m (corresponding to the central axis of the P -connect region that spans a lateral width of 200\AA ) across distinct time points ( T1−T7 ). Under drain bias of VD=500 V, the first temperature peak emerges at y=3.0μ m. The embedded subplots (left: magnified lattice temperature distribution near the gate oxide corner at T4=500ps; right: global lattice temperature distribution of the RPTMOS) reveal that this peak lattice temperature corresponds to the interface between the P -connect region and the P -bottom region in Fig.1(c). Between T4=500ps and T5=1 ns, the localized peak lattice temperature at this region exceeds 1500 K . Subsequently, in Fig.2, a secondary temperature peak emerges at y=11.0μ m, occurring between T4=500ps and T7=10 ns after heavy-ion irradiation. This peak corresponds to the temperature spike at the n+/n−junction between the N-drift region and the substrate. Many studies propose multilayer buffer structures to suppress this localized temperature rise[4,5,6].

[picture]

Fig. 3. The figure illustrates the current density distribution along x=4.99μ m of the RPTMOS under vertical heavy-ion irradiation at x=5.0μ m and drain voltage of VD=500 V at different transient time steps T1−T7.

Fig. 3. The figure illustrates the current density distribution along x = 4.99 μ m of the RPTMOS under vertical heavy-ion irradiation at x = 5.0 μ m and drain voltage of V D = 500 V at different transient time steps T 1 − T 7 .

Fig. 3 illustrates the current density distribution along the longitudinal tangent at x=4.99μ m for the trench-gate device under vertical heavy-ion irradiation at x=5.0μ m and a drain voltage of VD= 500 V . At T1=5ps, the hole current density reaches its maximum value near y=2.0μ m to 3.0μ m (marked by the white dotted box), predominantly discharged through the parasitic equivalent

PMOS clamping transistor. The inset subplot depicts the spatial hole current density distribution, demonstrating that the hole current constitutes the dominant component ( >2e+07 A/cm2 ) of the ioninduced current density at this stage.

[picture]

Fig. 4. The figure presents the electric field intensity distribution along x=4.99μ m of the RPTMOS under vertical heavy-ion irradiation at x=5.0μ m and drain voltage of VD=500 V at different transient time steps T1 - T7. The arrows indicates the evolution of local peak electric field intensity vs. each transient time steps T1−T7.

Fig. 4. The figure presents the electric field intensity distribution along x = 4.99 μ m of the RPTMOS under vertical heavy-ion irradiation at x = 5.0 μ m and drain voltage of V D = 500 V at different transient time steps T 1 - T 7 . The arrows indicates the evolution of local peak electric field intensity vs. each transient time steps T 1 − T 7 .

Fig. 4 presents the electric field intensity distribution along x=4.99μ m for the trench-gate device under vertical heavy-ion irradiation at x=5.0μ m and a drain voltage of VD=500 V. The arrows annotates the shift of the position of peak electric field intensity at different transient time steps T1 T7 within the RPTMOS at following heavy-ion irradiation. At T3=100ps, the peak electric field ( 3.3MV/cm ) localizes at y=3.0μ m (near the trench-gate bottom corner), accompanied by a mild electric field crowding ( ~0.6MV/cm) near y=11μ m(n+/n−junction).

The peak electric field at y=3.0μ m arises from the requirement for charge neutrality within the semiconductor. Specifically, heavy-ion irradiation induces localized lattice temperature elevation and generates a high density of electron-hole pairs. In the absence of the equivalent PMOS clamping transistor, holes accumulate at the gate oxide corner due to the lack of an efficient extraction path. Concurrently, electrons are retained to satisfy charge neutrality, leading to increased plasma density. This disrupts the space-charge region's shielding effect, resulting in electric field peaking at y=3.0μ m (the trench-gate bottom corner). Under these conditions, the combined effects of reduced critical breakdown field strength of the gate oxide at elevated temperatures and the high applied drain voltage render the gate oxide corner susceptible to dielectric breakdown due to severe electric field crowding.

In the RPTMOS proposed herein, the grounded equivalent PMOS clamping transistor integrated into the trench sidewall enables rapid extraction of excess holes. Furthermore, by reducing the electron concentration at the conduction band edge to maintain charge neutrality, part of the spacecharge shielding of the p -doping region is preserved, mitigating field crowding and suppressing rapid junction temperature escalation.

Simulation RESULT Discussions

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A comparative analysis of the transient distributions of lattice temperature, current density, and electric field along x=4.99μ m under vertical 19.0MeV·cm2/mg heavy-ion irradiation in Fig.24(vertical radiation incidence at x=5.0μ m, VD=500 V ) reveals the following:

At T1−T3, the y=3.0μ m vicinity first exhibits a current density peak of 2.3×107 A/cm2 at T1= 5 ps . This peak spans a broad y-axis range ( y=1.0−3.0μ m ), coinciding with the equivalent PMOS clamping transistor and P -well regions. By T2=20ps, the current density peak declines to
1.1×107 A/cm2. At T3=100ps, the current density peak further diminishes to ~4×106 A/cm2, representing an approximate order-of-magnitude reduction compared to T1. Concurrent observation of the lattice temperature profile shows that the peak temperature rises from ~500 K at T1 to ~650 K at T2 and further to 1260 K at T3. This decline in current density between T1 and T3 can be attributed to the increasing localized temperature near y=3.0μ m, which elevates the resistance of the equivalent PMOS clamping transistor, thereby suppressing hole extraction efficiency. The T3 time point coincides with the transient electric field intensity curve reaching its extreme at y=3.0μ m. This result arises from the high transient hole density coupled with inefficient extraction of the PMOS, which weakens the space-charge region's protective effect on the gate oxide corner. Beyond T3, the peak temperature near y=3.0μ m gradually decreases, primarily due to external thermal dissipation (simulated with a thermal conductivity coefficient α=1 W/cm·K ). As the heavy-ion irradiation is a single-event process with a Gaussian temporal charge generation profile (width Tc=2ps ), the massive hole extraction process concludes after T3. Consequently, the space-charge shielding effect is gradually restored, leading to reduced electric field peaking at y=3.0μ m and a further temperature decline to ~970 K by T7=10 ns.

[picture]

Fig. 5. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) of the RPTMOS(labeled as refill MOSFET) throughout the irradiation process under different heavy-ion incidence conditions and structural parameters.

Fig. 5. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) of the RPTMOS(labeled as refill MOSFET) throughout the irradiation process under different heavy-ion incidence conditions and structural parameters.

Furthermore, we compare the temporal evolution of the SiC peak temperature throughout the heavy-ion irradiation process in Fig.5. The black inverted-triangle curve in Fig. 5 corresponds to the aforementioned scenario (vertical 19.0MeV·cm2/mg ion strike at x =5.0μ m, incident at the gate oxide/ SiC interface, VD=500 V ), where the device peak temperature reaches 1770 K . As analyzed earlier, the limited lateral width ( 200\AA along the x -axis) of the equivalent PMOS clamping transistor introduces current-limiting effects under elevated lattice temperatures, reducing hole extraction efficiency and weakening field shielding. Therefore, the blue diamond-shaped curve in Fig. 5 corresponds to a P-connect x-axis thickness increased from 200\AA to 400\AA under VD=500 V, yielding a peak temperature of 1616 K-significantly lower than the 200\AA case 1770 K . This demonstrates that increasing the P -connect thickness enhances the device's radiation hardness, on the other hand, the thicker P-connect thickness suppresses the Rds,on, which is a trade-off. The black upright-triangle curve represents identical ion strike parameters compared to the black invertedtriangle curve with VD reduced to 400 V , resulting in a lower peak temperature 1336 K .

In Fig.5, the red square-shaped curve represents a scenario where the ion strike is offset by 100 nm from the gate oxide/semiconductor interface x=5.0μ m to x=4.9μ m, leads the peak temperature decreases to 824.6 K . This results validates that the gate oxide/semiconductor interface is the most SEB-sensitive region of SiC Trench MOSFET[2]. Under this condition, the RPTMOS(labeled as refill MOSFET in Fig.5) attains its peak temperature around T5=1 ns. The rightside inset subplot in Fig. 5 depicts the lattice temperature distribution of the RPTMOS at T5=1 ns.

Apart from the peak temperature at the n+/n−junction between the substrate and N -drift region, two additional hot-spots localize at the source and drain terminals of the parasitic PMOS clamping transistor is observed(pointed by arrow). It can be inferred that even for an ion strike's incident position offset to x=4.9μ m, the parasitic PMOS clamping transistor retains significant charge extraction capability for ion-generated electron-hole pairs compared to the main p−n junction formed by p -well and n -drift region in RPTMOS.

[picture]

Fig. 6. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) throughout the heavy-ion irradiation process between the RPTMOS(labeled as refill MOSFET) with baseline (BSL) SiC trench MOSFET(lacking the equivalent PMOS clamping transistor). The proposed RPTMOS design with P-connect thickness along the x-axis increased from 200\AA to 400\AA.

Fig. 6. Comparison of the temporal evolution(horizontal axis) of the SiC peak temperature(vertical axis) throughout the heavy-ion irradiation process between the RPTMOS(labeled as refill MOSFET) with baseline (BSL) SiC trench MOSFET(lacking the equivalent PMOS clamping transistor). The proposed RPTMOS design with P-connect thickness along the x-axis increased from 200 \AA to 400 \AA .

Finally, we compare the temporal evolution of the SiC peak temperature throughout the heavy-ion irradiation process between the proposed RPTMOS(labeled as refill MOSFET in Fig.6) design with a baseline (BSL), lacking the equivalent PMOS clamping transistor, SiC trench MOSFET(labeled as BSL MOSFET in Fig.6) in Fig.6. Both devices share identical critical dimensions and doping profiles. In Fig.6, the brown cross-shaped curve represents the BSL MOSFET under vertical 19.0MeV·cm2/mg irradiation ( x=5.0μ m, VD=500 V ), exhibiting a peak temperature exceeding 2000 K , higher than the RPTMOS. Furthermore, the brown asterisk-shaped curve corresponds to the BSL MOSFET under Vd=400 V, yielding a peak temperature of 1548 K , still higher than the RPTMOS under identical conditions. For the RPTMOS, the SEB withstand voltage is improved by approximately 20%.

New SIC MOSFET Structure and Experimental Results

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Fig. 7 propose a novel SiC trench MOSFET structure[13]. Fig.7(b) provides a top-down perspective of the proposed SiC trench MOSFET structure corresponds to the B-B' horizontal crosssection of Fig.7(a) and 7(c). Regions with identical colors or patterns in Fig.7(a), 7(b), and 7(c) represent the same material compositions within the device.

[picture]

Fig. 7. This figure ilustrates a novel SiC trench MOSFET structure.

Fig. 7. This figure ilustrates a novel SiC trench MOSFET structure.

Compared to the previously described RPTMOS[7], an additional process step is introduced in the fabrication process shown in Fig.1(c): periodic selective regions along the trench direction are defined. As shown near the G-G' location in Fig.7(b)(top-down perspective of the new SiC MOSFET), an isotropic SiC etching process is applied to remove the thin p -connect region in this area, thereby forming a low on-resistance zone in the new SiC MOSFET.

[picture]

Fig. 8. SEM figure of the core epi-refill process from Fig.1(b) to Fig.1(c).

Fig. 8. SEM figure of the core epi-refill process from Fig.1(b) to Fig.1(c).

Moreover, we have successfully demonstrated the core epi-refill process from the structure in Fig. 1(b) to that in Fig. 1(c) using an 8-inch SiC wafer in our in-house 8-inch pilot line, as illustrated in Fig. 8. It is shown that a thin p-channel for the accumulation-mode p-MOS can be effectively fabricated through p-type epi-refill. By adjusting the HCl flow rate (optimum condition HCl1SiH4~ 20), we achieved the required process conditions to realize the configuration demanded by RPTMOS device. The trench aspect ratio was set at 13.0μ m:1.6μ m, with the trench direction (into the paper) aligned along the [11-20] crystal orientation, maintaining a misalignment of less than 0.2∘. The configuration of the n+ source contact and the p -well in the proposed RPTMOS is also depicted in Fig. 8. Additionally, the subfigure in Fig. 8 confirms that the epi-refill process enables a relatively uniform distribution across the wafer.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

This work demonstrates that integrating a parasitic PMOS clamping transistor into RPTMOS effectively mitigates SEB vulnerability by enhancing hole extraction and reducing field crowding. The parasitic PMOS clamp rapidly discharges ion-generated holes, preserving space-charge shielding and limiting peak electric fields at the gate oxide corner. Peak lattice temperatures near critical junctions (e.g., P-connect/P-bottom interface) are reduced by >230 K in the RPTMOS under 500 V drain DC bias, achieves a 20% higher SEB voltage than baseline MOSFET, highlighting its superiority in radiation-hardened applications. Furthermore, increasing the P-connect thickness ( 400 Å) lowers peak temperatures by around 10%, validating design flexibility and the pivotal contribution from the parasitic PMOS. Furthermore, we propose a novel SiC trench MOSFET structure with periodical epi-refilled p-connect structure, to better leverage the design advantages of RPTMOS. In addition, we successfully demonstrated the configuration of the core epi-refill process to realize the proposed RPTMOS.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.75.pdf

Palmour, John W., et al. "Silicon carbide power MOSFETs: Breakthrough performance from 900 V up to 15 kV ." 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's (ISPSD). IEEE, 2014, doi: 10.1109/ISPSD.2014.6855980.

Chen, De-Xin, et al. "TCAD Analysis of Single-Event Burnout Hardness for an Improved CoolSiC Trench MOSFET." IEEE Transactions on Electron Devices (2024), doi: 10.1109/TED.2024.3418727.

McPherson, Joseph A., et al. "Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment." Materials Science Forum. Vol. 1062. Trans Tech Publications Ltd, 2022, doi: .

Wang, Ying, et al. "A comparative study of single-event-burnout for 4H-SiC UMOSFET." IEEE Journal of the Electron Devices Society 10 (2022): 373-378, doi: 10.1109/JEDS.2022.3158810.

Yang, Rui, et al. "An improved single-event effect performance SiC MOSFET of hole extraction pillar combined with multilayer P -shield structure." IEEE Transactions on Electron Devices 71.2 (2024): 1018-1023, doi: 10.1109/TED.2023.3346372.

Lu, Jiang, et al. "Impact of varied buffer layer designs on single-event response of power MOSFETs." IEEE Transactions on Electron Devices 67.9 (2020): 3698-3704, doi: 10.1109/TED.2020.3008398.

Zhi, Haizhao, et al. "A New Structure and Process Method for SiC Trench MOSFET." 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET). IEEE, 2024, doi: 10.1109/ISSET62871.2024.10779737.

R. Kosugi, S. Ji, K. Mochizuki, H. Kouketsu, Y. Kawada, H. Fujisawa, K. Kojima, Y. Yonezawa, and H. Okumura, "Strong impact of slight trench direction misalignment from [1120] on deep trench filling epitaxy for SiC super-junction devices" Jpn. J. Appl. Phys. 56, p. 04CR05, 2017, doi: 10.7567/JJAP.56.04CR05.

Ji, S., Kojima, K., Kosugi, R., Saito, S., Sakuma, Y., Tanaka, Y., ... & Okumura, H. (2015). "Influence of growth pressure on filling 4H-SiC trenches by CVD method." Japanese Journal of Applied Physics, 55(1S), 01AC04, doi:10.7567/JJAP.55.01AC04.

Tsunenobu Kimoto, James A. Cooper, "Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications", John Wiley & Sons, 2014.

H. Zhi, W. Zeng, Y. Wan, H. Hu, X. Wang. "A silicon carbide transistor, its manufacturing method and electronic device," C.N. Patent No. CN118352396B, April. 30, 2024.

Martinella, Corinna. "Single-event radiation effects in silicon carbide power MOSFETs." JYU dissertations (2021).

H. Zhi, X. Wan. "Silicon carbide device, manufacturing method of silicon carbide device and electronic device," C.N. Patent No. CN119767744A, April. 4, 2025.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 85-92

doi: 10.4028/p-uvfY1Y

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-18

Accepted:
2026-03-16

Online:
2026-05-19

Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

Kailun Zhong 1,a*, Vamsi Mulpuri 1, b, Vishank Talesara 1,c, Arash Salemi 1, d, Sumit Jadav 1,e and Siddarth Sundaresan 1,f

1 Navitas Semiconductor, 3520 Challenger Street, Torrance, CA 90503, USA

a* kailun.zhong@navitassemi.com, b  vamsi.mulpuri@navitassemi.com, c  vishank.talesare@navitassemi.com, darash.salemi@navitassemi.com, e  sumit.jadav@navitassemi.com, f  siddarth.sundaresan@navitassemi.com

Keywords: SiC MOSFET, on-resistance, avalanche, short-circuit, robustness, automotive, static characteristics.

Abstract

A comparative study of state-of-the-art commercial 1200 V trench-gate, planar-gate, and trench-assisted planar Silicon Carbide (SiC) MOSFETs is presented. The experimental study mainly focuses on disclosing the static and robustness characteristics of distinct SiC technologies targeting automotive applications under room and high temperatures. The benchmark study of static characteristics covers specific on-resistance ( RON,SP ), gate leakage ( IGSS ), drain leakage ( IDSS ), breakdown voltage ( BVDSS  ), and drain-induced barrier lowering (DIBL) effects. The avalanche robustness is investigated by the unclamping inductive switching (UIS) setup under 25∘C and 175 ∘C while the single-pulse and repetitive short-circuit capability is evaluated under hard switching fault (HSF) under 25∘C.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

Silicon carbide (SiC) power MOSFETs are promising switches for high-voltage, high-power, high-frequency, and high-temperature applications to replace legacy Silicon counterparts in existing applications, owing to wide bandgap, high breakdown electric field, and excellent thermal conductivity [1]. The adoption of 1200 V SiC MOSFETs into electric vehicles (EV) is increasingly popular because the superior efficiency, high power density, high-temperature operating capability, and faster switching speed contribute to longer driving range, shorter charging time, and more compact system design.

For automotive applications, the most important parameters of SiC power devices are lower onresistance to minimize the conduction losses, faster switching speeds to decrease the switching losses, high breakdown voltage to handle the high-voltage architecture, and wide operating temperature range to withstand harsh engine compartment conditions, contributing to the improved efficiency. In addition, the SiC power MOSFETs used for automotive applications can experience high voltage spikes and potential short circuits during motor control and power conversion, and their ability to withstand these events directly impacts the reliability and safety of the system, especially in demanding situations like rapid acceleration or sudden braking where large current surges can occur. The SiC MOSFETs with poor avalanche or short-circuit robustness could fail permanently, leading to system malfunction or even damage to other components.

Multiple manufacturers have released their latest generation of 1200 V silicon carbide (SiC) MOSFETs, which are qualified to AEC-Q101 standards for demanding automotive applications. These components are specifically designed to meet the requirements of high-power systems such as on-board chargers (OBCs), traction inverters, and e-compressor inverters [2]. These commercial 1200 V SiC MOSFETs adopt planar-gate, trench-gate, and trench-assisted planar technologies with their unique benefits and weaknesses as discussed in [3] and [4]. There are very limited studies making comprehensive benchmark between the state-of-the-art 1200 V SiC MOSFETs oriented towards automotive applications. However, the comparative study of various 1200 V SiC technologies
are valuable for the researchers and engineers in the field when understanding the device performance and choosing the most suitable SiC power devices for their applications.

In this work, the static and robust characteristics of commercial 1200 V trench-gate, planar-gate, and trench-assisted planar SiC MOSFETs from five mainstream manufacturers are characterized with side-by-side comparison.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

Table 1 summarizes the key information for the devices under test (DUTs). We selected the latest generation trench-gate SiC MOSFETs from two manufacturers: Manufacturer A (asymmetric trench technology) and Manufacturer B (double trench technology). We also included the latest generation trench-assisted planar SiC MOSFETs from Navitas, and the latest generation planar SiC MOSFETs from two other distinct manufacturers, D and E . The blocking voltage rating is 1200 V for all DUTs.

The current rating is extracted from the datasheets and used for on-resistance ( RDS,ON ) test. To make fair comparison, the active areas of DUTs are extracted by optical measurement after decapsulation. Trench-gate silicon carbide (SiC) MOSFETs exhibit a high static threshold voltage ( VGS,TH ) of 4.2−4.3 V at room temperature, while planar-gate SiC MOSFETs have a lower VTH of 2.62.7 V . This difference is due to the different crystal faces used: trench-gate devices are built on the aface, which has a lower interface trap density, leading to higher channel mobility and a larger VGS,TH [5]. Owing to the benefits of high VGS,TH, the trench-gate SiC MOSFETs can be driven using 0 V gate turn-off voltage ( VGS,OFF ) while planar-gate SiC MOSFETs recommend a negative VGS,OFF to avoid false turn-on. The trench-gate technologies show a higher temperature coefficient.

Table 1 also shows that trench-assisted planar technology offers several advantages over traditional planar technology, including lower RON,SP,QGD,QGD×RON,SP. While trench-gate technology offers a lower Ron,Sp, the trench-assisted planar technology delivers a superior FOM (Figure of Merit) considering both BVDSS and RON,SP(BVDSS2/RON,SP). Its performance surpasses that of planar-gate technology and is slightly inferior to trench-gate technology. The QGD and QGD×RON,SP

Table 1. Key information of devices under test from different manufacturers.

Manufacturer | A | B | Navitas | D | E
Technology | Asymmetric Trench | Double Trench | Trench-assisted Planar | Planar | Planar
Generation | Gen 2 | Gen 4 | Gen 4 | Gen 3 | Gen 4
Voltage Rating (V) | 1200 | 1200 | 1200 | 1200 | 1200
VGS,th (V) * | 4.3 | 4.2 | 2.6 | 2.7 | 2.6
BVDSS (V) at VGS = 0V * | 1486 | 1550 | 1696 | 1532 | 1609
Current Rating (A) | 56.7 | 42 | 70 | 74 | 84.3
RDS,ON (mΩ) at 25°C | 12.2 | 18 | 12.5 | 14 | 13
RON,SP (mΩ·cm²) at 25°C | 1.9 | 2.4 | 2.6 | 3.3 | 3
RDS,ON (mΩ) at 175°C | 28.9 | 43.1 | 25 | 29 | 23
Temperature coefficient | 2.15 | 2.40 | 2.07 | 2.11 | 1.94
BVDSS²/ RON,SP | 1.16E+06 | 1.00E+06 | 1.11E+06 | 7.11E+05 | 8.63E+05
QGD (nC) | 34 | 52 | 82 | 98 | 102
QGD x RON,SP (nC·mΩ·cm²) | 64.6 | 124.8 | 213.2 | 323.4 | 306
VGS,ON / VGS,OFF (V) | +18/0 | +18/0 | +18/-5 | +18/-3 | +15/-4

[picture]

Fig. 1. (a) IGSS−VGS curves under VDS=0 V, TC=175∘C, (b) IGSS at VGS=25 V with TC from 25∘C to 175∘C. (c) IDSS−VDS curves under VGS=0 V, TC=175∘C, (b) breakdown voltage, BVDSS, is defined at IDSS=100μ A and extracted from IDSS−VDS curves at TC from 25∘C to 175∘C.

Fig. 1. (a) I G S S − V G S curves under V D S = 0 V , T C = 175 ∘ C , (b) I G S S at V G S = 25 V with T C from 25 ∘ C to 175 ∘ C . (c) I D S S − V D S curves under V G S = 0 V , T C = 175 ∘ C , (b) breakdown voltage, B V D S S , is defined at I D S S = 100 μ A and extracted from I D S S − V D S curves at T C from 25 ∘ C to 175 ∘ C .

of planar-gate technology is obviously inferior to trench-gate technology, while that of trench-assisted planar-gate technology is better than pure planar-gate devices.

Gate leakage ( IGSS  ) and drain leakage ( IDSS  ) are critical parameters for device reliability. As depicted in Fig. 1, the device from Manufacturer B demonstrated a significantly higher IGSS at elevated temperatures compared to the other manufacturers. The device from Manufacturer E presented a high IGSS at VGS=25 V and TC=175∘C, which is attributed to utilizing a thinner gate oxide [6] and corresponds to a lower VGS,ON of 15 V in Table I. Furthermore, Manufacturer B also exhibited higher IDSS at low drain-source voltages, and a noticeable reduction in breakdown voltage (BV DSS) with increasing temperature. In contrast, the device from Navitas showed a robust BVDSS greater than 1700 V , indicating excellent immunity to high-voltage spikes.

The drain-induced barrier lowering (DIBL) effect, which influences the threshold voltage (V GS,TH), was also analyzed. The DIBL coefficient ( ΔVTH_dibl) was defined as the change in VGS,th as the drain-source voltage ( VDS ) increased from 3 V to 1200 V . As illustrated in Fig. 2, Manufacturer A's trench-gate device, despite having the highest initial VGS,TH, exhibited the largest reduction in VGS,TH across the tested voltage range. This figure also demonstrates that the other manufacturers show better control over threshold voltage stability at different voltages and temperatures.

The avalanche capability of the device under test (DUT) was characterized by using an unclamping inductive switching (UIS) setup in [7]. As shown in Fig. 3, a 1.0 mH inductor was utilized, and the inductor current was increased incrementally by approximately 1 A per step until either destructive or parametric failure was observed. The maximum current achieved just before failure was documented as the single-pulse avalanche current, designated as Ids,pk.

[picture]

Fig. 2. (a) Threshold voltage measured under different VDS,VTH_Dibl, at IDS=2.5 mA at TC=25∘C. (b) ΔVTH_DIBL  at IDS=2.5 mA with VDS from 3 V to 1200 V under TC=25∘C,125∘C,150∘C,175∘C.

Fig. 2. (a) Threshold voltage measured under different V D S , V T H _ D i b l , at I D S = 2.5 m A at T C = 25 ∘ C . (b) Δ V TH_DIBL at I D S = 2.5 m A with V D S from 3 V to 1200 V under T C = 25 ∘ C , 125 ∘ C , 150 ∘ C , 175 ∘ C .

Fig. 4 presents the normalized avalanche energy density ( EAS/ Active Area) and the normalized avalanche current density ( Ids,pk/ Active Area) for all DUTs at a junction temperature of 175∘C. The data indicates that the planar-gate and trench-assisted planar devices exhibited a superior energy handling capability per unit area compared to the trench-based devices, suggesting a more effective structural design for dissipating avalanche energy. This trend of greater robustness in planar devices is further supported by the data in Fig. 5, which illustrates the percentage change in these normalized parameters from 25∘C to 175∘C. The planar-gate and trench-assisted planar devices demonstrated a smaller reduction in avalanche energy and current density at elevated temperatures compared to the trench-gate devices. Notably, Manufacturer B, a double-trench MOSFET, showed the poorest avalanche performance among all tested technologies, suggesting a potential weakness in shielding at the bottom or corner of the gate trench.

[picture]

Fig. 3. UIS test circuit schematic [5].

Fig. 3. UIS test circuit schematic [5].

[picture]

Fig. 4. (a) normalized avalanche energy density ( EAS/ Active Area); (b) normalized avalanche current density ( Ids,pk/ Active Area).

Fig. 4. (a) normalized avalanche energy density ( E A S / Active Area); (b) normalized avalanche current density ( I d s , p k / Active Area).

[picture]

Fig. 5. Percentage change in normalized avalanche energy density and normalized avalanche current density from 25∘C to 175∘C.

Fig. 5. Percentage change in normalized avalanche energy density and normalized avalanche current density from 25 ∘ C to 175 ∘ C .

[picture]

Fig. 6. (a) Gate leakage characteristics of 1200 V SiC MOSFET from Manufacturer B tested at fresh status and after UIS fail at 25∘C with D-S short. (b) OBIRCH analysis of the decapsulated sample by applying 1 V/59μ A at gate with drain/source short to ground. (c) Zoom-in view of failure point beside gate pad.

Fig. 6. (a) Gate leakage characteristics of 1200 V SiC MOSFET from Manufacturer B tested at fresh status and after UIS fail at 25 ∘ C with D-S short. (b) OBIRCH analysis of the decapsulated sample by applying 1 V / 59 μ A at gate with drain/source short to ground. (c) Zoom-in view of failure point beside gate pad.

The parametric failure evidence of the device from Manufacturer B is explored from gate leakage characteristics as shown in Fig. 6(a). After UIS fail, IGSS  at VGS=−5 V and +18 V is 106 and 109 times higher than the values in the fresh status, respectively. The sample is further decapsulated without detecting destructive failure points. The optical beam induced resistance change (OBIRCH) analysis is conducted on the decapsulated die to find out the soft failure points located beside the gate pad, as shown in Fig 6 (b) and (c).

Single-pulse and repetitive short-circuit tests were conducted to evaluate the devices' fault tolerance. The single-pulse short-circuit test was used to quantify three critical parameters: the shortcircuit withstanding time (SCWT), the peak short-circuit current density ( Ids,pk ), and the short-circuit
energy density (ESC). As illustrated in Fig. 7, the device from Manufacturer B demonstrated the lowest Ids, highest SCWT, lowest normalized Ids,pk and highest normalized ESC. However, the other devices exhibited a much tighter range of SCWT, from 1.7 to 2.2μ s which are in acceptable range for the automotive applications.

A comparison of the UIS and SCWT results (Fig. 4 to 7) reveals a notable trade-off in Manufacturer B's design. The device's poor performance in the UIS test suggests susceptibility to gate oxide failure caused by electric field concentration at the trench corners. However, this structure appears to excel at thermal management and current limiting, resulting in a superior SCWT. This dichotomy highlights a fundamental design compromise in power semiconductors: optimizing for one type of fault tolerance often comes at the expense of another. Manufacturer B's design appears to have prioritized short-circuit robustness over avalanche capability.

[picture]

Fig. 7. (a) IDS waveforms during the single-pulse short-circuit test under VDS=800 V using VGS,ON/VGS,OFF and RG-total  shown in Table I. Comparison between five different manufacturers in terms of (b) short-circuit withstanding time (SCWT), (c) peak short-circuit current density ( Ids,pk/ active area) and short-circuit energy density ( ESC/ active area).

Fig. 7. (a) I D S waveforms during the single-pulse short-circuit test under V D S = 800 V using V G S , O N / V G S , O F F and R G -total shown in Table I. Comparison between five different manufacturers in terms of (b) short-circuit withstanding time (SCWT), (c) peak short-circuit current density ( I d s , p k / active area) and short-circuit energy density ( E S C / active area).

Furthermore, the repetitive short-circuit capability is investigated using a fixed VIN =800 V and a periodic gate driving scheme as shown in Fig. 8. The 1.4μ s gate driving pulse and 700 short-circuit shots are used by referring to literature [8]. The 20-second intervals are used to cool down DUTs and avoid self-heating effects during periodic short circuit tests. The intelligent LabVIEW control system can automatically capture IDS,VDS,VGS waveforms during every short-circuit shot. In addition, the IGSS and BVDSS  are monitored at 25∘C after every 100 short-circuit events to detect parametric failures.

The results, shown in Fig. 9, indicated that most devices, except for Manufacturer D, showed robust performance with no significant degradation in gate leakage or breakdown voltage. The device from Manufacturer D showed a marked increase in gate leakage and lost its blocking capability after the repetitive stress test, highlighting a potential reliability concern.

[picture]

Fig. 8. (a) Schematic of hard switching short-circuit testing setup with LabVIEW control system. Control schematic for (b) single-pulse and (c) repetitive short-circuit test.

Fig. 8. (a) Schematic of hard switching short-circuit testing setup with LabVIEW control system. Control schematic for (b) single-pulse and (c) repetitive short-circuit test.

[picture]

Fig. 9. (a) Ids,pk/ Active Area and (b) ESC/ Active Area, (c) IGSS under VGS=25 V, VDS=0 V at 25 ∘C, (d) percentage shift of BVDSS  at 25∘C after 1 to 700 repetitive short-circuit cycles under VDS= 800 V , gate driving pulse width of 1.4μ s.

Fig. 9. (a) I d s , p k / Active Area and (b) E S C / Active Area, (c) I G S S under V G S = 25 V , V D S = 0 V at 25 ∘ C , (d) percentage shift of B V DSS at 25 ∘ C after 1 to 700 repetitive short-circuit cycles under V D S = 800 V , gate driving pulse width of 1.4 μ s .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

This benchmark study comprehensively compares the static and robustness characteristics of five state-of-the-art commercial 1200 V SiC MOSFETs. The findings reveal a variety of performance trade-offs among different SiC technologies. Although trench-gate devices offer lower on-resistance at room temperature, planar-gate and trench-assisted planar devices demonstrate superior performance at higher temperatures and greater thermal robustness under avalanche conditions. Short-circuit tests also revealed significant differences in fault tolerance. This underscores the importance of thorough characterization beyond standard datasheet parameters, especially for highreliability automotive applications. The study confirms that while SiC technology is mature, significant variation still exists in the reliability and performance of commercially available devices.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.85.pdf

X. She, et al., "Review of Silicon Carbide Power Devices and Their Applications," in IEEE Trans. Ind. Electron., vol. 64, no. 10, pp. 8193-8205, Oct. 2017, doi: 10.1109/TIE.2017.2652401.

B. Shi, et al., "A review of silicon carbide MOSFETs in electrified vehicles: application, challenges, and future development," in IET Power Electron., vol. 16, no. 12, pp. 2103-2120, May 2023, doi: 10.1049/pel2.12524.

J. Wei et al., "Review on the Reliability Mechanisms of SiC Power MOSFETs: A Comparison Between Planar-Gate and Trench-Gate Structures," in IEEE Trans. Power Electron., vol. 38, no. 7, pp. 8990-9005, Jul. 2023, doi: 10.1109/TPEL.2023.3265864.

.

M. Chaturvedi, et al., "Comparison of Commercial Planar and Trench SiC MOSFETs by Electrical Characterization of Performance-Degrading Near-Interface Traps," in IEEE Trans. Electron Devices, vol. 69, no. 11, pp. 6225-6230, Nov. 2022, doi: 10.1109/TED.2022.3206184.

A. Piccioni, "Repetitive Short-Circuit Ruggedness of Different SiC MOSFET Channel Designs", in 2025 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2025, doi: 10.1109/IRPS48204.2025.10983574.

A. Fayyaz et al., "UIS failure mechanism of SiC power MOSFETs," in 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Fayetteville, AR, USA, 2016, pp. 118-122, doi: 10.1109/WiPDA.2016.7799921.

A. Romero, et al., "Active Short Circuit and Repetitive Short Circuit in 1.2 kV SiC MOSFETs", in 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), Phoenix, AZ, USA, 2021.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1055, pp 93-98

doi: 10.4028/p-VQop5J

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-08

Revised:
2025-12-15

Accepted:
2026-02-26

Online:
2026-05-19

Study of SiC Thyristors with Integrated Temperature Sensors

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Shuhao Cheng 1,a*, Kaiyu Chen 2, b, Zihan Zhang 1,c, Xiaowen Wang 2, d, Lei Yuan 1,e*, Da Huo 1,f, Xuesong Liu 3, g, Tongxiao Hou 3, h, Renxu Jia 1,i, Yuming Zhang 1,j

¹Faculty of Integrated Circuit, Xidian University, Xi'an 710071, China

2 Alkaidsemi Electronic Technology Ltd., Shanghai, China

3 Beijing BJAST Holdings Co., Ltd., Beijing, China

a 13757758666@163.com, b gary_chen@alkaidsemi.com c 24251111422@stu.xidian.edu.cn, d xiaowen_wang@alkaidsemi.com, e yuanlei@xidian.edu.cn, f 22111213858@stu.xidian.edu.cn, q |xs6721@126.com, n 644988605@qq.com, i rxjia@mail.xidian.edu.cn, j zhangym@xidian.edu.cn

Abstract

SiC GTOs, with high current handling capability, are promising for high-voltage and highpower applications, but they also have temperature-related reliability issues, so real-time junction temperature monitoring is needed. In this paper, a novel 4H−SiC gate turn-off thyristor (GTO) structure with integrated temperature sensor is proposed. The proposed sensor is compatible with the SiC GTO process and allows for real-time temperature monitoring. TCAD simulation results show that the integrated sensor has a high sensitivity of 1.64mV/K and linearity of 0.99891 , the temperature sensor monitors the internal temperature of the GTO device in real time with an error of no more than 2 K during complete GTO switching. This new structure is conducive to enhancing the reliability of SiC thyristor applications and system miniaturization.

Keywords: 4H−SiC GTO, PiN diode, Temperature sensor, Real-time temperature monitoring.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Gate turn-off thyristors (GTOs) are high-power semiconductor devices commonly used in applications such as power converters, inverters, and pulsed power switches. They serve as key components in wind power systems to stabilize output power and current [1], and are widely employed in high-speed railways and high-voltage direct current (HVDC) transmission [2]. However, conventional silicon ( Si ) GTOs are constrained by the material's theoretical limits, which are inadequate for modern high-voltage systems. To address these limitations, silicon carbide ( SiC ) has emerged as a promising third-generation semiconductor material due to its wide bandgap, high thermal conductivity, and high saturation carrier velocity, leading to significant research interest in SiC-based GTOs for their superior current capability, high blocking voltage, and high-temperature and high-frequency operation.

Despite these benefits, SiC GTOs also present several reliability challenges, most of which are temperature-related [3-5]. It is evident that, under high-voltage and high-current switching conditions, effective thermal management is essential to prevent junction overheating. Thermal failure occurs when the junction temperature exceeds safe limits. Therefore, real-time temperature monitoring is essential, and since conventional physical methods are prone to inaccuracy and delay, integrated temperature sensors represent a promising direction for future developments.

Recent developments in SiC temperature sensors include PN junctions, PiN transistors, Schottky barrier diodes (SBDs), and body resistors. Among these, SiC PiN diode-based sensors exhibit high sensitivity ( 4.3mV/∘C ) and excellent linearity ( 0.9996 ) from room temperature up to 460∘C [6]. The low temperature dependence of the saturation current Is Is contributes to improved linearity. Additionally, a PTAT (Proportional to Absolute Temperature) structure using the voltage difference between two SiC PiN diodes can eliminate the influence of series resistance [7].

In this paper, a novel SiC GTO structure with an integrated temperature sensor is designed and investigated, offering advantages in process compatibility and compact layout. The paper first introduces the structure and operational principle of the proposed device. followed by an analysis of
the temperature sensor's linearity and sensitivity. Finally, the switching characteristics of the integrated SiC GTO are simulated, and the carrier behavior, temperature distribution, and dynamic temperature measurement process are examined across different operational phases, demonstrating its capability for real-time thermal monitoring.

Device Structure

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

In order to study the operation of the device during the switching process and to obtain the carrier and temperature distribution inside the device, the device structure was modeled using TCAD software. It should be noted that the 2D simulation simplifies the actual three-dimensional heat transfer; therefore, the following thermal and sensor response results are intended for qualitative analysis of trends and operational principles, rather than as quantitatively precise predictions. Fig. 1 shows the device cross-section of the integrated temperature sensor GTO. Terminal structures are generated by ion implantation at the same time as the gate ohmic contact region after the P -drift region etching is completed, which has a width of 8μ m, an injection depth of 1μ m and a doping concentration of 2×1017 cm−3, this terminal structure also serves as an isolation area for the temperature sensors at the same time. N+ substrate doping concentration of 1×1019 cm−3. The thickness of the P buffer layer was 2μ m and the doping concentration was 2×1017 cm−3. The thickness of the P -drift region was 30μ m and the doping concentration was 3×1015 cm−3. The thickness of the N-base region was 3μ m and the doping concentration was 2×1017 cm−3. The thickness of the P+ Anode region was 2μ m and the doping concentration was 1×1019 cm−3.

[picture]

Fig. 1. 4H-SiC GTO Integrated Temperature Sensor Structure.

Fig. 1. 4H-SiC GTO Integrated Temperature Sensor Structure.

The physical models used in the simulation process include: Shockley-Read-Hall recombination model, Auger recombination model, IncompleteIonization model, DopingDependence model, HighFieldSaturation model, BandGapNarrowing model, thermodynamic model [8-12].

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Fig. 2 illustrates the current-voltage characteristics of the temperature sensor measured at different temperatures. The relationship between current and voltage follows Eq. 1 while qVd≫ηkT :

Vd=ηkTqln(IdIs)(1)

where η is the ideality factor, Is is the saturation current, and k is the Boltzmann constant. At low sensor currents, the voltage drop decreases as temperature increases, primarily due to the enhanced conductance modulation effect. Conversely, at high sensor currents, the influence of temperature on carrier mobility becomes dominant, leading to an increase in the sensor voltage drop with rising temperature.

[picture]

Fig. 2. I-V Characteristics of sensors at different temperature.

Fig. 2. I-V Characteristics of sensors at different temperature.

Fig. 3. V-T Characteristics of Temperature Sensors.

Fig. 3 shows the relationship between the temperature sensor voltage drop and temperature for a certain operating current Id. When the effect of temperature on the ideal factor and saturation current is not taken into account, there is an approximately linear relationship between the voltage drop Vd and the temperature.

Temperature sensors integrated on the GTO need to be compatible with the GTO process, the doping concentration, thickness and other parameters need to be kept constant, and only the operating current can be changed to adjust the linearity and sensitivity of two parameters. Sensitivity and linearity (R2) are two important parameters of temperature sensors that reflect their ability to monitor temperature.

The V-T characteristics of the sensors with different operating currents and the relationship between operating current and sensor sensitivity and linearity are shown in Fig. 4.

[picture]

Fig. 4. (a) Sensor V-T characteristics at different currents;(b) Relationship between sensor sensitivity and linearity at different currents.

Fig. 4. (a) Sensor V-T characteristics at different currents;(b) Relationship between sensor sensitivity and linearity at different currents.

From Fig. 4(b), it can be seen that the linearity and sensitivity of the sensor decreases with increasing operating current, The reason is that as the operating current increases the on-resistance of the sensor decreases and the reverse saturation current increases.

The integrated PiN temperature sensor has lower linearity and sensitivity parameters compared to the longitudinal PiN temperature sensor in [6] because of the need for compatibility with the GTO process. However, the sensitivity of the Schottky diode is 1.21mV/K compared to the Schottky diode sensor integrated in SiC MOS in [13] at the same operating current, whereas the sensitivity of the integrated PiN temperature sensor is better than the Schottky diode sensor at 1.54mV/K. It also has an advantage over Schottky diode temperature sensors with a maximum sensitivity of 1.18mV/K as mentioned in [14].

Simulation of an Integrated Temperature Sensor GTO Using Switching Circuits, Fig. 5 shows the switching characteristic test circuit of SiC GTO. The circuit system includes resistors R1 and R2, a GTO thyristor, a voltage source V2 and a current source I1 that generates a gate trigger signal.

[picture]

Fig. 5. Thyristor Switching Characteristics Simulation Circuit.

Fig. 5. Thyristor Switching Characteristics Simulation Circuit.

Fig. 6. GTO temperature change during switching.

While making the switching circuit connections to the GTO, a current source is also required to connect the temperature sensor, which operating current is set to 1 mA . The temperature variations during the switching process are shown in Fig. 6, and four time points during the switching process are selected to analyze the carrier distribution, the actual temperature of the device, the sensor detection temperature distribution.

During the switching process the thyristor experiences a complete operating state. At first a negative voltage is applied to the cathode and the device is in the blocking state, then a negative signal is applied to the gate and the device changes from the blocking state to the on state. Fig. 7 shows the temperature and carrier distribution before and after the GTO is turned on from T0 to T1.

[picture]

Fig. 7. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-on.

Fig. 7. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-on.

From the carrier distribution in Fig. 7, it can be seen that holes in the P+ anode region and electrons in the N+ substrate region arrive at the P -drift region during device turn-on to undergo conductance modulation to make the device voltage drop. From the distribution of holes, the PN junction formed by the N -base region and the P -drift region changes from reverse bias to forward bias, the device conducts, and the isolation region formed by the terminal structure can play a good role in isolation. Temperature changes during opening occur mainly in the isolated area of the sensor which are minimal.

The carrier distribution remains stable after GTO conducting. Temperature changes occur in the isolation zone are small at around 10 K , Fig. 8 shows the carrier and temperature distribution of the GTO during conduction from T1 to T2.

[picture]

Fig. 8. (a) Electron density (b) Hole density (c) Temperature distribution during device conduction.

Fig. 8. (a) Electron density (b) Hole density (c) Temperature distribution during device conduction.

During the change of the device from conducting to blocking, a positive signal needs to be applied to the gate to compound and extract the carriers in the drift region, The carrier and temperature distribution from T2 to T3 during turn-off is shown in Fig. 9.

[picture]

Fig. 9. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-off.

Fig. 9. (a) Electron density (b) Hole density (c) Temperature distribution during device turn-off.

Carrier concentration in the drift region during turn-off decreases with gate extraction, The conductivity of the drift region decreases and the PN junction formed by the N-base and P-drift regions is reversely biased as seen from the distribution of holes, the device voltage drop increases. The temperature of the device varies greatly due to the high current and voltage to be withstood during turn-off.

During the switching simulation of the integrated temperature sensor GTO, the operating current of the sensor is constant at 1 mA and the variation of the sensor's voltage drop with time is shown in Fig. 10.

[picture]

Fig. 10. Sensor current and voltage over time.

Fig. 10. Sensor current and voltage over time.

[picture]

Fig. 11. Comparison of sensor measurements with actual device temperature.

Fig. 11. Comparison of sensor measurements with actual device temperature.

In Fig. 10, as the sensor current stable, its voltage also remains stable. The voltage varies with the temperature of the integrated sensor, due to the large temperature change during turn-off, the sensor voltage change during turn-off is also more pronounced.

Based on the voltage response of the sensor shown in Fig. 10 and the previously established V-T relationship from Fig. 3, the temperature extracted from the sensor closely matches the actual device temperature. As illustrated in the real-time monitoring results in Fig. 11, during the turn-on phase under low operating voltage, both the actual temperature change and the sensor voltage drop are minimal, leading to only a slight detected temperature variation. In contrast, the turn-off transition
subjects the device to high voltage and current, causing significant heating reflected by a sharp decrease in sensor voltage and a corresponding large temperature rise, with the peak temperature occurring during turn-off. After turn-off, as the device cools due to reduced current, the sensor voltage increases and the detected temperature declines. Throughout the entire process, the sensor demonstrates high accuracy in tracking device temperature, with errors not exceeding 2 K .

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

In this paper, an integrated PiN temperature sensor 4H−SiC GTO structure compatible with the junction termination process is simulated using TCAD simulation software. The effect of sensitivity and linearity of the sensor at different operating currents was simulated, its sensitivity was maximized to 1.64mV/K and linearity was maximized to 0.99891. The device was simulated using a switching circuit to analyze the changes in carrier and temperature distributions at different stages of operation to analyze and compare sensor measurements, the results show that the sensor is able to monitor the temperature change of SiC GTO throughout the switching cycle in real time, measurement errors do not exceed 2 K , realizing the goal of integrating a temperature sensor in the GTO. The structure monitors the temperature inside the device can avoid the generation of thermal failure which have a better development prospect.

References

The original version of this paper is available on https://www.scientific.net/KEM.1055.93.pdf

Yarlagadda V, Karthika G A, Nagajyothi M, Bhavani J 2022 DSTATCOM based Closed Loop Controlled Wind Power Plant with Self Excited Induction Generator for Controlling Terminal Voltage against Load Disturbances p1-6.

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Li J, Pang L, Chen X, Zhang K, Wang X, Zhang Q 2021 Dianwang Jishu/Power System Technology 454941.

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Rao S, Di Benedetto L, Pangallo G, Rubino A, Bellone S, Della Corte F G 2016 IEEE Sensors Journal 166537.

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Chapter 9: SiC Devices for Quantum Applications and Harsh Radiation Environments

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 1-6

doi: 10.4028/p-E43pvH

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-31

Revised:
2025-12-15

Accepted:
2026-02-23

Online:
2026-05-20

Design and Characterization of an ODMR System for NV-Based Quantum Sensing

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

Luke Shoen 1,a, Jarod Remy 1, b, Lei Raymond Cao 1,c*

1 Nuclear Engineering Program, Department of Mechanical and Aerospace Engineering, The Ohio State University, Columbus, OH 43210, USA

a  shoen.3@osu.edu, b  Remy.45@osu.edu, c  cao.152@osu.edu

*Corresponding author

Keywords: silicon carbide, optically detected magnetic resonance, nitrogen-vacancy centers, radiation sensing, quantum defects, neutron irradiation.

Abstract

This paper presents the development of a confocal Optically Detected Magnetic Resonance (ODMR) system to study diamond and Silicon Carbide (SiC) for reactor dosimetry and quantum defect analysis. Initially, Nitrogen-Vacancy (NV) centers in diamond were characterized to establish a performance baseline, followed by plans to map and quantify color center populations in SiC crystals before and after alpha and neutron irradiation. By correlating ODMR data with electrical performance metrics, we aim to optimize fabrication and annealing protocols to investigate fast neutron sensitivity. The ODMR system, integrated with a home-built confocal microscopy setup, includes a microwave antenna, magnet, laser, objective, and advanced measurement devices such as Si-APD and Time Tagger 20 for high-resolution T2* and T2 measurements. The characterization of the instrument includes high-resolution fluorescence and ODMR spectra of NV centers in diamond, and improved resolution with confocal optics. Ongoing work focuses on correlating luminescence with reactor neutron fluence and the long-term goal is for the advancing SiC irradiation for integrated spin defect analysis.

1 Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

Silicon carbide ( SiC ) has emerged as a promising material for high-temperature and high dose-rate radiation detectors, due to its exceptional properties such as 10 times higher breakdown voltages and 3 times higher thermal conductivity compared to silicon, as well as suppressed leakage currents in high temperature environments. Beyond its traditional role in power electronics and radiation detection, SiC hosts spin defects, such as silicon vacancies (V_Si) and divacancies, that can function as quantum sensors [1], analogous to the nitrogen-vacancy (NV) centers in diamond. These defects enable sensitive measurements of magnetic fields, and temperature, making SiC a versatile platform for quantum sensing applications.
Our research began with setting up an in-house built optically detected magnetic resonance (ODMR) system to characterize the well-established NV center in diamond as a baseline model. In diamond, carbon atoms form a regular lattice where atomic point defects arise naturally during crystal formation or through irradiation. An NV center consists of a nitrogen atom substituting for a carbon atom, adjacent to a vacancy, forming an NV−color center when an electron is donated from the lattice [2]. This defect exhibits three ground spin states: m_s=0 (with strong fluorescence) and m_s=±1 (with weak fluorescence). Optical pumping with a green laser excites electrons to higher states, while a 2.87 GHz microwave field induces Rabi oscillations, driving transitions to the ±1 levels. These ±1 states, degenerate in the absence of a magnetic field, split via the Zeeman effect when a field is applied, allowing magnetic sensing through changes in photoluminescence. For instance, applying a magnetic field parallel to the [111] crystal axis splits the ±1 states proportionally to the field strength, enabling quantification as B_z=Δf/(2γ), where γ is the gyromagnetic ratio. Temperature shifts in resonance frequencies further enable thermal sensing [3]. Although diamonds host a wide range of color centers, such as N3 (colorless to brownish), H3/H4 (yellow to light green), and 480 nm bands (yellow to orange), the NV center is uniquely suited for quantum sensing because of its spin-
dependent photoluminescence and controllable energy-level structure.
To characterize these properties, we developed a confocal ODMR system and evaluated its performance on diamond samples. This setup allows for efficient screening of color centers, providing insights into spin state manipulation and sensing capabilities. Although ODMR has thus far been applied to diamond, our ultimate objective is to extend this to SiC, where silicon vacancies and divacancies closely mimic the NV center's behavior. Neutrons can induce such defects in SiC, and intuitively, these defects may enable neutron detection, either through ensemble luminance changes (e.g., yellow-red transitions in diamond analogs) or single-neutron events via spin coherence. As noted in [4] 3C-SiC divacancies have a millisecond Hahn-echo spin coherence time, which is among the longest measured in a naturally isotopic solid.
Our current efforts in irradiating diamond for reactor dosimetry highlight its potential, but SiC offers a lower-cost alternative with significant advantages. Unlike diamond, which lacks mature manufacturing facilities, SiC benefits from established synthetic production (as naturally occurring moissanite is extremely rare) and can be integrated with photonic devices. For example, spin defects can be incorporated into the epitaxial layer of SiC avalanche photodiodes (APDs), enabling an integrated quantum sensing platform via electrically detected magnetic resonance (EDMR) or photoelectrically detected magnetic resonance (PDMR) technique [5]. By advancing from diamondbased ODMR characterization toward SiC-focused development, this work presents our first step for developing scalable, real-world quantum sensors that is aimed to combine detection, readout, and processing in a single material system.

2 ODMR

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

2.1 System Description

The ODMR system (Figure 1) at The Ohio State University consists of a home-built confocal microscope integrated with a microwave antenna for spin manipulation, an electromagnetic coil to provide a magnetic field for Zeeman splitting, and a 532−nm laser for optical pumping. Fluorescence is collected with a 1.2-NA water-immersion objective and detected on a silicon avalanche photodiode, while a Time Tagger 20 ( 20 ps resolution) records timing for T2* and T2 measurements [6]. For baseline characterization, we used a 3.0×3.0×0.3 mm diamond plate containing 1−2ppm NV centers with ⟨100⟩ orientation, observed through a 550−nm long-pass filter [7].

[picture]

Fig. 1. OSU ODMR light path schematic. From right to left, antenna [8] radiates microwave frequency sequence, piezo stage allows for raster scanning, x−y stage for rough movement, objective to focus laser and collect fluorescence, electromagnetic coil ( L=6.8mH,∅58 mm, and length = 18 mm ) to induce Zeeman splitting, dichroic mirror to reflect laser and pass fluorescence, AOTF to allow for laser pulsing, variable neutral filter density filter to control laser intensity, laser to optically pump sample, 550 nm long pass filter to reduce background laser, confocal for higher resolution, spectrometer to collect fluorescence, EM-CCD for imaging NV centers, and SPAD to measure intensity/quantum parameters. The SPAD pulse counter (Time Tagger 20) can be seen in the top left.

Fig. 1. OSU ODMR light path schematic. From right to left, antenna [8] radiates microwave frequency sequence, piezo stage allows for raster scanning, x − y stage for rough movement, objective to focus laser and collect fluorescence, electromagnetic coil ( L = 6.8 m H , ∅ 58 m m , and length = 18 mm ) to induce Zeeman splitting, dichroic mirror to reflect laser and pass fluorescence, AOTF to allow for laser pulsing, variable neutral filter density filter to control laser intensity, laser to optically pump sample, 550 nm long pass filter to reduce background laser, confocal for higher resolution, spectrometer to collect fluorescence, EM-CCD for imaging NV centers, and SPAD to measure intensity/quantum parameters. The SPAD pulse counter (Time Tagger 20) can be seen in the top left.

2.2 Characterization

The system was tested by exciting the diamond sample with a 5 mW 532 nm continuous emission laser. Fluorescence spectra and ODMR spectra were collected to observe zero-field splitting and Zeeman splitting. Confocal microscopy was employed to enhance resolution by reducing phonon sideband scattering and to increase axial resolution.

3 Results

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

The ODMR system successfully characterized NV centers in diamond, producing fluorescence spectra with observable zero-phonon lines (ZPL) and ODMR spectra showing a peak at 2.868 GHz under zero magnetic field (Eq. 1). With an applied magnetic field, Zeeman splitting was observed at 2864 MHz and 2877 MHz , with four-fold splitting corresponding to the [111] NV ensemble crystal axis.

D=2.868GHz,ΔE=γeB(1)

[picture]

Fig. 2. Scanning fluorescence image of NV rich diamond (left). Fluorescence Spectrum of NV Center in Diamond (right). Black line demonstrates fluorescence collected without confocal system in place. The blue line shows fluorescence spectrum within a confocal volume ( dxy=324nm,dz=1μm,V=8.5×10−16 cm3 ).

Fig. 2. Scanning fluorescence image of NV rich diamond (left). Fluorescence Spectrum of NV Center in Diamond (right). Black line demonstrates fluorescence collected without confocal system in place. The blue line shows fluorescence spectrum within a confocal volume ( d x y = 324 n m , d z = 1 μ m , V = 8.5 × 10 − 16 c m 3 ).

As seen in Figure 2, the absorption spectrum is (nearly) identical to fluorescence spectrum and is mirrored about Zero Phonon Line (ZPL) [6]. Introducing a confocal lens suppresses much of the phonon sideband emission and rejects out-of-focus light, thereby reducing background scattering from the surrounding lattice and other defects. This results in a lower overall photon count but significantly improves spatial resolution and signal contrast within NV ensembles. In an NV- rich sample ( >200ppm ), a single confocal volume contains approximately twenty million NV color centers. Thus, ensemble optical/quantum behavior is measured, and distinguishability of single NV centers becomes impractical. A single crystal grown by chemical vapor deposition with high levels of purity, NV <0.02ppb, will allow for isolation of individual NV centers and precise determination of their quantum properties. The diffraction-limited lateral full width at half maximum (FWHM) of a single NV center is ~270 nm; therefore, the fluorescence scanning sampling step sizes are set to 100 nm to satisfy the Nyquist sampling criterion. Sigma-clipped frame averaging and z -stacking are used to improve fluorescence image quality, while ODMR resonance behavior are employed to confirm the presence of single NV centers.

[picture]

Fig. 3. ODMR Spectrum with Lorentzian Fit and 𝐁=0. Microwave frequency was swept in 0.1 GHz increments and relative intensity was measured using integration of fluorescence spectrum. Peak located at 2.868 GHz (Top left). High Resolution ODMR Spectrum of single NV center with B > 0 applied. Zeeman splitting is observed. Peaks observed at 2864 MHz and 2877 MHz .20 points per increment (Top right). ODMR Spectrum with B>0 aligned approximately to [111] NV ensemble crystal axis. Four-fold splitting is observed, corresponding to 4 crystal axis directions. Further splitting is degenerate and not observable (minimum detectable threshold 0.25% ) (bottom).

Fig. 3. ODMR Spectrum with Lorentzian Fit and 𝐁 = 0 . Microwave frequency was swept in 0.1 GHz increments and relative intensity was measured using integration of fluorescence spectrum. Peak located at 2.868 GHz (Top left). High Resolution ODMR Spectrum of single NV center with B > 0 applied. Zeeman splitting is observed. Peaks observed at 2864 MHz and 2877 MHz .20 points per increment (Top right). ODMR Spectrum with B > 0 aligned approximately to [111] NV ensemble crystal axis. Four-fold splitting is observed, corresponding to 4 crystal axis directions. Further splitting is degenerate and not observable (minimum detectable threshold 0.25 % ) (bottom).

To characterize the ODMR response of both NV ensembles and single NV centers, measurements were performed under varying magnetic field conditions, as summarized in Figure 3. At zero magnetic field, sweeping the microwave frequency in 0.1 GHz increments produces a single resonance dip at 2.868 GHz , consistent with the expected zero-field splitting of the NV center. When a finite magnetic field is applied to a single NV center, Zeeman splitting becomes evident, yielding two distinct resonances at 2864 MHz and 2877 MHz . These high-resolution measurements, averaged over 20 acquisitions per frequency point, demonstrate the sensitivity of the ODMR technique to small energy-level shifts. For an NV ensemble with the magnetic field aligned approximately along the [111] crystallographic axis, a characteristic fourfold splitting is observed, corresponding to the four
possible NV orientations in the diamond lattice. Additional fine structure associated with further sublevel splitting remains below the detectable contrast threshold of 0.25%, which was estimated based on the noise and off-resonance fluoresce signal. Together, these measurements validate the system's ability to resolve both ensemble and single-NV spin transitions across a range of magnetic field conditions.
The neutrally charged NV0 ( NV−without electron) does not produce ODMR signal, but does emit fluorescence, confounding the active center signal. The NV 0 presence necessitates for a method to differentiate the opposing color center fluorescence signals. Undesirable color centers can be distinguished by simultaneously measuring ODMR response and fluorescence, allowing each color center to be mapped according to its type. Similarly, in SiC, multiple fluorescence emitting color centers exist, varying the charge state and spin properties of the material. The ODMR system presented successfully differentiates NV−from NV0, allowing for accurate mapping of spin defect centers and providing a methodology for more complex materials such as SiC .

4 Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

The results confirm the efficacy of our newly built ODMR system in characterizing NV centers in diamond, providing a baseline for continuing SiC studies. The observed Zeeman splitting and fourfold splitting align with theoretical expectations for NV centers (5). SiC Schottky diodes exhibited promising stability at high temperatures, making them suitable for reactor dosimetry. The confocal system's ability to reduce background scattering enhances the resolution of fluorescence measurements, critical for quantum defect analysis. The current setup focuses on NV-diamond measurements but is designed with modularity to enable future extension to SiC -based defects. Detecting and addressing VSi centers in SiC is substantially more challenging, even with optimized high-contrast samples, making it important to understand the minimum ODMR contrast that this system can reliably detect. We estimate the lower detectable contrast boundary using C=k(σ/I0), where I0 is the mean off-resonance fluorescence, σ is its RMS noise, and k is the required signal-tonoise ratio (taken as 5 for a conservative criterion). Based on this analysis, the minimum detectable ODMR contrast for our setup is set at 0.25%.

5 Conclusion and Future Work

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

This study developed a confocal ODMR system to characterize NV centers in diamond, achieving high-resolution fluorescence and ODMR spectra. Future work includes irradiating diamond and SiC to correlate luminescence with reactor fluence, performing T2 measurements on single NV centers, and developing SiC sensors with integrated spin defect readouts.

Acknowledgments

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

We thank Dr. Jennifer Choy and Dr. Ricardo Vidrio for providing the microwave antenna and for constructive discussions. Dr. Raymond Cao acknowledges Dr. Takeshi Ohshima, Dr. Shinobu Onoda, Dr. Yuta Masuyama, and Dr. Shinichiro Sato for discussions and suggestions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.1.pdf

Castelletto, Stefania, and Alberto Boretti. "Silicon carbide color centers for quantum applications." Journal of Physics: Photonics 2, no. 2 (2020): 022001.

Gruber, A., A. Drabenstedt, C. Tietz, L. Fleury, Joerg Wrachtrup, and C. von Borczyskowski. "Scanning confocal optical microscopy and magnetic resonance on single defect centers." Science 276, no. 5321 (1997): 2012-2014.

Acosta, Victor M., Erik Bauch, Micah P. Ledbetter, Amir Waxman, L-S. Bouchard, and Dmitry Budker. "Temperature dependence of the nitrogen-vacancy magnetic resonance in diamond." Physical review letters 104, no. 7 (2010): 070801.

Christle, David J., Paul V. Klimov, Charles F. de las Casas, Krisztián Szász, Viktor Ivády, Valdas Jokubavicius, Jawad Ul Hassan et al. "Isolated spin qubits in SiC with a high-fidelity infrared spin-to-photon interface." Physical Review X 7, no. 2 (2017): 021046.

Nishikawa, Tetsuri, Naoya Morioka, Hiroshi Abe, Koichi Murata, Kazuki Okajima, Takeshi Ohshima, Hidekazu Tsuchida, and Norikazu Mizuochi. "Coherent photoelectrical readout of single spins in silicon carbide at room temperature." Nature Communications 16, no. 1 (2025): 3405.

Levine, E., Turner, M., Kehayias, P., Hart, C., Langellier, N., Trubko, R., Glenn, D., Fu, R., & Walsworth, R. (2019). Principles and techniques of the quantum diamond microscope. Nanophotonics, 8(11), 1945-1973. .

Diamond Plate Information. (n.d.). Adámas Nanotechnologies. .

K. Sasaki, Y. Monnai, S. Saijo, R. Fujita, H. Watanabe, J. Ishi-Hayase, K. M. Itoh, and E. Abe, "Broadband, large-area microwave antenna for optically detected magnetic resonance of nitrogen-vacancy centers in diamond," Rev. Sci. Instrum., vol. 87, no. 5, p. 053904, May 2016, doi: 10.1063/1.4952418.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 7-15

doi: 10.4028/p-tstCC7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-05

Revised:
2025-12-08

Accepted:
2026-02-23

Online:
2026-05-20

Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters

The original version of this paper is available on https://www.scientific.net/KEM.1056.7.pdf

Jannik H. Schwarberg 1,a*, Jan Dick 1, b, Alexander May 2,c, Paweł Michałowski 3, d, Birgit Kallinger 2,e, Robert Kammel 1,f, Mathias Rommel 2, g and Jörg Schulze 1,2, h

1 Friedrich-Alexander-Universität Erlangen-Nürnberg, Chair of Electron Devices, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer IISB, Schottkystraße 10, 91058 Erlangen, Germany

3 Łukasiewicz Research Network - Institute of Microelectronics and Photonics, al. Lotników 32/46 02-668 Warsaw, Poland

a jannik.schwarberg@fau.de, b  jan.dick@fau.de, c  alexander.may@iisb.fraunhofer.de, d  pawel.michalowski@imif.lukasiewicz.gov.pl, e  birgit.kallinger@iisb.fraunhofer.de, f robert.kammel@fau.de, 9 mathias.rommel@iisb.fraunhofer.de, h joerg.schulze@iisb.fraunhofer.de

Abstract

Silicon vacancies ( Vsi ) are relevant for quantum technologies, including sensing, computing, and communication. For the realization of quantum photonic integrated circuits (QPICs) and, therefore, co-integration of optical and electrical devices with resonant excitation through the wafer surface, a-plane 4H−SiC wafers are required. Transferring established complementary metal-oxide-semiconductor (CMOS)-compatible processes from c-plane to a-plane wafers is, therefore, a crucial step. In this work, key fabrication steps, namely ion implantation, thermal oxidation, and ohmic contact formation, were investigated for a-plane 4H−SiC substrates. To demonstrate successful process transfer, p-channel MOS field-effect transistors were fabricated and electrically characterized, showing comparable Ion /Ioff  ratios and mobilities to their c-plane counterparts, but with a threshold voltage shift from -7.1 V to -12 V on the a-plane. Additionally, tunneling diodes were realized as broadband light emitters, with a significant portion of the emission spectrum falling within the range of off-resonant excitation of Vsi centers. The devices maintained light emission functionality down to cryogenic temperatures.

Keywords: 4H−SiC a-Plane, CMOS , pMOS Transistor, Integrated Light Emitter, Tunneling Diode, Silicon Vacancy

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.7.pdf

Silicon vacancies ( Vssi ) in 4H−SiC emerged as a promising candidate for quantum sensing, communication and computing applications [1-5]. Electric fields enable tuning of their optical properties by depleting the local environment from free charge carriers thus reducing noise and by shifting resonance frequencies using the Stark effect [2,6]. Since the dipole moment of Vsi is aligned with the c-axis of the crystal, optical resonant excitation must be carried out perpendicular to this axis [7]. Conventional c-plane wafers only allow resonant excitation through a cleaved edge of the wafer [2], thus impairing the electrical properties of the devices. In contrast, lateral pin-diodes ( E→‖c→ ) on 4H−SiC a-plane wafers (a→⟂c→) enable convenient resonant excitation through the wafer surface.

Since these pin-diodes can be manufactured in a complementary metal-oxide-semiconductor (CMOS)-compatible process on the 4H−SiC platform [8, 9], co-integration of advanced integrated electronics and photonics is enabled which is a key step towards quantum photonic integrated circuits (QPICs) [1]. These allow for on-chip excitation and read-out of optical signals, thus lowering cost and complexity of the measurement setups needed.

In this work, we demonstrate the compatibility of the CMOS process on c-plane and a-plane wafers exemplarily using a p-channel MOS (pMOS) field-effect transistors, thus allowing transfer of state-of-the-art devices and circuits to a-plane wafers. Furthermore, a tunneling diode, which can be
manufactured in the same CMOS process, is proposed as a possible on-chip integrated light source for initialization and off-resonant excitation of VSi.

Methodology and Sample Fabrication

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The tunneling diodes and pMOS transistors were fabricated using a CMOS-compatible process [8] on two 35 mm on-axis 4H−SiC a-plane substrates. For reference, identical devices were also produced on four 150 mm c-plane wafers with a 4∘ off-cut. On both substrate types, 10μ m-thick n-type epitaxial layers were grown [9]. The nitrogen doping corresponds to the pMOS channel doping given in Table 3. To suppress ion channeling, a 30 nm scattering oxide was deposited prior to implantation. Aluminum and nitrogen ion implantation was employed to form the highly doped ptype and n-type regions, with implantation parameters as listed in Table 1. Dopant activation was carried out by annealing at 1700∘C in an argon atmosphere for 1 h using a carbon capping layer to mitigate carbon vacancy formation.

Table 1. Ion implantation parameters for generation of n -type and p -type profiles.

Parameter | n-type (nitrogen) | p-type (aluminum)
| Energy (keV) | Dose (1/cm²) | Energy (keV) | Dose (1/cm²)
Shot 1 | 90 | 4.0 · 10¹⁴ | 90 | 2.8 · 10¹⁴
Shot 2 | 50 | 2.3 · 10¹⁴ | 60 | 1.8 · 10¹⁴
Shot 3 | 25 | 2.0 · 10¹⁴ | 30 | 1.4 · 10¹⁴

The gate oxide was grown by dry thermal oxidation followed by an annealing in nitric oxide (NO) both at 880 mbar and 1300∘C. Due to different oxidation rates for a-plane and c-plane [9, 10], oxidation times were 6 min 30 s for a-plane and 33 min for c-plane substrates. The NO annealing time for a-plane devices was reduced from 60 min to 30 min .

The gate electrode was formed by low pressure chemical vapor deposition of n -doped polycrystalline silicon and patterned using a combination of dry and wet etching. After deposition of an insulating layer, contact areas were defined by dry etching of the contact holes, followed by selfaligned deposition of a 70 nm nickel-2.6wt% aluminum ( NiAl ) layer. This layer was patterned by lift-off, and ohmic contacts were formed by rapid thermal processing at 980∘C for 2 min . Residual NiAl was removed using Caro's acid. Following gate via etching, a metal stack of 40 nmTi/400 nmPt/40 nm Ti was deposited for metallization. Finally, a SiO2/Si3 N4/SiO2 layer stack was deposited and patterned by dry etching to passivate the devices against environmental exposure.

Evaluation of test structures for assessing process success

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Ion Implantation. For both c-plane and a-plane samples, ion implantation was performed using identical shots. Secondary ion mass spectrometry (SIMS) measurements are shown in Fig. 1 (left). The profiles reveal a deeper dopant penetration in the a-plane samples. This effect is attributed to extended channeling, which occurs despite the presence of a scattering oxide. The most plausible explanation for this is additional channeling along the m -axis, which is tilted by 30∘ relative to the a-axis and provides an additional channel path. Monte Carlo simulations conducted in Sentaurus technical computed aided design (TCAD) tool suggest that this behavior cannot be completely prevented no matter the implantation angle and scattering oxide thickness [9].

The influence of these implantation profiles on the sheet resistance of the p-type regions was evaluated based on transfer length method (TLM) measurements. A slight sheet resistance variation between a-plane ( 53.2±4.6kΩ/◻ ) and c-plane ( 40.7±0.8kΩ/◻ ) samples was observed. This impact may result from the higher background doping of the n-type epitaxial layer [9]. Since the TLM evaluation is based on purely ohmic behavior of the contacts, non-idealities also my lead to deviations

[picture]

Fig. 1. Left: SIMS measurements of the implanted 103±6.5 mΩ cm2 and 109±10.4 mΩ cm2-profiles on a -plane and c-plane samples. Middle: raw data of an I-V measurement of the p-type ohmic contacts. The straight lines are for better visibility of the measured data and underline the non-ideal ohmic behavior of the p-type ohmic contacts. Right: breakdown field strength of the thermally grown oxides of all samples grouped by substrate type. Sample sizes are 15 for a-plane and 51 for c-plane. Inset: exemplary leakage current density against applied electric field for samples 200μ m and 200μ m.

Fig. 1. Left: SIMS measurements of the implanted 103 ± 6.5 m Ω c m 2 and 109 ± 10.4 m Ω c m 2 -profiles on a -plane and c-plane samples. Middle: raw data of an I-V measurement of the p-type ohmic contacts. The straight lines are for better visibility of the measured data and underline the non-ideal ohmic behavior of the p-type ohmic contacts. Right: breakdown field strength of the thermally grown oxides of all samples grouped by substrate type. Sample sizes are 15 for a-plane and 51 for c-plane. Inset: exemplary leakage current density against applied electric field for samples 200 μ m and 200 μ m .

in the implanted dose cannot be excluded, as two different implantation systems had to be used due to the differences in wafer size.

For a complete process transfer, further testing with deeper implantation profiles - such as those used for p-well and n-well formation - is required. Nevertheless, the achieved high surface concentrations of the present process should allow for ohmic contact formation.

Ohmic Contact Formation. For characterization of the ohmic contacts, multiple TLM structures on a-plane and c-plane samples were characterized after processing was completed. The specific contact resistance of the n-type ohmic contact could not be determined exactly, because no p-well was used in this study. Consequently, the discussion focuses on the p-type ohmic contact, which is generally reported to be more challenging to form [11] and showed roughly 4 orders of magnitude higher specific contact resistance compared to n-type ohmic contacts. The contribution of the n-type contact resistance is, therefore, assumed to be negligible for the subsequent analysis.

Raw data from the I-V measurements of a p-type contact is presented in Fig. 1 (middle) for both investigated substrates. The I-V characteristics indicate that a perfectly ohmic behavior was not achieved in either case, still symmetric conductivity for positive and negative voltages is observed. Nonetheless, the evaluated specific contact resistances for a-plane ( C−V ) and c-plane ( C−V ) show no significant dependence on the substrate orientation. Thus, the process transfer to the a-plane substrate was successful. However, further optimization potential like utilization of different contact materials for each contact [8] remains.

Thermal Oxidation. Due to different oxidation rates especially in the reaction limited regime [9, 10] different processing times for a-plane and c-plane were chosen as stated in the methodology section. The resulting layer thicknesses were optically measured to be 50.1 nm (a-plane) and 53.1 nm (c-plane). Since not only physical layer thickness but mainly electrical properties are relevant, I-V and C-V measurements were carried out on multiple N∘1 by <0.1μ A/cm2 large vertical MOS capacitors on the epitaxial layer of each sample. From the 5MV/cm measurements at 100 kHz , the key parameters shown in Table 2 are evaluated.

Table 2. Evaluated key parameters of the 12μ m measurements for the different substrates.

Parameter | a-plane | c-plane
Eval. Oxide Thickness (nm) | 51.1 ± 0.4 | 55.1 ± 0.3
Oxide Capacitance (pF) | 27.0 ± 0.2 | 25.1 ± 0.1
Interface State Density (1/cm²eV)¹⁾ | 9.5 · 10¹¹ ± 0.6 · 10¹¹ | 8.8 · 10¹¹ ± 2.1 · 10¹¹

The evaluated oxide thickness matches the optically measured one within a deviation of below 2 nm . Since the thickness is evaluated using the oxide capacitance and the dielectric constant, the growth of an oxide with appropriate dielectric constant is confirmed. Deviations might be due to slight size variations of the MOS capacitor from the wet chemical etching of the electrode. The interface state density evaluated using the Terman method [12] shows higher concentration for the investigated a-plane samples. This might be explained by the shorter NO annealing time for these samples to avoid extensive layer growth while annealing. In the future, distinct processes for annealing of a-plane samples should be investigated to further reduce the interface state density.

From the I-V characterization, the breakdown behavior of the oxides is evaluated, as shown in Fig. 1 (right). The breakdown field of the oxides is comparable for most processed wafers and in line with the literature values for thermal silicon oxides (e.g. [13, 14]). The lower breakdown field of a-plane sample a- 1μ m, thus, is not related to the crystal orientation but likely stems from issues with subsequent wet chemical structuring of the polycrystalline silicon used as gate electrode for the MOS capacitors. As shown in the inset the leakage current density remains negligibly ( 3μ m ) small for electric fields up to 2μ m corresponding to roughly 25 V for the given oxide thickness.

Based on the results, the transfer of thermal oxidation process was successful but leaves room for improvement. In particular the post oxidation annealing process might further reduce the interface state density for a-plane samples. Nevertheless, the manufactured oxides with low leakage current and high dielectric breakdown are suitable as gate oxides for pMOS transistors.

Electrical Properties of the Manufactured pMOS Transistors

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Device Design. For demonstration of CMOS-compatibility of the process, standard pMOS field effect transistors were manufactured. The source and drain areas are highly doped p-type regions and the channel is formed by the n-type doping of the epitaxial layer, as shown in Fig. 2 (left). Using the ohmic contacts and metal layers, the source was shorted with the body potential, as can be seen in Fig. 2 (right). The width of the channel ( W ) is VTh and the length ( L ) varies from −VTh  to VTh. The gate overlaps slightly with the source and drain areas to compensate for misalignment during lithography, thus preventing channel pinch off. The structure is encapsulated using a multi-layer insulation and passivation.

[picture]

Fig. 2. Schematic cross section (left) and top view (right) of the manufactured pMOS transistors on c-plane and a-plane wafers. In the top view overlying metal layers are shown semi-transparent, and insulation layers are omitted for better visibility of the underlying structures.

Fig. 2. Schematic cross section (left) and top view (right) of the manufactured pMOS transistors on c-plane and a-plane wafers. In the top view overlying metal layers are shown semi-transparent, and insulation layers are omitted for better visibility of the underlying structures.

Electrical Measurements. For statistical characterization, output and transfer characteristics of the fabricated devices were measured with a semi-automatic probing station using a Keithley SCS4200 SMU. Transfer characteristics were recorded from 0 V to -20 V in -0.1 V steps at a drain voltage of -1 V . Output characteristics were measured from 0 V to -10 V in -0.1 V steps at gate voltage from 0 V to -15 V in -1 V steps.

Electrical Properties. Exemplary representative I-V characteristics for an a-plane and a c-plane device with a channel length of VTh  are shown in Fig. 3. The devices on both substrates are functional and clearly show an on and an off state. As can be seen in the transfer characteristics (left) the devices on a-plane substrates have a significantly lower threshold voltage ( 2μ m ) of -12 V compared to -7.1 V for c-plane samples. This is at least partwise explainable by the higher doping of the epitaxial layer of the a-plane samples (see Table 3 - top row) as well as their increased interface state density as discussed in the previous section.

[picture]

Fig. 3. Transfer characteristics (left) and output characteristics (middle) of representative pMOS transistors with a channel width of SiC/SiO2 and a length of n+. Inset: zoomed view of the linear region of the output characteristic. Right: representative characteristics of the mobility as function of the p+ corrected gate voltage.

Fig. 3. Transfer characteristics (left) and output characteristics (middle) of representative pMOS transistors with a channel width of S i C / S i O 2 and a length of n + . Inset: zoomed view of the linear region of the output characteristic. Right: representative characteristics of the mobility as function of the p + corrected gate voltage.

In the output characteristics (Fig. 3 middle) an extended influence of short-channel effects (drain induced barrier lowering ∅56μ m decreases and current increases with rising drain voltage [15]) on the c-plane samples can be seen. This is due to the lower doping of the epitaxial layer leading to stronger influence of the applied drain voltage compared to the a-plane devices. This effect gets stronger for shorter channel length (not shown). The inset in the output characteristics shows the not ideal ohmic behavior of the metal contacts on the p-type areas in the linear region of the pMOS.

Calculating the mobility dependance of the applied gate voltage (compensated for the 58μ m differences) gives the characteristics shown in Fig. 3 (right). As can be seen, the characteristic for a-plane is similar to c-plane. The slightly lower maximum mobility on a-plane samples compared to c-plane samples is likely due to the higher interface state density as discussed for the p+n+ variation. Due to these results and as stated before a post oxidation annealing which is distinctly tailored for a-plane interfaces should be investigated.

The evaluated characteristics for all measured a-plane and c-plane pMOS transistors with a channel length of 4H−SiC with their standard deviation are summarized in Table 3. As can be seen the transfer of the CMOS process to a-plane wafers was successful, thus enabling manufacturing of more complex devices and circuits on a-plane wafers. Process optimization especially for the Ion /Ioff  interface is needed to move the threshold voltage closer to 0 V and increase the carrier mobility.

Table 3. Evaluated key parameters and standard deviation of all pMOS transistors with channel width of n+− and length of p+.

Parameter | a-plane | c-plane
Channel Doping (10¹⁵/cm³) [3] | 8.9 ± 0.1 | 1.2 ± 0.1
IOn / IOff | 2.42 · 10⁶ ± 0.04 · 10⁶ | 2.48 · 10⁶ ± 0.69 · 10⁶
Threshold Voltage (V)¹⁾ | -12.0 ± 0.1 | -7.10 ± 0.6
Maximum Mobility (cm²/Vs) | 2.32 ± 0.14 | 2.84 ± 0.43
ROn @ |VG − VTh| = 3 V (kΩ) | 388 ± 7 | 321 ± 68

Electrical and Optical Properties of the Manufactured Tunneling Diodes

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Device Design. The light emitters are designed as circular devices. To achieve high tunneling currents with a broad radiative recombination spectrum the 500∘C- and 4H−SiC-implanted areas are designed as overlapping circles ( 500∘C to 6H−SiC ) represented in violet in Fig. 4. Since donors as well as acceptors are present in this region trap assisted tunneling with radiative recombination can take place. Both areas are contacted using ohmic contacts and the metal layer stack. To route the inner contact region to the contact pad the outer p-type implanted area and ohmic contacts are interrupted.

[picture]

Fig. 4. Schematic cross section (left) and top view (right) of the manufactured tunneling diode on c-plane and a-plane wafers. In the top view the overlying metal layers are shown semi-transparent, and the insulation layers are omitted for better visibility of the underlying structures.

Fig. 4. Schematic cross section (left) and top view (right) of the manufactured tunneling diode on c-plane and a-plane wafers. In the top view the overlying metal layers are shown semi-transparent, and the insulation layers are omitted for better visibility of the underlying structures.

Electrical and Optical Measurements. For electrical characterization at room temperature I-V measurements were carried out in a range from 5 V to -30 V in 0.1 V steps with a semi-automatic probing station using a Keithley SCS-4200. For cryogenic measurements the device was cooled using an attodry800 closed-cycle cryostat and a HP4145B semiconductor analyzer. For these measurements the range was changed to 10 V to -80 V with the current being limited to 10 mA in reverse mode to avoid extensive heating. Emission spectra in forward and reverse bias were recorded at 300 K using a Zeiss MCS CCD UV-NIR spectrometer with a glass fiber positioned closely above the device.

Electrical Properties at Room Temperature. In Fig. 5 (left) exemplary representative I-V characteristics of an a-plane and c-plane tunneling diode are shown. As can be seen, both diodes show diode-like behavior in forward bias, confirming the successful process transfer from c-plane to a-plane substrates. In reverse bias, both devices show a significant tunneling current originating from trap-assisted tunneling of charge carriers in the 4H−region. This current is not a leakage current, as pin-diodes manufactured in the same process without overlapping doped regions show blocking

[picture]

Fig. 5. Left: comparison of the I-V characteristics of the a-plane and c-plane tunneling didoes at room temperature. Right: electroluminescence emission spectra in forward (LED mode) and reverse biasing (tunneling mode) for the a-plane and c-plane tunneling diodes.

Fig. 5. Left: comparison of the I-V characteristics of the a-plane and c-plane tunneling didoes at room temperature. Right: electroluminescence emission spectra in forward (LED mode) and reverse biasing (tunneling mode) for the a-plane and c-plane tunneling diodes.

behavior for these applied voltages [18]. Increasing the reverse voltage further, increases the current and in turn also the light emission. In the region marked with the green circle, the emission becomes visible by human eye and the spectral analysis of the emitted light was carried out.

Electroluminescent Behavior at Room Temperature. Electroluminescence spectra, as shown in Fig. 5 (right), were recorded under both forward and reverse bias conditions, revealing distinct emission characteristics for the two operating modes. Under forward bias, the devices operate in an LED-like regime, exhibiting a sharp emission peak at a wavelength corresponding to the bandgap energy, accompanied by additional defect-related emission at longer wavelengths [19].

In reverse bias, the emission originates predominantly from tunneling-assisted radiative recombination between donor and acceptor states in the co-implanted region. As donors and acceptors cannot occupy the same lattice site, tunneling is facilitated by the presence of an electric field and the resulting band bending. The emitted spectrum in this regime is broad, reflecting the variation in energetic separation between donor and acceptor levels, which depends on the spatial distance between individual donor-acceptor pairs in the biased device [20]. The small deviations in the local maxima and minima of the spectra of a-plane and c-plane samples are attributed to interference effects caused by the slightly different thicknesses of the overlying passivation layers.

As highlighted in the green box in Figure 5 (right), a significant portion of emission was also observed from 730 nm to 785 nm , which is the range used for off-resonant excitation of the Vsi defect, thus making these devices a promising co-integrated light source.

Electrical Properties at Cryogenic Temperatures. As can be seen in Fig. 6, the devices remain operational at reduced temperatures down to 4 K . Light emission is still visible to the human eye, similar to operation at room temperature.

[picture]

Fig. 6. I-V characteristics of the a-plane tunneling diode for different measurement temperatures. Note the different x -axis scaling for forward (LED mode) and reverse (tunneling mode) voltages. In reverse bias the current was limited to 10 mA to avoid extensive heating.

Fig. 6. I-V characteristics of the a-plane tunneling diode for different measurement temperatures. Note the different x -axis scaling for forward (LED mode) and reverse (tunneling mode) voltages. In reverse bias the current was limited to 10 mA to avoid extensive heating.

Under forward bias, the onset behavior changes markedly due to carrier freeze-out at low temperatures. In this regime, charge carriers must first be ionized by free carriers accelerated by the applied electric field [21] before contributing to conduction. This process is analogous to avalanche breakdown, but it requires significantly smaller fields because the energy difference between the dopant levels and their corresponding bands is relatively small. As the temperature decreases, a greater field energy is required for carrier activation, resulting in a higher voltage threshold for the re-ionization process. Once re-ionization occurs, the current rapidly transitions to the diode behavior as observed at room temperature. This transition is not associated with a heating effect; thermal effects occur on a different timescale and were investigated separately (not shown). Notably, the power levels at which this field-assisted re-ionization sets in are much lower than those associated with thermal effects.

In reverse bias, higher electric fields are necessary to achieve the same tunneling current as at room temperature, consistent with rising bandgap and thus breakdown voltage of the device at cryogenic temperatures [22].

Summary

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CMOS-compatible fabrication processes, including ion implantation, thermal oxidation, and contact formation, were successfully transferred from c-plane to a-plane 4H−SiC wafers. pMOS transistors produced on a-plane wafers exhibited comparable mathematical formula ratios and mobilities to c-plane devices, with a threshold voltage shift from -7.1 V to -12 V . Tunneling diodes fabricated on the a-plane wafers emitted broadband light with a substantial spectral component suitable for off-resonant excitation of silicon vacancy centers. This emission remained stable at cryogenic temperatures.

Author Contribution Statement

The original version of this paper is available on https://www.scientific.net/KEM.1056.7.pdf

Jannik H. Schwarberg: Conceptualization, Methodology, Formal Analysis, Investigation, Visualization, Writing - Original Draft; Jan Dick: Conceptualization, Methodology, Investigation; Alexander May: Investigation, Pawel Michałowski: Investigation; Validation; Birgit Kallinger: Investigation; Robert Kammel: Formal Analysis; Mathias Rommel: Writing - Review & Editing, Supervision; Jörg Schulze: Supervision, Funding Acquisition

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The original version of this paper is available on https://www.scientific.net/KEM.1056.7.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Evaluated using Second-Derivative method [16] with slight smoothing according to [17]

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 17-25

doi: 10.4028/p-e4cgTB

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-05

Revised:
2025-12-18

Accepted:
2026-02-23

Online:
2026-05-20

Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

The original version of this paper is available on https://www.scientific.net/KEM.1056.17.pdf

Jannik H. Schwarberg 1,a*, Christian Gobert 2, b, Fedor Hrunski 4,c, Alexander May 2, d, Wolfgang Knolle 3,e, Birgit Kallinger 2,f, Fabian Schmid 1, g, Mathias Rommel 2, h and Jörg Schulze 1,2,i

1 Friedrich-Alexander-Universität Erlangen-Nürnberg, Chair of Electron Devices, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer IISB, Schottkystraße 10, 91058 Erlangen, Germany

3 Leibniz-Institut für Oberflächenmodifizierung, Permoserstraße 15, 04318 Leipzig, Germany

4 FAU Erlangen-Nürnberg, Institute of Applied Quantum Technologies, Konrad-Zuse-Straße 3-5, 91052 Erlangen, Germany

a  jannik.schwarberg@fau.de, b  christian.gobert@iisb.fraunhofer.de, cfedor.hrunski@fau.de, dalexander.may@iisb.fraunhofer.de, e  wolfgang.knolle@iom-leipzig.de, 

f  birgit.kallinger@iisb.fraunhofer.de, 9fabian.f.schmid@fau.de, h  mathias.rommel@iisb.fraunhofer.de,  ijoerg.schulze@iisb.fraunhofer.de

Abstract

Precise control of optical transitions of color centers like silicon vacancies ( VSi ) in 4H−SiC is essential for their functionalization. An applied electric field ( E→‖c→ ) of a pin-diode can be used to tune the optical properties of VSi centers via the Stark effect, while the associated space charge region under bias suppresses spectral diffusion. Unlike commonly used 4H−SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes and resonant laser excitation of the Vsi perpendicular to the wafer surface ( c→⟂a→ ). In this work non-circular lateral pin-diodes oriented perpendicular to the wafer flat were produced in a scalable, CMOS-compatible process. Electrical characterization revealed that 97% of the devices on an a-plane wafer with n-type epitaxial layer were functional, exhibiting breakdown voltages exceeding 200 V and reverse currents below 100pA/μm, enabling low current noise during optical measurements. The diodes remained operational at cryogenic temperatures after frozen-out charge carriers were re-ionized by the applied electric field. Electron irradiation followed by thermal annealing at 600∘C was used to generate V2 silicon vacancies in the intrinsic region without significantly altering the electrical characteristics. Optically detected magnetic resonance (ODMR) measurements on selected single emitters confirmed the presence of V2 centers by detecting a contrast at 70 MHz , while cryogenic photoluminescence (PL) spectra revealed a zero-phonon line (ZPL) peak at 916 nm .

Keywords: 4H−SiC a-Plane, Silicon Vacancy, Lateral pin-Diode, Scalability, Stark Tuning, CMOS

Introduction

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Color centers such as silicon vacancies ( Vssi ) in 4H−SiC crystals are promising candidates for quantum sensing, communication and computing applications [1-5]. Electric fields of pin-diodes ( E→‖c→ ) have been shown to reduce spectral diffusion and tune the resonant excitation and emission of Vsi [5, 6]. This is interesting for the measurement of local physical properties like the electric field inside of a semiconductor device [5], thus allowing for device optimization. Moreover, for possible quantum computing applications the photons emitted by different VSi must be indistinguishable [1]. To compensate for variances in the local environment, and thus the resonant excitation and emission wavelength [7], the electric field can be used to shift the optical transitions [5,6] to either allow or prohibit optical interaction between multiple VSi.

Unlike commonly used 4H-SiC c-plane wafers, a-plane wafers allow a scalable fabrication of lateral pin-diodes (E→‖c→) in a CMOS compatible process with convenient access to resonant excitation perpendicular to the Vsi dipole moment, which aligns with the c -axis [7]. This allows laser excitation of the VSi perpendicular to the wafer surface ( c→⟂a→ ) and in-plane excitation using a waveguide aligned to the m -axis (m→⟂a→), supporting high scalability and co-integration of advanced electronics and photonics, which is a key step towards quantum photonic integrated circuits (QPICs) [1].

This work demonstrates scalable production of lateral pin-diodes with a CMOS-compatible process on 4H−SiC a-plane wafers. These pin-diodes are electrically and optically characterized at room temperatures and at cryogenic temperatures to investigate their usability in respect to the quantum sensing and computing applications.

Methodology

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Device Design. For the design of the pin-diodes in the intended application, boundary conditions differ from those in standard power electronics, as discussed in the introduction. Key factors include the electric field orientation, high blocking capability with low leakage currents [5], and parameters influencing the optical properties of the color centers. The following design considerations refer to the lateral pin-diodes fabricated on a-plane wafers. The devices on c-plane wafers, sharing identical designs, serve as reference devices purely with respect to electrical characterization.

To achieve the required electric field orientation along the c -axis, unidirectional lateral pin-diodes were fabricated, oriented perpendicular to the wafer flat. Slightly rotated variants were included to compensate for possible crystal orientation deviations from wafer manufacturing. To minimize spectral diffusion, local electrical inhomogeneities and crystal damage, color centers were incorporated into a lowly n-type doped epitaxial layer. Consequently, ion implantations in this region for adjusting series resistance or breakdown field strength were omitted.

Leakage currents, particularly along the passivation interface, are reduced by using a high-quality oxide. Combined with the feature resolution and alignment constraints of the CMOS process, these considerations yield the devices schematically shown in Fig. 1.

[picture]

Fig. 1. Schematical cross section (left) and top view (right) of the manufactured lateral pin-diodes on a-plane and c-plane wafers. In the top view the overlying metal layers are shown semitransparent, and the insulation layers are omitted for better visibility of the underlying structures.

Fig. 1. Schematical cross section (left) and top view (right) of the manufactured lateral pin-diodes on a-plane and c-plane wafers. In the top view the overlying metal layers are shown semitransparent, and the insulation layers are omitted for better visibility of the underlying structures.

Additionally, diode dimensions as shown in Fig. 1 (right) were varied to study scalability limits and breakdown behavior. Lengths (L) ranged from 1μ m to 20μ m, and widths (W) from 3μ m to 50μ m. The nomenclature "W10L20" denotes a diode with a width of 10μ m and a length of 20μ m.

Sample Fabrication. The devices were fabricated using a CMOS-compatible process [8] on 35 mm on-axis 4H-SiC a-plane substrates. For reference, identical devices were also produced on 150 mm c-plane wafers with a 4∘ off-cut. On both substrate types, 10μ m-thick n-type epitaxial layers were grown [9]. An overview of the substrates and their parameters is given in Table 1.

Table 1. Overview of the manufactured samples and their key parameters.

Sample Name | Wafer Orientation | Epitaxial Layer Doping (cm⁻³)
a-plane n-type | 11̄20 | 8.9 · 10¹⁵
a-plane i-type | 11̄20 | 2.4 · 10¹³
c-plane n-type | 0001 | 1.2 · 10¹⁵
c-plane i-type | 0001 | 3.4 · 10¹²

To suppress channeling, a 30 nm scattering oxide was deposited prior to ion implantation. Aluminum and nitrogen ion implantations were employed to form the highly doped p-type and n-type regions. Dopant activation was carried out by annealing at 1700∘C in an argon atmosphere using a carbon capping layer to mitigate carbon vacancy formation. The gate oxide was grown by dry thermal oxidation at 880 mbar and 1300∘C, followed by annealing in nitric oxide (NO). Due to different oxidation rates for a-plane and c-plane [9, 10], oxidation times were 6 min 30 s for a-plane and 33 min for c-plane substrates. The NO annealing time for a-plane devices was reduced to 30 min compared to 60 min for c-plane.

After deposition of an additional insulating layer, contact areas were defined by dry etching of the contact holes, followed by self-aligned deposition of a 70 nm thick nickel- 2.6wt% aluminum ( NiAl ) layer. This layer was patterned by lift-off, and ohmic contacts were formed by rapid thermal processing at 980∘C for 2 min . Residual NiAl was removed using Caro's acid. A stack of 40 nm Ti /400 nmPt/40 nm Ti was deposited for metallization. Finally, a SiO2/Si3 N4/SiO2 layer stack was deposited and patterned by dry etching to passivate the devices against environmental exposure.

After full processing Vsi were generated by electron irradiation with an energy of roughly 2 MeV and a dose of 3·1012 cm−2 with subsequent annealing at 600∘C in vacuum for 30 min .

Electrical Measurements. Statistical room temperature I-V characterization was carried out by a semi-automatic probing station using a Keithley SCS-4200 SMU. The pin-diodes were measured in multiple measurements to have a high resolution in forward mode and a large measurement range in blocking mode of the device. In forward mode, the devices were measured from 10 V to -2 V in 50 mV steps. To investigate the current in blocking mode voltages up to -200 V with 0.5 V steps were applied. Finally, for characterization of the breakdown behavior up to -420 V were applied. For room temperature measurements, multiple chips with different design variations totaling to at least 300 pin-diodes on each wafer were investigated. Selected chips were also characterized after the electron irradiation and after the annealing step at 600∘C.

Furthermore, to investigate the electrical behavior at 4 K , selected devices were wire-bonded using 50μ m aluminum wire and characterized at various temperatures in an AttoDry800 closed-cycle cryostat. Due to limitations of the measurement setup blocking voltages of only up to -100 V can be applied.

Optical Measurements. Photoluminescence (PL) characterization was performed using a commercially available confocal PL setup developed by SQUTEC. Excitation was provided by a 730 nm laser operated at a power of 0.1 mW . The laser was focused onto the sample using a 100x Zeiss objective with a numerical aperture of 0.9 and a working distance of 1 mm . To suppress backreflected excitation light, the emitted PL signal was spectrally filtered using a dichroic mirror with a nominal cutoff at 875 nm , in combination with an 800 nm long-pass filter. The filtered light was coupled into an optical fiber and directed to a superconducting nanowire single-photon detector (SNSPD), read out using a Swabian Instruments Time Tagger 20.

PL xy-scans were conducted with a pixel scan rate of 30 Hz and a pixel spacing of roughly 100 nm . For cryogenic spectral measurements, the sample was cooled to 4 K using an AttoDry 800 closedcycle cryostat. Spectra were recorded using an Ocean Optics QEPro-XR300 spectrometer. ODMR measurements at room temperature were carried out at a similar home-built setup.

Statistical Electrical Characterization at Room Temperature

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Production Yield. After process completion, the wafer first was examined by optical microscope. An overview of a 35 mm a-plane wafer is shown in Fig. 2 (left), demonstrating a scalable process. The yield of the pin-diodes was determined using three criteria which had to be met simultaneously:
1.) Forward mode: current at 0.25 V lower than 1·10−10 A
2.) Forward mode: current at 3 V higher than 1·10−8 A
3.) Blocking mode: current at -50 V lower than 1·10−10 A

For both samples with n-type epitaxial layer the yield reaches as high as 97% (a-plane) or 99% (c-plane). For sample a-plane i-type, a reduced yield of only 23% is observed. This is due to a misalignment of the p-type ohmic contact, which leads to elevated currents in blocking mode on most of the chips, thus failing the third criteria for a working device. Moreover, the yield is reduced to 87% on sample c-plane i-type due to irregularities of the doping of the epitaxial layer in the outer regions.

Besides these effects, nearly all devices are functional and devices with the same design show comparable electrical behavior except some processing-related small variations as exemplarily shown for the diode W20L20 on sample a-plane n-type in Fig. 2 (middle).

[picture]

Fig. 2. Left: microscope image of a fully processed a-plane wafer showing a wide variety of integrated devices. Middle: I-V characteristics of all measured identically designed W10L20 pindiodes on sample a-plane n-type. Right: comparison of I-V characteristics of representative pindiodes from different samples. Note the different scaling of the x -axis for forward and reverse characteristic. Currents normalized on device width.

Fig. 2. Left: microscope image of a fully processed a-plane wafer showing a wide variety of integrated devices. Middle: I-V characteristics of all measured identically designed W10L20 pindiodes on sample a-plane n-type. Right: comparison of I-V characteristics of representative pindiodes from different samples. Note the different scaling of the x -axis for forward and reverse characteristic. Currents normalized on device width.

Evaluation of Key Parameters. A comparison of the I-V characteristics of the W10L20 pindiodes fabricated on different substrates is shown in Fig. 2 (right). In forward bias, the turn-on behavior was comparable for all devices, with only slight variations in the slope near turn-on. At higher forward voltages, however, the devices exhibited pronounced differences in current magnitude. In reverse bias, the behavior was largely similar, with the measured current limited by the accuracy of the measurement setup.

From these measurements, the characteristic parameters of the diodes were extracted and are summarized in Table 2. As expected, statistically significant differences were found in the ideality factor, and particularly the series resistance. Notably, the series resistance differed substantially between the n-type and i-type samples. The main distinguishing factor between the diodes is the doping concentration of the epitaxial layer, which will be further examined through analysis of the design variations. Note that rotating the devices relative to the flat of the wafer had negligible influence on the electrical properties.

Table 2. Evaluated series resistance and ideality factor from the I-V measurements of all measured W10L20 pin-diodes at room temperature for all substrate types.

Sample Name | Series Resistance (Ω) | Ideality Factor
a-plane n-type | 521 ± 42 | 1.81 ± 0.02
a-plane i-type¹⁾ | 27511 | 2.24
c-plane n-type | 1785 ± 45 | 2.22 ± 0.06
c-plane i-type | 15056 ± 2385 | 1.95 ± 0.10

Influence of Device Design on Breakdown Voltage. As Sentaurus technology computer-aided design simulations (not shown) revealed, breakdown in the investigated devices occurs near the surface, specifically at the corner of the p-type implanted region. Due to the small curvature radius at this location, strong electric-field crowding arises. As discussed in the device design section, no countermeasures were implemented to reduce this effect, as the design was optimized for quantum applications. Breakdown voltages were analyzed as a function of epitaxial layer doping and the length of the intrinsic region, as shown in Fig. 3 (left).

[picture]

Fig. 3. Left: evaluated breakdown voltages in dependence of the length L of the low doped region. Middle: dependence of the series resistance on the inverse width of the p-type ohmic contact of the n-type L1 samples. Right: dependence of the series resistance on the length of the drift region for the i-type W50 samples. The dashed lines are linear fits (y=m·x+b) to the data points. Their corresponding parameters and coefficient of determination ( R2 ) are given.

Fig. 3. Left: evaluated breakdown voltages in dependence of the length L of the low doped region. Middle: dependence of the series resistance on the inverse width of the p-type ohmic contact of the n-type L1 samples. Right: dependence of the series resistance on the length of the drift region for the i-type W50 samples. The dashed lines are linear fits ( y = m · x + b ) to the data points. Their corresponding parameters and coefficient of determination ( R 2 ) are given.

Device breakdown occurs when the local electric field at the p+/i-interface reaches the material's critical breakdown field. For the present 2D lateral geometry, the breakdown voltage ( VBD ) can be approximated as the integral over the course of the electric field E along the device axis [11]:

VBD=∫0LE·dl(1)

This implies that the expansion of the electric field into the highly doped areas is negligibly small compared to L. From Poisson's equation:

∇E=q·NDε0·εr(2)

in the low-doped i-region, the electric-field gradient is directly proportional to the doping concentration ND. Here, q is the elemental charge, ε0 the vacuum permittivity and εr the specific permittivity of 4H−SiC.
Two trends are observed:

Dependence on intrinsic region length: Increasing L of the pin-diode increases the area below the course of the electric field and thus VBD, until a saturation point is reached where the electric field has decayed to near zero before the depletion region reaches the n+contact. This corresponds to a non-punch-through condition in pin-diodes, where breakdown is governed entirely by the high-field p+/i-junction.

Dependence on doping: Higher doping increases the field gradient, causing the field to decay more rapidly along the depletion path, thereby reducing VBD.

Series Resistance in Forward Bias. The total series resistance R s can be expressed as:

RS=Rmetal +Rn− ohm +Rn++Rdrift +Rp++Rp− ohm (3)

Test structures (transfer length method structures and resistance meanders) confirmed that Rmetal ,Rn+, and Rn-ohm  are negligibly small. The dominant terms differ between n -type and i -type devices. For n-type, Rs scales with the width of the ohmic contact, as can be seen in Fig. 3 (middle). The influence of the p-doped-region width is comparatively low and results in a significantly poorer fit (not shown). Still, the deviations from the shown fit can be phenomenologically attributed to the contribution of the p-type implanted region, which was also qualitatively verified but is not shown here.

As shown in Fig. 3 (right), for i-type, RS is primarily determined by the intrinsic region length. L1 diodes were excluded from fitting due to excessive uncertainty caused by lithographic misalignment. In forward bias, the low-doped region is flooded with carriers, and the excess carrier concentration Δn(x) decays exponentially with distance according to:

Δn(x)∝e(−x(Dn·τn))(4)

where Dn is the diffusion constant and τn is the carrier lifetime [11]. Analog considerations can be made for holes. The short lifetime expected from the lateral geometry and increased interface recombination reduces the diffusion length, leaving a non-flooded region in longer i-type regions where conduction is limited by the background doping ND. Consequently, the fit for the c-plane sample (lower doping) shows a higher slope compared to the a-plane sample (higher doping).

Electrical behavior at Cryogenic Temperatures

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Modulation of the Onset-Voltage. At cryogenic temperatures, the aluminum acceptors and the nitrogen donors of 4H−SiC are largely not ionized due to their ionization energies of approximately 200 meV and 60 meV [12], respectively. Under small forward bias, the free carrier concentration is too small to support significant injection, and the diode current remains strongly suppressed, as can be seen in Fig. 4 (blue curves). When the electric field in the depletion region reaches a critical value, however, an abrupt increase in current is observed.

[picture]

Fig. 4. I-V characteristics of an a-plane lateral pin-diode for different measurement temperatures. Note the different x -axis scaling for forward and reverse bias.

Fig. 4. I-V characteristics of an a-plane lateral pin-diode for different measurement temperatures. Note the different x -axis scaling for forward and reverse bias.

This threshold behavior originates from field-assisted ionization of the frozen-out acceptors [13]. The applied electric field reduces the Coulombic binding potential via the Poole-Frenkel effect [11], lowering the effective ionization energy. In parallel, the few free carriers present are accelerated by the electric field, forming a non-equilibrium hot-carrier distribution with an effective temperature well above the lattice temperature. These hot carriers can transfer part of their kinetic energy to bound carriers in inelastic collisions, thereby ionizing them. Once released, these carriers are also
accelerated by the field, enabling them to activate further bound carriers. This positive feedback leads to an avalanche-like multiplication of free carriers once the field exceeds the critical threshold [13].

At elevated temperatures the onset voltage is shown to decrease. This is due to two reasons. On one hand, a larger fraction of dopants is already ionized at higher temperatures. On the other hand, with increasing temperature, thermal activation increasingly contributes to dopant ionization, thus lowering the barrier that must be overcome.

Conductivity in Forward Mode. As discussed in the previous chapter, the series resistance is strongly influenced by the resistance of the neutral drift region. The conductivity σ of this region where mainly electrons are present can be expressed as:

σ=q·n·μ (for electrons) (5)

where q is the elementary charge, n is the free carrier concentration, and μ is their mobility [11]. The temperature dependence of RS follows directly from the competing effects of carrier activation and carrier scattering:

Low temperatures: The free carrier concentration n is reduced due to incomplete dopant ionization, resulting in lower σ and thus higher RS.

Intermediate temperatures: All dopants are ionized, maximizing n, while phonon scattering is still low. Mobility μ is therefore high, leading to a minimum in RS.

High temperatures: While n remains constant (all dopants ionized), μ decreases due to increased lattice (phonon) scattering. At high T, the mobility approximately follows [11]:

μ∝T−32

Consequently, σ decreases, Rs increases, and the on-current decreases again.

Implementation of Silicon Vacancies and Optical Characterization

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Influence of Irradiation and Annealing on Device Performance. In Fig. 5 (left) exemplary I-V characteristics of a selected pin-diode after processing (reference), after electron irradiation and after the 600∘C anneal in vacuum are shown. As can be seen, the device performance degrades slightly by showing increased reverse currents at high blocking voltages. Moreover, after annealing the device shows extended recombination in low forward biasing due to introduced electrically active defects in the space charge region. Furthermore, the series resistance is slightly reduced after annealing, probably due to alterations in the ohmic contacts. These effects apply to many examined devices and are differently pronounced. This degradation should not strongly influence the usability of the devices for the intended quantum applications.

[picture]

Fig. 5. Left: I-V characteristics of an a-plane lateral pin-diode from sample a-plane i-type after processing, electron irradiation and 600∘C annealing in vacuum. Note the different x -axis scaling for forward and reverse bias. Middle: PL scan of the a-plane n-type pin-diode with generated color centers. The different areas of the pin-diode are marked for visibility. Right: exemplary room temperature ODMR scan and 4 K emission spectrum of selected single V2 center.

Fig. 5. Left: I-V characteristics of an a-plane lateral pin-diode from sample a-plane i-type after processing, electron irradiation and 600 ∘ C annealing in vacuum. Note the different x -axis scaling for forward and reverse bias. Middle: PL scan of the a-plane n-type pin-diode with generated color centers. The different areas of the pin-diode are marked for visibility. Right: exemplary room temperature ODMR scan and 4 K emission spectrum of selected single V2 center.

Optical Photoluminescence Characterization. The PL scans recorded after annealing show strong influence of the processing steps on background PL noise. The different device regions (compare Fig. 1 - right) are clearly visible in Fig. 5 (middle). Nevertheless, in the intrinsic region of the pin-diode bright spots are observed, which are shown to be single emitters (not shown). ODMR measurements on selected single emitters at room temperature reveal an ODMR contrast at roughly 70 MHz (Fig. 5 right-top). PL spectra recorded at 4 K show a zero-phonon line (ZPL) at 916 nm (Fig. 5 right-bottom). These are characteristic for V2 silicon vacancies [5], thus confirming the successful generation of the desired color centers in this region. These color centers are located in the region of the pin-diode, where the electric field can be varied with the applied voltage to tune the optical properties.

Summary

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Lateral pin-diodes on 4H-SiC a-plane wafers were successfully fabricated in a CMOS-compatible, scalable process with a device yield of 97%. The structures on the differently doped epitaxial a-plane layers demonstrated breakdown voltages above 200 V (a-plane n-type) and 350 V (a-plane i-type) and low reverse leakage currents ( <100pA/μm ). The devices maintain functionality at cryogenic temperatures after re-ionization of the frozen-out dopants by the electric field. Post-fabrication electron irradiation and annealing generated single V2 silicon vacancies in the intrinsic region without significantly degrading device performance. ODMR and cryogenic PL measurements on selected single emitters confirmed the presence of V2 centers, exhibiting an ODMR contrast at 70 MHz and a ZPL at 916 nm .

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1056.17.pdf

We would like to thank the whole cleanroom team at LEB & IISB for their extensive support in manufacturing of the samples. Furthermore, we would like to thank our colleagues for the fruitful discussions on various aspects of this research.

Author Contribution Statement

The original version of this paper is available on https://www.scientific.net/KEM.1056.17.pdf

Jannik H. Schwarberg: Conceptualization, Methodology, Formal Analysis, Investigation, Visualization, Writing - Original Draft; Mathias Rommel: Writing - Review & Editing, Supervision; Christian Gobert: Investigation; Wolfgang Knolle: Investigation; Fedor Hrunski: Investigation; Alexander May: Investigation, Validation; Birgit Kallinger: Investigation; Fabian Schmid: Resources; Jörg Schulze: Supervision, Funding Acquisition

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.17.pdf

G. Moody, V.J. Sorger, D.J. Blumenthal, et al., 2022 Roadmap on integrated quantum photonics, J. Phys. Photonics 4 (2022) 12501.

S.K. Parthasarathy, B. Kallinger, F. Kaiser, et al., Scalable quantum memory nodes using nuclear spins in Silicon Carbide, Phys. Rev. Applied 19 (2023) 11048.

N.T. Son, C.P. Anderson, A. Bourassa, et al., Developing silicon carbide for quantum spintronics, Appl. Phys. Lett. 116 (2020) 190501.

Y. Zhou, J. Tan, H. Hu, et al., Silicon carbide: A promising platform for scalable quantum networks, Applied Physics Reviews 12 (2025).

D. Scheller, F. Hrunski, J.H. Schwarberg, et al., Quantum-enhanced electric field mapping within semiconductor devices, Phys. Rev. Applied (2025).

C.P. Anderson, A. Bourassa, K.C. Miao, et al., Electrical and optical control of single spins integrated in scalable semiconductor devices, Science 366 (2019) 1225-1230.

R. Nagy, M. Niethammer, M. Widmann, et al., High-fidelity spin and optical control of single silicon-vacancy centres in silicon carbide, Nature communications 10 (2019) 1954.

A. May, M. Rommel, L. Baier, et al., A 4H-SiC CMOS Technology enabling Smart Sensor Integration and Circuit Operation above , in: 2024 Smart Systems Integration Conference and Exhibition (SSI), IEEE, 2024, pp. 1-5.

J.H. Schwarberg, R. Karhu, B. Kallinger, et al., Investigation of CMOS Single Process Steps on a-Plane Wafers for Quantum Applications, in: 2024 47th MIPRO ICT and Electronics Convention (MIPRO), IEEE, 2024, pp. 1566-1572.

D. Goto, Y. Hijikata, S. Yagi, H. Yaguchi, Differences in SiC thermal oxidation process between crystalline surface orientations observed by in-situ spectroscopic ellipsometry, Journal of Applied Physics 117 (2015).

S.M. Sze, Y. Li, K.K. Ng, Physik der Halbleiterbauelemente, Wiley-VCH GmbH, Weinheim, 2022.

T. Kimoto, J.A. Cooper, Fundamentals of silicon carbide technology: Growth, characterization, devices, and applications, Wiley, Singapore, 2014.

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Due to low yield no meaningful standard deviation can be calculated.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 27-32

doi: 10.4028/p-zW5TBc

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-20

Accepted:
2026-02-23

Online:
2026-05-20

4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

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Jan Frederik Dick 1,a*, Samuel Ultsch 1, b, Mathias Rommel 2,c and Jörg Schulze 1,2,d

¹Friedrich-Alexander-Universität Erlangen-Nürnberg, Chair of Electron Devices, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystraße 10, 91058 Erlangen, Germany

a* jan.dick@fau.de, b samuel.ultsch@fau.de, c mathias.rommel@iisb.fraunhofer.de, djoerg.schulze@fau.de

Keywords: light emitter, quantum tunneling, tunneling enhanced emission, light-source, offresonant excitation, silicon vacancy.

Abstract

We report a light emitter based on a 4H−SiC lateral Zener diode that is operated under reverse bias in the quantum tunneling regime. Wide bandwidth white light emission with a peak wavelength of 492 nm corresponding to the transition between the nitrogen donor state and the aluminum acceptor state and a full width half maximum breadth of 303 nm at room temperature is shown. The peak breadth can be attributed to the relative shift of the acceptor and donor levels in the high electric field within the space charge region under reverse bias. At the wavelength of 730 nm , which is commonly used for off-resonant excitation of silicon vacancy defects, the emitter achieves 43.1% of its peak intensity. The emitter shows no blue light peak corresponding to the transition between the donor level of nitrogen and the valence band at 391 nm , such as the LED spectrum under forward bias of the same diode does.

Introduction

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Recent advances in color-center technology show promising results towards room-temperature sensor applications using the silicon vacancy in 4H−SiC(VSi)[1]. For widespread use of this technology, it would be favorable to monolithically integrate all components for initialization and read-out of the Vsi. 4H-SiC offers the possibility of a complete CMOS process integration [2], as well as the integration of wave guides and other optical components for light transmission [3]. This is instrumental for the direct optical read-out [4] and the monolithic integration of VSi in a sensor chip. Furthermore, for the true monolithic integration of such sensors, an integrated light source is needed for the excitation of the VSi, which poses challenges due to the wide and indirect bandgap of 4H−SiC [5]. For this purpose, we propose a lateral 4H−SiC tunneling diode as light emitter for VSi excitation, which shows white light in Zener breakdown containing the wavelength necessary for off-resonant excitation at 730 nm [6, 7], which is fabricated using a subset of a 4 H -SiC CMOS process.

Experimental

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Device Geometry and Fabrication.

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The devices discussed here are lateral 4H-SiC Zener tunneling diodes, which were fabricated using a subset of steps of the 2μ m4H-SiC CMOS process at Fraunhofer IISB described in Fig. 1 [2]. A schematic cross-section of the diodes structure is shown in Fig. 1. The diode features n- and p-type doped regions, each with a doping concentration of 5·1019 cm−3 that overlap 2μ m to form the tunneling junction, which are implanted into a 1016 cm−3 n-type doped epitaxial 4H−SiC layer. The dopant species are aluminum for the p+-region and nitrogen for the n+-region, respectively. Passivation of the devices is provided through 400 nm of SiO2 deposited using plasma enhanced chemical vapor deposition (PECVD). Contact windows are etched using buffered hydrofluoric acid.

The highly doped regions are thereafter contacted with nickel silicide contacts, which are formed by nickel aluminum alloy lift-off and subsequent rapid thermal annealing (RTA). Aluminum is sputtered and patterned using a dry etching process to contact the device.

[picture]

Fig. 1. Schematic cross-section of the lateral 4H−SiC Zener diode with overlapping n+ and p+ region and the corresponding fabrication process.

Fig. 1. Schematic cross-section of the lateral 4 H − S i C Zener diode with overlapping n + and p + region and the corresponding fabrication process.

[picture]

Fig. 2. Quasi-static current-voltage characteristic of the 4H−SiC Zener diode with the tunneling model by Kane [8] for reference in red under reverse bias. Additionally, the operation points of the diode for CW electroluminescence are shown for the LED operation in blue and in the tunnel emission regime in green.

Fig. 2. Quasi-static current-voltage characteristic of the 4 H − S i C Zener diode with the tunneling model by Kane [8] for reference in red under reverse bias. Additionally, the operation points of the diode for CW electroluminescence are shown for the LED operation in blue and in the tunnel emission regime in green.

[picture]

Fig. 3. Micrograph of the 4H−SiC Zener diode in operation under forward bias a) and under reverse bias b). The images were taken under the same ambient lighting conditions.

Fig. 3. Micrograph of the 4 H − S i C Zener diode in operation under forward bias a) and under reverse bias b). The images were taken under the same ambient lighting conditions.

Optical and Electrical Characteristics.

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The quasistatic electrical characteristic of the Zener diode is given in Fig 2. Under reverse bias a Zener tunneling current is observed, which can be approximated by the theory of tunneling by Kane [8] shown in red in Fig. 2. For the electroluminescent characterization, the diodes were operated at different positive and negative constant current biases in continuous wave (CW) operation. Under forward bias, at injection currents between 1 mA and 85 mA , marked in blue in Fig. 2, the diode emits a spectrum with two distinct peaks. Fig. 3 a) shows a micrograph of the emission under forward bias. The peak at 391 nm is attributed to the transition between the nitrogen donor state and the valence band, since the diode is in strong injection in this operation point and therefore free holes are available in the valence band for recombination. A second peak at 470 nm is visible, which is attributed to the transition between the nitrogen donor level and deeper defect levels in the bandgap as shown in Fig. 3 a) and in Fig. 4. This emission is known from literature [9, 10]. It is observed that the peak attributed to the donor-valence band transition grows faster with larger injection current than the peak of the donor-deep-level transition, which is shown in the inset of Fig. 4. Under reverse bias, light emission is observed at voltages beyond -27.4 V . Those operation points are marked in green in Fig. 2. It is visible that the quasistatic characteristic (shown in black) deviates from the operation points, in which
the diode was operated to acquire the CW spectra. This is due to self-heating of the device. At current biases above 4 mA the voltage drop across the device is constant for each injection current due to excessive self-heating of the device. Under the reverse current biases, the diode emits white light as shown in Fig 3 b) and Fig 5. The spectrum in Fig. 5 shows only one peak at 492 nm with a full width half maximum (FWHM) breadth of 303 nm . At 730 nm , which is commonly used as off-resonant excitation of VSi,43.1% intensity relative to the peak value remains, which makes this mode of emission viable for off-resonant excitation of VSi. To avoid two color processes [11], or resonant excitation from the longer wavelength tail, passive optical band-pass filters, such as Bragg gratings [12] or plasmonic filters [13] must be co-integrated in future work for use in off-resonant excitation of VSi. In the same way, the shorter wavelength peak must be suppressed to avoid excitation into the conduction band.
At low injection currents, the peak intensity of the tunnel emission scales linearly with the injected current up to 4 mA , where self-heating of the device results in constant bias across the junction at any applied current. This is shown in Fig. 6. With no further voltage drop across the junction, the peak intensity saturates. Furthermore, the linear relationship between the peak intensity and injection current in the current limited regime passes through the origin. Therefore, there is no threshold current density for tunneling enhanced light emission.

[picture]

Fig. 4. Electroluminescence of the 4H−SiC Zener diode under forward current biases from 1 mA to 10 mA in 1 mA steps and from 10 mA to 85 mA in 5 mA steps. The inset shows the peak intensities of the two observed peaks with respect to the injection current.

Fig. 4. Electroluminescence of the 4 H − S i C Zener diode under forward current biases from 1 mA to 10 mA in 1 mA steps and from 10 mA to 85 mA in 5 mA steps. The inset shows the peak intensities of the two observed peaks with respect to the injection current.

[picture]

Fig. 5. Electroluminescence of the 4H−SiC Zener diode under reverse current biases from 100μ A to 50 mA . Above 4 mA of injection current the spectrum saturates, since the voltage drop across the diode stays the same due to selfheating.

Fig. 5. Electroluminescence of the 4 H − S i C Zener diode under reverse current biases from 100 μ A to 50 mA . Above 4 mA of injection current the spectrum saturates, since the voltage drop across the diode stays the same due to selfheating.

[picture]

Fig. 6. Maximum intensity of the tunneling emission peak from Fig. 5 with respect to the injected current. Up to the point, where self-heating makes the voltage constant, the peak intensity is linear with respect to the injection current. Without change in voltage the spectrum saturates.

Fig. 6. Maximum intensity of the tunneling emission peak from Fig. 5 with respect to the injected current. Up to the point, where self-heating makes the voltage constant, the peak intensity is linear with respect to the injection current. Without change in voltage the spectrum saturates.

Discussion

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The tunneling enhanced light emission is localized to the region exactly at the tunneling junction, which is shown in Fig 3 b). Therefore, it is assumed that the emission is localized to the high electric field region within the p-n junction. Consequently, a negligible amount of free charge carriers must be in the valence or the conduction band within the region of high electric field. This assumption is confirmed by the absence of a peak at 391 nm corresponding to a donor valence band transition. Free carriers that are generated through tunneling processes are quickly expelled from the space charge region. Within the region of high electric field, tunneling can happen from the valence band into any unoccupied defect within the bandgap, such as the nitrogen donor state. Since there are no holes available for optical transitions into the valence band, the only possible optical transitions are the ones between the nitrogen level and other trap states. At the p -n-junction, the p - and n -regions overlap, which makes the aluminum acceptor state the most available state that supports optical transition. The transition happens only when the acceptor state is unoccupied. This cascade of transitions is illustrated in Fig. 7 b). Since the acceptor state close to the valence band edge cannot be at the same position as the nitrogen donor, from which the electron recombines, an additional tunneling process during recombination is necessary. If the position of the acceptor state close to the valence band edge is shifted along the direction of the electric field, it also has a different energy level with respect to the donor state. Therefore, the energy of the emitted photon depends heavily on the distance r between the acceptor state and the donor state, the density of the acceptor states, the electric field strength, and the direction in which the defect is located.
The resulting spectrum from such a transition can be modeled by calculating the sum over all probabilities of tunneling from the donor state into an unoccupied acceptor state at a certain distance r with the photon energy Eph. There are two probability components to this problem: First, the probability pa of finding at least one acceptor state at distance r in the vicinity of the donor state. This expression is a function of the acceptor doping density NA and formulated as the inverse problem of finding no acceptor state at distance r .

pa=1−exp(−NA43πr3)(1)

Second, the tunneling probability pt between the donor and the acceptor is necessary for the calculation. It is a function of the effective tunneling mass m* and the tunneling barrier height Eb. The tunneling probability pt can be given as:

pt=exp(−22m*Ebℏr)(2)

To model the spectrum with respect to the photon energy Eph, the probabilities of an electron recombining and tunneling from the donor into an acceptor state must be integrated over all radii r . The integration is possible since for each fixed distance r0 around the donor, the energy of the acceptor states at that distance are uniformly distributed on the spherical shell with distance r0 around the donor state. To arrive at an expression that is proportional to the intensity I0 with respect to the photon energy Eph, a relation between r0 and Eph is necessary. It is given by (3) and depends on the electric field ε :

r0=Eph−Ebqε(3)

Since the dependence of the intensity I0 on the photon energy Eph is of interest and each photon energy is correlated to a value of r0, from which on it is part of the spherical shell, the integration must have a lower boundary of r0 (correlated to Eph in (3)) and a upper boundary of infinity. The expression can be written as follows:

I0~∫r0∞pa(r)pt(r)dr(4)

The integral is not analytically solvable and is therefore numerically evaluated. For the numeric evaluation a fixed upper boundary of 50 nm is chosen, since the tunneling probability for this distance is negligible. Unknown parameters, such as the electric field inside the p−n junction and the effective tunneling mass between the states are used as fit parameters to approximate the spectrum from Fig. 5. Known parameters, such as the acceptor concentration NA are fixed at the known value. In Fig. 8, the modeled spectrum is shown in red and the measured spectrum is shown in black. The parameters for the shown spectrum are a constant electric field of 5·106 V/cm, an effective tunneling mass of 0.018· m0, with m0 being the electron mass in vacuum, the fixed acceptor density of 5·1019 cm−3, and a tunneling barrier height of 2.45 eV between the nitrogen donor and the aluminum acceptor. The model does correspond well to the measurement shown in Fig. 8 with respect to the breadth of the peak, its general shaping, and in terms of skew. The model still lacks the consideration of absorption around the bandgap energy of 4H−SiC, which explains the minimally steeper fall-off of the measured curve at the wavelength corresponding to the bandgap energy of 4H−SiC, as well as the consideration of band bending and inhomogeneous electric field at the recombination site, which explains the lower intensity of the measurement at large wavelengths. The deviation between 500 nm and 700 nm is attributed to reflections at the passivation oxide. The good accordance of the model and the measurement indicates that the proposed mechanism for the luminescence under strong reverse bias directly at the p-n junction is most likely a donor to acceptor transition, which is broadened by the variance of energy due to the relative position of donor and acceptor along the electric field.

[picture]

Fig. 7. Band diagram of the transitions observed under a) forward bias or b) the proposed mechanism for tunneling enhanced emission under reverse bias.

Fig. 7. Band diagram of the transitions observed under a) forward bias or b) the proposed mechanism for tunneling enhanced emission under reverse bias.

[picture]

Fig. 8. Comparison between the measured spectrum of the tunneling light emitter and the proposed model with the empirically determined parameters for the effctive tunneling mass and the electric field.

Fig. 8. Comparison between the measured spectrum of the tunneling light emitter and the proposed model with the empirically determined parameters for the effctive tunneling mass and the electric field.

Conclusion

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In the tunneling enhanced light emission regime, optical transitions in 4H−SiC Zener diodes happen between states within the bandgap. Here, we dominantly observe the transition between the nitrogen donor state and the aluminum acceptor state. Due to the strong band bending, the states available for recombination have an energy distribution along the electric field, which leads to a broad spectrum below the bandgap energy of 4H−SiC. In this spectrum, the spectral component for the excitation of VSi at 730 nm is contained with a relative intensity of 43.1% of the peak intensity. Further filtering of the spectrum for such excitation using passive optical filters is necessary and subject of future work.

Acknowledgment

The original version of this paper is available on https://www.scientific.net/KEM.1056.27.pdf

We gratefully acknowledge the help of L. Baier with the measurement setup and the continuous support of the cleanroom staff at Fraunhofer IISB and LEB with the fabrication of the samples.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.27.pdf

S. Castelletto, C. T.-K. Lew, W.-X. Lin, and J.-S. Xu, "Quantum systems in silicon carbide for sensing applications," Reports on progress in physics. Physical Society (Great Britain), vol. 87, no. 1, p. 14501, 2023.

A. May, M. Rommel, L. Baier, M. Schraml, J.F. Dick, M.P.M. Jank, and J. Schulze, "A 4HSiC CMOS technology enabling smart sensor integration and circuit operation above ," 2024 Smart Systems Integration Conference and Exhibition (SSI),Hamburg, Germany, 2024.

C. Babin et al., "Fabrication and nanophotonic waveguide integration of silicon carbide colour centres with preserved spin-optical coherence," Nat. Mater., vol. 21, no. 1, pp. 67-73, 2022.

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M. Widmann et al., "Electrical Charge State Manipulation of Single Silicon Vacancies in a Silicon Carbide Quantum Optoelectronic Device," Nano Letters, vol. 19, no. 10, pp. 71737180, 2019.

R. Nagy et al., "High-fidelity spin and optical control of single silicon-vacancy centres in silicon carbide," Nat Commun, vol. 10, no. 1, p. 1954, 2019.

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S. Javid, F. T. Hamedani, P. Rezaei, and S. Khani, "Designing scalable single-mode to sevenmode plasmonic filters utilizing disk and ring-shaped resonators," Results in Optics, vol. 21, p. 100919, 2025.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 33-40

doi: 10.4028/p-34PxQw

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-04

Accepted:
2026-02-23

Online:
2026-05-20

A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

The original version of this paper is available on https://www.scientific.net/KEM.1056.33.pdf

F. J. Magerl 1,a,*, C. Pixius 2,b, J. Förthner 1,2,c, P. Berwian 2,d, E. Bär 2,e, and J. Schulze 1,2,f

1 Friedrich-Alexander-Universität Erlangen-Nürnberg, Chair of Electron Devices, Cauerstraße 6, 91058 Erlangen, Germany

2 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Schottkystraße 10, 91058 Erlangen, Germany

a  fabian.mager!@fau.de, b  christophe.pixius@iisb.fraunhofer.de, cjulietta.foerthner@iisb.fraunhofer.de, d  patrick.berwian@iisb.fraunhofer.de. e  eberhard.baer@iisb.fraunhofer.de, f  joerg.schulze@fau.de

Abstract

Point defects in 4 H silicon carbide (4H−SiC), such as the silicon vacancy, also known as color centers, offer considerable potential for quantum applications in the fields of quantum sensing as well as computing and communication. The latter two necessitate indistinguishable photons for entanglement swapping and consequently demand precise control over the electronic transition energies, i.e. emission and absorption wavelengths of color centers. One way to achieve this is through monolithic integration of electronic devices in combination with integrated photonics in 4H−SiC. This is considered a potential pathway for scalable quantum photonic integrated circuits. In this paper, we investigate the suitability of a signal-ground-modulator and a vertical pin diode in combination with a waveguide to (i) achieve local field strengths of 5 to 20MV/m in the crystal's c-direction, (ii) stabilize the charge state of the silicon vacancy by controlling the local Fermi level, (iii) meet the requirements for photonic single-mode operation, and (iv) minimize the absorption of the evanescent wave due to metal contacts. The findings of the electronic and optical simulations conducted with Synopsys Sentaurus and Ansys Lumerical suggest that the signal-ground-modulator, commonly used in integrated photonics, rarely attains the requisite field strength. In contrast, the vertical pin diode has the potential to meet these requirements even at reduced bias voltages. Furthermore, the intrinsic layer of the diode offers a wide region in which to host the color center in its optically active, negatively charged state.

Keywords: 4H−SiC, Color Centers, Quantum Applications, Qubits, TCAD Simulations

Introduction

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Due to its long spin-coherence time, the silicon vacancy VSi in 4 H Silicon Carbide (SiC) is among the most promising color centers for the realization of spin-qubits with potential applications in quantum computing, quantum communication and quantum sensing [1]. Adding to its appeal is the fact that SiC is a mature technology platform for power electronic devices and applications in photonics. This opens the prospect of designing integrated SiC-based quantum chips that combine both photonic and electronic structures on the same chip.

For quantum computing and quantum communication, it is crucial to reliably entangle color centers at different locations, which can be achieved over macroscopic distances by making use of photonmediated entanglement swapping [2]. To obtain a high success rate of entanglement, photons emitted from different color centers need to be indistinguishable. However, local variations in the electric field lead to a natural variability in the color centers' energy states, resulting in small shifts of the emitted photon frequencies. To offset the natural variability, precise control over the electronic transition energies is needed. This can be achieved by Stark shift tuning, embedding the color center into an electronic device to modify the electric field in its vicinity [3,4,5]. In current research demonstrators, the photons emitted by the color center are focused into an external optical fiber using solid immersion lenses [2,6]. For future applications, integrating both photonic and electronic structures on the
same chip would be desirable to allow for more scalable technological applications [7]. While there have been successful realizations of the control over electronic transition energies by embedding color centers into electronic devices [8], as well as the successful fabrication of SiC-based photonic structures [9, 10], embedding color centers into both electronic and photonic structures simultaneously has not been investigated yet to our knowledge.

We aim to explore the combined requirements of a VSi center embedded into both an electronic control structure and a single-mode (SM) waveguide made on a Silicon Carbide on Insulator (SiCOI) material. Recent studies on the fabrication of color centers demonstrate high positioning accuracy and implantation depths exceeding 150 nm , enabling precise placement within integrated waveguides and electronic devices [11]. To this end, we simulate two representative categories of electronic device designs compatible with the integration of a SM waveguide. We extract the internal electric field strength and the Fermi level position for the different device designs. The electrical field strength inside the device is essential to shift and to narrow the optical emission lines of individual color centers to make photons emitted by color centers at separate locations (potentially on different chips) indistinguishable. The Fermi level position is essential for the stabilization of the charge state of the color center in thermal equilibrium. Since only the negatively charged silicon vacancy VSi−is optically active, the equilibrium Fermi level must ensure that this charge state is energetically favorable [12]. Due to its wider availability and bigger substrate size, we restrict our analysis to c-plane 4H−SiC. Consequently, the focus is exclusively on device structures that generate vertical electric fields aligned with the dipole axis of the color center, putting a strong constraint on the possible geometries of the electronic structures under investigation. Although investigations have been made on 4H−SiC substrates with alternative crystal orientation, such as a-plane, processing on these substrates differs and is still under investigation [13].

Methods

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The electronic device simulations were performed using the latest version of Synopsys Sentaurus (X2025.06) [14]. Calibration of the simulation models was performed using measurements of forward characteristics of 4H−SiC pin diodes comparable to the simulated ones. We should point out, however, that the electric field and the Fermi level under reverse bias, are insensitive to changes in transport and recombination model parameters, as well as temperature. We are therefore confident that our results are applicable to a wide range of temperatures and device types.

[picture]

Fig. 1: Experimental and calculated values for the dipole moment of the silicon vacancy in 4H−SiC from different literature sources [ 3,8,9,15,16,17 ].

Fig. 1. Experimental and calculated values for the dipole moment of the silicon vacancy in 4 H − S i C from different literature sources [ 3 , 8 , 9 , 15 , 16 , 17 ].

A central requirement for a suitable electronic control structure for VSi−centers is the ability to offset the natural spectral distribution. In [18] Nagy et al. showed that silicon vacancies at hexagonal lattice sites have a spectral distribution of ±10GHz. Offsetting this potential 20 GHz shift between

[picture]

Fig. 2: (a) Schematic view of the simulated signal-ground-modulator with one signal electrode above and two ground electrodes next to the waveguide. (b) Schematic view of the vertical pin diode with a waveguide crossing the intrinsic region at the position of the color center. In both panels different regions are color-coded as follows: Intrinsic (low n-type) 4H-SiC (yellow), the VSi (red sphere), dielectric (green), n-type 4H-SiC (red), p-type 4H-SiC (blue) and metal contacts (grey).

Fig. 2. (a) Schematic view of the simulated signal-ground-modulator with one signal electrode above and two ground electrodes next to the waveguide. (b) Schematic view of the vertical pin diode with a waveguide crossing the intrinsic region at the position of the color center. In both panels different regions are color-coded as follows: Intrinsic (low n -type) 4H-SiC (yellow), the V S i (red sphere), dielectric (green), n -type 4H-SiC (red), p -type 4H-SiC (blue) and metal contacts (grey).

two color centers can be achieved by tuning the emission line via the linear Stark-effect [3]:

Δf=−d·E‖c,(1)

where Δf is the frequency shift of the optical transition, d is the dipole moment, and E‖c the electric field along the c -axis of the crystal. Published values for the dipole moment of the silicon vacancy from measurements and ab initio simulations [3, 8, 9, 15, 16, 17] are shown in Fig. 1. For a detailed discussion of the underlying experiments and calculations, we refer the reader to the respective papers. We use the two extreme values from the experimental data to calculate a range for the minimal strength of the electric field that needs to be achieved for the required detuning, resulting in E‖c, min  between 5MV/m and 20MV/m. In addition to Stark tuning, the electronic structure should stabilize the charge state of the silicon vacancy since only vacancies with a single negative charge are optically active. In thermal equilibrium, the charge state is controlled by the local Fermi-level, which is required to be located between the ( 0∣− ) and ( −∣2− ) transition energies, around 1.29 eV and 0.67 eV below the conduction band, respectively [12, 19]. Silicon vacancies can be either located at hexagonal VSi−(h) or cubic VSi−(k) lattice sites, where they give rise to the V1/V1' and the V2 emission lines, respectively. However, the electric dipole moment and the transition energies of VSi−(h) and VSi−(k) are largely similar [9, 12], such that we will not distinguish between both lattice sites in the following.

We focus on two structures for the generation of the electric field and the Fermi level control; (i) a signal-ground-modulator (SGM) structure, commonly used for optical modulators, and (ii) a vertical pin diode with an integrated waveguide. Both structures are shown schematically in Fig. 2. The SGM is considered as a representative for a wider group of structures that generate an electric field via a metal electrode sitting on a cladding dielectric.

Due to the high symmetry of the SGM, performing the corresponding TCAD simulations in 2D is sufficient. The vertical pin diode, on the other hand, is simulated in full 3D, since the lack of symmetry at the intersection between the electronic structure and the waveguide, shown in Fig. 2(b), does not allow for a 2D simplification.

Simulation Results

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We first determine suitable dimensions for the waveguide by performing finite-difference eigenmode (FDE) simulations using Ansys Lumerical Mode (2021 R1.2) [20]. A 4H-SiCOI rectangular strip waveguide was simulated to find the optimal waveguide geometry for single -mode operation at 861 nm (zero phonon line of V1). The waveguide was designed to support only the fundamental TE
mode with the dominant electric field parallel to the c -axis while suppressing higher order modes. The substrate was SiO2 with air cladding above the waveguide resulting in an optimal waveguide height of 650 nm and width of 220 nm . We additionally analyzed the expected propagation loss of the fundamental mode in the SM waveguide due to the presence of a 4μ m wide and 500 nm thick metal layer in its vicinity. This resembles typical metal interconnects in state of the art 4H−SiC CMOS technology [21]. Based on this information, we recommend a distance of at least 1.7μ m between the edges of the metal contact and the waveguide to ensure minimal absorption losses below 1·10−10 dB/cm. Note that this requirement eliminates the use of Schottky diodes for our purposes and requires unusually thick dielectrics when considering metal-insulator-semiconductor (MIS) structures.
The signal-ground-modulator. At first glance, simple MIS capacitors with a single gate electrode might seem like promising candidates for creating large electric fields around implanted color centers. However, due to the presence of large numbers of charge carriers in the inversion or accumulation layer for MIS devices, the electric field is effectively shielded from the interior of such devices [22]. This rules out MIS structures with a single gate electrode for the purpose of manipulating color centers that are implanted several tens or hundreds of nanometers into the SiC bulk. In the SGM, the presence of a signal and a ground electrode leads to a more homogeneous electric field, making it a potentially viable candidate for the wavelength tuning of color centers. Our 2D simulation model for the SGM is a rectangular SiC waveguide with homogeneous n-type doping of 1·1015 cm−3 sandwiched between thick dielectric layers.

The simulated local electric field is presented in Fig. 3(a). Inside the waveguide, the electric field is oriented vertically, parallel to the dipole moment of the color center. Most of the field strength is concentrated across the upper dielectric cladding, with distinct peaks appearing at the cladding edges. Fig. 3(b) illustrates the local field strength obtained in the different constituent materials along the 1D-cutline shown in the left panel of Fig. 3(a). Even at an applied voltage of 100 V at the signal electrode, the electric field in the waveguide barely reaches the lower threshold of 5MV/m, as derived in the previous section. This limitation arises from Fermi-level pinning at the SiC/SiO2 interface, shown schematically in the real-space band diagram of Fig. 3(c). As the applied bias across the SiO2−SiC−SiO2 stack is increased, both the conduction and valence band edges shift toward the intrinsic Fermi level. This process attracts charge carriers to the interface, which in turn shield the SiC core from the external electric field. Once the Fermi level reaches the edge of the bandgap on both sides, any further increase in applied bias is immediately compensated by additional charge carrier generation from the semiconductor, thus leading to a saturation in the electric field strength which depends on the thickness of the waveguide.

Fig. 3(c) additionally illustrates that, at 100 V signal bias, only a narrow region of approximately 250 nm , between 120 nm and 370 nm from the interface, supports the negatively charged state VSi−and consequently, the optically active state. On the one hand, this imposes stringent requirements on the fabrication and control of the VSi−implantation depth. On the other hand, the region with the correct equilibrium charge state varies depending on the applied signal bias, thus further limiting the allowed values of the signal bias. Fig. 3(d) illustrates the saturation of the maximum electric field strength in the waveguide for different waveguide thicknesses. For decreasing thickness, the maximum electric field strength increases significantly at high applied biases, which can be understood from the band diagram in Fig. 3(c) and the relation between electric field E and valence band energy Ev

E=1e∇Ev(2)

Assuming a constant gradient of the valence band energy, the electric field strength saturates when the Fermi energy reaches the band edges on the two opposed interfaces, yielding Emax ≈Eg/(eH), where H is the waveguide height and e is the electron charge. This simplified estimate, shown as the black curve in Fig. 3(d) correctly predicts the value where the field strength starts to saturate. Consequently, the waveguide height needs to be carefully adapted to the maximum required electric field to tune

[picture]

Fig. 3: (a) 2D electric field strength and field lines. (b) Electric field component parallel to the c-axis at different signal biases along the 1D-cutline shown in panel (a), 4H−SiC shown in light yellow, dielectric cladding in light green. (c) Real-space band diagram inside the 4H−SiC waveguide at 100 V signal bias. The blue and yellow curves mark the transition levels of the silicon vacancy between neutral and negative, as well as negative and doubly negative charge state, respectively. The green shaded region, where the Fermi level lies between both transition states, marks the locations where the color center is in the correct charge state in equilibrium. (d) Maximum field strength in the waveguide as a function of waveguide thickness for different signal bias values. The black curve shows the estimation for the maximally attainable field strength from simple geometric arguments.

Fig. 3. (a) 2D electric field strength and field lines. (b) Electric field component parallel to the c-axis at different signal biases along the 1D-cutline shown in panel (a), 4 H − S i C shown in light yellow, dielectric cladding in light green. (c) Real-space band diagram inside the 4 H − S i C waveguide at 100 V signal bias. The blue and yellow curves mark the transition levels of the silicon vacancy between neutral and negative, as well as negative and doubly negative charge state, respectively. The green shaded region, where the Fermi level lies between both transition states, marks the locations where the color center is in the correct charge state in equilibrium. (d) Maximum field strength in the waveguide as a function of waveguide thickness for different signal bias values. The black curve shows the estimation for the maximally attainable field strength from simple geometric arguments.

two VSi to the same wavelength. One should keep in mind, however, that a thinner waveguide also means a narrower region that supports optically active color centers, putting further constraints on the required manufacturing process. Thus we conclude that, although capacitor-like structures such as the SGM at first seem like promising devices for the tuning of color centers, our results show that they are not ideal for color center tuning. Due to the accumulation of charge carriers at the SiC/SiO2 interface, the attainable strength of the local electric field in the waveguide is severely limited.
The vertical pin diode. A structure that has already been used successfully for the charge stabilization and emission line tuning of color centers is the vertical pin diode. In [19], Widmann et al. reported successful integration and charge stabilization of VSi centers in a bulk vertical pin diode. However, some adaptations are needed for such a configuration to become compatible with integrated photonic platforms. We propose the device structure schematically shown in Fig. 2(b), which (i) keeps the metal contacts to the cathode and anode of the pin diode at the required distance from the waveguide to reduce optical losses and (ii) has a thin intrinsic region, adapted to the requirements of an SM waveguide. Our 3D simulation focuses on the central device region, where the waveguide crosses the electronic
structure. The cathode is a homogeneously doped n-type layer with a concentration of 1·1019 cm−3 while the anode is a shallow p-type profile with a maximum concentration of 5·1019 cm−3 implanted into an n-type epitaxy with low doping (1·1015 cm−3).

[picture]

Fig. 4: (a) 3D representation of the electric field strength around the intersection of the pin diode and waveguide at a reverse bias of 20 V . (b) 2D cut along the middle of the 3D structure in panel (a), showing the local field strength and the direction of the field lines. (c) Vertical cut of the field strength inside the pin diode at different reverse bias voltages. The colored regions indicate the doping according to the same color-coding as in Fig. 2(b). (d) Real-space band diagram along the same vertical cut as in panel (c) at a reverse bias of 8 V . The green shaded region indicates the depth range where the color center is present in the optically active charge state.

Fig. 4. (a) 3D representation of the electric field strength around the intersection of the pin diode and waveguide at a reverse bias of 20 V . (b) 2D cut along the middle of the 3D structure in panel (a), showing the local field strength and the direction of the field lines. (c) Vertical cut of the field strength inside the pin diode at different reverse bias voltages. The colored regions indicate the doping according to the same color-coding as in Fig. 2(b). (d) Real-space band diagram along the same vertical cut as in panel (c) at a reverse bias of 8 V . The green shaded region indicates the depth range where the color center is present in the optically active charge state.

Fig. 4(a) presents a 3D map of the electric field strength at the intersection of the waveguide and vertical pin diode structure at an applied voltage of 20 V . The shorter arm in the figure corresponds to the waveguide, while the extended arms to the left and right connect to the contact pads, as shown schematically in Fig. 2(b). As illustrated in Figs. 4(a) and 4(b), the application of a bias voltage of 20 V already yields electric field strengths that approach 100MV/m, oriented vertically across the waveguide region. The vertical pin diode reaches the required field strength at substantially lower applied voltages than the previous configuration. This significantly simplifies implementation in experimental setups and facilitates the design of quantum photonic integrated circuits (QPIC). Also note that, even with field-crowding effects at the edge of the implanted region in Fig. 4(b), the maximum electric field in the device is still well below the breakdown field of 4H−SiC. The intrinsic region of the pin diode supports a strong internal electric field even at zero applied bias, a consequence of the highly doped p - and n-regions. For a heavily doped p+/n+ junction, the maximum electric field within the
intrinsic region can be approximated by Emax ≈(Vext +Vbi )/Wi, where Vext  is the externally applied bias voltage, Vbi is the built-in potential, and Wi is the intrinsic layer thickness [22]. Furthermore, this electric field remains nearly constant across a spatial extent of approximately 300 nm . In contrast to the SGM, the maximum Stark-shift tuning of the color center is therefore not limited by the structure, but by the breakdown electric field strength of 4H−SiC itself. Compared to the SGM, the intrinsic region of the pin diode additionally offers a broader range for stabilizing VSi in its negatively charged state. This behavior is illustrated in the real-space band diagram of Fig. 4(d) at 8 V bias. Specifically, this region extends about 120 nm from the p-region, allowing a large degree of flexibility regarding the implantation depth of the color center.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1056.33.pdf

We employed TCAD simulations to investigate the performance of two distinct electronic structures for stabilizing the charge state and tuning the emission lines of color centers in 4H−SiC. Fundamental requirements, such as the distance between the integrated waveguide and metal contacts or the direction and penetration depth of the electric field rule out many basic device designs, such as Schottky diodes, lateral pin diodes and simple MIS structures. We therefore focused on the signal-groundmodulator and the vertical pin diode, both of which fulfill the minimum requirements. Our simulations revealed several advantages of the vertical pin diode over the signal-ground-modulator. These include a high electrical field strength parallel to the direction of the color center's dipole even at relatively low bias voltages. In addition, the space charge region in the intrinsic layer of the pin diode provides a large area to maintain the color center in the optically active charge state.

Although vertical pin diodes and a photonic single-mode waveguides are well-established structures in SiC, process related challenges to the integration of both components remain. While more work is needed for the technological realization of the proposed device structures, success would pave the way for scalable SiC quantum photonic integrated circuits.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1056.33.pdf

We thank C. Schwemmer (Fraunhofer IISB) for helpful discussions on spin-photon entanglement. We acknowledge that this work is funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) - 532769051, included in the QuantERA call 2023, and Lighthouse Project TeQSiC (State of Bavaria).

Author Contributions

The original version of this paper is available on https://www.scientific.net/KEM.1056.33.pdf

F. J. M. together with C. P. performed optical and electrical simulations. J. F. helped developing the concept and supervised the project. All authors discussed and contributed to the manuscript.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.33.pdf

S. Castelletto and A. Boretti, Silicon carbide color centers for quantum applications, J. Phys. Photonics, vol. 2, no. 2, p. 22001, 2020, doi: 10.1088/2515-7647/ab77a2.

H. Bernien et al., Heralded entanglement between solid-state qubits separated by 3 meters, Nature, vol. 497, no. 7447, pp. 86-90, 2013, doi: 10.1038/nature12016.

M. Rühl et al., Stark Tuning of the Silicon Vacancy in Silicon Carbide, Nano letters, vol. 20, no. 1, pp. 658-663, 2020, doi: 10.1021/acs.nanolett.9b04419.

C. F. de las Casas et al., Stark tuning and electrical charge state control of single divacancies in silicon carbide, Applied Physics Letters, vol. 111, no. 26, 2017, doi: 10.1063/1.5004174.

C. P. Anderson et al., Electrical and optical control of single spins integrated in scalable semiconductor devices, Science (New York, N.Y.), vol. 366, no. 6470, pp. 1225-1230, 2019, doi: 10.1126/science.aax9406.

R.-Z. Fang et al., Experimental Generation of Spin-Photon Entanglement in Silicon Carbide, Phys. Rev. Lett., vol. 132, no. 16, 2024, doi: 10.1103/PhysRevLett.132.160801.

G. Moody et al., 2022 Roadmap on integrated quantum photonics, J. Phys. Photonics, vol. 4, no. 1, p. 12501, 2022, doi: 10.1088/2515-7647/ac1ef4.

D. Scheller et al., Quantum-enhanced electric field mapping within semiconductor devices, Phys. Rev. Applied, vol. 24, no. 1, 2025, doi: 10.1103/pv13-vgcw.

D. M. Lukin et al., Spectrally reconfigurable quantum emitters enabled by optimized fast modulation, npj Quantum Inf, vol. 6, no. 1, 2020, doi: 10.1038/s41534-020-00310-0.

C. Babin et al., Fabrication and nanophotonic waveguide integration of silicon carbide colour centres with preserved spin-optical coherence, Nature materials, vol. 21, no. 1, pp. 67-73, 2022, doi: 10.1038/s41563-021-01148-3.

Y. Xue et al., Selective generation of V2 silicon vacancy centers in 4H-silicon carbide, Nano Letters, vol. 24, no. 7, p. 2369-2375, 2024, doi: 10.1021/acs.nanolett.3c03905.

M. E. Bathen et al., Electrical charge state identification and control for the silicon vacancy in 4H-SiC, npj Quantum Inf, vol. 5, no. 1, 2019, doi: 10.1038/s41534-019-0227-y.

J. H. Schwarberg et al., Investigation of CMOS Single Process Steps on 4H-SiC a-Plane Wafers for Quantum Applications, 2024, 47th MIPRO ICT and Electronics Convention (MIPRO). IEEE, 2024, doi: 10.1109/MIPRO60963.2024.10569589.

Sentaurus Process User Guide, Version X-2025.06, Synopsys Inc., 2025.

M. E. Bathen et al., First-principles calculations of Stark shifts of electronic transitions for defects in semiconductors: the Si vacancy in 4H-SiC, Journal of physics. Condensed matter : an Institute of Physics journal, vol. 33, no. 7, p. 75502, 2020, doi: 10.1088/1361-648X/abc804.

R. Nagy et al. High-fidelity spin and optical control of single silicon-vacancy centres in silicon carbide, Nat Commun 10, 1954 (2019), doi: 10.1038/s41467-019-09873-9.

P. Udvarhelyi et al., Spectrally Stable Defect Qubits with no Inversion Symmetry for Robust Spin-To-Photon Interface, Phys. Rev. Appl., vol. 11, no. 7, p. 044022, doi: 10.1103/PhysRevApplied.11.044022.

R. Nagy et al., Narrow inhomogeneous distribution of spin-active emitters in silicon carbide, Applied Physics Letters, vol. 118, no. 14, p. 46, 2021, doi: 10.1063/5.0046563.

M. Widmann et al., Electrical charge state manipulation of single silicon vacancies in a silicon carbide quantum optoelectronic device, Nano letters, vol. 19, no. 10, pp. 7173-7180, 2019, doi: 10.1021/acs.nanolett.9b02774.

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A. May et al., A 4H-SiC CMOS technology enabling smart sensor integration and circuit operation above 500 C, 2024 Smart Systems Integration Conference and Exhibition (SSI). IEEE, 2024, doi: 10.1109/SSI63222.2024.10740550.

S. M. Sze and K. K. Ng, Physics of Semiconductor Devices: Wiley, 2006, doi: 10.1002/0470068329.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 41-45

doi: 10.4028/p-SCR8gg

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-21

Revised:
2025-12-10

Accepted:
2026-02-28

Online:
2026-05-20

Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

The original version of this paper is available on https://www.scientific.net/KEM.1056.41.pdf

Zhiwen Zhang 1,a, Hao Yuan 1, b, Xiaoyan Tang 1,c and Qingwen Song 1, d*

1 Xidian University, School of Microelectronics, NO.2, Taibai Road, Xi'an, China

a  zhiwenzhang2023@126.com, b  haoyuan@xidian.edu.cn, c  xytang@mail.xidian.edu.cn, d * qwsong@xidian.edu.cn

Keywords: single-event effect, heavy-ion irradiation, silicon carbide, experimental results, postirradiation electrical characterization, focused ion beam.

Abstract

The deployment of silicon carbide ( SiC ) power devices in aerospace applications is constrained by their unexpected susceptibility to single-event effects (SEEs), despite the inherent advantages of wide bandgap materials. In this work, we experimentally investigate the SEE mechanisms in in-house fabricated 1200 V SiC VDMOSFETs under heavy-ion irradiation using Ta ions with a LET of 75MeV·cm2/mg. Real-time current monitoring, post-irradiation electrical characterization, and focused ion beam (FIB) analysis were employed to systematically examine device degradation and failure modes under various bias conditions. The results demonstrate a clear progression of damage with increasing bias voltage: no significant changes, single-event gate leakage degradation (SEGLD) at 100 V , single-event leakage current (SELC) in both Id=Ig and Id>Ig modes at 300−400 V, and catastrophic single-event burnout (SEB) at 500 V . Structural analyses reveal progressive deepening of gate oxide fractures, extension into the P+ source region, and eventual source metal melting, consistent with the observed electrical degradation. Notably, the threshold voltage remained stable throughout, suggesting that localized damage to limited unit cells has minimal influence on the global device threshold. These findings provide critical insights into SEEinduced degradation pathways in SiC MOSFETs and offer valuable guidelines for the design and radiation hardening of next-generation aerospace power systems.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.41.pdf

The rapid advancement of aerospace power systems imposes stringent requirements on power devices in terms of efficiency, reliability, and radiation tolerance. Silicon carbide (SiC) devices, owing to their wide bandgap, high breakdown field, and superior thermal conductivity, have emerged as strong candidates to replace conventional silicon-based power electronics in such environments [1].

However, recent experimental evidence indicates that SiC MOSFETs are far more vulnerable to single-event effects (SEEs) than initially expected. Phenomena such as single-event burnout (SEB), single-event leakage current (SELC), and single-event gate leakage degradation (SEGLD) have been observed at voltages significantly below the rated blocking voltage, in some cases at less than 30% [2-5]. These premature failures severely restrict the safe operating area of SiC MOSFETs in aerospace applications and highlight the urgent need for a deeper understanding of their degradation mechanisms under heavy-ion irradiation.

To date, considerable research efforts have been devoted to investigating SEE mechanisms in wide-bandgap devices. Prior studies have suggested that the onset of SEB is linked to localized thermal runaway triggered by heavy-ion tracks, while SELC and SEGLD are associated with microstructural damage in the gate oxide and channel regions. Nonetheless, the detailed evolution pathways of these failure modes, particularly under varying bias conditions, remain insufficiently explored. A systematic study that correlates bias-dependent failure behaviors with physical microstructural damage is essential to bridge this knowledge gap.

In this work, we conduct a comprehensive experimental investigation of SEE mechanisms in 1200 V SiC VDMOSFETs subjected to heavy-ion irradiation. Using Ta ions with a linear energy transfer (LET) of 75MeV·cm2/mg, we combine real-time current monitoring, post-irradiation electrical
characterization, and focused ion beam (FIB) cross-sectional analysis to examine device degradation under multiple bias conditions. By correlating electrical signatures with microstructural evidence, we establish the progression of SEE-induced failure modes-from SEGLD to SELC and ultimately SEB-and reveal critical insights into the physical origins of these degradation pathways. The results not only deepen the understanding of SEE mechanisms in SiC MOSFETs but also provide valuable design guidelines for the development of radiation-hardened power devices for aerospace applications.

Experimental Setup

The original version of this paper is available on https://www.scientific.net/KEM.1056.41.pdf

The devices under test (DUTs) were in-house fabricated 1200 V SiC vertical double-diffused MOSFETS (VDMOSFETs) packaged in TO-254. To minimize the energy loss of incident ions, the packaged devices were decapsulated prior to irradiation. Fig. 1(a) illustrates the device cross-section, while Fig. 1(b) presents the package configuration.

Heavy-ion irradiation experiments were conducted at the Institute of Modern Physics, Lanzhou, employing a tantalum (Ta) ion beam with a linear energy transfer (LET) of 75MeV·cm2/mg. During irradiation, the drain, source, and gate terminals of the DUTs were biased externally according to the test requirements. The applied drain-to-source voltages ranged from 0 V to 500 V , thereby enabling systematic investigation of SEE phenomena under different electrical stress conditions.

The experimental platform is shown in Fig. 1(c). Real-time monitoring of both drain current ( Id ) and gate current ( Ig ) was performed using high-precision current measurement equipment to capture transient single-event responses. After irradiation, comprehensive electrical characterizations, including transfer characteristics, output characteristics, gate leakage tests, and blocking capability were conducted to evaluate device degradation using a Keysight B1505A semiconductor power analyzer, as shown in Fig. 1(d).

In order to directly examine the physical damage induced by heavy-ion strikes, focused ion beam (FIB) analysis was employed. A total of 15 devices were tested across all bias conditions, with at least three DUTs assigned to each irradiation voltage level to ensure statistical consistency. Representative DUTs that exhibited distinct SEE behaviors-such as single-event gate leakage degradation (SEGLD), single-event leakage current (SELC), and single-event burnout (SEB)-were selected for structural analysis. The corresponding microstructural evidence was correlated with electrical characteristics to establish the progression of SEE failure mechanisms, as summarized in Fig. 1(e).

[picture]

Fig. 1. (a) Device cross-section diagram. (b) Packaging schematic diagram. (c) On-site test setup. (d) Post-irradiation test setup. (e) SEE characteristic of SiC MOSFET.

Fig. 1. (a) Device cross-section diagram. (b) Packaging schematic diagram. (c) On-site test setup. (d) Post-irradiation test setup. (e) SEE characteristic of SiC MOSFET.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1056.41.pdf

The irradiation experiments reveal a distinct evolution of SEE failure modes as the applied drain bias increases. The progression follows a sequence from negligible degradation, to SEGLD, then to SELC with two distinct modes, and finally to catastrophic SEB. For each bias condition ( 100 V,300V,400 V, and 500 V ), a minimum of three devices were irradiated, and all reported behaviors were consistently observed across repeated samples.

At a drain bias of 100 V , the DUTs exhibited SEGLD. A marked increase in gate leakage current was observed post-irradiation, while the threshold voltage and transfer characteristics remained nearly unchanged. This indicates localized damage to the gate oxide rather than significant alteration of channel conduction. No noticeable post-irradiation recovery or annealing behavior was observed during room-temperature monitoring over several hours, indicating that the induced damage is largely permanent without high-temperature annealing. Focused Ion Beam (FIB) analysis confirmed that there is an approximately 1μ m deep crack in the gate oxide at the center of the JFET region in only one cell [6]. These micro-cracks serve as leakage paths, explaining the increase in gate current without notable threshold voltage shifts.

[picture]

Fig. 2. (a)-(d) Test results (e) FIB cross-section image of the SEGLD DUTs, where the ILD layer corresponds to the interlayer dielectric between the metallization and gate oxide.

Fig. 2. (a)-(d) Test results (e) FIB cross-section image of the SEGLD DUTs, where the ILD layer corresponds to the interlayer dielectric between the metallization and gate oxide.

When the bias was raised to 300 V , DUTs transitioned into the Id=Ig mode of SELC. In this condition, both drain current and gate current increased simultaneously, suggesting charge transport through extended oxide damage regions. FIB cross-sections revealed oxide fractures reaching a depth of about 2μ m, accompanied by partial degradation of blocking voltage to about 500 V .

[picture]

Fig. 3. (a)-(d) Test results (e) FIB cross-section image of the SELC( Id=Ig ) DUTs.

Fig. 3. (a)-(d) Test results (e) FIB cross-section image of the SELC( I d = I g ) DUTs.

At a higher bias of 400 V , the DUTs entered the Id>Ig mode of SELC. In this regime, the drain current has created a new drain-source current leakage path, indicating that damage has occurred at the device's source. Structural analysis showed cracks propagating 3.5μ m deep into the P+ source region, together with localized melting of the source metal. Correspondingly, the blocking voltage further degraded to ~250 V. These observations confirm that SELC represents a progressive damage state, with Id>Ig being more destructive than Id=Ig.

[picture]

Fig. 4. (a)-(d) Test results (e) FIB cross-section image of the SELC( Id>Ig ) DUTs.

Fig. 4. (a)-(d) Test results (e) FIB cross-section image of the SELC( I d > I g ) DUTs.

At 500 V bias, catastrophic SEB was triggered. The devices exhibited uncontrollable current surges followed by permanent failure. FIB images revealed massive damage extending over 14μ m into the device structure, with complete oxide rupture and severe metallization destruction. This is consistent with a thermal runaway process initiated by heavy-ion energy deposition, leading to irreversible device breakdown [2]. It is worth noting that the identification of SELC and SEB mechanisms was based primarily on real-time transient current monitoring, while the extent of physical damage was confirmed through post-irradiation static electrical measurements and FIB cross-sectional analysis.

[picture]

Fig. 5. (a)-(d)Test results (e) FIB cross-section image of the SEB DUTs.

Fig. 5. (a)-(d)Test results (e) FIB cross-section image of the SEB DUTs.

An important observation is that the device threshold voltage remained stable throughout all degradation stages (except for SEB), despite substantial deterioration in gate leakage and breakdown characteristics [7]. This indicates that SEE-induced damage tends to be highly localized, affecting only a limited number of unit cells, which has little impact on the averaged threshold behavior of the entire device.

A concise summary of degradation levels at each failure mode is as follows:
SEGLD (100 V) : Gate leakage increased from <10−8 A to ~10−5 A, with no change in threshold voltage.

SELC (Id = Ig mode, 300 V ): Both Id and Ig increased to the 100 nA level; blocking voltage reduced to ~500 V.

SELC ( Id> Ig mode, 400 V ): Drain leakage exceeded tens of μA; blocking capability dropped to ~250 V.

SEB ( 500 V ): Catastrophic current surge ( >1 mA ) and permanent breakdown.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1056.41.pdf

This work experimentally investigated single-event effect mechanisms in 1200 V SiC VDMOSFETs under heavy-ion irradiation. The results revealed a clear bias-dependent evolution of failure modes, progressing from SEGLD to SELC and finally to catastrophic SEB. FIB analyses confirmed the progressive deepening of oxide fractures and structural damage, while the device threshold voltage remained stable, indicating localized damage. The correlation between electrical degradation and microstructural damage provides crucial insight into the physical origins of SEEs in SiC MOSFETs. These results suggest that improving the robustness of the gate oxide and mitigating source-side current crowding are key strategies for radiation hardening. The observed degradation sequence provides direct guidance for optimizing oxide thickness, cell topology, and terminal design in next-generation radiation-tolerant SiC MOSFETs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.41.pdf

X. She, A. Q. Huang, Ó. Lucía and B. Ozpineci, Review of Silicon Carbide Power Devices and Their Applications, IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 81938205, Oct. 2017.

D. R. Ball et al., Ion-Induced Energy Pulse Mechanism for Single-Event Burnout in HighVoltage SiC Power MOSFETs and Junction Barrier Schottky Diodes, IEEE Transactions on Nuclear Science, vol. 67, no. 1, pp. 22-28, Jan. 2020.

E. Mizuta, S. Kuboyama, H. Abe, Y. Iwata and T. Tamura, Investigation of Single-Event Damages on Silicon Carbide (SiC) Power MOSFETs, IEEE Transactions on Nuclear Science, vol. 61, no. 4, pp. 1924-1928, Aug. 2014.

J. L. Titus, An Updated Perspective of Single Event Gate Rupture and Single Event Burnout in Power MOSFETs, IEEE Transactions on Nuclear Science, vol. 60, no. 3, pp. 1912-1928, June 2013.

L. Qiu et al., Microstructure Damage for Single-Event Leakage Current II in SiC MOSFETs Induced by Heavy Ion, IEEE Transactions on Electron Devices, vol. 72, no. 5, pp. 2233-2239, May 2025.

L. Qiu et al., Analysis of Gate Oxide Degradation Induced by Heavy Ion in SiC Power MOSFETs, IEEE Transactions on Electron Devices, vol. 71, no. 4, pp. 2524-2529, April 2024.

Q. Yuan et al., Effect of Heavy-Ion-Induced Latent Damage on SiC MOSFETs' Gate Reliability, IEEE Transactions on Nuclear Science, vol. 72, no. 8, pp. 2419-2425, Aug. 2025.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 47-53

doi: 10.4028/p-P6rBld

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-05

Revised:
2025-12-08

Accepted:
2026-02-26

Online:
2026-05-20

Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

Chuan-Han Chen 1,a*, Cheng-Shu Chang 1, b, I-Chen Tsai 1,c, Der-Sheng Chao 2, d and Bing-Yue Tsui 1,e

¹Institute of Electronics, National Yang Ming Chiao Tung University No.1001, Ta-Hsueh Road, Hsinchu, Taiwan, R.O.C.

2 Nuclear Science and Technology Development Center No. 101, Kuang-Fu Road, Hsinchu, Taiwan, R.O.C.

a* david890611.ee11@nycu.edu.tw, b  andychang.ee12@nycu.edu.tw, c yichentsai.ee13@nycu.edu.tw, d dschao@mx.nthu.edu.tw, e bytsui@nycu.edu.tw

Keywords: PMOSFET, gamma-ray, irradiation, oxide charge, threshold voltage.

Abstract

Silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) technology and its circuit applications have been rapidly advancing, making the stability and reliability of planar p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) increasingly important. In this study, a channel-length-dependent threshold voltage instability was observed under both gate bias stress and gamma-ray irradiation. The results indicate that the majority of positive charge trapping originates from hole injection induced by external bias. Secondary ion mass spectrometry (SIMS) analysis confirmed the retention of aluminum species in the gate dielectric after thermal oxidation. Based on these experimental findings, a dopant diffusion model was proposed, suggesting that dopant contamination in the gate oxide is the primary cause of the channel-length-dependent instability.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

4 H -type silicon carbide (4H−SiC) is regarded as one of the most promising semiconductor materials for power electronic applications, owing to its wide bandgap, high thermal conductivity, and high electron mobility [1]. Various types of SiC devices, such as junction barrier Schottky (JBS) diodes [2] and vertical double-diffused MOSFETs (VDMOSFETs) [3, 4], are now widely used in automotive, renewable energy, and transportation applications [5]. Beyond these advantages, SiC has also attracted considerable attention from the aerospace industry for the past two decades due to its high threshold displacement energy [6]. This property enables SiC-based detectors to exhibit strong resistance to radiation damage while maintaining stable charge collection efficiency [7].

To further expand its applications, many studies have investigated the radiation effects on MOS structures, particularly VDMOSFETs. One of the most critical concerns is the generation of electronhole pairs in silicon dioxide under gamma-ray irradiation. Because holes have relatively low mobility, they tend to be trapped in the oxide [8]. If a significant number of charges are trapped, this can degrade both conduction and blocking characteristics, as demonstrated in previous studies [9, 10].

Moving beyond power MOSFETs, it is also essential to understand the effects of radiation on CMOS devices. With continuous progress in SiC CMOS technology, which is now capable of supporting simple circuit implementations [11, 12], evaluating its radiation tolerance has become increasingly important. Consequently, the electrical performance and stability of both NMOS and PMOS devices under radiation environments are critical research topics. Research on the electrical performance and stability of 4H−SiC PMOSFETs remains relatively limited. Therefore, in this work, we focus on the electrical characteristics of PMOSFETs and propose a novel explanation for the observed phenomenon.

Experiments

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

The simplified process steps and the cross-sectional structure of the PMOSFETs are illustrated in Fig. 1. The fabrication process began with a 4H−SiC wafer consisting of a 5.5−μm-thick epitaxial layer with a nitrogen concentration of 1×1016 cm−3. The N -well and N+regions were formed by phosphorus implantation, while aluminum implantation was employed for the p-type regions. To reduce the threshold voltage of the PMOSFETs, a counter-doping implantation was applied to the channel. Ion implantation was performed at 500∘C, followed by high-temperature activation at 1700∘C for 30 minutes. The 40 -nm-thick thermal gate oxide was grown in a wet ambient at 1050∘C, followed by pure NO post-oxidation-annealing (POA) at 1200∘C. Nickel was used as the contact metal, and ohmic contact was formed through appropriate annealing. More details of the fabrication process can be found in our previous work [12].

The experimental setup is shown in Fig. 2. The fabricated chips were packaged on a printed circuit board and mounted on an acrylic stand. A cobalt-60 gamma-ray source was used to irradiate the samples at a dose rate of 0.515kGy(Si)/hr. During irradiation, the PMOSFETs were subjected to a gate bias of -20 V , while all other terminals were grounded. The devices were divided into two groups: one group was exposed to a total gamma-ray dose of 1 kGy under gate bias, while the other was only subjected to gate bias stress for 2 hours (the same duration as the irradiation). This experimental design was intended to distinguish the effects of gamma-ray irradiation from bias stress

The threshold voltage ( Vth ) was defined as the gate to source voltage ( VGS ) at which the normalized drain current, ID×(L/W)-where L and W represent the channel length and width, respectivelyreached 10 nA at a drain to source voltage ( VDS ) of -0.1 V . However, the extracted Vth  is affected by the interface state density, making it difficult to accurately estimate the trapped charge density in the gate oxide using Vth  alone. To address this, an additional self-defined parameter, Vi, was introduced, defined as the gate voltage at which the normalized drain current reaches 1 pA . This parameter helps to minimize the ambiguity caused by subthreshold swing (S.S.). The S.S. was extracted from the normalized current in the range of 10 to 100 pA .

Well, S/D implantation

HT annealing and sacrficial oxidation

Field oxide formation

Gate oxidation (wet 1050∘𝐂 )

Post-oxidation annealing (NO 1200∘𝐂 )

Poly-Si gate deposition and patterning

S/D contact etching

Ohmic contact formation

Gate contact etching

Al Deposition and Patterning

[picture]

Fig. 1. Simplified process flow and cross-sectional structure of the PMOSFETs.

Fig. 1. Simplified process flow and cross-sectional structure of the PMOSFETs.

[picture]

Fig. 2. Experimental equipment and samples setup.

Fig. 2. Experimental equipment and samples setup.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

Fig. 3 presents the transfer characteristics of PMOSFETs with different channel lengths before and after gamma-ray irradiation. As expected, both devices exhibit a clear leftward shift in the I-V curves. However, an unexpected result is that the short-channel device ( L=0.8μ m ) shows a much larger shift compared to the long-channel device ( L=50μ m ). The precise changes in the extracted parameters are summarized in Table I. A difference of approximately 1.2 V in ΔVth  between the shortand long-channel devices was calculated, with only minor contributions from Δ S.S. The change of trapped charge per area ( ΔQox ) can still be reliably estimated from ΔVi using the relation

ΔQox=ΔVi/Cox.(1)

where Cox is the specific capacitance of gate oxide. Based on this calculation, the gate dielectric of the short-channel device is found to trap approximately 1.5 times more positive charges than that of the long-channel device.

Table 1. Change of electrical properties after irradiation and gate stress. All parameters were extracted at VD of -0.1 V .

Device | After Irradiation | After Gate Stress
L= 0.8 μm | L= 50 μm | L= 0.8 μm | L= 50 μm
ΔVt (V) | -1.56 | -0.63 | -1.46 | -0.61
ΔS.S. (mV/dec) | 39 | -2 | -73 | -78
ΔVth (V) | -1.79 | -0.59 | -0.78 | -0.39

[picture]

Fig. 3. Transfer characteristics of PMOSFET before and after gamma irradiation under a gate bias of -20 V for 2 hours. (a) ΔVth  (b) Vi.

Fig. 3. Transfer characteristics of PMOSFET before and after gamma irradiation under a gate bias of -20 V for 2 hours. (a) Δ V th (b) V i .

For the samples subjected to 2 hours of gate bias stress, the results are shown in Fig. 4, where a gate-length-dependent ΔVi is also observed. For devices with the same channel length, the irradiated samples exhibit a larger threshold voltage shift. This phenomenon is related to the improvement in S.S. caused by gate bias stress, although the exact mechanism remains unclear. The uncertainty in S.S. highlights the necessity of introducing the parameter SiC/. Interestingly, the ΔVth  values of PMOSFETs with the same channel length are found to be very similar in different groups. This indicates that gamma-ray irradiation contributes primarily to the maintenance or degradation of the S.S., whereas negative bias is more effective in trapping positive charges than gamma-ray-induced charge generation. The efficiency of trapping holes can be explained by considering that holes generated under irradiation tend to drift toward the poly-Si side under the electric field, thereby reducing their impact on the I-V curve shift. In contrast, carriers induced by gate bias can directly inject into the oxide near the ΔVi oxide interface. A schematic illustration of this explanation is provided in Fig. 5.

[picture]

Fig. 4. Transfer characteristics of PMOSFETs before and after gate stress at -20 V for 2 hours.
(a) SiO2 (b) SiO2/SiC.

Fig. 4. Transfer characteristics of PMOSFETs before and after gate stress at -20 V for 2 hours. (a) S i O 2 (b) S i O 2 / S i C .

[picture]

Fig. 5. The schematic of band diagram illustrating carriers movement in PMOSFETs under negative gate bias during gamma-ray exposure.

Fig. 5. The schematic of band diagram illustrating carriers movement in PMOSFETs under negative gate bias during gamma-ray exposure.

To account for the observed gate-length-dependent 1×1019 cm−3 and 1300∘C, a lateral dopant diffusion model was proposed. To establish this model, it is first necessary to confirm that aluminum species remain in the L=0.8μ m after oxidation and POA. A SIMS analysis was performed on an aluminum-implanted wafer after the thermal oxidation step, and the result is shown in Fig. 6(a). The Si intensity profile was used to identify the 1×1018 cm−3 interface, and a dopant concentration exceeding P+ was detected in the oxide. Since SiC processes typically involve high temperatures, often reaching L=50μm or higher, the retained dopants are able to laterally diffuse from the source and drain edges toward the gate center [13], as shown in Fig. 6(b). Under the same processing conditions, a larger fraction of the gate oxide in short-channel devices becomes contaminated by these dopant species. These atoms may act as trap centers [14, 15], resulting in a higher effective trapped charge density in short-channel devices and, consequently, larger shifts in the I-V characteristics.

[picture]

Fig. 6. (a) SIMS depth profile of Al atoms in the gate oxide and SiC . The dashed lines represent the oxide/SiC interface. (b) The schematic of lateral dopants diffusion model.

Fig. 6. (a) SIMS depth profile of Al atoms in the gate oxide and SiC . The dashed lines represent the oxide/SiC interface. (b) The schematic of lateral dopants diffusion model.

To further confirm that the trapped charges indeed affect the electrical characteristics, Sentaurus TCAD simulations were performed to analyze the electrostatic conditions of the PMOSFET gate oxide with and without positive charge incorporation under all electrodes grounded. Fig. 7(a) and 7(b) show the simulated potential distribution of a short-channel PMOSFET ( 4H−SiC ). In Fig. 7(a), the gate oxide is assumed to be free of trapped charges, whereas in Fig. 7(b), a Gaussian distribution of positive charges with a peak concentration of 4H−SiC is introduced at the edges of the 4H−SiCregions adjacent to the channel. In the charge-free case Fig. 7(a), the equipotential lines in both the gate oxide and the channel region remain flat and uniform, indicating stable electrostatic conditions. By contrast, in the charged case Fig. 7(b), the equipotential lines become distorted, particularly near the channel
edges, revealing a significant perturbation to the electrostatic potential profile. Fig. 8 shows the valence-band energy along the channel, taken very close to the oxide/ SiC interface (Line A in Fig. 7(b)). The case with oxide charges exhibits a lower valence-band energy in the channel region, which corresponds to a higher barrier for hole transport from source to drain. As a result, a higher gate voltage is required to induce sufficient carriers. This distortion strongly suggests that trapped charges in the oxide can degrade MOSFET operation, especially in short-channel devices where the entire channel is more sensitive to local field variations. For comparison, in a long-channel device ( 10−V ), the distortion caused by trapped charges is confined primarily to the channel edges, while the central channel region gradually recovers to a more uniform potential distribution, similar to the charge-free case. This highlights the channel-length dependence of charge-induced potential distortion in SiC PMOSFETs.

[picture]

Fig. 7. Equipontential lines distribution in short-channel PMOSFET (a) without and (b) with fixed oxide charges.

Fig. 7. Equipontential lines distribution in short-channel PMOSFET (a) without and (b) with fixed oxide charges.

[picture]

Fig. 8. Valence-band energy at line A in Fig. 7(b). (a) 600−V (b) SiO2/Si.

Fig. 8. Valence-band energy at line A in Fig. 7(b). (a) 600 − V (b) S i O 2 / S i .

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

In summary, a channel-length-dependent threshold voltage instability was observed under both gate bias stress and gamma-ray irradiation. The experimental results indicate that the majority of positive charge trapping originates from hole injection induced by external bias, and gamma-ray irradiation contributes the change in S.S. SIMS analysis further confirmed the retention of aluminum species in the gate dielectric after thermal oxidation. Based on these findings, a lateral dopant diffusion model was proposed, suggesting that aluminum contamination in the gate oxide is the primary cause of the channel-length-dependent instability. Finally, TCAD simulations were employed to analyze the electrostatic potential distribution in PMOSFETs, clearly revealing how trapped charges affect their electrical performance.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

This work was supported by the National Science and Technology Council, Taiwan, under the contract No. NSTC 113-2218-E-A49-018 and NSTC 113-2221-E-A49-093-MY2. Test structure fabrication were helped by Episil Technologies Inc.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.47.pdf

M.E. Levinshtein, S.L. Rumyantsev, M.S. Shur (Eds.), Properties of Advanced Semiconductor Materials: GaN, AIN, InN, BN, SiC, SiGe, Wiley, New York, 2001, pp. 31-47.

Min S.-J., Shin M.C., Thi Nguyen N., Oh J.-M., Koo S.-M., High-performance temperature sensors based on dual 4H-SiC JBS and SBD devices, Mater. 13 (2) (2020) 445.

S. Singh, N. Yadava, R.K. Chauhan, Performance comparison of power MOSFETs having different SiC substrate, Proc. Int. Conf. Electrical and Electronics Engineering (ICE3), Gorakhpur, India, 2020, pp. 650-655.

Information on .

F. Roccaforte, G. Greco, P. Fiorenza, Processing issues in SiC and GaN power devices technology: the cases of planar MOSFET and recessed hybrid GaN MISHEMT, Int. Semiconductor Conf. (CAS), 2018, pp. 7-16.

W. Li, L. Wang, L. Bian, F. Dong, M. Song, J. Shao, S. Jiang, H. Guo, Threshold displacement energies and displacement cascades in : molecular dynamic simulations, AIP Adv. 9 (2019) 055007.

S.K. Chaudhuri, K.C. Mandal, Radiation detection using n-type 4H-SiC epitaxial layer surface barrier detectors, in: Advanced Materials for Radiation Detection, Springer International Publishing, Cham, 2021, pp. 183-209.

T.P. Ma, P.V. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits, Wiley, New York, 1996.

C.H. Chen, B.Y. Tsui, D.S. Chao, Impact of gamma-ray irradiation on the blocking characteristics of edge termination on and a novel anti-ionizing radiation technology, IEEE J. Electron Devices Soc. 13 (2025) 472-476.

F.J. Hsu, C.C. Hung, K.T. Chu, L.S. Lee, W.B. Yeh, C.Y. Lee, D.S. Chao, J.Y. Jiang, C.F. Huang, Radiation Influence Comparison between SiC JMOS and DMOS, 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, 2020, pp. 146-149.

J. Romijn, S. Vollebregt, L.M. Middelburg, B. El Mansouri, H.W. van Zeijl, A. May, T. Erlbacher, G. Zhang, P.M. Sarro, Integrated digital and analog circuit blocks in a scalable silicon carbide CMOS technology, IEEE Trans. Electron Devices 69 (1) (2022) 4-10.

B.Y. Tsui, C.L. Hung, T.K. Tsai, Y.C. Tsui, T.W. Wang, Y.X. Wen, C.P. Shih, J.C. Wang, L.J. Lin, C.H. Wang, K.W. Chu, P.H. Chen, First integration of CMOS logic circuit, 20-V gate driver, and VDMOSFET on a 4 H -SiC single chip, Proc. IEEE Int. Symp. Power Semiconductor Devices and ICs (ISPSD), Vancouver, Canada, 2022, pp. 321-324.

A. La Ferla, G. Galvagno, S. Rinaudo, V. Raineri, G. Franco, M. Camalleri, A. Gasparotto, A. Carnera, E. Rimini, Ion implantation and diffusion of Al in a system, Nucl. Instrum. Methods Phys. Res. B 116 (1996) 378-381.

J.H. Mackey, J.W. Boss, D.E. Wood, EPR study of substitutional-aluminum-related hole centers in synthetic -quartz, Journal of Magnetic Resonance (1969) 3.1 (1970): 44-54.

M. Gerosa, C.D. Valentin, C.E. Bottani, G. Onida, G. Pacchioni, Communication: Hole localization in Al -doped quartz within ab initio hybrid-functional DFT, The Journal of Chemical Physics 143.11 (2015).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 55-60

doi: 10.4028/p-Y7deEt

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-10

Accepted:
2026-02-26

Online:
2026-05-20

High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

Takahiro Makino 1,a*, Tomoki Taoka 2, b, Kaito Yamamura 2,c and Takuro Tomita 2,d

1 National Institutes for Quantum Science and Technology, 1233 Watanuki, Takasaki, Gunma, Japan

2 Tokushima University, 2-1, Minamijosanjima, Tokushima, Tokushima, Japan

ª*makino.takahiro@qst.go.jp, bc612101921@gmail.com, cc612534031@tokushima-u.ac.jp, dtomita@tokushima-u.ac.jp

Keywords: high-voltage device testing, laser-induced transient response, silicon carbide (SiC), single event burnout (SEB), two-photon absorption.

Abstract

A laser-based experimental system was developed to investigate Single Event Burnout (SEB) in high-voltage silicon carbide (SiC) devices. By enabling transient measurements under high reverse-bias conditions, the setup emulates ion-induced charge generation with femtosecond laser pulses. Time-resolved waveforms and charge collection trends were obtained, showing consistency with previous heavy ion experiments. This confirms the system's capability to reproduce SEB-relevant dynamics. Further improvements in spatial resolution and impedance matching are required for detailed analysis of internal charge transport mechanisms.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

Silicon carbide (SiC) is widely recognized as a promising material for radiation-hardened (radhard) electronic devices due to its wide bandgap, high breakdown field, and excellent thermal conductivity. These properties give SiC devices strong resistance to Total Ionizing Dose (TID) effects [1-3], making them suitable for harsh radiation environments such as space and nuclear applications. However, energetic ions can generate dense electron-hole pairs in the device, causing Single Event Effects (SEEs) that may result in functional degradation or catastrophic failure. Among these, Single Event Burnout (SEB) is a particularly serious failure mode in power devices and has been widely observed in SiC Schottky Barrier Diodes (SBDs) and MOSFETs [4, 5].

While SEB has been studied in various SiC devices, most previous work has focused on macroscopic failure modes such as breakdown or permanent degradation from localized damage. Fewer studies have examined the internal physical processes-particularly transient charge transport in the prompt phase following ion strikes-that trigger SEB. Better understanding of these processes is crucial for accurate modeling and robust design.

Heavy ion testing with particle accelerators is commonly used to study SEB, but such methods are limited by high cost, restricted beam access, and narrow energy options. As a more accessible and flexible alternative, tabletop pulsed-laser systems have been used to emulate ion-induced charge generation. While this method allows controlled and repeatable testing, most laser-based studies have only evaluated SEB indirectly-typically by measuring total collected chargewithout resolving the time evolution of carrier transport that leads to failure [6-8]. This is mainly because transient measurements under high-voltage bias conditions, as required for SiC power devices, are technically demanding due to the need for high-speed, high-voltage-capable measurement systems.

In this study, we developed a laser-based measurement system that enables both high time resolution and operation under high reverse bias. This allows direct observation of transient voltage waveforms resulting from laser-induced charge transport, providing new insight into SEB mechanisms in SiC power devices.

Sample Description

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

The test sample used in this study was a silicon carbide (SiC) Schottky Barrier Diode (SBD), model S6307 ( 1200 V,30 A ) from ROHM. To allow laser irradiation of the epitaxial layer (sensitive region) without damaging the front-side electrode structure, a 50μ m×50μ m window was fabricated on the backside ohmic electrode using focused ion beam (FIB) processing.

The chip carrier was designed with a laser-through hole, as illustrated in Fig. 1(a), to allow optical access to the backside of the mounted device. The SBD was mounted such that its backside window aligned precisely with this through hole, enabling focused laser light to reach the sensitive region from the bottom side. Electrical connections were made using short bonding wires to two 50 Ω strip-lines ( 10 GHz analog bandwidth), as shown in Fig. 1(b).

[picture]

Fig. 1. (a): Top view of the chip carrier with a laser-through hole. (b): Side view of the chip carrier with the SBD mounted and wire-bonded.

Fig. 1. (a): Top view of the chip carrier with a laser-through hole. (b): Side view of the chip carrier with the SBD mounted and wire-bonded.

Laser and Measurement Setup

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

A Single Event is triggered by the flow of electron-hole pairs generated within a device by the incidence of a single energetic ion. In this study, we emulate the generation of such electron-hole pairs using a pulsed laser. An overview of the developed measurement system is shown in Fig. 2. A 400 nm laser was used to induce two-photon absorption in the SiC epitaxial layer, thereby generating electron-hole pairs. This wavelength was obtained by frequency-doubling an 800 nm Ti:sapphire laser using a lithium triborate (LBO) nonlinear optical crystal. After exiting the LBO crystal, the laser beam passed through a neutral density (ND) filter to control the irradiation power,
then through a half mirror and an objective lens, which enabled precise adjustment of the focal depth within the device. The irradiation position was monitored using a CCD camera to ensure accurate alignment. The laser had a pulse width of 130 fs , a repetition rate of 1 kHz , and an incident power of 280μ W.

To capture the transient response of the device, a reverse bias voltage (ranging from 100 V to 900 V) was applied through a Bias Tee with a 10 GHz analog bandwidth. The resulting transient signals were recorded using a single-shot oscilloscope with a 15 GHz analog bandwidth. However, the overall analog bandwidth of the measurement system was limited to 10 GHz due to the combined bandwidth constraints of the Bias Tee and strip-line configuration.

[picture]

Fig. 2. Laser-based measurement setup for transient response detection. A 400 nm pulsed laser is focused onto the SiC SBD through optical components. Transient signals are measured via a highbandwidth circuit and captured by a 15 GHz oscilloscope.

Fig. 2. Laser-based measurement setup for transient response detection. A 400 nm pulsed laser is focused onto the SiC SBD through optical components. Transient signals are measured via a highbandwidth circuit and captured by a 15 GHz oscilloscope.

Experimental Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

Figure 3 shows transient voltage waveforms measured at reverse bias voltages of 300 V,500 V, and 900 V . To reduce high-frequency noise, each waveform was smoothed using a Savitzky-Golay filter. In all cases, the waveforms exhibit a sharp rising edge followed by an exponential decaytypical of ion-induced transient behavior in semiconductor devices. The rise time was approximately 10 ns across all bias conditions, whereas the temporal resolution of the measurement system was 35 ps , confirming that the system could capture the full transient behavior, which lasted about 50 ns . Furthermore, the peak amplitude increased with higher reverse bias, indicating more efficient charge collection under stronger electric fields. A small pre-peak was also observed before the main transient, possibly due to overshoot or reflection caused by the measurement system.

[picture]

Fig. 3. Transient voltage waveforms smoothed by a Savitzky-Golay filter.

Fig. 3. Transient voltage waveforms smoothed by a Savitzky-Golay filter.

Figure 4 illustrates the dependence of total collected charge on reverse bias voltage. The charge was calculated by integrating the transient voltage waveform over time, which represents the total amount of charge observed during the transient event. As reverse bias increased, total collected charge also increased. This is typically explained by the expansion of the depletion region under higher electric fields, which enhances charge collection efficiency.

Therefore, it can be inferred that the laser reached the vicinity of the depletion region and generated electron-hole pairs. This interpretation is consistent with the observation that larger current responses were recorded under higher bias, indicating efficient carrier collection.

[picture]

Fig. 4. The dependence of total collected charge on the reverse bias voltage.

Fig. 4. The dependence of total collected charge on the reverse bias voltage.

Although the total collected charge increases with higher reverse bias, this trend cannot be fully explained by the expansion of the depletion region. As shown in Fig. 5, C−V measurements indicate that the depletion width saturates at approximately 400 V . Therefore, additional mechanisms must be responsible for the continued increase in collected charge at higher voltages.

A likely mechanism is impact ionization in the high-field region, which can generate secondary carriers and thereby increase the total collected charge. This effect becomes more pronounced as the electric field approaches the threshold for initiating carrier multiplication. This interpretation is consistent with previous heavy-ion-induced charge-collection studies on SiC Schottky Barrier Diodes [4].

[picture]

Fig. 5. C-V characteristic of the ROHM S6307 [9].

Fig. 5. C-V characteristic of the ROHM S6307 [9].

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

In this study, we successfully developed a laser-based experimental system capable of operating under high-voltage bias conditions for silicon carbide (SiC) devices. While improvements in spatial resolution and impedance matching are still required, the system enabled time-resolved measurements of transient responses induced by laser-generated charge carriers within the sensitive region of the device.

The observed transient characteristics, including the dependence of the collected charge on reverse bias voltage, exhibited trends similar to those reported in ion-beam irradiation experiments. This consistency supports the utility of the proposed laser-based approach as a practical and flexible alternative for investigating Single Event Effects (SEEs), particularly Single Event Burnout (SEB), in SiC power devices.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

This work was partially supported by JSPS KAKENHI Grant Number JP25K08488.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.55.pdf

T. Ohshima, H. Itoh, and M. Yoshikawa, Effect of Gamma-Ray Irradiation on the Characteristics of 6H Silicon Carbide Metal-Oxide-Semiconductor Field Effect Transistor with Hydrogen-Annealed Gate Oxide, J. Appl. Phys. 90, p. 3038, (2001).

Y. Tanaka, S. Onoda, A. Takatsuka, T. Ohshima, and T. Yatsuo, Radiation Hardness Evaluation of SiC-BGSIT, Mater. Sci. Forum 645-648, p. 941, (2010).

A. Takeyama, T. Makino, Y. Tanaka, S. Kuroki, T. Ohshima, Threshold voltage instability and hysteresis in gamma-rays irradiated junction field effect transistors, J. Appl. Phys. 131 (24), (2022).

T. Makino, M. Deki, N. Iwamoto, S. Onoda, N. Hoshino, H. Tsuchida, T. Hirao, and T. Ohshima, Heavy-Ion Induced Anomalous Charge Collection from 4H-SiC Schottky Barrier Diodes, IEEE Trans. Nucl. Sci. vol. 60, p. 218, (2013).

E. Mizuta, S. Kuboyama, H. Abe, Y. Iwata and T. Tamura, Investigation of Single-Event Damages on Silicon Carbide (SiC) Power MOSFETs, IEEE Trans. on Nucl. Sci., vol. 61, no. 4, p. 1924, (2014).

R. A. Johnson, A. F. Witulski, D. R. Ball, K. F. Galloway, A. L. Sternberg, E. Zhang, L. D. Ryder, R.A. Reed, R. D. Schrimpf, J. A. Kozub, J-M. Lauenstein, and, A. Javanainen, IEEE Trans. Nucl. Sci., vol. 66, No. 7, p. 1694, (2019).

S. Shangguan, Y. Ma, J. Han, Y. Cui, Y. Wang, R. Chen, Y. Liang, X. Zhu, and Y. Li, Aluminium corrosion in power semiconductor devices, Microelectronics Reliability, vol. 125, article no. 114364, (2021).

European Space Agency, Single-Event Effects Testing with a Laser Beam - Guidelines, ESA Technical Note TN2, Rev. TN2, (2022).

S6307 Datasheet, ROHM semiconductor, .

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 61-69

doi: 10.4028/p-utjOw2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-09

Accepted:
2026-03-14

Online:
2026-05-20

Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

Zhaoxu Song a, Yu Tian b, Zheyuan Zhang c, Suyu Xu d, Xiangrui Fan e, Yiren Yu f, Jiaxing Wei g , Siyang Liu h  and Weifeng Sun i 

The National ASIC System Engineering Research Center, School of Integrated Circuits, Southeast University, China

a  songzhaoxu_jnu@163.com, b 230258710@ seu.edu.cn, c 220246617@ seu.edu.cn, d  213211362@seu.edu.cn, efanxiangrui@seu.edu.cn, f  yirenyu2000@163.com, g *  jiaxingwei@seu.edu.cn, h  liusy2017@seu.edu.cn, i  swffrog@seu.edu.cn

Keywords: resistance degradation, trench SiC MOSFETs, total ionizing dose (TID) effect, high drain voltage bias, positive charges accumulation.

Abstract

In this paper, the resistance degradation behaviors of double trench (DT) and asymmetric trench (AT) SiC MOSFETs under total ionizing dose (TID) effect and high drain voltage bias are investigated in detail. The output characteristics measurements before and after the irradiation indicate that the TID effect with high drain voltage bias increases the drain current, resulting in the On-state resistance degradation, whereas the high drain voltage bias seems to have no impact on the degradation. In particular, the DT SiC MOSFETs demonstrate a greater degree of degradation in comparison to the AT SiC MOSFETs under the same gate voltage. This phenomenon can be attributed to a more pronounced decline in the channel resistance. Simultaneously, the threshold voltage ( VTH ), the drain leakage current ( IDSS ), and the gate leakage current ( IGSS ) are also measured, which can be concluded that the resistance degradation is attributable to the VTH negative shifting induced by the positive charge accumulation in the gate oxide. Furthermore, the AT SiC MOSFETs have better irradiation tolerance owing to the P -shield asymmetric trench structure, exhibiting slight shift in the VTH, the IDSS, and the IGSS. Finally, the TCAD simulations are utilized to successfully verify the degradation mechanism.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

As one of the most promising semiconductor devices, the silicon carbide ( SiC ) metal-oxidesemiconductor field-effect-transistors (MOSFETs) have been widely used in power electronic fields [1], such as the on-board charger (OBC), the photovoltaic inverter, and the motor drive owing to the merits of wide bandgap, high breakdown voltage, high thermal conductivity, and high switch speed. Meanwhile, SiC MOSFETs demonstrate considerable promise as potential candidates for aerospace applications [2]. However, in the complex space environment, the irradiation effects [3,4,5] often result in the degradation of the devices' electrical characteristics, and even failure, leading to a reduction in operation time of spacecraft and property loss. Among all those reliability issues, the total ionizing dose (TID) effect has garnered significant attention and increasing researches focusing on it [6, 7]. In particular, the SiC MOSFETs have to withstand the combined effect of the TID effect and the high drain bias in the Off-state [8, 9, 10]. It is imperative to explore the degradation behaviors and mechanism of the SiC MOSFETs under TID effect and high drain voltage bias.

Due to the differences in the gate process, SiC MOSFETs are equipped with two distinct gate technologies: planar [11] and trench [12]. For the latter case, the double trench (DT) type and the asymmetric trench (AT) type are two typical products, which both eliminate the junction field effect transistor (JFET) region, thus possessing a higher power density and a lower On-state resistance. However, there are many reports claiming that the trench SiC MOSFETs are more susceptible to the TID effect [13, 14]. For instance, Z. Fu et al. discovered that the AT SiC MOSFETs exhibited a more pronounced negative shifting trend in the threshold voltage ( VTH ) compared to the planar SiC MOSFETs under the TID irradiation. R. Luo et al. calculated the reduction percentage of the On-state resistance ( RDSON  ) and revealed that the DT SiC MOSFETs have a higher resistance degradation rate.
J. Jiang et al. compared the electrical parameters degradation behaviors and the annealing responses of various devices, discovering that the TID effect exerts a profound influence on the trench structure. Indeed, the RDSON  is of considerable importance for the SiC MOSFETs among the literatures above, which has a strong relation with the current variations and irradiation tolerance capability. As a result, it is necessary to undertake a comprehensive evaluation of the resistance degradation and elucidate the mechanisms of the trench SiC MOSFETs under the TID irradiation with high drain bias condition.

In this work, the DT and the AT SiC MOSFETs are exposed to gamma ray irradiation with different drain biases to investigate the resistance degradation mechanism in detail. Firstly, the output characteristics at varying gate voltages are measured and the values of the main resistance components are calculated based on the measurements. It is evident that the DT SiC MOSFETs are profoundly affected by the TID effect owing to the severe degradation of the channel resistance. Subsequently, the VTH, the drain leakage current ( IDSS ), and the gate leakage current ( IGSS ) are measured. Their results demonstrate that the resistance degradation is induced by the positive charge accumulation, which is a consequence of gamma ray exposure. Furthermore, it has been demonstrated that the P -shield structure enhances the irradiation tolerance of AT SiC MOSFETs, which is attributable to the low level of the leakage current. Finally, the TCAD simulations have been employed to successfully verify the degradation mechanism.

Experiment Conditions

The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

In this experiment, commercial 160 mΩ DT and 140 mΩ AT SiC MOSFETs with the breakdown voltage over 1200 V are selected as the samples and they are TO-247-3 packaged. Fig. 1 shows the schematic cross sections of the DT and the AT structure. Moreover, the Cobalt-60 (Co 60 ) gamma-ray at a dose rate of 100rad(Si)/s is adopted as the irradiation source. The irradiation dose is set to 600krad(Si) to imitate the devices' operating situation over years in the space environment considering that the dose rate is about 0.01rad(Si)/s near the Earth orbit. The detailed irradiation and bias conditions for the samples are listed in Table 1. Three samples are selected for each group during the irradiation so that possible deviations among devices could be minimized and hence we can obtain a credible result. Prior to the gamma ray irradiation, the electrical parameters ( VTH,IDSS,IGSS ) are measured, and the post-irradiation measurements are also completed within 24 hours. The device parameters for simulations are given in Table 2.

[picture]

Fig. 1. Schematic cross section of (a) the DT, and (b) the AT SiC MOSFET.

Fig. 1. Schematic cross section of (a) the DT, and (b) the AT SiC MOSFET.

[picture]

Fig. 1. Schematic cross section of (a) the DT, and (b) the AT SiC MOSFET.

Fig. 1. Schematic cross section of (a) the DT, and (b) the AT SiC MOSFET.

Table 1. Irradiation and Drain Voltage Bias Conditions.

Type | TID(krad(Si)) | Drain Voltage Bias (V)
|  | 600 | 800 | 1000
DT | 600 | Sample A1 | Sample B1 | Sample C1
AT | 600 | Sample A2 | Sample B2 | Sample C2

Table 2. Device Parameters for the Simulation.

Symbol | Device Parameter | Value
|  | DT | AT
LCH | Length of channel | 0.34 μm | 0.34 μm
WCELL | Width of Cell | 3.6 μm | 2.7 μm
WN+ | Width of N+ | 0.76 μm | 0.5 μm
WP+ | Width of P+ | 0.2 μm | 0.5μm(left)/1.3μm(right)
WP-base | Width of P-base | 1.26 μm | 0.5 μm
WGate | Width of Gate | 1 μm | 0.6 μm
WOHM | Width of Ohm Contact | 0.9 μm | 0.8 μm
TS-Oxide | Thickness of Side Oxide | 50 nm | 50 nm
TB-Oxide | Thickness of Bottom Oxide | 150 nm | 150 nm
DP+ | Depth of P+ | 0.3 μm | 1.5 μm
DP-base | Depth of P-base | 1.3 μm | 0.34 μm

Results and Discussions

The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

In this part, the electrical characteristics are measured in order to calculate the values of resistance variations and to further obtain the degradation mechanism. Meanwhile, TCAD simulations are used to validate the degradation behaviors with these measurements. As illustrated in Fig. 2, the output characteristics results of the DT and AT samples are presented. It is observed that the gamma ray irradiation leads to an augmentation in the drain current ( IDS ), especially for the DT samples, exhibiting a more severe degradation trend. Concurrently, the drain voltage bias exerts no impact on the IDS. Notably, when the gate source voltage ( VGS ) is 12 V , the IDS has a drastic increase for the samples A1, B1, and C 1 , while it has a slight increase for the samples A2, B2, and C 2 . Apparently, the TID effect degrades these samples' RDSON , but the degree of degradation is different.

[picture]

Fig. 2. Output characteristics results of the DT samples at (a) VDS=600 V, (b) VDS=800 V, (c) VDS=1000 V, and the AT samples at (d) VDS=600 V, (e) VDS=800 V, (f) VDS=1000 V with 600krad(Si) irradiation.

Fig. 2. Output characteristics results of the DT samples at (a) V D S = 600 V , (b) V D S = 800 V , (c) V D S = 1000 V , and the AT samples at (d) V D S = 600 V , (e) V D S = 800 V , (f) V D S = 1000 V with 600 k r a d ( S i ) irradiation.

In order to compare the RDSON  degradation behaviors between the DT samples and the AT samples, the On state resistance variations ( ΔRDSON ) are calculated, as shown in Fig. 3. On the one hand, all the samples' ΔRDSON  decreases as the VGS  increases, on the other hand, the DT samples' ΔRDSON  consistently exceeds that of the AT samples. In fact, with the increase of the VGS, the proportion of channel resistance begins to decrease, and the proportion of drift region resistance begins to increase. Furthermore, the drift region resistance is typically associated solely with the doping concentration and thickness. Based on these results, it can be inferred that the increase in the IDS is attributable to the channel resistance variation. As a result, the following equations are used to calculate the main resistance component as

RDSON≈RCH1,VGS=6 V,RDSON≈RCH2+RD,VGS=12 V,RDSON≈RD,VGS=18 V.

(1)(2)(3)

Here, RCH1 is the channel resistance when the VGS is 6 V,RCH2 is the channel resistance when the VGS is 12 V,RD is the drift region resistance. In Eq. 1, the channel just opens a little, leading to the channel resistance to be almost equal to the RDSON . After selecting the same drain source voltage ( VDS ), the values of the channel resistance have been calculated, i.e., RCH1, for the DT and AT samples. In Eq. 2, the channel opens partially. Therefore, the RDSON  can be calculated as the sum of the channel resistance RCH2 and the RD. In Eq. 3, the channel opens completely, making the RD occupy a high proportion, which is almost equal to the RDSON. After that, the values of the RCH1, the RCH2, and the RD are successfully obtained and depicted in Fig. 4 . It is easy to find that a remarkable decline occurs in the RCH1 and the RCH2 before and after the gamma ray irradiation. Specifically, the RCH1 and the RCH2 decrease 89% and 61% in the DT samples, while they decrease 57% and 21% in the AT samples. The RD has rarely changed during the irradiation. These calculated results suggest that the main reason for the RDSON  degradation is the channel resistance.

In a word, the RDSON  degradation of the DT samples and the AT samples both are caused by the reduction of the channel resistance induced by the gamma ray irradiation. In particular, the channel resistance of the DT samples has an obvious decrease trend compared to that of the AT samples under the same irradiation with drain bias condition, which leads to the variations in their IDS .

[picture]

Fig. 3. ΔRDSON results of the DT, and the AT samples before and after the TID irradiation.

Fig. 3. Δ R D S O N results of the DT, and the AT samples before and after the TID irradiation.

[picture]

Fig. 4. Resistance Component of the DT, and the AT samples before and after the TID irradiation.

Fig. 4. Resistance Component of the DT, and the AT samples before and after the TID irradiation.

Subsequently, the VTH, the IDSS, and the IGSS results are shown in Figs. 5-7. Fig. 5 illustrates that the TID effect damages the channel region of the DT and AT samples by introducing the positive charges into the gate oxide. In particular, the DT samples not only exhibit more heavily negative shifting than the AT samples, but also result in more current increase and the resistance decrease. In addition, the threshold voltage variations ( ΔVTH ) results are listed in Table 3, the ΔVTH of the DT samples is four times larger than that of the AT samples, indicating that the channel region of the DT samples is severely damaged. The VDS  also has no obvious impact on their ΔVTH , which is the same as their variation in the IDS .

[picture]

Fig. 5. Transfer characteristics of (a) the DT, and (b) the AT samples before and after the TID irradiation.

Fig. 5. Transfer characteristics of (a) the DT, and (b) the AT samples before and after the TID irradiation.

Table 3. Threshold Voltage Variation.

Type | ΔVTH(V)
| VDS=600V | VDS=800V | VDS=1000V
DT | -1.87799 | -1.99437 | -2.0003
AT | -0.42214 | -0.5229 | -0.52483

Meanwhile, the IDSS results are depicted in Fig. 6. Although the breakdown voltage of the DT and AT samples rarely shift after the TID irradiation, the IDSS  in DT samples has increased by four orders of magnitude in comparison with the fresh device. In contrast, the AT samples maintain a low IDSS  because of the minor fluctuations in the VTH . Moreover, Fig. 7 shows that there is no obvious change
in the IGSS for both of the DT and AT samples after the TID irradiation, because the IGSS still remains at nA or pA level. The IGSS  of the DT and AT samples demonstrate insensitivity to the TID effect and the drain voltage bias. Notably, the AT samples invariably maintain an ultra-low IGSS  before and after the TID effect experiments, which can be attributed to the P-shield trench structure. This illustrates that the AT samples have better irradiation tolerance capability to the TID effect.

[picture]

Fig. 6. Measured curves of IDSS−VDS of (a) the DT, and (b) the AT samples before and after the TID irradiation.

Fig. 6. Measured curves of I D S S − V D S of (a) the DT, and (b) the AT samples before and after the TID irradiation.

[picture]

Fig. 7. Measured curves of IGSS−VGS of (a) the DT, and (b) the AT samples before and after the TID irradiation.

Fig. 7. Measured curves of I G S S − V G S of (a) the DT, and (b) the AT samples before and after the TID irradiation.

Finally, the TCAD simulations are performed to imitate the gamma ray irradiation process. The simulation results are presented in Figs. 8-10. It is observed that the TID effect introduces the holes into the gate oxide, producing the positive charges accumulation and thereby leading to the open of the channel, as shown in Fig. 8. In particular, Fig. 9 shows that the irradiation makes the current path change from the PN junction to the channel when the body diode (BD) of the DT samples is conducting in the forward direction, and the current density of the channel is much higher than that of the BD. Therefore, the DT sample's current density increases compared to the original one. Furthermore, the DT structure exhibits a more obvious increase trend in the total current density than the AT structure under the same irradiation and bias conditions based on Fig. 10. These simulations have good agreements with the measurements, proving the correctness of the mechanism.

[picture]

Fig. 8. Simulated trapped hole concentration of the DT, and the AT SiC MOSFET before and after the TID irradiation with drain voltage bias.

Fig. 8. Simulated trapped hole concentration of the DT, and the AT SiC MOSFET before and after the TID irradiation with drain voltage bias.

[picture]

Fig. 9. Simulated body diode current density of the DT SiC MOSFET before and after the TID irradiation with drain voltage bias.

Fig. 9. Simulated body diode current density of the DT SiC MOSFET before and after the TID irradiation with drain voltage bias.

[picture]

Fig. 10. Simulated total current density of (a) the DT, and (b) the AT SiC MOSFET before and after the TID irradiation with drain voltage bias.

Fig. 10. Simulated total current density of (a) the DT, and (b) the AT SiC MOSFET before and after the TID irradiation with drain voltage bias.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

The resistance degradation of the DT and the AT SiC MOSFETs exposed to the gamma ray irradiation with the high drain voltage bias is discussed in this work. The electrical characteristics results before and after the irradiation suggest that the reduction of their On-state resistance has a strong relation with their channel resistance. Especially, the degradation degree of DT sample on the RCH1 is more than 1.5 times that of AT sample, while the degradation degree on the RCH2 is almost 3 times that of AT samples based on the resistance component calculation, demonstrating that the channel resistance of the DT samples is more severely degraded. Besides, the ΔVTH of the AT sample
before and after the irradiation is reduced by an order of magnitude compared to the DT samples and they are still maintaining ultra-low leakage current, proving that the P+ shield structure has better irradiation resistance to the TID effect. Ultimately, the simulation successfully imitates the irradiation and thereby verifies the degradation mechanism. Such an experiment has important guiding significance for the life assessment of the long-term operating devices in the space.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

This work was supported in part by the National Natural Science Foundation of China under grants 62574042, 62434002, and U25B2059; in part by the Fundamental Research Funds for the Central Universities under grant 2242024RCB0028; in part by the Science and Technology Major Project of Jiangsu Province under grant BG2024001; in part by the Fund for Transformation of Scientific and Technological Achievements of Jiangsu Province under grant BA2023001; in part by the Natural Science Foundation of Jiangsu Province under grant BK20232027; and in part by the Distinguished Young Scientists Foundation of Jiangsu Province under grant BK20230025.

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The original version of this paper is available on https://www.scientific.net/KEM.1056.61.pdf

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 71-77

doi: 10.4028/p-sHt91V

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-21

Accepted:
2026-02-28

Online:
2026-05-20

Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1056.71.pdf

V. Kotagama 1,a*, A. B. Renz 1,b, K. Melnyk 1,c, Z. Yuan 1,d, V. Kilchytska 2,e, D. Flandre 2,f, V. A. Shah 1, g, M. Antoniou 1, h, P. M. Gammon 1,i

1 School of Engineering, University of Warwick, Coventry, UK

2 ICTEAM, UCLouvain, Louvain-la Neuve, Belgium

a* Viren.Kotagama@warwick.ac.uk, b Arne.Renz@warwick.ac.uk, c Kyrylo.Melnyk@warwick.ac.uk, d  ZHAOXUE.YUAN@warwick.ac.uk, e  valeriya.kilchytska@uclouvain.be, f denis.flandre@uclouvain.be, g Vishal.Shah@warwick.ac.uk, h Marina.Antoniou@warwick.ac.uk, iP.M.Gammon@ warwick.ac.uk

Abstract

Cumulative heavy-ion irradiation effects were investigated in a commercial 4H−SiC double trench MOSFET through a combination of cyclotron experiments and TCAD simulations. Devices were exposed to continuous 124Xe35+ ion strikes at a linear energy transfer (LET) of 63MeV·cm2/mg under drain biases from 100 to 400 V . Experimental results revealed the onset of permanent drain and gate leakage at voltages as low as 200 V , with degradation rates increasing by several orders of magnitude at higher bias. Post-irradiation measurements confirmed trench oxide rupture and source leakage path formation, establishing single-event leakage current (SELC) as the dominant degradation mechanism. In contrast, TCAD simulations of isolated ion strikes predicted catastrophic single-event burnout (SEB) only at or above 250−300 V, highlighting the critical role of cumulative damage processes that are not captured in single-strike models. These findings demonstrate that permanent leakage-driven degradation effectively extends the SELC zone beyond conventional SEB thresholds, reducing the safe operating area of trench-based SiC MOSFETs. The results have significant implications for derating strategies in space applications, where current SEB-focused guidelines may underestimate vulnerability, and highlight the need for radiation-hardening by device design to ensure long-term reliability.

Keywords: 4H−SiC, space, reliability, single-event effect, radiation, commercial, MOSFET.

Introduction

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Wide bandgap (WBG) semiconductors such as 4 H -silicon carbide (SiC) have become critical enablers for next-generation high efficiency, temperature, and voltage power electronics. Compared to silicon (Si), SiC offers a critical electric field nearly an order of magnitude higher, a threefold higher thermal conductivity, and superior electron saturation velocity [1]. These material advantages allow SiC devices to operate with thinner drift layers and higher blocking voltages, enabling compact devices with lower conduction and switching losses. Consequently, SiC metal -oxide-semiconductor field effect transistors (MOSFETs) are increasingly displacing Si insulated gate bipolar transistors (IGBTs) in the 650−1700 V range, particularly in applications demanding high efficiency and fast switching.
Among SiC device topologies, the double trench MOSFET has emerged as a commercially relevant architecture due to its compact cell pitch and ability to shield the gate oxide from peak electric fields. Narrow cell geometries reduce specific on-resistance and chip area, while the lower gate configuration minimizes switching losses and provides resilience under fault conditions [2]. These advantages make trench MOSFETs attractive candidates for space systems, where efficiency directly translates into lower power budgets, reduced thermal management requirements, and decreased payload weight.
Despite these benefits, SiC power devices face significant challenges when exposed to the radiation environment of space, where single-event effects (SEE) induced by heavy ions or cosmic particles can compromise long-term reliability. The majority of qualification strategies have focused on
preventing single-event burnout (SEB), a catastrophic mode of failure driven by localized avalanche breakdown and thermal runaway. Therefore, literature derating guidelines for SiC space applications typically emphasize maintaining safe operating voltages well below the SEB threshold [3,4].
However, growing evidence suggests that cumulative SEE-induced degradation may occur well before catastrophic burnout, particularly in trench-based structures. SiC devices in space can be exposed to heavy-ion fluences exceeding 107 particles /cm2 with LET values above 60MeV·cm2/mg over the course of a 10 -year mission, making repeated strike effects a realistic concern [5]. Recent studies have documented the onset of single-event leakage current (SELC), defect generation, and gradual trench degradation under continuous irradiation [6-8]. These mechanisms may result in permanent leakage paths, compromised blocking capability, or degraded gate insulation - failure modes that do not manifest as immediate device destruction but can still render the component unsuitable for mission use. This evolving understanding challenges the adequacy of SEB-focused derating strategies for WBG devices.
In this work, we investigate cumulative SEE degradation in a commercial 4H−SiC double trench MOSFET through a combination of cyclotron irradiation experiments and Sentaurus TCAD simulations. Devices were subjected to continuous 124Xe35+ ion strikes at linear energy transfer (LET) of 63MeV·cm2/mg, across a range of drain bias voltages. Experimental results reveal the progressive development of drain and gate leakage currents at voltages as low as 200 V , indicating the presence of permanent structural damage to both source and gate trenches. Complementary TCAD simulations reproduce transient strike dynamics, including current surges and local lattice heating, and help identify the vulnerable device features most responsible for degradation. By isolating the onset of cumulative degradation and contrasting experimental outcomes with simulated SEB thresholds, this study provides new insights into failure precursors in SiC trench MOSFETs.

Methodology

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The device selected for this study was a commercially available 750 V SiC double trench MOSFET. The trench-gate structure features a compact cell pitch with deep gate and source trenches, offering both conduction efficiency and oxide field shielding [2]. Prior to irradiation, the device underwent baseline electrical characterization to establish transfer characteristics and leakage behaviour, ensuring that subsequent degradation could be attributed solely to irradiation.
Heavy-ion experiments were carried out at the UCLouvain Cyclotron Facility, using a beam of 124Xe35+ ions with a LET of 63MeV·cm2/mg. and ion penetration depth of approximately 73μ m in 4H−SiC, sufficient to traverse the full active region of the device. Devices were mounted in a vacuum chamber and biased in the off-state across a drain-source voltage range of 100 to 400 V while subjected to a constant ion flux, thereby replicating the conditions of repeated single-event strikes. The device testing board consisted of current limiting resistors placed on gate and drain side to protect the respective SMUs in case of explosive breakdown of the MOSFET under test, while a 1 nF coupling capacitor is used to ensure correct constant voltage biasing while the device is actively bombarded with heavy ion flux. These components are selected according to ESA standards for single-event effect testing [9]. Real-time monitoring of gate and drain leakage currents was performed throughout irradiation, allowing progressive degradation trends to be identified. Following irradiation, full current-voltage sweeps were repeated, including gate-source and drain-source leakage tests, as well as transfer measurements, to quantify permanent shifts in device behaviour. The total active flux seen by the device is calculated by the device active area of 6×10−6 m2.

[picture]

Fig. 1. Heavy ion board circuit schematic for commercial device testing.

Fig. 1. Heavy ion board circuit schematic for commercial device testing.

Complementary single-event simulations were performed in Synopsys Sentaurus TCAD to compare the experimental conditions and isolate the underlying failure mechanisms. The simulated device structure was previously benchmarked and validated in a prior study [10], reproducing the key geometrical and doping profiles of the epitaxial drift layer, source/body regions, and trench oxides. The key parameters of the simulated device can be seen in table.1. Heavy-ion strikes were modelled as Gaussian electron-hole pair generation along a cylindrical track, calibrated to the experimental LET and penetration depth. Strike locations were varied at two key points of vulnerability: 1) at the gate trench and 2) at the source trench to examine the relative susceptibility of these regions, seen in Fig.2. Transient simulations were carried out with a time step up to 1 ns after heavy ion impact, capturing the resulting current surges and lattice temperature evolution under drain biases from 10−400 V.
This combined methodology enabled direct correlation between experimental degradation phenomena and simulated single-event dynamics, providing a framework to interpret the onset of leakage-dominated failure modes in the double trench architecture.

Table 1. Summary of key device design geometry and parameters.

Symbol | Definition | Values | Units
tCSL | Charge storage layer thickness | 2.6 |
tcell | Cell pitch | 2 | μm
tsub | Substrate thickness | 140 |
td | Drift region thickness | 6.8 |
NCSL | Charge storage layer doping | 5×10¹⁶ |
Nd | Drift region doping | 1.5×10¹⁶ | cm³
Nsub | Substrate doping | 1×10¹⁹ |
Vth | Threshold Voltage | 4.81 | V
Ron,sp | Specific on-resistance | 1.69 | mΩ.cm²
BVmax | Max. Breakdown Voltage | 1001 | V

Experimental Results

The original version of this paper is available on https://www.scientific.net/KEM.1056.71.pdf

The progressive evolution of leakage currents in the double trench MOSFET during cumulative heavy-ion irradiation is illustrated in Fig.3. At drain biases up to 150 V , the device exhibits stable behaviour with no measurable increase in gate or drain leakage. However, from 200 V onwards, degradation became apparent. Successive irradiation under these conditions results in a permanent rise in both gate and drain leakage currents, reaching values of approximately 140 nA and 120μ A, respectively, at the end of the exposure sequence ( 400 V ). This behaviour is consistent with SELC phenomena reported in modern literature [6-8].

[picture]

Fig. 3. Experimental drain and gate leakage currents of the commercial double trench MOSFET under cumulative heavy ion strikes at increasing blocking voltage (100 to 400 V ).

Fig. 3. Experimental drain and gate leakage currents of the commercial double trench MOSFET under cumulative heavy ion strikes at increasing blocking voltage (100 to 400 V ).

Even at lower 'safe operating' voltages there is device failure via the formation of permanent leakage pathways within the trench regions. One possible explanation for why there is no instantaneous destruction of the device could be due to the continuous heavy-ion irradiation flux. This creates a continuous high electric field beneath the gate, promoting charge trapping and gradual oxide degradation, forming leakage paths across the dielectric. This pre-damaged path allows charge dissipation at high voltages, limiting field build-up and preventing full SEB despite reaching the simulated burnout threshold. The comparison with a commercial diode response at the same experimental conditions in Fig. 4 further emphasises this point: whereas the diode undergoes abrupt SEB with no intermediate degradation region, the trench MOSFET demonstrates progressive leakagedominated failure. This suggests that oxide-influenced SELC is the primary limiting factor in trenchbased structures.
The degradation rate extracted from cumulative irradiation testing is shown in Fig. 5, highlighting the increase in both drain and gate leakage pathways as a function of blocking voltage with each ion strike. At drain biases below 150 V , the degradation rate remains negligible, consistent with the absence of measurable leakage shifts in real-time monitoring. However, from 200 V upwards, both drain and gate degradation rates increase

[picture]

Fig. 4. Experimental leakage currents of a commercial diode under cumulative heavy ion strikes at increasing blocking voltage (100 to 200 V ), showing clear SEB.

Fig. 4. Experimental leakage currents of a commercial diode under cumulative heavy ion strikes at increasing blocking voltage (100 to 200 V ), showing clear SEB.

This behaviour indicates that permanent SELC damage effectively extends the safe operating area of the device into regions traditionally considered safe by SEB-based derating guidelines. In conventional singleevent frameworks, the catastrophic burnout threshold defines the boundary of device survival. By contrast, in this device architecture, cumulative trench degradation introduces a zone of permanent leakage
growth that precedes burnout, thereby reducing the effective safe operating area. In other words, even when catastrophic SEB is not triggered, the accumulation of SELC damage erodes device reliability at voltages well below the expected burnout threshold.
The manifestation of this cumulative degradation is further examined through post-irradiation I-V measurements. As shown in Fig.6, the pre-irradiation condition of the commercial MOSFET exhibits only a small leakage path dominated by the gate-drain overlap region. Following irradiation, a dramatic increase is observed, with both the gatesource and gate-drain characteristics rising

[picture]

Fig. 5. Degradation rate (A/ions) of a) drain and b) gate of the commercial MOSFET with response to increasing blocking voltage (100 to 200 V ).

Fig. 5. Degradation rate (A/ions) of a) drain and b) gate of the commercial MOSFET with response to increasing blocking voltage (100 to 200 V ).

Despite the clear trench rupture seen in Fig.6, the pre- and post-irradiation comparison of the transfer response in Fig. 7 shows channel functionality. While the on-state current was reduced, the overall transconductance profile remained recognisable, demonstrating that gate control was not fully compromised. The most likely explanation is that rupture occurred locally within specific trench regions, rather than uniformly across the active area, leaving enough intact channel area for the device to sustain limited functionality.

[picture]

Fig. 6. Comparison of pre- and post-irradiation gate-drain and gate-source leakage current with gate-source voltage sweep between -5 to 20 V at Vd=0 V.

Fig. 6. Comparison of pre- and post-irradiation gate-drain and gate-source leakage current with gate-source voltage sweep between -5 to 20 V at V d = 0 V .

[picture]

Fig. 7. Comparison of pre- and postirradiation drain current with gate-source voltage sweep between 0 to 12 V at Vd= 10 V .

Fig. 7. Comparison of pre- and postirradiation drain current with gate-source voltage sweep between 0 to 12 V at V d = 10 V .

Simulation Results

The original version of this paper is available on https://www.scientific.net/KEM.1056.71.pdf

To interpret the experimental degradation phenomena, transient single-event simulations were performed using the double trench MOSFET structure benchmarked against previously validated models. Throughout the simulations, the peak electric field was monitored during heavy ion strike, with the device not reaching the critical electric field at any blocking voltage up to 400 V .

Fig. 8 shows the transient drain current induced by a single heavy-ion strike under different blocking voltages. At all blocking voltages 10−400 V, the ion strike produces a sharp current surge, which persists for several nanoseconds before decaying, irrespective of blocking voltage and heavy ion location (gate or source). However, the peak source current rises with blocking voltage, approaching 60 mA at 400 V . By contrast, the monitored gate current transient seen in Fig. 9 shows minimal impact change at all blocking voltages. However, the gate heavy ion strike does increase the peak gate current by an order of magnitude due to the more charge being swept through the gate terminal. The rise in lattice temperature is the biggest indicator of thermal runaway within the device. In Fig.10, the simulated SEB threshold is 250 V for a source strike and 300 V for a gate strike. This is due to the more active sweep of charge through the gate terminal in the event of a gate strike. In the heavy ion events below the SEB threshold, the device temperature begins to reduce without thermal runaway, consistent with conventional single-strike expectations. This divergence highlights a key discrepancy: while simulations predict burnout only at or above 250 V , experimental results revealed permanent leakage degradation already at 200 V .
The difference suggests that cumulative irradiation effects, mainly progressive oxide weakening and localized trench damage, reduce the effective failure threshold in practice. Because the present simulations model single isolated strikes, they do not capture the gradual degradation pathways observed experimentally. Nevertheless, the simulations identify the gate and source trenches as the most critical regions of vulnerability, supporting the interpretation that trench oxide rupture and source leakage paths govern the observed experimental failure modes.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1056.71.pdf

This work has demonstrated that cumulative heavy-ion irradiation

[picture]

Fig. 8. Simulated 124Xe35+ ion strike response for source leakage current at varying reverse bias voltage (10 to 400 V ).

Fig. 8. Simulated 124 X e 35 + ion strike response for source leakage current at varying reverse bias voltage (10 to 400 V ).

[picture]

Fig. 9. Simulated 124Xe35+ ion strike response for gate leakage current at varying reverse bias voltage (10 to 400 V ).

Fig. 9. Simulated 124 X e 35 + ion strike response for gate leakage current at varying reverse bias voltage (10 to 400 V ).

[picture]

Fig. 10. Simulated 124Xe35+ ion strike response for rise in lattice temperature from 300 K at varying reverse bias voltage ( 10 to 400 V ).

Fig. 10. Simulated 124 X e 35 + ion strike response for rise in lattice temperature from 300 K at varying reverse bias voltage ( 10 to 400 V ).

commercial 4H−SiC double trench MOSFET, even at drain biases well below the simulated burnout threshold. Experimental testing revealed the onset of permanent drain and gate leakage at 200 V , with degradation rates increasing sharply at higher voltages. Post-irradiation measurements confirmed trench oxide rupture and source leakage path formation, establishing single-event leakage current SELC as the dominant degradation mode in this architecture.
Sentaurus TCAD simulations reproduced the transient current and thermal response of individual heavy-ion strikes, predicting catastrophic burnout only at or above 250−300 V. The divergence between simulation and experiment highlights the importance of cumulative irradiation effects, such as progressive oxide damage, which are not captured by single-strike models. Together, these findings confirm that the gate and source trenches are the most vulnerable features in double trench MOSFETs and that oxide-mediated SELC damage can extend the effective degradation zone beyond conventional SEB thresholds.
The implications for space applications are significant. Conventional derating strategies based solely on SEB thresholds may overestimate the safe operating area of trench-based SiC MOSFETs, as permanent leakage-driven damage can accumulate under realistic ion fluences long before catastrophic burnout occurs. Therefore, this work further supports the ongoing literature that derating strategies must be re-defined to better predict long-term reliability in space environments, and radiation-hardening by device design is required to push SiC into this market.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.71.pdf

X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, "Review of silicon carbide power devices and their applications," IEEE Transactions on Industrial Electronics, vol. 64, no. 10, pp. 81938205, 2017.

P.M.Gammon. "Rohm Gen 4: a Technical Review." .

J. L. Titus, "An updated perspective of single event gate rupture and single event burnout in power MOSFETs," IEEE Transactions on nuclear science, vol. 60, no. 3, pp. 1912-1928, 2013.

A. Witulski et al., "Single-event burnout of SiC junction barrier Schottky diode high-voltage power devices," IEEE Transactions on Nuclear Science, vol. 65, no. 1, pp. 256-261, 2017.

W. Atwell, S. Koontz, and E. Normand, "Practical applications of cosmic ray science: Spacecraft, aircraft, ground based computation and control systems, and human health and safety," in AIP Conference Proceedings, 2013, vol. 1516, no. 1: American Institute of Physics, pp. 107-116.

C. Martinella et al., "Heavy-ion effects in SiC power MOSFETs with trench-gate design," IEEE Transactions on Nuclear Science, vol. 71, no. 8, pp. 1440-1446, 2024.

C. Martinella et al., "Heavy-ion microbeam studies of single-event leakage current mechanism in SiC VD-MOSFETs," IEEE Transactions on Nuclear Science, vol. 67, no. 7, pp. 1381-1389, 2020.

H. G. de Medeiros et al., "Exploring the relation between SEEs caused by heavy-ion irradiation and defects in SiC devices," IEEE Transactions on Nuclear Science, 2025.

ESCC, "Single event effects test method and guidelines, ESCC Basic Specification No. 25100," ed.

K. Melnyk, P. M. Gammon, A. B. Renz, Q. Cao, V. A. Shah, and M. Antoniou, "Analysis and Performance Trade-Offs of State-of-the-Art 4H-SiC Trench MOSFET Technology," in 2024 IEEE Energy Conversion Congress and Exposition (ECCE), 2024: IEEE, pp. 6764-6770.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 79-83

doi: 10.4028/p-pv3S4F

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-25

Accepted:
2026-01-31

Online:
2026-05-20

Masayuki Yamamoto 1,2,a*, Takanori Amamiya 1,2, b, Akinori Takeyama 3,c, Ryuya Hirose 1,2, d, Mikihiro Yuzuriha 1,2,e, Koji Nakayama 1,f, Hitoshi Umezawa 1, g, Takeharu Kuroiwa 1, h, Takahide Sato 2,i, Takahiro Makino 3,j, Takeshi Ohshima 3,k, Shin-Ichiro Kuroki 4,l and Yasunori Tanaka 1, m

1 Advanced Power Electronics Research Center (ADPERC), National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan

2 Deptartment of Electrical and Electronic Engineering, University of Yamanashi, Kofu, Japan 3 National Institute for Quantum Science and Technology (QST), Takasaki, Japan

4 Research Institute for Semiconductor Engineering (RISE), Hiroshima University, HigashiHiroshima, Japan

ª*yamamoto.masayuki@aist.go.jp, bt.amamiya@aist.go.jp, ctakeyama.akinori@qst.go.jp, d  hirose-ryuya@aist.go.jp, e  g24te023.yuzuriha@aist.go.jp, f  koji.nakayama@aist.go.jp, g  hitoshi.umezawa@aist.go.jp, h  kuroiwa.takeharu@aist.go.jp, 'takahides@yamanashi.ac.jp, j makino.takahiro@qst.go.jp, k ohshima.takeshi@qst.go.jp, 'skuroki@hiroshima-u.ac.jp, myasunori-tanaka@aist.go.jp

Keywords: SiC, JFET, operational amplifier, gamma ray, wide bandgap semiconductors, integrated circuit, harsh environment.

Abstract

In this study, we conducted in-situ measurements on a SiC JFET operational amplifier operating under gamma-ray irradiation. It shows that the radiation did not affect the output waveform or voltage gain, but shifted the output offset voltage. This shift may result mainly from holes generated by irradiation and trapped in the oxide layer, which modified the I-V characteristics of the level-shifting diodes. It can be compensated by applying bias voltage, and it may also be prevented by optimizing the diode structure and/or circuit topology.

In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

Silicon carbide (SiC) is recognized for its outstanding material properties, including high thermal conductivity, high breakdown electric field, and radiation hardness [1]. These attributes make SiC devices promising candidates for next-generation electronics in extreme environments such as aerospace missions and nuclear instrumentation systems. Recent advances have enabled the fabrication of SiC-based MOSFETs, JFETs, and ICs with high temperature and radiation tolerance [2-4]. However, only a few studies have investigated irradiation effects in operating conditions [5,6]. For circuits deployed in actual systems, operation under irradiation is inevitable, and understanding real-time behavior is critical for ensuring stable performance.

In this work, we performed in-situ characterization of a SiC JFET operational amplifier during γ ray irradiation. The results indicate that while the irradiation had no observable effect on the output waveform or voltage gain, it caused a shift in the output offset voltage. This shift is attributed primarily to irradiation-induced holes trapped in the oxide layer, which alter the I-V characteristics of the level-shifting diodes. The offset shift can be effectively compensated by adjusting the bias voltage and may be mitigated in future designs through optimization of the diode structure and/or circuit topology.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

The SiC JFET was fabricated using ion implantation to form a stripe-shaped n-type channel region surrounded by p+-type gate regions in n - epitaxial layer ( 3×1016 cm−3,5μ m ) [7]. Figure 1(a) and (b) show the schematic draw of our lateral n-type SiC JFET and the SEM cross-sectional image of the channel region. Figure 1(c) and (d) show the transfer and output characteristics, respectively. The device operates in normally-on mode, with a threshold voltage of -3.7 V . At VGS=0 V and VDS=10 V, the transfer conductance is about gm≅30μ S while the output resistance ro≅5MΩ. Their product gives the maximum voltage gain in the common source amplifier, that is Avmax=gmro≅150.

As shown in Figure 2(a), the operational amplifier consists of three stages: differential input stage, gain stage, and source-follower output stage (buffer stage). Normally-on JFETs with gate-source short connections were used as current sources and active resistors, while PN junction diodes served as level shifters. To facilitate stage-by-stage evaluation, each stage was wire-bonded and connected to external pads on the package, avoiding multilayer interconnects (Fig. 2(b)).

Figure 2(c) shows the Bode plot, i.e., the voltage gain and phase as a function of frequency, for the gain stage, where the supply voltages are set to be VDD=20 V and VSS=−20 V, the bias voltage VBias2  to be from -14 V to -15 V , and the input signal amplitude is 0.1 V . The DC gain is about 35 dB and the cutoff frequency is around 1 kHz . Red and light blue marks show the data obtained before irradiation and after the total dose of 50 kGy . It shows that the properties are unchanged.

[picture]

Fig. 1. (a) Schematic draws of the lateral n-type SiC JFET. Left: cross-sectional view. Right: top view. (b) Cross-sectional SEM image of SiC JFET channels. (c) Transfer characteristics of a normally-on SiC JFET at VDS=10 V. Solid and dotted lines indicate linear (right axis) and log (left axis) plots, respectively. The drain current at VGS=0 V is about 45μ S. (d) Output characteristics of a normally-on SiC JFET from VGS=−3 V to 1 V .

Fig. 1. (a) Schematic draws of the lateral n-type SiC JFET. Left: cross-sectional view. Right: top view. (b) Cross-sectional SEM image of SiC JFET channels. (c) Transfer characteristics of a normally-on SiC JFET at V D S = 10 V . Solid and dotted lines indicate linear (right axis) and log (left axis) plots, respectively. The drain current at V G S = 0 V is about 45 μ S . (d) Output characteristics of a normally-on SiC JFET from V G S = − 3 V to 1 V .

[picture]

Fig. 2. (a) Circuit diagram of the n-type SiC JFET Operational Amplifier (OpAmp) with differential input, gain and buffer stages. (b) Picture of a wire bonded SiC JFET OpAmp. (c) Bode plot for the gain stage of SiC JFET OpAmp before (red) and after (light blue) 50kGy gamma-ray irradiation. Left axis: gain (circles). Right axis: phase (cross marks).

Fig. 2. (a) Circuit diagram of the n-type SiC JFET Operational Amplifier (OpAmp) with differential input, gain and buffer stages. (b) Picture of a wire bonded SiC JFET OpAmp. (c) Bode plot for the gain stage of SiC JFET OpAmp before (red) and after (light blue) 50kGy gamma-ray irradiation. Left axis: gain (circles). Right axis: phase (cross marks).

Gamma-ray irradiation was performed at the Takasaki Institute for Advanced Quantum Science (QST) using a Co-60 source with a dose rate of 2.17kGy/h under room temperature, atmospheric
conditions, and normal room-light laboratory conditions. The packaged SiC OpAmp was mounted on a printed circuit board and connected to external instruments via 10 m cables, enabling real-time monitoring outside the irradiation chamber. Input signals, supply voltages, and output signals were recorded continuously during the irradiation.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

Figures 3(a) and (b) show the input waveform (yellow) and output waveform (light blue) before γ ray irradiation and 10 minutes after the start of irradiation. The input signal was a 100 Hz sine wave with an amplitude of 0.1 V , and the circuit was operated with a supply voltage of ±20 V and a bias voltage of -14 V . No increase in output waveform noise or change in voltage gain was observed during irradiation. In contrast, the output offset voltage decreased by approximately 2 V due to irradiation.

Figure 3(c) shows the time evolution of the offset voltage shift. The offset voltage dropped sharply immediately after the start of irradiation and then its rate of change became more gradual after 20 minutes. After the 60-minute irradiation was completed, the offset voltage slowly recovered, reaching a value approximately 1.2 V below its original level about one hour after the end of irradiation (corresponding to a recovery ratio of roughly 40%).

[picture]

Fig. 3. (a) Snapshot of input (yellow) and output (light blue) waveforms before the gamma-ray irradiation. (b) Snapshot of waveforms during the gamma-ray irradiation. The output offset voltage decreased by approximately 2 V due to irradiation. (c) Time evolution of the offset voltage shift. The irradiation starts at 0 min . and ends at 60 min .

Fig. 3. (a) Snapshot of input (yellow) and output (light blue) waveforms before the gamma-ray irradiation. (b) Snapshot of waveforms during the gamma-ray irradiation. The output offset voltage decreased by approximately 2 V due to irradiation. (c) Time evolution of the offset voltage shift. The irradiation starts at 0 min . and ends at 60 min .

JFET

Diode

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

[picture]

Fig. 4. Lateral schematic of the JFET (left) and level-shifting diodes (right). While current (indicated by blue arrows) flows through the bulk region in the JFET, in the level-shifting diodes it mainly flows near the SiC/SiO2 interface within the n−layer.

Fig. 4. Lateral schematic of the JFET (left) and level-shifting diodes (right). While current (indicated by blue arrows) flows through the bulk region in the JFET, in the level-shifting diodes it mainly flows near the S i C / S i O 2 interface within the n − layer.

[picture]

Fig. 5. (a) Output offset voltage (upper panel) and the node voltage after level shifting (lower panel) measured simultaneously as a function of time. The irradiation starts at 0 min . and ends at 60 min . (b) the time evolution of the output offset voltage when the bias voltage was increased by 0.1 V , 20 minutes after the start of irradiation.

Fig. 5. (a) Output offset voltage (upper panel) and the node voltage after level shifting (lower panel) measured simultaneously as a function of time. The irradiation starts at 0 min . and ends at 60 min . (b) the time evolution of the output offset voltage when the bias voltage was increased by 0.1 V , 20 minutes after the start of irradiation.

Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

Now let us discuss the possible cause of the output offset shift. Figure 4 shows a lateral schematic of the JFET and level-shifting diodes that constitute the gain stage. While current (indicated by blue arrows) flows through the bulk region in the JFET, in the level-shifting diodes it mainly flows near the SiC/SiO2 interface within the n−layer.

During γ-ray irradiation, electron-hole pairs are generated in the SiC bulk, at the SiC/SiO2 interface, and in the SiO2 bulk, and these carriers are separated by the electric field present between the anode and cathode electrodes in diodes. Among them, the holes trapped in defects within the SiO2 bulk are considered to be the least likely to be collected by the electrodes. When these holes accumulate near the interface, the band bending at the SiC/SiO2 interface in the n−layer becomes more pronounced, which increases the electron concentration near the interface and consequently reduces the forward resistance of the diode.

As a result, for a given current, the voltage drop across the diode decreases under irradiation. This reduction in voltage drop causes the post-level-shift node potential in the gain stage circuit to increase. Meanwhile, the differential input on the opposite side is fixed by the bias voltage, leading to an imbalance in the differential pair and an increase in the current through the left-hand path. Since the JFET located at the upper part of the left-hand path operates as an active resistor, the increased current results in a larger voltage drop across this element, which in turn lowers the output potential.

Figure 5(a) shows the output offset voltage (upper panel) and the node voltage after level shifting (lower panel) measured simultaneously as a function of time. It can be seen that the decrease in the output offset voltage correlates with the increase in the post-level-shift node voltage, supporting the above discussion.

Finally, figure 5(b) shows the time evolution of the output offset voltage when the bias voltage was increased by 0.1 V,20 minutes after the start of irradiation. These results indicate that the shift of the output offset voltage can be compensated by a small adjustment of the bias voltage, corroborating that the observed phenomenon is primarily caused by the change in the voltage drop across the diodes.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

In this study, we performed in-situ measurements of a SiC JFET operational amplifier under gamma-ray irradiation. The results indicate that radiation exposure did not affect the output waveform or voltage gain but causes a shift in the output offset voltage. This shift is likely due to holes generated
by irradiation and trapped in the oxide layer, which altered the I-V characteristics of the level-shifting diodes. The offset shift can be compensated by applying an appropriate vias voltage and may also be mitigated through optimization of the diode structure and/or circuit topology.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

This work was partially supported by the commissioned research fund provided by FREI(JPFR25010501), and JSPS KAKENHI (S), Grant Number JP24H00035.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.79.pdf

T. Kimoto, J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices and Applications, IEEE Press, 2014.

M. Shakir, S. Hou, R. Hedayati, B.G. Maim, Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications, Electronics 2019, 8(5) (2019) 496.

A. Takeyama, T. Mikino, Y. Tanaka, S.-I. Kuroki, T. Ohshima, Threshold voltage instability and hysteresis in gamma-rays iraadiated junction field effect transistors, J. Appl. Phys. 131 (2022) 244503.

M. Tsutsumi, T. Meguro, A. Takeyama, T. Ohshima, Y. Tanaka, S.-I. Kuroki, Integrated 4HSiC Photosensors With Active Pixel Sensor-Type Circuits for MGy-Class Radiation Hardened CMOS UV Image Sensor, IEEE Electron Device Letters 44 (2023) 100-103.

Y. Kobayashi et al., Gamma-Ray Irradiation Response of the Motor-Driver Circuit with SiC MOSFETs, Material Science Forum 858 (2016) 868-871.

A. Metreveli, V.V. Cuong, S.-I. Kuroki, C.-M. Zetterling, Impact of Interface Oxide Type on the Gamma Radiation Response of SiC TTL ICs, Electronics and Energetics 37 (2024) 599607.

T. Amamiya, M. Yamamoto, H. Umezawa, K. Nakayama, T. Kuroiwa, S.-I. Kuroki, Y. Tanaka, Fabrication of the planer SiC gate-all-around JFET with channel dose modulation, presented at ICSCRM2024.

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The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1056, pp 85-92

doi: 10.4028/p-1f9tO3

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-03-16

Online:
2026-05-20

1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

The original version of this paper is available on https://www.scientific.net/KEM.1056.85.pdf

Z. Yuan 1,a*, V. Kotagama 1,b, B. Zhou 1,c, P. Gammon 1,d, M. Antoniou 1,e*

1 School of Engineering, University of Warwick, Coventry, CV4 7AL, UK

a  Zhaoxue.Yuan@warwick.ac.uk, b  viren.kotagama@warwick.ac.uk, c  Bailing.zhou@warwick.ac.uk, d  p.m.gammon@warwick.ac.uk, e  Marina.Antoniou@warwick.ac.uk

Keywords: Silicon Carbide, Schottky diode, Lateral device, RESURF device, Radiation hardness, Single event effect, Single event burnout.

Abstract

Radiation-hardened SiC power devices are essential to prevent leakage degradation and catastrophic failures such as SEE and SEB. Lateral device structures lower the risk of contact shorting by providing greater physical separation between conductive regions. Wider device geometries also improve radiation tolerance, as larger dimensions can accommodate charge buildup with less effect on device performance. In addition, RESURF structures enhance robustness by shifting the high electric field into the bulk, which reduces the impact of radiation-sensitive interface states on breakdown.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1056.85.pdf

Spaceborne electronics are continuously exposed to radiation from galactic cosmic rays, solar particle events, and trapped particles in Earth's magnetic field. These radiation sources induce several forms of degradation in semiconductor devices, including Total Ionizing Dose (TID), Displacement Damage (DD), and Single-Event Effects (SEE)[1]. TID causes cumulative charge trapping and interface state generation caused by prolonged exposure to ionize radiation, leading to shifts in threshold voltage and increased leakage current. DD introducing lattice defects introduced by highenergy particles such as neutrons or protons, which degrade carrier mobility and lifetime. SEE as a Transient or destructive events triggered by a single energetic particle[2]. Depending on severity, SEEs may result in soft errors like single-event upset (SEU), where a logic state is flipped, or hard errors such as single-event burnout (SEB), which permanently damages the device[3].

The impact of SEE on semiconductor device depend strongly on the Linear Energy Transfer (LET) of the particle, as well as device biasing, and circuit layout[4]. LET represents the energy deposited per unit path length as an ion traverses the semiconductor and is typically expressed in units of MeV·cm2/mg[5]. Typically, the LET value that a device can tolerate, and the single-event burnout (SEB) threshold voltage are critical parameters in assessing radiation resilience[6]. For instance, a 1200 V -rated SiC power MOSFET exhibits an SEB threshold voltage of approximately 330 V when subjected to a LET of 20MeV·cm2/mg[7].

A reverse-biased PN junction struck by a heavy ion undergoes multiple phases, including charge deposition[6], transient current flow, and potential device failure with leakage current degradation as a key signature. The applied voltage bias strongly influences these effects: under higher reverse bias, the electric field in the depletion region is stronger, which accelerates carrier separation and increases the likelihood of avalanche multiplication. This enhances the peak transient current generated by the ion strike, potentially triggering destructive single-event effects such as SEB. Conversely, at lower bias, the electric field is weaker, reducing the multiplication effect but increasing the collection time for carriers, which can lead to slower recovery and elevated transient leakage.

Device structures can be optimized to enhance charge collection efficiency and suppress parasitic effects, thereby increasing the SEB threshold voltage. Additionally, selecting appropriate materials and doping profiles can mitigate the impact of high-LET radiation, ensuring reliable operation in space environments.

Lateral device structures are particularly attractive in this context, as they inherently avoid contact shorting (Fig.1) and can be scaled laterally to provide additional current drive, thereby compensating for transient charge collection during radiation strikes.

[picture]

Fig. 1. Comparison between vertical device (left) and lateral device (right) under heavy ion strike.

Fig. 1. Comparison between vertical device (left) and lateral device (right) under heavy ion strike.

For high-voltage applications, reduced surface field (RESURF) structures are widely employed due to their ability to distribute the electric field laterally and vertically, thereby improving breakdown performance[8]. A conventional RESURF device typically relies on a uniformly doped N-type drift region (Fig.2), which suffers from excessive leakage current and limited breakdown voltage under edge-related field crowding[9]. To overcome these issues, advanced termination schemes such as field plates and corner protection structures have been proposed[10]. More recently, the two-zone RESURF approach has been introduced, in which vertically stacked N-regions with different doping concentrations are employed[11]. This configuration enhances electric field control and significantly improves breakdown voltage, although it comes at the expense of higher on-resistance due to the presence of lightly doped drift regions.

[picture]

Fig. 2. RESURF device cross section with Electrical Field and deplete region.

Fig. 2. RESURF device cross section with Electrical Field and deplete region.

Process

The original version of this paper is available on https://www.scientific.net/KEM.1056.85.pdf

In the optimization of RESURF-based lateral devices, a Two-Zone (TZ) structure is introduced to generate an additional electric field peak, thereby improving the breakdown voltage compared with a conventional Single-Zone (SZ) design. In the SZ device, both Zone-1 and Zone-2 share the same doping concentration, which limits the degree of electric field modulation and results in lower breakdown capability. In contrast, the TZ structure employs a lightly doped Zone-1 combined with a more heavily doped Zone-2, creating an auxiliary electric field peak (Fig.5) that enhances depletion and supports higher voltage blocking (Fig.4)

Further improvement is achieved with the Two-Zone P-ring (TZP) structure, where a P -ring is implemented at the anode corner to suppress leakage current, while a highly doped bottom layer in Zone-1 compensates for the resistance introduced by the additional field-control features. This combined approach enables both reduced leakage and maintained on-resistance, offering an effective trade-off between breakdown voltage and conduction loss.

[picture]

Fig. 3. (a) Layout of TZ RESURF SBD (b) Layout of TZP RESURF SBD.

Fig. 3. (a) Layout of TZ RESURF SBD (b) Layout of TZP RESURF SBD.

The designed device employs a P-type epitaxial layer with a doping concentration of 5×1015 cm−3, thickness of 11μ m, and width TW of 22μ m. This structural Table 1, providing a reference for design optimization and comparison with alternative RESURF- configuration supports a breakdown voltage of approximately 1700 V , while maintaining an on-resistance as low as 20 mΩ· cm2. Such performance highlights the effective trade-off achieved between high-voltage blocking capability and low conduction loss, which is essential for wide-bandgap power devices intended for both terrestrial and space applications. The structural parameters of the device are summarized in based architectures.

Table 1. Dimensions of the Single-Zone, Two-Zone and Two-Zone-P ring RESURF SBDs.

Property | Value(μm) | Property | Value(μm)
WP | 11 | WNL | 7.5/ 9/ 10.75
TW | 22 | WNR | 14/ 12.5/ 10.75
P Ring width | 1 | Oxide thickness | 0.2
P-pillar Depth | 2.5 |  |

Result

The original version of this paper is available on https://www.scientific.net/KEM.1056.85.pdf

Compared with the SZ and TZ structures, the proposed TZP device exhibits a clear advantage by suppressing leakage current while maintaining a high breakdown voltage (BV) and achieving a reduced on-resistance (Ron) (Fig.4). The incorporation of the P-ring at the anode corner effectively blocks potential leakage paths, thereby improving off-state performance without compromising conduction characteristics in the on-state.

[picture]

Fig. 4. On-state and off-state characteristics of SZ (dotted), TZ (solid), and TZP (dashed).

Fig. 4. On-state and off-state characteristics of SZ (dotted), TZ (solid), and TZP (dashed).

[picture]

Fig. 5. Off-state lateral surface electric field of RESURF SBDs (SZ, TZ, TZP) before avalanche, 10 nm below the interface.

Fig. 5. Off-state lateral surface electric field of RESURF SBDs (SZ, TZ, TZP) before avalanche, 10 nm below the interface.

The incorporation of TZ and TZP structures leads to a more uniform electric field distribution, which facilitates faster recovery after irradiation. As shown in Fig.6, under an LET of 60 MeV·cm2/mg and a reverse bias of 1000 V , when the ion strike occurs at the device center (the location of the middle electric-field peak, corresponding to the boundary between Zone-1 and Zone2), the TZP device shows only a 300 K temperature rise. In contrast, the SZ and TZ counterparts exhibit much larger increases of approximately 1500 K and 400 K , respectively. The enhanced field control in the TZP structure effectively suppresses localized field crowding, thereby reducing peak temperature rise and limiting excess leakage current following an SEE event, highlighting its potential for deployment in radiation-intense environments such as space applications.

[picture]

Fig. 6. Temperature and leakage current of the SZ, TZ and TZP after SEE.

Fig. 6. Temperature and leakage current of the SZ, TZ and TZP after SEE.

[picture]

Fig. 7. Temperature and leakage current of the TZ device under different reverse bias voltages.

Fig. 7. Temperature and leakage current of the TZ device under different reverse bias voltages.

At higher reverse bias (>1000 V), the electric field (EF) increase accelerates the separation and collection of electron and hole pairs generated by the ion strike. In Fig.7, when blocking voltage is 1200 V this rapid charge separation improves transient current response, also induces stronger energy dissipation within the lattice, resulting, the localized lattice temperature rises significantly and caused higher leakage current, increasing the likelihood of thermal runaway and device degradation.

[picture]

Fig. 8. Electron and hole density distributions, together with lattice temperature, at 0 ns,1 ns,2 ns, and 5ns after an SEE strike for both SZ and TZP devices.

Fig. 8. Electron and hole density distributions, together with lattice temperature, at 0 n s , 1 n s , 2 n s , and 5ns after an SEE strike for both SZ and TZP devices.

Fig. 8 illustrates the evolution of electron and hole density distributions, as well as the lattice temperature, at different times following an SEE strike. The results show that the highest temperature rise occurs in the P-pillar and N+ regions. These areas are particularly weak because the localized charge deposition and strong electric field concentration accelerate carrier multiplication and heat generation, which can potentially lead to thermal runaway or permanent device damage. Compared with the SZ device, the TZP structure shows lower peak temperature and more confined carrier distribution, indicating improved robustness against SEE strike.

The performance of lateral TZ and TZP RESURF devices is strongly influenced by the doping concentration and depth of the P-ring at the anode corner. In Fig. 9 and Fig.10, increased P-ring doping and depth have a direct impact on the peak electric field at the anode corner following a heavy ion strike, significantly reducing localized field crowding and lowering the associated peak electric field.

In addition, increasing the P-ring depth not only improves electric field modulation but also contributes to reducing the maximum lattice temperature following heavy-ion strikes. By mitigating localized field crowding at the anode corner, a deeper P-ring suppresses hot-spot formation, thereby lowering the risk of thermal runaway and enhancing the device's resilience to single-event effects. However, this improvement comes at the cost of increased hole injection into the drift region, which raises the device's on-resistance (from 21.07 mΩ· cm2 to 25.13 mΩ· cm2 with P ring depth changed from 0.05μ m to 0.25μ m ).

[picture]

Fig. 9. Temperature and leakage current evolution in the TZP device after SEE, depend on P-ring doping concentration and depth at 1000 V blocking voltage.

Fig. 9. Temperature and leakage current evolution in the TZP device after SEE, depend on P-ring doping concentration and depth at 1000 V blocking voltage.

[picture]

Fig. 10. Lateral surface electric field of the TZP SBD at 1 ns after SEE strike, extracted 10 nm below the interface at 1000 V blocking voltage.

Fig. 10. Lateral surface electric field of the TZP SBD at 1 ns after SEE strike, extracted 10 nm below the interface at 1000 V blocking voltage.

The Contact Open Length (COL) plays a critical role in balancing conduction and recovery performance in lateral RESURF devices. Increasing the COL allows more current to flow through the contact, thereby reducing the on-resistance (Ron) and enhancing forward conduction. As shown in Fig.12, increasing the COL from 1μ m to 5μ m reduces the device resistance from approximately 20 mΩ· cm2 to 11 mΩ· cm2, demonstrating the strong influence of contact geometry on conduction performance.

[picture]

Fig. 11. Temperature and leakage current variation over time in the double RESURF device with differences by COL after SEE at 1000 V blocking voltage.

Fig. 11. Temperature and leakage current variation over time in the double RESURF device with differences by COL after SEE at 1000 V blocking voltage.

[picture]

Fig. 12. Ron, BV, and maximum temperature of the double RESURF device after SEE, with variations distinguished by column (COL).

Fig. 12. Ron, BV, and maximum temperature of the double RESURF device after SEE, with variations distinguished by column (COL).

However, as shown in Fig.13, longer COL can impede the efficient collection of injected holes back to the P+ region, potentially affecting charge recovery and post-event leakage suppression. Careful optimization of COL is therefore essential to achieve a compromise between low Ron and effective off-state performance, particularly under radiation-induced transient conditions.

[picture]

Fig. 13. Hole density distributions of different COL devices at 0 ns , 1 ns , 2 ns and 5 ns after an SEE strike.

Fig. 13. Hole density distributions of different COL devices at 0 ns , 1 ns , 2 ns and 5 ns after an SEE strike.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1056.85.pdf

The integration of RESURF structures into lateral SiC diodes offers an effective strategy for achieving a well-balanced device performance profile. The combination of TZP and double RESURF structures in lateral SiC diodes enable the simultaneous realization of high breakdown voltage, low specific on-resistance, suppressed leakage current, and improved tolerance to single-event effects (SEE). The addition of P-ring structures plays a critical role in alleviating edge-related electric-field crowding, which not only enhances breakdown robustness but also contributes to faster postirradiation recovery. Furthermore, this configuration permits the use of higher N-type doping concentrations in the drift region, thereby lowering Ron while maintaining reliable off-state blocking characteristics. Collectively, these design features highlight a robust pathway for developing highvoltage, radiation-hardened SiC power devices. In addition, the incorporation of a P -pillar region facilitates more efficient collection of avalanche-generated charge carriers, which further strengthens the device's resistance to catastrophic failure mechanisms under heavy-ion irradiation.

These findings offer valuable guidelines for the design of next-generation wide-bandgap power devices, particularly for applications in radiation-rich environments such as space electronics. The combination of structural optimization and radiation-hardening design presents a promising pathway for deploying high-performance SiC devices in both terrestrial and extraterrestrial high-voltage systems.

References

The original version of this paper is available on https://www.scientific.net/KEM.1056.85.pdf

J.-M. Lauenstein, M. C. Casey, R. L. Ladbury, H. S. Kim, A. M. Phan, and A. D. Topper, "Space radiation effects on SiC power device reliability," in 2021 IEEE International Reliability Physics Symposium (IRPS), 2021: IEEE, pp. 1-8.

P. Hazdra, S. Popelka, V. Záhlava, and J. Vobecký, "Radiation damage in 4H-SiC and its effect on power device characteristics," Solid state phenomena, vol. 242, pp. 421-426, 2016.

A. Sengupta et al., "Impact of heavy-ion range on single-event effects in silicon carbide power junction barrier Schottky diodes," IEEE Transactions on Nuclear Science, vol. 70, no. 4, pp. 394-400, 2023.

A. Sengupta et al., "Single-Event Effects in Heavy-Ion Irradiated SiC Charge-Balanced Power Devices," IEEE Transactions on Nuclear Science, vol. 71, no. 8, pp. 1447-1454, 2024, doi: 10.1109/TNS.2024.3381964.

C. Martinella et al., "Heavy-ion induced single event effects and latent damages in SiC power MOSFETs," Microelectronics Reliability, vol. 128, p. 114423, 2022.

A. Akturk, J. McGarrity, S. Potbhare, and N. Goldsman, "Radiation effects in commercial 1200 V 24 A silicon carbide power MOSFETs," IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 3258-3264, 2013.

C. Martinella et al., "Heavy-ion effects in SiC power MOSFETs with trench-gate design," IEEE Transactions on Nuclear Science, vol. 71, no. 8, pp. 1440-1446, 2024.

M. Imam, M. Quddus, J. Adams, and Z. Hossain, "Efficacy of charge sharing in reshaping the surface electric field in high-voltage lateral RESURF devices," IEEE Transactions on Electron Devices, vol. 51, no. 1, pp. 141-148, 2004.

I. o. Electrical and E. Engineers, 2022 IEEE 9th Workshop on Wide Bandgap Power Devices & Applications (WiPDA). IEEE, 2022.

J. Matsuda, "High reliability and low switching loss dual RESURF 40 V N-LDMOS transistor with grounded multi-step field plate," Journal of Technology and Social Science, vol. 7, no. 1, pp. 1-12, 2023.

Y. Qi, P. M. Gammon, A. B. Renz, V. Kotagama, G. W. C. Baker, and M. Antoniou, "Lateral 1200 V SiC schottky barrier diode with single event burnout tolerance," Power Electronic Devices and Components, vol. 8, p. 100068, 2024.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

Chapter 10: Robustness and Reliability of SiC MOSFET Devices, SiC MOSFET Power Modules

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 1-8

doi: 10.4028/p-KxTj4u

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-27

Revised:
2025-12-17

Accepted:
2026-02-28

Online:
2026-05-18

Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

R. Schnitzler 1,a*, T. Fink 1,b, D. Halmer 1,c, D. Koch 1,d and Ingmar Kallfass 1,e

1 Institute of Robust Power Semiconductor Systems, University of Stuttgart, Germany

a* ruben.schnitzler@ilh.uni-stuttgart.de, b  tobias.fink@ilh.uni-stuttgart.de, c  david.halmer@gmx.de, d  domini.koch@ilh.uni-stuttgart.de, eingmar.kallfass@ilh.uni-stuttgart.de 

Keywords: reliability, gate switching stress, gate switching instability, threshold voltage degradation.

Abstract

The pursuit of ever-higher system efficiency and power density in power electronic applications paves the way for an increased utilization of wide bandgap semiconductor devices such as silicon carbide (SiC) MOSFETs, due to reduced conduction and switching losses compared to silicon. For real-world application reliable operation along its lifetime is of utmost importance. To assure robust operation in electric drives and traction inverters SiC MOSFETs are switched bipolar to prevent parasitic turn on. Recently, it has been shown that not only bias temperature instability, but also gate-switching instability in bipolar switched applications has to be considered as a reliability concern for SiC MOSFET. While in gate switching stress tests usually only critically damped conditions are investigated irrespective of rise and fall times, in real-world applications gate voltage overshoots may occur and a broad variety of slew rates may be used depending on the individual power converter design. Therefore, this work investigates the influence of gate voltage overshoot and voltage slopes on threshold voltage aging using high frequencies and online degradation monitoring. It is shown that overshoots have a dominating impact on the overall degradation, while the gate voltage slope impacts minorly.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

Besides the ever-increasing demand for power density and high power efficiency, power electronic devices have to work reliably for twenty years, and more [1,2]. For this, several different lifetime tests were evaluated over recent years. Most lifetime tests were originally developed for Silicon devices and later on adapted for Silicon Carbide (SiC) devices. In this work, the focus is set on gate oxide reliability. Unlike Si devices, SiC devices have a more deficient gate oxide/semiconductor interface. Interface state densities of 1012eV−1 cm−2 are commonly achieved, about two orders of magnitude higher than for Si [3]. Residual carbon atoms near the interface can explain this elevated defect density. This challenging interface has multiple effects on the threshold voltage ( Vth  ) characteristics. On the one hand, reversible trapping can be observed with a distinct difference whether a positive or negative gate-source voltage was applied beforehand [3]. Depending on the technology, this effect can include a change between 40 and 400 mV . Since this effect is fully reversible and is not impacted by aging, this effect is neglected for gate switching stress tests (GSS) [4]. On the other hand, significant degradation over the lifetime can be observed in two primary effects:

Bias Temperature Instability (BTI), this effect can be explained by an accumulation of mobile oxide charges near the interface for longer stress durations [3,5]. This effect is commonly known in Si , but is more pronounced in SiC . BTI is testable with traditional high-temperature gate bias tests (HTGB), as this effect is highly temperature-dependent, and standards are already established [6].

Gate Switching Instability (GSI) can be observed for bipolar switching from accumulation to strong inversion of SiC devices, a Vth -shift dependent on the number of switching cycles [713].
Unlike BTI, GSI is not dependent on the total test time, but on switching cycles. In recent years, further analysis on GSI has been done, and standards have been established [14]. Several different
influences such as temperature dependency, drain-source voltage ( Vds ), positive and negative gatesource voltages ( Vgs+,Vgs− ), have been investigated [7-15]. It has been shown that the temperature has a negligible influence on GSI, indicating that known field-based tunneling effects like FowlerNordheim tunneling are not responsible for the observed degradation [14]. In [13], a recombinationenhanced defect model was developed explaining observed GSI by introducing a multi-step activation of defects, which have a small time constant and act charge-like in steady-state. In this work, a detailed analysis of GSI and its creation within one switching period is done. For this, experiments with different voltage slopes and overshoots have been carried out.

Method

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

In this work, a custom testbench for the characterization of gate-switching stress is used [4]. This testbench is capable of cycling up to twelve devices with different Vgs+,Vgs−, junction temperature ( Tj ) , and swiching frequency ( fsw  ) of up to 10 MHz while monitoring in-situ Vth  and Rds,on  degradation. A distinguish measurement of Vth,up  and Vth,down  is done as specified by JEDEC JEP 184 [6]. Furthermore, variable external gate-resistance Rg can be used to adjust the gate voltage slew-rate. To further analyze the impact of voltage slope and gate overshoot on gate switching instability, we first consider the waveforms under switching operation. For this, the gate path is modelled as a simple RLC-circuit in which Rg is the total gate resistance, including the internal and external gate resistance ( Rg, ext  ) as well as the driver resistance. Furthermore, the C consists of the input capacitance ( Ciss  ) of the device under test and additional parasitics of the measurement board, and Lg is the parasitic gateloop inductance. In this work, Lg is 25 nH from the parasitics of the testbench layout, and Ciss  is approximately 1 nF for two different planar SiC MOSFET technologies with a comparable 63 mΩ, 1200 V planar SiC MOSFET. For the following considerations, we define a damping factor ζ as in Eq. 1:

ζ=Rg2·Ciss Lg(1)

Only Rg, ext  can be changed in a practical matter to adapt ζ. To test the influence of voltage overshoot on gate-switching instability, several different Vgs− and Vgs+ with matched peak voltages ( Vpeak  ) are used. These can be calculated with Eq. 2 and 3 for ζ<1, in which ΔVgs is the total gate voltage difference between Vgs+ and Vgs−.

Vpeak +=Vgs++ΔVgs·(1+e−π·ζ1−ζ2)(2)

Vpeak −=Vgs−−ΔVgs·(1+e−π·ζ1−ζ2)(3)

The required ζ value is 0.544 and 0.236 for 18/−5 V and 14/−1 V, respectively. This is reached by changing the external gate resistor Rg, ext  to 4Ω and 0Ω, respectively. It should be noted that the external gate driver has a finite resistance, which adds to the gate path and is not equal for charging and discharging, hence a higher damping is reached during turn-on compared to turn-off. The waveform for an underdamped system of 14/−1 V and critically damped 21/−9 V is depicted in Figure 1a. It can be seen that the peak voltages are identical, while the steady-state voltages differ. To test the influence of the gate-voltage slew rate on GSI, different gate resistors were used under the constraint that both critical damping conditions are fulfilled and the maximum voltage is reached within 0.5% at the end of the switching period. To achieve a high acceleration factor 1 MHz was chosen and the maximum Rg, ext  of 60Ω was used yielding a ζ of 1.6. The waveforms for these critically damped conditions with voltage slopes ranging from 100 to 400 V/μs is depicted in Fig. 1b.

[picture]

Fig. 1. Measured GSS waveforms of underdamped (a) and different critically damped (b) conditions.

Fig. 1. Measured GSS waveforms of underdamped (a) and different critically damped (b) conditions.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

Frequency-Dependency.

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

In this section, the GSI-dependency of a planar 75 mΩ1200 V SiC MOSFET from manufacturer B on fsw is investigated. For this, all devices are critically damped with 10Ω and are stressed with Vgs of 18/−9 V. The measurement is done with a preconditioning pulse of 10 ms at the same voltage as the stress voltage and with 10 mA of measurement current under shorted gate-drain conditions. fsw  is chosen as 5,50,500,2500kHz to cover a large range of application-close, and highly accelerated lifetimes. Vth,up  and Vth,down  are measured ten times per decade since no degradation of hysteresis is observed; only Vth,up  is depicted in Fig. 2a. It can be seen that very similar aging can be observed over cycles for all frequencies, hence suggesting that the observed failure mechanism is not timedependent, but rather cycle-dependent.

[picture]

Fig. 2. Frequency-dependent GSI at Vgs of 18/−9 V and gate voltage slew-rate of 388 V/μs with a 1200 V75 mΩSiC MOSFET of manufacturer A.

Fig. 2. Frequency-dependent GSI at V g s of 18 / − 9 V and gate voltage slew-rate of 388 V / μ s with a 1200 V 75 m Ω S i C MOSFET of manufacturer A.

Voltage-slope Dependency.

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

In this section, the influence of different voltage slopes is investigated. For this, the waveforms depicted in Fig. 1b are utilized for two different planar technologies with a stress frequency of 1 MHz . The results for this are depicted in Fig. 3a for manufacturer B and Fig. 3b for a 63 mΩ1200 V planar SiC MOSFET of manufacturer A with the same measurement method as ascribed before. For both technologies, no aging in the hysteresis was observed; hence, only one is depicted. After an initial increase of roughly 20 mV , which can be explained by BTI. Vth,down  decreases until 109 cycles; this can be explained by the self-heating of the devices since Vth  has a negative temperature coefficient. This effect is larger for high voltage slope DUTs since a larger share of the capacitive losses are dissipated in the DUT. For the second experiment, the cooldown time was increased, and the devices were measured at room temperature. Therefore, no self-heating is observed. However, the room temperature altered during the GSS-operating conditions, hence some additional dips are observed in Fig. 2b, especially at higher ncycles . For both manufacturers, the trend is identical: for higher voltage slew rates, the GSI degradation increases as the voltage slope increases. This can be explained with an energy barrier that has to be overcome to activate the GSI- related defects. For higher switching speeds, higher energies are reached, therefore increasing the possibility of an activation over this recombination-enhanced reaction [11]. However, this effect is not dominating, and similar aging is observed for all devices under test and slew rates.

[picture]

Fig. 3. Measured GSS stress degradation for two different manufacturers at fsw=1MHz.

Fig. 3. Measured GSS stress degradation for two different manufacturers at f s w = 1 M H z .

Peak-Voltage Dependency.

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

In this section, the influence of the peak gate voltage is discussed. The waveforms were discussed in detail in the previous section. The peak-voltage dependency is important since in switching transition, short-timed gate-voltage overshoots and especially undershoots may occur. This is especially the case if low Rg are utilized to reduce the overall switching losses. To show the influence of Rg, and the drainsource current ( Ids ) on Vgs-,peak  a custom double pulse test bench is used. A 75 mΩ1200 VSiC MOSFET from manufacturer B is characterized for different Ids,Rg and Vgs− at 800 V and Vgs+ of 15 V. For this, a commercial coaxial shunt with a high bandwidth up to 1 GHz for the current measurement and an isolated voltage probe with a bandwidth of 1 GHz for Vgs measurement is used [17]. In Figure 4a the turn-off transition at 800 VVds,20 AIds, and 15 V Vgs+ is shown for different turn-off gate resistances ( Rg, off  ) it can be seen that the transition time reduces significantly and hence the switching energy (Esw) gets significantly lower as depicted separately in Fig. 4b. While for 50, and 20ΩRg,off  critically damped conditions are fulfilled, significant overshoots may occur at lower
Rg, off  reaching Vgs peak values ( Vgs− peak  ) of up to -14 V . Besides a dependency on Rg, which is an initial design choice. A dependency of Ids can also be extracted; this is depicted in Fig. 4c.

[picture]

Fig. 4. Double pulse tests for a 1200 V,75 mΩSiC MOSFET of manufacturer B for different Vgs, Rg, off , and Ids.

Fig. 4. Double pulse tests for a 1200 V , 75 m Ω S i C MOSFET of manufacturer B for different V g s , R g , off , and I d s .

Here, Rg, off  of 5Ω,Vds of 800 V , and Vgs of 15/−9 V are used. It can be seen that the initial Vgs waveform looks identical until 25 ns after which a ringing effect arises. This ringing effect can be described by Eq. 4 in which Vgs,amp is the current dependent ringing amplitude, ω0 is the resonance frequency of the gate loop, consisting of Lg and the input capacitance ( Ciss  ) ascribed in Eq. 5 and δ is the damping factor calculated with Eq. 6, in which Rg, int  is the internal gate resistance and Rg, ext  the external gate resistance [18,19]. Furthermore, Vgs, ideal  is the ideal discharge curve without any ringing. In this work, a TO-247-4 adapter is used to reach a Lg of 25 nH comparable to the GSS measurements, which have similar parasitics. Therefore, the ringing phenomena is larger than in typical applications, however, if Lg is reduced, similar behaviour is observed for lower Rg.

Vgs(t)=Vgs,amp(Ids)·ω0ω02−δ2·e−δt·cos(ω02−δ2·t−φ)−Vgs,ideal(t)(4)

ω0=1Lg·Ciss(5)

δ=(Rg,int+Rg,ext)2·(Lpar,g)(6)

In Fig. 4c, it can be seen that irrespective of Ids,ω0 and δ remain unchanged, but there is a distinct influence on Vgs,amp, hence higher Ids increase ∣Vgs,peak−∣. In Fig. 4d, solely |Vgs,pak−∣| is depicted for different Rg, off , and Ids in a first approximation, a square-root relationship can be observed for underdamped systems, as in Rg,off  of 5 , and 10Ω.
In the following, the influence of these observable overshoots in the nanosecond range should be investigated. For this, the identical GSS measurement method is used compared to the prior section. 5 MHz was used as stress frequency unless stated otherwise, with the underdamped waveforms depicted in Fig.1a. In Fig. 5a, the aging curve of Vth,down  over switching cycles for manufacturer B , is shown. Until 106 cycles, an increase in Vth  can be observed due to BTI or some sort of charging effect. A slightly lower charging effect is observed for 18/−5 V as compared to 14/−1 V owing to the lower average voltage present [17]. It seems that there is a saturation of this charging effect for higher ncycle  than 106, for 14/-1 some additional self-heating related can be observed, due to insufficient cooldown time. For all samples with a peak voltage of 21/−9 V a sharp increase in Vth  with an onset at 109 cycles due to GSI can be observed. In contrast, critically damped 18/-5 V onset of this GSI degradation increase is much later with an initially at 3·1011 cycles. This agrees with the literature that higher absolute Vgs-  yield higher GSS- aging [13,17]. For this technology, it appears that the aging is irrespective of the set voltage, but rather on the peak voltage, even if the peak voltage lasts only a few nanoseconds. For comparison, a second planar technology from manufacturer A is investigated in Fig. 5b. Here, 18 V is chosen as peak voltage, and the voltage levels are set to 14/−3.5 V and 12/-1 V, respectively. To avoid the initial charging effect observed in Fig. 4a, the preconditioning voltage prior to each Vth  measurement was set to 18/−9 V [17]. The stress frequency is 5 MHz for all devices except the green one, which is critically damped at the same voltage slew rate, but stressed with only 1 MHz . For this technology, similar aging for all overshoots or critically damped conditions is observed until 1012 cycles. The only observable difference is that if a lower frequency is utilized, some saturation in the GSI-related Vth  can be seen after 1011 cycles. This indicates that the detrapping of GSI-related defects might be a function of the applied stress time, rather than the pure cycles. However, a clear conclusion regarding the detrapping of GSI-related defects is not possible from this measurement.

[picture]

Fig. 5. Measured gate switching stress degradation for two different manufacturers at Vgs of 21/−9 V and fsw of 1 MHz .

Fig. 5. Measured gate switching stress degradation for two different manufacturers at V g s of 21 / − 9 V and f s w of 1 MHz .

These findings suggest that the origin of GSI is mainly observed during the switching event, and it depends rather on the peak voltage than the respective time it requires to get to the individual peak voltages, since a few-nanoseconds transition time is already sufficient to create GSI related defects. This concludes that the time-constants related to GSI-defect generation have small time constants, and even undervoltage peaks as short as 4 ns are sufficient to dominate the observed GSI behavior. Since GSI-related aging is mostly related to Vgs− and hence Vgs− peak , low Lpar,g  has to be pursued to achieve low switching energy, while reducing the influence of GSI-related trapping [13,17].

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

In this work, the influence of frequency, gate voltage slope, and gate voltage overshoot on GSI was investigated. It has been shown that the switching frequency has no impact on GSI, while higher gate voltage slopes, and therefore lower rise and fall times, expose a slightly larger GSI degradation compared to slower switching transition. Additionally, the peak voltage was investigated, as it has a dominant impact on device degradation. The results show that matched undamped peak voltages and critically damped waveforms lead to nearly identical degradation levels. This suggests that the switching transition- and specifically the associated negative gate voltage - drives GSI with a time constant so short that, in practical applications, voltage undershoots must be considered in order to accurately approximate GSI-related Vth  degradation. Consequently, minimizing the gate inductance should be a design priority. At the same time, a careful balance must be struck between reducing turnoff losses and limiting gate-voltage undershoot.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

This work is part of ARCHIMEDES, supported by the Chips Joint Undertaking and its members, including the top-up funding by National Authorities under Grant Agreement No.101112295. This work is supported by the German Federal Ministry of Education and Research (BMBF) under Grant No.16MEE0326. The responsibility for the content of this publication lies with the authors.

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The original version of this paper is available on https://www.scientific.net/KEM.1054.1.pdf

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S. Thiele, C. Herrmann, D. Yang, M. Neumeister, and T. Basler, "Gate switching instability of sic mosfets under simultaneously high drain-source voltage and high frequency acceleration," in 2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD), IEEE, 2024, pp. 136-139.

M. Xie, P. Sun, K. Wang, Q. Luo, and X. Du, "Online gateoxide degradation monitoring of planar sic mosfets based on gate charge time," IEEE Transactions on Power Electronics, vol. 37, no. 6, pp. 7333-7343, 2022.

T. Grasser et al., "A recombination-enhanced-defect-reactionbased model for the gate switching instability in sic mosfets," in 2024 IEEE International Reliability Physics Symposium (IRPS), IEEE, 2024, 3B.1-1-3B.1-7.

M. W. Feil et al., "On the frequency dependence of the gate switching instability in silicon carbide mosfets," Materials Science Forum, vol. 1092, pp. 109-117, 2023.

M. W. Feil et al., "Gate switching instability in silicon carbide mosfets-part i: Experimental," IEEE Transactions on Electron Devices, vol. 71, no. 7, pp. 4210-4217, 2024.

D. B. Habersat and A. J. Lelis, "Ac-stress degradation and its anneal in sic mosfets," IEEE Transactions on Electron Devices, vol. 69, no. 9, pp. 5068-5073, 2022.

"Ecpe, "qualification of power modules for use in power electronics converter units in motor vehicles," ecpe guideline aqg 324, rev. 03.1/2021, 2019.," in.

E. H. Nicollian and J. R. Brews, MOS (metal oxide semiconductor) physics and technology (Wiley classics library), Wiley classics library ed. Hoboken, NJ: Wiley-Interscience, 2003.

Ruben Schnitzler, Tobias Fink, Dominik Koch, David Halmer and Ingmar Kallfass "ParameterDependent Analysis of Gate Switching Instability in SiC MOSFETs", Accepted, to be published at ECCE europe 2025.

Huerner, A., Sochor, P., Sun, Q., Feil, M. W., & Elpelt, R. (2022, May). Influence of turn-off gate-voltage undershoots on the turn-on behavior of SiC MOSFETs. In PCIM Europe 2022; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (pp. 1-8). VDE.

Zeng, Z., & Li, X. (2017). Comparative study on multiple degrees of freedom of gate drivers for transient behavior regulation of SiC MOSFET. IEEE Transactions on Power Electronics, 33(10), 8754-8763.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 9-16

doi: 10.4028/p-2L2smi

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-08-29

Revised:
2025-12-10

Accepted:
2026-03-08

Online:
2026-05-18

Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

Jeong-Hwan Jang 1,a, Jang-Kwon Lim 2, b*, Kalle Ilves 3,c, Ki-Sun Song 1, d, Dong-In Yang 1,e, Young-Jin Kim 1,f and Kyu-Bong Yeon 4, g

1 REVOTECH, 51 Neungwon-ro, Mohyeon-eup, Cheoin-gu, Yongin-si, Gyeonggi-do, South Korea

2 RISE Research Institutes of Sweden AB, Isafjordsgatan 2, Kista, Sweden

3 Coherent-KISTA, Isafjordsgatan 22B, Electrum 207, Kista, Sweden

4 KATECH Korea Automotive Technology Institute, 303 Pungse-ro, Pungse-Myeon, Cheonan-Si, Chungnam, South Korea

a  jhjang@revotech.kr, b* Jang-Kwon.Lim@ri.se, c  kalle.ilves@coherent.com, d  kssong@revotech.kr, e  diyang@revotech.kr, f  yjkim@revotech.kr, g  kbyeon@katech.re.kr

Abstract

This paper presents the development and evaluation of a 1.2 kV SiC MOSFET-based Positive Temperature Coefficient (PTC) controller designed for energy-efficient heating applications in electric vehicles (xEVs). To address the increasing demand for higher-voltage battery systems in modern xEVs, a PTC controller utilizing wide bandgap (WBG) semiconductor technology was developed. The proposed system leverages a 1.2 kV SiC MOSFET to enable high-frequency operation up to 20 kHz , thereby mitigating audible noise issues by operating beyond the human hearing range. Unlike conventional IGBT-based controllers, which exhibit significant limitations at high switching frequencies, the SiC MOSFET-based controller demonstrates reliable high-frequency operation, reduced switching losses, and improved overall efficiency. Experimental validation confirms that the proposed approach not only ensures low-noise heating operation but also enhances energy efficiency, making it a promising solution for next-generation xEV thermal management systems.

Keywords: HVAC (Heating Ventilation Air-Conditioning), SiC MOSFETs, positive temperature coefficient (PTC), negative temperature coefficient (NTC), junction temperature ( Tj ), heating application.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

As the adoption of electric vehicles (xEVs) continues to expand, the demand for effective and energy-efficient cabin heating systems is becoming increasingly critical. Modern xEVs rely on Heating, Ventilation, and Air Conditioning (HVAC) systems not only to maintain passenger comfort but also to ensure the safe operation of battery and electronic components through effective thermal management. Within the HVAC system, Positive Temperature Coefficient (PTC) heaters are widely used as an auxiliary heating source, especially under cold ambient conditions where heat pump efficiency drops significantly. Unlike internal combustion engine vehicles, battery electric vehicles (BEVs) do not benefit from waste heat generated by the engine and must generate heat electrically.

Conventional PTC systems employing silicon Insulated Gate Bipolar Transistors (Si-IGBTs) exhibit significant energy inefficiencies. These devices experience high conduction losses due to their inherent knee voltage characteristics and substantial switching losses resulting from long tail currents during turn-off [1,2]. In practical usage, electric taxis can experience up to a 40% reduction in available battery capacity for heating during winter, which reduces their effective driving range from 135 km to approximately 80 km per charge [3].

Such limitations highlight a fundamental barrier to the widespread adoption of xEVs in colder regions, where customer acceptance and operational feasibility are strongly influenced by heating efficiency. Moreover, as global automotive manufacturers transition toward higher-voltage battery platforms (600-1000 V and beyond) to shorten charging times and extend driving ranges, heating
controllers must be designed to operate reliably at elevated voltages while simultaneously achieving higher efficiency and reduced acoustic noise.

In response to these challenges, this work presents the design, development, and experimental evaluation of a next-generation PTC controller based on Silicon Carbide (SiC) MOSFET technology. Unlike conventional IGBTs, SiC devices can sustain high-frequency operation, enabling switching above 20 kHz to suppress audible noise and improve overall power conversion efficiency. SiC devices offer superior performance characteristics, including significantly lower switching and conduction losses, higher breakdown voltages, and excellent thermal robustness [4,5,6].

These advantages not only address the inherent drawbacks of IGBT-based PTC systems but also open the pathway for compact, lightweight, and energy-efficient heating solutions. Such improvements are especially critical in the context of electric mobility, where every increment in energy savings directly translates into extended driving range and reduced total cost of ownership. Preliminary acoustic tests indicated that when the switching frequency exceeded 20 kHz specifically at 100 kHz -the emitted sound resembled white noise, which is imperceptible within the human audible range. This feature not only suggests the potential to resolve passenger discomfort associated with noise but also contributes directly to enhanced service quality and customer satisfaction in electric vehicle applications.

Engineering of1200VSiC MOSFETs for Stable Temperature Operation

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

Building on the need for high-efficiency and thermally robust PTC controllers, we developed and evaluated SiC MOSFET devices designed for stable temperature operation. To enhance the thermal stability of the PTC controller over operational temperatures, we employed SiC MOSFETs engineered with different on-resistance ( RDSon ) and threshold voltage ( VTH ) specifications. By investigating the trade-off between VTH and RDS( on ) across temperatures, we aimed to balance conduction loss and switching performance under realistic PTC load conditions. We analyzed the trade-off between conduction and switching losses in our 1200 V SiC MOSFETs, with a particular focus on the temperature dependencies of VTH and RDSon, as shown in Figs 1 and 2. As temperature increases, VTH exhibits a negative temperature coefficient (NTC) behavior because elevated lattice temperature reduce carrier mobility in the MOS channel and enhance carrier scattering, thereby requiring a lower gate voltage to form the conducting channel. This shift can increase the risk of false turn-on or higher leakage currents. Conversely, RDSon shows a positive temperature coefficient (PTC) behavior due to mobility degradation in the drift region and increased resistivity from enhanced phonon scattering, leading to higher conduction losses at elevated temperatures. Our devices maintained consistent and predictable trends in both parameters up to 175∘C, enabling an optimized balance between switching speed and conduction efficiency. This favorable thermal behavior minimizes total power loss under realistic PTC load conditions and improves the controller's robustness against high ambient temperatures and transient heating environments. These results demonstrate that, with appropriate device selection and thermally aware gate-driving strategies, SiC MOSFETs can deliver stable, high-efficiency operation for next-generation xEV PTC controllers.

[picture]

Fig. 1. Comparison of on-state resistance and threshold voltage on temperature dependency for 1200 V/90 mΩ SiC MOSFET.

Fig. 1. Comparison of on-state resistance and threshold voltage on temperature dependency for 1200 V / 90 m Ω SiC MOSFET.

[picture]

Fig. 2. Comparison of on-state resistance and threshold voltage on temperature dependency for 1200 V/20 mΩ SiC mosfet.

Fig. 2. Comparison of on-state resistance and threshold voltage on temperature dependency for 1200 V / 20 m Ω SiC mosfet.

SiC MOSFET-adopted PTC Controller Design

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

Leveraging the favourable device characteristics confirmed in the previous section, we developed a 1.2 kV SiC MOSFET-based PTC controller optimized for high-voltage xEV heating applications, aiming to ensure stable operation, minimize audible noise through high-frequency switching, and enhance overall energy efficiency under realistic load conditions.

The overall system architecture of the proposed PTC controller, including the application of the isolated gate driver and peripheral circuitry, is illustrated in Fig. 3. The controller was designed based on a nominal xEV battery voltage of 523 V , ensuring compatibility with practical vehicle platforms. To accommodate voltage fluctuations and transient conditions, the system was engineered to operate reliably within a wide input range of 650 V±150 V range. In compliance with automotive design guidelines, power semiconductor devices rated for approximately twice the nominal operating voltage were employed to guarantee safe and reliable operation.

[picture]

Fig. 3. Block diagram of the proposed PTC controller system architecture.

Fig. 3. Block diagram of the proposed PTC controller system architecture.

Furthermore, in order to meet the requirements of an 8 kW PTC rod, the controller was designed in accordance with the RT-curve characteristics of the PTC ceramic, as illustrated in Fig. 4. To enhance heating flexibility and user comfort, the system was implemented with a four-channel architecture, enabling independent control of heating for both the driver and individual passengers.

[picture]

Fig. 4. RT-curve of the PTC ceramic used in the proposed 8 kW heater design.

Fig. 4. RT-curve of the PTC ceramic used in the proposed 8 kW heater design.

In addition, as shown in Fig. 5, electromagnetic compatibility was evaluated through SiWAVE simulations, while mechanical and thermal reliability was analyzed using Sherlock, thereby ensuring that the proposed PTC controller was developed with both electromagnetic compliance and long-term durability in mind.

[picture]

Fig. 5. PCB design validation using Siwave for EMC analysis and Sherlock for reliability evaluation.

Fig. 5. PCB design validation using Siwave for EMC analysis and Sherlock for reliability evaluation.

Fig. 6 presents both the 1.2 kV SiC MOSFET device and the fabricated PTC controller prototype incorporating the device. The prototype was implemented by applying design improvements derived from preliminary test analyses, which addressed issues such as low-voltage supply, isolation distance, and gate driver performance. The controller architecture is divided into four functional zones (Zone 1 -Zone 4), each corresponding to specific circuit and control functionalities.

[picture]

Fig. 6. Overview of the proposed four-channel PTC controller showing the 3D PCB layout, SiC MOSFET device, and the fabricated PCB prototype.

Fig. 6. Overview of the proposed four-channel PTC controller showing the 3D PCB layout, SiC MOSFET device, and the fabricated PCB prototype.

PTC Operation Circuit Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

A detailed circuit evaluation was conducted to investigate the interaction between resistive PTC loads and the parasitic capacitance of the PTC controller board under high switching frequencies. As shown in Fig. 7, thermal imaging revealed that the PCB temperature increased significantly faster at 20 kHz than at 10 kHz operation, even under a lower duty cycle. This non-linear temperature rise is attributed to elevated switching losses and cumulative heating effects caused by reduced cooling intervals, emphasizing the importance of effective thermal management and optimized PCB layout for ensuring long-term reliability. Measured switching waveforms in Fig. 8 further illustrate the transient behaviour of the SiC MOSFET under PTC load conditions. At turn-on, a pronounced current overshoot was observed, followed by a gradual reduction in the current slope. During turn-off, the drain-source voltage ( VDS ) exhibited a slow rise, while the current level remained higher than
expected. This behaviour indicates possible energy recirculation through parasitic elements within the PTC load. These findings suggest that reducing parasitic inductance and capacitance in the PCB layout, together with careful gate-drive tuning, is critical to controlling switching transients, minimizing power loss, and improving the system's thermal stability.

[picture]

Fig. 7. PTC load operation with thermal imaging.

Fig. 7. PTC load operation with thermal imaging.

[picture]

Fig. 8. Measured switching waveforms at the drain-source ( VDS ) terminal of the SiC mosfet.

Fig. 8. Measured switching waveforms at the drain-source ( V D S ) terminal of the SiC mosfet.

PTC Load Modelling and Switching Analysis

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

Since the measured switching waveforms under PTC load conditions did not follow the typical turn-on and turn-off behaviour observed with purely resistive or inductive loads, a detailed load analysis was performed. As illustrated in Fig. 9, the PTC heating module consists of multiple ceramic elements that inherently introduce parasitic resistance, capacitance, and inductance into the switching loop. In each row of the PTC heat load module, six ceramic pieces act as distributed parasitic capacitances and resistances, with each piece connected through parasitic inductances.

[picture]

Fig. 9. PTC load structure (left) and simplified RC modelling of the PTC load circuit (right).

Fig. 9. PTC load structure (left) and simplified RC modelling of the PTC load circuit (right).

To capture these characteristics, the complex PTC load structure was represented using a simplified equivalent RC network model in Fig. 10. Through this modelling, load conditions were simulated using a 150 nF capacitor in parallel with a 200Ω resistive element, representing the aggregated parasitic characteristics of the module. This equivalent model enabled quantitative analysis of transient overshoot currents, electromagnetic interference (EMI) behaviour, and energy loss distributions. The stored energy in the capacitor at 525 V was calculated to be 21 mJ . Total system losses were determined by subtracting the measured load dissipation from the total simulated input energy, including contributions from the DC-link capacitor. This approach isolates the energy dissipated within parasitic components and non-idealities in the circuit, which are not directly converted into useful heat by the PTC elements.

[picture]

Fig. 10. Switching circuit with simplified PTC load model (left) and comparison of measured and simulated switching waveforms (right).

Fig. 10. Switching circuit with simplified PTC load model (left) and comparison of measured and simulated switching waveforms (right).

The simplified RC modelling of the PTC load accurately reproduced the measured switching waveforms, confirming that the parasitic resistance, capacitance, and inductance of the ceramic elements significantly influence the switching transients. The analysis highlighted three key factors for optimal system performance: (i) current overshoot during turn-on can be substantial and requires careful evaluation under varying temperature conditions, (ii) the DC-link capacitor selection must balance low ESR for efficiency with sufficient damping to suppress turn-off ringing, and (iii) accurate load modelling is essential to predict transient behavior and minimize energy losses within parasitic elements.

Acoustic Noise Testing and Evaluation

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

For the noise measurement, the experimental setup was established inside an acoustic chamber isolated from external disturbances. A microphone was positioned at a distance of 50 cm from the PTC heater, and the measurements were conducted under controlled conditions to ensure accurate evaluation of the generated acoustic noise. The measurement environment is illustrated in Fig. 11.

[picture]

Fig. 11. Experimental setup for acoustic noise measurement.

Fig. 11. Experimental setup for acoustic noise measurement.

The test results revealed that when the PTC controller was operated at switching frequencies of 100 Hz,1kHz,10kHz, and 15 kHz , the corresponding audible noise could be clearly perceived by the human ear. In contrast, when the switching frequency was increased to 100 kHz , the generated noise was indistinguishable from the background level, and no audible difference could be detected compared to the no-operation condition where the controller was not operating. This finding indicates that operating the PTC controller in the ultrasonic range can effectively suppress audible noise. Furthermore, the spectrogram shown in Fig. 12 confirms this observation: while distinct frequency components are visible in the lower frequency cases, the 100 kHz operation exhibits only broadband white noise similar to the no-operation condition, thereby validating the effectiveness of the proposed high-frequency switching strategy in eliminating perceptible acoustic noise.

[picture]

Fig. 12. Spectrogram of noise signals at different switching frequencies.

Fig. 12. Spectrogram of noise signals at different switching frequencies.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

The switching performance and thermal stability of PTC controllers are influenced not only by the inherent advantages of SiC MOSFETs but also by the optimization of the entire system environment. To achieve strong temperature stability, it is crucial to carefully balance MOSFET conduction and switching losses with DC-link capacitor heating and electromagnetic interference (EMI) suppression. A proper trade-off among these factors is essential to ensure both high efficiency and long-term reliability. To prevent potential thermal runaway, the gate voltage and gate resistance must be selected with consideration of the device's gate-source capacitance and its impact on switching transients. In particular, controlling the turn-on current overshoot and mitigating turn-off ringing are key to reducing device stress and minimizing parasitic loss. In addition, the selection of the DC-link capacitor has a significant impact on overall system performance. While low-ESR capacitors can enhance efficiency, they may also increase the likelihood of oscillations during switching. Therefore, capacitor design should balance efficiency and oscillation suppression, with the potential inclusion of RC snubber circuits as an effective supplementary measure.

Finally, experimental results confirmed that when the switching frequency was raised to the ultrasonic range (e.g., 100 kHz ), the PTC controller produced only broadband white noise indistinguishable from the no-operation condition, meaning that no audible sound could be perceived by the human ear. This demonstrates that the proposed design not only ensures thermal and electrical stability but also effectively eliminates acoustic noise, thereby enhancing passenger comfort in practical xEV applications.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

This work was supported by the International Joint Technology Development Project (Global Cooperation Hub-type Joint R&D) under grant agreements No. P146500052 and No. P0026051, funded by the Korea Institute for Advancement of Technology (KIAT) through the Ministry of Trade, Industry and Energy (MOTIE), Republic of Korea.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.9.pdf

Albanna A., et al., "Performance comparison and device analysis Between Si IGBT and SiC MOSFET." presented in 2016 IEEE Transportation Electrification Conference and Expo (ITEC), IEEE, 2016, pp. 1-6. doi:10.1109/ITEC.2016.7520242.

Ranstad P., et al., "An experimental evaluation of SiC switches in soft-switching converters," IEEE Transactions on Power Electronics, vol. 29, no. 5, pp. 2527-2538, May 2014.

Hao X., et al., "Seasonal effects on electric vehicle energy consumption and driving range: A case study on personal, taxi, and ridesharing vehicles," Journal of Cleaner Production, vol. 249, article. 119403, 2020.

Sadik D.P., et al., "Comparison of thermal stress during short-circuit in different types of 1.2kV SiC transistors based on experiments and simulations," IEEE Transactions on Industrial Electronics, vol. 68, no.3, 2608-2616, Mar. 2021.

Lim, J.-K., et al., "Comparison of total losses of 1.2 kV SiC JFET and BJT in DC-DC converter including gate driver," Materials Science Forum, vols. 679-680, pp. 649-652, Apr. 2011.

Buffolo M., et al., "Review and Outlook on GaN and SiC Power Devices: Industrial State-of-the-Art, Applications, and Perspectives," IEEE Transactions on Electron Devices, vol. 71, no. 3, 1344-1355, Mar. 2024.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 17-24

doi: 10.4028/p-52OvYf

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-08

Revised:
2025-12-12

Accepted:
2026-02-26

Online:
2026-05-18

A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages

The original version of this paper is available on https://www.scientific.net/KEM.1054.17.pdf

Felix Hoffmann 1,2,a, Nando Kaminski 1, b

1 University of Bremen, Otto-Hahn-Allee 1, 28359 Bremen, Germany

2 Semikron Danfoss, Sigmundstraße 200, 90431 Nuremberg, Germany

a  felix.hoffmann@semikron-danfoss.com, b  nando.kaminski@uni-bremen.de

Keywords: SiC, MOSFET, Reliability, Power Cycling, Lifetime Modeling

Abstract

In this work, the power cycling capability of discrete SiC MOSFETs of seven manufacturers is investigated. The results show that even nominally similar devices can exhibit substantially different power cycling capabilities. The differences among the tested devices involve the scaling factor and the slope of the lifetime curves, but also the dependence of the baseline temperature. Furthermore, some devices exhibit a considerable increase in power cycling performance towards lower temperature swings, which cannot be characterized properly by power cycling tests at typical test conditions with much larger temperature swings. Thus for a proper assessment of the power cycling performance, multiple tests at suitable test conditions are necessary to obtain meaningful results.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.17.pdf

Today, discrete SiC MOSFET devices, particularly devices in TO packages such as the TO-247 family, are increasingly used for demanding applications. As a consequence of the mission profiles, particularly in terms of load cycling, the power cycling capability becomes increasingly relevant. While the research on thermo-mechanical ruggedness used to be mainly focused on power modules, more and more research related to power cycling is performed on discrete devices [1, 2]. The TO-247 package is a standard package and devices with similar primary electrical parameters are available from a variety of different manufacturers. Due to the different background of the different manufacturers, the landscape of devices in terms of device technology and packaging aspects is quite diverse. While the variability in power cycling lifetime of SiC MOSFETs was already reported in [1], no systematic comparison on a large scale has been performed so far. In this work, the power cycling capability of nominally similar SiC MOSFETs of different manufacturers is investigated to assess the variability in power cycling capability of different device designs on a larger scale.

Devices Under Test

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This investigation includes seven different SiC MOSFET designs from different manufacturers. All tested devices feature a nominal blocking capability of 1200 V and a similar RDS,on  between 70 mΩ to 90 mΩ. Both trench and planar designs were tested. While their primary electrical parameters are comparable, other design aspects and packaging parameters are different. The range of some relevant design and packaging parameters of the different designs is summarized in table 1. The parameters are normalized to the respective minimum of the considered designs. Even though all devices feature a similar RDS,on  and are packaged in similar housings, the number and diameter of bond wires is considerably different. Even though all devices feature a relatively similar drain current rating ID, the total bond wire cross-section, which is directly correlated with the bond loop resistance assuming equal bond wire length, varies substantially by a factor of 3.1 .

Besides the packaging related parameters, the device dimensions differ considerably. The device characteristics also reveal the strong correlation between chip thickness and required chip are to achieve the same RDS, on . Since the substrate resistance is reduced for thinned chips, the total chip area can be smaller. This correlation is visible through the even larger spread in chip volume. Besides

Table 1: Relevant design parameters, normalized to the respective minium value of all designs.

Properties | Parameter variation of all designs (normalized)
| min | max
No. of bond wires | 1 | 4
No of stitches per bond wire | 1 | 2
Bond wire diameter | 1 | 2.8
Total bond wire cross-section | 1 | 3.1
Chip area | 1 | 2.1
Chip thickness | 1 | 3.2
Chip volume | 1 | 6.7
Chip aspect ratio | 1 | 2.0
Rth,js (measured) | 1 | 1.2

Table 2: Summary of the test conditions of all test runs at target Tvj,min=50∘C.

Design | ΔTvj = 60 K | ΔTvj = 80 K | ΔTvj = 100 K | ΔTvj = 120 K
| run # | Iload | run # | Iload | run # | Iload | run # | Iload
A | 1 | 22.3 | 2 | 24.1 | 3 | 26.0 | 4 | 27.5
B | 5 | 19.0 | 6 | 22.0 | - | - | 7 | 23.5
C | 8 | 19.9 | 9 | 21.9 | 10 | 23.9 | - | -
D | 11 | 17.8 | 12 | 19.8 | 13 | 20.3 | 14 | 20.8
E | 15 | 16.3 | 16 | 16.8 | 17 | 17.5 | - | -
F | 18 | 21.6 | 19 | 23.3 | 20 | 24.6 | - | -
G | 21 | 21.3 | 22 | 22.3 | 23 | 23.5 | - | -
| Tair = 39 °C | Tair = 33 °C | Tair = 29 °C | Tair = 26 °C
ton = 3 s, toff = 6 s

the parameters given in table 1, other packaging properties, such as the mold compound and the solder composition, are also different among the tested devices, but could not be quantified in this work.

Test Setup and Test Conditions

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The PCTs were performed in a test bench with forced air cooling and with each DUT mounted on a separate heat-sink with controlled air inlet temperature (cf. [3]). Each considered device design is tested at least at three different target temperature swings ΔTvj between 60 K to 120 K . For all tests and all designs the target minimum temperature were kept constant at Tvj,min=50∘C. The heating and cooling times ( ton  and toff  ) were kept constant for all test runs and the target ΔTvj was set by adjusting the load current Iload  accordingly. Tvj,min was set by adjusting the air inlet temperature Tair . The test conditions and the deployed Iload  for all test runs are summarized in table 2 . While all devices were tested at target ΔTvj of 60 K and 80 K , design B had not been tested at 100 K and only three designs (A, B and D) were tested at a target ΔTvj of 120 K due to individual agreements with the manufacturers. For each run a total of 16 devices was tested. Test run 2 was performed twice to assess reproducibility and thus, a total of 384 devices had been tested. It is visible that even though the devices feature a similar nominal RDS,on , the required Iload  to achieve the same temperature swing differs considerably. To achieve a ΔTvj of 80 K , design A require an Iload  of 24.1 A , while design E only requires 16.8 A . This cannot be fully attributed to the differences in RDS,on  and thus, indicates a

[picture]

Fig. 1: Impact of the gate voltage on the third quadrant characteristics.

Fig. 1. Impact of the gate voltage on the third quadrant characteristics.

different RDS, on  temperature dependence for the different designs. The RDS, on  increase factor between 50∘C and 130∘C of the different designs is in the range of 1.4 to 2.4 . Also, it can be observed that the difference in Iload  between the test runs at ΔTvj of 60 K and 120 K differs among the different designs. The increase in Iload  between the two ΔTvj is only ca. 7% for design E , while is is 20% for design C . Due to the test bench topology, all DUTs of the same test run were subject to the same Iload ,ton ,toff  and Tair . To mitigate inevitable differences in ΔTvj due to parameter spread among the test lots, the gate voltage VGS  was slightly adjusted for each DUT individually to achieve roughly the same ΔTvj.

Junction Temperature Estimation by 𝐕SD-Method. The virtual junction temperature was estimated by deploying the VSD-Method. The sensing current was determined for each device design based on the ideality factor, as described in [4]. Since the VSD-Method relies on the voltage drop of the body-diode, it is important to make sure that the channel is completely closed. Since the required negative gate voltage VGS,off  varies considerably for different device designs, it must be determined for each design. For this investigation, the required VGS, off  was determined by considering the differential of VGS  versus VSD  as quality gauge. An illustration of the principle behind this method with samples outside the scope of this test campaign is shown in Fig. 1. The VGS  versus VSD  characteristics in Fig. 1a shows that all devices exhibit a significant impact of VGS on VSD above -4 V , which rapidly decreases for more negative VGS. However, the VGS at which its impact decreases is not the same for all devices. The differential of the The VGS  versus VSD  characteristics, which can be calculated by

|ΔVSDΔVGS(k)|=|VSD(k)−VSD(k−1)VGS(k)−VGS(k−1)|,(1)

can be used as a gauge for the minimum required VGS, where k is the index of the associated data point. The resulting characteristics is shown in Fig. 1b, whereas the y-axis is in log scale. Initially, the slope is relatively shallow and similar for all designs, but rapidly decreased below -3 V to -4 V . For more negative VGS the differences among the designs increase. In this work, a threshold of 0.1%(1mV/V) was deployed to determine a suitable VGS, off . The accuracy of the temperature estimation by the VSD− Method was assessed by the methods presented in [5] and the Tvj reading, where applicable, was corrected accordingly. However, this was only necessary for a very small number of designs and the vast majority of designs yield a good accuracy of the VSD-Method with optimized measurement parameters according to the aforementioned considerations and the method presented in [4].

Test Results

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The prevalent failure mechanism of all test runs was bond wire failures, which is consistent with previous reports [6, 2, 7]. As a failure criterion, a step-increase in VDS , which could not be attributed

Table 3: Summary of the test results of all test runs at target Tvj,min=50 K.

# | Des- ign | No. of DUTs | Cycles to failure (×10³ cycles) | ΔTvj (K) | Tvj,min (°C)
|  | Con | Cens. | Weibull Scale | Std. dev. | Weibull shape | Mean value | Std. dev. |
1 | A | 11 | 5 | 298.6 | 44.4 | 7.5 | 59.5 | 0.3 | 52.3
2 | A | 27 | 5 | 82.2 | 9.6 | 9.8 | 79.0 | 0.6 | 51.9
3 | A | 11 | 5 | 42.3 | 4.9 | 9.9 | 99.2 | 0.8 | 51.3
4 | A | 15 | 1 | 27.0 | 2.4 | 13.1 | 119.3 | 0.8 | 49.8
5 | B | 9 | 7 | 1257 | 150.7 | 9.5 | 59.5 | 0.5 | 51.9
6 | B | 11 | 5 | 109.4 | 21.6 | 5.4 | 79.0 | 1.1 | 50.5
7 | B | 11 | 5 | 18.1 | 2.6 | 7.7 | 119.3 | 1.1 | 52.5
8 | C | 14 | 2 | 200.2 | 55.2 | 3.6 | 59.4 | 0.5 | 51.8
9 | C | 11 | 5 | 57.3 | 9.7 | 6.4 | 78.6 | 1.2 | 51.4
10 | C | 12 | 4 | 23.2 | 5.3 | 4.6 | 97.4 | 3.1 | 53.1
11 | D | 11 | 5 | 192.6 | 18.5 | 12.1 | 59.9 | 0.4 | 50.1
12 | D | 16 | 0 | 110.3 | 18.4 | 6.5 | 77.5 | 0.8 | 48.7
13 | D | 13 | 3 | 64.1 | 9.3 | 7.7 | 99.5 | 1.2 | 51.5
14 | D | 16 | 0 | 41 | 10.8 | 3.8 | 116.2 | 1.8 | 50.3
15 | E | 11 | 5 | 170.7 | 13.4 | 15.1 | 59.0 | 0.5 | 51.6
16 | E | 13 | 3 | 42.4 | 6.2 | 7.6 | 80.3 | 0.6 | 51.8
17 | E | 13 | 3 | 16.8 | 2.3 | 8.1 | 99.8 | 0.9 | 51.2
18 | F | 11 | 5 | 270.2 | 49.7 | 4.6 | 60.2 | 0.3 | 52.7
19 | F | 13 | 3 | 78.3 | 10.7 | 8.2 | 80.6 | 1.8 | 52.1
20 | F | 13 | 3 | 28.9 | 3.5 | 5.6 | 99.8 | 0.8 | 52.0
21 | G | 15 | 1 | 118 | 26.7 | 4.6 | 59.2 | 0.8 | 53.2
22 | G | 15 | 1 | 42 | 6.6 | 7 | 79.2 | 0.6 | 52.3
23 | G | 15 | 1 | 16.3 | 3.2 | 5.4 | 97.9 | 1.8 | 52.1

to external causes, was considered. During this test campaign none of the DUTs exhibited clear signs of chip solder degradation. However, some DUTs exhibited other signs of degradation of the thermal path, i.e. thermal interface material (TIM). For the statistical analysis only DUTs with clear bond wire failures were considered. Furthermore, DUTs with an outlier RDS, on  that could not be homogenized by adjusting VGS within a reasonable range, as well as individual DUTs with a substantially different lifetime compared to the majority of DUTs of the same test run, were disregarded. Even though no systematic impact of Vth  drift effects on the PCT results could be observed for any design, some DUTs exhibited a non-package related parameter drift and thus, were also not considered for the statistical evaluation. For further information and illustrations refer to [3]. During this test campaign, on average 3 out of 16 DUTs had been disregarded per test run.

Lifetime Modeling The test results of all test runs with the respective test parameters and number of cycles to failure Nf are summarized in table 3 . For the lifetime modeling, the Weibull scale parameters, corresponding to the number of cycles to failure of 63.2% of the test population, are used. For each design, a lifetime model is derived by fitting the test data for the respective design to the Coffin-Manson equation:

Nf=K·ΔTvjβ1.(2)

The data points and the resulting lifetime models are shown in Fig. 2, whereas the error bars indicate the standard deviation of ΔTvj (along x -axis) and for the Weibull scale parameter (along y -axis).

[picture]

Fig. 2: Lifetime plots according to the Coffin-Manson equation, based on the fit to the test data (Weibull scale parameter) between ΔTvj=80 K to 120 K and with constant ΔTvj=60 K for all designs. The inset table summarizes the respective fitting parameters.

Fig. 2. Lifetime plots according to the Coffin-Manson equation, based on the fit to the test data (Weibull scale parameter) between Δ T v j = 80 K to 120 K and with constant Δ T v j = 60 K for all designs. The inset table summarizes the respective fitting parameters.

The respective Coffin-Manson fitting parameters are given in the inset table in Fig. 2. The lifetime model fits were obtained by considering the test data between K to 120 K , which is the range of typical test conditions for PCTs. The data points at ΔTvj=100 K is used for verification. The results show that even though all designs exhibit very similar primary electrical ratings, their power cycling capability is substantially different. The scaling factor β1 varies by 4 orders of magnitude and considering the model fits at ΔTvj=80 K, the resulting lifetime varies by a factor of 4.1. Due to the variation in ΔTvj=120 K, the variation at B,C,E,F is around 2.8 and as high as 5.8 at β1. While designs β1 and G feature a comparable Coffin-Manson exponent ΔTvj=80 K in the range of 4 to 4.5, which is comparable to the CIPS08 model, (ca. 4.4), a substantially lower ΔTvj was found for designs A and D with 2.75 and 2.2, respectively. As previously presented [3, 8], the model fits for design A and B yield a significant underestimation of the lifetime by a factor of ca. 1.68 for design A and 3.42 for design B . In contrast, the model fit to the data in the range of C,D,E,F to 120 K exhibit a very good agreement with the test data at all K for designs β1 and G .

Hence, based on the results of this work, the investigated designs differ in three aspects, namely difference in scaling factors β1 for all designs, different ΔTvj=60 K parameters with 5 out of 7 designs exhibiting a ΔTvj comparable to the CIPS08 model, and a significant underestimation of the lifetime by the CoffinManson fit for ΔTvj for 2 out of 7 designs.

The deployed lifetime model only considers the impact of Tvj,min to avoid ambiguous fitting results, since the majority of devices had only been tested at three different test conditions, i.e. at different ton. Some more elaborate lifetime models consider additional test related parameters such as Iload , Tvj,min and ton [9, 10]. While Iload  and ΔTvj have been held constant for these tests, ΔTvj was used to achieve the respective target ΔTvj for each run and thus, varied among the different designs and for the respective Iload , which leads to a strong correlation between D and V. Additionally, device and packaging related parameters such as the bond wire diameter Ibw and voltage class, i.e. device thickness β1, are considered in the mentioned lifetime models.

[picture]

Fig. 3: Regression analyses for chip thickness and current per bond stitch versus ΔTvj

Fig. 3. Regression analyses for chip thickness and current per bond stitch versus Δ T v j

To assess if known parameters could explain the differences among the different designs, regression analyses were performed for multiple parameters such as chip thickness, bond wire diameter, bond wire aspect ratio, total bond wire cross-section and current per bond stitch Ibw, i.e. current per bond wire divided by the number of bonds attached to the chip per wire [9]. It is worth noting that a regression analysis was only performed to assess whether the respective parameter could possibly explain the differences between the designs, not how the respective parameter correlates with the lifetime in general. The results of these regression analyses only yield positive signal, i.e. a p-value below 0.05, for the chip thickness and β1. The associated regression plots are shown in Fig. 3. The result suggests that the chip thickness impacts the Ibw parameter, i.e. the slope of the lifetime curve with respect to β1, whereas thinner chips exhibit a steeper slope, i.e. a larger Ibw. This is in agreement with previous reports on different SiC MOSFETs in SOT-227 package [11]. Additionally, the results indicate a correlation between β1 and Ibwα, whereas a lower β1 leads to a larger Iload. This is in agreement with the CIPS08 model and previous reports on discrete silicon IGBTs, which suggest a strong impact of the current per bond stitch [2,12]. While these reports suggests a relationship described by a power term ΔTvj and not an impact on the Coffin-Manson exponent Iload, this could be explained by the strong correlation between ΔTvj and β1. However, it must be considered that in this work, the correlation could also be the result of the pronounced link between K and ΔTvj. While the differences in Tvj,min and ΔTvj could be explained at least to some extend by the aforementioned considerations, the substantial gain in lifetime towards lower Tvj,min, observed for the designs A and B , could not be elucidated.

Impact of the Minimum Temperature To assess the impact of the minimum temperature 80∘C, two designs ( A and C ) were also tested at three

Nf=K·ΔTvjβ1·eβ2Tvj,min(3)

but at an elevated β1 of Tvj,min. The results were fitted to the equation

β1

consisting of the Coffin-Manson term according to eq. (2) and extended by an Arrhenius term, which is commonly used to include the baseline temperature [9, 10]. Equation (3) is commonly referred to as LESIT model. The resulting lifetime plots are shown in Fig. 4 and the respective parameters are summarized in the inset table in Fig. 4. For both designs the ΔTvj=60 K parameters are consistent for the two Tvj,min and the differences in Tvj,min=50∘C between the two designs could be confirmed. Additionally, the discrepancy between the fitted model and the data point at Tvj,min=80∘C for design A is visible for both Tvj,min. The model underestimates the lifetime by a factor of 1.68 at β2 and 1.45 at β2. However, the Tvj,min dependency is considerably different for both designs. While the fitted K factor is 774 for design A , is is substantially larger with 2598 for design B . By comparison, the CIPS08 model used a β1 of 1285 while for discrete silicon IGBTs a value of around 1950 was

[picture]

Fig. 4: Lifetime plots according to the LESIT equation with ΔTvj as baseline temperature for all designs. The test data (Weibull scale parameter) is fitted between β1 to 120 K and for β1 and ΔTvj. The inset table summarizes the respective fitting parameters.

Fig. 4. Lifetime plots according to the LESIT equation with Δ T v j as baseline temperature for all designs. The test data (Weibull scale parameter) is fitted between β 1 to 120 K and for β 1 and Δ T v j . The inset table summarizes the respective fitting parameters.

proposed [2]. Though the root cause for the different β1 dependency could not be elucidated, the results clearly show that besides differences in scaling factor Tvj, min , Coffin-Manson parameter ΔTvj=60 K, as well as the deviation from the model fit towards lower ΔTvj, the power cycling capability of SiC MOSFETs can also exhibit a substantially different dependence on the baseline temperature. Thus, it is important to thoroughly assess the power cycling capability for each device design individually and similarities should be assessed carefully, when experiences from other designs are incorporated.

Summary and Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1054.17.pdf

In this work, the power cycling capability of different SiC MOSFET designs in TO-247 packages was investigated. For that purpose a power cycling test campaign with seven different device designs and a total of 384 DUTs was performed. The results were used for lifetime modeling and the power cycling results and fitted lifetime model parameter were assessed. The results indicate that seemingly comparable SiC MOSFETs can exhibit vastly different power cycling performances and fitting parameters for lifetime models. Furthermore, the results suggest a considerable impact by the chip itself, whereas the chip thickness seems to impact the slope of the lifetime curve through the Coffin-Manson exponent ΔTvj. While some designs exhibit similar Coffin-Manson parameters ΔTvj, i.e. dependency of the lifetime on mathematical formula, others show a considerably different superscript number. Additionally, further tests at a higher mathematical formula indicate a substantially different dependency on the baseline temperature for different designs. Furthermore, two designs exhibit a substantially increased lifetime at mathematical formula and below, which is not reflected by the power cycling test results at typically deployed power cycling test conditions, i.e. mathematical formula of 80 K to 120 K . Therefore, testing at a single mathematical formula is insufficient to characterize the power cycling performance of SiC MOSFETs and comparative tests of different designs at high mathematical formula do not necessarily reflect their performances under field conditions. Consequently, for a proper estimation of the power cycling performance under field operation it is necessary to perform multiple tests under suitable test conditions. Furthermore, for comparative tests of different designs the potential variability in lifetime influencing factors should be considered to avoid misinterpretation of the test results.

Acknowledgment The authors gratefully acknowledge the support of our industrial partners, who provided the test samples and contributed through valuable technical discussions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.17.pdf

T. Ziemann, U. Grossner, and J. Neuenschwander, "Power cycling of commercial sic mosfets," in 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Oct 2018, pp. 24-31.

G. Zeng, L. Borucki, O. Wenzel, O. Schilling, and J. Lutz, "First results of development of a lifetime model for transfer molded discrete power devices," in PCIM Europe 2018; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2018.

F. Hoffmann and N. Kaminski, "Power cycling capability and lifetime estimation of discrete silicon carbide power devices," in Silicon Carbide and Related Materials 2019, vol. 1004, August 2020, pp. 977-984.

F. Hoffmann, S. Rugen, D. Silber, and N. Kaminski, "Impact of the sensing current density on pn-junction based temperature estimation methods for si and sic power devices," Microelectronics Reliability, vol. 114, p. 113834, 2020, 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020.

F. Hoffmann and N. Kaminski, "Investigation on the accuracy of the vsd-method for different sic mosfet designs considering different measurement parameters," in 2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2021.

I. Kovacevic-Badstuebner, S. Race, U. Grossner, E. Mengotti, C. Kenel, E. Bianda, and J. Jormanainen, "Extended analysis of power cycling behavior of to-packaged sic power mosfets," in 2023 IEEE International Reliability Physics Symposium (IRPS).

R. Amro, J. Lutz, and A. Lindemann, "Power cycling with high temperature swing of discrete components based on different technologies," in 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551), vol. 4, 2004, pp. 2593-2598 Vol.4.

F. Hoffmann and N. Kaminski, "Impact of device design on the power cycling capability of discrete SiC MOSFETs at different temperature swings," in 2020 IEEE 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Sep. 2020, pp. 533-536.

R. Bayerer, T. Herrmann, T. Licht, J. Lutz, and M. Feller, "Model for power cycling lifetime of IGBT modules - various factors influencing lifetime," in CIPS 2008; 5th International Conference on Integrated Power Electronics Systems, 2008.

U. Scheuermann and R. Schmidt, "A new lifetime model for advanced power modules with sintered chips and optimized al wire bonds," in Proceedings of PCIM Europe 2013; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, May 2013.

F. Hoffmann and N. Kaminski, "Impact of the chip properties on the power cycling performance of silicon carbide mosfets at different temperature swings," in 2022 34th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2022.

G. Zeng, "Some aspects in lifetime prediction of power semiconductor devices," Dissertation, Chemnitz, 2019, ISBN: 978-3961000968.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 25-29

doi: 10.4028/p-2iRgXd

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-16

Accepted:
2026-02-28

Online:
2026-05-18

Temperature Dependence of the AC-BTI in SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1054.25.pdf

Kohei Takei 1,a*, Hideya Kishigami 1, b and Takashi Setoya 1,c

¹Oki Engineering Co.,Ltd., 3-20-16 Hikawadai, Nerima, Tokyo, Japan

a  takei757@oki.com, b  kishigami645@oki.com, c  setoya457@oki.com

Keywords: bias temperature instability (BTI), AC-BTI, gate switching instability (GSI), dynamic gate stress (DGS).

Abstract

The reliability of silicon carbide (SiC) MOSFETs under alternating current bias temperature instability (AC-BTI) is a critical issue for power electronics. Previous studies show inconsistent temperature dependence of threshold voltage drift ( ΔVth  ) induced by AC-BTI and have not conducted tests at temperatures below room temperature. In this study, ΔVth  was measured in four commercially available SiC MOSFETs across a wide temperature range ( −40∘C to 150∘C ) under bipolar AC stress up to 1011 cycles. Most devices showed larger ΔVth  at lower temperatures, while one device exhibited increased ΔVth  also at high temperatures. These results may be explained by interface recombination mechanisms, with the device-dependent behavior possibly attributable to structural differences. The findings suggest the need for sub-room temperature testing to identify worst-case degradation scenarios in SiC MOSFETs.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.25.pdf

SiC MOSFETs are widely adopted in the power electronics field as highly efficient devices compared to Si-based devices. However, these devices are known to exhibit inherent degradation modes, one of which is alternating current bias temperature instability (AC-BTI). It has been reported that applying bipolar AC stress (alternating positive and negative voltages) to the gate of a SiC MOSFET induces a drift of threshold voltage ( Vth  ) [1-7]. The magnitude of Vth  drift ( ΔVth  ) is known to depend on the test temperature; however, previous studies show inconsistent results regarding the temperature dependence of ΔVth . While one study reports that ΔVth  increases with rising temperature [1], another study reports a decrease in ΔVth  with rising temperature [2]. These inconsistencies suggest that temperature dependence of ΔVth  varies with specific characteristics of the device. Nevertheless, previous studies have only evaluated this phenomenon at temperatures above room temperature. This study investigated temperature dependence of ΔVth in SiC MOSFETs through AC-BTI tests across a wide temperature range, including both below and above room temperature.

Experimental

The original version of this paper is available on https://www.scientific.net/KEM.1054.25.pdf

AC-BTI tests were performed using a newly developed AC-BTI test system, in which the devices were placed inside a temperature chamber (Fig. 1(a)). This system automatically switches between AC stress application and Vth  measurement through a relay matrix switch, enabling highly reproducible testing conditions. Fig. 1(b) shows the test circuit diagram of Vth  measurement and AC stress application.

In these experiments, the application of AC stress ( +20 V/−10 V at 500 kHz ) and the measurement of the threshold voltage ( Vth  ) were alternately conducted at several specified temperatures. Notably, the test conditions included not only higher temperatures but also temperatures significantly below room temperature ( −40∘C and −10∘C ), allowing for a detailed investigation of device behavior under low-temperature environments, which have not been reported in previous studies.

The number of AC stress cycles was set at 1011, which is specified as the minimum test cycle in AQG 324 [8] and is also used as a benchmark for automotive inverters in JEITA EDR 4713 Amend. 1 [9]. This number is regarded as an important benchmark for long-term reliability evaluation.
Vth  was measured using the triple sense protocol [8] (Fig. 2), and the values of Vth_Up  were used to compare ΔVth  across different test conditions.

Prior to each Vth  measurement, a thermal stabilization interval of five minutes was established. This interval was essential because the application of AC stress leads to repeated charging and discharging at the gate, causing the device under test (DUT) to heat up. By allowing the DUT to cool down and return to the ambient temperature of the chamber during this interval, the influence of temperature variations on the measured Vth  was eliminated. As a result, changes in ΔVth  could be accurately compared, without interference from temperature-dependent fluctuations.

Tests were conducted on four commercially available SiC MOSFETs (Table 1).

[picture]

Fig. 1. (a) Schematic of AC-BTI test system. The DUT is placed inside a temperature chamber, and both AC stress application and Vth  measurement are automatically switched and conducted via a relay matrix switch during the test. (b) Test circuit diagram of Vth  measurement and AC stress application.

Fig. 1. (a) Schematic of AC-BTI test system. The DUT is placed inside a temperature chamber, and both AC stress application and V th measurement are automatically switched and conducted via a relay matrix switch during the test. (b) Test circuit diagram of V th measurement and AC stress application.

[picture]

Fig. 2. Schematic waveforms of VGS and VDS in the AC-BTI test. An interval is provided between the AC stress application and the Vth  measurement to allow the heated DUT to return to the ambient temperature.

Fig. 2. Schematic waveforms of V G S and V D S in the AC-BTI test. An interval is provided between the AC stress application and the V th measurement to allow the heated DUT to return to the ambient temperature.

Table 1. SiC MOSFETs employed for testing.

DUT | Gate structure | Rated VGS [V] | Sample size
DUT_A | Trench | -5/+23 | 2
DUT_B | Trench | -4/+21 | 3
DUT_C | Planar | -8/+19 | 3
DUT_D | Planar | -10/+22 | 3

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1054.25.pdf

Fig. 3 shows the results of AC-BTI tests conducted under various temperature conditions. In all cases, ΔVth  increased as the number of AC stress cycles increased. Fig. 3(c) illustrates the relationship between ΔVth  at the end of the test ( 1×1011 cycles) and the test temperature. For DUT-B, C, and D, ΔVth  became larger as the test temperature decreased. On the other hand, DUT-A exhibited an increase in ΔVth  toward lower temperatures, as seen in the other devices, but uniquely also showed an increase in ΔVth  at higher temperatures.

The Vth  drift caused by AC-BTI may be explained using two main mechanisms: the PhotonAssisted Electron Injection model (Model A) [3-4] and the Recombination Enhanced Defect Reaction model (Model B) [5-7].

Both models attribute the origin of ΔVth  to the recombination of electrons and holes via SiC/SiO2 interface traps that occurs during gate switching (from accumulation to inversion). However, they differ in the proposed energy transfer process: Model A attributes the effect to photons generated during recombination, while Model B considers the role of phonons produced in these reactions.

According to these models, the larger ΔVth observed at lower temperatures in this study can be explained by the longer release time of holes trapped at the interface, reducing the number of holes released before recombination with electrons. This leads to more recombination events and, consequently, more electrons with sufficient energy to exceed the conduction band offset are injected into the gate oxide, where they are captured by oxide traps, resulting in a greater ΔVth , as described in Model A. Since photon generation is essentially temperature-independent, this behavior is consistent with the photon-assisted mechanism in Model A. On the other hand, the notable increase in ΔVth  at higher temperatures, observed in DUT-A, may be better explained by Model B, in which enhanced phonon generation at high temperatures promotes the formation of additional interface defects, resulting in the increased ΔVth.

Importantly, it is possible that both photon-assisted and phonon-assisted mechanisms are influencing ΔVth  simultaneously, with their relative contributions varying according to temperature. At lower temperatures, the photon-related process may dominate, consistent with the observed increase in ΔVth  across most devices in the low temperature range. In contrast, at higher temperatures, the increased presence of phonons may enhance the recombination enhanced defect reaction, leading to additional degradation in devices such as DUT-A.

Furthermore, the extent to which each mechanism contributes to device degradation appears to depend on the specific device, likely due to variations in structure, processing conditions, or interface state densities among the tested MOSFETs. As a result, the relative impact of photon- and phononrelated mechanisms-and consequently, the temperature dependence of ΔVth -can vary depending on both the device and the temperature range. Since our study did not specifically separate the effects of device structure, this hypothesis remains under consideration and will require further research to be fully validated. These results thus highlight the unique interplay between these processes in the tested devices under the experimental conditions, emphasizing the necessity of evaluating AC-BTI reliability in SiC MOSFETs across both low and high temperature environments.

[picture]

Fig. 3. AC-BTI test results at various temperatures for each DUT. (a) ΔVth as a function of number of AC stress cycle. (b) Zoomed-in image of the region highlighted by the square in (a). (c) Relationship between ΔVth at the end of the test ( 1×1011 cycles) and the test temperature. The value indicated in the figure represents the mean ΔVth  tested at 25∘C.

Fig. 3. AC-BTI test results at various temperatures for each DUT. (a) Δ V t h as a function of number of AC stress cycle. (b) Zoomed-in image of the region highlighted by the square in (a). (c) Relationship between Δ V t h at the end of the test ( 1 × 10 11 cycles) and the test temperature. The value indicated in the figure represents the mean Δ V th tested at 25 ∘ C .

Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1054.25.pdf

In this study, the temperature dependence of ΔVth caused by AC-BTI was investigated for four commercially available SiC MOSFETs over a wide temperature range, including sub-room temperatures. Most devices exhibited larger ΔVth at lower temperatures, while one device showed increased drift also at high temperatures, indicating that the ΔVth  behavior is device-dependent and likely influenced by intrinsic factors such as structural and interface characteristics.

The results highlight that limiting reliability testing to temperatures above room temperature may overlook worst-case degradation scenarios, as significant drift can occur at lower temperatures. These findings emphasize the importance of conducting AC-BTI tests covering a broad temperature range to ensure accurate assessment of SiC MOSFET reliability in practical applications.

The measurement variability of Vth in this study was within 10 mV , indicating good repeatability under controlled measurement protocol and temperature conditions. However, as the number of tested devices was limited ( N=2 or 3), a broader evaluation of device-to-device variation will be addressed in future studies.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.25.pdf

"How Infineon controls and assures the reliability of SiC based power semiconductors," Infineon Technologies AG (2020).

X. Zhong, H. Jiang, G. Qiu, L. Tang, H. Mao, C. Xu, X. Jiang, J. Hu, X. Qi, and Li Ran, IEEE Transactions on Power Electronics, Vol.37, No.2, (2022) 1998-2008.

Y. Enjoji, N. Iwamuro, and H. Yano, ICSCRM 2023, (2023) Mo.C.11.

H. Yano, Y. Enjoji, R. Shingo and N. Iwamuro, ICSCRM 2024, Vol.8, (2024) pp.367-358.

M.W. Feil, K. Waschneck, H. Reisinger, J. Berens, T. Aichinger, P. Salmen, G. Rescher, W. Gustin and T. Grasser, IRPS 2023, 3B.1, (2023) pp.1-10.

M.W. Feil, K. Waschneck, H. Reisinger, J. Berens, T. Aichinger, S. Prigann, G. Pobegen, P. Salmen, G. Rescher, D. Waldhoer, A. Vasilev, W. Gustin, M. Waltl and Tibor Grasser, IEEE Transactions on electron devices, Vol.71, No.7, (2024) pp.4210-4217.

T. Grasser, M. W. Feil, K. Waschneck, H. Reisinger, J. Berens, D. Waldhoer, A. Vasilev, M. Waltl, T. Aichinger, M. Bockstedte, W. Gustin and Gregor Pobegen, IEEE Transactions on electron devices, Vol.71, No.7, (2024) pp.4218-4226.

ECPE, "Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles" ECPE Guideline AQG 324, (2025) QL-09.

JEITA standards, "Guidelines for Compound Power Semiconductor Device Reliability Test Method Amendment 1", JEITA EDR-4713 Amend.1, (2023) Appendix E.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 31-37

doi: 10.4028/p-zj4Y9l

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2026-01-22

Accepted:
2026-02-28

Online:
2026-05-18

Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

The original version of this paper is available on https://www.scientific.net/KEM.1054.31.pdf

Jihong Zhu a, Jingjing Cui b, Jinying Yu c, Bao Hu d, Ming Jiang e and Baocheng Yuan f

Li Auto Inc. Beijing 101300, China

a  zhujihong@lixiang.com, b  cuijingjing@lixiang.com, c  yujinying@lixiang.com, d  hubao@lixiang.com, ejiangming5@lixiang.com, , yuanbaocheng@lixiang.com

Keywords: SiC MOSFETs, dual-bias, lifetime prediction, dual-acceleration-factor E-model, edge-thinning.

Abstract

This study investigated the reliability challenges of SiC MOSFETs under continuous dualbias stress conditions in electric vehicle (EV) applications. Accelerated dual-bias time-dependent dielectric breakdown (DB-TDDB) tests were performed on 1.2 kV SiC MOSFETs by applying a negative gate-source voltage and a high drain-source voltage simultaneously. Experimental analysis and TCAD simulations revealed a nonlinear coupling effect between gate and drain biases, leading to a spatial relocation of the maximum gate oxide electric field under dual-bias conditions. An improved dual-acceleration-factor E-model was proposed to characterize this behavior. Based on this model, the projected lifetime at 1 ppm failure rate is 5.11×1013 hours, exceeding the 20 -year automotive standard (AEC-Q101) by several orders of magnitude. Furthermore, failure analysis identified edge-thinning and JFET-region effects as two primary degradation mechanisms affecting gate oxide reliability, and corresponding process and design optimizations are proposed to mitigate this vulnerability. The findings offer critical insights for improving the reliability of SiC MOSFETs in EV applications under prolonged dual-bias stress.

Introduction

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Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) have become the preferred choice for electric vehicle (EV) traction inverters owing to their exceptional electrical and thermal properties [1, 2]. High temperature reverse bias (HTRB), high temperature gate bias (HTGB), and constant-voltage time-dependent dielectric breakdown (TDDB) testing represent standard methodologies for assessing the reliability and lifetime of SiC MOSFETs. However, these conventional approaches typically evaluate individual stress factors in isolation, critically failing to account for the simultaneous application of drain-source and gate-source bias voltages that SiC MOSFETs experience during the switching-off duration in traction inverter applications. The conventional methodologies neglect the coupled effects arising from the simultaneous application of gate and drain biases, leading to a significant gap in understanding degradation mechanisms and accurate lifetime modeling under combined electrical stress conditions.

Furthermore, in practical applications such as the sentry mode of some EVs, SiC MOSFETs are required to endure prolonged periods blocking high bus voltages while parked. This significantly extends the device's actual operational duration. Consequently, it is imperative to reassess SiC MOSFET reliability and lifetime predictions based on these actual operational conditions in EVs.

In this study, the lifetime characteristics of 1.2 kV SiC MOSFETs (Fig. 1(a)) were investigated through dual-bias time-dependent dielectric breakdown (DB-TDDB) testing. By integrating experimental results with TCAD simulations, an improved dual-acceleration-factor E-model was established for lifetime prediction under dual-bias conditions. Failure analysis further identified distinct gate oxide failure locations that correlated with different real-time monitored drain-source leakage current ( IDSS ) trends, significantly advancing the understanding of degradation mechanisms under dual-bias stresses.

Experiments and Results

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The devices used in this study are 1.2kV/16 mΩ rated planar MOSFETs packaged in TO-247. The fabrication process and device structure, previously reported in literature [6], are illustrated in Fig. 1(a). To investigate dual-bias stress mechanisms, reverse drain-source bias and negative gate voltage were applied to the device under test (DUT). The DB-TDDB test configuration is shown in Fig. 1(b). Prior to the main experiment, gate oxide V-ramp characterization was performed to determine the negative gate breakdown voltage which was -50 V at a leakage current threshold of 1 mA , as shown in Fig. 2(a). Accordingly, 90% of this value (−45 V) was selected as the aging condition. During testing, a negative gate-source voltage ( VGS=−45 V ) was applied to the DUT while maintaining VDS  at 880 V (matching the actual bus voltage in EV traction inverters) at 175∘C. Device failure was identified by monitoring the drain leakage current ( IDSS ) behavior, which was characterized by either a sudden increase or a drop to zero (indicating fuse burnout).

[picture]

Fig. 1. (a) Structure of SiC MOSFET. (b)Test circuit for dual-bias TDDB test.

Fig. 1. (a) Structure of SiC MOSFET. (b)Test circuit for dual-bias TDDB test.

Complementary TDDB characterization was also conducted under identical gate bias condition ( VGS=−45 V, Tj=175∘C ) for comparison. The results clearly demonstrate that the single-stress TDDB lifetime is significantly longer than that under DB-TDDB, confirming that the dual-stress condition (with additional reverse bias voltage applied) accelerates device degradation. To determine the temperature acceleration factor, constant-voltage TDDB tests ( VGS=+45 V ) were performed at different temperatures ( Tj=125∘C,150∘C, and 175∘C ). The Weibull distributions of the time-tobreakdown ( tBD ) are shown in Fig. 2(b). Each test group comprised 60 samples, and testing continued until a cumulative failure rate of at least 63% was reached (corresponding to failure in 38 devices).

[picture]

Fig. 2. (a)The gate oxide breakdown characteristics. (b)Weibull distributions of tBD under accelerated stress conditions.

Fig. 2. (a)The gate oxide breakdown characteristics. (b)Weibull distributions of t B D under accelerated stress conditions.

TCAD Simulation and Lifetime Modeling

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To characterize gate oxide stress states under various accelerated conditions, Silvaco TCAD simulations were performed to analyze the gate oxide electric field distribution under different VGS and VDS combinations. The simulations revealed two distinct patterns: (1) Under standard reverse bias conditions, the maximum gate oxide electric field ( Emax ) was localized in the JFET region; (2) When applying the proposed DB-TDDB stress framework, Emax  spatially shifted to the source region, as quantitatively demonstrated in Fig. 3.

[picture]

Fig. 3. Simulation of the gate oxide field distribution under (a) standard reverse bias situation ( VDS=880 V ) and (b) dual-bias condition ( VDS=880 V, VGS=−45 V ).

Fig. 3. Simulation of the gate oxide field distribution under (a) standard reverse bias situation ( V D S = 880 V ) and (b) dual-bias condition ( V D S = 880 V , V G S = − 45 V ).

This spatial redistribution of Emax  indicates that dual-bias operation induces a nonlinear fieldcoupling effect between the gate and drain voltages. To account for this interaction, we developed a dual-acceleration-factor E-model:

TTF=A0*exp(EakT)*exp(−γ1EOX)*exp(−γ2VDC).(1)

Given the computational complexity of directly deriving the gate oxide electric field from drain voltage, an empirical approach was adopted to quantify the voltage acceleration factor. In this model, A0 is a constant, while Ea represents the temperature acceleration factor. The parameters γ1 and γ2 correspond to the acceleration factors for gate-voltage and drain-bias, respectively. Notably, the activation energy depends on the bond dissociation energy of the gate oxide under standard Boltzmann thermal process, so we obtained Ea using TDDB tests at different temperatures [7]. Acceleration coefficients were quantified through both single and dual-bias TDDB tests:

Activation energy: Ea=0.532eV

Gate-voltage acceleration factor: γ1=3.9 cm/MV

Drain-voltage acceleration factor: γ2=0.5kV−1

Weibull analysis (shape parameter β=2.52 ) enabled lifetime extrapolation:

tqtp=[ln(1−F(tq))ln(1−F(tp)))1β.(2)

This study primarily focused on two critical operational scenarios: the actual operating equivalent condition ( VDS=880 V, VGS=−5 V, Tj=100∘C ) and the maximum rating condition ( VDS=1200 V, VGS=−10 V, Tj=175∘C ), as summarized in Table 1. Notably, even under the maximum rating scenario, the predicted lifetime at the 1 ppm failure level ( 1.1×109 hours) substantially exceeds the 20 -year service life requirement specified in the AEC-Q101 Rev-H qualification standard for automotive power electronics. The complete experimental matrix, including the extracted time-tofailure (TTF) at 63% failure level and corresponding fitting results, is comprehensively summarized in Table 1 and graphically represented in Fig. 4.

Table 1. The test matrix and fitting results.

Groups | Test conditions | T63 [h] | T1% [h] | T0.01% [h] | T10 ppm [h] | Tl ppm [h]
A | VDS = 880 V, VGS = -40.5 V, Tj = 175 °C | 31.5 | / | / | / | /
B | VDS = 0 V, VGS = -40.5V, Tj = 175 °C | 49.3 | / | / | / | /
C(fitting) | VDS = 880 V, VGS = -5V, Tj = 100 °C | 1.2 × 10¹⁶ | 2.0 × 10¹⁵ | 3.2 × 10¹⁴ | 1.3 × 10¹⁴ | 5.1 × 10¹³
D(fitting) | VDS = 1200 V, VGS = -10V, Tj = 175 °C | 2.6 × 10¹¹ | 4.32× 10¹⁰ | 6.8 × 10⁹ | 2.8 × 10⁹ | 1.1 × 10⁹

[picture]

Fig. 4. (a) Field-accelerated lifetime extrapolation based on the VDS. (b) Cumulative failure rates corresponding to operation lifetime.

Fig. 4. (a) Field-accelerated lifetime extrapolation based on the V D S . (b) Cumulative failure rates corresponding to operation lifetime.

Failure Mechanism Analysis

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During the dual-bias testing, the real-time IDSS of each DUT was continuously monitored with three distinct failure modes identified:

Mode A: The I DSS abruptly drops to zero.
Mode B: The IDSS exhibits a sharp increase followed by a gradual decline.
Mode C: The I DSS  shows a progressive increase without recovery.
Representative real-time IDSS characteristics for each failure mode are illustrated in Fig. 5(a). Statistical analysis of the failure distribution revealed that Mode A accounted for 70% of cases ( 35 out of 50), Mode B for 26% ( 13 out of 50 ), and Mode C for 4% ( 2 out of 50 ), as summarized in Fig. 5(b).

[picture]

Fig. 5. (a) Inline IDSS current with different failure modes. (b) The proportions of different failure modes.

Fig. 5. (a) Inline IDSS current with different failure modes. (b) The proportions of different failure modes.

To elucidate the underlying failure mechanisms associated with each mode, comprehensive failure analysis was conducted on all three failure types. This established a clear correlation between the observed electrical characteristics and distinct physical failure locations within the gate oxide. For the dominant Mode A ( 70% occurrence), failures are located at the edge of the active area, confirming this region as a primary reliability weakness in the chip structure. Cross-sectional TEM imaging was performed to further investigate the physical origin of this phenomenon. Quantitative analysis revealed a gate oxide thickness of 47.1 nm at the active area edge, significantly thinner than the 50 nm measured in the center region (Fig. 6). This thickness variation directly correlates with local electric field enhancement in the edge region, accounting for breakdown more often here. These findings are consistent with the established edge effect in power devices [8], wherein field crowding at structural discontinuities amplifies local electric fields.

[picture]

Fig. 6. (a)The failure location of Mode A. (b)TEM image of the gate oxide at the edge and the center of the active area.

Fig. 6. (a)The failure location of Mode A. (b)TEM image of the gate oxide at the edge and the center of the active area.

For Mode B and Mode C, each occurred in distinct regions that matched their electrical behaviors. Mode B failures occurred in the JFET region, while Mode C failures originated in the channel, as schematically depicted in Fig. 7.

[picture]

Fig. 7. Image of the failure locations of (a) Mode A (b) Mode B and (c) Mode C.

Fig. 7. Image of the failure locations of (a) Mode A (b) Mode B and (c) Mode C.

The electrical characteristics of gate oxide failures exhibit location-dependent mechanisms governed by fundamental physical processes. Under dual bias conditions, hole tunneling occurs at the semiconductor-oxide interface. This creates distinct operational regimes: A very thin inversion
layer in the n-type SiC JFET region contains only a small number of holes, whereas majority carrier holes accumulate at the P -well/ SiO2 interface in the channel region, as shown in Fig. 8. This physical asymmetry therefore leads to contrasting failure manifestations. Breakdown in the channel region (Mode C) exhibits a continuously increasing current characteristic due to the abundance of majority carriers. Conversely, in the JFET region (Mode B), the absence of holes creates a non-replenishable charge condition at the n−SiC/SiO2 interface, resulting in the observed gradual leakage current decay following breakdown.

[picture]

Fig. 8. Holes distribution in a cell under dual stress conditions.

Fig. 8. Holes distribution in a cell under dual stress conditions.

For failure Mode A (active area edge breakdown), analysis identified a primary cause: gate oxide thickness non-uniformity resulting from pattern-dependent oxidation rate variations during thermal oxidation. Process improvements aimed at improving oxidation uniformity, including optimized temperature ramping rates and ambient gas flow dynamics, could reduce Mode A occurrence by enhancing gate oxide thickness homogeneity. In contrast, failure Mode B (JFET region breakdown) originates mainly from inherent electric field crowding in the highly doped JFET region, where simultaneous drain stress and gate bias cause localized field enhancement. Design optimizations such as doping profile adjustments and gate structure modifications can effectively mitigate field crowding, thereby reducing peak field strength. Experimental validation has demonstrated that combining both process and design optimizations can collectively address 96% of the identified reliability weaknesses. Future work will focus on:

Advanced oxidation process control for sub-nanometer-level gate oxide uniformity.

TCAD-guided design optimization of JFET structures.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1054.31.pdf

In conclusion, this study established an enhanced DB-TDDB methodology that incorporates both negative gate-voltage effects and reverse-bias coupling stresses under actual operational conditions. Through comprehensive gate oxide lifetime testing using this framework, key acceleration factors were quantitatively extracted ( γ1=3.9 cm/MV for gate voltage, γ2=0.5kV−1 for drain bias). Multivariable stress analysis yielded a projected operational lifetime under combined electrothermal stress conditions. Failure mode analysis revealed distinct spatial distributions of degradation mechanisms: the predominant failure mode ( 70% occurrence) localized at the active area edge, while 26% failures occurred in the JFET region. These reliability limitations can be addressed via process optimization and design improvements. The proposed methodology and associated findings provide critical insights for developing more reliable SiC power devices for automotive applications.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.31.pdf

C.C. Wu, U.S. Rout, Y.L. Wang, Y.L. Lin and J.S. Hu, A comparative analysis of SiC MOSFET performance in a traction inverter, IEEE Asia Pacific Conference on Circuits and Systems. (2024) 377-381.

B. Shi, A. I. Ramons, Y. Liu, H. Wang Y. Li, S. Pischinger and J. Ander, A review of silicon carbide MOSFETs in electrified vehicles: Application, challenges, and future development, IET Power Electronics. 16 (2023) 2103-2120.

G. Rescher, G. Pobegen, T. Aichinger and T. Grasser, Preconditioned BTI on 4H-SiC: Proposal for a nearly delay time-independent measurement technique, IEEE Trans on Electron Devices. 65 (2018) 1419-1425.

W. Jouha, M. Masmoudi, A. E. Oualkadi, E. Joubert and P. Dherbécourt, Physical study of SiC power MOSFETs towards HTRB stress based on C-V characteristics, IEEE Transactions on Device and Materials Reliability. 20 (2020) 505-511.

S. Zhu, T. Liu, L. Shi, M. Jin, H.L. R. Maddi, M. H. White and A. K. Agarwal, Comparison of gate oxide lifetime predictions with charge-to-breakdown approach and constant-voltage TDDB on SiC power MOSFET, IEEE Workshop on Wide Bandgap Power Devices and Applications. (2021) 1-4.

J. Yu, J. Cui, B. Hu, J. Deng and B. Yuan, Analysis on BVDSS outlier chips and screening technology for 1.2 kV automotive SiC MOSFETs, International Symposium on Power Semiconductor Devices & ICs. (2025) 501-504.

K. Matocha, Member IEEE, G. Dunne, S. Soloviev and R. Beaupre, Time-dependent dielectric breakdown of 4 H -SiC MOS capacitors and DMOSFETs, IEEE Transactions on Electron Devices. 55 (2008) 1830-1834.

L.W.Y. Ying, D. K. Pal, R. Tan, N. H. Seng, M. Ong, T. G. Hong and W. J. Sang, Failure mechanism and improvement on gate oxide failure at the edge of LOCOS, IEEE International Conference on Semiconductor Electronics. (2012) 588-591.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 39-46

doi: 10.4028/p-ll6D0C

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-09

Accepted:
2026-02-28

Online:
2026-05-18

Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1054.39.pdf

Rajrupa Paul 1,a*, Reza Soleimanzadeh 1, b, Stephan Wirths 1,c

1 Hitachi Energy Research, 5404 Baden-Dättwil, Switzerland

a*rajrupa.paul@hitachienergy.com, b  reza.soleimanzadeh@hitachienergy.com, c  stephan.wirths@hitachienergy.com

Keywords: SiC-MOSFETs, reliability, dynamic gate switching (DGS), high-temperature gate bias (HTGB), time-dependent dielectric breakdown (TDDB).

Abstract

The long-term reliability of silicon carbide MOSFETs is critically influenced by the stability of the gate oxide, which is susceptible to degradation due to high defect densities at the oxide-semiconductor interface. This work presents a comprehensive investigation of gate oxide degradation in next-generation SiC MOSFETs, comparing planar and trench device topologies under both static and dynamic stress conditions. Time-dependent dielectric breakdown measurements reveal degradation phases that are strongly dependent on device topology. Comparative analysis of various gate stress methodologies shows that dynamic switching stress exerts a more pronounced impact on trench devices than on planar devices. Thus, highlighting the need of tailoring reliability test protocols to the specific device topology, rather than adopting a generalized approach.

Introduction

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Silicon Carbide (SiC) MOSFETs have emerged as vital components in high-power and hightemperature applications, offering significant advantages over traditional silicon-based devices [1]. Particularly, their superior material properties, including higher breakdown voltage, lower onresistance, and enhanced thermal conductivity, enable efficient operation under high voltage, high temperature, and fast switching conditions [2], [3]. These characteristics make SiC MOSFETs particularly attractive for demanding applications such as electric vehicles, renewable energy systems, and industrial power conversion. Despite its performance benefits, the long-term reliability of SiC MOSFETs remains a critical concern, specifically regarding gate oxide stability. The gate oxide in SiC devices are inherently more prone to degradation due to the high defect density at the SiC/SiO2 interface compared to their silicon counterparts [4]. This susceptibility leads to threshold voltage ( Vth  ) instability and gate oxide degradation, resulting in increased conduction losses, elevated leakage currents, parasitic turn-on events, and even premature dielectric breakdown, which ultimately compromising device performance, reliability, and system safety. The reliability of SiC MOSFETs is governed by both static and dynamic stresses acting on the gate oxide. Static stresses, such as those applied during time-dependent dielectric breakdown (TDDB) and high-temperature gate bias (HTGB) tests, accelerate intrinsic dielectric degradation and charge trapping under constant high electric fields and elevated temperatures, ultimately determining oxide lifetime and early failure risk. Additionally, dynamic stresses during real switching operation introduce degradation mechanisms that static stress tests cannot capture, most notably bias temperature instability (BTI) and gate switching instability (GSI). These mechanisms drive progressive threshold voltage drift through defect charging and recombination-enhanced reactions [5], [6], [7]. Recent studies have shown that BTI and GSI are the dominant mechanisms contributing to Vth  drift in SiC MOSFETs. BTI occurs under prolonged DC gate bias at elevated temperatures and involves charge trapping at the SiC/SiO2 interface and near-interface oxide traps. Both positive (PBTI) and negative (NBTI) stress conditions have been investigated, revealing that SiC devices exhibit larger Vth  shifts compared to silicon MOSFETs due to higher defect densities and carbon-related traps [8], [9]. In contrast, GSI is a dynamic degradation mode observed during high-frequency bipolar gate switching, where alternating electron and hole injection triggers recombination-enhanced defect reactions (REDRs), leading to progressive and sometimes partially reversible Vth  shifts [10], [11]. Although both BTI and GSI
contribute to threshold voltage shift during dynamic stress testing, GSI fundamentally differs from BTI in that it is primarily governed by the cumulative number of switching events and exhibits only a weak dependence on temperature. Together with static stress effects, these dynamic phenomena critically influence the long-term reliability of SiC MOSFETs, underscoring the need for integrated assessment approaches to ensure accurate lifetime prediction and robust device design. This work investigates the degradation behavior of SiC MOSFETs under both static and dynamic stress conditions. The study encompasses planar and trench device topologies, providing a comparative analysis that highlights key similarities and differences in their stress responses.

Experimental Details

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In this study, two distinct SiC MOSFET topologies were investigated: planar- and trench-type devices. An overview of the tested SiC MOSFETs is provided in Table 1. The experimental methodology incorporates both static and dynamic stress techniques to comprehensively assess gate oxide reliability. Static stress tests include TDDB and HTGB, whereas dynamic stress tests consist of dynamic gate switching (DGS). This approach enables the assessment of both intrinsic gate oxide degradation mechanisms and threshold voltage instabilities that are relevant under practical operating conditions.

Table 1. Overview of tested commercial SiC MOSFETs.

Device Type | Current Rating | Typical Vth | RDS,ON
Planar | 160 A | 2.4 V | 9–15 mΩ
Trench | 150 A | 4.4 V | 8.4–17.6 mΩ

The devices were configured in a discrete TO-247-4L package. For each static test, 10 DUTs were allocated per device type and stress conditions. TDDB and HTGB measurements were performed using a high-temperature PCB test board equipped with multiple TO- 247 sockets. This board was housed within a temperature-controlled oven to ensure stable thermal conditions during stress testing. While the setup supports the optional application of drain-source voltage, all static tests conducted in this study were performed with the drain and source terminals shorted. The modular design of the setup allows for simultaneous operation of multiple test boards, each with independently controlled voltage parameters. The DAQ system consisted of a LabJack unit interfaced with a custom measurement card populated with shunt and protection resistors. Each device was connected in parallel, with gate voltage applied through a voltage divider comprising a shunt resistor and a protection resistor. The voltage drop across shunt resistor is used to calculate the leakage current, while protection resistor limits the input voltage to the LabJack in case of dielectric failure.

For dynamic stress tests a commercial setup was used, equipped with pulsed width modulation and power stage for stress generation [12]. Here 40 DUTs were allocated per device type and stress conditions. Switching frequency was set to 300 kHz with a duty cycle of 50%. Gate-source on-state voltage (V GS,ON  ) and gate-source off-state voltage (V GS,OFF  ) were set according to the device data sheet recommended maximum and minimum gate voltage limit. A gate resistor of 3.9Ω was used to ensure no over- and undershoot of the gate-source voltage. The drain was shorted to source during the stress cycle. The readout circuit measures the Vth  followed by the drain-source on resistance (RDS,ON). Prior to Vth  measurement, a preconditioning sequence is applied. This begins with a 100 ms positive preconditioning pulse at the device-specific VGS,ON, followed by a down-slope transition from 9.5 V to 0 V to determine the down-slope threshold voltage ( Vth, down  ), during which the drain current is maintained at 10 mA . Subsequently, a 100 ms negative preconditioning pulse at the devicespecific VGS, OFF  is applied. This is followed by an up-slope transition from 0 V to 9.5 V to determine the up-slope threshold voltage ( Vth,up  ), with a drain current of 10 mA . Finally, the on-state resistance ( RDS,ON ) is measured using a drain pulse current of 10 A and the corresponding VGS,ON for the device.

Results and Discussion

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As part of device pre-characterization, gate leakage current ( IG ) measurements were performed at 175∘C until device failure, and threshold voltage values were extracted across a range of temperatures. These preliminary evaluations are essential for establishing appropriate stress conditions for subsequent long-term tests. Fig. 1(a) shows the gate leakage current obtained from planar- and trench-type devices; the trench-type SiC MOSFETs exhibit lower leakage current at the same voltage compared to planar type. This is primarily due to the lower effective electric field in trench devices, which is a result of the thicker oxide layer typically used in trench-type devices [13]. Additionally, the threshold voltages of the devices were determined prior to conducting stress tests. The transfer characteristics for both device types are plotted in Fig. 1(b), both devices show an expected negative temperature coefficient for Vth  and a nominal hysteresis of 80−100mV.

[picture]

Fig. 1. (a) Gate current-voltage characteristics, and (b) Transfer characteristics, obtained from planar and trench devices.

Fig. 1. (a) Gate current-voltage characteristics, and (b) Transfer characteristics, obtained from planar and trench devices.

For TDDB measurements, three distinct bias conditions were applied to each device topology, while the test temperature was consistently maintained at 175∘C. The bias conditions applied to planar-type devices were 35 V,34 V, and 33 V , while higher biases of 45 V,44 V, and 43 V were applied to the trench-type devices. The devices were stressed until failure, with gate leakage current continuously monitored throughout the stress duration. The oxide breakdown is characterized by an abrupt change in the measured current across each device, which corresponds to the typical time-tofailure for the device. Fig. 2(a) and Fig. 2(c) show the gate leakage current as function of time (IG-t) for all individual MOSFETs stressed at different bias conditions for the planar- and trench-type devices, respectively. For all the stress conditions the leakage current decreases with time till the device fails. The leakage current shows a sharper decline for the higher bias values. For the planartype devices the average time to failure shows a gradual decrease with increase in bias values. In contrast, the trench-type devices demonstrate an abrupt reduction in oxide lifetime at the highest stress condition. This behavior could suggest the activation of an additional degradation mode, which is triggered at highest applied bias value at 175∘C. Fig. 2(b) and Fig. 2(d) depict the IG−t plot in log-log scale for planar- and trench-type devices, respectively. It is clear that there are two distinct degradation phases for both trench- and planar-types of devices. The first phase that is depicted till to shows no significant change in the measured leakage current, this phase is characterized by minimal charge trapping that causes the slight decrease in the measured leakage current, and it is reported to have negligeable influence on the V′′ and Rsd,On [14]. The second phase starts at the end of to and lasts till the device fails ( tf ), this phase is known as the 'wear-out' phase [14]. During the 'wear-out' phase the gate leakage current drops significantly, indicating a high-degree of charge trapping during this phase. This drop in the gate leakage current has been previously attributed to the build-up of electrons, which in turn results in an increase in the threshold voltage [15]. The 'wear-out' phase of the trench-type devices is notably different than the planar-type devices, it shows a significantly higher and longer decrease in leakage current until device failure. This is mainly attributed to a larger number of electron trap sites at the interface or in the dielectric layer [13], [16].

[picture]

Fig. 2. Evolution of gate leakage current obtained from constant voltage TDDB at 175∘C for, (a) planar devices under different stress conditions, (b) planar device depicted in double-logarithmic plot at 35 V bias condition, (c) trench devices under different stress conditions, (b) trench device depicted in double-logarithmic plot at 45 V bias condition.

Fig. 2. Evolution of gate leakage current obtained from constant voltage TDDB at 175 ∘ C for, (a) planar devices under different stress conditions, (b) planar device depicted in double-logarithmic plot at 35 V bias condition, (c) trench devices under different stress conditions, (b) trench device depicted in double-logarithmic plot at 45 V bias condition.

The measured time-to-failure is used to construct the Weibull plot for each bias condition. A twoparameter Weibull distribution has the cumulative density function of the following form:

F(t)=1−exp[−(tη)β](1)

This can be alternatively expressed as:

ln[−ln(1−F(t))]=βln(t)−βln(η)(2)

where, b and h are the shape parameter and characteristic lifetime of the Weibull distribution [15]. A Weibull plot is obtained by plotting ln(−ln(1−F(t))) as function of time in log scale. The slope of this plot corresponds to b, while the intercept provides h. Alternatively, h is also defined as the time at which 63% of the devices fail for the given stress condition. The Weibull plot obtained from planarand trench-type devices is shown in Fig. 3(a) and Fig. 3(c), respectively. The shape parameters from the Weibull distributions obtained from both types of devices are greater than 1 , indicating the main reason for failure is aging related. The slight variations in the shape parameters across the different stress conditions could stem from the limited sample size. However, a large shift in the shape parameter that is observed for the highest stress condition for the trench-type devices could indicate a failure mode transition, as previously highlighted in the IG-t plot for the same device type (see Fig. 2(c)). It has been previously reported that trench-type SiC MOSFET may experience accelerated failure under high bias due to localized field enhancements and trap-assisted tunneling effect [13], [17]. Further, the lifetime estimation plots are shown in Fig. 3(b) and Fig. 3(d) for planar- and trenchtype devices, respectively. By plotting the h for each bias condition, a linear fit can be obtained. This fit is then used to extrapolate the intrinsic gate oxide lifetime of the devices at lower operating oxide fields. The estimated lifetime under operational stress is significantly higher for trench-type devices
compared to planar-type devices; however, this may be an overestimation caused by a failure mode transition at the highest applied bias conditions. Previous report on TDDB performed on commercially available devices highlighted the importance of not over stressing the gate oxide as this might lead to a modified failure modes that can influence the lifetime estimation [15].

[picture]

Fig. 3. (a) and (b) Weibull distribution and projected time to failure with t63% for planar devices. (c) and (d) Weibull distribution and projected time to failure with t63% for trench devices.

Fig. 3. (a) and (b) Weibull distribution and projected time to failure with t 63 % for planar devices. (c) and (d) Weibull distribution and projected time to failure with t 63 % for trench devices.

The static HTGB test was conducted to evaluate the Vth stability under prolonged positive gate bias stress. A constant gate bias of 25 V was applied under a temperature condition of 175∘C for a total duration of 1000 hours. The Vth  was recorded at three intervals: prior to stress application (prestress), at the midpoint ( 500 hours), and at the end ( 1000 hours). Threshold voltage at 175∘C is plotted as a function of stress duration for the planar- and trench-type devices in Fig. 4(a) and Fig. 4(b), respectively. Typically, under positive gate bias stress, the Vth  is expected to drift to higher values due to electron trapping in the gate oxide or at the SiC/SiO2 interface [18], [19], [20]. Electrons can be trapped in pre-existing or stress-induced trap sites. It is evident from Fig. 4(a) that the planar-type devices exhibit a more pronounced Vth  shift, with a total drift of 1.45 V over 1000 hours of stress. In contrast, the trench-type devices show a moderate Vth  shift of 0.5 V over the same stress period. It should be noted that given both the types of devices were subjected to same gate bias, the effective electric field for planar-type device is much higher due to the thinner oxide layer. Making the planartype device more susceptible to electron injection and trapping, thereby accelerating the Vth  drift.

[picture]

Fig. 4. Threshold voltage measured before and after static HTGB for (a) planar, and (b) trench devices.

Fig. 4. Threshold voltage measured before and after static HTGB for (a) planar, and (b) trench devices.

Following static stress methods, which evaluate gate oxide reliability under constant bias conditions, it is equally important to assess device behavior under dynamic stress. In practical applications, SiC MOSFETs experience repetitive gate voltage transitions rather than steady-state bias. DGS was used to capture degradation mechanisms that are pertinent to dynamic stress.

[picture]

Fig. 5. Threshold voltage drift as a function of stress cycles measured at 150∘C and 175∘C for (a) planar devices, (b) trench devices, (c) planar devices depicted in double-logarithmic plot, and (d) trench devices depicted in double-logarithmic plot.

Fig. 5. Threshold voltage drift as a function of stress cycles measured at 150 ∘ C and 175 ∘ C for (a) planar devices, (b) trench devices, (c) planar devices depicted in double-logarithmic plot, and (d) trench devices depicted in double-logarithmic plot.

Two different temperature conditions were used for the DGS measurements, specifically 150∘C and 175∘C. For each temperature, 40 devices were tested per device type. The planar-type devices were stressed with VGS,ON=+19 V and VGS,OFF=−8 V. Fig. 5(a) depicts the Vth  drift as a function of number of stress cycles for planar-type devices. The Vth drift progression for the planar-type devices is similar for both temperatures, accounting for a total drift of 0.4 V . Whereas the Vth  drift for the trench-type devices demonstrates a clear distinction between the two temperatures, as shown in Fig. 5(b). Fig. 5(b) depicts the Vth  drift as a function of number of stress cycles, here the devices were stress with VGS,ON=+25 V and VGS,OFF=−11 V. For the higher temperature the Vth  drift was more severe resulting in a total Vth  drift of 0.56 V . Additionally, no substantial drift in the RDS,ON value was observed after the total stress period for either device type. Indicating the Vth  drift does not have a significant impact on the RDS,ON value. Fig. 5(c) and Fig. 5(d) illustrate the Vth  drift as a function of stress cycles for different temperatures in a double-logarithmic plot for planar- and trenchtype devices, respectively. The total V th drift is expected to be composed of BTI and GSI parts, where the GSI component is dependent on the cumulative number of switching cycles [10], [21]. Whereas the BTI component is temperature dependent and frequency independent [10], [11]. For the given stress conditions, we observed the planar-type devices only display the BTI component, which can be fitted by power law exponent of 0.2 . For the trench-type devices a deviation from the BTI component is observed at higher switching cycles, predominantly noticeable for the higher temperature. The BTI component has a power law slope of 0.17 and 0.19 for 175∘C and 150∘C, respectively. The deviation observed for the trench-type devices at higher switching cycles has a slope of lower than 1, this slope is lower than the expected power law slope of unity for the GSI component [10].

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.39.pdf

This study provides a detailed assessment of gate oxide stability and degradation mechanisms in next-generation SiC MOSFETs, comparing planar and trench topologies under static and dynamic stress conditions. The results demonstrate that trench-type devices generally exhibit superior threshold voltage stability under static stress conditions, this is most likely due to the thicker gate oxide used in trench-type devices in comparison to planar-type devices. Thus, calibrating the stress based on oxide thickness is crucial. Additionally, trench-type devices show higher predicted lifetime under operating conditions. However, this can be an overestimation from including high-bias stress in TDDB that leads to a shift in degradation mode. Trench-type devices are more susceptible to accelerated failure at extreme bias, likely due to localized field effects. Dynamic stress testing indicates the dominant contributor to the total Vth drift is the BTI component. Planar-type devices show minimal temperature dependence in Vth  drift, whereas trench-type devices show a pronounced temperature dependence, resulting in higher Vth  drift compared to static stress conditions. Furthermore, at higher switching cycles, the Vth  drift in trench-type devices deviates from the expected BTI behavior, suggesting the on-set of additional degradation mechanisms. These findings underscore the importance of adapting reliability assessment methodologies to specific device topologies, rather than relying on generalized approaches, to ensure robust design and accurate lifetime prediction for SiC MOSFETs in advanced power electronics applications.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.39.pdf

D. J. Lichtenwalner et al., "Performance and Reliability of SiC Power MOSFETs," MRS Adv., vol. 1, no. 2, pp. 81-89, Jan. 2016, doi: 10.1557/adv.2015.57.

S. Wirths et al., "Study of 1.2 kV High-k SiC Power MOSFETS Under Harsh Repetitive Switching Conditions," in 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2021, pp. 107-110. doi: 10.23919/ISPSD50666.2021.9452286.

G. Romano, S. Wirths, A. Mihaila, Y. Arango, A. Ruiz, and L. Knoll, "Rugged Dynamic Behaviour of 3.3 kV SiC Power MOSFETs with High-k Gate Dielectric," in 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD), May 2021, pp. 263-266. doi: 10.23919/ISPSD50666.2021.9452193.

M. W. Feil, K. Puschkarsky, W. Gustin, H. Reisinger, and T. Grasser, "On the Physical Meaning of Single-Value Activation Energies for BTI in Si and SiC MOSFET Devices," IEEE Trans. Electron Devices, vol. 68, no. 1, pp. 236-243, Jan. 2021, doi: 10.1109/TED.2020.3036321.

A. K. Biswas et al., "Hole-Induced Threshold Voltage Instability Under High Positive and Negative Gate Stress in SiC MOSFETs," in 2024 IEEE International Reliability Physics Symposium (IRPS), Apr. 2024, pp. 1-5. doi: 10.1109/IRPS48228.2024.10529422.

S. Yu et al., "Threshold Voltage Instability of Commercial 1.2 kV SiC Power MOSFETs," in 2020 IEEE International Reliability Physics Symposium (IRPS), Apr. 2020, pp. 1-5. doi: 10.1109/IRPS45951.2020.9129071.

B. Hull et al., "Reliability and stability of SiC power mosfets and next-generation SiC MOSFETs," in 2014 IEEE Workshop on Wide Bandgap Power Devices and Applications, Oct. 2014, pp. 139-142. doi: 10.1109/WiPDA.2014.6964641.

C. X. Zhang et al., "Origins of Low-Frequency Noise and Interface Traps in MOSFETs," IEEE Electron Device Lett., vol. 34, no. 1, pp. 117-119, Jan. 2013, doi: 10.1109/LED.2012.2228161.

I. Matacena et al., " interface traps effect on SiC MOSFETs Gate capacitance with biased Drain," in 2022 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Jul. 2022, pp. 1-5. doi: 10.1109/IPFA55383.2022.9915748.

M. W. Feil et al., "Gate Switching Instability in Silicon Carbide MOSFETs-Part I: Experimental," IEEE Trans. Electron Devices, vol. 71, no. 7, pp. 4210-4217, Jul. 2024, doi: 10.1109/TED.2024.3397636.

T. Grasser et al., "Gate Switching Instability in Silicon Carbide MOSFETs-Part II: Modeling," IEEE Trans. Electron Devices, vol. 71, no. 7, pp. 4218-4226, Jul. 2024, doi: 10.1109/TED.2024.3397629.

M. Gebhardt and G. Lieser, "Comparison of Dynamic Gate Stress Test Results of SiC MOSFETs," in PCIM Europe 2024; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Jun. 2024, pp. 2764-2772. doi: 10.30420/566262391.

L. Shi et al., "Gate Oxide Reliability in Silicon Carbide Planar and Trench Metal-OxideSemiconductor Field-Effect Transistors Under Positive and Negative Electric Field Stress," Electronics, vol. 13, no. 22, p. 4516, Jan. 2024, doi: 10.3390/electronics 13224516.

P. Moens, S. Maslougkas, M. Avramenko, G. Gomez-Garcia, S. Kuzmanoska, and M. Domeij, "A Status Overview of SiC MOSFET Reliability," in 2024 IEEE International Electron Devices Meeting (IEDM), Dec. 2024, pp. 1-4. doi: 10.1109/IEDM50854.2024.10873560.

T. Liu, S. Zhu, M. H. White, A. Salemi, D. Sheridan, and A. K. Agarwal, "Time-Dependent Dielectric Breakdown of Commercial 1.2 kV 4H-SiC Power MOSFETs," IEEE J. Electron Devices Soc., vol. 9, pp. 633-639, 2021, doi: 10.1109/JEDS.2021.3091898.

M. Bhattacharya et al., "Analyzing the Impact of Gate Oxide Screening on Interface Trap Density in SiC Power MOSFETs Using a Novel Temperature-Triggered Method," Micromachines, vol. 16, no. 4, p. 371, Apr. 2025, doi: 10.3390/mi16040371.

Z. Wei et al., "Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example," Materials, vol. 15, no. 2, p. 457, Jan. 2022, doi: .

M. Chaturvedi, S. Dimitrijev, D. Haasmann, H. A. Moghadam, P. Pande, and U. Jadli, "Quantified density of performance-degrading near-interface traps in SiC MOSFETs," Sci. Rep., vol. 12, no. 1, p. 4076, Mar. 2022, doi: 10.1038/s41598-022-08014-5.

J. Rozen, S. Dhar, M. E. Zvanut, J. R. Williams, and L. C. Feldman, "Density of interface states, electron traps, and hole traps as a function of the nitrogen density in SiO 2 on SiC ," J. Appl. Phys., vol. 105, no. 12, p. 124506, Jun. 2009, doi: 10.1063/1.3131845.

S. T. Pantelides et al., "Si-SiO2 and SiC-SiO2 interfaces for MOSFETs - Challenges and advances".

J. R. Garcia-Mere, A. A. Gomez, J. Roig-Guitart, J. Rodriguez, and A. Rodriguez, "Aging Modeling and Simulation of the Gate Switching Instability Degradation in SiC MOSFETs," in 2024 IEEE Applied Power Electronics Conference and Exposition (APEC), Feb. 2024, pp. 653658. doi: 10.1109/APEC48139.2024.10509430.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 47-54

doi: 10.4028/p-6mHIuS

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2026-01-27

Accepted:
2026-02-26

Online:
2026-05-18

Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Saeed Jahdi 1,a*, Konstantinos Floros 2,b, Ingo Ludtke 2,c, Olayiwola Alatise 3,d and Martin Kuball 1,e

¹University of Bristol, Bristol, BS8 1UB, UK

2 Compound Semiconductor Applications Catapult, Newport, NP10 8BE, UK

3 University of Warwick, Coventry, CV4 7AL, UK

a* saeed.jahdi@bristol.ac.uk, b konstantinos.floros@csa.catapult.org.uk,

Keywords: SiC MOSFETs, packaging, dies, discrete, measurements, datasheet.

Abstract

This paper presents a comparative analysis of 1200 V Silicon Carbide (SiC) MOSFETs characterized at bare die level and in TO-247 packaging. Static parameters including transconductance (gm), drain leakage current ( IDS-OFF  ), output ( IDS −VDS  ) and transfer characteristics ( IDS−VGS ), gate threshold voltage ( VGS(th) ) and on-state resistance ( RDS(on) ) are examined. Results show that the TO-247 package introduces parasitic resistance/inductance and higher thermal impedance, leading to disrupted gm, though lower leakage IDS−OFF, shifted VGS(th), and elevated RDS(on). The study quantifies the discrepancy between intrinsic die behavior and packaged device performance, underscoring the need to de-embed packaging effects for accurate device modelling and optimization.

Introduction

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SiC MOSFETs are increasingly adopted in high-voltage, high-frequency power converters due to their high breakdown field, wide bandgap, and low specific on-resistance [1]. Device datasheets, however, are either derived from discrete packaged devices, where bond-wire inductance, lead-frame resistance, and limited thermal conduction influence measured performance, or on bare die which does not represent the actual final product. These parasitic and thermal effects in packaging could distort key device parameters such as gm,VGS(th), and RDS(on), complicating the extraction of intrinsic device properties required for physics-based modelling [2].

To address this, this paper presents a direct comparison made between bare die and TO-247 packaged SiC MOSFETs. Bare die measurements, performed with Kelvin probing and controlled chuck temperature, isolate intrinsic semiconductor behavior, while TO-247 results reflect applicationlevel operation under parasitic and thermal constraints. The discrepancies observed provide insights into the extent of packaging-induced artefacts and their relevance for both device benchmarking and converter design.

In short, we have characterized 1200 V Silicon Carbide (SiC) power MOSFETs from COOLCAD, to measure potential discrepancies that may arise between measurements performed on bare die versus those taken from devices in TO-247 packaging [3], due to the introduction of parasitic elements and thermal impedance in the package [4,5].

Measurements Set-Up

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The device characterizations were performed using a Keysight B1505A Power Device Analyzer/Curve Tracer, enabling high-voltage, high-current measurements with precision parameter extraction. For the TO-247 packaged devices, the N1265A high-current expander fixture was used as in Fig. 1, providing low-inductance Kelvin connections suitable for discrete characterization. For the bare die measurements, the devices were mounted on an MPI TS2000-HP semi-automatic on-wafer prober as in Fig. 2, which allows direct probing of source, drain, and gate pads with high accuracy and controlled chuck temperature.

The two setups introduce distinct measurement environments. The expander fixture for the TO-247 inevitably incorporates package-related parasitics, including bond-wire inductance, lead-frame resistance, and finite thermal conductivity through the case-to-ambient path. These effects manifest as increased RDS(on) and threshold voltage shifts due to higher influence of junction temperature. By contrast, on-wafer probing minimizes electrical parasitics via Kelvin contacts placed directly on the device pads and ensures efficient thermal management through the temperature-controlled chuck, thereby yielding values closer to the intrinsic device behavior.
Although any measurement system introduces small offsets, such as milliohm-level contributions to RDS(on) from cabling resistance or microamp-level offsets in leakage current from instrument resolution or equipment calibration precision, these errors are less significant compared to the impact of device packaging. For example, the TO-247 package can increase RDS( on ) due to series resistance and self-heating. Therefore, the observed discrepancies between bare die and packaged devices are primarily dominated by the parasitic and thermal constraints imposed by the package itself.

[picture]

Fig. 1. The Keysight B1505A Power Device Analyzer/Curve Tracer, enabling high-voltage, highcurrent measurements. For the TO-247 packaged devices, the N1265A expander fixture is used.

Fig. 1. The Keysight B1505A Power Device Analyzer/Curve Tracer, enabling high-voltage, highcurrent measurements. For the TO-247 packaged devices, the N1265A expander fixture is used.

[picture]

Fig. 2. The Keysight B1505A Power Device Analyzer for the bare die measurements too where the devices were mounted on an MPI TS2000-HP semi-automatic on-wafer prober.

Fig. 2. The Keysight B1505A Power Device Analyzer for the bare die measurements too where the devices were mounted on an MPI TS2000-HP semi-automatic on-wafer prober.

Analysis of Measurements Results

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Transconductance (gm).

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The experimental results presented in Fig. 3 offer critical insight into the influence of packaging on a foundational parameter: transconductance (gm). The transconductance measurements of the TO-247 packaged device display a more sharply peaked gm, reflective of instabilities observed when testing unpackaged devices and superior thermal management during probing. The properties, can however, display alternative trends if the measurement conditions are changed. For example, by reducing the pulse period from 200 ms to 10 ms , the impact of conduction power leading to internal heat generation and temperature rise is eliminated, enabling higher gm. The differences in gm peak shape and magnitude between bare die and packaged devices arise from the combined influence of thermal impedance, series resistance, amongst other parameters. The V DS applied for the measurements shown in Fig. 3 has been 10 volts. The range selected for VGS would is sufficient to support the conclusions regarding packaging-induced discrepancies.

[picture]

Fig. 3. Measurements of transconductance ( gm ) on the bare die, compared with the same die packaged as a TO-247 discrete in different test conditions.

Fig. 3. Measurements of transconductance ( g m ) on the bare die, compared with the same die packaged as a TO-247 discrete in different test conditions.

Drain-Source Leakage (Ids-off).

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Fig. 4 offers critical insight into the influence of packaging on another foundational parameter: the drain-source leakage current. The drain-source leakage current is consistently higher for the bare die, particularly at elevated drain voltages, due to the impact of environment on the bare die, leading to higher leakage, together with surface leakage induced by contamination, while the packaged device is fully protected from external influences. The differences also underline the importance of thermal
and parasitic considerations when interpreting the device datasheet values. Given the wide-bandgap of SiC, photo-generated effects under normal laboratory illumination are considered negligible compared with the leakage current levels measured. Furthermore, the leakage trends in Fig. 4 are consistent across the entire voltage range and do not show features typically associated with photoinduced leakage.

[picture]

Fig. 4. Measurement of drain-source leakage current (IDS-OFF) on the bare die, compared with the same die packaged as a TO-247 discrete.

Fig. 4. Measurement of drain-source leakage current (IDS-OFF) on the bare die, compared with the same die packaged as a TO-247 discrete.

Output Characteristics (Ids-Vds).

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Fig. 5 focuses on the output characteristics ( IDS−VDS ) in different test conditions, revealing the extent to which packaging influences the device's output behavior under various operating conditions. The bare die displays the expected output behavior with different triode and saturation regions, reflecting the ideal field-effect behavior of a well-controlled SiC MOSFET channel. However, the TO-247 device exhibits some discrepancies, including a more gradual transition to the saturation region and reduced drain current at high V DS at longer pulse widths. With reduction of pulse width and period, the impact of internal junction temperature build-up is reduced, relatively increasing the current of the packaged device. These shifts can be attributed to the increased RDS(on) and potential voltage drops across internal package resistance ( Rpkg ), as well as possible thermal degradation under extended bias conditions. Additionally, dynamic effects such as current crowding and self-heating within the package can distort the output curves, causing non-linearity and early onset of quasi-saturation. Longer pulse widths allow greater self-heating, which reduces IDS through increased RDS( on ) and mobility degradation. This effect is more pronounced in the TO-247 device due to higher thermal impedance and additional series resistance introduced by the package.

[picture]

Fig. 5. The comparison and discrepancy of output characteristics ( IDS−VDS ) between the bare die and TO-247 packaged device in different test conditions.

Fig. 5. The comparison and discrepancy of output characteristics ( I D S − V D S ) between the bare die and TO-247 packaged device in different test conditions.

Saturation (Vds-Vgs).

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

In Fig. 6, the comparison of VDS versus VGS curves and extracted gate threshold voltages (VGS(th)) between the two formats highlights further impacts of packaging. Initially, the device is in the cut-off region where the VGS is lower than the VGS(th). Once VGS increases beyond VGS(th) at low VDS values, the current starts to flow, and the device is in the linear mode, effectively as a high resistor. Once the VDS rises, the device effectively moves into the saturation mode of operation. The impact of additional resistance imposed by the packaging of the device means the onset of saturation is slightly delayed compared to the bare die. It must be noted that the pulse width affects saturation behavior through thermal effects. Longer pulses lead to delayed saturation due to increased effective RDS (on)  from selfheating and package resistance.

[picture]

Fig. 6. Comparison of saturation by VDS−VGS on the bare die, compared with the same die packaged as a TO-247 discrete.

Fig. 6. Comparison of saturation by V D S − V G S on the bare die, compared with the same die packaged as a TO-247 discrete.

Gate Threshold Voltage (Vth).

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Fig. 7 highlights the comparison of the extracted gate threshold voltages (VGS(th)). The limit for drain current to calculate the gate threshold voltage is 1 mA . During the measurements, the bare die showed a consistent threshold voltage with minimal hysteresis or drift due to its controlled thermal environment and the absence of mechanical or electrical stress. The TO-247 packaged device could demonstrate a slight shift in VGS(th), typically toward lower values, indicating temperature-induced threshold voltage drop and packaging-induced mechanical strain. Furthermore, voltage drops across the source connection in the TO-247 lead to inaccurate gate biasing, especially during fast transients, which can manifest as a threshold shift in measurement. The threshold voltage of the packaged device was measured to be slightly less than that of the bare die as the impact of internal temperature in packaged devices is higher, while the bare die is subject to surface leakage current. Nevertheless, it must be noted that the measured difference in VGS(th) between bare die and packaged devices is small and the difference is comparable to extraction uncertainty and likely influenced by a combination of temperature, surface effects, and measurement conditions.

[picture]

Fig. 7. Comparison of the gate threshold voltage on the bare die, compared with the same die packaged as a TO-247 discrete.

Fig. 7. Comparison of the gate threshold voltage on the bare die, compared with the same die packaged as a TO-247 discrete.

Transfer Characteristics (Ids-Vgs).

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Fig. 8 examines the transfer characteristics ( IDS−VGS ) of the device in bare die versus TO- 247 format. The V DS  applied in these measurements is 10 volts. Extending the VGS range is not necessary as the presented data demonstrates the key trends. The transfer characteristics of both devices show a steep increase in drain current with gate bias, suggesting high channel transconductance and uniform carrier mobility. This is especially true when testing with reduced pulse periods (pulse period reduced from 200 ms to 10 ms ) which minimizes the impact of self-heating. The packaged device curve peaks higher, due to the more stable measurement mechanism on the device terminals and reduced surface leakage current, despite better thermal dissipation by the bare die on the Chuke.

[picture]

Fig. 8. Comparison of transfer characteristics ( IDS−VGS ) on the bare die, compared with the same die packaged as a TO-247 discrete in different test conditions.

Fig. 8. Comparison of transfer characteristics ( I D S − V G S ) on the bare die, compared with the same die packaged as a TO-247 discrete in different test conditions.

On-state Resistance (Rdd-on).

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Fig. 9 has depicted the RDS-ON  values as another key parameter to evaluate. The RDS(on)  values, derived from the linear region of these curves, are significantly higher in the TO-247 packaged device due to series resistances introduced by bond wires and lead frames, as well as junction heating under load. This increased RDS( on ) not only affects conduction losses but also reflects how real-world packaging can obscure the true performance potential of the semiconductor die. This emphasizes the critical need for careful de-embedding of packaging effects in both datasheet interpretation and advanced power circuit design. However, the apparent reduction of extracted RDS(on) in these measurements for the packaged device at high current is not superior intrinsic performance. This is likely to have arisen from contact resistance, probe effects in bare-die measurements, and differing self-heating dynamics under pulsed conditions. For the bare-die measurements, true Kelvin sensing was implemented by placing separate force and sense probes directly on the source and drain pads, thereby minimizing series resistance and isolating the intrinsic die behavior. For the TO-247-3 package, a dedicated Kelvin source terminal does not exist, so the measured on-state resistance necessarily includes the
contribution of the source lead, bond wires, and internal package resistance. However, the Keysight N1265A fixture provides low-inductance connections and remote sensing up to the package terminals.

[picture]

Fig. 9. Comparison of the on-state resistance ( RDS−ON ) on the bare die, compared with the same die packaged as a TO-247 discrete.

Fig. 9. Comparison of the on-state resistance ( R D S − O N ) on the bare die, compared with the same die packaged as a TO-247 discrete.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

The comparisons confirm that TO-247 packaging modifies the measured static behavior of 1200 V SiC MOSFETs. Direct junction temperature measurement was not performed. Packaging-induced parasitic elements impact the transconductance, increase RDS( on ), and shift the VGS( th ), while elevated thermal impedance raises leakage current and distorts output/transfer characteristics. Datasheet values derived from packaged devices therefore underestimate intrinsic die capability. Accurate compact models and loss predictions require careful de-embedding of packaging contributions. Bare die characterization remains essential to capture the true device physics, while packaged measurements are necessary to assess performance under practical operating conditions. Both perspectives are complementary to optimize SiC MOSFETs in high-performance power electronics.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

This work was partly funded by the UK EPSRC grant EP/Z531091/1 and partly funded by the UK EPSRC grant EP/Y000307/1. We would like to acknowledge the support of the UK Compound Semiconductor Applications Catapult and EPSRC's 'Innovation Launchpad Network' Researcher-inResidence stream, and CoolCAD Electronics Inc. for providing us with the device samples.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.47.pdf

Z. Zhu, R. Yao, H. Li, J. Li and Z. Chen, "Comparative Analysis on Switching Characteristics of Discrete SiC MOSFET in Press-pack Package and Wire-bonded Package", IEEE Int. Power Elec. Conf. & Expo. (PEAC), Guangzhou, China, 2022, p. 66-71, doi: 10.1109/PEAC56338.2022.9959610.

J. O. Gonzalez, R. Wu, S. Jahdi and O. Alatise, "Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs," in IEEE Transactions on Industrial Electronics, vol. 67, no. 9, pp. 7375-7385, Sept. 2020, doi: 10.1109/TIE.2019.2945299.

A. Lemmon, S. Banerjee, K. Matocha and L. Gant, "Analysis of Packaging Impedance on Performance of SiC MOSFETs," PCIM Europe 2016, Nuremberg, Germany, 2016, pp. 1-8.

A. Anthon, J. C. Hernandez, Z. Zhang and M. A. E. Andersen, "Switching investigations on a SiC MOSFET in a TO-247 package," IECON 2014-40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, 2014, pp. 1854-1860, doi: 10.1109/IECON.2014.7048754.

N. Phankong, T. Yanagi and T. Hikihara, "Evaluation of inherent elements in a SiC power MOSFET by its equivalent circuit," 14th Euro. Conf. on Power Electronics, UK, 2011, pp. 18.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 55-67

doi: 10.4028/p-HwDA3m

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2026-01-18

Accepted:
2026-02-28

Online:
2026-05-18

Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

The original version of this paper is available on https://www.scientific.net/KEM.1054.55.pdf

Madhu Lakshman Mysore 1,a*, Rahul-Vijaybhai Chavda 1, b, Josef Lutz 1,c, Thomas Basler 1, d

1 Chemnitz University of Technology, Chair of Power Electronics, Chemnitz, Germany

a* madhu-lakshman.mysore@etit.tu-chemnitz.de, b rahul-vijaybhai.chavda@etit.tu-chemnitz.de, c josef.lutz@etit.tu−chemnitz.de, d  thomas.basler@etit.tu-chemnitz.de

Keywords: short-circuit robustness, SC failures, thermal runaway, npn BJT activation, gate-leakage, TCAD.

Abstract

This work investigates the short-circuit (SC) robustness of 1200 V SiC MOSFETs from two different manufacturers (M1: trench-gate, M2: planar-gate) up to their destruction limits. Both devices, packaged in TO-247 4-pin housings with a nominal on-state resistance ( Rds, on  ) of 80 mΩ, were systematically tested under a gate-source voltage of VGS, on =15 V and at a fixed DC-link voltage of 800 V . In addition to determining the SC withstand capability, the study focuses on the influence of the negative gate bias ( VGS, off  ) on device robustness. Results show that SC capability and dominant failure mechanisms are strongly dependent on gate technology as well as on the applied VGS, off . Trench-gate M1 devices primarily fail due to gate oxide degradation under strong negative bias, while planar-gate M2 devices exhibit failures linked to parasitic BJT activation at SC turn-off or thermal runaway at VGS, off =0 V. Additionally, TCAD simulations closely reproduce the measured trends and provide physical insight into the failure mechanisms. The experimental-simulation approach establishes a comprehensive understanding of SC robustness limits and failure types in state-of-theart SiC MOSFET technologies.

Introduction

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Short-Circuit (SC) events in Silicon Carbide (SiC) power MOSFETs are critical failure modes in many high-power applications, such as motor drives, electric vehicle (EV) traction inverters, and uninterruptible power supply (UPS) units. During an SC event, devices experience severe electrical and thermal overstress and must possess sufficient short-circuit withstand capability until e.g. an external protection circuitry can safely interrupt the fault or the gate driver turn-off the device safely. A comprehensive understanding of SC robustness and the associated physical failure mechanisms is therefore essential for ensuring the reliability of SiC MOSFETs in demanding environments.

The short-circuit behaviour of SiC MOSFETs has been widely studied. Prior work has demonstrated that, despite lower on-resistance, the higher drain saturation current, and reduced chip area of SiC MOSFETs accelerate junction temperature rise, thereby degrading SC capability as compared to Si IGBT [1]. Repetitive SC stress has been reported to be more detrimental on planar devices compared to trench counterparts due to the differences in gate oxide thickness [2]. Highspeed optical imaging in [3] further revealed aluminum metallization melting during the SC transient, highlighting the severity of the thermal stress. Detailed SC failure analysis of trench-gate and planargate SiC MOSFETs in [4] revealed that at a DC-link voltage of 400 V , fracture of the gate interlayer dielectric occurs, whereas at 800 V , failure is exacerbated by the activation of the parasitic bipolar junction transistor (BJT) due to extreme junction temperatures. Furthermore, in converter applications, negative turn-off gate voltages are often employed to suppress unintended turn-on from Miller capacitance-induced cross-talk - the parasitic turn-on effect [5]. However, all the aforementioned studies consider SC ruggedness at a fixed negative gate voltage ( VGS, off  ), leaving the dependence of SC withstand capability and failure modes on VGS, off  largely unexplored. Notably, application of negative gate voltage prior to SC turn-on can the trapping of holes at the SiC/SiO2 interface which leads to a shift (reduction) in threshold voltage known from the Vth -hysteresis effect.

In this work, the impact of negative gate bias on the SC robustness and failure mechanisms type on different gate technologies (trench and planar) for 1.2 kV SiC MOSFETs is systematically investigated at a DC-link voltage of 800 V . By combining experimental characterization with physicsbased TCAD simulations, a comprehensive study is presented that elucidates the interplay between VGS, off  values, device structure design, and SC withstand capability, thereby providing new insights into SC induced failure mechanisms for both gate technologies.

Device Under Test and Simulation Model

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The Device Under Test (DUTs) were commercially available 1.2 kV SiC MOSFET from two different manufacturers (denoted as M1, and M2) with similar current ratings but employs distinct cell technologies, as illustrated in Fig. 1. The device parameters for both SiC MOSFETs are summarized in Table. 1. Electro-thermal simulations were performed to understand the SC robustness dependency on VGS, off  values and to analyze the associated SC failure mechanisms, using Synopsys TCAD [6]. As shown in Fig. 1, 1200 V half-cell trench-gate and planar-gate structures were designed and modelled to match the real structure and were subsequently calibrated [7]. Further, the doping concentrations for these models were derived from simulation-oriented literature and may not precisely replicate the parameters of commercial devices [4]. Nevertheless, these values are representative and adequate to capture the essential electrical and thermal behaviour of the studied structures [4]. The coupled electro-thermal behaviour was simulated using Synopsys Sentaurus Device, wherein the electrical and thermal domains were solved self-consistently to account for the strong temperature dependence of SiC material properties under high-stress conditions. The simulations incorporated periodic boundary conditions and employed advanced physical models, including the Okuto avalanche model, incomplete ionization model, Shockley-Read-Hall (SRH), Auger recombination, high-field carrier velocity saturation, temperature-dependent bandgap narrowing, temperature-dependent carrier mobility (Inverse Accumulation Layer model), and thermodynamic heat transport.

For thermal boundary conditions, surface thermal contacts were defined at the drain electrode with thermal resistance values of 1.1 K/W for the planar MOSFET and 0.69 K/W for the trench MOSFET, in accordance with device datasheets. To improve the accuracy of transient temperature predictions, the volume-specific heat capacities of SiC and Al were adjusted according to experimentally validated data reported from [8].

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Fig. 1. Schematic cross-section of the cell head of SiC MOSFETs from different manufacturers.

Fig. 1. Schematic cross-section of the cell head of SiC MOSFETs from different manufacturers.

Table 1. Device parameters of the SiC MOSFETs from different manufacturers.

Device parameters | M1 | M2
Gate technology | Trench | Planar
Rated current | 31 A | 32 A
Rds,on | 80 mΩ | 80 mΩ
Recommended VGS,on | 18 V | 15 V
Recommended VGS,off | 0 V | -4 V
Package type | TO-247-4

Threshold Voltage Characterization

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Fig. 2. Measured threshold voltage trend ( Vth  and Vth  ) as function of temperature for two different manufacturers at a datasheet given current. Measured conditions of Vth .

Fig. 2. Measured threshold voltage trend ( V th and V th ) as function of temperature for two different manufacturers at a datasheet given current. Measured conditions of V th .

The SiC MOSFETs are susceptible to threshold voltage ( Vth  ) drift and shift due to mechanisms such as bias temperature instability (BTI) and charge trapping at the SiC/SiO2 interface (hysteresis phenomenon). The measurement procedure for each DUT is applied according to the JEDEC standard JEP184 [9]. The pulse pattern and measurement principle is described in [10]. Accurate Vth  characterization of SiC MOSFETs, especially when combined with preconditioning, are crucial for assessing their reliability and performance. Preconditioning, like applying specific gate voltage pulse pattern as discussed in [10], can stabilize the Vth  and improve the measurement repeatability. In this study, both gate technologies were subjected to identical up-sweep and down-sweep voltage ramps for VGS, off  extraction as shown in Fig. 2. As the temperature increases, the Vth  decreases for both manufacturers. For the M1 device at fixed temperature, VGS decreased progressively as Vth  decreased from 0 V to -15 V . In contrast, the M 2 device exhibited a smaller Lpar  reduction, with values earlier saturating when VGS,off exceeded -7 V . Under down-sweep conditions, VDS remained essentially unchanged for both gate-technologies, regardless of the applied negative gate bias during switching transients.

Experimental Setup

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The short-circuit (SC) measurement setup for the SiC MOSFET is schematically illustrated in Fig. 3(a). The protection IGBT (PIGBT) and the device under test (DUT) are connected in series close to the DC-link capacitors. The commutation loop parasitic inductance ( (L s) ) was measured to be 25 nH . The gate-source voltage ( VGS  ) and drain-source voltage ( 15 V/−5 V ) were measured at the sense-source (SS) terminal without the influence of load-source inductance RG. A Rogowski coil was used to measure the current. An exemplary SC waveform at a DC-link voltage of 800 V , with 3( b) switched between RG for two different gate resistances ( 3Ω ), is shown in Fig. VGS,peak . For jD,peak  of djD/dt, the SiC MOSFETs exhibited significantly faster SC switching transients, resulting in slightly higher gate voltage overshoot ( tSC ) and a correspondingly larger drain current density peak ( 15 V/0 V ). The increased current slope ( 2μ s ) causes a significant induced undershoot and overvoltage across the drain and source, thereby higher electrical stress.

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Fig. 3. (a) Schematic diagram of the short-circuit measurement setup (b) Measured SC behaviour of M1 devices at two different gate resistance for given conditions of IGSS . (c) Zoomed dVGD/dt turn-on.

Fig. 3. (a) Schematic diagram of the short-circuit measurement setup (b) Measured SC behaviour of M1 devices at two different gate resistance for given conditions of I GSS . (c) Zoomed d V G D / d t turn-on.

Short-Circuit Results and Analysis

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The short-circuit characteristics of SiC MOSFETs are strongly influenced by multiple factors, including gate driving conditions and negative gate voltage prior to SC turn-on. In the following section, the effects of pulse width and negative gate voltages on SC behaviour are analyzed through a combination of experimental measurements and electro-thermal TCAD simulations.

Influence of theVth

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Fig. 4. Measured SC behaviour of the planar-gate SiC MOSFETs for VGS, off . Measurement conditions:

VDC, link =800 V,RG=33Ω,Tstart =300 K,Lpar =25nH,VGS, on =15 V.

.

Fig. 4. Measured SC behaviour of the planar-gate SiC MOSFETs for V G S , off . Measurement conditions: V D C , link = 800 V , R G = 33 Ω , T start = 300 K , L par = 25 n H , V G S , on = 15 V . .

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Fig. 5. Simulated SC behaviour of the planar-gate (M2) SiC MOSFETs for Vth  (a) jD,peak , tSC=3.8μ s and maximum temperature transients. (b) tSC=2.4μ s and VGS, off  transients. (c) electron current density at VDC, link =800 V,RG=33Ω,Tstart =300 K,Lpar =25nH. Simulation conditions: VGS,on=15 V, and jD,peak.

Fig. 5. Simulated SC behaviour of the planar-gate (M2) SiC MOSFETs for V th (a) j D,peak , t S C = 3.8 μ s and maximum temperature transients. (b) t S C = 2.4 μ s and V G S , off transients. (c) electron current density at V D C , link = 800 V , R G = 33 Ω , T start = 300 K , L par = 25 n H . Simulation conditions: V G S , o n = 15 V , and j D , p e a k .

At a DC-link voltage of 800 V , SC measurements were carried out on M1 devices under switched gate voltage of VGS, off , as shown in Fig. 4. A gate voltage droop was pronounced for an SC pulse width beyond VDC, link =800 V,RG=33Ω,Tstart =300 K,Lpar =25nH, [Fig. 4(a)]. The drain current density (jD) reaches a peak value shortly after the onset of SC event, but decreases with increasing tsc due to carrier mobility reduction in combination with JFET effect [11]. Additionally, a prolonged drain current tail was observed after SC turn-off, which becomes more prominent with longer SC durations. This is due to the strongly reduced gate threshold voltage at very high temperature from SC event and a possible parasitic npn turn-on [12]. Further, the simulations utilized the Direct Tunneling model (includes thermionic emission model) to capture the non-permanent increased gate leakage current during SC event, as previously reported in [13]. The simulated SC behaviour for planar-gate at DC-link voltage of 800 V is plotted in Fig. 5. A significant rise in the maximum temperature was observed during the SC pulse, [Fig.5 (a)], which directly contributes to the increased VGS, on =15 V via thermionic emission mechanisms in time region-3, as depicted in Fig. 5(b). This rise in IGS results in a pronounced droop in the steady-state gate voltage. In contrast, the gate leakage current in region-1 and region-2 is primarily dominated by the classical gate charging pulse and displacement currents via tsc across the Miller capacitance. After SC turn-off, the electron current flowing through channel reflects the reduced VGS induced by very high junction temperature.

Influence of theTstart=300K

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Fig. 6. Measured SC behaviour at different VGS, off  values for both manufacturers. Conditions:

Fig. 6. Measured SC behaviour at different V G S , off values for both manufacturers. Conditions:

VGS,off 

The applied negative gate voltages before the SC event influences jD,peak. Due to hysteresis effect, the threshold voltage is reduced in a manner similar to the up-sweep behaviour shown in Fig. 2 [14]. This reduction in RG improves the device transconductance, thereby increasing VGS, off  as illustrated in

Fig. 6. The corresponding zoomed-in drain current tail is plotted in Fig. 7. For the M1 devices, jD,peak,peak increased monotonically with decreasing tsc However, the M2 devices exhibited an increase in VGS, off  when VGS, off  was reduced from 0 V to -5 V , after which 2.5μ s saturated despite further increases in negative bias. This behaviour correlates closely with the measured 2.9μ s trends obtained from the upsweep characterization for both devices. The plotted VGS, off =−5 V for different RG values for both manufacturers is displayed in Fig. 8. Following SC turn-off, achieved by switching the jD,peak  from positive to negative value, the drain current tail was observed to be only slightly affected, see Fig. 7. For a fixed VGS, off =0 V and RG, the switching transients becomes faster with increasing magnitude of VGS,off, . The substantial IGSS  reduction caused by the elevated channel temperature during the SC event can prolong the longer channel-on condition [Fig. 5(c)]. However, by applying larger negative T enables the channel can be close more rapidly, thereby slightly reducing drain current tail duration.

(a) M1 with =425 K
(b) M 2 with V

Fig. 7. Zoomed-in SC drain current tail at different V values for both manufacturers from Fig. 6. Conditions: =−5 V, VGS.

Fig. 8. Measured V as a function of VGS, off  for trench and planar-gate SiC MOSFETs during SC turn-on. Conditions: 15 V/0 V, 7.4μ s.

SC Robustness Limit

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The SC capability was determined by gradually increasing the pulse width duration ( 4.2μ s ) in steps of 100 ns for a fixed switched VGS and DC-link voltage. To determine their robustness limit, the measurements were carried out until the destruction of the DUTs or a strong drift in the electrical parameters such as gate leakage current (IGSS), loss of blocking capability or increased drain-source leakage current (IDss) is detected, which indicate damage in the device.

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Fig. 9. Comparison of the trench and planar-gate SiC MOSFETs as a function of IGSS for two different VGS, off . Measurement conditions: VGS, off , and IGSS .

Fig. 9. Comparison of the trench and planar-gate SiC MOSFETs as a function of I G S S for two different V G S , off . Measurement conditions: V G S , off , and I GSS .

At4.2μs

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To determine the SC robustness at each VGS level, more than two devices were tested for each conditions. The measured short-circuit withstand time (SCWT) varied between 100 ns to 200 ns for a fixed test conditions. The SCWT for both technologies is compared as a function of 15 V/−10 V for two different IGSs, as shown in Fig. 9(a). The trench-gate device exhibited a monotonic decrease in SCWT with more negative VGS, off  values. Because the applied negative gate voltages before the SC event reduces the threshold voltage and correspondingly improves the transconductance, which leads to higher short-circuit current density peak ( tSC ) as shown in Fig. 6(a). Hence, a higher energy dissipation for same 3.9μ s. In contrast, the planar-gate device displayed decreased SCWT till VGS, off  of -5 V and for further lower jD,peak  values, the SCWT increases from jD, peak  at -5 V to tsC at -15 V . The corresponding critical energy density of both devices is plotted in Fig. 9(b). The energy density shows a similar trend that of the SCWT. The planar-gate device exhibits a minimum critical energy density at t1. A smaller VGS, off  resulted in faster SC switching transients and increased energy dissipation due to t, see Fig. 3(b). Nonetheless, the overall trends in SCWT and energy density remained consistent, with slightly reduced SCWT values within the range of 100 ns to 200 ns . At VGS,off , both gate technologies exhibit the thermal runaway failure irrespective of the t1. With increasingly negative VGS, off  the M1 devices demonstrated failures dominated by elevated VGS values far above the datasheet limit, as confirmed through post SC pulse verification via source measurement unit (SMU). In contrast, planar-gate devices primarily show a SC turn-off failure under the same conditions.

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Fig. 10. Comparison of the trench and planar-gate SiC MOSFETs as a function of VGS,off.  for two different VGS, off . Measurement conditions: VGS, off , and 7.2MV/cm.

Fig. 10. Comparison of the trench and planar-gate SiC MOSFETs as a function of V GS,off. for two different V G S , off . Measurement conditions: V G S , off , and 7.2 M V / c m .

At3.9μsstartVGS,off

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Overall, the failure modes remained consistent for both manufacturers when the starting junction temperature (Tstart) was increased, as shown in Fig. 10. At 425 K, the SCWT tendency remains the same for both manufacturers. However, the last-pass SC event occurred 100-300 ns earlier compared to room temperature. For the M2 device, the failures at the corresponding negative VGS, off  GS,off remained similar to those at room temperature. In contrast, the M1 device exhibited a shift in failure mechanism at Vth  GS,off VGS, off , transitioning from increased gate leakage current failure at 300 K to thermal runaway failure at elevated temperature.

Notably, M1 device exhibited its longest SCWT at VGS, off ,off of 0 V for both temperatures. Whereas the M2 device demonstrated higher SC robustness at tSC GS,off of -15 V across both temperature conditions. The lower critical energy density of the M2 device, compared to M1 device, can be attributed to the higher energy dissipation per unit channel-width, which further amplified by the unfavorable thermal network of the planar-gate [2]. The different SC failure modes observed in devices from both manufacturers are discussed in detail in the next section.

SC Failure Types

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The SC failure mechanisms in both gate technologies are analyzed using post-failure microscopic images along with TCAD simulations. Furthermore, the SCWT trends observed for both manufacturers are investigated and interpreted through detailed electro-thermal TCAD simulations.

Fig. 11 depicts the thermal runaway failure of the M 1 SiC MOSFET at 3μ s of 0 V under elevated starting temperature. Although the device was switched-off to the preset condition of n+, a prolonged drain current tail persisted leading to thermal runaway at t1 for an SC pulse width of VGS, off . At the onset of thermal runaway, the device losses its blocking capability, accompanied by rapid increase in both VGS, off values 2.4μ s and jd. Inset in Fig. 11 shows the post-failure chip surface of the M1device after decapsulating the TO package. Microscopic image reveals a completely burned surface caused by aluminum metallization melting, while the bond wire remained intact.
All M1 devices exhibited failure due to post SC increased jD1 with increased negative VGS, off  values, except at -5 V for 425 K . Fig. 12 shows a representative non-destructive SC event at p+ of -10 V , where the device survives the SC stress without displaying any distinct failure transient. Nevertheless, only the intermediate measured VGS, off  in between the SC event shows a sudden increase after an SC pulse width of VDS  for p+ of VGS, off , as illustrated in Fig. 13 . For M 1 devices, post VGS  remains nearly unchanged with increased SC pulse width, until an abrupt rise occurred, a similar observation for M1 devices is reported under overcurrent turn-off failure in [7]. Such a sharp increase in IGss is indicative of pre-damage to the gate oxide, with measured values exceeding the maximum limits specified in the datasheet. The inset in Fig. 12 presents the post-failure chip surface of an M1 device after decapsulating the TO packages, revealing no damage or failure region on the chip surface or even on the gate runner.

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Fig. 11. Measured thermal runaway failure of the M1 device. Conditions: VGS, off  nH . Inset: microscopic image of the failed device.

Fig. 11. Measured thermal runaway failure of the M1 device. Conditions: V G S , off nH . Inset: microscopic image of the failed device.

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Fig. 13. Measured VGS, off ,SCWT in between SC measurements for M1 manufacturer. Conditions as per the datasheet value: IGSS.

Fig. 13. Measured V G S , off , S C W T in between SC measurements for M1 manufacturer. Conditions as per the datasheet value: I G S S .

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Fig. 12. Measured non-destructive pulse of the M1 device. Conditions: VGS, off  25 nH . Inset: Microscopic image of the device.

Fig. 12. Measured non-destructive pulse of the M1 device. Conditions: V G S , off 25 nH . Inset: Microscopic image of the device.

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Fig. 14. Simulated SC behaviour of the trenchgate SiC MOSFETs for different VGS, off  values. Conditions: VGS, off , and 21st .

Fig. 14. Simulated SC behaviour of the trenchgate SiC MOSFETs for different V G S , off values. Conditions: V G S , off , and 21 st .

To investigate the mechanism behind the reduced SCWT with lower negative 20th  values, SC simulations were performed for SiO2 of mathematical formula at different mathematical formula values, as plotted in Fig. 14. Applying a negative gate bias prior to the SC event reduces the threshold voltage because of hysteresis effect [14], thereby increasing the mathematical formula through enhanced transconductance, see Fig. 6 and Fig. 14. The resulting higher mathematical formula translates to greater energy dissipation and a corresponding rise in device maximum temperature during the SC event for the same mathematical formula. In measurements, the degraded M1 devices exhibit a permanent increase in IGSS post SC event after exceeding the critical SCWT, indicating gate-oxide degradation. To understand this effect, the time point superscript number was considered at simulated SC turn-off to study the influence of the negative voltage on the gate oxide field. Fig. 15(a) displays the plotted electric field distribution at the trench gate oxide adjacent to the channel for different mathematical formula values at mathematical formula. The electric field distribution in the simulated gate structure for various mathematical formula values at superscript number is shown in Fig. 15(b).

For a same SC duration, the electric field at the trench gate oxide adjacent to the channel increase with more negative mathematical formula. The high electric field contribution from the pn-junction under an 800 V DC-link voltage, combined with gate voltage driven field from mathematical formula, sum up to an effective high electric field in trench oxide. Furthermore, the simulation reveal that electric field at the dielectric/ Al interface [highlighted by the red dot in Fig. 15(b)] also intensifies with more negative mathematical formula The elevated device temperature under stronger negative mathematical formula additionally induce higher thermomechanical expansion stress between layers, which may lead to inter-layer dielectric cracking, as discussed in the literature [4, 15]. For mathematical formula of -15 V , a peak electric field of superscript number was obtained at the interface between the dielectric and Al, see Fig. 15(b). This higher field accelerates localized degradation, eventually triggering pre-damage to the gate oxide of the devices which fits to increased IGSS at longer SC events. While these simulations were carried out at mathematical formula, it is expected that further increase in pulse width similar to measurement conditions would raise the localized oxide field even further in gate oxide for -5 V and -10 V , thereby accelerating the gate degradation.

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Fig. 15. (a) Simulated electric field in the trench gate oxide adjacent to channel. (b) Electric field distribution of the M1 gate structure at time point of superscript number for different mathematical formula values. Conditions:
superscript reference, and mathematical formula. For cut, see

Fig. 15. (a) Simulated electric field in the trench gate oxide adjacent to channel. (b) Electric field distribution of the M1 gate structure at time point of for different values. Conditions: , and . For cut, see

Fig. 14.

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Fig. 16. (a) Measured thermal runaway failure of the M2 device. Inset: microscopic image of the failed device. (b) Simulated thermal runaway failure of the M2 device. (c) Total current density at superscript number. Conditions: superscript reference, and superscript number.

Fig. 16. (a) Measured thermal runaway failure of the M2 device. Inset: microscopic image of the failed device. (b) Simulated thermal runaway failure of the M2 device. (c) Total current density at . Conditions: , and .

Fig. 16(a) shows the measured thermal runaway failure for the M 2 device at mathematical formula of 0 V . The inset microscopic image reveals a post-failure signature similar to that of M1 device, characterized by strong surface damage caused by Al metallization melting. Fig. 16(b) displays the simulated thermal runaway event for conditions similar to measurements. Although the simulated SC behaviour does not perfectly replicate the experimental results at extreme high temperatures due to the limitation in the high temperature physical models in simulator. The failure tendency of the simulated results matches with measured results and underlying mechanisms are consistent with measurements.

At mathematical formula of 0 V , simulation result shows a pronounced drain current tail after SC is turned off, despite the gate being switched 0 V from preset conditions. This behaviour arises from strong reduction in mathematical formula at extreme junction temperature, which sustains partial channel conduction even after SC turn-off, see Fig. 16(c). The drain current tail, in combination with high DC-link voltage, imposes additional thermal stress on the device. This triggers a positive feedback loop in which higher temperatures enhance thermal generation. At such extreme temperatures, the parasitic npn bipolar junction transistor (BJT) could be activated and contributes one part of the remaining current tail as shown in Fig. 16(c). Once activated, this results in catastrophic device destruction and the current might focus to a single cell.

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Fig. 17. (a) Measured SC turn-off failure. Inset: microscopic image of the failed device. (b) Simulated SC turn-off failure of the M2 device. (c) Total current density at superscript number. Conditions: superscript reference, and mathematical formula.

Fig. 17. (a) Measured SC turn-off failure. Inset: microscopic image of the failed device. (b) Simulated SC turn-off failure of the M2 device. (c) Total current density at . Conditions: , and .

All M2 device with planar-gate consistently exhibited SC turn-off failure for mathematical formula values ranging from -5 V to -15 V . A representative SC turn-off failure at mathematical formula of -15 V and mathematical formula of mathematical formula, is shown in Fig. 17(a), together with corresponding TCAD simulation under comparable conditions in Fig. 17(b). In the simulation, SC turn-off failure occurs when the maximum SiC temperature reaches approximately 1900 K . At this extreme temperature, the voltage drop across the mathematical formula-source and p -body junction forward-biases the base-emitter junction of the parasitic BJT, thereby initiating its activation and triggering an uncontrollable increase in the current [4]. Fig. 17(c) shows the simulated total current density distribution at superscript number [marked in Fig. 17(b)], clearly revealing conduction paths consistent with parasitic BJT activation. Moreover, once the parasitic BJT is activated, the current level becomes uncontrollable and the rising temperature further intensifies the failure process. Experimentally, SC turn-off failures in these conditions caused complete destruction of the TO packages. Post-failure microscopic analysis revealed extensive burning of the chip surface, with large regions of the Al metallization melted away.

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Fig. 18. (a) Simulated SC behaviour of the planar-gate SiC MOSFETs for different mathematical formula values.
(b) total current density distribution for different mathematical formula values at same current density superscript number.
Conditions: superscript reference, and superscript number.

Fig. 18. (a) Simulated SC behaviour of the planar-gate SiC MOSFETs for different values. (b) total current density distribution for different values at same current density . Conditions: , and .

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Fig. 19. (a) Hole density (b) electric field for different mathematical formula values at same current density superscript number. For plots cut was across mathematical formulasource, mathematical formula-body and drift region, see Fig. 18(b).

Fig. 19. (a) Hole density (b) electric field for different values at same current density . For plots cut was across source, -body and drift region, see Fig. 18(b).

Interestingly, the M2 SCWT increases with more negative mathematical formula values, see Fig. 10. To gain insight into this trend, SC simulations were performed at different superscript reference, as shown in Fig. 18(a). The corresponding total current density distribution at the same current density of superscript number [marked in Fig. 18(a)] is displayed in Fig. 18(b). At mathematical formula of -5 V , a clear latch-up of the parasitic npn BJT is observed. In contrast, at -10 V only a weak BJT activation occurs, while at -15 V the BJT remains effectively suppressed. This behaviour is governed by the gate-bias-dependent transient charging of the mathematical formula-body during SC turn-off. At mathematical formula of -5 V , the slower gate discharge and miller plateau enhance capacitive coupling between gate, drain and body regions. Consequently, a displacement current associated with rising mathematical formula influences the p -body, leading to transient hole
accumulation and partial forward biasing of the parasitic BJT as shown in Fig. 19(a). With stronger negative gate bias, faster gate discharge results in stronger mathematical formula-body depletion. The increased overvoltage at SC turn-off generates slightly higher electric field peak as shown in Fig. 19(b). This field enhances more carrier sweep-out, suppress the hole storage in the base, and prevents sufficient base current formation, thereby inhibiting parasitic BJT activation. Nevertheless, with further increase in SC pulse width, the maximum SiC device temperature rises due to higher energy dissipation and eventually leading to the SC turn-off failure at higher negative mathematical formula values. All the failure types observed in this work for trench and planar-gate is summarized in Table 2.

Table 2. Failure types at different Vth,up  between trench and planar-gate SiC MOSFETs.

| Failure types at 300 K | Failure types at 425 K
Trench | Planar | Trench | Planar
VGS,off values |  |  |  |
0 V | Thermal runaway | Thermal runaway | Thermal runaway | Thermal runaway
-5 V | Post increased IGSS | SC turn-off | Thermal runaway | SC turn-off
-10 V | Post increased IGSS | SC turn-off | Post increased IGSS | SC turn-off
-15 V | Post increased IGSS | SC turn-off | Post increased IGSS | SC turn-off

Summary

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The short-circuit (SC) robustness and failure mechanisms of SiC MOSFETs with distinct cell technologies from different manufacturers were systematically investigated through measurements supported by TCAD simulations. The observed mathematical formula droop during the SC event is attributed to the increased gate leakage current from thermionic emission at very high junction temperatures.

Further, the trench-gate M1 device is strongly influenced by the applied negative gate bias prior to turn-on due to hysteresis effect. The M1 device exhibits the highest short-circuit withstand time (SCWT) at mathematical formula of 0 V , with failure governed by thermal runaway. At more negative mathematical formula decreases significantly due to increased mathematical formula. TCAD simulations confirm that negative gate bias enhances the electric field at the interface between the dielectric and Al , thereby accelerating gate oxide degradation. In contrast, the planar-gate M2 device shows a distinct behavior: SCWT decreases when mathematical formula is shifted from 0 V to -5 V , but subsequently increases for stronger negative bias, with the highest SCWT observed at -15 V . However, this bias exceeds datasheet limits, making mathematical formula of 0 V the most reliable operating point within specification. Failure analysis reveals that at 0 V bias, M2 devices fail through thermal runaway, validated by TCAD simulations that show parasitic npn BJT activation after SC turn-off. At higher negative bias, SC turn-off failures dominate, also triggered by parasitic BJT latch-up as confirmed in simulations. Practically, these results indicate that for trench-gate devices, negative mathematical formula should be minimized to reduce gate oxide field stress, whereas for planar-gate devices, moderate negative bias can improve the SCWT.

Overall, the results highlight a fundamental trade-off between gate oxide reliability in trench devices and parasitic BJT suppression in planar devices. These findings emphasize that SC robustness is not universal but highly dependent on device architecture, gate biasing strategy, and thermal limits. The combined measurement-simulation approach not only validates the physical failure mechanisms but also provides practical design guidelines for optimized gate drive strategies and reliability improvements in next-generation SiC MOSFET technologies.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1054.55.pdf

We would like to express our sincere gratitude to Detlef Conrad from Synopsys for his support to the understanding and implementation of the models investigated in this work.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.55.pdf

J. Sun, H. Xu, et. al., "Comparison and analysis of short circuit capability of 1200 V singlechip SiC MOSFET and Si IGBT," in Proc. 13th China Int. Forum Solid State Lighting, Nov. 2016, pp. 42-45.

A. Piccioni, "Repetitive Short-Circuit Ruggedness of Different of SiC MOSFETs channel Design" in Proc. 2025 IEEE Int. Reliability Physics Symp. (IRPS), Monterey, CA USA, Mar. 2025, pp. 2B. 2 1-6.

T. Ziemann, et. al., "Time resolved short circuit failure analysis of SiC MOSFETs," in Proc. 31st Int. Symp. Power Semiconductor Devices ICs (ISPSD), May 2019, pp. 219-222.

K. Yao, et. al., "Investigation of SiC MOSFET Short-Circuit Failure Mechanisms Using Electrical, Thermal, and Mechanical Stress Analyses" in IEEE transactions on Electron Devices, Vol. 67, NO. 10, OCTOBER 2020, pp. 4328-4334.

S. Jahdi, et. al., "Temperature and Switching Rate Dependence of Crosstalk in Si-IGBT and SiC Power Modules," IEEE Transactions on Industrial Electronics, vol. 63, no. 2, pp. 849-863, 2016.

TCAD Sentaurus Manual, Synopsys Inc., Mountain View, CA, USA,2025.

M. L. Mysore, et al., "Investigation of Overcurrent Turn-Off Robustness of 1200 V SiC MOSFETs", will be published in the conference ICSCRM, Raleigh, USA, Sep. 2024.

A. Tsibizov, et. al., "Accurate temperature estimation of SiC power MOSFETs under extreme operating conditions," IEEE Trans. Power Electron., vol. 35, no. 2, pp. 1855-1865, Feb. 2020.

JEDEC, "Guideline for evaluating Bias Temperature Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion," in JEDEC JEP 184, 2021.

C. Schwabe, et. al., "SiC MOSFET threshold voltage stability during power cycling testing and the impact on the result interpretation," in Proc. 2023 IEEE Int. Reliability Physics Symp. (IRPS), Monterey, CA USA, Mar. 2023, pp. p86.SiC1-6.

T. Basler, et. al., "Practical Aspects and Body Diode Robustness of a 1200 V SiC Trench MOSFET" in PCIM Europe 2018, 5 - 7 June 2018, Nuremberg, Germany, pp. 536-542.

B. Kakarla, "Short-Circuit Behaviour SiC MOSFETs" PhD thesis, ETH Zürich, 2021.

J. Roig, et. al., "On the TCAD Modeling of Non-Permanent Gate Current Increase During Short-Circuit Test in SiC MOSFETs" in Proc. ICSCRM, Sorrento, Italy, 2023, pp. 866872.

T. Aichinger, et. al., "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs" Microelectronics Reliability, vol 80, pp. 68-78, 2018.

P. D. Reigosa, et. al., "Effects of short-circuit stress on the degradation of the dielectric in SiC power MOSFETs" Microelectronics Reliability, 88-90, pp. 577-583, 2018.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 69-77

doi: 10.4028/p-ownaK0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-16

Accepted:
2026-03-21

Online:
2026-05-18

Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/KEM.1054.69.pdf

Wu Jiale 1,a, Wang Zhiwei 1, b*, Chen Zhongyuan 1,c and Ran Li1, d

1 Beijing Institute of Smart Energy, Beijing, China

a  wujialencepu@163.com, b  tjuwangzhi@163.com, c  chenzhongyuan@bise.hrl.ac.cn, d  L.Ran@warwick.ac.uk

Keywords: SiC MOSFET, dynamic reverse bias stress, blocking capability, reliability.

Abstract

As a switching device, a SiC MOSFET operates under high-frequency and fast switching edges, facing severe reliability challenges in the dynamic mode. The degradation of electrical characteristics of SiC MOSFETs under high-voltage dynamic switching conditions is systematically investigated in this study. It is found that the threshold voltage and on-resistance exhibit initial transient degradation but they both stabilize, with changes remaining within ±5%. They show no dependence on the pulse amplitude, frequency, duty cycle, or temperature. This is attributed to the shielding effect of the P -well structure on the electric field in the channel region, which suppresses the continuous accumulation of interface charges. Additionally, the body diode voltage drop shows no significant shift, indicating that the dynamic reverse bias stress has no substantial impact on the n - drift region. However, the blocking capability can degrade and the degradation trajectory exhibits cross-coupling effects of multiple factors. Breakdown voltage degradation is positively correlated with the pulse voltage amplitude, frequency, duty cycle, and test temperature. As these stressors increase, carriers gain higher energy in the couple electro-thermal fields, leading to enhanced charge injection efficiency and trapping depth, increased interface charge accumulation, and localized electric field distortion, resulting in nonlinear degradation of the device's blocking capability. This study reveals the degradation mechanisms of SiC MOSFET under dynamic stress conditions, providing a theoretical basis for the optimization of interface engineering and dynamic operation adaptation design of high-reliability power devices.

Introduction

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In practical applications, Silicon carbide ( SiC ) MOSFETs experience coupled electro-thermal stresses induced by the complex operating condition, imposing stringent reliability challenges on the devices. Currently, the evaluation of high-temperature voltage endurance in SiC MOSFETs primarily relies on constant-stress high temperature reverse bias (HTRB) testing. This involves applying a DC bias slightly below or equal to the rated voltage continuously at the maximum operating junction temperature to verify long-term stability of the blocking performance [1]. However, in the power conversion circuits where SiC MOSFETs operate as switching devices, their working mode requires high-frequency transitions among blocking, turn-on, conduction, and turnoff states. The drain-source voltage is not constant but instead a high-voltage, fast-switching, positively off-set, high-frequency repetitive pulse waveform [2]. Under such dynamic reverse bias (DRB) stresses, SiC MOSFETs face significantly more severe reliability challenges. The traditional constant-stress reliability evaluation methods, primarily developed for silicon ( Si ) devices, fail to adequately assess the insulation capability of the chip termination structures and gate oxides under high-frequency switching conditions specific to SiC devices [3].

The European power electronics center's testing standard AQG-324 emphasizes the necessity of conducting DRB test to evaluate the impact of high-frequency pulse stress on the performance stability of SiC devices. Building upon the traditional constant-bias HTRB tests, the standard establishes fundamental principles and testing conditions for dynamic bias evaluation [4]. Roomtemperature DRB testing has also been recommended as an additional qualification requirement in standards such as AEC-Q101 [5]. To address reliability challenges on SiC devices under dynamic
operating conditions, researchers worldwide have conducted some studies. A self-developed DRB test platform with adjustable drain-source voltage slew rate ( dVDS/dt ) was reported in [6]. Using this platform, the impact of dynamic drain-source stress on the electrical property of SiC MOSFETs was investigated. The results demonstrated increases in both threshold voltage Vth  drift and body diode forward voltage drop VSD . Through simulation analysis, the degradation behavior was attributed to enhanced hole trapping in the gate oxide layer above the JFET region and body diode area. Simulation studies on the failure mechanisms of SiC MOSFETs under extreme dVDS /dt switching conditions were reported in [7]. The results revealed that the charging/discharging current in the Pwell of the main junction region generates high transient electric fields in the gate oxide at the boundary between the transition zone and active area. These findings underscore that chip design must account for not only static voltage endurance but also transient blocking capability under DRB stresses like in applications.

This paper investigates the influences of main DRB variables, including pulse amplitude, pulse frequency, duty cycle, and temperature, on the blocking capability reliability of a 1200 V,4H−SiC MOSFETs by monitoring the change of electrical parameters during the aging process. The poststress recovery characteristics of device performance are also tracked, and the difference in reliability degradation mechanisms between the HTRB and DRB conditions is analyzed. The findings are expected to provide insights which can be used for the design, manufacturing, and application validation of SiC MOSFETs from a reliability testing perspective.

Experiment Setup

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The DRB stress reliability tests on SiC MOSFETs are conducted using the commercial test platform. As illustrated in Fig. 1, the experimental procedure involves the electrothermal aging and performance testing phases. The parameter measurement circuit is exemplified by the blocking property test.

[picture]

Fig. 1. Program for dynamic reverse bias test.

Fig. 1. Program for dynamic reverse bias test.

During the aging phase, a positive-polarity square-wave pulse voltage is applied as the drainsource stress to the device under test (DUT), with adjustable pulse amplitude, frequency, and duty cycle. The voltage slew rate ( dVDS/dt ) at pulse rising and falling edges is 50 V/ns. And the case temperature is set according to test requirements. To eliminate interference from active gate stress introduction, the gate-source terminals of DUT are maintained in short-circuited state. After continuous aging for a specified duration, the applied electrothermal stress is removed, and the DUT is allowed to cool to room temperature ( 25±1∘C ). Electrical parameters are then measured using the Agilent B1505A power device analyzer. The test program described here is repeated until the cumulative DRB stress duration reached 168 hours. Three DUTs are tested under each condition.

To differentiate the degradation sites in the chip under DRB stress from an electrical testing perspective, the cell structure is partitioned into the functional areas correlated with specific evaluation parameters in Fig. 2. The threshold voltage ( Vth  ) is primarily associated with the state of channel region and its overlaying gate oxide layer. For 1200 V SiC MOSFETs, the drift region resistance constitutes the dominant component ( 40%−50% ) of the total on-resistance ( RDSon  ), followed by the channel resistance (30%−40%). The conduction performance of the DUT is primarily governed by the health condition of the two regions. Under blocking conditions, reverse
bias stress in the active area is sustained by the PN junction formed between the P-well region and the N- drift region. The body diode forward voltage drop ( VSD ) can serve as a key indicator for assessing the structural integrity of the critical drift region. The blocking capability of the DUT stems from the widening and overlapping of the depletion layer in the termination field-ring PN junctions. The breakdown voltage ( BV ) is predominantly determined by the design and integrity of edge termination structure.

[picture]

Fig. 2. Correlation between device cell structure and key electrical parameters.

Fig. 2. Correlation between device cell structure and key electrical parameters.

This study is conducted on 1200 V SiC MOSFET devices, where ten samples from the same production batch undergo HTRB testing with stress conditions VDS=960 V and TJ=175∘C. Throughout the 168 hour aging period, all DUTs maintained stable blocking performance without exhibiting significant BV degradation.

Result and Discussion

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Impact of Pulse Voltage Amplitude.

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The impact of pulse magnitude ( Am ) is investigated through the application of square-wave pulse voltages at three discrete amplitude levels ( 80%,60%, and 40% ) relative to the rated operating voltage ( 1200 V ). Meanwhile, the remaining DRB stress variables are maintained constant with a pulse frequency of 25 kHz , duty cycle of 50%, and ambient temperature of 30∘C during the testing period.The time-dependent degradation characteristics of device performance parameters under different Am values are shown in Fig. 3.

[picture]

Fig. 3. Time-dependent degradation of device performance parameters under different Am values.

Fig. 3. Time-dependent degradation of device performance parameters under different A m values.

The degradation ratio is quantitatively defined as the ratio of the difference between the measured values at each time point and their initial values with respect to the initial values, serving as a metric to characterize the performance attenuation of devices under specific stress conditions. A positive degradation indicates that the measured value exceeds the initial value, meaning the performance parameter increases over time, while a negative value signifies that the measured value falls below the initial value, reflecting a decreasing trend of change. Through normalization, this metric eliminates individual variations, enabling effective comparison of degradation behaviors under different stress conditions.

As shown in Fig. 3(a)-(c), with increasing stress time, Vth  and RDSon  of the device exhibit consistent degradation trends. During the first hour of stressing, the degradation is relatively rapid before gradually stabilizing. VSD  shows no observable degradation throughout the period. Under DRB testing, the N- drift region serves as the primary voltage-bearing zone within the active area.

The absence of degradation in VSD  indicates this region remains unaffected, implying no variation occurred in the drift region resistance. The observed synchronous short-term degradation of both Vth  and RDSon could predominantly be associated with the channel region. 

At gate oxide/SiC interface near the channel region, an electric-field-induced charge transfer phenomenon can occur [8]. Under high drain-side electric fields, positive charges (holes) generated by impact ionization are transported to the SiO2/SiC interface, with some becoming trapped there. These trapped charges effectively act as an additional forward bias applied to gate, enhancing channel conductivity and leading to transient reductions in both Vth  and RDSon . Although DRB stress affects the channel region to some extent, the shielding effect of the P -well on nearby electric field prevents sustained degradation progression [9]. The observed degradation remains to be transient and limited in magnitude, with no discernible dependence on the pulse amplitude.

In contrast to Vth  and RDSon, the degradation of BV exhibits pronounced dependence on Am, as illustrated in Fig. 3(d). With the same stress duration, the degradation of BV shows a nonlinear increasing trend with elevated pulse amplitudes. At 480 V,BV exhibits no measurable degradation. At 720 V , the degradation rapidly exceeded 10% before stabilizing towards 15−20%. At 960 V , the degradation of BV reached 40%.

This suggests that when Am exceeds a critical value ranging from 480 V to 720 V for the device under study in this paper, the high electric field between the drain and source imparts sufficient kinetic energy to charge carriers, thereby triggering impact ionization process. As shown in Fig. 4, a high hole concentration is generated near the field oxide/SiC interface within the termination region. The electric field induces hole injection into the interface, where the holes are captured by deeplevel traps. These trapped charges cause field distortion, thereby degrading the blocking capability of the terminal field-ring PN junction [10]. Further increasing the pulse voltage amplitude enhances the vertical electric field at field oxide/SiC interface, leading to improved charge injection efficiency as well as deeper trap penetration. This intensified interface charge accumulation effect significantly degrades the BV stability of SiC device.

[picture]

Fig. 4. Mechanism analysis of breakdown voltage degradation in devices.

Fig. 4. Mechanism analysis of breakdown voltage degradation in devices.

Impact of Pulse Voltage frequency and duty cycle.

The original version of this paper is available on https://www.scientific.net/KEM.1054.69.pdf

SiC MOSFETs are widely employed in high-frequency applications such as the photovoltaic inverters and industrial motor drives, where the devices are consistently subjected to voltage transients during switching operations. It is therefore essential to investigate degradation behavior for devices under DRB stress with varying frequencies and duty cycles.

To investigate the influence of pulse frequency on device electrical parameter degradation, the experiment was conducted with pulse frequencies set at 5kHz,15kHz, and 25 kHz , while maintaining constant amplitude, duty cycle, and temperature at 960 V,50%, and 30∘C, respectively. The time-dependent degradation characteristics of device performance parameters under varying frequencies are shown in Fig. 5.

As shown in Fig. 5(a)-(c), similar to the case under different voltage amplitudes, Vth  and RDSon  of the device exhibit a brief degradation followed by stabilization with increasing stress time under different pulse frequencies. The degradation is limited (within 5% ) and shows no dependence on pulse frequency. Meanwhile, the voltage drop of VSD  shows no signs of degradation.

In contrast, the degradation of BV demonstrates significant dependence on the pulse frequency, as shown in Fig. 5(d). The degradation of BV is consistent across different pulse frequencies - it
increases with stress time and becomes more pronounced at higher pulse frequencies. Under dynamic reverse bias stress at 5 kHz , the degradation of BV after 168 h is 2.7%, indicating negligible degradation. After the same effective stress time, the drop of BV reaches 31% at 15 kHz and 40% at 25 kHz .

At low pulse frequencies (0−5kHz), the device experiences fewer high-electric-field stress events per unit time. This allows more time for charges trapped in deep-level traps to relax, with some detrapping occurring during stress intervals, thereby mitigating charge accumulation and its modulation of the electric field. As the pulse frequency increases, although the total duration of high and low voltage levels remains unchanged, the number of voltage transitions per unit time rises significantly. This reduces the available charge relaxation time, enhances residual charge accumulation, and consequently accelerates BV degradation [11].

[picture]

Fig. 5. Time-dependent degradation of device performance parameters under different frequencies.

Fig. 5. Time-dependent degradation of device performance parameters under different frequencies.

To investigate the influence of pulse duty cycle on the device electrical parameter degradation, square-wave pulses with duty cycles of 20%,50%, and 80% were applied under fixed amplitude, frequency, and temperature conditions of 960 V,25kHz, and 30∘C. The time-dependent degradation characteristics of the device performance parameters under different duty cycles are shown in Fig. 6.

[picture]

Fig. 6. Time-dependent degradation of device performance parameters under different duty cycles.

Fig. 6. Time-dependent degradation of device performance parameters under different duty cycles.

As shown in Fig. 6(a)-(c), the degradation behaviors of Vth ,RDSon  and VSD  under different pulse duty cycles are consistent with those observed under various pulse frequencies. Vth  and RDSon  show a brief degradation at the initial stage of stressing before settling down, with the level of degradation remaining within 5%. No duty cycle dependence was observed. Meanwhile, no degradation in V SD was detected under any of the tested duty cycle conditions.

A positive correlation is observed between BV degradation and the pulse duty cycle, as shown in Fig. 6(d). After the same stress duration, the degradation of BV increases with higher duty cycles. When the duty cycle rises from 20% to 50%, the degradation increases from 27% to 40%. Beyond 50% duty cycle, the degradation growth slows. The pulse duty cycle represents the proportion of high-level voltage duration within each stress cycle. A higher duty cycle extends the time during which the device is under high reverse bias electric field. This prolongs carrier acceleration in the electric field, increasing the probability of impact ionization. More charges are driven by the field to fill deep-level traps and form fixed charges. The resulting charge accumulation distorts the local electric field, macroscopically leading to an increased BV degradation.

Impact of Temperature.

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Given that SiC MOSFET devices may operate in high-temperature harsh environments, their dynamic reliability under such conditions warrants thorough investigation. To examine the impact of dynamic reverse bias stress on the degradation of electrical parameters at different temperatures, tests were conducted at 30∘C,100∘C, and 175∘C. Other stress conditions (amplitude, frequency, and duty cycle) were set to 960 V,25kHz, and 50%, respectively. Figure 7 shows the degradation of the SiC MOSFET performance parameters as a function of stress time under these temperature conditions.

As shown in Fig. 7(a)-(c), under different test temperatures, Vth  and RDSon  of the device exhibit an initial brief degradation followed by stabilization with the increase of stress time. Owing to the protective effect of the P -well on the channel region in the active area, the overall degradation remains limited. Meanwhile, VSD shows no signs of degradation.

In contrast, a positive correlation is observed between the degradation of BV and temperature, as shown in Fig. 7(d). After 168 hours of stress at 30∘C, the degradation reaches 40%. At 100∘C under the same electrical stress conditions and duration, the drop of breakdown voltage increases to 50%, while at 175∘C, the degradation rises to 55%. Under the same electric field strength near the drainsource region induced by the pulsed voltage, elevated temperature enhances the thermal motion of carriers, increasing the probability of high-energy attainment and intensifying the hot carrier injection effect. This leads to deeper charge trapping and reduced detrapping likelihood. Furthermore, higher temperatures significantly lower the activation energy for trap generation in the oxide layer, accelerating the formation of defects at the SiO2/SiC interface and within the oxide. These defects act as charge trapping centres, capturing carriers and forming fixed charges, which distort the local electric field and ultimately degrade the breakdown robustness of the device.

[picture]

Fig. 7. Time-dependent degradation of device performance parameters under different temperatures.

Fig. 7. Time-dependent degradation of device performance parameters under different temperatures.

Post-stress Recovery Behavior of Device.

The original version of this paper is available on https://www.scientific.net/KEM.1054.69.pdf

After removing the dynamic reverse bias stress, the recovery of the SiC MOSFET's electrical performance was tracked for over 200 h to determine the nature of the parameter degradation. As mentioned in the previous results, Vth  and RDSon  showed no significant dependence on pulse amplitude, frequency, duty cycle, or temperature. Therefore, the recovery behavior of Vth  and RDSon  under different pulse amplitudes is presented here as an example, with the results shown in Fig. 8.

During the initial recovery phase (within 24 h ), the degradation of both Vth  and RDSon  decreased rapidly. After 50 h of recovery, the parameters entered a saturated state, with the residual degradation stabilizing around 0.5%. After stress removal, both Vth and RDSon  demonstrated a selfrecovery capability, with a distinct time-dependent characteristic. This behavior is attributed to the release of trapped charges at the SiO2/SiC interface in the channel region. The P -well structure in the SiC MOSFET shields the electric field in the channel, resulting in shallow charge injection and limited accumulation during dynamic reverse bias stress. Under room-temperature storage after stress removal, the shallow trapped charges are released through lattice vibrations or thermal motion, leading to a gradual recovery of carrier concentration and mobility in the channel region.

[picture]

Fig. 8. The degradation of threshold voltage and on resistance varies with recovery time.

Fig. 8. The degradation of threshold voltage and on resistance varies with recovery time.

The recovery of breakdown voltage under different dynamic stress conditions is shown in Fig. 9. For comparison, Fig. 9(a) also includes the breakdown voltage recovery behavior after constant reverse bias stress (HTRB, under VDS=960 V and TJ=175∘C ).

[picture]

Fig. 9. Recovery of breakdown voltage under different dynamic stress variables.

Fig. 9. Recovery of breakdown voltage under different dynamic stress variables.

After conventional constant-stress HTRB tests, degraded SiC MOSFETs can gradually recover under room-temperature storage, and the level of degradation further decreases after hightemperature baking. In contrast, devices degraded under dynamic reverse bias stress show no recovery in breakdown voltage - neither after room-temperature storage nor high-temperature baking.

The difference in breakdown voltage recovery behavior after constant and dynamic reverse bias stressing is primarily attributed to the charge injection depth and the types of traps involved. Under constant bias, the electric field is relatively stable, and charge injection is mainly confined to shallow-level traps near the SiO2/SiC interface. These traps have low energy barriers, allowing captured charges to be gradually released via thermal relaxation at room or elevated temperatures, thereby restoring the breakdown voltage close to the initial value. Under dynamic stress, however, the high-frequency pulsed electric field induces higher-energy charge injection, resulting in greater injection efficiency and deeper trapping [11]. Deep-level traps have higher energy barriers and require larger de-trapping activation energies, making charge release difficult even after hightemperature baking. This leads to irreversible degradation of the breakdown voltage.

To improve the degradation of blocking capability under DRB stress, scholars have proposed recommendations from the perspective of optimizing the chip cell structure design. These include inserting isolation rings in the transition zone between the active and terminal regions to shunt transient currents [7], or introducing local buffer layers in the edge termination area to suppress hole injection [12], thereby enhancing the robustness of the device.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1054.69.pdf

This study experimentally investigates the possible degradation of the electrical characteristics of SiC MOSFETs under high-voltage fast-switching dynamic stressing. The main conclusions are as follows:

With increasing stress time, the threshold voltage and on-resistance exhibit brief degradation before stabilizing. The extent of degradation is limited and shows no dependence on pulse amplitude, frequency, duty cycle, or temperature, which is primarily attributed to the electric field
shielding effect of the P -well near the channel region. The body diode voltage drop shows no degradation, indicating that the dynamic reverse bias stress does not affect the N- drift region. After stress removal, both the threshold voltage and on-resistance demonstrate self-recovery behavior with distinct time-dependent characteristics.

The degradation of the breakdown voltage shows a positive correlation with pulse amplitude, frequency, duty cycle, and temperature. As any of these factors increases, carriers gain more energy from the coupled electro-thermal fields, enhancing charge injection efficiency and trapping depth. This intensifies interface charge accumulation, leading to local electric field distortion and a significant reduction in the breakdown voltage. After stress removal, neither room-temperature storage nor high-temperature baking can reverse the negative shift of breakdown voltage.

The difference in breakdown voltage recovery behavior under constant and dynamic reverse bias conditions stems primarily from the charge injection depth and the trap types involved. Under constant stress, charge injection is confined to shallow-level traps near the interface, and the trapped charges can be released via thermal relaxation at room or elevated temperatures, making the degradation reversible. Under dynamic stress, the high-frequency pulsed electric field enhances the energy and depth of charge injection. Deep-level traps have higher energy barriers and require larger detrapping activation energies, preventing charge release even after high-temperature baking and resulting in irreversible breakdown voltage degradation.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1054.69.pdf

This work is supported by the State Grid Corporation of China Science and Technology Program (Grant No. 5500-202499378A-3-3-ZH).

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.69.pdf

W. Jouha, M. Masmoudi, A.E. Oualkadi, et al. Physical study of SiC power MOSFETs towards HTRB stress based on C-V characteristics. IEEE Transactions on Device and Materials Reliability, 2020, 20(3): 506-511.

Z.C. Liu, X. Cui, X.B. Li, et al. Review on the Electric Field Calculation of Insulation Structure of High-voltage and High-power IGBT Device. Proceedings of the CSEE, 2024, 44(1): 214-230.

Y.H. Wang, E.P. Deng, Y.X. Yan, et al. Review on Accelerated Aging Models and Test Conditions for Power Devices'High Temperature Reliability Test. Journal of North China Electric Power University, 2023, 50(5): 68-77.

ECPE Guideline AQG 324: Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles. 2021.

Automotive Electronics Council (AEC). AEC-Q101: Failure Mechanism Based Stress Test Qualification for Discrete Semiconductors. 2021.

L.W. Zuo, H. Meng, Z. Zhou, et al. Dynamic Reverse Bias Test Circuit for SiC MOSFET with Adjustable dVds/dt. IPEMC2024 ECCE Asia, Chengdu, China, 2024, pp. 3688-3693.

B.T. Sun, G.Y. Lei and J. Zhang. Over dV/dt Robustness of Switching Behavior of SiC MOSFET and a Novel Main Junction Region Design. IEEE Transactions on Electron Devices, 2024, 71(5): 3109-3115.

X.H Zhong, H.P. Jiang, G.Q. Qiu, et al. Bias Temperature Instability of Silicon Carbide Power MOSFET Under AC Gate Stresses. IEEE Transactions on Power Electronics, 2022, 37(2): 1998-2008.

W.J. Ni, X.L. Wang, M.L. Xu, et al. Comparative Study of SiC Planar MOSFETs With Different p-Body Designs. IEEE Transactions on Electron Devices, 2020, 67(3): 1071-1076.

Q.W. Song, H. Yuan, Q.J. Sun, et al. Reverse-Bias Stress-Induced Electrical Parameters Instability in 4H-SiC JBS Diodes Terminated Non-equidistance FLRs. IEEE Transactions on Electron Devices, 2019, 66(9): 3935-3939.

D.X. He, T. Zhang, X.G. Chen, et al. Research Overview on Charge Characteristics of Power Electronic Equipment Insulation under the Pulse Voltage[J]. Transactions of China Electrotechnical Society, 2021, 36(22): 4795-4808.

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 79-84

doi: 10.4028/p-1iEOWa

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-16

Accepted:
2026-02-28

Online:
2026-05-18

Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

Ayan K. Biswas a , Callie Woods b , Daniel J. Lichtenwalner c , Shadi Sabri d , Sei-Hyung Ryu e, Brett Hull f, Adam Barkley g, Donald A. Gajewski h, Elif Balkas i

Keywords: SiC MOSFETs, gate screening, lifetime modeling, gate oxide reliability, time dependent dielectric breakdown (TDDB).

Abstract

Intrinsic gate oxide reliability of silicon carbide (SiC) power MOSFETs has improved significantly over the years. Nonetheless, to achieve a level of overall reliability comparable to silicon devices, it is essential to address extrinsic defects that could introduce early life failures in the gate oxide of SiC devices. Gate screening can be performed to eliminate these early life failures; however, proper optimization of screening methodology is required to maximize the useful life of the devices while maintaining a low failure rate and avoiding potential adverse effects, such as threshold voltage instability, due to the high gate stress during screening. In this paper, we demonstrate enhanced intrinsic and extrinsic reliability of gate oxide across two distinct wafer fabrication facilities, achieved through optimized processing and screening methodologies.

Wolfspeed, Inc, 4600 Silicon Drive, Durham, NC 27703, USAa ayan.biswas@wolfspeed.com, b callie.woods@wolfspeed.com, c  daniel.lichtenwalner@wolfspeed.com, d  shadi.sabri@wolfspeed.com, e sei-hyung.ryu@wolfspeed.com, f brett.hull@wolfspeed.com 9 adam.barkley@wolfspeed.com, h  don.gajewski@wolfspeed.com, i  elif.balkas@wolfspeed.com

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

Silicon carbide ( SiC ) vertical power MOSFETs offer efficient switching, thanks to their wide-band gap leading to lower on-resistance at a similar operating voltage as compared to their silicon counterparts [1]. Therefore, ensuring excellent reliability has become a primary focus for SiC -based devices. Although gate oxide intrinsic reliability has shown great improvements over the years, there has not been much discussion about extrinsic reliability until recently [2-3]. In Ref. [2], it has been argued that gate oxide screening should be performed on SiC MOSFETs that suffer several orders of magnitude higher failure rate due to larger extrinsic populations when compared with Si MOSFETs. This paper addresses gate oxide reliability across all three phases of the bathtub curve, addressing early life failure regime from extrinsic defects, constant failure regime due to random failures, and wear-out failure regimes due to intrinsic failures. It also demonstrates enhanced gate oxide reliability obtained through highly optimized processing and screening in both 150 mm and 200 mm wafer fabrication/process technologies.

Overview of Gate Screening through a Bathtub Curve

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

Figure 1 illustrates a schematic representation of the screening effect on the failure rate of the gate oxide over time in terms of a bathtub curve. Despite proper screening of the devices, random failures can still occur due to the stochastic thermal process represented by the Weibull shape parameter value of β~1 within the screened population (see Fig. 1a-b). Once the devices are screened down to the random failure regime at the bottom of the bathtub curve, additional screening will reduce the useful life of the devices (see Fig. 1c). Therefore, it is essential to develop an optimized screening methodology that effectively eliminates the early extrinsic population, while minimizing the reduction of useful lifetime. In addition to useful lifetime consideration, the screening method should not be so overly aggressive as to produce large gate threshold instabilities, or cause impact-ionizationdriven negative threshold voltage drift (see Fig. 2) [4-6].

[picture]

Fig. 1. Schematics of bathtub curves showing all three phases of device lifetimes in the context of gate oxide reliability under different scenarios of gate screening - (a) partially screened population (b) optimally screened population (c) overly screened population.

Fig. 1. Schematics of bathtub curves showing all three phases of device lifetimes in the context of gate oxide reliability under different scenarios of gate screening - (a) partially screened population (b) optimally screened population (c) overly screened population.

It has been shown in Ref. [4] that over screening with high gate bias stress above a critical electric field can lead to bandgap impact ionization in SiO2 as shown in Fig. 2. Due to impact ionization, holes can be generated which then travel back towards SiC/SiO2 interface and get trapped near or at the interface resulting in a semi-permanent negative drift in threshold voltages. Recent charge pumping experiment showed higher charge pumping current with high gate stress indicating generation of new interface traps [5]. Gate Hall measurements exhibited mobility degradation under high gate stress along with the increase in interface traps [6]. Therefore, a proper optimization of screening methodology is required to obtain benefits of screening without causing unwanted adverse effects.

[picture]

Fig. 2. Negative threshold drift under high positive bias due to hole generation via impact ionization and trapping (reproduced from reference [4]).

Fig. 2. Negative threshold drift under high positive bias due to hole generation via impact ionization and trapping (reproduced from reference [4]).

Results of Gate Screening Experiment in150mmWafer Fabrication Facility

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

A highly optimized screening methodology has been developed by Wolfspeed to effectively eliminate defective populations, considering the aforementioned factors. Figure 3 illustrates the decrease in failure rate down to <0.5 parts per billion device hours ( ppb/ device-hour), as derived from a large volume of devices subjected to gate screening stress on the 150 mm wafer fabrication process. In order to study the lifetime and failure rate at the operating conditions, approximately 1600 screened devices were stressed under constant bias time-dependent dielectric breakdown (TDDB) test below the critical field (defined in Fig. 2) over a wide range of fields and temperatures, allowing for the extraction of electric field acceleration and activation energy for the thermochemical model [6].

TDDB tests are performed at electron trapping regime as indicated in Fig. 2 to avoid impact ionization (hole trapping) at higher electric fields that overestimate the lifetime projections at the operating conditions under low electric field.

[picture]

Fig. 3. Measured FIT observed during screening of gate oxide from a large number of devices.

Fig. 3. Measured FIT observed during screening of gate oxide from a large number of devices.

Figure 4 shows the lifetime projection under typical operating conditions for two different populations - a wear-out region with β>1 and a random failure region with β~1. This demonstrates that all defective populations with β<1 are screened out and the devices are well within the random failure regime. When the lifetime was estimated for a typical mission condition, the projection from the β=1 branch indicates a low failure probability value of ~1ppb for automotive mission maximum. In case of an industrial application (e.g. solar), that failure probability at mission maximum ( ~100 years) can be ~100ppb.

[picture]

Fig. 4. Lifetime projection from TDDB data collected ( 1.6 k devices from 150 mm process technology) over a wide range of voltages and temperatures using the thermochemical model with a defective subpopulation.

Fig. 4. Lifetime projection from TDDB data collected ( 1.6 k devices from 150 mm process technology) over a wide range of voltages and temperatures using the thermochemical model with a defective subpopulation.

After calculating failure-in-time (FIT) rate of the screened-in devices at the typical mission condition from TDDB study in Fig. 4 and FIT rate of the screened-out devices from the gate screening
study in Fig. 3, a bathtub curve is constructed which features a decreasing failure rate initially, a constant failure rate in the middle and a wear-out failure rate at the end, analogous to an ideal reliability bathtub curve (see Fig. 5). To the best of our knowledge, a gate oxide reliability bathtub is presented for the first time for SiC devices utilizing data acquired from gate screening and TDDB tests. It is crucial to emphasize that early life failures (β<1) have been completely screened-out prior to shipping. As a result, shipped devices exhibit only a low constant failure rate from the onset and maintain this rate during the entire operational life. However, it is important to note that the minimum failure in time (FIT) achieved after optimized screening is determined by the random failure rate, which could potentially be improved by optimizing process technology.

[picture]

Fig. 5. Gox reliability bathtub curve constructed by combining gate screening failure data and TDDB data from Fig. 3 and 4.

Fig. 5. Gox reliability bathtub curve constructed by combining gate screening failure data and TDDB data from Fig. 3 and 4.

Enhanced Reliability of Gate Oxide in200mmWafer Fabrication Facility

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

Analogous to the study in 150 wafer fabrication facility, a targeted TDDB study has been performed to evaluate the effectiveness of screening methodology in 200 mm where further enhancement of gate oxide reliability has been achieved by optimizing processing and screening. Figure 6 presents TDDB data for approximately 900 screened-in packaged devices over a wide range of temperatures (125∘C to .200∘C) and at multiple constant gate voltages. It is noteworthy to mention again that TDDB tests were performed in the electron trapping regime, ensuring that the failure mechanism under TDDB conditions remains consistent with the operating conditions at low electric fields. Hence, thermochemical (Linear E) model is utilized to project lifetime at the operating condition. The extracted thermochemical model parameters for SiC/SiO2, namely Si -O bond strength at zero field ( ΔH0 ) and effective dipole moment ( Peff  ) are found to be 1.74 eV and 13.8e\AA, respectively. These values are comparable to those reported for Si/SiO2 [7] devices, indicating the gate oxide quality and reliability in SiC/SiO2 devices are similar.

[picture]

Fig. 6. Cumulative failure distribution over time from a TDDB test of ~900 devices from 200 mm process technology.

Fig. 6. Cumulative failure distribution over time from a TDDB test of ~ 900 devices from 200 mm process technology.

Additionally, approximately 3400 screened devices were stressed under TDDB to extract information about the extrinsic population. Figure 7 shows the lifetime projection for the 4300 tested devices under typical operating conditions, showing ≪1ppb at even 100 years. It is noteworthy that the percentage of random failure population is reduced by at least ~100x as compared to the 150 mm technology. In addition, all of the defective population is now being screened, to the detection level of this study.

[picture]

Fig. 7. Lifetime projection from TDDB data collected (4.3k devices from 200 mm process technology) over a wide range of voltages and temperatures showing ~100 x decrease in random failures.

Fig. 7. Lifetime projection from TDDB data collected (4.3k devices from 200 mm process technology) over a wide range of voltages and temperatures showing ~ 100 x decrease in random failures.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

We provide an overview of gate oxide screening utilizing a bathtub curve for gate oxide reliability and show how excessive screening can impact intrinsic device lifetimes and threshold voltage stability. Through accelerated lifetime testing, we demonstrate that optimized gate screening, along with improved processing and quality measures for MOSFETs fabricated on 150 mm and 200 mm wafers, result in highly reliable gate oxide and extremely low failure rates across two distinct manufacturing facilities.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.79.pdf

J. W. Palmour et al., IEEE Int. Symp. on Power Semi. Dev. & IC's, 2014, 79-82.

T. Aichinger and M. Schmidt, IEEE International Reliability Physics Symposium (IRPS), 2020, pp. 1-6.

P. Moens et al., IEEE International Reliability Physics Symposium (IRPS), 2024, pp. 1-7.

A. Biswas et al., IEEE International Reliability Physics Symposium (IRPS), 2024, pp. 1-5.

S. R. Stein, et al., IEEE International Reliability Physics Symposium (IRPS), 2024, pp. 1-5.

S. Das, et al., Solid State Phenomena., 2025, pp. 49-53.

J. W. McPherson, Reliability Physics and Engineering, 3rd Ed., Springer Publishing, 2019.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 85-89

doi: 10.4028/p-z4RfMy

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-27

Revised:
2025-12-23

Accepted:
2026-02-28

Online:
2026-05-18

Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

Ke Wei 1,a, Wangchen Li1, b, Chenxi Li1,c, Huaxing Jiang 1, d*

1 School of Microelectronics, South China University of Technology, Guangzhou, China

a 202320161238@mail.scut.edu.cn, b 202421062550@ mail.scut.edu.cn, c 202220160746 @mail.scut.edu.cn, d* hxjiang@scut.edu.cn

*Corresponding author

Keywords: Gate Switching Instability, Surges Current, Stress, Recovery, Threshold Voltage.

Abstract

In this work, we report the impact of combined surge current stress and bipolar gate switching stress (GSS) on the threshold voltage ( Vth  ) shift of planar SiC MOSFETs. The Vth  shift exhibits a strong dependence on the sequence of these two applied stresses. It is found that both the surge current stress and GSS can separately result in a positive shift in Vth , and the Vth  shift is cumulatively aggravated in the combined stresses only if the bipolar GSS is applied first. This is attributed to the generation of new defects during the bipolar gate switching, which act as trap centers for subsequent surge stress. This finding reveals the cumulative damage characteristics of SiC MOSFETs under complex operating conditions.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

SiC MOSFETs have demonstrated excellent performance for high-voltage power conversion applications owing to their superior characteristics, leading to their wide adoption in electric vehicle traction inverters, aerospace power systems, and solar power converters [1-3]. However, threshold voltage instability in SiC MOSFETs remains a concern affecting device reliability and performance, primarily due to charge trapping at the SiC/SiO2 interface [4].

In industrial applications, the switching transients associated with capacitors and inductors give rise to surge currents that can reach magnitudes several times the rated current of SiC MOSFETs. Surge current represents a common electrical stress condition that can lead to a shift in the Vth  of SiC MOSFETs [5]. On the other hand, in practical high-power converter applications, to ensure the stability and efficiency of power systems, applying a negative turn-off voltage is an effective way to prevent false turn-on in SiC MOSFETs. Therefore, bipolar gate switching stress is consistently applied to the gate electrode. Under bipolar gate switching operation, the switching cycle emerges as an additional influencing factor, contributing to a more severe degradation of the Vth  compared to static gate stress conditions [6]. In previous studies, the Vth  instability of SiC MOSFETs under either bipolar GSS or surge current stress has been extensively investigated separately [5,6]. However, in real-world applications, SiC MOSFETs are often subjected to combined stress conditions, yet their impact on Vth  remains unclear. In this work, the influence of combined stress on Vth  degradation is systematically investigated.

Experimental Details and Results

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

For comparison, two Measurement-Stress-Measurement (MSM) procedures were designed to evaluate the impact of the combined stress on Vth  instability, as depicted in Fig. 1(a). In Case One, the surge-first stress sequence was designed to replicate the application scenario in which a device is required to perform switching operations after experiencing surge current stress. Conversely, to evaluate the impact of long-term bipolar gate switching operations on surge reliability, Case Two employed the reverse stress order. In both cases, Vth  recovery was monitored after the combined stress.

In the bipolar GSS test, a +18 V/−8 V bipolar square wave at 1 MHz (duty cycle of 50%, see Fig. 1(b)) was applied to the gate terminal, while the source and drain terminals were shorted to ground.

To more accurately characterize the transient changes in V th during the reliability test, stress-tomeasurement delays and Vth  measurement times should be minimized [7]. Therefore, an ultrafast (≤10μ s)Vth  measurement technique was employed in our test to accurately monitor variations in Vth  and stress-to-measurement delays were reduced to 5μ s to minimize the impact of Vth  recovery.

[picture]

Fig. 1. (a) Two procedures with combined bipolar GSS and surge current stress. (b) Bipolar gate switching and triangular Vth  measurement waveform for the bipolar GSS test.

Fig. 1. (a) Two procedures with combined bipolar GSS and surge current stress. (b) Bipolar gate switching and triangular V th measurement waveform for the bipolar GSS test.

A group of 650−V commercially available planar-gate SiC MOSFETs (RDS(on)=60 mΩ,ID@25∘C=29 A) was selected as the device under test (DUT). First, a single pulse surge test was performed. A half-sinusoidal surge current, with a duration of 10 ms , was generated by a resonating capacitor and inductor. Figure 2(a) shows the half-sinusoidal waveforms of surge current (IsD) from 30 A to 70 A for the DUT biased at VGS of 0 V . The Vth  was monitored after each surge current stress, as shown in Fig. 2(b). The Vth  of the SiC MOSFET is defined as the gate-source voltage when the drain current reaches 10 mA at VDS=2 V. The Vth  increased slightly after the initial 30-A surge stress and then remained nearly unchanged for further surge stress before the device failed. At the 70-A surge current stress, the Vth  shift of the SiC MOSFET was around 0.26 V .

[picture]

Fig. 2. (a) Surge current waveforms of a 650 V/29 A planar SiC MOSFET under varied surge stress. (b) Vth  shift after each surge current stress.

Fig. 2. (a) Surge current waveforms of a 650 V / 29 A planar SiC MOSFET under varied surge stress. (b) V th shift after each surge current stress.

Figure 3(a) compares the Vth  shift as a function of switching cycles during the bipolar GSS test for a fresh device and a device that had undergone a 40-A surge current. Both devices exhibited a positive Vth  shift of approximately 0.2 V after 109-cycle bipolar gate switching. Similar to the Vth  shift observed in the stress phase, the Vth  recovery behavior also exhibited little difference between the two devices, as shown in Fig. 3(b). After a 10 -minute recovery period, approximately 0.1 V of the
Vth  shift induced by bipolar gate switching was recovered. These results suggest that the initial surge stress has minimal impact on how Vth  degrades during the subsequent bipolar GSS phase and recovers afterwards.

[picture]

Fig. 3. (a) Vth  shift during bipolar gate switching stress for fresh and post-40-A-surge-current devices. (b) The Vth  recovery process for device with bipolar stress only and surge-first device with bipolar GSS.

Fig. 3. (a) V th shift during bipolar gate switching stress for fresh and post-40-A-surge-current devices. (b) The V th recovery process for device with bipolar stress only and surge-first device with bipolar GSS.

In contrast, when the device was first stressed with bipolar gate switching for 109 cycles and then subjected to a 40 -A current surge, the Vth  shift was ~0.2 V larger than that in the device with surge only or the device with bipolar gate switching only, as compared in Fig. 4. The Vth  shift induced by surge stress following the bipolar GSS showed minimal recovery in a 10 -minute period. These results indicate that the Vth  shifts induced by combined bipolar GSS and surge stress exhibit a cumulative effect, particularly when the bipolar GSS was applied first.

[picture]

Fig. 4. The Vth  recovery process for bipolar-stress-first device after surge and other stress conditions.

Fig. 4. The V th recovery process for bipolar-stress-first device after surge and other stress conditions.

Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

The Vth  degradation in SiC MOSFETs is mainly due to the presence and charging of trap states at the SiO2−SiC interface or inside the gate oxide. The distinctive Vth  shift under the two stress sequences can be explained as follows. In reverse conduction, partial surge current flows through the MOSFET channel at VGS of 0 V during the single surge test, resulting in electron trapping at the SiO2−SiC interface without generating defects [8], as shown in Fig. 5(a). An increase in net negative charges beneath the gate leads to a positive Vth  shift. Figure 5(b) illustrates the gate oxide degradation and Vth  shift mechanisms under bipolar gate switching. Due to the rapidly changing electric field stress in the gate, the bipolar gate switching can generate additional acceptor-like interface defects at the SiO2 SiC interface [9]. For the case with the bipolar GSS test applied first, the bipolar switching stress acts
as a defect-generation phase, creating additional acceptor-like interface states. Crucially, the subsequent surge stress involves high-density channel carrier injection. This high electron flux efficiently fills these newly generated interface traps. This generation-then-filling process leads to a significantly larger positive Vth  shift. In contrast, for the surge-first case, trap generation is negligible; hence, the Vth  degradation induced by the subsequent bipolar stress remains comparable to that of the bipolar-stress-only condition. Therefore, the cumulative degradation mechanism is fundamentally attributed to the coupling between defect generation and charge trapping under combined stress conditions.

[picture]

Fig. 5. Schematic of Vth  shift mechanism of planar SiC MOSFETs under (a) surge current stress and under (b) bipolar gate switching stress.

Fig. 5. Schematic of V th shift mechanism of planar SiC MOSFETs under (a) surge current stress and under (b) bipolar gate switching stress.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

The Vth  shift in planar SiC power MOSFETs under combined stress conditions involving surge current stress and bipolar GSS was experimentally investigated. Applying surge current stress prior to the bipolar GSS test has minimal impact on the GSS-induced degradation and the subsequent recovery behavior. In contrast, the combined stress can induce a cumulative Vth  shift when the bipolar GSS test is applied before the surge stress. This cumulative effect is attributed to the generation of additional traps at the SiO2-SiC interface during bipolar gate switching stress. These newly generated traps can capture more electrons under subsequent surge current stress, leading to an additional Vth  shift. Our work reveals the aggravated cumulative degradation of SiC MOSFETs under complex stress scenarios. It suggests that conventional single-stress assessment methodologies are inadequate to fully capture device reliability issues, necessitating the consideration of combined-stress interactions in practical evaluations. It can also offer circuit designers some valuable guidelines regarding the necessity of monitoring the long-term Vth  stability of SiC MOSFETs during highfrequency bipolar gate switching ( >109 cycles) in practical applications.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

This work was financially supported in part by the Guangdong Basic and Applied Basic Research Foundation, China, under grant 2023A1515011054, and in part by the Guangzhou Municipal Science and Technology Bureau, China, under grant 2025A04J5383.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.85.pdf

J. Millán, P. Godignon, X. Perpiñà, A. Pérez-Tomás, and J. Rebollo, "A survey of wide bandgap power semiconductor devices," Transactions on Power Electronics 29 (5), pp. 2155-2163 (2014).

T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology: Growth, Characterization, Devices, and Applications. Wiley, Singapore, 2014.

Q. Zhang et al., "Latest results on 1200 V 4H-SiC CIMOSFETs with Rsp,on of at ," in 27th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Hong Kong, pp. 89-92 (2015).

T. Aichinger, G. Rescher, andG. Pobegen, "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs," Microelectronics Reliability 80, pp. 68-78 (2018).

L. Knoll et al., "Robust 3.3 kV silicon carbide MOSFETs with surge and short circuit capability," in 29th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Sapporo, pp. 243-246 (2017).

H. Jiang, X. Zhong, G. Qiu, L. Tang, X. Qi, and L. Ran, "Dynamic gate stress induced threshold voltage drift of silicon carbide MOSFET," Electron Device Letters 41 (9), pp. 1284-1287 (2020).

Lelis, A. J., et al., "Basic mechanisms of threshold-voltage instability and implications for reliability testing of SiC MOSFETs." in IEEE Transactions on Electron Devices 62 (2), pp. 316-323 (2015).

H. Xu et al., "Methodology for enhanced surge robustness of SiC MOSFET body diode," Journal of Emerging and Selected Topics in Power Electronics 10 (5), pp. 5039-5047 (2022).

M.W. Feil et al., "Gate switching instability in Silicon Carbide MOSFETs-Part I: experimental," in IEEE Transactions on Electron Devices 71 (7), pp. 4210-4217 (2024).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 91-97

doi: 10.4028/p-H2CsyY

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-02-28

Online:
2026-05-18

Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

The original version of this paper is available on https://www.scientific.net/KEM.1054.91.pdf

Kung-Yen Lee 1,2,a*, Pei-Chi Liao 1, b, Tsai-Pei Lu 2,c, Ruei-Ci Wu 3, d, Pei-Chun Liao 1,e, Sang-Mo Koo 4,f and Yi-Pin Lee 2, g

1 Graduate School of Advanced Technology, National Taiwan University, Taipei, Taiwan

2 Department of Engineering Science and Ocean Engineering, National Taiwan University, Taipei, Taiwan

3 SiCEV Electronics Co., Hsinchu, Taiwan

4 Department of Electron Materials Engineering, Kwangwoon University, Seoul, Republic of South Korea

a * kylee@ntu.edu.tw, b  r13k43003@ntu.edu.tw, c  r12525103@ntu.edu.tw, d  f07525122@ntu.edu.tw, er13k44005@ntu.edu.tw, f  smkoo@kw.ac.kr, g  r13525045@ntu.edu.tw 

Abstract

This study investigates the degradation behavior of 1200 V 4H-SiC planar MOSFETs under negative high-temperature gate bias (HTGB) stress. The devices were stressed at -20 V and 150∘C for 1008 hours. Key electrical parameters, including threshold voltage ( Vth  ) and reverse transfer capacitance ( Crss ), were monitored to evaluate time-dependent changes. The results reveal a clear two-phase degradation behavior characterized by a transition between electron-dominated and hole-dominated charge injection mechanisms. In the early stage, electron injection via FowlerNordheim (FN) tunneling causes a positive shift in Vth  and a reduction in Crss. With prolonged stress, partial charge compensation leads to a reversal of the electrical trends. These results demonstrate a time-dependent transition between electron injection and hole injection mechanisms. The findings provide insight into the long-term reliability of planar SiC MOSFETs under negative HTGB stress.

Keywords: SiC MOSFET, high-temperature gate bias (HTGB), reliability, threshold voltage ( Vth  ), reverse transfer capacitance ( Crss ), Fowler-Nordheim tunneling, hole injection.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.91.pdf

SiC MOSFETs enable high-efficiency and high-voltage applications due to their superior breakdown voltage and switching speed [1]. However, interface traps at the SiC/SiO2 boundary under high-temperature operation remain a key reliability concern [ 2,3,4 ].

To evaluate the stability of the gate oxide and interface, high-temperature gate bias (HTGB) testing is widely used [5,6]. Under positive bias conditions, electrons can tunnel from the poly gate into the oxide or interface traps. This causes an increase in Vth  and a shift in the Cg−Vgs curve, similar to the positive bias temperature instability (PBTI) effect observed in silicon MOSFETs [7]. However, SiC devices have lower barrier heights and more complex interface reactions. As a result, electron injection and trap generation are more sensitive and often irreversible, and this condition causes permanent degradation. In actual applications, negative gate bias is more common. When the device operates in switching circuits, applying 0 V during the off-state may lead to false turn-on due to dv/dt or common-mode noise. Applying a negative gate bias ( -5 to -20 V ) can effectively suppress such noise and improve system stability. Previous studies have shown that negative HTGB may trigger two competing carrier injection mechanisms. One is electron injection from the poly gate, and the other is hole injection from the P -well into the interface or oxide. These two processes may alternate during stress and interact with each other. This interaction causes non-monotonic changes in electrical parameters, such as Vth  increases in the initial stage and then decreases, while Crss decreases first and then increases. These effects indicate that negative HTGB involves complex dual-carrier behavior.

In addition, oxide traps located above the JFET region have a strong impact on the C−V characteristics [8]. Although the degradation under positive HTGB has been well studied, there is
limited data on long-term effects under negative HTGB. Studies often lack full tracking of gate capacitance and dynamic capacitance.

This work focuses on a 1200 V planar SiC MOSFET stressed under Vgs=−20 V and 150∘C for 1008 hours. The time-dependent behavior of Vth,Crss, and Cg−Vgs is carefully analyzed. By comparing experimental results with physical models, this study aims to clarify the degradation mechanisms under negative HTGB and provide insights for the long-term reliability of SiC MOSFETs under extreme bias conditions.

Experiment

The original version of this paper is available on https://www.scientific.net/KEM.1054.91.pdf

This study uses a vertically structured 1200 V/13 A planar SiC MOSFET developed in our laboratory using a conventional SiC MOSFET process [9]. A total of three devices with identical planar MOSFET structures were tested in this study. A cross-sectional view of the device is shown in Fig. 1. The P-well plays a key role in the device operation. It defines the channel behavior and may serve as the source of hole injection under negative HTGB stress. The JFET region controls the current path and the electric field distribution, which are closely related to interface field strength and long-term reliability. The device is packaged in a TO-247 format, making it suitable for high-voltage industrial and automotive power systems. It also offers stable high-temperature operation and good thermal conductivity.

[picture]

Fig. 1. The cross-sectional diagram of the planar MOSFET.

Fig. 1. The cross-sectional diagram of the planar MOSFET.

To simulate the off-state bias condition in real applications, this study conducted a continuous HTGB aging test. The gate bias was set to Vgs=−20 V, and the devices were placed in a hightemperature chamber at 150∘C under a constant gate voltage. Electrical measurements were performed at room temperature by interrupting the stress at predefined time intervals. Fresh devices were first characterized before stress, and subsequent measurements were carried out after stress durations of 168, 504, and 1008 hours using a Keysight B1505 analyzer. According to AEC-Q101 standards [10], the test was terminated if any key parameter shifted by more than ±20% from its initial value. Three key electrical parameters were monitored, and the full test procedure is illustrated in Fig. 2.

[picture]

Fig. 2. Flow chart of the HTGB test procedure.

Fig. 2. Flow chart of the HTGB test procedure.

First, the Vth  was extracted using the constant-current method. The Vds was set to 10 V , and the Vgs was swept from 0 V to 20 V . The Vgs corresponding to Ids=10 mA was defined as Vth . Second, the Crss was measured to study the depletion behavior between the JFET and drift regions. Third, the Cg was measured by applying a small-signal AC voltage of 25 mV at 1 MHz , sweeping Vgs from -15 V to +15 V .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1054.91.pdf

A. Influence of HTGB on Threshold Voltage. Under HTGB stress, charge trapping at the SiC/SiO2 interface or inside the gate oxide may cause a shift in threshold voltage ( Vth  ) over time. This shift can affect the device's turn-on characteristics and pose a long-term reliability concern if the degradation accumulates. Therefore, this study focuses on analyzing the Vth  shift behavior under negative HTGB conditions. The Ids−Vgs transfer curves of the MOSFET are shown in Fig. 3. After 1008 hours of HTGB stress, the device still maintains good turn-on capability. However, near the steepest region of the curve (around Vgs=11.5 V ), a gradual shift is observed at each measurement point, indicating a time-dependent change in threshold behavior. To further evaluate device-to-device variation, Fig. 4 summarizes the distribution of Vth  extracted from three structurally identical planar MOSFETs at different HTGB stress durations. The results show a clear time-dependent evolution of Vth , confirming that the observed shift is a consistent degradation trend rather than measurement fluctuation.

Fig. 5 shows the time-dependent trend of Vth  variation extracted from the same device at different HTGB stress durations. The threshold voltage can be theoretically expressed by Eq. (1) [11]:
Vth=Vth0−QotCox−QitCox.

Here, Qot represents the oxide trap charge, Qit denotes the interface trap charge, and Cox is the gate oxide capacitance. The theoretical threshold voltage Vth 0 can be further expressed by Eq. (2):
Vth 0=4εSkTNAln(NAni)Cox +2kTqln(NAni).

In Eq. (2), εs is the dielectric constant of SiC, k is the Boltzmann constant, T is the absolute temperature, NA is the doping concentration in the P -well region, and ni is the intrinsic carrier concentration of SiC .

This study divides the Vth  behavior into two phases. In Phase 1 ( 0−504 hours), Vth  increased by approximately 2.17%. This is attributed to electrons tunneling from the poly gate into the oxide through the FN mechanism and being trapped at the interface, forming negative charges [6]. According to Eq. (1), these trapped negative charges in the oxide raise Vth . In Phase 2 (504-1008 hours), Vth  decreased by about 1.16%. This is likely due to holes injected from the P -well being
trapped at the interface, resulting in positive charge accumulation. Based on Eq. (1), the presence of positive oxide trap charges leads to a reduction in Vth . This behavior is consistent with the dual-charge-trapping model proposed by Shen et al. [7].

[picture]

Fig. 3. Measured Ids−Vgs curves of MOSFET.

Fig. 3. Measured I d s − V g s curves of MOSFET.

[picture]

Fig. 4. Distribution of Vth  measured from multiple devices under negative HTGB stress.

Fig. 4. Distribution of V th measured from multiple devices under negative HTGB stress.

[picture]

Fig. 5. Variations of Vth  of the MOSFET under HTGB stress.

Fig. 5. Variations of V th of the MOSFET under HTGB stress.

B. Influence of HTGB on Crss−Vds.Crss is the capacitance between the gate and drain. It reflects the depletion behavior in the JFET and drift regions, both of which are crucial for determining the device's dynamic switching characteristics. Crss affects the dV/dt rate during switching events. It is a key parameter for evaluating switching losses and device reliability. In the planar structure used in this study, Crss is particularly affected by trap distribution in the oxide above the JFET region. Fig. 6 shows the Crss−Vds curves at different stress durations. To further evaluate device-to-device variation, Fig. 7 summarizes the distribution of Crss measured from multiple devices under negative HTGB stress, confirming that the observed trend is not dominated by sample-to-sample fluctuation. Fig. 8 presents the extracted Crss values at Vds=1000 V for each time point. The results show a clear twophase degradation change during the 1008-hour negative HTGB stress. In Phase 1 ( 0−504 hours), Crss dropped by approximately 13.69%. This drop is likely caused by electrons tunneling from the poly gate and being trapped in the oxide, which expands the depletion region and suppresses the capacitive coupling. In Phase 2 (504-1008 hours), Crss shows a gradual increase of about 6.71%, compared to the value at 504 hours. This rise is attributed to hole injection from the P -well into the oxide or interface. These holes partially neutralize the previously accumulated negative charge, resulting in a narrowed depletion region and hence an increase in capacitance.

This observed two-phase behavior of Crss strongly supports the dual carrier injection mechanism proposed in Shen's model, where the dominant charge species changes over time. It also highlights the time-dependent and spatially dynamic nature of oxide trap evolution under long-term stress conditions.

[picture]

Fig. 6. Measured Crss−Vds curves of MOSFET.

Fig. 6. Measured C r s s − V d s curves of MOSFET.

[picture]

Fig. 7. Distribution of Crss measured from multiple devices under negative HTGB stress.

Fig. 7. Distribution of C r s s measured from multiple devices under negative HTGB stress.

[picture]

Fig. 8. Variations of Crss of the MOSFET under HTGB stress.

Fig. 8. Variations of C r s s of the MOSFET under HTGB stress.

C. Influence of HTGB on Cg−Vgs. To further investigate the degradation mechanism of SiC MOSFETs under negative HTGB stress, this study compares the Cg−Vgs curves at 0 and 1008 hours, as shown in Fig. 7. In the range of Vgs=−9 to -6 V , defined as Region 1, the device is not fully turned on but the channel begins to modulate. After 1008 hours of stress, the Cg−Vgs curve in Region 1 shows a clear positive shift, and the slope increases significantly. This behavior suggests that a significant number of electrons are trapped in the oxide above the JFET region, increasing the local trap charge density.

Such localized trapping behavior reveals that the degradation is not uniformly distributed across the oxide but is highly dependent on the device's internal electric field profile and structure. The observation supports the spatial selectivity of trap formation, especially near high-field regions like the JFET. This finding is consistent with the time-dependent variations of Vth  and Crss, confirming the physical linkage between capacitance shifts and trap evolution. Overall, the positive shift in Cg−Vgs provides further evidence of position-dependent reliability degradation in SiC power devices under long-term negative bias stress.

[picture]

Fig. 9. Measured Cg−Vgs of MOSFET.

Fig. 9. Measured C g − V g s of MOSFET.

Conclusion

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This study investigates the long-term degradation of 1200 V planar SiC MOSFETs under negative HTGB stress conditions. Electrical parameters including Vth,Crss, and Cg−Vgs were monitored and analyzed over time. In Phase 1, Vth  increased by 2.17% due to electron injection from the poly gate via FN tunneling. In Phase 2, Vth  decreased by 1.16%, attributed to hole injection from the P -well and partial charge compensation. Crss also showed a two-phase behavior. It dropped by 13.69% in Phase 1, suggesting expansion of the depletion region due to electron trapping above the JFET region. In Phase 2, Crss increased by 6.71%, which implies that holes neutralized the trapped charges and caused the depletion region to shrink. Additionally, the Cg−Vgs curve showed a clear positive shift in Region 1, suggesting local trap formation above the JFET region and increased effective capacitance.

These findings confirm that negative HTGB triggers competing carrier injection behaviors and non-uniform trap distribution. The results offer insight into degradation physics and provide guidance for improved reliability modeling and bias design in SiC power devices. Furthermore, the spatial selectivity of trap generation highlights the importance of electric field engineering in device layout. Future work can focus on optimizing oxide quality and structural design to suppress localized stress effects. These insights contribute to extending the lifetime and ensuring robust operation of SiC MOSFETs in high-temperature, high-reliability applications.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.91.pdf

Baliga, B. Jayant. Fundamentals of power semiconductor devices. Springer, 2018.

Afanasev, Valeri V., et al. "Intrinsic sic/sio2 interface states." physica status solidi (a) 162.1 (1997): 321-337.

Xin, Jinlei, et al. "Threshold voltage monitoring method for SiC MOSFET based on body diode voltage under body effect." 2021 IEEE 4th International Electrical and Energy Conference (CIEEC). IEEE, 2021.

Aichinger, Thomas, Gerald Rescher, and Gregor Pobegen. "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs." Microelectronics Reliability 80 (2018): 6878.

Zhong, Yongle, et al. "Review of HTRB and HTGB Reliability of SiC MOSFETs." 2024 7th International Conference on Energy, Electrical and Power Engineering (CEEPE). IEEE, 2024.

Zhao, Haoran, et al. "Study of Influence of HTGB and HTRB Tests on Parameters of 1200 V SiC MOSFETs." 2024 3rd International Symposium on Semiconductor and Electronic Technology (ISSET). IEEE, 2024.

Shen, Yutong, et al. "Time-dependent degradation mechanism of 1.2 kV SiC MOSFET under long-term high-temperature gate bias stress." IEEE Transactions on Electron Devices 70.3 (2022): 1162-1167.

Wei, Jiaxing, et al. "Interfacial damage extraction method for SiC power MOSFETs based on CV characteristics." 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD). IEEE, 2017.

Kimoto, T., & Cooper, J. A. (2014). Fundamentals of silicon carbide technology: growth, characterization, devices and applications. John Wiley & Sons.

AEC-Q101 Rev. H, Stress Test Qualification for Automotive Grade Discrete Semiconductors, Automotive Electronics Council, 2020.

Cochrane, C. J., P. M. Lenahan, and A. J. Lelis. "An electrically detected magnetic resonance study of performance limiting defects in SiC metal oxide semiconductor field effect transistors." Journal of Applied Physics 109.1 (2011).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 99-113

doi: 10.4028/p-HQ1kov

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-18

Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

The original version of this paper is available on https://www.scientific.net/KEM.1054.99.pdf

Madhu Lakshman Mysore a*, Maximillian Goller b, Rahul-Vijaybhai Chavda c, Mohamed Alaluss d, Josef Lutz e, Thomas Basler f

1 Chemnitz University of Technology, Chair of Power Electronics, Chemnitz, Germany

a* madhu-lakshman.mysore@etit.tu-chemnitz.de, b  maximilian.goller@etit.tu-chemnitz.de, c rahul-vijaybhai.chavda@etit.tu-chemnitz.de, d mohamed.alaluss@etit.tu-chemnitz.de, e  josef.lutz@etit.tu-chemnitz.de, f  thomas.basler@etit.tu-chemnitz.de

Abstract

An accurate junction temperature estimation is crucial for all reliability tests (e.g., power cycling tests) of power semiconductor devices, as it directly impacts the lifetime estimation. Studies on advanced silicon carbide ( SiC ) MOSFETs from various manufacturers indicate that conventional static temperature calibration methods can introduce significant error in virtual junction temperature determination due to the dynamic behaviour of the body diode's voltage drop ( VSD ). In this study, a similar dynamic VSD  behaviour was observed by switching the gate voltage without applying a load current, using only a sense current across the body diode. However, this time-dependent dynamic VSD behaviour can be completely eliminated by applying sufficiently negative voltage. Furthermore, dynamic VSD behaviour is strongly influenced by different parameters such as gate loop inductance, gate resistance, turn-on gate voltage, junction temperature and sense current. Moreover, complementary 2D TCAD simulations under experimental conditions reveal that charge trapping and de-trapping at the SiC/SiO2 interface, together with current sharing between the channel and body diode, fundamentally govern the observed transient VSD  dynamics. These findings provide critical insights for an accurate temperature determination and characterization of SiC MOSFETs under dynamic gate conditions.

Keywords: dynamic VSD,VSD(T) method, power cycling test, body effect, interface traps, TCAD.

Introduction

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The ECPE Guideline AQG 324 standardized procedures and methodologies for the lifetime characterization of power electronic converters for automotive applications [1]. These procedures include thermal impedance measurement ( Zth ) and active power cycling tests (PCT). During PCT, the virtual junction temperature ( Tvj ) of the device under test (DUT) is estimated using temperaturesensitive electrical parameters (TSEP). For SiC MOSFETs, the temperature-dependent built-in voltage drop across the intrinsic body diode ( VSD ) is employed to determine Tvj by applying a sense current (Isense )[1,2]. However, this method faces several challenges - specifically, when the MOSFET channel is still partially-on at certain negative gate-source voltage. In general, a more pronounced body effect for SiC MOSFETs intensifies this effect. However, it can be mitigated by applying a sufficiently negative gate voltage [3]. Although in some cases, this mitigation value exceeds the lower limit of the gate voltage specified in the datasheet. Additionally, interface traps at the SiC/SiO2 interface can influence the transient VSD behaviour [4]. Experimental measurements have shown that the VSD  transient often exhibits a slow decay lasting up to seconds before reaching steady-state voltage values, especially in the absence of load current [5]. However, this anomalous VSD behaviour remains unexplained in the existing literature. In this work, a pulse pattern similar to the PCT cool-down measurement routine was applied by switching the gate source voltage ( VGS ) without applying a load current ( Iload  ). The time-dependent dynamic behaviour of the body diode's forward voltage drop ( VSD ), was investigated by using only a small Isense  (like the sense current in a PCT) in the range of milliampere.

In this study, the influence of various parameters such as negative gate-source voltage ( VGS, off  ), gate inductance ( Lg ) and gate resistance ( RG, off  ) on dynamic VSD  behaviour is systematically analyzed. Additionally, 2D electro-thermal TCAD simulations were performed under measured conditions to gain deeper understanding of the device's internal behaviour, with specific focus on the impact of SiC/SiO2 interface traps.

Device Under Test and Experimental Setup

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[picture]

Fig. 1. Schematic cross-section of the cell head of SiC MOSFETs from different manufacturers.

Fig. 1. Schematic cross-section of the cell head of SiC MOSFETs from different manufacturers.

The Devices Under Test (DUTs) were commercially available 1.2 kV SiC MOSFET from three different manufacturers (denoted as M1, M2, and M3) with similar current ratings. Despite their similar current ratings, the three SiC MOSFETs have different cell technologies, as illustrated in Fig. 1. The corresponding device parameters are summarized in Table. 1. The measured input capacitance ( Ciss  ) and reverse capacitance ( Crss  ) are plotted as a function of voltage for different manufacturers in Fig. 2. M1 device show the lowest Ciss  along with smallest internal gate resistance as compared to other manufacturers. The planar-gate technology M3 have the lowest Crss  compared to the other trench-gate technologies, see Table 1. These capacitance characteristics are important for interpreting the dynamic VSD behaviour for different gate technologies.

Table 1. Device parameters of the SiC MOSFETs from different manufacturers.

Device parameters | M1 | M2 | M3
Gate technology | Trench | Double trench | Planar
Rated current | 31 A | 31 A | 32 A
Rds,on | 80 mΩ
Recommended VGS,on | 18 V | 18 V | 15 V
Maximum allowed VGS,off | -10 V | -4 V | -8 V
Internal gate resistance (RG,int) | 2 Ω | 12 Ω | 9 Ω
Ciss at 15 V | 840 pF | 912 pF | 1545 pF
Crss at 15 V | 15 pF | 140 pF | 7 pF
Package type | TO-247-4

[picture]

Fig. 2. Comparison of the input and reverse capacitance as a function of voltage for three different manufacturers.

Fig. 2. Comparison of the input and reverse capacitance as a function of voltage for three different manufacturers.

[picture]

Fig. 3. (a) Schematic diagram of the measurement circuit used for dynamic VSD behaviour. (b) Pulse pattern.

Fig. 3. (a) Schematic diagram of the measurement circuit used for dynamic V S D behaviour. (b) Pulse pattern.

The experimental setup used to measure the dynamic Tvj(VSD) behaviour of a SiC MOSFET is schematically illustrated in Fig. 3(a). A similar circuit can be employed for Zth  calibration as well as VSD and PCT measurements. Generally, the maximum and minimum junction temperatures are extrapolated during off-time of each cycle. In the absence of a load current, Tvj, which corresponds to toff, is expected to remain constant throughout the off-time ( ton ) and during the transition from ontime ( Iload =0 A ), as no temperature and current variation occurs when VSD  and only the sense current of 100 mA is flowing constantly. However, by merely switching the gate voltage from positive to negative values, a dynamic VGS behaviour is observed, as shown in Fig. 3(b). A similar observation has been reported in [5]. All VDS and VSD values were measured using a Kelvin source connection without the influence of load-source inductance for SiC MOSFETs.
TCAD Simulation Model

Table 2. VSD interface trap values used in the simulation model.

Trap types | Energy [eV] | Density (Dit) [cm⁻² eV⁻¹] | Reference
Shallow acceptors | EC - 0.14 | 1×10¹² | [6, 7]
Shallow donors | EV + 0.20 | 1×10¹² | [8, 9]
Mid-gap donors | EC - 0.70 | 4×10¹¹ | [8, 10]

In this framework, the pn-junction voltage serves as the TSEP, while a parallel current in the channel may influence the dynamic VSD behaviour and correspondingly the estimated junction temperature. To analyze the influence of the traps and channel dynamics on transient VSD  behaviour, a trench-gate half-cell 1.2 kV SiC MOSFET structure from M1 was designed and modeled using Synopsys TCAD tool [11], as shown in Fig. 4. Electro-thermal simulations were performed to investigate the dynamic SiC/SiO2 characteristic of the body diode.

The SiC/SiO2 interface hosts a variety of potential traps [8]. In the simulations, traps were localized at the (−2 V) interface. Shallow and deep trap levels were implemented in this work according to the literature (see, Table 2). Further, the simulated I-V characteristic of the body diode are compared with measurements for channel-on (−10 V) and channel-off 1μ A conditions, as shown in Fig. 5. The simulated results show a slightly lower voltage drop but are in good agreement with measured results.

Additionally, a sense current of VSD  was used for the half-cell simulation model instead of 100 mA . The sense current applied for the simulation model was scaled down according to the area factor of the real device.

DynamicVSDMeasurement Results and Analysis

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In the following, the focus is on the VGS dynamic effects caused by the undershoot and overshoot in the gate voltage transients. These VGS  oscillation occurs at the turn-off of the gate voltage and typically persist for less than some hundreds of nanoseconds. The conventional real-time recording systems of the PCT are generally unable to resolve the Isense =100 mA oscillations due to their limited sampling rate. Therefore, an oscilloscope based measurement setup was employed to capture transient events and reveal their effect.

Si MOSFET Results

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[picture]

Fig. 6. Measured VDS  behaviour and corresponding 10μ of the Si MOSFET with gate loop inductance of Lg for different 1.1μH values at a given conditions. Note: the time scaling for the Ciss  is logarithmic, and for the Lg is linear.

Fig. 6. Measured V DS behaviour and corresponding 10 μ of the Si MOSFET with gate loop inductance of L g for different 1.1 μ H values at a given conditions. Note: the time scaling for the C iss is logarithmic, and for the L g is linear.

As an initial calibration step, the measurement setup was validated using a silicon MOSFET (IPP65R099C6) with an 1.1μH. The gate voltage was switched from +15 V to -2 V and -10 V . The measured VSD  remained unchanged after VSD(Tvj) s irrespective of the applied negative gate voltage, with a steady voltage drop of 0.65 V , see Fig. 6(a). The corresponding gate voltage transients show small undershoot even with a VSD  of VGS,off  due to high L𝐠 of the device. The used R𝐆, off  of VSD is an exemplary value at a PCT bench with a wired gate connection. The measured VGS, off  characteristics align well with the expected behaviour of this Si MOSFET, thereby validating that the measurement setup is reliable and introduces no significant artifacts into the experimental data.

SiC MOSFET Results

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During temperature determination using VGS, off  method, several factors may influence the measured VSD. The impact of these parameters is analyzed in the following sections through a combination of measurements and TCAD simulations.
Influence of ΔVSD at different VGS, on  and SiC/SiO2

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Fig. 7. Measured dynamic VSD behaviour of the trench-gate M1 device with gate loop inductance of 50 nH for different Vth  values. Note: the time scaling for the toff  is logarithmic, and for the VSD  is linear.

Fig. 7. Measured dynamic V S D behaviour of the trench-gate M1 device with gate loop inductance of 50 nH for different V th values. Note: the time scaling for the t off is logarithmic, and for the V SD is linear.

[picture]

Fig. 8. Measured dynamic VGS, off  behaviour of the trench-gate M1 device with gate loop inductance of Lg for different VGS values. Note: the time scaling for the VSD  is logarithmic, and for the VGS, off  is linear.

Fig. 8. Measured dynamic V G S , off behaviour of the trench-gate M1 device with gate loop inductance of L g for different V G S values. Note: the time scaling for the V SD is logarithmic, and for the V G S , off is linear.

For a low gate inductance of 50 nH , the dynamic 1.1μH behaviour for different 10Ω is displayed in Fig. 7, along with corresponding gate signal measured using an oscilloscope to detect the faster signal transients. At Lg values of -2 V and -4 V , the dynamic VGS effect is clearly visible after gate turnoff. This initial transient VSD  is attributed to electron trapping during the on-state of the gate voltage ( VGS  ) at Vth  interface states, and this results in elevated third quadrant voltage drop ( VSD  ) due to still increased threshold voltage ( VGS  ) [4]. Especially, at -2 V condition (MOS depletion) holes for quick neutralization are missing. During the subsequent off-time Vth  (similar to the relaxation phase), electrons are emitted over time and the SiC/SiO2 gradually stabilizes, with the final steady-state value being dependent on both the applied VGS and the impact of the body effect. Notably, for Vth  of 50 nH , no transient gate voltage over- or undershoot was observed during VGS, off  turn-off, [see Fig. 7(b)]. For e.g. the -10 V condition, enough holes (MOS accumulation) are quickly neutralizing the before trapped electrons from on-state and lead to a very quick stabilization of the −2 V,−4 V. Also, the body effect does not play a role at this low VSD [12].

It is important to note that in larger PCT systems, the gate inductance loop can be much higher due to the use of longer gate-source connections as there is no need of high frequency switching in these test systems. To replicate such conditions, measurements were carried out with a gate loop inductance of 1μ s as shown in Fig. 8. The small gate resistance ( VSD  ) in combination with the higher Lg leads to some oscillations in the RG.off  transients at turn-off which are very important for the subsequent VSD  behaviour. The over- and undershoots persist for less than 200 ns , see Fig. 8(b). The VGS oscillations closely define the dynamic VSD and consequently influence the VGS response, as depicted in Fig. 8(a). A more negative Tvj undershoot occurring shortly after turn-off dynamically lowers the effective L𝐠=1.1μ𝐇 due to enhanced hole trapping at the VSD interface which is neutralizing
captured electrons from the Lg on-state quickly. This results in a slightly more and longer opened channel (similar to the 1.1μH hysteresis effect). As a result, the current sharing between the channel and body diode is altered [see Fig. 8(a)]. For VGS values of VSD and -6 V , the dynamic 1μ s initially decreases at VSD, followed by an exponential decay towards its steady-state value. This observed dynamic 10μ s behaviour is in contrast when compared to the low gate inductance loop but it seems to be more realistic focusing on real PCT-benches. In the next section, TCAD simulation results will be used to explain this observed phenomenon.

[picture]

Fig. 9. Measured Dynamic VGS behaviour of the trench-gate SiC MOSFET at of SiC/SiO2 and for different t1 values. Note: the time scaling for the t5 is logarithmic, and for the 1μ s is linear.

Fig. 9. Measured Dynamic V G S behaviour of the trench-gate SiC MOSFET at of S i C / S i O 2 and for different t 1 values. Note: the time scaling for the t 5 is logarithmic, and for the 1 μ s is linear.

The oscillations in the gate voltage due to high SiC/SiO2 can be mitigated by increasing the turn-off gate resistance ( VGS, off  ) as demonstrated in Fig. 9. The measured dynamic t2 behaviour is similar to conditions shown in Fig. 7. However, it could be summarized that at sufficiently negative t3, the VGS, off  becomes stable very shortly after VGS, off  turn-off and should lead to a stable t2 readout - at least for the measured trench technology.
TCAD simulation results at t4

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Fig. 10. Simulated dynamic t5 behaviour of the trench-gate M1 device with gate loop inductance of VSD  for different 1μ s values at a given conditions. Note: the time scaling for the VSD is logarithmic, and for the 1μ s is linear.

Fig. 10. Simulated dynamic t 5 behaviour of the trench-gate M1 device with gate loop inductance of V SD for different 1 μ s values at a given conditions. Note: the time scaling for the V S D is logarithmic, and for the 1 μ s is linear.

Fig. 10 presents the simulated dynamic t6 behaviour at t10 of t6. The simulated results exhibit a good agreement with corresponding measurements shown in Fig. 8. For t10 of -2 V , the VSD
waveform demonstrates an exponential decay in the interval from VGS, off  to 10 ms , followed by a steadystate value. A slight transient in t8 is observed up to VSD  for 10μ s of -10 V . This transient behaviour can be mainly attributed to oscillations in the gate voltage. To clarify the underlying mechanisms and role of VSD interface traps, the simulation results are analyzed in two stages.

In the first stage, the effect of the gate voltage transients is examined using five different time points from t6 to t10, corresponding to undershoot and overshoot occurring within the interval of 100 ns to VGS, off  [see, Fig. 10(b)].

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Fig. 11. Simulated (a) e-interface (b) h-interface trapped charges at the SiC/SiO2 interface at different time points ( VSD to VGS, off  ) in t7 oscillation with VGS, off . For time points, see Fig. 10(b). cut-1 at interface. For -2 V case, electrons are quickly neutralized between Vth  and VSD.

Fig. 11. Simulated (a) e-interface (b) h-interface trapped charges at the S i C / S i O 2 interface at different time points ( V S D to V G S , off ) in t 7 oscillation with V G S , off . For time points, see Fig. 10(b). cut-1 at interface. For -2 V case, electrons are quickly neutralized between V th and V S D .

The electron and hole interface trapped charges at VGS, off  are plotted in Fig. 11 for two values of Isense . At Vth , corresponding to gate maximum undershoot, the strong negative bias enhances hole accumulation at the interface, promoting electron de-trapping and neutralization. The subsequent overshoot at VSD , which lasts only a few nanoseconds, has negligible influence on electron and hole detrapping process at VGS of -2 V . For L𝐠=50nH of -10 V condition and at VSD, a very low amount of electrons is present at the interface since they are very quickly neutralized by the accumulated holes. As gate voltage stabilizes at Lg and VGS, fast electron de-trapping and hole emission approaches saturation, which determines the initial VGS value at VSD, but especially in the case of -2 V condition the amount of trapped electron at the interface is still much higher compared to -10 V condition. In the second stage, the dynamic SiC/SiO2 behaviour beyond VGS is analyzed at time points ΔVSD  to VGS, as illustrated in Fig. 10(a).

The simulated electron and hole density profile across the channel (cut-2) at different time points ( Lg to Vth  ) extracted from dynamic VSD behaviour are shown in Fig. 12. For wide bandgap semiconductors devices like SiC MOSFETs, the electric field induced by the moderate negative gate bias (e.g. -2 V) is insufficient to fully deplete the channel due to the pronounced body effect. As a result, the electron density in the channel region remains significantly higher as compared to that at VGS of -10 V [Fig. 12(a)]. The weakened inversion channel at -2 V leads to parallel current flow between the channel and the intrinsic body diode of the SiC MOSFETs. The electron density continues to increases up to VSD, after which it saturates during 1μ s steady state. However, under a strong negative voltage ( -10 V ), the channel is completely pinched-off and the conduction occurs exclusively through body diode. In this condition, the measured voltage drop remains constant after VGS, and the carrier density distribution shows negligible variation across different time points. Furthermore, the strong negative bias of the gate electrode attracts a high density of holes, see Fig. 12(b).

[picture]

Fig. 12. Simulated charge carrier densities through channel (cut-2) for different time points ( VGS to Lg for the given simulation conditions with VGS . For time points see Fig. 9(a).

Fig. 12. Simulated charge carrier densities through channel (cut-2) for different time points ( V G S to L g for the given simulation conditions with V GS . For time points see Fig. 9(a).

In SiC MOSFETs, the oxide layer can exhibit a higher density of interface traps (defects or localized charge sites) compared to Si based power devices [12]. The trapping and de-trapping mechanism, along with the partially-on channel conditions due to body effect for certain negative gate voltages, can modulate the VSD  transients. To investigate this dynamic behaviour, five different time points ( VGS,on  to VGS, on  ) were analyzed for Lg values of -2 V and -10 V [see, Fig. 10(a)].

[picture]

Fig. 13. Simulated (a) e-interface (b) h-interface trapped charges at the 1.1μH interface for two different VSD  values at different time points ( 1μ s to VGS ) with Vth . For time points, see Fig. 10(a). cut-1 at interface.

Fig. 13. Simulated (a) e-interface (b) h-interface trapped charges at the 1.1 μ H interface for two different V SD values at different time points ( 1 μ s to V G S ) with V th . For time points, see Fig. 10(a). cut-1 at interface.

Fig. 13 displays the electron and hole trapped charges at SiC/SiO2 interface during dynamic ton transients. For Isense  of -10 V , the strong negative bias fully depletes the channel, results in negligible change in either electron or hole trapping dynamics. These values remain constant over time after VGS, off . In contrast, for VGS, off  value of -2 V , the electron occupancy of deeper levels increases progressively before saturating after a few milliseconds, which means the Isense  is increasing again and the absolute value of VSD is increasing. This phenomenon is attributed to the weak channel inversion taking the body effect into account (close to depletion) under moderate SiC/SiO2 value, which enhances local electron-density near the interface. The electrons are available from reverse current ( VGS, off  ) flow through the partially open channel. Meanwhile, the slow emission of holes locally affects the electrostatic potential, thereby dynamically modulating the current sharing between the channel and
pn-junction of the body diode via Isense  change. Fig. 14 illustrates the simulated electrostatic potential distribution across channel and deep p-region. The slower trapping mechanism of deeper trap levels relative to the conduction band influences the electrostatic potential distribution profile, particularly under partially-on channel conditions, thereby contributing to the observed transient toff  behaviour. For - 2 V case, it can be clearly seen that with longer times after ni turn-off, the voltage drop across the body diode gradually rises.

[picture]

Fig. 14. Electrostatic potential for two different VGS, off  values at different time points ( VSD  to VSD  ) with 150∘C. For time points, see Fig. 10(a).

Fig. 14. Electrostatic potential for two different V G S , off values at different time points ( V SD to V SD ) with 150 ∘ C . For time points, see Fig. 10(a).

TCAD simulation results at150∘C

The original version of this paper is available on https://www.scientific.net/KEM.1054.99.pdf

Fig. 15 presents the simulated dynamic 27∘C behaviour for VSD of 50 nH . The simulated results show good agreement with corresponding measurements in Fig. 7. Due to the relatively small gate loop inductance, no oscillations (no undershoot) in Lg are observed. For 1.1μH of -2 V , the VSD  behaviour exhibit a slow exponential increase between 200 ns to 5 ms , after which it reaches a steady-state value. To analyze this behaviour, the electron and hole trapping dynamics at the VGS interface were examined at three representative time points during the transient, as shown in Fig. 16. At Ciss  of -2 V , all available electron traps are initially filled from the preceding on-state condition, see Fig. 16(a). The combination of fully occupied traps and a still weakly inverted channel explains the initial increase in RG, int  observed at 200 ns , in contrasting to the high-inductance case discussed in Fig. 10(a). Due to the missing undershoot in VSD at RG, int  of 50 nH condition, the accumulated holes for quick neutralization are missing. Over time, gradual and slow electron de-trapping occurs, approaching saturation after several milliseconds. The release of trapped charge locally modifies the electrostatic potential leading to a slightly decreasing effective Ciss  and reduced VGS, thereby modulating the current distribution between the inversion channel and the body-diode pn-junction. In contrast, for Lg of 10 V , the channel is fully depleted. The strong negative bias attracts holes to the interface, leading to efficient neutralization of trapped electrons. Under these conditions, the VSD stabilizes after approximately RG, int  with no significant change in trapped charge. The corresponding electrostatic potential distribution are shown in Fig. 17. For Ciss  of -10 V , the potential decreases slightly within the first 200 ns and subsequently saturates without further variation. In contrast, under VSD of -2 V , the potential exhibits a gradual reduction over time, consistent with the progressive de-trapping process as shown in Fig. 17(b). This behaviour is opposite to that observed under high Lg conditions, highlighting the critical role of gate-loop inductance and VSD undershoot behaviour in shaping the dynamic Isense  response.

[picture]

Fig. 15. Simulated dynamic Lg behaviour of the trench-gate M 1 device with gate loop inductance of 50 nH for different 3rd  values at a given conditions. Note: the time scaling for the VSD  is logarithmic, and for the Tvj is linear.

Fig. 15. Simulated dynamic L g behaviour of the trench-gate M 1 device with gate loop inductance of 50 nH for different 3 rd values at a given conditions. Note: the time scaling for the V SD is logarithmic, and for the T v j is linear.

[picture]

Fig. 16. Simulated (a) e-interface (b) h-interface trapped charges at the SiC/SiO2 interface for two different VSD values at different time points with Lg. For time points, see Fig. 15(a). cut-1 at interface. Electrons de-trap very slowly.

Fig. 16. Simulated (a) e-interface (b) h-interface trapped charges at the S i C / S i O 2 interface for two different V S D values at different time points with L g . For time points, see Fig. 15(a). cut-1 at interface. Electrons de-trap very slowly.

[picture]

Fig. 17. Electrostatic potential across deep p-region (cut-3) for two different 1.1μH values at different time points with VGS. For time points, see Fig. 15(a).

Fig. 17. Electrostatic potential across deep p-region (cut-3) for two different 1.1 μ H values at different time points with V G S . For time points, see Fig. 15(a).

Influence of theVGS

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Fig. 18 illustrates the influence of different VSD  values under fixed measurement conditions with Lg of VGS . As the gate voltage is switched from higher levels, the undershoot peak during gate turn-off increases [Fig. 18(b)]. This effect directly correlates with a reduction in the measured VSD  at
Ciss  [Fig. 18(a)]. The observed behaviour can be explained by the stronger negative RG, int  undershoot occurring immediately after turn-off, which dynamically reduces the effective VGS through enhanced hole trapping at the VSD interface leading to more electrons neutralization quickly. As a result, the channel remains slightly more conductive for a longer duration, thereby reduced voltage drop across the device [3,12].

[picture]

Fig. 18. Measured dynamic Isense  behaviour of the trench-gate M 1 device with VSD  of VSD  for different 22nd  values at a given conditions. Note: the time scaling for the SiO2/4H−SiC is logarithmic, and for the SiC/SiO2 is linear.

Fig. 18. Measured dynamic I sense behaviour of the trench-gate M 1 device with V SD of V SD for different 22 nd values at a given conditions. Note: the time scaling for the S i O 2 / 4 H − S i C is logarithmic, and for the S i C / S i O 2 is linear.

Other parameters influence

The original version of this paper is available on https://www.scientific.net/KEM.1054.99.pdf

In the following section the influences of the sense current and the junction temperature will be discussed. However, there was no influence of the SiO2/4H−SiC found in this work which means the on-time is long enough to fully charge the interface traps with electrons.

[picture]

Fig. 19. Comparison of the dynamic mathematical formula behaviour of the M1 device with mathematical formula of superscript number for different sense current values at a given conditions.

Fig. 19. Comparison of the dynamic behaviour of the M1 device with of for different sense current values at a given conditions.

[picture]

Fig. 20. Comparison of the dynamic mathematical formula behaviour of the M1 device with mathematical formula of superscript number for different junction temperature values at a given conditions.

Fig. 20. Comparison of the dynamic behaviour of the M1 device with of for different junction temperature values at a given conditions.

Fig. 19 compares the influence of two different sense currents mathematical formula for mathematical formula of -2 V and -10 V . In general, a lower sense current results in a reduced voltage drop. For mathematical formula of -2 V , where the channel is not fully pinched off, reducing mathematical formula by a factor of ten, leads to a slower decay in the dynamic mathematical formula compared to the 100 mA case. This behaviour is attributed to the reduced current conduction through both the channel and the body diode. The lower carrier density at the superscript number interface with less hole available for neutralization consequently slows down the trapping process. In contrast, for mathematical formula of -10 V , the lower mathematical formula results in an lower voltage drop and remains approximately constant during mathematical formula as the channel is fully closed.

As the junction temperature increases, the built-in potential of the body diode decreases due to the rise in intrinsic carrier concentration ( mathematical formula ), as illustrated in Fig. 20. For mathematical formula of -2 V , where the channel remains partially on, the duration of the transient dynamic mathematical formula response shortens by a few milliseconds at elevated temperatures compared to room temperature. This behaviour can be attributed to the temperature dependence of trap kinetics. Specifically, the capture and emission time constant reduces with increase in temperature, thereby reducing the dynamic mathematical formula behaviour [12]. In addition, due to bandgap narrowing at superscript number, the bandgap reduces which shifts the trap energy levels
closer to the conduction band, further accelerating the trapping of electrons. For stronger negative gate bias ( -10 V ), the channel is fully depleted, and the measured voltage drop is lower at superscript number compared to superscript number, while maintaining a similar steady-state trend.

Gate technology influence

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[picture]

Fig. 21. Measured dynamic mathematical formula behaviour of the M2 device with mathematical formula of superscript number for different mathematical formula values at a given conditions.

Fig. 21. Measured dynamic behaviour of the M2 device with of for different values at a given conditions.

[picture]

Fig. 23. Measured dynamic mathematical formula behaviour of the M2 device with gate loop inductance of 50 nH for different mathematical formula values at a given conditions.

Fig. 23. Measured dynamic behaviour of the M2 device with gate loop inductance of 50 nH for different values at a given conditions.

[picture]

Fig. 22. Measured dynamic mathematical formula behaviour of the M3 device with mathematical formula of superscript number for different mathematical formula values at a given conditions.

Fig. 22. Measured dynamic behaviour of the M3 device with of for different values at a given conditions.

[picture]

Fig. 24. Measured dynamic mathematical formula behaviour of the M3 device with gate loop inductance of 50 nH for different mathematical formula values at a given conditions.

Fig. 24. Measured dynamic behaviour of the M3 device with gate loop inductance of 50 nH for different values at a given conditions.

Figures 21 and 22 present the measured dynamic mathematical formula behaviour for the M 2 and M 3 devices at mathematical formula of superscript number. Compared to the M1 device, the M2 samples exhibit a slightly lower dynamic mathematical formula under partially-on channel conditions. This reduction is attributed to the smaller mathematical formula undershoot and overshoot, resulting from their relatively higher input capacitance ( mathematical formula ) and internal gate resistance ( mathematical formula ). The M 3 device show the weakest transient mathematical formula response among the three manufacturers. This behaviour is consistent with their highest mathematical formula and mathematical formula, which together suppress gate-voltage oscillations and thus minimize the undershoot in mathematical formula. Additionally, each manufacturer has different interface trap density. At a reduced gate-loop inductance of mathematical formula of 50 nH , however, the dynamic mathematical formula behaviour of both M2 and M3 devices closely resembles that of the M1 device, as shown in Figures 23 and 24. These results indicate that device-specific parameters such as mathematical formula and mathematical formula have a pronounced effect on the transient mathematical formula only under high- mathematical formula conditions, whereas their influence becomes negligible when the gate inductance is minimized.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.99.pdf

This work systematically investigates the dynamic voltage drop ( mathematical formula ) behaviour of SiC MOSFET body diodes under sense-current ( mathematical formula ) conditions, where the devices are solely driven by gatevoltage switching without external load. Devices from three different manufacturers, encompassing different cell technologies, were analyzed under two gate-loop inductances mathematical formula. The results demonstrate that under partially-on channel conditions in the mathematical formula quadrant, significant transient mathematical formula responses occur, which can introduce substantial errors in junction temperature ( mathematical formula ) estimation. Accurate temperature readout thus requires complete n-channel pinch-off by applying sufficiently negative gate voltages, below standard datasheet recommendations. 2D TCAD simulations elucidate the underlying mechanisms: parallel current flow between the n -channel and body diode, coupled with electron trapping, de-trapping and hole accumulation dynamics at the superscript number interface, strongly modulates the transient mathematical formula behaviour. High gate-loop inductance ( mathematical formula of superscript number ) induces pronounced mathematical formula oscillations, especially strong mathematical formula undershoots, leading to enhanced hole trapping, thus electron neutralization at the interface and a quick decay in mathematical formula shortly after turning off the device. Afterwards a slower decay is followed mostly dominated by further hole emission effects. In contrast, low gate-loop inductance ( mathematical formula of 50 nH ) suppresses oscillations and mathematical formula undershoots, producing a slow exponential rise in mathematical formula primarily governed by electron de-trapping via emission. Furthermore, device-specific parameters such as input capacitance ( mathematical formula ) and internal gate resistance ( mathematical formula ) strongly influence mathematical formula undershoot and, consequently, the dynamic mathematical formula response and varies with manufacturers. On top the interface quality might be strongly different. Additional factors, including reduced mathematical formula and elevated junction temperature, respectively prolong or shorten the transient mathematical formula duration, highlighting the interplay of electrical and thermal effects. Overall, this study provides a comprehensive understanding of the intrinsic and extrinsic factors controlling transient mathematical formula in SiC MOSFETs, offering critical insights for reliable temperature measurement and device characterization under dynamic gate conditions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.99.pdf

ECPE Guideline AQG 324: Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles, 03.1/2021, ECPE Euro-pean Center for Power Electronics e.V., May. 2021.

Y. Zhang, et al., "A Guideline for Silicon Carbide MOSFET Thermal Characterization based on Source-Drain Voltage," in 2023 IEEE APEC, Orlando, FL, USA, 2023, pp. 378-385.

J. A. O. González and O. Alatise, "A Novel Non-In-trusive Technique for BTI Characterization in SiC MOSFETs," IEEE Trans. Power Electron., vol. 34, no. 6, pp. 5737-5747, 2019.

T. Funaki and S. Fukunaga, "Difficulties in characterizing transient thermal resistance of SiC MOSFETs," in Proc. THERMINIC. IEEE, 2016, pp. 141-146.

J. Breuer, et al., "Challenges of Junction Temperature Calibration of SiC MOSFETs for Power Cycling - a Dynamic Approach," in 2024 CIPS conference, Düsseldorf, Germany, 2024.

P. Fiorenza, et al., "Identification of two trapping mechanisms responsible of the threshold voltage variation in MOSFETs" in Appl. Phys. Lett. 117, 103502, Sep. 2020.

T. Hatakeyama, et al., "Characterization of traps in interfaces close to the conduction band by deep-level transient spectroscopy," in Jpn. J. Appl. Phys. 54 111301, 2015.

M. Waltl, et al., "Physical Modelling of Charge Trapping Effects in SiC MOSFETs," in Materials Science Forum, ISSSN: 1662-9752, vol.1090, 2023, pp. 185-191.

E. Pippel, et al., "Interfaces between 4H-SiC and : Microstructure, nanochemistry, and nearinterface traps," in J. Appl. Phys. 97, 034302, 2005.

P. Fiorenza, et al., "Electron trapping at interface probed by transient capacitance measurements and atomic resolution chemical analysis" in Nanotechnology 29 395702, 2018.

TCAD Sentaurus Manual, Synopsys Inc., Mountain View, CA, USA, 2022.

T. Aichinger, et. al., "Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs" Microelectronics Reliability, vol 80, pp. 68-78, 2018.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 115-120

doi: 10.4028/p-av2Xg7

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-07

Revised:
2025-12-27

Accepted:
2026-02-28

Online:
2026-05-18

Design Space Exploration of SiC Power Module Package via Surrogate Model

The original version of this paper is available on https://www.scientific.net/KEM.1054.115.pdf

Lu Wan 1,a*, Nicolo Ripamonti 1, b, Yanfei Zhao 1,c, Reza Soleimanzadeh 1, d, Arne Schröder 1,e

¹Hitachi Energy Research, Segelhofstrasse 1A, Baden-Dättwil, Switzerland

alu.wan@hitachienergy.com, b  nicolo.ripamonti@hitachienergy.com, c  yanfei.zhao@hitachienergy.com, d  reza.soleimanzadeh@hitachienergy.com, e  arne.schroeder@hitachienergy.com

Keywords: power module, electromagnetic, packaging, surrogate model, optimization.

Abstract

This study introduces a surrogate model-based optimization methodology to explore a wide design space of power module packages for achieving user-defined electromagnetic design objectives, such as minimizing commutation loop stray inductance, gate loop stray inductance and balancing mutual inductance. A half-bridge module with four parallel SiC devices per switch position is analyzed, incorporating 17 design variables across terminals and substrate dimensions. Using Sobol sampling, 4096 design variations were simulated in Ansys Q3D to train the surrogate model, enabling efficient gradient-based single- and multi-objective optimization. Results show that the proposed methodology significantly accelerates exploration in a wide design space and outperforms traditional expert-driven methods by identifying superior electromagnetic performance.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.115.pdf

The advancement in transportation, such as electric vehicles, has increased the demand for silicon carbide (SiC) power modules due to their superior switching loss, speed, and current density over silicon modules. However, managing parasitic elements in SiC power module design is crucial due to the high di/dt and dv/dt feature and often challenging due to compact packages [1]. Expert-based iterative design can only cover a limited design space and may result in a local optimum as it is a time-consuming manual process. Recent research has focused on automatic layout design methods which are, however, limited in the number of design variables to achieve desired performance [2-5].

Methodology

The original version of this paper is available on https://www.scientific.net/KEM.1054.115.pdf

Study Case of SiC Module and Design Variables. A half-bridge power module with four parallelconnected SiC devices at both high-side (HS) and low-side (LS) switch positions is investigated with a total number of 17 design variables. Without losing generality of the proposed methodology, the selected design variables determine three common structures of any power modules, that is, main terminals, auxiliary emitter terminals and thickness of substrates. Specifically, as shown in Fig.1a, for three main terminals (AC, DC+ and DC-), their width ( w ), length ( l ), thickness ( t ) and distance w.r.t. the connected metal plate ( p ) are selected as design variables. For the auxiliary emitter terminals, their positions (x,y) and height (h) are selected (see Fig. 1b). Besides, the thickness of substrates ( d ) and distance between source of chips and the metal plate ( s ) are selected.

The workflow of the proposed surrogate model-based optimization includes three stages.
Stage 1: Preparation of Training Database. The first stage prepares a training dataset, which should cover a variety of electromagnetic behaviors. The dataset includes the design geometry of power modules and its electromagnetic features. For the case study, 4096 design variations of this power module are evaluated in Ansys Q3D [6], where the input is the 17 design variables, and the output is the evaluated parasitic inductances: stray inductance of the commutation loop (Ls), stray inductance of the gate signal loop ( Lg ) and the mutual coupling between commutation loop and signal loop ( M ). The design variables are sampled by the Sobol sequence algorithm to achieve randomness in a large design space. The parametric simulations in Ansys Q3D were carried out at 1 MHz and the resulting
inductance matrices were exported by a Python client library that interacts with Ansys (PyAEDT). The simulation took around 125 hours for 4096 design variations. All evaluated parasitic inductances are used to create the training database for the surrogate model. The dataset was randomly split into 90% training and 10% testing. Model performance was evaluated using mean squared error on the test set at each epoch.

[picture]

Fig. 1. Main design parameters to determine the optimal dimensions and locations of the main terminals (a), and the location and length of the auxiliary emitter terminal of a power module (b).

Fig. 1. Main design parameters to determine the optimal dimensions and locations of the main terminals (a), and the location and length of the auxiliary emitter terminal of a power module (b).

Stage 2: Build-up Surrogate Model. In the second stage, a surrogate model is trained using either an Attention Network or Gaussian Process regressor, both taking 17 design variables as inputs and predicting parasitic inductances ( Ls,Lg, and M ). The trained surrogate model is capable of evaluating a single power module design within milliseconds (typical 3 ms ), whereas Ansys Q3D typically requires approximately 30 mins for the same assessment. Thus, the computational cost reduction achieved by the surrogate model compared to full electromagnetic simulations is 99.99983%. Additionally, the surrogate model delivers rapid evaluations with predictions of parasitic inductance that closely align with those produced by Ansys Q3D. The prediction errors between the surrogate model and Ansys Q3D results are below 0.01%. One example of the comparison of the surrogate model with Ansys is shown in Fig. 2.

[picture]

Fig. 2. Comparison of EM features per chip: (a) gate inductance, (b) stray inductance, (c) mutual coupling between commutation loop and gate signal loop.

Fig. 2. Comparison of EM features per chip: (a) gate inductance, (b) stray inductance, (c) mutual coupling between commutation loop and gate signal loop.

Stage 3: Optimization of Power Module. In the last stage, the trained surrogate model is used to optimize the power module by adopting a flexible gradient-based optimization. In general, the target is to minimize stray inductance and mutual coupling and to reduce the variation of these EM features among chips on the same side. To this end, an objective function is formulated as a weighted combination of EM features ( Ls,Lg and M ) for both HS and LS, and deviations between chips on the same side. Specifically, the objective function can be described as:

F=∑wif¯i+∑wjΔfi(1)

where, fi―∈{LgHS―,LgLS―,LSHS―,LSHS―,MHS―,MLS―}, and Δfi being its variance over different chips, and wi,wj are the corresponding weights specified by the user.

Since the surrogate model is a differentiable map between design variables and EM features, the gradient-based optimization is suitable for this optimization. The optimization process starts with a randomly selected initial feasible configuration, then the algorithm optimizes the 17 design variables to minimize the objective function F following its gradient. The optimization follows the geometry constraints which are formulated as dependence among design variables.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1054.115.pdf

Here we show three test cases. The first two test cases target at optimizing a single EM feature and the last case shows the capability of the surrogate model to explore a large design space to optimize multiple objects simultaneously.
Single-Objective Optimization for Gate Inductance. The goal of this test case is to minimize the gate inductance, which is reflected in the objective function f¯∈{LgHS―,LgLS―}. The optimization process firstly creates a population of random initial configurations as starting points. During the optimization iterations, the algorithm leads towards optimal design to minimize the gate inductance. The illustration of several optimization iterations in one configuration depicted in Fig. 3, in terms of the position of the auxiliary emitter terminal (blue dot) with respect to the gate terminal (circle). The leftmost figures show the initial position of the auxiliary emitter terminal for a feasible configuration of the power module. During each iteration, the auxiliary emitter terminals are moved into the direction that decreases the objective function, therefore reducing the gate inductance. The rightmost figures display the optimal positions of auxiliary emitter terminals determined by the optimization process to minimize the gate inductance.

[picture]

Fig. 3. This figure depicts the optimization process undertaken to reduce gate inductance, illustrating the topside interconnects of HS (a-d) and LS (e-h). The process is repeated at intervals of 1000 cycles from (a) to (d), and from (e) to (h). Blue dots indicate the locations of auxiliary emitter terminals, while circles denote the positions of gate terminals. The optimization procedure achieves minimized gate inductance by relocating the auxiliary emitter terminals in proximity to the gate terminal.

Fig. 3. This figure depicts the optimization process undertaken to reduce gate inductance, illustrating the topside interconnects of HS (a-d) and LS (e-h). The process is repeated at intervals of 1000 cycles from (a) to (d), and from (e) to (h). Blue dots indicate the locations of auxiliary emitter terminals, while circles denote the positions of gate terminals. The optimization procedure achieves minimized gate inductance by relocating the auxiliary emitter terminals in proximity to the gate terminal.

A population of random initial configurations is generated by the Sobol sequence algorithm as starting points (see blue dots in Fig. 4a-b). The optimal locations (red cross marks in Fig. 4a-b) for minimized gate inductance for these configurations are determined using the same gradient-based optimization as in Fig. 3. The red traces show the trajectories of auxiliary emitter terminals throughout the optimization process. The results indicate that the optimal designs are located near the gate terminal positions, which demonstrates that shorter gate loops yield smaller gate inductance. To further examine this, a parametric Ansys Q3D simulation is conducted, where only the position of auxiliary
emitter terminal is varied uniformly on the topside interconnects (see Fig. 4c-d). The simulation results validate the conclusion that the minimum gate inductance can be achieved when the auxiliary emitter terminal is positioned close to the gate terminal.

[picture]

Fig. 4. Optimization of gate inductance based on our surrogate model for (a) LS and (b) HS, and the validation in Ansys Q3D parametric simulation for (c) LS and (d) HS.

Fig. 4. Optimization of gate inductance based on our surrogate model for (a) LS and (b) HS, and the validation in Ansys Q3D parametric simulation for (c) LS and (d) HS.

Single-Objective Optimization for Mutual Coupling. The goal of this test case is to minimize the maximum mutual coupling among chips on each side, which is reflected in the objective function as f¯∈{M¯HS,MLS―}. Similar to the first test case, the optimization process creates a population of random initial configurations as starting point (see blue circles in Fig. 5a-b), and the optimal locations (see red cross marks in Fig. 5a-b) are determined by the gradient-based optimization. The red traces indicate the trajectories of auxiliary emitter terminal during the optimization process. The determination of the optimal position of auxiliary emitter terminals depends on the analysis of both the trajectories and final positions in red cross marks. For the LS, the trajectories for most samples end up in the bottom left corner. Some trajectories end up around the gate terminal because the penalty of violation of geometry constraints is set so high that the optimization process is terminated. Thus, the optimal position to obtain negative mutual coupling is in the bottom left corner on the topside interconnects for the LS auxiliary emitter terminal. Similarly, for the HS auxiliary emitter terminal, the optimal designs are clustered in the bottom right corner. Some trajectories terminated around the gate terminal due to the same reason as LS. To validate the surrogate model results, the parametric simulations in Ansys are performed as shown in Fig. 5 c-f, and the distribution of the mutual inductance validates the conclusion of the surrogate model.
Multi-Objective Optimization. The proposed optimization framework allows multiple objectives to be included in the objective function. Optimization of various EM features can occur concurrently by assigning specific weights to each feature within the objective function. By increasing the number of combinations of weights, a large design space can be efficiently treated by the surrogate model.
For instance, Fig. 6 shows the Pareto plot of the optimization for two EM features: gate inductance and mutual coupling (i.e., in the objective function, fi―∈{LgHS―LgLS―,MHS―,MLS―} ), where distinct weight combinations are represented by differently colored circles. To demonstrate the breadth of the design
space, previous designs from Ansys parametric simulations, which consider only two parameters (location of auxiliary emitter terminal (x,y) ), are shown together with the results of the surrogate model. The designs in Ansys are depicted as black cross, and the black curve indicates the Pareto front derived from these designs. By exploring a larger design space, the surrogate model-based optimization achieves an expanded Pareto front (blue cure in Fig. 6), indicating a better electromagnetic performance can be achieved compared to the expert-based iterative design.

[picture]

Fig. 5. Optimization of mutual coupling based on our surrogate model for (a) LS and (b) HS, and the validation in Ansys Q3D parametric simulation for (c) LS and (d) HS.

Fig. 5. Optimization of mutual coupling based on our surrogate model for (a) LS and (b) HS, and the validation in Ansys Q3D parametric simulation for (c) LS and (d) HS.

[picture]

Fig. 6. Pareto-front of two objectives (gate inductance Lg, maximum mutual coupling inductance M ) for (a) HS chips and (b) LS chips, obtained by the surrogate-model based optimization and expertbased parametric simulation in Ansys.

Fig. 6. Pareto-front of two objectives (gate inductance L g , maximum mutual coupling inductance M ) for (a) HS chips and (b) LS chips, obtained by the surrogate-model based optimization and expertbased parametric simulation in Ansys.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.115.pdf

A robust surrogate model-based optimization methodology is introduced for exploring power module design spaces, with the capability to optimize multiple objectives involving several design variables simultaneously. The surrogate model reduces computational cost by 99.99983% compared to full
electromagnetic simulations, cutting computation time from 30 minutes to just 3 milliseconds. The prediction errors between the surrogate model and reference simulation results are below 0.01%. This approach provides a fast optimization of key electromagnetic parameters and enables efficient evaluation of large design spaces, which is challenging and time-consuming to discover through knowledge-based approaches alone. Future work will focus on increasing design variables, extending the surrogate model to capture frequency-dependent effects and dynamic switching transient. Additionally, active learning strategies could be studied to reduce the number of high-fidelity simulations and transfer learning could be applied to adapt the surrogate across different module topologies.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.115.pdf

C. Chen, F. Luo and Y. Kang, A review of SiC power module packaging: Layout, material system and integration, CPSS T. Power Elec. Appl. 02, 03 (2017).

V. Parque, A. Nakamura, T. Miyashita, A study on the inductance and thermal regression and optimization for automatic layout design of power modules, IEEE CPMT Sympo. Jap. 117, 120, (2023).

Y. Abe, A. Hirao, R. Kato, Y. Ikeda, V. Parque, M.K. Faiz, M. Yoshida, T. Miyashita, Design optimization of copper patterns and location of power semiconductors and terminals, Int. Conf. Electron. Pkg (ICEP). 157, 158, (2021).

Y. Zhou, Y. Jin, Y. Chen, H. Luo, W. Li, X. He, Graph-model-based generative layout optimization for heterogeneous SiC multichip power modules with reduced and balanced parasitic inductance, IEEE Trans. Power Electron. 37, 8, (2022).

T.M. Evans, Q. Le, S. Mukherjee, I.A. Razi, T. Vrotsos, Y. Peng, H.A. Mantooth, PowerSynth: A power module layout generation tool, IEEE Trans. Power Electron. 34, 6, (2019).

ANSYS, ANSYS Electronics Desktop 2024 R2, (2024).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 121-126

doi: 10.4028/p-Tv6uJ9

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-16

Accepted:
2026-01-31

Online:
2026-05-18

Dynamic HV-H 3 TRB Test on 3.3 kV SiC MOSFET Modules 

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

Jan-Hendrik Peters a*, Michael Hanf b, Sven Clausner c, Nando Kaminski d

University of Bremen, Institute for Electrical Drives, Power Electronics, and Devices (IALB), 28359 Bremen, Germany

aj.peters@uni-bremen.de, b  michael.hanf@uni-bremen.de, c  sven.clausner@uni-bremen.de, d  nando.kaminski@uni-bremen.de

Abstract

In standard environmental reliability tests, Silicon Carbide (SiC) MOSFETs show excellent performance even compared to their Silicon counterparts. This raises the question if the SiC modules are robust and reliable under all circumstances in the field and against all failure mechanisms or only in the standard laboratory tests. The HV-H 3 TRB (High Voltage - High Humidity High Temperature Reverse Bias) test is the standard test for humidity reliability and SiC modules survive this test for several thousand hours, easily surpassing the 1,000 h qualification requirement. However, in field service the devices are exposed to steep voltage slopes (high dv/dt) instead of the DC voltage stress applied in a standard HV-H 3 TRB. In this work, a dynamic HV- H3 TRB test was performed on 3.3 kV SiC MOSFET modules for more than 4,000 h with switched high voltages of 80% Vnom , only observing minor degradations and reversible blocking capabilities.

Keywords: humidity, HV-H3TRB, dynamic H3 TRB, reliability, power modules, SiC-MOSFET.

From DC to Dynamic

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

The standard test for humidity induced degradation of power semiconductors is the HV-H3 TRB [13] and in recent years, more and more Silicon devices show excellent robustness in this test [4]. SiC MOSFETs can surpass this performance and survive the HV-H3TRB for several thousand hours, easily fulfilling the 1,000 h qualification standards [5-6]. In a previous publication [6] a comparative HV- H3 TRB test with more than 6,300 h of testing time showed a higher reliability of SiC MOSFETs compared to Silicon IGBTs. Even after this time, no SiC MOSFET failed or even showed a degradation in their blocking capability, while every Silicon IGBT of the test group reached the failure criterion. Even the rather high voltage stress of 90% of the nominal voltage ( Vnom  ) did not accelerate the test sufficiently to reach end-of-life of the SiC MOSFETs within the 6,300 h.
In [7] the impact of temperature, relative humidity (RH) and voltage on the test acceleration were investigated for SiC MOSFETs with the conclusion that temperature has a similar impact, relative humidity a lower impact and voltage acceleration a higher impact for SiC devices compared to Silicon devices. The test can be accelerated to reach end-of-life in a fraction of the test time required with the standard parameters of 85∘C and 85%RH(85/85). Unfortunately, this moves the test even further away from field application conditions.
However, as one of the benefits of SiC MOSFETs is their fast switching leading to low switching losses, the stress introduced by the steep voltage slopes (high dv/dt) might be more harmful than a usual HV- H3 TRB procedure with DC voltage stress only. High electric field changes due to the switching combined with field distortions caused by humidity in the silicone gel on top of the chip's junction termination establishes additional stress for the devices. Another point is the change in electro-chemical reactions due to the switched high voltage instead of DC voltage and therefore, the impact on corrosion and dendrites.
For some SiC devices, the dynamic HV-H3TRB was only mentioned as passed [8] and a first test approach was reported in [9] in which 3.3 kV modules were tested under switched conditions, but with a focus on overshoots during condensation conditions at rather low dv/dt.

[picture]

Fig. 1. Left: Single chip 3.3 kV SiC MOSFET in an engineering package filled with silicone gel; right: test stack built up with three half-bridges mounted on air coolers, busbar connection realised with a humidity robust multilayer PCB and additional snubber capacitors for the overvoltage suppression.

Fig. 1. Left: Single chip 3.3 kV SiC MOSFET in an engineering package filled with silicone gel; right: test stack built up with three half-bridges mounted on air coolers, busbar connection realised with a humidity robust multilayer PCB and additional snubber capacitors for the overvoltage suppression.

To meet the high reliability demand of automotive applications for power semiconductors, the dynamic HV- H3 TRB test is already proposed in the appendix of [3]. Parameters aimed for are a dv/dt higher than 30 V/ns and a switching frequency between 15 kHz and 25 kHz . A dynamic HV-H3 TRB conducted until end-of-life and with comparable DC HV-H 3 TRB results is still pending and is the aim of this work.

Design of Experiment

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

The Devices Under Test (DUTs) for the dynamic HV-H3TRB are 3.3 kV SiC MOSFETs similar to those of previous publications [5-6] (see Figure 1). They showed excellent robustness against the HVH3 TRB test over 6,300 h. These single chip modules are engineering samples with frame-based packages designed for research, but with materials used in the production line of modules for traction use cases. The interior of the package and the chip are covered with silicone gel.
Unlike standard HV- H3TRB, the complexity to perform a dynamic HV- H3TRB is significantly higher. Instead of a DC voltage, a pulsed voltage is required, which is generated either by the DUTs themselves (active switching) or by other devices to which the DUTs are connected (passive switching). Depending on the active or passive approach, the amount of DUTs can be easily increased and gate units (GUs) might not have to be inside the climate chamber. Another important point is the acceleration factor of possible degradation of the DUTs with active or passive switching. So far, the available and published test results do not indicate, if the DUTs degrade quicker with active or passive switching. Therefore, 6 DUTs were arranged into three half-bridges (see Figure 1 for the built up DUT group and Figure 2 for the schematic).

[picture]

Fig. 2. Six DUTs arranged in three half-bridges, one half-bridge is actively switching with gate-units directly on top of them (HS: high side switch, LS: low side switch), the other two are passive halfbridges with their gates shorted to their source.

Fig. 2. Six DUTs arranged in three half-bridges, one half-bridge is actively switching with gate-units directly on top of them (HS: high side switch, LS: low side switch), the other two are passive halfbridges with their gates shorted to their source.

One half-bridge is actively switching with a GU at the gates, while the two other half-bridges have shorted gates and are subjected to the voltage slopes only passively. With no load current, the interconnections between the DUTs do not have to be copper busbars but can be achieved through a humidity robust multilayer PCB busbar with ceramic interlayers to ensure the high voltage insulation for the 3.3 kV devices even under 85%RH.

[picture]

Fig. 3. Switching curves of the DUT stack, installed inside the climate chamber with parasitics like long DC voltage cables etc., achievable dv/dt of ca. 7 V/ns at 80% Vnom (2,640 V).

Fig. 3. Switching curves of the DUT stack, installed inside the climate chamber with parasitics like long DC voltage cables etc., achievable dv/dt of ca. 7 V / n s at 80 % V nom ( 2 , 640 V ) .

To compare later test results with HV- H3 TRB tested DUTs high voltages are needed, because the 50 50% duty cycle doubles the test duration if there is neither additional nor accelerated degradation due to the switching. With this DUT stack, pulsed voltages up to 80% Vnom  can be achieved using DC link snubber capacitors to suppress the voltage overshoots (see Figure 3). Because of the engineering package, the existing HV-H3 3 TRB test setup with long cables leading into the climate chamber and to minimize the need of additional devices inside the climate chamber like clamping diodes, which have to be also humidity robust, only rather low switching speeds are achievable. Voltage transients of about 7 V/ns were measured at 1 kHz switching frequency calculated between 10% and 90% of 2640 V . The recommended 30 V/ns [3] are unrealistic with these DUTs and the setup, due to overshoots and ringing.

[picture]

Fig. 4. Dynamic HV- H3 TRB climate profile with a ramp up to 85/85 and after 24 h the turn-on of the switched test voltage, starting the actual test duration. A drying phase with 50∘C&10%RH for 24 h follows at the end before every intermediate measurement.

Fig. 4. Dynamic HV- H 3 TRB climate profile with a ramp up to 85 / 85 and after 24 h the turn-on of the switched test voltage, starting the actual test duration. A drying phase with 50 ∘ C & 10 % R H for 24 h follows at the end before every intermediate measurement.

[picture]

Fig. 5. Blocking curves of the DUTs, degraded active DUT HS even after extended drying, active and passive DUT LS before extended drying with a reduced blocking capability and passive DUT HS 1, HS 2 and LS 2 with no changes.

Fig. 5. Blocking curves of the DUTs, degraded active DUT HS even after extended drying, active and passive DUT LS before extended drying with a reduced blocking capability and passive DUT HS 1, HS 2 and LS 2 with no changes.

In [3] a switching frequency between 15 kHz and 25 kHz is suggested. At these frequencies, first tests with these DUTs show a too strong self-heating, which should be avoided according to the standards of H3 TRB testing. Therefore, the switching frequency was lowered to 1 kHz with a duty cycle of 50 50% for this test. The test procedure is based on the standard HV-H3TRB procedure. After a ramp up to 85/85 within 1 h the pulsed voltage is turned on after a 24 h soaking phase (see Figure 4). With the voltage on the test duration starts. Intermediate blocking measurements are a proven method to detect humidity induced degradation and were taken after defined time steps to record the behaviour of the DUTs. Each intermediate measurement was preceded by a drying phase at 50∘C and 10%RH for 24 h to ensure safe electrical measurements. The test was started with 50% of the nominal voltage ( Vnom ,1,650 V ) at first to cover early failures and was raised to 80% Vnom  after 1,000 h.

Results

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

So far, 4,054 h of testing were completed and no module failed catastrophically yet. The "leakage" current is monitored, but is overlaid with oscillations caused by the switching currents, and is only used to detect a catastrophic failure of the DUT stack if the current exceeds the threshold of 50 mA . The intermediate measurements (IMs) were taken roughly every 1,000 h(1,022 h,2,070 h,2,836 h and 4,054 h ) (see Figure 5). At first one active switching DUT showed a reduced blocking capability and two additional DUTs showed this behaviour in the last IMs. Two phenomena can be observed. Firstly, a reduced inception voltage, i.e. the voltage at which the leakage current starts to rise exponentially. Secondly, an increased leakage current compared to previous IMs, which is especially dominant for the active DUT HS. After the last IM at 4,054 h, an extended drying procedure at 85∘C and 10%RH for more than 24 h was performed with the DUT stack to check if the deteriorated blocking behaviour is reversible. Except for one DUT, Figure 5 active DUT HS, with an only partially reversible blocking curve, all blocking curves returned to their initial measurements. This can be an indication of either residual moisture inside the silicone gel or possible delamination of layers at the junction termination that were filled with water layers and dried out only after the extra drying.
As there are no catastrophic failures, Weibull analysis does not work and an alternative method is required to compare different test groups. In Figure 6, the method is to extract the inception voltage values by defining an appropriate current level of the blocking measurement for each DUT and plot the median voltage with the corresponding 25% and 75% quartiles of the test group. This gives the development of the blocking capability over test time. In Figure 6, test results of [6, 10] and the dynamic test are compared. As reference the Silicon IGBT groups of [10] are included to show test groups with catastrophic failures and no blocking capabilities left. The DC HV-H3TRB test group of SiC MOSFETs survived over 6,000 h at two different test voltages, one even higher as for the dynamic test, and show no reduced blocking capabilities or changes that can be reversed through drying. The dynamic test group on the other hand has a drop at 4,054 h, which still slightly remains after extended drying. This leads to the assumption that the dynamic testing influences the DUTs already at lower testing time compared to the DC testing. If the duty-cycle of 50% is considered, the dynamic test group has only about 2,000 h, in which the DUTs are exposed to voltage.
It remains open, if it is a problem of the switching, humidity induced degradation or something else that is triggered. This can be only fully understood with analyses of failed DUTs, that still need to be generated within the continuation of the test. In any case, the modules already fulfil twice the qualification requirements for a standard HV-H3TRB ( 4,000 h·50% duty cycle =2,000 h net exposure time to DC voltage) even under these harsher conditions, in contrast to the gate units with failures after 2,000 h.

[picture]

Fig. 6. Normalised remaining blocking capability over testing time for the DUTs and for comparison DUTs from previous publications [6, 10].

Fig. 6. Normalised remaining blocking capability over testing time for the DUTs and for comparison DUTs from previous publications [6, 10].

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

A dynamic HV-H 3 TRB test with 3.3 kV SiC MOSFET in engineering packages was carried out for more than 4,000 h of testing time. The DUTs were stressed with high temperature, high humidity and switched high voltage. Within the test time no catastrophic failures occurred, but some DUTs changed their blocking behaviour in intermediate measurements. Most of these changes could be reversed through extended drying.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

This work was supported by the Horizon 2020 Shift2Rail Joint Undertaking project RECET4Rail under grant agreement number 101015423.
The authors are grateful to their colleagues of Mitsubishi Electric Europe and Japan for providing the special DUTs.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.121.pdf

J. Leppänen et al., Aluminium corrosion in power semiconductor devices, Microelectronics Reliability, vol. 137, 2022.

ECPE PSRRA01, HV-H3TRB tests for Power Semiconductor, 2019.

ECPE AQG 324, Qualification of Power Modules for Use in Power Electronics Converter Units in Motor Vehicles, 2025.

J.-H. Peters et al., Improved HV-H3TRB robustness of a 1700 V IGBT chip set in standard power modules, Microelectronics Reliability, vol. 126, 2021.

F. Hoffmann et al., Reliability of SiC MOSFET Power Modules under Consecutive H3TRB and Power Cycling Stress, Materials Science Forum, Vol. 1092, 2023.

M. Hanf et al., Power Cycling Performance of 3.3 kV SiC-MOSFETs and the Impact of the Thermo-Mechanical Stress on Humidity Induced Degradation, Solid State Phenomena, Vol. 360, 2024.

K. Hatori et al., Investigation of acceleration factors of the HV-H3TRB test on 3.3 kV SiC SBDs, EPE23 (2023).

I. Voss et al., Reliability and Ruggedness of SiC Trench MOSFETs for Long-Term Applications in Humid Environment, PCIM 2018, 2018.

O. Schilling et al., Generating and characterizing condensation phenomena in power modules, Microelectronics Reliability, vol. 126, 2021.

M. Hanf et al., Humidity Robustness of 3.3 kV SiC-MOSFETs for Traction Applications Compared to Standard Silicon IGBTs in Identical Packages, Material Science Forum, Vol. 1092, 2023.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 127-134

doi: 10.4028/p-eOEr1T

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-15

Accepted:
2026-02-27

Online:
2026-05-18

Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

Peter S. Ying 1,a*, Darwin Tsai 1, b, Alex Ma 1,c, George Wu 1, d, Akira Kamisawa 2,e, Shuichi Miyaoka 2,f, Nobuo Machida 2, g, Jimmy Wu 2, h

¹Actron Tech Co, 22,Sec.2,Nakan Rd, Luzhu Dis, Taoyuan City, Taiwan ROC

2 ANJET Corp, 5F.-6, No.308, Zhifu Rd., Zhongshan Dist., Taipei, Taiwan ROC

a* peter_ying@actron.com.tw, b Darwin_Tsai@actron.com.tw, c Alex_ma@actron.com.tw,

d  george_wu@actron.com.tw, e  dyx6m@anjet.com, f  s.miyaoka@anjet.com, g  n.machida@anjet.com, hjimmy@anjet.com

Keywords: power module, SiC, MOSFET, resonance, damping, planar, trench, power, output.

Abstract

Paralleling SiC MOSFETs in high-power modules introduces overvoltage and oscillation risks due to parasitic capacitances and inductances. This study presents a 200 kW EV inverter module co-designed at the device and packaging level to ensure switching reliability under harsh automotive conditions. At 800 V , the planar SiC MOSFET maintained stable gate voltage, while a benchmark trench device module experienced severe ringing and failure. Kelvin-source structures and internal gate resistors mitigated parasitic turn-on, and device-level optimizations-including a 0.5μ m foundry technology, silicide gate, and hexagonal cell layout-improved body-diode performance, together with the channel mobility, blocking voltage, and minimized on-resistance and switching losses. The resulting AEPR25B12C1STJN module demonstrated effective resonance damping, matched the performance of commercial trench module FS03MR12A6MA1B in static and dynamic tests, and achieved 98% AC efficiency with over 200 kW output at 150∘C junction temperature.

1. Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

Switching transients in SiC MOSFETs can induce unwanted oscillations, or ringing, due to the interaction of parasitic capacitances and inductances. While trench SiC MOSFETs offer performance advantages, they are particularly sensitive to these effects. Ensuring stable and reliable switching requires effective damping and careful device-module co-design[1][7]. This study presents the development of a 200 kW planar SiC power module for EV traction inverters, emphasizing resonance-damped gating, low on-resistance, and device-level optimization, especially in the Rg and Vt[4]. Improvements in device design, foundry technology, and cell layout enhanced blocking voltage, oxide reliability, and minimized switching losses. The resulting 6 -in- 1 AEPR25B12C1STJN module avoids ringing damage, achieves performance comparable to a commercial trench module (FS03MR12A6MA1B), and was validated via Dyno testing for high-reliability EV powertrain application.

2. Device Samples for1200𝐕Planar and Trench SiC MOSFET Modules

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

Paralleling SiC MOSFETs in high-power modules introduces overvoltage and oscillation risks due to parasitic inductance. To evaluate switching behavior, 1200 V planar and trench SiC MOSFETs were compared. The trench device was sourced from a 4th-generation commercial product [2], while the planar device was custom-fabricated using foundry technology [3]. Figure 1 presents the cross-sectional SEM and cell layouts, and Table 1 summarizes key datasheet parameters.

Table 1. Data sheet of both Trench and Planar SiC MOSFETs.

[picture]

Fig. 1. Cross section, SEM and cell top view of trench and planar SiC MOSFETs.

Fig. 1. Cross section, SEM and cell top view of trench and planar SiC MOSFETs.

3. Switching Waveform Comparison via Double Pulse Test (DPT)

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

Both devices were assembled into identical 6-in-1 half-bridge power modules using the same layout and packaging process. Double Pulse Test was conducted at HVDC =800 V, Id =100 A, Vgs, on =+15 V,Vgs, off =−5 V, and Rg, on/off =5.1Ω. As shown in Figure 2, the planar module maintained acceptable gate voltage swing (+12.3 V to 2 V), while the trench module exhibited excessive ringing ( 24.9 V to -11.7 V ) leading to device failure. Dynamic characteristics are detailed in Table 2.

[picture]

Fig. 2. Waveform comparison of trench and planar modules.
Table 2. Dynamics characteristics of trench and planar module.

Fig. 2. Waveform comparison of trench and planar modules. Table 2. Dynamics characteristics of trench and planar module.

[picture]

Fig. 3. TCAD simulation showed junction profiles enable E-field at Gox @ Vds =1200 V.

Fig. 3. TCAD simulation showed junction profiles enable E-field at Gox @ Vds = 1200 V .

4. Customization of Planar 1200 V SiC MOSFET with Foundry Technology

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

The planar device was optimized for high-performance switching. Enhancements included a Kelvin source structure, internal gate resistance, and improved body diode design to support reverse recovery without an external Schottky Barrier Diode. TCAD simulation (Figure 3) confirmed reduced electric field stress ( <2.83MV/cm ) at 1200 V Vds.

Key foundry process steps included dry oxidation with NO anneal for high-quality gate oxide, high-temperature ion implantation and >1400∘C anneal to reduce interface trap density (Dit), Short channel ( 0.5μ m ) to reduce Ron, and optimized doping profiles in N+/N- drift and P-well/P-body regions.
Layout enhancements (Figure 4), including hexagonal cell structures, silicide-gate integration, optimized gate runners, and Rg-spreading control (Figure 5), resulted in improved thermal performance and reduced switching losses. Benchmark evaluations further verified the reduction in Eon and demonstrated robust high-temperature performance.

[picture]

Fig. 4. Hexagonal & cellular layout for uniform current.

Fig. 4. Hexagonal & cellular layout for uniform current.

[picture]

Fig. 5. 10% Rg control.

Fig. 5. 10 % Rg control.

[picture]

Fig. 6. Less or equal Eon with Rg Spreading.

Fig. 6. Less or equal Eon with Rg Spreading.

Figure 6. showed the equal or less Eon loss benchmarked with two competitors. The key performance metrics is then to achieve greater than 1400 V Breakdown Voltage, less than 10 mΩ·cm2 area specific resistance, achieved gate oxide reliability of >106hrs at 25∘C with the <2.5 V Vf of body diode. Low Qgd<50nC is for fast switching purpose.

5.200 kW Power Module Design for EV Traction Inverter

A holistic design strategy was applied to the 200−kW half-bridge module, combining a customized planar SiC MOSFET with a gate-drive scheme tuned for resonance damping. The resulting 1200 V/400 A module focused on minimizing parasitic capacitance and inductance, improving thermal performance, and maintaining layout symmetry. Key features include a high-density, low-inductance structure; Cu-clip and Al-wire bonding for enhanced electrical and thermal efficiency; and a pin-fin baseplate on a Si3 N4 AMB substrate for direct liquid cooling. The design incorporates an integrated NTC sensor and press-fit terminals (Figure 8) and meets UL 94 V-0 and CTI >200 requirements (Figure 9).
The symmetric current layout (Figure 7) ensures uniform current sharing and thermal distribution, supporting high-power operation. The improved planar MOSFET body-diode performance eliminates the need for an external SBD. The module structure employs lead-free interconnects, a liquid-cooled pin-fin baseplate, and a Si3 N4AMB substrate, with press-fit contacts and a 150 ∘C-rated NTC enabling flexible integration into EV inverter systems.

[picture]

Fig. 7. Symmetric current layout.

Fig. 7. Symmetric current layout.

[picture]

Fig. 8. Schematic of power module design.

Fig. 8. Schematic of power module design.

[picture]

Fig. 9. Top view &outfit of the Actron power module.

Fig. 9. Top view &outfit of the Actron power module.

Figure 9 shows the top view and the outfit of the power module. The power module frame has passed rigorous vertical burning test UL 94 V-0, and insulation resistance of a material Comparative Tracking Index CTI > 200. This module has qualified according to AQG 324 with KS pin available and Negative Temperature Control (NTC) integrated.

6. Benchmark against Commercial Trench Module

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

[picture]

Fig. 10. AEPR25B12C1STJN benchmark with FS03MR12A6MA1B.

Fig. 10. AEPR25B12C1STJN benchmark with FS03MR12A6MA1B.

The AEPR25B12C1STJN planar module (same 216 mm2 chip area with competition) was benchmarked against the FS03MR12A6MA1B trench module [5]. (Figure 10) DPT at HVDC =600 V, Id =400 A with Rg,on /Rg,off =5.1Ω/5.1Ω showed comparable switching behavior. Planar SiC MOSFETs has lower Cgd and weaker Miller coupling with stable inversion channel under fast switching. It can safely operate with a lower Vt without risking false triggering therefore it is naturally more immune to dV/dt noise showing in Figure 11.

[picture]

Fig. 11. Waveform comparison between planar and trench Module.
Table 3. Static and dynamic test comparison Between Planar and trench module.

Fig. 11. Waveform comparison between planar and trench Module. Table 3. Static and dynamic test comparison Between Planar and trench module.

VGS=−5 V/+15 V at IFX datasheet

Commercial trench SiC MOSFETs provide higher channel density and current capability, enabling current peaks of several hundred amperes per switch during motor transients or regenerative braking in >100−kW EV inverter operation. As shown in Figure 11, both devices exhibit comparable switching behavior; however, the trench module produces a higher turn-on surge voltage ( 248 V ) than the planar module ( 219.7 V ), reflecting its greater susceptibility to voltage overshoot.
This behavior is linked to an inherent structural disadvantage of trench devices: the vertical gate geometry and tight cell pitch significantly increase the gate-to-drain capacitance Cgd and higher Miller coupling, making the device highly sensitive to dv/dt induced parasitic turn-on. Under these conditions, the complementary switch in the half-bridge can inadvertently conduct, creating a shoot-through path that threatens module reliability.
To prevent this, the trench MOSFET must operate with a substantially higher threshold voltage 4.56 V as shown in Table 3, to provide sufficient immunity against noise-induced gate excitation, premature channel formation, and field-stress-induced oxide degradation at the trench corners. In contrast, planar SiC MOSFETs inherently exhibit lower Cgd, weaker gate-drain coupling, and a more uniform electric-field distribution, enabling them to operate safely with a lower Vth of 2.52 V while still achieving comparable switching energy loss and overall efficiency.

7. Dyno Test and System-Level Efficiency

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

As summarized in table 4, Dyno testing conducted at 800 V and 1000 rpm confirmed that both the planar and trench SiC MOSFET modules delivered 220 kW AC output at 2000 Nm torque with a comparable inverter efficiency of 98%. The measured torque, rotational speed, and output power demonstrate that both module technologies meet the performance targets under full-load operating conditions.
However, the competitor's trench-based module exhibited a slightly higher junction temperature, indicating that the planar-based design provides marginally superior thermal conduction. This improved thermal behavior suggests additional margin for sustaining higher output capability or enhanced reliability under real-world EV operating conditions[6].

Table 4. Dyno test comparison between planar and trench module.

Cooler temp. (°C) | Module | Operation mode | Speed (rpm) | Torque (Nm) | HVDC (V) | DC Current (A) | DC Power (W) | AC Voltage (V) | AC Current (Arms) | AC Pow (kW) | MCU eff (%) | Tj (°C)
65 | Ixx | Low torque | 1000 | 1151 | 799.9 | 158.77 | 126.9 | 404.2 | 197.7 | 124.5 | 98.03 | 73.96
ATC | 1000 | 1142 | 799.9 | 157.67 | 126.1 | 391 | 197.9 | 123.4 | 97.9 | 75.12
Ixx | High torque | 1000 | 2040.8 | 799.5 | 285.66 | 228.3 | 489.3 | 339.4 | 223.1 | 97.69 | 101.8
ATC | 1000 | 2009 | 799.52 | 282.72 | 226 | 475.6 | 332.9 | 220.7 | 97.6 | 99.2

8. Summary and Conclusions

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

This study presents a resonance-damping strategy to ensure safe and reliable operation of a 200−kW EV-inverter power module. Double-pulse testing showed that the planar SiC MOSFET module maintained stable gate behavior, whereas the benchmark trench module exhibited severe ringing and catastrophic failure at 800 V,100 A. Consequently, the planar architecture-enhanced with a Kelvin-source layout and integrated gate resistance-was selected for further development.

A custom 1200 V planar SiC MOSFET module was designed and validated through simulation, Double Pulse Testing, and system-level testing, featuring optimized junction doping to balance reverse-recovery softness, conduction performance, and power density.
The device achieved >1400 V blocking capability, specific Ron <10 mΩ· cm2, gate-oxide lifetime >106 hours, body-diode Vf <2.5 V, and Qgd<50nC. The AEPR25B12C1STJN module employed a high-reliability packaging platform with Cu -clip and Al -wire bonding, a Si3 N4AMB pin-fin baseplate for liquid cooling, an NTC rated to 150∘C, and press-fit terminals.
System-level evaluation confirmed superior switching performance, thermal robustness, and efficiency compared with commercial trench modules. The design passed UL 94 V-0 and insulation tests (CTI > 200) and qualified under AQG 324 standards. Benchmarking against the FS03MR12A6MA1B commercial trench module demonstrated reduced ringing, improved damping, lower Rds(on), reduced Eon/Eoff at high temperatures, and enhanced thermal stability. Dynamometer testing at 800 V and 1000 rpm further verified 220 kW AC output at 2000 Nm torque with 98% inverter efficiency and a slight thermal advantage under real-world conditions.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.127.pdf

IET Power Electronics, Vol 15, Issue 11, Pages 989-1109 (2022).

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B.J. Baliga, "Fundamentals of Power Semiconductor Devices", Springer-Scientific Press, New York, 2008.

Saeed Anwar, Zhiqiang (Jack) Wang, and Madhu Chinthavali, "Characterization and Comparison of Trench and Planar Silicon Carbide (SiC) MOSFET at Different Temperatures" 2018 IEEE Transportation Electrification Conference and Expo (ITEC) 13-15 June 2018.

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Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 135-142

doi: 10.4028/p-BE7jb4

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-12

Accepted:
2026-02-28

Online:
2026-05-18

Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with  Different Wire Bond Layouts

The original version of this paper is available on https://www.scientific.net/KEM.1054.135.pdf

Masaki Takahashi 1,a*, Zhongchao Sun 1, b, Stig Munk-Nielsen 1,c, and Asger Bjørn Jørgensen 1, d

1 AAU Energy, Aalborg University, Pontoppidanstræde 111, 9220 Aalborg Øst, Denmark

a mata@energy.aau.dk, b zs@energy.aau.dk, c smn@energy.aau.dk, d abj@energy.aau.dk

Keywords: 10 kV SiC-MOSFET, Power Cycle Failure Mode, Wire Bond Layout

Abstract

V SiC-MOSFET power modules are being developed for medium-voltage applications, but their reliability has not yet been fully verified. This study demonstrates the power cycle test (PCT) on 10 kV SiC-MOSFET power modules with different wire bond layout designs to investigate the influence on their failure points. The 10 kV SiC-MOSFET is 8.1 mm square in size and 20 A/ die. Only four source wire bonds are needed, which provides enough flexibility for the wire bond layout. The wire bonds are placed on the edge of each source pad to reduce the wire heating ΔTwire  by 6.2% compared to the conventional central wire bond placement from the 3D simulation. These differences were verified in the PCT on ΔTdiemax :104−108∘C. As a result, it was observed that samples with the modified layout, which achieved a lower ΔTwire , exhibited a shift in failure mode from wire lift-off to solder failure, while maintaining a similar lifetime under higher die temperatures.

Introduction

The original version of this paper is available on https://www.scientific.net/KEM.1054.135.pdf

The 10 kV silicon carbide metal-oxide-semiconductor field effect transistors (SiC-MOSFETs) have the potential for the next generation power electronics due to their superior performance at mediumvoltage applications more than 6.5 kV [1]. To operate in this voltage range, 10 kV SiC-MOSFET dies have a larger edge area than lower voltage ones. This edge structure mitigates the concentration of electric fields at the edge of the die. Previous research [2] shows that the wide edge area of 10 kV SiC-MOSFETs makes the temperature gradient greater from the hot spot in the center of the die to the edge. Fig. 1 compares the die model of the 10 kV SiC MOSFET (Wolfspeed, samples under development) with a modelled 1.2 kV SiC-MOSFET, both having the same die size. The 1.2 kV SiCMOSFET is a hypothetical die with the same edge width and die thickness as the commercial product [20]. An optical microscope and micrometer measured the edge lengths and die thickness. The edge area ratio is the percentage of the edge region relative to all die surface area. Comparison of die surface temperature as line profiles using 3D finite element method (FEM) in [2] is also shown.

[picture]

Fig. 1: Die structural comparison and the die surface temperature profile [2].

Fig. 1. Die structural comparison and the die surface temperature profile [2].

The edge area ratio of a 10 kV SiC MOSFET is greater than that of a 1.2 kV SiC-MOSFET. Temperature simulations show that the ΔTdiesurface  at the die edge is about 10∘C larger for the 10 kV SiC-MOSFETs. In addition, a 10 kV SiC-MOSFET has a relatively large on-resistance, such as 340 mΩ[6,7], with a small current rating, 20 A/ die at room temperature. Due to their low current rating,
the number of source wires on the 10 kV SiC-MOSFETs is reduced. It has been reported that wire bond heating can be suppressed by optimizing the wire bond configuration on the die surface [8]. Thus, it will be a valuable design indicator if the structural weak points of the 10 kV SiC-MOSFET power module are the wire bond connections. A major approach to reliability investigation is the power cycle (PC) curve-based investigation [15]. This allows for their lifetime prediction. The main failure modes in power cycle test (PCT) are wire bond lift-off and solder failure in conventional Si and SiC devices [13,14]. However, no investigation has been performed on the impact of 10 kV SiC-MOSFET thermal performance on PC failure points. Therefore, evaluating the dominating failure mode on 10 kV SiC MOSFETs is the first step. The evaluation of failure points using PC curves requires a large number of samples, which is challenging for 10 kV SiC-MOSFETs because it is currently difficult to obtain sufficient samples. They are currently under development, and only a few engineering samples are available. Power module designers who do not manufacture devices in-house cannot access sufficient samples to evaluate reliability using the conventional PC curve method. This problem will be faced when developing all new innovative samples, not only 10 kV SiC-MOSFETs. Digital design using 3D modeling effectively solves this situation, especially in the early design phase when sufficient samples are unavailable [16]. The 3D temperature simulation suggests that improving the wire bond layout on the 10 kV SiC-MOSFET can suppress the wire heating temperature [3]. Since no PCTs have been performed on 10 kV SiC-MOSFET power modules, the literature has not yet discussed the influence of wire layout design on wire heating and its impact on reliability.

This study demonstrates the wire bond layout design of 10 kV SiC -MOSFET power modules based on 3D FEM temperature simulations as an initial investigation with minimal physical prototypes. 3D FEM calculates the wire bond temperature, and the layout that can suppress the wire bond temperature swing is investigated. Thus, the validity of these digital designs is demonstrated by evaluating the actual PCTs with physical prototypes of 10 kV SiC-MOSFET power modules that have two designs (conventional and modified).

Temperature Modeling of10kVSiC-MOSFET with Different Wire Bond Layouts

The original version of this paper is available on https://www.scientific.net/KEM.1054.135.pdf

The wire bond layouts with reduced wire heating were designed using a 3D temperature simulation of a 10 kV SiC-MOSFET power module model. In this research, half-bridge power modules with 10 kV SiC-MOSFETs were manufactured [5]. This is the same as the module used in Fig. 1. A 3D model

[picture]

Fig. 2: 10 kV SiC-MOSFET power module structures in this research

Fig. 2. 10 kV SiC-MOSFET power module structures in this research

with the same structure as this module was created, and a temperature simulation was performed using ANSYS Mechanical. In this modeling, the SiC-MOSFET die is 4H−SiC only for simplicity, and the metalization layer is not considered. Other structures and physical properties were reused from those shown in [2]. For simulation, this module model was fixed on a 10 mm -thick aluminum heat sink, and the bottom temperature of the heat sink was kept T0=70∘C as a boundary condition. The turn-on pulse width tW was 5 seconds. The die surface maximum temperature was heated to Tdiemax =175
∘C by applying the power PW. Two wire bond layouts on the 10 kV SiC-MOSFETs were prepared: a conventional layout (typical wire bonding at the center of each source pad) and a modified layout (wire placement at the edge of each source pad, which is a lower temperature place). Fig. 3 shows the respective wire bond layouts, sample photographs, and the simulated temperature of the interface between wire bonds and the die, maximum wire bond heating temperatures ΔTwiremax .

[picture]

Fig. 3: Two different wire bond layouts and their temperature simulation results.

Fig. 3. Two different wire bond layouts and their temperature simulation results.

The simulation results showed that the modified wire bond layout has 6.2% lower ΔTwiremax  than the conventional one. This is because the center of the die, where the surface temperature is higher, is physically avoided as a wire bond location.

Actual PCT Evaluation

The original version of this paper is available on https://www.scientific.net/KEM.1054.135.pdf

Test setup and conditions. As an evaluation of their reliability performance, actual PCTs are used to confirm the influence of the wire bond layout in Fig. 3. The test setup photograph and its circuit diagram are shown in Fig. 4.

[picture]

Fig. 4: Power cycle test setup and a circuit diagram.

Fig. 4. Power cycle test setup and a circuit diagram.

These power module samples were mounted on an aluminum heat sink and kept at a constant temperature throughout the test with liquid cooling using Julabo 1000 F . The temperature of the heat sink was Th=60 or 70∘C to reach the target maximum temperature. Although the resulting die temperature slightly varied among samples, the number of cycles to failure Nf is considered to be predominantly governed by the temperature swing within this experimental range, as is often the case in PCTs. The target maximum die surface temperature was Tdiemax =175∘C. This Tdiemax  was

Table 1: All sample PCT results

Sample No.
Wire bond layout

[cycles]

Failure mode

A | Conventional | 176.2 | 104.2 | 32757 | Wire bond lift-off
B | Conventional | 185.4 | 113.4 | 19998 | Wire bond lift-off
C | Conventional | 157.0 | 95.0 | 67975 | Solder failure
D | Modified | 180.0 | 108.0 | 32002 | Solder failure
E | Modified | 175.8 | 113.8 | 38024 | Solder failure
F | Modified | 173.7 | 111.7 | 24212 | Solder failure

measured using the fiber optic sensor from Opsens Solutions Coresens [4] to match the simulated physical temperature. A multichannel DC power analyzer, Keysight N6705C DC, supplied the gate and central power, which are VGS=17.5 V and ID=15 A. Two samples were tested simultaneously and alternately switched. That is, when one device was turned on, the other device was turned off. This test circuit supplies constant DC from the power supply by alternating between the samples under test. When the first sample broke, it was replaced by another sample, and the test continued. The on and off times were 5 seconds each. The power module's on-voltage, as the drain-source voltage VDS(on), was monitored using the same equipment. A sample failure criterion is usually established for measuring the Nf, defining failure as an increase in the VDS(on) of 5% relative to the initial value.
Lifetime measurement results. Fig. 5 shows the monitoring results of VDS(on) measured during the PCTs. All PCT results are summarized in the Table. 1 showing the Nf values and observed failure modes.

[picture]

Fig. 5: VDS(on) monitoring results for all samples during PCTs.

Fig. 5. V D S ( o n ) monitoring results for all samples during PCTs.

As shown in the Table. 1, all samples have different Tdiemax , which is thought to be due to variations in the on-resistance of each die. In Sample A and B with conventional layouts, a sharp drop in onvoltage was observed after the rapid increase in Fig. 5. This is expected because the wire cracks spread to the wire bond-die interface and deteriorated the electrical connectivity, resulting in a temporary increase VDS(on). This was followed by a complete wire bond lift-off from the die surface, resulting in a disconnection state and a sudden drop in the measured on-state voltage. The VDS(on) value of Sample C-F reached the failure criteria. From these results, the Nf was calculated. Next, to confirm the cause of the changes in VDS(on), various evaluations of each sample before and after PCT were performed. Failure mode analysis. The failure mode of all six samples in Table. 1 was verified. The ID−VDS characteristics of the MOSFETs as electrical characteristics are compared before and after the PCT using a curve tracer. In addition, the transient thermal impedance Zth ( diemax −h) was calculated from
the die surface temperature measurement to compare a Sample D after PCT and a reference 10 kV SiC-MOSFET power module that has not undergone any PCTs. The measurement setup used the same setup as in Fig. 4 and an optical fiber. The Zth(diemax-h)  was calculated by the equation;

Zth( diemax-h )=(Tdiemax −Th)÷(VDS×ID)(1)

Constant DC was applied to these two modules for 5 seconds under the same conditions as the PCT. Baseplate temperatures were also kept 70∘C by a water-cooled aluminum heat sink. Fig. 6 shows the ID−VDS characteristics of the MOSFETs before and after the PCTs and the transient thermal impedance measurements results on Sample D.

[picture]

Fig. 6: Sample evaluation before and after PCTs; ID−VDS, and Thermal impedance.

Fig. 6. Sample evaluation before and after PCTs; I D − V D S , and Thermal impedance.

Samples A and B did not show any difference between the drain-source, even though the gate voltage was applied. This suggests that the circuit between the gate-source is non-destructive, while the circuit between the drain-source may have been broken. This will be confirmed later by the microscopic observation of the failure points in the sample. Sample C-F showed no changes in I-V characteristics after PCTs. This could be due to increased thermal resistance without changing the module's package resistance, which could have caused the sharp rise in on-voltage seen in Fig. 5. Such an increase in on-voltage due to an enlargement in thermal resistance is known to be caused by the degradation of the solder layer under the die [17]. Sample D after the PCT increases Zth(diemax-h)  after 100 ms compared with the reference sample. At 2,000 ms (2 seconds), the thermal resistance of Sample D is more than three times that of the reference. The results show that the rise in on-voltage on Sample D, as seen in Fig. 5, is due to higher Tdiemax  with increasing thermal resistance. As a direct comparison, the differences in failure points were observed in Sample A and Sample D. They are similar Tdiemax  and ΔTdiemax , may indicate different failure modes. Those hypotheses were verified by direct observation using an optical microscope. Each of the failure points is shown in Fig. 7.

It was also observed that the failure points changed from wire bond lift-off in Sample A to solder degradation (cracking) in Sample D. In Sample A, wire bonds and the die surface were disconnected during the PCT, resulting in a lost measurement signal, as seen in Fig. 5. In Sample D, the PCT did not noticeably change the internal connection caused by the wire bond failure, but the thermal resistance increased due to the solder failure. Fig. 5 shows the rapid increase in on-voltage caused by the rising die temperatures during the PCT. The Nf of Sample A was 32,757 cycles, and Sample D was 32,002 cycles. The change in the wire bond layout on Sample D showed a similar Nf with different failure modes.

Discussion

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The results are summarized in Fig. 8 as the PC curve with Nf and ΔTdiemax . Their wire bond layouts and failure modes differentiated each plot.

[picture]

Fig. 7: Failure point observation results for Sample A and D

Fig. 7. Failure point observation results for Sample A and D

[picture]

Fig. 8: PC curve with failure mode difference and the description of the failure mode shift.

Fig. 8. PC curve with failure mode difference and the description of the failure mode shift.

Furthermore, the PC curves were classified into two lines according to the failure mode. The PC curve of wire bond lift-off in Samples A and B is lower than that of solder failure. Samples A and B are also conventional wire bond layouts. On the other hand, Sample C, along with the other conventional layout, was in solder failure mode under low ΔTdiemax  test conditions. All samples with a modified layout (Sample D-F) were also in solder failure mode with a higher Nf PC curve line. Previous research estimated the Nf on PCT by the following equation (2) [19]. The model is generally formulated by fitting the Nf with different die temperature swings ΔT.

Nf=A×ΔTα×exp(β/Tjmean )(2)

where A,α, and β are constants from the measured data fittings. Then, these values are determined by the design, such as die area, die thickness, and bond wire diameters [19]. These models from references contain a mixture of two failure modes: wire bond lift-off and solder degradation. In particular, in Nf(ΔT), which is a function of ΔT, the constant α is a factor that determines the slope of PC curves. The experimental results show that the slope α of the PC curve differs depending on the failure mode of power modules [12, 18]. The slope value α is larger in the wire bond lift-off failure mode than in solder degradation in the reference [12]. As a result, under high temperature swing ΔT conditions, wire bond lift-off is the dominant failure mode, and the failure mode at low ΔT shifts to the solder layer. Under lower ΔT conditions, the solder failure mode is predicted to be the main failure factor, as shown in Fig. 8. This may explain why a solder failure mode was identified in Sample C. On the other hand, at high ΔT conditions, the solder lifetime at the same temperature swing is higher than the wire bond lift-off lifetime. This explains why sample D-F (modified layout) with solder failure has a higher Nf than sample A-B (conventional layout) with wire lift-off in the PCT at the same ΔT. Comparing Sample A and D , both have about the same ΔT test conditions with different ΔTwire  shown in Fig 3. For example, 6.2% lower ΔTwire  caused a shift in the failure mode. This suggests that the suppression
of wire heating ΔTwire  increased the wire bond lifetime, and the shift of the failure mode from wire bond lift-off to solder failure occurred at the higher ΔT condition. Wire bond lift-off in PCT is due to shear stress. It has been reported that the driving force of this shear stress is the self-expansion of the wire during heat generation [11]. In this case, a large wire heating ΔTwire  causes a larger selfexpansion of the wire. Therefore, suppressing ΔTwire  reduces the shear stress at the wire-die interface and improves the wire bond lift-off lifetime. As a result, it is considered that the solder degradation was observed in Sample D-F, where the wire bond lifetime was higher than the solder layer lifetime. Although only two data points were obtained for wire bond lift-off in the PCTs, the steeper slope is consistent with previously reported findings [12], which indicate a stronger dependency of wire bond lift-off on ΔT compared to solder degradation.

These were the two PC failure modes on 10 kV SiC-MOSFETs: wire bond lift-off and solder failure. The changes in failure modes can also be used to assess the optimization of the wire bond design. For example, if the wire bond layout minimizes ΔTwire  and the PC failure mode is solder failure, the wire design can be assessed as sufficiently optimized. Thus, changes in failure modes may be sensitive to the wire bond layout design, especially for dies with small wire bond density, such as 10 kV SiC-MOSFETs. Therefore, the validity of the design can be evaluated by considering the presence or absence of wire bond lift-off as a design parameter in the wire bonding layout design optimization method. This research presents a structural optimization method for improving their wire bond reliability. The wire bond layout with the lowest ΔTwire  in the simulation has the maximum PC lifetime to wire lift-off failure mode for 10 kV SiC-MOSFET power modules. This wire bond design strategy is superior because it is technically the simplest and can be implemented without additional cost. This discussion does not aim to improve the reliability of the solder layer. To extend the PC lifetime, structural design against solder degradation is necessary, and increasing the number of wire bonds is meaningless because the failure mode shifts from wire bonds to the solder layer. The identification of structural weak points obtained through this demonstration provides essential knowledge for designing more reliable power module structures.

Conclusion

The original version of this paper is available on https://www.scientific.net/KEM.1054.135.pdf

For 10 kV SiC-MOSFET power modules, the effect of changing the wire bond layout on PC failure modes was demonstrated. The large edge area of the 10 kV SiC-MOSFET results in a significant temperature gradient on the die. However, the low current density of the die provides the high flexibility of the wire bond layout. These unique factors of 10 kV SiC-MOSFETs enabled the improvement of Nf through a modified wire bond layout by suppressing the ΔTwire . The result revealed that the wire bond layout modification with ΔTwire  reduced by 6.2% in the simulation changed the failure point from wire bonds to solder layers. This failure mode shift was expected to a higher Nf from the statistical understanding based on the PC curve. The results show that wire bonds can be optimized by layout design using the 3D temperature simulation and a minimum number of prototypes. In other words, this study demonstrated an efficient design method to improve the reliability of 10 kV SiC -MOSFET power modules using 3D simulations.
Acknowledgments. This research is carried out as a part of the Center of Digitalized Electronics (CoDE) project at Aalborg University, funded by the Poul Due Jensen Foundation, Denmark.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.135.pdf

V. Pala, et. al., 10 kV and 15 kV Silicon Carbide Power MOSFETs for Next-Generation Energy Conversion and Transmission Systems, ECCE (2014), p. 449-454

M. Takahashi, et. al., Temperature distribution of 10 kV and 15 kV SiC-MOSFETs with large edge area, EPE'23 ECCE Europe (2023)

M. Takahashi, et. al., Digital design demonstration of 10 kV SiC-MOSFET power module to improve wire-bonding layout for power cycle capabilities, IWIPP (2022)

K. Zhang and F. Iannuzzo, Measuring Temperature Swing with Optical Fibers during Power Cycling of Power Components, PEDG (2022)

A. B. Jørgensen, et. al., Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM, EPE'17 ECCE Europe (2017), 1-8

J. B. Casady, et. al., New Generation 10 kV SiC Power MOSFET and Diodes for Industrial Applications, PCIM Europe (2015), 1-8.

C. DiMarino, et. al., Characterization and comparison of 1.2 kV SiC power semiconductor devices, EPE'13 ECCE Europe (2013), 1-10,

I. Masayasu, et. al., Design concept for wire-bonding reliability improvement by optimizing position in power devices, Microelectronics Journal 37 (2006) 262-268

R. Ø. Nielsen, et. al., Innovative Measuring System for Wear-out Indication of High Power IGBT Modules, ECCE (2011), 1785-1790

U.M. Choi, et. al., Power cycling test and failure analysis of molded Intelligent Power IGBT Module under different temperature swing durations, Microelectronics Reliability 64 (2016) 403-408

T.Y. Hung, et. al., Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test, Microelectronics Reliability 51 (2011) 1819-1823

M. Junghaenel, et. al., Investigation on Isolated Failure Mechanisms in Active Power Cycle Testing, PCIM Europe (2015) 1-8

A. Morozumi, et. al., Reliability of Power Cycling for IGBT Power Semiconductor Modules, IEEE Transactions on Industry Applications, Vol.39, No. 3 (2003) 665-671

B. Hu, et. al., ailure and Reliability Analysis of a SiC Power Module Based on Stress Comparison to a Si Device, IEEE Transactions on Device and Materials Reliability, vol.17, no. 4 (2017) 727-737

R. Bayerer, et. al., Model for Power Cycling lifetime of IGBT Modules - various factors influencing lifetime, CIPS (2008) 1-6

A. B. Jørgensen, et. al., Overview of Digital Design and Finite-Element Analysis in Modern Power Electronic Packaging, IEEE Transactions on Power Electronics 35, 10 (2020) 10892-10905

Y. Jia, et. al., Impact of Solder Degradation on VCE of IGBT Module: Experiments and Modeling, IEEE Journal of Emerging and Selected Topics in Power Electronics 10, 4 (2022) 4536-4545

R. Schmidt, et. al., Power Cycle Testing at Low Temperature Swings - Evaluating the Stability of SAC- and SnSb-based Chip Solder Layers, CIPS (2020) 196-201

F. Hoffmann and N. Kaminski, Impact of Device Design on the Power Cycling Capability of Discrete SiC MOSFETs at Different Temperature Swings, ISPSD (2020) 533-536

Wolfspeed, CPM2-1200-0025A datasheet Rev. 01, (2021) (Viewed on 21st August, 2025)

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/the-22nd-international-conference-on-silicon-carbide-and-related-materials-icscrm/978-3-0364-1825-4

Key Engineering Materials, ISSN: 1662-9795, Vol. 1054, pp 143-148

doi: 10.4028/p-KunI9m

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-11

Revised:
2025-12-29

Accepted:
2026-02-28

Online:
2026-05-18

Low-Inductance Packaging Design for SiC Power MOSFET Modules

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

Zhaobo Zhang 1,a, Renze Yu 1, b, Saeed Jahdi 1,c*, Olayiwola Alatise 2, d, Francesco lannuzzo 3,e and Bernard Stark 1,f

1 University of Bristol, Bristol, BS8 1UB, UK

2 University of Warwick, Coventry, CV4 7AL, UK

3 Polytechnic University of Turin, Torino, 10129, Italy

a  zhaobo.zhang@bristol.ac.uk, b  renze.yu@bristol.ac.uk, c  saeed.jahdi@bristol.ac.uk,

d  o.alatise@warwick.ac.uk, efrancesco.iannuzzo@polito.it, f  bernard.stark@bristol.ac.uk 

Keywords: SiC MOSFETs, packaging, energy density, power modules.

Abstract

With the continuous advancement of SiC device design and manufacturing processes, devices of the same ratings are achieving higher turn-on speeds and smaller chip areas. These improvements enhance the speed and power density of power electronic systems but also pose greater challenges for thermal management and the parasitic parameters of packaging. To address these issues, this paper proposes a multi-chip SiC power module packaging structure based on a multilayer ceramic substrate. Compared to a conventional single-layer DBC substrate, the multilayer substrate structure incorporates an additional intermediate copper layer, which serves as a current return path. Due to the close proximity between this return path and the upper copper layer, the overall loop area is reduced, thereby lowering the parasitic loop inductance. Simulation results show that the designed 800 V,50 kW SiC power module achieves a parasitic loop inductance of around 3.22 nH at 10 MHz . In addition, traditional multilayer DBC structures are typically formed by soldering two separate DBC substrates together. Such soldered interfaces are often mechanically unstable, and electrical continuity between the upper and intermediate copper layers is not established. The structure proposed in this work adopts a monolithic substrate, in which a single 300μ m thick copper layer is embedded without the use of additional solder. Compared to conventional multilayer substrates, this configuration offers improved thermal conduction by eliminating solder interfaces and enhancing heat flow.

Introduction

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The advancement of silicon carbide ( SiC ) power devices demands innovative packaging solutions that can fully exploit their superior electrical, thermal, and switching performance. Traditional silicon-based packaging techniques often fall short in meeting the high-temperature operation, fast switching speeds, and reduced parasitics that SiC devices enable [1]. As a result, novel packaging approaches are being developed to address these challenges [2,3]. These include double-sided cooling configurations [4,5], the use of advanced substrates such as silicon nitride (Si3 N4) and aluminum nitride (AlN) for improved thermal conductivity and mechanical reliability [6], and the integration of 3D packaging structures [7]. Additionally, low-inductance interconnections using wide metal clips or embedded die technology are gaining traction, aiming to minimize loop inductance and enable high-speed switching with reduced voltage overshoot and oscillations which could have serious reliability consequences [8].

More recently, high-temperature capable materials, such as sintered silver (Ag) die attach and high-temperature polymers, are being explored to increase the thermal and mechanical robustness of SiC modules [9]. The shift toward fully lead-free, high-reliability interconnects also aligns with global sustainability goals and regulatory standards. Embedded passive components, integrated sensors, and advanced thermal interface materials are being incorporated to enable smart, compact, and more efficient power modules. These packaging innovations are not only essential for leveraging the benefits of SiC devices, but they also represent a critical step toward achieving higher power density, longer lifetime, and lower system cost in next-generation power electronics.

The aim of this paper is to investigate a low-parasitic, high-reliability multi-chip power module packaging structure for Wolfspeed Gen 3+ SiC MOSFETs. In this context, a multilayer ceramic substrate for the power module is designed. The fabricated module employs silver sintering for die attachment and wire bonding for electrical interconnection. Furthermore, the simulations are conducted using COMSOL to analyze the thermal, parasitic inductance, and electric field distributions within the multilayer substrate-based power module.

Design Approach

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Module development.

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

Fig. 1 shows the proposed multilayer power module structure. The monolithic substrate consists of three copper layers. Apart from the top and bottom layers, which are similar to a standard DBC design, an additional middle layer serves as the return path for the current. The DC pattern fills the entire middle layer and connects it to the top layer. This substrate structure enables a shorter distance between the DC+ and DC- patterns, thereby increasing the mutual inductance between them and reducing the overall loop inductance.

[picture]

Fig. 1. Schematic diagram of multilayer substrate power module. The middle layer copper works as the current return loop.

Fig. 1. Schematic diagram of multilayer substrate power module. The middle layer copper works as the current return loop.

Based on the multilayer substrate, a 1200 V,50 kW SiC half-bridge power module is designed, as shown in Fig.2(b). Two parallel Wolfspeed EPM3-1200-R013D SiC MOSFET dies are used for each half-phase leg to ensure a 200A rated current. Laminated DC+ and DC- busbars are chosen to further reduce loop inductance. The module integrates a hybrid PCB as the current loop for the gate signal. A Kelvin connection is used for the gate signal design to ensure the separation of the power loop and the drive loop. For comparison, a conventional power module is designed, as shown in Fig.2(a).

For the proposed multi-chip SiC power module structure, the design is also well-suited for scaling the number of chips, for example, from two in parallel to four or even six in parallel. Such scaling can be achieved while maintaining the module's symmetrical layout and ensuring current sharing among individual chips. Moreover, although the width of the overall power loop increases with scaling, its length remains unchanged, which is beneficial for reducing loop inductance. In contrast, for the conventional chip layout shown in Fig. 2(a), it is difficult to expand the number of chips while preserving both compact module design and low loop inductance.

[picture]

Fig. 2. (a) Conventional power module structure. (b) Multi-chip power module packaging with multilayer ceramic substrate.

Fig. 2. (a) Conventional power module structure. (b) Multi-chip power module packaging with multilayer ceramic substrate.

Fig. 3 illustrates the assembly process of the power module. The primary difference in the proposed structure lies in the use of a multilayer ceramic substrate. Aside from the substrate, the assembly process remains similar to that of a conventional module. The process begins with the preparation of the multilayer ceramic substrate. Subsequently, the power semiconductor dies are attached to the substrate, followed by bonding of the substrate to the baseplate. The PCB for the gate drive loop is then mounted onto the substrate. This step is followed by wire bonding and the installation of current sensors on the PCB. Next, the external terminals and pins are soldered to the module. Finally, the case is installed, and encapsulation is carried out to complete the assembly.

[picture]

Fig. 3. Manufacturing process of a novel SiC Module.

Fig. 3. Manufacturing process of a novel SiC Module.

Modeling and Simulation.

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

To verify the thermal performance and measure the loop inductance of the module, a COMSOL Multiphysics model is developed. The module employs liquid cooling for heat dissipation. To simulate forced convection liquid cooling, a thermal convection coefficient of 15000 W/m2 K is applied to the bottom surface of the baseplate [10]. The coolant temperature is set to 24∘C, and the power dissipation of each die is specified as 150 W .

Results and Discussion

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

Fig. 4 illustrates both the single-layer and multilayer substrate structures. In the case of the multilayer substrate, the electrical connection between the upper and lower copper layers results in a thicker overall copper structure, which can cause significant mechanical stress at the bonding interface near the ceramic edge. This stress concentration may lead to cracking of the ceramic. To mitigate this issue, a stepped design is applied at the edge of the interconnected copper layers, effectively reducing the localized stress in that region.

For the substrate, the copper layer has a thickness of 300μ m, and its surface is plated with silver to facilitate the silver sintering process during die attachment. Aluminum nitride (AlN) is used as the ceramic material, providing a high thermal conductivity of approximately 180 W/m·K.

[picture]

Fig. 4. The fabricated substrates for the modules. (a) Single-layer substrate. (b) Multilayer substrate.

Fig. 4. The fabricated substrates for the modules. (a) Single-layer substrate. (b) Multilayer substrate.

The temperature field of the module is shown in Fig.5. The results indicate that the maximum junction temperatures of conventional packaging and multilayer substrate packaging are 114.2∘C and 105.3∘C, respectively. For the multilayer substrate module, the average device temperatures are in the range of 90.5∘C to 91.2∘C, indicating a relatively uniform current and temperature distribution during operation. The maximum junction temperature also corresponds to a favorable operating point for the package. The thermal resistances from junction to coolant for the conventional module and the multilayer power module are 0.150 K/W and 0.136 K/W, respectively. These results demonstrate that, although the substrate thickness increases due to the additional layers, the thermal performance can still be improved through an optimized module layout.

[picture]

Fig. 5. Modelled temperature field of module with (a) conventional & (b) multilayer ceramic substrate.

Fig. 5. Modelled temperature field of module with (a) conventional & (b) multilayer ceramic substrate.

The simulated loop inductances of the conventional power module and the multilayer power module are 4.82 nH and 3.22 nH at 10 MHz , respectively, demonstrating the improved performance of the proposed design in minimizing parasitic inductance [11]. Fig. 6 illustrates the magnetic flux density distribution of the conventional and multilayer substrate power modules.

[picture]

Fig. 6. Magnetic flux density distribution of (a) conventional and (b) multilayer substrate module.

Fig. 6. Magnetic flux density distribution of (a) conventional and (b) multilayer substrate module.

Fig. 7 illustrates the simulated electric field distribution of the modules. The strongest electric fields appear at the triple-point regions of each module. In this case, the results actually indicated a slightly higher electric field in the multilayer substrate 1.2 kV module compared with the conventional design, albeit with small margin. This is likely due to the reduced spacing between the 800 V and 0 V nodes in the multilayer configuration. Nevertheless, for low voltage SiC power modules (with operating voltage below 2 kV ), the overall electric field strength remains significantly lower than that in medium voltage power modules [2,3]. Consequently, the risk of partial discharge failure is extremely low, and the increase in electric field strength introduced by the multilayer substrate technology remains well within the safety margin.

[picture]

Fig. 7. Electrical field distribution in (a) single-layer packaging and (b) multilayer packaging.

Fig. 7. Electrical field distribution in (a) single-layer packaging and (b) multilayer packaging.

Summary

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

A SiC power module with a multilayer substrate is designed and evaluated using COMSOL Multiphysics. The module incorporates four SiC MOSFETs, with two parallel-connected devices used for the high side and the other two for the low side. Simulation results indicate that the proposed multilayer substrate design outperforms the conventional module in terms of thermal performance and loop inductance, demonstrating the potential of the proposed structure for improved power module performance.

Acknowledgement

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

We would like to acknowledge the support of the UK Engineering and Physical Sciences Research Council (EPSRC) through research grants EP/Y000307/1 and EP/Z531091/1 to fund this project.

References

The original version of this paper is available on https://www.scientific.net/KEM.1054.143.pdf

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T. Ueda, et al., "Simple, compact, robust and high-performance power module T-PM (transfermolded power module)", in Proc. Int. Symp. Power Semicond. Devices ICs, 2010, pp. 47-50.

L. Wang, et al., "A Review of Partial Discharge in Medium Voltage SiC Power Modules Under Square Wave Excitation: Characterization, Mitigation, and Detection," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 12, no. 4, pp. 3588-3606, Aug. 2024, doi: 10.1109/JESTPE.2024.3408449.

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M. Appleby et al., "Instrumentation Requirements for Fast Switching of mOmega SiC MOSFETs," PCIM Europe 2024, Nürnberg, Germany, 2024, pp. 3271-3280, doi: .

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Keywords Index

#

10 Kv Sic-mosfet Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

12-inch 4h-sic Substrate 300 mm4H-SiC Crystal and Substrate Development

1ssf Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

200 Mm SiC Wafer Technology Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

300 Mm 4 H -sic Crystal 300 mm4H-SiC Crystal and Substrate Development

3300 V 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

3c Inclusions Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

3D Tcad Simulation Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

4 H -sic DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes; Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

4 H -sic Detectors Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

4 H -sic Mosfet Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

4 H -sic; Characterization; X-ray Topography; Defects Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method

4 H -silicon Carbide Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

4h-sic Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine; Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation; NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC; Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

4h-sic Lateral Cmos Technology Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

4h-silicon Carbide (sic) Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

A

Ac-bti Temperature Dependence of the AC-BTI in SiC MOSFETs

Activation Annealing Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Afm DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes; A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Ald Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Altair Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Analytical Modeling An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

And Electroluminescence Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

And Lateral Ion Straggle Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Atomic Layer Deposition Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Augmented Reality (ar) Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Automotive Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Avalanche Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

B

Backside Contact Resistance Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Backside Reflection Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Basal Plane Dislocation Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density; Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Basal Plane Dislocation (bpd) Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

Basal Plane Dislocations BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Bi-directional Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Bi-directional Mosfet Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Bi-directional Switch Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Bias Temperature Instability Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Bias Temperature Instability (bti) Temperature Dependence of the AC-BTI in SiC MOSFETs

Bidirectional Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Bipolar Degradation Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET; Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Bipolar Phototransistor Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Blocking Capability Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

Body Diode Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET; Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs; Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Bonded Substrate Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Bonding Technique Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Border Traps Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Boron Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Bpd Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Bpd Crowding Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Bpd Pileup Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Breakdown Voltage Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Brewster's Angle Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Bulk Growth Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Bumps Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Burger Vector Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

C

C-v Characteristics Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Candela Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Capacitance Measurements Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Capacitance Peak Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Capacitors Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Carbon Vacancy Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Channeling Implantation Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Characterization DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Charge Carrier Lifetime Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Charge Pumping Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Charge-balance Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Charge-imbalance JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Chemical Vapor Deposition (cvd) Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Circular Tlm Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Clamped Pmos Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Close Space Pvt Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Common Drain Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Contact End Resistance Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Contact Length Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Contact Resistance Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Coulomb Scattering Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Cover Wafer Effect Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Critical Dimension Metrology Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Cryogenic Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Cryogenic Temperatures Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

Crystal Diameter Expansion 300 mm4H-SiC Crystal and Substrate Development

Cs-pvt Growth Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Cv Characteristics Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Cv Measurement Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Cvd Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways

D

Damping Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Datasheet Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Deep Level Defects DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Deep Levels Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Deep Oxide Traps Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Defect Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay; Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Defect Characterization Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Defect Formation Polytype Transitions in Silicon Carbide: A Macroscopic View

Defect Reduction Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Defects Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications; Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Micropipes in SiC die Observed by Molten KOH Etching

Density Of Interface States Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Design Approach Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Device Degradation Polytype Transitions in Silicon Carbide: A Macroscopic View

Device Failure Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Dies Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Discrete Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Dislocations Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Dlts DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC; A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Doping Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Draininduced Barrier Lowering (dibl) Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Dual-acceleration-factor E-model Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Dual-bias Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Dynamic Breakdown Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Dynamic Conduction Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Dynamic Gate Stress (dgs) Temperature Dependence of the AC-BTI in SiC MOSFETs

Dynamic Gate Switching (dgs) Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

Dynamic Losses 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Dynamic Reverse Bias Stress Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

E

Edge Exclusion Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Edge Termination Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Edge Termination Techniques Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Edge-thinning Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Effective Lifetime A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Electric Field Characterization Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Electrical Characteristics Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Electrochemical Etching CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Electrochemical Passivation Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Electromagnetic Design Space Exploration of SiC Power Module Package via Surrogate Model

Electron Beam Induced Current A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Elfr Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Ellipsometry Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Em.mi Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Embedded Cmos Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Energy Density Low-Inductance Packaging Design for SiC Power MOSFET Modules

Energy Filtered Ion Implantation Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Epitaxial Growth Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications; A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Ews Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Experimental Results Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

F

Failure Analysis Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Far-uvc Detection Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Field Limiting Rings (flrs) Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Fixed-abrasive Lapping Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Flat-band Voltage Shift Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Focused Ion Beam Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Forward Voltage Drop Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Fowler-nordheim Current Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Frequency Scanning Interferometry Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

G

Gamma Ray In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Gamma-ray Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Gan Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Gate Capacitance Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Gate Leakage Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Gate Oxide Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Gate Oxide Field Crowding Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Gate Oxide Reliability Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Gate Screening Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Gate Switching Instability Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET; Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Gate Switching Instability (gsi) Temperature Dependence of the AC-BTI in SiC MOSFETs

Gate Switching Stress Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Gate-leakage Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Gated Hall Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Glow Discharge Mass Spectrometry (gdms) Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Graphene Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways

H

Hall Measurement Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Hall Mobility Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Harsh Environment In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Heavy-ion Irradiation Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

High Current Characteristics of High Current 4H-SiC Schottky Barrier Diodes

High Drain Voltage Bias Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

High Temperature SiC Oxidation Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

High Voltage Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

High-frequency Power Electronics The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

High-k 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

High-temperature Gate Bias (htgb) Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

High-voltage Device Testing High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Htrb Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Hv-h³trb Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Hysteresis Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

I

Idss Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

In-grown Stacking Fault Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

In-situ Observation Solution Growth Technique of Silicon Carbide with In Situ Observation

Induction Heating Solution Growth Technique of Silicon Carbide with In Situ Observation

Integrated Circuit In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Interface Traps Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Ion Implant Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Ion Implantation Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Ion Implantation Depth Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Irradiation Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Irradiation Temperature Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Isotopically Enriched Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

J

Jbs Diode Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Jfet In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Junction Termination Extension Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Junction Termination Extension (jte) JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

K

Koh Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Koh Etching Micropipes in SiC die Observed by Molten KOH Etching

L

Large-area Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Laser Ablation BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Laser Annealing NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Laser Slice Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Laser Slicing Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Laser Slicing; Crack Propagation; Kerf Loss Effects of Processing Passes on Laser-Sliced SiC

Laser Split Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Laser-induced Transient Response High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Lateral Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Lateral Device 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Lateral Straggle Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Leakage Current Degradation Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Lifetime Modeling A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages; Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Lifetime Prediction Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Light Emitter 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Light-source 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Linear Component Separation Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Low Specific On-resistance 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Low-angle Grain Boundary Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Low-resistivity Polycrystalline Layer Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Lpcvd Teos Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

M

Macrostepped Morphology DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Mcts Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Measurement Parameters DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Measurements Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Mechanical Stress Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Meniscus Solution Growth Technique of Silicon Carbide with In Situ Observation

Merged Pn Schottky Diode Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Metal-oxide-semiconductor (mos) Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Mev Implantation Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Micro Photoluminescence Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Micropipe Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Micropipes Micropipes in SiC die Observed by Molten KOH Etching

Minority Carrier Lifetime Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Minority Charge Carrier Lifetime A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Mobility Modeling Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Molten Koh A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Monolithic Integration Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Mosfet Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation; A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages; Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

N

N+ Source Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Nanoindentation Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Neutron Activation Analysis (naa) Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Neutron Irradiation Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Nitrogen-vacancy Centers Design and Characterization of an ODMR System for NV-Based Quantum Sensing

No Annealing Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Non-repetitive Surge Current Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Nonequilibriums State Polytype Transitions in Silicon Carbide: A Macroscopic View

Not Logic Gate Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K

Npn Bjt Activation Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Numerical Simulation Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

O

Obic (optical Beam Induced Current) Technique Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Ocd Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Offresonant Excitation 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Ohmic Contact NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

On-current Improvement 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

On-resistance Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Operational Amplifier In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Optical Applications Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Optically Detected Magnetic Resonance Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Optimization Design Space Exploration of SiC Power Module Package via Surrogate Model

Output Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Oxide Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Oxide Charge Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Oxide Thickness Distribution Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

P

P-i-n Diodes An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery

P-well Bias 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Packaging Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors; Design Space Exploration of SiC Power Module Package via Surrogate Model; Low-Inductance Packaging Design for SiC Power MOSFET Modules

Phase Transition Polytype Transitions in Silicon Carbide: A Macroscopic View

Photoconductivity Decay Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Photoelastic Measurements Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Photoluminescence Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography; Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Photoluminescence (pl) Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

Physical Vapor Growth Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Physical Vapor Transpor Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

Physical Vapor Transport (pvt) Growth Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Pits Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Pl Imaging Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Pl Mapping Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

Planar Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Planar Mosfet Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Pmosfet Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Polarization Curve Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Polishing Of Epilayers Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Polycrystalline 3c-sic Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Polytype Stability Polytype Transitions in Silicon Carbide: A Macroscopic View

Polytype Transition Polytype Transitions in Silicon Carbide: A Macroscopic View

Pore Nucleation CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Positive Charges Accumulation Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Postirradiation Electrical Characterization Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Power Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Power Cycle Failure Mode Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

Power Cycling A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages

Power Module Design Space Exploration of SiC Power Module Package via Surrogate Model; Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Power Modules Low-Inductance Packaging Design for SiC Power MOSFET Modules

Power Mosfet Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Power Semiconductor Device Concept The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Power-tfet The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Precision Grinding Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Precursors Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

Process Robustness JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Process Window Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Profilometr Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Proton Implantation Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers; Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Protons Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Q

Quantum Defects Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Quantum Technology Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

Quantum Tunneling 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

R

Radial Temperature Gradient 300 mm4H-SiC Crystal and Substrate Development

Radiation Hardness 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Radiation Resistance Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Radiation Sensing Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Reactive Ion Etching CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Recombination Lifetime A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Recovery Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Recrystallization Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

Recycling Of By-products A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Recycling Wafer Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Reflectometry Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Refractive Index Homogeneity Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Reliability Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET; A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages; Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs; Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

Remote Epitaxy Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways

Repetitive Surge Current Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Resistance Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Resistance Degradation Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Resonance Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Resurf Device 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Reutilization Process Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Reverse Recovery Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Reverse Recovery Charge Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Robustness Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

S

Sbd DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Sbd Embedded Mosfet Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Sc Failures Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Scanning Electron Microscope A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Schottky Barrier Diode A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction; Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Schottky Diode 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Secondary Ion Mass Spectrometry (sims) Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Self-organization Polytype Transitions in Silicon Carbide: A Macroscopic View

Sem Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Semi-superjunction Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Sheet Resistance Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Shockley-type Stacking Fault (ssf) Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

Short-circuit Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Short-circuit Reliability Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Short-circuit Robustness Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Si-based Materials A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

SiC Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC; Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation; Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching; In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation; A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages; Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

SiC Die Micropipes in SiC die Observed by Molten KOH Etching

SiC Mosfet Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications; Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

SiC Mosfets Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes; Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications; Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors; Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening; Low-Inductance Packaging Design for SiC Power MOSFET Modules

SiC Pin Diode Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

SiC Powders A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

SiC Trench Mosfet Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

SiC Wafer Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Sic-mosfets Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

Silicide NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Silicon Carbide Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching; Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer; Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes; Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion; 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET; Design and Characterization of an ODMR System for NV-Based Quantum Sensing; Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation; 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Silicon Carbide (sic) Ultra-Pure SiC Source Material for Optical SiC Crystal Growth; Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Silicon Carbide Epitaxy Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Silicon Vacancy 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Sims A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction; Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Simulation Analysis Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Sin 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Single Event Burn-out Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Single Event Burnout 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Single Event Burnout (seb) High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Single Event Effect 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Single-event Effect Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Sio2 Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Smim DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Solution Growth Solution Growth Technique of Silicon Carbide with In Situ Observation

Specific Contact Resistivity Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Specific On-state Resistance Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Spectroscopic Ellipsometry Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Split-gate Mosfet (sg-mosfet) Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Srh Recombination Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Ssrm DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Stacking Fault Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Stacking Faults Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Static Characteristics Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Statistical Process Control Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Strain Relief Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Stress Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Sub-threshold Regime Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Substrate Engineering Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Super-junction A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Superjunction Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Superjunction (sj) JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Surface Phonon Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Surface Roughness Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements

Surface Structuring DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Surge Current Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Surges Current Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Surrogate Model Design Space Exploration of SiC Power Module Package via Surrogate Model

Synchrotron X-ray Characterization Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Synopsis Tcad Simulations Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Synthesis Of Si And SiC A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

T

Tantalum Carbide Coating Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Tcad Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC; Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Tcad Simulation Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Tem Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Temperature Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Tfet The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Thermal Gradient Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Thermal Oxide Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Thermal Runaway Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations

Thermal Stress 300 mm4H-SiC Crystal and Substrate Development

Thermodynamics Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers; Polytype Transitions in Silicon Carbide: A Macroscopic View

Thick Epitaxial Layer Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Thick Epitaxy Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor; Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Thin Oxide Layer Measurements Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Threshold Resistivity Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Threshold Voltage Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements; Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs; Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Threshold Voltage Degradation Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Time Dependent Dielectric Breakdown (tddb) Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Time-dependent Dielectric Breakdown (tddb) Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

Time-resolved Ebic A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Tlm Test Structure Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Total Ionizing Dose (tid) Effect Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Total Thickness Variation (ttv) Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Trace Impurities Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Transconductance Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Transfer Length Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Transparent Wafers Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Trench Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation; Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Trench Mosfet Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Trench Refill Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Trench SiC Mosfets Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Trench Sidewall Capacitance Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Trench Umosfet Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Triple Sense Method Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Tunneling Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Tunneling Enhanced Emission 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Tunneling Transistor The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics

Two-photon Absorption High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

U

Ultra Thick Epitaxy Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Ultra-high Purity Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Ultra-high-voltage Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Ultraviolet Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Uv Irradiation Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers

V

Vertical Oxidation Furnace Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Virtual Reactor Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

W

Wafer Dicing BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Wafer Thinning Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Wafer Warpage Analysis Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Water Jet Guided Laser BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Wet Etching Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Wet Processing Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Wide Bandgap Semiconductors In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Wide-bandgap Materials Micropipes in SiC die Observed by Molten KOH Etching

Wire Bond Layout Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

X

X-ray Topography Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Y

Yield Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Authors Index

A

Abe, K. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Abe, T. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Abe, Y. Solution Growth Technique of Silicon Carbide with In Situ Observation

Adamo, S. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Agbo, N. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Akiyoshi, K. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Alaluss, M. Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Alatise, O. Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors; Low-Inductance Packaging Design for SiC Power MOSFET Modules

Alberti, A. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Albrechtvechietti, F. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Alessandrino, M. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Amamiya, T. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Amishiro, H. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Antoniou, M. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs; Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET; 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Anzalone, R. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Micropipes in SiC die Observed by Molten KOH Etching

Arena, G. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Arneberg, N. Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Asenov, A. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Azimi, H. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

B

Badalà, P. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Baier, L. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Balkas, E. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Balogh, E. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Barbisan, L. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Barkley, A. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Bartolf, H. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization

Basler, T. Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations; Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Bassi, A. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Bay, N. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Bean, A. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Becker, T. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Belanche, M. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Bellocchi, G. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Benedetto, L. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Bensouiah, D. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Bentivegna, N. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Berwian, P. A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

Binder, A. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Biswas, A. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Boccarossa, M. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Boldrini, V. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Bongiorno, C. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Borca-Tasciuc, G. An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET; Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Borghese, A. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Boscaglia, M. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Boschi, C. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Bottari, C. Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Bouch, C. Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Breglio, G. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Briggs, B. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Buompane, R. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Burk, A. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Bär, E. A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

C

Calabretta, C. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure; Micropipes in SiC die Observed by Molten KOH Etching

Calcagno, L. Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Canino, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Cannizzaro, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Cao, L. Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Cao, Q. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Carbone, B. Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Carrano, V. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Casali, N. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Chang, C. Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Chao, D. Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Charles, W. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Chavda, R. Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations; Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Che, L. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Chen, C. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer; Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Chen, D. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Chen, H. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Chen, K. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Chen, Q. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Chen, X. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Chen, Z. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals; Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

Cheng, C. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Cheng, P. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Cheng, S. Study of SiC Thyristors with Integrated Temperature Sensors

Cho, Y. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Choi, J. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Choi, S. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Chow, T. An Improved Analytical Model for SiC P-i-N Diode Reverse Recovery; Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET; Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Chu, J. Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET

Chudzik, M. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Clark, D. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Clausner, S. Dynamic HV-H 3 TRB Test on 3.3 kV SiC MOSFET Modules

Cooper, J. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Coppola, M. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Csato, C. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Cui, J. Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Cui, P. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Cui, Y. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

D

D'Arrigo, G. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Daliento, S. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Damcevska, J. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Dansako, D. Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Das, S. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements

Date, L. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Davydovskaya, K. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Dayyala, M. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

deBoer, S. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Delahaye, F. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Dick, J. The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics; Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters; 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Dikó, B. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Dimitrijev, S. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Dong, L. Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Du, Y. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Dudley, M. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Dukes, D. High Quality P-Type 4H-SiC Growth by PVT Method

Dutta, T. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

E

Engler, W. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Erlbacher, T. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC; Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation; Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Erlekampf, J. Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

F

Faisal, F. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Fan, H. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Fan, X. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Feiler, W. Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Feng, G. Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers; Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Feng, S. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Ferro, G. DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Fidler, T. Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Fink, T. Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Fiorenza, P. Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure; Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC; Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Fischer, B. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Flandre, D. Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

Flicker, J. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Floros, K. Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Floyd, R. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Fodor, B. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Fontana, E. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Formicola, A. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Franco, S. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Fu, Z. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Fuchs, A. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Furukawa, A. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Förthner, J. A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

G

Gajewski, D. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Gammon, P. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET; 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Gao, C. 300 mm4H-SiC Crystal and Substrate Development

Gay, X. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Ge, L. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Germanicus, R. DC and RF Local Electrical Properties of Macrostepped 4H-SiC Surface Probed by Scanning Spreading Resistance Microscopy and Scanning Microwave Impedance Microscopy Modes

Ghandi, R. Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Ghezellou, M. Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways; Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Gialanella, L. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Giannazzo, F. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC; Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Giuffrida, F. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Gloth, M. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Gobert, C. Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications; Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Goller, M. Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Gott, J. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Grazzi, C. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine; Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Greco, G. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Greulich-Weber, S. Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Grossner, U. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Gruber, C. A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Guo, Y. 300 mm4H-SiC Crystal and Substrate Development

H

Haasmann, D. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Hallén, A. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Halmer, D. Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Hamano, K. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Hamid, R. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Han, J. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Han, W. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Hanf, M. Dynamic HV-H 3 TRB Test on 3.3 kV SiC MOSFET Modules

Hao, X. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Harada, S. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates; Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

He, Z. Demonstration of Integrated 3.3kV 4H-SiC Bidirectional Conventional DMOSFETs at Cryogenic Temperatures

Higashi, Y. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Hinojosa, M. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Hirano, S. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Hirose, R. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Hitchcock, C. Anomalous Reverse Recovery of Body Diode in 4H-SiC Superjunction DMOSFET

Hoffmann, F. A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages

Holt, J. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Hou, T. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Hrunski, F. Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Hsiao, Y. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Hu, B. Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Hu, H. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density; Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Hu, S. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Hu, X. Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Huang, A. Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Huang, F. Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers; Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Huang, S. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Hull, B. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Hung, C. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Huo, D. Study of SiC Thyristors with Integrated Temperature Sensors

Häublein, V. Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

I

Iannuzzo, F. Low-Inductance Packaging Design for SiC Power MOSFET Modules

Iden, S. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Igarashi, Y. Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers; Quantitative Analysis of Excess Minority Carrier Density and Critical Duration in UV Irradiation-Based Screening for Bipolar Degradation in 4H-SiC

Ilves, K. Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Iosifidis, N. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Irace, A. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Ishibashi, H. Solution Growth Technique of Silicon Carbide with In Situ Observation

Ishikawa, S. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Ivanova, T. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Iwanaga, K. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

J

Jadav, S. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Jahdi, S. Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors; Low-Inductance Packaging Design for SiC Power MOSFET Modules

Jain, S. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Jang, J. Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Jang, S. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Jang, Y. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Jank, M. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Jayaprakash, H. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Jia, R. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Jia, Y. Effects of Processing Passes on Laser-Sliced SiC

Jiang, H. Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation; Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Jiang, M. Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Jiang, Y. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Johar, M. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Johnson, S. Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Jr, A. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Jørgensen, A. Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

K

Kagawa, Y. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET; Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs; Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Kakushima, K. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Kallfass, I. Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Kallinger, B. Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications; Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay; Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC; Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements; Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters; Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Kalliomaki, J. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Kaminski, N. A Multi-Manufacturer Test Campaign to Assess the Power Cycling Capability of Silicon Carbide MOSFETs in TO-247 Packages; Dynamic HV-H 3 TRB Test on 3.3 kV SiC MOSFET Modules

Kamisawa, A. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Kammel, R. Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters

Kang, J. Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers; Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Kaplar, R. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Karhu, R. Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications; Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Karim, T. Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Kauth, J. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Kawabe, A. Solution Growth Technique of Silicon Carbide with In Situ Observation

Keaton, G. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Kelmendi, D. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Kilchytska, V. Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

Kim, H. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Kim, J. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal; A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices; Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Kim, S. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Kim, Y. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices; Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Kishigami, H. Temperature Dependence of the AC-BTI in SiC MOSFETs

Kiss, Z. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Kiyoi, A. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Knoll, L. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Knolle, W. Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Kobayashi, M. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Koch, D. Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Kojima, J. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Kojima, K. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Konstantinov, A. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Koo, S. Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Kotagama, V. Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET; 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Kozlovski, V. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Kranert, C. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Krippendorf, F. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Ku, K. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Kuball, M. Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Kuehnlein, H. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Kuo, H. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration; Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Kurashige, K. Solution Growth Technique of Silicon Carbide with In Situ Observation

Kuroi, T. Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Kuroiwa, T. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Kuroki, S. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Kurtash, V. Polytype Transitions in Silicon Carbide: A Macroscopic View

Kusolitsch, M. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Kyun, M. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Köhler, J. Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

Kölbel, N. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

Körfer, J. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry; Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

L

Laborie, L. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Lai, W. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Laubenstein, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Lebedev, A. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Lee, B. Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

Lee, C. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal; Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Lee, D. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Lee, H. Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Lee, K. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET; Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Lee, W. Optimization of Seed Crystal Stability at the Initial Growth Stage Depending on Heating Ramp Rates and Gas Flow Channels of SiC Source Powder for Growth of 8-inch n-Type 4H-SiC Single Crystal

Lee, Y. Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Lelis, A. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes

Levinstein, M. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Ley, M. Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC

Li, B. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Li, C. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric; Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Li, J. Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers; Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Li, R. Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

Li, W. Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Li, Y. 300 mm4H-SiC Crystal and Substrate Development; High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Liang, L. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Liao, P. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET; Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Licciardo, G. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Lichtenwalner, D. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements; Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET; Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Liguori, R. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Lim, J. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress; Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Lin, W. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Lin, X. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Liu, S. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Liu, X. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Liu, Y. Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals; Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors

Lombardo, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Lu, T. Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Luca, S. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Ludtke, I. Impact of Packaging on Discrepancy of Datasheet Static Measurements of SiC Power MOSFETs in Bare Dies and TO-247 Packaged Form-Factors

Luo, L. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Luo, X. Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Lutz, J. Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations; Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Lynch, D. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Lynch, J. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes; High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

M

Ma, A. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Machida, N. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Magerl, F. A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

Magna, A. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Magnusson, B. The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Mahadik, N. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Maira, G. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Maistriuk, O. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Makai, L. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Makino, T. High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena; In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Malevsky, D. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Manchineni, H. Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Mancini, S. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes; High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction; Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Mancuso, A. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Maresca, L. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Masui, S. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Matacena, I. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Matsumura, Y. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Matsuoka, M. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Matsushita, Y. Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers; Quantitative Analysis of Excess Minority Carrier Density and Critical Duration in UV Irradiation-Based Screening for Bipolar Degradation in 4H-SiC

Mawby, P. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

May, A. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K; Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters; Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Megalini, L. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Melnyk, K. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

Metreveli, A. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Michałowski, P. Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters

Mikolajick, T. Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Misra, V. Threshold Voltage Control in 4H-SiC MOS Devices by Atomic Layer Deposited Al2O3/SiO2 Interface Dipole Engineering

Mitsou, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Miyaoka, S. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Miyazaki, K. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs; Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Morgan, A. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Morisette, D. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Morita, I. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Morita, T. Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers; Quantitative Analysis of Excess Minority Carrier Density and Critical Duration in UV Irradiation-Based Screening for Bipolar Degradation in 4H-SiC

Mudiyanselage, D. Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs

Muhammad, S. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Mulpuri, V. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Munk-Nielsen, S. Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

Muoio, A. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Murphy, J. Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Myalitsin, A. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Mysore, M. Impact of the Negative Gate Bias on Short-Circuit Robustness of SiC MOSFETs with Measurements and Simulations; Understanding the Influence of Different Parameters on the Dynamic VsD Behaviour of SiC MOSFETs during Power Cycling Test

Müller, S. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC

N

Nagasawa, H. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Nakanishi, H. Solution Growth Technique of Silicon Carbide with In Situ Observation

Nakayama, K. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Nania, C. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Micropipes in SiC die Observed by Molten KOH Etching

Narita, S. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Naureen, S. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Nebesnyi, V. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Neitzert, H. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Neubert, F. Polytype Transitions in Silicon Carbide: A Macroscopic View

Nigro, R. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Nikolaev, A. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Ning, X. 300 mm4H-SiC Crystal and Substrate Development

Nishizawa, S. Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

Nitta, T. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs; Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Niwa, H. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Nufer, S. Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

O

Ohba, T. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Ohshima, T. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Ohtani, N. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Okamoto, M. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Oki, T. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Onda, S. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Ortiz-Gonzalez, J. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Osada, J. Solution Growth Technique of Silicon Carbide with In Situ Observation

Oshiyama, A. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

P

Palisaitis, J. Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways

Pan, Y. 300 mm4H-SiC Crystal and Substrate Development

Panasci, S. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Pang, A. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Pap, Z. Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry

Parisi, P. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Park, J. Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Park, M. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Paul, R. Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

Peng, B. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Peng, H. 300 mm4H-SiC Crystal and Substrate Development

Peng, Y. Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Per, J. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Perazzi, M. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Peters, J. Dynamic HV-H 3 TRB Test on 3.3 kV SiC MOSFET Modules

Pezoldt, J. Polytype Transitions in Silicon Carbide: A Macroscopic View

Pfusterschmied, G. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Philpott, R. Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Pieruccini, M. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Piluso, N. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure; Micropipes in SiC die Observed by Molten KOH Etching

Pixius, C. A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

Pobegen, G. A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Q

Qi, Y. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Qian, W. Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers; Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

R

Rabbi, S. High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction

Rabinzohn, P. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Raciti, D. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Micropipes in SiC die Observed by Molten KOH Etching

Raghothamachar, B. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Ramadoss, K. Enhanced Mobility in SiC (0001) MOSFETs Using a Decoupled Plasma Nitridation (DPN) Process and Oxide Deposition

Rana, T. Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Rascunà, S. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Rathi, S. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Rathnakar, A. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Rawat, T. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Reigosa, P. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Remy, J. Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Renz, A. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

Reshanov, S. Gate Leakage Imaging of Silicon Carbide Power MOSFETs under Negative-Bias Gate Stress

Riccio, M. Investigation of SiC MOSFETs Gate Capacitance Peak with Biased Drain and its Relation with Transconductance

Richter, J. Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Rinaldi, N. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Ripamonti, N. Design Space Exploration of SiC Power Module Package via Surrogate Model

Roccaforte, F. Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure; Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC; Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Rommel, M. Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay; Challenges in Measuring Thin SiO 2 Layers on 4H-SiC via Spectroscopic Ellipsometry; Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements; Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K; The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics; Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters; Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies; 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Rossitto, A. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Rubino, A. Effects of 673K Temperature Anneal on a 4H-SiC CMOS NOT Logic Gate; 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime; Experimental Analysis of 4H-SiC CMOS NOT Logic Gate Down to 100K; Characterization of 4H-SiC Lateral MOSFETs Up to 773 K

Rueb, M. Characterization of Deep Levels Introduced by Energy Filtered Ion Implantation with DLTS and MCTS in 4H-SiC

Rusch, O. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

Russo, A. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure

Ryu, S. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements; Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET; Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

S

Sabri, S. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Saito, W. Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

Sakharov, A. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Sakuraba, M. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Salamone, M. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Salemi, A. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Samperi, O. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Sanchez, E. Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Sangregorio, E. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Sano, M. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Sano, Y. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Santonastaso, C. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Sanzaro, S. NiSi Alloy/4H-SiC Reaction and Silicide Formation under Excimer Laser Annealing for Ohmic Contact

Sato, S. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Sato, T. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Schaaff, F. Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Schilirò, E. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Schley, M. Ultra-Pure SiC Source Material for Optical SiC Crystal Growth

Schmid, F. Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Schmid, P. Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Schmid, U. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Schmidt, K. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Schneider, N. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Schneider, O. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Schnitzler, R. Peak Voltage and Switching Slope Dependency of Gate Switching Instability in SiC MOSFET

Scholten, D. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization; Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Schröder, A. Design Space Exploration of SiC Power Module Package via Surrogate Model

Schulze, J. Process-Dependent Photoluminescence Behavior Evolution of Stacking Faults in 4H-SiC; High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization; Influence of Different Contact Lengths on the Correct Extraction of the Resistance Parameters of TLM Test Structures on 4H-SiC; The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics; Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters; Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies; 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications; A Simulation Study of Electronic Device Designs for the Control of SiC Color Centers as Spin Qubits

Schunemann, P. Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

Schwarberg, J. The Tunneling Field-Effect Transistor as Novel Device Concept for High-Frequency Hard-Switching Power Electronics; Towards a Fully Integrated 4H-SiC a-Plane Quantum-Chip Transistors and Light Emitters; Scalable Fabrication and Electrical Characterization of Lateral pin-Diodes on 4H-SiC a-Plane Wafers for Functionalization of Silicon Vacancies

Setoya, T. Temperature Dependence of the AC-BTI in SiC MOSFETs

Severino, A. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure; Micropipes in SiC die Observed by Molten KOH Etching

Sezaki, H. Analysis of Backside Metal Contact Resistance on Low-Resistivity Polycrystalline in 4H-SiC-Bonded Substrates

Shah, V. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching; Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET; Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET

Shao, H. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Shao, Y. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Sharma, P. Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices

Shi, D. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Shimbori, A. Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Shiraishi, K. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Shoen, L. Design and Characterization of an ODMR System for NV-Based Quantum Sensing

Shu, J. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Singh, K. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Smoliner, J. A Frequency-EBIC Technique for High Spatial Resolution of the Effective Minority Charge Carrier Lifetime in SiC PN-Junctions

Soda, D. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Soleimanzadeh, R. Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs; Design Space Exploration of SiC Power Module Package via Surrogate Model

Solonitsyn, N. Comparison of the Irradiation Temperature Effect of on the Carrier Removal Rates in GaN and SiC

Song, K. Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Song, Q. Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Song, X. Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration

Song, Z. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Soukhojak, A. Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Souzis, A. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Stahlbush, R. Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices

Stark, B. Low-Inductance Packaging Design for SiC Power MOSFET Modules

Stark, R. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Stecconi, T. 1.2 kV SiC MOSFET with Reduced Dynamic Losses Enabled by SiN Gate Dielectric

Stein, S. Study of Interface Traps and Scattering Mechanisms in the 4H-SiC MOS Channel Using Gated Hall Measurements; Insight into Bias-Temperature Instability of SiC MOSFETs Using Charge Pumping and Triple-Sense Threshold Measurements; Investigation of the P-Body Effect on Reverse Recovery and Static Characteristics of 1.2 kV4H−SiC Power MOSFET

Straub, T. Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Strüber, S. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine; Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Subramanian, S. Silicon Carbide Epitaxial Defects and Substrate Defects Analysis by Dynamic Photoluminescence and X-Ray Topography

Suemitsu, M. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Sugawara, K. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Sun, L. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Sun, W. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Sun, Y. Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Sun, Z. Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

Sundaresan, S. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Sung, W. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM); Effect of Varying 𝐍+ Source Implantation Depth on the Electrical Characteristics of 1.2 kV 4H-SiC MOSFETs; Impact of Active Cell Geometry on the Static Performance of 10−kV 4H-SiC JBS (Junction Barrier Schottky) Diodes; High-Voltage Performance Evaluation of 6.5 kV 4H-SiC JBSFET Architectures and MOSFET with Enhanced 3rd  Quadrant Conduction; Comparative Study of 1.2kV 4H-SiC Bi-Directional MOSFET (BiD-MOS) Design Approaches: 2-Chip vs Monolithic Integration; Design Optimization of 600V 4H-SiC Lateral Bi-Directional MOSFET (L-BiD-MOSFET) with 3D TCAD Simulation

Szabo, M. Extraction of Trench Sidewall Capacitance by Linear Component Separation towards Wafer Level Evaluation

Söderlund, M. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

Sütő, A. Optical Critical Dimension Metrology for the SiC Trench MOSFET Process

T

Takahashi, M. Power Cycle Failure Modes of 10 kV SiC−MOSFET Power Modules with Different Wire Bond Layouts

Takahashi, S. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics; BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Takano, K. Proton Implantation-Induced Reduction of SSF Width and Associated Adverse Effects in 4H-SiC Epitaxial Layers; Trial Implementation of Operando PL Spectrum Mapping Using a Mini-Spectrometer in EVC Screening of 4H-SiC Wafers; Quantitative Analysis of Excess Minority Carrier Density and Critical Duration in UV Irradiation-Based Screening for Bipolar Degradation in 4H-SiC

Takei, K. Temperature Dependence of the AC-BTI in SiC MOSFETs

Takenaka, K. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Takeyama, A. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Talesara, V. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Tana, L. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Tanaka, T. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET; Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Tanaka, Y. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Tang, X. Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Tani, S. Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

Tanioka, T. Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs; Design of the Robust Edge Termination Applied to 4.5 kV SiC SBD Embedded MOSFET against Humidity

Tanner, P. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Taoka, T. High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Tawara, T. Body Diode Reliability and Reverse Recovery Characteristics of Short Tapered SJ-MOSFET Fabricated by MeV AI Ion Implantation

Taylor, P. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Thierry-Jebali, N. Ultra-Thick (~200μ𝐦) Epitaxy on 150mm4H-SiC Wafers Using Single Wafer CVD Reactor

Thörnberg, J. The Elusive Bulk Inclusion, Sizing, Wafer- and Ingot-Level Localization and their Effect on Dislocation Generation and Epitaxial Defectivity in 4H-SiC

Tian, X. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Tian, Y. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Titl, M. Growth and Characterization of "IsoPure" Epitaxial Layers for Quantum Applications

Toh, D. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Tojima, K. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET; Carbon Vacancy Engineering on High-Temperature Annealing as a Cost-Effective Approach for Reverse Recovery Suppression in SiC-MOSFETs

Tokoro, N. Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Tomita, T. High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Torky, M. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Torres, V. High Quality P-Type 4H-SiC Growth by PVT Method

Tsai, D. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Tsai, I. Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Tsui, B. A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction; Channel Length Effects on Threshold Voltage Instability in Gamma Irradiated 4H-SiC PMOSFETs

Turchetti, S. Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals

U

Ueno, T. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Ujihara, T. Solution Growth Technique of Silicon Carbide with In Situ Observation

Ul-Hassan, J. Remote Epitaxy of SiC: Feasibility, Challenges, and Pathways; Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Ultsch, S. 4H-SiC Tunneling Light Emitter as a Light-Source for Quantum Applications

Umezawa, H. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Urakami, M. Numerical Simulation of Optimal Source Temperature Distribution in PVT Method for SiC Single Crystals

V

Vento, F. Epitaxial Growth and Characterization of 4𝐇-SiC Layer on C-Face and Si-Face Substrates; Advanced Defects Study and Monitoring in New Generation 4H-SiC Devices; Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis; Challenges in 1SSF Detection in 4H-SiC Epilayer and Related Failure; Micropipes in SiC die Observed by Molten KOH Etching

Via, F. Characterization of the Electric Field in Silicon Carbide Detectors by Optical Beam Induced Current

Vines, L. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers

Vitanza, E. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Vivona, M. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Votadoro, V. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC

Vozny, A. Demonstration of ALD SiO2 as Gate Oxide in the 1.7 kV SiC UMOSFET for High-Power and Embedded CMOS Circuit Integration

W

Wachowiak, A. Impact of ALD Oxidant and Deposition Temperature on Electrical Characteristics of Al2O3/SiO2/SiC MOS-Capacitors

Wada, R. Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Wagner, T. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Wan, L. Design Space Exploration of SiC Power Module Package via Surrogate Model

Wan, Y. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Wang, G. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Wang, H. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Wang, J. Effects of Processing Passes on Laser-Sliced SiC

Wang, R. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Wang, W. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Wang, X. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET; Study of SiC Thyristors with Integrated Temperature Sensors

Wang, Y. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Wang, Z. Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs

Watahiki, T. Investigation on Bipolar Degradation Caused by In-Grown Stacking Fault in 3.3 kV SiC-MOSFET

Watanabe, H. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Watanabe, S. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Watanabe, Y. Characterization of AI-Gate MOS Capacitor on Thermally Oxidized 3C/4H Hybrid Polytype-Heterostructure Si-Face SiC(0001) Wafer Fabricated by Simultaneous Lateral Epitaxy (SLE) Method

Wei, J. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Wei, K. Cumulative Threshold Voltage Shift Induced by Surge Current in Planar SiC MOSFETs after Bipolar Gate Switching Stress

Weigt, B. Dynamic Conduction Behavior of SiC-MOSFETs in the Sub-Threshold Regime and the Impact of Deep Oxide Traps to the Channel Depletion

Wellmann, P. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine; Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals

Wen, Y. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs

Whear, O. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Widjaja, Y. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Wiedemann, J. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

Wilson, M. Evaluation of Oxide Processing Steps in SiC Technology Using Contactless Corona-Based CV Measurements

Wirths, S. Gate Oxide Stability and Degradation Modes of Next Generation SiC MOSFETs

Wißgott, C. Minority Charge Carrier Lifetime for Evaluating 4H-SiC Epitaxial Growth by Microwave Detected Photoconductivity Decay

Wong, H. Depth-Dependent Suppression of Bipolar Degradation in 4H-SiC Diodes via Proton Implantation and Evaluation of Safe Operating Current Density Range

Woods, C. Enhanced Gate Oxide Reliability in Vertical SiC Power MOSFETs via Optimized Processing and Screening

Wu, C. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Wu, D. Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography

Wu, G. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Wu, J. Effects of Dynamic Reverse Bias Stress on the Blocking Capability of SiC MOSFETs; Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Wu, Q. Investigation of Mechanical Stress and Warpage in 200 mm Silicon Carbide Wafers: Implications for Production Scalability

Wu, R. Short-Circuit Reliability Analysis of SG-MOSFETs Versus Planar 4H-SiC MOSFETs; Influence of Cell Structure and Topology on Coss  of 4H-SiC MOSFET; Degradation Mechanisms of 1200 V 4H-SiC Planar Power MOSFET under Negative HTGB Stress

Wu, T. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Wu, Y. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density; A Study on Simplifying the Process of a Single Cycle for Multiple Epitaxy and Implantation Method to Fabricate SiC Super Junction

Wunder, P. Close Space PVT Growth of N- and P-Type Quasi-Bulk SiC in a Classic PVT Setup and a Newly Developed TableTopCS TM  Growth Machine

X

Xeni, N. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Xie, X. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Xu, M. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Xu, S. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Xu, X. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography; Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Xue, Y. Effects of Processing Passes on Laser-Sliced SiC

Y

Yadav, R. 4H-SiC Diodes to Probe Stark Effect Detection in 7Be Decay Lifetime

Yamada, J. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Yamamoto, M. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Yamamura, K. High-Bandwidth Measurement of Laser-Induced Transient Responses in SiC Devices for Understanding Single Event Burnout Phenomena

Yang, D. Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Yang, T. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Yang, X. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates; Investigation of Micropipe Defects and Their Strain Field Distortions in SiC Substrates Using X-Ray Topography

Yang, Y. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Yeon, K. Development and Evaluation of a 1.2kV SiC MOSFET-Based PTC Controller for Energy-Efficient xEV Heating Applications

Yildirim, M. Body Diode Performance of the 4H-SiC 3.3 kV Semi-SJ MOSFET

Yildirm, M. Preliminary Study into Ferroelectric Properties of ALD AI-Doped HfO2/SiO2/4H-SiC MOS Capacitors for Improved Short Circuit Reliability

Ying, P. Resonance Damping Optimization in 1200V Power Modules with Planar SiC MOSFET Devices for 200 kW Output

Yoda, T. Exploring the Ion Implantation Mechanism for Suppressing Stacking Fault Expansion in 4H-SiC: A Fundamental Approach

Young, R. 2x Current Boosting Scheme in 3300 V 4H-SiC VDMOSFET

Yu, G. Influence of Temperature Field and Doping on BPD Distribution in 8-Inch 4H-SiC Substrates

Yu, J. Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Yu, M. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs

Yu, R. Low-Inductance Packaging Design for SiC Power MOSFET Modules

Yu, W. Electrical Performance of 4H-SiC MOSFETs with Different Gate Oxide Processes

Yu, Y. Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias

Yuan, B. Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Yuan, H. Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation

Yuan, L. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Yuan, Z. Investigating the Temperature Dependence of Charge Carrier Lifetime in Low-Doped Epitaxial 4H-SiC Layers; Isolation of Cumulative Heavy-Ion Induced Trench Degradation Effects within a Commercial 4H-SiC Double Trench MOSFET; 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Yun, N. Edge Termination Design for Ultra High-Voltage (>10 kV) 4H-SiC Power Devices Using Background Doping Modulation (BDM)

Yuzuriha, M. In-Situ Measurement of the Gain Stage of a SiC JFET Operational Amplifier under Gamma Ray Irradiation

Z

Zappalà, S. Unveiling the Role of Crystallographic Defects in SiC Device Reliability with Multi Modal Structural Analysis

Zellner, C. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Zeng, F. Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes

Zhang, B. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Zhang, C. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Zhang, F. Growth of 8-Inch SiC Single Crystals with Low Basal Plane Dislocation Density

Zhang, J. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method; Synchrotron X-Ray Topography Analysis of Low Angle Grain Boundaries Induced by Growth Step Flow in PVT-Grown 4H-SiC Crystals; Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Zhang, K. High Quality P-Type 4H-SiC Growth by PVT Method; Observation and Analysis of the "Galaxy" Defect in 4H-SiC Through X-Ray Synchrotron Topography; Growth and Characterization of High-Quality Thick Epitaxial 4H-SiC Wafers for High Voltage Devices; Investigation of Spoke Pattern of Stacking Faults in 4H-SiC Wafers Grown by Physical Vapor Transport Method

Zhang, X. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Zhang, Y. Impact of Device Structure on the Performance of Ion-Implanted SiC Phototransistors; JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors

Zhang, Z. JTE-Based Termination Design and Technology Considerations for 1500V VH-SiC Superjunction MOSFETs; Study of SiC Thyristors with Integrated Temperature Sensors; Experimental Investigation of Single-Event Effect Mechanisms in 1200V SiC VDMOSFETs under Heavy-Ion Irradiation; Investigation on the Resistance Degradation of Trench SiC MOSFETs under Total lonizing Dose Irradiation and High Drain Voltage Bias; Low-Inductance Packaging Design for SiC Power MOSFET Modules

Zhao, J. Development of High Concentration Uniformity Epitaxial Growth on 200 mm 4H−SiC Wafers; Formation Mechanism and Reduction of Surface Pits on 4H-SiC Epitaxial Layer

Zhao, Q. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters

Zhao, Y. Design Space Exploration of SiC Power Module Package via Surrogate Model

Zhao, Z. Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Zheng, S. Enhanced Breakdown Voltage and Enlarged Process Window for Junction Termination Extension in SiC Power Devices Using Hybrid Random and Channeling Implantation

Zhi, H. Study of Single-Event-Burnout for Refilled-PMOS SiC Trench MOSFET

Zhong, K. Benchmark Study of State-of-the-Art Commercial 1200V SiC MOSFETs for Automotive Applications

Zhong, Y. DLTS Analysis of Deep Levels in 4H-SiC Schottky Barrier Diode under Different Measurement Parameters; Application of a New Method and Criterion for Analyzing Repetitive Surge Current in Commercial SiC Schottky Diodes; Characteristics of High Current 4H-SiC Schottky Barrier Diodes

Zhou, B. 1200 V Lateral SiC Schottky Diode Radiation Hardness Enhancement

Zhou, P. Characterizations of 4H−SiC/SiO2 Interface by High-Temperature 𝐍2/𝐇2 Pretreatment

Zhou, Y. 300 mm4H-SiC Crystal and Substrate Development

Zhu, J. Reliability Challenges of SiC MOSFETs under Continuous Dual-Bias Stress in EV Applications

Ziegler, J. High-Temperature 𝐇2 - and 𝐍2-Containing Surface Conditioning for SiO2/4H-SiC Interface Optimization; Fowler-Nordheim Current at Negative Gate Bias in SiC MOSFETs

Zignale, M. Electrical Characterization of Mo-Carbide Schottky Contacts on 4H-SiC; Calculation of the Whole Interface State Density Profile in SiO2/SiC Lateral MOSFETs

Zong, Y. 300 mm4H-SiC Crystal and Substrate Development

Zöcklein, J. Application of a Fine Grain 3C-SiC Powder Source Material during PVT Growth of 4H-SiC Crystals