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ISBN print: 978-3-0364-2128-5
ISBN eBook: 978-3-0364-3128-4
DOI book: 10.4028/b-P3Il2A
© 2026 Trans Tech Publications Ltd, All Rights Reserved

Wafer Processing

Edited by
Sang Mo Koo
Hoon Kyu Shin

Wafer Processing

Special topic volume with invited peer-reviewed papers only

Edited by

Sang Mo Koo and Hoon Kyu Shin

Scientific.Net

Copyright © 2026 Trans Tech Publications Ltd, Switzerland

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Volume 1193 of
Materials Science Forum
ISSN print 0255-5476
ISSN web 1662-9752

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp -1-0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Accepted:
2026-05-19

Online:
2026-05-21

Preface

The original version of this paper is available on https://www.scientific.net/MSF.1193.-1.pdf

Silicon carbide ( SiC ) is one of the most strategically important semiconductor materials for modern power electronics, owing to its unique properties that enable highly efficient devices for electric vehicles, renewable energy systems, industrial power conversion, and aerospace applications. But at the same time, the exceptional hardness and brittleness of SiC present significant challenges in substrate preparation and wafer processing, where achieving high accuracy and minimal surface damage is essential for device performance and manufacturing yield.

This special edition focuses on scientific principles and the technologies that underpin the preparation and processing of SiC wafers. The technological operations involved in transforming a bulk SiC crystal into a device-ready substrate, including laser slicing, precision grinding, fixedabrasive lapping, plasma chemical vaporisation machining, and wafer dicing, are described. Particular attention is given to crack propagation, thickness variation, and the generation of subsurface damage, as these factors strongly influence wafer flatness, structural integrity, and subsequent epitaxial growth.

The defect-related phenomena, such as basal plane dislocations and their interactions with mechanical and thermal processing steps, are also examined. Surface conditioning and material removal techniques, including wet etching, electrochemical etching, and high-temperature oxidation in vertical furnaces are also presented.

Emerging approaches to wafer recycling and water-jet-guided laser processing are discussed as innovative strategies to reduce material loss and enhance manufacturing efficiency.

We hope that the information presented in this edition will contribute to continued advances in SiC substrate manufacturing and support the development of the next generation of high-performance electronic devices.

Table of Contents

Preface

Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Bi Xue Li, Xing Zhang, Qiu Chen, Lin Lin Che, Jian Fei Zhang, Hao Yu Fan, Xian Gang Xu, Rong Kun Wang, Xiu Fang Chen

Effects of Processing Passes on Laser-Sliced SiC

Jian Fei Zhang, Bi Xue Li, Qiu Chen, Lin Lin Che, Xing Zhang, Hao Yu Fan, Yang Yang Jia, Jia Wei Wang, Yu Feng Xue, Rong Kun Wang, Xiu Fang Chen

Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Takanori Tanaka, Kyohei Akiyoshi, Kazumasa Iwanaga, Shunta Takahashi, Hiroshi Watanabe, Kenichi Hamano, Akihiko Furukawa

Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Kyohei Akiyoshi, Takanori Tanaka, Shunta Takahashi, Kazumasa Iwanaga, Kenichi Hamano, Akihiko Furukawa

A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Myung Beom Park, Jungwon Kim, Yigil Cho, Yun Ho Kim, Sam Jong Choi

Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Yuken Matsumura, Shunto Iden, Daisetsu Toh, Jumpei Yamada, Yasuhisa Sano

Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

David M. Lynch, Gregory L. Keaton, Christopher A. Lee, Alexander T. Bean

Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Tamara Fidler, Patrick Schmid

Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Norbert Bay, Athul Rathnakar, Xavier Gay, Wyatt Engler, Rahim Hamid, Franck Delahaye, Oliver Whear, Vishal A. Shah, Holger Kuehnlein

CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Georg Pfusterschmied, Michael Kusolitsch, Christopher Zellner, Marco Perazzi, Ting Qiang Yang, Ulrich Schmid

BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Shunya Hirano, Hyuk Kim, Satoru Takahashi, Shuzo Masui, Noboru Ohtani, Kozo Abe

Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Chen Hang Wu, Chao Jun Zhang, Shao Yuan Huang, Chao Chang Arthur Chen

Keywords Index

Authors Index

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 1-7

doi: 10.4028/p-Xc7FbW

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-09

Revised:
2025-12-20

Accepted:
2026-02-26

Online:
2026-05-21

Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Bixue Li 1,a, Xing Zhang 1, b, Qiu Chen 1,c, Linlin Che 1, d, Jianfei Zhang 1,e, Haoyu Fan 1,f, Xiangang Xu 1, g, Rongkun Wang 1, h*, Xiufang Chen 1,i*

1 State Key Laboratory of Crystal Materials, Institute of Novel Semiconductors, Shandong University, Jinan 250100, China

alibx@mail.sdu.edu.cn, b17731872242 @163.com, c chenqiu0629@sdu.edu.cn, d 202214075@ mail.sdu.edu.cn, e  zjf2531@163.com, f  fanhaoyu2001@163.com, g  xxu@sdu.edu.cn, h wrk@sdu.edu.cn, i cxf@sdu.edu.cn

Keywords: laser slicing, nanoindentation, precision grinding, silicon carbide.

Abstract

With the growing application of wide-bandgap semiconductors such as SiC in power electronics, efficient and low-damage machining of large-diameter, high-quality 4H−SiC wafers has become a critical research priority. This study systematically compares the grinding behavior of the C - and Si-faces of laser-sliced 4H−SiC wafers and reveals the effect of crystallographic anisotropy on tool wear. In the experiments, a picosecond laser was used to induce internal crystal modification, and multiple pairs of 12-inch high-purity semi-insulating crystals and wafers were obtained through ultrasonic separation. These wafers were subsequently ground using #800/#8000 resin-bonded diamond wheels. Material removal and wheel wear were recorded in real time, and the wheel wear ratio (W/M) was adopted as the key evaluation metric. Nanoindentation and white-light interferometry were further employed to characterize the mechanical properties and surface morphology of the two crystal faces. Results show that in both rough and fine grinding, the C-face demonstrates superior material removal performance despite its higher hardness, whereas the Si-face is more prone to wheel degradation. For thin wafers, residual laser focus near the surface further aggravates wheel wear. These findings establish a link between crystallographic anisotropy, laser-modified layer position, and wheel wear behavior, providing an experimental foundation for clarifying the underlying mechanisms and developing face-specific grinding strategies for high-quality SiC wafer fabrication.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

With the rapid development of next-generation power electronics, wide-bandgap semiconductors such as silicon carbide (SiC) have become essential materials for high-performance devices, enabling applications in electric vehicles, renewable energy systems, 5G communications, and aerospace electronics. Among them, 4H−SiC stands out due to its wide bandgap, high critical electric field, superior thermal conductivity, and excellent chemical stability. These properties offer significant advantages under high-power, high-frequency, and high-temperature conditions, positioning 4H−SiC as a promising alternative to conventional silicon-based devices. Consequently, the demand for high-quality, large-diameter SiC wafers has grown rapidly, highlighting the need for efficient and low-damage processing technologies.

Although diamond wire sawing is widely used for SiC wafer preparation, it suffers from excessive kerf loss and low processing efficiency, which increase costs and limit wafer quality [1]. In contrast, laser-induced modification and slicing technologies enable high-precision wafer separation by inducing localized modifications within the crystal through nonlinear absorption [2−7]. Nevertheless, laser-sliced wafers often exhibit kerf marks and heat-affected zones, necessitating subsequent precision grinding. By integrating these two processes, laser slicing not only significantly reduces material loss but also enables low-damage wafer preparation while maintaining high processing efficiency.

However, grinding, as a necessary process for removing the surface damage layer after laser slicing, still faces challenges. The anisotropy of 4H−SiC leads to significant differences in
mechanical responses under different crystallographic orientations. The carbon end ( C -face) and the silicon end (Si-face) differ in hardness, elastic modulus and fracture toughness, which directly affect crack initiation, plastic deformation, dislocation structures and material removal mechanisms. In recent years, several scholars have investigated the material removal mechanisms of 4H−SiC with different orientations [8−10]. Other studies have also reported that crystal orientation influences the wear and micro-chipping of diamond tools. However, these studies have mostly focused on nanoscale or small-scale simulations, and lacks systematic investigations of wafer-scale grinding behavior after laser slicing. At the same time, some studies have primarily focused on surface quality indicators such as roughness and subsurface damage [11], while insufficient attention has been given to the quantitative correlation between grinding wheel wear and crystal orientation. This gap constrains the development of differentiated grinding strategies.

Therefore, a comparative investigation of the grinding behavior between the C -face and Si -face of laser-sliced 4H−SiC wafers is of great importance. Such a study not only enhances the understanding of how crystallographic anisotropy influences tool wear and material removal mechanisms, but also provides an experimental foundation for optimizing face-specific grinding parameters, thereby reducing wheel wear, improving machining efficiency, and extending tool life. In this work, C -face and Si -face wafers prepared by laser slicing are systematically compared in terms of material removal thickness, grinding wheel wear ratio, and surface morphology. The objective is to elucidate face-dependent grinding mechanisms and to offer guidance for the optimized manufacturing of high-quality 4H−SiC wafers.

Experimental Methods

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Sample Preparation.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

A 12 -inch high-purity 4H−SiC single crystal was sliced using a picosecond laser operated at a wavelength of 1030 nm , a pulse width of 15 ps , and a maximum output power of 40 W . During slicing, the crystal was fixed on a five-axis precision motion platform with a ceramic vacuum chuck to ensure stability and positioning accuracy. Laser scanning was performed along a predefined trajectory perpendicular to the (112―0) crystal plane, with a scanning pitch of 200μ m. The target wafer thickness was 700±20μ m. After laser modification, ultrasonic-assisted separation was employed to detach the wafers near the incident surface from the parent crystal, yielding complete thin-sheet structures.

Grinding Experiments.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

The separated crystal-wafer pairs were ground using a grinding machine developed by the China Electronics Technology Group Corporation (CETC). Resin-bonded diamond grinding wheels (ZZSM) with grit sizes of #800 and #8000 were employed for rough and fine grinding, respectively. The overall process flow is illustrated in Figure 1. For grinding wheels of the same grit size, identical procedures were applied, with precise control of grinding depth to remove the laser-modified layer and residual slicing marks. Simultaneously, the material removal thickness and grinding wheel wear were recorded in real time, enabling direct comparison between the C-face and Si-face. To quantitatively evaluate tool degradation, the wheel wear ratio (W/M) was adopted as the primary metric, defined as the ratio of wheel wear to material removal. Both wafer removal thickness and wheel wear were automatically measured by the thinning machine with an accuracy of ±1μ m.

[picture]

Fig. 1. Schematic of laser slicing and subsequent grinding applied to 4H−SiC wafers.

Fig. 1. Schematic of laser slicing and subsequent grinding applied to 4 H − S i C wafers.

Characterization.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

To evaluate the mechanical responses and machining quality of the C -face and Si -face, a KLA nanoindentation system was employed to measure the mechanical properties of polished 4H−SiC samples ( Ra<5 nm ). A three-sided pyramidal Berkovich indenter was used in continuous stiffness measurement mode, and hardness (H) was extracted from the load-displacement curves. Surface topography and morphology were further characterized using a white-light interferometer (Sneox 090, Sensofar).

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Nanoindentation Testing.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

Multi-point nanoindentation tests were conducted on the C -face and Si -face of a high-purity 4H−SiC sample. The corresponding hardness-displacement into surface curves are presented in Figure 2. As shown, the hardness exhibits a rapid increase during the initial loading stage ( 0−50 nm ), primarily due to surface roughness and residual surface stress [12]. With further indentation (approximately 100−200 nm ), the curves gradually stabilize and enter a plateau region. Statistical analysis within the stable range ( 300−350 nm ) indicates that the average hardness of the C -face is approximately 44.21±0.68GPa, whereas that of the Si-face is approximately 41.34±0.91GPa. These values are consistent with the theoretical hardness of 4H−SiC reported in the literature [13]. A direct comparison confirms that the C -face exhibits higher hardness than the Si -face.

[picture]

Fig. 2. Hardness measurement results: (a) Hardness of the C-face; (b) Hardness of the Si-face.

Fig. 2. Hardness measurement results: (a) Hardness of the C-face; (b) Hardness of the Si-face.

Effect of Crystal Plane Orientation on Wheel Wear Ratio.

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

During the rough grinding stage, distinct laser modification marks were observed on both the Cand Si-faces. After rough grinding, both faces gradually transitioned to flat regions, and by the completion of fine grinding, they exhibited uniform and smooth morphologies. Figure 3 presents the surface morphology evolution of the Si -face of a 4H−SiC wafer at different processing stages. Given the similar morphological evolution trends observed on both crystal faces, the Si-face is selected as a representative example to illustrate the typical surface morphology changes of laser-sliced wafers during rough and fine grinding.

As shown in Figure 4, under grinding wheels with different grit sizes, the wheel wear ratio of the C-face was consistently lower than that of the Si-face in both the rough and fine grinding stages, indicating that the Si-face is more susceptible to wheel degradation during grinding. Previous studies have also reported that although the C-face exhibits higher hardness and lower fracture toughness, its higher dislocation density facilitates stress release, thereby resulting in more favorable material removal behavior. In contrast, although the Si-face exhibits a slightly lower hardness than the C-face, its crystallographic orientation may to some extent restrict dislocation activity and weaken stress relaxation through dislocation slip during grinding, thereby promoting local stress accumulation and intermittent brittle removal events [10]. This relatively single-dominant removal mechanism lacks the buffering effect of cooperative deformation modes, causing diamond abrasives and the bond to be continuously subjected to high local mechanical loading and frictional work. As a result, grit micro-crack propagation and bond degradation are accelerated, ultimately leading to an increased wheel wear ratio.

A further comparison between the rough and fine grinding stages reveals that the difference in wear ratio between the two faces is much greater during rough grinding than during fine grinding. This phenomenon arises not only from differences in crystal surface hardness but is also closely
related to the focal position in the laser slicing process. For laser sliced wafers, the laser focus typically resides near the upper wafer surface (Figure 5), making the Si-face more susceptible to grinding-induced wheel wear in subsequent processes, and consequently leading to a significant increase in its wear ratio.

[picture]

Fig. 3. Surface morphologies of the Si -face of 4H−SiC wafers: (a) as-received surface; (b) after grinding with #800 diamond wheel; (c) after fine grinding with #8000 diamond wheel.

Fig. 3. Surface morphologies of the Si -face of 4 H − S i C wafers: (a) as-received surface; (b) after grinding with #800 diamond wheel; (c) after fine grinding with #8000 diamond wheel.

[picture]

Fig. 4. Comparison of grinding performance between the C -face and Si -face:
(a) material removal thickness, wheel wear, and wheel wear ratio during #800 rough grinding;
(b) material removal thickness, wheel wear, and wheel wear ratio during #8000 fine grinding.
The triangular symbols ( A ) and error bars represent the wheel wear ratio (W/M), defined as the ratio of wheel wear to material removal.

Fig. 4. Comparison of grinding performance between the C -face and Si -face: (a) material removal thickness, wheel wear, and wheel wear ratio during #800 rough grinding; (b) material removal thickness, wheel wear, and wheel wear ratio during #8000 fine grinding. The triangular symbols ( A ) and error bars represent the wheel wear ratio (W/M), defined as the ratio of wheel wear to material removal.

[picture]

Fig. 5. Cross-sectional morphology of the 4H−SiC wafer after laser modification.

Fig. 5. Cross-sectional morphology of the 4 H − S i C wafer after laser modification.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

This study systematically compares the grinding behavior of the C - and Si -faces in laser-sliced 4H−SiC wafers. The results reveal pronounced differences in material removal and wheel wear. Under identical grinding conditions, the Si-face exhibits a higher wheel wear ratio. This behavior is closely related to the intrinsic anisotropy of 4H−SiC : the C -face possesses higher hardness and distinct fracture characteristics, while its higher dislocation density facilitates stress release, thereby reducing tool wear. In contrast, the Si-face displays a relatively single-dominant removal mechanism, which leads to increased wheel wear. Moreover, for thin wafers obtained by laser slicing, the focal position of the laser strongly influences subsequent grinding performance. When the focus remains near the wafer surface, the wear ratio of the Si-face increases significantly.

These findings provide valuable insights for optimizing SiC wafer grinding processes. Future work will integrate nanoindentation experiments with micro-cutting simulations to further elucidate the differences in mechanical response and crack evolution between crystal planes. In addition, the coupling between the laser-modified layer and subsequent grinding will be investigated to better elucidate the removal mechanisms of different crystallographic orientations, ultimately guiding the development of efficient processes for fabricating large-diameter, high-quality 4H−SiC wafers.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

This work was supported by the National Natural Science Foundation of China (Grant No. U23A20569), the National Natural Science Foundation of China (62305189), the Key R&D Program of Shandong Province, China (2022ZLGX02) and Shandong Provincial Natural Science Foundation, China (ZR2022QF129).

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.1.pdf

M. Zou, F. Dou, Review of silicon carbide wafer cutting methods, Superhard Mater. Eng. 34 (2022) 35-41. (in Chinese).

E. Kim, Y. Shimotsuma, M. Sakakura, et al., Ultrashort pulse laser slicing of semiconductor crystal, Proc. Pac. Rim Laser Damage 2016: Opt. Mater. High-Power Lasers 9983 (2016) 4045.

E. Kim, Y. Shimotsuma, M. Sakakura, et al., 4H-SiC wafer slicing by using femtosecond laser double-pulses, Opt. Mater. Express 7 (2017) 2450-2460.

K. Hirata, New laser slicing technology named KABRA process enables high speed and high efficiency SiC slicing, Laser-Based Micro-and Nanoprocessing XII 10520 (2018) 1052003.

M. Swoboda, R. Rieske, C. Beyer, et al., Cold split kerf-free wafering results for doped 4H-SiC boules, Mater. Sci. Forum 963 (2019) 10-13.

Y. Yao, Q. Chen, B. Li, et al., Influence of crystal orientation and incident plane on n-type 4H-SiC wafer slicing by using picosecond laser, Opt. Laser Technol. 182 (2025) 112174.

Q. Chen, Y. Yao, J. Zhang, et al., Effect of nitrogen doping concentration on 4H-SiC laser slicing, J. Am. Ceram. Soc. (2025) e20555.

Z. Tian, X. Chen, X. Xu, Molecular dynamics simulation of material removal mechanism during scratching of 4H-SiC and 6H-SiC, Extreme Manuf. 2 (2020) 045104. (in Chinese).

K. Tang, W. Ou, C. Mao, et al., Material removal characteristics of single-crystal 4H-SiC based on varied-load nanoscratch tests, Chin. J. Mech. Eng. 36 (2023) 111.

H. Wang, Z. Dong, R. Kang, et al., Surface characteristics and material removal mechanisms during nanogrinding on C -face and Si -face of 4 H -SiC crystals: Experimental and molecular dynamics insights, Appl. Surf. Sci. 665 (2024) 160293.

J. Xia, Q. Yan, J. Pan, et al., Mechanism analysis and process optimization of nanogrinding single-crystal SiC, Mater. Sci. Semicond. Process. 175 (2024) 108218.

J. Cui, X. Yang, Y. Li, et al., Study on ultraprecision cutting characteristics of single-crystal silicon based on nanoindentation and nanoscratch experiments, J. Synth. Cryst. 52 (2023). (in Chinese).

K.E. Prasad, K.T. Ramesh, Hardness and mechanical anisotropy of hexagonal SiC single crystal polytypes, J. Alloys Compd. 770 (2019) 158-165.

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The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 9-17

doi: 10.4028/p-OGH9rS

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-10

Revised:
2025-12-22

Accepted:
2026-02-26

Online:
2026-05-21

Effects of Processing Passes on Laser-Sliced SiC

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Jianfei Zhang 1,a, Bixue Li1, b, Qiu Chen 1,c, Linlin Che 1, d, Xing Zhang 1,e, Haoyu Fan 1,f, Yangyang Jia 1, g, Jiawei Wang 1, h, Yufeng Xue 1,i, Rongkun Wang 1,j*, Xiufang Chen 1,k*

1 State Key Laboratory of Crystal Materials, Institute of Novel Semiconductors, Shandong University, Jinan 250100, China

Keywords: Laser slicing; Crack propagation; Kerf loss.

Abstract

Silicon carbide (SiC), a representative of next-generation wide-bandgap semiconductors, exhibits enormous application potential in fields such as new energy vehicles, aerospace, and photovoltaic power generation. Conventional cutting methods based on diamond wire sawing suffer from high material loss and are prone to causing fractures. In contrast, laser slicing, as a kerf-free processing technology, enables the acquisition of high-quality wafers with minimal material removal. This study systematically investigates the effect of processing cycles on crack propagation and delamination strength during laser slicing of SiC. The experimental results demonstrate that under optimized parameters, an appropriate number of processing cycles can achieve successful wafer separation while maintaining surface integrity, reducing material loss, and lowering delamination strength. The established processing window provides practical guidance for improving SiC slicing quality and holds significant implications for advancing innovative wafer manufacturing technologies in power electronics applications.

a zjf2531@163.com, blibx@mail.sdu.edu.cn, c 724717776@qq.com, d 202214075@ mail.sdu.edu.cn, e17731872242@163.com,f fanhaoyu2001@163.com, g202534175@mail.sdu.edu.cn,h15634035763@163.com, i2904562783@qq.com, j wrk @ sdu.edu.cn, k cxf@sdu.edu.cn

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Silicon carbide ( SiC ), as one of the core representatives of third-generation wide-bandgap semiconductor materials, has become a critical supporting material in strategically emerging fields such as rail transit traction converters, 5G base station radio frequency devices, aerospace extreme environment sensors, and new energy vehicle power modules, thanks to its excellent hightemperature stability, high breakdown electric field strength, high-frequency signal response capability, and high-power bearing characteristics [1,2]. In the manufacturing process of SiC power chips, it is first necessary to grow high-quality single-crystal ingots via techniques such as Physical Vapor Transport (PVT). Subsequently, precision processing procedures including slicing, grinding, and polishing are performed to produce substrates that meet epitaxial requirements. Finally, device fabrication steps such as epitaxial growth, photolithographic patterning, ion implantation, and annealing activation are sequentially completed [3,4]. Throughout the entire process mentioned above, the processing accuracy and quality control of the crystal slicing step are particularly critical-the thickness uniformity, surface roughness, and subsurface damage layer depth of the substrate after slicing directly determine the crystalline quality and interface integrity of the subsequent epitaxial layer, thereby exerting a significant impact on the on-resistance, breakdown voltage, and long-term reliability of the final power device. However, the extremely high hardness (Mohs hardness of 9.29.5 ) and brittle nature of single-crystal SiC pose challenges such as difficult material removal and easy accumulation of processing damage during precision slicing, making it difficult for traditional processing technologies to balance efficiency and quality [5,6]. Currently, the mainstream SiC slicing technologies in industry and academia are mainly divided into two categories: laser slicing and wire saw slicing. Among them, laser slicing, based on the principle of non-contact processing, has significant advantages including high processing efficiency, low kerf loss, high dimensional accuracy, and strong damage controllability, and has become an important development direction for slicing
large-size SiC ingots. The core principle of this technology is as follows: a pulsed laser with a specific wavelength is focused to a preset depth inside the SiC ingot, so that the energy density in the focused area reaches the material damage threshold and a modified layer (e.g., amorphized region, microcrack region) is generated; by designing a high-precision laser scanning path, adjacent modified regions are connected to form a continuous separation surface, weakening the internal bonding force of the ingot; finally, with the assistance of ultrasonic vibration-assisted peeling, mechanical tensile separation, or electrochemical etching, efficient separation of the wafer from the ingot is achieved [7,8].

Continuous technological iterations and mechanism research have driven the rapid development of the field of SiC laser slicing. Kim et al. [9,10] took the lead in focusing ultrafast pulsed lasers with a dual-pulse structure into 4H−SiC crystals, realizing the precise separation of thin wafers; through Raman spectroscopy and high-resolution microscopic characterization, they found that significant structural transformation occurred in the laser-affected region, specifically manifested as the amorphization of 4H−SiC crystals and their decomposition into amorphous silicon and amorphous carbon phases; mechanical tests further confirmed that the tensile force required for wafer separation under the dual-pulse processing method was significantly lower than that under single-pulse processing. Han et al. [11] used a 1064 nm picosecond laser to induce multiphoton-induced microexplosions in 4H−SiC; these micro-explosions confined the micro-explosion layer to the vicinity of the laser beam focus, and due to the generated instantaneous high temperature, 4H−SiC decomposed into amorphous silicon and carbon, and two 4H−SiC wafers with a thickness of 250μ m were successfully prepared. Geng et al. [12] proposed a composite slicing technology combining femtosecond laser irradiation and bandgap-selective photoelectrochemical (PEC) peeling, achieving high-yield (yield >95% ) separation of 4H−SiC wafers. Characterization and analysis via optical absorption spectroscopy, micro-Raman, and photoluminescence (PL) showed that the damage layer induced by femtosecond lasers inside 4H−SiC was mainly composed of amorphous silicon (a-Si) and amorphous carbon (a-C), with its bandgap width reduced to 0.4 eV , which was significantly different from that of intact 4H-SiC (bandgap of 3.26 eV ); using this characteristic, the damage layer could be selectively removed from the intact region of 4H−SiC via bandgap-selective PEC etching, avoiding secondary damage to the wafer surface caused by mechanical separation. Jiang et al. [13] proposed a continuous laser-assisted SiC wafer splitting method based on a picosecond laser-modified layer, showing that the modified layer prepared by picosecond lasers in SiC samples significantly improved laser absorption rate, and the absorption coefficient of the modified SiC samples at 1064 nm was increased by 2720 times. Lv et al. [14] designed orthogonal experiments on ultrasonic-assisted peeling for laser-modified 4H−SiC single crystals, systematically investigating the influence of ultrasonic frequency, vibration time, and ultrasonic power on the bonding force of the modified layer. The results showed that ultrasonic vibration could promote the propagation of microcracks inside the modified layer through cavitation effect, reducing the bonding force between the modified layer and the matrix by 25%−60%. Wang et al. [15] conducted laser cutting experiments on 4H−SiC samples with different surface roughness. The study found that good surface quality could reduce damage to the wafer surface during laser cutting, decrease the occurrence of cleavage, and improve the flatness and uniformity of the modified layer. Chen et al. [16] combined experiments with two-temperature model analysis to explore the influence of different doping concentrations on the laser cutting of n-type 4HSiC; the results showed that an increase in nitrogen doping concentration led to a decrease in resistivity and an increase in laser absorption rate, which in turn affected the crack propagation length and modified line width. By optimizing processing parameters, high-quality laser cutting of SiC wafers with five gradient doping concentrations was successfully achieved. Finally, an 8-inch N-type 4H−SiC wafer was successfully sliced.

Although existing studies on laser slicing of 4H−SiC wafers have achieved breakthroughs in multiple aspects, there is a lack of systematic research on the key variable of laser repeated processing cycles. In actual industrial production, to achieve efficient slicing of large-size 4H−SiC ingots (e.g., 6-8 inches), multiple laser scans are often required to enhance the continuity of the modified layer, thereby reducing the difficulty of subsequent separation; however, the cumulative effect of energy during repeated processing may lead to excessive expansion of the modified layer, causing problems
such as an increase in the depth of longitudinal microcracks and an expansion of the subsurface damage range, which in turn affect the material removal efficiency of subsequent grinding processes and the final quality of the substrate.

Based on this, this study takes semi-insulating 4H-SiC single crystals as the research object. On the basis of fixing the core laser parameters (wavelength of 1030 nm , pulse width of 10 ps ) and optimizing process conditions (C-face incidence, scanning along the [11―00] orientation), experimental groups with 1-9 laser repeated processing cycles were designed. Optical microscopy was used to analyze the influence of processing cycles on crack morphology, and an electronic universal testing machine was employed to measure the change in tensile force required for wafer separation. The study aims to clarify the quantitative relationship between the number of laser repeated processing cycles and the slicing quality of 4H−SiC, reveal the cumulative mechanism of longitudinal damage caused by multiple processing cycles, and avoid discontinuous modified layers and excessively high separation tensile force due to insufficient processing cycles, or excessive damage diffusion caused by excessive processing cycles. Based on the comprehensive evaluation of crack propagation uniformity, separation tensile force stability, and damage controllability, the optimal number of laser repeated processing cycles and supporting process parameters are determined, providing a quantitative basis for reducing longitudinal damage and improving slicing efficiency. The results of this study can not only fill the research gap in the optimization of processing cycles in existing laser slicing technologies but also provide technical guidance with both theoretical value and engineering practicality for the precision processing and advanced manufacturing of 4H−SiC wafers.

Experiment

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

The experimental material used in this study was a 6-inch SiC wafer, which was laboratoryfabricated with a thickness of 700μ m and a surface roughness (Ra) of approximately 1 nm . This wafer was then cut into rectangular cuboids with dimensions of 20 mm×20 mm×700μ m. A schematic diagram of the laser slicing system used in the experiment is shown in Fig.1. The laser cutting parameters were as follows: wavelength λ=1030 nm, pulse width τ=10ps, pulse repetition frequency (PRF) of 100−1000kHz, and scanning speed of 100−400 mm/s. A Liquid Crystal Spatial Light Modulator (LCSLM) was used to accurately compensate and correct the spherical aberration caused by the difference in refractive index between air and 4H−SiC, realizing distortion correction of the laser-focused spot. Under the conditions of a power of 1 W and a step distance of 200μ m, the samples were subjected to complete laser modification with different numbers of cycles ( 1 to 9 cycles). An industrial microscope was used to observe the connection of crack propagation in the top and side views. To further quantify the laser modification effect and slicing feasibility, a mechanical peeling experiment was conducted on the modified samples using an electronic universal testing machine. Both ends of the samples were fixed to the fixtures with high-strength epoxy adhesive, a tensile force was applied at a constant speed, and the peeling force was recorded simultaneously. The cutting quality was evaluated based on the changes in crack propagation and peeling force.

[picture]

Fig. 1. Schematic of laser-slicing system.

Fig. 1. Schematic of laser-slicing system.

Results and Discussion

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Top-View Observation of Crack Propagation.

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The integrity, continuity, and morphological regularity of crack propagation are core indicators for evaluating laser slicing quality, as they directly determine the feasibility of subsequent wafer separation and the flatness of the separation surface. In this study, an industrial inspection microscope was used to conduct top-view observations of 4H−SiC samples after 1−9 laser processing cycles, and the crack propagation morphologies under different processing cycles were obtained; the results are shown in Fig. 2 (a-i). From Fig. 2 (a) (1 processing cycle), clear laser scanning traces can be observed on the sample surface, with an interval of approximately 200μ m between adjacent traces. This interval completely matches the preset scanning step parameter in the experiment, verifying the accuracy of the laser scanning path. Measurements of typical regions in this group of samples revealed that the width of the laser traces was approximately 19.8μ m, and the total crack propagation length was about 65.6μ m. Notably, the cracks between adjacent traces did not form effective connections. This phenomenon is attributed to the limited energy input of a single laser processing cycle, which only generates a local modified layer (mainly composed of amorphized regions and microcracks) near the scanning path. A continuous separation surface is not established between adjacent modified layers, resulting in a relatively high internal bonding force of the wafer and significant difficulty in subsequent separation.

[picture]

Fig. 2. (a)-(i) Top-view optical micrographs corresponding to 1−9 processing passes.

Fig. 2. (a)-(i) Top-view optical micrographs corresponding to 1 − 9 processing passes.

When the number of processing cycles increased to 2−3 (Fig. 2( b−c) ), the cracks induced by adjacent laser traces began to connect with each other, forming a preliminary continuous separation path. However, the crack morphology exhibited partial irregular feather-like branches. This is because during the second and third laser scans, the laser energy caused a stress concentration effect at the tips of the already formed microcracks; while this effect promotes the lateral propagation of cracks, it also triggers local irregular branching. As the number of processing cycles further increased to 4− 6 (Fig. 2 (d-f)), the cumulative effect of laser energy became increasingly prominent. On one hand, multiple scans increased the width of the laser traces and further expanded the range of crack propagation; on the other hand, obvious ablation marks appeared in local areas of the samples. When the number of processing cycles reached 7−9 (Fig. 2 (g-i)), the surface ablation marks deepened further, and significant height differences emerged in some regions. This is because excessive laser energy input not only intensifies crack propagation but also causes stress accumulation inside the modified layer, leading to tiny bulges or depressions in local areas and damaging the surface flatness. To meet the substrate requirements, a thicker damaged layer must be removed through subsequent grinding processes, which increases processing costs and material loss.

Side-View Observation of Cracks and Peeling Force.

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To further investigate the effect of laser processing cycles on the longitudinal damage of 4 H SiC samples, side-view observations were conducted on the samples after side polishing to analyze the propagation depth of transverse cracks and the distribution of longitudinal damage. Meanwhile, an electronic universal testing machine was used to measure the peeling force of the laser-modified samples, establishing a correlation among "processing cycles-crack morphology-peeling force". As shown in Fig.3, different numbers of processing cycles exhibit a significant regulatory effect on the transverse propagation of cracks and longitudinal damage. When processed only once (Fig. 3 (a)), crack propagation is limited and the cracks are disconnected; the typical spacing between cracks induced by adjacent laser traces is approximately 30.6μ m, and no continuous damage layer is formed.

This result mutually confirms the "disconnected cracks" observation from the top-view analysis. When processed twice (Fig. 3 (b)), the cracks extend further and begin to transition toward a continuous state, though local disconnected regions still exist. When processed 3-4 times (Fig.3 (cd)), the transverse cracks are completely connected, accompanied by slight longitudinal delamination damage. This phenomenon occurs because multiple laser scans increase the thickness of the modified layer; while transverse cracks are connecting, the accumulation of longitudinal stress triggers local delamination. When the number of processing cycles increases to 5−9 (Fig.3 (e-i)), the transverse cracks are already fully and stably connected, but the longitudinal damage intensifies significantly. The core reason for this phenomenon is that under a large number of processing cycles, the modified layer formed by previous laser scans alters the energy absorption and focusing state of subsequent lasers (the refractive index of the modified layer differs from that of intact SiC , leading to the deviation of the laser focus point). This causes excessive energy accumulation in the longitudinal direction, triggering damage diffusion along the depth. Such diffusion not only increases the amount of material to be removed in subsequent grinding but may also reduce the thickness uniformity of the substrate.

[picture]

Fig. 3. (a-i) Cross-sectional crack morphology images corresponding to 1−9 processing passes.

Fig. 3. (a-i) Cross-sectional crack morphology images corresponding to 1 − 9 processing passes.

The variation trend of tensile strength shows a strong correlation with the crack propagation effect (as shown in Fig.4). When processed only once, due to disconnected cracks and high internal bonding force of the wafer, the peeling force required for sample separation is as high as 3.01 MPa . With the increase in processing cycles, the transverse cracks gradually connect, the bonding force weakens progressively, and the peeling force decreases accordingly. When the number of processing cycles reaches 5, the peeling force drops to 0.68 MPa and then stabilizes. This indicates that an appropriate number of processing cycles can not only reduce longitudinal damage but also lower the peeling force during the cutting process.

[picture]

Fig. 4. Trend chart of tensile strength versus number of processing passes.

Fig. 4. Trend chart of tensile strength versus number of processing passes.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

This study systematically investigates the regulatory law of laser processing cycles on the slicing quality of 4H−SiC wafers, with a focus on analyzing the evolutionary characteristics of crack propagation morphology and peeling force. The key findings are as follows: When processed only once, limited by the constraints of energy input, the generated cracks are limited in scope and disconnected from each other. In this case, the internal bonding force of the wafer is not effectively weakened, resulting in a relatively large peeling force. For 2−4 processing cycles, the cumulative effect of laser energy promotes the transverse propagation of cracks and enables their connection; however, there is a risk of longitudinal delamination. When the number of processing cycles reaches 5-9, although the transverse cracks are already fully connected, the longitudinal damage intensifies significantly, which increases cutting loss. The test results of peeling force show a strong correlation with the crack propagation morphology: the peeling force decreases with the increase in processing cycles, and stabilizes when the number of processing cycles reaches 5 . This indicates that an optimal balance is achieved between crack connectivity and damage minimization at this point. An appropriate number of laser processing cycles can reduce longitudinal damage and peeling force during the cutting process, providing practical references for improving the quality of SiC laser slicing and advancing the development of wafer manufacturing technology.

Authorship Contribution Statement

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Jianfei Zhang: Writing - review & editing, Writing - original draft, Validation, Investigation, Conceptualization. Bixue Li: Writing original draft, Validation, Data curation, Conceptualization. Qiu Chen: Data curation, Formal analysis. Linlin Che: Conceptualization, Validation. Xing Zhang: Writing - review & editing, Supervision. Haoyu Fan: Visualization, Formal analysis. Yangyang Jia: Visualization, Formal analysis. Jiawei Wang: Visualization, Formal analysis. Yufeng Xue: Visualization, Formal analysis. Rongkun Wang: Project administration, Methodology. Xiufang Chen:

Writing review & editing, Supervision, Resources, Project administration, Funding acquisition, Conceptualization.

Acknowledgements

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

This work was supported by the National Natural Science Foundation of China (Grant No. U23A20569), the Key R&D Program of Shandong Province, China (2022ZLGX02).

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.9.pdf

Zhao J, Ji P, Li Y, et al. Ultrahigh-mobility semiconducting epitaxial graphene on silicon carbide[J]. Nature, 2024, 625(7993): 60-65.

Nakamura D, Gunjishima I, Yamaguchi S, et al. Ultrahigh-quality silicon carbide single crystals[J]. Nature, 2004, 430(7003): 1009-1012.

Eddy C R, Gaskill D K. Silicon Carbide as a Platform for Power Electronics[J]. Science, 2009, 324(5933): 1398-1400.

Chen X, Yang X, Xie X, et al. Research progress of large size SiC single crystal materials and devices[J]. Light: Science & Applications, 2023, 12(1): 28.

Wang G, Sheng D, Yang Y, et al. High-Quality and Wafer-Scale Cubic Silicon Carbide Single Crystals[J]. ENERGY & ENVIRONMENTAL MATERIALS, n/a(n/a): e12678.

Li Y, Zhang Z, Song Q, et al. Surface micromorphology and nanostructures evolution in hybrid laser processes of slicing and polishing single crystal 4H-SiC[J]. Journal of Materials Science & Technology, 2024, 184: 235-244.

Peng Y, Zeng J, Xie X, et al. Laser machining of silicon carbide: current status, applications and challenges[J]. Optics & Laser Technology, 2025, 191: 113376.

Jiang K, Zhang P, Song S, et al. A review of ultra-short pulse laser micromachining of wide bandgap semiconductor materials: SiC and GaN[J]. Materials Science in Semiconductor Processing, 2024, 180: 108559.

Kim E, Shimotsuma Y, Sakakura M, et al. Ultrashort pulse laser slicing of semiconductor crystal[C]//Jitsuno T, Shao J, Rudolph W. Pacific Rim Laser Damage 2016: Optical Materials for High Power Lasers. Yokohama, Japan, 2016: 99831B.

Kim E, Shimotsuma Y, Sakakura M, et al. 4H-SiC wafer slicing by using femtosecond laser double-pulses[J]. Optical Materials Express, 2017, 7(7): 2450.

Shifei Han, Haijuan Yu, Chaojian He, et al. Laser slicing of wafers based on picosecond laser-induced micro-explosion via multiphoton processes[J]. Optics & Laser Technology, 2022, 154: 108323.

Geng W, Shao Q, Pei Y, et al. Slicing of 4H-SiC Wafers Combining Ultrafast Laser Irradiation and Bandgap-Selective Photo-Electrochemical Exfoliation[J]. Advanced Materials Interfaces, 2023, 10(21): 2300200.

Lu Jiang, Zhao S, Han S, et al. CW laser-assisted splitting of SiC wafer based on modified layer by picosecond laser[J]. Optics & Laser Technology, 2024, 174: 110700.

Lv B, Ye L, Zhu X, et al. Ultrasonic-assisted stripping of single-crystal SiC after laser modification[J]. Ceramics International, 2024: S0272884224042081.

Hanwen Wang, Chen Q, Yao Y, et al. Influence of Surface Preprocessing on 4H-SiC Wafer Slicing by Using Ultrafast Laser[J]. Crystals, 2023, 13(1): 15.

Chen Q, Yao Y, Zhang J, et al. Effect of nitrogen doping concentration on laser slicing[J]. Journal of the American Ceramic Society, n/a(n/a): e20555.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 19-24

doi: 10.4028/p-jAm4lU

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-27

Online:
2026-05-21

Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

Takanori Tanaka 1,a*, Kyohei Akiyoshi 1, b, Kazumasa Iwanaga 1,c, Shunta Takahashi 2, d, Hiroshi Watanabe 2,e, Kenichi Hamano 1,f and Akihiko Furukawa 1, g

1 Power Device Works, Mitsubishi Electric Corporation, 1-1-1, Imajyukuhigashi, Nishi-ku, Fukuoka 819-0192, Japan

2 Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki, Hyogo 661-8661, Japan

a Tanaka.Takanori@cb.MitsubishiElectric.co.jp, b Akiyoshi.Kyohei@ea.MitsubishiElectric.co.jp, c  Iwanaga.Kazumasa@aj.MitsubishiElectric.co.jp, d  Takahashi.Shunta@bp.MitsubishiElectric.co.jp,

eWatanabe.Hiroshi@dh.mitsubishielectric.co.jp, f  hamano.kenichi@df.mitsubishielectric.co.jp, g  Furukawa.Akihiko@df.MitsubishiElectric.co.jp

Keywords: SiC wafer, reutilization process, recycling wafer, laser split, bonding technique.

Abstract

We propose a novel SiC wafer recycling process that employs the laser splitting and wafer bonding techniques. The process allows us to attain the recycled SiC wafers suitable for conventional device processes, leading to the reduction of SiC device costs and environmental burdens. Preliminary evaluations were conducted on the key technologies of the process: surface activated bonding and laser splitting for SiC wafers. The bonding interface was confirmed to withstand the stresses encountered during device manufacturing thanks to the recrystallization of the interface layer. The electrical characteristics of MOSFETs thinned using laser splitting showed no significant difference compared to those thinned by conventional grinding. These results demonstrate that the proposed process is a feasible technique that offers a cost-effective and ecofriendly solution for SiC power device production.

Introduction

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The high cost of SiC wafers is one of the major issues in further promoting the adoption of SiC devices. SiC wafers are frequently thinned through grinding to reduce on-resistance and mitigate thermal stress caused by differences in thermal expansion coefficients within power modules. Reducing the amount of discarded SiC material and, ideally, reusing it in device fabrication is highly desirable. This approach not only helps reduce costs but also minimizes environmental impact. Several potential technologies for reducing wafer costs have been reported [1, 2], but there are still challenges to tackle from both technical and cost perspectives.

We propose a novel SiC wafer reutilization process that employs laser splitting and bonding techniques. The laser splitting technology is progressing markedly today and well-suited for this process. Preliminary experiments have been conducted on wafer bonding and laser splitting, which are key technologies for the proposed wafer reutilization process. In this paper we present the findings and examine the feasibility of the proposed approach.

Proposal of Novel SiC Wafer Reutilization Process

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A novel SiC wafer reutilization process for device fabrication is proposed. Fig. 1 illustrates the rough sequence of the SiC wafer reutilization process. In this process, a wafer is split into two wafers at a certain thickness after fabricating device structures on its top surface. The wafer with the device structures undergoes usually used wafer processing. Meanwhile, the surface of the split wafer without device structures is polished, cleaned, and then bonded with another split wafer. This results in a recycled wafer with a thickness suitable for device fabrication. After forming device structures on the

[picture]

Fig. 1. Schematic of Novel SiC Wafer Reutilization Process using laser splitting and bonding techniques.

Fig. 1. Schematic of Novel SiC Wafer Reutilization Process using laser splitting and bonding techniques.

bonded wafer, it is split again into two wafers: one with devices and one without devices. The split wafer without devices then repeats the above-mentioned process, and thereby the recycled wafer is fabricated again.

The proposed process is expected to attain several advantages. Firstly, it leads to reduction in costs and material loss, which is crucial for SiC device manufacturing. Specifically, this process increases the chip yield (in this case referring to the number of chips) per initial wafer, thereby drastically reducing the chip cost. Secondly, it eliminates the need for externally procured heterogeneous support wafers, such as poly-SiC wafers, and the recycled wafers are formed entirely from 4H−SiC material. This not only reduces costs but also enhances compatibility with conventional device production processes. Furthermore, it is possible for the sprit wafer with devices to exclude the junction interface, ensuring that there are no negative effects on device characteristics resulting from including the bonding interface such as increase in resistance.

The wafer bonding technique and the laser splitting technique are key technologies in this wafer reutilization process. To verify the feasibility of this wafer reutilization process, preliminary experiments were conducted on these two techniques.

Investigation of Wafer Bonding Technique

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

We investigated the bonding technique for split SiC wafers and the feasibility to split the bonded wafer at a designed thickness. The SiC wafer bonding method is schematically shown in Fig. 2. Two 6-inch 4∘ off 4H-SiC wafers were thinned to 150μ m by grinding, and their surfaces for bonding (both C - and Si -face) were flattened using a CMP method. Subsequently, the two wafers were bonded at room temperature using the surface activated bonding method [3].

The bonded wafer fabricated using above method were implanted with Al ions at a doping concentration of 2×1015 cm−2 across the entire wafer surface and subsequently annealed at 1750∘C to electrically activate the Al. Additionally, another bonded wafer was divided again by the laser

[picture]

Fig. 2. Fabrication method of bonded wafers.

Fig. 2. Fabrication method of bonded wafers.

splitting technique after epitaxial growth. The evaluation was conducted through optical microscope observation, warpage measurement, and cross-sectional TEM analysis.

Fig. 3(a) shows appearance of the wafer immediately after wafer bonding. No significant differences in appearance between the bonded and normal wafers are noted except for a few small voids ( 1−5 mm in diameter) caused by particles at the bonding interface. Photos of the whole wafers after the Al implantation and the thermal annealing are shown in Fig. 3(b) and (c), respectively. Change of color due to Al implantation is observed in Fig. 3(b), but the color returns to the original color of as-bonded wafers after the thermal annealing. No cracks, chips or peelings originating from voids or wafer edges are observed after the bonding and subsequent Al implantation and the annealing processes. Despite the strong stress imposed on the wafer by high dose ion implantation and high temperature annealing, the bonded wafer shows no fatal changes.

The bonding interfaces immediately after bonding and after the annealing were observed in detail using the cross-sectional TEM. Corresponding TEM images are shown in Fig. 4(a) and (b), respectively. In the TEM image of the as-bonded wafer (Fig. 4(a)), an interface layer is clearly observed between the upper and lower wafers, and it is confirmed from the magnified image that this layer exhibits an amorphous structure. In contrast, at the bonding interface after the thermal annealing, the distinct amorphous layer disappears, indicating that solid phase reaction has occurred and yielded polycrystals at the interface during the high temperature annealing process. Since the polycrystals are strongly bonded to each other, the bonded wafers do not break or peel and are expected to withstand harsh wafer processes.

We investigated warpage of the bonded wafer. Fig. 5 shows the relationship between the SORI and the wafer thickness for the bonded and standard wafers. SORI of both types of wafers decreases with increasing the wafer thickness. It is found that they are on the curve calculated using Stoney's equation. Additionally, it has been confirmed that the SORI does not change significantly even after implantation and annealing. This indicates that we need no special care to handle the bonded wafers.

[picture]

Fig. 3. Appearances of the wafer (a) after bonding, (b) Al implantation at a doping concentration of 2×1015 cm−2, and (c) thermal annealing at 1750∘C.

Fig. 3. Appearances of the wafer (a) after bonding, (b) Al implantation at a doping concentration of 2 × 10 15 c m − 2 , and (c) thermal annealing at 1750 ∘ C .

[picture]

Fig. 4. Cross-sectional TEM images of the bonding interface (a) immediately after bonding, and (b) after thermal annealing.

Fig. 4. Cross-sectional TEM images of the bonding interface (a) immediately after bonding, and (b) after thermal annealing.

[picture]

Fig. 5. Wafer thickness dependence of SORI for standard wafers and bonded wafers.

Fig. 5. Wafer thickness dependence of SORI for standard wafers and bonded wafers.

[picture]

Fig. 6. Cross-sectional structure and splitting position of bonded wafers.

Fig. 6. Cross-sectional structure and splitting position of bonded wafers.

[picture]

Fig. 7. Images of the bonded wafer (a) before laser splitting, and (b) the top side without bonding interface and (c) the bottom side with bonding interface after laser splitting.

Fig. 7. Images of the bonded wafer (a) before laser splitting, and (b) the top side without bonding interface and (c) the bottom side with bonding interface after laser splitting.

Next, feasibility of re-splitting the bonded wafer using laser splitting technique [4, 5] was investigated. Cross-sectional structure and splitting position of the bonded wafer is illustrated in Fig.
6. After SiC epitaxial growth on top side of the bonded wafer, a protective tape was put onto it. The splitting was set at the position between the bonding interface and the epitaxial layer. Since the laser beam scan is performed from the backside of the wafer, the laser light focuses beyond the bonding interface.

Fig. 7 shows surface images of bonded wafer before laser splitting (a) and after laser splitting (b, c). The bonding interface exists in the bottom side wafer. No noticeable cracks or chips are observed in the wafer after splitting, indicating that the bonding interface does not negatively affect the laser splitting. This result shows that the bonded wafer can be re-split with the designed thickness irrespective of the position of bonding interface.

Influence of Laser Splitting Process on MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

The influences of laser splitting on characteristics of SiC power devices has been investigated to verify the feasibility of applying the laser splitting technique to device fabrication. SiC MOSFETs were fabricated using the laser splitting technique for the thinning process.

The fabrication procedure for the SiC MOSFETs is illustrated in Fig. 8. An epitaxial layer was grown on a standard 6 -inch 4H−SiC substrate with a 4∘ off-cut angle, and 1200 V SiC MOSFET structures were subsequently fabricated on this epitaxial layer. This wafer was then divided at a depth of 180μ m from the top surface by precisely controlling the laser focus during the laser splitting

[picture]

Fig. 8. Fabrication procedure.

Fig. 8. Fabrication procedure.

[picture]

Fig. 10. Comparison of main electrical characteristics ((a) Igss, (b) Vth, (c) Idss, and (d) Vds(ON)) of MOSFETs fabricated using laser splitting and conventional grinding process.

Fig. 10. Comparison of main electrical characteristics ((a) Igss, (b) Vth, (c) Idss, and (d) Vds(ON)) of MOSFETs fabricated using laser splitting and conventional grinding process.

process. The rough splitting surfaces were subsequently ground to achieve a final thickness of 100 μm. Finally, a backside metal electrode was formed, and the wafer was diced into chips. Image of the wafers observed from the top side after laser splitting are shown in Fig. 9. No damage is visible in the image.

The main electrical characteristics of MOSFETs, including gate leakage current (Igss), threshold voltage ( Vth  ), drain leakage current (Idss) and on-voltage (Vds(on)), were measured.

Fig. 10 shows the characteristics of the MOSFETs. In the figure, the values of the MOSFETs thinned by the laser splitting process are compared to those of MOSFETs thinned by the conventional grinding process. The Igss remains very low for the MOSFETs with the laser process (as shown in Fig. 10(a)), and the Vth shows no change compared to MOSFETs with conventional thinning process (as shown in Fig. 10(b)), meaning that the gate oxide film was not subjected to significant damage from the laser irradiation. No significant changes in mean values and deviations were observed for the Idss and the Vds(On) (as shown in Fig. 10(c) and (d)), indicating that the laser splitting process does not damage the drift layer or electrodes. So far, we have obtained no results that show the laser process negatively impacts the MOSFET electrical characteristics.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

We proposed a novel SiC wafer reutilization process that integrates laser splitting and wafer bonding techniques. This approach aims to drastically reduce costs and material loss in SiC power device manufacturing by enabling the recycling of the wafers.

Our preliminary investigations have demonstrated the technical feasibility of this proposed process. Through comprehensive experiments on SiC wafer bonding, we confirmed that strong and stable bonds can be achieved using the SAB technique. The bonded wafers withstand processes such as high-temperature annealing and high-dose ion implantation without significant changes or delamination. Detailed cross-sectional TEM analysis revealed the formation of robust polycrystalline bonds at the interface due to solid phase reactions during thermal annealing, confirming their suitability for subsequent device processing.

The influence of the laser splitting process on device characteristics was evaluated using SiC MOSFETs. The electrical characteristics of the devices thinned by laser splitting showed no significant degradation compared to those thinned by conventional grinding. This confirms that the laser splitting process does not induce damage to the gate oxide film, drift layer, or electrodes.

These results demonstrate the technical feasibility of the proposed approach, which offers a costeffective and eco-friendly solution for SiC power device production. It will be necessary to conduct evaluations of thermal stress accumulation after multiple cycles of splitting and bonding, as well as reliability assessments of the MOSFET after laser splitting in the future.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.19.pdf

S. Rouchier, G. Gaudin, J. Widiez, F. Allibert, E. Rolland, K. Vladimirova, G. Gélineau, N. Troutot, C. Navone, G. Berre, D. Bosch, Y.L. Leow, A. Duboust, A. Drouin, J-M. Bethoux, R. Boulet, A. Chapelle, E. Cela, G. Lavaitte, A. Bouville-Lallart, L. Viravaux, F. Servant, S. Bhargava, S. Thomas, I. Radu, C. Maleville and W. Schwarzenbach, Materials Science Forum 1062, 131 (2022).

H.Uchida, M. Kobayashi, N. Hatta, S. Ishikawa, K. Ozono, K. Masumoto, S. Kurihara, S. Harada and K. Kojima, Defect and Diffusion Forum 434, 39 (2024).

T. Suga, F. Mu, M. Fujino, Y. Takahashi, H. Nakazawa and K. Iguchi, Jpn. J. Appl. Phys., 54, 030214 (2015).

K. Hirata, Proc. of SPIE, 10520, 1052003 (2018).

K. Akiyoshi, T. Tanaka, S. Takahashi, K. Iwanaga, K. Hamano and A. Furukawa, "Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics", Proc. of ICSCRM 2025 (in press).

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 25-32

doi: 10.4028/p-lQ20LA

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-19

Accepted:
2026-02-26

Online:
2026-05-21

Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Kyohei Akiyoshi 1,a*, Takanori Tanaka 1, b, Shunta Takahashi 2,c, Kazumasa Iwanaga 1, d, Kenichi Hamano 1,e and Akihiko Furukawa 1,f

¹Power Device Works, Mitsubishi Electric Corporation, 1-1-1 Imajuku-higashi, Nishi-ku, Fukuoka, Fukuoka, 819-0192, Japan

2 Advanced Technology R&D Center, Mitsubishi Electric Corporation, 8-1-1 Tsukaguchi-honmachi, Amagasaki, Hyogo, 661-8661, Japan

a* Akiyoshi.Kyohei@ea.MitsubishiElectric.co.jp, b Tanaka.Takanori@cb.MitsubishiElectric.co.jp, c Takahashi.Shunta@bp.MitsubishiElectric.co.jp, d Iwanaga.Kazumasa@aj.MitsubishiElectric.co.jp, èhamano.kenichi@df.mitsubishielectric.co.jp, f  Furukawa.Akihiko@df.MitsubishiElectric.co.jp 

Keywords: SiC wafer, reutilization process, recycling wafer, laser slice, JBS diode, MOSFET.

Abstract

A laser slicing technique is an attractive alternative to grinding for thinning SiC wafers. This method has the potential to enable the reutilization of SiC wafers and reduce the waste generated during the grinding process. This paper comprehensively investigates the technical feasibility of laser slicing for the fabrication of SiC power devices. SiC JBS samples fabricated with laser irradiation revealed that by selecting the appropriate laser conditions, we can employ the technique without adversely affecting the JBS leakage current characteristics. Additionally, we fabricated SiC MOSFETs through wafer thinning using the laser slicing technique. The key electrical characteristics of the MOSFETs, including IGSS, IDSS,Vth  and VDS(on), showed no differences compared to those fabricated using conventional grinding. These results indicate that laser slicing is a highly promising thinning technique for the fabrication of SiC power devices.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Silicon carbide (SiC) power devices offer superior characteristics, including high breakdown voltage, low on-resistance, low switching loss, and high-temperature operation. In their application to high-power systems, significantly improved performance is expected compared to their Si counterparts [1].

However, the manufacturing costs of SiC power devices remain high due to the high costs of SiC wafers. The high costs of SiC wafers are attributed not only to the costly sublimation bulk growth process but also to wafering processes such as slicing and grinding, which are challenging due to the inherent hardness and brittleness of SiC [2, 3]. Additionally, in the fabrication of SiC power devices, SiC wafers are thinned to enhance their performance. The conventional thinning process used today employs mechanical grinding, which removes valuable SiC material as sludge, creating a significant environmental burden.

Recently, the laser slicing technique has attracted significant attention as a method for slicing wafers from ingots [4]. Laser slicing can substantially reduce material loss (kerf loss) while maintaining high throughput [5]. In light of these advantages, the use of laser slicing for wafer thinning has been proposed as a replacement for conventional grinding. The sequence of wafer thinning process is illustrated in Fig. 1 [6]. This method enables device re-manufacturing on the wafer left after laser slicing. By applying this method to SiC power devices, it is expected to reduce manufacturing costs and decrease the environmental impact associated with SiC sludge.
A primary concern regarding the application of laser slicing for SiC wafer thinning is its potential adverse impacts on the characteristics of SiC power devices. This paper comprehensively evaluates the impacts of the laser slicing technology on device characteristics. First, we systematically

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Fig. 1. An example of a wafer reutilization process applying laser slicing technology for wafer thinning.

Fig. 1. An example of a wafer reutilization process applying laser slicing technology for wafer thinning.

investigate the effects of focused laser irradiation on Junction Barrier Schottky (JBS) electrodes, which are sensitive to heat. Second, we apply the laser slicing technique to the thinning process of SiC MOSFETs and present their electrical characteristics in comparison to those fabricated using conventional grinding process, demonstrating that the laser slicing is a promising technique to replace grinding.

Impacts of Laser Irradiation on JBS Electrodes

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Sample Chip Preparation and Evaluation Procedure.

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

1200 V SiC JBS diodes were fabricated to examine the impacts of laser slicing. The schematic top view and 3D cross-sectional view of the sample JBS diode, along with the fabrication and evaluation flow of the JBS diodes, are shown in Fig. 2 and 3. An epitaxial layer was grown on the Si-face of a 6 -inch N -type 4H−SiC substrate with a 4∘ off-cut angle, and a JBS structure was formed on this epitaxial layer. Using a laser slicing apparatus, the laser beam was irradiated to the SiC wafer from the backside ( C -face), focusing it at the desired depth from the JBS electrodes. The focused laser beam was scanned along a line depicted in Fig. 2, generating a modified layer and line-shaped cracks within the wafers. The laser power was set at 2.5 W,5.0 W, and 7.5 W , and the distance between the laser focal point and the surface electrode was varied from 20μ m to 160μ m in 20μ m increments. Finally, a backside metal electrode was formed on the C -face, and the wafer was diced into sample JBS chips.

We measured the reverse characteristics (leakage current) of the sample JBS diodes as an indicator sensitive to the heat generated by laser irradiation. For samples exhibiting increased leakage current, emission microscopy (EMS) was employed from the backside of the samples. Using EMS, we can detect light emissions from current leakage points, allowing us to pinpoint the defective locations. After removing the anode and Schottky barrier electrodes (Ti), scanning electron microscopy (SEM) observation was performed to assess the surface morphology, followed by energy-dispersive X-ray spectroscopy (EDX) conducted at the leakage points.

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Fig. 2. (a) Top view and (b) 3D cross-sectional view of the fabricated 1200 V JBS diode.

Fig. 2. (a) Top view and (b) 3D cross-sectional view of the fabricated 1200 V JBS diode.

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Fig. 3. Fabrication and evaluation process flow of 1200 V JBS diodes.

Fig. 3. Fabrication and evaluation process flow of 1200 V JBS diodes.

Leakage Current Measurement and Analysis.

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

The reverse characteristics of the fabricated JBS diodes under laser power of 2.5 W,5.0 W and 7.5 W are shown in Fig. 4(a), (b) and (c), respectively. At 2.5 W , all the chips exhibited I-V curves almost identical to that without laser irradiation. At 5.0 W and 7.5 W , the chips with the focal point distances ranging from 60μ m to 140μ m also exhibited I-V curves comparable to that without laser irradiation. In contrast, increase in leakage current was observed for the samples with shorter focal point distances and higher laser power.

To clarify the relationship between the increase in leakage current and laser irradiation to the JBS diodes, EMS analysis was performed on the defective chips with leakage current. The light emission was clearly observed from the backside when the leakage current flew over around 10μ A. Optical and EMS images and the I-V curve taken during EMS analysis of the sample are shown in Fig. 5(a), (b), and (c). The laser irradiation conditions for this sample are a laser power of 5.0 W and a focal point distance of 40μ m. In Fig. 5(b), the dark line indicates the modified layer with internal cracks generated by the laser irradiation. At the center of the line (just above the laser focus scanning line),

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Fig. 4. Reverse characteristics of 1200 V JBS diodes with irradiated laser power at (a) 2.5 W , (b) 5.0 W , and (c) 7.5 W .

Fig. 4. Reverse characteristics of 1200 V JBS diodes with irradiated laser power at (a) 2.5 W , (b) 5.0 W , and (c) 7.5 W .

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Fig. 5. (a) Optical + EMS image of JBS with leakage current, (b) an enlarged view of the emission point in (a), and (c) I-V characteristics during the EMS analysis. Laser slicing for the sample was performed under a laser power of 5.0 W and a focal point distance of 40μ m.

Fig. 5. (a) Optical + EMS image of JBS with leakage current, (b) an enlarged view of the emission point in (a), and (c) I-V characteristics during the EMS analysis. Laser slicing for the sample was performed under a laser power of 5.0 W and a focal point distance of 40 μ m .

an emission is clearly visible when the leakage current flows. This result suggests that the laser irradiation is the direct cause for the pinpoint leakage current. To reveal the mechanism by which leakage current occurred, we examined JBS surfaces after etching electrodes. Fig. 6(a) shows an optical image of the JBS diode surface that is subjected to laser irradiation at a power of 7.5 W and a laser focal point distance from the surface of 20μ m. Cracks are visible inside the wafer along the line where the laser beam was scanned. Fig. 6(b) and (c) show SEM images of the chip edge and JBS area of the sample, respectively. It should be noted that there is no Ti deposition in the chip peripheral area shown in Fig. 6(b). Although no laser-induced melting marks are observed in Fig. 6(b), small melting marks are observed just on the laser irradiated point in Fig. 6(c). EDX spectra at the points, melting marks (i) and non-melting marks (ii), in Fig. 6(c) are shown in Fig. 7. EDX analysis revealed that detectable Ti exists exclusively at the melting marks after removal of the Ti electrode. This indicates that the melting marks are alloys including Ti , and that the presence of the Ti is a key factor to the formation of these melting traces, which generate leakage current paths.
To investigate the parameter range where melting traces, specifically current leakage points, are created, we systematically examined the sample surfaces after stripping the electrodes. The surface

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Fig. 6. (a) An optical image of the sample JBS chip after the removal of electrodes. Inner cracks are visible along the laser-irradiated line. (b) A SEM image of the chip edge including the laser-irradiated line. No melting marks are present in the area. (c) A SEM image of the surface in JBS area. Melting marks are visible on the laser-irradiated line. A laser power and a focal point distance from the Ti electrode are 7.5 W and 20μ m.

Fig. 6. (a) An optical image of the sample JBS chip after the removal of electrodes. Inner cracks are visible along the laser-irradiated line. (b) A SEM image of the chip edge including the laser-irradiated line. No melting marks are present in the area. (c) A SEM image of the surface in JBS area. Melting marks are visible on the laser-irradiated line. A laser power and a focal point distance from the Ti electrode are 7.5 W and 20 μ m .

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Fig. 7. EDX spectrum at the points indicated in Fig. 6(c): (a) melting marks (i) and (b) nonmelting marks (ii).

Fig. 7. EDX spectrum at the points indicated in Fig. 6(c): (a) melting marks (i) and (b) nonmelting marks (ii).

images of the JBS diodes observed by SEM are shown in Fig. 8. Melting traces were observed on the SiC surface directly above the laser irradiation line. It was found that the higher the laser power and the shorter the distance from the electrodes the larger the area of the melting trace tended to be.

Based on these results, we take the discussion a step further. When the Ti electrode does not exist, no trace was observed (Fig. 6(b)). This means that Ti electrodes absorb the laser light effectively, and it is converted to heat. As indicated in Fig. 7, Ti is detected in and around the melting traces. It is known that SiC and Ti can react to form silicide and the silicide formation can occur at relatively low temperatures (below 1100∘C [7]) compared to Ti melting point of 1668∘C, suggesting that the formation of alloy makes it easier to form melting marks. Fig. 9 schematically illustrates how melting marks are formed above laser focal points.

From Fig. 4, it is evident that no significant impact on electrical characteristics was detected when the focal point distance from the electrode exceeded 60μ m. Considering that the typical final wafer thickness for power devices is more than around 100μ m, it is possible to establish the laser irradiation conditions for laser slicing that does not affect device characteristics.

Application of Laser Slicing to SiC MOSFETs

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

Laser slicing was applied to the thinning of 1200 V SiC MOSFETs. The fabrication process flow for SiC MOSFETs is shown in Fig. 10. An epitaxial layer was grown on the Si-face of a 6-inch Ntype 4H−SiC substrate with a 4∘ off-cut angle, and a MOSFET structure was fabricated on it. Using a laser slicing apparatus, the laser beam was irradiated and focused inside the SiC wafer from the backside (C-face) at a depth of 140μ m from the MOSFET surface. The laser beam was scanned over the entire wafer, forming a modified layer and cracks inside the wafer. Then the wafer was split into two pieces. Images of the wafers observed from the top side before and after laser slicing are shown in Fig. 11(a), (b) and (c). No middle or large size defects such as cracks or chippings are visible on the laser-sliced wafers. The detached surfaces were subsequently ground to achieve a final thickness of 100μ m. Finally, a backside metal electrode was formed, and the wafer was diced into chips.

The main electrical characteristics of the MOSFETs, including the gate leakage current (IGSS), the threshold voltage ( Vth  ), the drain leakage current at 1200 V(IDSS), and the on-voltage ( VDS(ON) ), were measured. The results are shown in Fig. 12(a), (b), (c), and (d). The electrical characteristics of the MOSFETs thinned by the laser slicing process are compared to those thinned by the conventional grinding process. The IGSS remains very low for the laser-processed MOSFETs and the threshold voltage Vth  shows no significant change compared to MOSFETs thinned by conventional grinding, indicating that the gate oxide film was not damaged by the laser irradiation. Furthermore, no significant changes, including standard deviation, are observed for the IDSS. The VDS(ON) also shows no significant change, suggesting that the laser slicing process does not damage the drift layer or electrode. Overall, we observe no adverse impacts on MOSFET characteristics due to the laser slicing.

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Fig. 8. SEM images of the JBS sample surface on the laser-irradiated line with various laser conditions ((a)-(o)) after the removal of anode electrodes and Schottky barrier electrodes (Ti).

Fig. 8. SEM images of the JBS sample surface on the laser-irradiated line with various laser conditions ((a)-(o)) after the removal of anode electrodes and Schottky barrier electrodes (Ti).

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Fig. 9. Illustrative diagram depicting the impact on electrodes due to laser light irradiation during laser slicing.

Fig. 9. Illustrative diagram depicting the impact on electrodes due to laser light irradiation during laser slicing.

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Fig. 10. 1200 V MOSFET fabrication process flow.

Fig. 10. 1200 V MOSFET fabrication process flow.

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Fig. 11. Top surface images of wafers: (a) before laser slicing, (b) with device structures after laser slicing, and (c) without device structures after laser slicing.

Fig. 11. Top surface images of wafers: (a) before laser slicing, (b) with device structures after laser slicing, and (c) without device structures after laser slicing.

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Fig. 12. Comparison of the main electrical characteristics ((a) IGSS, (b) Vth , (c) IDSS, and (d) VDS(ON) ) of the MOSFETs thinned by laser slicing and grinding only. Error bars represent ±1σ.

Fig. 12. Comparison of the main electrical characteristics ((a) I G S S , (b) V th , (c) I D S S , and (d) V D S ( O N ) ) of the MOSFETs thinned by laser slicing and grinding only. Error bars represent ± 1 σ .

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

We investigated the laser slicing technique as an alternative to grinding for thinning SiC wafers. The impacts of focused laser light onto the SiC wafers were examined using test devices with JBS electrodes, whose characteristics are sensitive to heat. Measurements of leakage current revealed that higher laser power and shorter distances between the laser focus and JBS electrodes (below 60μ m ) increased leakage current. SEM observation and EMS analysis revealed that the heat from the laser beam creates melting traces on the SiC surface, generating leakage current paths. However, these results suggest that by selecting the appropriate laser irradiating parameters, laser slicing can be applied to the fabrication of SiC power devices. Based on our findings, SiC MOSFETs were experimentally fabricated utilizing the laser slicing technique. The performance of the MOSFETs exhibited no significant differences when compared to those fabricated using the conventional grinding technique. These results demonstrate that the laser slicing is a promising SiC wafer thinning technique replacing grinding.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.25.pdf

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This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 33-40

doi: 10.4028/p-uAfni2

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-31

Accepted:
2026-02-23

Online:
2026-05-21

A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

The original version of this paper is available on https://www.scientific.net/MSF.1193.33.pdf

Myung-Beom Park 1,a*, Jungwon Kim 1,b, Yigil Cho 1,c, Yun Ho Kim 1,d, Sam-Jong Choi 1,e

1 Samsung Electronics Co., Ltd., 1, Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do, 18448, South Korea

a* m.b.park@samsung.com, b  jwon88.kim@samsung.com, c  yigil.cho@samsung.com, d  yunho17.kim@samsung.com, e  wafer@samsung.com

Keywords: SiC powders, Si-based materials, synthesis of Si and SiC, recycling of by-products.

Abstract

This study delves into the synthesis of high-purity SiC powders utilizing two distinct silicon (Si) sources of recycled Si wafers and back-grind wastewater-both of which are abundant byproducts in semiconductor manufacturing processes. The synthesis involved the high-temperature reaction of these Si sources with ultra-high-purity graphite ( >6 N ) at temperatures exceeding 2100∘C. The resulting α-phase SiC powders derived from previously used Si wafers demonstrated unparalleled quality, achieving a purity level surpassing 99.9999% and exhibiting particle sizes exceeding 500 μm. These characteristics render them highly suitable for the fabrication of SiC wafers, a cornerstone of advanced semiconductor applications. This research underscores the potential of leveraging industrial by-products as sustainable Si sources for SiC synthesis, highlighting the superiority of α phase SiC produced from recycled Si wafers in high-purity applications.

1. Introduction

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Silicon carbide ( SiC ) has cemented its position as a cornerstone material in modern power electronics, owing to its unparalleled electrical and thermal properties [1]. These attributes, including its wide bandgap, high thermal conductivity, and superior mechanical strength, make SiC an ideal candidate for high-performance power semiconductor devices, such as Schottky diodes, MOSFETs, and IGBTs[2, 3]. However, the success of SiC-based devices is intricately linked to the quality and consistency of SiC wafers, which are directly dependent on the purity and physical properties of the precursor materials used in their fabrication [4-7]. Achieving a stable supply chain for these precursors is critical to meeting the growing demand for SiC technology in electric vehicles (EVs), renewable energy systems, and other power electronics applications [8].

The quality of SiC wafers is fundamentally determined by the characteristics of the precursor materials, particularly the SiC powders used as the foundational raw material [4]. High-purity SiC powders with consistent particle sizes and controlled crystalline phases are essential for producing wafers with the desired electrical conductivity, thermal stability, and mechanical integrity [9,10]. Any impurities or deviations in the powder properties can lead to defects in the SiC lattice structure, compromising the performance and reliability of the final semiconductor devices [9]. Therefore, the development of high-quality SiC powders is a cornerstone of advancing SiC wafer manufacturing and ensuring the long-term success of power semiconductor technologies.

The rapid increase in silicon sludge generated is a significant trend accompanying in from silicon solar cell manufacturing [11,12]. This by-product, rich in silicon content, presents a valuable opportunity for recovery and utilization across various industries, including semiconductors, where high-purity silicon is essential for wafer fabrication and device manufacturing. Additionally, silicon sludge can be processed into fine powders, which serve as a sustainable source of silicon for the production of silicon carbide (SiC) powders-a critical material in power electronics and semiconductor devices. By integrating these by-products into the silicon supply chain, industries can reduce reliance on virgin raw materials, enhance process efficiency, and contribute to environmental sustainability. Cutting is achieved by abrasive slurry, which consists of suspension silicon carbide
particles. During the process of wafer cutting almost 50% of silicon is lost in the sludge [13]. Several attempts were made to recycle the silicon sludge retrieved from the wire saw machines. However, there are no high successful results reported so far.

In the semiconductor industry, silicon is extracted from used wafers and back-grind wastewater, offering a reliable and sustainable source for SiC synthesis. These advancements in material recovery and processing not only optimize resource utilization but also align with the growing demand for high-performance materials in applications such as power electronics, electric vehicles (EVs), and renewable energy systems. By leveraging silicon sludge and other by-products, industries can achieve a more circular and efficient supply chain, supporting both economic and environmental objectives.

To address the challenges of obtaining high-quality SiC powders while ensuring a stable supply chain, this study explored the potential of utilizing semiconductor process by-products as sustainable raw materials for SiC wafer fabrication. Silicon by-products such as used Si wafers and back-grind wastewater, are readily available in semiconductor manufacturing facilities and offer a promising source of high-purity Si. These by-products can be processed into silicon powders, which can then be synthesized into SiC powders for SiC wafer production. By capitalizing on these readily available materials, manufacturers can reduce reliance on virgin raw materials, minimize waste generation, and enhance the environmental sustainability of SiC production processes. In detail, this research investigated the preparation and characterization of SiC powders derived from two distinct Si sources: used Si wafers and back-grind wastewater. Used Si wafers, which are inherently high-purity and large-particle materials, were crushed to produce fine Si powders, while back-grind wastewater, a byproduct of wafer back-grinding, was processed to extract Si through solvent evaporation and milling. The resulting Si powders were then synthesized into SiC powders under carefully controlled conditions, with the aim of evaluating their suitability for SiC wafer manufacturing.

This study underscores the critical importance of optimizing precursor materials and supply chain management in the advancement of SiC wafer fabrication and power semiconductor technology. By leveraging semiconductor process by-products as sustainable raw materials, manufacturers can significantly enhance the efficiency, cost-effectiveness, and environmental sustainability of SiC production processes.

2. Experimental

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In order to recycle these generated silicon in semiconductors and other industries, it is important to find a best methods for the solidified powder form Si solution. Two powders prepared from different methods is various, as shown in Fig.1. Si powder was prepared by crushing from the used Si wafer, as shown in Fig. 1(a). On the other hand, as for the method of recycling silicon wastewater, as shown in Fig. 1.(b), typical method of making solid silicon from various silicon byproducts is a method of solidifying a Si solution by forming a solid phase using a filter press with a silicon solution as shown in Figure 2. Specifically, a method of forming a silicon cake by extracting deionized water

Processed Wafer

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Fig. 1. (a) Cleaned wafer and back-grinding process and in semiconductor processes.

Fig. 1. (a) Cleaned wafer and back-grinding process and in semiconductor processes.

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Fig. 2. Methods of Si powders prepared from the Si solution.

Fig. 2. Methods of Si powders prepared from the Si solution.

from a silicon solution is typical, and silicon cake can be dried to finally produce silicon powder. This study focuses on the synthesis and evaluation of silicon carbide ( SiC ) powders derived from two distinct silicon (Si) sources (used Si wafers and back-grind wastewater) for SiC wafer. Two different SiC powders were prepared by reaction of both Si powders with pure graphite (purity >6 N ) at over 2100∘C. Key objectives include analyzing the purity, particle size, and crystalline phases of the resultant SiC powders, as well as exploring their applications in semiconductor SiC devices manufacturing. Advanced analytical techniques, including energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM), were employed to investigate the composition and structural properties of the Si and SiC materials.

3. Results & Discussion

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3.1 Characterization of Si Powders and Optimization of SiC Powder Synthesis for Semiconductor Applications

Si powders derived from back-grind wastewater yielded larger particle sizes (around 1μ m ), which SiC powders are less suitable for advanced SiC wafer applications. The primary constituents of silicon (Si) powders derived from back-grind wastewater were confirmed through energy-dispersive X-ray spectroscopy (EDX) to be Si,O, and C , as illustrated in Figure 3(a). X-ray photoelectron spectroscopy (XPS) further revealed the presence of SiOx phases, indicative of an amorphous structure, as shown in Figure 3(b). These findings suggest that the surface of the Si powders interacted with ambient oxygen forming SiOx layers that significantly influenced their reactivity and applicability, as depicted in Figure 3(c).

In contrast, Si powders were successfully synthesized from used Si wafers with small oxidation

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Fig. 3. Chemical composition results of Si powders: (a) EDX results, (b) and XPS results. And then, a schematic diagram of Si powders coated oxidized and carbonized Si as shown in (c).

Fig. 3. Chemical composition results of Si powders: (a) EDX results, (b) and XPS results. And then, a schematic diagram of Si powders coated oxidized and carbonized Si as shown in (c).

Table I. Characteristics of Si Powders Prepared Using Various Methods.

under 0.1%, characterized by particle sizes around 100μ m, as shown in Table I. These attributes make them highly suitable for SiC wafer fabrication, aligning with the stringent requirements of power semiconductor manufacturing.

The quality of SiC powders, which are critical raw materials for SiC wafer manufacturing in power semiconductors, is determined by several key factors, including metal impurities and physical properties. High-quality Si powders are essential for achieving the purity and structural integrity required for SiC wafers. As such, the quality of Si powders and their supply chain management (SCM) are paramount for the success of SiC power semiconductor manufacturing. Obtaining Si powders from semiconductor processes, particularly through Si wafer back-grinding, is a promising approach to ensure the quality and consistency of SiC powders.
To evaluate the feasibility of Si powder synthesis from Si by-products, this study prepared Si powders using Si generated within a semiconductor company. In order to compare the quality of the synthesized Si powder, Si prepared for each raw material was analyzed, as shown in Table I. The results demonstrated that the Si powders prepared from used Si wafer exhibited superior quality, exceeding the performance of conventional raw materials. The size of Si powder over 80 um prepared from the used Si wafer, as shown in Table I with under 0.1% oxidation. These powders were further assessed at a SiC powder mass production facility, and their suitability for SiC wafer fabrication was confirmed. From used Si wafers, high-purity Si powders were successfully synthesized.

This research highlights the potential of leveraging silicon by-products from semiconductor processes as sustainable raw materials for SiC powder synthesis. By securing high-quality SiC powders from used Si wafers, manufacturers can improve the efficiency and scalability of SiC wafer production, ultimately enhancing the performance of power semiconductor devices.

3.2. High-Purity α-Phase SiC Powders and Their Role in SiC Wafer Fabrication and Semiconductor Device Enhancement

The intrinsic properties of SiC powders are pivotal in determining their suitability for SiC wafer fabrication and the subsequent performance of semiconductor devices. High-purity α-phase SiC powders, specifically those derived from crushed Si wafers, exhibit a remarkable combination of characteristics that make them exceptionally well-suited for SiC wafer production, as shown in Fig.4. These powders possess particle sizes exceeding 500μ m, which not only enhance the structural integrity of the wafers but also facilitate efficient processing during manufacturing in Table II. Furthermore, their purity levels exceeding 99.9999% ensure minimal impurity incorporation, which is critical for achieving high-quality SiC wafers with superior electrical and thermal properties, as

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Fig. 4. XRD of two Size distribution of two different SiC powders prepared from different methods of filtered powder from back-grinding Si and crushed powders from process wafer in semiconductor industries.

Fig. 4. XRD of two Size distribution of two different SiC powders prepared from different methods of filtered powder from back-grinding Si and crushed powders from process wafer in semiconductor industries.

shown in Table II. These attributes align seamlessly with current manufacturing workflows, enabling manufacturers to integrate SiC powders into existing production processes without significant modifications. This compatibility ensures a smooth transition to scalable SiC -based power device production, which is essential to meet the growing demands of the electric vehicle (EV) and renewable energy sectors. The large particle sizes of the α-phase SiC powders also contribute to reducing processing times and material waste, further enhancing the economic viability of SiC wafer fabrication.

Conversely, Si powder obtained from backgrind wastewater showed oxidation ratio ( 16% ) of 1.7 μm in size, causing the problem of producing β-phase SiC , which is essential for SiC wafer applications, as shown in Fig. 4. The study highlights the critical role of SiC powder quality in determining the performance of SiC -based devices. Si powders from back-grind wastewater, though viable for certain applications, were found to be less effective for SiC wafer production. Si powders derived from back-grind wastewater present notable challenges for SiC wafer applications. These powders typically exhibit smaller particle sizes (~1.7μ m), which can lead to increased aggregation and poor sinterability, resulting in lower-quality wafers. Additionally, their higher oxidation ratios ( 16% ) introduce oxygen impurities that can adversely affect the electrical properties of the final SiC devices. These characteristics render them less suitable for high-performance SiC wafer fabrication, though they may still find utility in applications where material cost and processing efficiency are prioritized over ultimate device performance.

In the realm of SiC wafer fabrication, high-purity α-phase SiC powders derived from polished Si wafers stand out as a highly promising material for SiC wafer production [9,10]. These powders, with their exceptional purity levels exceeding 99.9999% and particle sizes exceeding 500μ m, offer distinct advantages that align with modern manufacturing requirements for SiC -based power devices. Their superior quality ensures compatibility with existing production workflows, enabling manufacturers to seamlessly integrate advanced materials into current processes without the need for significant modifications. This characteristic is particularly valuable in the context of scalability, as it allows for the efficient and cost-effective production of high-performance SiC wafers, which are increasingly in demand for applications in electric vehicles (EVs), renewable energy systems, and other power electronics sectors. The use of α-phase SiC powders derived from polished Si wafers also enhances the intrinsic properties of the resulting SiC wafers, such as electrical conductivity, thermal stability, and mechanical strength. These improvements directly contribute to the performance of power semiconductor devices manufactured using these wafers, such as Schottky diodes, MOSFETs, and IGBTs. By leveraging the high purity and large particle sizes of these powders

Table II. Characteristics of SiC Powders.

manufacturers can achieve wafers with minimal impurities, which is critical for maintaining the integrity of the lattice structure and ensuring optimal device characteristics. Furthermore, the scalability of SiC-based power devices is significantly enhanced, as these wafers can be processed using established manufacturing techniques, thereby reducing the time and cost associated with process development and implementation.

Si powders derived from back-grind wastewater, despite their potential as sustainable raw materials, fall short of meeting the stringent requirements for SiC wafer fabrication. These powders typically exhibit smaller particle sizes ( ~1.7μ m ) and higher oxidation ratios ( 16% ), which lead to challenges in achieving the desired purity and structural integrity for high-performance SiC wafers. The increased particle aggregation and poor sinterability associated with these powders result in wafers that are less suitable for applications requiring exceptional electrical and thermal properties.

However, these Si powders still offer viable alternatives for applications where material cost and processing scalability are prioritized over ultimate device performance. For instance, they can be utilized in lower-cost SiC devices or as part of hybrid manufacturing processes that combine different SiC powder sources to optimize material utilization and cost-effectiveness. Therefore, high-purity α phase SiC powders derived from polished Si wafers represent a transformative solution for SiC wafer fabrication, offering superior quality, compatibility with existing workflows, and scalability for SiCbased power devices. These materials not only enhance the performance of the final devices but also align with the sustainability goals of the semiconductor industry by leveraging by-products from existing fabrication processes. While Si powders from back-grind wastewater may have limitations for high-performance SiC wafer applications, they provide valuable alternatives for specific use cases, demonstrating the diverse potential of Si -based materials in advancing semiconductor technology.

As you know, general Si wafer were doped with n-type or p-type dopant I used this doped wafer for preparation of SiC powder. The doping depth is very shallow and very low concentration, compared to that bulk wafer thickness and Si bulk atomic concentration. I did not any action for removing this doping amount for pure SiC powders. I checked the main doping amount. I do not observe remarkable impurities depending on doping amount in Table II.

3.3. Properties of SiC Powders and Their Impact on SiC Wafer Fabrication and Device Performance

The intrinsic properties of SiC powders are pivotal in determining their suitability for SiC wafer fabrication and the subsequent performance of semiconductor devices. High-purity α-phase SiC powders, specifically those derived from crushed Si wafers, exhibit a remarkable combination of characteristics that make them exceptionally well-suited for SiC wafer production. These powders possess particle sizes exceeding 500μ m, which not only enhance the structural integrity of the wafers but also facilitate efficient processing during manufacturing.

Conversely, Si powders derived from back-grind wastewater present notable challenges for SiC wafer applications. These powders typically exhibit smaller particle sizes (~1.7μ m), which can lead to increased aggregation and poor sinterability, resulting in lower-quality wafers. Additionally, their higher oxidation ratios ( 16% ) introduce oxygen impurities that can adversely affect the electrical properties of the final SiC devices. These characteristics render them less suitable for highperformance SiC wafer fabrication, though they may still find utility in applications where material cost and processing efficiency are prioritized over ultimate device performance.

4. Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1193.33.pdf

Silicon carbide (SiC) has emerged as a pivotal material in modern power electronics due to its exceptional electrical and thermal properties, making it essential for high-performance semiconductor devices. However, the production of SiC wafers relies heavily on the quality and purity of precursor materials, which directly impact the performance of the final products. This study explores the synthesis and characterization of SiC powders derived from two distinct silicon (Si) sources: used Si wafers and back-grind wastewater. These by-products, readily available in semiconductor manufacturing, were selected as potential raw materials for SiC wafer fabrication. The research focuses on optimizing the production process to maximize the quality of SiC powders. High-purity α-phase SiC powders were successfully synthesized from used Si wafers, exhibiting exceptional purity ( >99.9999% ) and large particle sizes ( >500μ m ), making them highly suitable for SiC wafer manufacturing. Conversely, Si powders obtained from back-grind wastewater, while similar in size of 1.7μ m, showed higher oxidation ratios ( 16% ) and were less effective in producing α-phase SiC, which is essential for SiC wafer applications. The study highlights the critical role of SiC powder quality in determining the performance of SiC-based devices. High-purity α-phase SiC powders derived from used Si wafers demonstrated outstanding compatibility with existing manufacturing workflows, supporting the scalability of SiC-based power electronics. By controlling the characteristics of SiC powders from Si raw materials to SiC devices, this study contributes to advancing Si-based material technology and enhancing the performance of power semiconductor devices. The findings provide valuable insights for optimizing SiC wafer fabrication processes, ensuring a stable supply chain, and meeting the growing demand for high-performance SiC materials in power electronics.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.33.pdf

P.J. Wellmann, Semicond Sci Technol, 33, 103001 (2018).

G. Grant, S. Villastefan, Nature Electronics, 6(2), 64-73 (2023).

Y. H. Park, C. H. Byeon, J. H. Kim, Journal of Electronic Materials, 51, 2684 (2022).

S. Zhang, Y. Ren, X. Yang, W. Ma, H. Chen, et. al., J. Mat. Res. & Tech., 34, 2593 (2025).

J. M. Fernández, A. Muñoz, A.R. de A. López, et. al., Acta Mater, 51, 3259 (2003).

J. Lamon, Comprehensive Nuclear Materials, 2, 323 (2012).

H. Sakidin, M.A.H. M. Sohor, et al., UTP-UMP Sympos. Ener. Sys., 131, 04003 (2017).

Chopra, S. and Meindl, P. Supply Chain Management: Strategy, Planning, and Operation. Prentice-Hall, Upper Saddle River, NJ. (2001).

J. G. Kim, E. J. Jung, Y. Kim, Y. Makarov, D. J. Choi, Ceramics Inter., 40, 3953 (2014).

E. Jung, M. H. Lee, Y. J. Kwon, et al., J. Kor. Cryst. Growth & Cryst. Tech., 27, 57 (2017).

W. T. Kwon, S. R. Kim, Y. H. Kim, Y. J. Lee, E. J Jung, W.-K. Park, S. C. Oh, Mat. Sci. For. 724.49 (2012).

Y.H. Kim, E.B. Kim, S.R. Kim, M.H. Suh, D.J. Choi, W.T. Kwon Adv. Mater. Res. 26-28, 271 (2007).

R.A. Andrievski, Rev. Adv. Mater. Sci. 22, 1 (2009).

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The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 41-45

doi: 10.4028/p-BAyAw0

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2025-12-23

Accepted:
2026-03-16

Online:
2026-05-21

Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Yuken Matsumura 1,a*, Shunto Iden 1, b, Daisetsu Toh 1,c, Jumpei Yamada 1, d and Yasuhisa Sano 1,e

1 Department of Precision Engineering, Graduate School of Engineering, The University of Osaka, Osaka, Japan

a*y.matsumura@up.prec.eng.osaka-u.ac.jp, b  iden@up.prec.eng.osaka-u.ac.jp, ctoh@prec.eng.osaka-u.ac.jp, d  yamada@prec.eng.osaka-u.ac.jp, e  sano@prec.eng.osaka-u.ac.jp

Abstract

Plasma chemical vaporization machining (PCVM) is a high-rate etching method that uses atmospheric-pressure plasma. Its application to the plasma dicing of SiC wafers is anticipated. However, since the reaction is mainly driven by neutral radicals, it is difficult to maintain anisotropy, and issues such as side etching are of concern. In this study, PCVM processing was performed using SF6 gas with a Ni mask to investigate vertical and lateral etching behaviors. We achieved vertical etching of 100μ m within approximately 35 minutes, and lateral side etching of about 50μ m. The lateral etch rate remained nearly constant, whereas the vertical etch rate was initially high but decreased as the etching progressed, approaching the lateral rate. Finite element-based electrostatic field analysis revealed that, as the etching depth increased, electric field shielding by the mask weakened the field at the bottom of the trench, leading to a transition toward neutral radicaldominated reactions.

Keywords: plasma chemical vaporization machining, atmospheric-pressure plasma, etching, dicing, SF6, damage-free, time dependance.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

In semiconductor device manufacturing, wafer dicing is an indispensable process. SiC has attracted significant attention as a material for power devices; however, due to its high hardness and brittleness, conventional mechanical dicing using diamond blades often introduces defects and cracks, leading to reduced chip strength and yield. Laser-based dicing techniques, such as laser thermal dicing and stealth dicing, have also been explored as non-contact alternatives; however, they involve localized thermal modification or internal damage layers, which may induce residual stress and microcracks, thereby limiting the mechanical reliability of SiC chips. In contrast, plasma dicing-non-contact and damage-free processing using plasma-has already been put into practical use for silicon. Nevertheless, when applied to SiC , the removal rate is too slow for practical implementation. To address this issue, we propose the application of plasma chemical vaporization machining (PCVM) [1,2]-a high-pressure plasma process operating in the kPa -to-atmospheric-pressure range-to SiC dicing. PCVM removes material through chemical reactions using high-density radicals generated in atmospheric-pressure plasma. Owing to its non-contact nature, it suppresses cracks and chipping while enabling high-rate processing. It has previously been reported that a high etching rate of approximately 15μ m/min can be achieved on 2-inch SiC wafers [2]. In our previous work, we conducted etching experiments with varying metal mask widths and demonstrated that the etch rate decreases with narrower mask openings and deeper trenches. However, due to the limited durability of the masks, the etching depth was restricted to about 40μ m, which prevented sufficient evaluation of the time dependence of side etching or detailed electrostatic field analysis [3]. In this study, we applied PCVM to SiC wafers covered with a thick, durable Ni mask prepared by electroplating. By systematically measuring the trench depth and lateral progression as a function of processing time, we evaluated the development of side etching and the evolution of anisotropy. In
addition, finite element analysis was employed to examine the electrostatic field distribution, and the observed decrease in the electric field at the trench bottom was interpreted as being attributable to mask-induced field shielding. Through this approach, we clarified the side etching behavior in SiC plasma dicing and provided a fundamental investigation toward its practical application.

Experimental Procedure

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Figure 1 shows a schematic of the PCVM processing system. The sample was prepared by cutting a commercially available n-type 4H-SiC wafer into pieces of 10×20 mm2; the ( 0001― ) surface, corresponding to the back side of devices, was used as the processing surface. As the mask, a 100 nm-thick Ni metal layer was first deposited via vacuum evaporation, followed by electroplated Ni growth to a thickness of approximately 0.7μ m. To confine the plasma irradiation region, the mask was patterned with a cross-shaped slit opening about 50μ m wide. To prevent arc discharge during processing, the aluminum sample stage was coated with yttria via thermal spraying, to provide surface insulation and serve as a protective coating. The electrode was a water-cooled aluminum alloy plate with a diameter of approximately 2 inches in which numerous micro holes for gas injection were distributed on the surface facing the sample. A 13.56−MHz RF power supply was employed for plasma generation. The process gas was pure SF6, supplied at a flow rate of 250 sccm . The chamber pressure was maintained at 2.5 kPa , with an electrode-to-sample distance of 1.7 mm and an applied RF power of 1200 W .

The experimental procedure was as follows: The chamber was first evacuated with a dry pump down to approximately 30 kPa , after which SF6 was introduced to reach 2.5 kPa . The pressure was then kept at 2.5 kPa by adjusting the exhaust valve opening. RF voltage was applied between the plasma-generating electrode and the sample to ignite the plasma, and etching was carried out. Processing times were set to 5 or 10 minutes, and etching followed by evaluation was repeated multiple times. For post-process evaluation, the vertical etch depth was measured using a confocal laser scanning microscope (LEXT3000, Olympus). The lateral etch amount was determined using a scanning electron microscope (S-4800, Hitachi) to observe the cross-shaped mask opening from an oblique angle, as shown in Fig 2. To aid in the interpretation of the results, electrostatic field simulations were performed using the two-dimensional finite element analysis software E-STAT (Field Precision LLC) [4].

[picture]

Fig. 1. PCVM experimental apparatus.

Fig. 1. PCVM experimental apparatus.

[picture]

Fig. 2. Method for measuring side etching.

Fig. 2. Method for measuring side etching.

Results and Discussion

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Removal rate.

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Figures 3 and 4 show the time evolution of etch depth and etch rate. In this experiment, vertical etching to a depth of 100μ m-comparable to the thickness of thinned wafers after backside thinning-was successfully achieved within approximately 35 minutes. As for the amount of side etching accompanying the vertical etch, cross-sectional SEM images (Fig. 5) revealed that, after 35 minutes, lateral etching beneath the mask reached up to approximately 50μ m. Focusing on the time dependence of the etch rates, the lateral etch rate remained almost constant regardless of etching duration, whereas the vertical etch rate exhibited a pronounced time variation. Specifically, the vertical etch rate was initially very high, but gradually decreased as etching proceeded, eventually converging to a value comparable to that of the lateral etch rate.

[picture]

Fig. 3. Time evolution of removal amount (red: lateral, blue: vertical).

Fig. 3. Time evolution of removal amount (red: lateral, blue: vertical).

[picture]

Fig. 4. Time evolution of removal rate (red: lateral, blue: vertical).

Fig. 4. Time evolution of removal rate (red: lateral, blue: vertical).

[picture]

Fig. 5. Cross-sectional SEM image of the processed sample ( 600× magnification).

Fig. 5. Cross-sectional SEM image of the processed sample ( 600 × magnification).

Electrostatic field analysis.

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

To elucidate the physical factors underlying this behavior, two-dimensional finite elementbased electrostatic field analyses were performed to calculate the field distribution within the etched trench. Fig. 6 shows an example of the calculated distribution at a trench depth of 100μ m. The trench depth varied from 0 to 100μ m, in 10−μm increments, and the electric field intensity at the trench bottom was extracted; the results are summarized in Fig. 7, illustrating the quantitative relationship between trench depth and bottom field intensity. At the early stage of etching, the high vertical etch rate can be attributed to the strong electric field formed between the electrode and the sample when the trench was shallow and close to the surface. In this region, ions were slightly accelerated by the near-surface electric field and bombarded the sample surface, thereby promoting material removal reactions and resulting in rapid vertical etching. It has been reported elsewhere that, in SiC , even slightly accelerated ions can enhance the etching reaction [5]. In our experiment, the estimated ion energy, derived from the field strength and mean free path, was below 2 eV , suggesting that physical damage to the sample was negligible. As the etching progressed and the trench deepened, however, the electric field intensity at the trench bottom was found to decrease, due to the shielding effect of the mask structure. Consequently, ions were less able to reach and be accelerated at the bottom, and the dominant reactive species gradually shifted to neutral radicals. Unlike ions, neutral radicals are unaffected by electric fields; therefore, the etching proceeded isotopically. This explains the observed trend in which the vertical etch rate approached the lateral etch rate over time. From these results, we could demonstrate that, in the plasma etching of SiC using the PCVM method, the strong electric field present in the initial stage plays a crucial role in achieving high vertical etch rates. As etching proceeds and the bottom field intensity diminishes, the etching mechanism transitions to radicaldominated isotropic etching. Future studies should focus on optimizing processing conditions to maintain higher anisotropy while achieving fast and precise SiC dicing.

[picture]

Fig. 6. Electrostatic field analysis example (trench depth: 100μ m ).

Fig. 6. Electrostatic field analysis example (trench depth: 100 μ m ).

[picture]

Fig. 7. Electric field distribution at each etch depth.

Fig. 7. Electric field distribution at each etch depth.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

In this study, PCVM was applied to SiC wafers with patterned mask openings, and damagefree dicing with a vertical etch depth of 100μ m was successfully demonstrated within approximately 35 minutes. We observed a decrease in the vertical etch rate accompanied by an increasing depth. which was mainly attributable to the reduction of ion contributions caused by electric field attenuation. Future work will systematically investigate the effects of plasma generation conditions - such as pressure, electrode configuration, and RF power - on both vertical and lateral etch rates, with the aim of optimizing dicing conditions to achieve greater anisotropy in SiC etching.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.41.pdf

Y. Mori, K. Yamauchi, K. Yamamura, and Y. Sano. Rev. Sci. Instrum. 71, 4627-4632 (2000).

Y. Sano et al. ECS J. Solid State Sci. Technol. 10, 014005 (2021).

Y. Sano et al. Mater. Sci. Forum 1124, 51-55 (2024).

E-Stat: Electric Field Distribution Simulation Tool, Field Precision LLC. [Online]. Available: .

S. Iden, Y. Matsumura, J. Yamada, D. Toh, K. Yamauchi, and Y. Sano. "Basic study of plasma dicing for SiC wafer using high-pressure plasma," presented at the 20th International Conference on Precision Engineering (ICPE2024), Oral, GS17-05, Tohoku University Aobayama Campus, Miyagi, Japan, Oct. 23-26, 2024.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 47-54

doi: 10.4028/p-3CfRaK

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-06

Accepted:
2026-03-21

Online:
2026-05-21

Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

David M. Lynch 1,a*, Gregory L. Keaton 1,b, Christopher A. Lee 2,c and Alexander T. Bean 3,d

1 Halo Industries, 3270 Scott Blvd., Santa Clara, CA 95054, USA

2 Corning Incorporated, 60 O'Connor Rd., Fairport, NY 14450, USA

3 Landmark Measurement Solutions Inc., 9990 Coconut Rd., Estero, FL 34135, USA

a* david.lynch@halo-industries.com, b  greg@halo-industries.com, c  leeca@corning.com, dalex@landmarkmeasurement.com

Keywords: total thickness variation (TTV), frequency scanning interferometry, refractive index homogeneity.

Abstract

Accurate total thickness variation (TTV) measurement is essential for silicon carbide (SiC) wafer manufacturing and process control. This work evaluates the accuracy of interferometric TTV measurements using the Corning Tropel FlatMaster MSP system, benchmarked against a dual-source chromatic white light (CWL) profilometer. We investigate the influence of spatial refractive index variation on interferometric accuracy by comparing MSP and CWL results. The analysis reveals high MSP repeatability with small deviations linked to index variation. These trends provide a framework for interpreting interferometric TTV data and improving metrology practices for SiC substrates.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

The rapid growth of power and optoelectronic devices has positioned silicon carbide ( SiC ) as a critical semiconductor valued for its wide bandgap, high thermal conductivity, and high breakdown field strength. As demand accelerates, particularly for larger-diameter substrates, efficient and scalable manufacturing becomes essential.

SiC wafer production faces persistent challenges. Mechanical wire sawing introduces kerf loss, residual stress, and geometric distortions such as bow, warp, and total thickness variation (TTV). Post-processing steps like grinding and chemical mechanical polishing (CMP) can mitigate these effects but add material loss. Emerging laser-based wafering methods aim to minimize kerf loss and stress-induced deformation; such approaches are under development by Halo Industries and others.

Accurate wafer geometry measurement is crucial for process control and device yield. Chromatic white light (CWL) profilometry provides direct thickness mapping by measuring both wafer surfaces, but its scanning nature limits speed and spatial resolution. Interferometric systems, such as the Corning Tropel FlatMaster MSP, enable rapid, full-field measurements with high sampling density [1,2].

However, interferometry depends on the substrate's refractive index to convert optical path distance into physical thickness. Variations in index arising from doping or other local inhomogeneities introduce systematic errors. While these effects are recognized, existing studies of these dependencies are sparse and often restricted to single-wavelength data [3].

This work evaluates interferometric TTV measurements of 4H−SiC wafers on the MSP, benchmarked against a dual-source CWL profilometer. We quantify refractive index effects across both intentional doping levels (semi-insulating to heavily doped) and unintentional material variations (e.g., near basal facet regions). Results demonstrate high MSP repeatability and systematic deviations linked to index variation, offering more robust TTV metrology in SiC manufacturing.

Experimental Plan

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Samples.

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We analyzed the thickness and optical properties of 4H−SiC wafers fabricated by Halo Industries' laser-based wafering method. Most samples were 150 mm device-grade n-type wafers ( N -doped, 1924 mΩ· cm ) with a 4∘ miscut toward [ 1120 ]; five were 200 mm optical-grade, undoped, and without miscut.

Measurement Methods.

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Interferometric thickness was measured by frequency-scanning interferometry on a Corning Tropel FlatMaster MSP 300 with an 830 nm laser. Results were benchmarked against physical thickness measured using a Camtek FRT Microprof MHU, equipped with dual chromatic white light (CWL) sensors for simultaneous mapping of the top and bottom surfaces.

The MSP collects 128 interferograms while stepping the laser from 825−835 nm. A Fourier transform yields spectra with peaks from different surface pairs [Fig.1(a)]. The location of each peak in Fourier space gives the optical path difference (OPD) between the two surfaces, where the OPD is defined as:

OPD=ng·t(1)

where ng is the group index and t is the distance between surfaces. Therefore, the Fourier spectrum can be used to calculate the thickness of the sample if the group index is known. Since illumination is nearly parallel to the crystallographic c-axis, the ordinary group index is appropriate for MSP thickness calculations [5, 6]. For initial calculations, we assumed an ng of 2.690 , and any residual index error was corrected by calibration against CWL thickness measurements:

[picture]

Fig. 1. (a) Schematic of the MSP measurement [4]. Fourier spectrum of the interference patterns shows peaks from different surface pairs. (b) MSP stack with an optical flat, enabling independent measurement of wafer thickness and group index via additional surface pairs.

Fig. 1. (a) Schematic of the MSP measurement [4]. Fourier spectrum of the interference patterns shows peaks from different surface pairs. (b) MSP stack with an optical flat, enabling independent measurement of wafer thickness and group index via additional surface pairs.

Refractive Index Verification.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Refractive index verification was performed using two independent methods. Phase index was measured at 632.8 nm with a Metricon prism-coupler (TE-polarized HeNe laser). Group index at 950 nm was measured on a custom MSP with a 950 nm laser and optical flat [Fig. 1(b)], enabling independent determination of thickness and index.

Optical Retardance.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Optical retardance maps were collected with an Ilis StrainScope Stepper 200. For doped wafers with a 4∘ tilt, samples were physically tilted ~12∘ toward [1120] to align with the optic axis and suppress intrinsic birefringence. The measured retardance therefore primarily reflects stress-induced birefringence.

MSP vs. CWL Thickness Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Measurement Overview.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Fig. 2(a) shows an MSP thickness map of a CMP-processed 150 mm doped wafer measured in ~30 s ( 340μ m average thickness, 170μ m pixel size, ~600k points). This combination of speed and dense sampling highlights the strength of interferometry for full-wafer metrology.

Nanotopography maps can be generated directly from MSP data by removing low-order Zernike terms and applying a Gaussian filter [Fig. 2(b)]. This reveals sub-micron features ( ± 200 nm here) that are otherwise obscured in the raw map, such as radial patterns from residual grinding damage and concentric CMP artifacts. The ability to extract these details rapidly from high-resolution wafer-level maps is a key advantage of the MSP approach.

By contrast, CWL profilometry achieves direct physical thickness mapping without index assumptions but at the cost of throughput. Fig. 2(c) shows a CWL map of comparable resolution ( 341 μm average thickness, 100μ m pitch), which required ~90 minutes per wafer. To reduce acquisition time to ~10 minutes, the measurement pitch must be coarsened to 1.5 mm ( ~8k points), as in Fig. 2(d), but this sacrifices spatial detail.

These examples illustrate a fundamental trade-off: CWL provides direct thickness but only with slow, step-and-scan measurements, while MSP delivers fast, high-resolution maps suitable for waferlevel process control. This contrast is expected to become even more pronounced at larger wafer diameters, underscoring the scalability advantage of interferometric metrology.

[picture]

Fig. 2. Example thickness maps for a 150 mm wafer: (a) MSP thickness map, (b) MSP nanotopography map (Gaussian-filtered with cutoff wavelength of 20 mm ), (c) high-resolution CWL map, and (d) low-resolution CWL map.

Fig. 2. Example thickness maps for a 150 mm wafer: (a) MSP thickness map, (b) MSP nanotopography map (Gaussian-filtered with cutoff wavelength of 20 mm ), (c) high-resolution CWL map, and (d) low-resolution CWL map.

Refractive Index Calibration.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

MSP thickness relies on the assumed refractive index. At a given OPD measurement,

t=OPDng(3)

so a small index error Δng produces a thickness error

Δt=−tngΔng(4)

Thus, thickness error scales with wafer thickness and the fractional index error. Table 1 shows that a 1/1000 index error yields ~100−200 nm thickness error. While modest, larger index deviations can quickly become significant.

Table 1. Estimated thickness error from a 1/1000 error in assumed group index, evaluated for nominal wafer thicknesses at ng=2.690.

Wafer

Thickness mathematical formula

2.690 | 350 | 130
500 | 186

A simple calibration method is to compare MSP average thickness with physical thickness from CWL. Fig. 3 shows this relationship for doped wafers, with a fit slope giving

tMSPtCWL=ncalnused=1.00066(5)

indicating a ~0.07% overestimation and suggesting a true index of 2.692 (vs. 2.690).

[picture]

Fig. 3. MSP vs. CWL average thickness for doped wafers, with proportional fit showing a ~0.07% overestimation of MSP thickness with a chosen index of 2.690.

Fig. 3. MSP vs. CWL average thickness for doped wafers, with proportional fit showing a ~ 0.07 % overestimation of MSP thickness with a chosen index of 2.690.

While global averages provide a quick calibration, they can be skewed by outliers or macroscopic distortions (e.g., dimples, residual grind marks). To mitigate these effects, we instead compared full wafer maps by subtracting CWL and MSP thickness data after alignment and pixel matching [Fig. 4]. Although this approach can still be influenced by misalignment, edge exclusion differences, and CWL artifacts, the average value of the resulting difference maps offers a more robust estimate of index miscalibration.

[picture]

Fig. 4. Difference maps (CWL - MSP) for two wafers: (a) 279-4, variation mainly from map misalignment; (b) 104-3, variation dominated by basal facet region.

Fig. 4. Difference maps (CWL - MSP) for two wafers: (a) 279-4, variation mainly from map misalignment; (b) 104-3, variation dominated by basal facet region.

Table 2 summarizes mean difference map values by material type and source. Doped wafers showed consistent offsets of -210 to -250 nm across three suppliers, corresponding to calibrated indices of 2.691-2.692. Optical-grade wafers showed +310 nm average difference, corresponding to 2.688. These values imply ~0.04−0.07% systematic error in calculated thickness.

Table 2. Mean values of difference map averages by material source and type, with corresponding calibrated group index.

Material Source | Material Type | Difference Average [μm] | ncal
A | Doped | -0.2476 | 2.692
B | Doped | -0.2169 | 2.691
C | Doped | -0.2351 | 2.692
D | Optical | 0.3064 | 2.688

Refractive Index Uniformity.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Difference maps also reveal the spatial uniformity of the group index. While average offsets support global calibration, the standard deviation and range of the maps quantify local variation within each wafer [Fig. 5].

[picture]

Fig. 5. Variation in wafer difference maps, shown as range (top) and standard deviation (bottom). Data are grouped by source (A-C: doped; D: optical), ingot ID, and wafer ID. Wafers from Fig. 4 are highlighted.

Fig. 5. Variation in wafer difference maps, shown as range (top) and standard deviation (bottom). Data are grouped by source (A-C: doped; D: optical), ingot ID, and wafer ID. Wafers from Fig. 4 are highlighted.

Across all wafers, the variation shows a noise floor of ~70−80 nm in standard deviation and 0.5−0.7μ m in range. This baseline largely reflects scan artifacts (e.g., the horizontal feature in Fig. 4(b)) and residual misalignment between MSP and CWL maps. Wafer 279-4 [Fig. 4(a)] illustrates this baseline: its minimal within-wafer variation demonstrates the agreement achievable between MSP and CWL thickness in the absence of material inhomogeneities.

Excursions above this floor point to spatially varying optical effects not explained by measurement artifacts. These deviations are typically linked to microstructural features that alter the index. For wafer 104-3 [Fig. 4(b)], the basal facet region appears 100−200 nm thicker than the wafer bulk. Nanotopography maps [Fig. 6] confirm this is not true thickness variation: the facet appears in the thickness map but not in the Si-face topography. This indicates an optical artifact caused by index variation, corresponding to a local index ~0.001 lower than the bulk value.

[picture]

Fig. 6. Wafer 104-3 (a) thickness nanotopography and (b) Si face Nanotopography maps. The basal facet appears in (a) but not in (b), indicating an optical artifact rather than a true thickness variation.

Fig. 6. Wafer 104-3 (a) thickness nanotopography and (b) Si face Nanotopography maps. The basal facet appears in (a) but not in (b), indicating an optical artifact rather than a true thickness variation.

Index Validation Measurements

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Prism Coupling.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

To independently assess the bulk index observed with MSP measurements, we performed prismcoupling measurements on selected wafers using TE-polarized light at 632.8 nm . This provides the ordinary phase index, the most relevant parameter since MSP primarily probes this direction under normal incidence. Results for doped and optical-grade wafers, including basal facet regions where available, are shown in Fig. 7 and summarized in Table 3. Measured indices agree with literature values [5] to within 0.04%.

[picture]

Fig. 7. In-plane refractive index measured by prism-coupling refractometry at 632.8 nm for select wafers at multiple radial positions. The first nine samples are doped wafers (with basal facet measurements labeled "Dark Region"); the final two are optical-grade wafers.

Fig. 7. In-plane refractive index measured by prism-coupling refractometry at 632.8 nm for select wafers at multiple radial positions. The first nine samples are doped wafers (with basal facet measurements labeled "Dark Region"); the final two are optical-grade wafers.

Table 3. Literature and measured ordinary refractive index at 632.8 nm [5].

Measured | Literature Phase Index (o-ray) | 2.634
Doped Bulk | 2.633
Doped Basal | 2.632
Optical Bulk | 2.634

Measured index showed excellent uniformity across wafers, with typical within-wafer variations of ±0.0001, corresponding to ±20 nm effective thickness error in interferometric measurements. Localized deviations were observed in basal facet regions, where the index was reduced by ~0.001 : an order of magnitude larger than bulk variation. This corresponds to a thickness error of ~130 nm, consistent with estimates from wafer 104-3 [Fig. 4]. These results confirm that basal facets introduce small but measurable refractive index shifts, which can impact MSP-derived TTV.

Interferometry.

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Difference maps provide useful insight, but they are limited by CWL resolution and scan/alignment artifacts. These limitations can be avoided by measuring index-independent thickness directly on the

MSP using the configuration shown in Fig. 1(b). Inserting an optical flat introduces additional surface pairs in the measurement stack, allowing both OPD and thickness to be independently measured. From these, an index map can be calculated across the wafer. Examples are shown in Fig. 8 for a doped wafer with a basal facet and for an optical-grade wafer.

[picture]

Fig. 8. Group index maps measured with an MSP at 950 nm using the configuration in Fig. 1(b). (a) Doped wafer 104-4, showing a large basal facet region with lower index than the wafer bulk. (b) Optical-grade wafer with highly uniform index.

Fig. 8. Group index maps measured with an MSP at 950 nm using the configuration in Fig. 1(b). (a) Doped wafer 104-4, showing a large basal facet region with lower index than the wafer bulk. (b) Optical-grade wafer with highly uniform index.

The doped wafer [Fig. 8(a)] exhibits a bimodal index distribution: 2.665 in the basal facet region and 2.666 in the wafer bulk (Table 4). These measurements, performed at 950 nm , differ slightly from earlier 830 nm data. The lower basal index is consistent with preferential dopant incorporation on basal facets during growth; n-type SiC index decreases with nitrogen concentration [7]. Using a single global index would introduce a ~130 nm thickness error, consistent with prism-coupling estimates.

Table 4. Literature and measured group index from the difference map method ( 830 nm ) and optical flat method (950 nm) [5].

| Wavelength
| 830 nm | 950 nm
Literature Group Index (o-ray) | 2.692 | 2.661
Measured | Doped Bulk | 2.692 | 2.666
Doped Basal | 2.688 | 2.665
Optical Bulk | 2.688 | 2.663

In contrast, the optical-grade wafer [Fig. 8(b)] shows high uniformity, with an average index of 2.663 and standard deviation of 0.0001 . This corresponds to a ±20 nm thickness error, indicating that a single calibrated global index can yield accurate thickness for high-quality optical wafers.

Optical Retardance.

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

Intrinsic stress in the SiC crystal manifests as stress-induced birefringence, which can be quantified and visualized [8, 9]. Optical retardance maps for the wafers in Fig. 8 (rotated 90∘ ) highlight stressinduced birefringence. For the doped wafer, a 12∘ tilt was applied to suppress intrinsic birefringence, isolating stress contributions. The map reveals a radial stress field: the center is nearly stress-free, while edges show stronger radial alignment. The maximum retardance ( ~12 nm ) corresponds to a birefringence of 3×10−5 for a 350μ m wafer: an order of magnitude smaller than the index variations measured with the MSP. The optical-grade wafer shows a similar maximum birefringence ( 2×10−5 for 500μ m wafer), but with improved uniformity, as most of the wafer remains at ~4×10−6.

This contrast indicates that stress in doped material is more localized and directional, whereas optical-grade material remains low, homogeneous stress. Although these stress signatures are small compared to index variation, they may reflect wafer thermal or mechanical history. Radial patterns could originate from growth gradients, while reduced stress in optical-grade material suggests improved processing. Further correlation of retardance with growth conditions and yield could clarify their significance.

[picture]

Fig. 9. Optical retardance maps of wafers from Fig. 8 shown as vector maps and heat maps (retardance in nm ). (a) Doped wafer with a radial stress field and higher edge retardance. (b) Optical-grade wafer with improved retardance uniformity (central data missing in stitched map).

Fig. 9. Optical retardance maps of wafers from Fig. 8 shown as vector maps and heat maps (retardance in nm ). (a) Doped wafer with a radial stress field and higher edge retardance. (b) Optical-grade wafer with improved retardance uniformity (central data missing in stitched map).

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

The MSP provides rapid, high-resolution wafer measurements with excellent repeatability, far exceeding CWL throughput. Bulk refractive index uniformity was stable, introducing only ±20 nm thickness error when a single global index is applied, and localized deviations near basal facets produced errors ~100−200 nm. Though small relative to wafer thickness, these effects show that local inhomogeneities can bias results if overlooked. MSP offers a robust, scalable approach for SiC wafer metrology if index calibration and awareness of local variations are maintained.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.47.pdf

J. Wang et al., Optical characterization of high refractive index glass wafers for augmented reality wearables, Optical Interference Coatings Conference (2019).

T. Dunn, C. Lee, M. Tronolone, and A. Shorey, Characterization of wafer thickness uniformity during 3D-IC processing, IEEE 62nd Electronic Components and Technology Conference (2012).

G. Lim, T. Manzur, and A. Kar, Improved optical properties and defectivity of an uncooled silicon carbide mid-wave infrared optical detector with increased dopant concentration, J. Opt. 14, (2012) 105601.

FlatMaster MSP for augmented reality waveguides, Corning Tropel Applications (2019).

S. Wang et al., 4H-SiC: A new nonlinear material for infrared lasers, Laser Photonics Rev. 7 (2013) 831-838.

"Effective index", Sellmeier coefficients, and glass thickness measurements on FM-MSP, Corning Tropel Applications (2024).

T. Bosma et al., Broadband single-mode planar waveguides in monolithic 4H-SiC, J. Appl. Phys. 131(2) (2022) 025703.

K. Gomi et al., Residual stress estimation in SiC wafer using IR polariscope, 2008 International Conference on Electronic Materials and Packaging (2008).

V. Ganapati et al., Infrared birefringence imaging of residual stress and bulk defects in multicrystalline silicon, J. Appl. Phys. 108 (2010) 063528.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 55-61

doi: 10.4028/p-np1tSH

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-12

Revised:
2026-01-28

Accepted:
2026-02-26

Online:
2026-05-21

Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

Tamara Fidler 1,a* and Patrick Schmid 1, b

1 Centrotherm International AG, Württemberger Str. 31, 89143 Blaubeuren, Germany

a*tamara.fidler@centrotherm.de, b  patrick.schmid@centrotherm.de

*corresponding author

Keywords: high temperature SiC oxidation, oxide thickness distribution, vertical oxidation furnace, cover wafer effect.

Abstract

H}-\mathrm{SiC}) wafers were processed in thermal oxidation furnace and impact of oxidation temperature up to 1500∘C, processing pressure and different gaseous ambient on oxide thickness distribution was investigated. Beside the impact of thermal distribution within oxidation furnace, an additional effect on oxide thickness distribution has been observed, due to promotion of oxidation rate in the center of the wafer. Within this work, we have examined which influence processing parameters have on described effect, specific for SiC oxidation.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

Vertical furnaces are essential tools for implant anneal as well as thermal oxidation processes in high-performance mass production SiC device manufacturing lines. The thermal distribution in these tools is thoroughly studied by different temperature measuring methods and simulations and specified by manufacturer [1]. Likewise, due to vital role of thermal oxidation and oxide quality in SiC device production, thermal oxidation kinetics and mechanism have been a topic of numerous experimental and theoretical studies [2-4]. However, until now there is no comprehensive study of impact of different ambient and cover wafer conditions on oxide thickness distribution on SiC substrate in thermal oxidation production furnaces.

The design of the furnace for thermal oxidation is the determining factor for oxide thickness distribution. Specifically, the thermal distribution is defined by furnace configuration (the number, dimensions and location of heaters and insulation parts) and its temperature measurement and control system. Also supply and ventilation systems that have impact on ambient distributions inside the process chamber are of importance. The oxidation furnaces used in this work are state-of-the-art production tools. The temperature measurement and control are executed by pyrometers, which are profiled with thermocouple up to the highest oxidation temperature of 1500∘C. The power monitoring ensures processing stability over long time periods. There are different possibilities how temperature distribution inside of a furnace can be determined. Apart from pyrometrical measurements on the surface of the chamber and measurements with thermocouples inside of the processing chamber, one of the conventional methods to determine the thermal distribution of oxidation furnace can be measurement of oxide uniformity on the processed wafer. With known temperature sensitivity, oxide thickness distribution can be converted to temperature distribution. Within this study, another influence on oxide thickness has been observed for thermal SiC oxidation process in conjunction with covered or stacked wafers, which neither matches the thermal distribution pattern nor can it be explained by the consumption or depletion of oxygen and expectations based on published SiC oxidation mechanism [2-4]. Furthermore, influence of different ambient parameters on observed center accentuated distribution has been investigated.

Experimental

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Oxides were grown on n-type 150 mm or 200 mm SiC wafers with Si-face front surface and Cface rear surface orientation, with 4∘ miscut angle, using centrotherm's vertical production furnace c.OXIDATOR 150 or c.OXIDATOR 200. After tube evacuation, a process pressure in a range between 100 to 890 mbar is set with defined gas flow of diluted oxidation gas mixture. In this study oxygen, nitrogen monoxide or carbon dioxide were used as oxidation agents. Nitrogen or argon were used for dilution. The wafers were heated to target oxidation temperature. In described experiments temperature range from 1150∘C−1500∘C was investigated. The ramp rate to target temperature was 10 K/min. At targeted temperature, gas flow was set to tested pure gas or mixture and temperature was maintained for a defined time. Oxidation time was chosen to reach desired oxide thickness in a range up to 60 nm . At the end of the oxidation step, the heating was turned off and the tube was evacuated and refilled with nitrogen. Afterwards wafers were cooled down to 350∘C in free fall cooling.

The oxide thickness on Si wafers was determined with laser ellipsometry measurements on a Plasmos SD4000 laser ellipsometer at wavelength of 633 nm . The oxide thickness on SiC wafers was determined with spectral ellipsometry measurements on a Sentech SE800 spectral ellipsometer in a wavelength range of 280−370 nm. The angel of incidence was 70∘. A two-layer structure was assumed as the analysis model, consisting of SiC/SiO2.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

According to the thermal distribution of the furnace, wafer loading position inside of furnace will impact the oxide distribution. During the ramp, steady state and cooldown, the thermal distribution inside of the furnace will change. How much the change of thermal distribution in furnace during one processing run will impact the final oxide thickness distribution, depends on oxide growth rate in each of these stages. For observation of oxide thickness distribution across the wafer and easier comparison which influence various parameters have on the distribution, we have chosen center-toedge oxide thickness ratio (C/E), described in Eq. 1.
CE=SiO2 thickness wafer center SiO2 thickness wafer edge .

By observing C/E ratio, we can easily distinguish if we have center-accentuated e.g. hill distribution ( C/E>1 ) or edge-accentuated e.g. bowl oxide distribution ( C/E<1 ) on the wafer.

In figure 1. silicon and silicon carbide oxide distributions processed in different positions inside of the process are presented as illustrated by center-to-edge ( C/E ) oxide thickness ratios. The tested oxidation condition in this example is 1350∘C processing temperature, in pure oxygen atmosphere with 18 minutes steady state time is identical for silicon and silicon carbide wafers. The oxidation rates of silicon and C -face SiC is faster than the oxidation rate of Si -face SiC . This processing condition grows approximately 50 nm oxide on Si -face SiC e.g. 170 nm on Si or 110 nm on C -face SiC, due to different oxidation rates of these substrates.

[picture]

Fig. 1. Ratio of oxide thickness in the center vs. edge of the wafer ( C/E ) for Si and 4H−SiC substrates.

Fig. 1. Ratio of oxide thickness in the center vs. edge of the wafer ( C / E ) for Si and 4 H − S i C substrates.

On silicon wafer, oxide distribution is mostly flat ( C/E close to 1 ), with slight bowl distribution at bottom positions of the boat and slight hill distribution in upper boat positions. C/E ratio of oxide on C -face follows the same trend and is mainly influenced by thermal distribution inside of the chamber. C/E ratio of oxide grown on Si -face is significantly different to C/E ratio from other two substrates. There is an obvious additional impact that promotes oxide growth in the center of the wafer more than on the edge, which is not in direct correlation with temperature distribution across the wafer nor within the expected ambient distribution in the chamber. We would like to point out that the oxide thickness measurements from Si -face and C -face oxide layers are determined on the same wafer and therefore confirm that temperature distribution is not origin of center-accentuated oxide distribution on Si -face SiC . The gas inlet and outlet are located at the opposite side of the process chamber, and liner tube directs the flow from the bottom towards top of the chamber, with main flow path between liner wall and wafers. Consequently, the gas exchange between wafers is mainly driven by the diffusion and relatively low. Limited ambient exchange could lead to depletion of oxidant species in the center area between wafers. This would result in lower thickness in the middle of the wafer and therefore C/R ratio below 1 , because oxidation rate scales with the square root of the oxygen partial pressure [5]. Also, it would be expected that accumulation of carbon monoxide as byproduct of SiC oxidation, would also further dilute the oxygen ambient leading to lower oxidation rate in the wafer center, which is clearly not the case here.

Further evidence that the observed oxide thickness pattern on Si-face is not temperature distribution related is depicted in figure 2, showing the impact of distance between processed wafers in the chamber and the covering wafer material type.

[picture]

Fig. 2. C/E ratio for 4H−SiC substrates with different wafer coverage.

Fig. 2. C / E ratio for 4 H − S i C substrates with different wafer coverage.

In conventional production, the wafers are processed in vertical furnace with Si-face pointing up. In this case each Si -face is pointing towards C -face of 4H−SiC wafer. For test in figure 2. (left) two runs were executed with 18 minutes steady state at 1350∘C oxidation temperature. In first run two wafers were placed in the same area of the processing chamber face-to-back and in the second run face-to-face so that Si -face is turned towards Si -face of the adjacent wafer. C/E ratio of the uncovered wafer is additionally shown for comparison. Since the wafers in both runs were processed in a same way with the same number of wafers, loaded in the same boat positions and therefore with thermal mass remaining equal in both runs, the thermal distribution across the wafer is in these two runs is identical and flow pattern of incoming pure oxygen gas is matching as well. Unexpectedly, the thickness in the center is significantly higher, if the processed SiC wafer is covered with C -face, with respect to covering of processed wafer with Si -face SiC . Since there is a clear relation to occurrence of the elevated oxidation rate and covering of the wafer, we can postulate that the observed cover wafer effect is most probably ambient related. In another test, shown in Fig. 2 (right) same processing condition was performed but Si-face of SiC wafer was placed below silicon wafer, which still had slight influence on the oxide thickness in the center of the wafer. Uncovered wafer situation is a reference value for each example, depending on thermal distribution in respective loading position in the processing chamber e.g. boat slot and therefore different in (left) and (right) example.

In the next experiment, shown in figure 3, very big influence of oxidation temperature on cover wafer effect can be observed. Remarkably, if we compare C/R ratio of Si -face 4H−SiC substrate processed at 1150∘C to substrate processed at 1350∘C in pure oxygen, the cover wafer effect is substantially bigger at lower temperature. The experiment with diluted oxygen mixture in figure 3. (right) demonstrates same temperature behavior. Oxidation times for experiments is figure 3. were chosen to grow approx. 50 nm oxide on Si -face of 4H−SiC, therefore oxidation time at lower temperature was longer.

[picture]

Fig. 3. C/E for Si -face 4H−SiC substrates covered with C -face 4H−SiC or uncovered at different temperatures for pure (left) and diluted oxygen (right).

Fig. 3. C / E for Si -face 4 H − S i C substrates covered with C -face 4 H − S i C or uncovered at different temperatures for pure (left) and diluted oxygen (right).

It must be considered that oxide is partially grown during ramp-up period and with higher oxidation temperature more oxide grows during ramp-up. During ramp-up the wafer edge in a stack of wafers is expected to be colder at the edge of the wafer. Also, in this case we can use uncovered wafer situation as a reference value, which relates better to thermal distribution of different processes to distinguish thermal from ambient related effects, to conclude that effect on higher oxidation rate in the wafer center is clearly higher at lower temperature but not due to thermal distribution.

The strong dependency of elevated oxidation rates in the middle of the wafer to temperature as well as strong effect from covering of wafer with C-face lead to assumption that might be explained by the higher amount of generated oxidation byproducts, due to much higher oxidation rate of C -face in relation to Si -face at 1150∘C [5, 6], are causing observed effect. It's unclear if presence of COx
byproduct of C -face SiC oxidation is catalyzing SiC oxidation on Si -face of neighboring wafer or if elevated oxidation rates are caused by improved diffusion of oxidant through oxide. In both cases, concentration of oxidation byproducts is center accentuated under tested pressure and flow conditions and contributes to observed center to edge thickness distribution.

Change of the oxide thickness across the wafer length is exemplary illustrated for 1200∘C oxidation temperature for covered and uncovered sample in figure 4. As has been explained above, at 1200∘C covering effect is more pronounced, hence it is convenient for observation of oxidation time and thickness influence on spatial distribution. Oxide thickness distribution across the uncovered wafer (full symbols) is similar for different wafer thicknesses and is mainly impacted by temperature distribution during steady state at 1200∘C and placement in the central position of the boat. On the contrary, oxide distribution across the covered wafer (empty symbols) is center accentuated and is getting more pronounced with higher thickness.

[picture]

Fig. 4. Spatial oxide thickness distribution across the covered (empty symbols) vs. uncovered wafer (full symbols) for different oxidation times of Si-face 4H−SiC oxidation at 1200∘C in pure oxygen illustrated as oxide thickness at measured position on the wafer relative to mean oxide thickness of covered wafer.

Fig. 4. Spatial oxide thickness distribution across the covered (empty symbols) vs. uncovered wafer (full symbols) for different oxidation times of Si-face 4 H − S i C oxidation at 1200 ∘ C in pure oxygen illustrated as oxide thickness at measured position on the wafer relative to mean oxide thickness of covered wafer.

The oxide thickness growth of uncovered Si -face wafers as well as covered and uncovered C -face 4H−SiC at 1200∘C fits well with the model for SiC oxidation based on Deal-Grove model with Massoud's empirical corrections for thin oxides, implemented in the process simulator Sentaurus Process [5], as shown in figure 5. Oxidation rate of covered Si -face 4H−SiC wafers is higher than values predicted by the model in examined thickness range.

[picture]

Fig. 5. Oxide thickness as a function of time for Si -face (left) and C -face (right) 4H−SiC oxidation at 1200∘C in pure oxygen. Experimental data for covered and uncovered substrates, indicated by symbols, are compared to data obtained by SiC oxidation process model published by Zechner et al. [5], indicated by full line.

Fig. 5. Oxide thickness as a function of time for Si -face (left) and C -face (right) 4 H − S i C oxidation at 1200 ∘ C in pure oxygen. Experimental data for covered and uncovered substrates, indicated by symbols, are compared to data obtained by SiC oxidation process model published by Zechner et al. [5], indicated by full line.

Furthermore, we have investigated influence of different gaseous ambient, on described enhanced growth in the center of the wafer, as demonstrated in figure 6. On the left side we see example of oxide distribution in different ambientes for thin oxides around 5 nm , which are thinner in the middle of the wafer and example for growing 50 nm thick oxide in carbon dioxide on the right side. With change of ambient due to altered oxidation mechanism [7, 8] and absence of species essential for oxidation rate enhancement, we have influenced the growth in the middle of the wafer.

[picture]

Fig. 6. C/E ratio comparison for covered and uncovered wafers processed in different gaseous ambient at 1400∘C for oxide thickness around 5 nm (left). C/E ratio comparison for wafer covered and uncovered wafers processed in pure carbon dioxide at 1450∘C for oxide thickness around 50 nm (right).

Fig. 6. C/E ratio comparison for covered and uncovered wafers processed in different gaseous ambient at 1400 ∘ C for oxide thickness around 5 nm (left). C/E ratio comparison for wafer covered and uncovered wafers processed in pure carbon dioxide at 1450 ∘ C for oxide thickness around 50 nm (right).

Since changing oxidation parameters (temperature, pressure, oxidant species or concentration) may impact quality of oxide and increasing space between wafers would impact the throughput of the tool, another approach is recommended to improve oxide uniformity in SiC oxidation process. Diminishing COx byproduct concentration with preventing or reducing oxidation rate on C -face by protective layer is a viable approach in a case when higher oxidation temperature or ambient change are not possible. Deposition of silicon nitride, silicon dioxide or poly silicon can be considered as possible options.

Summary

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

In conclusion, we have presented empirical oxide thickness data for crucial ambient parameters that have to be considered for optimization of oxide uniformity of thermal oxidation furnace for SiC substrates. We have reported unexpected, elevated oxidation rates, which are in contradiction with low oxidant concentration between wafers expected for described flow pattern in the furnace. Based on observed temperature dependence and wafer coverage dependence we have proposed explanation for observed behavior as well as preventing measures against it.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.55.pdf

P. Schmid, ECSCRM 2020-2021, Industrial Session: c.ACTIVATOR 200 & c.OXIDATOR 200 (2021).

V. Šimonka, A. Hössinger, J. Weinbub, S. Selberherr, J. Appl. Phys. 120 (2016) 135705.

D. Goto, Y. Hijikata, J. Phys. D: Appl. Phys. 49 (2016) 225103.

N. S. Jacobson, D. L. Myers, Oxid. Met. 75 (2011) 1.

C. Zechner, A. Johnsson, T. Fidler, P. Schmid, Phys. Status Solidi A 217 (2024) 2400234.

D. Goto, Y. Hijikata, S. Yagi, H. Yaguchi, J. Appl. Phys. 117 (2015) 095306.

R. Deguchi, T. Hosoi, ICSCRM 2023, Thermal oxidation of surface in a pure ambient (2023).

S. A. Corrêa, C. Radtke, G. V. Soares, L. Miotti, I. J. R. Baumvol, S. Dimitrije, J. Han, L. Hold, F. Kong, F. C. Stedile, Appl. Phys. Lett. 94 (2009) 251909.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 63-68

doi: 10.4028/p-92Xjcg

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-13

Revised:
2025-12-19

Accepted:
2026-02-23

Online:
2026-05-21

Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

1 Rena Technologies GmbH, Hoehenweg 1, D-78148, Guetenbach, Germany

2 School of Engineering, University of Warwick, Coventry, CV47AL, UK

a  norbert.bay@rena.com, b  Athul.Rathnakar@warwick.ac.uk, c  Xavier.gay@rena.com, d wyatt.engler@rena.com, e rahim.hamid@rena.com, f franck.delahaye@rena.com, g  Oliver.Whear@rena.com, h  vishal.shah@warwick.ac.uk, 'holger.kuehnlein@rena.com

*Corresponding author: franck.delahaye@rena.com

Keywords: SiC, silicon carbide, wet etching, strain relief, wet processing, substrate engineering.

Abstract

Strain relief etching is a critical wet process technique use in high volume manufacturing of semiconductor substrates and device wafers. The goal of a strain relief etch is application dependent but can generally be considered for removal of warp/bow or improving mechanical strength by removing sub-surface damage thereby optimizing yields. Silicon Carbide (SiC) has a high chemical resistance which has blocked SiC wafer manufacturers from using strain relief etching to date. In this work, we demonstrate strain relief etching using an Advanced Chemical Etching (ACE) process of the full wafer surface on commercial grade 4H−SiC wafers and poly- SiC wafers at high etch rates ( μ m's/hr) which enable ACE as a production technique. The data shows a 4 times improvement of breakage strength, from 13 to 55 N , in laser split wafers. Bow and warp of ground wafers is reduced from 70/250μ m to −5/25μ m approx. respectively, matching Chemical Mechanical Polished (CMP) wafers which is the industrial method for preparing wafers. Thus showing the potential of stronger, flatter wafers being available for chemical mechanical polishing.

Norbert Bay1,a, Athul Rathnakar2,b, Xavier Gay1,c, Wyatt Engler1,d, Rahim Hamid1,e, Franck Delahaye1,f⋆, Oliver Whear1,g, Vishal A. Shah2,h, Holger Kuehnlein1,i

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

1 Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

Wet chemical etching is a well-established process in the semiconductor industry, particularly for silicon-based wafer manufacturing. It plays a key role in device fabrication, substrate preparation, and surface conditioning due to its scalability, controllability, and compatibility with high-volume manufacturing. However, extending this technique to wide bandgap semiconductors such as silicon carbide ( SiC ) has proven challenging due to SiC 's exceptional chemical inertness. As a result, SiC substrates typically undergo aggressive mechanical processes-such as grinding and polishing-to achieve the desired thickness and surface flatness. These techniques can introduce significant subsurface damage, residual stress, and wafer bow or warp, especially early in the manufacturing line when wafers are thin and fragile[2,3]. Use of extensive mechanical techniques is also expensive and difficult to perform at volume where wafers are fragile early in the substrate manufacturing line. Research has explored mechanisms of wet etching for creating microstructures on 4H−SiC[4] and trenches in 6H−SiC [5].
ACE performs wet etching of 4H−SiC in an innovative approach. The ACE technology allows controlled material removal in a single-sided processing set-up with no edge exclusion with material removal rates between 15 and 20μ m/h.
We also postulate that one of the primary applications of ACE on SiC wafers is strain relief etching, where the removal of damaged and strained surface layers leads to reductions in bow and warp, and a marked improvement in mechanical strength. This is particularly beneficial prior to downstream steps such as chemical mechanical polishing (CMP), where wafer flatness and stress state directly impact process yield and wafer survival.
In this study, we investigate the effects of ACE strain relief etching on commercial-grade n+ type SiC wafers. The focus is on providing evidence of the strain-relieving properties of the ACE and
quantifying any improvements in mechanical strength and wafer shape (bow/warp) achieved through ACE processing. A combination of metrology techniques is used to characterize the impact of the process.

2 Methodology

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Sample Description

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Samples were obtained from SiC wafer manufacturers, which have undergone wafer cutting with wire-sawing or laser-splitting and coarse grinding. Wafers were 150 mm in diameter, nominally (0001) orientated with a 4 deg offcut, 350μ m thick and doped with Nitrogen so that the resistivity was 10−20mOhm.cm. In addition, wafers after laser-splitting were processed as well. Finally, 4 H monocrystalline wafers as well as poly-SiC substrates both thinned with backside-grinding were obtained from another commercial supplier.

Characterization Techniques Used

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To assess the strain relief and damage removal capabilities of ACE on 4H−SiC wafers.
Stress/Strain was compared using:

Laser scatterometry (Onto Primascan) for visualization of grinding-induced surface damage.

X-ray topography (XRT) using the Rigaku Micron 3-300 in reflection mode to assess subsurface strain. Instead of typical plan view images, cross sectional images were obtained to demonstrate the surface effect.
Thickness of removed material was measured by weighing the wafers before and after the etching with a laboratory scale. Wafer breakage strength was measured on a 3-point bending set-up.

3 Results and Discussion

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Here we characterise ACE etching on three important components of SiC technology: 1) standard processing of monocrystalline wafers, 2 ) new laser split monocrystalline wafers and 3 ) device wafers which are thinned as the final step on both monocrystalline and polycrystalline wafers.

Impact of ACE on Strain in Ground Monocrystalline 4H-SiC Wafers

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In this section we show the comparison of laser scatterometry images and XRT images captured in reflection mode before and after the 3μ m ACE etch on commercial coarse ground 4H−SiC wafers

Laser Scatterometry

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Prior to etching [Fig. 1a], the typical wafer surface displays a dense pattern of radial grinding marks, typical of mechanical thinning processes and indicative of residual surface stress and microcracking. After etching [Fig. 1c], these features are significantly reduced or eliminated, suggesting effective removal of the mechanically damaged surface layer. This result implies a more uniform surface stress profile and is consistent with strain relief from the etching process.

Subsurface Strain Mapping with XRT

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The pre-etch wafer [Fig. 1b] exhibits a dark linear feature near the surface-this line corresponds to a region of high strain effects introduced by coarse grinding. After the 3μmACE etch [Fig. 1d], this feature is completely absent, suggesting that the strained layer has been removed and the near-surface lattice has relaxed. This behaviour is additionally underlined by the XRT cross section scan [Fig. 1e]: while the scan of the ground wafer exhibits large strain peaks close the the wafer surface, these are reduced almost down to bulk level in the etched wafer.

[picture]

Fig. 1. Laser scatterometry images of 6′′SiC wafers (a) before and (c) after 3μ m ACE etching. Grinding marks are largely diminished post-etch, indicating reduced surface strain and damage. Cross-sectional XRT images (b) before and (d) after 3μ m ACE etching. The high-strain layer present in the unetched wafer is fully relieved post-etch. Large peaks witnessing the high amount of subsurface strain after grinding in the XRT cross-section scan (e) almost completely disappear after etching.

Fig. 1. Laser scatterometry images of 6 ′ ′ S i C wafers (a) before and (c) after 3 μ m ACE etching. Grinding marks are largely diminished post-etch, indicating reduced surface strain and damage. Cross-sectional XRT images (b) before and (d) after 3 μ m ACE etching. The high-strain layer present in the unetched wafer is fully relieved post-etch. Large peaks witnessing the high amount of subsurface strain after grinding in the XRT cross-section scan (e) almost completely disappear after etching.

Enhancement of Mechanical Strength on Laser Split Monocrystalline 4H-SiC Wafers

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To evaluate the mechanical benefits of ACE following laser splitting, a batch of 6-inch 4H-SiC wafers was subjected to ACE etching with a removal depth of 5μ m. The mechanical robustness of the as split and etched wafers was assessed via 3-point bend breakage testing. For comparison, a control group of wafers underwent coarse backside grinding instead of ACE etching.
Figure 2 presents the break force results across the three conditions: post-laser split (no treatment), post-coarse grind, and post-ACE etch. The as-split wafers exhibit low break strength, with values around 13 N. Following ACE etching, the breakage force increases by a factor of four, reaching values above those achieved by coarse grinding ( ~40 N vs. ~50−60 N ). This substantial improvement indicates that ACE etching effectively strengthens the wafer against mechanical failure, likely by smoothing out the sharp surface features of the post-laser-split surfaces.
This indicates that integrating a 5μ m ACE etch immediately after laser splitting can significantly improve wafer robustness and reduce breakage rates in subsequent handling or grinding operations.

3-pt Bend Break Force vs Process Step

Fig. 2. 3-point bend break force measurements for SiC wafers after laser splitting, after coarse grinding, and after 5μ m ACE etching. ACE-treated wafers show the highest mechanical strength.

Reduction of Bow and Warp Through ACE Etching After Grinding

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To assess the impact of ACE on wafer shape distortion, 25 6-inch SiC wafers were first subjected to frontside (Si face) grinding. The wafers were then split into two groups: Group A ( 20 wafers) underwent ACE etching with a removal depth of 5μ m, while Group B ( 5 wafers) was processed through chemical mechanical polishing (CMP) as a control.
Figure 3 illustrates the evolution of bow and warp through the sequence of process steps. After grinding, wafers show significant shape distortion, with bow values exceeding 100μ m and warp values reaching ~250μ m. However, after ACE etching, both bow and warp are reduced to levels comparable to those achieved with CMP.
This significant reduction in mechanical distortion confirms that ACE etching effectively removes the stressed and damaged surface layer introduced by grinding. By eliminating this strain, ACE restores flatness and dimensional stability to the wafers and this way provides a better starting point for the following CMP processing.

[picture]

Fig. 3. Bow and warp measurements of 6′′SiC wafers after grinding, ACE etching (Group A), and CMP (Group B). ACE etching reduces both parameters to the level of the CMP control group.

Fig. 3. Bow and warp measurements of 6 ′ ′ S i C wafers after grinding, ACE etching (Group A), and CMP (Group B). ACE etching reduces both parameters to the level of the CMP control group.

Implementation of ACE on Wafers after Backside Thinning

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Warp and Bow reduction

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To evaluate the effectiveness of ACE etching wafers after backside grinding, two types of 6-inch SiC substrates - 4H−SiC monocrystalline and poly-SiC - were processed. The monocrystalline wafer carried front-side devices, the poly wafer was still blank on both sides. Both were subjected to backside grinding to thin the substrate. Subsequently, a backside ACE etch was performed, removing residual damage.
Figure 4 shows the resulting bow and warp values before and after ACE etching.

On the 4H−SiC wafer, warp was slightly reduced from 399μ m to 317μ m. However, bow changed significantly - from −202μ m to +315μ m. This suggests that the compressive stress introduced by grinding was effectively removed from the backside, leaving the tensile stress from the front-side device layers dominant. This implies that partial etching, leaving some compressive stress on the backside, might yield a flatter wafer overall.

On the poly-SiC wafer, both warp and bow were significantly reduced - warp dropped from 886μ m to 85μ m, and bow from −260μ m to +34μ m. This indicates effective stress relaxation and damage removal on this wafer type through ACE.
These results highlight the importance of stress balancing in post-thinning processes and demonstrate the potential of ACE to improve wafer flatness on complex device wafers.

[picture]

Fig. 4. Effect of ACE etching on warp and bow for 4H−SiC device wafer and poly- SiC substrate after backside grinding. ACE etching leads to significant improvements in flatness, especially on poly-SiC material.

Fig. 4. Effect of ACE etching on warp and bow for 4 H − S i C device wafer and poly- SiC substrate after backside grinding. ACE etching leads to significant improvements in flatness, especially on poly-SiC material.

4 Conclusion

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ACE technology enables effective strain relief in SiC wafers through wet etching. It significantly improves wafer strength after laser splitting, flattens ground wafers to levels comparable to CMP, and reduces strain-induced distortion in device wafers. Optical and structural characterization confirms the removal of sub-surface damage and residual stress. These findings highlight the potential of ACE for enabling more robust, cost-effective, and high-yield SiC wafer processing. While these findings are encouraging, further work is needed to evaluate long-term device performance and the integration of ACE into high-volume manufacturing environments.
The results demonstrate that ACE etching enables production-scale wet processing of SiC, opening new pathways for cost-effective, high-throughput manufacturing of SiC substrates and devices.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.63.pdf

Yole Développement, Wafer Starts for More Than Moore Applications report, April 2023.

Moeggenborg K, Kegg T, Parfeniuk C, Stoney T, Quast J. Effect of Surface Damage on SiC Wafer Shape. MSF 2015; 821-823: 545-8. https: -doi-org.pugwash.lib.warwick.ac.uk/10.4028/www.scientific.net/msf.821-823.545.

Yang et al Journal of Manufacturing Processes, Volume 70, , October 2021, Pages 350-360.

Yang et al. ACS Appl. Mater. Interfaces. 2018 DOI: 10.1021/acsami.8b19557.

Chang et al. JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 15, NO. 3, JUNE 200.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 69-76

doi: 10.4028/p-onsJ9i

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-23

Revised:
2025-12-28

Accepted:
2026-02-23

Online:
2026-05-21

CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

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Georg Pfusterschmied 1,2,a*, Michael Kusolitsch 1,2, b and Christopher Zellner 1,2,c, Marco Perazzi 1,2, d, Tingqiang Yang 1,2,e, Ulrich Schmid 1,f

1 Institute of Sensor and Actuator Systems, TU Wien, Gusshausstrasse 27-29, 1040, Vienna, Austria

2 Christian Doppler Laboratory for Sustainable Silicon Carbide Technology, Gusshausstrasse 27-29, 1040 Vienna, Austria

a* georg.pfusterschmied@tuwien.ac.at, b michael.kusolitsch@tuwien.ac.at, c  christopher.zellner@tuwien.ac.at, d  marco.perazzi@tuwien.ac.at, et  ingqiang.yang@tuwien.ac.at, fulrich.e366.schmid@tuwien.ac.at

Keywords: electrochemical etching, pore nucleation, reactive ion etching.

Abstract

Electrochemical etching (ECE) of silicon carbide is a powerful route to porous 4H−SiC. Yet, reliable pore initiation on the Si-face typically requires additional sophisticated pre-conditioning (e.g. masked KOH etching, metal-assisted photochemical etching (MAPCE), focused ion beam (FIB) milling), limiting industrial adoption. We demonstrate a simple, CMOS-compatible pre-conditioning based on short reactive-ion-etching (RIE) steps ( 10−30 s,SF6/O2 ) that reproducibly nucleate pores on the Si-face of highly doped 4H−SiC (resistivity <0.02Ω· cm ) and enable homogeneous ECE in HF/ethanol without UV illumination. Surface roughness increases modestly with RIE time ( Ra≈1.3 nm to 4.0 nm ), while subsequent ECE does not significantly degrade topography. SEM cross-sections reveal continuous porous layers; image-based quantification shows enhanced vertical pore alignment with longer RIE duration. A stepwise voltage program ( 11.5 V→8.5 V→11.5 V ) yields stable current transients during etching. Eliminating noble metals and lithography reduces contamination risk. It improves process compatibility with front-end manufacturing while remaining synergistic with our previously established ECE process flows and high-temperature reorganisation of thin, porous SiC layers.

Introduction

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Porous semiconductors are essential for several processes in today's semiconductor industry, due to their unique properties as well as cost aspects. In silicon, electrochemical porosification followed by bonding, annealing, or selective dissolution is used at scale to implement ELTRAN® layer transfer for SOI [1] and to form sacrificial or architected layers in MEMS [2]. Extending the same strategy to silicon carbide would offer clear advantages for device operation at high temperature, or chemically aggressive media. Even more, the integration into process flows for power electronics would open up new possibilities [3], [4]. However, progress has been limited because the electrochemistry of SiC compared to silicon is more demanding, and the etching kinetics depend strongly on the exposed crystal face. Early work established that n-type 4H-SiC forms porous layers by photoelectrochemical etching (PECE) in HF electrolytes, with the Si- and C-terminated faces exhibiting substantially different oxidation as well as etching behaviours (e.g., C-face typically faster and yielding more columnar morphologies) [5], [6], [7].
To enable application-relevant morphologies and stacking, our group previously combined metalassisted photochemical etching (MAPCE) with PECE to tailor porosity depth profiles and avoid cap or skin layers [8]. We used this approach to demonstrate that single-crystalline, porous 4H−SiC foils can be released from the mother substrate and later be compactified by high-temperature annealing while preserving crystallinity. This is an analogue to silicon "reorganisation" used in ELTRAN® and related processes [9]. Notably, we scaled PECE foil release to 2-inch diameter areas. We verified single crystallinity by TEM after He-annealing up to 1600∘C, highlighting a viable path toward
substrate re-use and advanced SiC substrate concepts [10]. In parallel, we demonstrated controlled spalling of SiC using a Ni stressor layer anchored in MAPCE-generated surface porosity. This is another wafer-economical route that benefits from predictable, uniform near-surface microstructures [11]. But, all These developments point to porous-SiC-enabled integration strategies analogous to mature silicon technologies such as ELTRAN®, which rely on porous layers for bonding and controlled splitting. However, a persistent bottleneck in SiC is reliable, lithography-free pore nucleation on the Si-face in a manner compatible with CMOS contamination control. Common preconditioners include patterned KOH pits (silicon) [12], noble-metal seeding (MAPCE) [8], or FIB nanocavities [13]; in SiC, these either add topography, introduce metals, or lack throughput.
In this work, a reactive-ion-etching (RIE) pre-treatment is explored as a noble-metal-free approach for preparing the Si-face of 4 H -SiC prior to electrochemical etching. Short SF6/O2 RIE steps are applied before ECE, resulting in a controlled modification of the near-surface region. Fluorine-based plasmas are known to induce subtle nanoscale roughness, micro-masking effects, and chemical surface modifications, which can influence surface energy, wettability, and local electric fields [14], [15]. The following sections investigate how such an RIE pre-conditioning affects pore initiation behaviour during subsequent electrochemical etching, including its influence on current transients, pore morphology, and pore orientation. The study focuses on evaluating the suitability of this approach as a CMOS-compatible pre-treatment for Si-face porosification.
Finally, we want to place this approach in the broader context of porous-SiC manufacturing. Beyond layer transfer and substrate engineering, recent works have revisited ECE of SiC for optical mirrors [16] and MEMS membranes [17], while other groups explore architected 3D microstructures by combined dry/wet routes. These directions reinforce the need for pre-conditioning methods that are selective, scalable, and fab-compatible-requirements our RIE-assisted ECE approach directly addresses [18], [19].

Experimental Details

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Samples ( 2.5×2.5 cm2 ) were diced from 4 -inch, N -doped 4 H -SiC wafers ( 4∘ off-axis, Si-face roughness <0.1 nm, resistivity 0.02Ω· cm ) from SiCrystal. After an HF dip, they received reactive-ion-etching (RIE) in a parallel-plate plasma (STS) at 300 W with 25sccmO2 and 5sccmSF6 for 10, 20, or 30 s. ECE was performed in a tabletop AMMT cell (see Fig. 1) with the SiC piece acting as the separator between anodic and cathodic compartments; pore formation occurred at the side facing the cathode, in an aqueous solution of HF and ethanol ( 5.52 mol L−1HF,1.7 mol L−1 ethanol). No UV illumination was required due to the high electrical conductivity of the samples. A step-programmed bias was applied (first minute 11.5 V , then 8.5 V for 2 min , followed by 11.5 V for 1 min ) to manage nucleation and growth transients (see the current-time trace analogous to Fig. 2). More information about the ECE mechanism and setup is presented in Ref. [8]. Surface roughness was measured with a stylus profilometry (Bruker Dektak) and AFM (Bruker Dimension Edge). SEM (Hitachi SU8030) was used for plan-view and cross-section imaging. A custom Python/OpenCV workflow quantified pore alignment: pore cross-sections were segmented and clustered into orientation kernels, fitted by ellipses to extract principal axes, and visualised as polar histograms (see Fig. 5).

[picture]

Fig. 1. a) Optical photograph of the tabletop etching cell from AMMT, and b) illustration of the applied voltage profile during electrochemical etching.

Fig. 1. a) Optical photograph of the tabletop etching cell from AMMT, and b) illustration of the applied voltage profile during electrochemical etching.

Current-Time Curves for Different RIE Durations

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[picture]

Fig. 2. Typical current response during electrochemical etching of RIE pre-treated samples. The applied voltage in the first minute was 11.5 V , followed by 8.5 V for two minutes and again 11.5 V for one minute.

Fig. 2. Typical current response during electrochemical etching of RIE pre-treated samples. The applied voltage in the first minute was 11.5 V , followed by 8.5 V for two minutes and again 11.5 V for one minute.

Results

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When analysing samples exposed to 10 , 20 , and 30 s RIE steps, the arithmetic mean roughness increased from Ra≈1.3 nm(10 s) and 1.4 nm(20 s) to 4.0 nm(30 s) as listed in Table 1. After ECE, Ra values were 1.3, 1.5, and 5.2 nm , respectively. The corresponding Rq values followed the same trend, thus the ECE step did not measurably degrade surface quality beyond the RIE-imposed baseline. Fig. 3 illustrates the surface after 20 seconds of RIE treatment prior to ECE. The currenttime response exhibited characteristic plateaus/decays at each voltage level (11.5 V→8.5 V→11.5 V ), indicating controlled transitions from nucleation-dominated to growth-dominated regimes (Fig. 2). The final 11.5 V step restored a stable current consistent with sustained pore propagation.

Table 1. Roughness results gained from surface profilometry.

Surface roughness [nm] | Before ECE | After ECE
| Ra | Rq | Ra | Rq
10 s RIE | 1.3 | 1.9 | 1.3 | 1.6
20 s RIE | 1.4 | 1.7 | 1.5 | 1.8
30 s RIE | 4.0 | 6.2 | 5.2 | 5.9

[picture]

Fig. 3. Results from AFM analysis of a sample with 20 s RIE treatment before ECE.

Fig. 3. Results from AFM analysis of a sample with 20 s RIE treatment before ECE.

SEM plan-views before and after ECE (Fig. 4a-f) show the RIE-textured Si-face surface. The corresponding cross-sectional views are shown in Fig. 4 g -i, revealing continuous porosity across the processed depth. Residual flakes seen in plan-view originate from dicing tape and are not morphological features of the RIE process nor from the porosified SiC using ECE. Image analysis of cross-sectional SEMs showed a progressive narrowing of the angular distribution of pore axes with increasing RIE time (polar histograms in Fig. 5), i.e., longer RIE pretreatments yielded a higher fraction of pores aligned closer to the surface normal.

Discussion

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It is known from literature, that the Si -face is less reactive than the C -face. This demonstrated in multiple studies which show faster oxidation and higher etch rates under comparable conditions, which correlate with the prevalence of columnar pores on the C-face in PECE [5], [7]. Recent mechanistic analyses of SiC oxidation further indicate that the C -face develops thicker oxides within a given time frame and higher reaction currents than the Si -face, consistent with kinetically easier formation and/or removal of carbon-containing by-products on the C-face [20].

[picture]

Fig. 4. SEM micrographs of the sample surface and cross-sections before and after RIE pre-treatment with different etching durations: 10 s (left column), 20 s (middle column), and 30 s (right column). The top row (a-c) shows the surface morphology before electrochemical etching (ECE), the middle row ( d−f ) shows the surface after ECE, and the bottom row ( g−i ) presents the cross-sectional views after ECE. The flake-like structures shown in the top-view micrographs are residuals from the dicing tape.

Fig. 4. SEM micrographs of the sample surface and cross-sections before and after RIE pre-treatment with different etching durations: 10 s (left column), 20 s (middle column), and 30 s (right column). The top row (a-c) shows the surface morphology before electrochemical etching (ECE), the middle row ( d − f ) shows the surface after ECE, and the bottom row ( g − i ) presents the cross-sectional views after ECE. The flake-like structures shown in the top-view micrographs are residuals from the dicing tape.

Our data suggest that brief SF6/O2 RIE steps compensate this kinetic disadvantage of the Si-face by (i) introducing sub-nanometric roughness and micro-defect sites that act as local field concentrators and oxidation nuclei, (ii) modifying surface chemistry (fluorination/oxygenation) to lower the barrier for initial SiC oxidation in HF electrolytes, and (iii) improving electrolyte wetting and transport into nascent cavities, which is enhanced by ethanol in the electrolyte [14], [15], [21]. The outcome is a reproducible pore nucleation density that enables homogeneous ECE at moderate voltages, without UV. The observed current transients under the 11.5→8.5→11.5 V program are consistent with an initial field-assisted nucleation burst followed by growth stabilisation and a re-acceleration step to sustain front propagation. This control principle mirrors our prior MAPCE/PECE approach, where time-programmed potentials were used to engineer porosity gradients and avoid cap layer formation [8]. In highly doped n-type SiC, band-bending at the semiconductor/electrolyte interface already confines holes at the surface under forward bias, enabling UV-free ECE when contact/transport conditions are favourable. The sharpening of the pore-axis angular distribution with longer RIE (Fig. 5) implies a transition from lateral/branched to preferentially vertical growth as the density and uniformity of initiation sites increase. We ascribe this to a combination of (i) more uniform initial pit geometry and (ii) reduction of local lateral field inhomogeneities once a dense array of nearly equally spaced pits forms, leading to self-screening of lateral growth paths. This interpretation is consistent with prior observations that controlled initiation influences pore directionality and that facedependent kinetics reinforce vertical growth once nucleation is spatially homogeneous [8].

[picture]

Fig. 5. Binarised SEM cross-section images (a-c) and corresponding polar histograms (d-f) of porous structures after electrochemical etching of samples pretreated by RIE for 10 s(a and d),20 s( b and e ), and 30 s (c and f). The pore orientation was analysed using Python and OpenCV: pores were segmented and clustered into orientation-specific kernels, then approximated by ellipses to extract the main axis direction. The resulting angle distribution was visualised in polar histograms, revealing increasing pore alignment with longer RIE duration.

Fig. 5. Binarised SEM cross-section images (a-c) and corresponding polar histograms (d-f) of porous structures after electrochemical etching of samples pretreated by RIE for 10 s ( a and d ) , 20 s ( b and e ), and 30 s (c and f). The pore orientation was analysed using Python and OpenCV: pores were segmented and clustered into orientation-specific kernels, then approximated by ellipses to extract the main axis direction. The resulting angle distribution was visualised in polar histograms, revealing increasing pore alignment with longer RIE duration.

Compared with MAPCE pore nucleation, the RIE pre-treatment removes a significant contamination possibility (Pt/Au residues) and avoids lithography or FIB. It uses standard precursor gas chemistry ( SF6/O2 ) and short recipes compatible with front-end cleanliness protocols. In integration terms, the present method is complementary to our ECE-based foil release and high-temperature compactification: RIE-assisted ECE can pre-define homogeneous porous layers on the Si-face, after which ECE and post-annealing can yield homogeneously compactified, crystalline surfaces suitable for bonding to alternative carriers, similar to the ELTRAN® approach in silicon [10] [2]. The tradeoff between nucleation reliability and surface roughness is evident: 30 s RIE provides the best alignment but increases Ra to ~5 nm after ECE. We hypothesise that the benefit from RIE derives from two coupled factors: (i) nanoscale topography that locally concentrates the interfacial field and (ii) a modified near-surface chemistry/defect state that lowers the barrier for pore nucleation.

Summary

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We demonstrate a CMOS-compatible route to reliably initiate homogeneous pore formation on the Si -face of 4 H - SiC without noble metals or added lithography. A short O2/SF6 reactive-ion etch ( 10−30 s,300 W) raises the surface roughness from ~1.3 nm to ~4.0 nm, which is sufficient to seed uniform electrochemical etching in HF/ethanol (no UV required for highly conductive wafers). The increased roughness on the nanoscale correlates with (i) suppression of the initial current spike in the ECE transient, (ii) higher pore nucleation density with smaller pore diameter, and (iii) tighter poreorientation distributions, yielding laterally uniform porosification across cm-scale areas. AFM/SEM and cross-sectional image analysis confirm a progression from sparse, misoriented pores ( 10 s RIE) to dense, aligned morphologies ( 30 s RIE). Compared with MAPCE-based preconditioning, the proposed RIE step is simpler, contamination-resilient, and backend-compatible. It can be combined with established ECE processes to engineer porosity profiles for applications such as photonics, power electronics, or MEMS. Overall, controlled nano scaled roughness ( ~4 nmRMS ) is identified as a practical initiator for robust, homogeneous porosification even of the Si -face of 4H−SiC samples.

Further investigations will focus on the structural and chemical analysis using AFM, TEM, XPS and ToF-SIMS to identify the driving mechanisms of pore nucleation. Future investigations will be performed in a 3-electrode ECE setup to improve the validity of the current response.

Acknowledgement

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The financial support by the Austrian Federal Ministry for Labour and Economy and the National Foundation for Research, Technology and Development and the Christian DopplerResearch Association is gratefully acknowledged.

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The original version of this paper is available on https://www.scientific.net/MSF.1193.69.pdf

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S. N. Wahid, M. Leitgeb, G. Pfusterschmied, and U. Schmid, 'A Novel Approach for Thin 4HSiC Foil Realization Using Controlled Spalling from a Wafer', presented at the ICSCRM 2023, Trans Tech Publ, 2023, pp. 35-41.

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L. Jiang and R. Cheung, 'Impact of Ar addition to inductively coupled plasma etching of SiC in SF6/O2', Microelectronic Engineering, vol. 73-74, pp. 306-311, June 2004, doi: 10.1016/j.mee.2004.02.058.

M. Huff, 'Recent Advances in Reactive Ion Etching and Applications of High-Aspect-Ratio Microfabrication', Micromachines (Basel), vol. 12, no. 8, p. 991, Aug. 2021, doi: 10.3390/mi12080991.

M. Leitgeb, C. Zellner, M. Schneider, and U. Schmid, 'Porous single crystalline 4H silicon carbide rugate mirrors', APL Mater., vol. 5, no. 10, p. 106106, Oct. 2017, doi: 10.1063/1.5001876.

M. Leitgeb, C. Zellner, G. Pfusterschmied, M. Schneider, and U. Schmid, 'Porous Silicon Carbide for MEMS', EUROSENSORS 2017, vol. 1, no. 4, p. 297, 2017, doi: .

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A. Hochreiter, F. Groß, M.-N. Möller, M. Krieger, and H. B. Weber, 'Electrochemical etching strategy for shaping monolithic 3D structures from 4H-SiC wafers', Sci Rep, vol. 13, no. 1, p. 19086, Nov. 2023, doi: 10.1038/s41598-023-46110-2.

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Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 77-82

doi: 10.4028/p-XZ6YqE

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-26

Revised:
2025-12-16

Accepted:
2026-01-31

Online:
2026-05-21

BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

Shunya Hirano 1,a*, Hyuk Kim 1,b, Satoru Takahashi 2,c, Shuzo Masui 2,d, Noboru Ohtani 3,e, Kozo Abe 3,f

¹Makino Milling Machine Co., Ltd., Engineering Development Group of LASER Business Division, 2-10-4 Nakane, Meguro-ku, Tokyo, 152-8578, Japan

2 The University of Tokyo, Dept. of Precision Engineering, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

3 Kwansei Gakuin University, School of Engineering, 1 Gakuen Uegahara, Sanda, Hyogo 669-1330, Japan

a*h iranosh@makino.co.jp, b kimh@makino.co.jp, c takahashi@nanolab.t.u-tokyo.ac.jp, d  masui.s@nanolab.t.u-tokyo.ac.jp, e  ohtani.noboru@kwansei.ac.jp, f  abekzw@outlook.jp

*corresponding author

Keywords: wafer dicing, water jet guided laser, laser ablation, basal plane dislocations.

Abstract

Silicon carbide (SiC) wafers are essential for next-generation power devices; however, conventional dicing methods often induce cracks and Basal Plane Dislocations (BPDs), reducing device reliability. This study demonstrates BPD-free dicing of epitaxial SiC wafers using Water jet Guided Laser (WGL) processing. Full-thickness cutting was performed on 350μ m-thick wafers with a 10μ m-thick epitaxial layer using a YAG laser ( 532 nm wavelength, 200 ns pulse width, 10 kHz repetition rate, 30−80 W output) on an LB300 system. BPD evaluation was carried out by X-ray topography (XRT) with the −1−128 reflection before and after cutting. The results showed no generation or propagation of new BPDs, and pre-existing BPDs did not glide, confirming that WGL processing enables BPD-free machining. These results are attributed to the ablation-based nature of WGL with water assistance, which avoids mechanical stress on epitaxial SiC wafers.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

Silicon carbide ( SiC ) wafers are increasingly used in next-generation power devices due to their superior power handling and efficiency characteristics. In SiC power devices, the epitaxial layer is particularly important because it is closely related to the active region where device operation occurs. Therefore, defects introduced into or propagated near the epitaxial layer during dicing may directly affect device performance and long-term reliability. For this reason, it is necessary to evaluate not only the macroscopic cutting quality, such as kerf width and chipping, but also the crystallographic quality of epitaxial SiC wafers after dicing [1]. Various dicing and separation methods, including ultrasonic-assisted wafer sawing and laser-based separation techniques, have been investigated for hard and brittle SiC wafers [2-4]. Although these methods are effective for chip separation, processinduced mechanical loading and thermal effects must be carefully considered in SiC device manufacturing. Therefore, achieving defect-free, particularly BPD-free, dicing remains a significant challenge. This study aims to demonstrate a BPD-free dicing technique for epitaxial SiC wafers using Water jet guided laser (WGL) processing. As illustrated in Fig. 1, WGL utilizes a high-pressure, micron-scale water jet as an optical waveguide for a pulsed laser beam, facilitating precise material ablation and simultaneous cooling [5]. The water jet confines and guides the laser beam due to total internal reflection within the jet, allowing the laser to maintain a tight focus over a longer working distance. This guidance effect reduces beam divergence and enables highly accurate, narrow kerf cutting. In addition, the water jet removes debris from the cutting area, preventing redeposition and thermal damage to surrounding material. The combination of optical guidance and cooling allows WGL to perform defect-free machining even on brittle or hard materials. Moreover, by adjusting the water pressure and jet diameter, the energy density of the laser at the workpiece can be precisely controlled, optimizing the ablation efficiency. While previous studies have shown that WGL did not
generate BPDs in bulk SiC, its applicability for dicing epitaxial layers has not yet been confirmed. In addition, the damage-free nature of WGL dicing was evaluated by analyzing XRT images of grooved SiC wafers from two directions and by performing EDX analysis on the cleaved surfaces. Although previous studies have evaluated WGL-grooved SiC wafers using XRT and EDX analysis [6-7], the effect of WGL full-thickness cutting on the BPD distribution of epitaxial SiC wafers has not been sufficiently investigated. Since XRT is effective for observing crystallographic defects such as BPDs in SiC wafers [8], the same area was examined before and after cutting in this study. This approach enables evaluation of whether detectable BPDs were newly generated or whether pre-existing BPDs propagated during WGL full-thickness cutting. In this study, WGL-based dicing is applied to epitaxial SiC wafers, and the resulting crystal quality is evaluated by X-ray topography (XRT).

[picture]

Fig. 1. Schematic illustration of WGL.

Fig. 1. Schematic illustration of WGL.

Method

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

A schematic view of WGL dicing is shown in Fig. 1, and the experimental flow for BPD evaluation is shown in Fig. 2. To evaluate whether WGL processing induced detectable new BPDs or caused the propagation of pre-existing BPDs, XRT observations were performed at the same position before and after cutting. In step (a), alignment markings were processed to enable positional correlation between the pre- and post-processing XRT images. In step (b), XRT observation was performed near the alignment markings before WGL cutting. In step (c), the SiC wafer was fully cut by WGL inside the marked region. In step (d), XRT observation was performed again at the same position after WGL dicing. The alignment markings were used as reference features to identify the same observation area before and after WGL cutting. The WGL cutting path was set inside the marked region so that the area surrounding the cut could be included in the XRT observation field. This arrangement allowed the BPD distribution near the full-thickness cutting region to be compared directly before and after processing. The XRT observation area was selected to include both the cutting region and the surrounding wafer area. Therefore, changes in BPD-related line contrasts could be evaluated with respect to the initial defect distribution of the wafer.

The wafer was mounted using dicing tape, and the working distance between the nozzle and the wafer surface was set to 10 mm . Full-thickness cutting was performed on a 350μ m-thick SiC wafer with a 10μ m-thick epitaxial layer using an LB300 system. The main WGL processing conditions are summarized in Table 1. BPD evaluation was conducted before and after WGL cutting at the same position using XRT with the −1−128 reflection. The XRT evaluation conditions are summarized in Table 2.

[picture]

Fig. 2. Process flow for BPD evaluation at the same position using XRT observation.

Fig. 2. Process flow for BPD evaluation at the same position using XRT observation.

(a) Alignment markings for position identification.
(b) XRT observation before WGL cutting.
(c) WGL full-thickness cutting inside the marked region.
(d) XRT observation at the same position after WGL cutting. The BPD distributions before and after processing were compared in the XRT observation area.

Table 1. WGL processing conditions used for full-thickness cutting of the epitaxial SiC wafer.

Item | Condition
Workpiece | Epitaxial SiC wafer
Wafer thickness | 350 μm
Epitaxial layer thickness | 10 μm
Machine | LB300, Makino Milling Machine Co., Ltd.
Laser source | YAG laser
Wavelength | 532 nm
Pulse width | Approximately 200 ns
Repetition rate | 10 kHz
Output power | 30–80 W

Table 2. XRT evaluation conditions used for comparing BPD distributions before and after WGL cutting.

Item | Condition
Evaluation method | X-ray topography
XRT system | XRTmicron, Rigaku Holdings Corporation
Reflection | -1-128
Exposure area | 8.0 mm × 6.0 mm
Pixel size | 2.3 μm

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

As shown in Fig. 3, XRT images were acquired before and after WGL full-thickness cutting to evaluate changes in the BPD distribution. The overview XRT images in Fig. 3(a) and (b) show the same observation area before and after processing. The overall distribution of line contrasts attributed to pre-existing BPDs was maintained after processing, and no significant change in the defect contrast was observed around the cutting region. This result indicates that no detectable generation or propagation of BPDs occurred within the XRT observation area. This stability of the BPD distribution was confirmed not only in a single observation area but also in multiple regions of the wafer. In addition, similar tendencies were observed for cutting directions rotated by 90 degrees, indicating that the absence of detectable BPD generation was reproducible under the present experimental conditions. These observations suggest that WGL processing can maintain the initial BPD distribution of epitaxial SiC wafers during full-thickness cutting. Specifically, Fig. 3(c)-(h) shows magnified XRT images of selected areas before and after processing, where no emergence or growth of BPDs was observed. The contrast in images (c)-(h) was adjusted to improve BPD visibility. In particular, images (c) and (d) confirm that no new BPDs were generated in areas initially free of BPDs, while images (e)-(h) demonstrate that even pre-existing BPDs ( δ,ε ) did not glide during processing. The absence of detectable BPD generation and propagation is considered to be related to the non-contact and water-assisted nature of WGL processing. Unlike blade dicing, WGL removes material mainly by laser ablation without direct mechanical contact with the wafer. In addition, the water jet assists cooling during processing. These characteristics can reduce process-induced mechanical loading and suppress excessive thermal influence around the cutting region, which is consistent with the stable BPD distribution observed by XRT.

[picture]

Fig. 3. XRT images of full-thickness cutting.

Fig. 3. XRT images of full-thickness cutting.

(a), (b) XRT images before and after processing.
(c), (e), (g) magnified XRT images of selected areas before processing.
(d), (f), (h) magnified XRT images of selected areas after processing. α−η indicate pre-existing BPDs. (Contrast was adjusted in (c)-(h) to enhance the visibility of BPDs.).

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

In this study, Water jet Guided Laser (WGL) processing was applied to full-thickness cutting of epitaxial SiC wafers. XRT evaluation before and after processing confirmed that no new Basal Plane Dislocations (BPDs) were generated and that pre-existing BPDs did not propagate or glide. These results confirm that WGL processing enables BPD-free machining by an ablation-based technique with water assistance that does not impart mechanical stress to epitaxial SiC wafers. Future studies will be directed toward optimizing the processing parameters and validating the technique under mass-production conditions for practical application in SiC power device fabrication.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.77.pdf

M. Skowronski et al., J. Appl. Phys. 99, 011101 (2006).

Y.H. Wang et al., Proceedings of CSS MANTECH (Denver, Colorado, USA, 2014), 271-274.

E. Ohmura et al., J. Achiev. Mater. Manuf. Eng., 17, 381-384 (2006).

A. Bauer, H. Ryssel, Mater. Sci. Forum, 821-823, 528-532 (2014).

B. Richerzhagen, U.S. Patent No. 5,902,499, May 11, 1999.

S. Kadoya et al., "Proposal of Damage-Free SiC Wafer Dicing Using Water Jet Guided Laser," Materials Science Forum, Vol. 1124, pp. 85-89, 2024.

S. Masui et al., "Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser," ICSCRM2024, pp. 666-668, Raleigh, NC, USA, 2024.

K. Omote et al., Rigaku Journal, Vol. 29, No. 1, pp. 1-8, 2013.

This ePub file was created using machine-generated methods and automated software to convert the source text into an ePub format and may contain formatting inconsistencies from the original version. Formatting may vary depending on the device used.

The original version of this eBook is available on https://www.scientific.net/book/wafer-processing/978-3-0364-3128-4

Materials Science Forum, ISSN: 1662-9752, Vol. 1193, pp 83-88

doi: 10.4028/p-eyjUb3

© 2026 The Author(s). Published by Trans Tech Publications Ltd, Switzerland.

Submitted:
2025-09-28

Revised:
2025-12-21

Accepted:
2026-02-27

Online:
2026-05-21

Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

Chen-Hang Wu 1,a, Chao-Jun Zhang 1,b, Shao-Yuan Huang 1,c and Chao-Chang A. Chen 1, d*

1 National Taiwan University of Science and Technology, No. 43, Sec. 4, Keelung Rd., Taipei, 10607, Taiwan

ªM11103241@mail.ntust.edu.tw, bM11203203@mail.ntust.edu.tw, c M11303241@mail.ntust.edu.tw, d*artchen@mail.ntust.edu.tw

Keywords: fixed-abrasive lapping, electrochemical passivation, polarization curve, silicon carbide, wafer thinning.

Abstract

This study aims to develop an electrochemical assisted fixed-abrasive lapping (ECAL) process for thinning 4H−SiC wafers ( C -face). Process with 20wt%NaNO3 electrolyte to generate a softened passivation layer has been formed and simultaneously removed by a fixed diamond lap wheel. Electrochemical tests using a potentiostat have verified 20 V as the selected experimental potential, and a significant reduction in hardness has been confirmed by nanoindentation. Under these conditions, the 4-inch wafer has achieved a material removal rate (MRR) of 3.181μ m/h with wafer quality (Bow −7.80μ m, Warp 48.50μ m, TTV 7.70μ m ). When the same conditions have been applied to 6-inch wafers, an MRR of 2.457μ m/h and wafer quality (Bow −5.00μ m, Warp 36.70μ m, TTV 6.60μ m) have been obtained. These results have demonstrated the scalability of ECAL for larger SiC substrates, offering potential for next-generation device manufacturing.

Introduction

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

Monocrystalline silicon carbide ( SiC ) is a key material for high-power applications such as electric vehicles, renewable energy systems, and 5G communication technologies due to its wide bandgap, high thermal conductivity, and excellent breakdown field. To meet the packaging and reliability demands, wafer thinning becomes an essential process for improving heat dissipation capability and ensuring reliable device operation. However, conventional thinning processes often introduce subsurface damage (SSD) and residual stress, which have been identified as having negative impact on wafer quality and device performance. Therefore, an electrochemical assisted fixed-abrasive lapping (ECAL) process has been developed in this study, combining electrochemical reaction with mechanical removal of material, with the aim of reducing surface damage while improving process efficiency.

Research and Experimental Conditions

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

An electrochemical assisted fixed-abrasive lapping (ECAL) process has been developed for 4-inch and 6 -inch 4 H -SiC wafers, in which the wafer has been connected as the anode and the diamond lapping plate as the cathode. The process schematic and setup are shown in Fig. 1. A direct current has been applied through the electrolyte to form a passivation layer on the wafer surface, which has been simultaneously removed by the lapping plate during processing. Electrochemical characterization has been first carried out using a potentiostat to determine the potential and electrolyte conditions used in the subsequent ECAL experiments. Potentiodynamic polarization curves obtained in 20wt%NaNO3 at 70∘C have revealed a distinct passivation region, from which an applied potential of 20 V has been selected as shown in Fig. 2. Potentiostatic polarization tests further have indicated that at 20 V , the current density has the highest initial value and has rapidly decayed, resulting in a stable level within 60 s as shown in Fig. 3.
To investigate the mechanical effect of passivation, nanoindentation hardness tests have been conducted on untreated wafers and wafers after 20 V anodic polarization. For the untreated SiC wafer,
the hardness has been measured as 24.59 GPa and the Young's modulus has been measured as 271.56 GPa . Under the condition of 20 V , the hardness has decreased significantly to 1.50 GPa and the Young's modulus to 64.60 GPa , confirming the formation of a softened passivation layer as shown in Fig. 4. Although tests at 15 V and 25 V have also been performed, the 20 V condition has been selected for subsequent experiments, as it has revealed stable passivation behavior.

[picture]

Fig. 1. Schematic and experimental setup of ECAL process [2].

Fig. 1. Schematic and experimental setup of ECAL process [2].

[picture]

Fig. 2. Potentiodynamic polarization of SiC in 20wt%NaNO3 at 70∘C [2].

Fig. 2. Potentiodynamic polarization of SiC in 20 w t % N a N O 3 at 70 ∘ C [2].

[picture]

Fig. 3. Potentiostatic polarization of SiC at 20 V for 60 s [2].

Fig. 3. Potentiostatic polarization of SiC at 20 V for 60 s [2].

[picture]

Fig. 4. Nanoindentation load and displacement curve under 20 V [2].

Fig. 4. Nanoindentation load and displacement curve under 20 V [2].

The ECAL process for 4 -inch SiC wafers has been performed with a NaNO3 electrolyte concentration of 20wt%, an applied potential of 20 V , a head/platen rotation speed of 50/60rpm, and a down pressure of 3 psi , ensuring uniform and stable contact between the SiC wafer and the diamond lap wheel. To verify the scalability of the process, the same electrochemical and mechanical parameters have been applied to 6-inch wafers. The electrochemical mechanism is illustrated in Fig. 5.

[picture]

Fig. 5. Electrochemical reaction mechanism.

Fig. 5. Electrochemical reaction mechanism.

Results and Discussion

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

Based on the electrochemical reaction studies of 4 H -monocrystalline silicon carbide ( 4H−SiC ), the electrolyte parameters have been determined to be 70∘C and 20wt%NaNO3 from potentiodynamic polarization experiments. Potentiostatic tests further have indicated that 20 V provides the highest and distinct passivation layer growth rate. Under these conditions, electrochemical assisted fixedabrasive lapping (ECAL) experiments have been carried out on 4 -inch SiC wafers using a #800 diamond lapping plate. The effects of down pressure and rotational speed on MRR and surface quality have been evaluated, as summarized in Table 1.

Table 1. 4-inch SiC wafer (C-face) ECAL parameters [2].

4-inch SiC wafer lapping parameters
Process | ECAL
Diamond Plate | #800
Down Pressure | 1 psi / 3 psi
Electrolyte Type | NaNO₃ 20 wt%
Temperature | 70°C
Flow Rate | 0.5 L/min
Head/Platen Rotation Speed | 30/40 rpm, 50/60 rpm
Process Time | 1 h

In this section, the results of the ECAL process for 4-inch monocrystalline silicon carbide (SiC) wafers under different experimental parameters are summarized. The discussion focuses on the effects of varying down pressure and rotational speed on wafer surface quality and MRR. At 1 psi and 30/40rpm,MRRH has been measured as 1.770μ m/h and Sa0.4394μ m. At the same pressure with 50/60rpm,MRRH has increased to 1.938μ m/h and Sa0.4888μ m. For 3 psi and 30/40rpm, MRRH has reached 2.213μ m/h and Sa0.5085μ m. The highest efficiency has been obtained at 3 psi and 50/60rpm, with MRRH3.180μ m/h and Sa0.6538μ m.
The 4-inch 4H-SiC wafer after ECAL processing under the 3 psi and 50/60 rpm as shown in Fig. 6. According to the experimental results, higher pressure and speed have enhanced the MRR but have slightly degraded the surface quality. The corresponding wafer quality results are summarized in Table 2. Although the Warp value has been slightly higher, the overall wafer has maintained good flatness and can be further improved by subsequent CMP processes.

[picture]

Fig. 6. 4-inch 4H−SiC after ECAL processing [2].
Table 2. Measurement results of Bow, Warp, TTV for 4-inch 4H-SiC [2].

Fig. 6. 4-inch 4 H − S i C after ECAL processing [2]. Table 2. Measurement results of Bow, Warp, TTV for 4-inch 4H-SiC [2].

To evaluate the scalability of the ECAL process, the same conditions have been applied to 6 -inch monocrystalline SiC wafers. The resulting MRR is lower than that of the 4 -inch wafers, with an MRRH of 2.457μ m/h and Sa of 0.457μ m. This reduction has been attributed to the reduced current density on the larger surface area, while the surface roughness has remained comparable and relatively stable.
The wafer quality after ECAL has been summarized in Table 3. For the 6-inch wafers, Bow, Warp, TTV have been measured as −5.00μ m,36.70μ m, and 6.60μ m, respectively. The 6-inch wafer has maintained overall flatness and surface condition after ECAL processing, with the Bow/Warp/TTV measurement map shown in Fig. 7(a) and the wafer photograph after processing in Fig. 7(b).

Table 3. 6-inch SiC Wafer (C-face) ECAL parameters [2].

6-inch SiC wafer lapping parameters
Process | ECAL
Diamond Plate | #800
Down Pressure | 3 psi
Electrolyte Type | NaNO₃ 20 wt%
Temperature | 70°C
Flow Rate | 0.5 L/min
Head/Platen Rotation Speed | 50/60 rpm
Process Time | 1 h

[picture]

Fig. 7. (a) 6 -inch 4H−SiC Bow/Warp/TTV measurement (b) 6 -inch 4 H -SiC after ECAL processing [2].

Fig. 7. (a) 6 -inch 4 H − S i C Bow/Warp/TTV measurement (b) 6 -inch 4 H -SiC after ECAL processing [2].

Conclusion

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

In this study, the electrochemical assisted fixed-abrasive lapping (ECAL) process has been demonstrated on 4 -inch and extended to 6 -inch 4 H - SiC wafers. Electrochemical analyses have confirmed that 20 V has provided stable passivation, enabling effective wafer thinning. The applied process parameters have resulted in high removal efficiency while maintaining wafer flatness. The successful demonstration on 6 -inch wafers has emphasized the scalability of ECAL for nextgeneration SiC substrates. Future work can focus on further optimizing electrochemical conditions and integrating ECAL with CMP to improve overall wafer quality. These findings have demonstrated that ECAL has strong potential for integration into large-scale SiC wafer manufacturing, contributing to improved device performance in power electronics and communication applications.

References

The original version of this paper is available on https://www.scientific.net/MSF.1193.83.pdf

P. Wu, et al., Effect of voltage on electrochemical mechanical polishing (ECMP) of 4H-SiC with fixed abrasives, Journal of Materials Research and Technology (2025).

C.-H. Wu, Research on electrochemical-assisted fixed abrasive lapping process for monocrystalline silicon carbide wafer, M.S. Thesis, National Taiwan University of Science and Technology, Taipei, Taiwan (2024).

T.-C. Wu, Research on electrochemical-assisted fixed abrasive lapping process for monocrystalline silicon wafer thinning, M.S. Thesis, National Taiwan University of Science and Technology, Taipei, Taiwan (2023).

X. Yang, et al., Selective electrochemical mechanical polishing of surface employing porous material impregnated with electrolyte, Ceramics International 49 (22) (2023) 3456934581.

X. Yang, et al., Charge utilization efficiency and side reactions in the electrochemical mechanical polishing of 4H-SiC (0001), Journal of the Electrochemical Society 169 (2) (2022) 023501.

Z. Chen, Y. Zhao, Investigation into electrochemical oxidation behavior of with varying anodizing conditions, Electrochemistry Communications 109 (2019) 106608.

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Keywords Index

B

Basal Plane Dislocations BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Bonding Technique Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

C

Cover Wafer Effect Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

E

Electrochemical Etching CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Electrochemical Passivation Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

F

Fixed-abrasive Lapping Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Frequency Scanning Interferometry Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

H

High Temperature SiC Oxidation Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

J

Jbs Diode Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

L

Laser Ablation BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Laser Slice Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Laser Slicing Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Laser Slicing; Crack Propagation; Kerf Loss Effects of Processing Passes on Laser-Sliced SiC

Laser Split Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

M

Mosfet Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

N

Nanoindentation Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

O

Oxide Thickness Distribution Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

P

Polarization Curve Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Pore Nucleation CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Precision Grinding Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

R

Reactive Ion Etching CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Recycling Of By-products A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Recycling Wafer Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Refractive Index Homogeneity Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Reutilization Process Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

S

Si-based Materials A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

SiC Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

SiC Powders A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

SiC Wafer Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Silicon Carbide Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching; Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Strain Relief Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Substrate Engineering Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Synthesis Of Si And SiC A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

T

Total Thickness Variation (ttv) Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

V

Vertical Oxidation Furnace Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

W

Wafer Dicing BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Wafer Thinning Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Water Jet Guided Laser BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Wet Etching Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Wet Processing Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Authors Index

A

Abe, K. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Akiyoshi, K. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

B

Bay, N. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Bean, A. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

C

Che, L. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Chen, C. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Chen, Q. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Chen, X. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Cho, Y. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Choi, S. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

D

Delahaye, F. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

E

Engler, W. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

F

Fan, H. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Fidler, T. Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Furukawa, A. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

G

Gay, X. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

H

Hamano, K. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Hamid, R. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Hirano, S. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Huang, S. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

I

Iden, S. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Iwanaga, K. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

J

Jia, Y. Effects of Processing Passes on Laser-Sliced SiC

K

Keaton, G. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Kim, H. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Kim, J. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Kim, Y. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Kuehnlein, H. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Kusolitsch, M. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

L

Lee, C. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

Li, B. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Lynch, D. Correlation Study of Physical and Optical Total Thickness Variation in 4H-SiC Substrates

M

Masui, S. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Matsumura, Y. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

O

Ohtani, N. BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

P

Park, M. A Study on the Synthesis and Evaluation of Si/SiC Powders for SiC Wafers Fabrication and Si-Based Devices

Perazzi, M. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Pfusterschmied, G. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

R

Rathnakar, A. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

S

Sano, Y. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Schmid, P. Impact of Ambient Conditions on Oxide Thickness Distribution on 4H-SiC in Thermal Oxidation Furnace

Schmid, U. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Shah, V. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

T

Takahashi, S. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics; BPD-Free Dicing of Epitaxial SiC Wafers Using Water Jet Guided Laser

Tanaka, T. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques; Impacts of Wafer Thinning Process Using Laser Slice Technique on Silicon Carbide Device Characteristics

Toh, D. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

W

Wang, J. Effects of Processing Passes on Laser-Sliced SiC

Wang, R. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Watanabe, H. Feasibility Study of SiC Wafer Reutilization Process through Laser Splitting and Bonding Techniques

Whear, O. Strain Relief of Silicon Carbide Substrates ( 4H-SiC) by Wet Etching

Wu, C. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

X

Xu, X. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers

Xue, Y. Effects of Processing Passes on Laser-Sliced SiC

Y

Yamada, J. Damage-Free Dicing of SiC Substrate Using High-Pressure SF6 Plasma: The Time Dependence of Processed Groove Profiles

Yang, T. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Z

Zellner, C. CMOS-Compatible Pore Nucleation on 4H-SiC Si-Face via Reactive Ion Etching for Homogeneous Electrochemical Etching

Zhang, C. Study on Electrochemical Assisted Fixed-Abrasive Lapping for Wafer Thinning of Monocrystalline Silicon Carbide Wafer

Zhang, J. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC

Zhang, X. Comparative Study on Grinding Behavior of C-Face and Si-Face in Laser-Sliced 4H-SiC Wafers; Effects of Processing Passes on Laser-Sliced SiC