Papers by Keyword: C-Face

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Authors: Hiroshi Kono, Takuma Suzuki, Kazuto Takao, Masaru Furukawa, Makoto Mizukami, Chiharu Ota, Shinsuke Harada, Junji Senzaki, Kenji Fukuda, Takashi Shinohe
Abstract: 1.2 mm × 1.2 mm and 2.7 mm × 2.7 mm silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. 1.2 mm × 1.2 mm DIMOSFETs were characterized from room temperature to 150°C. At room temperature, the specific on-resistance of this MOSFET was 5.7 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The blocking voltage of this MOSFET was 1450 V based on the avalanche current. At 150 °C, the specific on-resistance increased from 5.7 mΩcm2 to 9.1 mΩcm2 and the threshold voltage decreased from 4.9 V to 4.1 V. The blocking voltage increased from 1450V to 1500V. 2.7 mm × 2.7 mm DIMOSFETs were also characterized at room temperature. They showed a specific on-resistance of 8.0 mΩcm2 at a gate bias of 20 V and a drain voltage of 1 V. The blocking voltage of this device was 1550 V, which was determined by the avalanche current. The time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) characteristics of 180 μm × 180 μm MOS capacitor were estimated. At room temperature (RT), TZDB was 9.3 MV/cm and the charge to breakdown value of 63% cumulative failure (Qbd) was 72 C/cm2. The temperature dependence of Qbd measurements showed that it deceased from 72 C/cm2 at RT to 14 C/cm2 at 250 °C. Switching characteristics of 1.2 mm × 1.2 mm DIMOSFETs were obtained by the double-pulse measurements. The turn-on time and the turn-off time were 36 nsec and 53 nsec, respectively.
607
Authors: Hiroshi Kono, Masaru Furukawa, Keiko Ariyoshi, Takuma Suzuki, Yasunori Tanaka, Takashi Shinohe
Abstract: Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.
935
Authors: Akira Miyasaka, Jun Norimatsu, Keisuke Fukada, Yutaka Tajima, Yoshiaki Kageshima, Daisuke Muto, Michiya Odawara, Taichi Okano, Kenji Momose, Yuji Osawa, Hiroshi Osawa, Takayuki Sato
Abstract: The production of 150 mm-diameter SiC epitaxial wafers is the key to the spread of SiC power devices. We have developed production technology of the epitaxial growth for 4° off Carbon face (C-face) 4H-SiC epitaxial layers on 150 mm diameter substrates. Several growth parameters and hardware were optimized to obtain high uniformity wafers. We have succeeded in fabricating high quality C-face wafers with smooth surface and high uniformity.
193
Authors: Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida, Toshiyuki Miyanagi, Isaho Kamata, Tomonori Nakamura, Katsunori Asano, R. Ishii
Abstract: The dependence of forward voltage degradation on crystal faces for 4H-SiC pin diodes has been investigated. The forward voltage degradation has been reduced by fabricating the diodes on the (000-1) C-face off-angled toward <11-20>. High-voltage 4H-SiC pin diodes on the (000-1) C-face with small forward voltage degradation have also been fabricated successfully. A high breakdown voltage of 4.6 kV and DVf of 0.04 V were achieved for a (000-1) C-face pin diode. A 8.3 kV blocking performance, which is the highest voltage in the use of (000-1) C-face, is also demonstrated in 4H-SiC pin diode.
969
Authors: Stanislav I. Soloviev, Ying Gao, Yuri I. Khlebnikov, I.I. Khlebnikov, Tangali S. Sudarshan
557
Authors: Yuji Kiuchi, Hidenori Kitai, Hiromu Shiomi, Masatoshi Tsujimura, Daisuke Nakata, Shinsuke Harada, Yoshiyuki Yonezawa, Kenji Fukuda, Kunihiro Sakamoto, Kimiyoshi Yamasaki, Hiroshi Yano, Hajime Okumura
Abstract: Wet and N2O oxidized SiO2/SiC for C-face substrates were comprehensively investigated to clarify the origin of oxide defects which affect channel mobility and threshold voltage stability by using leakage-current analysis. The estimated defects are identified by cathode luminescence, X-ray photoelectron spectroscopy, and high-resolution Rutherford backscattering spectroscopy. The origin of the observed oxide defects might be complex defect of O vacancy defects and/or C related defects including N.
449
Authors: Hidenori Koketsu, Tomoaki Hatayama, Hiroshi Yano, Takashi Fuyuki
Abstract: The sub-trenches in 4H-SiC Si- and C-faces could be disappeared by the thermal treatment in chlorine ambience at 900-1000oC. The surface morphologies of the thermally treated trench-sidewalls were unchanged. It is considered that the sub-trench is selectively removed because thermally Cl2 etching rate of the (0001) Si- and (000-1) C-face are different to the (11-20) and (1-100).
881
Authors: Takashi Aigo, Wataru Itoh, Tatsuo Fujimoto, Takayuki Yano
Abstract: In this paper, we present a comparison of defects in 4H-SiC epilayers grown on 4o off-axis (0001) and (000-1) substrates. It was confirmed using high sensitive surface observation and micro-Raman spectroscopy that the generation of epitaxial defects on (000-1) C-face substrates was less susceptible to substrate morphological defects such as pits than that on (0001) Si-face substrates and 'comet-like' defects on (000-1) C-faces were caused by the inclusion of 3C-SiC. Moreover, PL imaging observation showed that stacking fault densities decreased when increasing the growth temperature, and they increased when increasing the C/Si ratio, irrespective of the face polarity. The densities, however, were lower for C-faces at higher growth temperature and C/Si ratio. The present results indicated that C-faces were preferable to Si-faces to achieve smooth step-flow growth suppressing epitaxial defects and stacking faults, which were influenced by the substrate morphological defects and the fluctuation of C/Si ratio in the epitaxial growth.
143
Authors: Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura, Koji Nakayama, R. Ishii, Yoshitaka Sugawara
Abstract: Propagation and nucleation of basal plane dislocations (BPDs) in 4H-SiC(000-1) and (0001) epitaxy were compared. Synchrotron reflection X-ray topography was performed before and after epitaxial growth to classify the BPDs into those propagated from the substrate into the epilayer and those nucleated in the epilayer. It was revealed that the propagation ratio of BPDs for the (000-1) epitaxy was significantly smaller than that for the (0001) epitaxy. Growing (000-1) epilayers at a high C/Si ratio of 1.2 achieves a further reduction in BPDs to only 3 cm-2 for those propagated from the substrate, and 16 cm-2 for those nucleated in the epilayer. A dramatic increase was also found in the nucleation of BPDs omitting the re-polishing and in-situ H2 etching procedure.
231
Authors: Tetsuo Hatakeyama, Kyoichi Ichinoseki, Hiroshi Yamaguchi, N. Sugiyama, Hirofumi Matsuhata
Abstract: The origins of certain types of micrometer-scale surface morphological defects on SiC epitaxial layers are clarified using X-ray topography. Two types of surface morphological defects are commonly observed on Si- and C-face epitaxial layers. Relatively large pits (around 4μm×2μm) originate from threading screw dislocations (TSDs). Relatively small pits (around 1.5μm×1μm) originate from threading edge dislocations (TEDs). The shapes and depths of these surface morphological pits depend on the fabrication history of the epitaxial wafers.
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