Papers by Keyword: Channel Mobility

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Authors: Eiichi Okuno, Takeshi Endo, Jun Kawai, Toshio Sakakibara, Shoichi Onda
Abstract: We have investigated the techniques to improve the channel mobility of SiC MOSFETs and found that the hydrogen termination of dangling bonds at a MOS interface is very effective in improving the channel mobility, particularly that of the interface fabricated on a (11-20) face wafer. A high channel mobility of MOSFET on the (11-20) face was achieved to 244cm2/Vs by new process which can terminate dangling bonds by hydrogen. The vertical MOSFET, which is prepared using this process, has a low on-resistance of 5.7 mΩcm2 and a breakdown voltage of 1100 V. The channel resistance is estimated at 0.58 mΩcm2.
1119
Authors: Motoki Kobayashi, Hidetsugu Uchida, Akiyuki Minami, Toyokazu Sakata, Romain Esteve, Adolf Schöner
Abstract: 3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.
645
Authors: Qamar-ul Wahab, Hajime Kosugi, Hiroshi Yano, Christer Hallin, Tsunenobu Kimoto, Hiroyuki Matsunami
1215
Authors: T. Hirao, Hiroshi Yano, Tsunenobu Kimoto, Hiroyuki Matsunami, Hiromu Shiomi
1065
Authors: Mitsuo Okamoto, Tsutomu Yatsuo, Kenji Fukuda, Hajime Okumura, Kazuo Arai
Abstract: From a viewpoint of device application using p-channel SiC MOSFETs, control of their channel properties is of great importance. We aimed to control the electrical properties of 4H-SiC p-channel MOSFETs through locating the p-type epitaxial layer at the channel area, so called “epi-channel MOSFET” structure. We varied the dopant concentrations and the thickness of the epi-channel layer, and investigated their electrical properties. In case of heavily doped epi-channel samples, the devices indicated “normally-on” characteristics, and their channel mobility decreased slightly in comparison with the inversion-type devices. As for lightly doped epi-channel samples, the subthreshold current increased with thickness of the epi-channel layer keeping their “normally-off” characteristics. Their channel mobility also increased with thickness of the epi-channel layer. The peak value of field effect channel mobility of the sample with 2.5 μm thickness and 5×1015 /cm3 dopant concentration epi-channel was 18.1 cm2/Vs.
711
Authors: Dethard Peters, Adolf Schöner, Peter Friedrichs, Dietrich Stephani
769
Authors: Pedro Barquinha, Elvira Fortunato, Alexandra Gonçalves, Ana Pimentel, António Marques, Luís Pereira, Rodrigo Martins
Abstract: The purpose of this work is to present in-depth electrical characterization on transparent TFTs, using zinc oxide produced at room temperature as the semiconductor material. Some of the studied aspects were the relation between the output conductance in the post-pinch-off regime and width-to-length ratios, the gate leakage current, the semiconductor/insulator interface traps density and its relation with threshold voltage. The main point of the analysis was focused on channel mobility. Values extracted using different methodologies, like effective, saturation and average mobility, are presented and discussed regarding their significance and validity. The evolution of the different types of mobility with the applied gate voltage was investigated and the obtained results are somehow in disagreement with the typical behavior found on classical silicon based MOSFETs, which is mainly attributed to the completely different structures of the semiconductor materials used in the two situations: while in MOSFETS we have monocrystalline silicon, our transparent TFTs use poly/nanocrystalline zinc oxide with grain sizes of about 10 nm.
68
Authors: Shiro Hino, Tomohiro Hatayama, Jun Kato, Naruhisa Miura, Tatsuo Oomori, Eisuke Tokumitsu
Abstract: 4H-SiC MOSFETs with Al2O3/SiC and Al2O3/SiOx/SiC gate structures have been fabricated and characterized. Al2O3 was deposited by metal-organic chemical vapor deposition (MOCVD) and the SiOx layer was formed by dry-O2 oxidation. Insertion of 1.2 nm-thickness-SiOx layer drastically improves the channel mobility of Al2O3/SiC-MOSFET and anomalously high field effect mobility (μFE) of 284 cm2/Vs was obtained. The μFE of Al2O3/SiOx/SiC-MOSFET with various SiOx thickness was investigated, and it was found that insertion of a thin SiOx layer (< 2 nm) followed by the low temperature deposition of Al2O3 results in Al2O3/SiOx/SiC-MOSFET with such a high channel mobility.
683
Authors: Kenji Fukuda, Shinsuke Harada, Junji Senzaki, Mitsuo Okamoto, Yasunori Tanaka, Akimasa Kinoshita, Ryouji Kosugi, Kazu Kojima, Makoto Kato, Atsushi Shimozato, Kenji Suzuki, Yusuke Hayashi, Kazuto Takao, Tomohisa Kato, Shin Ichi Nishizawa, Tsutomu Yatsuo, Hajime Okumura, Hiromichi Ohashi, Kazuo Arai
Abstract: The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm2 and excellent dynamic characteristics.
907
Authors: Junji Senzaki, Atsushi Shimozato, Kazutoshi Kojima, Tomohisa Kato, Yasunori Tanaka, Kenji Fukuda, Hajime Okumura
Abstract: Influences of wafer-related defect and gate oxide fabrication process on MOS characteristics with gate oxides thermally grown on 4H-SiC (0001) wafer have been investigated for a realization of SiC MOS power devices. The SiC MOS characteristics depend on the gate oxide fabrication process, and are improved by the increase of DRY oxidation temperature and the applying of N2O and H2 POAs. In addition, it was clearly shown that predominant origins of SiC MOS reliability degradation are wafer-related defects such as dislocation and surface defects of epitaxial layer. Moreover, the planarization of SiC epitaxial layer surface using a CMP treatment is effective technique for the improvement of SiC MOS reliability.
703
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